//--------------------------------------------------------------------------------------------------
//
// Title       : MISCouts
// Design      : U4
// Author      : mbari###
// Company     : MBARI
//
//-------------------------------------------------------------------------------------------------
//
// File        : c:\Projects\genosensor\2g\CPLDs\Core\U4\src\MISCouts.v
// Generated   : Wed Dec 24 10:50:17 2003
// From        : interface description file
// By          : Itf2Vhdl ver. 1.20
//
//-------------------------------------------------------------------------------------------------
//
// Description : 
//
//-------------------------------------------------------------------------------------------------
`timescale 1ps / 1ps

//{{ Section below this comment is automatically maintained
//   and may be overwritten
//{module {MISCouts}}
module MISCouts ( inDATA ,Reset ,AS ,LED1 ,RD ,LED2 ,Mclk ,LED3 ,LED4 ,WR ,MTRpwrn ,LED5 ,ADDR ,MTRpwr ,WRslct );

input WR ;
wire WR ;
input [7:0] inDATA ;
wire [7:0] inDATA ;
input Reset ;
wire Reset ;
input [7:0] ADDR ;
wire [7:0] ADDR ;
input AS ;
wire AS ;
input RD ;
wire RD ;
input WRslct ;
wire WRslct ;
input Mclk ;
wire Mclk ;

output LED3 ;
wire LED3 ;
output LED4 ;
wire LED4 ;
output MTRpwrn ;
wire MTRpwrn ;
output LED5 ;
wire LED5 ;
output MTRpwr ;
wire MTRpwr ;
output LED1 ;
wire LED1 ;
output LED2 ;
wire LED2 ;

//}} End of automatically maintained section

// -- Enter your statements here -- //



reg [5:0] MISCr;

assign LED1 = MISCr[0];
assign LED2 = MISCr[1];
assign LED3 = MISCr[2];
assign LED4 = MISCr[3];
assign LED5 = MISCr[4];
assign MTRpwr = MISCr[5];
assign MTRpwrn = !MISCr[5];

always @ (posedge Mclk)
	begin
		if (Reset) MISCr <= 6'b0;
		else if (WRslct) MISCr <= {inDATA[7], inDATA[4:0]};
		else MISCr <= MISCr;
	end
endmodule
