//--------------------------------------------------------------------------------------------------
//
// Title       : Servos
// Design      : U4
// Author      : mbari###
// Company     : MBARI
//
//-------------------------------------------------------------------------------------------------
//
// File        : C:\Projects\genosensor\2g\CPLDs\Core\U21\restore\U4\compile\Servos.v
// Generated   : Fri Mar  5 13:59:32 2004
// From        : C:\Projects\genosensor\2g\CPLDs\Core\U21\restore\U4\src\Servos.bde
// By          : Bde2Verilog ver. 2.01
//
//-------------------------------------------------------------------------------------------------
//
// Description : 
//
//-------------------------------------------------------------------------------------------------

// synopsys translate_off
`ifdef _VCP
`else
`define library(a,b)
`endif
// synopsys translate_on


// ---------- Design Unit Header ---------- //
`timescale 1ps / 1ps

module Servos (AS,Home_Encoder1,Home_Encoder2,PhaseA_Encoder1,PhaseA_Encoder2,PhaseB_Encoder1,PhaseB_Encoder2,RD,RDslct1,RDslct2,
RDslct3,RDslct4,RDslct5,Reset,Sclk,WR,WRslct,ADDR,inDATA,outDATA) ;

// ------------ Port declarations --------- //
input AS;
wire AS;
input Home_Encoder1;
wire Home_Encoder1;
input Home_Encoder2;
wire Home_Encoder2;
input PhaseA_Encoder1;
wire PhaseA_Encoder1;
input PhaseA_Encoder2;
wire PhaseA_Encoder2;
input PhaseB_Encoder1;
wire PhaseB_Encoder1;
input PhaseB_Encoder2;
wire PhaseB_Encoder2;
input RD;
wire RD;
input RDslct1;
wire RDslct1;
input RDslct2;
wire RDslct2;
input RDslct3;
wire RDslct3;
input RDslct4;
wire RDslct4;
input RDslct5;
wire RDslct5;
input Reset;
wire Reset;
input Sclk;
wire Sclk;
input WR;
wire WR;
input WRslct;
wire WRslct;
input [7:0] ADDR;
wire [7:0] ADDR;
input [7:0] inDATA;
wire [7:0] inDATA;
output [7:0] outDATA;
wire [7:0] outDATA;

// ----------- Signal declarations -------- //
wire NET145;
wire NET149;
wire NET1880;
wire NET1884;
wire NET1888;
wire Zero1;
wire [23:0] BUS1871;
wire [23:0] BUS231;

// -------- Component instantiations -------//

Decode U1
(
	.Reset(Reset),
	.Sclk(Sclk),
	.ce(NET145),
	.phaseA(PhaseA_Encoder1),
	.phaseB(PhaseB_Encoder1),
	.updown(NET149)
);



Counter U2
(
	.Reset(Reset),
	.Sclk(Sclk),
	.Zero(Zero1),
	.ce(NET145),
	.count(BUS231),
	.updown(NET149)
);



Holdreg U3
(
	.ADDR(ADDR),
	.AS(AS),
	.RD(RD),
	.RDslct1(RDslct1),
	.RDslct2(RDslct2),
	.RDslct3(RDslct3),
	.RDslct4(RDslct4),
	.Reset(Reset),
	.Sclk(Sclk),
	.WR(WR),
	.ch0in(BUS231),
	.ch1in(BUS1871),
	.outDATA(outDATA)
);



HomeConfig U4
(
	.ADDR(ADDR),
	.AS(AS),
	.HF1(outDATA[3]),
	.HF2(outDATA[7]),
	.Home_Encoder1(Home_Encoder1),
	.Home_Encoder2(Home_Encoder2),
	.RD(RD),
	.RDslct(RDslct5),
	.Reset(Reset),
	.Sclk(Sclk),
	.WR(WR),
	.WRslct(WRslct),
	.Zero1(Zero1),
	.Zero2(NET1888),
	.inDATA(inDATA)
);



Counter U5
(
	.Reset(Reset),
	.Sclk(Sclk),
	.Zero(NET1888),
	.ce(NET1880),
	.count(BUS1871),
	.updown(NET1884)
);



Decode U6
(
	.Reset(Reset),
	.Sclk(Sclk),
	.ce(NET1880),
	.phaseA(PhaseA_Encoder2),
	.phaseB(PhaseB_Encoder2),
	.updown(NET1884)
);



endmodule 
