// Xilinx Verilog netlist produced by netgen application (version G.26)
// Command      : -sim -ofmt verilog -sdf_path c:\Projects\genosensor\2g\CPLDs\Core\U21\implement U21.nga c:\Projects\genosensor\2g\CPLDs\Core\U21\implement\ver0\rev3\time_sim.v 
// Input file   : U21.nga
// Output file  : c:/Projects/genosensor/2g/CPLDs/Core/U21/implement/ver0/rev3/time_sim.v
// Design name  : U21.nga
// # of Modules : 1
// Xilinx       : C:/Xilinx
// Device       : XCR3384XL-7-TQ144 (Speed File: Version 6.0)

// This verilog netlist is a simulation model and uses simulation 
// primitives which may not represent the true implementation of the 
// device, however the netlist is functionally correct and should not 
// be modified. This file cannot be synthesized and should only be used 
// with supported simulation tools.

`timescale 1 ns/1 ps

module U21 (
  WR, RD, MSPReset, AS, Mclk, SCLreset, SCLinc, FLS1, Home15FLG, Home133FLG, Home05FLG, Home033FLG, Enc15FLG, Enc133FLG, Enc05FLG, Enc033FLG, 
PhaseA_Encoder0, PhaseB_Encoder0, PhaseB_Encoder1, PhaseA_Encoder1, GP_Motor0_0, GP_Motor1_0, Brake0, Brake1, DIR0, DIR1, FLS0, PWM5, PWM3, HSI, MHSO
, INTbus, RLS0, RLS1, LightSense, TXI, PWM1, PWM2, Home0, Home1, Enc033ctrl, Enc05ctrl, Enc133ctrl, Enc15ctrl, GPIO8, GPIO9, GP_Motor0_1, GP_Motor1_1
, HSO, Home033ctrl, Home05ctrl, Home133ctrl, Home15ctrl, INT, LED1, LED2, LED3, LED4, LED5, MHSI, MTRpwr, MTRpwrn, MTXI, PAH0, PAH1, PAL0, PAL1, PBH0
, PBH1, PBL0, PBL1, PresEn, PresSlct, SCLout, TP10, TP11, TP12, TmpEn, TmpSlct, SCL, I2CS, AD
);
  input WR;
  input RD;
  input MSPReset;
  input AS;
  input Mclk;
  input SCLreset;
  input SCLinc;
  input FLS1;
  input Home15FLG;
  input Home133FLG;
  input Home05FLG;
  input Home033FLG;
  input Enc15FLG;
  input Enc133FLG;
  input Enc05FLG;
  input Enc033FLG;
  input PhaseA_Encoder0;
  input PhaseB_Encoder0;
  input PhaseB_Encoder1;
  input PhaseA_Encoder1;
  input GP_Motor0_0;
  input GP_Motor1_0;
  input Brake0;
  input Brake1;
  input DIR0;
  input DIR1;
  input FLS0;
  input PWM5;
  input PWM3;
  input HSI;
  input MHSO;
  input INTbus;
  input RLS0;
  input RLS1;
  input LightSense;
  input TXI;
  input PWM1;
  input PWM2;
  input Home0;
  input Home1;
  output Enc033ctrl;
  output Enc05ctrl;
  output Enc133ctrl;
  output Enc15ctrl;
  output GPIO8;
  output GPIO9;
  output GP_Motor0_1;
  output GP_Motor1_1;
  output HSO;
  output Home033ctrl;
  output Home05ctrl;
  output Home133ctrl;
  output Home15ctrl;
  output INT;
  output LED1;
  output LED2;
  output LED3;
  output LED4;
  output LED5;
  output MHSI;
  output MTRpwr;
  output MTRpwrn;
  output MTXI;
  output PAH0;
  output PAH1;
  output PAL0;
  output PAL1;
  output PBH0;
  output PBH1;
  output PBL0;
  output PBL1;
  output PresEn;
  output PresSlct;
  output SCLout;
  output TP10;
  output TP11;
  output TP12;
  output TmpEn;
  output TmpSlct;
  inout SCL;
  input [5 : 0] I2CS;
  inout [7 : 0] AD;
  wire NlwRenamedSig_IO_WR;
  wire \WR_II/UIM ;
  wire NlwRenamedSig_IO_RD;
  wire \RD_II/UIM ;
  wire \MSPReset_II/UIM ;
  wire \AD<0>_II/UIM ;
  wire \AD<0>_II/IREG ;
  wire \FOOBAR3__ctinst/7 ;
  wire PRLD = glbl.PRLD;
  wire \U9/MISCr<0>_MC_tsimcreated_prld_ ;
  wire \Mclk_II/FCLK ;
  wire \U9/MISCr<0>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ;
  wire Gnd;
  wire \U9/MISCr<0>_MC.CE ;
  wire NlwRenamedSig_IO_AS;
  wire \AS_II/UIM ;
  wire U2_ASedge;
  wire \AS_II/IREG ;
  wire \U2_ASedge_MC.REG_tsimcreated_inv_Mclk_II/FCLK ;
  wire Vcc;
  wire \AD<4>_II/UIM ;
  wire \AD<4>_II/IREG ;
  wire \U9/MISCr<4>_MC_tsimcreated_prld_ ;
  wire \U9/MISCr<4>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ;
  wire \U9/MISCr<4>_MC.CE ;
  wire \AD<5>_II/UIM ;
  wire \AD<6>_II/UIM ;
  wire \U4/ctrlr[6] ;
  wire \AD<6>_II/IREG ;
  wire \U4/ctrlr<6>_MC_tsimcreated_prld_ ;
  wire \U4/ctrlr<6>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ;
  wire \FOOBAR10__ctinst/4 ;
  wire \AD<7>_II/UIM ;
  wire \U4/ctrlr[7] ;
  wire \AD<7>_II/IREG ;
  wire \U4/ctrlr<7>_MC_tsimcreated_prld_ ;
  wire \U4/ctrlr<7>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ;
  wire \FOOBAR9__ctinst/4 ;
  wire \AD<3>_II/UIM ;
  wire \U4/ctrlr[3] ;
  wire \AD<3>_II/IREG ;
  wire \U4/ctrlr<3>_MC_tsimcreated_prld_ ;
  wire \U4/ctrlr<3>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ;
  wire \FOOBAR12__ctinst/4 ;
  wire \AD<1>_II/UIM ;
  wire \AD<1>_II/IREG ;
  wire \U9/MISCr<1>_MC_tsimcreated_prld_ ;
  wire \U9/MISCr<1>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ;
  wire \U9/MISCr<1>_MC.CE ;
  wire \AD<2>_II/UIM ;
  wire \U4/ctrlr[2] ;
  wire \AD<2>_II/IREG ;
  wire \U4/ctrlr<2>_MC_tsimcreated_prld_ ;
  wire \U4/ctrlr<2>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ;
  wire \SCLreset_II/UIM ;
  wire \U11_U4/Line_last ;
  wire \SCLreset_II/IREG ;
  wire \U11_U4/Line_last_MC.REG_tsimcreated_inv_Mclk_II/FCLK ;
  wire \SCLinc_II/UIM ;
  wire \U11_U1/Line_last ;
  wire \SCLinc_II/IREG ;
  wire \U11_U1/Line_last_MC.REG_tsimcreated_inv_Mclk_II/FCLK ;
  wire \SCL_II/UIM ;
  wire \U11_U2/Line_last ;
  wire \SCL_II/IREG ;
  wire \U11_U2/Line_last_MC.REG_tsimcreated_inv_Mclk_II/FCLK ;
  wire \I2CS<5>_II/UIM ;
  wire \FLS1_II/UIM ;
  wire NlwRenamedSig_IO_Home15FLG;
  wire \Home15FLG_II/UIM ;
  wire \Home15FLG_II/IREG ;
  wire \U4/Flgreg<5>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ;
  wire \FOOBAR21__ctinst/4 ;
  wire NlwRenamedSig_IO_Home133FLG;
  wire \Home133FLG_II/UIM ;
  wire \Home133FLG_II/IREG ;
  wire \U4/Flgreg<4>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ;
  wire NlwRenamedSig_IO_Home05FLG;
  wire \Home05FLG_II/UIM ;
  wire \Home05FLG_II/IREG ;
  wire \U4/Flgreg<1>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ;
  wire NlwRenamedSig_IO_Home033FLG;
  wire \Home033FLG_II/UIM ;
  wire \Home033FLG_II/IREG ;
  wire \U4/Flgreg<0>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ;
  wire NlwRenamedSig_IO_Enc15FLG;
  wire \Enc15FLG_II/UIM ;
  wire \Enc15FLG_II/IREG ;
  wire \U4/Flgreg<7>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ;
  wire \FOOBAR24__ctinst/4 ;
  wire NlwRenamedSig_IO_Enc133FLG;
  wire \Enc133FLG_II/UIM ;
  wire \Enc133FLG_II/IREG ;
  wire \U4/Flgreg<6>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ;
  wire NlwRenamedSig_IO_Enc05FLG;
  wire \Enc05FLG_II/UIM ;
  wire \Enc05FLG_II/IREG ;
  wire \U4/Flgreg<3>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ;
  wire NlwRenamedSig_IO_Enc033FLG;
  wire \Enc033FLG_II/UIM ;
  wire \Enc033FLG_II/IREG ;
  wire \U4/Flgreg<2>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ;
  wire \PhaseA_Encoder0_II/UIM ;
  wire \PhaseB_Encoder0_II/UIM ;
  wire \PhaseB_Encoder1_II/UIM ;
  wire \PhaseA_Encoder1_II/UIM ;
  wire \GP_Motor0_0_II/UIM ;
  wire \U1/U4/InEdge0r ;
  wire \GP_Motor0_0_II/IREG ;
  wire \U1/U4/InEdge0r_MC.REG_tsimcreated_inv_Mclk_II/FCLK ;
  wire \GP_Motor1_0_II/UIM ;
  wire \U1/U4/InEdge1r ;
  wire \GP_Motor1_0_II/IREG ;
  wire \U1/U4/InEdge1r_MC.REG_tsimcreated_inv_Mclk_II/FCLK ;
  wire \Brake0_II/UIM ;
  wire \Brake1_II/UIM ;
  wire \DIR0_II/UIM ;
  wire \DIR1_II/UIM ;
  wire \FLS0_II/UIM ;
  wire \PWM5_II/UIM ;
  wire \PWM3_II/UIM ;
  wire \HSI_II/UIM ;
  wire \MHSO_II/UIM ;
  wire \I2CS<0>_II/UIM ;
  wire \I2CS<1>_II/UIM ;
  wire \I2CS<2>_II/UIM ;
  wire \I2CS<3>_II/UIM ;
  wire \I2CS<4>_II/UIM ;
  wire \INTbus_II/UIM ;
  wire \RLS0_II/UIM ;
  wire \RLS1_II/UIM ;
  wire \LightSense_II/UIM ;
  wire \TXI_II/UIM ;
  wire \PWM1_II/UIM ;
  wire \PWM2_II/UIM ;
  wire \Home0_II/UIM ;
  wire \U1/U4/HE0stater ;
  wire \Home0_II/IREG ;
  wire \U1/U4/HE0stater_MC.REG_tsimcreated_inv_Mclk_II/FCLK ;
  wire \Home1_II/UIM ;
  wire \U1/U4/HE1stater ;
  wire \Home1_II/IREG ;
  wire \U1/U4/HE1stater_MC.REG_tsimcreated_inv_Mclk_II/FCLK ;
  wire \AD<5>_MC.Q ;
  wire \AD<5>_MC.OE ;
  wire \Enc033ctrl_MC.Q ;
  wire \Enc05ctrl_MC.Q ;
  wire \Enc133ctrl_MC.Q ;
  wire \Enc15ctrl_MC.Q ;
  wire \GPIO8_MC.Q ;
  wire \GPIO9_MC.Q ;
  wire \GP_Motor0_1_MC.Q ;
  wire \GP_Motor1_1_MC.Q ;
  wire \HSO_MC.Q ;
  wire \Home033ctrl_MC.Q ;
  wire \Home05ctrl_MC.Q ;
  wire \Home133ctrl_MC.Q ;
  wire \Home15ctrl_MC.Q ;
  wire \INT_MC.Q ;
  wire \LED1_MC.Q ;
  wire \LED2_MC.Q ;
  wire \LED3_MC.Q ;
  wire \LED4_MC.Q ;
  wire \LED5_MC.Q ;
  wire \MHSI_MC.Q ;
  wire \MTRpwr_MC.Q ;
  wire \MTRpwrn_MC.Q ;
  wire \MTXI_MC.Q ;
  wire \PAH0_MC.Q ;
  wire \PAH1_MC.Q ;
  wire \PAL0_MC.Q ;
  wire \PAL1_MC.Q ;
  wire \PBH0_MC.Q ;
  wire \PBH1_MC.Q ;
  wire \PBL0_MC.Q ;
  wire \PBL1_MC.Q ;
  wire \PresEn_MC.Q ;
  wire \PresSlct_MC.Q ;
  wire \SCLout_MC.Q ;
  wire \TP10_MC.Q ;
  wire \TP11_MC.Q ;
  wire \TP12_MC.Q ;
  wire \TmpEn_MC.Q ;
  wire \TmpSlct_MC.Q ;
  wire \U11_U2/Line_last_MC.Q ;
  wire \U11_U2/Line_last_MC.OE ;
  wire \U4/ctrlr<2>_MC.Q ;
  wire \U4/ctrlr<2>_MC.OE ;
  wire \U4/ctrlr<3>_MC.Q ;
  wire \U4/ctrlr<3>_MC.OE ;
  wire \U4/ctrlr<6>_MC.Q ;
  wire \U4/ctrlr<6>_MC.OE ;
  wire \U4/ctrlr<7>_MC.Q ;
  wire \U4/ctrlr<7>_MC.OE ;
  wire \U9/MISCr<0>_MC.Q ;
  wire \U9/MISCr<0>_MC.OE ;
  wire \U9/MISCr<1>_MC.Q ;
  wire \U9/MISCr<1>_MC.OE ;
  wire \U9/MISCr<4>_MC.Q ;
  wire \U9/MISCr<4>_MC.OE ;
  wire \AD<5>_MC.Q_tsimrenamed_net_ ;
  wire \AD<5>_MC.BUFOE.OUT ;
  wire \FOOBAR1__ctinst/7 ;
  wire \AD<5>_MC.D ;
  wire \AD<5>_MC.D1 ;
  wire \AD<5>_MC.D2 ;
  wire DCORI2CCNTr;
  wire \outDATA<5>\$WA0.UIM ;
  wire \AD<5>_MC.D2_PT_0 ;
  wire DCORCONFIGr;
  wire \outDATA<5>\$WA1.UIM ;
  wire \AD<5>_MC.D2_PT_1 ;
  wire DCORLIMITSr;
  wire \outDATA<5>\$WA2.UIM ;
  wire \AD<5>_MC.D2_PT_2 ;
  wire DCORENCPWRr;
  wire \outDATA<5>\$WA3.UIM ;
  wire \AD<5>_MC.D2_PT_3 ;
  wire \outDATA<5>\$WA5.UIM ;
  wire N_PZ_961;
  wire \AD<5>_MC.D2_PT_4 ;
  wire \outDATA<5>\$WA6.UIM ;
  wire N_PZ_987;
  wire \AD<5>_MC.D2_PT_5 ;
  wire \DCORI2CCNTr_MC.Q ;
  wire \DCORI2CCNTr_MC.D ;
  wire \DCORI2CCNTr_MC.D1 ;
  wire \DCORI2CCNTr_MC.D2 ;
  wire \U2_ADDR_reg<0>_MC.Q ;
  wire \U2_ADDR_reg<0>_MC.D ;
  wire \U2_ADDR_reg<0>_MC_tsimcreated_xor_ ;
  wire \U2_ADDR_reg<0>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ;
  wire \U2_ADDR_reg<0>_MC.D1 ;
  wire \U2_ADDR_reg<0>_MC.D2 ;
  wire \U2_ADDR_reg<0>_MC.D2_PT_0 ;
  wire \U2_ADDR_reg<0>_MC.D2_PT_1 ;
  wire \U2_ADDR_reg<0>_MC.D2_PT_2 ;
  wire U2_AutoInc;
  wire U2_WRRDedge;
  wire N_PZ_938;
  wire \U2_ADDR_reg<0>_MC.D2_PT_3 ;
  wire \U2_ADDR_reg<4>_MC.Q ;
  wire \U2_ADDR_reg<4>_MC.D ;
  wire \U2_ADDR_reg<4>_MC_tsimcreated_xor_ ;
  wire \U2_ADDR_reg<4>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ;
  wire \U2_ADDR_reg<4>_MC.D1 ;
  wire \U2_ADDR_reg<4>_MC.D2 ;
  wire \U2_ADDR_reg<4>_MC.D2_PT_0 ;
  wire \U2_ADDR_reg<4>_MC.D2_PT_1 ;
  wire \U2_ADDR_reg<4>_MC.D2_PT_2 ;
  wire \U2_ADDR_reg<5>_MC.Q ;
  wire \U2_ADDR_reg<5>_MC.D ;
  wire \U2_ADDR_reg<5>_MC_tsimcreated_xor_ ;
  wire \U2_ADDR_reg<5>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ;
  wire \U2_ADDR_reg<5>_MC.D1 ;
  wire \U2_ADDR_reg<5>_MC.D2 ;
  wire \U2_ADDR_reg<5>_MC.D2_PT_0 ;
  wire \U2_ADDR_reg<5>_MC.D2_PT_1 ;
  wire \U2_ADDR_reg<5>_MC.D2_PT_2 ;
  wire \U2_ADDR_reg<6>_MC.Q ;
  wire \U2_ADDR_reg<6>_MC.D ;
  wire \U2_ADDR_reg<6>_MC_tsimcreated_xor_ ;
  wire \U2_ADDR_reg<6>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ;
  wire \U2_ADDR_reg<6>_MC.D1 ;
  wire \U2_ADDR_reg<6>_MC.D2 ;
  wire \U2_ADDR_reg<6>_MC.D2_PT_0 ;
  wire \U2_ADDR_reg<6>_MC.D2_PT_1 ;
  wire \U2_ADDR_reg<6>_MC.D2_PT_2 ;
  wire \U2_ADDR_reg<7>_MC.Q ;
  wire \U2_ADDR_reg<7>_MC.D ;
  wire \U2_ADDR_reg<7>_MC_tsimcreated_xor_ ;
  wire \U2_ADDR_reg<7>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ;
  wire \U2_ADDR_reg<7>_MC.D1 ;
  wire \U2_ADDR_reg<7>_MC.D2 ;
  wire \U2_ADDR_reg<7>_MC.D2_PT_0 ;
  wire \U2_ADDR_reg<7>_MC.D2_PT_1 ;
  wire \U2_ADDR_reg<7>_MC.D2_PT_2 ;
  wire \U2_AutoInc_MC.Q ;
  wire \U2_AutoInc_MC.D ;
  wire \U2_AutoInc_MC.REG_tsimcreated_inv_Mclk_II/FCLK ;
  wire \FOOBAR5__ctinst/4 ;
  wire \U2_AutoInc_MC.D1 ;
  wire \U2_AutoInc_MC.D2 ;
  wire \U2_WRRDedge_MC.Q ;
  wire \U2_WRRDedge_MC.D ;
  wire \U2_WRRDedge_MC.REG_tsimcreated_inv_Mclk_II/FCLK ;
  wire \U2_WRRDedge_MC.D1 ;
  wire \U2_WRRDedge_MC.D2 ;
  wire \N_PZ_953_MC.Q ;
  wire N_PZ_953;
  wire \N_PZ_953_MC.D ;
  wire \N_PZ_953_MC.D1 ;
  wire \N_PZ_953_MC.D2 ;
  wire \N_PZ_938_MC.Q ;
  wire \N_PZ_938_MC.D ;
  wire \N_PZ_938_MC.D1 ;
  wire \N_PZ_938_MC.D2 ;
  wire \N_PZ_938_MC.D2_PT_0 ;
  wire \N_PZ_938_MC.D2_PT_1 ;
  wire \U2_ADDR_reg<3>_MC.Q ;
  wire \U2_ADDR_reg<3>_MC.D ;
  wire \U2_ADDR_reg<3>_MC_tsimcreated_xor_ ;
  wire \U2_ADDR_reg<3>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ;
  wire \U2_ADDR_reg<3>_MC.D1 ;
  wire \U2_ADDR_reg<3>_MC.D2 ;
  wire \U2_ADDR_reg<3>_MC.D2_PT_0 ;
  wire \U2_ADDR_reg<3>_MC.D2_PT_1 ;
  wire \U2_ADDR_reg<3>_MC.D2_PT_2 ;
  wire \U2_ADDR_reg<3>_MC.D2_PT_3 ;
  wire \U2_ADDR_reg<1>_MC.Q ;
  wire \U2_ADDR_reg<1>_MC.D ;
  wire \U2_ADDR_reg<1>_MC_tsimcreated_xor_ ;
  wire \U2_ADDR_reg<1>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ;
  wire \U2_ADDR_reg<1>_MC.D1 ;
  wire \U2_ADDR_reg<1>_MC.D2 ;
  wire \U2_ADDR_reg<1>_MC.D2_PT_0 ;
  wire \U2_ADDR_reg<1>_MC.D2_PT_1 ;
  wire \U2_ADDR_reg<1>_MC.D2_PT_2 ;
  wire \U2_ADDR_reg<1>_MC.D2_PT_3 ;
  wire \U2_ADDR_reg<2>_MC.Q ;
  wire \U2_ADDR_reg<2>_MC.D ;
  wire \U2_ADDR_reg<2>_MC_tsimcreated_xor_ ;
  wire \U2_ADDR_reg<2>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ;
  wire \U2_ADDR_reg<2>_MC.D1 ;
  wire \U2_ADDR_reg<2>_MC.D2 ;
  wire \U2_ADDR_reg<2>_MC.D2_PT_0 ;
  wire \U2_ADDR_reg<2>_MC.D2_PT_1 ;
  wire \U2_ADDR_reg<2>_MC.D2_PT_2 ;
  wire \U2_ADDR_reg<2>_MC.D2_PT_3 ;
  wire \outDATA<5>\$WA0.UIM_MC.Q ;
  wire \outDATA<5>\$WA0.UIM_MC.D ;
  wire \outDATA<5>\$WA0.UIM_MC.D1 ;
  wire \outDATA<5>\$WA0.UIM_MC.D2 ;
  wire \U11_U3_counterr<5>_MC.Q ;
  wire \U11_U3_counterr<5>_MC.D ;
  wire \U11_U3_counterr<5>_MC_tsimcreated_xor_ ;
  wire \U11_U3_counterr<5>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ;
  wire \U11_U3_counterr<5>_MC.D1 ;
  wire \U11_U3_counterr<5>_MC.D2 ;
  wire N_PZ_1065;
  wire \U11_U3_counterr<5>_MC.D2_PT_0 ;
  wire U11_Incdetect;
  wire \U11_U3_counterr<5>_MC.D2_PT_1 ;
  wire U11_SCLdetect;
  wire \U11_U3_counterr<5>_MC.D2_PT_2 ;
  wire \U11_U3_counterr<5>_MC.D2_PT_3 ;
  wire \N_PZ_1065_MC.Q ;
  wire \N_PZ_1065_MC.D ;
  wire \N_PZ_1065_MC.D1 ;
  wire \N_PZ_1065_MC.D2 ;
  wire \N_PZ_1065_MC.D2_PT_0 ;
  wire U11_ResetDetect;
  wire \N_PZ_1065_MC.D2_PT_1 ;
  wire \outDATA<7>\$WA4.UIM ;
  wire \N_PZ_1065_MC.D2_PT_2 ;
  wire \U11_Incdetect_MC.Q ;
  wire \U11_Incdetect_MC.D ;
  wire \U11_Incdetect_MC.REG_tsimcreated_inv_Mclk_II/FCLK ;
  wire \U11_Incdetect_MC.D1 ;
  wire \U11_Incdetect_MC.D2 ;
  wire \U11_ResetDetect_MC.Q ;
  wire \U11_ResetDetect_MC.D ;
  wire \U11_ResetDetect_MC.REG_tsimcreated_inv_Mclk_II/FCLK ;
  wire \U11_ResetDetect_MC.D1 ;
  wire \U11_ResetDetect_MC.D2 ;
  wire \U11_SCLdetect_MC.Q ;
  wire \U11_SCLdetect_MC.D ;
  wire \U11_SCLdetect_MC.REG_tsimcreated_inv_Mclk_II/FCLK ;
  wire \U11_SCLdetect_MC.D1 ;
  wire \U11_SCLdetect_MC.D2 ;
  wire \U11_U2/Line_last_MC.D ;
  wire \U11_U2/Line_last_MC.BUFOE.OUT ;
  wire \FOOBAR4__ctinst/0 ;
  wire \U11_U2/Line_last_MC.D1 ;
  wire \U11_U2/Line_last_MC.D2 ;
  wire \TP12_MC.Q_tsimrenamed_net_ ;
  wire \TP12_MC.UIM ;
  wire \TP12_MC.D ;
  wire \TP12_MC.D1 ;
  wire \TP12_MC.D2 ;
  wire \U11_U3_counterr<3>_MC.Q ;
  wire \U11_U3_counterr<3>_MC.D ;
  wire \U11_U3_counterr<3>_MC_tsimcreated_xor_ ;
  wire \U11_U3_counterr<3>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ;
  wire \U11_U3_counterr<3>_MC.D1 ;
  wire \U11_U3_counterr<3>_MC.D2 ;
  wire \U11_U3_counterr<3>_MC.D2_PT_0 ;
  wire \U11_U3_counterr<3>_MC.D2_PT_1 ;
  wire \U11_U3_counterr<3>_MC.D2_PT_2 ;
  wire \U11_U3_counterr<3>_MC.D2_PT_3 ;
  wire \U11_U3_counterr<3>_MC.D2_PT_4 ;
  wire \U11_U3_counterr<3>_MC.D2_PT_5 ;
  wire \U11_U3_counterr<3>_MC.D2_PT_6 ;
  wire \U11_U3_counterr<0>_MC.Q ;
  wire \U11_U3_counterr<0>_MC.D ;
  wire \U11_U3_counterr<0>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ;
  wire \U11_U3_counterr<0>_MC.D1 ;
  wire \U11_U3_counterr<0>_MC.D2 ;
  wire \U11_U3_counterr<0>_MC.D2_PT_0 ;
  wire \U11_U3_counterr<0>_MC.D2_PT_1 ;
  wire \U11_U3_counterr<0>_MC.D2_PT_2 ;
  wire \U11_U3_counterr<0>_MC.D2_PT_3 ;
  wire \U11_U3_counterr<0>_MC.D2_PT_4 ;
  wire \U11_U3_counterr<0>_MC.D2_PT_5 ;
  wire \U11_U3_counterr<1>_MC.Q ;
  wire \U11_U3_counterr<1>_MC.D ;
  wire \U11_U3_counterr<1>_MC_tsimcreated_xor_ ;
  wire \U11_U3_counterr<1>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ;
  wire \U11_U3_counterr<1>_MC.D1 ;
  wire \U11_U3_counterr<1>_MC.D2 ;
  wire \U11_U3_counterr<1>_MC.D2_PT_0 ;
  wire \U11_U3_counterr<1>_MC.D2_PT_1 ;
  wire \U11_U3_counterr<1>_MC.D2_PT_2 ;
  wire \U11_U3_counterr<2>_MC.Q ;
  wire \U11_U3_counterr<2>_MC.D ;
  wire \U11_U3_counterr<2>_MC_tsimcreated_xor_ ;
  wire \U11_U3_counterr<2>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ;
  wire \U11_U3_counterr<2>_MC.D1 ;
  wire \U11_U3_counterr<2>_MC.D2 ;
  wire \U11_U3_counterr<2>_MC.D2_PT_0 ;
  wire \U11_U3_counterr<2>_MC.D2_PT_1 ;
  wire \U11_U3_counterr<2>_MC.D2_PT_2 ;
  wire \U11_U3_counterr<4>_MC.Q ;
  wire \U11_U3_counterr<4>_MC.D ;
  wire \U11_U3_counterr<4>_MC_tsimcreated_xor_ ;
  wire \U11_U3_counterr<4>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ;
  wire \U11_U3_counterr<4>_MC.D1 ;
  wire \U11_U3_counterr<4>_MC.D2 ;
  wire \U11_U3_counterr<4>_MC.D2_PT_0 ;
  wire \U11_U3_counterr<4>_MC.D2_PT_1 ;
  wire \U11_U3_counterr<4>_MC.D2_PT_2 ;
  wire \U11_U3_counterr<4>_MC.D2_PT_3 ;
  wire \outDATA<7>\$WA4.UIM_MC.Q ;
  wire \outDATA<7>\$WA4.UIM_MC.D ;
  wire \outDATA<7>\$WA4.UIM_MC.D1 ;
  wire \outDATA<7>\$WA4.UIM_MC.D2 ;
  wire \DCORCONFIGr_MC.Q ;
  wire \DCORCONFIGr_MC.D ;
  wire \DCORCONFIGr_MC.D1 ;
  wire \DCORCONFIGr_MC.D2 ;
  wire \outDATA<5>\$WA1.UIM_MC.Q ;
  wire \outDATA<5>\$WA1.UIM_MC.D ;
  wire \outDATA<5>\$WA1.UIM_MC.D1 ;
  wire \outDATA<5>\$WA1.UIM_MC.D2 ;
  wire \DCORLIMITSr_MC.Q ;
  wire \DCORLIMITSr_MC.D ;
  wire \DCORLIMITSr_MC.D1 ;
  wire \DCORLIMITSr_MC.D2 ;
  wire \outDATA<5>\$WA2.UIM_MC.Q ;
  wire \outDATA<5>\$WA2.UIM_MC.D ;
  wire \outDATA<5>\$WA2.UIM_MC.D1 ;
  wire \outDATA<5>\$WA2.UIM_MC.D2 ;
  wire \DCORENCPWRr_MC.Q ;
  wire \DCORENCPWRr_MC.D ;
  wire \DCORENCPWRr_MC.D1 ;
  wire \DCORENCPWRr_MC.D2 ;
  wire \outDATA<5>\$WA3.UIM_MC.Q ;
  wire \outDATA<5>\$WA3.UIM_MC.D ;
  wire \outDATA<5>\$WA3.UIM_MC.D1 ;
  wire \outDATA<5>\$WA3.UIM_MC.D2 ;
  wire NET2528;
  wire \outDATA<5>\$WA3.UIM_MC.D2_PT_0 ;
  wire \outDATA<5>\$WA3.UIM_MC.D2_PT_1 ;
  wire \NET2528_MC.Q ;
  wire \NET2528_MC.D ;
  wire \NET2528_MC.REG_tsimcreated_inv_Mclk_II/FCLK ;
  wire \NET2528_MC.D1 ;
  wire \NET2528_MC.D2 ;
  wire DCORIFGw;
  wire \NET2528_MC.D2_PT_0 ;
  wire \NET2528_MC.D2_PT_1 ;
  wire \DCORIFGw_MC.Q ;
  wire \DCORIFGw_MC.D ;
  wire \DCORIFGw_MC.D1 ;
  wire \DCORIFGw_MC.D2 ;
  wire \U4/orFLGs_MC.Q ;
  wire \U4/orFLGs ;
  wire \U4/orFLGs_MC.D ;
  wire \U4/orFLGs_MC.D1 ;
  wire \U4/orFLGs_MC.D2 ;
  wire \outDATA<5>\$WA5.UIM_MC.Q ;
  wire \outDATA<5>\$WA5.UIM_MC.D ;
  wire \outDATA<5>\$WA5.UIM_MC.D1 ;
  wire \outDATA<5>\$WA5.UIM_MC.D2 ;
  wire DCOR0CNTLOWr;
  wire \outDATA<5>\$WA5.UIM_MC.D2_PT_0 ;
  wire DCOR1CNTLOWr;
  wire \outDATA<5>\$WA5.UIM_MC.D2_PT_1 ;
  wire DCOR0CNTHIGHr;
  wire \outDATA<5>\$WA5.UIM_MC.D2_PT_2 ;
  wire \outDATA<5>\$WA5.UIM_MC.D2_PT_3 ;
  wire \U1/U3/holdingreg0<5>_MC.Q ;
  wire \U1/U3/holdingreg0<5>_MC.D ;
  wire \U1/U3/holdingreg0<5>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ;
  wire \U1/U3/holdingreg0<5>_MC.D1 ;
  wire \U1/U3/holdingreg0<5>_MC.D2 ;
  wire \U1/U3/holdingreg0<5>_MC.D2_PT_0 ;
  wire \U1/U3/holdingreg0<5>_MC.D2_PT_1 ;
  wire \U1/Channel0<5>_MC.Q ;
  wire \U1/Channel0<5>_MC.D ;
  wire \U1/Channel0<5>_MC_tsimcreated_xor_ ;
  wire \U1/Channel0<5>_MC.D1 ;
  wire \U1/Channel0<5>_MC.D2 ;
  wire N_PZ_928;
  wire \U1/Channel0<5>_MC.D2_PT_0 ;
  wire N_PZ_964;
  wire \U1/Channel0<5>_MC.D2_PT_1 ;
  wire N_PZ_968;
  wire \U1/Channel0<5>_MC.D2_PT_2 ;
  wire \N_PZ_928_MC.Q ;
  wire \N_PZ_928_MC.D ;
  wire \N_PZ_928_MC.D1 ;
  wire \N_PZ_928_MC.D2 ;
  wire \U1/Zero0 ;
  wire \U1/Zero0_MC.Q ;
  wire \U1/Zero0_MC.D ;
  wire \U1/Zero0_MC.REG_tsimcreated_inv_Mclk_II/FCLK ;
  wire \U1/Zero0_MC.D1 ;
  wire \U1/Zero0_MC.D2 ;
  wire \U1/Zero0_MC.D2_PT_0 ;
  wire \U1/Zero0_MC.D2_PT_1 ;
  wire DCORENCCTLw;
  wire \U1/Zero0_MC.D2_PT_2 ;
  wire NET2482;
  wire \U1/U4/RF0r ;
  wire \U1/U4/E0r ;
  wire \U1/U4/HE0statelastr ;
  wire \U1/Zero0_MC.D2_PT_3 ;
  wire \U1/Zero0_MC.D2_PT_4 ;
  wire \DCORENCCTLw_MC.Q ;
  wire \DCORENCCTLw_MC.D ;
  wire \DCORENCCTLw_MC.D1 ;
  wire \DCORENCCTLw_MC.D2 ;
  wire \NET2482_MC.Q ;
  wire \NET2482_MC.D ;
  wire NET2482_MC_tsimcreated_xor_;
  wire \NET2482_MC.REG_tsimcreated_inv_Mclk_II/FCLK ;
  wire \NET2482_MC.D1 ;
  wire \NET2482_MC.D2 ;
  wire \NET2482_MC.D2_PT_0 ;
  wire \NET2482_MC.D2_PT_1 ;
  wire \NET2482_MC.D2_PT_2 ;
  wire \NET2482_MC.D2_PT_3 ;
  wire \U1/U4/RF0r_MC.Q ;
  wire \U1/U4/RF0r_MC.D ;
  wire \U1/U4/RF0r_MC.REG_tsimcreated_inv_Mclk_II/FCLK ;
  wire \U1/U4/RF0r_MC.D1 ;
  wire \U1/U4/RF0r_MC.D2 ;
  wire \U1/U4/RF0r_MC.D2_PT_0 ;
  wire \U1/U4/RF0r_MC.D2_PT_1 ;
  wire \U1/U4/E0r_MC.Q ;
  wire \U1/U4/E0r_MC.D ;
  wire \U1/U4/E0r_MC.REG_tsimcreated_inv_Mclk_II/FCLK ;
  wire \U1/U4/E0r_MC.D1 ;
  wire \U1/U4/E0r_MC.D2 ;
  wire \U1/U4/E0r_MC.D2_PT_0 ;
  wire \U1/U4/E0r_MC.D2_PT_1 ;
  wire \U1/U4/HE0statelastr_MC.Q ;
  wire \U1/U4/HE0statelastr_MC.D ;
  wire \U1/U4/HE0statelastr_MC.REG_tsimcreated_inv_Mclk_II/FCLK ;
  wire \U1/U4/HE0statelastr_MC.D1 ;
  wire \U1/U4/HE0statelastr_MC.D2 ;
  wire \U1/U2/location_Maddsub__n0000__n0067<0>_MC.Q ;
  wire \U1/U2/location_Maddsub__n0000__n0067<0>_MC.D ;
  wire \U1/U2/location_Maddsub__n0000__n0067<0>_MC.D1 ;
  wire \U1/U2/location_Maddsub__n0000__n0067<0>_MC.D2 ;
  wire N_PZ_943;
  wire \U1/U2/location_Maddsub__n0000__n0067<0>_MC.D2_PT_0 ;
  wire \U1/U2/location_Maddsub__n0000__n0067<0>_MC.D2_PT_1 ;
  wire \N_PZ_943_MC.Q ;
  wire \N_PZ_943_MC.D ;
  wire \N_PZ_943_MC.D1 ;
  wire \N_PZ_943_MC.D2 ;
  wire \U1/NET3721 ;
  wire \U1/U1/CurrState_Sreg0_FFD1 ;
  wire \U1/U1/CurrState_Sreg0_FFD3 ;
  wire \U1/U1/CurrState_Sreg0_FFD2 ;
  wire \N_PZ_943_MC.D2_PT_0 ;
  wire \U1/U1/CurrState_Sreg0_FFD4 ;
  wire \N_PZ_943_MC.D2_PT_1 ;
  wire \U1/NET3721_MC.Q ;
  wire \U1/NET3721_MC.D ;
  wire \U1/NET3721_MC.REG_tsimcreated_inv_Mclk_II/FCLK ;
  wire \U1/NET3721_MC.D1 ;
  wire \U1/NET3721_MC.D2 ;
  wire \U1/NET3721_MC.D2_PT_0 ;
  wire \U1/NET3721_MC.D2_PT_1 ;
  wire \U1/U1/CurrState_Sreg0_FFD1_MC.Q ;
  wire \U1/U1/CurrState_Sreg0_FFD1_MC.D ;
  wire \U1/U1/CurrState_Sreg0_FFD1_MC.D1 ;
  wire \U1/U1/CurrState_Sreg0_FFD1_MC.D2 ;
  wire \U1/U1/CurrState_Sreg0_FFD1_MC.D2_PT_0 ;
  wire \U1/U1/CurrState_Sreg0_FFD1_MC.D2_PT_1 ;
  wire \U1/U1/CurrState_Sreg0_FFD1_MC.D2_PT_2 ;
  wire \U1/U1/CurrState_Sreg0_FFD3_MC.Q ;
  wire \U1/U1/CurrState_Sreg0_FFD3_MC.D ;
  wire \U1/U1/CurrState_Sreg0_FFD3_MC.D1 ;
  wire \U1/U1/CurrState_Sreg0_FFD3_MC.D2 ;
  wire \U1/U1/CurrState_Sreg0_FFD3_MC.D2_PT_0 ;
  wire \U1/U1/CurrState_Sreg0_FFD3_MC.D2_PT_1 ;
  wire \U1/U1/CurrState_Sreg0_FFD3_MC.D2_PT_2 ;
  wire \U1/U1/CurrState_Sreg0_FFD3_MC.D2_PT_3 ;
  wire \U1/U1/CurrState_Sreg0_FFD2_MC.Q ;
  wire \U1/U1/CurrState_Sreg0_FFD2_MC.D ;
  wire \U1/U1/CurrState_Sreg0_FFD2_MC.D1 ;
  wire \U1/U1/CurrState_Sreg0_FFD2_MC.D2 ;
  wire \U1/U1/CurrState_Sreg0_FFD2_MC.D2_PT_0 ;
  wire \U1/U1/CurrState_Sreg0_FFD2_MC.D2_PT_1 ;
  wire \U1/U1/CurrState_Sreg0_FFD2_MC.D2_PT_2 ;
  wire \U1/U1/CurrState_Sreg0_FFD2_MC.D2_PT_3 ;
  wire \U1/U1/CurrState_Sreg0_FFD2_MC.D2_PT_4 ;
  wire \U1/U1/CurrState_Sreg0_FFD2_MC.D2_PT_5 ;
  wire \U1/U1/CurrState_Sreg0_FFD2_MC.D2_PT_6 ;
  wire \U1/U1/CurrState_Sreg0_FFD2_MC.D2_PT_7 ;
  wire \U1/U1/CurrState_Sreg0_FFD4_MC.Q ;
  wire \U1/U1/CurrState_Sreg0_FFD4_MC.D ;
  wire \U1/U1/CurrState_Sreg0_FFD4_MC.D1 ;
  wire \U1/U1/CurrState_Sreg0_FFD4_MC.D2 ;
  wire \U1/Channel0<0>_MC.Q ;
  wire \U1/Channel0<0>_MC.D ;
  wire \U1/Channel0<0>_MC_tsimcreated_xor_ ;
  wire \U1/Channel0<0>_MC.D1 ;
  wire \U1/Channel0<0>_MC.D2 ;
  wire \U1/Channel0<0>_MC.D2_PT_0 ;
  wire \U1/Channel0<0>_MC.D2_PT_1 ;
  wire \U1/Channel0<0>_MC.D2_PT_2 ;
  wire \U1/Channel0<1>_MC.Q ;
  wire \U1/Channel0<1>_MC.D ;
  wire \U1/Channel0<1>_MC_tsimcreated_xor_ ;
  wire \U1/Channel0<1>_MC.D1 ;
  wire \U1/Channel0<1>_MC.D2 ;
  wire \U1/Channel0<1>_MC.D2_PT_0 ;
  wire \U1/Channel0<1>_MC.D2_PT_1 ;
  wire \U1/Channel0<1>_MC.D2_PT_2 ;
  wire \N_PZ_964_MC.Q ;
  wire \N_PZ_964_MC.D ;
  wire \N_PZ_964_MC.D1 ;
  wire \N_PZ_964_MC.D2 ;
  wire \N_PZ_964_MC.D2_PT_0 ;
  wire \N_PZ_964_MC.D2_PT_1 ;
  wire \N_PZ_968_MC.Q ;
  wire \N_PZ_968_MC.D ;
  wire \N_PZ_968_MC.D1 ;
  wire \N_PZ_968_MC.D2 ;
  wire \N_PZ_968_MC.D2_PT_0 ;
  wire \N_PZ_968_MC.D2_PT_1 ;
  wire \U1/Channel0<2>_MC.Q ;
  wire \U1/Channel0<2>_MC.D ;
  wire \U1/Channel0<2>_MC_tsimcreated_xor_ ;
  wire \U1/Channel0<2>_MC.D1 ;
  wire \U1/Channel0<2>_MC.D2 ;
  wire \U1/Channel0<2>_MC.D2_PT_0 ;
  wire \U1/Channel0<2>_MC.D2_PT_1 ;
  wire \U1/Channel0<2>_MC.D2_PT_2 ;
  wire \U1/Channel0<3>_MC.Q ;
  wire \U1/Channel0<3>_MC.D ;
  wire \U1/Channel0<3>_MC_tsimcreated_xor_ ;
  wire \U1/Channel0<3>_MC.D1 ;
  wire \U1/Channel0<3>_MC.D2 ;
  wire \U1/Channel0<3>_MC.D2_PT_0 ;
  wire \U1/Channel0<3>_MC.D2_PT_1 ;
  wire \U1/Channel0<3>_MC.D2_PT_2 ;
  wire \U1/Channel0<4>_MC.Q ;
  wire \U1/Channel0<4>_MC.D ;
  wire \U1/Channel0<4>_MC_tsimcreated_xor_ ;
  wire \U1/Channel0<4>_MC.D1 ;
  wire \U1/Channel0<4>_MC.D2 ;
  wire \U1/Channel0<4>_MC.D2_PT_0 ;
  wire \U1/Channel0<4>_MC.D2_PT_1 ;
  wire \U1/Channel0<4>_MC.D2_PT_2 ;
  wire \U1/Channel0<4>_MC.D2_PT_3 ;
  wire \U1/Channel0<4>_MC.D2_PT_4 ;
  wire \U1/Channel0<4>_MC.D2_PT_5 ;
  wire \DCOR0CNTLOWr_MC.Q ;
  wire \DCOR0CNTLOWr_MC.D ;
  wire \DCOR0CNTLOWr_MC.D1 ;
  wire \DCOR0CNTLOWr_MC.D2 ;
  wire \U1/U3/holdingreg1<5>_MC.Q ;
  wire \U1/U3/holdingreg1<5>_MC.D ;
  wire \U1/U3/holdingreg1<5>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ;
  wire \U1/U3/holdingreg1<5>_MC.D1 ;
  wire \U1/U3/holdingreg1<5>_MC.D2 ;
  wire \U1/U3/holdingreg1<5>_MC.D2_PT_0 ;
  wire \U1/U3/holdingreg1<5>_MC.D2_PT_1 ;
  wire \U1/Channel1<5>_MC.Q ;
  wire \U1/Channel1<5>_MC.D ;
  wire \U1/Channel1<5>_MC_tsimcreated_xor_ ;
  wire \U1/Channel1<5>_MC.D1 ;
  wire \U1/Channel1<5>_MC.D2 ;
  wire N_PZ_929;
  wire \U1/Channel1<5>_MC.D2_PT_0 ;
  wire \U1/Zero1 ;
  wire \U1/U6/CurrState_Sreg0_FFD3 ;
  wire \U1/U6/CurrState_Sreg0_FFD2 ;
  wire N_PZ_921;
  wire \U1/Channel1<5>_MC.D2_PT_1 ;
  wire N_PZ_1092;
  wire \U1/Channel1<5>_MC.D2_PT_2 ;
  wire \N_PZ_929_MC.Q ;
  wire \N_PZ_929_MC.D ;
  wire \N_PZ_929_MC.D1 ;
  wire \N_PZ_929_MC.D2 ;
  wire \U1/Zero1_MC.Q ;
  wire \U1/Zero1_MC.D ;
  wire \U1/Zero1_MC.REG_tsimcreated_inv_Mclk_II/FCLK ;
  wire \U1/Zero1_MC.D1 ;
  wire \U1/Zero1_MC.D2 ;
  wire \U1/Zero1_MC.D2_PT_0 ;
  wire \U1/Zero1_MC.D2_PT_1 ;
  wire \U1/Zero1_MC.D2_PT_2 ;
  wire NET2493;
  wire \U1/U4/RF1r ;
  wire \U1/U4/E1r ;
  wire \U1/U4/HE1statelastr ;
  wire \U1/Zero1_MC.D2_PT_3 ;
  wire \U1/Zero1_MC.D2_PT_4 ;
  wire \NET2493_MC.Q ;
  wire \NET2493_MC.D ;
  wire NET2493_MC_tsimcreated_xor_;
  wire \NET2493_MC.REG_tsimcreated_inv_Mclk_II/FCLK ;
  wire \NET2493_MC.D1 ;
  wire \NET2493_MC.D2 ;
  wire \NET2493_MC.D2_PT_0 ;
  wire \NET2493_MC.D2_PT_1 ;
  wire \NET2493_MC.D2_PT_2 ;
  wire \NET2493_MC.D2_PT_3 ;
  wire \U1/U4/RF1r_MC.Q ;
  wire \U1/U4/RF1r_MC.D ;
  wire \U1/U4/RF1r_MC.REG_tsimcreated_inv_Mclk_II/FCLK ;
  wire \U1/U4/RF1r_MC.D1 ;
  wire \U1/U4/RF1r_MC.D2 ;
  wire \U1/U4/RF1r_MC.D2_PT_0 ;
  wire \U1/U4/RF1r_MC.D2_PT_1 ;
  wire \U1/U4/E1r_MC.Q ;
  wire \U1/U4/E1r_MC.D ;
  wire \U1/U4/E1r_MC.REG_tsimcreated_inv_Mclk_II/FCLK ;
  wire \U1/U4/E1r_MC.D1 ;
  wire \U1/U4/E1r_MC.D2 ;
  wire \U1/U4/E1r_MC.D2_PT_0 ;
  wire \U1/U4/E1r_MC.D2_PT_1 ;
  wire \U1/U4/HE1statelastr_MC.Q ;
  wire \U1/U4/HE1statelastr_MC.D ;
  wire \U1/U4/HE1statelastr_MC.REG_tsimcreated_inv_Mclk_II/FCLK ;
  wire \U1/U4/HE1statelastr_MC.D1 ;
  wire \U1/U4/HE1statelastr_MC.D2 ;
  wire \U1/U6/CurrState_Sreg0_FFD3_MC.Q ;
  wire \U1/U6/CurrState_Sreg0_FFD3_MC.D ;
  wire \U1/U6/CurrState_Sreg0_FFD3_MC.D1 ;
  wire \U1/U6/CurrState_Sreg0_FFD3_MC.D2 ;
  wire \U1/U6/CurrState_Sreg0_FFD4 ;
  wire \U1/U6/CurrState_Sreg0_FFD3_MC.D2_PT_0 ;
  wire \U1/U6/CurrState_Sreg0_FFD1 ;
  wire \U1/U6/CurrState_Sreg0_FFD3_MC.D2_PT_1 ;
  wire \U1/U6/CurrState_Sreg0_FFD3_MC.D2_PT_2 ;
  wire \U1/U6/CurrState_Sreg0_FFD3_MC.D2_PT_3 ;
  wire \U1/U6/CurrState_Sreg0_FFD1_MC.Q ;
  wire \U1/U6/CurrState_Sreg0_FFD1_MC.D ;
  wire \U1/U6/CurrState_Sreg0_FFD1_MC.D1 ;
  wire \U1/U6/CurrState_Sreg0_FFD1_MC.D2 ;
  wire \U1/U6/CurrState_Sreg0_FFD1_MC.D2_PT_0 ;
  wire \U1/U6/CurrState_Sreg0_FFD1_MC.D2_PT_1 ;
  wire \U1/U6/CurrState_Sreg0_FFD1_MC.D2_PT_2 ;
  wire \U1/U6/CurrState_Sreg0_FFD4_MC.Q ;
  wire \U1/U6/CurrState_Sreg0_FFD4_MC.D ;
  wire \U1/U6/CurrState_Sreg0_FFD4_MC.D1 ;
  wire \U1/U6/CurrState_Sreg0_FFD4_MC.D2 ;
  wire \U1/U6/CurrState_Sreg0_FFD2_MC.Q ;
  wire \U1/U6/CurrState_Sreg0_FFD2_MC.D ;
  wire \U1/U6/CurrState_Sreg0_FFD2_MC.D1 ;
  wire \U1/U6/CurrState_Sreg0_FFD2_MC.D2 ;
  wire \U1/U6/CurrState_Sreg0_FFD2_MC.D2_PT_0 ;
  wire \U1/U6/CurrState_Sreg0_FFD2_MC.D2_PT_1 ;
  wire \U1/U6/CurrState_Sreg0_FFD2_MC.D2_PT_2 ;
  wire \U1/U6/CurrState_Sreg0_FFD2_MC.D2_PT_3 ;
  wire \U1/U6/CurrState_Sreg0_FFD2_MC.D2_PT_4 ;
  wire \U1/U6/CurrState_Sreg0_FFD2_MC.D2_PT_5 ;
  wire \U1/U6/CurrState_Sreg0_FFD2_MC.D2_PT_6 ;
  wire \U1/U6/CurrState_Sreg0_FFD2_MC.D2_PT_7 ;
  wire \U1/U5/location_Maddsub__n0000__n0067<0>_MC.Q ;
  wire \U1/U5/location_Maddsub__n0000__n0067<0>_MC.D ;
  wire \U1/U5/location_Maddsub__n0000__n0067<0>_MC.D1 ;
  wire \U1/U5/location_Maddsub__n0000__n0067<0>_MC.D2 ;
  wire N_PZ_944;
  wire \U1/U5/location_Maddsub__n0000__n0067<0>_MC.D2_PT_0 ;
  wire \U1/U5/location_Maddsub__n0000__n0067<0>_MC.D2_PT_1 ;
  wire \N_PZ_944_MC.Q ;
  wire \N_PZ_944_MC.D ;
  wire \N_PZ_944_MC.D1 ;
  wire \N_PZ_944_MC.D2 ;
  wire \U1/NET3720 ;
  wire \N_PZ_944_MC.D2_PT_0 ;
  wire \N_PZ_944_MC.D2_PT_1 ;
  wire \U1/NET3720_MC.Q ;
  wire \U1/NET3720_MC.D ;
  wire \U1/NET3720_MC.REG_tsimcreated_inv_Mclk_II/FCLK ;
  wire \U1/NET3720_MC.D1 ;
  wire \U1/NET3720_MC.D2 ;
  wire \U1/NET3720_MC.D2_PT_0 ;
  wire \U1/NET3720_MC.D2_PT_1 ;
  wire \U1/Channel1<0>_MC.Q ;
  wire \U1/Channel1<0>_MC.D ;
  wire \U1/Channel1<0>_MC_tsimcreated_xor_ ;
  wire \U1/Channel1<0>_MC.D1 ;
  wire \U1/Channel1<0>_MC.D2 ;
  wire \U1/Channel1<0>_MC.D2_PT_0 ;
  wire \U1/Channel1<0>_MC.D2_PT_1 ;
  wire \N_PZ_1092_MC.Q ;
  wire \N_PZ_1092_MC.D ;
  wire \N_PZ_1092_MC.D1 ;
  wire \N_PZ_1092_MC.D2 ;
  wire \N_PZ_1092_MC.D2_PT_0 ;
  wire \N_PZ_1092_MC.D2_PT_1 ;
  wire \U1/Channel1<1>_MC.Q ;
  wire \U1/Channel1<1>_MC.D ;
  wire \U1/Channel1<1>_MC_tsimcreated_xor_ ;
  wire \U1/Channel1<1>_MC.D1 ;
  wire \U1/Channel1<1>_MC.D2 ;
  wire \U1/Channel1<1>_MC.D2_PT_0 ;
  wire \U1/Channel1<1>_MC.D2_PT_1 ;
  wire \U1/Channel1<1>_MC.D2_PT_2 ;
  wire \N_PZ_921_MC.Q ;
  wire \N_PZ_921_MC.D ;
  wire \N_PZ_921_MC.D1 ;
  wire \N_PZ_921_MC.D2 ;
  wire \N_PZ_921_MC.D2_PT_0 ;
  wire \N_PZ_921_MC.D2_PT_1 ;
  wire \U1/Channel1<2>_MC.Q ;
  wire \U1/Channel1<2>_MC.D ;
  wire \U1/Channel1<2>_MC_tsimcreated_xor_ ;
  wire \U1/Channel1<2>_MC.D1 ;
  wire \U1/Channel1<2>_MC.D2 ;
  wire \U1/Channel1<2>_MC.D2_PT_0 ;
  wire \U1/Channel1<2>_MC.D2_PT_1 ;
  wire \U1/Channel1<2>_MC.D2_PT_2 ;
  wire \U1/Channel1<3>_MC.Q ;
  wire \U1/Channel1<3>_MC.D ;
  wire \U1/Channel1<3>_MC_tsimcreated_xor_ ;
  wire \U1/Channel1<3>_MC.D1 ;
  wire \U1/Channel1<3>_MC.D2 ;
  wire \U1/Channel1<3>_MC.D2_PT_0 ;
  wire \U1/Channel1<3>_MC.D2_PT_1 ;
  wire \U1/Channel1<3>_MC.D2_PT_2 ;
  wire \U1/Channel1<4>_MC.Q ;
  wire \U1/Channel1<4>_MC.D ;
  wire \U1/Channel1<4>_MC_tsimcreated_xor_ ;
  wire \U1/Channel1<4>_MC.D1 ;
  wire \U1/Channel1<4>_MC.D2 ;
  wire \U1/Channel1<4>_MC.D2_PT_0 ;
  wire \U1/Channel1<4>_MC.D2_PT_1 ;
  wire \U1/Channel1<4>_MC.D2_PT_2 ;
  wire \U1/Channel1<4>_MC.D2_PT_3 ;
  wire \U1/Channel1<4>_MC.D2_PT_4 ;
  wire \U1/Channel1<4>_MC.D2_PT_5 ;
  wire \U1/Channel1<4>_MC.D2_PT_6 ;
  wire \U1/Channel1<4>_MC.D2_PT_7 ;
  wire \DCOR1CNTLOWr_MC.Q ;
  wire \DCOR1CNTLOWr_MC.D ;
  wire \DCOR1CNTLOWr_MC.D1 ;
  wire \DCOR1CNTLOWr_MC.D2 ;
  wire \U1/U3/holdingreg0<13>_MC.Q ;
  wire \U1/U3/holdingreg0<13>_MC.D ;
  wire \U1/U3/holdingreg0<13>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ;
  wire \U1/U3/holdingreg0<13>_MC.D1 ;
  wire \U1/U3/holdingreg0<13>_MC.D2 ;
  wire \U1/U3/holdingreg0<13>_MC.D2_PT_0 ;
  wire \U1/U3/holdingreg0<13>_MC.D2_PT_1 ;
  wire \U1/Channel0<13>_MC.Q ;
  wire \U1/Channel0<13>_MC.D ;
  wire \U1/Channel0<13>_MC_tsimcreated_xor_ ;
  wire \U1/Channel0<13>_MC.D1 ;
  wire \U1/Channel0<13>_MC.D2 ;
  wire \U1/Channel0<13>_MC.D2_PT_0 ;
  wire \U1/Channel0<13>_MC.D2_PT_1 ;
  wire \U1/Channel0<13>_MC.D2_PT_2 ;
  wire \U1/Channel0<10>_MC.Q ;
  wire \U1/Channel0<10>_MC.D ;
  wire \U1/Channel0<10>_MC_tsimcreated_xor_ ;
  wire \U1/Channel0<10>_MC.D1 ;
  wire \U1/Channel0<10>_MC.D2 ;
  wire \U1/Channel0<10>_MC.D2_PT_0 ;
  wire \U1/Channel0<10>_MC.D2_PT_1 ;
  wire \U1/Channel0<10>_MC.D2_PT_2 ;
  wire \U1/Channel0<9>_MC.Q ;
  wire \U1/Channel0<9>_MC.D ;
  wire \U1/Channel0<9>_MC_tsimcreated_xor_ ;
  wire \U1/Channel0<9>_MC.D1 ;
  wire \U1/Channel0<9>_MC.D2 ;
  wire \U1/Channel0<9>_MC.D2_PT_0 ;
  wire \U1/Channel0<9>_MC.D2_PT_1 ;
  wire \U1/Channel0<9>_MC.D2_PT_2 ;
  wire \U1/U2/location_Maddsub__n0000__n0075<0>_MC.Q ;
  wire \U1/U2/location_Maddsub__n0000__n0075<0>_MC.D ;
  wire \U1/U2/location_Maddsub__n0000__n0075<0>_MC.D1 ;
  wire \U1/U2/location_Maddsub__n0000__n0075<0>_MC.D2 ;
  wire \U1/U2/location_Maddsub__n0000__n0075<0>_MC.D2_PT_0 ;
  wire \U1/U2/location_Maddsub__n0000__n0075<0>_MC.D2_PT_1 ;
  wire \U1/Channel0<6>_MC.Q ;
  wire \U1/Channel0<6>_MC.D ;
  wire \U1/Channel0<6>_MC_tsimcreated_xor_ ;
  wire \U1/Channel0<6>_MC.D1 ;
  wire \U1/Channel0<6>_MC.D2 ;
  wire \U1/Channel0<6>_MC.D2_PT_0 ;
  wire \U1/Channel0<6>_MC.D2_PT_1 ;
  wire \U1/Channel0<6>_MC.D2_PT_2 ;
  wire \U1/Channel0<7>_MC.Q ;
  wire \U1/Channel0<7>_MC.D ;
  wire \U1/Channel0<7>_MC_tsimcreated_xor_ ;
  wire \U1/Channel0<7>_MC.D1 ;
  wire \U1/Channel0<7>_MC.D2 ;
  wire \U1/Channel0<7>_MC.D2_PT_0 ;
  wire \U1/Channel0<7>_MC.D2_PT_1 ;
  wire \U1/Channel0<7>_MC.D2_PT_2 ;
  wire \U1/Channel0<8>_MC.Q ;
  wire \U1/Channel0<8>_MC.D ;
  wire \U1/Channel0<8>_MC_tsimcreated_xor_ ;
  wire \U1/Channel0<8>_MC.D1 ;
  wire \U1/Channel0<8>_MC.D2 ;
  wire \U1/Channel0<8>_MC.D2_PT_0 ;
  wire \U1/Channel0<8>_MC.D2_PT_1 ;
  wire \U1/Channel0<8>_MC.D2_PT_2 ;
  wire \U1/Channel0<8>_MC.D2_PT_3 ;
  wire \U1/Channel0<8>_MC.D2_PT_4 ;
  wire \U1/Channel0<8>_MC.D2_PT_5 ;
  wire \U1/Channel0<11>_MC.Q ;
  wire \U1/Channel0<11>_MC.D ;
  wire \U1/Channel0<11>_MC_tsimcreated_xor_ ;
  wire \U1/Channel0<11>_MC.D1 ;
  wire \U1/Channel0<11>_MC.D2 ;
  wire \U1/Channel0<11>_MC.D2_PT_0 ;
  wire \U1/Channel0<11>_MC.D2_PT_1 ;
  wire \U1/Channel0<11>_MC.D2_PT_2 ;
  wire \U1/Channel0<12>_MC.Q ;
  wire \U1/Channel0<12>_MC.D ;
  wire \U1/Channel0<12>_MC_tsimcreated_xor_ ;
  wire \U1/Channel0<12>_MC.D1 ;
  wire \U1/Channel0<12>_MC.D2 ;
  wire \U1/Channel0<12>_MC.D2_PT_0 ;
  wire \U1/Channel0<12>_MC.D2_PT_1 ;
  wire \U1/Channel0<12>_MC.D2_PT_2 ;
  wire \DCOR0CNTHIGHr_MC.Q ;
  wire \DCOR0CNTHIGHr_MC.D ;
  wire \DCOR0CNTHIGHr_MC.D1 ;
  wire \DCOR0CNTHIGHr_MC.D2 ;
  wire \U1/U3/holdingreg1<13>_MC.Q ;
  wire \U1/U3/holdingreg1<13>_MC.D ;
  wire \U1/U3/holdingreg1<13>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ;
  wire \U1/U3/holdingreg1<13>_MC.D1 ;
  wire \U1/U3/holdingreg1<13>_MC.D2 ;
  wire \U1/U3/holdingreg1<13>_MC.D2_PT_0 ;
  wire \U1/U3/holdingreg1<13>_MC.D2_PT_1 ;
  wire \U1/Channel1<13>_MC.Q ;
  wire \U1/Channel1<13>_MC.D ;
  wire \U1/Channel1<13>_MC_tsimcreated_xor_ ;
  wire \U1/Channel1<13>_MC.D1 ;
  wire \U1/Channel1<13>_MC.D2 ;
  wire \U1/Channel1<13>_MC.D2_PT_0 ;
  wire \U1/Channel1<13>_MC.D2_PT_1 ;
  wire \U1/Channel1<13>_MC.D2_PT_2 ;
  wire \U1/Channel1<10>_MC.Q ;
  wire \U1/Channel1<10>_MC.D ;
  wire \U1/Channel1<10>_MC_tsimcreated_xor_ ;
  wire \U1/Channel1<10>_MC.D1 ;
  wire \U1/Channel1<10>_MC.D2 ;
  wire \U1/Channel1<10>_MC.D2_PT_0 ;
  wire \U1/Channel1<10>_MC.D2_PT_1 ;
  wire \U1/Channel1<10>_MC.D2_PT_2 ;
  wire \U1/Channel1<9>_MC.Q ;
  wire \U1/Channel1<9>_MC.D ;
  wire \U1/Channel1<9>_MC_tsimcreated_xor_ ;
  wire \U1/Channel1<9>_MC.D1 ;
  wire \U1/Channel1<9>_MC.D2 ;
  wire \U1/Channel1<9>_MC.D2_PT_0 ;
  wire \U1/Channel1<9>_MC.D2_PT_1 ;
  wire \U1/Channel1<9>_MC.D2_PT_2 ;
  wire \U1/U5/location_Maddsub__n0000__n0075<0>_MC.Q ;
  wire \U1/U5/location_Maddsub__n0000__n0075<0>_MC.D ;
  wire \U1/U5/location_Maddsub__n0000__n0075<0>_MC.D1 ;
  wire \U1/U5/location_Maddsub__n0000__n0075<0>_MC.D2 ;
  wire \U1/U5/location_Maddsub__n0000__n0075<0>_MC.D2_PT_0 ;
  wire \U1/U5/location_Maddsub__n0000__n0075<0>_MC.D2_PT_1 ;
  wire \U1/Channel1<6>_MC.Q ;
  wire \U1/Channel1<6>_MC.D ;
  wire \U1/Channel1<6>_MC_tsimcreated_xor_ ;
  wire \U1/Channel1<6>_MC.D1 ;
  wire \U1/Channel1<6>_MC.D2 ;
  wire \U1/Channel1<6>_MC.D2_PT_0 ;
  wire \U1/Channel1<6>_MC.D2_PT_1 ;
  wire \U1/Channel1<6>_MC.D2_PT_2 ;
  wire \U1/Channel1<7>_MC.Q ;
  wire \U1/Channel1<7>_MC.D ;
  wire \U1/Channel1<7>_MC_tsimcreated_xor_ ;
  wire \U1/Channel1<7>_MC.D1 ;
  wire \U1/Channel1<7>_MC.D2 ;
  wire \U1/Channel1<7>_MC.D2_PT_0 ;
  wire \U1/Channel1<7>_MC.D2_PT_1 ;
  wire \U1/Channel1<7>_MC.D2_PT_2 ;
  wire \U1/Channel1<8>_MC.Q ;
  wire \U1/Channel1<8>_MC.D ;
  wire \U1/Channel1<8>_MC_tsimcreated_xor_ ;
  wire \U1/Channel1<8>_MC.D1 ;
  wire \U1/Channel1<8>_MC.D2 ;
  wire \U1/Channel1<8>_MC.D2_PT_0 ;
  wire \U1/Channel1<8>_MC.D2_PT_1 ;
  wire \U1/Channel1<8>_MC.D2_PT_2 ;
  wire \U1/Channel1<8>_MC.D2_PT_3 ;
  wire \U1/Channel1<8>_MC.D2_PT_4 ;
  wire \U1/Channel1<8>_MC.D2_PT_5 ;
  wire \U1/Channel1<8>_MC.D2_PT_6 ;
  wire \U1/Channel1<8>_MC.D2_PT_7 ;
  wire \U1/Channel1<11>_MC.Q ;
  wire \U1/Channel1<11>_MC.D ;
  wire \U1/Channel1<11>_MC_tsimcreated_xor_ ;
  wire \U1/Channel1<11>_MC.D1 ;
  wire \U1/Channel1<11>_MC.D2 ;
  wire \U1/Channel1<11>_MC.D2_PT_0 ;
  wire \U1/Channel1<11>_MC.D2_PT_1 ;
  wire \U1/Channel1<11>_MC.D2_PT_2 ;
  wire \U1/Channel1<12>_MC.Q ;
  wire \U1/Channel1<12>_MC.D ;
  wire \U1/Channel1<12>_MC_tsimcreated_xor_ ;
  wire \U1/Channel1<12>_MC.D1 ;
  wire \U1/Channel1<12>_MC.D2 ;
  wire \U1/Channel1<12>_MC.D2_PT_0 ;
  wire \U1/Channel1<12>_MC.D2_PT_1 ;
  wire \U1/Channel1<12>_MC.D2_PT_2 ;
  wire \N_PZ_961_MC.Q ;
  wire \N_PZ_961_MC.D ;
  wire \N_PZ_961_MC.D1 ;
  wire \N_PZ_961_MC.D2 ;
  wire DCOR1CNTHIGHr;
  wire \DCOR1CNTHIGHr_MC.Q ;
  wire \DCOR1CNTHIGHr_MC.D ;
  wire \DCOR1CNTHIGHr_MC.D1 ;
  wire \DCOR1CNTHIGHr_MC.D2 ;
  wire \outDATA<5>\$WA6.UIM_MC.Q ;
  wire \outDATA<5>\$WA6.UIM_MC.D ;
  wire \outDATA<5>\$WA6.UIM_MC.D1 ;
  wire \outDATA<5>\$WA6.UIM_MC.D2 ;
  wire DCOR0THRESLOWr;
  wire \outDATA<5>\$WA6.UIM_MC.D2_PT_0 ;
  wire NET2501;
  wire DCORIFGr;
  wire \outDATA<5>\$WA6.UIM_MC.D2_PT_1 ;
  wire DCOR0THRESHIGHr;
  wire \outDATA<5>\$WA6.UIM_MC.D2_PT_2 ;
  wire DCOR1THRESLOWr;
  wire \outDATA<5>\$WA6.UIM_MC.D2_PT_3 ;
  wire \outDATA<5>\$WA6.UIM_MC.D2_PT_4 ;
  wire \U1/U4/Latch0r<5>_MC.Q ;
  wire \U1/U4/Latch0r<5>_MC.D ;
  wire \U1/U4/Latch0r<5>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ;
  wire \U1/U4/Latch0r<5>_MC.D1 ;
  wire \U1/U4/Latch0r<5>_MC.D2 ;
  wire N_PZ_963;
  wire \U1/U4/Latch0r<5>_MC.D2_PT_0 ;
  wire \U1/U4/Latch0r<5>_MC.D2_PT_1 ;
  wire \N_PZ_963_MC.Q ;
  wire \N_PZ_963_MC.D ;
  wire \N_PZ_963_MC.D1 ;
  wire \N_PZ_963_MC.D2 ;
  wire \U1/U4/LatchEdge0r ;
  wire \outDATA<6>\$WA1.UIM ;
  wire \N_PZ_963_MC.D2_PT_0 ;
  wire \N_PZ_963_MC.D2_PT_1 ;
  wire \NET2501_MC.Q ;
  wire \NET2501_MC.D ;
  wire NET2501_MC_tsimcreated_xor_;
  wire \NET2501_MC.REG_tsimcreated_inv_Mclk_II/FCLK ;
  wire \NET2501_MC.D1 ;
  wire \NET2501_MC.D2 ;
  wire \NET2501_MC.D2_PT_0 ;
  wire \NET2501_MC.D2_PT_1 ;
  wire \U1/U4/LatchEdge0r_MC.Q ;
  wire \U1/U4/LatchEdge0r_MC.D ;
  wire \U1/U4/LatchEdge0r_MC.REG_tsimcreated_inv_Mclk_II/FCLK ;
  wire \U1/U4/LatchEdge0r_MC.D1 ;
  wire \U1/U4/LatchEdge0r_MC.D2 ;
  wire \U1/U4/LatchEdge0r_MC.D2_PT_0 ;
  wire \U1/U4/LatchEdge0r_MC.D2_PT_1 ;
  wire \outDATA<6>\$WA1.UIM_MC.Q ;
  wire \outDATA<6>\$WA1.UIM_MC.D ;
  wire \outDATA<6>\$WA1.UIM_MC.D1 ;
  wire \outDATA<6>\$WA1.UIM_MC.D2 ;
  wire \DCOR0THRESLOWr_MC.Q ;
  wire \DCOR0THRESLOWr_MC.D ;
  wire \DCOR0THRESLOWr_MC.D1 ;
  wire \DCOR0THRESLOWr_MC.D2 ;
  wire \DCORIFGr_MC.Q ;
  wire \DCORIFGr_MC.D ;
  wire \DCORIFGr_MC.D1 ;
  wire \DCORIFGr_MC.D2 ;
  wire \U1/U4/Latch0r<13>_MC.Q ;
  wire \U1/U4/Latch0r<13>_MC.D ;
  wire \U1/U4/Latch0r<13>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ;
  wire \U1/U4/Latch0r<13>_MC.D1 ;
  wire \U1/U4/Latch0r<13>_MC.D2 ;
  wire \U1/U4/Latch0r<13>_MC.D2_PT_0 ;
  wire \U1/U4/Latch0r<13>_MC.D2_PT_1 ;
  wire \DCOR0THRESHIGHr_MC.Q ;
  wire \DCOR0THRESHIGHr_MC.D ;
  wire \DCOR0THRESHIGHr_MC.D1 ;
  wire \DCOR0THRESHIGHr_MC.D2 ;
  wire \U1/U4/Latch1r<5>_MC.Q ;
  wire \U1/U4/Latch1r<5>_MC.D ;
  wire \U1/U4/Latch1r<5>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ;
  wire \U1/U4/Latch1r<5>_MC.D1 ;
  wire \U1/U4/Latch1r<5>_MC.D2 ;
  wire N_PZ_962;
  wire \U1/U4/Latch1r<5>_MC.D2_PT_0 ;
  wire \U1/U4/Latch1r<5>_MC.D2_PT_1 ;
  wire \N_PZ_962_MC.Q ;
  wire \N_PZ_962_MC.D ;
  wire \N_PZ_962_MC.D1 ;
  wire \N_PZ_962_MC.D2 ;
  wire NET2512;
  wire \U1/U4/LatchEdge1r ;
  wire \outDATA<7>\$WA1.UIM ;
  wire \N_PZ_962_MC.D2_PT_0 ;
  wire \N_PZ_962_MC.D2_PT_1 ;
  wire \NET2512_MC.Q ;
  wire \NET2512_MC.D ;
  wire NET2512_MC_tsimcreated_xor_;
  wire \NET2512_MC.REG_tsimcreated_inv_Mclk_II/FCLK ;
  wire \NET2512_MC.D1 ;
  wire \NET2512_MC.D2 ;
  wire \NET2512_MC.D2_PT_0 ;
  wire \NET2512_MC.D2_PT_1 ;
  wire \U1/U4/LatchEdge1r_MC.Q ;
  wire \U1/U4/LatchEdge1r_MC.D ;
  wire \U1/U4/LatchEdge1r_MC.REG_tsimcreated_inv_Mclk_II/FCLK ;
  wire \U1/U4/LatchEdge1r_MC.D1 ;
  wire \U1/U4/LatchEdge1r_MC.D2 ;
  wire \U1/U4/LatchEdge1r_MC.D2_PT_0 ;
  wire \U1/U4/LatchEdge1r_MC.D2_PT_1 ;
  wire \outDATA<7>\$WA1.UIM_MC.Q ;
  wire \outDATA<7>\$WA1.UIM_MC.D ;
  wire \outDATA<7>\$WA1.UIM_MC.D1 ;
  wire \outDATA<7>\$WA1.UIM_MC.D2 ;
  wire \DCOR1THRESLOWr_MC.Q ;
  wire \DCOR1THRESLOWr_MC.D ;
  wire \DCOR1THRESLOWr_MC.D1 ;
  wire \DCOR1THRESLOWr_MC.D2 ;
  wire \U1/U4/Latch1r<13>_MC.Q ;
  wire \U1/U4/Latch1r<13>_MC.D ;
  wire \U1/U4/Latch1r<13>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ;
  wire \U1/U4/Latch1r<13>_MC.D1 ;
  wire \U1/U4/Latch1r<13>_MC.D2 ;
  wire \U1/U4/Latch1r<13>_MC.D2_PT_0 ;
  wire \U1/U4/Latch1r<13>_MC.D2_PT_1 ;
  wire \N_PZ_987_MC.Q ;
  wire \N_PZ_987_MC.D ;
  wire \N_PZ_987_MC.D1 ;
  wire \N_PZ_987_MC.D2 ;
  wire DCOR1THRESHIGHr;
  wire \DCOR1THRESHIGHr_MC.Q ;
  wire \DCOR1THRESHIGHr_MC.D ;
  wire \DCOR1THRESHIGHr_MC.D1 ;
  wire \DCOR1THRESHIGHr_MC.D2 ;
  wire \U2_Enable_AD_MC.Q ;
  wire U2_Enable_AD;
  wire \U2_Enable_AD_MC.D ;
  wire \U2_Enable_AD_MC.D1 ;
  wire \U2_Enable_AD_MC.D2 ;
  wire \Enc033ctrl_MC.Q_tsimrenamed_net_ ;
  wire \Enc033ctrl_MC.D ;
  wire \Enc033ctrl_MC.D1 ;
  wire \Enc033ctrl_MC.D2 ;
  wire \U4/ctrlr<2>_MC.D ;
  wire \U4/ctrlr<2>_MC.BUFOE.OUT ;
  wire \U4/ctrlr<2>_MC.D1 ;
  wire \U4/ctrlr<2>_MC.D2 ;
  wire \outDATA<2>\$WA0.UIM ;
  wire \U4/ctrlr<2>_MC.D2_PT_0 ;
  wire \outDATA<2>\$WA1.UIM ;
  wire \U4/ctrlr<2>_MC.D2_PT_1 ;
  wire \outDATA<2>\$WA2.UIM ;
  wire \U4/ctrlr<2>_MC.D2_PT_2 ;
  wire \outDATA<2>\$WA3.UIM ;
  wire \U4/ctrlr<2>_MC.D2_PT_3 ;
  wire \outDATA<2>\$WA5.UIM ;
  wire \U4/ctrlr<2>_MC.D2_PT_4 ;
  wire \outDATA<2>\$WA6.UIM ;
  wire \U4/ctrlr<2>_MC.D2_PT_5 ;
  wire \DCORENCPWRw_MC.Q ;
  wire DCORENCPWRw;
  wire \DCORENCPWRw_MC.D ;
  wire \DCORENCPWRw_MC.D1 ;
  wire \DCORENCPWRw_MC.D2 ;
  wire \U4/ctrlr<3>_MC.D ;
  wire \U4/ctrlr<3>_MC.BUFOE.OUT ;
  wire \U4/ctrlr<3>_MC.D1 ;
  wire \U4/ctrlr<3>_MC.D2 ;
  wire \outDATA<3>\$WA0.UIM ;
  wire \U4/ctrlr<3>_MC.D2_PT_0 ;
  wire \outDATA<3>\$WA1.UIM ;
  wire \U4/ctrlr<3>_MC.D2_PT_1 ;
  wire \outDATA<3>\$WA2.UIM ;
  wire \U4/ctrlr<3>_MC.D2_PT_2 ;
  wire \outDATA<3>\$WA3.UIM ;
  wire \U4/ctrlr<3>_MC.D2_PT_3 ;
  wire \outDATA<3>\$WA5.UIM ;
  wire \U4/ctrlr<3>_MC.D2_PT_4 ;
  wire \outDATA<3>\$WA6.UIM ;
  wire \U4/ctrlr<3>_MC.D2_PT_5 ;
  wire \Enc05ctrl_MC.Q_tsimrenamed_net_ ;
  wire \Enc05ctrl_MC.D ;
  wire \Enc05ctrl_MC.D1 ;
  wire \Enc05ctrl_MC.D2 ;
  wire \Enc133ctrl_MC.Q_tsimrenamed_net_ ;
  wire \Enc133ctrl_MC.D ;
  wire \Enc133ctrl_MC.D1 ;
  wire \Enc133ctrl_MC.D2 ;
  wire \U4/ctrlr<6>_MC.D ;
  wire \U4/ctrlr<6>_MC.BUFOE.OUT ;
  wire \U4/ctrlr<6>_MC.D1 ;
  wire \U4/ctrlr<6>_MC.D2 ;
  wire \outDATA<6>\$WA0.UIM ;
  wire \U4/ctrlr<6>_MC.D2_PT_0 ;
  wire \U4/ctrlr<6>_MC.D2_PT_1 ;
  wire \outDATA<6>\$WA2.UIM ;
  wire \U4/ctrlr<6>_MC.D2_PT_2 ;
  wire \outDATA<6>\$WA3.UIM ;
  wire \U4/ctrlr<6>_MC.D2_PT_3 ;
  wire \outDATA<6>\$WA5.UIM ;
  wire \U4/ctrlr<6>_MC.D2_PT_4 ;
  wire \outDATA<6>\$WA6.UIM ;
  wire \U4/ctrlr<6>_MC.D2_PT_5 ;
  wire \U4/ctrlr<7>_MC.D ;
  wire \U4/ctrlr<7>_MC.BUFOE.OUT ;
  wire \U4/ctrlr<7>_MC.D1 ;
  wire \U4/ctrlr<7>_MC.D2 ;
  wire \outDATA<7>\$WA0.UIM ;
  wire \U4/ctrlr<7>_MC.D2_PT_0 ;
  wire \U4/ctrlr<7>_MC.D2_PT_1 ;
  wire \outDATA<7>\$WA2.UIM ;
  wire \U4/ctrlr<7>_MC.D2_PT_2 ;
  wire \outDATA<7>\$WA3.UIM ;
  wire \U4/ctrlr<7>_MC.D2_PT_3 ;
  wire \outDATA<7>\$WA5.UIM ;
  wire \U4/ctrlr<7>_MC.D2_PT_4 ;
  wire \U4/ctrlr<7>_MC.D2_PT_5 ;
  wire \outDATA<7>\$WA6.UIM ;
  wire \U4/ctrlr<7>_MC.D2_PT_6 ;
  wire \U4/ctrlr<7>_MC.D2_PT_7 ;
  wire \Enc15ctrl_MC.Q_tsimrenamed_net_ ;
  wire \Enc15ctrl_MC.D ;
  wire \Enc15ctrl_MC.D1 ;
  wire \Enc15ctrl_MC.D2 ;
  wire \GPIO8_MC.Q_tsimrenamed_net_ ;
  wire \GPIO8_MC.D ;
  wire \GPIO8_MC.D1 ;
  wire \GPIO8_MC.D2 ;
  wire \GPIO9_MC.Q_tsimrenamed_net_ ;
  wire \GPIO9_MC.D ;
  wire \GPIO9_MC.D1 ;
  wire \GPIO9_MC.D2 ;
  wire \GP_Motor0_1_MC.Q_tsimrenamed_net_ ;
  wire GP_Motor0_1_MC_tsimcreated_prld_;
  wire \GP_Motor0_1_MC.D ;
  wire \GP_Motor0_1_MC.REG_tsimcreated_inv_Mclk_II/FCLK ;
  wire \FOOBAR8__ctinst/4 ;
  wire \GP_Motor0_1_MC.D1 ;
  wire \GP_Motor0_1_MC.D2 ;
  wire \DCOROUTw_MC.Q ;
  wire DCOROUTw;
  wire \DCOROUTw_MC.D ;
  wire \DCOROUTw_MC.D1 ;
  wire \DCOROUTw_MC.D2 ;
  wire \GP_Motor1_1_MC.Q_tsimrenamed_net_ ;
  wire GP_Motor1_1_MC_tsimcreated_prld_;
  wire \GP_Motor1_1_MC.D ;
  wire \GP_Motor1_1_MC.REG_tsimcreated_inv_Mclk_II/FCLK ;
  wire \FOOBAR15__ctinst/4 ;
  wire \GP_Motor1_1_MC.D1 ;
  wire \GP_Motor1_1_MC.D2 ;
  wire \HSO_MC.Q_tsimrenamed_net_ ;
  wire \HSO_MC.D ;
  wire \HSO_MC.D1 ;
  wire \HSO_MC.D2 ;
  wire \Home033ctrl_MC.Q_tsimrenamed_net_ ;
  wire \FOOBAR2__ctinst/7 ;
  wire Home033ctrl_MC_tsimcreated_prld_;
  wire \Home033ctrl_MC.D ;
  wire \Home033ctrl_MC.REG_tsimcreated_inv_Mclk_II/FCLK ;
  wire \Home033ctrl_MC.CE ;
  wire \Home033ctrl_MC.D1 ;
  wire \Home033ctrl_MC.D2 ;
  wire \Home05ctrl_MC.Q_tsimrenamed_net_ ;
  wire Home05ctrl_MC_tsimcreated_prld_;
  wire \Home05ctrl_MC.D ;
  wire \Home05ctrl_MC.REG_tsimcreated_inv_Mclk_II/FCLK ;
  wire \FOOBAR14__ctinst/4 ;
  wire \Home05ctrl_MC.D1 ;
  wire \Home05ctrl_MC.D2 ;
  wire \Home133ctrl_MC.Q_tsimrenamed_net_ ;
  wire Home133ctrl_MC_tsimcreated_prld_;
  wire \Home133ctrl_MC.D ;
  wire \Home133ctrl_MC.REG_tsimcreated_inv_Mclk_II/FCLK ;
  wire \FOOBAR23__ctinst/4 ;
  wire \Home133ctrl_MC.D1 ;
  wire \Home133ctrl_MC.D2 ;
  wire \Home15ctrl_MC.Q_tsimrenamed_net_ ;
  wire Home15ctrl_MC_tsimcreated_prld_;
  wire \Home15ctrl_MC.D ;
  wire \Home15ctrl_MC.REG_tsimcreated_inv_Mclk_II/FCLK ;
  wire \Home15ctrl_MC.CE ;
  wire \Home15ctrl_MC.D1 ;
  wire \Home15ctrl_MC.D2 ;
  wire \INT_MC.Q_tsimrenamed_net_ ;
  wire \INT_MC.D ;
  wire \INT_MC.D1 ;
  wire \INT_MC.D2 ;
  wire \INT_MC.D2_PT_0 ;
  wire \INT_MC.D2_PT_1 ;
  wire \INT_MC.D2_PT_2 ;
  wire \INT_MC.D2_PT_3 ;
  wire \INT_MC.D2_PT_4 ;
  wire \INT_MC.D2_PT_5 ;
  wire \INT_MC.D2_PT_6 ;
  wire NET2575;
  wire \INT_MC.D2_PT_7 ;
  wire \U3/DCORIE<0>_MC.Q ;
  wire \U3/DCORIE<0>_MC.D ;
  wire \U3/DCORIE<0>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ;
  wire \U3/DCORIE<0>_MC.D1 ;
  wire \U3/DCORIE<0>_MC.D2 ;
  wire DCORIEw;
  wire \U3/DCORIE<0>_MC.D2_PT_0 ;
  wire \U3/DCORIE<0>_MC.D2_PT_1 ;
  wire \DCORIEw_MC.Q ;
  wire \DCORIEw_MC.D ;
  wire \DCORIEw_MC.D1 ;
  wire \DCORIEw_MC.D2 ;
  wire \U3/DCORIE<1>_MC.Q ;
  wire \U3/DCORIE<1>_MC.D ;
  wire \U3/DCORIE<1>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ;
  wire \U3/DCORIE<1>_MC.D1 ;
  wire \U3/DCORIE<1>_MC.D2 ;
  wire \U3/DCORIE<1>_MC.D2_PT_0 ;
  wire \U3/DCORIE<1>_MC.D2_PT_1 ;
  wire \U3/DCORIE<2>_MC.Q ;
  wire \U3/DCORIE<2>_MC.D ;
  wire \U3/DCORIE<2>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ;
  wire \U3/DCORIE<2>_MC.D1 ;
  wire \U3/DCORIE<2>_MC.D2 ;
  wire \U3/DCORIE<2>_MC.D2_PT_0 ;
  wire \U3/DCORIE<2>_MC.D2_PT_1 ;
  wire \U3/DCORIE<3>_MC.Q ;
  wire \U3/DCORIE<3>_MC.D ;
  wire \U3/DCORIE<3>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ;
  wire \U3/DCORIE<3>_MC.D1 ;
  wire \U3/DCORIE<3>_MC.D2 ;
  wire \U3/DCORIE<3>_MC.D2_PT_0 ;
  wire \U3/DCORIE<3>_MC.D2_PT_1 ;
  wire \NET2575_MC.Q ;
  wire \NET2575_MC.D ;
  wire \NET2575_MC.REG_tsimcreated_inv_Mclk_II/FCLK ;
  wire \NET2575_MC.D1 ;
  wire \NET2575_MC.D2 ;
  wire \NET2575_MC.D2_PT_0 ;
  wire \NET2575_MC.D2_PT_1 ;
  wire \NET2575_MC.D2_PT_2 ;
  wire \NET2575_MC.D2_PT_3 ;
  wire \NET2575_MC.D2_PT_4 ;
  wire \NET2575_MC.D2_PT_5 ;
  wire \U3/DCORIE<4>_MC.Q ;
  wire \U3/DCORIE<4>_MC.D ;
  wire \U3/DCORIE<4>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ;
  wire \U3/DCORIE<4>_MC.D1 ;
  wire \U3/DCORIE<4>_MC.D2 ;
  wire \U3/DCORIE<4>_MC.D2_PT_0 ;
  wire \U3/DCORIE<4>_MC.D2_PT_1 ;
  wire \U3/DCORIE<5>_MC.Q ;
  wire \U3/DCORIE<5>_MC.D ;
  wire \U3/DCORIE<5>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ;
  wire \U3/DCORIE<5>_MC.D1 ;
  wire \U3/DCORIE<5>_MC.D2 ;
  wire \U3/DCORIE<5>_MC.D2_PT_0 ;
  wire \U3/DCORIE<5>_MC.D2_PT_1 ;
  wire \U3/DCORIE<6>_MC.Q ;
  wire \U3/DCORIE<6>_MC.D ;
  wire \U3/DCORIE<6>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ;
  wire \U3/DCORIE<6>_MC.D1 ;
  wire \U3/DCORIE<6>_MC.D2 ;
  wire \U3/DCORIE<6>_MC.D2_PT_0 ;
  wire \U3/DCORIE<6>_MC.D2_PT_1 ;
  wire \U3/DCORIE<7>_MC.Q ;
  wire \U3/DCORIE<7>_MC.D ;
  wire \U3/DCORIE<7>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ;
  wire \U3/DCORIE<7>_MC.D1 ;
  wire \U3/DCORIE<7>_MC.D2 ;
  wire \U3/DCORIE<7>_MC.D2_PT_0 ;
  wire \U3/DCORIE<7>_MC.D2_PT_1 ;
  wire \LED1_MC.Q_tsimrenamed_net_ ;
  wire \LED1_MC.D ;
  wire \LED1_MC.D1 ;
  wire \LED1_MC.D2 ;
  wire \U9/MISCr<0>_MC.D ;
  wire \U9/MISCr<0>_MC.BUFOE.OUT ;
  wire \U9/MISCr<0>_MC.D1 ;
  wire \U9/MISCr<0>_MC.D2 ;
  wire \outDATA<0>\$WA0.UIM ;
  wire \U9/MISCr<0>_MC.D2_PT_0 ;
  wire \outDATA<0>\$WA1.UIM ;
  wire \U9/MISCr<0>_MC.D2_PT_1 ;
  wire \outDATA<0>\$WA2.UIM ;
  wire \U9/MISCr<0>_MC.D2_PT_2 ;
  wire \outDATA<0>\$WA3.UIM ;
  wire \U9/MISCr<0>_MC.D2_PT_3 ;
  wire \outDATA<0>\$WA5.UIM ;
  wire \U9/MISCr<0>_MC.D2_PT_4 ;
  wire \outDATA<0>\$WA6.UIM ;
  wire \U9/MISCr<0>_MC.D2_PT_5 ;
  wire \outDATA<0>\$WA4.UIM ;
  wire \U9/MISCr<0>_MC.D2_PT_6 ;
  wire \U9/MISCr<0>_MC.D2_PT_7 ;
  wire \LED2_MC.Q_tsimrenamed_net_ ;
  wire \LED2_MC.D ;
  wire \LED2_MC.D1 ;
  wire \LED2_MC.D2 ;
  wire \U9/MISCr<1>_MC.D ;
  wire \U9/MISCr<1>_MC.BUFOE.OUT ;
  wire \U9/MISCr<1>_MC.D1 ;
  wire \U9/MISCr<1>_MC.D2 ;
  wire \outDATA<1>\$WA0.UIM ;
  wire \U9/MISCr<1>_MC.D2_PT_0 ;
  wire \outDATA<1>\$WA1.UIM ;
  wire \U9/MISCr<1>_MC.D2_PT_1 ;
  wire \outDATA<1>\$WA2.UIM ;
  wire \U9/MISCr<1>_MC.D2_PT_2 ;
  wire \outDATA<1>\$WA3.UIM ;
  wire \U9/MISCr<1>_MC.D2_PT_3 ;
  wire \outDATA<1>\$WA5.UIM ;
  wire \U9/MISCr<1>_MC.D2_PT_4 ;
  wire \outDATA<1>\$WA6.UIM ;
  wire \U9/MISCr<1>_MC.D2_PT_5 ;
  wire \U9/MISCr<1>_MC.D2_PT_6 ;
  wire \U9/MISCr<1>_MC.D2_PT_7 ;
  wire \LED3_MC.Q_tsimrenamed_net_ ;
  wire \LED3_MC.D ;
  wire \LED3_MC.D1 ;
  wire \LED3_MC.D2 ;
  wire \U9/MISCr<2>_MC.Q ;
  wire \U9/MISCr<2>_MC_tsimcreated_prld_ ;
  wire \U9/MISCr<2>_MC.D ;
  wire \U9/MISCr<2>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ;
  wire \FOOBAR1__ctinst/4 ;
  wire \U9/MISCr<2>_MC.D1 ;
  wire \U9/MISCr<2>_MC.D2 ;
  wire \LED4_MC.Q_tsimrenamed_net_ ;
  wire \LED4_MC.D ;
  wire \LED4_MC.D1 ;
  wire \LED4_MC.D2 ;
  wire \U9/MISCr<3>_MC.Q ;
  wire \U9/MISCr<3>_MC_tsimcreated_prld_ ;
  wire \U9/MISCr<3>_MC.D ;
  wire \U9/MISCr<3>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ;
  wire \U9/MISCr<3>_MC.D1 ;
  wire \U9/MISCr<3>_MC.D2 ;
  wire \LED5_MC.Q_tsimrenamed_net_ ;
  wire \LED5_MC.D ;
  wire \LED5_MC.D1 ;
  wire \LED5_MC.D2 ;
  wire \U9/MISCr<4>_MC.D ;
  wire \U9/MISCr<4>_MC.BUFOE.OUT ;
  wire \U9/MISCr<4>_MC.D1 ;
  wire \U9/MISCr<4>_MC.D2 ;
  wire \outDATA<4>\$WA0.UIM ;
  wire \U9/MISCr<4>_MC.D2_PT_0 ;
  wire \outDATA<4>\$WA1.UIM ;
  wire \U9/MISCr<4>_MC.D2_PT_1 ;
  wire \outDATA<4>\$WA2.UIM ;
  wire \U9/MISCr<4>_MC.D2_PT_2 ;
  wire \outDATA<4>\$WA3.UIM ;
  wire \U9/MISCr<4>_MC.D2_PT_3 ;
  wire \outDATA<4>\$WA5.UIM ;
  wire \U9/MISCr<4>_MC.D2_PT_4 ;
  wire \outDATA<4>\$WA6.UIM ;
  wire \U9/MISCr<4>_MC.D2_PT_5 ;
  wire \outDATA<4>\$WA4.UIM ;
  wire \U9/MISCr<4>_MC.D2_PT_6 ;
  wire \U9/MISCr<4>_MC.D2_PT_7 ;
  wire \MHSI_MC.Q_tsimrenamed_net_ ;
  wire \MHSI_MC.D ;
  wire \MHSI_MC.D1 ;
  wire \MHSI_MC.D2 ;
  wire \MTRpwr_MC.Q_tsimrenamed_net_ ;
  wire MTRpwr_MC_tsimcreated_prld_;
  wire \MTRpwr_MC.D ;
  wire \MTRpwr_MC.REG_tsimcreated_inv_Mclk_II/FCLK ;
  wire \FOOBAR18__ctinst/4 ;
  wire \MTRpwr_MC.D1 ;
  wire \MTRpwr_MC.D2 ;
  wire \MTRpwrn_MC.Q_tsimrenamed_net_ ;
  wire MTRpwrn_MC_tsimcreated_prld_;
  wire \MTRpwrn_MC.D ;
  wire \MTRpwrn_MC.REG_tsimcreated_inv_Mclk_II/FCLK ;
  wire \FOOBAR7__ctinst/4 ;
  wire \MTRpwrn_MC.D1 ;
  wire \MTRpwrn_MC.D2 ;
  wire \MTXI_MC.Q_tsimrenamed_net_ ;
  wire \MTXI_MC.D ;
  wire \MTXI_MC.D1 ;
  wire \MTXI_MC.D2 ;
  wire \PAH0_MC.Q_tsimrenamed_net_ ;
  wire \PAH0_MC.UIM ;
  wire \PAH0_MC.D ;
  wire \PAH0_MC.D1 ;
  wire \PAH0_MC.D2 ;
  wire NET3248;
  wire \NET3248_MC.Q ;
  wire \NET3248_MC.D ;
  wire \NET3248_MC.REG_tsimcreated_inv_Mclk_II/FCLK ;
  wire \NET3248_MC.D1 ;
  wire \NET3248_MC.D2 ;
  wire \NET3248_MC.D2_PT_0 ;
  wire \NET3248_MC.D2_PT_1 ;
  wire \NET3248_MC.D2_PT_2 ;
  wire \PAH1_MC.Q_tsimrenamed_net_ ;
  wire \PAH1_MC.UIM ;
  wire \PAH1_MC.D ;
  wire \PAH1_MC.D1 ;
  wire \PAH1_MC.D2 ;
  wire NET3253;
  wire \NET3253_MC.Q ;
  wire \NET3253_MC.D ;
  wire \NET3253_MC.REG_tsimcreated_inv_Mclk_II/FCLK ;
  wire \NET3253_MC.D1 ;
  wire \NET3253_MC.D2 ;
  wire \NET3253_MC.D2_PT_0 ;
  wire \NET3253_MC.D2_PT_1 ;
  wire \NET3253_MC.D2_PT_2 ;
  wire \PAL0_MC.Q_tsimrenamed_net_ ;
  wire \PAL0_MC.D ;
  wire \PAL0_MC.D1 ;
  wire \PAL0_MC.D2 ;
  wire \PAL0_MC.D2_PT_0 ;
  wire \PAL0_MC.D2_PT_1 ;
  wire \PAL1_MC.Q_tsimrenamed_net_ ;
  wire \PAL1_MC.D ;
  wire \PAL1_MC.D1 ;
  wire \PAL1_MC.D2 ;
  wire \PAL1_MC.D2_PT_0 ;
  wire \PAL1_MC.D2_PT_1 ;
  wire \PBH0_MC.Q_tsimrenamed_net_ ;
  wire \PBH0_MC.UIM ;
  wire \PBH0_MC.D ;
  wire \PBH0_MC.D1 ;
  wire \PBH0_MC.D2 ;
  wire \PBH1_MC.Q_tsimrenamed_net_ ;
  wire \PBH1_MC.UIM ;
  wire \PBH1_MC.D ;
  wire \PBH1_MC.D1 ;
  wire \PBH1_MC.D2 ;
  wire \PBL0_MC.Q_tsimrenamed_net_ ;
  wire \PBL0_MC.D ;
  wire \PBL0_MC.D1 ;
  wire \PBL0_MC.D2 ;
  wire \PBL0_MC.D2_PT_0 ;
  wire \PBL0_MC.D2_PT_1 ;
  wire \PBL1_MC.Q_tsimrenamed_net_ ;
  wire \PBL1_MC.D ;
  wire \PBL1_MC.D1 ;
  wire \PBL1_MC.D2 ;
  wire \PBL1_MC.D2_PT_0 ;
  wire \PBL1_MC.D2_PT_1 ;
  wire \PresEn_MC.Q_tsimrenamed_net_ ;
  wire PresEn_MC_tsimcreated_prld_;
  wire \PresEn_MC.D ;
  wire \PresEn_MC.REG_tsimcreated_inv_Mclk_II/FCLK ;
  wire \FOOBAR19__ctinst/4 ;
  wire \PresEn_MC.D1 ;
  wire \PresEn_MC.D2 ;
  wire \DCORSENSORw_MC.Q ;
  wire DCORSENSORw;
  wire \DCORSENSORw_MC.D ;
  wire \DCORSENSORw_MC.D1 ;
  wire \DCORSENSORw_MC.D2 ;
  wire \PresSlct_MC.Q_tsimrenamed_net_ ;
  wire PresSlct_MC_tsimcreated_prld_;
  wire \PresSlct_MC.D ;
  wire \PresSlct_MC.REG_tsimcreated_inv_Mclk_II/FCLK ;
  wire \PresSlct_MC.D1 ;
  wire \PresSlct_MC.D2 ;
  wire \SCLout_MC.Q_tsimrenamed_net_ ;
  wire \SCLout_MC.D ;
  wire \SCLout_MC.D1 ;
  wire \SCLout_MC.D2 ;
  wire \TP10_MC.Q_tsimrenamed_net_ ;
  wire \TP10_MC.D ;
  wire \TP10_MC.D1 ;
  wire \TP10_MC.D2 ;
  wire \TP11_MC.Q_tsimrenamed_net_ ;
  wire \TP11_MC.D ;
  wire \TP11_MC.D1 ;
  wire \TP11_MC.D2 ;
  wire \TmpEn_MC.Q_tsimrenamed_net_ ;
  wire TmpEn_MC_tsimcreated_prld_;
  wire \TmpEn_MC.D ;
  wire \TmpEn_MC.REG_tsimcreated_inv_Mclk_II/FCLK ;
  wire \TmpEn_MC.D1 ;
  wire \TmpEn_MC.D2 ;
  wire \TmpSlct_MC.Q_tsimrenamed_net_ ;
  wire TmpSlct_MC_tsimcreated_prld_;
  wire \TmpSlct_MC.D ;
  wire \TmpSlct_MC.REG_tsimcreated_inv_Mclk_II/FCLK ;
  wire \TmpSlct_MC.D1 ;
  wire \TmpSlct_MC.D2 ;
  wire \outDATA<2>\$WA0.UIM_MC.Q ;
  wire \outDATA<2>\$WA0.UIM_MC.D ;
  wire \outDATA<2>\$WA0.UIM_MC.D1 ;
  wire \outDATA<2>\$WA0.UIM_MC.D2 ;
  wire \outDATA<2>\$WA1.UIM_MC.Q ;
  wire \outDATA<2>\$WA1.UIM_MC.D ;
  wire \outDATA<2>\$WA1.UIM_MC.D1 ;
  wire \outDATA<2>\$WA1.UIM_MC.D2 ;
  wire \outDATA<2>\$WA2.UIM_MC.Q ;
  wire \outDATA<2>\$WA2.UIM_MC.D ;
  wire \outDATA<2>\$WA2.UIM_MC.D1 ;
  wire \outDATA<2>\$WA2.UIM_MC.D2 ;
  wire \outDATA<2>\$WA3.UIM_MC.Q ;
  wire \outDATA<2>\$WA3.UIM_MC.D ;
  wire \outDATA<2>\$WA3.UIM_MC.D1 ;
  wire \outDATA<2>\$WA3.UIM_MC.D2 ;
  wire \outDATA<2>\$WA3.UIM_MC.D2_PT_0 ;
  wire \outDATA<2>\$WA3.UIM_MC.D2_PT_1 ;
  wire \outDATA<2>\$WA5.UIM_MC.Q ;
  wire \outDATA<2>\$WA5.UIM_MC.D ;
  wire \outDATA<2>\$WA5.UIM_MC.D1 ;
  wire \outDATA<2>\$WA5.UIM_MC.D2 ;
  wire \outDATA<2>\$WA5.UIM_MC.D2_PT_0 ;
  wire \outDATA<2>\$WA5.UIM_MC.D2_PT_1 ;
  wire \outDATA<2>\$WA5.UIM_MC.D2_PT_2 ;
  wire \outDATA<2>\$WA5.UIM_MC.D2_PT_3 ;
  wire \U1/U3/holdingreg0<2>_MC.Q ;
  wire \U1/U3/holdingreg0<2>_MC.D ;
  wire \U1/U3/holdingreg0<2>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ;
  wire \U1/U3/holdingreg0<2>_MC.D1 ;
  wire \U1/U3/holdingreg0<2>_MC.D2 ;
  wire \U1/U3/holdingreg0<2>_MC.D2_PT_0 ;
  wire \U1/U3/holdingreg0<2>_MC.D2_PT_1 ;
  wire \U1/U3/holdingreg1<2>_MC.Q ;
  wire \U1/U3/holdingreg1<2>_MC.D ;
  wire \U1/U3/holdingreg1<2>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ;
  wire \U1/U3/holdingreg1<2>_MC.D1 ;
  wire \U1/U3/holdingreg1<2>_MC.D2 ;
  wire \U1/U3/holdingreg1<2>_MC.D2_PT_0 ;
  wire \U1/U3/holdingreg1<2>_MC.D2_PT_1 ;
  wire \U1/U3/holdingreg0<10>_MC.Q ;
  wire \U1/U3/holdingreg0<10>_MC.D ;
  wire \U1/U3/holdingreg0<10>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ;
  wire \U1/U3/holdingreg0<10>_MC.D1 ;
  wire \U1/U3/holdingreg0<10>_MC.D2 ;
  wire \U1/U3/holdingreg0<10>_MC.D2_PT_0 ;
  wire \U1/U3/holdingreg0<10>_MC.D2_PT_1 ;
  wire \U1/U3/holdingreg1<10>_MC.Q ;
  wire \U1/U3/holdingreg1<10>_MC.D ;
  wire \U1/U3/holdingreg1<10>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ;
  wire \U1/U3/holdingreg1<10>_MC.D1 ;
  wire \U1/U3/holdingreg1<10>_MC.D2 ;
  wire \U1/U3/holdingreg1<10>_MC.D2_PT_0 ;
  wire \U1/U3/holdingreg1<10>_MC.D2_PT_1 ;
  wire \outDATA<2>\$WA6.UIM_MC.Q ;
  wire \outDATA<2>\$WA6.UIM_MC.D ;
  wire \outDATA<2>\$WA6.UIM_MC.D1 ;
  wire \outDATA<2>\$WA6.UIM_MC.D2 ;
  wire \outDATA<2>\$WA6.UIM_MC.D2_PT_0 ;
  wire \outDATA<2>\$WA6.UIM_MC.D2_PT_1 ;
  wire \outDATA<2>\$WA6.UIM_MC.D2_PT_2 ;
  wire \outDATA<2>\$WA6.UIM_MC.D2_PT_3 ;
  wire \outDATA<2>\$WA6.UIM_MC.D2_PT_4 ;
  wire \U1/U4/Latch0r<2>_MC.Q ;
  wire \U1/U4/Latch0r<2>_MC.D ;
  wire \U1/U4/Latch0r<2>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ;
  wire \U1/U4/Latch0r<2>_MC.D1 ;
  wire \U1/U4/Latch0r<2>_MC.D2 ;
  wire \U1/U4/Latch0r<2>_MC.D2_PT_0 ;
  wire \U1/U4/Latch0r<2>_MC.D2_PT_1 ;
  wire \U1/U4/Latch0r<10>_MC.Q ;
  wire \U1/U4/Latch0r<10>_MC.D ;
  wire \U1/U4/Latch0r<10>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ;
  wire \U1/U4/Latch0r<10>_MC.D1 ;
  wire \U1/U4/Latch0r<10>_MC.D2 ;
  wire \U1/U4/Latch0r<10>_MC.D2_PT_0 ;
  wire \U1/U4/Latch0r<10>_MC.D2_PT_1 ;
  wire \U1/U4/Latch1r<2>_MC.Q ;
  wire \U1/U4/Latch1r<2>_MC.D ;
  wire \U1/U4/Latch1r<2>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ;
  wire \U1/U4/Latch1r<2>_MC.D1 ;
  wire \U1/U4/Latch1r<2>_MC.D2 ;
  wire \U1/U4/Latch1r<2>_MC.D2_PT_0 ;
  wire \U1/U4/Latch1r<2>_MC.D2_PT_1 ;
  wire \U1/U4/Latch1r<10>_MC.Q ;
  wire \U1/U4/Latch1r<10>_MC.D ;
  wire \U1/U4/Latch1r<10>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ;
  wire \U1/U4/Latch1r<10>_MC.D1 ;
  wire \U1/U4/Latch1r<10>_MC.D2 ;
  wire \U1/U4/Latch1r<10>_MC.D2_PT_0 ;
  wire \U1/U4/Latch1r<10>_MC.D2_PT_1 ;
  wire \outDATA<3>\$WA0.UIM_MC.Q ;
  wire \outDATA<3>\$WA0.UIM_MC.D ;
  wire \outDATA<3>\$WA0.UIM_MC.D1 ;
  wire \outDATA<3>\$WA0.UIM_MC.D2 ;
  wire \outDATA<3>\$WA1.UIM_MC.Q ;
  wire \outDATA<3>\$WA1.UIM_MC.D ;
  wire \outDATA<3>\$WA1.UIM_MC.D1 ;
  wire \outDATA<3>\$WA1.UIM_MC.D2 ;
  wire \outDATA<3>\$WA2.UIM_MC.Q ;
  wire \outDATA<3>\$WA2.UIM_MC.D ;
  wire \outDATA<3>\$WA2.UIM_MC.D1 ;
  wire \outDATA<3>\$WA2.UIM_MC.D2 ;
  wire \outDATA<3>\$WA3.UIM_MC.Q ;
  wire \outDATA<3>\$WA3.UIM_MC.D ;
  wire \outDATA<3>\$WA3.UIM_MC.D1 ;
  wire \outDATA<3>\$WA3.UIM_MC.D2 ;
  wire \outDATA<3>\$WA3.UIM_MC.D2_PT_0 ;
  wire \outDATA<3>\$WA3.UIM_MC.D2_PT_1 ;
  wire \outDATA<3>\$WA5.UIM_MC.Q ;
  wire \outDATA<3>\$WA5.UIM_MC.D ;
  wire \outDATA<3>\$WA5.UIM_MC.D1 ;
  wire \outDATA<3>\$WA5.UIM_MC.D2 ;
  wire \outDATA<3>\$WA5.UIM_MC.D2_PT_0 ;
  wire \outDATA<3>\$WA5.UIM_MC.D2_PT_1 ;
  wire \outDATA<3>\$WA5.UIM_MC.D2_PT_2 ;
  wire \outDATA<3>\$WA5.UIM_MC.D2_PT_3 ;
  wire \U1/U3/holdingreg0<3>_MC.Q ;
  wire \U1/U3/holdingreg0<3>_MC.D ;
  wire \U1/U3/holdingreg0<3>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ;
  wire \U1/U3/holdingreg0<3>_MC.D1 ;
  wire \U1/U3/holdingreg0<3>_MC.D2 ;
  wire \U1/U3/holdingreg0<3>_MC.D2_PT_0 ;
  wire \U1/U3/holdingreg0<3>_MC.D2_PT_1 ;
  wire \U1/U3/holdingreg1<3>_MC.Q ;
  wire \U1/U3/holdingreg1<3>_MC.D ;
  wire \U1/U3/holdingreg1<3>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ;
  wire \U1/U3/holdingreg1<3>_MC.D1 ;
  wire \U1/U3/holdingreg1<3>_MC.D2 ;
  wire \U1/U3/holdingreg1<3>_MC.D2_PT_0 ;
  wire \U1/U3/holdingreg1<3>_MC.D2_PT_1 ;
  wire \U1/U3/holdingreg0<11>_MC.Q ;
  wire \U1/U3/holdingreg0<11>_MC.D ;
  wire \U1/U3/holdingreg0<11>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ;
  wire \U1/U3/holdingreg0<11>_MC.D1 ;
  wire \U1/U3/holdingreg0<11>_MC.D2 ;
  wire \U1/U3/holdingreg0<11>_MC.D2_PT_0 ;
  wire \U1/U3/holdingreg0<11>_MC.D2_PT_1 ;
  wire \U1/U3/holdingreg1<11>_MC.Q ;
  wire \U1/U3/holdingreg1<11>_MC.D ;
  wire \U1/U3/holdingreg1<11>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ;
  wire \U1/U3/holdingreg1<11>_MC.D1 ;
  wire \U1/U3/holdingreg1<11>_MC.D2 ;
  wire \U1/U3/holdingreg1<11>_MC.D2_PT_0 ;
  wire \U1/U3/holdingreg1<11>_MC.D2_PT_1 ;
  wire \outDATA<3>\$WA6.UIM_MC.Q ;
  wire \outDATA<3>\$WA6.UIM_MC.D ;
  wire \outDATA<3>\$WA6.UIM_MC.D1 ;
  wire \outDATA<3>\$WA6.UIM_MC.D2 ;
  wire \outDATA<3>\$WA6.UIM_MC.D2_PT_0 ;
  wire \outDATA<3>\$WA6.UIM_MC.D2_PT_1 ;
  wire \outDATA<3>\$WA6.UIM_MC.D2_PT_2 ;
  wire \outDATA<3>\$WA6.UIM_MC.D2_PT_3 ;
  wire \outDATA<3>\$WA6.UIM_MC.D2_PT_4 ;
  wire \U1/U4/Latch0r<3>_MC.Q ;
  wire \U1/U4/Latch0r<3>_MC.D ;
  wire \U1/U4/Latch0r<3>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ;
  wire \U1/U4/Latch0r<3>_MC.D1 ;
  wire \U1/U4/Latch0r<3>_MC.D2 ;
  wire \U1/U4/Latch0r<3>_MC.D2_PT_0 ;
  wire \U1/U4/Latch0r<3>_MC.D2_PT_1 ;
  wire \U1/U4/Latch0r<11>_MC.Q ;
  wire \U1/U4/Latch0r<11>_MC.D ;
  wire \U1/U4/Latch0r<11>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ;
  wire \U1/U4/Latch0r<11>_MC.D1 ;
  wire \U1/U4/Latch0r<11>_MC.D2 ;
  wire \U1/U4/Latch0r<11>_MC.D2_PT_0 ;
  wire \U1/U4/Latch0r<11>_MC.D2_PT_1 ;
  wire \U1/U4/Latch1r<3>_MC.Q ;
  wire \U1/U4/Latch1r<3>_MC.D ;
  wire \U1/U4/Latch1r<3>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ;
  wire \U1/U4/Latch1r<3>_MC.D1 ;
  wire \U1/U4/Latch1r<3>_MC.D2 ;
  wire \U1/U4/Latch1r<3>_MC.D2_PT_0 ;
  wire \U1/U4/Latch1r<3>_MC.D2_PT_1 ;
  wire \U1/U4/Latch1r<11>_MC.Q ;
  wire \U1/U4/Latch1r<11>_MC.D ;
  wire \U1/U4/Latch1r<11>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ;
  wire \U1/U4/Latch1r<11>_MC.D1 ;
  wire \U1/U4/Latch1r<11>_MC.D2 ;
  wire \U1/U4/Latch1r<11>_MC.D2_PT_0 ;
  wire \U1/U4/Latch1r<11>_MC.D2_PT_1 ;
  wire \outDATA<6>\$WA0.UIM_MC.Q ;
  wire \outDATA<6>\$WA0.UIM_MC.D ;
  wire \outDATA<6>\$WA0.UIM_MC.D1 ;
  wire \outDATA<6>\$WA0.UIM_MC.D2 ;
  wire \outDATA<6>\$WA2.UIM_MC.Q ;
  wire \outDATA<6>\$WA2.UIM_MC.D ;
  wire \outDATA<6>\$WA2.UIM_MC.D1 ;
  wire \outDATA<6>\$WA2.UIM_MC.D2 ;
  wire \outDATA<6>\$WA3.UIM_MC.Q ;
  wire \outDATA<6>\$WA3.UIM_MC.D ;
  wire \outDATA<6>\$WA3.UIM_MC.D1 ;
  wire \outDATA<6>\$WA3.UIM_MC.D2 ;
  wire \outDATA<6>\$WA3.UIM_MC.D2_PT_0 ;
  wire \outDATA<6>\$WA3.UIM_MC.D2_PT_1 ;
  wire \outDATA<6>\$WA5.UIM_MC.Q ;
  wire \outDATA<6>\$WA5.UIM_MC.D ;
  wire \outDATA<6>\$WA5.UIM_MC.D1 ;
  wire \outDATA<6>\$WA5.UIM_MC.D2 ;
  wire \outDATA<6>\$WA5.UIM_MC.D2_PT_0 ;
  wire \outDATA<6>\$WA5.UIM_MC.D2_PT_1 ;
  wire \outDATA<6>\$WA5.UIM_MC.D2_PT_2 ;
  wire \outDATA<6>\$WA5.UIM_MC.D2_PT_3 ;
  wire \U1/U3/holdingreg0<6>_MC.Q ;
  wire \U1/U3/holdingreg0<6>_MC.D ;
  wire \U1/U3/holdingreg0<6>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ;
  wire \U1/U3/holdingreg0<6>_MC.D1 ;
  wire \U1/U3/holdingreg0<6>_MC.D2 ;
  wire \U1/U3/holdingreg0<6>_MC.D2_PT_0 ;
  wire \U1/U3/holdingreg0<6>_MC.D2_PT_1 ;
  wire \U1/U3/holdingreg1<6>_MC.Q ;
  wire \U1/U3/holdingreg1<6>_MC.D ;
  wire \U1/U3/holdingreg1<6>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ;
  wire \U1/U3/holdingreg1<6>_MC.D1 ;
  wire \U1/U3/holdingreg1<6>_MC.D2 ;
  wire \U1/U3/holdingreg1<6>_MC.D2_PT_0 ;
  wire \U1/U3/holdingreg1<6>_MC.D2_PT_1 ;
  wire \U1/U3/holdingreg0<14>_MC.Q ;
  wire \U1/U3/holdingreg0<14>_MC.D ;
  wire \U1/U3/holdingreg0<14>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ;
  wire \U1/U3/holdingreg0<14>_MC.D1 ;
  wire \U1/U3/holdingreg0<14>_MC.D2 ;
  wire \U1/U3/holdingreg0<14>_MC.D2_PT_0 ;
  wire \U1/U3/holdingreg0<14>_MC.D2_PT_1 ;
  wire \U1/Channel0<14>_MC.Q ;
  wire \U1/Channel0<14>_MC.D ;
  wire \U1/Channel0<14>_MC_tsimcreated_xor_ ;
  wire \U1/Channel0<14>_MC.D1 ;
  wire \U1/Channel0<14>_MC.D2 ;
  wire \U1/Channel0<14>_MC.D2_PT_0 ;
  wire \U1/Channel0<14>_MC.D2_PT_1 ;
  wire \U1/Channel0<14>_MC.D2_PT_2 ;
  wire \U1/U3/holdingreg1<14>_MC.Q ;
  wire \U1/U3/holdingreg1<14>_MC.D ;
  wire \U1/U3/holdingreg1<14>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ;
  wire \U1/U3/holdingreg1<14>_MC.D1 ;
  wire \U1/U3/holdingreg1<14>_MC.D2 ;
  wire \U1/U3/holdingreg1<14>_MC.D2_PT_0 ;
  wire \U1/U3/holdingreg1<14>_MC.D2_PT_1 ;
  wire \U1/Channel1<14>_MC.Q ;
  wire \U1/Channel1<14>_MC.D ;
  wire \U1/Channel1<14>_MC_tsimcreated_xor_ ;
  wire \U1/Channel1<14>_MC.D1 ;
  wire \U1/Channel1<14>_MC.D2 ;
  wire \U1/Channel1<14>_MC.D2_PT_0 ;
  wire \U1/Channel1<14>_MC.D2_PT_1 ;
  wire \U1/Channel1<14>_MC.D2_PT_2 ;
  wire \outDATA<6>\$WA6.UIM_MC.Q ;
  wire \outDATA<6>\$WA6.UIM_MC.D ;
  wire \outDATA<6>\$WA6.UIM_MC.D1 ;
  wire \outDATA<6>\$WA6.UIM_MC.D2 ;
  wire \outDATA<6>\$WA6.UIM_MC.D2_PT_0 ;
  wire \outDATA<6>\$WA6.UIM_MC.D2_PT_1 ;
  wire \outDATA<6>\$WA6.UIM_MC.D2_PT_2 ;
  wire \outDATA<6>\$WA6.UIM_MC.D2_PT_3 ;
  wire \outDATA<6>\$WA6.UIM_MC.D2_PT_4 ;
  wire \U1/U4/Latch0r<6>_MC.Q ;
  wire \U1/U4/Latch0r<6>_MC.D ;
  wire \U1/U4/Latch0r<6>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ;
  wire \U1/U4/Latch0r<6>_MC.D1 ;
  wire \U1/U4/Latch0r<6>_MC.D2 ;
  wire \U1/U4/Latch0r<6>_MC.D2_PT_0 ;
  wire \U1/U4/Latch0r<6>_MC.D2_PT_1 ;
  wire \U1/U4/Latch0r<14>_MC.Q ;
  wire \U1/U4/Latch0r<14>_MC.D ;
  wire \U1/U4/Latch0r<14>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ;
  wire \U1/U4/Latch0r<14>_MC.D1 ;
  wire \U1/U4/Latch0r<14>_MC.D2 ;
  wire \U1/U4/Latch0r<14>_MC.D2_PT_0 ;
  wire \U1/U4/Latch0r<14>_MC.D2_PT_1 ;
  wire \U1/U4/Latch1r<6>_MC.Q ;
  wire \U1/U4/Latch1r<6>_MC.D ;
  wire \U1/U4/Latch1r<6>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ;
  wire \U1/U4/Latch1r<6>_MC.D1 ;
  wire \U1/U4/Latch1r<6>_MC.D2 ;
  wire \U1/U4/Latch1r<6>_MC.D2_PT_0 ;
  wire \U1/U4/Latch1r<6>_MC.D2_PT_1 ;
  wire \U1/U4/Latch1r<14>_MC.Q ;
  wire \U1/U4/Latch1r<14>_MC.D ;
  wire \U1/U4/Latch1r<14>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ;
  wire \U1/U4/Latch1r<14>_MC.D1 ;
  wire \U1/U4/Latch1r<14>_MC.D2 ;
  wire \U1/U4/Latch1r<14>_MC.D2_PT_0 ;
  wire \U1/U4/Latch1r<14>_MC.D2_PT_1 ;
  wire \outDATA<7>\$WA0.UIM_MC.Q ;
  wire \outDATA<7>\$WA0.UIM_MC.D ;
  wire \outDATA<7>\$WA0.UIM_MC.D1 ;
  wire \outDATA<7>\$WA0.UIM_MC.D2 ;
  wire \outDATA<7>\$WA2.UIM_MC.Q ;
  wire \outDATA<7>\$WA2.UIM_MC.D ;
  wire \outDATA<7>\$WA2.UIM_MC.D1 ;
  wire \outDATA<7>\$WA2.UIM_MC.D2 ;
  wire \outDATA<7>\$WA3.UIM_MC.Q ;
  wire \outDATA<7>\$WA3.UIM_MC.D ;
  wire \outDATA<7>\$WA3.UIM_MC.D1 ;
  wire \outDATA<7>\$WA3.UIM_MC.D2 ;
  wire \outDATA<7>\$WA3.UIM_MC.D2_PT_0 ;
  wire \outDATA<7>\$WA3.UIM_MC.D2_PT_1 ;
  wire \outDATA<7>\$WA6.UIM_MC.Q ;
  wire \outDATA<7>\$WA6.UIM_MC.D ;
  wire \outDATA<7>\$WA6.UIM_MC.D1 ;
  wire \outDATA<7>\$WA6.UIM_MC.D2 ;
  wire \outDATA<7>\$WA6.UIM_MC.D2_PT_0 ;
  wire \outDATA<7>\$WA6.UIM_MC.D2_PT_1 ;
  wire \outDATA<7>\$WA6.UIM_MC.D2_PT_2 ;
  wire \outDATA<7>\$WA6.UIM_MC.D2_PT_3 ;
  wire \U1/U4/Latch0r<7>_MC.Q ;
  wire \U1/U4/Latch0r<7>_MC.D ;
  wire \U1/U4/Latch0r<7>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ;
  wire \U1/U4/Latch0r<7>_MC.D1 ;
  wire \U1/U4/Latch0r<7>_MC.D2 ;
  wire \U1/U4/Latch0r<7>_MC.D2_PT_0 ;
  wire \U1/U4/Latch0r<7>_MC.D2_PT_1 ;
  wire \U1/U4/Latch0r<15>_MC.Q ;
  wire \U1/U4/Latch0r<15>_MC.D ;
  wire \U1/U4/Latch0r<15>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ;
  wire \U1/U4/Latch0r<15>_MC.D1 ;
  wire \U1/U4/Latch0r<15>_MC.D2 ;
  wire \U1/U4/Latch0r<15>_MC.D2_PT_0 ;
  wire \U1/U4/Latch0r<15>_MC.D2_PT_1 ;
  wire \U1/Channel0<15>_MC.Q ;
  wire \U1/Channel0<15>_MC.D ;
  wire \U1/Channel0<15>_MC_tsimcreated_xor_ ;
  wire \U1/Channel0<15>_MC.D1 ;
  wire \U1/Channel0<15>_MC.D2 ;
  wire \U1/Channel0<15>_MC.D2_PT_0 ;
  wire \U1/Channel0<15>_MC.D2_PT_1 ;
  wire \U1/Channel0<15>_MC.D2_PT_2 ;
  wire \U1/U4/Latch1r<7>_MC.Q ;
  wire \U1/U4/Latch1r<7>_MC.D ;
  wire \U1/U4/Latch1r<7>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ;
  wire \U1/U4/Latch1r<7>_MC.D1 ;
  wire \U1/U4/Latch1r<7>_MC.D2 ;
  wire \U1/U4/Latch1r<7>_MC.D2_PT_0 ;
  wire \U1/U4/Latch1r<7>_MC.D2_PT_1 ;
  wire \U1/U4/Latch1r<15>_MC.Q ;
  wire \U1/U4/Latch1r<15>_MC.D ;
  wire \U1/U4/Latch1r<15>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ;
  wire \U1/U4/Latch1r<15>_MC.D1 ;
  wire \U1/U4/Latch1r<15>_MC.D2 ;
  wire \U1/U4/Latch1r<15>_MC.D2_PT_0 ;
  wire \U1/U4/Latch1r<15>_MC.D2_PT_1 ;
  wire \U1/Channel1<15>_MC.Q ;
  wire \U1/Channel1<15>_MC.D ;
  wire \U1/Channel1<15>_MC_tsimcreated_xor_ ;
  wire \U1/Channel1<15>_MC.D1 ;
  wire \U1/Channel1<15>_MC.D2 ;
  wire \U1/Channel1<15>_MC.D2_PT_0 ;
  wire \U1/Channel1<15>_MC.D2_PT_1 ;
  wire \U1/Channel1<15>_MC.D2_PT_2 ;
  wire \outDATA<7>\$WA5.UIM_MC.Q ;
  wire \outDATA<7>\$WA5.UIM_MC.D ;
  wire \outDATA<7>\$WA5.UIM_MC.D1 ;
  wire \outDATA<7>\$WA5.UIM_MC.D2 ;
  wire \outDATA<7>\$WA5.UIM_MC.D2_PT_0 ;
  wire \outDATA<7>\$WA5.UIM_MC.D2_PT_1 ;
  wire \outDATA<7>\$WA5.UIM_MC.D2_PT_2 ;
  wire \outDATA<7>\$WA5.UIM_MC.D2_PT_3 ;
  wire \U1/U3/holdingreg0<7>_MC.Q ;
  wire \U1/U3/holdingreg0<7>_MC.D ;
  wire \U1/U3/holdingreg0<7>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ;
  wire \U1/U3/holdingreg0<7>_MC.D1 ;
  wire \U1/U3/holdingreg0<7>_MC.D2 ;
  wire \U1/U3/holdingreg0<7>_MC.D2_PT_0 ;
  wire \U1/U3/holdingreg0<7>_MC.D2_PT_1 ;
  wire \U1/U3/holdingreg1<7>_MC.Q ;
  wire \U1/U3/holdingreg1<7>_MC.D ;
  wire \U1/U3/holdingreg1<7>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ;
  wire \U1/U3/holdingreg1<7>_MC.D1 ;
  wire \U1/U3/holdingreg1<7>_MC.D2 ;
  wire \U1/U3/holdingreg1<7>_MC.D2_PT_0 ;
  wire \U1/U3/holdingreg1<7>_MC.D2_PT_1 ;
  wire \U1/U3/holdingreg0<15>_MC.Q ;
  wire \U1/U3/holdingreg0<15>_MC.D ;
  wire \U1/U3/holdingreg0<15>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ;
  wire \U1/U3/holdingreg0<15>_MC.D1 ;
  wire \U1/U3/holdingreg0<15>_MC.D2 ;
  wire \U1/U3/holdingreg0<15>_MC.D2_PT_0 ;
  wire \U1/U3/holdingreg0<15>_MC.D2_PT_1 ;
  wire \U1/U3/holdingreg1<15>_MC.Q ;
  wire \U1/U3/holdingreg1<15>_MC.D ;
  wire \U1/U3/holdingreg1<15>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ;
  wire \U1/U3/holdingreg1<15>_MC.D1 ;
  wire \U1/U3/holdingreg1<15>_MC.D2 ;
  wire \U1/U3/holdingreg1<15>_MC.D2_PT_0 ;
  wire \U1/U3/holdingreg1<15>_MC.D2_PT_1 ;
  wire \outDATA<0>\$WA0.UIM_MC.Q ;
  wire \outDATA<0>\$WA0.UIM_MC.D ;
  wire \outDATA<0>\$WA0.UIM_MC.D1 ;
  wire \outDATA<0>\$WA0.UIM_MC.D2 ;
  wire \outDATA<0>\$WA1.UIM_MC.Q ;
  wire \outDATA<0>\$WA1.UIM_MC.D ;
  wire \outDATA<0>\$WA1.UIM_MC.D1 ;
  wire \outDATA<0>\$WA1.UIM_MC.D2 ;
  wire \outDATA<0>\$WA2.UIM_MC.Q ;
  wire \outDATA<0>\$WA2.UIM_MC.D ;
  wire \outDATA<0>\$WA2.UIM_MC.D1 ;
  wire \outDATA<0>\$WA2.UIM_MC.D2 ;
  wire \outDATA<0>\$WA3.UIM_MC.Q ;
  wire \outDATA<0>\$WA3.UIM_MC.D ;
  wire \outDATA<0>\$WA3.UIM_MC.D1 ;
  wire \outDATA<0>\$WA3.UIM_MC.D2 ;
  wire \outDATA<0>\$WA3.UIM_MC.D2_PT_0 ;
  wire \outDATA<0>\$WA3.UIM_MC.D2_PT_1 ;
  wire \outDATA<0>\$WA4.UIM_MC.Q ;
  wire \outDATA<0>\$WA4.UIM_MC.D ;
  wire \outDATA<0>\$WA4.UIM_MC.D1 ;
  wire \outDATA<0>\$WA4.UIM_MC.D2 ;
  wire \outDATA<0>\$WA6.UIM_MC.Q ;
  wire \outDATA<0>\$WA6.UIM_MC.D ;
  wire \outDATA<0>\$WA6.UIM_MC.D1 ;
  wire \outDATA<0>\$WA6.UIM_MC.D2 ;
  wire \outDATA<0>\$WA6.UIM_MC.D2_PT_0 ;
  wire \outDATA<0>\$WA6.UIM_MC.D2_PT_1 ;
  wire \outDATA<0>\$WA6.UIM_MC.D2_PT_2 ;
  wire \outDATA<0>\$WA6.UIM_MC.D2_PT_3 ;
  wire \U1/U4/Latch0r<0>_MC.Q ;
  wire \U1/U4/Latch0r<0>_MC.D ;
  wire \U1/U4/Latch0r<0>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ;
  wire \U1/U4/Latch0r<0>_MC.D1 ;
  wire \U1/U4/Latch0r<0>_MC.D2 ;
  wire \U1/U4/Latch0r<0>_MC.D2_PT_0 ;
  wire \U1/U4/Latch0r<0>_MC.D2_PT_1 ;
  wire \U1/U4/Latch0r<8>_MC.Q ;
  wire \U1/U4/Latch0r<8>_MC.D ;
  wire \U1/U4/Latch0r<8>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ;
  wire \U1/U4/Latch0r<8>_MC.D1 ;
  wire \U1/U4/Latch0r<8>_MC.D2 ;
  wire \U1/U4/Latch0r<8>_MC.D2_PT_0 ;
  wire \U1/U4/Latch0r<8>_MC.D2_PT_1 ;
  wire \U1/U4/Latch1r<0>_MC.Q ;
  wire \U1/U4/Latch1r<0>_MC.D ;
  wire \U1/U4/Latch1r<0>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ;
  wire \U1/U4/Latch1r<0>_MC.D1 ;
  wire \U1/U4/Latch1r<0>_MC.D2 ;
  wire \U1/U4/Latch1r<0>_MC.D2_PT_0 ;
  wire \U1/U4/Latch1r<0>_MC.D2_PT_1 ;
  wire \U1/U4/Latch1r<8>_MC.Q ;
  wire \U1/U4/Latch1r<8>_MC.D ;
  wire \U1/U4/Latch1r<8>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ;
  wire \U1/U4/Latch1r<8>_MC.D1 ;
  wire \U1/U4/Latch1r<8>_MC.D2 ;
  wire \U1/U4/Latch1r<8>_MC.D2_PT_0 ;
  wire \U1/U4/Latch1r<8>_MC.D2_PT_1 ;
  wire \outDATA<0>\$WA5.UIM_MC.Q ;
  wire \outDATA<0>\$WA5.UIM_MC.D ;
  wire \outDATA<0>\$WA5.UIM_MC.D1 ;
  wire \outDATA<0>\$WA5.UIM_MC.D2 ;
  wire \outDATA<0>\$WA5.UIM_MC.D2_PT_0 ;
  wire \outDATA<0>\$WA5.UIM_MC.D2_PT_1 ;
  wire \outDATA<0>\$WA5.UIM_MC.D2_PT_2 ;
  wire \outDATA<0>\$WA5.UIM_MC.D2_PT_3 ;
  wire \U1/U3/holdingreg0<0>_MC.Q ;
  wire \U1/U3/holdingreg0<0>_MC.D ;
  wire \U1/U3/holdingreg0<0>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ;
  wire \U1/U3/holdingreg0<0>_MC.D1 ;
  wire \U1/U3/holdingreg0<0>_MC.D2 ;
  wire \U1/U3/holdingreg0<0>_MC.D2_PT_0 ;
  wire \U1/U3/holdingreg0<0>_MC.D2_PT_1 ;
  wire \U1/U3/holdingreg1<0>_MC.Q ;
  wire \U1/U3/holdingreg1<0>_MC.D ;
  wire \U1/U3/holdingreg1<0>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ;
  wire \U1/U3/holdingreg1<0>_MC.D1 ;
  wire \U1/U3/holdingreg1<0>_MC.D2 ;
  wire \U1/U3/holdingreg1<0>_MC.D2_PT_0 ;
  wire \U1/U3/holdingreg1<0>_MC.D2_PT_1 ;
  wire \U1/U3/holdingreg0<8>_MC.Q ;
  wire \U1/U3/holdingreg0<8>_MC.D ;
  wire \U1/U3/holdingreg0<8>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ;
  wire \U1/U3/holdingreg0<8>_MC.D1 ;
  wire \U1/U3/holdingreg0<8>_MC.D2 ;
  wire \U1/U3/holdingreg0<8>_MC.D2_PT_0 ;
  wire \U1/U3/holdingreg0<8>_MC.D2_PT_1 ;
  wire \U1/U3/holdingreg1<8>_MC.Q ;
  wire \U1/U3/holdingreg1<8>_MC.D ;
  wire \U1/U3/holdingreg1<8>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ;
  wire \U1/U3/holdingreg1<8>_MC.D1 ;
  wire \U1/U3/holdingreg1<8>_MC.D2 ;
  wire \U1/U3/holdingreg1<8>_MC.D2_PT_0 ;
  wire \U1/U3/holdingreg1<8>_MC.D2_PT_1 ;
  wire \outDATA<1>\$WA0.UIM_MC.Q ;
  wire \outDATA<1>\$WA0.UIM_MC.D ;
  wire \outDATA<1>\$WA0.UIM_MC.D1 ;
  wire \outDATA<1>\$WA0.UIM_MC.D2 ;
  wire \outDATA<1>\$WA1.UIM_MC.Q ;
  wire \outDATA<1>\$WA1.UIM_MC.D ;
  wire \outDATA<1>\$WA1.UIM_MC.D1 ;
  wire \outDATA<1>\$WA1.UIM_MC.D2 ;
  wire \outDATA<1>\$WA2.UIM_MC.Q ;
  wire \outDATA<1>\$WA2.UIM_MC.D ;
  wire \outDATA<1>\$WA2.UIM_MC.D1 ;
  wire \outDATA<1>\$WA2.UIM_MC.D2 ;
  wire \outDATA<1>\$WA3.UIM_MC.Q ;
  wire \outDATA<1>\$WA3.UIM_MC.D ;
  wire \outDATA<1>\$WA3.UIM_MC.D1 ;
  wire \outDATA<1>\$WA3.UIM_MC.D2 ;
  wire \outDATA<1>\$WA3.UIM_MC.D2_PT_0 ;
  wire \outDATA<1>\$WA3.UIM_MC.D2_PT_1 ;
  wire \outDATA<1>\$WA3.UIM_MC.D2_PT_2 ;
  wire \outDATA<1>\$WA6.UIM_MC.Q ;
  wire \outDATA<1>\$WA6.UIM_MC.D ;
  wire \outDATA<1>\$WA6.UIM_MC.D1 ;
  wire \outDATA<1>\$WA6.UIM_MC.D2 ;
  wire \outDATA<1>\$WA6.UIM_MC.D2_PT_0 ;
  wire \outDATA<1>\$WA6.UIM_MC.D2_PT_1 ;
  wire \outDATA<1>\$WA6.UIM_MC.D2_PT_2 ;
  wire \outDATA<1>\$WA6.UIM_MC.D2_PT_3 ;
  wire \U1/U4/Latch0r<1>_MC.Q ;
  wire \U1/U4/Latch0r<1>_MC.D ;
  wire \U1/U4/Latch0r<1>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ;
  wire \U1/U4/Latch0r<1>_MC.D1 ;
  wire \U1/U4/Latch0r<1>_MC.D2 ;
  wire \U1/U4/Latch0r<1>_MC.D2_PT_0 ;
  wire \U1/U4/Latch0r<1>_MC.D2_PT_1 ;
  wire \U1/U4/Latch0r<9>_MC.Q ;
  wire \U1/U4/Latch0r<9>_MC.D ;
  wire \U1/U4/Latch0r<9>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ;
  wire \U1/U4/Latch0r<9>_MC.D1 ;
  wire \U1/U4/Latch0r<9>_MC.D2 ;
  wire \U1/U4/Latch0r<9>_MC.D2_PT_0 ;
  wire \U1/U4/Latch0r<9>_MC.D2_PT_1 ;
  wire \U1/U4/Latch1r<1>_MC.Q ;
  wire \U1/U4/Latch1r<1>_MC.D ;
  wire \U1/U4/Latch1r<1>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ;
  wire \U1/U4/Latch1r<1>_MC.D1 ;
  wire \U1/U4/Latch1r<1>_MC.D2 ;
  wire \U1/U4/Latch1r<1>_MC.D2_PT_0 ;
  wire \U1/U4/Latch1r<1>_MC.D2_PT_1 ;
  wire \U1/U4/Latch1r<9>_MC.Q ;
  wire \U1/U4/Latch1r<9>_MC.D ;
  wire \U1/U4/Latch1r<9>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ;
  wire \U1/U4/Latch1r<9>_MC.D1 ;
  wire \U1/U4/Latch1r<9>_MC.D2 ;
  wire \U1/U4/Latch1r<9>_MC.D2_PT_0 ;
  wire \U1/U4/Latch1r<9>_MC.D2_PT_1 ;
  wire \outDATA<1>\$WA5.UIM_MC.Q ;
  wire \outDATA<1>\$WA5.UIM_MC.D ;
  wire \outDATA<1>\$WA5.UIM_MC.D1 ;
  wire \outDATA<1>\$WA5.UIM_MC.D2 ;
  wire \outDATA<1>\$WA5.UIM_MC.D2_PT_0 ;
  wire \outDATA<1>\$WA5.UIM_MC.D2_PT_1 ;
  wire \outDATA<1>\$WA5.UIM_MC.D2_PT_2 ;
  wire \outDATA<1>\$WA5.UIM_MC.D2_PT_3 ;
  wire \U1/U3/holdingreg0<1>_MC.Q ;
  wire \U1/U3/holdingreg0<1>_MC.D ;
  wire \U1/U3/holdingreg0<1>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ;
  wire \U1/U3/holdingreg0<1>_MC.D1 ;
  wire \U1/U3/holdingreg0<1>_MC.D2 ;
  wire \U1/U3/holdingreg0<1>_MC.D2_PT_0 ;
  wire \U1/U3/holdingreg0<1>_MC.D2_PT_1 ;
  wire \U1/U3/holdingreg1<1>_MC.Q ;
  wire \U1/U3/holdingreg1<1>_MC.D ;
  wire \U1/U3/holdingreg1<1>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ;
  wire \U1/U3/holdingreg1<1>_MC.D1 ;
  wire \U1/U3/holdingreg1<1>_MC.D2 ;
  wire \U1/U3/holdingreg1<1>_MC.D2_PT_0 ;
  wire \U1/U3/holdingreg1<1>_MC.D2_PT_1 ;
  wire \U1/U3/holdingreg0<9>_MC.Q ;
  wire \U1/U3/holdingreg0<9>_MC.D ;
  wire \U1/U3/holdingreg0<9>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ;
  wire \U1/U3/holdingreg0<9>_MC.D1 ;
  wire \U1/U3/holdingreg0<9>_MC.D2 ;
  wire \U1/U3/holdingreg0<9>_MC.D2_PT_0 ;
  wire \U1/U3/holdingreg0<9>_MC.D2_PT_1 ;
  wire \U1/U3/holdingreg1<9>_MC.Q ;
  wire \U1/U3/holdingreg1<9>_MC.D ;
  wire \U1/U3/holdingreg1<9>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ;
  wire \U1/U3/holdingreg1<9>_MC.D1 ;
  wire \U1/U3/holdingreg1<9>_MC.D2 ;
  wire \U1/U3/holdingreg1<9>_MC.D2_PT_0 ;
  wire \U1/U3/holdingreg1<9>_MC.D2_PT_1 ;
  wire \outDATA<4>\$WA0.UIM_MC.Q ;
  wire \outDATA<4>\$WA0.UIM_MC.D ;
  wire \outDATA<4>\$WA0.UIM_MC.D1 ;
  wire \outDATA<4>\$WA0.UIM_MC.D2 ;
  wire \outDATA<4>\$WA1.UIM_MC.Q ;
  wire \outDATA<4>\$WA1.UIM_MC.D ;
  wire \outDATA<4>\$WA1.UIM_MC.D1 ;
  wire \outDATA<4>\$WA1.UIM_MC.D2 ;
  wire \outDATA<4>\$WA2.UIM_MC.Q ;
  wire \outDATA<4>\$WA2.UIM_MC.D ;
  wire \outDATA<4>\$WA2.UIM_MC.D1 ;
  wire \outDATA<4>\$WA2.UIM_MC.D2 ;
  wire \outDATA<4>\$WA3.UIM_MC.Q ;
  wire \outDATA<4>\$WA3.UIM_MC.D ;
  wire \outDATA<4>\$WA3.UIM_MC.D1 ;
  wire \outDATA<4>\$WA3.UIM_MC.D2 ;
  wire \outDATA<4>\$WA3.UIM_MC.D2_PT_0 ;
  wire \outDATA<4>\$WA3.UIM_MC.D2_PT_1 ;
  wire \outDATA<4>\$WA4.UIM_MC.Q ;
  wire \outDATA<4>\$WA4.UIM_MC.D ;
  wire \outDATA<4>\$WA4.UIM_MC.D1 ;
  wire \outDATA<4>\$WA4.UIM_MC.D2 ;
  wire \outDATA<4>\$WA6.UIM_MC.Q ;
  wire \outDATA<4>\$WA6.UIM_MC.D ;
  wire \outDATA<4>\$WA6.UIM_MC.D1 ;
  wire \outDATA<4>\$WA6.UIM_MC.D2 ;
  wire \outDATA<4>\$WA6.UIM_MC.D2_PT_0 ;
  wire \outDATA<4>\$WA6.UIM_MC.D2_PT_1 ;
  wire \outDATA<4>\$WA6.UIM_MC.D2_PT_2 ;
  wire \outDATA<4>\$WA6.UIM_MC.D2_PT_3 ;
  wire \U1/U4/Latch0r<4>_MC.Q ;
  wire \U1/U4/Latch0r<4>_MC.D ;
  wire \U1/U4/Latch0r<4>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ;
  wire \U1/U4/Latch0r<4>_MC.D1 ;
  wire \U1/U4/Latch0r<4>_MC.D2 ;
  wire \U1/U4/Latch0r<4>_MC.D2_PT_0 ;
  wire \U1/U4/Latch0r<4>_MC.D2_PT_1 ;
  wire \U1/U4/Latch0r<12>_MC.Q ;
  wire \U1/U4/Latch0r<12>_MC.D ;
  wire \U1/U4/Latch0r<12>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ;
  wire \U1/U4/Latch0r<12>_MC.D1 ;
  wire \U1/U4/Latch0r<12>_MC.D2 ;
  wire \U1/U4/Latch0r<12>_MC.D2_PT_0 ;
  wire \U1/U4/Latch0r<12>_MC.D2_PT_1 ;
  wire \U1/U4/Latch1r<4>_MC.Q ;
  wire \U1/U4/Latch1r<4>_MC.D ;
  wire \U1/U4/Latch1r<4>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ;
  wire \U1/U4/Latch1r<4>_MC.D1 ;
  wire \U1/U4/Latch1r<4>_MC.D2 ;
  wire \U1/U4/Latch1r<4>_MC.D2_PT_0 ;
  wire \U1/U4/Latch1r<4>_MC.D2_PT_1 ;
  wire \U1/U4/Latch1r<12>_MC.Q ;
  wire \U1/U4/Latch1r<12>_MC.D ;
  wire \U1/U4/Latch1r<12>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ;
  wire \U1/U4/Latch1r<12>_MC.D1 ;
  wire \U1/U4/Latch1r<12>_MC.D2 ;
  wire \U1/U4/Latch1r<12>_MC.D2_PT_0 ;
  wire \U1/U4/Latch1r<12>_MC.D2_PT_1 ;
  wire \outDATA<4>\$WA5.UIM_MC.Q ;
  wire \outDATA<4>\$WA5.UIM_MC.D ;
  wire \outDATA<4>\$WA5.UIM_MC.D1 ;
  wire \outDATA<4>\$WA5.UIM_MC.D2 ;
  wire \outDATA<4>\$WA5.UIM_MC.D2_PT_0 ;
  wire \outDATA<4>\$WA5.UIM_MC.D2_PT_1 ;
  wire \outDATA<4>\$WA5.UIM_MC.D2_PT_2 ;
  wire \outDATA<4>\$WA5.UIM_MC.D2_PT_3 ;
  wire \U1/U3/holdingreg0<4>_MC.Q ;
  wire \U1/U3/holdingreg0<4>_MC.D ;
  wire \U1/U3/holdingreg0<4>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ;
  wire \U1/U3/holdingreg0<4>_MC.D1 ;
  wire \U1/U3/holdingreg0<4>_MC.D2 ;
  wire \U1/U3/holdingreg0<4>_MC.D2_PT_0 ;
  wire \U1/U3/holdingreg0<4>_MC.D2_PT_1 ;
  wire \U1/U3/holdingreg1<4>_MC.Q ;
  wire \U1/U3/holdingreg1<4>_MC.D ;
  wire \U1/U3/holdingreg1<4>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ;
  wire \U1/U3/holdingreg1<4>_MC.D1 ;
  wire \U1/U3/holdingreg1<4>_MC.D2 ;
  wire \U1/U3/holdingreg1<4>_MC.D2_PT_0 ;
  wire \U1/U3/holdingreg1<4>_MC.D2_PT_1 ;
  wire \U1/U3/holdingreg0<12>_MC.Q ;
  wire \U1/U3/holdingreg0<12>_MC.D ;
  wire \U1/U3/holdingreg0<12>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ;
  wire \U1/U3/holdingreg0<12>_MC.D1 ;
  wire \U1/U3/holdingreg0<12>_MC.D2 ;
  wire \U1/U3/holdingreg0<12>_MC.D2_PT_0 ;
  wire \U1/U3/holdingreg0<12>_MC.D2_PT_1 ;
  wire \U1/U3/holdingreg1<12>_MC.Q ;
  wire \U1/U3/holdingreg1<12>_MC.D ;
  wire \U1/U3/holdingreg1<12>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ;
  wire \U1/U3/holdingreg1<12>_MC.D1 ;
  wire \U1/U3/holdingreg1<12>_MC.D2 ;
  wire \U1/U3/holdingreg1<12>_MC.D2_PT_0 ;
  wire \U1/U3/holdingreg1<12>_MC.D2_PT_1 ;
  wire \NlwInverterSignal_AD<5>_MC.D/IN0 ;
  wire \NlwInverterSignal_AD<5>_MC.D2_PT_0/IN1 ;
  wire \NlwInverterSignal_AD<5>_MC.D2_PT_1/IN1 ;
  wire \NlwInverterSignal_AD<5>_MC.D2_PT_2/IN1 ;
  wire \NlwInverterSignal_AD<5>_MC.D2_PT_3/IN1 ;
  wire \NlwInverterSignal_AD<5>_MC.D2_PT_4/IN0 ;
  wire \NlwInverterSignal_AD<5>_MC.D2_PT_4/IN1 ;
  wire \NlwInverterSignal_AD<5>_MC.D2_PT_5/IN0 ;
  wire \NlwInverterSignal_AD<5>_MC.D2_PT_5/IN1 ;
  wire \NlwInverterSignal_DCORI2CCNTr_MC.D1/IN1 ;
  wire \NlwInverterSignal_DCORI2CCNTr_MC.D1/IN2 ;
  wire \NlwInverterSignal_DCORI2CCNTr_MC.D1/IN3 ;
  wire \NlwInverterSignal_DCORI2CCNTr_MC.D1/IN4 ;
  wire \NlwInverterSignal_DCORI2CCNTr_MC.D1/IN5 ;
  wire \NlwInverterSignal_DCORI2CCNTr_MC.D1/IN6 ;
  wire \NlwInverterSignal_DCORI2CCNTr_MC.D1/IN7 ;
  wire \NlwInverterSignal_DCORI2CCNTr_MC.D1/IN8 ;
  wire \NlwInverterSignal_DCORI2CCNTr_MC.D1/IN9 ;
  wire \NlwInverterSignal_U2_ADDR_reg<0>_MC.D2_PT_0/IN1 ;
  wire \NlwInverterSignal_U2_ADDR_reg<0>_MC.D2_PT_1/IN3 ;
  wire \NlwInverterSignal_U2_ADDR_reg<0>_MC.D2_PT_1/IN4 ;
  wire \NlwInverterSignal_U2_ADDR_reg<0>_MC.D2_PT_2/IN2 ;
  wire \NlwInverterSignal_U2_ADDR_reg<0>_MC.D2_PT_2/IN5 ;
  wire \NlwInverterSignal_U2_ADDR_reg<0>_MC.D2_PT_3/IN2 ;
  wire \NlwInverterSignal_U2_ADDR_reg<0>_MC.D2_PT_3/IN3 ;
  wire \NlwInverterSignal_U2_ADDR_reg<0>_MC.D2_PT_3/IN4 ;
  wire \NlwInverterSignal_U2_ADDR_reg<0>_MC.D2_PT_3/IN5 ;
  wire \NlwInverterSignal_U2_ADDR_reg<0>_MC.D2_PT_3/IN7 ;
  wire \NlwInverterSignal_U2_ADDR_reg<4>_MC.D2_PT_0/IN1 ;
  wire \NlwInverterSignal_U2_ADDR_reg<4>_MC.D2_PT_1/IN3 ;
  wire \NlwInverterSignal_U2_ADDR_reg<4>_MC.D2_PT_1/IN5 ;
  wire \NlwInverterSignal_U2_ADDR_reg<4>_MC.D2_PT_2/IN2 ;
  wire \NlwInverterSignal_U2_ADDR_reg<4>_MC.D2_PT_2/IN4 ;
  wire \NlwInverterSignal_U2_ADDR_reg<5>_MC.D2_PT_0/IN1 ;
  wire \NlwInverterSignal_U2_ADDR_reg<5>_MC.D2_PT_1/IN3 ;
  wire \NlwInverterSignal_U2_ADDR_reg<5>_MC.D2_PT_1/IN5 ;
  wire \NlwInverterSignal_U2_ADDR_reg<5>_MC.D2_PT_2/IN2 ;
  wire \NlwInverterSignal_U2_ADDR_reg<5>_MC.D2_PT_2/IN4 ;
  wire \NlwInverterSignal_U2_ADDR_reg<6>_MC.D2_PT_0/IN1 ;
  wire \NlwInverterSignal_U2_ADDR_reg<6>_MC.D2_PT_1/IN3 ;
  wire \NlwInverterSignal_U2_ADDR_reg<6>_MC.D2_PT_1/IN5 ;
  wire \NlwInverterSignal_U2_ADDR_reg<6>_MC.D2_PT_2/IN2 ;
  wire \NlwInverterSignal_U2_ADDR_reg<6>_MC.D2_PT_2/IN4 ;
  wire \NlwInverterSignal_U2_ADDR_reg<7>_MC.D2_PT_0/IN1 ;
  wire \NlwInverterSignal_U2_ADDR_reg<7>_MC.D2_PT_1/IN3 ;
  wire \NlwInverterSignal_U2_ADDR_reg<7>_MC.D2_PT_1/IN5 ;
  wire \NlwInverterSignal_U2_ADDR_reg<7>_MC.D2_PT_2/IN2 ;
  wire \NlwInverterSignal_U2_ADDR_reg<7>_MC.D2_PT_2/IN4 ;
  wire \NlwInverterSignal_U2_AutoInc_MC.D/IN0 ;
  wire \NlwInverterSignal_N_PZ_938_MC.D2_PT_1/IN1 ;
  wire \NlwInverterSignal_U2_ADDR_reg<3>_MC.D2_PT_0/IN1 ;
  wire \NlwInverterSignal_U2_ADDR_reg<3>_MC.D2_PT_1/IN3 ;
  wire \NlwInverterSignal_U2_ADDR_reg<3>_MC.D2_PT_1/IN5 ;
  wire \NlwInverterSignal_U2_ADDR_reg<3>_MC.D2_PT_2/IN2 ;
  wire \NlwInverterSignal_U2_ADDR_reg<3>_MC.D2_PT_2/IN4 ;
  wire \NlwInverterSignal_U2_ADDR_reg<3>_MC.D2_PT_3/IN3 ;
  wire \NlwInverterSignal_U2_ADDR_reg<3>_MC.D2_PT_3/IN4 ;
  wire \NlwInverterSignal_U2_ADDR_reg<3>_MC.D2_PT_3/IN5 ;
  wire \NlwInverterSignal_U2_ADDR_reg<3>_MC.D2_PT_3/IN6 ;
  wire \NlwInverterSignal_U2_ADDR_reg<3>_MC.D2_PT_3/IN10 ;
  wire \NlwInverterSignal_U2_ADDR_reg<1>_MC.D2_PT_0/IN1 ;
  wire \NlwInverterSignal_U2_ADDR_reg<1>_MC.D2_PT_1/IN3 ;
  wire \NlwInverterSignal_U2_ADDR_reg<1>_MC.D2_PT_1/IN5 ;
  wire \NlwInverterSignal_U2_ADDR_reg<1>_MC.D2_PT_2/IN2 ;
  wire \NlwInverterSignal_U2_ADDR_reg<1>_MC.D2_PT_2/IN4 ;
  wire \NlwInverterSignal_U2_ADDR_reg<1>_MC.D2_PT_3/IN3 ;
  wire \NlwInverterSignal_U2_ADDR_reg<1>_MC.D2_PT_3/IN4 ;
  wire \NlwInverterSignal_U2_ADDR_reg<1>_MC.D2_PT_3/IN5 ;
  wire \NlwInverterSignal_U2_ADDR_reg<1>_MC.D2_PT_3/IN6 ;
  wire \NlwInverterSignal_U2_ADDR_reg<1>_MC.D2_PT_3/IN8 ;
  wire \NlwInverterSignal_U2_ADDR_reg<2>_MC.D2_PT_0/IN1 ;
  wire \NlwInverterSignal_U2_ADDR_reg<2>_MC.D2_PT_1/IN3 ;
  wire \NlwInverterSignal_U2_ADDR_reg<2>_MC.D2_PT_1/IN5 ;
  wire \NlwInverterSignal_U2_ADDR_reg<2>_MC.D2_PT_2/IN2 ;
  wire \NlwInverterSignal_U2_ADDR_reg<2>_MC.D2_PT_2/IN4 ;
  wire \NlwInverterSignal_U2_ADDR_reg<2>_MC.D2_PT_3/IN3 ;
  wire \NlwInverterSignal_U2_ADDR_reg<2>_MC.D2_PT_3/IN4 ;
  wire \NlwInverterSignal_U2_ADDR_reg<2>_MC.D2_PT_3/IN5 ;
  wire \NlwInverterSignal_U2_ADDR_reg<2>_MC.D2_PT_3/IN6 ;
  wire \NlwInverterSignal_U2_ADDR_reg<2>_MC.D2_PT_3/IN9 ;
  wire \NlwInverterSignal_U11_U3_counterr<5>_MC.D2_PT_1/IN0 ;
  wire \NlwInverterSignal_U11_U3_counterr<5>_MC.D2_PT_2/IN0 ;
  wire \NlwInverterSignal_U11_U3_counterr<5>_MC.D2_PT_2/IN3 ;
  wire \NlwInverterSignal_U11_U3_counterr<5>_MC.D2_PT_3/IN0 ;
  wire \NlwInverterSignal_U11_U3_counterr<5>_MC.D2_PT_3/IN1 ;
  wire \NlwInverterSignal_U11_U3_counterr<5>_MC.D2_PT_3/IN2 ;
  wire \NlwInverterSignal_U11_U3_counterr<5>_MC.D2_PT_3/IN3 ;
  wire \NlwInverterSignal_U11_U3_counterr<5>_MC.D2_PT_3/IN5 ;
  wire \NlwInverterSignal_U11_U3_counterr<5>_MC.D2_PT_3/IN6 ;
  wire \NlwInverterSignal_U11_U3_counterr<5>_MC.D2_PT_3/IN7 ;
  wire \NlwInverterSignal_N_PZ_1065_MC.D2_PT_1/IN1 ;
  wire \NlwInverterSignal_N_PZ_1065_MC.D2_PT_2/IN0 ;
  wire \NlwInverterSignal_U11_Incdetect_MC.D1/IN0 ;
  wire \NlwInverterSignal_U11_ResetDetect_MC.D1/IN0 ;
  wire \NlwInverterSignal_U11_SCLdetect_MC.D1/IN0 ;
  wire \NlwInverterSignal_TP12_MC.D1/IN0 ;
  wire \NlwInverterSignal_TP12_MC.D1/IN1 ;
  wire \NlwInverterSignal_TP12_MC.D1/IN2 ;
  wire \NlwInverterSignal_TP12_MC.D1/IN3 ;
  wire \NlwInverterSignal_TP12_MC.D1/IN4 ;
  wire \NlwInverterSignal_TP12_MC.D1/IN5 ;
  wire \NlwInverterSignal_U11_U3_counterr<3>_MC.D/IN0 ;
  wire \NlwInverterSignal_U11_U3_counterr<3>_MC.D2_PT_1/IN1 ;
  wire \NlwInverterSignal_U11_U3_counterr<3>_MC.D2_PT_1/IN2 ;
  wire \NlwInverterSignal_U11_U3_counterr<3>_MC.D2_PT_2/IN0 ;
  wire \NlwInverterSignal_U11_U3_counterr<3>_MC.D2_PT_2/IN1 ;
  wire \NlwInverterSignal_U11_U3_counterr<3>_MC.D2_PT_2/IN2 ;
  wire \NlwInverterSignal_U11_U3_counterr<3>_MC.D2_PT_3/IN0 ;
  wire \NlwInverterSignal_U11_U3_counterr<3>_MC.D2_PT_3/IN1 ;
  wire \NlwInverterSignal_U11_U3_counterr<3>_MC.D2_PT_4/IN0 ;
  wire \NlwInverterSignal_U11_U3_counterr<3>_MC.D2_PT_4/IN1 ;
  wire \NlwInverterSignal_U11_U3_counterr<3>_MC.D2_PT_5/IN0 ;
  wire \NlwInverterSignal_U11_U3_counterr<3>_MC.D2_PT_5/IN1 ;
  wire \NlwInverterSignal_U11_U3_counterr<3>_MC.D2_PT_6/IN0 ;
  wire \NlwInverterSignal_U11_U3_counterr<3>_MC.D2_PT_6/IN1 ;
  wire \NlwInverterSignal_U11_U3_counterr<0>_MC.D2_PT_1/IN3 ;
  wire \NlwInverterSignal_U11_U3_counterr<0>_MC.D2_PT_2/IN1 ;
  wire \NlwInverterSignal_U11_U3_counterr<0>_MC.D2_PT_2/IN2 ;
  wire \NlwInverterSignal_U11_U3_counterr<0>_MC.D2_PT_2/IN3 ;
  wire \NlwInverterSignal_U11_U3_counterr<0>_MC.D2_PT_3/IN1 ;
  wire \NlwInverterSignal_U11_U3_counterr<0>_MC.D2_PT_3/IN2 ;
  wire \NlwInverterSignal_U11_U3_counterr<0>_MC.D2_PT_4/IN0 ;
  wire \NlwInverterSignal_U11_U3_counterr<0>_MC.D2_PT_4/IN1 ;
  wire \NlwInverterSignal_U11_U3_counterr<0>_MC.D2_PT_4/IN3 ;
  wire \NlwInverterSignal_U11_U3_counterr<0>_MC.D2_PT_5/IN0 ;
  wire \NlwInverterSignal_U11_U3_counterr<0>_MC.D2_PT_5/IN2 ;
  wire \NlwInverterSignal_U11_U3_counterr<0>_MC.D2_PT_5/IN3 ;
  wire \NlwInverterSignal_U11_U3_counterr<0>_MC.D2_PT_5/IN4 ;
  wire \NlwInverterSignal_U11_U3_counterr<1>_MC.D2_PT_0/IN2 ;
  wire \NlwInverterSignal_U11_U3_counterr<1>_MC.D2_PT_1/IN0 ;
  wire \NlwInverterSignal_U11_U3_counterr<1>_MC.D2_PT_1/IN2 ;
  wire \NlwInverterSignal_U11_U3_counterr<1>_MC.D2_PT_2/IN0 ;
  wire \NlwInverterSignal_U11_U3_counterr<1>_MC.D2_PT_2/IN1 ;
  wire \NlwInverterSignal_U11_U3_counterr<1>_MC.D2_PT_2/IN3 ;
  wire \NlwInverterSignal_U11_U3_counterr<2>_MC.D2_PT_1/IN0 ;
  wire \NlwInverterSignal_U11_U3_counterr<2>_MC.D2_PT_1/IN2 ;
  wire \NlwInverterSignal_U11_U3_counterr<2>_MC.D2_PT_2/IN0 ;
  wire \NlwInverterSignal_U11_U3_counterr<2>_MC.D2_PT_2/IN1 ;
  wire \NlwInverterSignal_U11_U3_counterr<2>_MC.D2_PT_2/IN3 ;
  wire \NlwInverterSignal_U11_U3_counterr<2>_MC.D2_PT_2/IN4 ;
  wire \NlwInverterSignal_U11_U3_counterr<4>_MC.D2_PT_1/IN0 ;
  wire \NlwInverterSignal_U11_U3_counterr<4>_MC.D2_PT_2/IN0 ;
  wire \NlwInverterSignal_U11_U3_counterr<4>_MC.D2_PT_2/IN2 ;
  wire \NlwInverterSignal_U11_U3_counterr<4>_MC.D2_PT_3/IN0 ;
  wire \NlwInverterSignal_U11_U3_counterr<4>_MC.D2_PT_3/IN1 ;
  wire \NlwInverterSignal_U11_U3_counterr<4>_MC.D2_PT_3/IN2 ;
  wire \NlwInverterSignal_U11_U3_counterr<4>_MC.D2_PT_3/IN4 ;
  wire \NlwInverterSignal_U11_U3_counterr<4>_MC.D2_PT_3/IN5 ;
  wire \NlwInverterSignal_U11_U3_counterr<4>_MC.D2_PT_3/IN6 ;
  wire \NlwInverterSignal_DCORCONFIGr_MC.D1/IN1 ;
  wire \NlwInverterSignal_DCORCONFIGr_MC.D1/IN3 ;
  wire \NlwInverterSignal_DCORCONFIGr_MC.D1/IN4 ;
  wire \NlwInverterSignal_DCORCONFIGr_MC.D1/IN5 ;
  wire \NlwInverterSignal_DCORCONFIGr_MC.D1/IN6 ;
  wire \NlwInverterSignal_DCORLIMITSr_MC.D1/IN1 ;
  wire \NlwInverterSignal_DCORLIMITSr_MC.D1/IN2 ;
  wire \NlwInverterSignal_DCORLIMITSr_MC.D1/IN3 ;
  wire \NlwInverterSignal_DCORLIMITSr_MC.D1/IN4 ;
  wire \NlwInverterSignal_DCORLIMITSr_MC.D1/IN5 ;
  wire \NlwInverterSignal_DCORLIMITSr_MC.D1/IN6 ;
  wire \NlwInverterSignal_DCORLIMITSr_MC.D1/IN7 ;
  wire \NlwInverterSignal_DCORLIMITSr_MC.D1/IN9 ;
  wire \NlwInverterSignal_DCORENCPWRr_MC.D1/IN1 ;
  wire \NlwInverterSignal_DCORENCPWRr_MC.D1/IN2 ;
  wire \NlwInverterSignal_DCORENCPWRr_MC.D1/IN3 ;
  wire \NlwInverterSignal_DCORENCPWRr_MC.D1/IN4 ;
  wire \NlwInverterSignal_DCORENCPWRr_MC.D1/IN5 ;
  wire \NlwInverterSignal_DCORENCPWRr_MC.D1/IN6 ;
  wire \NlwInverterSignal_outDATA<5>\$WA3.UIM_MC.D2_PT_0/IN1 ;
  wire \NlwInverterSignal_NET2528_MC.D1/IN1 ;
  wire \NlwInverterSignal_NET2528_MC.D2_PT_0/IN1 ;
  wire \NlwInverterSignal_NET2528_MC.D2_PT_1/IN2 ;
  wire \NlwInverterSignal_NET2528_MC.D2_PT_1/IN3 ;
  wire \NlwInverterSignal_DCORIFGw_MC.D1/IN0 ;
  wire \NlwInverterSignal_DCORIFGw_MC.D1/IN3 ;
  wire \NlwInverterSignal_DCORIFGw_MC.D1/IN4 ;
  wire \NlwInverterSignal_DCORIFGw_MC.D1/IN5 ;
  wire \NlwInverterSignal_DCORIFGw_MC.D1/IN6 ;
  wire \NlwInverterSignal_DCORIFGw_MC.D1/IN7 ;
  wire \NlwInverterSignal_DCORIFGw_MC.D1/IN8 ;
  wire \NlwInverterSignal_DCORIFGw_MC.D1/IN9 ;
  wire \NlwInverterSignal_outDATA<5>\$WA5.UIM_MC.D2_PT_1/IN0 ;
  wire \NlwInverterSignal_outDATA<5>\$WA5.UIM_MC.D2_PT_2/IN0 ;
  wire \NlwInverterSignal_outDATA<5>\$WA5.UIM_MC.D2_PT_2/IN1 ;
  wire \NlwInverterSignal_outDATA<5>\$WA5.UIM_MC.D2_PT_3/IN0 ;
  wire \NlwInverterSignal_outDATA<5>\$WA5.UIM_MC.D2_PT_3/IN1 ;
  wire \NlwInverterSignal_outDATA<5>\$WA5.UIM_MC.D2_PT_3/IN2 ;
  wire \NlwInverterSignal_U1/U3/holdingreg0<5>_MC.D2_PT_1/IN1 ;
  wire \NlwInverterSignal_U1/Channel0<5>_MC.D2_PT_0/IN1 ;
  wire \NlwInverterSignal_U1/Channel0<5>_MC.D2_PT_2/IN0 ;
  wire \NlwInverterSignal_N_PZ_928_MC.D1/IN1 ;
  wire \NlwInverterSignal_U1/Zero0_MC.D2_PT_0/IN0 ;
  wire \NlwInverterSignal_U1/Zero0_MC.D2_PT_3/IN1 ;
  wire \NlwInverterSignal_U1/Zero0_MC.D2_PT_3/IN2 ;
  wire \NlwInverterSignal_U1/Zero0_MC.D2_PT_3/IN3 ;
  wire \NlwInverterSignal_U1/Zero0_MC.D2_PT_3/IN7 ;
  wire \NlwInverterSignal_U1/Zero0_MC.D2_PT_4/IN1 ;
  wire \NlwInverterSignal_U1/Zero0_MC.D2_PT_4/IN2 ;
  wire \NlwInverterSignal_U1/Zero0_MC.D2_PT_4/IN3 ;
  wire \NlwInverterSignal_U1/Zero0_MC.D2_PT_4/IN4 ;
  wire \NlwInverterSignal_U1/Zero0_MC.D2_PT_4/IN6 ;
  wire \NlwInverterSignal_DCORENCCTLw_MC.D1/IN0 ;
  wire \NlwInverterSignal_DCORENCCTLw_MC.D1/IN3 ;
  wire \NlwInverterSignal_DCORENCCTLw_MC.D1/IN4 ;
  wire \NlwInverterSignal_DCORENCCTLw_MC.D1/IN5 ;
  wire \NlwInverterSignal_DCORENCCTLw_MC.D1/IN6 ;
  wire \NlwInverterSignal_DCORENCCTLw_MC.D1/IN7 ;
  wire \NlwInverterSignal_DCORENCCTLw_MC.D1/IN9 ;
  wire \NlwInverterSignal_NET2482_MC.D2_PT_0/IN0 ;
  wire \NlwInverterSignal_NET2482_MC.D2_PT_1/IN2 ;
  wire \NlwInverterSignal_NET2482_MC.D2_PT_2/IN1 ;
  wire \NlwInverterSignal_NET2482_MC.D2_PT_2/IN2 ;
  wire \NlwInverterSignal_NET2482_MC.D2_PT_2/IN3 ;
  wire \NlwInverterSignal_NET2482_MC.D2_PT_2/IN7 ;
  wire \NlwInverterSignal_NET2482_MC.D2_PT_3/IN1 ;
  wire \NlwInverterSignal_NET2482_MC.D2_PT_3/IN2 ;
  wire \NlwInverterSignal_NET2482_MC.D2_PT_3/IN3 ;
  wire \NlwInverterSignal_NET2482_MC.D2_PT_3/IN4 ;
  wire \NlwInverterSignal_NET2482_MC.D2_PT_3/IN6 ;
  wire \NlwInverterSignal_U1/U4/RF0r_MC.D2_PT_1/IN1 ;
  wire \NlwInverterSignal_U1/U4/E0r_MC.D2_PT_1/IN1 ;
  wire \NlwInverterSignal_U1/U2/location_Maddsub__n0000__n0067<0>_MC.D2_PT_1/IN0 ;
  wire \NlwInverterSignal_U1/U2/location_Maddsub__n0000__n0067<0>_MC.D2_PT_1/IN1 ;
  wire \NlwInverterSignal_U1/U2/location_Maddsub__n0000__n0067<0>_MC.D2_PT_1/IN2 ;
  wire \NlwInverterSignal_U1/U2/location_Maddsub__n0000__n0067<0>_MC.D2_PT_1/IN3 ;
  wire \NlwInverterSignal_U1/U2/location_Maddsub__n0000__n0067<0>_MC.D2_PT_1/IN4 ;
  wire \NlwInverterSignal_U1/U2/location_Maddsub__n0000__n0067<0>_MC.D2_PT_1/IN5 ;
  wire \NlwInverterSignal_N_PZ_943_MC.D2_PT_0/IN0 ;
  wire \NlwInverterSignal_N_PZ_943_MC.D2_PT_0/IN2 ;
  wire \NlwInverterSignal_N_PZ_943_MC.D2_PT_1/IN0 ;
  wire \NlwInverterSignal_N_PZ_943_MC.D2_PT_1/IN2 ;
  wire \NlwInverterSignal_U1/NET3721_MC.D2_PT_1/IN1 ;
  wire \NlwInverterSignal_U1/U1/CurrState_Sreg0_FFD1_MC.D2_PT_0/IN3 ;
  wire \NlwInverterSignal_U1/U1/CurrState_Sreg0_FFD1_MC.D2_PT_1/IN2 ;
  wire \NlwInverterSignal_U1/U1/CurrState_Sreg0_FFD1_MC.D2_PT_1/IN3 ;
  wire \NlwInverterSignal_U1/U1/CurrState_Sreg0_FFD1_MC.D2_PT_2/IN1 ;
  wire \NlwInverterSignal_U1/U1/CurrState_Sreg0_FFD1_MC.D2_PT_2/IN2 ;
  wire \NlwInverterSignal_U1/U1/CurrState_Sreg0_FFD1_MC.D2_PT_2/IN3 ;
  wire \NlwInverterSignal_U1/U1/CurrState_Sreg0_FFD1_MC.D2_PT_2/IN4 ;
  wire \NlwInverterSignal_U1/U1/CurrState_Sreg0_FFD3_MC.D2_PT_0/IN1 ;
  wire \NlwInverterSignal_U1/U1/CurrState_Sreg0_FFD3_MC.D2_PT_0/IN3 ;
  wire \NlwInverterSignal_U1/U1/CurrState_Sreg0_FFD3_MC.D2_PT_0/IN4 ;
  wire \NlwInverterSignal_U1/U1/CurrState_Sreg0_FFD3_MC.D2_PT_1/IN3 ;
  wire \NlwInverterSignal_U1/U1/CurrState_Sreg0_FFD3_MC.D2_PT_1/IN4 ;
  wire \NlwInverterSignal_U1/U1/CurrState_Sreg0_FFD3_MC.D2_PT_2/IN3 ;
  wire \NlwInverterSignal_U1/U1/CurrState_Sreg0_FFD3_MC.D2_PT_2/IN5 ;
  wire \NlwInverterSignal_U1/U1/CurrState_Sreg0_FFD3_MC.D2_PT_3/IN1 ;
  wire \NlwInverterSignal_U1/U1/CurrState_Sreg0_FFD3_MC.D2_PT_3/IN3 ;
  wire \NlwInverterSignal_U1/U1/CurrState_Sreg0_FFD2_MC.D2_PT_0/IN4 ;
  wire \NlwInverterSignal_U1/U1/CurrState_Sreg0_FFD2_MC.D2_PT_1/IN2 ;
  wire \NlwInverterSignal_U1/U1/CurrState_Sreg0_FFD2_MC.D2_PT_1/IN4 ;
  wire \NlwInverterSignal_U1/U1/CurrState_Sreg0_FFD2_MC.D2_PT_1/IN5 ;
  wire \NlwInverterSignal_U1/U1/CurrState_Sreg0_FFD2_MC.D2_PT_2/IN2 ;
  wire \NlwInverterSignal_U1/U1/CurrState_Sreg0_FFD2_MC.D2_PT_2/IN3 ;
  wire \NlwInverterSignal_U1/U1/CurrState_Sreg0_FFD2_MC.D2_PT_3/IN3 ;
  wire \NlwInverterSignal_U1/U1/CurrState_Sreg0_FFD2_MC.D2_PT_3/IN5 ;
  wire \NlwInverterSignal_U1/U1/CurrState_Sreg0_FFD2_MC.D2_PT_4/IN1 ;
  wire \NlwInverterSignal_U1/U1/CurrState_Sreg0_FFD2_MC.D2_PT_4/IN4 ;
  wire \NlwInverterSignal_U1/U1/CurrState_Sreg0_FFD2_MC.D2_PT_4/IN5 ;
  wire \NlwInverterSignal_U1/U1/CurrState_Sreg0_FFD2_MC.D2_PT_5/IN1 ;
  wire \NlwInverterSignal_U1/U1/CurrState_Sreg0_FFD2_MC.D2_PT_5/IN3 ;
  wire \NlwInverterSignal_U1/U1/CurrState_Sreg0_FFD2_MC.D2_PT_6/IN1 ;
  wire \NlwInverterSignal_U1/U1/CurrState_Sreg0_FFD2_MC.D2_PT_6/IN2 ;
  wire \NlwInverterSignal_U1/U1/CurrState_Sreg0_FFD2_MC.D2_PT_6/IN4 ;
  wire \NlwInverterSignal_U1/U1/CurrState_Sreg0_FFD2_MC.D2_PT_7/IN1 ;
  wire \NlwInverterSignal_U1/U1/CurrState_Sreg0_FFD2_MC.D2_PT_7/IN2 ;
  wire \NlwInverterSignal_U1/U1/CurrState_Sreg0_FFD2_MC.D2_PT_7/IN3 ;
  wire \NlwInverterSignal_U1/U1/CurrState_Sreg0_FFD2_MC.D2_PT_7/IN5 ;
  wire \NlwInverterSignal_U1/U1/CurrState_Sreg0_FFD4_MC.D1/IN1 ;
  wire \NlwInverterSignal_U1/U1/CurrState_Sreg0_FFD4_MC.D1/IN3 ;
  wire \NlwInverterSignal_U1/U1/CurrState_Sreg0_FFD4_MC.D1/IN4 ;
  wire \NlwInverterSignal_U1/U1/CurrState_Sreg0_FFD4_MC.D1/IN5 ;
  wire \NlwInverterSignal_U1/U1/CurrState_Sreg0_FFD4_MC.D1/IN6 ;
  wire \NlwInverterSignal_U1/Channel0<0>_MC.D2_PT_0/IN0 ;
  wire \NlwInverterSignal_U1/Channel0<0>_MC.D2_PT_1/IN1 ;
  wire \NlwInverterSignal_U1/Channel0<0>_MC.D2_PT_1/IN4 ;
  wire \NlwInverterSignal_U1/Channel0<0>_MC.D2_PT_1/IN5 ;
  wire \NlwInverterSignal_U1/Channel0<0>_MC.D2_PT_2/IN1 ;
  wire \NlwInverterSignal_U1/Channel0<0>_MC.D2_PT_2/IN2 ;
  wire \NlwInverterSignal_U1/Channel0<0>_MC.D2_PT_2/IN4 ;
  wire \NlwInverterSignal_U1/Channel0<1>_MC.D2_PT_0/IN0 ;
  wire \NlwInverterSignal_U1/Channel0<1>_MC.D2_PT_1/IN1 ;
  wire \NlwInverterSignal_N_PZ_964_MC.D2_PT_0/IN1 ;
  wire \NlwInverterSignal_N_PZ_964_MC.D2_PT_0/IN3 ;
  wire \NlwInverterSignal_N_PZ_964_MC.D2_PT_0/IN5 ;
  wire \NlwInverterSignal_N_PZ_964_MC.D2_PT_1/IN1 ;
  wire \NlwInverterSignal_N_PZ_964_MC.D2_PT_1/IN2 ;
  wire \NlwInverterSignal_N_PZ_964_MC.D2_PT_1/IN5 ;
  wire \NlwInverterSignal_N_PZ_964_MC.D2_PT_1/IN6 ;
  wire \NlwInverterSignal_N_PZ_968_MC.D2_PT_0/IN1 ;
  wire \NlwInverterSignal_N_PZ_968_MC.D2_PT_0/IN5 ;
  wire \NlwInverterSignal_N_PZ_968_MC.D2_PT_0/IN6 ;
  wire \NlwInverterSignal_N_PZ_968_MC.D2_PT_1/IN1 ;
  wire \NlwInverterSignal_N_PZ_968_MC.D2_PT_1/IN2 ;
  wire \NlwInverterSignal_N_PZ_968_MC.D2_PT_1/IN3 ;
  wire \NlwInverterSignal_N_PZ_968_MC.D2_PT_1/IN5 ;
  wire \NlwInverterSignal_U1/Channel0<2>_MC.D2_PT_0/IN0 ;
  wire \NlwInverterSignal_U1/Channel0<2>_MC.D2_PT_1/IN1 ;
  wire \NlwInverterSignal_U1/Channel0<2>_MC.D2_PT_1/IN2 ;
  wire \NlwInverterSignal_U1/Channel0<3>_MC.D2_PT_0/IN0 ;
  wire \NlwInverterSignal_U1/Channel0<3>_MC.D2_PT_1/IN1 ;
  wire \NlwInverterSignal_U1/Channel0<3>_MC.D2_PT_1/IN2 ;
  wire \NlwInverterSignal_U1/Channel0<3>_MC.D2_PT_1/IN3 ;
  wire \NlwInverterSignal_U1/Channel0<4>_MC.D1/IN0 ;
  wire \NlwInverterSignal_U1/Channel0<4>_MC.D2_PT_0/IN0 ;
  wire \NlwInverterSignal_U1/Channel0<4>_MC.D2_PT_1/IN0 ;
  wire \NlwInverterSignal_U1/Channel0<4>_MC.D2_PT_1/IN1 ;
  wire \NlwInverterSignal_U1/Channel0<4>_MC.D2_PT_2/IN2 ;
  wire \NlwInverterSignal_U1/Channel0<4>_MC.D2_PT_3/IN6 ;
  wire \NlwInverterSignal_U1/Channel0<4>_MC.D2_PT_4/IN0 ;
  wire \NlwInverterSignal_U1/Channel0<4>_MC.D2_PT_4/IN2 ;
  wire \NlwInverterSignal_U1/Channel0<4>_MC.D2_PT_4/IN3 ;
  wire \NlwInverterSignal_U1/Channel0<4>_MC.D2_PT_4/IN4 ;
  wire \NlwInverterSignal_U1/Channel0<4>_MC.D2_PT_4/IN5 ;
  wire \NlwInverterSignal_U1/Channel0<4>_MC.D2_PT_4/IN6 ;
  wire \NlwInverterSignal_U1/Channel0<4>_MC.D2_PT_5/IN1 ;
  wire \NlwInverterSignal_U1/Channel0<4>_MC.D2_PT_5/IN3 ;
  wire \NlwInverterSignal_U1/Channel0<4>_MC.D2_PT_5/IN7 ;
  wire \NlwInverterSignal_DCOR0CNTLOWr_MC.D1/IN1 ;
  wire \NlwInverterSignal_DCOR0CNTLOWr_MC.D1/IN2 ;
  wire \NlwInverterSignal_DCOR0CNTLOWr_MC.D1/IN3 ;
  wire \NlwInverterSignal_DCOR0CNTLOWr_MC.D1/IN4 ;
  wire \NlwInverterSignal_DCOR0CNTLOWr_MC.D1/IN5 ;
  wire \NlwInverterSignal_DCOR0CNTLOWr_MC.D1/IN6 ;
  wire \NlwInverterSignal_DCOR0CNTLOWr_MC.D1/IN7 ;
  wire \NlwInverterSignal_DCOR0CNTLOWr_MC.D1/IN8 ;
  wire \NlwInverterSignal_U1/U3/holdingreg1<5>_MC.D2_PT_1/IN1 ;
  wire \NlwInverterSignal_U1/Channel1<5>_MC.D2_PT_0/IN1 ;
  wire \NlwInverterSignal_U1/Channel1<5>_MC.D2_PT_1/IN1 ;
  wire \NlwInverterSignal_U1/Channel1<5>_MC.D2_PT_1/IN3 ;
  wire \NlwInverterSignal_U1/Channel1<5>_MC.D2_PT_1/IN4 ;
  wire \NlwInverterSignal_U1/Channel1<5>_MC.D2_PT_2/IN1 ;
  wire \NlwInverterSignal_U1/Channel1<5>_MC.D2_PT_2/IN3 ;
  wire \NlwInverterSignal_U1/Channel1<5>_MC.D2_PT_2/IN5 ;
  wire \NlwInverterSignal_N_PZ_929_MC.D1/IN1 ;
  wire \NlwInverterSignal_U1/Zero1_MC.D2_PT_0/IN0 ;
  wire \NlwInverterSignal_U1/Zero1_MC.D2_PT_3/IN1 ;
  wire \NlwInverterSignal_U1/Zero1_MC.D2_PT_3/IN2 ;
  wire \NlwInverterSignal_U1/Zero1_MC.D2_PT_3/IN3 ;
  wire \NlwInverterSignal_U1/Zero1_MC.D2_PT_3/IN7 ;
  wire \NlwInverterSignal_U1/Zero1_MC.D2_PT_4/IN1 ;
  wire \NlwInverterSignal_U1/Zero1_MC.D2_PT_4/IN2 ;
  wire \NlwInverterSignal_U1/Zero1_MC.D2_PT_4/IN3 ;
  wire \NlwInverterSignal_U1/Zero1_MC.D2_PT_4/IN4 ;
  wire \NlwInverterSignal_U1/Zero1_MC.D2_PT_4/IN6 ;
  wire \NlwInverterSignal_NET2493_MC.D2_PT_0/IN0 ;
  wire \NlwInverterSignal_NET2493_MC.D2_PT_1/IN2 ;
  wire \NlwInverterSignal_NET2493_MC.D2_PT_2/IN1 ;
  wire \NlwInverterSignal_NET2493_MC.D2_PT_2/IN2 ;
  wire \NlwInverterSignal_NET2493_MC.D2_PT_2/IN3 ;
  wire \NlwInverterSignal_NET2493_MC.D2_PT_2/IN7 ;
  wire \NlwInverterSignal_NET2493_MC.D2_PT_3/IN1 ;
  wire \NlwInverterSignal_NET2493_MC.D2_PT_3/IN2 ;
  wire \NlwInverterSignal_NET2493_MC.D2_PT_3/IN3 ;
  wire \NlwInverterSignal_NET2493_MC.D2_PT_3/IN4 ;
  wire \NlwInverterSignal_NET2493_MC.D2_PT_3/IN6 ;
  wire \NlwInverterSignal_U1/U4/RF1r_MC.D2_PT_1/IN1 ;
  wire \NlwInverterSignal_U1/U4/E1r_MC.D2_PT_1/IN1 ;
  wire \NlwInverterSignal_U1/U6/CurrState_Sreg0_FFD3_MC.D2_PT_0/IN3 ;
  wire \NlwInverterSignal_U1/U6/CurrState_Sreg0_FFD3_MC.D2_PT_0/IN4 ;
  wire \NlwInverterSignal_U1/U6/CurrState_Sreg0_FFD3_MC.D2_PT_1/IN2 ;
  wire \NlwInverterSignal_U1/U6/CurrState_Sreg0_FFD3_MC.D2_PT_1/IN3 ;
  wire \NlwInverterSignal_U1/U6/CurrState_Sreg0_FFD3_MC.D2_PT_1/IN4 ;
  wire \NlwInverterSignal_U1/U6/CurrState_Sreg0_FFD3_MC.D2_PT_2/IN3 ;
  wire \NlwInverterSignal_U1/U6/CurrState_Sreg0_FFD3_MC.D2_PT_2/IN5 ;
  wire \NlwInverterSignal_U1/U6/CurrState_Sreg0_FFD3_MC.D2_PT_3/IN3 ;
  wire \NlwInverterSignal_U1/U6/CurrState_Sreg0_FFD3_MC.D2_PT_3/IN4 ;
  wire \NlwInverterSignal_U1/U6/CurrState_Sreg0_FFD1_MC.D2_PT_0/IN2 ;
  wire \NlwInverterSignal_U1/U6/CurrState_Sreg0_FFD1_MC.D2_PT_1/IN1 ;
  wire \NlwInverterSignal_U1/U6/CurrState_Sreg0_FFD1_MC.D2_PT_1/IN3 ;
  wire \NlwInverterSignal_U1/U6/CurrState_Sreg0_FFD1_MC.D2_PT_2/IN1 ;
  wire \NlwInverterSignal_U1/U6/CurrState_Sreg0_FFD1_MC.D2_PT_2/IN2 ;
  wire \NlwInverterSignal_U1/U6/CurrState_Sreg0_FFD1_MC.D2_PT_2/IN3 ;
  wire \NlwInverterSignal_U1/U6/CurrState_Sreg0_FFD1_MC.D2_PT_2/IN4 ;
  wire \NlwInverterSignal_U1/U6/CurrState_Sreg0_FFD4_MC.D1/IN2 ;
  wire \NlwInverterSignal_U1/U6/CurrState_Sreg0_FFD4_MC.D1/IN3 ;
  wire \NlwInverterSignal_U1/U6/CurrState_Sreg0_FFD4_MC.D1/IN4 ;
  wire \NlwInverterSignal_U1/U6/CurrState_Sreg0_FFD4_MC.D1/IN5 ;
  wire \NlwInverterSignal_U1/U6/CurrState_Sreg0_FFD4_MC.D1/IN6 ;
  wire \NlwInverterSignal_U1/U6/CurrState_Sreg0_FFD2_MC.D2_PT_0/IN3 ;
  wire \NlwInverterSignal_U1/U6/CurrState_Sreg0_FFD2_MC.D2_PT_1/IN3 ;
  wire \NlwInverterSignal_U1/U6/CurrState_Sreg0_FFD2_MC.D2_PT_1/IN4 ;
  wire \NlwInverterSignal_U1/U6/CurrState_Sreg0_FFD2_MC.D2_PT_1/IN5 ;
  wire \NlwInverterSignal_U1/U6/CurrState_Sreg0_FFD2_MC.D2_PT_2/IN3 ;
  wire \NlwInverterSignal_U1/U6/CurrState_Sreg0_FFD2_MC.D2_PT_2/IN4 ;
  wire \NlwInverterSignal_U1/U6/CurrState_Sreg0_FFD2_MC.D2_PT_3/IN1 ;
  wire \NlwInverterSignal_U1/U6/CurrState_Sreg0_FFD2_MC.D2_PT_3/IN3 ;
  wire \NlwInverterSignal_U1/U6/CurrState_Sreg0_FFD2_MC.D2_PT_3/IN5 ;
  wire \NlwInverterSignal_U1/U6/CurrState_Sreg0_FFD2_MC.D2_PT_4/IN1 ;
  wire \NlwInverterSignal_U1/U6/CurrState_Sreg0_FFD2_MC.D2_PT_4/IN3 ;
  wire \NlwInverterSignal_U1/U6/CurrState_Sreg0_FFD2_MC.D2_PT_4/IN4 ;
  wire \NlwInverterSignal_U1/U6/CurrState_Sreg0_FFD2_MC.D2_PT_5/IN1 ;
  wire \NlwInverterSignal_U1/U6/CurrState_Sreg0_FFD2_MC.D2_PT_5/IN3 ;
  wire \NlwInverterSignal_U1/U6/CurrState_Sreg0_FFD2_MC.D2_PT_6/IN1 ;
  wire \NlwInverterSignal_U1/U6/CurrState_Sreg0_FFD2_MC.D2_PT_6/IN3 ;
  wire \NlwInverterSignal_U1/U6/CurrState_Sreg0_FFD2_MC.D2_PT_6/IN4 ;
  wire \NlwInverterSignal_U1/U6/CurrState_Sreg0_FFD2_MC.D2_PT_6/IN5 ;
  wire \NlwInverterSignal_U1/U6/CurrState_Sreg0_FFD2_MC.D2_PT_7/IN3 ;
  wire \NlwInverterSignal_U1/U6/CurrState_Sreg0_FFD2_MC.D2_PT_7/IN5 ;
  wire \NlwInverterSignal_U1/U5/location_Maddsub__n0000__n0067<0>_MC.D2_PT_1/IN0 ;
  wire \NlwInverterSignal_U1/U5/location_Maddsub__n0000__n0067<0>_MC.D2_PT_1/IN1 ;
  wire \NlwInverterSignal_U1/U5/location_Maddsub__n0000__n0067<0>_MC.D2_PT_1/IN2 ;
  wire \NlwInverterSignal_U1/U5/location_Maddsub__n0000__n0067<0>_MC.D2_PT_1/IN3 ;
  wire \NlwInverterSignal_U1/U5/location_Maddsub__n0000__n0067<0>_MC.D2_PT_1/IN4 ;
  wire \NlwInverterSignal_U1/U5/location_Maddsub__n0000__n0067<0>_MC.D2_PT_1/IN5 ;
  wire \NlwInverterSignal_N_PZ_944_MC.D2_PT_0/IN1 ;
  wire \NlwInverterSignal_N_PZ_944_MC.D2_PT_0/IN2 ;
  wire \NlwInverterSignal_N_PZ_944_MC.D2_PT_1/IN1 ;
  wire \NlwInverterSignal_N_PZ_944_MC.D2_PT_1/IN2 ;
  wire \NlwInverterSignal_U1/NET3720_MC.D2_PT_1/IN1 ;
  wire \NlwInverterSignal_U1/Channel1<0>_MC.D2_PT_0/IN0 ;
  wire \NlwInverterSignal_U1/Channel1<0>_MC.D2_PT_1/IN1 ;
  wire \NlwInverterSignal_U1/Channel1<0>_MC.D2_PT_1/IN3 ;
  wire \NlwInverterSignal_N_PZ_1092_MC.D2_PT_0/IN1 ;
  wire \NlwInverterSignal_N_PZ_1092_MC.D2_PT_1/IN0 ;
  wire \NlwInverterSignal_U1/Channel1<1>_MC.D2_PT_0/IN0 ;
  wire \NlwInverterSignal_U1/Channel1<1>_MC.D2_PT_1/IN1 ;
  wire \NlwInverterSignal_U1/Channel1<1>_MC.D2_PT_1/IN3 ;
  wire \NlwInverterSignal_U1/Channel1<1>_MC.D2_PT_2/IN1 ;
  wire \NlwInverterSignal_U1/Channel1<1>_MC.D2_PT_2/IN3 ;
  wire \NlwInverterSignal_U1/Channel1<1>_MC.D2_PT_2/IN4 ;
  wire \NlwInverterSignal_U1/Channel1<1>_MC.D2_PT_2/IN6 ;
  wire \NlwInverterSignal_N_PZ_921_MC.D2_PT_0/IN1 ;
  wire \NlwInverterSignal_N_PZ_921_MC.D2_PT_0/IN2 ;
  wire \NlwInverterSignal_N_PZ_921_MC.D2_PT_1/IN0 ;
  wire \NlwInverterSignal_U1/Channel1<2>_MC.D2_PT_0/IN0 ;
  wire \NlwInverterSignal_U1/Channel1<2>_MC.D2_PT_1/IN1 ;
  wire \NlwInverterSignal_U1/Channel1<2>_MC.D2_PT_1/IN3 ;
  wire \NlwInverterSignal_U1/Channel1<2>_MC.D2_PT_2/IN1 ;
  wire \NlwInverterSignal_U1/Channel1<2>_MC.D2_PT_2/IN3 ;
  wire \NlwInverterSignal_U1/Channel1<2>_MC.D2_PT_2/IN4 ;
  wire \NlwInverterSignal_U1/Channel1<2>_MC.D2_PT_2/IN6 ;
  wire \NlwInverterSignal_U1/Channel1<2>_MC.D2_PT_2/IN7 ;
  wire \NlwInverterSignal_U1/Channel1<3>_MC.D2_PT_0/IN0 ;
  wire \NlwInverterSignal_U1/Channel1<3>_MC.D2_PT_1/IN1 ;
  wire \NlwInverterSignal_U1/Channel1<3>_MC.D2_PT_1/IN3 ;
  wire \NlwInverterSignal_U1/Channel1<3>_MC.D2_PT_2/IN1 ;
  wire \NlwInverterSignal_U1/Channel1<3>_MC.D2_PT_2/IN3 ;
  wire \NlwInverterSignal_U1/Channel1<3>_MC.D2_PT_2/IN4 ;
  wire \NlwInverterSignal_U1/Channel1<3>_MC.D2_PT_2/IN6 ;
  wire \NlwInverterSignal_U1/Channel1<3>_MC.D2_PT_2/IN7 ;
  wire \NlwInverterSignal_U1/Channel1<3>_MC.D2_PT_2/IN8 ;
  wire \NlwInverterSignal_U1/Channel1<4>_MC.D2_PT_0/IN0 ;
  wire \NlwInverterSignal_U1/Channel1<4>_MC.D2_PT_1/IN1 ;
  wire \NlwInverterSignal_U1/Channel1<4>_MC.D2_PT_1/IN2 ;
  wire \NlwInverterSignal_U1/Channel1<4>_MC.D2_PT_1/IN4 ;
  wire \NlwInverterSignal_U1/Channel1<4>_MC.D2_PT_2/IN1 ;
  wire \NlwInverterSignal_U1/Channel1<4>_MC.D2_PT_2/IN2 ;
  wire \NlwInverterSignal_U1/Channel1<4>_MC.D2_PT_2/IN4 ;
  wire \NlwInverterSignal_U1/Channel1<4>_MC.D2_PT_3/IN1 ;
  wire \NlwInverterSignal_U1/Channel1<4>_MC.D2_PT_3/IN2 ;
  wire \NlwInverterSignal_U1/Channel1<4>_MC.D2_PT_3/IN4 ;
  wire \NlwInverterSignal_U1/Channel1<4>_MC.D2_PT_4/IN1 ;
  wire \NlwInverterSignal_U1/Channel1<4>_MC.D2_PT_4/IN2 ;
  wire \NlwInverterSignal_U1/Channel1<4>_MC.D2_PT_5/IN1 ;
  wire \NlwInverterSignal_U1/Channel1<4>_MC.D2_PT_5/IN3 ;
  wire \NlwInverterSignal_U1/Channel1<4>_MC.D2_PT_5/IN5 ;
  wire \NlwInverterSignal_U1/Channel1<4>_MC.D2_PT_5/IN7 ;
  wire \NlwInverterSignal_U1/Channel1<4>_MC.D2_PT_6/IN1 ;
  wire \NlwInverterSignal_U1/Channel1<4>_MC.D2_PT_6/IN2 ;
  wire \NlwInverterSignal_U1/Channel1<4>_MC.D2_PT_6/IN4 ;
  wire \NlwInverterSignal_U1/Channel1<4>_MC.D2_PT_6/IN5 ;
  wire \NlwInverterSignal_U1/Channel1<4>_MC.D2_PT_6/IN6 ;
  wire \NlwInverterSignal_U1/Channel1<4>_MC.D2_PT_6/IN7 ;
  wire \NlwInverterSignal_U1/Channel1<4>_MC.D2_PT_7/IN1 ;
  wire \NlwInverterSignal_U1/Channel1<4>_MC.D2_PT_7/IN3 ;
  wire \NlwInverterSignal_U1/Channel1<4>_MC.D2_PT_7/IN10 ;
  wire \NlwInverterSignal_DCOR1CNTLOWr_MC.D1/IN1 ;
  wire \NlwInverterSignal_DCOR1CNTLOWr_MC.D1/IN2 ;
  wire \NlwInverterSignal_DCOR1CNTLOWr_MC.D1/IN3 ;
  wire \NlwInverterSignal_DCOR1CNTLOWr_MC.D1/IN4 ;
  wire \NlwInverterSignal_DCOR1CNTLOWr_MC.D1/IN5 ;
  wire \NlwInverterSignal_DCOR1CNTLOWr_MC.D1/IN6 ;
  wire \NlwInverterSignal_DCOR1CNTLOWr_MC.D1/IN7 ;
  wire \NlwInverterSignal_U1/U3/holdingreg0<13>_MC.D2_PT_1/IN1 ;
  wire \NlwInverterSignal_U1/Channel0<13>_MC.D2_PT_0/IN0 ;
  wire \NlwInverterSignal_U1/Channel0<13>_MC.D2_PT_1/IN1 ;
  wire \NlwInverterSignal_U1/Channel0<13>_MC.D2_PT_1/IN2 ;
  wire \NlwInverterSignal_U1/Channel0<13>_MC.D2_PT_1/IN4 ;
  wire \NlwInverterSignal_U1/Channel0<13>_MC.D2_PT_1/IN5 ;
  wire \NlwInverterSignal_U1/Channel0<13>_MC.D2_PT_2/IN3 ;
  wire \NlwInverterSignal_U1/Channel0<10>_MC.D2_PT_0/IN0 ;
  wire \NlwInverterSignal_U1/Channel0<10>_MC.D2_PT_1/IN1 ;
  wire \NlwInverterSignal_U1/Channel0<10>_MC.D2_PT_2/IN2 ;
  wire \NlwInverterSignal_U1/Channel0<9>_MC.D2_PT_0/IN0 ;
  wire \NlwInverterSignal_U1/Channel0<9>_MC.D2_PT_2/IN1 ;
  wire \NlwInverterSignal_U1/U2/location_Maddsub__n0000__n0075<0>_MC.D2_PT_0/IN1 ;
  wire \NlwInverterSignal_U1/U2/location_Maddsub__n0000__n0075<0>_MC.D2_PT_1/IN0 ;
  wire \NlwInverterSignal_U1/U2/location_Maddsub__n0000__n0075<0>_MC.D2_PT_1/IN2 ;
  wire \NlwInverterSignal_U1/U2/location_Maddsub__n0000__n0075<0>_MC.D2_PT_1/IN3 ;
  wire \NlwInverterSignal_U1/U2/location_Maddsub__n0000__n0075<0>_MC.D2_PT_1/IN4 ;
  wire \NlwInverterSignal_U1/U2/location_Maddsub__n0000__n0075<0>_MC.D2_PT_1/IN5 ;
  wire \NlwInverterSignal_U1/Channel0<6>_MC.D2_PT_0/IN0 ;
  wire \NlwInverterSignal_U1/Channel0<6>_MC.D2_PT_1/IN1 ;
  wire \NlwInverterSignal_U1/Channel0<6>_MC.D2_PT_2/IN0 ;
  wire \NlwInverterSignal_U1/Channel0<7>_MC.D2_PT_0/IN0 ;
  wire \NlwInverterSignal_U1/Channel0<7>_MC.D2_PT_1/IN1 ;
  wire \NlwInverterSignal_U1/Channel0<7>_MC.D2_PT_2/IN0 ;
  wire \NlwInverterSignal_U1/Channel0<7>_MC.D2_PT_2/IN3 ;
  wire \NlwInverterSignal_U1/Channel0<8>_MC.D1/IN1 ;
  wire \NlwInverterSignal_U1/Channel0<8>_MC.D2_PT_0/IN0 ;
  wire \NlwInverterSignal_U1/Channel0<8>_MC.D2_PT_0/IN1 ;
  wire \NlwInverterSignal_U1/Channel0<8>_MC.D2_PT_1/IN0 ;
  wire \NlwInverterSignal_U1/Channel0<8>_MC.D2_PT_2/IN2 ;
  wire \NlwInverterSignal_U1/Channel0<8>_MC.D2_PT_3/IN1 ;
  wire \NlwInverterSignal_U1/Channel0<8>_MC.D2_PT_3/IN6 ;
  wire \NlwInverterSignal_U1/Channel0<8>_MC.D2_PT_4/IN0 ;
  wire \NlwInverterSignal_U1/Channel0<8>_MC.D2_PT_4/IN3 ;
  wire \NlwInverterSignal_U1/Channel0<8>_MC.D2_PT_4/IN4 ;
  wire \NlwInverterSignal_U1/Channel0<8>_MC.D2_PT_4/IN5 ;
  wire \NlwInverterSignal_U1/Channel0<8>_MC.D2_PT_4/IN6 ;
  wire \NlwInverterSignal_U1/Channel0<8>_MC.D2_PT_5/IN2 ;
  wire \NlwInverterSignal_U1/Channel0<8>_MC.D2_PT_5/IN4 ;
  wire \NlwInverterSignal_U1/Channel0<8>_MC.D2_PT_5/IN5 ;
  wire \NlwInverterSignal_U1/Channel0<8>_MC.D2_PT_5/IN7 ;
  wire \NlwInverterSignal_U1/Channel0<11>_MC.D2_PT_0/IN0 ;
  wire \NlwInverterSignal_U1/Channel0<11>_MC.D2_PT_1/IN1 ;
  wire \NlwInverterSignal_U1/Channel0<11>_MC.D2_PT_1/IN2 ;
  wire \NlwInverterSignal_U1/Channel0<11>_MC.D2_PT_2/IN3 ;
  wire \NlwInverterSignal_U1/Channel0<12>_MC.D2_PT_0/IN0 ;
  wire \NlwInverterSignal_U1/Channel0<12>_MC.D2_PT_1/IN1 ;
  wire \NlwInverterSignal_U1/Channel0<12>_MC.D2_PT_1/IN2 ;
  wire \NlwInverterSignal_U1/Channel0<12>_MC.D2_PT_1/IN4 ;
  wire \NlwInverterSignal_U1/Channel0<12>_MC.D2_PT_2/IN3 ;
  wire \NlwInverterSignal_DCOR0CNTHIGHr_MC.D1/IN1 ;
  wire \NlwInverterSignal_DCOR0CNTHIGHr_MC.D1/IN3 ;
  wire \NlwInverterSignal_DCOR0CNTHIGHr_MC.D1/IN4 ;
  wire \NlwInverterSignal_DCOR0CNTHIGHr_MC.D1/IN5 ;
  wire \NlwInverterSignal_DCOR0CNTHIGHr_MC.D1/IN6 ;
  wire \NlwInverterSignal_DCOR0CNTHIGHr_MC.D1/IN7 ;
  wire \NlwInverterSignal_DCOR0CNTHIGHr_MC.D1/IN8 ;
  wire \NlwInverterSignal_U1/U3/holdingreg1<13>_MC.D2_PT_1/IN1 ;
  wire \NlwInverterSignal_U1/Channel1<13>_MC.D2_PT_0/IN0 ;
  wire \NlwInverterSignal_U1/Channel1<13>_MC.D2_PT_1/IN1 ;
  wire \NlwInverterSignal_U1/Channel1<13>_MC.D2_PT_1/IN3 ;
  wire \NlwInverterSignal_U1/Channel1<13>_MC.D2_PT_1/IN7 ;
  wire \NlwInverterSignal_U1/Channel1<13>_MC.D2_PT_2/IN1 ;
  wire \NlwInverterSignal_U1/Channel1<13>_MC.D2_PT_2/IN3 ;
  wire \NlwInverterSignal_U1/Channel1<13>_MC.D2_PT_2/IN4 ;
  wire \NlwInverterSignal_U1/Channel1<13>_MC.D2_PT_2/IN6 ;
  wire \NlwInverterSignal_U1/Channel1<13>_MC.D2_PT_2/IN7 ;
  wire \NlwInverterSignal_U1/Channel1<13>_MC.D2_PT_2/IN9 ;
  wire \NlwInverterSignal_U1/Channel1<13>_MC.D2_PT_2/IN10 ;
  wire \NlwInverterSignal_U1/Channel1<10>_MC.D2_PT_0/IN0 ;
  wire \NlwInverterSignal_U1/Channel1<10>_MC.D2_PT_1/IN1 ;
  wire \NlwInverterSignal_U1/Channel1<10>_MC.D2_PT_1/IN3 ;
  wire \NlwInverterSignal_U1/Channel1<10>_MC.D2_PT_1/IN6 ;
  wire \NlwInverterSignal_U1/Channel1<10>_MC.D2_PT_2/IN1 ;
  wire \NlwInverterSignal_U1/Channel1<10>_MC.D2_PT_2/IN3 ;
  wire \NlwInverterSignal_U1/Channel1<10>_MC.D2_PT_2/IN4 ;
  wire \NlwInverterSignal_U1/Channel1<10>_MC.D2_PT_2/IN6 ;
  wire \NlwInverterSignal_U1/Channel1<9>_MC.D2_PT_0/IN0 ;
  wire \NlwInverterSignal_U1/Channel1<9>_MC.D2_PT_1/IN1 ;
  wire \NlwInverterSignal_U1/Channel1<9>_MC.D2_PT_1/IN3 ;
  wire \NlwInverterSignal_U1/Channel1<9>_MC.D2_PT_1/IN5 ;
  wire \NlwInverterSignal_U1/Channel1<9>_MC.D2_PT_2/IN1 ;
  wire \NlwInverterSignal_U1/Channel1<9>_MC.D2_PT_2/IN3 ;
  wire \NlwInverterSignal_U1/Channel1<9>_MC.D2_PT_2/IN4 ;
  wire \NlwInverterSignal_U1/U5/location_Maddsub__n0000__n0075<0>_MC.D2_PT_0/IN1 ;
  wire \NlwInverterSignal_U1/U5/location_Maddsub__n0000__n0075<0>_MC.D2_PT_1/IN0 ;
  wire \NlwInverterSignal_U1/U5/location_Maddsub__n0000__n0075<0>_MC.D2_PT_1/IN2 ;
  wire \NlwInverterSignal_U1/U5/location_Maddsub__n0000__n0075<0>_MC.D2_PT_1/IN3 ;
  wire \NlwInverterSignal_U1/U5/location_Maddsub__n0000__n0075<0>_MC.D2_PT_1/IN4 ;
  wire \NlwInverterSignal_U1/U5/location_Maddsub__n0000__n0075<0>_MC.D2_PT_1/IN5 ;
  wire \NlwInverterSignal_U1/Channel1<6>_MC.D2_PT_0/IN0 ;
  wire \NlwInverterSignal_U1/Channel1<6>_MC.D2_PT_1/IN2 ;
  wire \NlwInverterSignal_U1/Channel1<6>_MC.D2_PT_1/IN4 ;
  wire \NlwInverterSignal_U1/Channel1<6>_MC.D2_PT_1/IN5 ;
  wire \NlwInverterSignal_U1/Channel1<6>_MC.D2_PT_2/IN1 ;
  wire \NlwInverterSignal_U1/Channel1<6>_MC.D2_PT_2/IN2 ;
  wire \NlwInverterSignal_U1/Channel1<6>_MC.D2_PT_2/IN4 ;
  wire \NlwInverterSignal_U1/Channel1<6>_MC.D2_PT_2/IN6 ;
  wire \NlwInverterSignal_U1/Channel1<7>_MC.D2_PT_0/IN0 ;
  wire \NlwInverterSignal_U1/Channel1<7>_MC.D2_PT_1/IN2 ;
  wire \NlwInverterSignal_U1/Channel1<7>_MC.D2_PT_1/IN4 ;
  wire \NlwInverterSignal_U1/Channel1<7>_MC.D2_PT_1/IN5 ;
  wire \NlwInverterSignal_U1/Channel1<7>_MC.D2_PT_2/IN1 ;
  wire \NlwInverterSignal_U1/Channel1<7>_MC.D2_PT_2/IN2 ;
  wire \NlwInverterSignal_U1/Channel1<7>_MC.D2_PT_2/IN4 ;
  wire \NlwInverterSignal_U1/Channel1<7>_MC.D2_PT_2/IN6 ;
  wire \NlwInverterSignal_U1/Channel1<7>_MC.D2_PT_2/IN8 ;
  wire \NlwInverterSignal_U1/Channel1<8>_MC.D2_PT_0/IN0 ;
  wire \NlwInverterSignal_U1/Channel1<8>_MC.D2_PT_1/IN0 ;
  wire \NlwInverterSignal_U1/Channel1<8>_MC.D2_PT_1/IN2 ;
  wire \NlwInverterSignal_U1/Channel1<8>_MC.D2_PT_1/IN4 ;
  wire \NlwInverterSignal_U1/Channel1<8>_MC.D2_PT_2/IN1 ;
  wire \NlwInverterSignal_U1/Channel1<8>_MC.D2_PT_2/IN4 ;
  wire \NlwInverterSignal_U1/Channel1<8>_MC.D2_PT_3/IN1 ;
  wire \NlwInverterSignal_U1/Channel1<8>_MC.D2_PT_3/IN3 ;
  wire \NlwInverterSignal_U1/Channel1<8>_MC.D2_PT_3/IN4 ;
  wire \NlwInverterSignal_U1/Channel1<8>_MC.D2_PT_4/IN1 ;
  wire \NlwInverterSignal_U1/Channel1<8>_MC.D2_PT_4/IN3 ;
  wire \NlwInverterSignal_U1/Channel1<8>_MC.D2_PT_5/IN1 ;
  wire \NlwInverterSignal_U1/Channel1<8>_MC.D2_PT_5/IN3 ;
  wire \NlwInverterSignal_U1/Channel1<8>_MC.D2_PT_5/IN4 ;
  wire \NlwInverterSignal_U1/Channel1<8>_MC.D2_PT_5/IN7 ;
  wire \NlwInverterSignal_U1/Channel1<8>_MC.D2_PT_6/IN0 ;
  wire \NlwInverterSignal_U1/Channel1<8>_MC.D2_PT_6/IN2 ;
  wire \NlwInverterSignal_U1/Channel1<8>_MC.D2_PT_6/IN5 ;
  wire \NlwInverterSignal_U1/Channel1<8>_MC.D2_PT_6/IN6 ;
  wire \NlwInverterSignal_U1/Channel1<8>_MC.D2_PT_6/IN7 ;
  wire \NlwInverterSignal_U1/Channel1<8>_MC.D2_PT_7/IN2 ;
  wire \NlwInverterSignal_U1/Channel1<8>_MC.D2_PT_7/IN4 ;
  wire \NlwInverterSignal_U1/Channel1<8>_MC.D2_PT_7/IN5 ;
  wire \NlwInverterSignal_U1/Channel1<8>_MC.D2_PT_7/IN10 ;
  wire \NlwInverterSignal_U1/Channel1<11>_MC.D2_PT_0/IN0 ;
  wire \NlwInverterSignal_U1/Channel1<11>_MC.D2_PT_1/IN1 ;
  wire \NlwInverterSignal_U1/Channel1<11>_MC.D2_PT_1/IN3 ;
  wire \NlwInverterSignal_U1/Channel1<11>_MC.D2_PT_1/IN7 ;
  wire \NlwInverterSignal_U1/Channel1<11>_MC.D2_PT_2/IN1 ;
  wire \NlwInverterSignal_U1/Channel1<11>_MC.D2_PT_2/IN3 ;
  wire \NlwInverterSignal_U1/Channel1<11>_MC.D2_PT_2/IN4 ;
  wire \NlwInverterSignal_U1/Channel1<11>_MC.D2_PT_2/IN6 ;
  wire \NlwInverterSignal_U1/Channel1<11>_MC.D2_PT_2/IN7 ;
  wire \NlwInverterSignal_U1/Channel1<12>_MC.D2_PT_0/IN0 ;
  wire \NlwInverterSignal_U1/Channel1<12>_MC.D2_PT_1/IN1 ;
  wire \NlwInverterSignal_U1/Channel1<12>_MC.D2_PT_1/IN3 ;
  wire \NlwInverterSignal_U1/Channel1<12>_MC.D2_PT_1/IN7 ;
  wire \NlwInverterSignal_U1/Channel1<12>_MC.D2_PT_2/IN1 ;
  wire \NlwInverterSignal_U1/Channel1<12>_MC.D2_PT_2/IN3 ;
  wire \NlwInverterSignal_U1/Channel1<12>_MC.D2_PT_2/IN4 ;
  wire \NlwInverterSignal_U1/Channel1<12>_MC.D2_PT_2/IN6 ;
  wire \NlwInverterSignal_U1/Channel1<12>_MC.D2_PT_2/IN7 ;
  wire \NlwInverterSignal_U1/Channel1<12>_MC.D2_PT_2/IN9 ;
  wire \NlwInverterSignal_N_PZ_961_MC.D1/IN0 ;
  wire \NlwInverterSignal_N_PZ_961_MC.D1/IN1 ;
  wire \NlwInverterSignal_N_PZ_961_MC.D1/IN2 ;
  wire \NlwInverterSignal_N_PZ_961_MC.D1/IN3 ;
  wire \NlwInverterSignal_DCOR1CNTHIGHr_MC.D1/IN1 ;
  wire \NlwInverterSignal_DCOR1CNTHIGHr_MC.D1/IN3 ;
  wire \NlwInverterSignal_DCOR1CNTHIGHr_MC.D1/IN4 ;
  wire \NlwInverterSignal_DCOR1CNTHIGHr_MC.D1/IN5 ;
  wire \NlwInverterSignal_DCOR1CNTHIGHr_MC.D1/IN6 ;
  wire \NlwInverterSignal_DCOR1CNTHIGHr_MC.D1/IN7 ;
  wire \NlwInverterSignal_outDATA<5>\$WA6.UIM_MC.D2_PT_1/IN0 ;
  wire \NlwInverterSignal_outDATA<5>\$WA6.UIM_MC.D2_PT_2/IN0 ;
  wire \NlwInverterSignal_outDATA<5>\$WA6.UIM_MC.D2_PT_2/IN1 ;
  wire \NlwInverterSignal_outDATA<5>\$WA6.UIM_MC.D2_PT_3/IN0 ;
  wire \NlwInverterSignal_outDATA<5>\$WA6.UIM_MC.D2_PT_3/IN1 ;
  wire \NlwInverterSignal_outDATA<5>\$WA6.UIM_MC.D2_PT_3/IN2 ;
  wire \NlwInverterSignal_outDATA<5>\$WA6.UIM_MC.D2_PT_4/IN0 ;
  wire \NlwInverterSignal_outDATA<5>\$WA6.UIM_MC.D2_PT_4/IN1 ;
  wire \NlwInverterSignal_outDATA<5>\$WA6.UIM_MC.D2_PT_4/IN2 ;
  wire \NlwInverterSignal_outDATA<5>\$WA6.UIM_MC.D2_PT_4/IN3 ;
  wire \NlwInverterSignal_U1/U4/Latch0r<5>_MC.D2_PT_1/IN2 ;
  wire \NlwInverterSignal_N_PZ_963_MC.D2_PT_0/IN0 ;
  wire \NlwInverterSignal_N_PZ_963_MC.D2_PT_0/IN1 ;
  wire \NlwInverterSignal_N_PZ_963_MC.D2_PT_0/IN2 ;
  wire \NlwInverterSignal_N_PZ_963_MC.D2_PT_0/IN4 ;
  wire \NlwInverterSignal_N_PZ_963_MC.D2_PT_1/IN0 ;
  wire \NlwInverterSignal_N_PZ_963_MC.D2_PT_1/IN1 ;
  wire \NlwInverterSignal_N_PZ_963_MC.D2_PT_1/IN2 ;
  wire \NlwInverterSignal_N_PZ_963_MC.D2_PT_1/IN3 ;
  wire \NlwInverterSignal_N_PZ_963_MC.D2_PT_1/IN5 ;
  wire \NlwInverterSignal_NET2501_MC.D2_PT_1/IN3 ;
  wire \NlwInverterSignal_U1/U4/LatchEdge0r_MC.D2_PT_1/IN1 ;
  wire \NlwInverterSignal_DCOR0THRESLOWr_MC.D1/IN1 ;
  wire \NlwInverterSignal_DCOR0THRESLOWr_MC.D1/IN2 ;
  wire \NlwInverterSignal_DCOR0THRESLOWr_MC.D1/IN3 ;
  wire \NlwInverterSignal_DCOR0THRESLOWr_MC.D1/IN4 ;
  wire \NlwInverterSignal_DCOR0THRESLOWr_MC.D1/IN5 ;
  wire \NlwInverterSignal_DCOR0THRESLOWr_MC.D1/IN6 ;
  wire \NlwInverterSignal_DCOR0THRESLOWr_MC.D1/IN8 ;
  wire \NlwInverterSignal_DCOR0THRESLOWr_MC.D1/IN9 ;
  wire \NlwInverterSignal_DCORIFGr_MC.D1/IN1 ;
  wire \NlwInverterSignal_DCORIFGr_MC.D1/IN3 ;
  wire \NlwInverterSignal_DCORIFGr_MC.D1/IN4 ;
  wire \NlwInverterSignal_DCORIFGr_MC.D1/IN5 ;
  wire \NlwInverterSignal_DCORIFGr_MC.D1/IN6 ;
  wire \NlwInverterSignal_DCORIFGr_MC.D1/IN7 ;
  wire \NlwInverterSignal_DCORIFGr_MC.D1/IN8 ;
  wire \NlwInverterSignal_DCORIFGr_MC.D1/IN9 ;
  wire \NlwInverterSignal_U1/U4/Latch0r<13>_MC.D2_PT_1/IN2 ;
  wire \NlwInverterSignal_DCOR0THRESHIGHr_MC.D1/IN1 ;
  wire \NlwInverterSignal_DCOR0THRESHIGHr_MC.D1/IN3 ;
  wire \NlwInverterSignal_DCOR0THRESHIGHr_MC.D1/IN4 ;
  wire \NlwInverterSignal_DCOR0THRESHIGHr_MC.D1/IN5 ;
  wire \NlwInverterSignal_DCOR0THRESHIGHr_MC.D1/IN6 ;
  wire \NlwInverterSignal_DCOR0THRESHIGHr_MC.D1/IN8 ;
  wire \NlwInverterSignal_DCOR0THRESHIGHr_MC.D1/IN9 ;
  wire \NlwInverterSignal_U1/U4/Latch1r<5>_MC.D2_PT_1/IN2 ;
  wire \NlwInverterSignal_N_PZ_962_MC.D2_PT_0/IN0 ;
  wire \NlwInverterSignal_N_PZ_962_MC.D2_PT_0/IN1 ;
  wire \NlwInverterSignal_N_PZ_962_MC.D2_PT_0/IN2 ;
  wire \NlwInverterSignal_N_PZ_962_MC.D2_PT_0/IN4 ;
  wire \NlwInverterSignal_N_PZ_962_MC.D2_PT_1/IN0 ;
  wire \NlwInverterSignal_N_PZ_962_MC.D2_PT_1/IN1 ;
  wire \NlwInverterSignal_N_PZ_962_MC.D2_PT_1/IN2 ;
  wire \NlwInverterSignal_N_PZ_962_MC.D2_PT_1/IN3 ;
  wire \NlwInverterSignal_N_PZ_962_MC.D2_PT_1/IN5 ;
  wire \NlwInverterSignal_NET2512_MC.D2_PT_1/IN3 ;
  wire \NlwInverterSignal_U1/U4/LatchEdge1r_MC.D2_PT_1/IN1 ;
  wire \NlwInverterSignal_DCOR1THRESLOWr_MC.D1/IN1 ;
  wire \NlwInverterSignal_DCOR1THRESLOWr_MC.D1/IN2 ;
  wire \NlwInverterSignal_DCOR1THRESLOWr_MC.D1/IN3 ;
  wire \NlwInverterSignal_DCOR1THRESLOWr_MC.D1/IN4 ;
  wire \NlwInverterSignal_DCOR1THRESLOWr_MC.D1/IN5 ;
  wire \NlwInverterSignal_DCOR1THRESLOWr_MC.D1/IN6 ;
  wire \NlwInverterSignal_DCOR1THRESLOWr_MC.D1/IN9 ;
  wire \NlwInverterSignal_U1/U4/Latch1r<13>_MC.D2_PT_1/IN2 ;
  wire \NlwInverterSignal_N_PZ_987_MC.D1/IN0 ;
  wire \NlwInverterSignal_N_PZ_987_MC.D1/IN1 ;
  wire \NlwInverterSignal_N_PZ_987_MC.D1/IN2 ;
  wire \NlwInverterSignal_N_PZ_987_MC.D1/IN3 ;
  wire \NlwInverterSignal_N_PZ_987_MC.D1/IN4 ;
  wire \NlwInverterSignal_DCOR1THRESHIGHr_MC.D1/IN1 ;
  wire \NlwInverterSignal_DCOR1THRESHIGHr_MC.D1/IN3 ;
  wire \NlwInverterSignal_DCOR1THRESHIGHr_MC.D1/IN4 ;
  wire \NlwInverterSignal_DCOR1THRESHIGHr_MC.D1/IN5 ;
  wire \NlwInverterSignal_DCOR1THRESHIGHr_MC.D1/IN6 ;
  wire \NlwInverterSignal_DCOR1THRESHIGHr_MC.D1/IN9 ;
  wire \NlwInverterSignal_U2_Enable_AD_MC.D1/IN1 ;
  wire \NlwInverterSignal_U2_Enable_AD_MC.D1/IN2 ;
  wire \NlwInverterSignal_U2_Enable_AD_MC.D1/IN3 ;
  wire \NlwInverterSignal_U2_Enable_AD_MC.D1/IN4 ;
  wire \NlwInverterSignal_U2_Enable_AD_MC.D1/IN5 ;
  wire \NlwInverterSignal_Enc033ctrl_MC.D/IN0 ;
  wire \NlwInverterSignal_Enc033ctrl_MC.D1/IN1 ;
  wire \NlwInverterSignal_U4/ctrlr<2>_MC.D/IN0 ;
  wire \NlwInverterSignal_U4/ctrlr<2>_MC.D2_PT_0/IN1 ;
  wire \NlwInverterSignal_U4/ctrlr<2>_MC.D2_PT_1/IN1 ;
  wire \NlwInverterSignal_U4/ctrlr<2>_MC.D2_PT_2/IN1 ;
  wire \NlwInverterSignal_U4/ctrlr<2>_MC.D2_PT_3/IN1 ;
  wire \NlwInverterSignal_U4/ctrlr<2>_MC.D2_PT_4/IN0 ;
  wire \NlwInverterSignal_U4/ctrlr<2>_MC.D2_PT_4/IN1 ;
  wire \NlwInverterSignal_U4/ctrlr<2>_MC.D2_PT_5/IN0 ;
  wire \NlwInverterSignal_U4/ctrlr<2>_MC.D2_PT_5/IN1 ;
  wire \NlwInverterSignal_DCORENCPWRw_MC.D1/IN0 ;
  wire \NlwInverterSignal_DCORENCPWRw_MC.D1/IN2 ;
  wire \NlwInverterSignal_DCORENCPWRw_MC.D1/IN3 ;
  wire \NlwInverterSignal_DCORENCPWRw_MC.D1/IN4 ;
  wire \NlwInverterSignal_DCORENCPWRw_MC.D1/IN5 ;
  wire \NlwInverterSignal_DCORENCPWRw_MC.D1/IN6 ;
  wire \NlwInverterSignal_U4/ctrlr<3>_MC.D/IN0 ;
  wire \NlwInverterSignal_U4/ctrlr<3>_MC.D2_PT_0/IN1 ;
  wire \NlwInverterSignal_U4/ctrlr<3>_MC.D2_PT_1/IN1 ;
  wire \NlwInverterSignal_U4/ctrlr<3>_MC.D2_PT_2/IN1 ;
  wire \NlwInverterSignal_U4/ctrlr<3>_MC.D2_PT_3/IN1 ;
  wire \NlwInverterSignal_U4/ctrlr<3>_MC.D2_PT_4/IN0 ;
  wire \NlwInverterSignal_U4/ctrlr<3>_MC.D2_PT_4/IN1 ;
  wire \NlwInverterSignal_U4/ctrlr<3>_MC.D2_PT_5/IN0 ;
  wire \NlwInverterSignal_U4/ctrlr<3>_MC.D2_PT_5/IN1 ;
  wire \NlwInverterSignal_Enc05ctrl_MC.D/IN0 ;
  wire \NlwInverterSignal_Enc05ctrl_MC.D1/IN0 ;
  wire \NlwInverterSignal_Enc133ctrl_MC.D/IN0 ;
  wire \NlwInverterSignal_U4/ctrlr<6>_MC.D/IN0 ;
  wire \NlwInverterSignal_U4/ctrlr<6>_MC.D2_PT_0/IN1 ;
  wire \NlwInverterSignal_U4/ctrlr<6>_MC.D2_PT_1/IN1 ;
  wire \NlwInverterSignal_U4/ctrlr<6>_MC.D2_PT_2/IN1 ;
  wire \NlwInverterSignal_U4/ctrlr<6>_MC.D2_PT_3/IN1 ;
  wire \NlwInverterSignal_U4/ctrlr<6>_MC.D2_PT_4/IN0 ;
  wire \NlwInverterSignal_U4/ctrlr<6>_MC.D2_PT_4/IN1 ;
  wire \NlwInverterSignal_U4/ctrlr<6>_MC.D2_PT_5/IN0 ;
  wire \NlwInverterSignal_U4/ctrlr<6>_MC.D2_PT_5/IN1 ;
  wire \NlwInverterSignal_U4/ctrlr<7>_MC.D/IN0 ;
  wire \NlwInverterSignal_U4/ctrlr<7>_MC.D2_PT_0/IN1 ;
  wire \NlwInverterSignal_U4/ctrlr<7>_MC.D2_PT_1/IN1 ;
  wire \NlwInverterSignal_U4/ctrlr<7>_MC.D2_PT_2/IN1 ;
  wire \NlwInverterSignal_U4/ctrlr<7>_MC.D2_PT_3/IN1 ;
  wire \NlwInverterSignal_U4/ctrlr<7>_MC.D2_PT_4/IN0 ;
  wire \NlwInverterSignal_U4/ctrlr<7>_MC.D2_PT_4/IN1 ;
  wire \NlwInverterSignal_U4/ctrlr<7>_MC.D2_PT_5/IN0 ;
  wire \NlwInverterSignal_U4/ctrlr<7>_MC.D2_PT_6/IN1 ;
  wire \NlwInverterSignal_U4/ctrlr<7>_MC.D2_PT_7/IN0 ;
  wire \NlwInverterSignal_U4/ctrlr<7>_MC.D2_PT_7/IN1 ;
  wire \NlwInverterSignal_U4/ctrlr<7>_MC.D2_PT_7/IN2 ;
  wire \NlwInverterSignal_Enc15ctrl_MC.D/IN0 ;
  wire \NlwInverterSignal_Enc15ctrl_MC.D1/IN0 ;
  wire \NlwInverterSignal_DCOROUTw_MC.D1/IN0 ;
  wire \NlwInverterSignal_DCOROUTw_MC.D1/IN3 ;
  wire \NlwInverterSignal_DCOROUTw_MC.D1/IN4 ;
  wire \NlwInverterSignal_DCOROUTw_MC.D1/IN5 ;
  wire \NlwInverterSignal_DCOROUTw_MC.D1/IN6 ;
  wire \NlwInverterSignal_Home033ctrl_MC.D/IN0 ;
  wire \NlwInverterSignal_Home05ctrl_MC.D/IN0 ;
  wire \NlwInverterSignal_Home133ctrl_MC.D/IN0 ;
  wire \NlwInverterSignal_Home15ctrl_MC.D/IN0 ;
  wire \NlwInverterSignal_INT_MC.D2_PT_6/IN0 ;
  wire \NlwInverterSignal_U3/DCORIE<0>_MC.D2_PT_1/IN2 ;
  wire \NlwInverterSignal_DCORIEw_MC.D1/IN0 ;
  wire \NlwInverterSignal_DCORIEw_MC.D1/IN2 ;
  wire \NlwInverterSignal_DCORIEw_MC.D1/IN3 ;
  wire \NlwInverterSignal_DCORIEw_MC.D1/IN4 ;
  wire \NlwInverterSignal_DCORIEw_MC.D1/IN5 ;
  wire \NlwInverterSignal_DCORIEw_MC.D1/IN6 ;
  wire \NlwInverterSignal_DCORIEw_MC.D1/IN7 ;
  wire \NlwInverterSignal_DCORIEw_MC.D1/IN8 ;
  wire \NlwInverterSignal_DCORIEw_MC.D1/IN9 ;
  wire \NlwInverterSignal_U3/DCORIE<1>_MC.D2_PT_1/IN2 ;
  wire \NlwInverterSignal_U3/DCORIE<2>_MC.D2_PT_1/IN2 ;
  wire \NlwInverterSignal_U3/DCORIE<3>_MC.D2_PT_1/IN2 ;
  wire \NlwInverterSignal_NET2575_MC.D2_PT_0/IN1 ;
  wire \NlwInverterSignal_NET2575_MC.D2_PT_1/IN1 ;
  wire \NlwInverterSignal_NET2575_MC.D2_PT_2/IN1 ;
  wire \NlwInverterSignal_NET2575_MC.D2_PT_3/IN2 ;
  wire \NlwInverterSignal_NET2575_MC.D2_PT_4/IN1 ;
  wire \NlwInverterSignal_NET2575_MC.D2_PT_4/IN2 ;
  wire \NlwInverterSignal_NET2575_MC.D2_PT_5/IN1 ;
  wire \NlwInverterSignal_NET2575_MC.D2_PT_5/IN2 ;
  wire \NlwInverterSignal_U3/DCORIE<4>_MC.D2_PT_1/IN2 ;
  wire \NlwInverterSignal_U3/DCORIE<5>_MC.D2_PT_1/IN2 ;
  wire \NlwInverterSignal_U3/DCORIE<6>_MC.D2_PT_1/IN2 ;
  wire \NlwInverterSignal_U3/DCORIE<7>_MC.D2_PT_1/IN2 ;
  wire \NlwInverterSignal_LED1_MC.D/IN0 ;
  wire \NlwInverterSignal_LED1_MC.D1/IN1 ;
  wire \NlwInverterSignal_U9/MISCr<0>_MC.D/IN0 ;
  wire \NlwInverterSignal_U9/MISCr<0>_MC.D2_PT_0/IN1 ;
  wire \NlwInverterSignal_U9/MISCr<0>_MC.D2_PT_1/IN1 ;
  wire \NlwInverterSignal_U9/MISCr<0>_MC.D2_PT_2/IN1 ;
  wire \NlwInverterSignal_U9/MISCr<0>_MC.D2_PT_3/IN1 ;
  wire \NlwInverterSignal_U9/MISCr<0>_MC.D2_PT_4/IN0 ;
  wire \NlwInverterSignal_U9/MISCr<0>_MC.D2_PT_4/IN1 ;
  wire \NlwInverterSignal_U9/MISCr<0>_MC.D2_PT_5/IN1 ;
  wire \NlwInverterSignal_U9/MISCr<0>_MC.D2_PT_6/IN1 ;
  wire \NlwInverterSignal_U9/MISCr<0>_MC.D2_PT_7/IN0 ;
  wire \NlwInverterSignal_U9/MISCr<0>_MC.D2_PT_7/IN1 ;
  wire \NlwInverterSignal_U9/MISCr<0>_MC.D2_PT_7/IN2 ;
  wire \NlwInverterSignal_LED2_MC.D/IN0 ;
  wire \NlwInverterSignal_LED2_MC.D1/IN1 ;
  wire \NlwInverterSignal_U9/MISCr<1>_MC.D/IN0 ;
  wire \NlwInverterSignal_U9/MISCr<1>_MC.D2_PT_0/IN1 ;
  wire \NlwInverterSignal_U9/MISCr<1>_MC.D2_PT_1/IN1 ;
  wire \NlwInverterSignal_U9/MISCr<1>_MC.D2_PT_2/IN1 ;
  wire \NlwInverterSignal_U9/MISCr<1>_MC.D2_PT_3/IN1 ;
  wire \NlwInverterSignal_U9/MISCr<1>_MC.D2_PT_4/IN0 ;
  wire \NlwInverterSignal_U9/MISCr<1>_MC.D2_PT_4/IN1 ;
  wire \NlwInverterSignal_U9/MISCr<1>_MC.D2_PT_5/IN1 ;
  wire \NlwInverterSignal_U9/MISCr<1>_MC.D2_PT_6/IN1 ;
  wire \NlwInverterSignal_U9/MISCr<1>_MC.D2_PT_7/IN0 ;
  wire \NlwInverterSignal_U9/MISCr<1>_MC.D2_PT_7/IN1 ;
  wire \NlwInverterSignal_U9/MISCr<1>_MC.D2_PT_7/IN2 ;
  wire \NlwInverterSignal_LED3_MC.D/IN0 ;
  wire \NlwInverterSignal_LED3_MC.D1/IN1 ;
  wire \NlwInverterSignal_LED4_MC.D/IN0 ;
  wire \NlwInverterSignal_LED4_MC.D1/IN1 ;
  wire \NlwInverterSignal_LED5_MC.D/IN0 ;
  wire \NlwInverterSignal_LED5_MC.D1/IN1 ;
  wire \NlwInverterSignal_U9/MISCr<4>_MC.D/IN0 ;
  wire \NlwInverterSignal_U9/MISCr<4>_MC.D2_PT_0/IN1 ;
  wire \NlwInverterSignal_U9/MISCr<4>_MC.D2_PT_1/IN1 ;
  wire \NlwInverterSignal_U9/MISCr<4>_MC.D2_PT_2/IN1 ;
  wire \NlwInverterSignal_U9/MISCr<4>_MC.D2_PT_3/IN1 ;
  wire \NlwInverterSignal_U9/MISCr<4>_MC.D2_PT_4/IN0 ;
  wire \NlwInverterSignal_U9/MISCr<4>_MC.D2_PT_4/IN1 ;
  wire \NlwInverterSignal_U9/MISCr<4>_MC.D2_PT_5/IN1 ;
  wire \NlwInverterSignal_U9/MISCr<4>_MC.D2_PT_6/IN1 ;
  wire \NlwInverterSignal_U9/MISCr<4>_MC.D2_PT_7/IN0 ;
  wire \NlwInverterSignal_U9/MISCr<4>_MC.D2_PT_7/IN1 ;
  wire \NlwInverterSignal_U9/MISCr<4>_MC.D2_PT_7/IN2 ;
  wire \NlwInverterSignal_MTRpwrn_MC.D/IN0 ;
  wire \NlwInverterSignal_PAH0_MC.D1/IN0 ;
  wire \NlwInverterSignal_PAH0_MC.D1/IN1 ;
  wire \NlwInverterSignal_PAH0_MC.D1/IN3 ;
  wire \NlwInverterSignal_NET3248_MC.D2_PT_0/IN1 ;
  wire \NlwInverterSignal_NET3248_MC.D2_PT_1/IN2 ;
  wire \NlwInverterSignal_NET3248_MC.D2_PT_2/IN1 ;
  wire \NlwInverterSignal_NET3248_MC.D2_PT_2/IN2 ;
  wire \NlwInverterSignal_PAH1_MC.D1/IN0 ;
  wire \NlwInverterSignal_PAH1_MC.D1/IN1 ;
  wire \NlwInverterSignal_PAH1_MC.D1/IN3 ;
  wire \NlwInverterSignal_NET3253_MC.D2_PT_0/IN1 ;
  wire \NlwInverterSignal_NET3253_MC.D2_PT_1/IN1 ;
  wire \NlwInverterSignal_NET3253_MC.D2_PT_2/IN1 ;
  wire \NlwInverterSignal_NET3253_MC.D2_PT_2/IN2 ;
  wire \NlwInverterSignal_PAL0_MC.D2_PT_1/IN0 ;
  wire \NlwInverterSignal_PAL0_MC.D2_PT_1/IN2 ;
  wire \NlwInverterSignal_PAL0_MC.D2_PT_1/IN3 ;
  wire \NlwInverterSignal_PAL1_MC.D2_PT_1/IN0 ;
  wire \NlwInverterSignal_PAL1_MC.D2_PT_1/IN2 ;
  wire \NlwInverterSignal_PAL1_MC.D2_PT_1/IN3 ;
  wire \NlwInverterSignal_PBH0_MC.D1/IN0 ;
  wire \NlwInverterSignal_PBH0_MC.D1/IN3 ;
  wire \NlwInverterSignal_PBH1_MC.D1/IN0 ;
  wire \NlwInverterSignal_PBH1_MC.D1/IN3 ;
  wire \NlwInverterSignal_PBL0_MC.D2_PT_1/IN0 ;
  wire \NlwInverterSignal_PBL0_MC.D2_PT_1/IN1 ;
  wire \NlwInverterSignal_PBL0_MC.D2_PT_1/IN2 ;
  wire \NlwInverterSignal_PBL0_MC.D2_PT_1/IN3 ;
  wire \NlwInverterSignal_PBL1_MC.D2_PT_1/IN0 ;
  wire \NlwInverterSignal_PBL1_MC.D2_PT_1/IN1 ;
  wire \NlwInverterSignal_PBL1_MC.D2_PT_1/IN2 ;
  wire \NlwInverterSignal_PBL1_MC.D2_PT_1/IN3 ;
  wire \NlwInverterSignal_PresEn_MC.D/IN0 ;
  wire \NlwInverterSignal_DCORSENSORw_MC.D1/IN0 ;
  wire \NlwInverterSignal_DCORSENSORw_MC.D1/IN2 ;
  wire \NlwInverterSignal_DCORSENSORw_MC.D1/IN3 ;
  wire \NlwInverterSignal_DCORSENSORw_MC.D1/IN4 ;
  wire \NlwInverterSignal_DCORSENSORw_MC.D1/IN5 ;
  wire \NlwInverterSignal_DCORSENSORw_MC.D1/IN6 ;
  wire \NlwInverterSignal_DCORSENSORw_MC.D1/IN8 ;
  wire \NlwInverterSignal_TP11_MC.D/IN0 ;
  wire \NlwInverterSignal_TmpEn_MC.D/IN0 ;
  wire \NlwInverterSignal_outDATA<2>\$WA3.UIM_MC.D2_PT_1/IN0 ;
  wire \NlwInverterSignal_outDATA<2>\$WA5.UIM_MC.D2_PT_1/IN0 ;
  wire \NlwInverterSignal_outDATA<2>\$WA5.UIM_MC.D2_PT_2/IN0 ;
  wire \NlwInverterSignal_outDATA<2>\$WA5.UIM_MC.D2_PT_2/IN1 ;
  wire \NlwInverterSignal_outDATA<2>\$WA5.UIM_MC.D2_PT_3/IN0 ;
  wire \NlwInverterSignal_outDATA<2>\$WA5.UIM_MC.D2_PT_3/IN1 ;
  wire \NlwInverterSignal_outDATA<2>\$WA5.UIM_MC.D2_PT_3/IN2 ;
  wire \NlwInverterSignal_U1/U3/holdingreg0<2>_MC.D2_PT_1/IN1 ;
  wire \NlwInverterSignal_U1/U3/holdingreg1<2>_MC.D2_PT_1/IN1 ;
  wire \NlwInverterSignal_U1/U3/holdingreg0<10>_MC.D2_PT_1/IN1 ;
  wire \NlwInverterSignal_U1/U3/holdingreg1<10>_MC.D2_PT_1/IN1 ;
  wire \NlwInverterSignal_outDATA<2>\$WA6.UIM_MC.D2_PT_1/IN1 ;
  wire \NlwInverterSignal_outDATA<2>\$WA6.UIM_MC.D2_PT_2/IN0 ;
  wire \NlwInverterSignal_outDATA<2>\$WA6.UIM_MC.D2_PT_2/IN1 ;
  wire \NlwInverterSignal_outDATA<2>\$WA6.UIM_MC.D2_PT_3/IN0 ;
  wire \NlwInverterSignal_outDATA<2>\$WA6.UIM_MC.D2_PT_3/IN1 ;
  wire \NlwInverterSignal_outDATA<2>\$WA6.UIM_MC.D2_PT_3/IN2 ;
  wire \NlwInverterSignal_outDATA<2>\$WA6.UIM_MC.D2_PT_4/IN0 ;
  wire \NlwInverterSignal_outDATA<2>\$WA6.UIM_MC.D2_PT_4/IN1 ;
  wire \NlwInverterSignal_outDATA<2>\$WA6.UIM_MC.D2_PT_4/IN2 ;
  wire \NlwInverterSignal_outDATA<2>\$WA6.UIM_MC.D2_PT_4/IN3 ;
  wire \NlwInverterSignal_U1/U4/Latch0r<2>_MC.D2_PT_1/IN1 ;
  wire \NlwInverterSignal_U1/U4/Latch0r<10>_MC.D2_PT_1/IN1 ;
  wire \NlwInverterSignal_U1/U4/Latch1r<2>_MC.D2_PT_1/IN1 ;
  wire \NlwInverterSignal_U1/U4/Latch1r<10>_MC.D2_PT_1/IN1 ;
  wire \NlwInverterSignal_outDATA<3>\$WA3.UIM_MC.D2_PT_1/IN0 ;
  wire \NlwInverterSignal_outDATA<3>\$WA5.UIM_MC.D2_PT_1/IN0 ;
  wire \NlwInverterSignal_outDATA<3>\$WA5.UIM_MC.D2_PT_2/IN0 ;
  wire \NlwInverterSignal_outDATA<3>\$WA5.UIM_MC.D2_PT_2/IN1 ;
  wire \NlwInverterSignal_outDATA<3>\$WA5.UIM_MC.D2_PT_3/IN0 ;
  wire \NlwInverterSignal_outDATA<3>\$WA5.UIM_MC.D2_PT_3/IN1 ;
  wire \NlwInverterSignal_outDATA<3>\$WA5.UIM_MC.D2_PT_3/IN2 ;
  wire \NlwInverterSignal_U1/U3/holdingreg0<3>_MC.D2_PT_1/IN1 ;
  wire \NlwInverterSignal_U1/U3/holdingreg1<3>_MC.D2_PT_1/IN1 ;
  wire \NlwInverterSignal_U1/U3/holdingreg0<11>_MC.D2_PT_1/IN1 ;
  wire \NlwInverterSignal_U1/U3/holdingreg1<11>_MC.D2_PT_1/IN1 ;
  wire \NlwInverterSignal_outDATA<3>\$WA6.UIM_MC.D2_PT_1/IN1 ;
  wire \NlwInverterSignal_outDATA<3>\$WA6.UIM_MC.D2_PT_2/IN0 ;
  wire \NlwInverterSignal_outDATA<3>\$WA6.UIM_MC.D2_PT_2/IN1 ;
  wire \NlwInverterSignal_outDATA<3>\$WA6.UIM_MC.D2_PT_3/IN0 ;
  wire \NlwInverterSignal_outDATA<3>\$WA6.UIM_MC.D2_PT_3/IN1 ;
  wire \NlwInverterSignal_outDATA<3>\$WA6.UIM_MC.D2_PT_3/IN2 ;
  wire \NlwInverterSignal_outDATA<3>\$WA6.UIM_MC.D2_PT_4/IN0 ;
  wire \NlwInverterSignal_outDATA<3>\$WA6.UIM_MC.D2_PT_4/IN1 ;
  wire \NlwInverterSignal_outDATA<3>\$WA6.UIM_MC.D2_PT_4/IN2 ;
  wire \NlwInverterSignal_outDATA<3>\$WA6.UIM_MC.D2_PT_4/IN3 ;
  wire \NlwInverterSignal_U1/U4/Latch0r<3>_MC.D2_PT_1/IN1 ;
  wire \NlwInverterSignal_U1/U4/Latch0r<11>_MC.D2_PT_1/IN1 ;
  wire \NlwInverterSignal_U1/U4/Latch1r<3>_MC.D2_PT_1/IN1 ;
  wire \NlwInverterSignal_U1/U4/Latch1r<11>_MC.D2_PT_1/IN1 ;
  wire \NlwInverterSignal_outDATA<6>\$WA3.UIM_MC.D2_PT_1/IN0 ;
  wire \NlwInverterSignal_outDATA<6>\$WA5.UIM_MC.D2_PT_1/IN0 ;
  wire \NlwInverterSignal_outDATA<6>\$WA5.UIM_MC.D2_PT_2/IN0 ;
  wire \NlwInverterSignal_outDATA<6>\$WA5.UIM_MC.D2_PT_2/IN1 ;
  wire \NlwInverterSignal_outDATA<6>\$WA5.UIM_MC.D2_PT_3/IN0 ;
  wire \NlwInverterSignal_outDATA<6>\$WA5.UIM_MC.D2_PT_3/IN1 ;
  wire \NlwInverterSignal_outDATA<6>\$WA5.UIM_MC.D2_PT_3/IN2 ;
  wire \NlwInverterSignal_U1/U3/holdingreg0<6>_MC.D2_PT_1/IN1 ;
  wire \NlwInverterSignal_U1/U3/holdingreg1<6>_MC.D2_PT_1/IN1 ;
  wire \NlwInverterSignal_U1/U3/holdingreg0<14>_MC.D2_PT_1/IN1 ;
  wire \NlwInverterSignal_U1/Channel0<14>_MC.D2_PT_0/IN0 ;
  wire \NlwInverterSignal_U1/Channel0<14>_MC.D2_PT_1/IN1 ;
  wire \NlwInverterSignal_U1/Channel0<14>_MC.D2_PT_1/IN2 ;
  wire \NlwInverterSignal_U1/Channel0<14>_MC.D2_PT_1/IN3 ;
  wire \NlwInverterSignal_U1/Channel0<14>_MC.D2_PT_1/IN5 ;
  wire \NlwInverterSignal_U1/Channel0<14>_MC.D2_PT_1/IN6 ;
  wire \NlwInverterSignal_U1/Channel0<14>_MC.D2_PT_2/IN4 ;
  wire \NlwInverterSignal_U1/U3/holdingreg1<14>_MC.D2_PT_1/IN1 ;
  wire \NlwInverterSignal_U1/Channel1<14>_MC.D2_PT_0/IN0 ;
  wire \NlwInverterSignal_U1/Channel1<14>_MC.D2_PT_1/IN1 ;
  wire \NlwInverterSignal_U1/Channel1<14>_MC.D2_PT_1/IN3 ;
  wire \NlwInverterSignal_U1/Channel1<14>_MC.D2_PT_1/IN8 ;
  wire \NlwInverterSignal_U1/Channel1<14>_MC.D2_PT_2/IN1 ;
  wire \NlwInverterSignal_U1/Channel1<14>_MC.D2_PT_2/IN3 ;
  wire \NlwInverterSignal_U1/Channel1<14>_MC.D2_PT_2/IN4 ;
  wire \NlwInverterSignal_U1/Channel1<14>_MC.D2_PT_2/IN6 ;
  wire \NlwInverterSignal_U1/Channel1<14>_MC.D2_PT_2/IN7 ;
  wire \NlwInverterSignal_U1/Channel1<14>_MC.D2_PT_2/IN8 ;
  wire \NlwInverterSignal_U1/Channel1<14>_MC.D2_PT_2/IN10 ;
  wire \NlwInverterSignal_U1/Channel1<14>_MC.D2_PT_2/IN11 ;
  wire \NlwInverterSignal_outDATA<6>\$WA6.UIM_MC.D2_PT_1/IN0 ;
  wire \NlwInverterSignal_outDATA<6>\$WA6.UIM_MC.D2_PT_2/IN0 ;
  wire \NlwInverterSignal_outDATA<6>\$WA6.UIM_MC.D2_PT_2/IN1 ;
  wire \NlwInverterSignal_outDATA<6>\$WA6.UIM_MC.D2_PT_3/IN0 ;
  wire \NlwInverterSignal_outDATA<6>\$WA6.UIM_MC.D2_PT_3/IN1 ;
  wire \NlwInverterSignal_outDATA<6>\$WA6.UIM_MC.D2_PT_3/IN2 ;
  wire \NlwInverterSignal_outDATA<6>\$WA6.UIM_MC.D2_PT_4/IN0 ;
  wire \NlwInverterSignal_outDATA<6>\$WA6.UIM_MC.D2_PT_4/IN1 ;
  wire \NlwInverterSignal_outDATA<6>\$WA6.UIM_MC.D2_PT_4/IN2 ;
  wire \NlwInverterSignal_outDATA<6>\$WA6.UIM_MC.D2_PT_4/IN3 ;
  wire \NlwInverterSignal_U1/U4/Latch0r<6>_MC.D2_PT_1/IN1 ;
  wire \NlwInverterSignal_U1/U4/Latch0r<14>_MC.D2_PT_1/IN1 ;
  wire \NlwInverterSignal_U1/U4/Latch1r<6>_MC.D2_PT_1/IN1 ;
  wire \NlwInverterSignal_U1/U4/Latch1r<14>_MC.D2_PT_1/IN1 ;
  wire \NlwInverterSignal_outDATA<7>\$WA3.UIM_MC.D2_PT_1/IN0 ;
  wire \NlwInverterSignal_outDATA<7>\$WA6.UIM_MC.D2_PT_1/IN0 ;
  wire \NlwInverterSignal_outDATA<7>\$WA6.UIM_MC.D2_PT_2/IN0 ;
  wire \NlwInverterSignal_outDATA<7>\$WA6.UIM_MC.D2_PT_2/IN1 ;
  wire \NlwInverterSignal_outDATA<7>\$WA6.UIM_MC.D2_PT_3/IN0 ;
  wire \NlwInverterSignal_outDATA<7>\$WA6.UIM_MC.D2_PT_3/IN1 ;
  wire \NlwInverterSignal_outDATA<7>\$WA6.UIM_MC.D2_PT_3/IN2 ;
  wire \NlwInverterSignal_U1/U4/Latch0r<7>_MC.D2_PT_1/IN1 ;
  wire \NlwInverterSignal_U1/U4/Latch0r<15>_MC.D2_PT_1/IN1 ;
  wire \NlwInverterSignal_U1/Channel0<15>_MC.D2_PT_0/IN0 ;
  wire \NlwInverterSignal_U1/Channel0<15>_MC.D2_PT_1/IN1 ;
  wire \NlwInverterSignal_U1/Channel0<15>_MC.D2_PT_1/IN2 ;
  wire \NlwInverterSignal_U1/Channel0<15>_MC.D2_PT_1/IN3 ;
  wire \NlwInverterSignal_U1/Channel0<15>_MC.D2_PT_1/IN5 ;
  wire \NlwInverterSignal_U1/Channel0<15>_MC.D2_PT_1/IN6 ;
  wire \NlwInverterSignal_U1/Channel0<15>_MC.D2_PT_1/IN7 ;
  wire \NlwInverterSignal_U1/Channel0<15>_MC.D2_PT_2/IN4 ;
  wire \NlwInverterSignal_U1/U4/Latch1r<7>_MC.D2_PT_1/IN1 ;
  wire \NlwInverterSignal_U1/U4/Latch1r<15>_MC.D2_PT_1/IN1 ;
  wire \NlwInverterSignal_U1/Channel1<15>_MC.D2_PT_0/IN0 ;
  wire \NlwInverterSignal_U1/Channel1<15>_MC.D2_PT_1/IN1 ;
  wire \NlwInverterSignal_U1/Channel1<15>_MC.D2_PT_1/IN3 ;
  wire \NlwInverterSignal_U1/Channel1<15>_MC.D2_PT_1/IN8 ;
  wire \NlwInverterSignal_U1/Channel1<15>_MC.D2_PT_2/IN1 ;
  wire \NlwInverterSignal_U1/Channel1<15>_MC.D2_PT_2/IN3 ;
  wire \NlwInverterSignal_U1/Channel1<15>_MC.D2_PT_2/IN4 ;
  wire \NlwInverterSignal_U1/Channel1<15>_MC.D2_PT_2/IN6 ;
  wire \NlwInverterSignal_U1/Channel1<15>_MC.D2_PT_2/IN7 ;
  wire \NlwInverterSignal_U1/Channel1<15>_MC.D2_PT_2/IN8 ;
  wire \NlwInverterSignal_U1/Channel1<15>_MC.D2_PT_2/IN10 ;
  wire \NlwInverterSignal_U1/Channel1<15>_MC.D2_PT_2/IN11 ;
  wire \NlwInverterSignal_U1/Channel1<15>_MC.D2_PT_2/IN12 ;
  wire \NlwInverterSignal_outDATA<7>\$WA5.UIM_MC.D2_PT_1/IN0 ;
  wire \NlwInverterSignal_outDATA<7>\$WA5.UIM_MC.D2_PT_2/IN0 ;
  wire \NlwInverterSignal_outDATA<7>\$WA5.UIM_MC.D2_PT_2/IN1 ;
  wire \NlwInverterSignal_outDATA<7>\$WA5.UIM_MC.D2_PT_3/IN0 ;
  wire \NlwInverterSignal_outDATA<7>\$WA5.UIM_MC.D2_PT_3/IN1 ;
  wire \NlwInverterSignal_outDATA<7>\$WA5.UIM_MC.D2_PT_3/IN2 ;
  wire \NlwInverterSignal_U1/U3/holdingreg0<7>_MC.D2_PT_1/IN1 ;
  wire \NlwInverterSignal_U1/U3/holdingreg1<7>_MC.D2_PT_1/IN1 ;
  wire \NlwInverterSignal_U1/U3/holdingreg0<15>_MC.D2_PT_1/IN1 ;
  wire \NlwInverterSignal_U1/U3/holdingreg1<15>_MC.D2_PT_1/IN1 ;
  wire \NlwInverterSignal_outDATA<0>\$WA3.UIM_MC.D2_PT_1/IN0 ;
  wire \NlwInverterSignal_outDATA<0>\$WA6.UIM_MC.D2_PT_1/IN0 ;
  wire \NlwInverterSignal_outDATA<0>\$WA6.UIM_MC.D2_PT_2/IN0 ;
  wire \NlwInverterSignal_outDATA<0>\$WA6.UIM_MC.D2_PT_2/IN1 ;
  wire \NlwInverterSignal_outDATA<0>\$WA6.UIM_MC.D2_PT_3/IN0 ;
  wire \NlwInverterSignal_outDATA<0>\$WA6.UIM_MC.D2_PT_3/IN1 ;
  wire \NlwInverterSignal_outDATA<0>\$WA6.UIM_MC.D2_PT_3/IN2 ;
  wire \NlwInverterSignal_U1/U4/Latch0r<0>_MC.D2_PT_1/IN1 ;
  wire \NlwInverterSignal_U1/U4/Latch0r<8>_MC.D2_PT_1/IN1 ;
  wire \NlwInverterSignal_U1/U4/Latch1r<0>_MC.D2_PT_1/IN1 ;
  wire \NlwInverterSignal_U1/U4/Latch1r<8>_MC.D2_PT_1/IN1 ;
  wire \NlwInverterSignal_outDATA<0>\$WA5.UIM_MC.D2_PT_1/IN0 ;
  wire \NlwInverterSignal_outDATA<0>\$WA5.UIM_MC.D2_PT_2/IN0 ;
  wire \NlwInverterSignal_outDATA<0>\$WA5.UIM_MC.D2_PT_2/IN1 ;
  wire \NlwInverterSignal_outDATA<0>\$WA5.UIM_MC.D2_PT_3/IN0 ;
  wire \NlwInverterSignal_outDATA<0>\$WA5.UIM_MC.D2_PT_3/IN1 ;
  wire \NlwInverterSignal_outDATA<0>\$WA5.UIM_MC.D2_PT_3/IN2 ;
  wire \NlwInverterSignal_U1/U3/holdingreg0<0>_MC.D2_PT_1/IN1 ;
  wire \NlwInverterSignal_U1/U3/holdingreg1<0>_MC.D2_PT_1/IN1 ;
  wire \NlwInverterSignal_U1/U3/holdingreg0<8>_MC.D2_PT_1/IN1 ;
  wire \NlwInverterSignal_U1/U3/holdingreg1<8>_MC.D2_PT_1/IN1 ;
  wire \NlwInverterSignal_outDATA<1>\$WA3.UIM_MC.D2_PT_0/IN0 ;
  wire \NlwInverterSignal_outDATA<1>\$WA3.UIM_MC.D2_PT_2/IN1 ;
  wire \NlwInverterSignal_outDATA<1>\$WA6.UIM_MC.D2_PT_1/IN0 ;
  wire \NlwInverterSignal_outDATA<1>\$WA6.UIM_MC.D2_PT_2/IN0 ;
  wire \NlwInverterSignal_outDATA<1>\$WA6.UIM_MC.D2_PT_2/IN1 ;
  wire \NlwInverterSignal_outDATA<1>\$WA6.UIM_MC.D2_PT_3/IN0 ;
  wire \NlwInverterSignal_outDATA<1>\$WA6.UIM_MC.D2_PT_3/IN1 ;
  wire \NlwInverterSignal_outDATA<1>\$WA6.UIM_MC.D2_PT_3/IN2 ;
  wire \NlwInverterSignal_U1/U4/Latch0r<1>_MC.D2_PT_1/IN1 ;
  wire \NlwInverterSignal_U1/U4/Latch0r<9>_MC.D2_PT_1/IN1 ;
  wire \NlwInverterSignal_U1/U4/Latch1r<1>_MC.D2_PT_1/IN1 ;
  wire \NlwInverterSignal_U1/U4/Latch1r<9>_MC.D2_PT_1/IN1 ;
  wire \NlwInverterSignal_outDATA<1>\$WA5.UIM_MC.D2_PT_1/IN0 ;
  wire \NlwInverterSignal_outDATA<1>\$WA5.UIM_MC.D2_PT_2/IN0 ;
  wire \NlwInverterSignal_outDATA<1>\$WA5.UIM_MC.D2_PT_2/IN1 ;
  wire \NlwInverterSignal_outDATA<1>\$WA5.UIM_MC.D2_PT_3/IN0 ;
  wire \NlwInverterSignal_outDATA<1>\$WA5.UIM_MC.D2_PT_3/IN1 ;
  wire \NlwInverterSignal_outDATA<1>\$WA5.UIM_MC.D2_PT_3/IN2 ;
  wire \NlwInverterSignal_U1/U3/holdingreg0<1>_MC.D2_PT_1/IN1 ;
  wire \NlwInverterSignal_U1/U3/holdingreg1<1>_MC.D2_PT_1/IN1 ;
  wire \NlwInverterSignal_U1/U3/holdingreg0<9>_MC.D2_PT_1/IN1 ;
  wire \NlwInverterSignal_U1/U3/holdingreg1<9>_MC.D2_PT_1/IN1 ;
  wire \NlwInverterSignal_outDATA<4>\$WA3.UIM_MC.D2_PT_1/IN0 ;
  wire \NlwInverterSignal_outDATA<4>\$WA6.UIM_MC.D2_PT_1/IN0 ;
  wire \NlwInverterSignal_outDATA<4>\$WA6.UIM_MC.D2_PT_2/IN0 ;
  wire \NlwInverterSignal_outDATA<4>\$WA6.UIM_MC.D2_PT_2/IN1 ;
  wire \NlwInverterSignal_outDATA<4>\$WA6.UIM_MC.D2_PT_3/IN0 ;
  wire \NlwInverterSignal_outDATA<4>\$WA6.UIM_MC.D2_PT_3/IN1 ;
  wire \NlwInverterSignal_outDATA<4>\$WA6.UIM_MC.D2_PT_3/IN2 ;
  wire \NlwInverterSignal_U1/U4/Latch0r<4>_MC.D2_PT_1/IN1 ;
  wire \NlwInverterSignal_U1/U4/Latch0r<12>_MC.D2_PT_1/IN1 ;
  wire \NlwInverterSignal_U1/U4/Latch1r<4>_MC.D2_PT_1/IN1 ;
  wire \NlwInverterSignal_U1/U4/Latch1r<12>_MC.D2_PT_1/IN1 ;
  wire \NlwInverterSignal_outDATA<4>\$WA5.UIM_MC.D2_PT_1/IN0 ;
  wire \NlwInverterSignal_outDATA<4>\$WA5.UIM_MC.D2_PT_2/IN0 ;
  wire \NlwInverterSignal_outDATA<4>\$WA5.UIM_MC.D2_PT_2/IN1 ;
  wire \NlwInverterSignal_outDATA<4>\$WA5.UIM_MC.D2_PT_3/IN0 ;
  wire \NlwInverterSignal_outDATA<4>\$WA5.UIM_MC.D2_PT_3/IN1 ;
  wire \NlwInverterSignal_outDATA<4>\$WA5.UIM_MC.D2_PT_3/IN2 ;
  wire \NlwInverterSignal_U1/U3/holdingreg0<4>_MC.D2_PT_1/IN1 ;
  wire \NlwInverterSignal_U1/U3/holdingreg1<4>_MC.D2_PT_1/IN1 ;
  wire \NlwInverterSignal_U1/U3/holdingreg0<12>_MC.D2_PT_1/IN1 ;
  wire \NlwInverterSignal_U1/U3/holdingreg1<12>_MC.D2_PT_1/IN1 ;
  wire \NlwInverterSignal_FOOBAR2__ctinst/7/OUT ;
  wire \NlwInverterSignal_FOOBAR3__ctinst/7/OUT ;
  wire \NlwInverterSignal_FOOBAR5__ctinst/4/IN1 ;
  wire \NlwInverterSignal_FOOBAR21__ctinst/4/IN0 ;
  wire \NlwInverterSignal_FOOBAR21__ctinst/4/IN1 ;
  wire \NlwInverterSignal_FOOBAR24__ctinst/4/IN0 ;
  wire \NlwInverterSignal_FOOBAR24__ctinst/4/IN1 ;
  wire [4 : 0] \U9/MISCr ;
  wire [7 : 0] \U4/Flgreg ;
  wire [7 : 0] U2_ADDR_reg;
  wire [5 : 0] U11_U3_counterr;
  wire [15 : 0] \U1/U3/holdingreg0 ;
  wire [15 : 0] \U1/U3/holdingreg1 ;
  wire [15 : 0] \U1/Channel0 ;
  wire [0 : 0] \U1/U2/location_Maddsub__n0000__n0067 ;
  wire [15 : 0] \U1/Channel1 ;
  wire [0 : 0] \U1/U5/location_Maddsub__n0000__n0067 ;
  wire [0 : 0] \U1/U2/location_Maddsub__n0000__n0075 ;
  wire [0 : 0] \U1/U5/location_Maddsub__n0000__n0075 ;
  wire [15 : 0] \U1/U4/Latch0r ;
  wire [15 : 0] \U1/U4/Latch1r ;
  wire [7 : 0] \U3/DCORIE ;
  assign
    NlwRenamedSig_IO_WR = WR,
    NlwRenamedSig_IO_RD = RD,
    NlwRenamedSig_IO_AS = AS,
    NlwRenamedSig_IO_Home15FLG = Home15FLG,
    NlwRenamedSig_IO_Home133FLG = Home133FLG,
    NlwRenamedSig_IO_Home05FLG = Home05FLG,
    NlwRenamedSig_IO_Home033FLG = Home033FLG,
    NlwRenamedSig_IO_Enc15FLG = Enc15FLG,
    NlwRenamedSig_IO_Enc133FLG = Enc133FLG,
    NlwRenamedSig_IO_Enc05FLG = Enc05FLG,
    NlwRenamedSig_IO_Enc033FLG = Enc033FLG;
  initial $sdf_annotate("c:/projects/genosensor/2g/cplds/core/u21/implement/time_sim.sdf");
  X_IPAD \WR.PAD  (
    .PAD(NlwRenamedSig_IO_WR)
  );
  X_PU WR_tsimcreated__pullup_ (
    .O(NlwRenamedSig_IO_WR)
  );
  X_BUF \WR_II/UIM_0  (
    .I(NlwRenamedSig_IO_WR),
    .O(\WR_II/UIM )
  );
  X_IPAD \RD.PAD  (
    .PAD(NlwRenamedSig_IO_RD)
  );
  X_PU RD_tsimcreated__pullup_ (
    .O(NlwRenamedSig_IO_RD)
  );
  X_BUF \RD_II/UIM_1  (
    .I(NlwRenamedSig_IO_RD),
    .O(\RD_II/UIM )
  );
  X_IPAD \MSPReset.PAD  (
    .PAD(MSPReset)
  );
  X_BUF \MSPReset_II/UIM_2  (
    .I(MSPReset),
    .O(\MSPReset_II/UIM )
  );
  X_BUF \AD<0>_II/UIM_3  (
    .I(AD[0]),
    .O(\AD<0>_II/UIM )
  );
  X_BUF \AD<0>_II/IREG_4  (
    .I(\U9/MISCr [0]),
    .O(\AD<0>_II/IREG )
  );
  X_OR2 \U9/MISCr<0>_MC_tsimcreated_prld__5  (
    .I0(\FOOBAR3__ctinst/7 ),
    .I1(PRLD),
    .O(\U9/MISCr<0>_MC_tsimcreated_prld_ )
  );
  X_FF \U9/MISCr<0>_MC.REG  (
    .I(AD[0]),
    .CE(\U9/MISCr<0>_MC.CE ),
    .CLK(\U9/MISCr<0>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(\U9/MISCr<0>_MC_tsimcreated_prld_ ),
    .O(\U9/MISCr [0])
  );
  X_INV \U9/MISCr<0>_MC.REG_tsimcreated_inv_Mclk_II/FCLK_6  (
    .I(\Mclk_II/FCLK ),
    .O(\U9/MISCr<0>_MC.REG_tsimcreated_inv_Mclk_II/FCLK )
  );
  X_ZERO Gnd_7 (
    .O(Gnd)
  );
  X_IPAD \AS.PAD  (
    .PAD(NlwRenamedSig_IO_AS)
  );
  X_PU AS_tsimcreated__pullup_ (
    .O(NlwRenamedSig_IO_AS)
  );
  X_BUF \AS_II/UIM_8  (
    .I(NlwRenamedSig_IO_AS),
    .O(\AS_II/UIM )
  );
  X_BUF \AS_II/IREG_9  (
    .I(U2_ASedge),
    .O(\AS_II/IREG )
  );
  X_FF \U2_ASedge_MC.REG  (
    .I(NlwRenamedSig_IO_AS),
    .CE(Vcc),
    .CLK(\U2_ASedge_MC.REG_tsimcreated_inv_Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(U2_ASedge)
  );
  X_INV \U2_ASedge_MC.REG_tsimcreated_inv_Mclk_II/FCLK_10  (
    .I(\Mclk_II/FCLK ),
    .O(\U2_ASedge_MC.REG_tsimcreated_inv_Mclk_II/FCLK )
  );
  X_ONE Vcc_11 (
    .O(Vcc)
  );
  X_IPAD \Mclk.PAD  (
    .PAD(Mclk)
  );
  X_BUF \Mclk_II/FCLK_12  (
    .I(Mclk),
    .O(\Mclk_II/FCLK )
  );
  X_BUF \AD<4>_II/UIM_13  (
    .I(AD[4]),
    .O(\AD<4>_II/UIM )
  );
  X_BUF \AD<4>_II/IREG_14  (
    .I(\U9/MISCr [4]),
    .O(\AD<4>_II/IREG )
  );
  X_OR2 \U9/MISCr<4>_MC_tsimcreated_prld__15  (
    .I0(\FOOBAR3__ctinst/7 ),
    .I1(PRLD),
    .O(\U9/MISCr<4>_MC_tsimcreated_prld_ )
  );
  X_FF \U9/MISCr<4>_MC.REG  (
    .I(AD[4]),
    .CE(\U9/MISCr<4>_MC.CE ),
    .CLK(\U9/MISCr<4>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(\U9/MISCr<4>_MC_tsimcreated_prld_ ),
    .O(\U9/MISCr [4])
  );
  X_INV \U9/MISCr<4>_MC.REG_tsimcreated_inv_Mclk_II/FCLK_16  (
    .I(\Mclk_II/FCLK ),
    .O(\U9/MISCr<4>_MC.REG_tsimcreated_inv_Mclk_II/FCLK )
  );
  X_BUF \AD<5>_II/UIM_17  (
    .I(AD[5]),
    .O(\AD<5>_II/UIM )
  );
  X_BUF \AD<6>_II/UIM_18  (
    .I(AD[6]),
    .O(\AD<6>_II/UIM )
  );
  X_BUF \AD<6>_II/IREG_19  (
    .I(\U4/ctrlr[6] ),
    .O(\AD<6>_II/IREG )
  );
  X_OR2 \U4/ctrlr<6>_MC_tsimcreated_prld__20  (
    .I0(\FOOBAR3__ctinst/7 ),
    .I1(PRLD),
    .O(\U4/ctrlr<6>_MC_tsimcreated_prld_ )
  );
  X_FF \U4/ctrlr<6>_MC.REG  (
    .I(AD[6]),
    .CE(\FOOBAR10__ctinst/4 ),
    .CLK(\U4/ctrlr<6>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(\U4/ctrlr<6>_MC_tsimcreated_prld_ ),
    .O(\U4/ctrlr[6] )
  );
  X_INV \U4/ctrlr<6>_MC.REG_tsimcreated_inv_Mclk_II/FCLK_21  (
    .I(\Mclk_II/FCLK ),
    .O(\U4/ctrlr<6>_MC.REG_tsimcreated_inv_Mclk_II/FCLK )
  );
  X_BUF \AD<7>_II/UIM_22  (
    .I(AD[7]),
    .O(\AD<7>_II/UIM )
  );
  X_BUF \AD<7>_II/IREG_23  (
    .I(\U4/ctrlr[7] ),
    .O(\AD<7>_II/IREG )
  );
  X_OR2 \U4/ctrlr<7>_MC_tsimcreated_prld__24  (
    .I0(\FOOBAR3__ctinst/7 ),
    .I1(PRLD),
    .O(\U4/ctrlr<7>_MC_tsimcreated_prld_ )
  );
  X_FF \U4/ctrlr<7>_MC.REG  (
    .I(AD[7]),
    .CE(\FOOBAR9__ctinst/4 ),
    .CLK(\U4/ctrlr<7>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(\U4/ctrlr<7>_MC_tsimcreated_prld_ ),
    .O(\U4/ctrlr[7] )
  );
  X_INV \U4/ctrlr<7>_MC.REG_tsimcreated_inv_Mclk_II/FCLK_25  (
    .I(\Mclk_II/FCLK ),
    .O(\U4/ctrlr<7>_MC.REG_tsimcreated_inv_Mclk_II/FCLK )
  );
  X_BUF \AD<3>_II/UIM_26  (
    .I(AD[3]),
    .O(\AD<3>_II/UIM )
  );
  X_BUF \AD<3>_II/IREG_27  (
    .I(\U4/ctrlr[3] ),
    .O(\AD<3>_II/IREG )
  );
  X_OR2 \U4/ctrlr<3>_MC_tsimcreated_prld__28  (
    .I0(\FOOBAR3__ctinst/7 ),
    .I1(PRLD),
    .O(\U4/ctrlr<3>_MC_tsimcreated_prld_ )
  );
  X_FF \U4/ctrlr<3>_MC.REG  (
    .I(AD[3]),
    .CE(\FOOBAR12__ctinst/4 ),
    .CLK(\U4/ctrlr<3>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(\U4/ctrlr<3>_MC_tsimcreated_prld_ ),
    .O(\U4/ctrlr[3] )
  );
  X_INV \U4/ctrlr<3>_MC.REG_tsimcreated_inv_Mclk_II/FCLK_29  (
    .I(\Mclk_II/FCLK ),
    .O(\U4/ctrlr<3>_MC.REG_tsimcreated_inv_Mclk_II/FCLK )
  );
  X_BUF \AD<1>_II/UIM_30  (
    .I(AD[1]),
    .O(\AD<1>_II/UIM )
  );
  X_BUF \AD<1>_II/IREG_31  (
    .I(\U9/MISCr [1]),
    .O(\AD<1>_II/IREG )
  );
  X_OR2 \U9/MISCr<1>_MC_tsimcreated_prld__32  (
    .I0(\FOOBAR3__ctinst/7 ),
    .I1(PRLD),
    .O(\U9/MISCr<1>_MC_tsimcreated_prld_ )
  );
  X_FF \U9/MISCr<1>_MC.REG  (
    .I(AD[1]),
    .CE(\U9/MISCr<1>_MC.CE ),
    .CLK(\U9/MISCr<1>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(\U9/MISCr<1>_MC_tsimcreated_prld_ ),
    .O(\U9/MISCr [1])
  );
  X_INV \U9/MISCr<1>_MC.REG_tsimcreated_inv_Mclk_II/FCLK_33  (
    .I(\Mclk_II/FCLK ),
    .O(\U9/MISCr<1>_MC.REG_tsimcreated_inv_Mclk_II/FCLK )
  );
  X_BUF \AD<2>_II/UIM_34  (
    .I(AD[2]),
    .O(\AD<2>_II/UIM )
  );
  X_BUF \AD<2>_II/IREG_35  (
    .I(\U4/ctrlr[2] ),
    .O(\AD<2>_II/IREG )
  );
  X_OR2 \U4/ctrlr<2>_MC_tsimcreated_prld__36  (
    .I0(\FOOBAR3__ctinst/7 ),
    .I1(PRLD),
    .O(\U4/ctrlr<2>_MC_tsimcreated_prld_ )
  );
  X_FF \U4/ctrlr<2>_MC.REG  (
    .I(AD[2]),
    .CE(\FOOBAR12__ctinst/4 ),
    .CLK(\U4/ctrlr<2>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(\U4/ctrlr<2>_MC_tsimcreated_prld_ ),
    .O(\U4/ctrlr[2] )
  );
  X_INV \U4/ctrlr<2>_MC.REG_tsimcreated_inv_Mclk_II/FCLK_37  (
    .I(\Mclk_II/FCLK ),
    .O(\U4/ctrlr<2>_MC.REG_tsimcreated_inv_Mclk_II/FCLK )
  );
  X_IPAD \SCLreset.PAD  (
    .PAD(SCLreset)
  );
  X_BUF \SCLreset_II/UIM_38  (
    .I(SCLreset),
    .O(\SCLreset_II/UIM )
  );
  X_BUF \SCLreset_II/IREG_39  (
    .I(\U11_U4/Line_last ),
    .O(\SCLreset_II/IREG )
  );
  X_FF \U11_U4/Line_last_MC.REG  (
    .I(SCLreset),
    .CE(Vcc),
    .CLK(\U11_U4/Line_last_MC.REG_tsimcreated_inv_Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\U11_U4/Line_last )
  );
  X_INV \U11_U4/Line_last_MC.REG_tsimcreated_inv_Mclk_II/FCLK_40  (
    .I(\Mclk_II/FCLK ),
    .O(\U11_U4/Line_last_MC.REG_tsimcreated_inv_Mclk_II/FCLK )
  );
  X_IPAD \SCLinc.PAD  (
    .PAD(SCLinc)
  );
  X_BUF \SCLinc_II/UIM_41  (
    .I(SCLinc),
    .O(\SCLinc_II/UIM )
  );
  X_BUF \SCLinc_II/IREG_42  (
    .I(\U11_U1/Line_last ),
    .O(\SCLinc_II/IREG )
  );
  X_FF \U11_U1/Line_last_MC.REG  (
    .I(SCLinc),
    .CE(Vcc),
    .CLK(\U11_U1/Line_last_MC.REG_tsimcreated_inv_Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\U11_U1/Line_last )
  );
  X_INV \U11_U1/Line_last_MC.REG_tsimcreated_inv_Mclk_II/FCLK_43  (
    .I(\Mclk_II/FCLK ),
    .O(\U11_U1/Line_last_MC.REG_tsimcreated_inv_Mclk_II/FCLK )
  );
  X_BUF \SCL_II/UIM_44  (
    .I(SCL),
    .O(\SCL_II/UIM )
  );
  X_BUF \SCL_II/IREG_45  (
    .I(\U11_U2/Line_last ),
    .O(\SCL_II/IREG )
  );
  X_FF \U11_U2/Line_last_MC.REG  (
    .I(SCL),
    .CE(Vcc),
    .CLK(\U11_U2/Line_last_MC.REG_tsimcreated_inv_Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\U11_U2/Line_last )
  );
  X_INV \U11_U2/Line_last_MC.REG_tsimcreated_inv_Mclk_II/FCLK_46  (
    .I(\Mclk_II/FCLK ),
    .O(\U11_U2/Line_last_MC.REG_tsimcreated_inv_Mclk_II/FCLK )
  );
  X_IPAD \I2CS<5>.PAD  (
    .PAD(I2CS[5])
  );
  X_BUF \I2CS<5>_II/UIM_47  (
    .I(I2CS[5]),
    .O(\I2CS<5>_II/UIM )
  );
  X_IPAD \FLS1.PAD  (
    .PAD(FLS1)
  );
  X_BUF \FLS1_II/UIM_48  (
    .I(FLS1),
    .O(\FLS1_II/UIM )
  );
  X_IPAD \Home15FLG.PAD  (
    .PAD(NlwRenamedSig_IO_Home15FLG)
  );
  X_PU Home15FLG_tsimcreated__pullup_ (
    .O(NlwRenamedSig_IO_Home15FLG)
  );
  X_BUF \Home15FLG_II/UIM_49  (
    .I(NlwRenamedSig_IO_Home15FLG),
    .O(\Home15FLG_II/UIM )
  );
  X_BUF \Home15FLG_II/IREG_50  (
    .I(\U4/Flgreg [5]),
    .O(\Home15FLG_II/IREG )
  );
  X_FF \U4/Flgreg<5>_MC.REG  (
    .I(NlwRenamedSig_IO_Home15FLG),
    .CE(\FOOBAR21__ctinst/4 ),
    .CLK(\U4/Flgreg<5>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\U4/Flgreg [5])
  );
  X_INV \U4/Flgreg<5>_MC.REG_tsimcreated_inv_Mclk_II/FCLK_51  (
    .I(\Mclk_II/FCLK ),
    .O(\U4/Flgreg<5>_MC.REG_tsimcreated_inv_Mclk_II/FCLK )
  );
  X_IPAD \Home133FLG.PAD  (
    .PAD(NlwRenamedSig_IO_Home133FLG)
  );
  X_PU Home133FLG_tsimcreated__pullup_ (
    .O(NlwRenamedSig_IO_Home133FLG)
  );
  X_BUF \Home133FLG_II/UIM_52  (
    .I(NlwRenamedSig_IO_Home133FLG),
    .O(\Home133FLG_II/UIM )
  );
  X_BUF \Home133FLG_II/IREG_53  (
    .I(\U4/Flgreg [4]),
    .O(\Home133FLG_II/IREG )
  );
  X_FF \U4/Flgreg<4>_MC.REG  (
    .I(NlwRenamedSig_IO_Home133FLG),
    .CE(\FOOBAR21__ctinst/4 ),
    .CLK(\U4/Flgreg<4>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\U4/Flgreg [4])
  );
  X_INV \U4/Flgreg<4>_MC.REG_tsimcreated_inv_Mclk_II/FCLK_54  (
    .I(\Mclk_II/FCLK ),
    .O(\U4/Flgreg<4>_MC.REG_tsimcreated_inv_Mclk_II/FCLK )
  );
  X_IPAD \Home05FLG.PAD  (
    .PAD(NlwRenamedSig_IO_Home05FLG)
  );
  X_PU Home05FLG_tsimcreated__pullup_ (
    .O(NlwRenamedSig_IO_Home05FLG)
  );
  X_BUF \Home05FLG_II/UIM_55  (
    .I(NlwRenamedSig_IO_Home05FLG),
    .O(\Home05FLG_II/UIM )
  );
  X_BUF \Home05FLG_II/IREG_56  (
    .I(\U4/Flgreg [1]),
    .O(\Home05FLG_II/IREG )
  );
  X_FF \U4/Flgreg<1>_MC.REG  (
    .I(NlwRenamedSig_IO_Home05FLG),
    .CE(\FOOBAR21__ctinst/4 ),
    .CLK(\U4/Flgreg<1>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\U4/Flgreg [1])
  );
  X_INV \U4/Flgreg<1>_MC.REG_tsimcreated_inv_Mclk_II/FCLK_57  (
    .I(\Mclk_II/FCLK ),
    .O(\U4/Flgreg<1>_MC.REG_tsimcreated_inv_Mclk_II/FCLK )
  );
  X_IPAD \Home033FLG.PAD  (
    .PAD(NlwRenamedSig_IO_Home033FLG)
  );
  X_PU Home033FLG_tsimcreated__pullup_ (
    .O(NlwRenamedSig_IO_Home033FLG)
  );
  X_BUF \Home033FLG_II/UIM_58  (
    .I(NlwRenamedSig_IO_Home033FLG),
    .O(\Home033FLG_II/UIM )
  );
  X_BUF \Home033FLG_II/IREG_59  (
    .I(\U4/Flgreg [0]),
    .O(\Home033FLG_II/IREG )
  );
  X_FF \U4/Flgreg<0>_MC.REG  (
    .I(NlwRenamedSig_IO_Home033FLG),
    .CE(\FOOBAR21__ctinst/4 ),
    .CLK(\U4/Flgreg<0>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\U4/Flgreg [0])
  );
  X_INV \U4/Flgreg<0>_MC.REG_tsimcreated_inv_Mclk_II/FCLK_60  (
    .I(\Mclk_II/FCLK ),
    .O(\U4/Flgreg<0>_MC.REG_tsimcreated_inv_Mclk_II/FCLK )
  );
  X_IPAD \Enc15FLG.PAD  (
    .PAD(NlwRenamedSig_IO_Enc15FLG)
  );
  X_PU Enc15FLG_tsimcreated__pullup_ (
    .O(NlwRenamedSig_IO_Enc15FLG)
  );
  X_BUF \Enc15FLG_II/UIM_61  (
    .I(NlwRenamedSig_IO_Enc15FLG),
    .O(\Enc15FLG_II/UIM )
  );
  X_BUF \Enc15FLG_II/IREG_62  (
    .I(\U4/Flgreg [7]),
    .O(\Enc15FLG_II/IREG )
  );
  X_FF \U4/Flgreg<7>_MC.REG  (
    .I(NlwRenamedSig_IO_Enc15FLG),
    .CE(\FOOBAR24__ctinst/4 ),
    .CLK(\U4/Flgreg<7>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\U4/Flgreg [7])
  );
  X_INV \U4/Flgreg<7>_MC.REG_tsimcreated_inv_Mclk_II/FCLK_63  (
    .I(\Mclk_II/FCLK ),
    .O(\U4/Flgreg<7>_MC.REG_tsimcreated_inv_Mclk_II/FCLK )
  );
  X_IPAD \Enc133FLG.PAD  (
    .PAD(NlwRenamedSig_IO_Enc133FLG)
  );
  X_PU Enc133FLG_tsimcreated__pullup_ (
    .O(NlwRenamedSig_IO_Enc133FLG)
  );
  X_BUF \Enc133FLG_II/UIM_64  (
    .I(NlwRenamedSig_IO_Enc133FLG),
    .O(\Enc133FLG_II/UIM )
  );
  X_BUF \Enc133FLG_II/IREG_65  (
    .I(\U4/Flgreg [6]),
    .O(\Enc133FLG_II/IREG )
  );
  X_FF \U4/Flgreg<6>_MC.REG  (
    .I(NlwRenamedSig_IO_Enc133FLG),
    .CE(\FOOBAR24__ctinst/4 ),
    .CLK(\U4/Flgreg<6>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\U4/Flgreg [6])
  );
  X_INV \U4/Flgreg<6>_MC.REG_tsimcreated_inv_Mclk_II/FCLK_66  (
    .I(\Mclk_II/FCLK ),
    .O(\U4/Flgreg<6>_MC.REG_tsimcreated_inv_Mclk_II/FCLK )
  );
  X_IPAD \Enc05FLG.PAD  (
    .PAD(NlwRenamedSig_IO_Enc05FLG)
  );
  X_PU Enc05FLG_tsimcreated__pullup_ (
    .O(NlwRenamedSig_IO_Enc05FLG)
  );
  X_BUF \Enc05FLG_II/UIM_67  (
    .I(NlwRenamedSig_IO_Enc05FLG),
    .O(\Enc05FLG_II/UIM )
  );
  X_BUF \Enc05FLG_II/IREG_68  (
    .I(\U4/Flgreg [3]),
    .O(\Enc05FLG_II/IREG )
  );
  X_FF \U4/Flgreg<3>_MC.REG  (
    .I(NlwRenamedSig_IO_Enc05FLG),
    .CE(\FOOBAR24__ctinst/4 ),
    .CLK(\U4/Flgreg<3>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\U4/Flgreg [3])
  );
  X_INV \U4/Flgreg<3>_MC.REG_tsimcreated_inv_Mclk_II/FCLK_69  (
    .I(\Mclk_II/FCLK ),
    .O(\U4/Flgreg<3>_MC.REG_tsimcreated_inv_Mclk_II/FCLK )
  );
  X_IPAD \Enc033FLG.PAD  (
    .PAD(NlwRenamedSig_IO_Enc033FLG)
  );
  X_PU Enc033FLG_tsimcreated__pullup_ (
    .O(NlwRenamedSig_IO_Enc033FLG)
  );
  X_BUF \Enc033FLG_II/UIM_70  (
    .I(NlwRenamedSig_IO_Enc033FLG),
    .O(\Enc033FLG_II/UIM )
  );
  X_BUF \Enc033FLG_II/IREG_71  (
    .I(\U4/Flgreg [2]),
    .O(\Enc033FLG_II/IREG )
  );
  X_FF \U4/Flgreg<2>_MC.REG  (
    .I(NlwRenamedSig_IO_Enc033FLG),
    .CE(\FOOBAR24__ctinst/4 ),
    .CLK(\U4/Flgreg<2>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\U4/Flgreg [2])
  );
  X_INV \U4/Flgreg<2>_MC.REG_tsimcreated_inv_Mclk_II/FCLK_72  (
    .I(\Mclk_II/FCLK ),
    .O(\U4/Flgreg<2>_MC.REG_tsimcreated_inv_Mclk_II/FCLK )
  );
  X_IPAD \PhaseA_Encoder0.PAD  (
    .PAD(PhaseA_Encoder0)
  );
  X_BUF \PhaseA_Encoder0_II/UIM_73  (
    .I(PhaseA_Encoder0),
    .O(\PhaseA_Encoder0_II/UIM )
  );
  X_IPAD \PhaseB_Encoder0.PAD  (
    .PAD(PhaseB_Encoder0)
  );
  X_BUF \PhaseB_Encoder0_II/UIM_74  (
    .I(PhaseB_Encoder0),
    .O(\PhaseB_Encoder0_II/UIM )
  );
  X_IPAD \PhaseB_Encoder1.PAD  (
    .PAD(PhaseB_Encoder1)
  );
  X_BUF \PhaseB_Encoder1_II/UIM_75  (
    .I(PhaseB_Encoder1),
    .O(\PhaseB_Encoder1_II/UIM )
  );
  X_IPAD \PhaseA_Encoder1.PAD  (
    .PAD(PhaseA_Encoder1)
  );
  X_BUF \PhaseA_Encoder1_II/UIM_76  (
    .I(PhaseA_Encoder1),
    .O(\PhaseA_Encoder1_II/UIM )
  );
  X_IPAD \GP_Motor0_0.PAD  (
    .PAD(GP_Motor0_0)
  );
  X_BUF \GP_Motor0_0_II/UIM_77  (
    .I(GP_Motor0_0),
    .O(\GP_Motor0_0_II/UIM )
  );
  X_BUF \GP_Motor0_0_II/IREG_78  (
    .I(\U1/U4/InEdge0r ),
    .O(\GP_Motor0_0_II/IREG )
  );
  X_FF \U1/U4/InEdge0r_MC.REG  (
    .I(GP_Motor0_0),
    .CE(Vcc),
    .CLK(\U1/U4/InEdge0r_MC.REG_tsimcreated_inv_Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\U1/U4/InEdge0r )
  );
  X_INV \U1/U4/InEdge0r_MC.REG_tsimcreated_inv_Mclk_II/FCLK_79  (
    .I(\Mclk_II/FCLK ),
    .O(\U1/U4/InEdge0r_MC.REG_tsimcreated_inv_Mclk_II/FCLK )
  );
  X_IPAD \GP_Motor1_0.PAD  (
    .PAD(GP_Motor1_0)
  );
  X_BUF \GP_Motor1_0_II/UIM_80  (
    .I(GP_Motor1_0),
    .O(\GP_Motor1_0_II/UIM )
  );
  X_BUF \GP_Motor1_0_II/IREG_81  (
    .I(\U1/U4/InEdge1r ),
    .O(\GP_Motor1_0_II/IREG )
  );
  X_FF \U1/U4/InEdge1r_MC.REG  (
    .I(GP_Motor1_0),
    .CE(Vcc),
    .CLK(\U1/U4/InEdge1r_MC.REG_tsimcreated_inv_Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\U1/U4/InEdge1r )
  );
  X_INV \U1/U4/InEdge1r_MC.REG_tsimcreated_inv_Mclk_II/FCLK_82  (
    .I(\Mclk_II/FCLK ),
    .O(\U1/U4/InEdge1r_MC.REG_tsimcreated_inv_Mclk_II/FCLK )
  );
  X_IPAD \Brake0.PAD  (
    .PAD(Brake0)
  );
  X_BUF \Brake0_II/UIM_83  (
    .I(Brake0),
    .O(\Brake0_II/UIM )
  );
  X_IPAD \Brake1.PAD  (
    .PAD(Brake1)
  );
  X_BUF \Brake1_II/UIM_84  (
    .I(Brake1),
    .O(\Brake1_II/UIM )
  );
  X_IPAD \DIR0.PAD  (
    .PAD(DIR0)
  );
  X_BUF \DIR0_II/UIM_85  (
    .I(DIR0),
    .O(\DIR0_II/UIM )
  );
  X_IPAD \DIR1.PAD  (
    .PAD(DIR1)
  );
  X_BUF \DIR1_II/UIM_86  (
    .I(DIR1),
    .O(\DIR1_II/UIM )
  );
  X_IPAD \FLS0.PAD  (
    .PAD(FLS0)
  );
  X_BUF \FLS0_II/UIM_87  (
    .I(FLS0),
    .O(\FLS0_II/UIM )
  );
  X_IPAD \PWM5.PAD  (
    .PAD(PWM5)
  );
  X_BUF \PWM5_II/UIM_88  (
    .I(PWM5),
    .O(\PWM5_II/UIM )
  );
  X_IPAD \PWM3.PAD  (
    .PAD(PWM3)
  );
  X_BUF \PWM3_II/UIM_89  (
    .I(PWM3),
    .O(\PWM3_II/UIM )
  );
  X_IPAD \HSI.PAD  (
    .PAD(HSI)
  );
  X_BUF \HSI_II/UIM_90  (
    .I(HSI),
    .O(\HSI_II/UIM )
  );
  X_IPAD \MHSO.PAD  (
    .PAD(MHSO)
  );
  X_BUF \MHSO_II/UIM_91  (
    .I(MHSO),
    .O(\MHSO_II/UIM )
  );
  X_IPAD \I2CS<0>.PAD  (
    .PAD(I2CS[0])
  );
  X_BUF \I2CS<0>_II/UIM_92  (
    .I(I2CS[0]),
    .O(\I2CS<0>_II/UIM )
  );
  X_IPAD \I2CS<1>.PAD  (
    .PAD(I2CS[1])
  );
  X_BUF \I2CS<1>_II/UIM_93  (
    .I(I2CS[1]),
    .O(\I2CS<1>_II/UIM )
  );
  X_IPAD \I2CS<2>.PAD  (
    .PAD(I2CS[2])
  );
  X_BUF \I2CS<2>_II/UIM_94  (
    .I(I2CS[2]),
    .O(\I2CS<2>_II/UIM )
  );
  X_IPAD \I2CS<3>.PAD  (
    .PAD(I2CS[3])
  );
  X_BUF \I2CS<3>_II/UIM_95  (
    .I(I2CS[3]),
    .O(\I2CS<3>_II/UIM )
  );
  X_IPAD \I2CS<4>.PAD  (
    .PAD(I2CS[4])
  );
  X_BUF \I2CS<4>_II/UIM_96  (
    .I(I2CS[4]),
    .O(\I2CS<4>_II/UIM )
  );
  X_IPAD \INTbus.PAD  (
    .PAD(INTbus)
  );
  X_BUF \INTbus_II/UIM_97  (
    .I(INTbus),
    .O(\INTbus_II/UIM )
  );
  X_IPAD \RLS0.PAD  (
    .PAD(RLS0)
  );
  X_BUF \RLS0_II/UIM_98  (
    .I(RLS0),
    .O(\RLS0_II/UIM )
  );
  X_IPAD \RLS1.PAD  (
    .PAD(RLS1)
  );
  X_BUF \RLS1_II/UIM_99  (
    .I(RLS1),
    .O(\RLS1_II/UIM )
  );
  X_IPAD \LightSense.PAD  (
    .PAD(LightSense)
  );
  X_BUF \LightSense_II/UIM_100  (
    .I(LightSense),
    .O(\LightSense_II/UIM )
  );
  X_IPAD \TXI.PAD  (
    .PAD(TXI)
  );
  X_BUF \TXI_II/UIM_101  (
    .I(TXI),
    .O(\TXI_II/UIM )
  );
  X_IPAD \PWM1.PAD  (
    .PAD(PWM1)
  );
  X_BUF \PWM1_II/UIM_102  (
    .I(PWM1),
    .O(\PWM1_II/UIM )
  );
  X_IPAD \PWM2.PAD  (
    .PAD(PWM2)
  );
  X_BUF \PWM2_II/UIM_103  (
    .I(PWM2),
    .O(\PWM2_II/UIM )
  );
  X_IPAD \Home0.PAD  (
    .PAD(Home0)
  );
  X_BUF \Home0_II/UIM_104  (
    .I(Home0),
    .O(\Home0_II/UIM )
  );
  X_BUF \Home0_II/IREG_105  (
    .I(\U1/U4/HE0stater ),
    .O(\Home0_II/IREG )
  );
  X_FF \U1/U4/HE0stater_MC.REG  (
    .I(Home0),
    .CE(Vcc),
    .CLK(\U1/U4/HE0stater_MC.REG_tsimcreated_inv_Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\U1/U4/HE0stater )
  );
  X_INV \U1/U4/HE0stater_MC.REG_tsimcreated_inv_Mclk_II/FCLK_106  (
    .I(\Mclk_II/FCLK ),
    .O(\U1/U4/HE0stater_MC.REG_tsimcreated_inv_Mclk_II/FCLK )
  );
  X_IPAD \Home1.PAD  (
    .PAD(Home1)
  );
  X_BUF \Home1_II/UIM_107  (
    .I(Home1),
    .O(\Home1_II/UIM )
  );
  X_BUF \Home1_II/IREG_108  (
    .I(\U1/U4/HE1stater ),
    .O(\Home1_II/IREG )
  );
  X_FF \U1/U4/HE1stater_MC.REG  (
    .I(Home1),
    .CE(Vcc),
    .CLK(\U1/U4/HE1stater_MC.REG_tsimcreated_inv_Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\U1/U4/HE1stater )
  );
  X_INV \U1/U4/HE1stater_MC.REG_tsimcreated_inv_Mclk_II/FCLK_109  (
    .I(\Mclk_II/FCLK ),
    .O(\U1/U4/HE1stater_MC.REG_tsimcreated_inv_Mclk_II/FCLK )
  );
  X_BPAD \AD<5>.PAD  (
    .PAD(AD[5])
  );
  X_TRI \AD<5>  (
    .I(\AD<5>_MC.Q ),
    .CTL(\AD<5>_MC.OE ),
    .O(AD[5])
  );
  X_OPAD \Enc033ctrl.PAD  (
    .PAD(Enc033ctrl)
  );
  X_BUF Enc033ctrl_110 (
    .I(\Enc033ctrl_MC.Q ),
    .O(Enc033ctrl)
  );
  X_OPAD \Enc05ctrl.PAD  (
    .PAD(Enc05ctrl)
  );
  X_BUF Enc05ctrl_111 (
    .I(\Enc05ctrl_MC.Q ),
    .O(Enc05ctrl)
  );
  X_OPAD \Enc133ctrl.PAD  (
    .PAD(Enc133ctrl)
  );
  X_BUF Enc133ctrl_112 (
    .I(\Enc133ctrl_MC.Q ),
    .O(Enc133ctrl)
  );
  X_OPAD \Enc15ctrl.PAD  (
    .PAD(Enc15ctrl)
  );
  X_BUF Enc15ctrl_113 (
    .I(\Enc15ctrl_MC.Q ),
    .O(Enc15ctrl)
  );
  X_OPAD \GPIO8.PAD  (
    .PAD(GPIO8)
  );
  X_BUF GPIO8_114 (
    .I(\GPIO8_MC.Q ),
    .O(GPIO8)
  );
  X_OPAD \GPIO9.PAD  (
    .PAD(GPIO9)
  );
  X_BUF GPIO9_115 (
    .I(\GPIO9_MC.Q ),
    .O(GPIO9)
  );
  X_OPAD \GP_Motor0_1.PAD  (
    .PAD(GP_Motor0_1)
  );
  X_BUF GP_Motor0_1_116 (
    .I(\GP_Motor0_1_MC.Q ),
    .O(GP_Motor0_1)
  );
  X_OPAD \GP_Motor1_1.PAD  (
    .PAD(GP_Motor1_1)
  );
  X_BUF GP_Motor1_1_117 (
    .I(\GP_Motor1_1_MC.Q ),
    .O(GP_Motor1_1)
  );
  X_OPAD \HSO.PAD  (
    .PAD(HSO)
  );
  X_BUF HSO_118 (
    .I(\HSO_MC.Q ),
    .O(HSO)
  );
  X_OPAD \Home033ctrl.PAD  (
    .PAD(Home033ctrl)
  );
  X_BUF Home033ctrl_119 (
    .I(\Home033ctrl_MC.Q ),
    .O(Home033ctrl)
  );
  X_OPAD \Home05ctrl.PAD  (
    .PAD(Home05ctrl)
  );
  X_BUF Home05ctrl_120 (
    .I(\Home05ctrl_MC.Q ),
    .O(Home05ctrl)
  );
  X_OPAD \Home133ctrl.PAD  (
    .PAD(Home133ctrl)
  );
  X_BUF Home133ctrl_121 (
    .I(\Home133ctrl_MC.Q ),
    .O(Home133ctrl)
  );
  X_OPAD \Home15ctrl.PAD  (
    .PAD(Home15ctrl)
  );
  X_BUF Home15ctrl_122 (
    .I(\Home15ctrl_MC.Q ),
    .O(Home15ctrl)
  );
  X_OPAD \INT.PAD  (
    .PAD(INT)
  );
  X_BUF INT_123 (
    .I(\INT_MC.Q ),
    .O(INT)
  );
  X_OPAD \LED1.PAD  (
    .PAD(LED1)
  );
  X_BUF LED1_124 (
    .I(\LED1_MC.Q ),
    .O(LED1)
  );
  X_OPAD \LED2.PAD  (
    .PAD(LED2)
  );
  X_BUF LED2_125 (
    .I(\LED2_MC.Q ),
    .O(LED2)
  );
  X_OPAD \LED3.PAD  (
    .PAD(LED3)
  );
  X_BUF LED3_126 (
    .I(\LED3_MC.Q ),
    .O(LED3)
  );
  X_OPAD \LED4.PAD  (
    .PAD(LED4)
  );
  X_BUF LED4_127 (
    .I(\LED4_MC.Q ),
    .O(LED4)
  );
  X_OPAD \LED5.PAD  (
    .PAD(LED5)
  );
  X_BUF LED5_128 (
    .I(\LED5_MC.Q ),
    .O(LED5)
  );
  X_OPAD \MHSI.PAD  (
    .PAD(MHSI)
  );
  X_BUF MHSI_129 (
    .I(\MHSI_MC.Q ),
    .O(MHSI)
  );
  X_OPAD \MTRpwr.PAD  (
    .PAD(MTRpwr)
  );
  X_BUF MTRpwr_130 (
    .I(\MTRpwr_MC.Q ),
    .O(MTRpwr)
  );
  X_OPAD \MTRpwrn.PAD  (
    .PAD(MTRpwrn)
  );
  X_BUF MTRpwrn_131 (
    .I(\MTRpwrn_MC.Q ),
    .O(MTRpwrn)
  );
  X_OPAD \MTXI.PAD  (
    .PAD(MTXI)
  );
  X_BUF MTXI_132 (
    .I(\MTXI_MC.Q ),
    .O(MTXI)
  );
  X_OPAD \PAH0.PAD  (
    .PAD(PAH0)
  );
  X_BUF PAH0_133 (
    .I(\PAH0_MC.Q ),
    .O(PAH0)
  );
  X_OPAD \PAH1.PAD  (
    .PAD(PAH1)
  );
  X_BUF PAH1_134 (
    .I(\PAH1_MC.Q ),
    .O(PAH1)
  );
  X_OPAD \PAL0.PAD  (
    .PAD(PAL0)
  );
  X_BUF PAL0_135 (
    .I(\PAL0_MC.Q ),
    .O(PAL0)
  );
  X_OPAD \PAL1.PAD  (
    .PAD(PAL1)
  );
  X_BUF PAL1_136 (
    .I(\PAL1_MC.Q ),
    .O(PAL1)
  );
  X_OPAD \PBH0.PAD  (
    .PAD(PBH0)
  );
  X_BUF PBH0_137 (
    .I(\PBH0_MC.Q ),
    .O(PBH0)
  );
  X_OPAD \PBH1.PAD  (
    .PAD(PBH1)
  );
  X_BUF PBH1_138 (
    .I(\PBH1_MC.Q ),
    .O(PBH1)
  );
  X_OPAD \PBL0.PAD  (
    .PAD(PBL0)
  );
  X_BUF PBL0_139 (
    .I(\PBL0_MC.Q ),
    .O(PBL0)
  );
  X_OPAD \PBL1.PAD  (
    .PAD(PBL1)
  );
  X_BUF PBL1_140 (
    .I(\PBL1_MC.Q ),
    .O(PBL1)
  );
  X_OPAD \PresEn.PAD  (
    .PAD(PresEn)
  );
  X_BUF PresEn_141 (
    .I(\PresEn_MC.Q ),
    .O(PresEn)
  );
  X_OPAD \PresSlct.PAD  (
    .PAD(PresSlct)
  );
  X_BUF PresSlct_142 (
    .I(\PresSlct_MC.Q ),
    .O(PresSlct)
  );
  X_OPAD \SCLout.PAD  (
    .PAD(SCLout)
  );
  X_BUF SCLout_143 (
    .I(\SCLout_MC.Q ),
    .O(SCLout)
  );
  X_OPAD \TP10.PAD  (
    .PAD(TP10)
  );
  X_BUF TP10_144 (
    .I(\TP10_MC.Q ),
    .O(TP10)
  );
  X_OPAD \TP11.PAD  (
    .PAD(TP11)
  );
  X_BUF TP11_145 (
    .I(\TP11_MC.Q ),
    .O(TP11)
  );
  X_OPAD \TP12.PAD  (
    .PAD(TP12)
  );
  X_BUF TP12_146 (
    .I(\TP12_MC.Q ),
    .O(TP12)
  );
  X_OPAD \TmpEn.PAD  (
    .PAD(TmpEn)
  );
  X_BUF TmpEn_147 (
    .I(\TmpEn_MC.Q ),
    .O(TmpEn)
  );
  X_OPAD \TmpSlct.PAD  (
    .PAD(TmpSlct)
  );
  X_BUF TmpSlct_148 (
    .I(\TmpSlct_MC.Q ),
    .O(TmpSlct)
  );
  X_BPAD \SCL.PAD  (
    .PAD(SCL)
  );
  X_TRI SCL_149 (
    .I(\U11_U2/Line_last_MC.Q ),
    .CTL(\U11_U2/Line_last_MC.OE ),
    .O(SCL)
  );
  X_BPAD \AD<2>.PAD  (
    .PAD(AD[2])
  );
  X_TRI \AD<2>  (
    .I(\U4/ctrlr<2>_MC.Q ),
    .CTL(\U4/ctrlr<2>_MC.OE ),
    .O(AD[2])
  );
  X_BPAD \AD<3>.PAD  (
    .PAD(AD[3])
  );
  X_TRI \AD<3>  (
    .I(\U4/ctrlr<3>_MC.Q ),
    .CTL(\U4/ctrlr<3>_MC.OE ),
    .O(AD[3])
  );
  X_BPAD \AD<6>.PAD  (
    .PAD(AD[6])
  );
  X_TRI \AD<6>  (
    .I(\U4/ctrlr<6>_MC.Q ),
    .CTL(\U4/ctrlr<6>_MC.OE ),
    .O(AD[6])
  );
  X_BPAD \AD<7>.PAD  (
    .PAD(AD[7])
  );
  X_TRI \AD<7>  (
    .I(\U4/ctrlr<7>_MC.Q ),
    .CTL(\U4/ctrlr<7>_MC.OE ),
    .O(AD[7])
  );
  X_BPAD \AD<0>.PAD  (
    .PAD(AD[0])
  );
  X_TRI \AD<0>  (
    .I(\U9/MISCr<0>_MC.Q ),
    .CTL(\U9/MISCr<0>_MC.OE ),
    .O(AD[0])
  );
  X_BPAD \AD<1>.PAD  (
    .PAD(AD[1])
  );
  X_TRI \AD<1>  (
    .I(\U9/MISCr<1>_MC.Q ),
    .CTL(\U9/MISCr<1>_MC.OE ),
    .O(AD[1])
  );
  X_BPAD \AD<4>.PAD  (
    .PAD(AD[4])
  );
  X_TRI \AD<4>  (
    .I(\U9/MISCr<4>_MC.Q ),
    .CTL(\U9/MISCr<4>_MC.OE ),
    .O(AD[4])
  );
  X_BUF \AD<5>_MC.Q_150  (
    .I(\AD<5>_MC.Q_tsimrenamed_net_ ),
    .O(\AD<5>_MC.Q )
  );
  X_BUF \AD<5>_MC.OE_151  (
    .I(\AD<5>_MC.BUFOE.OUT ),
    .O(\AD<5>_MC.OE )
  );
  X_BUF \AD<5>_MC.BUFOE.OUT_152  (
    .I(\FOOBAR1__ctinst/7 ),
    .O(\AD<5>_MC.BUFOE.OUT )
  );
  X_BUF \AD<5>_MC.Q_tsimrenamed_net__153  (
    .I(\AD<5>_MC.D ),
    .O(\AD<5>_MC.Q_tsimrenamed_net_ )
  );
  X_XOR2 \AD<5>_MC.D_154  (
    .I0(\NlwInverterSignal_AD<5>_MC.D/IN0 ),
    .I1(\AD<5>_MC.D2 ),
    .O(\AD<5>_MC.D )
  );
  X_ZERO \AD<5>_MC.D1_155  (
    .O(\AD<5>_MC.D1 )
  );
  X_AND2 \AD<5>_MC.D2_PT_0_156  (
    .I0(DCORI2CCNTr),
    .I1(\NlwInverterSignal_AD<5>_MC.D2_PT_0/IN1 ),
    .O(\AD<5>_MC.D2_PT_0 )
  );
  X_AND2 \AD<5>_MC.D2_PT_1_157  (
    .I0(DCORCONFIGr),
    .I1(\NlwInverterSignal_AD<5>_MC.D2_PT_1/IN1 ),
    .O(\AD<5>_MC.D2_PT_1 )
  );
  X_AND2 \AD<5>_MC.D2_PT_2_158  (
    .I0(DCORLIMITSr),
    .I1(\NlwInverterSignal_AD<5>_MC.D2_PT_2/IN1 ),
    .O(\AD<5>_MC.D2_PT_2 )
  );
  X_AND2 \AD<5>_MC.D2_PT_3_159  (
    .I0(DCORENCPWRr),
    .I1(\NlwInverterSignal_AD<5>_MC.D2_PT_3/IN1 ),
    .O(\AD<5>_MC.D2_PT_3 )
  );
  X_AND2 \AD<5>_MC.D2_PT_4_160  (
    .I0(\NlwInverterSignal_AD<5>_MC.D2_PT_4/IN0 ),
    .I1(\NlwInverterSignal_AD<5>_MC.D2_PT_4/IN1 ),
    .O(\AD<5>_MC.D2_PT_4 )
  );
  X_AND2 \AD<5>_MC.D2_PT_5_161  (
    .I0(\NlwInverterSignal_AD<5>_MC.D2_PT_5/IN0 ),
    .I1(\NlwInverterSignal_AD<5>_MC.D2_PT_5/IN1 ),
    .O(\AD<5>_MC.D2_PT_5 )
  );
  X_OR6 \AD<5>_MC.D2_162  (
    .I0(\AD<5>_MC.D2_PT_0 ),
    .I1(\AD<5>_MC.D2_PT_1 ),
    .I2(\AD<5>_MC.D2_PT_2 ),
    .I3(\AD<5>_MC.D2_PT_3 ),
    .I4(\AD<5>_MC.D2_PT_4 ),
    .I5(\AD<5>_MC.D2_PT_5 ),
    .O(\AD<5>_MC.D2 )
  );
  X_BUF DCORI2CCNTr_163 (
    .I(\DCORI2CCNTr_MC.Q ),
    .O(DCORI2CCNTr)
  );
  X_BUF \DCORI2CCNTr_MC.Q_164  (
    .I(\DCORI2CCNTr_MC.D ),
    .O(\DCORI2CCNTr_MC.Q )
  );
  X_XOR2 \DCORI2CCNTr_MC.D_165  (
    .I0(\DCORI2CCNTr_MC.D1 ),
    .I1(\DCORI2CCNTr_MC.D2 ),
    .O(\DCORI2CCNTr_MC.D )
  );
  X_AND16 \DCORI2CCNTr_MC.D1_166  (
    .I0(\WR_II/UIM ),
    .I1(\NlwInverterSignal_DCORI2CCNTr_MC.D1/IN1 ),
    .I2(\NlwInverterSignal_DCORI2CCNTr_MC.D1/IN2 ),
    .I3(\NlwInverterSignal_DCORI2CCNTr_MC.D1/IN3 ),
    .I4(\NlwInverterSignal_DCORI2CCNTr_MC.D1/IN4 ),
    .I5(\NlwInverterSignal_DCORI2CCNTr_MC.D1/IN5 ),
    .I6(\NlwInverterSignal_DCORI2CCNTr_MC.D1/IN6 ),
    .I7(\NlwInverterSignal_DCORI2CCNTr_MC.D1/IN7 ),
    .I8(\NlwInverterSignal_DCORI2CCNTr_MC.D1/IN8 ),
    .I9(\NlwInverterSignal_DCORI2CCNTr_MC.D1/IN9 ),
    .I10(Vcc),
    .I11(Vcc),
    .I12(Vcc),
    .I13(Vcc),
    .I14(Vcc),
    .I15(Vcc),
    .O(\DCORI2CCNTr_MC.D1 )
  );
  X_ZERO \DCORI2CCNTr_MC.D2_167  (
    .O(\DCORI2CCNTr_MC.D2 )
  );
  X_BUF \U2_ADDR_reg<0>  (
    .I(\U2_ADDR_reg<0>_MC.Q ),
    .O(U2_ADDR_reg[0])
  );
  X_XOR2 \U2_ADDR_reg<0>_MC_tsimcreated_xor__168  (
    .I0(\U2_ADDR_reg<0>_MC.D ),
    .I1(\U2_ADDR_reg<0>_MC.Q ),
    .O(\U2_ADDR_reg<0>_MC_tsimcreated_xor_ )
  );
  X_FF \U2_ADDR_reg<0>_MC.REG  (
    .I(\U2_ADDR_reg<0>_MC_tsimcreated_xor_ ),
    .CE(Vcc),
    .CLK(\U2_ADDR_reg<0>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\U2_ADDR_reg<0>_MC.Q )
  );
  X_INV \U2_ADDR_reg<0>_MC.REG_tsimcreated_inv_Mclk_II/FCLK_169  (
    .I(\Mclk_II/FCLK ),
    .O(\U2_ADDR_reg<0>_MC.REG_tsimcreated_inv_Mclk_II/FCLK )
  );
  X_XOR2 \U2_ADDR_reg<0>_MC.D_170  (
    .I0(\U2_ADDR_reg<0>_MC.D1 ),
    .I1(\U2_ADDR_reg<0>_MC.D2 ),
    .O(\U2_ADDR_reg<0>_MC.D )
  );
  X_ZERO \U2_ADDR_reg<0>_MC.D1_171  (
    .O(\U2_ADDR_reg<0>_MC.D1 )
  );
  X_AND2 \U2_ADDR_reg<0>_MC.D2_PT_0_172  (
    .I0(U2_ADDR_reg[0]),
    .I1(\NlwInverterSignal_U2_ADDR_reg<0>_MC.D2_PT_0/IN1 ),
    .O(\U2_ADDR_reg<0>_MC.D2_PT_0 )
  );
  X_AND6 \U2_ADDR_reg<0>_MC.D2_PT_1_173  (
    .I0(\WR_II/UIM ),
    .I1(\RD_II/UIM ),
    .I2(U2_ADDR_reg[0]),
    .I3(\NlwInverterSignal_U2_ADDR_reg<0>_MC.D2_PT_1/IN3 ),
    .I4(\NlwInverterSignal_U2_ADDR_reg<0>_MC.D2_PT_1/IN4 ),
    .I5(U2_ASedge),
    .O(\U2_ADDR_reg<0>_MC.D2_PT_1 )
  );
  X_AND7 \U2_ADDR_reg<0>_MC.D2_PT_2_174  (
    .I0(\WR_II/UIM ),
    .I1(\RD_II/UIM ),
    .I2(\NlwInverterSignal_U2_ADDR_reg<0>_MC.D2_PT_2/IN2 ),
    .I3(\MSPReset_II/UIM ),
    .I4(\AD<0>_II/UIM ),
    .I5(\NlwInverterSignal_U2_ADDR_reg<0>_MC.D2_PT_2/IN5 ),
    .I6(U2_ASedge),
    .O(\U2_ADDR_reg<0>_MC.D2_PT_2 )
  );
  X_AND16 \U2_ADDR_reg<0>_MC.D2_PT_3_175  (
    .I0(\WR_II/UIM ),
    .I1(\RD_II/UIM ),
    .I2(\NlwInverterSignal_U2_ADDR_reg<0>_MC.D2_PT_3/IN2 ),
    .I3(\NlwInverterSignal_U2_ADDR_reg<0>_MC.D2_PT_3/IN3 ),
    .I4(\NlwInverterSignal_U2_ADDR_reg<0>_MC.D2_PT_3/IN4 ),
    .I5(\NlwInverterSignal_U2_ADDR_reg<0>_MC.D2_PT_3/IN5 ),
    .I6(U2_AutoInc),
    .I7(\NlwInverterSignal_U2_ADDR_reg<0>_MC.D2_PT_3/IN7 ),
    .I8(N_PZ_938),
    .I9(Vcc),
    .I10(Vcc),
    .I11(Vcc),
    .I12(Vcc),
    .I13(Vcc),
    .I14(Vcc),
    .I15(Vcc),
    .O(\U2_ADDR_reg<0>_MC.D2_PT_3 )
  );
  X_OR4 \U2_ADDR_reg<0>_MC.D2_176  (
    .I0(\U2_ADDR_reg<0>_MC.D2_PT_0 ),
    .I1(\U2_ADDR_reg<0>_MC.D2_PT_1 ),
    .I2(\U2_ADDR_reg<0>_MC.D2_PT_2 ),
    .I3(\U2_ADDR_reg<0>_MC.D2_PT_3 ),
    .O(\U2_ADDR_reg<0>_MC.D2 )
  );
  X_BUF \U2_ADDR_reg<4>  (
    .I(\U2_ADDR_reg<4>_MC.Q ),
    .O(U2_ADDR_reg[4])
  );
  X_XOR2 \U2_ADDR_reg<4>_MC_tsimcreated_xor__177  (
    .I0(\U2_ADDR_reg<4>_MC.D ),
    .I1(\U2_ADDR_reg<4>_MC.Q ),
    .O(\U2_ADDR_reg<4>_MC_tsimcreated_xor_ )
  );
  X_FF \U2_ADDR_reg<4>_MC.REG  (
    .I(\U2_ADDR_reg<4>_MC_tsimcreated_xor_ ),
    .CE(Vcc),
    .CLK(\U2_ADDR_reg<4>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\U2_ADDR_reg<4>_MC.Q )
  );
  X_INV \U2_ADDR_reg<4>_MC.REG_tsimcreated_inv_Mclk_II/FCLK_178  (
    .I(\Mclk_II/FCLK ),
    .O(\U2_ADDR_reg<4>_MC.REG_tsimcreated_inv_Mclk_II/FCLK )
  );
  X_XOR2 \U2_ADDR_reg<4>_MC.D_179  (
    .I0(\U2_ADDR_reg<4>_MC.D1 ),
    .I1(\U2_ADDR_reg<4>_MC.D2 ),
    .O(\U2_ADDR_reg<4>_MC.D )
  );
  X_ZERO \U2_ADDR_reg<4>_MC.D1_180  (
    .O(\U2_ADDR_reg<4>_MC.D1 )
  );
  X_AND2 \U2_ADDR_reg<4>_MC.D2_PT_0_181  (
    .I0(U2_ADDR_reg[4]),
    .I1(\NlwInverterSignal_U2_ADDR_reg<4>_MC.D2_PT_0/IN1 ),
    .O(\U2_ADDR_reg<4>_MC.D2_PT_0 )
  );
  X_AND6 \U2_ADDR_reg<4>_MC.D2_PT_1_182  (
    .I0(\WR_II/UIM ),
    .I1(\RD_II/UIM ),
    .I2(U2_ADDR_reg[4]),
    .I3(\NlwInverterSignal_U2_ADDR_reg<4>_MC.D2_PT_1/IN3 ),
    .I4(U2_ASedge),
    .I5(\NlwInverterSignal_U2_ADDR_reg<4>_MC.D2_PT_1/IN5 ),
    .O(\U2_ADDR_reg<4>_MC.D2_PT_1 )
  );
  X_AND7 \U2_ADDR_reg<4>_MC.D2_PT_2_183  (
    .I0(\WR_II/UIM ),
    .I1(\RD_II/UIM ),
    .I2(\NlwInverterSignal_U2_ADDR_reg<4>_MC.D2_PT_2/IN2 ),
    .I3(\MSPReset_II/UIM ),
    .I4(\NlwInverterSignal_U2_ADDR_reg<4>_MC.D2_PT_2/IN4 ),
    .I5(U2_ASedge),
    .I6(\AD<4>_II/UIM ),
    .O(\U2_ADDR_reg<4>_MC.D2_PT_2 )
  );
  X_OR3 \U2_ADDR_reg<4>_MC.D2_184  (
    .I0(\U2_ADDR_reg<4>_MC.D2_PT_0 ),
    .I1(\U2_ADDR_reg<4>_MC.D2_PT_1 ),
    .I2(\U2_ADDR_reg<4>_MC.D2_PT_2 ),
    .O(\U2_ADDR_reg<4>_MC.D2 )
  );
  X_BUF \U2_ADDR_reg<5>  (
    .I(\U2_ADDR_reg<5>_MC.Q ),
    .O(U2_ADDR_reg[5])
  );
  X_XOR2 \U2_ADDR_reg<5>_MC_tsimcreated_xor__185  (
    .I0(\U2_ADDR_reg<5>_MC.D ),
    .I1(\U2_ADDR_reg<5>_MC.Q ),
    .O(\U2_ADDR_reg<5>_MC_tsimcreated_xor_ )
  );
  X_FF \U2_ADDR_reg<5>_MC.REG  (
    .I(\U2_ADDR_reg<5>_MC_tsimcreated_xor_ ),
    .CE(Vcc),
    .CLK(\U2_ADDR_reg<5>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\U2_ADDR_reg<5>_MC.Q )
  );
  X_INV \U2_ADDR_reg<5>_MC.REG_tsimcreated_inv_Mclk_II/FCLK_186  (
    .I(\Mclk_II/FCLK ),
    .O(\U2_ADDR_reg<5>_MC.REG_tsimcreated_inv_Mclk_II/FCLK )
  );
  X_XOR2 \U2_ADDR_reg<5>_MC.D_187  (
    .I0(\U2_ADDR_reg<5>_MC.D1 ),
    .I1(\U2_ADDR_reg<5>_MC.D2 ),
    .O(\U2_ADDR_reg<5>_MC.D )
  );
  X_ZERO \U2_ADDR_reg<5>_MC.D1_188  (
    .O(\U2_ADDR_reg<5>_MC.D1 )
  );
  X_AND2 \U2_ADDR_reg<5>_MC.D2_PT_0_189  (
    .I0(U2_ADDR_reg[5]),
    .I1(\NlwInverterSignal_U2_ADDR_reg<5>_MC.D2_PT_0/IN1 ),
    .O(\U2_ADDR_reg<5>_MC.D2_PT_0 )
  );
  X_AND6 \U2_ADDR_reg<5>_MC.D2_PT_1_190  (
    .I0(\WR_II/UIM ),
    .I1(\RD_II/UIM ),
    .I2(U2_ADDR_reg[5]),
    .I3(\NlwInverterSignal_U2_ADDR_reg<5>_MC.D2_PT_1/IN3 ),
    .I4(U2_ASedge),
    .I5(\NlwInverterSignal_U2_ADDR_reg<5>_MC.D2_PT_1/IN5 ),
    .O(\U2_ADDR_reg<5>_MC.D2_PT_1 )
  );
  X_AND7 \U2_ADDR_reg<5>_MC.D2_PT_2_191  (
    .I0(\WR_II/UIM ),
    .I1(\RD_II/UIM ),
    .I2(\NlwInverterSignal_U2_ADDR_reg<5>_MC.D2_PT_2/IN2 ),
    .I3(\MSPReset_II/UIM ),
    .I4(\NlwInverterSignal_U2_ADDR_reg<5>_MC.D2_PT_2/IN4 ),
    .I5(U2_ASedge),
    .I6(\AD<5>_II/UIM ),
    .O(\U2_ADDR_reg<5>_MC.D2_PT_2 )
  );
  X_OR3 \U2_ADDR_reg<5>_MC.D2_192  (
    .I0(\U2_ADDR_reg<5>_MC.D2_PT_0 ),
    .I1(\U2_ADDR_reg<5>_MC.D2_PT_1 ),
    .I2(\U2_ADDR_reg<5>_MC.D2_PT_2 ),
    .O(\U2_ADDR_reg<5>_MC.D2 )
  );
  X_BUF \U2_ADDR_reg<6>  (
    .I(\U2_ADDR_reg<6>_MC.Q ),
    .O(U2_ADDR_reg[6])
  );
  X_XOR2 \U2_ADDR_reg<6>_MC_tsimcreated_xor__193  (
    .I0(\U2_ADDR_reg<6>_MC.D ),
    .I1(\U2_ADDR_reg<6>_MC.Q ),
    .O(\U2_ADDR_reg<6>_MC_tsimcreated_xor_ )
  );
  X_FF \U2_ADDR_reg<6>_MC.REG  (
    .I(\U2_ADDR_reg<6>_MC_tsimcreated_xor_ ),
    .CE(Vcc),
    .CLK(\U2_ADDR_reg<6>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\U2_ADDR_reg<6>_MC.Q )
  );
  X_INV \U2_ADDR_reg<6>_MC.REG_tsimcreated_inv_Mclk_II/FCLK_194  (
    .I(\Mclk_II/FCLK ),
    .O(\U2_ADDR_reg<6>_MC.REG_tsimcreated_inv_Mclk_II/FCLK )
  );
  X_XOR2 \U2_ADDR_reg<6>_MC.D_195  (
    .I0(\U2_ADDR_reg<6>_MC.D1 ),
    .I1(\U2_ADDR_reg<6>_MC.D2 ),
    .O(\U2_ADDR_reg<6>_MC.D )
  );
  X_ZERO \U2_ADDR_reg<6>_MC.D1_196  (
    .O(\U2_ADDR_reg<6>_MC.D1 )
  );
  X_AND2 \U2_ADDR_reg<6>_MC.D2_PT_0_197  (
    .I0(U2_ADDR_reg[6]),
    .I1(\NlwInverterSignal_U2_ADDR_reg<6>_MC.D2_PT_0/IN1 ),
    .O(\U2_ADDR_reg<6>_MC.D2_PT_0 )
  );
  X_AND6 \U2_ADDR_reg<6>_MC.D2_PT_1_198  (
    .I0(\WR_II/UIM ),
    .I1(\RD_II/UIM ),
    .I2(U2_ADDR_reg[6]),
    .I3(\NlwInverterSignal_U2_ADDR_reg<6>_MC.D2_PT_1/IN3 ),
    .I4(U2_ASedge),
    .I5(\NlwInverterSignal_U2_ADDR_reg<6>_MC.D2_PT_1/IN5 ),
    .O(\U2_ADDR_reg<6>_MC.D2_PT_1 )
  );
  X_AND7 \U2_ADDR_reg<6>_MC.D2_PT_2_199  (
    .I0(\WR_II/UIM ),
    .I1(\RD_II/UIM ),
    .I2(\NlwInverterSignal_U2_ADDR_reg<6>_MC.D2_PT_2/IN2 ),
    .I3(\MSPReset_II/UIM ),
    .I4(\NlwInverterSignal_U2_ADDR_reg<6>_MC.D2_PT_2/IN4 ),
    .I5(U2_ASedge),
    .I6(\AD<6>_II/UIM ),
    .O(\U2_ADDR_reg<6>_MC.D2_PT_2 )
  );
  X_OR3 \U2_ADDR_reg<6>_MC.D2_200  (
    .I0(\U2_ADDR_reg<6>_MC.D2_PT_0 ),
    .I1(\U2_ADDR_reg<6>_MC.D2_PT_1 ),
    .I2(\U2_ADDR_reg<6>_MC.D2_PT_2 ),
    .O(\U2_ADDR_reg<6>_MC.D2 )
  );
  X_BUF \U2_ADDR_reg<7>  (
    .I(\U2_ADDR_reg<7>_MC.Q ),
    .O(U2_ADDR_reg[7])
  );
  X_XOR2 \U2_ADDR_reg<7>_MC_tsimcreated_xor__201  (
    .I0(\U2_ADDR_reg<7>_MC.D ),
    .I1(\U2_ADDR_reg<7>_MC.Q ),
    .O(\U2_ADDR_reg<7>_MC_tsimcreated_xor_ )
  );
  X_FF \U2_ADDR_reg<7>_MC.REG  (
    .I(\U2_ADDR_reg<7>_MC_tsimcreated_xor_ ),
    .CE(Vcc),
    .CLK(\U2_ADDR_reg<7>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\U2_ADDR_reg<7>_MC.Q )
  );
  X_INV \U2_ADDR_reg<7>_MC.REG_tsimcreated_inv_Mclk_II/FCLK_202  (
    .I(\Mclk_II/FCLK ),
    .O(\U2_ADDR_reg<7>_MC.REG_tsimcreated_inv_Mclk_II/FCLK )
  );
  X_XOR2 \U2_ADDR_reg<7>_MC.D_203  (
    .I0(\U2_ADDR_reg<7>_MC.D1 ),
    .I1(\U2_ADDR_reg<7>_MC.D2 ),
    .O(\U2_ADDR_reg<7>_MC.D )
  );
  X_ZERO \U2_ADDR_reg<7>_MC.D1_204  (
    .O(\U2_ADDR_reg<7>_MC.D1 )
  );
  X_AND2 \U2_ADDR_reg<7>_MC.D2_PT_0_205  (
    .I0(U2_ADDR_reg[7]),
    .I1(\NlwInverterSignal_U2_ADDR_reg<7>_MC.D2_PT_0/IN1 ),
    .O(\U2_ADDR_reg<7>_MC.D2_PT_0 )
  );
  X_AND6 \U2_ADDR_reg<7>_MC.D2_PT_1_206  (
    .I0(\WR_II/UIM ),
    .I1(\RD_II/UIM ),
    .I2(U2_ADDR_reg[7]),
    .I3(\NlwInverterSignal_U2_ADDR_reg<7>_MC.D2_PT_1/IN3 ),
    .I4(U2_ASedge),
    .I5(\NlwInverterSignal_U2_ADDR_reg<7>_MC.D2_PT_1/IN5 ),
    .O(\U2_ADDR_reg<7>_MC.D2_PT_1 )
  );
  X_AND7 \U2_ADDR_reg<7>_MC.D2_PT_2_207  (
    .I0(\WR_II/UIM ),
    .I1(\RD_II/UIM ),
    .I2(\NlwInverterSignal_U2_ADDR_reg<7>_MC.D2_PT_2/IN2 ),
    .I3(\MSPReset_II/UIM ),
    .I4(\NlwInverterSignal_U2_ADDR_reg<7>_MC.D2_PT_2/IN4 ),
    .I5(U2_ASedge),
    .I6(\AD<7>_II/UIM ),
    .O(\U2_ADDR_reg<7>_MC.D2_PT_2 )
  );
  X_OR3 \U2_ADDR_reg<7>_MC.D2_208  (
    .I0(\U2_ADDR_reg<7>_MC.D2_PT_0 ),
    .I1(\U2_ADDR_reg<7>_MC.D2_PT_1 ),
    .I2(\U2_ADDR_reg<7>_MC.D2_PT_2 ),
    .O(\U2_ADDR_reg<7>_MC.D2 )
  );
  X_BUF U2_AutoInc_209 (
    .I(\U2_AutoInc_MC.Q ),
    .O(U2_AutoInc)
  );
  X_FF \U2_AutoInc_MC.REG  (
    .I(\U2_AutoInc_MC.D ),
    .CE(\FOOBAR5__ctinst/4 ),
    .CLK(\U2_AutoInc_MC.REG_tsimcreated_inv_Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\U2_AutoInc_MC.Q )
  );
  X_INV \U2_AutoInc_MC.REG_tsimcreated_inv_Mclk_II/FCLK_210  (
    .I(\Mclk_II/FCLK ),
    .O(\U2_AutoInc_MC.REG_tsimcreated_inv_Mclk_II/FCLK )
  );
  X_XOR2 \U2_AutoInc_MC.D_211  (
    .I0(\NlwInverterSignal_U2_AutoInc_MC.D/IN0 ),
    .I1(\U2_AutoInc_MC.D2 ),
    .O(\U2_AutoInc_MC.D )
  );
  X_AND2 \U2_AutoInc_MC.D1_212  (
    .I0(\AS_II/UIM ),
    .I1(\AS_II/UIM ),
    .O(\U2_AutoInc_MC.D1 )
  );
  X_ZERO \U2_AutoInc_MC.D2_213  (
    .O(\U2_AutoInc_MC.D2 )
  );
  X_BUF U2_WRRDedge_214 (
    .I(\U2_WRRDedge_MC.Q ),
    .O(U2_WRRDedge)
  );
  X_FF \U2_WRRDedge_MC.REG  (
    .I(\U2_WRRDedge_MC.D ),
    .CE(Vcc),
    .CLK(\U2_WRRDedge_MC.REG_tsimcreated_inv_Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\U2_WRRDedge_MC.Q )
  );
  X_INV \U2_WRRDedge_MC.REG_tsimcreated_inv_Mclk_II/FCLK_215  (
    .I(\Mclk_II/FCLK ),
    .O(\U2_WRRDedge_MC.REG_tsimcreated_inv_Mclk_II/FCLK )
  );
  X_XOR2 \U2_WRRDedge_MC.D_216  (
    .I0(\U2_WRRDedge_MC.D1 ),
    .I1(\U2_WRRDedge_MC.D2 ),
    .O(\U2_WRRDedge_MC.D )
  );
  X_AND2 \U2_WRRDedge_MC.D1_217  (
    .I0(\WR_II/UIM ),
    .I1(\RD_II/UIM ),
    .O(\U2_WRRDedge_MC.D1 )
  );
  X_ZERO \U2_WRRDedge_MC.D2_218  (
    .O(\U2_WRRDedge_MC.D2 )
  );
  X_BUF N_PZ_953_219 (
    .I(\N_PZ_953_MC.Q ),
    .O(N_PZ_953)
  );
  X_BUF \N_PZ_953_MC.Q_220  (
    .I(\N_PZ_953_MC.D ),
    .O(\N_PZ_953_MC.Q )
  );
  X_XOR2 \N_PZ_953_MC.D_221  (
    .I0(\N_PZ_953_MC.D1 ),
    .I1(\N_PZ_953_MC.D2 ),
    .O(\N_PZ_953_MC.D )
  );
  X_AND2 \N_PZ_953_MC.D1_222  (
    .I0(\WR_II/UIM ),
    .I1(\RD_II/UIM ),
    .O(\N_PZ_953_MC.D1 )
  );
  X_ZERO \N_PZ_953_MC.D2_223  (
    .O(\N_PZ_953_MC.D2 )
  );
  X_BUF N_PZ_938_224 (
    .I(\N_PZ_938_MC.Q ),
    .O(N_PZ_938)
  );
  X_BUF \N_PZ_938_MC.Q_225  (
    .I(\N_PZ_938_MC.D ),
    .O(\N_PZ_938_MC.Q )
  );
  X_XOR2 \N_PZ_938_MC.D_226  (
    .I0(\N_PZ_938_MC.D1 ),
    .I1(\N_PZ_938_MC.D2 ),
    .O(\N_PZ_938_MC.D )
  );
  X_ZERO \N_PZ_938_MC.D1_227  (
    .O(\N_PZ_938_MC.D1 )
  );
  X_AND2 \N_PZ_938_MC.D2_PT_0_228  (
    .I0(\MSPReset_II/UIM ),
    .I1(\AS_II/UIM ),
    .O(\N_PZ_938_MC.D2_PT_0 )
  );
  X_AND2 \N_PZ_938_MC.D2_PT_1_229  (
    .I0(\MSPReset_II/UIM ),
    .I1(\NlwInverterSignal_N_PZ_938_MC.D2_PT_1/IN1 ),
    .O(\N_PZ_938_MC.D2_PT_1 )
  );
  X_OR2 \N_PZ_938_MC.D2_230  (
    .I0(\N_PZ_938_MC.D2_PT_0 ),
    .I1(\N_PZ_938_MC.D2_PT_1 ),
    .O(\N_PZ_938_MC.D2 )
  );
  X_BUF \U2_ADDR_reg<3>  (
    .I(\U2_ADDR_reg<3>_MC.Q ),
    .O(U2_ADDR_reg[3])
  );
  X_XOR2 \U2_ADDR_reg<3>_MC_tsimcreated_xor__231  (
    .I0(\U2_ADDR_reg<3>_MC.D ),
    .I1(\U2_ADDR_reg<3>_MC.Q ),
    .O(\U2_ADDR_reg<3>_MC_tsimcreated_xor_ )
  );
  X_FF \U2_ADDR_reg<3>_MC.REG  (
    .I(\U2_ADDR_reg<3>_MC_tsimcreated_xor_ ),
    .CE(Vcc),
    .CLK(\U2_ADDR_reg<3>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\U2_ADDR_reg<3>_MC.Q )
  );
  X_INV \U2_ADDR_reg<3>_MC.REG_tsimcreated_inv_Mclk_II/FCLK_232  (
    .I(\Mclk_II/FCLK ),
    .O(\U2_ADDR_reg<3>_MC.REG_tsimcreated_inv_Mclk_II/FCLK )
  );
  X_XOR2 \U2_ADDR_reg<3>_MC.D_233  (
    .I0(\U2_ADDR_reg<3>_MC.D1 ),
    .I1(\U2_ADDR_reg<3>_MC.D2 ),
    .O(\U2_ADDR_reg<3>_MC.D )
  );
  X_ZERO \U2_ADDR_reg<3>_MC.D1_234  (
    .O(\U2_ADDR_reg<3>_MC.D1 )
  );
  X_AND2 \U2_ADDR_reg<3>_MC.D2_PT_0_235  (
    .I0(U2_ADDR_reg[3]),
    .I1(\NlwInverterSignal_U2_ADDR_reg<3>_MC.D2_PT_0/IN1 ),
    .O(\U2_ADDR_reg<3>_MC.D2_PT_0 )
  );
  X_AND6 \U2_ADDR_reg<3>_MC.D2_PT_1_236  (
    .I0(\WR_II/UIM ),
    .I1(\RD_II/UIM ),
    .I2(U2_ADDR_reg[3]),
    .I3(\NlwInverterSignal_U2_ADDR_reg<3>_MC.D2_PT_1/IN3 ),
    .I4(U2_ASedge),
    .I5(\NlwInverterSignal_U2_ADDR_reg<3>_MC.D2_PT_1/IN5 ),
    .O(\U2_ADDR_reg<3>_MC.D2_PT_1 )
  );
  X_AND7 \U2_ADDR_reg<3>_MC.D2_PT_2_237  (
    .I0(\WR_II/UIM ),
    .I1(\RD_II/UIM ),
    .I2(\NlwInverterSignal_U2_ADDR_reg<3>_MC.D2_PT_2/IN2 ),
    .I3(\MSPReset_II/UIM ),
    .I4(\NlwInverterSignal_U2_ADDR_reg<3>_MC.D2_PT_2/IN4 ),
    .I5(U2_ASedge),
    .I6(\AD<3>_II/UIM ),
    .O(\U2_ADDR_reg<3>_MC.D2_PT_2 )
  );
  X_AND16 \U2_ADDR_reg<3>_MC.D2_PT_3_238  (
    .I0(\WR_II/UIM ),
    .I1(\RD_II/UIM ),
    .I2(U2_ADDR_reg[0]),
    .I3(\NlwInverterSignal_U2_ADDR_reg<3>_MC.D2_PT_3/IN3 ),
    .I4(\NlwInverterSignal_U2_ADDR_reg<3>_MC.D2_PT_3/IN4 ),
    .I5(\NlwInverterSignal_U2_ADDR_reg<3>_MC.D2_PT_3/IN5 ),
    .I6(\NlwInverterSignal_U2_ADDR_reg<3>_MC.D2_PT_3/IN6 ),
    .I7(U2_ADDR_reg[1]),
    .I8(U2_ADDR_reg[2]),
    .I9(U2_AutoInc),
    .I10(\NlwInverterSignal_U2_ADDR_reg<3>_MC.D2_PT_3/IN10 ),
    .I11(N_PZ_938),
    .I12(Vcc),
    .I13(Vcc),
    .I14(Vcc),
    .I15(Vcc),
    .O(\U2_ADDR_reg<3>_MC.D2_PT_3 )
  );
  X_OR4 \U2_ADDR_reg<3>_MC.D2_239  (
    .I0(\U2_ADDR_reg<3>_MC.D2_PT_0 ),
    .I1(\U2_ADDR_reg<3>_MC.D2_PT_1 ),
    .I2(\U2_ADDR_reg<3>_MC.D2_PT_2 ),
    .I3(\U2_ADDR_reg<3>_MC.D2_PT_3 ),
    .O(\U2_ADDR_reg<3>_MC.D2 )
  );
  X_BUF \U2_ADDR_reg<1>  (
    .I(\U2_ADDR_reg<1>_MC.Q ),
    .O(U2_ADDR_reg[1])
  );
  X_XOR2 \U2_ADDR_reg<1>_MC_tsimcreated_xor__240  (
    .I0(\U2_ADDR_reg<1>_MC.D ),
    .I1(\U2_ADDR_reg<1>_MC.Q ),
    .O(\U2_ADDR_reg<1>_MC_tsimcreated_xor_ )
  );
  X_FF \U2_ADDR_reg<1>_MC.REG  (
    .I(\U2_ADDR_reg<1>_MC_tsimcreated_xor_ ),
    .CE(Vcc),
    .CLK(\U2_ADDR_reg<1>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\U2_ADDR_reg<1>_MC.Q )
  );
  X_INV \U2_ADDR_reg<1>_MC.REG_tsimcreated_inv_Mclk_II/FCLK_241  (
    .I(\Mclk_II/FCLK ),
    .O(\U2_ADDR_reg<1>_MC.REG_tsimcreated_inv_Mclk_II/FCLK )
  );
  X_XOR2 \U2_ADDR_reg<1>_MC.D_242  (
    .I0(\U2_ADDR_reg<1>_MC.D1 ),
    .I1(\U2_ADDR_reg<1>_MC.D2 ),
    .O(\U2_ADDR_reg<1>_MC.D )
  );
  X_ZERO \U2_ADDR_reg<1>_MC.D1_243  (
    .O(\U2_ADDR_reg<1>_MC.D1 )
  );
  X_AND2 \U2_ADDR_reg<1>_MC.D2_PT_0_244  (
    .I0(U2_ADDR_reg[1]),
    .I1(\NlwInverterSignal_U2_ADDR_reg<1>_MC.D2_PT_0/IN1 ),
    .O(\U2_ADDR_reg<1>_MC.D2_PT_0 )
  );
  X_AND6 \U2_ADDR_reg<1>_MC.D2_PT_1_245  (
    .I0(\WR_II/UIM ),
    .I1(\RD_II/UIM ),
    .I2(U2_ADDR_reg[1]),
    .I3(\NlwInverterSignal_U2_ADDR_reg<1>_MC.D2_PT_1/IN3 ),
    .I4(U2_ASedge),
    .I5(\NlwInverterSignal_U2_ADDR_reg<1>_MC.D2_PT_1/IN5 ),
    .O(\U2_ADDR_reg<1>_MC.D2_PT_1 )
  );
  X_AND7 \U2_ADDR_reg<1>_MC.D2_PT_2_246  (
    .I0(\WR_II/UIM ),
    .I1(\RD_II/UIM ),
    .I2(\NlwInverterSignal_U2_ADDR_reg<1>_MC.D2_PT_2/IN2 ),
    .I3(\MSPReset_II/UIM ),
    .I4(\NlwInverterSignal_U2_ADDR_reg<1>_MC.D2_PT_2/IN4 ),
    .I5(U2_ASedge),
    .I6(\AD<1>_II/UIM ),
    .O(\U2_ADDR_reg<1>_MC.D2_PT_2 )
  );
  X_AND16 \U2_ADDR_reg<1>_MC.D2_PT_3_247  (
    .I0(\WR_II/UIM ),
    .I1(\RD_II/UIM ),
    .I2(U2_ADDR_reg[0]),
    .I3(\NlwInverterSignal_U2_ADDR_reg<1>_MC.D2_PT_3/IN3 ),
    .I4(\NlwInverterSignal_U2_ADDR_reg<1>_MC.D2_PT_3/IN4 ),
    .I5(\NlwInverterSignal_U2_ADDR_reg<1>_MC.D2_PT_3/IN5 ),
    .I6(\NlwInverterSignal_U2_ADDR_reg<1>_MC.D2_PT_3/IN6 ),
    .I7(U2_AutoInc),
    .I8(\NlwInverterSignal_U2_ADDR_reg<1>_MC.D2_PT_3/IN8 ),
    .I9(N_PZ_938),
    .I10(Vcc),
    .I11(Vcc),
    .I12(Vcc),
    .I13(Vcc),
    .I14(Vcc),
    .I15(Vcc),
    .O(\U2_ADDR_reg<1>_MC.D2_PT_3 )
  );
  X_OR4 \U2_ADDR_reg<1>_MC.D2_248  (
    .I0(\U2_ADDR_reg<1>_MC.D2_PT_0 ),
    .I1(\U2_ADDR_reg<1>_MC.D2_PT_1 ),
    .I2(\U2_ADDR_reg<1>_MC.D2_PT_2 ),
    .I3(\U2_ADDR_reg<1>_MC.D2_PT_3 ),
    .O(\U2_ADDR_reg<1>_MC.D2 )
  );
  X_BUF \U2_ADDR_reg<2>  (
    .I(\U2_ADDR_reg<2>_MC.Q ),
    .O(U2_ADDR_reg[2])
  );
  X_XOR2 \U2_ADDR_reg<2>_MC_tsimcreated_xor__249  (
    .I0(\U2_ADDR_reg<2>_MC.D ),
    .I1(\U2_ADDR_reg<2>_MC.Q ),
    .O(\U2_ADDR_reg<2>_MC_tsimcreated_xor_ )
  );
  X_FF \U2_ADDR_reg<2>_MC.REG  (
    .I(\U2_ADDR_reg<2>_MC_tsimcreated_xor_ ),
    .CE(Vcc),
    .CLK(\U2_ADDR_reg<2>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\U2_ADDR_reg<2>_MC.Q )
  );
  X_INV \U2_ADDR_reg<2>_MC.REG_tsimcreated_inv_Mclk_II/FCLK_250  (
    .I(\Mclk_II/FCLK ),
    .O(\U2_ADDR_reg<2>_MC.REG_tsimcreated_inv_Mclk_II/FCLK )
  );
  X_XOR2 \U2_ADDR_reg<2>_MC.D_251  (
    .I0(\U2_ADDR_reg<2>_MC.D1 ),
    .I1(\U2_ADDR_reg<2>_MC.D2 ),
    .O(\U2_ADDR_reg<2>_MC.D )
  );
  X_ZERO \U2_ADDR_reg<2>_MC.D1_252  (
    .O(\U2_ADDR_reg<2>_MC.D1 )
  );
  X_AND2 \U2_ADDR_reg<2>_MC.D2_PT_0_253  (
    .I0(U2_ADDR_reg[2]),
    .I1(\NlwInverterSignal_U2_ADDR_reg<2>_MC.D2_PT_0/IN1 ),
    .O(\U2_ADDR_reg<2>_MC.D2_PT_0 )
  );
  X_AND6 \U2_ADDR_reg<2>_MC.D2_PT_1_254  (
    .I0(\WR_II/UIM ),
    .I1(\RD_II/UIM ),
    .I2(U2_ADDR_reg[2]),
    .I3(\NlwInverterSignal_U2_ADDR_reg<2>_MC.D2_PT_1/IN3 ),
    .I4(U2_ASedge),
    .I5(\NlwInverterSignal_U2_ADDR_reg<2>_MC.D2_PT_1/IN5 ),
    .O(\U2_ADDR_reg<2>_MC.D2_PT_1 )
  );
  X_AND7 \U2_ADDR_reg<2>_MC.D2_PT_2_255  (
    .I0(\WR_II/UIM ),
    .I1(\RD_II/UIM ),
    .I2(\NlwInverterSignal_U2_ADDR_reg<2>_MC.D2_PT_2/IN2 ),
    .I3(\MSPReset_II/UIM ),
    .I4(\NlwInverterSignal_U2_ADDR_reg<2>_MC.D2_PT_2/IN4 ),
    .I5(U2_ASedge),
    .I6(\AD<2>_II/UIM ),
    .O(\U2_ADDR_reg<2>_MC.D2_PT_2 )
  );
  X_AND16 \U2_ADDR_reg<2>_MC.D2_PT_3_256  (
    .I0(\WR_II/UIM ),
    .I1(\RD_II/UIM ),
    .I2(U2_ADDR_reg[0]),
    .I3(\NlwInverterSignal_U2_ADDR_reg<2>_MC.D2_PT_3/IN3 ),
    .I4(\NlwInverterSignal_U2_ADDR_reg<2>_MC.D2_PT_3/IN4 ),
    .I5(\NlwInverterSignal_U2_ADDR_reg<2>_MC.D2_PT_3/IN5 ),
    .I6(\NlwInverterSignal_U2_ADDR_reg<2>_MC.D2_PT_3/IN6 ),
    .I7(U2_ADDR_reg[1]),
    .I8(U2_AutoInc),
    .I9(\NlwInverterSignal_U2_ADDR_reg<2>_MC.D2_PT_3/IN9 ),
    .I10(N_PZ_938),
    .I11(Vcc),
    .I12(Vcc),
    .I13(Vcc),
    .I14(Vcc),
    .I15(Vcc),
    .O(\U2_ADDR_reg<2>_MC.D2_PT_3 )
  );
  X_OR4 \U2_ADDR_reg<2>_MC.D2_257  (
    .I0(\U2_ADDR_reg<2>_MC.D2_PT_0 ),
    .I1(\U2_ADDR_reg<2>_MC.D2_PT_1 ),
    .I2(\U2_ADDR_reg<2>_MC.D2_PT_2 ),
    .I3(\U2_ADDR_reg<2>_MC.D2_PT_3 ),
    .O(\U2_ADDR_reg<2>_MC.D2 )
  );
  X_BUF \outDATA<5>\$WA0.UIM_258  (
    .I(\outDATA<5>\$WA0.UIM_MC.Q ),
    .O(\outDATA<5>\$WA0.UIM )
  );
  X_BUF \outDATA<5>\$WA0.UIM_MC.Q_259  (
    .I(\outDATA<5>\$WA0.UIM_MC.D ),
    .O(\outDATA<5>\$WA0.UIM_MC.Q )
  );
  X_XOR2 \outDATA<5>\$WA0.UIM_MC.D_260  (
    .I0(\outDATA<5>\$WA0.UIM_MC.D1 ),
    .I1(\outDATA<5>\$WA0.UIM_MC.D2 ),
    .O(\outDATA<5>\$WA0.UIM_MC.D )
  );
  X_AND2 \outDATA<5>\$WA0.UIM_MC.D1_261  (
    .I0(U11_U3_counterr[5]),
    .I1(U11_U3_counterr[5]),
    .O(\outDATA<5>\$WA0.UIM_MC.D1 )
  );
  X_ZERO \outDATA<5>\$WA0.UIM_MC.D2_262  (
    .O(\outDATA<5>\$WA0.UIM_MC.D2 )
  );
  X_BUF \U11_U3_counterr<5>  (
    .I(\U11_U3_counterr<5>_MC.Q ),
    .O(U11_U3_counterr[5])
  );
  X_XOR2 \U11_U3_counterr<5>_MC_tsimcreated_xor__263  (
    .I0(\U11_U3_counterr<5>_MC.D ),
    .I1(\U11_U3_counterr<5>_MC.Q ),
    .O(\U11_U3_counterr<5>_MC_tsimcreated_xor_ )
  );
  X_FF \U11_U3_counterr<5>_MC.REG  (
    .I(\U11_U3_counterr<5>_MC_tsimcreated_xor_ ),
    .CE(Vcc),
    .CLK(\U11_U3_counterr<5>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\U11_U3_counterr<5>_MC.Q )
  );
  X_INV \U11_U3_counterr<5>_MC.REG_tsimcreated_inv_Mclk_II/FCLK_264  (
    .I(\Mclk_II/FCLK ),
    .O(\U11_U3_counterr<5>_MC.REG_tsimcreated_inv_Mclk_II/FCLK )
  );
  X_XOR2 \U11_U3_counterr<5>_MC.D_265  (
    .I0(\U11_U3_counterr<5>_MC.D1 ),
    .I1(\U11_U3_counterr<5>_MC.D2 ),
    .O(\U11_U3_counterr<5>_MC.D )
  );
  X_ZERO \U11_U3_counterr<5>_MC.D1_266  (
    .O(\U11_U3_counterr<5>_MC.D1 )
  );
  X_AND2 \U11_U3_counterr<5>_MC.D2_PT_0_267  (
    .I0(U11_U3_counterr[5]),
    .I1(N_PZ_1065),
    .O(\U11_U3_counterr<5>_MC.D2_PT_0 )
  );
  X_AND4 \U11_U3_counterr<5>_MC.D2_PT_1_268  (
    .I0(\NlwInverterSignal_U11_U3_counterr<5>_MC.D2_PT_1/IN0 ),
    .I1(U11_Incdetect),
    .I2(U11_U3_counterr[3]),
    .I3(U11_U3_counterr[4]),
    .O(\U11_U3_counterr<5>_MC.D2_PT_1 )
  );
  X_AND7 \U11_U3_counterr<5>_MC.D2_PT_2_269  (
    .I0(\NlwInverterSignal_U11_U3_counterr<5>_MC.D2_PT_2/IN0 ),
    .I1(U11_Incdetect),
    .I2(U11_U3_counterr[4]),
    .I3(\NlwInverterSignal_U11_U3_counterr<5>_MC.D2_PT_2/IN3 ),
    .I4(U11_U3_counterr[0]),
    .I5(U11_U3_counterr[1]),
    .I6(U11_U3_counterr[2]),
    .O(\U11_U3_counterr<5>_MC.D2_PT_2 )
  );
  X_AND8 \U11_U3_counterr<5>_MC.D2_PT_3_270  (
    .I0(\NlwInverterSignal_U11_U3_counterr<5>_MC.D2_PT_3/IN0 ),
    .I1(\NlwInverterSignal_U11_U3_counterr<5>_MC.D2_PT_3/IN1 ),
    .I2(\NlwInverterSignal_U11_U3_counterr<5>_MC.D2_PT_3/IN2 ),
    .I3(\NlwInverterSignal_U11_U3_counterr<5>_MC.D2_PT_3/IN3 ),
    .I4(U11_SCLdetect),
    .I5(\NlwInverterSignal_U11_U3_counterr<5>_MC.D2_PT_3/IN5 ),
    .I6(\NlwInverterSignal_U11_U3_counterr<5>_MC.D2_PT_3/IN6 ),
    .I7(\NlwInverterSignal_U11_U3_counterr<5>_MC.D2_PT_3/IN7 ),
    .O(\U11_U3_counterr<5>_MC.D2_PT_3 )
  );
  X_OR4 \U11_U3_counterr<5>_MC.D2_271  (
    .I0(\U11_U3_counterr<5>_MC.D2_PT_0 ),
    .I1(\U11_U3_counterr<5>_MC.D2_PT_1 ),
    .I2(\U11_U3_counterr<5>_MC.D2_PT_2 ),
    .I3(\U11_U3_counterr<5>_MC.D2_PT_3 ),
    .O(\U11_U3_counterr<5>_MC.D2 )
  );
  X_BUF N_PZ_1065_272 (
    .I(\N_PZ_1065_MC.Q ),
    .O(N_PZ_1065)
  );
  X_BUF \N_PZ_1065_MC.Q_273  (
    .I(\N_PZ_1065_MC.D ),
    .O(\N_PZ_1065_MC.Q )
  );
  X_XOR2 \N_PZ_1065_MC.D_274  (
    .I0(\N_PZ_1065_MC.D1 ),
    .I1(\N_PZ_1065_MC.D2 ),
    .O(\N_PZ_1065_MC.D )
  );
  X_ZERO \N_PZ_1065_MC.D1_275  (
    .O(\N_PZ_1065_MC.D1 )
  );
  X_AND2 \N_PZ_1065_MC.D2_PT_0_276  (
    .I0(\SCLreset_II/UIM ),
    .I1(\SCLreset_II/UIM ),
    .O(\N_PZ_1065_MC.D2_PT_0 )
  );
  X_AND3 \N_PZ_1065_MC.D2_PT_1_277  (
    .I0(U11_Incdetect),
    .I1(\NlwInverterSignal_N_PZ_1065_MC.D2_PT_1/IN1 ),
    .I2(U11_ResetDetect),
    .O(\N_PZ_1065_MC.D2_PT_1 )
  );
  X_AND3 \N_PZ_1065_MC.D2_PT_2_278  (
    .I0(\NlwInverterSignal_N_PZ_1065_MC.D2_PT_2/IN0 ),
    .I1(U11_SCLdetect),
    .I2(\outDATA<7>\$WA4.UIM ),
    .O(\N_PZ_1065_MC.D2_PT_2 )
  );
  X_OR3 \N_PZ_1065_MC.D2_279  (
    .I0(\N_PZ_1065_MC.D2_PT_0 ),
    .I1(\N_PZ_1065_MC.D2_PT_1 ),
    .I2(\N_PZ_1065_MC.D2_PT_2 ),
    .O(\N_PZ_1065_MC.D2 )
  );
  X_BUF U11_Incdetect_280 (
    .I(\U11_Incdetect_MC.Q ),
    .O(U11_Incdetect)
  );
  X_FF \U11_Incdetect_MC.REG  (
    .I(\U11_Incdetect_MC.D ),
    .CE(Vcc),
    .CLK(\U11_Incdetect_MC.REG_tsimcreated_inv_Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\U11_Incdetect_MC.Q )
  );
  X_INV \U11_Incdetect_MC.REG_tsimcreated_inv_Mclk_II/FCLK_281  (
    .I(\Mclk_II/FCLK ),
    .O(\U11_Incdetect_MC.REG_tsimcreated_inv_Mclk_II/FCLK )
  );
  X_XOR2 \U11_Incdetect_MC.D_282  (
    .I0(\U11_Incdetect_MC.D1 ),
    .I1(\U11_Incdetect_MC.D2 ),
    .O(\U11_Incdetect_MC.D )
  );
  X_AND2 \U11_Incdetect_MC.D1_283  (
    .I0(\NlwInverterSignal_U11_Incdetect_MC.D1/IN0 ),
    .I1(\U11_U1/Line_last ),
    .O(\U11_Incdetect_MC.D1 )
  );
  X_ZERO \U11_Incdetect_MC.D2_284  (
    .O(\U11_Incdetect_MC.D2 )
  );
  X_BUF U11_ResetDetect_285 (
    .I(\U11_ResetDetect_MC.Q ),
    .O(U11_ResetDetect)
  );
  X_FF \U11_ResetDetect_MC.REG  (
    .I(\U11_ResetDetect_MC.D ),
    .CE(Vcc),
    .CLK(\U11_ResetDetect_MC.REG_tsimcreated_inv_Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\U11_ResetDetect_MC.Q )
  );
  X_INV \U11_ResetDetect_MC.REG_tsimcreated_inv_Mclk_II/FCLK_286  (
    .I(\Mclk_II/FCLK ),
    .O(\U11_ResetDetect_MC.REG_tsimcreated_inv_Mclk_II/FCLK )
  );
  X_XOR2 \U11_ResetDetect_MC.D_287  (
    .I0(\U11_ResetDetect_MC.D1 ),
    .I1(\U11_ResetDetect_MC.D2 ),
    .O(\U11_ResetDetect_MC.D )
  );
  X_AND2 \U11_ResetDetect_MC.D1_288  (
    .I0(\NlwInverterSignal_U11_ResetDetect_MC.D1/IN0 ),
    .I1(\U11_U4/Line_last ),
    .O(\U11_ResetDetect_MC.D1 )
  );
  X_ZERO \U11_ResetDetect_MC.D2_289  (
    .O(\U11_ResetDetect_MC.D2 )
  );
  X_BUF U11_SCLdetect_290 (
    .I(\U11_SCLdetect_MC.Q ),
    .O(U11_SCLdetect)
  );
  X_FF \U11_SCLdetect_MC.REG  (
    .I(\U11_SCLdetect_MC.D ),
    .CE(Vcc),
    .CLK(\U11_SCLdetect_MC.REG_tsimcreated_inv_Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\U11_SCLdetect_MC.Q )
  );
  X_INV \U11_SCLdetect_MC.REG_tsimcreated_inv_Mclk_II/FCLK_291  (
    .I(\Mclk_II/FCLK ),
    .O(\U11_SCLdetect_MC.REG_tsimcreated_inv_Mclk_II/FCLK )
  );
  X_XOR2 \U11_SCLdetect_MC.D_292  (
    .I0(\U11_SCLdetect_MC.D1 ),
    .I1(\U11_SCLdetect_MC.D2 ),
    .O(\U11_SCLdetect_MC.D )
  );
  X_AND2 \U11_SCLdetect_MC.D1_293  (
    .I0(\NlwInverterSignal_U11_SCLdetect_MC.D1/IN0 ),
    .I1(\U11_U2/Line_last ),
    .O(\U11_SCLdetect_MC.D1 )
  );
  X_ZERO \U11_SCLdetect_MC.D2_294  (
    .O(\U11_SCLdetect_MC.D2 )
  );
  X_BUF \U11_U2/Line_last_MC.Q_295  (
    .I(\U11_U2/Line_last_MC.D ),
    .O(\U11_U2/Line_last_MC.Q )
  );
  X_BUF \U11_U2/Line_last_MC.OE_296  (
    .I(\U11_U2/Line_last_MC.BUFOE.OUT ),
    .O(\U11_U2/Line_last_MC.OE )
  );
  X_BUF \U11_U2/Line_last_MC.BUFOE.OUT_297  (
    .I(\FOOBAR4__ctinst/0 ),
    .O(\U11_U2/Line_last_MC.BUFOE.OUT )
  );
  X_XOR2 \U11_U2/Line_last_MC.D_298  (
    .I0(\U11_U2/Line_last_MC.D1 ),
    .I1(\U11_U2/Line_last_MC.D2 ),
    .O(\U11_U2/Line_last_MC.D )
  );
  X_ZERO \U11_U2/Line_last_MC.D1_299  (
    .O(\U11_U2/Line_last_MC.D1 )
  );
  X_ZERO \U11_U2/Line_last_MC.D2_300  (
    .O(\U11_U2/Line_last_MC.D2 )
  );
  X_BUF \TP12_MC.Q_301  (
    .I(\TP12_MC.Q_tsimrenamed_net_ ),
    .O(\TP12_MC.Q )
  );
  X_BUF \TP12_MC.UIM_302  (
    .I(\TP12_MC.Q_tsimrenamed_net_ ),
    .O(\TP12_MC.UIM )
  );
  X_BUF \TP12_MC.Q_tsimrenamed_net__303  (
    .I(\TP12_MC.D ),
    .O(\TP12_MC.Q_tsimrenamed_net_ )
  );
  X_XOR2 \TP12_MC.D_304  (
    .I0(\TP12_MC.D1 ),
    .I1(\TP12_MC.D2 ),
    .O(\TP12_MC.D )
  );
  X_AND6 \TP12_MC.D1_305  (
    .I0(\NlwInverterSignal_TP12_MC.D1/IN0 ),
    .I1(\NlwInverterSignal_TP12_MC.D1/IN1 ),
    .I2(\NlwInverterSignal_TP12_MC.D1/IN2 ),
    .I3(\NlwInverterSignal_TP12_MC.D1/IN3 ),
    .I4(\NlwInverterSignal_TP12_MC.D1/IN4 ),
    .I5(\NlwInverterSignal_TP12_MC.D1/IN5 ),
    .O(\TP12_MC.D1 )
  );
  X_ZERO \TP12_MC.D2_306  (
    .O(\TP12_MC.D2 )
  );
  X_BUF \U11_U3_counterr<3>  (
    .I(\U11_U3_counterr<3>_MC.Q ),
    .O(U11_U3_counterr[3])
  );
  X_XOR2 \U11_U3_counterr<3>_MC_tsimcreated_xor__307  (
    .I0(\U11_U3_counterr<3>_MC.D ),
    .I1(\U11_U3_counterr<3>_MC.Q ),
    .O(\U11_U3_counterr<3>_MC_tsimcreated_xor_ )
  );
  X_FF \U11_U3_counterr<3>_MC.REG  (
    .I(\U11_U3_counterr<3>_MC_tsimcreated_xor_ ),
    .CE(Vcc),
    .CLK(\U11_U3_counterr<3>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\U11_U3_counterr<3>_MC.Q )
  );
  X_INV \U11_U3_counterr<3>_MC.REG_tsimcreated_inv_Mclk_II/FCLK_308  (
    .I(\Mclk_II/FCLK ),
    .O(\U11_U3_counterr<3>_MC.REG_tsimcreated_inv_Mclk_II/FCLK )
  );
  X_XOR2 \U11_U3_counterr<3>_MC.D_309  (
    .I0(\NlwInverterSignal_U11_U3_counterr<3>_MC.D/IN0 ),
    .I1(\U11_U3_counterr<3>_MC.D2 ),
    .O(\U11_U3_counterr<3>_MC.D )
  );
  X_ZERO \U11_U3_counterr<3>_MC.D1_310  (
    .O(\U11_U3_counterr<3>_MC.D1 )
  );
  X_AND2 \U11_U3_counterr<3>_MC.D2_PT_0_311  (
    .I0(U11_U3_counterr[3]),
    .I1(\SCLreset_II/UIM ),
    .O(\U11_U3_counterr<3>_MC.D2_PT_0 )
  );
  X_AND3 \U11_U3_counterr<3>_MC.D2_PT_1_312  (
    .I0(N_PZ_1065),
    .I1(\NlwInverterSignal_U11_U3_counterr<3>_MC.D2_PT_1/IN1 ),
    .I2(\NlwInverterSignal_U11_U3_counterr<3>_MC.D2_PT_1/IN2 ),
    .O(\U11_U3_counterr<3>_MC.D2_PT_1 )
  );
  X_AND3 \U11_U3_counterr<3>_MC.D2_PT_2_313  (
    .I0(\NlwInverterSignal_U11_U3_counterr<3>_MC.D2_PT_2/IN0 ),
    .I1(\NlwInverterSignal_U11_U3_counterr<3>_MC.D2_PT_2/IN1 ),
    .I2(\NlwInverterSignal_U11_U3_counterr<3>_MC.D2_PT_2/IN2 ),
    .O(\U11_U3_counterr<3>_MC.D2_PT_2 )
  );
  X_AND3 \U11_U3_counterr<3>_MC.D2_PT_3_314  (
    .I0(\NlwInverterSignal_U11_U3_counterr<3>_MC.D2_PT_3/IN0 ),
    .I1(\NlwInverterSignal_U11_U3_counterr<3>_MC.D2_PT_3/IN1 ),
    .I2(U11_U3_counterr[0]),
    .O(\U11_U3_counterr<3>_MC.D2_PT_3 )
  );
  X_AND3 \U11_U3_counterr<3>_MC.D2_PT_4_315  (
    .I0(\NlwInverterSignal_U11_U3_counterr<3>_MC.D2_PT_4/IN0 ),
    .I1(\NlwInverterSignal_U11_U3_counterr<3>_MC.D2_PT_4/IN1 ),
    .I2(U11_U3_counterr[1]),
    .O(\U11_U3_counterr<3>_MC.D2_PT_4 )
  );
  X_AND3 \U11_U3_counterr<3>_MC.D2_PT_5_316  (
    .I0(\NlwInverterSignal_U11_U3_counterr<3>_MC.D2_PT_5/IN0 ),
    .I1(\NlwInverterSignal_U11_U3_counterr<3>_MC.D2_PT_5/IN1 ),
    .I2(U11_U3_counterr[2]),
    .O(\U11_U3_counterr<3>_MC.D2_PT_5 )
  );
  X_AND5 \U11_U3_counterr<3>_MC.D2_PT_6_317  (
    .I0(\NlwInverterSignal_U11_U3_counterr<3>_MC.D2_PT_6/IN0 ),
    .I1(\NlwInverterSignal_U11_U3_counterr<3>_MC.D2_PT_6/IN1 ),
    .I2(U11_U3_counterr[0]),
    .I3(U11_U3_counterr[1]),
    .I4(U11_U3_counterr[2]),
    .O(\U11_U3_counterr<3>_MC.D2_PT_6 )
  );
  X_OR7 \U11_U3_counterr<3>_MC.D2_318  (
    .I0(\U11_U3_counterr<3>_MC.D2_PT_0 ),
    .I1(\U11_U3_counterr<3>_MC.D2_PT_1 ),
    .I2(\U11_U3_counterr<3>_MC.D2_PT_2 ),
    .I3(\U11_U3_counterr<3>_MC.D2_PT_3 ),
    .I4(\U11_U3_counterr<3>_MC.D2_PT_4 ),
    .I5(\U11_U3_counterr<3>_MC.D2_PT_5 ),
    .I6(\U11_U3_counterr<3>_MC.D2_PT_6 ),
    .O(\U11_U3_counterr<3>_MC.D2 )
  );
  X_BUF \U11_U3_counterr<0>  (
    .I(\U11_U3_counterr<0>_MC.Q ),
    .O(U11_U3_counterr[0])
  );
  X_FF \U11_U3_counterr<0>_MC.REG  (
    .I(\U11_U3_counterr<0>_MC.D ),
    .CE(Vcc),
    .CLK(\U11_U3_counterr<0>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\U11_U3_counterr<0>_MC.Q )
  );
  X_INV \U11_U3_counterr<0>_MC.REG_tsimcreated_inv_Mclk_II/FCLK_319  (
    .I(\Mclk_II/FCLK ),
    .O(\U11_U3_counterr<0>_MC.REG_tsimcreated_inv_Mclk_II/FCLK )
  );
  X_XOR2 \U11_U3_counterr<0>_MC.D_320  (
    .I0(\U11_U3_counterr<0>_MC.D1 ),
    .I1(\U11_U3_counterr<0>_MC.D2 ),
    .O(\U11_U3_counterr<0>_MC.D )
  );
  X_ZERO \U11_U3_counterr<0>_MC.D1_321  (
    .O(\U11_U3_counterr<0>_MC.D1 )
  );
  X_AND2 \U11_U3_counterr<0>_MC.D2_PT_0_322  (
    .I0(\SCLreset_II/UIM ),
    .I1(\SCLinc_II/UIM ),
    .O(\U11_U3_counterr<0>_MC.D2_PT_0 )
  );
  X_AND4 \U11_U3_counterr<0>_MC.D2_PT_1_323  (
    .I0(U11_Incdetect),
    .I1(U11_SCLdetect),
    .I2(U11_U3_counterr[0]),
    .I3(\NlwInverterSignal_U11_U3_counterr<0>_MC.D2_PT_1/IN3 ),
    .O(\U11_U3_counterr<0>_MC.D2_PT_1 )
  );
  X_AND4 \U11_U3_counterr<0>_MC.D2_PT_2_324  (
    .I0(U11_Incdetect),
    .I1(\NlwInverterSignal_U11_U3_counterr<0>_MC.D2_PT_2/IN1 ),
    .I2(\NlwInverterSignal_U11_U3_counterr<0>_MC.D2_PT_2/IN2 ),
    .I3(\NlwInverterSignal_U11_U3_counterr<0>_MC.D2_PT_2/IN3 ),
    .O(\U11_U3_counterr<0>_MC.D2_PT_2 )
  );
  X_AND4 \U11_U3_counterr<0>_MC.D2_PT_3_325  (
    .I0(U11_Incdetect),
    .I1(\NlwInverterSignal_U11_U3_counterr<0>_MC.D2_PT_3/IN1 ),
    .I2(\NlwInverterSignal_U11_U3_counterr<0>_MC.D2_PT_3/IN2 ),
    .I3(U11_ResetDetect),
    .O(\U11_U3_counterr<0>_MC.D2_PT_3 )
  );
  X_AND4 \U11_U3_counterr<0>_MC.D2_PT_4_326  (
    .I0(\NlwInverterSignal_U11_U3_counterr<0>_MC.D2_PT_4/IN0 ),
    .I1(\NlwInverterSignal_U11_U3_counterr<0>_MC.D2_PT_4/IN1 ),
    .I2(U11_U3_counterr[0]),
    .I3(\NlwInverterSignal_U11_U3_counterr<0>_MC.D2_PT_4/IN3 ),
    .O(\U11_U3_counterr<0>_MC.D2_PT_4 )
  );
  X_AND5 \U11_U3_counterr<0>_MC.D2_PT_5_327  (
    .I0(\NlwInverterSignal_U11_U3_counterr<0>_MC.D2_PT_5/IN0 ),
    .I1(U11_SCLdetect),
    .I2(\NlwInverterSignal_U11_U3_counterr<0>_MC.D2_PT_5/IN2 ),
    .I3(\NlwInverterSignal_U11_U3_counterr<0>_MC.D2_PT_5/IN3 ),
    .I4(\NlwInverterSignal_U11_U3_counterr<0>_MC.D2_PT_5/IN4 ),
    .O(\U11_U3_counterr<0>_MC.D2_PT_5 )
  );
  X_OR6 \U11_U3_counterr<0>_MC.D2_328  (
    .I0(\U11_U3_counterr<0>_MC.D2_PT_0 ),
    .I1(\U11_U3_counterr<0>_MC.D2_PT_1 ),
    .I2(\U11_U3_counterr<0>_MC.D2_PT_2 ),
    .I3(\U11_U3_counterr<0>_MC.D2_PT_3 ),
    .I4(\U11_U3_counterr<0>_MC.D2_PT_4 ),
    .I5(\U11_U3_counterr<0>_MC.D2_PT_5 ),
    .O(\U11_U3_counterr<0>_MC.D2 )
  );
  X_BUF \U11_U3_counterr<1>  (
    .I(\U11_U3_counterr<1>_MC.Q ),
    .O(U11_U3_counterr[1])
  );
  X_XOR2 \U11_U3_counterr<1>_MC_tsimcreated_xor__329  (
    .I0(\U11_U3_counterr<1>_MC.D ),
    .I1(\U11_U3_counterr<1>_MC.Q ),
    .O(\U11_U3_counterr<1>_MC_tsimcreated_xor_ )
  );
  X_FF \U11_U3_counterr<1>_MC.REG  (
    .I(\U11_U3_counterr<1>_MC_tsimcreated_xor_ ),
    .CE(Vcc),
    .CLK(\U11_U3_counterr<1>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\U11_U3_counterr<1>_MC.Q )
  );
  X_INV \U11_U3_counterr<1>_MC.REG_tsimcreated_inv_Mclk_II/FCLK_330  (
    .I(\Mclk_II/FCLK ),
    .O(\U11_U3_counterr<1>_MC.REG_tsimcreated_inv_Mclk_II/FCLK )
  );
  X_XOR2 \U11_U3_counterr<1>_MC.D_331  (
    .I0(\U11_U3_counterr<1>_MC.D1 ),
    .I1(\U11_U3_counterr<1>_MC.D2 ),
    .O(\U11_U3_counterr<1>_MC.D )
  );
  X_AND2 \U11_U3_counterr<1>_MC.D1_332  (
    .I0(N_PZ_1065),
    .I1(U11_U3_counterr[1]),
    .O(\U11_U3_counterr<1>_MC.D1 )
  );
  X_AND3 \U11_U3_counterr<1>_MC.D2_PT_0_333  (
    .I0(N_PZ_1065),
    .I1(\SCLreset_II/UIM ),
    .I2(\NlwInverterSignal_U11_U3_counterr<1>_MC.D2_PT_0/IN2 ),
    .O(\U11_U3_counterr<1>_MC.D2_PT_0 )
  );
  X_AND4 \U11_U3_counterr<1>_MC.D2_PT_1_334  (
    .I0(\NlwInverterSignal_U11_U3_counterr<1>_MC.D2_PT_1/IN0 ),
    .I1(U11_Incdetect),
    .I2(\NlwInverterSignal_U11_U3_counterr<1>_MC.D2_PT_1/IN2 ),
    .I3(U11_U3_counterr[0]),
    .O(\U11_U3_counterr<1>_MC.D2_PT_1 )
  );
  X_AND4 \U11_U3_counterr<1>_MC.D2_PT_2_335  (
    .I0(\NlwInverterSignal_U11_U3_counterr<1>_MC.D2_PT_2/IN0 ),
    .I1(\NlwInverterSignal_U11_U3_counterr<1>_MC.D2_PT_2/IN1 ),
    .I2(U11_SCLdetect),
    .I3(\NlwInverterSignal_U11_U3_counterr<1>_MC.D2_PT_2/IN3 ),
    .O(\U11_U3_counterr<1>_MC.D2_PT_2 )
  );
  X_OR3 \U11_U3_counterr<1>_MC.D2_336  (
    .I0(\U11_U3_counterr<1>_MC.D2_PT_0 ),
    .I1(\U11_U3_counterr<1>_MC.D2_PT_1 ),
    .I2(\U11_U3_counterr<1>_MC.D2_PT_2 ),
    .O(\U11_U3_counterr<1>_MC.D2 )
  );
  X_BUF \U11_U3_counterr<2>  (
    .I(\U11_U3_counterr<2>_MC.Q ),
    .O(U11_U3_counterr[2])
  );
  X_XOR2 \U11_U3_counterr<2>_MC_tsimcreated_xor__337  (
    .I0(\U11_U3_counterr<2>_MC.D ),
    .I1(\U11_U3_counterr<2>_MC.Q ),
    .O(\U11_U3_counterr<2>_MC_tsimcreated_xor_ )
  );
  X_FF \U11_U3_counterr<2>_MC.REG  (
    .I(\U11_U3_counterr<2>_MC_tsimcreated_xor_ ),
    .CE(Vcc),
    .CLK(\U11_U3_counterr<2>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\U11_U3_counterr<2>_MC.Q )
  );
  X_INV \U11_U3_counterr<2>_MC.REG_tsimcreated_inv_Mclk_II/FCLK_338  (
    .I(\Mclk_II/FCLK ),
    .O(\U11_U3_counterr<2>_MC.REG_tsimcreated_inv_Mclk_II/FCLK )
  );
  X_XOR2 \U11_U3_counterr<2>_MC.D_339  (
    .I0(\U11_U3_counterr<2>_MC.D1 ),
    .I1(\U11_U3_counterr<2>_MC.D2 ),
    .O(\U11_U3_counterr<2>_MC.D )
  );
  X_ZERO \U11_U3_counterr<2>_MC.D1_340  (
    .O(\U11_U3_counterr<2>_MC.D1 )
  );
  X_AND2 \U11_U3_counterr<2>_MC.D2_PT_0_341  (
    .I0(N_PZ_1065),
    .I1(U11_U3_counterr[2]),
    .O(\U11_U3_counterr<2>_MC.D2_PT_0 )
  );
  X_AND5 \U11_U3_counterr<2>_MC.D2_PT_1_342  (
    .I0(\NlwInverterSignal_U11_U3_counterr<2>_MC.D2_PT_1/IN0 ),
    .I1(U11_Incdetect),
    .I2(\NlwInverterSignal_U11_U3_counterr<2>_MC.D2_PT_1/IN2 ),
    .I3(U11_U3_counterr[0]),
    .I4(U11_U3_counterr[1]),
    .O(\U11_U3_counterr<2>_MC.D2_PT_1 )
  );
  X_AND5 \U11_U3_counterr<2>_MC.D2_PT_2_343  (
    .I0(\NlwInverterSignal_U11_U3_counterr<2>_MC.D2_PT_2/IN0 ),
    .I1(\NlwInverterSignal_U11_U3_counterr<2>_MC.D2_PT_2/IN1 ),
    .I2(U11_SCLdetect),
    .I3(\NlwInverterSignal_U11_U3_counterr<2>_MC.D2_PT_2/IN3 ),
    .I4(\NlwInverterSignal_U11_U3_counterr<2>_MC.D2_PT_2/IN4 ),
    .O(\U11_U3_counterr<2>_MC.D2_PT_2 )
  );
  X_OR3 \U11_U3_counterr<2>_MC.D2_344  (
    .I0(\U11_U3_counterr<2>_MC.D2_PT_0 ),
    .I1(\U11_U3_counterr<2>_MC.D2_PT_1 ),
    .I2(\U11_U3_counterr<2>_MC.D2_PT_2 ),
    .O(\U11_U3_counterr<2>_MC.D2 )
  );
  X_BUF \U11_U3_counterr<4>  (
    .I(\U11_U3_counterr<4>_MC.Q ),
    .O(U11_U3_counterr[4])
  );
  X_XOR2 \U11_U3_counterr<4>_MC_tsimcreated_xor__345  (
    .I0(\U11_U3_counterr<4>_MC.D ),
    .I1(\U11_U3_counterr<4>_MC.Q ),
    .O(\U11_U3_counterr<4>_MC_tsimcreated_xor_ )
  );
  X_FF \U11_U3_counterr<4>_MC.REG  (
    .I(\U11_U3_counterr<4>_MC_tsimcreated_xor_ ),
    .CE(Vcc),
    .CLK(\U11_U3_counterr<4>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\U11_U3_counterr<4>_MC.Q )
  );
  X_INV \U11_U3_counterr<4>_MC.REG_tsimcreated_inv_Mclk_II/FCLK_346  (
    .I(\Mclk_II/FCLK ),
    .O(\U11_U3_counterr<4>_MC.REG_tsimcreated_inv_Mclk_II/FCLK )
  );
  X_XOR2 \U11_U3_counterr<4>_MC.D_347  (
    .I0(\U11_U3_counterr<4>_MC.D1 ),
    .I1(\U11_U3_counterr<4>_MC.D2 ),
    .O(\U11_U3_counterr<4>_MC.D )
  );
  X_ZERO \U11_U3_counterr<4>_MC.D1_348  (
    .O(\U11_U3_counterr<4>_MC.D1 )
  );
  X_AND2 \U11_U3_counterr<4>_MC.D2_PT_0_349  (
    .I0(N_PZ_1065),
    .I1(U11_U3_counterr[4]),
    .O(\U11_U3_counterr<4>_MC.D2_PT_0 )
  );
  X_AND3 \U11_U3_counterr<4>_MC.D2_PT_1_350  (
    .I0(\NlwInverterSignal_U11_U3_counterr<4>_MC.D2_PT_1/IN0 ),
    .I1(U11_Incdetect),
    .I2(U11_U3_counterr[3]),
    .O(\U11_U3_counterr<4>_MC.D2_PT_1 )
  );
  X_AND6 \U11_U3_counterr<4>_MC.D2_PT_2_351  (
    .I0(\NlwInverterSignal_U11_U3_counterr<4>_MC.D2_PT_2/IN0 ),
    .I1(U11_Incdetect),
    .I2(\NlwInverterSignal_U11_U3_counterr<4>_MC.D2_PT_2/IN2 ),
    .I3(U11_U3_counterr[0]),
    .I4(U11_U3_counterr[1]),
    .I5(U11_U3_counterr[2]),
    .O(\U11_U3_counterr<4>_MC.D2_PT_2 )
  );
  X_AND7 \U11_U3_counterr<4>_MC.D2_PT_3_352  (
    .I0(\NlwInverterSignal_U11_U3_counterr<4>_MC.D2_PT_3/IN0 ),
    .I1(\NlwInverterSignal_U11_U3_counterr<4>_MC.D2_PT_3/IN1 ),
    .I2(\NlwInverterSignal_U11_U3_counterr<4>_MC.D2_PT_3/IN2 ),
    .I3(U11_SCLdetect),
    .I4(\NlwInverterSignal_U11_U3_counterr<4>_MC.D2_PT_3/IN4 ),
    .I5(\NlwInverterSignal_U11_U3_counterr<4>_MC.D2_PT_3/IN5 ),
    .I6(\NlwInverterSignal_U11_U3_counterr<4>_MC.D2_PT_3/IN6 ),
    .O(\U11_U3_counterr<4>_MC.D2_PT_3 )
  );
  X_OR4 \U11_U3_counterr<4>_MC.D2_353  (
    .I0(\U11_U3_counterr<4>_MC.D2_PT_0 ),
    .I1(\U11_U3_counterr<4>_MC.D2_PT_1 ),
    .I2(\U11_U3_counterr<4>_MC.D2_PT_2 ),
    .I3(\U11_U3_counterr<4>_MC.D2_PT_3 ),
    .O(\U11_U3_counterr<4>_MC.D2 )
  );
  X_BUF \outDATA<7>\$WA4.UIM_354  (
    .I(\outDATA<7>\$WA4.UIM_MC.Q ),
    .O(\outDATA<7>\$WA4.UIM )
  );
  X_BUF \outDATA<7>\$WA4.UIM_MC.Q_355  (
    .I(\outDATA<7>\$WA4.UIM_MC.D ),
    .O(\outDATA<7>\$WA4.UIM_MC.Q )
  );
  X_XOR2 \outDATA<7>\$WA4.UIM_MC.D_356  (
    .I0(\outDATA<7>\$WA4.UIM_MC.D1 ),
    .I1(\outDATA<7>\$WA4.UIM_MC.D2 ),
    .O(\outDATA<7>\$WA4.UIM_MC.D )
  );
  X_AND2 \outDATA<7>\$WA4.UIM_MC.D1_357  (
    .I0(\TP12_MC.UIM ),
    .I1(\TP12_MC.UIM ),
    .O(\outDATA<7>\$WA4.UIM_MC.D1 )
  );
  X_ZERO \outDATA<7>\$WA4.UIM_MC.D2_358  (
    .O(\outDATA<7>\$WA4.UIM_MC.D2 )
  );
  X_BUF DCORCONFIGr_359 (
    .I(\DCORCONFIGr_MC.Q ),
    .O(DCORCONFIGr)
  );
  X_BUF \DCORCONFIGr_MC.Q_360  (
    .I(\DCORCONFIGr_MC.D ),
    .O(\DCORCONFIGr_MC.Q )
  );
  X_XOR2 \DCORCONFIGr_MC.D_361  (
    .I0(\DCORCONFIGr_MC.D1 ),
    .I1(\DCORCONFIGr_MC.D2 ),
    .O(\DCORCONFIGr_MC.D )
  );
  X_AND16 \DCORCONFIGr_MC.D1_362  (
    .I0(\WR_II/UIM ),
    .I1(\NlwInverterSignal_DCORCONFIGr_MC.D1/IN1 ),
    .I2(U2_ADDR_reg[0]),
    .I3(\NlwInverterSignal_DCORCONFIGr_MC.D1/IN3 ),
    .I4(\NlwInverterSignal_DCORCONFIGr_MC.D1/IN4 ),
    .I5(\NlwInverterSignal_DCORCONFIGr_MC.D1/IN5 ),
    .I6(\NlwInverterSignal_DCORCONFIGr_MC.D1/IN6 ),
    .I7(U2_ADDR_reg[3]),
    .I8(U2_ADDR_reg[1]),
    .I9(U2_ADDR_reg[2]),
    .I10(Vcc),
    .I11(Vcc),
    .I12(Vcc),
    .I13(Vcc),
    .I14(Vcc),
    .I15(Vcc),
    .O(\DCORCONFIGr_MC.D1 )
  );
  X_ZERO \DCORCONFIGr_MC.D2_363  (
    .O(\DCORCONFIGr_MC.D2 )
  );
  X_BUF \outDATA<5>\$WA1.UIM_364  (
    .I(\outDATA<5>\$WA1.UIM_MC.Q ),
    .O(\outDATA<5>\$WA1.UIM )
  );
  X_BUF \outDATA<5>\$WA1.UIM_MC.Q_365  (
    .I(\outDATA<5>\$WA1.UIM_MC.D ),
    .O(\outDATA<5>\$WA1.UIM_MC.Q )
  );
  X_XOR2 \outDATA<5>\$WA1.UIM_MC.D_366  (
    .I0(\outDATA<5>\$WA1.UIM_MC.D1 ),
    .I1(\outDATA<5>\$WA1.UIM_MC.D2 ),
    .O(\outDATA<5>\$WA1.UIM_MC.D )
  );
  X_AND2 \outDATA<5>\$WA1.UIM_MC.D1_367  (
    .I0(\I2CS<5>_II/UIM ),
    .I1(\I2CS<5>_II/UIM ),
    .O(\outDATA<5>\$WA1.UIM_MC.D1 )
  );
  X_ZERO \outDATA<5>\$WA1.UIM_MC.D2_368  (
    .O(\outDATA<5>\$WA1.UIM_MC.D2 )
  );
  X_BUF DCORLIMITSr_369 (
    .I(\DCORLIMITSr_MC.Q ),
    .O(DCORLIMITSr)
  );
  X_BUF \DCORLIMITSr_MC.Q_370  (
    .I(\DCORLIMITSr_MC.D ),
    .O(\DCORLIMITSr_MC.Q )
  );
  X_XOR2 \DCORLIMITSr_MC.D_371  (
    .I0(\DCORLIMITSr_MC.D1 ),
    .I1(\DCORLIMITSr_MC.D2 ),
    .O(\DCORLIMITSr_MC.D )
  );
  X_AND16 \DCORLIMITSr_MC.D1_372  (
    .I0(\WR_II/UIM ),
    .I1(\NlwInverterSignal_DCORLIMITSr_MC.D1/IN1 ),
    .I2(\NlwInverterSignal_DCORLIMITSr_MC.D1/IN2 ),
    .I3(\NlwInverterSignal_DCORLIMITSr_MC.D1/IN3 ),
    .I4(\NlwInverterSignal_DCORLIMITSr_MC.D1/IN4 ),
    .I5(\NlwInverterSignal_DCORLIMITSr_MC.D1/IN5 ),
    .I6(\NlwInverterSignal_DCORLIMITSr_MC.D1/IN6 ),
    .I7(\NlwInverterSignal_DCORLIMITSr_MC.D1/IN7 ),
    .I8(U2_ADDR_reg[1]),
    .I9(\NlwInverterSignal_DCORLIMITSr_MC.D1/IN9 ),
    .I10(Vcc),
    .I11(Vcc),
    .I12(Vcc),
    .I13(Vcc),
    .I14(Vcc),
    .I15(Vcc),
    .O(\DCORLIMITSr_MC.D1 )
  );
  X_ZERO \DCORLIMITSr_MC.D2_373  (
    .O(\DCORLIMITSr_MC.D2 )
  );
  X_BUF \outDATA<5>\$WA2.UIM_374  (
    .I(\outDATA<5>\$WA2.UIM_MC.Q ),
    .O(\outDATA<5>\$WA2.UIM )
  );
  X_BUF \outDATA<5>\$WA2.UIM_MC.Q_375  (
    .I(\outDATA<5>\$WA2.UIM_MC.D ),
    .O(\outDATA<5>\$WA2.UIM_MC.Q )
  );
  X_XOR2 \outDATA<5>\$WA2.UIM_MC.D_376  (
    .I0(\outDATA<5>\$WA2.UIM_MC.D1 ),
    .I1(\outDATA<5>\$WA2.UIM_MC.D2 ),
    .O(\outDATA<5>\$WA2.UIM_MC.D )
  );
  X_AND2 \outDATA<5>\$WA2.UIM_MC.D1_377  (
    .I0(\FLS1_II/UIM ),
    .I1(\FLS1_II/UIM ),
    .O(\outDATA<5>\$WA2.UIM_MC.D1 )
  );
  X_ZERO \outDATA<5>\$WA2.UIM_MC.D2_378  (
    .O(\outDATA<5>\$WA2.UIM_MC.D2 )
  );
  X_BUF DCORENCPWRr_379 (
    .I(\DCORENCPWRr_MC.Q ),
    .O(DCORENCPWRr)
  );
  X_BUF \DCORENCPWRr_MC.Q_380  (
    .I(\DCORENCPWRr_MC.D ),
    .O(\DCORENCPWRr_MC.Q )
  );
  X_XOR2 \DCORENCPWRr_MC.D_381  (
    .I0(\DCORENCPWRr_MC.D1 ),
    .I1(\DCORENCPWRr_MC.D2 ),
    .O(\DCORENCPWRr_MC.D )
  );
  X_AND16 \DCORENCPWRr_MC.D1_382  (
    .I0(\WR_II/UIM ),
    .I1(\NlwInverterSignal_DCORENCPWRr_MC.D1/IN1 ),
    .I2(\NlwInverterSignal_DCORENCPWRr_MC.D1/IN2 ),
    .I3(\NlwInverterSignal_DCORENCPWRr_MC.D1/IN3 ),
    .I4(\NlwInverterSignal_DCORENCPWRr_MC.D1/IN4 ),
    .I5(\NlwInverterSignal_DCORENCPWRr_MC.D1/IN5 ),
    .I6(\NlwInverterSignal_DCORENCPWRr_MC.D1/IN6 ),
    .I7(U2_ADDR_reg[3]),
    .I8(U2_ADDR_reg[1]),
    .I9(U2_ADDR_reg[2]),
    .I10(Vcc),
    .I11(Vcc),
    .I12(Vcc),
    .I13(Vcc),
    .I14(Vcc),
    .I15(Vcc),
    .O(\DCORENCPWRr_MC.D1 )
  );
  X_ZERO \DCORENCPWRr_MC.D2_383  (
    .O(\DCORENCPWRr_MC.D2 )
  );
  X_BUF \outDATA<5>\$WA3.UIM_384  (
    .I(\outDATA<5>\$WA3.UIM_MC.Q ),
    .O(\outDATA<5>\$WA3.UIM )
  );
  X_BUF \outDATA<5>\$WA3.UIM_MC.Q_385  (
    .I(\outDATA<5>\$WA3.UIM_MC.D ),
    .O(\outDATA<5>\$WA3.UIM_MC.Q )
  );
  X_XOR2 \outDATA<5>\$WA3.UIM_MC.D_386  (
    .I0(\outDATA<5>\$WA3.UIM_MC.D1 ),
    .I1(\outDATA<5>\$WA3.UIM_MC.D2 ),
    .O(\outDATA<5>\$WA3.UIM_MC.D )
  );
  X_ZERO \outDATA<5>\$WA3.UIM_MC.D1_387  (
    .O(\outDATA<5>\$WA3.UIM_MC.D1 )
  );
  X_AND2 \outDATA<5>\$WA3.UIM_MC.D2_PT_0_388  (
    .I0(\Home15FLG_II/UIM ),
    .I1(\NlwInverterSignal_outDATA<5>\$WA3.UIM_MC.D2_PT_0/IN1 ),
    .O(\outDATA<5>\$WA3.UIM_MC.D2_PT_0 )
  );
  X_AND2 \outDATA<5>\$WA3.UIM_MC.D2_PT_1_389  (
    .I0(NET2528),
    .I1(\U4/Flgreg [5]),
    .O(\outDATA<5>\$WA3.UIM_MC.D2_PT_1 )
  );
  X_OR2 \outDATA<5>\$WA3.UIM_MC.D2_390  (
    .I0(\outDATA<5>\$WA3.UIM_MC.D2_PT_0 ),
    .I1(\outDATA<5>\$WA3.UIM_MC.D2_PT_1 ),
    .O(\outDATA<5>\$WA3.UIM_MC.D2 )
  );
  X_BUF NET2528_391 (
    .I(\NET2528_MC.Q ),
    .O(NET2528)
  );
  X_FF \NET2528_MC.REG  (
    .I(\NET2528_MC.D ),
    .CE(Vcc),
    .CLK(\NET2528_MC.REG_tsimcreated_inv_Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\NET2528_MC.Q )
  );
  X_INV \NET2528_MC.REG_tsimcreated_inv_Mclk_II/FCLK_392  (
    .I(\Mclk_II/FCLK ),
    .O(\NET2528_MC.REG_tsimcreated_inv_Mclk_II/FCLK )
  );
  X_XOR2 \NET2528_MC.D_393  (
    .I0(\NET2528_MC.D1 ),
    .I1(\NET2528_MC.D2 ),
    .O(\NET2528_MC.D )
  );
  X_AND2 \NET2528_MC.D1_394  (
    .I0(\MSPReset_II/UIM ),
    .I1(\NlwInverterSignal_NET2528_MC.D1/IN1 ),
    .O(\NET2528_MC.D1 )
  );
  X_AND4 \NET2528_MC.D2_PT_0_395  (
    .I0(\MSPReset_II/UIM ),
    .I1(\NlwInverterSignal_NET2528_MC.D2_PT_0/IN1 ),
    .I2(NET2528),
    .I3(DCORIFGw),
    .O(\NET2528_MC.D2_PT_0 )
  );
  X_AND16 \NET2528_MC.D2_PT_1_396  (
    .I0(\MSPReset_II/UIM ),
    .I1(\Home15FLG_II/UIM ),
    .I2(\NlwInverterSignal_NET2528_MC.D2_PT_1/IN2 ),
    .I3(\NlwInverterSignal_NET2528_MC.D2_PT_1/IN3 ),
    .I4(\Home133FLG_II/UIM ),
    .I5(\Home05FLG_II/UIM ),
    .I6(\Home033FLG_II/UIM ),
    .I7(\Enc15FLG_II/UIM ),
    .I8(\Enc133FLG_II/UIM ),
    .I9(\Enc05FLG_II/UIM ),
    .I10(\Enc033FLG_II/UIM ),
    .I11(Vcc),
    .I12(Vcc),
    .I13(Vcc),
    .I14(Vcc),
    .I15(Vcc),
    .O(\NET2528_MC.D2_PT_1 )
  );
  X_OR2 \NET2528_MC.D2_397  (
    .I0(\NET2528_MC.D2_PT_0 ),
    .I1(\NET2528_MC.D2_PT_1 ),
    .O(\NET2528_MC.D2 )
  );
  X_BUF DCORIFGw_398 (
    .I(\DCORIFGw_MC.Q ),
    .O(DCORIFGw)
  );
  X_BUF \DCORIFGw_MC.Q_399  (
    .I(\DCORIFGw_MC.D ),
    .O(\DCORIFGw_MC.Q )
  );
  X_XOR2 \DCORIFGw_MC.D_400  (
    .I0(\DCORIFGw_MC.D1 ),
    .I1(\DCORIFGw_MC.D2 ),
    .O(\DCORIFGw_MC.D )
  );
  X_AND16 \DCORIFGw_MC.D1_401  (
    .I0(\NlwInverterSignal_DCORIFGw_MC.D1/IN0 ),
    .I1(\RD_II/UIM ),
    .I2(U2_ADDR_reg[0]),
    .I3(\NlwInverterSignal_DCORIFGw_MC.D1/IN3 ),
    .I4(\NlwInverterSignal_DCORIFGw_MC.D1/IN4 ),
    .I5(\NlwInverterSignal_DCORIFGw_MC.D1/IN5 ),
    .I6(\NlwInverterSignal_DCORIFGw_MC.D1/IN6 ),
    .I7(\NlwInverterSignal_DCORIFGw_MC.D1/IN7 ),
    .I8(\NlwInverterSignal_DCORIFGw_MC.D1/IN8 ),
    .I9(\NlwInverterSignal_DCORIFGw_MC.D1/IN9 ),
    .I10(Vcc),
    .I11(Vcc),
    .I12(Vcc),
    .I13(Vcc),
    .I14(Vcc),
    .I15(Vcc),
    .O(\DCORIFGw_MC.D1 )
  );
  X_ZERO \DCORIFGw_MC.D2_402  (
    .O(\DCORIFGw_MC.D2 )
  );
  X_BUF \U4/orFLGs_403  (
    .I(\U4/orFLGs_MC.Q ),
    .O(\U4/orFLGs )
  );
  X_BUF \U4/orFLGs_MC.Q_404  (
    .I(\U4/orFLGs_MC.D ),
    .O(\U4/orFLGs_MC.Q )
  );
  X_XOR2 \U4/orFLGs_MC.D_405  (
    .I0(\U4/orFLGs_MC.D1 ),
    .I1(\U4/orFLGs_MC.D2 ),
    .O(\U4/orFLGs_MC.D )
  );
  X_AND8 \U4/orFLGs_MC.D1_406  (
    .I0(\Home15FLG_II/UIM ),
    .I1(\Home133FLG_II/UIM ),
    .I2(\Home05FLG_II/UIM ),
    .I3(\Home033FLG_II/UIM ),
    .I4(\Enc15FLG_II/UIM ),
    .I5(\Enc133FLG_II/UIM ),
    .I6(\Enc05FLG_II/UIM ),
    .I7(\Enc033FLG_II/UIM ),
    .O(\U4/orFLGs_MC.D1 )
  );
  X_ZERO \U4/orFLGs_MC.D2_407  (
    .O(\U4/orFLGs_MC.D2 )
  );
  X_BUF \outDATA<5>\$WA5.UIM_408  (
    .I(\outDATA<5>\$WA5.UIM_MC.Q ),
    .O(\outDATA<5>\$WA5.UIM )
  );
  X_BUF \outDATA<5>\$WA5.UIM_MC.Q_409  (
    .I(\outDATA<5>\$WA5.UIM_MC.D ),
    .O(\outDATA<5>\$WA5.UIM_MC.Q )
  );
  X_XOR2 \outDATA<5>\$WA5.UIM_MC.D_410  (
    .I0(\outDATA<5>\$WA5.UIM_MC.D1 ),
    .I1(\outDATA<5>\$WA5.UIM_MC.D2 ),
    .O(\outDATA<5>\$WA5.UIM_MC.D )
  );
  X_ZERO \outDATA<5>\$WA5.UIM_MC.D1_411  (
    .O(\outDATA<5>\$WA5.UIM_MC.D1 )
  );
  X_AND2 \outDATA<5>\$WA5.UIM_MC.D2_PT_0_412  (
    .I0(\U1/U3/holdingreg0 [5]),
    .I1(DCOR0CNTLOWr),
    .O(\outDATA<5>\$WA5.UIM_MC.D2_PT_0 )
  );
  X_AND3 \outDATA<5>\$WA5.UIM_MC.D2_PT_1_413  (
    .I0(\NlwInverterSignal_outDATA<5>\$WA5.UIM_MC.D2_PT_1/IN0 ),
    .I1(\U1/U3/holdingreg1 [5]),
    .I2(DCOR1CNTLOWr),
    .O(\outDATA<5>\$WA5.UIM_MC.D2_PT_1 )
  );
  X_AND4 \outDATA<5>\$WA5.UIM_MC.D2_PT_2_414  (
    .I0(\NlwInverterSignal_outDATA<5>\$WA5.UIM_MC.D2_PT_2/IN0 ),
    .I1(\NlwInverterSignal_outDATA<5>\$WA5.UIM_MC.D2_PT_2/IN1 ),
    .I2(\U1/U3/holdingreg0 [13]),
    .I3(DCOR0CNTHIGHr),
    .O(\outDATA<5>\$WA5.UIM_MC.D2_PT_2 )
  );
  X_AND4 \outDATA<5>\$WA5.UIM_MC.D2_PT_3_415  (
    .I0(\NlwInverterSignal_outDATA<5>\$WA5.UIM_MC.D2_PT_3/IN0 ),
    .I1(\NlwInverterSignal_outDATA<5>\$WA5.UIM_MC.D2_PT_3/IN1 ),
    .I2(\NlwInverterSignal_outDATA<5>\$WA5.UIM_MC.D2_PT_3/IN2 ),
    .I3(\U1/U3/holdingreg1 [13]),
    .O(\outDATA<5>\$WA5.UIM_MC.D2_PT_3 )
  );
  X_OR4 \outDATA<5>\$WA5.UIM_MC.D2_416  (
    .I0(\outDATA<5>\$WA5.UIM_MC.D2_PT_0 ),
    .I1(\outDATA<5>\$WA5.UIM_MC.D2_PT_1 ),
    .I2(\outDATA<5>\$WA5.UIM_MC.D2_PT_2 ),
    .I3(\outDATA<5>\$WA5.UIM_MC.D2_PT_3 ),
    .O(\outDATA<5>\$WA5.UIM_MC.D2 )
  );
  X_BUF \U1/U3/holdingreg0<5>  (
    .I(\U1/U3/holdingreg0<5>_MC.Q ),
    .O(\U1/U3/holdingreg0 [5])
  );
  X_FF \U1/U3/holdingreg0<5>_MC.REG  (
    .I(\U1/U3/holdingreg0<5>_MC.D ),
    .CE(Vcc),
    .CLK(\U1/U3/holdingreg0<5>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\U1/U3/holdingreg0<5>_MC.Q )
  );
  X_INV \U1/U3/holdingreg0<5>_MC.REG_tsimcreated_inv_Mclk_II/FCLK_417  (
    .I(\Mclk_II/FCLK ),
    .O(\U1/U3/holdingreg0<5>_MC.REG_tsimcreated_inv_Mclk_II/FCLK )
  );
  X_XOR2 \U1/U3/holdingreg0<5>_MC.D_418  (
    .I0(\U1/U3/holdingreg0<5>_MC.D1 ),
    .I1(\U1/U3/holdingreg0<5>_MC.D2 ),
    .O(\U1/U3/holdingreg0<5>_MC.D )
  );
  X_ZERO \U1/U3/holdingreg0<5>_MC.D1_419  (
    .O(\U1/U3/holdingreg0<5>_MC.D1 )
  );
  X_AND2 \U1/U3/holdingreg0<5>_MC.D2_PT_0_420  (
    .I0(N_PZ_938),
    .I1(\U1/U3/holdingreg0 [5]),
    .O(\U1/U3/holdingreg0<5>_MC.D2_PT_0 )
  );
  X_AND4 \U1/U3/holdingreg0<5>_MC.D2_PT_1_421  (
    .I0(\MSPReset_II/UIM ),
    .I1(\NlwInverterSignal_U1/U3/holdingreg0<5>_MC.D2_PT_1/IN1 ),
    .I2(U2_ASedge),
    .I3(\U1/Channel0 [5]),
    .O(\U1/U3/holdingreg0<5>_MC.D2_PT_1 )
  );
  X_OR2 \U1/U3/holdingreg0<5>_MC.D2_422  (
    .I0(\U1/U3/holdingreg0<5>_MC.D2_PT_0 ),
    .I1(\U1/U3/holdingreg0<5>_MC.D2_PT_1 ),
    .O(\U1/U3/holdingreg0<5>_MC.D2 )
  );
  X_BUF \U1/Channel0<5>  (
    .I(\U1/Channel0<5>_MC.Q ),
    .O(\U1/Channel0 [5])
  );
  X_XOR2 \U1/Channel0<5>_MC_tsimcreated_xor__423  (
    .I0(\U1/Channel0<5>_MC.D ),
    .I1(\U1/Channel0<5>_MC.Q ),
    .O(\U1/Channel0<5>_MC_tsimcreated_xor_ )
  );
  X_FF \U1/Channel0<5>_MC.REG  (
    .I(\U1/Channel0<5>_MC_tsimcreated_xor_ ),
    .CE(Vcc),
    .CLK(\Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\U1/Channel0<5>_MC.Q )
  );
  X_XOR2 \U1/Channel0<5>_MC.D_424  (
    .I0(\U1/Channel0<5>_MC.D1 ),
    .I1(\U1/Channel0<5>_MC.D2 ),
    .O(\U1/Channel0<5>_MC.D )
  );
  X_ZERO \U1/Channel0<5>_MC.D1_425  (
    .O(\U1/Channel0<5>_MC.D1 )
  );
  X_AND2 \U1/Channel0<5>_MC.D2_PT_0_426  (
    .I0(\U1/Channel0 [5]),
    .I1(\NlwInverterSignal_U1/Channel0<5>_MC.D2_PT_0/IN1 ),
    .O(\U1/Channel0<5>_MC.D2_PT_0 )
  );
  X_AND2 \U1/Channel0<5>_MC.D2_PT_1_427  (
    .I0(\U1/U2/location_Maddsub__n0000__n0067 [0]),
    .I1(N_PZ_964),
    .O(\U1/Channel0<5>_MC.D2_PT_1 )
  );
  X_AND2 \U1/Channel0<5>_MC.D2_PT_2_428  (
    .I0(\NlwInverterSignal_U1/Channel0<5>_MC.D2_PT_2/IN0 ),
    .I1(N_PZ_968),
    .O(\U1/Channel0<5>_MC.D2_PT_2 )
  );
  X_OR3 \U1/Channel0<5>_MC.D2_429  (
    .I0(\U1/Channel0<5>_MC.D2_PT_0 ),
    .I1(\U1/Channel0<5>_MC.D2_PT_1 ),
    .I2(\U1/Channel0<5>_MC.D2_PT_2 ),
    .O(\U1/Channel0<5>_MC.D2 )
  );
  X_BUF N_PZ_928_430 (
    .I(\N_PZ_928_MC.Q ),
    .O(N_PZ_928)
  );
  X_BUF \N_PZ_928_MC.Q_431  (
    .I(\N_PZ_928_MC.D ),
    .O(\N_PZ_928_MC.Q )
  );
  X_XOR2 \N_PZ_928_MC.D_432  (
    .I0(\N_PZ_928_MC.D1 ),
    .I1(\N_PZ_928_MC.D2 ),
    .O(\N_PZ_928_MC.D )
  );
  X_AND2 \N_PZ_928_MC.D1_433  (
    .I0(\MSPReset_II/UIM ),
    .I1(\NlwInverterSignal_N_PZ_928_MC.D1/IN1 ),
    .O(\N_PZ_928_MC.D1 )
  );
  X_ZERO \N_PZ_928_MC.D2_434  (
    .O(\N_PZ_928_MC.D2 )
  );
  X_BUF \U1/Zero0_435  (
    .I(\U1/Zero0_MC.Q ),
    .O(\U1/Zero0 )
  );
  X_FF \U1/Zero0_MC.REG  (
    .I(\U1/Zero0_MC.D ),
    .CE(Vcc),
    .CLK(\U1/Zero0_MC.REG_tsimcreated_inv_Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\U1/Zero0_MC.Q )
  );
  X_INV \U1/Zero0_MC.REG_tsimcreated_inv_Mclk_II/FCLK_436  (
    .I(\Mclk_II/FCLK ),
    .O(\U1/Zero0_MC.REG_tsimcreated_inv_Mclk_II/FCLK )
  );
  X_XOR2 \U1/Zero0_MC.D_437  (
    .I0(\U1/Zero0_MC.D1 ),
    .I1(\U1/Zero0_MC.D2 ),
    .O(\U1/Zero0_MC.D )
  );
  X_ZERO \U1/Zero0_MC.D1_438  (
    .O(\U1/Zero0_MC.D1 )
  );
  X_AND2 \U1/Zero0_MC.D2_PT_0_439  (
    .I0(\NlwInverterSignal_U1/Zero0_MC.D2_PT_0/IN0 ),
    .I1(\U1/Zero0 ),
    .O(\U1/Zero0_MC.D2_PT_0 )
  );
  X_AND2 \U1/Zero0_MC.D2_PT_1_440  (
    .I0(DCORIFGw),
    .I1(\U1/Zero0 ),
    .O(\U1/Zero0_MC.D2_PT_1 )
  );
  X_AND2 \U1/Zero0_MC.D2_PT_2_441  (
    .I0(\U1/Zero0 ),
    .I1(DCORENCCTLw),
    .O(\U1/Zero0_MC.D2_PT_2 )
  );
  X_AND8 \U1/Zero0_MC.D2_PT_3_442  (
    .I0(\MSPReset_II/UIM ),
    .I1(\NlwInverterSignal_U1/Zero0_MC.D2_PT_3/IN1 ),
    .I2(\NlwInverterSignal_U1/Zero0_MC.D2_PT_3/IN2 ),
    .I3(\NlwInverterSignal_U1/Zero0_MC.D2_PT_3/IN3 ),
    .I4(\U1/U4/RF0r ),
    .I5(\U1/U4/E0r ),
    .I6(\U1/U4/HE0stater ),
    .I7(\NlwInverterSignal_U1/Zero0_MC.D2_PT_3/IN7 ),
    .O(\U1/Zero0_MC.D2_PT_3 )
  );
  X_AND8 \U1/Zero0_MC.D2_PT_4_443  (
    .I0(\MSPReset_II/UIM ),
    .I1(\NlwInverterSignal_U1/Zero0_MC.D2_PT_4/IN1 ),
    .I2(\NlwInverterSignal_U1/Zero0_MC.D2_PT_4/IN2 ),
    .I3(\NlwInverterSignal_U1/Zero0_MC.D2_PT_4/IN3 ),
    .I4(\NlwInverterSignal_U1/Zero0_MC.D2_PT_4/IN4 ),
    .I5(\U1/U4/E0r ),
    .I6(\NlwInverterSignal_U1/Zero0_MC.D2_PT_4/IN6 ),
    .I7(\U1/U4/HE0statelastr ),
    .O(\U1/Zero0_MC.D2_PT_4 )
  );
  X_OR5 \U1/Zero0_MC.D2_444  (
    .I0(\U1/Zero0_MC.D2_PT_0 ),
    .I1(\U1/Zero0_MC.D2_PT_1 ),
    .I2(\U1/Zero0_MC.D2_PT_2 ),
    .I3(\U1/Zero0_MC.D2_PT_3 ),
    .I4(\U1/Zero0_MC.D2_PT_4 ),
    .O(\U1/Zero0_MC.D2 )
  );
  X_BUF DCORENCCTLw_445 (
    .I(\DCORENCCTLw_MC.Q ),
    .O(DCORENCCTLw)
  );
  X_BUF \DCORENCCTLw_MC.Q_446  (
    .I(\DCORENCCTLw_MC.D ),
    .O(\DCORENCCTLw_MC.Q )
  );
  X_XOR2 \DCORENCCTLw_MC.D_447  (
    .I0(\DCORENCCTLw_MC.D1 ),
    .I1(\DCORENCCTLw_MC.D2 ),
    .O(\DCORENCCTLw_MC.D )
  );
  X_AND16 \DCORENCCTLw_MC.D1_448  (
    .I0(\NlwInverterSignal_DCORENCCTLw_MC.D1/IN0 ),
    .I1(\RD_II/UIM ),
    .I2(U2_ADDR_reg[0]),
    .I3(\NlwInverterSignal_DCORENCCTLw_MC.D1/IN3 ),
    .I4(\NlwInverterSignal_DCORENCCTLw_MC.D1/IN4 ),
    .I5(\NlwInverterSignal_DCORENCCTLw_MC.D1/IN5 ),
    .I6(\NlwInverterSignal_DCORENCCTLw_MC.D1/IN6 ),
    .I7(\NlwInverterSignal_DCORENCCTLw_MC.D1/IN7 ),
    .I8(U2_ADDR_reg[1]),
    .I9(\NlwInverterSignal_DCORENCCTLw_MC.D1/IN9 ),
    .I10(Vcc),
    .I11(Vcc),
    .I12(Vcc),
    .I13(Vcc),
    .I14(Vcc),
    .I15(Vcc),
    .O(\DCORENCCTLw_MC.D1 )
  );
  X_ZERO \DCORENCCTLw_MC.D2_449  (
    .O(\DCORENCCTLw_MC.D2 )
  );
  X_BUF NET2482_450 (
    .I(\NET2482_MC.Q ),
    .O(NET2482)
  );
  X_XOR2 NET2482_MC_tsimcreated_xor__451 (
    .I0(\NET2482_MC.D ),
    .I1(\NET2482_MC.Q ),
    .O(NET2482_MC_tsimcreated_xor_)
  );
  X_FF \NET2482_MC.REG  (
    .I(NET2482_MC_tsimcreated_xor_),
    .CE(Vcc),
    .CLK(\NET2482_MC.REG_tsimcreated_inv_Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\NET2482_MC.Q )
  );
  X_INV \NET2482_MC.REG_tsimcreated_inv_Mclk_II/FCLK_452  (
    .I(\Mclk_II/FCLK ),
    .O(\NET2482_MC.REG_tsimcreated_inv_Mclk_II/FCLK )
  );
  X_XOR2 \NET2482_MC.D_453  (
    .I0(\NET2482_MC.D1 ),
    .I1(\NET2482_MC.D2 ),
    .O(\NET2482_MC.D )
  );
  X_ZERO \NET2482_MC.D1_454  (
    .O(\NET2482_MC.D1 )
  );
  X_AND2 \NET2482_MC.D2_PT_0_455  (
    .I0(\NlwInverterSignal_NET2482_MC.D2_PT_0/IN0 ),
    .I1(NET2482),
    .O(\NET2482_MC.D2_PT_0 )
  );
  X_AND4 \NET2482_MC.D2_PT_1_456  (
    .I0(\AD<2>_II/UIM ),
    .I1(DCORIFGw),
    .I2(\NlwInverterSignal_NET2482_MC.D2_PT_1/IN2 ),
    .I3(NET2482),
    .O(\NET2482_MC.D2_PT_1 )
  );
  X_AND8 \NET2482_MC.D2_PT_2_457  (
    .I0(\MSPReset_II/UIM ),
    .I1(\NlwInverterSignal_NET2482_MC.D2_PT_2/IN1 ),
    .I2(\NlwInverterSignal_NET2482_MC.D2_PT_2/IN2 ),
    .I3(\NlwInverterSignal_NET2482_MC.D2_PT_2/IN3 ),
    .I4(\U1/U4/RF0r ),
    .I5(\U1/U4/E0r ),
    .I6(\U1/U4/HE0stater ),
    .I7(\NlwInverterSignal_NET2482_MC.D2_PT_2/IN7 ),
    .O(\NET2482_MC.D2_PT_2 )
  );
  X_AND8 \NET2482_MC.D2_PT_3_458  (
    .I0(\MSPReset_II/UIM ),
    .I1(\NlwInverterSignal_NET2482_MC.D2_PT_3/IN1 ),
    .I2(\NlwInverterSignal_NET2482_MC.D2_PT_3/IN2 ),
    .I3(\NlwInverterSignal_NET2482_MC.D2_PT_3/IN3 ),
    .I4(\NlwInverterSignal_NET2482_MC.D2_PT_3/IN4 ),
    .I5(\U1/U4/E0r ),
    .I6(\NlwInverterSignal_NET2482_MC.D2_PT_3/IN6 ),
    .I7(\U1/U4/HE0statelastr ),
    .O(\NET2482_MC.D2_PT_3 )
  );
  X_OR4 \NET2482_MC.D2_459  (
    .I0(\NET2482_MC.D2_PT_0 ),
    .I1(\NET2482_MC.D2_PT_1 ),
    .I2(\NET2482_MC.D2_PT_2 ),
    .I3(\NET2482_MC.D2_PT_3 ),
    .O(\NET2482_MC.D2 )
  );
  X_BUF \U1/U4/RF0r_460  (
    .I(\U1/U4/RF0r_MC.Q ),
    .O(\U1/U4/RF0r )
  );
  X_FF \U1/U4/RF0r_MC.REG  (
    .I(\U1/U4/RF0r_MC.D ),
    .CE(Vcc),
    .CLK(\U1/U4/RF0r_MC.REG_tsimcreated_inv_Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\U1/U4/RF0r_MC.Q )
  );
  X_INV \U1/U4/RF0r_MC.REG_tsimcreated_inv_Mclk_II/FCLK_461  (
    .I(\Mclk_II/FCLK ),
    .O(\U1/U4/RF0r_MC.REG_tsimcreated_inv_Mclk_II/FCLK )
  );
  X_XOR2 \U1/U4/RF0r_MC.D_462  (
    .I0(\U1/U4/RF0r_MC.D1 ),
    .I1(\U1/U4/RF0r_MC.D2 ),
    .O(\U1/U4/RF0r_MC.D )
  );
  X_ZERO \U1/U4/RF0r_MC.D1_463  (
    .O(\U1/U4/RF0r_MC.D1 )
  );
  X_AND3 \U1/U4/RF0r_MC.D2_PT_0_464  (
    .I0(\MSPReset_II/UIM ),
    .I1(\AD<0>_II/UIM ),
    .I2(DCORENCCTLw),
    .O(\U1/U4/RF0r_MC.D2_PT_0 )
  );
  X_AND3 \U1/U4/RF0r_MC.D2_PT_1_465  (
    .I0(\MSPReset_II/UIM ),
    .I1(\NlwInverterSignal_U1/U4/RF0r_MC.D2_PT_1/IN1 ),
    .I2(\U1/U4/RF0r ),
    .O(\U1/U4/RF0r_MC.D2_PT_1 )
  );
  X_OR2 \U1/U4/RF0r_MC.D2_466  (
    .I0(\U1/U4/RF0r_MC.D2_PT_0 ),
    .I1(\U1/U4/RF0r_MC.D2_PT_1 ),
    .O(\U1/U4/RF0r_MC.D2 )
  );
  X_BUF \U1/U4/E0r_467  (
    .I(\U1/U4/E0r_MC.Q ),
    .O(\U1/U4/E0r )
  );
  X_FF \U1/U4/E0r_MC.REG  (
    .I(\U1/U4/E0r_MC.D ),
    .CE(Vcc),
    .CLK(\U1/U4/E0r_MC.REG_tsimcreated_inv_Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\U1/U4/E0r_MC.Q )
  );
  X_INV \U1/U4/E0r_MC.REG_tsimcreated_inv_Mclk_II/FCLK_468  (
    .I(\Mclk_II/FCLK ),
    .O(\U1/U4/E0r_MC.REG_tsimcreated_inv_Mclk_II/FCLK )
  );
  X_XOR2 \U1/U4/E0r_MC.D_469  (
    .I0(\U1/U4/E0r_MC.D1 ),
    .I1(\U1/U4/E0r_MC.D2 ),
    .O(\U1/U4/E0r_MC.D )
  );
  X_ZERO \U1/U4/E0r_MC.D1_470  (
    .O(\U1/U4/E0r_MC.D1 )
  );
  X_AND3 \U1/U4/E0r_MC.D2_PT_0_471  (
    .I0(\MSPReset_II/UIM ),
    .I1(\AD<1>_II/UIM ),
    .I2(DCORENCCTLw),
    .O(\U1/U4/E0r_MC.D2_PT_0 )
  );
  X_AND3 \U1/U4/E0r_MC.D2_PT_1_472  (
    .I0(\MSPReset_II/UIM ),
    .I1(\NlwInverterSignal_U1/U4/E0r_MC.D2_PT_1/IN1 ),
    .I2(\U1/U4/E0r ),
    .O(\U1/U4/E0r_MC.D2_PT_1 )
  );
  X_OR2 \U1/U4/E0r_MC.D2_473  (
    .I0(\U1/U4/E0r_MC.D2_PT_0 ),
    .I1(\U1/U4/E0r_MC.D2_PT_1 ),
    .O(\U1/U4/E0r_MC.D2 )
  );
  X_BUF \U1/U4/HE0statelastr_474  (
    .I(\U1/U4/HE0statelastr_MC.Q ),
    .O(\U1/U4/HE0statelastr )
  );
  X_FF \U1/U4/HE0statelastr_MC.REG  (
    .I(\U1/U4/HE0statelastr_MC.D ),
    .CE(Vcc),
    .CLK(\U1/U4/HE0statelastr_MC.REG_tsimcreated_inv_Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\U1/U4/HE0statelastr_MC.Q )
  );
  X_INV \U1/U4/HE0statelastr_MC.REG_tsimcreated_inv_Mclk_II/FCLK_475  (
    .I(\Mclk_II/FCLK ),
    .O(\U1/U4/HE0statelastr_MC.REG_tsimcreated_inv_Mclk_II/FCLK )
  );
  X_XOR2 \U1/U4/HE0statelastr_MC.D_476  (
    .I0(\U1/U4/HE0statelastr_MC.D1 ),
    .I1(\U1/U4/HE0statelastr_MC.D2 ),
    .O(\U1/U4/HE0statelastr_MC.D )
  );
  X_AND2 \U1/U4/HE0statelastr_MC.D1_477  (
    .I0(\U1/U4/HE0stater ),
    .I1(\U1/U4/HE0stater ),
    .O(\U1/U4/HE0statelastr_MC.D1 )
  );
  X_ZERO \U1/U4/HE0statelastr_MC.D2_478  (
    .O(\U1/U4/HE0statelastr_MC.D2 )
  );
  X_BUF \U1/U2/location_Maddsub__n0000__n0067<0>  (
    .I(\U1/U2/location_Maddsub__n0000__n0067<0>_MC.Q ),
    .O(\U1/U2/location_Maddsub__n0000__n0067 [0])
  );
  X_BUF \U1/U2/location_Maddsub__n0000__n0067<0>_MC.Q_479  (
    .I(\U1/U2/location_Maddsub__n0000__n0067<0>_MC.D ),
    .O(\U1/U2/location_Maddsub__n0000__n0067<0>_MC.Q )
  );
  X_XOR2 \U1/U2/location_Maddsub__n0000__n0067<0>_MC.D_480  (
    .I0(\U1/U2/location_Maddsub__n0000__n0067<0>_MC.D1 ),
    .I1(\U1/U2/location_Maddsub__n0000__n0067<0>_MC.D2 ),
    .O(\U1/U2/location_Maddsub__n0000__n0067<0>_MC.D )
  );
  X_AND2 \U1/U2/location_Maddsub__n0000__n0067<0>_MC.D1_481  (
    .I0(N_PZ_943),
    .I1(N_PZ_943),
    .O(\U1/U2/location_Maddsub__n0000__n0067<0>_MC.D1 )
  );
  X_AND6 \U1/U2/location_Maddsub__n0000__n0067<0>_MC.D2_PT_0_482  (
    .I0(N_PZ_943),
    .I1(\U1/Channel0 [0]),
    .I2(\U1/Channel0 [1]),
    .I3(\U1/Channel0 [2]),
    .I4(\U1/Channel0 [3]),
    .I5(\U1/Channel0 [4]),
    .O(\U1/U2/location_Maddsub__n0000__n0067<0>_MC.D2_PT_0 )
  );
  X_AND6 \U1/U2/location_Maddsub__n0000__n0067<0>_MC.D2_PT_1_483  (
    .I0(\NlwInverterSignal_U1/U2/location_Maddsub__n0000__n0067<0>_MC.D2_PT_1/IN0 ),
    .I1(\NlwInverterSignal_U1/U2/location_Maddsub__n0000__n0067<0>_MC.D2_PT_1/IN1 ),
    .I2(\NlwInverterSignal_U1/U2/location_Maddsub__n0000__n0067<0>_MC.D2_PT_1/IN2 ),
    .I3(\NlwInverterSignal_U1/U2/location_Maddsub__n0000__n0067<0>_MC.D2_PT_1/IN3 ),
    .I4(\NlwInverterSignal_U1/U2/location_Maddsub__n0000__n0067<0>_MC.D2_PT_1/IN4 ),
    .I5(\NlwInverterSignal_U1/U2/location_Maddsub__n0000__n0067<0>_MC.D2_PT_1/IN5 ),
    .O(\U1/U2/location_Maddsub__n0000__n0067<0>_MC.D2_PT_1 )
  );
  X_OR2 \U1/U2/location_Maddsub__n0000__n0067<0>_MC.D2_484  (
    .I0(\U1/U2/location_Maddsub__n0000__n0067<0>_MC.D2_PT_0 ),
    .I1(\U1/U2/location_Maddsub__n0000__n0067<0>_MC.D2_PT_1 ),
    .O(\U1/U2/location_Maddsub__n0000__n0067<0>_MC.D2 )
  );
  X_BUF N_PZ_943_485 (
    .I(\N_PZ_943_MC.Q ),
    .O(N_PZ_943)
  );
  X_BUF \N_PZ_943_MC.Q_486  (
    .I(\N_PZ_943_MC.D ),
    .O(\N_PZ_943_MC.Q )
  );
  X_XOR2 \N_PZ_943_MC.D_487  (
    .I0(\N_PZ_943_MC.D1 ),
    .I1(\N_PZ_943_MC.D2 ),
    .O(\N_PZ_943_MC.D )
  );
  X_AND2 \N_PZ_943_MC.D1_488  (
    .I0(\U1/NET3721 ),
    .I1(\U1/NET3721 ),
    .O(\N_PZ_943_MC.D1 )
  );
  X_AND3 \N_PZ_943_MC.D2_PT_0_489  (
    .I0(\NlwInverterSignal_N_PZ_943_MC.D2_PT_0/IN0 ),
    .I1(\U1/U1/CurrState_Sreg0_FFD3 ),
    .I2(\NlwInverterSignal_N_PZ_943_MC.D2_PT_0/IN2 ),
    .O(\N_PZ_943_MC.D2_PT_0 )
  );
  X_AND3 \N_PZ_943_MC.D2_PT_1_490  (
    .I0(\NlwInverterSignal_N_PZ_943_MC.D2_PT_1/IN0 ),
    .I1(\U1/U1/CurrState_Sreg0_FFD2 ),
    .I2(\NlwInverterSignal_N_PZ_943_MC.D2_PT_1/IN2 ),
    .O(\N_PZ_943_MC.D2_PT_1 )
  );
  X_OR2 \N_PZ_943_MC.D2_491  (
    .I0(\N_PZ_943_MC.D2_PT_0 ),
    .I1(\N_PZ_943_MC.D2_PT_1 ),
    .O(\N_PZ_943_MC.D2 )
  );
  X_BUF \U1/NET3721_492  (
    .I(\U1/NET3721_MC.Q ),
    .O(\U1/NET3721 )
  );
  X_FF \U1/NET3721_MC.REG  (
    .I(\U1/NET3721_MC.D ),
    .CE(Vcc),
    .CLK(\U1/NET3721_MC.REG_tsimcreated_inv_Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\U1/NET3721_MC.Q )
  );
  X_INV \U1/NET3721_MC.REG_tsimcreated_inv_Mclk_II/FCLK_493  (
    .I(\Mclk_II/FCLK ),
    .O(\U1/NET3721_MC.REG_tsimcreated_inv_Mclk_II/FCLK )
  );
  X_XOR2 \U1/NET3721_MC.D_494  (
    .I0(\U1/NET3721_MC.D1 ),
    .I1(\U1/NET3721_MC.D2 ),
    .O(\U1/NET3721_MC.D )
  );
  X_ZERO \U1/NET3721_MC.D1_495  (
    .O(\U1/NET3721_MC.D1 )
  );
  X_AND3 \U1/NET3721_MC.D2_PT_0_496  (
    .I0(\MSPReset_II/UIM ),
    .I1(\AD<3>_II/UIM ),
    .I2(DCORENCCTLw),
    .O(\U1/NET3721_MC.D2_PT_0 )
  );
  X_AND3 \U1/NET3721_MC.D2_PT_1_497  (
    .I0(\MSPReset_II/UIM ),
    .I1(\NlwInverterSignal_U1/NET3721_MC.D2_PT_1/IN1 ),
    .I2(\U1/NET3721 ),
    .O(\U1/NET3721_MC.D2_PT_1 )
  );
  X_OR2 \U1/NET3721_MC.D2_498  (
    .I0(\U1/NET3721_MC.D2_PT_0 ),
    .I1(\U1/NET3721_MC.D2_PT_1 ),
    .O(\U1/NET3721_MC.D2 )
  );
  X_BUF \U1/U1/CurrState_Sreg0_FFD1_499  (
    .I(\U1/U1/CurrState_Sreg0_FFD1_MC.Q ),
    .O(\U1/U1/CurrState_Sreg0_FFD1 )
  );
  X_FF \U1/U1/CurrState_Sreg0_FFD1_MC.REG  (
    .I(\U1/U1/CurrState_Sreg0_FFD1_MC.D ),
    .CE(Vcc),
    .CLK(\Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\U1/U1/CurrState_Sreg0_FFD1_MC.Q )
  );
  X_XOR2 \U1/U1/CurrState_Sreg0_FFD1_MC.D_500  (
    .I0(\U1/U1/CurrState_Sreg0_FFD1_MC.D1 ),
    .I1(\U1/U1/CurrState_Sreg0_FFD1_MC.D2 ),
    .O(\U1/U1/CurrState_Sreg0_FFD1_MC.D )
  );
  X_ZERO \U1/U1/CurrState_Sreg0_FFD1_MC.D1_501  (
    .O(\U1/U1/CurrState_Sreg0_FFD1_MC.D1 )
  );
  X_AND4 \U1/U1/CurrState_Sreg0_FFD1_MC.D2_PT_0_502  (
    .I0(\MSPReset_II/UIM ),
    .I1(\U1/U1/CurrState_Sreg0_FFD1 ),
    .I2(\U1/U1/CurrState_Sreg0_FFD2 ),
    .I3(\NlwInverterSignal_U1/U1/CurrState_Sreg0_FFD1_MC.D2_PT_0/IN3 ),
    .O(\U1/U1/CurrState_Sreg0_FFD1_MC.D2_PT_0 )
  );
  X_AND5 \U1/U1/CurrState_Sreg0_FFD1_MC.D2_PT_1_503  (
    .I0(\MSPReset_II/UIM ),
    .I1(\U1/U1/CurrState_Sreg0_FFD1 ),
    .I2(\NlwInverterSignal_U1/U1/CurrState_Sreg0_FFD1_MC.D2_PT_1/IN2 ),
    .I3(\NlwInverterSignal_U1/U1/CurrState_Sreg0_FFD1_MC.D2_PT_1/IN3 ),
    .I4(\PhaseA_Encoder0_II/UIM ),
    .O(\U1/U1/CurrState_Sreg0_FFD1_MC.D2_PT_1 )
  );
  X_AND6 \U1/U1/CurrState_Sreg0_FFD1_MC.D2_PT_2_504  (
    .I0(\MSPReset_II/UIM ),
    .I1(\NlwInverterSignal_U1/U1/CurrState_Sreg0_FFD1_MC.D2_PT_2/IN1 ),
    .I2(\NlwInverterSignal_U1/U1/CurrState_Sreg0_FFD1_MC.D2_PT_2/IN2 ),
    .I3(\NlwInverterSignal_U1/U1/CurrState_Sreg0_FFD1_MC.D2_PT_2/IN3 ),
    .I4(\NlwInverterSignal_U1/U1/CurrState_Sreg0_FFD1_MC.D2_PT_2/IN4 ),
    .I5(\PhaseB_Encoder0_II/UIM ),
    .O(\U1/U1/CurrState_Sreg0_FFD1_MC.D2_PT_2 )
  );
  X_OR3 \U1/U1/CurrState_Sreg0_FFD1_MC.D2_505  (
    .I0(\U1/U1/CurrState_Sreg0_FFD1_MC.D2_PT_0 ),
    .I1(\U1/U1/CurrState_Sreg0_FFD1_MC.D2_PT_1 ),
    .I2(\U1/U1/CurrState_Sreg0_FFD1_MC.D2_PT_2 ),
    .O(\U1/U1/CurrState_Sreg0_FFD1_MC.D2 )
  );
  X_BUF \U1/U1/CurrState_Sreg0_FFD3_506  (
    .I(\U1/U1/CurrState_Sreg0_FFD3_MC.Q ),
    .O(\U1/U1/CurrState_Sreg0_FFD3 )
  );
  X_FF \U1/U1/CurrState_Sreg0_FFD3_MC.REG  (
    .I(\U1/U1/CurrState_Sreg0_FFD3_MC.D ),
    .CE(Vcc),
    .CLK(\Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\U1/U1/CurrState_Sreg0_FFD3_MC.Q )
  );
  X_XOR2 \U1/U1/CurrState_Sreg0_FFD3_MC.D_507  (
    .I0(\U1/U1/CurrState_Sreg0_FFD3_MC.D1 ),
    .I1(\U1/U1/CurrState_Sreg0_FFD3_MC.D2 ),
    .O(\U1/U1/CurrState_Sreg0_FFD3_MC.D )
  );
  X_ZERO \U1/U1/CurrState_Sreg0_FFD3_MC.D1_508  (
    .O(\U1/U1/CurrState_Sreg0_FFD3_MC.D1 )
  );
  X_AND5 \U1/U1/CurrState_Sreg0_FFD3_MC.D2_PT_0_509  (
    .I0(\MSPReset_II/UIM ),
    .I1(\NlwInverterSignal_U1/U1/CurrState_Sreg0_FFD3_MC.D2_PT_0/IN1 ),
    .I2(\U1/U1/CurrState_Sreg0_FFD3 ),
    .I3(\NlwInverterSignal_U1/U1/CurrState_Sreg0_FFD3_MC.D2_PT_0/IN3 ),
    .I4(\NlwInverterSignal_U1/U1/CurrState_Sreg0_FFD3_MC.D2_PT_0/IN4 ),
    .O(\U1/U1/CurrState_Sreg0_FFD3_MC.D2_PT_0 )
  );
  X_AND5 \U1/U1/CurrState_Sreg0_FFD3_MC.D2_PT_1_510  (
    .I0(\MSPReset_II/UIM ),
    .I1(\U1/U1/CurrState_Sreg0_FFD3 ),
    .I2(\U1/U1/CurrState_Sreg0_FFD2 ),
    .I3(\NlwInverterSignal_U1/U1/CurrState_Sreg0_FFD3_MC.D2_PT_1/IN3 ),
    .I4(\NlwInverterSignal_U1/U1/CurrState_Sreg0_FFD3_MC.D2_PT_1/IN4 ),
    .O(\U1/U1/CurrState_Sreg0_FFD3_MC.D2_PT_1 )
  );
  X_AND6 \U1/U1/CurrState_Sreg0_FFD3_MC.D2_PT_2_511  (
    .I0(\MSPReset_II/UIM ),
    .I1(\U1/U1/CurrState_Sreg0_FFD1 ),
    .I2(\U1/U1/CurrState_Sreg0_FFD2 ),
    .I3(\NlwInverterSignal_U1/U1/CurrState_Sreg0_FFD3_MC.D2_PT_2/IN3 ),
    .I4(\PhaseA_Encoder0_II/UIM ),
    .I5(\NlwInverterSignal_U1/U1/CurrState_Sreg0_FFD3_MC.D2_PT_2/IN5 ),
    .O(\U1/U1/CurrState_Sreg0_FFD3_MC.D2_PT_2 )
  );
  X_AND6 \U1/U1/CurrState_Sreg0_FFD3_MC.D2_PT_3_512  (
    .I0(\MSPReset_II/UIM ),
    .I1(\NlwInverterSignal_U1/U1/CurrState_Sreg0_FFD3_MC.D2_PT_3/IN1 ),
    .I2(\U1/U1/CurrState_Sreg0_FFD2 ),
    .I3(\NlwInverterSignal_U1/U1/CurrState_Sreg0_FFD3_MC.D2_PT_3/IN3 ),
    .I4(\PhaseA_Encoder0_II/UIM ),
    .I5(\PhaseB_Encoder0_II/UIM ),
    .O(\U1/U1/CurrState_Sreg0_FFD3_MC.D2_PT_3 )
  );
  X_OR4 \U1/U1/CurrState_Sreg0_FFD3_MC.D2_513  (
    .I0(\U1/U1/CurrState_Sreg0_FFD3_MC.D2_PT_0 ),
    .I1(\U1/U1/CurrState_Sreg0_FFD3_MC.D2_PT_1 ),
    .I2(\U1/U1/CurrState_Sreg0_FFD3_MC.D2_PT_2 ),
    .I3(\U1/U1/CurrState_Sreg0_FFD3_MC.D2_PT_3 ),
    .O(\U1/U1/CurrState_Sreg0_FFD3_MC.D2 )
  );
  X_BUF \U1/U1/CurrState_Sreg0_FFD2_514  (
    .I(\U1/U1/CurrState_Sreg0_FFD2_MC.Q ),
    .O(\U1/U1/CurrState_Sreg0_FFD2 )
  );
  X_FF \U1/U1/CurrState_Sreg0_FFD2_MC.REG  (
    .I(\U1/U1/CurrState_Sreg0_FFD2_MC.D ),
    .CE(Vcc),
    .CLK(\Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\U1/U1/CurrState_Sreg0_FFD2_MC.Q )
  );
  X_XOR2 \U1/U1/CurrState_Sreg0_FFD2_MC.D_515  (
    .I0(\U1/U1/CurrState_Sreg0_FFD2_MC.D1 ),
    .I1(\U1/U1/CurrState_Sreg0_FFD2_MC.D2 ),
    .O(\U1/U1/CurrState_Sreg0_FFD2_MC.D )
  );
  X_ZERO \U1/U1/CurrState_Sreg0_FFD2_MC.D1_516  (
    .O(\U1/U1/CurrState_Sreg0_FFD2_MC.D1 )
  );
  X_AND6 \U1/U1/CurrState_Sreg0_FFD2_MC.D2_PT_0_517  (
    .I0(\MSPReset_II/UIM ),
    .I1(\U1/U1/CurrState_Sreg0_FFD1 ),
    .I2(\U1/U1/CurrState_Sreg0_FFD3 ),
    .I3(\U1/U1/CurrState_Sreg0_FFD2 ),
    .I4(\NlwInverterSignal_U1/U1/CurrState_Sreg0_FFD2_MC.D2_PT_0/IN4 ),
    .I5(\PhaseB_Encoder0_II/UIM ),
    .O(\U1/U1/CurrState_Sreg0_FFD2_MC.D2_PT_0 )
  );
  X_AND6 \U1/U1/CurrState_Sreg0_FFD2_MC.D2_PT_1_518  (
    .I0(\MSPReset_II/UIM ),
    .I1(\U1/U1/CurrState_Sreg0_FFD1 ),
    .I2(\NlwInverterSignal_U1/U1/CurrState_Sreg0_FFD2_MC.D2_PT_1/IN2 ),
    .I3(\U1/U1/CurrState_Sreg0_FFD2 ),
    .I4(\NlwInverterSignal_U1/U1/CurrState_Sreg0_FFD2_MC.D2_PT_1/IN4 ),
    .I5(\NlwInverterSignal_U1/U1/CurrState_Sreg0_FFD2_MC.D2_PT_1/IN5 ),
    .O(\U1/U1/CurrState_Sreg0_FFD2_MC.D2_PT_1 )
  );
  X_AND6 \U1/U1/CurrState_Sreg0_FFD2_MC.D2_PT_2_519  (
    .I0(\MSPReset_II/UIM ),
    .I1(\U1/U1/CurrState_Sreg0_FFD1 ),
    .I2(\NlwInverterSignal_U1/U1/CurrState_Sreg0_FFD2_MC.D2_PT_2/IN2 ),
    .I3(\NlwInverterSignal_U1/U1/CurrState_Sreg0_FFD2_MC.D2_PT_2/IN3 ),
    .I4(\PhaseA_Encoder0_II/UIM ),
    .I5(\PhaseB_Encoder0_II/UIM ),
    .O(\U1/U1/CurrState_Sreg0_FFD2_MC.D2_PT_2 )
  );
  X_AND6 \U1/U1/CurrState_Sreg0_FFD2_MC.D2_PT_3_520  (
    .I0(\MSPReset_II/UIM ),
    .I1(\U1/U1/CurrState_Sreg0_FFD1 ),
    .I2(\U1/U1/CurrState_Sreg0_FFD2 ),
    .I3(\NlwInverterSignal_U1/U1/CurrState_Sreg0_FFD2_MC.D2_PT_3/IN3 ),
    .I4(\PhaseA_Encoder0_II/UIM ),
    .I5(\NlwInverterSignal_U1/U1/CurrState_Sreg0_FFD2_MC.D2_PT_3/IN5 ),
    .O(\U1/U1/CurrState_Sreg0_FFD2_MC.D2_PT_3 )
  );
  X_AND6 \U1/U1/CurrState_Sreg0_FFD2_MC.D2_PT_4_521  (
    .I0(\MSPReset_II/UIM ),
    .I1(\NlwInverterSignal_U1/U1/CurrState_Sreg0_FFD2_MC.D2_PT_4/IN1 ),
    .I2(\U1/U1/CurrState_Sreg0_FFD3 ),
    .I3(\U1/U1/CurrState_Sreg0_FFD2 ),
    .I4(\NlwInverterSignal_U1/U1/CurrState_Sreg0_FFD2_MC.D2_PT_4/IN4 ),
    .I5(\NlwInverterSignal_U1/U1/CurrState_Sreg0_FFD2_MC.D2_PT_4/IN5 ),
    .O(\U1/U1/CurrState_Sreg0_FFD2_MC.D2_PT_4 )
  );
  X_AND6 \U1/U1/CurrState_Sreg0_FFD2_MC.D2_PT_5_522  (
    .I0(\MSPReset_II/UIM ),
    .I1(\NlwInverterSignal_U1/U1/CurrState_Sreg0_FFD2_MC.D2_PT_5/IN1 ),
    .I2(\U1/U1/CurrState_Sreg0_FFD3 ),
    .I3(\NlwInverterSignal_U1/U1/CurrState_Sreg0_FFD2_MC.D2_PT_5/IN3 ),
    .I4(\PhaseA_Encoder0_II/UIM ),
    .I5(\PhaseB_Encoder0_II/UIM ),
    .O(\U1/U1/CurrState_Sreg0_FFD2_MC.D2_PT_5 )
  );
  X_AND6 \U1/U1/CurrState_Sreg0_FFD2_MC.D2_PT_6_523  (
    .I0(\MSPReset_II/UIM ),
    .I1(\NlwInverterSignal_U1/U1/CurrState_Sreg0_FFD2_MC.D2_PT_6/IN1 ),
    .I2(\NlwInverterSignal_U1/U1/CurrState_Sreg0_FFD2_MC.D2_PT_6/IN2 ),
    .I3(\U1/U1/CurrState_Sreg0_FFD2 ),
    .I4(\NlwInverterSignal_U1/U1/CurrState_Sreg0_FFD2_MC.D2_PT_6/IN4 ),
    .I5(\PhaseB_Encoder0_II/UIM ),
    .O(\U1/U1/CurrState_Sreg0_FFD2_MC.D2_PT_6 )
  );
  X_AND6 \U1/U1/CurrState_Sreg0_FFD2_MC.D2_PT_7_524  (
    .I0(\MSPReset_II/UIM ),
    .I1(\NlwInverterSignal_U1/U1/CurrState_Sreg0_FFD2_MC.D2_PT_7/IN1 ),
    .I2(\NlwInverterSignal_U1/U1/CurrState_Sreg0_FFD2_MC.D2_PT_7/IN2 ),
    .I3(\NlwInverterSignal_U1/U1/CurrState_Sreg0_FFD2_MC.D2_PT_7/IN3 ),
    .I4(\PhaseA_Encoder0_II/UIM ),
    .I5(\NlwInverterSignal_U1/U1/CurrState_Sreg0_FFD2_MC.D2_PT_7/IN5 ),
    .O(\U1/U1/CurrState_Sreg0_FFD2_MC.D2_PT_7 )
  );
  X_OR8 \U1/U1/CurrState_Sreg0_FFD2_MC.D2_525  (
    .I0(\U1/U1/CurrState_Sreg0_FFD2_MC.D2_PT_0 ),
    .I1(\U1/U1/CurrState_Sreg0_FFD2_MC.D2_PT_1 ),
    .I2(\U1/U1/CurrState_Sreg0_FFD2_MC.D2_PT_2 ),
    .I3(\U1/U1/CurrState_Sreg0_FFD2_MC.D2_PT_3 ),
    .I4(\U1/U1/CurrState_Sreg0_FFD2_MC.D2_PT_4 ),
    .I5(\U1/U1/CurrState_Sreg0_FFD2_MC.D2_PT_5 ),
    .I6(\U1/U1/CurrState_Sreg0_FFD2_MC.D2_PT_6 ),
    .I7(\U1/U1/CurrState_Sreg0_FFD2_MC.D2_PT_7 ),
    .O(\U1/U1/CurrState_Sreg0_FFD2_MC.D2 )
  );
  X_BUF \U1/U1/CurrState_Sreg0_FFD4_526  (
    .I(\U1/U1/CurrState_Sreg0_FFD4_MC.Q ),
    .O(\U1/U1/CurrState_Sreg0_FFD4 )
  );
  X_FF \U1/U1/CurrState_Sreg0_FFD4_MC.REG  (
    .I(\U1/U1/CurrState_Sreg0_FFD4_MC.D ),
    .CE(Vcc),
    .CLK(\Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\U1/U1/CurrState_Sreg0_FFD4_MC.Q )
  );
  X_XOR2 \U1/U1/CurrState_Sreg0_FFD4_MC.D_527  (
    .I0(\U1/U1/CurrState_Sreg0_FFD4_MC.D1 ),
    .I1(\U1/U1/CurrState_Sreg0_FFD4_MC.D2 ),
    .O(\U1/U1/CurrState_Sreg0_FFD4_MC.D )
  );
  X_AND7 \U1/U1/CurrState_Sreg0_FFD4_MC.D1_528  (
    .I0(\MSPReset_II/UIM ),
    .I1(\NlwInverterSignal_U1/U1/CurrState_Sreg0_FFD4_MC.D1/IN1 ),
    .I2(\U1/U1/CurrState_Sreg0_FFD3 ),
    .I3(\NlwInverterSignal_U1/U1/CurrState_Sreg0_FFD4_MC.D1/IN3 ),
    .I4(\NlwInverterSignal_U1/U1/CurrState_Sreg0_FFD4_MC.D1/IN4 ),
    .I5(\NlwInverterSignal_U1/U1/CurrState_Sreg0_FFD4_MC.D1/IN5 ),
    .I6(\NlwInverterSignal_U1/U1/CurrState_Sreg0_FFD4_MC.D1/IN6 ),
    .O(\U1/U1/CurrState_Sreg0_FFD4_MC.D1 )
  );
  X_ZERO \U1/U1/CurrState_Sreg0_FFD4_MC.D2_529  (
    .O(\U1/U1/CurrState_Sreg0_FFD4_MC.D2 )
  );
  X_BUF \U1/Channel0<0>  (
    .I(\U1/Channel0<0>_MC.Q ),
    .O(\U1/Channel0 [0])
  );
  X_XOR2 \U1/Channel0<0>_MC_tsimcreated_xor__530  (
    .I0(\U1/Channel0<0>_MC.D ),
    .I1(\U1/Channel0<0>_MC.Q ),
    .O(\U1/Channel0<0>_MC_tsimcreated_xor_ )
  );
  X_FF \U1/Channel0<0>_MC.REG  (
    .I(\U1/Channel0<0>_MC_tsimcreated_xor_ ),
    .CE(Vcc),
    .CLK(\Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\U1/Channel0<0>_MC.Q )
  );
  X_XOR2 \U1/Channel0<0>_MC.D_531  (
    .I0(\U1/Channel0<0>_MC.D1 ),
    .I1(\U1/Channel0<0>_MC.D2 ),
    .O(\U1/Channel0<0>_MC.D )
  );
  X_ZERO \U1/Channel0<0>_MC.D1_532  (
    .O(\U1/Channel0<0>_MC.D1 )
  );
  X_AND2 \U1/Channel0<0>_MC.D2_PT_0_533  (
    .I0(\NlwInverterSignal_U1/Channel0<0>_MC.D2_PT_0/IN0 ),
    .I1(\U1/Channel0 [0]),
    .O(\U1/Channel0<0>_MC.D2_PT_0 )
  );
  X_AND6 \U1/Channel0<0>_MC.D2_PT_1_534  (
    .I0(\MSPReset_II/UIM ),
    .I1(\NlwInverterSignal_U1/Channel0<0>_MC.D2_PT_1/IN1 ),
    .I2(\U1/U1/CurrState_Sreg0_FFD1 ),
    .I3(\U1/U1/CurrState_Sreg0_FFD3 ),
    .I4(\NlwInverterSignal_U1/Channel0<0>_MC.D2_PT_1/IN4 ),
    .I5(\NlwInverterSignal_U1/Channel0<0>_MC.D2_PT_1/IN5 ),
    .O(\U1/Channel0<0>_MC.D2_PT_1 )
  );
  X_AND6 \U1/Channel0<0>_MC.D2_PT_2_535  (
    .I0(\MSPReset_II/UIM ),
    .I1(\NlwInverterSignal_U1/Channel0<0>_MC.D2_PT_2/IN1 ),
    .I2(\NlwInverterSignal_U1/Channel0<0>_MC.D2_PT_2/IN2 ),
    .I3(\U1/U1/CurrState_Sreg0_FFD3 ),
    .I4(\NlwInverterSignal_U1/Channel0<0>_MC.D2_PT_2/IN4 ),
    .I5(\U1/U1/CurrState_Sreg0_FFD4 ),
    .O(\U1/Channel0<0>_MC.D2_PT_2 )
  );
  X_OR3 \U1/Channel0<0>_MC.D2_536  (
    .I0(\U1/Channel0<0>_MC.D2_PT_0 ),
    .I1(\U1/Channel0<0>_MC.D2_PT_1 ),
    .I2(\U1/Channel0<0>_MC.D2_PT_2 ),
    .O(\U1/Channel0<0>_MC.D2 )
  );
  X_BUF \U1/Channel0<1>  (
    .I(\U1/Channel0<1>_MC.Q ),
    .O(\U1/Channel0 [1])
  );
  X_XOR2 \U1/Channel0<1>_MC_tsimcreated_xor__537  (
    .I0(\U1/Channel0<1>_MC.D ),
    .I1(\U1/Channel0<1>_MC.Q ),
    .O(\U1/Channel0<1>_MC_tsimcreated_xor_ )
  );
  X_FF \U1/Channel0<1>_MC.REG  (
    .I(\U1/Channel0<1>_MC_tsimcreated_xor_ ),
    .CE(Vcc),
    .CLK(\Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\U1/Channel0<1>_MC.Q )
  );
  X_XOR2 \U1/Channel0<1>_MC.D_538  (
    .I0(\U1/Channel0<1>_MC.D1 ),
    .I1(\U1/Channel0<1>_MC.D2 ),
    .O(\U1/Channel0<1>_MC.D )
  );
  X_ZERO \U1/Channel0<1>_MC.D1_539  (
    .O(\U1/Channel0<1>_MC.D1 )
  );
  X_AND2 \U1/Channel0<1>_MC.D2_PT_0_540  (
    .I0(\NlwInverterSignal_U1/Channel0<1>_MC.D2_PT_0/IN0 ),
    .I1(\U1/Channel0 [1]),
    .O(\U1/Channel0<1>_MC.D2_PT_0 )
  );
  X_AND2 \U1/Channel0<1>_MC.D2_PT_1_541  (
    .I0(N_PZ_964),
    .I1(\NlwInverterSignal_U1/Channel0<1>_MC.D2_PT_1/IN1 ),
    .O(\U1/Channel0<1>_MC.D2_PT_1 )
  );
  X_AND2 \U1/Channel0<1>_MC.D2_PT_2_542  (
    .I0(N_PZ_968),
    .I1(\U1/Channel0 [0]),
    .O(\U1/Channel0<1>_MC.D2_PT_2 )
  );
  X_OR3 \U1/Channel0<1>_MC.D2_543  (
    .I0(\U1/Channel0<1>_MC.D2_PT_0 ),
    .I1(\U1/Channel0<1>_MC.D2_PT_1 ),
    .I2(\U1/Channel0<1>_MC.D2_PT_2 ),
    .O(\U1/Channel0<1>_MC.D2 )
  );
  X_BUF N_PZ_964_544 (
    .I(\N_PZ_964_MC.Q ),
    .O(N_PZ_964)
  );
  X_BUF \N_PZ_964_MC.Q_545  (
    .I(\N_PZ_964_MC.D ),
    .O(\N_PZ_964_MC.Q )
  );
  X_XOR2 \N_PZ_964_MC.D_546  (
    .I0(\N_PZ_964_MC.D1 ),
    .I1(\N_PZ_964_MC.D2 ),
    .O(\N_PZ_964_MC.D )
  );
  X_ZERO \N_PZ_964_MC.D1_547  (
    .O(\N_PZ_964_MC.D1 )
  );
  X_AND7 \N_PZ_964_MC.D2_PT_0_548  (
    .I0(\MSPReset_II/UIM ),
    .I1(\NlwInverterSignal_N_PZ_964_MC.D2_PT_0/IN1 ),
    .I2(\U1/NET3721 ),
    .I3(\NlwInverterSignal_N_PZ_964_MC.D2_PT_0/IN3 ),
    .I4(\U1/U1/CurrState_Sreg0_FFD3 ),
    .I5(\NlwInverterSignal_N_PZ_964_MC.D2_PT_0/IN5 ),
    .I6(\U1/U1/CurrState_Sreg0_FFD4 ),
    .O(\N_PZ_964_MC.D2_PT_0 )
  );
  X_AND7 \N_PZ_964_MC.D2_PT_1_549  (
    .I0(\MSPReset_II/UIM ),
    .I1(\NlwInverterSignal_N_PZ_964_MC.D2_PT_1/IN1 ),
    .I2(\NlwInverterSignal_N_PZ_964_MC.D2_PT_1/IN2 ),
    .I3(\U1/U1/CurrState_Sreg0_FFD1 ),
    .I4(\U1/U1/CurrState_Sreg0_FFD3 ),
    .I5(\NlwInverterSignal_N_PZ_964_MC.D2_PT_1/IN5 ),
    .I6(\NlwInverterSignal_N_PZ_964_MC.D2_PT_1/IN6 ),
    .O(\N_PZ_964_MC.D2_PT_1 )
  );
  X_OR2 \N_PZ_964_MC.D2_550  (
    .I0(\N_PZ_964_MC.D2_PT_0 ),
    .I1(\N_PZ_964_MC.D2_PT_1 ),
    .O(\N_PZ_964_MC.D2 )
  );
  X_BUF N_PZ_968_551 (
    .I(\N_PZ_968_MC.Q ),
    .O(N_PZ_968)
  );
  X_BUF \N_PZ_968_MC.Q_552  (
    .I(\N_PZ_968_MC.D ),
    .O(\N_PZ_968_MC.Q )
  );
  X_XOR2 \N_PZ_968_MC.D_553  (
    .I0(\N_PZ_968_MC.D1 ),
    .I1(\N_PZ_968_MC.D2 ),
    .O(\N_PZ_968_MC.D )
  );
  X_ZERO \N_PZ_968_MC.D1_554  (
    .O(\N_PZ_968_MC.D1 )
  );
  X_AND7 \N_PZ_968_MC.D2_PT_0_555  (
    .I0(\MSPReset_II/UIM ),
    .I1(\NlwInverterSignal_N_PZ_968_MC.D2_PT_0/IN1 ),
    .I2(\U1/NET3721 ),
    .I3(\U1/U1/CurrState_Sreg0_FFD1 ),
    .I4(\U1/U1/CurrState_Sreg0_FFD3 ),
    .I5(\NlwInverterSignal_N_PZ_968_MC.D2_PT_0/IN5 ),
    .I6(\NlwInverterSignal_N_PZ_968_MC.D2_PT_0/IN6 ),
    .O(\N_PZ_968_MC.D2_PT_0 )
  );
  X_AND7 \N_PZ_968_MC.D2_PT_1_556  (
    .I0(\MSPReset_II/UIM ),
    .I1(\NlwInverterSignal_N_PZ_968_MC.D2_PT_1/IN1 ),
    .I2(\NlwInverterSignal_N_PZ_968_MC.D2_PT_1/IN2 ),
    .I3(\NlwInverterSignal_N_PZ_968_MC.D2_PT_1/IN3 ),
    .I4(\U1/U1/CurrState_Sreg0_FFD3 ),
    .I5(\NlwInverterSignal_N_PZ_968_MC.D2_PT_1/IN5 ),
    .I6(\U1/U1/CurrState_Sreg0_FFD4 ),
    .O(\N_PZ_968_MC.D2_PT_1 )
  );
  X_OR2 \N_PZ_968_MC.D2_557  (
    .I0(\N_PZ_968_MC.D2_PT_0 ),
    .I1(\N_PZ_968_MC.D2_PT_1 ),
    .O(\N_PZ_968_MC.D2 )
  );
  X_BUF \U1/Channel0<2>  (
    .I(\U1/Channel0<2>_MC.Q ),
    .O(\U1/Channel0 [2])
  );
  X_XOR2 \U1/Channel0<2>_MC_tsimcreated_xor__558  (
    .I0(\U1/Channel0<2>_MC.D ),
    .I1(\U1/Channel0<2>_MC.Q ),
    .O(\U1/Channel0<2>_MC_tsimcreated_xor_ )
  );
  X_FF \U1/Channel0<2>_MC.REG  (
    .I(\U1/Channel0<2>_MC_tsimcreated_xor_ ),
    .CE(Vcc),
    .CLK(\Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\U1/Channel0<2>_MC.Q )
  );
  X_XOR2 \U1/Channel0<2>_MC.D_559  (
    .I0(\U1/Channel0<2>_MC.D1 ),
    .I1(\U1/Channel0<2>_MC.D2 ),
    .O(\U1/Channel0<2>_MC.D )
  );
  X_ZERO \U1/Channel0<2>_MC.D1_560  (
    .O(\U1/Channel0<2>_MC.D1 )
  );
  X_AND2 \U1/Channel0<2>_MC.D2_PT_0_561  (
    .I0(\NlwInverterSignal_U1/Channel0<2>_MC.D2_PT_0/IN0 ),
    .I1(\U1/Channel0 [2]),
    .O(\U1/Channel0<2>_MC.D2_PT_0 )
  );
  X_AND3 \U1/Channel0<2>_MC.D2_PT_1_562  (
    .I0(N_PZ_964),
    .I1(\NlwInverterSignal_U1/Channel0<2>_MC.D2_PT_1/IN1 ),
    .I2(\NlwInverterSignal_U1/Channel0<2>_MC.D2_PT_1/IN2 ),
    .O(\U1/Channel0<2>_MC.D2_PT_1 )
  );
  X_AND3 \U1/Channel0<2>_MC.D2_PT_2_563  (
    .I0(N_PZ_968),
    .I1(\U1/Channel0 [0]),
    .I2(\U1/Channel0 [1]),
    .O(\U1/Channel0<2>_MC.D2_PT_2 )
  );
  X_OR3 \U1/Channel0<2>_MC.D2_564  (
    .I0(\U1/Channel0<2>_MC.D2_PT_0 ),
    .I1(\U1/Channel0<2>_MC.D2_PT_1 ),
    .I2(\U1/Channel0<2>_MC.D2_PT_2 ),
    .O(\U1/Channel0<2>_MC.D2 )
  );
  X_BUF \U1/Channel0<3>  (
    .I(\U1/Channel0<3>_MC.Q ),
    .O(\U1/Channel0 [3])
  );
  X_XOR2 \U1/Channel0<3>_MC_tsimcreated_xor__565  (
    .I0(\U1/Channel0<3>_MC.D ),
    .I1(\U1/Channel0<3>_MC.Q ),
    .O(\U1/Channel0<3>_MC_tsimcreated_xor_ )
  );
  X_FF \U1/Channel0<3>_MC.REG  (
    .I(\U1/Channel0<3>_MC_tsimcreated_xor_ ),
    .CE(Vcc),
    .CLK(\Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\U1/Channel0<3>_MC.Q )
  );
  X_XOR2 \U1/Channel0<3>_MC.D_566  (
    .I0(\U1/Channel0<3>_MC.D1 ),
    .I1(\U1/Channel0<3>_MC.D2 ),
    .O(\U1/Channel0<3>_MC.D )
  );
  X_ZERO \U1/Channel0<3>_MC.D1_567  (
    .O(\U1/Channel0<3>_MC.D1 )
  );
  X_AND2 \U1/Channel0<3>_MC.D2_PT_0_568  (
    .I0(\NlwInverterSignal_U1/Channel0<3>_MC.D2_PT_0/IN0 ),
    .I1(\U1/Channel0 [3]),
    .O(\U1/Channel0<3>_MC.D2_PT_0 )
  );
  X_AND4 \U1/Channel0<3>_MC.D2_PT_1_569  (
    .I0(N_PZ_964),
    .I1(\NlwInverterSignal_U1/Channel0<3>_MC.D2_PT_1/IN1 ),
    .I2(\NlwInverterSignal_U1/Channel0<3>_MC.D2_PT_1/IN2 ),
    .I3(\NlwInverterSignal_U1/Channel0<3>_MC.D2_PT_1/IN3 ),
    .O(\U1/Channel0<3>_MC.D2_PT_1 )
  );
  X_AND4 \U1/Channel0<3>_MC.D2_PT_2_570  (
    .I0(N_PZ_968),
    .I1(\U1/Channel0 [0]),
    .I2(\U1/Channel0 [1]),
    .I3(\U1/Channel0 [2]),
    .O(\U1/Channel0<3>_MC.D2_PT_2 )
  );
  X_OR3 \U1/Channel0<3>_MC.D2_571  (
    .I0(\U1/Channel0<3>_MC.D2_PT_0 ),
    .I1(\U1/Channel0<3>_MC.D2_PT_1 ),
    .I2(\U1/Channel0<3>_MC.D2_PT_2 ),
    .O(\U1/Channel0<3>_MC.D2 )
  );
  X_BUF \U1/Channel0<4>  (
    .I(\U1/Channel0<4>_MC.Q ),
    .O(\U1/Channel0 [4])
  );
  X_XOR2 \U1/Channel0<4>_MC_tsimcreated_xor__572  (
    .I0(\U1/Channel0<4>_MC.D ),
    .I1(\U1/Channel0<4>_MC.Q ),
    .O(\U1/Channel0<4>_MC_tsimcreated_xor_ )
  );
  X_FF \U1/Channel0<4>_MC.REG  (
    .I(\U1/Channel0<4>_MC_tsimcreated_xor_ ),
    .CE(Vcc),
    .CLK(\Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\U1/Channel0<4>_MC.Q )
  );
  X_XOR2 \U1/Channel0<4>_MC.D_573  (
    .I0(\U1/Channel0<4>_MC.D1 ),
    .I1(\U1/Channel0<4>_MC.D2 ),
    .O(\U1/Channel0<4>_MC.D )
  );
  X_AND3 \U1/Channel0<4>_MC.D1_574  (
    .I0(\NlwInverterSignal_U1/Channel0<4>_MC.D1/IN0 ),
    .I1(N_PZ_968),
    .I2(\U1/Channel0 [4]),
    .O(\U1/Channel0<4>_MC.D1 )
  );
  X_AND3 \U1/Channel0<4>_MC.D2_PT_0_575  (
    .I0(\NlwInverterSignal_U1/Channel0<4>_MC.D2_PT_0/IN0 ),
    .I1(\U1/U2/location_Maddsub__n0000__n0067 [0]),
    .I2(\U1/Channel0 [4]),
    .O(\U1/Channel0<4>_MC.D2_PT_0 )
  );
  X_AND3 \U1/Channel0<4>_MC.D2_PT_1_576  (
    .I0(\NlwInverterSignal_U1/Channel0<4>_MC.D2_PT_1/IN0 ),
    .I1(\NlwInverterSignal_U1/Channel0<4>_MC.D2_PT_1/IN1 ),
    .I2(\U1/Channel0 [4]),
    .O(\U1/Channel0<4>_MC.D2_PT_1 )
  );
  X_AND3 \U1/Channel0<4>_MC.D2_PT_2_577  (
    .I0(\U1/U2/location_Maddsub__n0000__n0067 [0]),
    .I1(N_PZ_964),
    .I2(\NlwInverterSignal_U1/Channel0<4>_MC.D2_PT_2/IN2 ),
    .O(\U1/Channel0<4>_MC.D2_PT_2 )
  );
  X_AND7 \U1/Channel0<4>_MC.D2_PT_3_578  (
    .I0(\U1/U2/location_Maddsub__n0000__n0067 [0]),
    .I1(N_PZ_968),
    .I2(\U1/Channel0 [0]),
    .I3(\U1/Channel0 [1]),
    .I4(\U1/Channel0 [2]),
    .I5(\U1/Channel0 [3]),
    .I6(\NlwInverterSignal_U1/Channel0<4>_MC.D2_PT_3/IN6 ),
    .O(\U1/Channel0<4>_MC.D2_PT_3 )
  );
  X_AND8 \U1/Channel0<4>_MC.D2_PT_4_579  (
    .I0(\NlwInverterSignal_U1/Channel0<4>_MC.D2_PT_4/IN0 ),
    .I1(N_PZ_964),
    .I2(\NlwInverterSignal_U1/Channel0<4>_MC.D2_PT_4/IN2 ),
    .I3(\NlwInverterSignal_U1/Channel0<4>_MC.D2_PT_4/IN3 ),
    .I4(\NlwInverterSignal_U1/Channel0<4>_MC.D2_PT_4/IN4 ),
    .I5(\NlwInverterSignal_U1/Channel0<4>_MC.D2_PT_4/IN5 ),
    .I6(\NlwInverterSignal_U1/Channel0<4>_MC.D2_PT_4/IN6 ),
    .I7(\U1/Channel0 [4]),
    .O(\U1/Channel0<4>_MC.D2_PT_4 )
  );
  X_AND16 \U1/Channel0<4>_MC.D2_PT_5_580  (
    .I0(\MSPReset_II/UIM ),
    .I1(\NlwInverterSignal_U1/Channel0<4>_MC.D2_PT_5/IN1 ),
    .I2(N_PZ_968),
    .I3(\NlwInverterSignal_U1/Channel0<4>_MC.D2_PT_5/IN3 ),
    .I4(\U1/Channel0 [0]),
    .I5(\U1/Channel0 [1]),
    .I6(\U1/Channel0 [2]),
    .I7(\NlwInverterSignal_U1/Channel0<4>_MC.D2_PT_5/IN7 ),
    .I8(\U1/Channel0 [4]),
    .I9(Vcc),
    .I10(Vcc),
    .I11(Vcc),
    .I12(Vcc),
    .I13(Vcc),
    .I14(Vcc),
    .I15(Vcc),
    .O(\U1/Channel0<4>_MC.D2_PT_5 )
  );
  X_OR6 \U1/Channel0<4>_MC.D2_581  (
    .I0(\U1/Channel0<4>_MC.D2_PT_0 ),
    .I1(\U1/Channel0<4>_MC.D2_PT_1 ),
    .I2(\U1/Channel0<4>_MC.D2_PT_2 ),
    .I3(\U1/Channel0<4>_MC.D2_PT_3 ),
    .I4(\U1/Channel0<4>_MC.D2_PT_4 ),
    .I5(\U1/Channel0<4>_MC.D2_PT_5 ),
    .O(\U1/Channel0<4>_MC.D2 )
  );
  X_BUF DCOR0CNTLOWr_582 (
    .I(\DCOR0CNTLOWr_MC.Q ),
    .O(DCOR0CNTLOWr)
  );
  X_BUF \DCOR0CNTLOWr_MC.Q_583  (
    .I(\DCOR0CNTLOWr_MC.D ),
    .O(\DCOR0CNTLOWr_MC.Q )
  );
  X_XOR2 \DCOR0CNTLOWr_MC.D_584  (
    .I0(\DCOR0CNTLOWr_MC.D1 ),
    .I1(\DCOR0CNTLOWr_MC.D2 ),
    .O(\DCOR0CNTLOWr_MC.D )
  );
  X_AND16 \DCOR0CNTLOWr_MC.D1_585  (
    .I0(\WR_II/UIM ),
    .I1(\NlwInverterSignal_DCOR0CNTLOWr_MC.D1/IN1 ),
    .I2(\NlwInverterSignal_DCOR0CNTLOWr_MC.D1/IN2 ),
    .I3(\NlwInverterSignal_DCOR0CNTLOWr_MC.D1/IN3 ),
    .I4(\NlwInverterSignal_DCOR0CNTLOWr_MC.D1/IN4 ),
    .I5(\NlwInverterSignal_DCOR0CNTLOWr_MC.D1/IN5 ),
    .I6(\NlwInverterSignal_DCOR0CNTLOWr_MC.D1/IN6 ),
    .I7(\NlwInverterSignal_DCOR0CNTLOWr_MC.D1/IN7 ),
    .I8(\NlwInverterSignal_DCOR0CNTLOWr_MC.D1/IN8 ),
    .I9(U2_ADDR_reg[2]),
    .I10(Vcc),
    .I11(Vcc),
    .I12(Vcc),
    .I13(Vcc),
    .I14(Vcc),
    .I15(Vcc),
    .O(\DCOR0CNTLOWr_MC.D1 )
  );
  X_ZERO \DCOR0CNTLOWr_MC.D2_586  (
    .O(\DCOR0CNTLOWr_MC.D2 )
  );
  X_BUF \U1/U3/holdingreg1<5>  (
    .I(\U1/U3/holdingreg1<5>_MC.Q ),
    .O(\U1/U3/holdingreg1 [5])
  );
  X_FF \U1/U3/holdingreg1<5>_MC.REG  (
    .I(\U1/U3/holdingreg1<5>_MC.D ),
    .CE(Vcc),
    .CLK(\U1/U3/holdingreg1<5>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\U1/U3/holdingreg1<5>_MC.Q )
  );
  X_INV \U1/U3/holdingreg1<5>_MC.REG_tsimcreated_inv_Mclk_II/FCLK_587  (
    .I(\Mclk_II/FCLK ),
    .O(\U1/U3/holdingreg1<5>_MC.REG_tsimcreated_inv_Mclk_II/FCLK )
  );
  X_XOR2 \U1/U3/holdingreg1<5>_MC.D_588  (
    .I0(\U1/U3/holdingreg1<5>_MC.D1 ),
    .I1(\U1/U3/holdingreg1<5>_MC.D2 ),
    .O(\U1/U3/holdingreg1<5>_MC.D )
  );
  X_ZERO \U1/U3/holdingreg1<5>_MC.D1_589  (
    .O(\U1/U3/holdingreg1<5>_MC.D1 )
  );
  X_AND2 \U1/U3/holdingreg1<5>_MC.D2_PT_0_590  (
    .I0(N_PZ_938),
    .I1(\U1/U3/holdingreg1 [5]),
    .O(\U1/U3/holdingreg1<5>_MC.D2_PT_0 )
  );
  X_AND4 \U1/U3/holdingreg1<5>_MC.D2_PT_1_591  (
    .I0(\MSPReset_II/UIM ),
    .I1(\NlwInverterSignal_U1/U3/holdingreg1<5>_MC.D2_PT_1/IN1 ),
    .I2(U2_ASedge),
    .I3(\U1/Channel1 [5]),
    .O(\U1/U3/holdingreg1<5>_MC.D2_PT_1 )
  );
  X_OR2 \U1/U3/holdingreg1<5>_MC.D2_592  (
    .I0(\U1/U3/holdingreg1<5>_MC.D2_PT_0 ),
    .I1(\U1/U3/holdingreg1<5>_MC.D2_PT_1 ),
    .O(\U1/U3/holdingreg1<5>_MC.D2 )
  );
  X_BUF \U1/Channel1<5>  (
    .I(\U1/Channel1<5>_MC.Q ),
    .O(\U1/Channel1 [5])
  );
  X_XOR2 \U1/Channel1<5>_MC_tsimcreated_xor__593  (
    .I0(\U1/Channel1<5>_MC.D ),
    .I1(\U1/Channel1<5>_MC.Q ),
    .O(\U1/Channel1<5>_MC_tsimcreated_xor_ )
  );
  X_FF \U1/Channel1<5>_MC.REG  (
    .I(\U1/Channel1<5>_MC_tsimcreated_xor_ ),
    .CE(Vcc),
    .CLK(\Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\U1/Channel1<5>_MC.Q )
  );
  X_XOR2 \U1/Channel1<5>_MC.D_594  (
    .I0(\U1/Channel1<5>_MC.D1 ),
    .I1(\U1/Channel1<5>_MC.D2 ),
    .O(\U1/Channel1<5>_MC.D )
  );
  X_ZERO \U1/Channel1<5>_MC.D1_595  (
    .O(\U1/Channel1<5>_MC.D1 )
  );
  X_AND2 \U1/Channel1<5>_MC.D2_PT_0_596  (
    .I0(\U1/Channel1 [5]),
    .I1(\NlwInverterSignal_U1/Channel1<5>_MC.D2_PT_0/IN1 ),
    .O(\U1/Channel1<5>_MC.D2_PT_0 )
  );
  X_AND6 \U1/Channel1<5>_MC.D2_PT_1_597  (
    .I0(\MSPReset_II/UIM ),
    .I1(\NlwInverterSignal_U1/Channel1<5>_MC.D2_PT_1/IN1 ),
    .I2(\U1/U6/CurrState_Sreg0_FFD3 ),
    .I3(\NlwInverterSignal_U1/Channel1<5>_MC.D2_PT_1/IN3 ),
    .I4(\NlwInverterSignal_U1/Channel1<5>_MC.D2_PT_1/IN4 ),
    .I5(N_PZ_921),
    .O(\U1/Channel1<5>_MC.D2_PT_1 )
  );
  X_AND7 \U1/Channel1<5>_MC.D2_PT_2_598  (
    .I0(\MSPReset_II/UIM ),
    .I1(\NlwInverterSignal_U1/Channel1<5>_MC.D2_PT_2/IN1 ),
    .I2(\U1/U6/CurrState_Sreg0_FFD3 ),
    .I3(\NlwInverterSignal_U1/Channel1<5>_MC.D2_PT_2/IN3 ),
    .I4(\U1/U5/location_Maddsub__n0000__n0067 [0]),
    .I5(\NlwInverterSignal_U1/Channel1<5>_MC.D2_PT_2/IN5 ),
    .I6(N_PZ_1092),
    .O(\U1/Channel1<5>_MC.D2_PT_2 )
  );
  X_OR3 \U1/Channel1<5>_MC.D2_599  (
    .I0(\U1/Channel1<5>_MC.D2_PT_0 ),
    .I1(\U1/Channel1<5>_MC.D2_PT_1 ),
    .I2(\U1/Channel1<5>_MC.D2_PT_2 ),
    .O(\U1/Channel1<5>_MC.D2 )
  );
  X_BUF N_PZ_929_600 (
    .I(\N_PZ_929_MC.Q ),
    .O(N_PZ_929)
  );
  X_BUF \N_PZ_929_MC.Q_601  (
    .I(\N_PZ_929_MC.D ),
    .O(\N_PZ_929_MC.Q )
  );
  X_XOR2 \N_PZ_929_MC.D_602  (
    .I0(\N_PZ_929_MC.D1 ),
    .I1(\N_PZ_929_MC.D2 ),
    .O(\N_PZ_929_MC.D )
  );
  X_AND2 \N_PZ_929_MC.D1_603  (
    .I0(\MSPReset_II/UIM ),
    .I1(\NlwInverterSignal_N_PZ_929_MC.D1/IN1 ),
    .O(\N_PZ_929_MC.D1 )
  );
  X_ZERO \N_PZ_929_MC.D2_604  (
    .O(\N_PZ_929_MC.D2 )
  );
  X_BUF \U1/Zero1_605  (
    .I(\U1/Zero1_MC.Q ),
    .O(\U1/Zero1 )
  );
  X_FF \U1/Zero1_MC.REG  (
    .I(\U1/Zero1_MC.D ),
    .CE(Vcc),
    .CLK(\U1/Zero1_MC.REG_tsimcreated_inv_Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\U1/Zero1_MC.Q )
  );
  X_INV \U1/Zero1_MC.REG_tsimcreated_inv_Mclk_II/FCLK_606  (
    .I(\Mclk_II/FCLK ),
    .O(\U1/Zero1_MC.REG_tsimcreated_inv_Mclk_II/FCLK )
  );
  X_XOR2 \U1/Zero1_MC.D_607  (
    .I0(\U1/Zero1_MC.D1 ),
    .I1(\U1/Zero1_MC.D2 ),
    .O(\U1/Zero1_MC.D )
  );
  X_ZERO \U1/Zero1_MC.D1_608  (
    .O(\U1/Zero1_MC.D1 )
  );
  X_AND2 \U1/Zero1_MC.D2_PT_0_609  (
    .I0(\NlwInverterSignal_U1/Zero1_MC.D2_PT_0/IN0 ),
    .I1(\U1/Zero1 ),
    .O(\U1/Zero1_MC.D2_PT_0 )
  );
  X_AND2 \U1/Zero1_MC.D2_PT_1_610  (
    .I0(DCORIFGw),
    .I1(\U1/Zero1 ),
    .O(\U1/Zero1_MC.D2_PT_1 )
  );
  X_AND2 \U1/Zero1_MC.D2_PT_2_611  (
    .I0(DCORENCCTLw),
    .I1(\U1/Zero1 ),
    .O(\U1/Zero1_MC.D2_PT_2 )
  );
  X_AND8 \U1/Zero1_MC.D2_PT_3_612  (
    .I0(\MSPReset_II/UIM ),
    .I1(\NlwInverterSignal_U1/Zero1_MC.D2_PT_3/IN1 ),
    .I2(\NlwInverterSignal_U1/Zero1_MC.D2_PT_3/IN2 ),
    .I3(\NlwInverterSignal_U1/Zero1_MC.D2_PT_3/IN3 ),
    .I4(\U1/U4/RF1r ),
    .I5(\U1/U4/E1r ),
    .I6(\U1/U4/HE1stater ),
    .I7(\NlwInverterSignal_U1/Zero1_MC.D2_PT_3/IN7 ),
    .O(\U1/Zero1_MC.D2_PT_3 )
  );
  X_AND8 \U1/Zero1_MC.D2_PT_4_613  (
    .I0(\MSPReset_II/UIM ),
    .I1(\NlwInverterSignal_U1/Zero1_MC.D2_PT_4/IN1 ),
    .I2(\NlwInverterSignal_U1/Zero1_MC.D2_PT_4/IN2 ),
    .I3(\NlwInverterSignal_U1/Zero1_MC.D2_PT_4/IN3 ),
    .I4(\NlwInverterSignal_U1/Zero1_MC.D2_PT_4/IN4 ),
    .I5(\U1/U4/E1r ),
    .I6(\NlwInverterSignal_U1/Zero1_MC.D2_PT_4/IN6 ),
    .I7(\U1/U4/HE1statelastr ),
    .O(\U1/Zero1_MC.D2_PT_4 )
  );
  X_OR5 \U1/Zero1_MC.D2_614  (
    .I0(\U1/Zero1_MC.D2_PT_0 ),
    .I1(\U1/Zero1_MC.D2_PT_1 ),
    .I2(\U1/Zero1_MC.D2_PT_2 ),
    .I3(\U1/Zero1_MC.D2_PT_3 ),
    .I4(\U1/Zero1_MC.D2_PT_4 ),
    .O(\U1/Zero1_MC.D2 )
  );
  X_BUF NET2493_615 (
    .I(\NET2493_MC.Q ),
    .O(NET2493)
  );
  X_XOR2 NET2493_MC_tsimcreated_xor__616 (
    .I0(\NET2493_MC.D ),
    .I1(\NET2493_MC.Q ),
    .O(NET2493_MC_tsimcreated_xor_)
  );
  X_FF \NET2493_MC.REG  (
    .I(NET2493_MC_tsimcreated_xor_),
    .CE(Vcc),
    .CLK(\NET2493_MC.REG_tsimcreated_inv_Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\NET2493_MC.Q )
  );
  X_INV \NET2493_MC.REG_tsimcreated_inv_Mclk_II/FCLK_617  (
    .I(\Mclk_II/FCLK ),
    .O(\NET2493_MC.REG_tsimcreated_inv_Mclk_II/FCLK )
  );
  X_XOR2 \NET2493_MC.D_618  (
    .I0(\NET2493_MC.D1 ),
    .I1(\NET2493_MC.D2 ),
    .O(\NET2493_MC.D )
  );
  X_ZERO \NET2493_MC.D1_619  (
    .O(\NET2493_MC.D1 )
  );
  X_AND2 \NET2493_MC.D2_PT_0_620  (
    .I0(\NlwInverterSignal_NET2493_MC.D2_PT_0/IN0 ),
    .I1(NET2493),
    .O(\NET2493_MC.D2_PT_0 )
  );
  X_AND4 \NET2493_MC.D2_PT_1_621  (
    .I0(\AD<3>_II/UIM ),
    .I1(DCORIFGw),
    .I2(\NlwInverterSignal_NET2493_MC.D2_PT_1/IN2 ),
    .I3(NET2493),
    .O(\NET2493_MC.D2_PT_1 )
  );
  X_AND8 \NET2493_MC.D2_PT_2_622  (
    .I0(\MSPReset_II/UIM ),
    .I1(\NlwInverterSignal_NET2493_MC.D2_PT_2/IN1 ),
    .I2(\NlwInverterSignal_NET2493_MC.D2_PT_2/IN2 ),
    .I3(\NlwInverterSignal_NET2493_MC.D2_PT_2/IN3 ),
    .I4(\U1/U4/RF1r ),
    .I5(\U1/U4/E1r ),
    .I6(\U1/U4/HE1stater ),
    .I7(\NlwInverterSignal_NET2493_MC.D2_PT_2/IN7 ),
    .O(\NET2493_MC.D2_PT_2 )
  );
  X_AND8 \NET2493_MC.D2_PT_3_623  (
    .I0(\MSPReset_II/UIM ),
    .I1(\NlwInverterSignal_NET2493_MC.D2_PT_3/IN1 ),
    .I2(\NlwInverterSignal_NET2493_MC.D2_PT_3/IN2 ),
    .I3(\NlwInverterSignal_NET2493_MC.D2_PT_3/IN3 ),
    .I4(\NlwInverterSignal_NET2493_MC.D2_PT_3/IN4 ),
    .I5(\U1/U4/E1r ),
    .I6(\NlwInverterSignal_NET2493_MC.D2_PT_3/IN6 ),
    .I7(\U1/U4/HE1statelastr ),
    .O(\NET2493_MC.D2_PT_3 )
  );
  X_OR4 \NET2493_MC.D2_624  (
    .I0(\NET2493_MC.D2_PT_0 ),
    .I1(\NET2493_MC.D2_PT_1 ),
    .I2(\NET2493_MC.D2_PT_2 ),
    .I3(\NET2493_MC.D2_PT_3 ),
    .O(\NET2493_MC.D2 )
  );
  X_BUF \U1/U4/RF1r_625  (
    .I(\U1/U4/RF1r_MC.Q ),
    .O(\U1/U4/RF1r )
  );
  X_FF \U1/U4/RF1r_MC.REG  (
    .I(\U1/U4/RF1r_MC.D ),
    .CE(Vcc),
    .CLK(\U1/U4/RF1r_MC.REG_tsimcreated_inv_Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\U1/U4/RF1r_MC.Q )
  );
  X_INV \U1/U4/RF1r_MC.REG_tsimcreated_inv_Mclk_II/FCLK_626  (
    .I(\Mclk_II/FCLK ),
    .O(\U1/U4/RF1r_MC.REG_tsimcreated_inv_Mclk_II/FCLK )
  );
  X_XOR2 \U1/U4/RF1r_MC.D_627  (
    .I0(\U1/U4/RF1r_MC.D1 ),
    .I1(\U1/U4/RF1r_MC.D2 ),
    .O(\U1/U4/RF1r_MC.D )
  );
  X_ZERO \U1/U4/RF1r_MC.D1_628  (
    .O(\U1/U4/RF1r_MC.D1 )
  );
  X_AND3 \U1/U4/RF1r_MC.D2_PT_0_629  (
    .I0(\MSPReset_II/UIM ),
    .I1(\AD<4>_II/UIM ),
    .I2(DCORENCCTLw),
    .O(\U1/U4/RF1r_MC.D2_PT_0 )
  );
  X_AND3 \U1/U4/RF1r_MC.D2_PT_1_630  (
    .I0(\MSPReset_II/UIM ),
    .I1(\NlwInverterSignal_U1/U4/RF1r_MC.D2_PT_1/IN1 ),
    .I2(\U1/U4/RF1r ),
    .O(\U1/U4/RF1r_MC.D2_PT_1 )
  );
  X_OR2 \U1/U4/RF1r_MC.D2_631  (
    .I0(\U1/U4/RF1r_MC.D2_PT_0 ),
    .I1(\U1/U4/RF1r_MC.D2_PT_1 ),
    .O(\U1/U4/RF1r_MC.D2 )
  );
  X_BUF \U1/U4/E1r_632  (
    .I(\U1/U4/E1r_MC.Q ),
    .O(\U1/U4/E1r )
  );
  X_FF \U1/U4/E1r_MC.REG  (
    .I(\U1/U4/E1r_MC.D ),
    .CE(Vcc),
    .CLK(\U1/U4/E1r_MC.REG_tsimcreated_inv_Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\U1/U4/E1r_MC.Q )
  );
  X_INV \U1/U4/E1r_MC.REG_tsimcreated_inv_Mclk_II/FCLK_633  (
    .I(\Mclk_II/FCLK ),
    .O(\U1/U4/E1r_MC.REG_tsimcreated_inv_Mclk_II/FCLK )
  );
  X_XOR2 \U1/U4/E1r_MC.D_634  (
    .I0(\U1/U4/E1r_MC.D1 ),
    .I1(\U1/U4/E1r_MC.D2 ),
    .O(\U1/U4/E1r_MC.D )
  );
  X_ZERO \U1/U4/E1r_MC.D1_635  (
    .O(\U1/U4/E1r_MC.D1 )
  );
  X_AND3 \U1/U4/E1r_MC.D2_PT_0_636  (
    .I0(\MSPReset_II/UIM ),
    .I1(\AD<5>_II/UIM ),
    .I2(DCORENCCTLw),
    .O(\U1/U4/E1r_MC.D2_PT_0 )
  );
  X_AND3 \U1/U4/E1r_MC.D2_PT_1_637  (
    .I0(\MSPReset_II/UIM ),
    .I1(\NlwInverterSignal_U1/U4/E1r_MC.D2_PT_1/IN1 ),
    .I2(\U1/U4/E1r ),
    .O(\U1/U4/E1r_MC.D2_PT_1 )
  );
  X_OR2 \U1/U4/E1r_MC.D2_638  (
    .I0(\U1/U4/E1r_MC.D2_PT_0 ),
    .I1(\U1/U4/E1r_MC.D2_PT_1 ),
    .O(\U1/U4/E1r_MC.D2 )
  );
  X_BUF \U1/U4/HE1statelastr_639  (
    .I(\U1/U4/HE1statelastr_MC.Q ),
    .O(\U1/U4/HE1statelastr )
  );
  X_FF \U1/U4/HE1statelastr_MC.REG  (
    .I(\U1/U4/HE1statelastr_MC.D ),
    .CE(Vcc),
    .CLK(\U1/U4/HE1statelastr_MC.REG_tsimcreated_inv_Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\U1/U4/HE1statelastr_MC.Q )
  );
  X_INV \U1/U4/HE1statelastr_MC.REG_tsimcreated_inv_Mclk_II/FCLK_640  (
    .I(\Mclk_II/FCLK ),
    .O(\U1/U4/HE1statelastr_MC.REG_tsimcreated_inv_Mclk_II/FCLK )
  );
  X_XOR2 \U1/U4/HE1statelastr_MC.D_641  (
    .I0(\U1/U4/HE1statelastr_MC.D1 ),
    .I1(\U1/U4/HE1statelastr_MC.D2 ),
    .O(\U1/U4/HE1statelastr_MC.D )
  );
  X_AND2 \U1/U4/HE1statelastr_MC.D1_642  (
    .I0(\U1/U4/HE1stater ),
    .I1(\U1/U4/HE1stater ),
    .O(\U1/U4/HE1statelastr_MC.D1 )
  );
  X_ZERO \U1/U4/HE1statelastr_MC.D2_643  (
    .O(\U1/U4/HE1statelastr_MC.D2 )
  );
  X_BUF \U1/U6/CurrState_Sreg0_FFD3_644  (
    .I(\U1/U6/CurrState_Sreg0_FFD3_MC.Q ),
    .O(\U1/U6/CurrState_Sreg0_FFD3 )
  );
  X_FF \U1/U6/CurrState_Sreg0_FFD3_MC.REG  (
    .I(\U1/U6/CurrState_Sreg0_FFD3_MC.D ),
    .CE(Vcc),
    .CLK(\Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\U1/U6/CurrState_Sreg0_FFD3_MC.Q )
  );
  X_XOR2 \U1/U6/CurrState_Sreg0_FFD3_MC.D_645  (
    .I0(\U1/U6/CurrState_Sreg0_FFD3_MC.D1 ),
    .I1(\U1/U6/CurrState_Sreg0_FFD3_MC.D2 ),
    .O(\U1/U6/CurrState_Sreg0_FFD3_MC.D )
  );
  X_ZERO \U1/U6/CurrState_Sreg0_FFD3_MC.D1_646  (
    .O(\U1/U6/CurrState_Sreg0_FFD3_MC.D1 )
  );
  X_AND5 \U1/U6/CurrState_Sreg0_FFD3_MC.D2_PT_0_647  (
    .I0(\MSPReset_II/UIM ),
    .I1(\U1/U6/CurrState_Sreg0_FFD3 ),
    .I2(\U1/U6/CurrState_Sreg0_FFD2 ),
    .I3(\NlwInverterSignal_U1/U6/CurrState_Sreg0_FFD3_MC.D2_PT_0/IN3 ),
    .I4(\NlwInverterSignal_U1/U6/CurrState_Sreg0_FFD3_MC.D2_PT_0/IN4 ),
    .O(\U1/U6/CurrState_Sreg0_FFD3_MC.D2_PT_0 )
  );
  X_AND5 \U1/U6/CurrState_Sreg0_FFD3_MC.D2_PT_1_648  (
    .I0(\MSPReset_II/UIM ),
    .I1(\U1/U6/CurrState_Sreg0_FFD3 ),
    .I2(\NlwInverterSignal_U1/U6/CurrState_Sreg0_FFD3_MC.D2_PT_1/IN2 ),
    .I3(\NlwInverterSignal_U1/U6/CurrState_Sreg0_FFD3_MC.D2_PT_1/IN3 ),
    .I4(\NlwInverterSignal_U1/U6/CurrState_Sreg0_FFD3_MC.D2_PT_1/IN4 ),
    .O(\U1/U6/CurrState_Sreg0_FFD3_MC.D2_PT_1 )
  );
  X_AND6 \U1/U6/CurrState_Sreg0_FFD3_MC.D2_PT_2_649  (
    .I0(\MSPReset_II/UIM ),
    .I1(\U1/U6/CurrState_Sreg0_FFD2 ),
    .I2(\PhaseA_Encoder1_II/UIM ),
    .I3(\NlwInverterSignal_U1/U6/CurrState_Sreg0_FFD3_MC.D2_PT_2/IN3 ),
    .I4(\U1/U6/CurrState_Sreg0_FFD1 ),
    .I5(\NlwInverterSignal_U1/U6/CurrState_Sreg0_FFD3_MC.D2_PT_2/IN5 ),
    .O(\U1/U6/CurrState_Sreg0_FFD3_MC.D2_PT_2 )
  );
  X_AND6 \U1/U6/CurrState_Sreg0_FFD3_MC.D2_PT_3_650  (
    .I0(\MSPReset_II/UIM ),
    .I1(\U1/U6/CurrState_Sreg0_FFD2 ),
    .I2(\PhaseA_Encoder1_II/UIM ),
    .I3(\NlwInverterSignal_U1/U6/CurrState_Sreg0_FFD3_MC.D2_PT_3/IN3 ),
    .I4(\NlwInverterSignal_U1/U6/CurrState_Sreg0_FFD3_MC.D2_PT_3/IN4 ),
    .I5(\PhaseB_Encoder1_II/UIM ),
    .O(\U1/U6/CurrState_Sreg0_FFD3_MC.D2_PT_3 )
  );
  X_OR4 \U1/U6/CurrState_Sreg0_FFD3_MC.D2_651  (
    .I0(\U1/U6/CurrState_Sreg0_FFD3_MC.D2_PT_0 ),
    .I1(\U1/U6/CurrState_Sreg0_FFD3_MC.D2_PT_1 ),
    .I2(\U1/U6/CurrState_Sreg0_FFD3_MC.D2_PT_2 ),
    .I3(\U1/U6/CurrState_Sreg0_FFD3_MC.D2_PT_3 ),
    .O(\U1/U6/CurrState_Sreg0_FFD3_MC.D2 )
  );
  X_BUF \U1/U6/CurrState_Sreg0_FFD1_652  (
    .I(\U1/U6/CurrState_Sreg0_FFD1_MC.Q ),
    .O(\U1/U6/CurrState_Sreg0_FFD1 )
  );
  X_FF \U1/U6/CurrState_Sreg0_FFD1_MC.REG  (
    .I(\U1/U6/CurrState_Sreg0_FFD1_MC.D ),
    .CE(Vcc),
    .CLK(\Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\U1/U6/CurrState_Sreg0_FFD1_MC.Q )
  );
  X_XOR2 \U1/U6/CurrState_Sreg0_FFD1_MC.D_653  (
    .I0(\U1/U6/CurrState_Sreg0_FFD1_MC.D1 ),
    .I1(\U1/U6/CurrState_Sreg0_FFD1_MC.D2 ),
    .O(\U1/U6/CurrState_Sreg0_FFD1_MC.D )
  );
  X_ZERO \U1/U6/CurrState_Sreg0_FFD1_MC.D1_654  (
    .O(\U1/U6/CurrState_Sreg0_FFD1_MC.D1 )
  );
  X_AND4 \U1/U6/CurrState_Sreg0_FFD1_MC.D2_PT_0_655  (
    .I0(\MSPReset_II/UIM ),
    .I1(\U1/U6/CurrState_Sreg0_FFD2 ),
    .I2(\NlwInverterSignal_U1/U6/CurrState_Sreg0_FFD1_MC.D2_PT_0/IN2 ),
    .I3(\U1/U6/CurrState_Sreg0_FFD1 ),
    .O(\U1/U6/CurrState_Sreg0_FFD1_MC.D2_PT_0 )
  );
  X_AND5 \U1/U6/CurrState_Sreg0_FFD1_MC.D2_PT_1_656  (
    .I0(\MSPReset_II/UIM ),
    .I1(\NlwInverterSignal_U1/U6/CurrState_Sreg0_FFD1_MC.D2_PT_1/IN1 ),
    .I2(\PhaseA_Encoder1_II/UIM ),
    .I3(\NlwInverterSignal_U1/U6/CurrState_Sreg0_FFD1_MC.D2_PT_1/IN3 ),
    .I4(\U1/U6/CurrState_Sreg0_FFD1 ),
    .O(\U1/U6/CurrState_Sreg0_FFD1_MC.D2_PT_1 )
  );
  X_AND6 \U1/U6/CurrState_Sreg0_FFD1_MC.D2_PT_2_657  (
    .I0(\MSPReset_II/UIM ),
    .I1(\NlwInverterSignal_U1/U6/CurrState_Sreg0_FFD1_MC.D2_PT_2/IN1 ),
    .I2(\NlwInverterSignal_U1/U6/CurrState_Sreg0_FFD1_MC.D2_PT_2/IN2 ),
    .I3(\NlwInverterSignal_U1/U6/CurrState_Sreg0_FFD1_MC.D2_PT_2/IN3 ),
    .I4(\NlwInverterSignal_U1/U6/CurrState_Sreg0_FFD1_MC.D2_PT_2/IN4 ),
    .I5(\PhaseB_Encoder1_II/UIM ),
    .O(\U1/U6/CurrState_Sreg0_FFD1_MC.D2_PT_2 )
  );
  X_OR3 \U1/U6/CurrState_Sreg0_FFD1_MC.D2_658  (
    .I0(\U1/U6/CurrState_Sreg0_FFD1_MC.D2_PT_0 ),
    .I1(\U1/U6/CurrState_Sreg0_FFD1_MC.D2_PT_1 ),
    .I2(\U1/U6/CurrState_Sreg0_FFD1_MC.D2_PT_2 ),
    .O(\U1/U6/CurrState_Sreg0_FFD1_MC.D2 )
  );
  X_BUF \U1/U6/CurrState_Sreg0_FFD4_659  (
    .I(\U1/U6/CurrState_Sreg0_FFD4_MC.Q ),
    .O(\U1/U6/CurrState_Sreg0_FFD4 )
  );
  X_FF \U1/U6/CurrState_Sreg0_FFD4_MC.REG  (
    .I(\U1/U6/CurrState_Sreg0_FFD4_MC.D ),
    .CE(Vcc),
    .CLK(\Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\U1/U6/CurrState_Sreg0_FFD4_MC.Q )
  );
  X_XOR2 \U1/U6/CurrState_Sreg0_FFD4_MC.D_660  (
    .I0(\U1/U6/CurrState_Sreg0_FFD4_MC.D1 ),
    .I1(\U1/U6/CurrState_Sreg0_FFD4_MC.D2 ),
    .O(\U1/U6/CurrState_Sreg0_FFD4_MC.D )
  );
  X_AND7 \U1/U6/CurrState_Sreg0_FFD4_MC.D1_661  (
    .I0(\MSPReset_II/UIM ),
    .I1(\U1/U6/CurrState_Sreg0_FFD3 ),
    .I2(\NlwInverterSignal_U1/U6/CurrState_Sreg0_FFD4_MC.D1/IN2 ),
    .I3(\NlwInverterSignal_U1/U6/CurrState_Sreg0_FFD4_MC.D1/IN3 ),
    .I4(\NlwInverterSignal_U1/U6/CurrState_Sreg0_FFD4_MC.D1/IN4 ),
    .I5(\NlwInverterSignal_U1/U6/CurrState_Sreg0_FFD4_MC.D1/IN5 ),
    .I6(\NlwInverterSignal_U1/U6/CurrState_Sreg0_FFD4_MC.D1/IN6 ),
    .O(\U1/U6/CurrState_Sreg0_FFD4_MC.D1 )
  );
  X_ZERO \U1/U6/CurrState_Sreg0_FFD4_MC.D2_662  (
    .O(\U1/U6/CurrState_Sreg0_FFD4_MC.D2 )
  );
  X_BUF \U1/U6/CurrState_Sreg0_FFD2_663  (
    .I(\U1/U6/CurrState_Sreg0_FFD2_MC.Q ),
    .O(\U1/U6/CurrState_Sreg0_FFD2 )
  );
  X_FF \U1/U6/CurrState_Sreg0_FFD2_MC.REG  (
    .I(\U1/U6/CurrState_Sreg0_FFD2_MC.D ),
    .CE(Vcc),
    .CLK(\Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\U1/U6/CurrState_Sreg0_FFD2_MC.Q )
  );
  X_XOR2 \U1/U6/CurrState_Sreg0_FFD2_MC.D_664  (
    .I0(\U1/U6/CurrState_Sreg0_FFD2_MC.D1 ),
    .I1(\U1/U6/CurrState_Sreg0_FFD2_MC.D2 ),
    .O(\U1/U6/CurrState_Sreg0_FFD2_MC.D )
  );
  X_ZERO \U1/U6/CurrState_Sreg0_FFD2_MC.D1_665  (
    .O(\U1/U6/CurrState_Sreg0_FFD2_MC.D1 )
  );
  X_AND6 \U1/U6/CurrState_Sreg0_FFD2_MC.D2_PT_0_666  (
    .I0(\MSPReset_II/UIM ),
    .I1(\U1/U6/CurrState_Sreg0_FFD3 ),
    .I2(\U1/U6/CurrState_Sreg0_FFD2 ),
    .I3(\NlwInverterSignal_U1/U6/CurrState_Sreg0_FFD2_MC.D2_PT_0/IN3 ),
    .I4(\U1/U6/CurrState_Sreg0_FFD1 ),
    .I5(\PhaseB_Encoder1_II/UIM ),
    .O(\U1/U6/CurrState_Sreg0_FFD2_MC.D2_PT_0 )
  );
  X_AND6 \U1/U6/CurrState_Sreg0_FFD2_MC.D2_PT_1_667  (
    .I0(\MSPReset_II/UIM ),
    .I1(\U1/U6/CurrState_Sreg0_FFD3 ),
    .I2(\U1/U6/CurrState_Sreg0_FFD2 ),
    .I3(\NlwInverterSignal_U1/U6/CurrState_Sreg0_FFD2_MC.D2_PT_1/IN3 ),
    .I4(\NlwInverterSignal_U1/U6/CurrState_Sreg0_FFD2_MC.D2_PT_1/IN4 ),
    .I5(\NlwInverterSignal_U1/U6/CurrState_Sreg0_FFD2_MC.D2_PT_1/IN5 ),
    .O(\U1/U6/CurrState_Sreg0_FFD2_MC.D2_PT_1 )
  );
  X_AND6 \U1/U6/CurrState_Sreg0_FFD2_MC.D2_PT_2_668  (
    .I0(\MSPReset_II/UIM ),
    .I1(\U1/U6/CurrState_Sreg0_FFD3 ),
    .I2(\PhaseA_Encoder1_II/UIM ),
    .I3(\NlwInverterSignal_U1/U6/CurrState_Sreg0_FFD2_MC.D2_PT_2/IN3 ),
    .I4(\NlwInverterSignal_U1/U6/CurrState_Sreg0_FFD2_MC.D2_PT_2/IN4 ),
    .I5(\PhaseB_Encoder1_II/UIM ),
    .O(\U1/U6/CurrState_Sreg0_FFD2_MC.D2_PT_2 )
  );
  X_AND6 \U1/U6/CurrState_Sreg0_FFD2_MC.D2_PT_3_669  (
    .I0(\MSPReset_II/UIM ),
    .I1(\NlwInverterSignal_U1/U6/CurrState_Sreg0_FFD2_MC.D2_PT_3/IN1 ),
    .I2(\U1/U6/CurrState_Sreg0_FFD2 ),
    .I3(\NlwInverterSignal_U1/U6/CurrState_Sreg0_FFD2_MC.D2_PT_3/IN3 ),
    .I4(\U1/U6/CurrState_Sreg0_FFD1 ),
    .I5(\NlwInverterSignal_U1/U6/CurrState_Sreg0_FFD2_MC.D2_PT_3/IN5 ),
    .O(\U1/U6/CurrState_Sreg0_FFD2_MC.D2_PT_3 )
  );
  X_AND6 \U1/U6/CurrState_Sreg0_FFD2_MC.D2_PT_4_670  (
    .I0(\MSPReset_II/UIM ),
    .I1(\NlwInverterSignal_U1/U6/CurrState_Sreg0_FFD2_MC.D2_PT_4/IN1 ),
    .I2(\U1/U6/CurrState_Sreg0_FFD2 ),
    .I3(\NlwInverterSignal_U1/U6/CurrState_Sreg0_FFD2_MC.D2_PT_4/IN3 ),
    .I4(\NlwInverterSignal_U1/U6/CurrState_Sreg0_FFD2_MC.D2_PT_4/IN4 ),
    .I5(\PhaseB_Encoder1_II/UIM ),
    .O(\U1/U6/CurrState_Sreg0_FFD2_MC.D2_PT_4 )
  );
  X_AND6 \U1/U6/CurrState_Sreg0_FFD2_MC.D2_PT_5_671  (
    .I0(\MSPReset_II/UIM ),
    .I1(\NlwInverterSignal_U1/U6/CurrState_Sreg0_FFD2_MC.D2_PT_5/IN1 ),
    .I2(\PhaseA_Encoder1_II/UIM ),
    .I3(\NlwInverterSignal_U1/U6/CurrState_Sreg0_FFD2_MC.D2_PT_5/IN3 ),
    .I4(\U1/U6/CurrState_Sreg0_FFD1 ),
    .I5(\PhaseB_Encoder1_II/UIM ),
    .O(\U1/U6/CurrState_Sreg0_FFD2_MC.D2_PT_5 )
  );
  X_AND6 \U1/U6/CurrState_Sreg0_FFD2_MC.D2_PT_6_672  (
    .I0(\MSPReset_II/UIM ),
    .I1(\NlwInverterSignal_U1/U6/CurrState_Sreg0_FFD2_MC.D2_PT_6/IN1 ),
    .I2(\PhaseA_Encoder1_II/UIM ),
    .I3(\NlwInverterSignal_U1/U6/CurrState_Sreg0_FFD2_MC.D2_PT_6/IN3 ),
    .I4(\NlwInverterSignal_U1/U6/CurrState_Sreg0_FFD2_MC.D2_PT_6/IN4 ),
    .I5(\NlwInverterSignal_U1/U6/CurrState_Sreg0_FFD2_MC.D2_PT_6/IN5 ),
    .O(\U1/U6/CurrState_Sreg0_FFD2_MC.D2_PT_6 )
  );
  X_AND6 \U1/U6/CurrState_Sreg0_FFD2_MC.D2_PT_7_673  (
    .I0(\MSPReset_II/UIM ),
    .I1(\U1/U6/CurrState_Sreg0_FFD2 ),
    .I2(\PhaseA_Encoder1_II/UIM ),
    .I3(\NlwInverterSignal_U1/U6/CurrState_Sreg0_FFD2_MC.D2_PT_7/IN3 ),
    .I4(\U1/U6/CurrState_Sreg0_FFD1 ),
    .I5(\NlwInverterSignal_U1/U6/CurrState_Sreg0_FFD2_MC.D2_PT_7/IN5 ),
    .O(\U1/U6/CurrState_Sreg0_FFD2_MC.D2_PT_7 )
  );
  X_OR8 \U1/U6/CurrState_Sreg0_FFD2_MC.D2_674  (
    .I0(\U1/U6/CurrState_Sreg0_FFD2_MC.D2_PT_0 ),
    .I1(\U1/U6/CurrState_Sreg0_FFD2_MC.D2_PT_1 ),
    .I2(\U1/U6/CurrState_Sreg0_FFD2_MC.D2_PT_2 ),
    .I3(\U1/U6/CurrState_Sreg0_FFD2_MC.D2_PT_3 ),
    .I4(\U1/U6/CurrState_Sreg0_FFD2_MC.D2_PT_4 ),
    .I5(\U1/U6/CurrState_Sreg0_FFD2_MC.D2_PT_5 ),
    .I6(\U1/U6/CurrState_Sreg0_FFD2_MC.D2_PT_6 ),
    .I7(\U1/U6/CurrState_Sreg0_FFD2_MC.D2_PT_7 ),
    .O(\U1/U6/CurrState_Sreg0_FFD2_MC.D2 )
  );
  X_BUF \U1/U5/location_Maddsub__n0000__n0067<0>  (
    .I(\U1/U5/location_Maddsub__n0000__n0067<0>_MC.Q ),
    .O(\U1/U5/location_Maddsub__n0000__n0067 [0])
  );
  X_BUF \U1/U5/location_Maddsub__n0000__n0067<0>_MC.Q_675  (
    .I(\U1/U5/location_Maddsub__n0000__n0067<0>_MC.D ),
    .O(\U1/U5/location_Maddsub__n0000__n0067<0>_MC.Q )
  );
  X_XOR2 \U1/U5/location_Maddsub__n0000__n0067<0>_MC.D_676  (
    .I0(\U1/U5/location_Maddsub__n0000__n0067<0>_MC.D1 ),
    .I1(\U1/U5/location_Maddsub__n0000__n0067<0>_MC.D2 ),
    .O(\U1/U5/location_Maddsub__n0000__n0067<0>_MC.D )
  );
  X_AND2 \U1/U5/location_Maddsub__n0000__n0067<0>_MC.D1_677  (
    .I0(N_PZ_944),
    .I1(N_PZ_944),
    .O(\U1/U5/location_Maddsub__n0000__n0067<0>_MC.D1 )
  );
  X_AND6 \U1/U5/location_Maddsub__n0000__n0067<0>_MC.D2_PT_0_678  (
    .I0(N_PZ_944),
    .I1(\U1/Channel1 [0]),
    .I2(\U1/Channel1 [1]),
    .I3(\U1/Channel1 [2]),
    .I4(\U1/Channel1 [3]),
    .I5(\U1/Channel1 [4]),
    .O(\U1/U5/location_Maddsub__n0000__n0067<0>_MC.D2_PT_0 )
  );
  X_AND6 \U1/U5/location_Maddsub__n0000__n0067<0>_MC.D2_PT_1_679  (
    .I0(\NlwInverterSignal_U1/U5/location_Maddsub__n0000__n0067<0>_MC.D2_PT_1/IN0 ),
    .I1(\NlwInverterSignal_U1/U5/location_Maddsub__n0000__n0067<0>_MC.D2_PT_1/IN1 ),
    .I2(\NlwInverterSignal_U1/U5/location_Maddsub__n0000__n0067<0>_MC.D2_PT_1/IN2 ),
    .I3(\NlwInverterSignal_U1/U5/location_Maddsub__n0000__n0067<0>_MC.D2_PT_1/IN3 ),
    .I4(\NlwInverterSignal_U1/U5/location_Maddsub__n0000__n0067<0>_MC.D2_PT_1/IN4 ),
    .I5(\NlwInverterSignal_U1/U5/location_Maddsub__n0000__n0067<0>_MC.D2_PT_1/IN5 ),
    .O(\U1/U5/location_Maddsub__n0000__n0067<0>_MC.D2_PT_1 )
  );
  X_OR2 \U1/U5/location_Maddsub__n0000__n0067<0>_MC.D2_680  (
    .I0(\U1/U5/location_Maddsub__n0000__n0067<0>_MC.D2_PT_0 ),
    .I1(\U1/U5/location_Maddsub__n0000__n0067<0>_MC.D2_PT_1 ),
    .O(\U1/U5/location_Maddsub__n0000__n0067<0>_MC.D2 )
  );
  X_BUF N_PZ_944_681 (
    .I(\N_PZ_944_MC.Q ),
    .O(N_PZ_944)
  );
  X_BUF \N_PZ_944_MC.Q_682  (
    .I(\N_PZ_944_MC.D ),
    .O(\N_PZ_944_MC.Q )
  );
  X_XOR2 \N_PZ_944_MC.D_683  (
    .I0(\N_PZ_944_MC.D1 ),
    .I1(\N_PZ_944_MC.D2 ),
    .O(\N_PZ_944_MC.D )
  );
  X_AND2 \N_PZ_944_MC.D1_684  (
    .I0(\U1/NET3720 ),
    .I1(\U1/NET3720 ),
    .O(\N_PZ_944_MC.D1 )
  );
  X_AND3 \N_PZ_944_MC.D2_PT_0_685  (
    .I0(\U1/U6/CurrState_Sreg0_FFD3 ),
    .I1(\NlwInverterSignal_N_PZ_944_MC.D2_PT_0/IN1 ),
    .I2(\NlwInverterSignal_N_PZ_944_MC.D2_PT_0/IN2 ),
    .O(\N_PZ_944_MC.D2_PT_0 )
  );
  X_AND3 \N_PZ_944_MC.D2_PT_1_686  (
    .I0(\U1/U6/CurrState_Sreg0_FFD2 ),
    .I1(\NlwInverterSignal_N_PZ_944_MC.D2_PT_1/IN1 ),
    .I2(\NlwInverterSignal_N_PZ_944_MC.D2_PT_1/IN2 ),
    .O(\N_PZ_944_MC.D2_PT_1 )
  );
  X_OR2 \N_PZ_944_MC.D2_687  (
    .I0(\N_PZ_944_MC.D2_PT_0 ),
    .I1(\N_PZ_944_MC.D2_PT_1 ),
    .O(\N_PZ_944_MC.D2 )
  );
  X_BUF \U1/NET3720_688  (
    .I(\U1/NET3720_MC.Q ),
    .O(\U1/NET3720 )
  );
  X_FF \U1/NET3720_MC.REG  (
    .I(\U1/NET3720_MC.D ),
    .CE(Vcc),
    .CLK(\U1/NET3720_MC.REG_tsimcreated_inv_Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\U1/NET3720_MC.Q )
  );
  X_INV \U1/NET3720_MC.REG_tsimcreated_inv_Mclk_II/FCLK_689  (
    .I(\Mclk_II/FCLK ),
    .O(\U1/NET3720_MC.REG_tsimcreated_inv_Mclk_II/FCLK )
  );
  X_XOR2 \U1/NET3720_MC.D_690  (
    .I0(\U1/NET3720_MC.D1 ),
    .I1(\U1/NET3720_MC.D2 ),
    .O(\U1/NET3720_MC.D )
  );
  X_ZERO \U1/NET3720_MC.D1_691  (
    .O(\U1/NET3720_MC.D1 )
  );
  X_AND3 \U1/NET3720_MC.D2_PT_0_692  (
    .I0(\MSPReset_II/UIM ),
    .I1(\AD<7>_II/UIM ),
    .I2(DCORENCCTLw),
    .O(\U1/NET3720_MC.D2_PT_0 )
  );
  X_AND3 \U1/NET3720_MC.D2_PT_1_693  (
    .I0(\MSPReset_II/UIM ),
    .I1(\NlwInverterSignal_U1/NET3720_MC.D2_PT_1/IN1 ),
    .I2(\U1/NET3720 ),
    .O(\U1/NET3720_MC.D2_PT_1 )
  );
  X_OR2 \U1/NET3720_MC.D2_694  (
    .I0(\U1/NET3720_MC.D2_PT_0 ),
    .I1(\U1/NET3720_MC.D2_PT_1 ),
    .O(\U1/NET3720_MC.D2 )
  );
  X_BUF \U1/Channel1<0>  (
    .I(\U1/Channel1<0>_MC.Q ),
    .O(\U1/Channel1 [0])
  );
  X_XOR2 \U1/Channel1<0>_MC_tsimcreated_xor__695  (
    .I0(\U1/Channel1<0>_MC.D ),
    .I1(\U1/Channel1<0>_MC.Q ),
    .O(\U1/Channel1<0>_MC_tsimcreated_xor_ )
  );
  X_FF \U1/Channel1<0>_MC.REG  (
    .I(\U1/Channel1<0>_MC_tsimcreated_xor_ ),
    .CE(Vcc),
    .CLK(\Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\U1/Channel1<0>_MC.Q )
  );
  X_XOR2 \U1/Channel1<0>_MC.D_696  (
    .I0(\U1/Channel1<0>_MC.D1 ),
    .I1(\U1/Channel1<0>_MC.D2 ),
    .O(\U1/Channel1<0>_MC.D )
  );
  X_ZERO \U1/Channel1<0>_MC.D1_697  (
    .O(\U1/Channel1<0>_MC.D1 )
  );
  X_AND2 \U1/Channel1<0>_MC.D2_PT_0_698  (
    .I0(\NlwInverterSignal_U1/Channel1<0>_MC.D2_PT_0/IN0 ),
    .I1(\U1/Channel1 [0]),
    .O(\U1/Channel1<0>_MC.D2_PT_0 )
  );
  X_AND5 \U1/Channel1<0>_MC.D2_PT_1_699  (
    .I0(\MSPReset_II/UIM ),
    .I1(\NlwInverterSignal_U1/Channel1<0>_MC.D2_PT_1/IN1 ),
    .I2(\U1/U6/CurrState_Sreg0_FFD3 ),
    .I3(\NlwInverterSignal_U1/Channel1<0>_MC.D2_PT_1/IN3 ),
    .I4(N_PZ_1092),
    .O(\U1/Channel1<0>_MC.D2_PT_1 )
  );
  X_OR2 \U1/Channel1<0>_MC.D2_700  (
    .I0(\U1/Channel1<0>_MC.D2_PT_0 ),
    .I1(\U1/Channel1<0>_MC.D2_PT_1 ),
    .O(\U1/Channel1<0>_MC.D2 )
  );
  X_BUF N_PZ_1092_701 (
    .I(\N_PZ_1092_MC.Q ),
    .O(N_PZ_1092)
  );
  X_BUF \N_PZ_1092_MC.Q_702  (
    .I(\N_PZ_1092_MC.D ),
    .O(\N_PZ_1092_MC.Q )
  );
  X_XOR2 \N_PZ_1092_MC.D_703  (
    .I0(\N_PZ_1092_MC.D1 ),
    .I1(\N_PZ_1092_MC.D2 ),
    .O(\N_PZ_1092_MC.D )
  );
  X_ZERO \N_PZ_1092_MC.D1_704  (
    .O(\N_PZ_1092_MC.D1 )
  );
  X_AND2 \N_PZ_1092_MC.D2_PT_0_705  (
    .I0(\U1/U6/CurrState_Sreg0_FFD4 ),
    .I1(\NlwInverterSignal_N_PZ_1092_MC.D2_PT_0/IN1 ),
    .O(\N_PZ_1092_MC.D2_PT_0 )
  );
  X_AND2 \N_PZ_1092_MC.D2_PT_1_706  (
    .I0(\NlwInverterSignal_N_PZ_1092_MC.D2_PT_1/IN0 ),
    .I1(\U1/U6/CurrState_Sreg0_FFD1 ),
    .O(\N_PZ_1092_MC.D2_PT_1 )
  );
  X_OR2 \N_PZ_1092_MC.D2_707  (
    .I0(\N_PZ_1092_MC.D2_PT_0 ),
    .I1(\N_PZ_1092_MC.D2_PT_1 ),
    .O(\N_PZ_1092_MC.D2 )
  );
  X_BUF \U1/Channel1<1>  (
    .I(\U1/Channel1<1>_MC.Q ),
    .O(\U1/Channel1 [1])
  );
  X_XOR2 \U1/Channel1<1>_MC_tsimcreated_xor__708  (
    .I0(\U1/Channel1<1>_MC.D ),
    .I1(\U1/Channel1<1>_MC.Q ),
    .O(\U1/Channel1<1>_MC_tsimcreated_xor_ )
  );
  X_FF \U1/Channel1<1>_MC.REG  (
    .I(\U1/Channel1<1>_MC_tsimcreated_xor_ ),
    .CE(Vcc),
    .CLK(\Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\U1/Channel1<1>_MC.Q )
  );
  X_XOR2 \U1/Channel1<1>_MC.D_709  (
    .I0(\U1/Channel1<1>_MC.D1 ),
    .I1(\U1/Channel1<1>_MC.D2 ),
    .O(\U1/Channel1<1>_MC.D )
  );
  X_ZERO \U1/Channel1<1>_MC.D1_710  (
    .O(\U1/Channel1<1>_MC.D1 )
  );
  X_AND2 \U1/Channel1<1>_MC.D2_PT_0_711  (
    .I0(\NlwInverterSignal_U1/Channel1<1>_MC.D2_PT_0/IN0 ),
    .I1(\U1/Channel1 [1]),
    .O(\U1/Channel1<1>_MC.D2_PT_0 )
  );
  X_AND6 \U1/Channel1<1>_MC.D2_PT_1_712  (
    .I0(\MSPReset_II/UIM ),
    .I1(\NlwInverterSignal_U1/Channel1<1>_MC.D2_PT_1/IN1 ),
    .I2(\U1/U6/CurrState_Sreg0_FFD3 ),
    .I3(\NlwInverterSignal_U1/Channel1<1>_MC.D2_PT_1/IN3 ),
    .I4(N_PZ_921),
    .I5(\U1/Channel1 [0]),
    .O(\U1/Channel1<1>_MC.D2_PT_1 )
  );
  X_AND7 \U1/Channel1<1>_MC.D2_PT_2_713  (
    .I0(\MSPReset_II/UIM ),
    .I1(\NlwInverterSignal_U1/Channel1<1>_MC.D2_PT_2/IN1 ),
    .I2(\U1/U6/CurrState_Sreg0_FFD3 ),
    .I3(\NlwInverterSignal_U1/Channel1<1>_MC.D2_PT_2/IN3 ),
    .I4(\NlwInverterSignal_U1/Channel1<1>_MC.D2_PT_2/IN4 ),
    .I5(N_PZ_1092),
    .I6(\NlwInverterSignal_U1/Channel1<1>_MC.D2_PT_2/IN6 ),
    .O(\U1/Channel1<1>_MC.D2_PT_2 )
  );
  X_OR3 \U1/Channel1<1>_MC.D2_714  (
    .I0(\U1/Channel1<1>_MC.D2_PT_0 ),
    .I1(\U1/Channel1<1>_MC.D2_PT_1 ),
    .I2(\U1/Channel1<1>_MC.D2_PT_2 ),
    .O(\U1/Channel1<1>_MC.D2 )
  );
  X_BUF N_PZ_921_715 (
    .I(\N_PZ_921_MC.Q ),
    .O(N_PZ_921)
  );
  X_BUF \N_PZ_921_MC.Q_716  (
    .I(\N_PZ_921_MC.D ),
    .O(\N_PZ_921_MC.Q )
  );
  X_XOR2 \N_PZ_921_MC.D_717  (
    .I0(\N_PZ_921_MC.D1 ),
    .I1(\N_PZ_921_MC.D2 ),
    .O(\N_PZ_921_MC.D )
  );
  X_ZERO \N_PZ_921_MC.D1_718  (
    .O(\N_PZ_921_MC.D1 )
  );
  X_AND3 \N_PZ_921_MC.D2_PT_0_719  (
    .I0(\U1/U6/CurrState_Sreg0_FFD4 ),
    .I1(\NlwInverterSignal_N_PZ_921_MC.D2_PT_0/IN1 ),
    .I2(\NlwInverterSignal_N_PZ_921_MC.D2_PT_0/IN2 ),
    .O(\N_PZ_921_MC.D2_PT_0 )
  );
  X_AND3 \N_PZ_921_MC.D2_PT_1_720  (
    .I0(\NlwInverterSignal_N_PZ_921_MC.D2_PT_1/IN0 ),
    .I1(\U1/U6/CurrState_Sreg0_FFD1 ),
    .I2(\U1/NET3720 ),
    .O(\N_PZ_921_MC.D2_PT_1 )
  );
  X_OR2 \N_PZ_921_MC.D2_721  (
    .I0(\N_PZ_921_MC.D2_PT_0 ),
    .I1(\N_PZ_921_MC.D2_PT_1 ),
    .O(\N_PZ_921_MC.D2 )
  );
  X_BUF \U1/Channel1<2>  (
    .I(\U1/Channel1<2>_MC.Q ),
    .O(\U1/Channel1 [2])
  );
  X_XOR2 \U1/Channel1<2>_MC_tsimcreated_xor__722  (
    .I0(\U1/Channel1<2>_MC.D ),
    .I1(\U1/Channel1<2>_MC.Q ),
    .O(\U1/Channel1<2>_MC_tsimcreated_xor_ )
  );
  X_FF \U1/Channel1<2>_MC.REG  (
    .I(\U1/Channel1<2>_MC_tsimcreated_xor_ ),
    .CE(Vcc),
    .CLK(\Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\U1/Channel1<2>_MC.Q )
  );
  X_XOR2 \U1/Channel1<2>_MC.D_723  (
    .I0(\U1/Channel1<2>_MC.D1 ),
    .I1(\U1/Channel1<2>_MC.D2 ),
    .O(\U1/Channel1<2>_MC.D )
  );
  X_ZERO \U1/Channel1<2>_MC.D1_724  (
    .O(\U1/Channel1<2>_MC.D1 )
  );
  X_AND2 \U1/Channel1<2>_MC.D2_PT_0_725  (
    .I0(\NlwInverterSignal_U1/Channel1<2>_MC.D2_PT_0/IN0 ),
    .I1(\U1/Channel1 [2]),
    .O(\U1/Channel1<2>_MC.D2_PT_0 )
  );
  X_AND7 \U1/Channel1<2>_MC.D2_PT_1_726  (
    .I0(\MSPReset_II/UIM ),
    .I1(\NlwInverterSignal_U1/Channel1<2>_MC.D2_PT_1/IN1 ),
    .I2(\U1/U6/CurrState_Sreg0_FFD3 ),
    .I3(\NlwInverterSignal_U1/Channel1<2>_MC.D2_PT_1/IN3 ),
    .I4(N_PZ_921),
    .I5(\U1/Channel1 [0]),
    .I6(\U1/Channel1 [1]),
    .O(\U1/Channel1<2>_MC.D2_PT_1 )
  );
  X_AND8 \U1/Channel1<2>_MC.D2_PT_2_727  (
    .I0(\MSPReset_II/UIM ),
    .I1(\NlwInverterSignal_U1/Channel1<2>_MC.D2_PT_2/IN1 ),
    .I2(\U1/U6/CurrState_Sreg0_FFD3 ),
    .I3(\NlwInverterSignal_U1/Channel1<2>_MC.D2_PT_2/IN3 ),
    .I4(\NlwInverterSignal_U1/Channel1<2>_MC.D2_PT_2/IN4 ),
    .I5(N_PZ_1092),
    .I6(\NlwInverterSignal_U1/Channel1<2>_MC.D2_PT_2/IN6 ),
    .I7(\NlwInverterSignal_U1/Channel1<2>_MC.D2_PT_2/IN7 ),
    .O(\U1/Channel1<2>_MC.D2_PT_2 )
  );
  X_OR3 \U1/Channel1<2>_MC.D2_728  (
    .I0(\U1/Channel1<2>_MC.D2_PT_0 ),
    .I1(\U1/Channel1<2>_MC.D2_PT_1 ),
    .I2(\U1/Channel1<2>_MC.D2_PT_2 ),
    .O(\U1/Channel1<2>_MC.D2 )
  );
  X_BUF \U1/Channel1<3>  (
    .I(\U1/Channel1<3>_MC.Q ),
    .O(\U1/Channel1 [3])
  );
  X_XOR2 \U1/Channel1<3>_MC_tsimcreated_xor__729  (
    .I0(\U1/Channel1<3>_MC.D ),
    .I1(\U1/Channel1<3>_MC.Q ),
    .O(\U1/Channel1<3>_MC_tsimcreated_xor_ )
  );
  X_FF \U1/Channel1<3>_MC.REG  (
    .I(\U1/Channel1<3>_MC_tsimcreated_xor_ ),
    .CE(Vcc),
    .CLK(\Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\U1/Channel1<3>_MC.Q )
  );
  X_XOR2 \U1/Channel1<3>_MC.D_730  (
    .I0(\U1/Channel1<3>_MC.D1 ),
    .I1(\U1/Channel1<3>_MC.D2 ),
    .O(\U1/Channel1<3>_MC.D )
  );
  X_ZERO \U1/Channel1<3>_MC.D1_731  (
    .O(\U1/Channel1<3>_MC.D1 )
  );
  X_AND2 \U1/Channel1<3>_MC.D2_PT_0_732  (
    .I0(\NlwInverterSignal_U1/Channel1<3>_MC.D2_PT_0/IN0 ),
    .I1(\U1/Channel1 [3]),
    .O(\U1/Channel1<3>_MC.D2_PT_0 )
  );
  X_AND8 \U1/Channel1<3>_MC.D2_PT_1_733  (
    .I0(\MSPReset_II/UIM ),
    .I1(\NlwInverterSignal_U1/Channel1<3>_MC.D2_PT_1/IN1 ),
    .I2(\U1/U6/CurrState_Sreg0_FFD3 ),
    .I3(\NlwInverterSignal_U1/Channel1<3>_MC.D2_PT_1/IN3 ),
    .I4(N_PZ_921),
    .I5(\U1/Channel1 [0]),
    .I6(\U1/Channel1 [1]),
    .I7(\U1/Channel1 [2]),
    .O(\U1/Channel1<3>_MC.D2_PT_1 )
  );
  X_AND16 \U1/Channel1<3>_MC.D2_PT_2_734  (
    .I0(\MSPReset_II/UIM ),
    .I1(\NlwInverterSignal_U1/Channel1<3>_MC.D2_PT_2/IN1 ),
    .I2(\U1/U6/CurrState_Sreg0_FFD3 ),
    .I3(\NlwInverterSignal_U1/Channel1<3>_MC.D2_PT_2/IN3 ),
    .I4(\NlwInverterSignal_U1/Channel1<3>_MC.D2_PT_2/IN4 ),
    .I5(N_PZ_1092),
    .I6(\NlwInverterSignal_U1/Channel1<3>_MC.D2_PT_2/IN6 ),
    .I7(\NlwInverterSignal_U1/Channel1<3>_MC.D2_PT_2/IN7 ),
    .I8(\NlwInverterSignal_U1/Channel1<3>_MC.D2_PT_2/IN8 ),
    .I9(Vcc),
    .I10(Vcc),
    .I11(Vcc),
    .I12(Vcc),
    .I13(Vcc),
    .I14(Vcc),
    .I15(Vcc),
    .O(\U1/Channel1<3>_MC.D2_PT_2 )
  );
  X_OR3 \U1/Channel1<3>_MC.D2_735  (
    .I0(\U1/Channel1<3>_MC.D2_PT_0 ),
    .I1(\U1/Channel1<3>_MC.D2_PT_1 ),
    .I2(\U1/Channel1<3>_MC.D2_PT_2 ),
    .O(\U1/Channel1<3>_MC.D2 )
  );
  X_BUF \U1/Channel1<4>  (
    .I(\U1/Channel1<4>_MC.Q ),
    .O(\U1/Channel1 [4])
  );
  X_XOR2 \U1/Channel1<4>_MC_tsimcreated_xor__736  (
    .I0(\U1/Channel1<4>_MC.D ),
    .I1(\U1/Channel1<4>_MC.Q ),
    .O(\U1/Channel1<4>_MC_tsimcreated_xor_ )
  );
  X_FF \U1/Channel1<4>_MC.REG  (
    .I(\U1/Channel1<4>_MC_tsimcreated_xor_ ),
    .CE(Vcc),
    .CLK(\Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\U1/Channel1<4>_MC.Q )
  );
  X_XOR2 \U1/Channel1<4>_MC.D_737  (
    .I0(\U1/Channel1<4>_MC.D1 ),
    .I1(\U1/Channel1<4>_MC.D2 ),
    .O(\U1/Channel1<4>_MC.D )
  );
  X_ZERO \U1/Channel1<4>_MC.D1_738  (
    .O(\U1/Channel1<4>_MC.D1 )
  );
  X_AND2 \U1/Channel1<4>_MC.D2_PT_0_739  (
    .I0(\NlwInverterSignal_U1/Channel1<4>_MC.D2_PT_0/IN0 ),
    .I1(\U1/Channel1 [4]),
    .O(\U1/Channel1<4>_MC.D2_PT_0 )
  );
  X_AND6 \U1/Channel1<4>_MC.D2_PT_1_740  (
    .I0(\U1/U6/CurrState_Sreg0_FFD3 ),
    .I1(\NlwInverterSignal_U1/Channel1<4>_MC.D2_PT_1/IN1 ),
    .I2(\NlwInverterSignal_U1/Channel1<4>_MC.D2_PT_1/IN2 ),
    .I3(N_PZ_921),
    .I4(\NlwInverterSignal_U1/Channel1<4>_MC.D2_PT_1/IN4 ),
    .I5(\U1/Channel1 [4]),
    .O(\U1/Channel1<4>_MC.D2_PT_1 )
  );
  X_AND6 \U1/Channel1<4>_MC.D2_PT_2_741  (
    .I0(\U1/U6/CurrState_Sreg0_FFD3 ),
    .I1(\NlwInverterSignal_U1/Channel1<4>_MC.D2_PT_2/IN1 ),
    .I2(\NlwInverterSignal_U1/Channel1<4>_MC.D2_PT_2/IN2 ),
    .I3(N_PZ_921),
    .I4(\NlwInverterSignal_U1/Channel1<4>_MC.D2_PT_2/IN4 ),
    .I5(\U1/Channel1 [4]),
    .O(\U1/Channel1<4>_MC.D2_PT_2 )
  );
  X_AND6 \U1/Channel1<4>_MC.D2_PT_3_742  (
    .I0(\U1/U6/CurrState_Sreg0_FFD3 ),
    .I1(\NlwInverterSignal_U1/Channel1<4>_MC.D2_PT_3/IN1 ),
    .I2(\NlwInverterSignal_U1/Channel1<4>_MC.D2_PT_3/IN2 ),
    .I3(N_PZ_921),
    .I4(\NlwInverterSignal_U1/Channel1<4>_MC.D2_PT_3/IN4 ),
    .I5(\U1/Channel1 [4]),
    .O(\U1/Channel1<4>_MC.D2_PT_3 )
  );
  X_AND6 \U1/Channel1<4>_MC.D2_PT_4_743  (
    .I0(\U1/U6/CurrState_Sreg0_FFD3 ),
    .I1(\NlwInverterSignal_U1/Channel1<4>_MC.D2_PT_4/IN1 ),
    .I2(\NlwInverterSignal_U1/Channel1<4>_MC.D2_PT_4/IN2 ),
    .I3(N_PZ_921),
    .I4(\U1/Channel1 [3]),
    .I5(\U1/Channel1 [4]),
    .O(\U1/Channel1<4>_MC.D2_PT_4 )
  );
  X_AND8 \U1/Channel1<4>_MC.D2_PT_5_744  (
    .I0(\MSPReset_II/UIM ),
    .I1(\NlwInverterSignal_U1/Channel1<4>_MC.D2_PT_5/IN1 ),
    .I2(\U1/U6/CurrState_Sreg0_FFD3 ),
    .I3(\NlwInverterSignal_U1/Channel1<4>_MC.D2_PT_5/IN3 ),
    .I4(\U1/U5/location_Maddsub__n0000__n0067 [0]),
    .I5(\NlwInverterSignal_U1/Channel1<4>_MC.D2_PT_5/IN5 ),
    .I6(N_PZ_1092),
    .I7(\NlwInverterSignal_U1/Channel1<4>_MC.D2_PT_5/IN7 ),
    .O(\U1/Channel1<4>_MC.D2_PT_5 )
  );
  X_AND16 \U1/Channel1<4>_MC.D2_PT_6_745  (
    .I0(\U1/U6/CurrState_Sreg0_FFD3 ),
    .I1(\NlwInverterSignal_U1/Channel1<4>_MC.D2_PT_6/IN1 ),
    .I2(\NlwInverterSignal_U1/Channel1<4>_MC.D2_PT_6/IN2 ),
    .I3(N_PZ_1092),
    .I4(\NlwInverterSignal_U1/Channel1<4>_MC.D2_PT_6/IN4 ),
    .I5(\NlwInverterSignal_U1/Channel1<4>_MC.D2_PT_6/IN5 ),
    .I6(\NlwInverterSignal_U1/Channel1<4>_MC.D2_PT_6/IN6 ),
    .I7(\NlwInverterSignal_U1/Channel1<4>_MC.D2_PT_6/IN7 ),
    .I8(\U1/Channel1 [4]),
    .I9(Vcc),
    .I10(Vcc),
    .I11(Vcc),
    .I12(Vcc),
    .I13(Vcc),
    .I14(Vcc),
    .I15(Vcc),
    .O(\U1/Channel1<4>_MC.D2_PT_6 )
  );
  X_AND16 \U1/Channel1<4>_MC.D2_PT_7_746  (
    .I0(\MSPReset_II/UIM ),
    .I1(\NlwInverterSignal_U1/Channel1<4>_MC.D2_PT_7/IN1 ),
    .I2(\U1/U6/CurrState_Sreg0_FFD3 ),
    .I3(\NlwInverterSignal_U1/Channel1<4>_MC.D2_PT_7/IN3 ),
    .I4(\U1/U5/location_Maddsub__n0000__n0067 [0]),
    .I5(N_PZ_1092),
    .I6(\U1/Channel1 [0]),
    .I7(\U1/Channel1 [1]),
    .I8(\U1/Channel1 [2]),
    .I9(\U1/Channel1 [3]),
    .I10(\NlwInverterSignal_U1/Channel1<4>_MC.D2_PT_7/IN10 ),
    .I11(Vcc),
    .I12(Vcc),
    .I13(Vcc),
    .I14(Vcc),
    .I15(Vcc),
    .O(\U1/Channel1<4>_MC.D2_PT_7 )
  );
  X_OR8 \U1/Channel1<4>_MC.D2_747  (
    .I0(\U1/Channel1<4>_MC.D2_PT_0 ),
    .I1(\U1/Channel1<4>_MC.D2_PT_1 ),
    .I2(\U1/Channel1<4>_MC.D2_PT_2 ),
    .I3(\U1/Channel1<4>_MC.D2_PT_3 ),
    .I4(\U1/Channel1<4>_MC.D2_PT_4 ),
    .I5(\U1/Channel1<4>_MC.D2_PT_5 ),
    .I6(\U1/Channel1<4>_MC.D2_PT_6 ),
    .I7(\U1/Channel1<4>_MC.D2_PT_7 ),
    .O(\U1/Channel1<4>_MC.D2 )
  );
  X_BUF DCOR1CNTLOWr_748 (
    .I(\DCOR1CNTLOWr_MC.Q ),
    .O(DCOR1CNTLOWr)
  );
  X_BUF \DCOR1CNTLOWr_MC.Q_749  (
    .I(\DCOR1CNTLOWr_MC.D ),
    .O(\DCOR1CNTLOWr_MC.Q )
  );
  X_XOR2 \DCOR1CNTLOWr_MC.D_750  (
    .I0(\DCOR1CNTLOWr_MC.D1 ),
    .I1(\DCOR1CNTLOWr_MC.D2 ),
    .O(\DCOR1CNTLOWr_MC.D )
  );
  X_AND16 \DCOR1CNTLOWr_MC.D1_751  (
    .I0(\WR_II/UIM ),
    .I1(\NlwInverterSignal_DCOR1CNTLOWr_MC.D1/IN1 ),
    .I2(\NlwInverterSignal_DCOR1CNTLOWr_MC.D1/IN2 ),
    .I3(\NlwInverterSignal_DCOR1CNTLOWr_MC.D1/IN3 ),
    .I4(\NlwInverterSignal_DCOR1CNTLOWr_MC.D1/IN4 ),
    .I5(\NlwInverterSignal_DCOR1CNTLOWr_MC.D1/IN5 ),
    .I6(\NlwInverterSignal_DCOR1CNTLOWr_MC.D1/IN6 ),
    .I7(\NlwInverterSignal_DCOR1CNTLOWr_MC.D1/IN7 ),
    .I8(U2_ADDR_reg[1]),
    .I9(U2_ADDR_reg[2]),
    .I10(Vcc),
    .I11(Vcc),
    .I12(Vcc),
    .I13(Vcc),
    .I14(Vcc),
    .I15(Vcc),
    .O(\DCOR1CNTLOWr_MC.D1 )
  );
  X_ZERO \DCOR1CNTLOWr_MC.D2_752  (
    .O(\DCOR1CNTLOWr_MC.D2 )
  );
  X_BUF \U1/U3/holdingreg0<13>  (
    .I(\U1/U3/holdingreg0<13>_MC.Q ),
    .O(\U1/U3/holdingreg0 [13])
  );
  X_FF \U1/U3/holdingreg0<13>_MC.REG  (
    .I(\U1/U3/holdingreg0<13>_MC.D ),
    .CE(Vcc),
    .CLK(\U1/U3/holdingreg0<13>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\U1/U3/holdingreg0<13>_MC.Q )
  );
  X_INV \U1/U3/holdingreg0<13>_MC.REG_tsimcreated_inv_Mclk_II/FCLK_753  (
    .I(\Mclk_II/FCLK ),
    .O(\U1/U3/holdingreg0<13>_MC.REG_tsimcreated_inv_Mclk_II/FCLK )
  );
  X_XOR2 \U1/U3/holdingreg0<13>_MC.D_754  (
    .I0(\U1/U3/holdingreg0<13>_MC.D1 ),
    .I1(\U1/U3/holdingreg0<13>_MC.D2 ),
    .O(\U1/U3/holdingreg0<13>_MC.D )
  );
  X_ZERO \U1/U3/holdingreg0<13>_MC.D1_755  (
    .O(\U1/U3/holdingreg0<13>_MC.D1 )
  );
  X_AND2 \U1/U3/holdingreg0<13>_MC.D2_PT_0_756  (
    .I0(N_PZ_938),
    .I1(\U1/U3/holdingreg0 [13]),
    .O(\U1/U3/holdingreg0<13>_MC.D2_PT_0 )
  );
  X_AND4 \U1/U3/holdingreg0<13>_MC.D2_PT_1_757  (
    .I0(\MSPReset_II/UIM ),
    .I1(\NlwInverterSignal_U1/U3/holdingreg0<13>_MC.D2_PT_1/IN1 ),
    .I2(U2_ASedge),
    .I3(\U1/Channel0 [13]),
    .O(\U1/U3/holdingreg0<13>_MC.D2_PT_1 )
  );
  X_OR2 \U1/U3/holdingreg0<13>_MC.D2_758  (
    .I0(\U1/U3/holdingreg0<13>_MC.D2_PT_0 ),
    .I1(\U1/U3/holdingreg0<13>_MC.D2_PT_1 ),
    .O(\U1/U3/holdingreg0<13>_MC.D2 )
  );
  X_BUF \U1/Channel0<13>  (
    .I(\U1/Channel0<13>_MC.Q ),
    .O(\U1/Channel0 [13])
  );
  X_XOR2 \U1/Channel0<13>_MC_tsimcreated_xor__759  (
    .I0(\U1/Channel0<13>_MC.D ),
    .I1(\U1/Channel0<13>_MC.Q ),
    .O(\U1/Channel0<13>_MC_tsimcreated_xor_ )
  );
  X_FF \U1/Channel0<13>_MC.REG  (
    .I(\U1/Channel0<13>_MC_tsimcreated_xor_ ),
    .CE(Vcc),
    .CLK(\Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\U1/Channel0<13>_MC.Q )
  );
  X_XOR2 \U1/Channel0<13>_MC.D_760  (
    .I0(\U1/Channel0<13>_MC.D1 ),
    .I1(\U1/Channel0<13>_MC.D2 ),
    .O(\U1/Channel0<13>_MC.D )
  );
  X_ZERO \U1/Channel0<13>_MC.D1_761  (
    .O(\U1/Channel0<13>_MC.D1 )
  );
  X_AND2 \U1/Channel0<13>_MC.D2_PT_0_762  (
    .I0(\NlwInverterSignal_U1/Channel0<13>_MC.D2_PT_0/IN0 ),
    .I1(\U1/Channel0 [13]),
    .O(\U1/Channel0<13>_MC.D2_PT_0 )
  );
  X_AND6 \U1/Channel0<13>_MC.D2_PT_1_763  (
    .I0(N_PZ_964),
    .I1(\NlwInverterSignal_U1/Channel0<13>_MC.D2_PT_1/IN1 ),
    .I2(\NlwInverterSignal_U1/Channel0<13>_MC.D2_PT_1/IN2 ),
    .I3(\U1/U2/location_Maddsub__n0000__n0075 [0]),
    .I4(\NlwInverterSignal_U1/Channel0<13>_MC.D2_PT_1/IN4 ),
    .I5(\NlwInverterSignal_U1/Channel0<13>_MC.D2_PT_1/IN5 ),
    .O(\U1/Channel0<13>_MC.D2_PT_1 )
  );
  X_AND6 \U1/Channel0<13>_MC.D2_PT_2_764  (
    .I0(N_PZ_968),
    .I1(\U1/Channel0 [10]),
    .I2(\U1/Channel0 [9]),
    .I3(\NlwInverterSignal_U1/Channel0<13>_MC.D2_PT_2/IN3 ),
    .I4(\U1/Channel0 [11]),
    .I5(\U1/Channel0 [12]),
    .O(\U1/Channel0<13>_MC.D2_PT_2 )
  );
  X_OR3 \U1/Channel0<13>_MC.D2_765  (
    .I0(\U1/Channel0<13>_MC.D2_PT_0 ),
    .I1(\U1/Channel0<13>_MC.D2_PT_1 ),
    .I2(\U1/Channel0<13>_MC.D2_PT_2 ),
    .O(\U1/Channel0<13>_MC.D2 )
  );
  X_BUF \U1/Channel0<10>  (
    .I(\U1/Channel0<10>_MC.Q ),
    .O(\U1/Channel0 [10])
  );
  X_XOR2 \U1/Channel0<10>_MC_tsimcreated_xor__766  (
    .I0(\U1/Channel0<10>_MC.D ),
    .I1(\U1/Channel0<10>_MC.Q ),
    .O(\U1/Channel0<10>_MC_tsimcreated_xor_ )
  );
  X_FF \U1/Channel0<10>_MC.REG  (
    .I(\U1/Channel0<10>_MC_tsimcreated_xor_ ),
    .CE(Vcc),
    .CLK(\Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\U1/Channel0<10>_MC.Q )
  );
  X_XOR2 \U1/Channel0<10>_MC.D_767  (
    .I0(\U1/Channel0<10>_MC.D1 ),
    .I1(\U1/Channel0<10>_MC.D2 ),
    .O(\U1/Channel0<10>_MC.D )
  );
  X_ZERO \U1/Channel0<10>_MC.D1_768  (
    .O(\U1/Channel0<10>_MC.D1 )
  );
  X_AND2 \U1/Channel0<10>_MC.D2_PT_0_769  (
    .I0(\NlwInverterSignal_U1/Channel0<10>_MC.D2_PT_0/IN0 ),
    .I1(\U1/Channel0 [10]),
    .O(\U1/Channel0<10>_MC.D2_PT_0 )
  );
  X_AND3 \U1/Channel0<10>_MC.D2_PT_1_770  (
    .I0(N_PZ_964),
    .I1(\NlwInverterSignal_U1/Channel0<10>_MC.D2_PT_1/IN1 ),
    .I2(\U1/U2/location_Maddsub__n0000__n0075 [0]),
    .O(\U1/Channel0<10>_MC.D2_PT_1 )
  );
  X_AND3 \U1/Channel0<10>_MC.D2_PT_2_771  (
    .I0(N_PZ_968),
    .I1(\U1/Channel0 [9]),
    .I2(\NlwInverterSignal_U1/Channel0<10>_MC.D2_PT_2/IN2 ),
    .O(\U1/Channel0<10>_MC.D2_PT_2 )
  );
  X_OR3 \U1/Channel0<10>_MC.D2_772  (
    .I0(\U1/Channel0<10>_MC.D2_PT_0 ),
    .I1(\U1/Channel0<10>_MC.D2_PT_1 ),
    .I2(\U1/Channel0<10>_MC.D2_PT_2 ),
    .O(\U1/Channel0<10>_MC.D2 )
  );
  X_BUF \U1/Channel0<9>  (
    .I(\U1/Channel0<9>_MC.Q ),
    .O(\U1/Channel0 [9])
  );
  X_XOR2 \U1/Channel0<9>_MC_tsimcreated_xor__773  (
    .I0(\U1/Channel0<9>_MC.D ),
    .I1(\U1/Channel0<9>_MC.Q ),
    .O(\U1/Channel0<9>_MC_tsimcreated_xor_ )
  );
  X_FF \U1/Channel0<9>_MC.REG  (
    .I(\U1/Channel0<9>_MC_tsimcreated_xor_ ),
    .CE(Vcc),
    .CLK(\Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\U1/Channel0<9>_MC.Q )
  );
  X_XOR2 \U1/Channel0<9>_MC.D_774  (
    .I0(\U1/Channel0<9>_MC.D1 ),
    .I1(\U1/Channel0<9>_MC.D2 ),
    .O(\U1/Channel0<9>_MC.D )
  );
  X_ZERO \U1/Channel0<9>_MC.D1_775  (
    .O(\U1/Channel0<9>_MC.D1 )
  );
  X_AND2 \U1/Channel0<9>_MC.D2_PT_0_776  (
    .I0(\NlwInverterSignal_U1/Channel0<9>_MC.D2_PT_0/IN0 ),
    .I1(\U1/Channel0 [9]),
    .O(\U1/Channel0<9>_MC.D2_PT_0 )
  );
  X_AND2 \U1/Channel0<9>_MC.D2_PT_1_777  (
    .I0(N_PZ_964),
    .I1(\U1/U2/location_Maddsub__n0000__n0075 [0]),
    .O(\U1/Channel0<9>_MC.D2_PT_1 )
  );
  X_AND2 \U1/Channel0<9>_MC.D2_PT_2_778  (
    .I0(N_PZ_968),
    .I1(\NlwInverterSignal_U1/Channel0<9>_MC.D2_PT_2/IN1 ),
    .O(\U1/Channel0<9>_MC.D2_PT_2 )
  );
  X_OR3 \U1/Channel0<9>_MC.D2_779  (
    .I0(\U1/Channel0<9>_MC.D2_PT_0 ),
    .I1(\U1/Channel0<9>_MC.D2_PT_1 ),
    .I2(\U1/Channel0<9>_MC.D2_PT_2 ),
    .O(\U1/Channel0<9>_MC.D2 )
  );
  X_BUF \U1/U2/location_Maddsub__n0000__n0075<0>  (
    .I(\U1/U2/location_Maddsub__n0000__n0075<0>_MC.Q ),
    .O(\U1/U2/location_Maddsub__n0000__n0075 [0])
  );
  X_BUF \U1/U2/location_Maddsub__n0000__n0075<0>_MC.Q_780  (
    .I(\U1/U2/location_Maddsub__n0000__n0075<0>_MC.D ),
    .O(\U1/U2/location_Maddsub__n0000__n0075<0>_MC.Q )
  );
  X_XOR2 \U1/U2/location_Maddsub__n0000__n0075<0>_MC.D_781  (
    .I0(\U1/U2/location_Maddsub__n0000__n0075<0>_MC.D1 ),
    .I1(\U1/U2/location_Maddsub__n0000__n0075<0>_MC.D2 ),
    .O(\U1/U2/location_Maddsub__n0000__n0075<0>_MC.D )
  );
  X_AND2 \U1/U2/location_Maddsub__n0000__n0075<0>_MC.D1_782  (
    .I0(N_PZ_943),
    .I1(N_PZ_943),
    .O(\U1/U2/location_Maddsub__n0000__n0075<0>_MC.D1 )
  );
  X_AND6 \U1/U2/location_Maddsub__n0000__n0075<0>_MC.D2_PT_0_783  (
    .I0(\U1/Channel0 [5]),
    .I1(\NlwInverterSignal_U1/U2/location_Maddsub__n0000__n0075<0>_MC.D2_PT_0/IN1 ),
    .I2(N_PZ_943),
    .I3(\U1/Channel0 [6]),
    .I4(\U1/Channel0 [7]),
    .I5(\U1/Channel0 [8]),
    .O(\U1/U2/location_Maddsub__n0000__n0075<0>_MC.D2_PT_0 )
  );
  X_AND6 \U1/U2/location_Maddsub__n0000__n0075<0>_MC.D2_PT_1_784  (
    .I0(\NlwInverterSignal_U1/U2/location_Maddsub__n0000__n0075<0>_MC.D2_PT_1/IN0 ),
    .I1(\U1/U2/location_Maddsub__n0000__n0067 [0]),
    .I2(\NlwInverterSignal_U1/U2/location_Maddsub__n0000__n0075<0>_MC.D2_PT_1/IN2 ),
    .I3(\NlwInverterSignal_U1/U2/location_Maddsub__n0000__n0075<0>_MC.D2_PT_1/IN3 ),
    .I4(\NlwInverterSignal_U1/U2/location_Maddsub__n0000__n0075<0>_MC.D2_PT_1/IN4 ),
    .I5(\NlwInverterSignal_U1/U2/location_Maddsub__n0000__n0075<0>_MC.D2_PT_1/IN5 ),
    .O(\U1/U2/location_Maddsub__n0000__n0075<0>_MC.D2_PT_1 )
  );
  X_OR2 \U1/U2/location_Maddsub__n0000__n0075<0>_MC.D2_785  (
    .I0(\U1/U2/location_Maddsub__n0000__n0075<0>_MC.D2_PT_0 ),
    .I1(\U1/U2/location_Maddsub__n0000__n0075<0>_MC.D2_PT_1 ),
    .O(\U1/U2/location_Maddsub__n0000__n0075<0>_MC.D2 )
  );
  X_BUF \U1/Channel0<6>  (
    .I(\U1/Channel0<6>_MC.Q ),
    .O(\U1/Channel0 [6])
  );
  X_XOR2 \U1/Channel0<6>_MC_tsimcreated_xor__786  (
    .I0(\U1/Channel0<6>_MC.D ),
    .I1(\U1/Channel0<6>_MC.Q ),
    .O(\U1/Channel0<6>_MC_tsimcreated_xor_ )
  );
  X_FF \U1/Channel0<6>_MC.REG  (
    .I(\U1/Channel0<6>_MC_tsimcreated_xor_ ),
    .CE(Vcc),
    .CLK(\Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\U1/Channel0<6>_MC.Q )
  );
  X_XOR2 \U1/Channel0<6>_MC.D_787  (
    .I0(\U1/Channel0<6>_MC.D1 ),
    .I1(\U1/Channel0<6>_MC.D2 ),
    .O(\U1/Channel0<6>_MC.D )
  );
  X_ZERO \U1/Channel0<6>_MC.D1_788  (
    .O(\U1/Channel0<6>_MC.D1 )
  );
  X_AND2 \U1/Channel0<6>_MC.D2_PT_0_789  (
    .I0(\NlwInverterSignal_U1/Channel0<6>_MC.D2_PT_0/IN0 ),
    .I1(\U1/Channel0 [6]),
    .O(\U1/Channel0<6>_MC.D2_PT_0 )
  );
  X_AND3 \U1/Channel0<6>_MC.D2_PT_1_790  (
    .I0(\U1/Channel0 [5]),
    .I1(\NlwInverterSignal_U1/Channel0<6>_MC.D2_PT_1/IN1 ),
    .I2(N_PZ_968),
    .O(\U1/Channel0<6>_MC.D2_PT_1 )
  );
  X_AND3 \U1/Channel0<6>_MC.D2_PT_2_791  (
    .I0(\NlwInverterSignal_U1/Channel0<6>_MC.D2_PT_2/IN0 ),
    .I1(\U1/U2/location_Maddsub__n0000__n0067 [0]),
    .I2(N_PZ_964),
    .O(\U1/Channel0<6>_MC.D2_PT_2 )
  );
  X_OR3 \U1/Channel0<6>_MC.D2_792  (
    .I0(\U1/Channel0<6>_MC.D2_PT_0 ),
    .I1(\U1/Channel0<6>_MC.D2_PT_1 ),
    .I2(\U1/Channel0<6>_MC.D2_PT_2 ),
    .O(\U1/Channel0<6>_MC.D2 )
  );
  X_BUF \U1/Channel0<7>  (
    .I(\U1/Channel0<7>_MC.Q ),
    .O(\U1/Channel0 [7])
  );
  X_XOR2 \U1/Channel0<7>_MC_tsimcreated_xor__793  (
    .I0(\U1/Channel0<7>_MC.D ),
    .I1(\U1/Channel0<7>_MC.Q ),
    .O(\U1/Channel0<7>_MC_tsimcreated_xor_ )
  );
  X_FF \U1/Channel0<7>_MC.REG  (
    .I(\U1/Channel0<7>_MC_tsimcreated_xor_ ),
    .CE(Vcc),
    .CLK(\Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\U1/Channel0<7>_MC.Q )
  );
  X_XOR2 \U1/Channel0<7>_MC.D_794  (
    .I0(\U1/Channel0<7>_MC.D1 ),
    .I1(\U1/Channel0<7>_MC.D2 ),
    .O(\U1/Channel0<7>_MC.D )
  );
  X_ZERO \U1/Channel0<7>_MC.D1_795  (
    .O(\U1/Channel0<7>_MC.D1 )
  );
  X_AND2 \U1/Channel0<7>_MC.D2_PT_0_796  (
    .I0(\NlwInverterSignal_U1/Channel0<7>_MC.D2_PT_0/IN0 ),
    .I1(\U1/Channel0 [7]),
    .O(\U1/Channel0<7>_MC.D2_PT_0 )
  );
  X_AND4 \U1/Channel0<7>_MC.D2_PT_1_797  (
    .I0(\U1/Channel0 [5]),
    .I1(\NlwInverterSignal_U1/Channel0<7>_MC.D2_PT_1/IN1 ),
    .I2(N_PZ_968),
    .I3(\U1/Channel0 [6]),
    .O(\U1/Channel0<7>_MC.D2_PT_1 )
  );
  X_AND4 \U1/Channel0<7>_MC.D2_PT_2_798  (
    .I0(\NlwInverterSignal_U1/Channel0<7>_MC.D2_PT_2/IN0 ),
    .I1(\U1/U2/location_Maddsub__n0000__n0067 [0]),
    .I2(N_PZ_964),
    .I3(\NlwInverterSignal_U1/Channel0<7>_MC.D2_PT_2/IN3 ),
    .O(\U1/Channel0<7>_MC.D2_PT_2 )
  );
  X_OR3 \U1/Channel0<7>_MC.D2_799  (
    .I0(\U1/Channel0<7>_MC.D2_PT_0 ),
    .I1(\U1/Channel0<7>_MC.D2_PT_1 ),
    .I2(\U1/Channel0<7>_MC.D2_PT_2 ),
    .O(\U1/Channel0<7>_MC.D2 )
  );
  X_BUF \U1/Channel0<8>  (
    .I(\U1/Channel0<8>_MC.Q ),
    .O(\U1/Channel0 [8])
  );
  X_XOR2 \U1/Channel0<8>_MC_tsimcreated_xor__800  (
    .I0(\U1/Channel0<8>_MC.D ),
    .I1(\U1/Channel0<8>_MC.Q ),
    .O(\U1/Channel0<8>_MC_tsimcreated_xor_ )
  );
  X_FF \U1/Channel0<8>_MC.REG  (
    .I(\U1/Channel0<8>_MC_tsimcreated_xor_ ),
    .CE(Vcc),
    .CLK(\Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\U1/Channel0<8>_MC.Q )
  );
  X_XOR2 \U1/Channel0<8>_MC.D_801  (
    .I0(\U1/Channel0<8>_MC.D1 ),
    .I1(\U1/Channel0<8>_MC.D2 ),
    .O(\U1/Channel0<8>_MC.D )
  );
  X_AND3 \U1/Channel0<8>_MC.D1_802  (
    .I0(N_PZ_968),
    .I1(\NlwInverterSignal_U1/Channel0<8>_MC.D1/IN1 ),
    .I2(\U1/Channel0 [8]),
    .O(\U1/Channel0<8>_MC.D1 )
  );
  X_AND3 \U1/Channel0<8>_MC.D2_PT_0_803  (
    .I0(\NlwInverterSignal_U1/Channel0<8>_MC.D2_PT_0/IN0 ),
    .I1(\NlwInverterSignal_U1/Channel0<8>_MC.D2_PT_0/IN1 ),
    .I2(\U1/Channel0 [8]),
    .O(\U1/Channel0<8>_MC.D2_PT_0 )
  );
  X_AND3 \U1/Channel0<8>_MC.D2_PT_1_804  (
    .I0(\NlwInverterSignal_U1/Channel0<8>_MC.D2_PT_1/IN0 ),
    .I1(\U1/U2/location_Maddsub__n0000__n0075 [0]),
    .I2(\U1/Channel0 [8]),
    .O(\U1/Channel0<8>_MC.D2_PT_1 )
  );
  X_AND3 \U1/Channel0<8>_MC.D2_PT_2_805  (
    .I0(N_PZ_964),
    .I1(\U1/U2/location_Maddsub__n0000__n0075 [0]),
    .I2(\NlwInverterSignal_U1/Channel0<8>_MC.D2_PT_2/IN2 ),
    .O(\U1/Channel0<8>_MC.D2_PT_2 )
  );
  X_AND7 \U1/Channel0<8>_MC.D2_PT_3_806  (
    .I0(\U1/Channel0 [5]),
    .I1(\NlwInverterSignal_U1/Channel0<8>_MC.D2_PT_3/IN1 ),
    .I2(N_PZ_968),
    .I3(\U1/U2/location_Maddsub__n0000__n0075 [0]),
    .I4(\U1/Channel0 [6]),
    .I5(\U1/Channel0 [7]),
    .I6(\NlwInverterSignal_U1/Channel0<8>_MC.D2_PT_3/IN6 ),
    .O(\U1/Channel0<8>_MC.D2_PT_3 )
  );
  X_AND8 \U1/Channel0<8>_MC.D2_PT_4_807  (
    .I0(\NlwInverterSignal_U1/Channel0<8>_MC.D2_PT_4/IN0 ),
    .I1(\U1/U2/location_Maddsub__n0000__n0067 [0]),
    .I2(N_PZ_964),
    .I3(\NlwInverterSignal_U1/Channel0<8>_MC.D2_PT_4/IN3 ),
    .I4(\NlwInverterSignal_U1/Channel0<8>_MC.D2_PT_4/IN4 ),
    .I5(\NlwInverterSignal_U1/Channel0<8>_MC.D2_PT_4/IN5 ),
    .I6(\NlwInverterSignal_U1/Channel0<8>_MC.D2_PT_4/IN6 ),
    .I7(\U1/Channel0 [8]),
    .O(\U1/Channel0<8>_MC.D2_PT_4 )
  );
  X_AND16 \U1/Channel0<8>_MC.D2_PT_5_808  (
    .I0(\MSPReset_II/UIM ),
    .I1(\U1/Channel0 [5]),
    .I2(\NlwInverterSignal_U1/Channel0<8>_MC.D2_PT_5/IN2 ),
    .I3(N_PZ_968),
    .I4(\NlwInverterSignal_U1/Channel0<8>_MC.D2_PT_5/IN4 ),
    .I5(\NlwInverterSignal_U1/Channel0<8>_MC.D2_PT_5/IN5 ),
    .I6(\U1/Channel0 [6]),
    .I7(\NlwInverterSignal_U1/Channel0<8>_MC.D2_PT_5/IN7 ),
    .I8(\U1/Channel0 [8]),
    .I9(Vcc),
    .I10(Vcc),
    .I11(Vcc),
    .I12(Vcc),
    .I13(Vcc),
    .I14(Vcc),
    .I15(Vcc),
    .O(\U1/Channel0<8>_MC.D2_PT_5 )
  );
  X_OR6 \U1/Channel0<8>_MC.D2_809  (
    .I0(\U1/Channel0<8>_MC.D2_PT_0 ),
    .I1(\U1/Channel0<8>_MC.D2_PT_1 ),
    .I2(\U1/Channel0<8>_MC.D2_PT_2 ),
    .I3(\U1/Channel0<8>_MC.D2_PT_3 ),
    .I4(\U1/Channel0<8>_MC.D2_PT_4 ),
    .I5(\U1/Channel0<8>_MC.D2_PT_5 ),
    .O(\U1/Channel0<8>_MC.D2 )
  );
  X_BUF \U1/Channel0<11>  (
    .I(\U1/Channel0<11>_MC.Q ),
    .O(\U1/Channel0 [11])
  );
  X_XOR2 \U1/Channel0<11>_MC_tsimcreated_xor__810  (
    .I0(\U1/Channel0<11>_MC.D ),
    .I1(\U1/Channel0<11>_MC.Q ),
    .O(\U1/Channel0<11>_MC_tsimcreated_xor_ )
  );
  X_FF \U1/Channel0<11>_MC.REG  (
    .I(\U1/Channel0<11>_MC_tsimcreated_xor_ ),
    .CE(Vcc),
    .CLK(\Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\U1/Channel0<11>_MC.Q )
  );
  X_XOR2 \U1/Channel0<11>_MC.D_811  (
    .I0(\U1/Channel0<11>_MC.D1 ),
    .I1(\U1/Channel0<11>_MC.D2 ),
    .O(\U1/Channel0<11>_MC.D )
  );
  X_ZERO \U1/Channel0<11>_MC.D1_812  (
    .O(\U1/Channel0<11>_MC.D1 )
  );
  X_AND2 \U1/Channel0<11>_MC.D2_PT_0_813  (
    .I0(\NlwInverterSignal_U1/Channel0<11>_MC.D2_PT_0/IN0 ),
    .I1(\U1/Channel0 [11]),
    .O(\U1/Channel0<11>_MC.D2_PT_0 )
  );
  X_AND4 \U1/Channel0<11>_MC.D2_PT_1_814  (
    .I0(N_PZ_964),
    .I1(\NlwInverterSignal_U1/Channel0<11>_MC.D2_PT_1/IN1 ),
    .I2(\NlwInverterSignal_U1/Channel0<11>_MC.D2_PT_1/IN2 ),
    .I3(\U1/U2/location_Maddsub__n0000__n0075 [0]),
    .O(\U1/Channel0<11>_MC.D2_PT_1 )
  );
  X_AND4 \U1/Channel0<11>_MC.D2_PT_2_815  (
    .I0(N_PZ_968),
    .I1(\U1/Channel0 [10]),
    .I2(\U1/Channel0 [9]),
    .I3(\NlwInverterSignal_U1/Channel0<11>_MC.D2_PT_2/IN3 ),
    .O(\U1/Channel0<11>_MC.D2_PT_2 )
  );
  X_OR3 \U1/Channel0<11>_MC.D2_816  (
    .I0(\U1/Channel0<11>_MC.D2_PT_0 ),
    .I1(\U1/Channel0<11>_MC.D2_PT_1 ),
    .I2(\U1/Channel0<11>_MC.D2_PT_2 ),
    .O(\U1/Channel0<11>_MC.D2 )
  );
  X_BUF \U1/Channel0<12>  (
    .I(\U1/Channel0<12>_MC.Q ),
    .O(\U1/Channel0 [12])
  );
  X_XOR2 \U1/Channel0<12>_MC_tsimcreated_xor__817  (
    .I0(\U1/Channel0<12>_MC.D ),
    .I1(\U1/Channel0<12>_MC.Q ),
    .O(\U1/Channel0<12>_MC_tsimcreated_xor_ )
  );
  X_FF \U1/Channel0<12>_MC.REG  (
    .I(\U1/Channel0<12>_MC_tsimcreated_xor_ ),
    .CE(Vcc),
    .CLK(\Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\U1/Channel0<12>_MC.Q )
  );
  X_XOR2 \U1/Channel0<12>_MC.D_818  (
    .I0(\U1/Channel0<12>_MC.D1 ),
    .I1(\U1/Channel0<12>_MC.D2 ),
    .O(\U1/Channel0<12>_MC.D )
  );
  X_ZERO \U1/Channel0<12>_MC.D1_819  (
    .O(\U1/Channel0<12>_MC.D1 )
  );
  X_AND2 \U1/Channel0<12>_MC.D2_PT_0_820  (
    .I0(\NlwInverterSignal_U1/Channel0<12>_MC.D2_PT_0/IN0 ),
    .I1(\U1/Channel0 [12]),
    .O(\U1/Channel0<12>_MC.D2_PT_0 )
  );
  X_AND5 \U1/Channel0<12>_MC.D2_PT_1_821  (
    .I0(N_PZ_964),
    .I1(\NlwInverterSignal_U1/Channel0<12>_MC.D2_PT_1/IN1 ),
    .I2(\NlwInverterSignal_U1/Channel0<12>_MC.D2_PT_1/IN2 ),
    .I3(\U1/U2/location_Maddsub__n0000__n0075 [0]),
    .I4(\NlwInverterSignal_U1/Channel0<12>_MC.D2_PT_1/IN4 ),
    .O(\U1/Channel0<12>_MC.D2_PT_1 )
  );
  X_AND5 \U1/Channel0<12>_MC.D2_PT_2_822  (
    .I0(N_PZ_968),
    .I1(\U1/Channel0 [10]),
    .I2(\U1/Channel0 [9]),
    .I3(\NlwInverterSignal_U1/Channel0<12>_MC.D2_PT_2/IN3 ),
    .I4(\U1/Channel0 [11]),
    .O(\U1/Channel0<12>_MC.D2_PT_2 )
  );
  X_OR3 \U1/Channel0<12>_MC.D2_823  (
    .I0(\U1/Channel0<12>_MC.D2_PT_0 ),
    .I1(\U1/Channel0<12>_MC.D2_PT_1 ),
    .I2(\U1/Channel0<12>_MC.D2_PT_2 ),
    .O(\U1/Channel0<12>_MC.D2 )
  );
  X_BUF DCOR0CNTHIGHr_824 (
    .I(\DCOR0CNTHIGHr_MC.Q ),
    .O(DCOR0CNTHIGHr)
  );
  X_BUF \DCOR0CNTHIGHr_MC.Q_825  (
    .I(\DCOR0CNTHIGHr_MC.D ),
    .O(\DCOR0CNTHIGHr_MC.Q )
  );
  X_XOR2 \DCOR0CNTHIGHr_MC.D_826  (
    .I0(\DCOR0CNTHIGHr_MC.D1 ),
    .I1(\DCOR0CNTHIGHr_MC.D2 ),
    .O(\DCOR0CNTHIGHr_MC.D )
  );
  X_AND16 \DCOR0CNTHIGHr_MC.D1_827  (
    .I0(\WR_II/UIM ),
    .I1(\NlwInverterSignal_DCOR0CNTHIGHr_MC.D1/IN1 ),
    .I2(U2_ADDR_reg[0]),
    .I3(\NlwInverterSignal_DCOR0CNTHIGHr_MC.D1/IN3 ),
    .I4(\NlwInverterSignal_DCOR0CNTHIGHr_MC.D1/IN4 ),
    .I5(\NlwInverterSignal_DCOR0CNTHIGHr_MC.D1/IN5 ),
    .I6(\NlwInverterSignal_DCOR0CNTHIGHr_MC.D1/IN6 ),
    .I7(\NlwInverterSignal_DCOR0CNTHIGHr_MC.D1/IN7 ),
    .I8(\NlwInverterSignal_DCOR0CNTHIGHr_MC.D1/IN8 ),
    .I9(U2_ADDR_reg[2]),
    .I10(Vcc),
    .I11(Vcc),
    .I12(Vcc),
    .I13(Vcc),
    .I14(Vcc),
    .I15(Vcc),
    .O(\DCOR0CNTHIGHr_MC.D1 )
  );
  X_ZERO \DCOR0CNTHIGHr_MC.D2_828  (
    .O(\DCOR0CNTHIGHr_MC.D2 )
  );
  X_BUF \U1/U3/holdingreg1<13>  (
    .I(\U1/U3/holdingreg1<13>_MC.Q ),
    .O(\U1/U3/holdingreg1 [13])
  );
  X_FF \U1/U3/holdingreg1<13>_MC.REG  (
    .I(\U1/U3/holdingreg1<13>_MC.D ),
    .CE(Vcc),
    .CLK(\U1/U3/holdingreg1<13>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\U1/U3/holdingreg1<13>_MC.Q )
  );
  X_INV \U1/U3/holdingreg1<13>_MC.REG_tsimcreated_inv_Mclk_II/FCLK_829  (
    .I(\Mclk_II/FCLK ),
    .O(\U1/U3/holdingreg1<13>_MC.REG_tsimcreated_inv_Mclk_II/FCLK )
  );
  X_XOR2 \U1/U3/holdingreg1<13>_MC.D_830  (
    .I0(\U1/U3/holdingreg1<13>_MC.D1 ),
    .I1(\U1/U3/holdingreg1<13>_MC.D2 ),
    .O(\U1/U3/holdingreg1<13>_MC.D )
  );
  X_ZERO \U1/U3/holdingreg1<13>_MC.D1_831  (
    .O(\U1/U3/holdingreg1<13>_MC.D1 )
  );
  X_AND2 \U1/U3/holdingreg1<13>_MC.D2_PT_0_832  (
    .I0(N_PZ_938),
    .I1(\U1/U3/holdingreg1 [13]),
    .O(\U1/U3/holdingreg1<13>_MC.D2_PT_0 )
  );
  X_AND4 \U1/U3/holdingreg1<13>_MC.D2_PT_1_833  (
    .I0(\MSPReset_II/UIM ),
    .I1(\NlwInverterSignal_U1/U3/holdingreg1<13>_MC.D2_PT_1/IN1 ),
    .I2(U2_ASedge),
    .I3(\U1/Channel1 [13]),
    .O(\U1/U3/holdingreg1<13>_MC.D2_PT_1 )
  );
  X_OR2 \U1/U3/holdingreg1<13>_MC.D2_834  (
    .I0(\U1/U3/holdingreg1<13>_MC.D2_PT_0 ),
    .I1(\U1/U3/holdingreg1<13>_MC.D2_PT_1 ),
    .O(\U1/U3/holdingreg1<13>_MC.D2 )
  );
  X_BUF \U1/Channel1<13>  (
    .I(\U1/Channel1<13>_MC.Q ),
    .O(\U1/Channel1 [13])
  );
  X_XOR2 \U1/Channel1<13>_MC_tsimcreated_xor__835  (
    .I0(\U1/Channel1<13>_MC.D ),
    .I1(\U1/Channel1<13>_MC.Q ),
    .O(\U1/Channel1<13>_MC_tsimcreated_xor_ )
  );
  X_FF \U1/Channel1<13>_MC.REG  (
    .I(\U1/Channel1<13>_MC_tsimcreated_xor_ ),
    .CE(Vcc),
    .CLK(\Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\U1/Channel1<13>_MC.Q )
  );
  X_XOR2 \U1/Channel1<13>_MC.D_836  (
    .I0(\U1/Channel1<13>_MC.D1 ),
    .I1(\U1/Channel1<13>_MC.D2 ),
    .O(\U1/Channel1<13>_MC.D )
  );
  X_ZERO \U1/Channel1<13>_MC.D1_837  (
    .O(\U1/Channel1<13>_MC.D1 )
  );
  X_AND2 \U1/Channel1<13>_MC.D2_PT_0_838  (
    .I0(\NlwInverterSignal_U1/Channel1<13>_MC.D2_PT_0/IN0 ),
    .I1(\U1/Channel1 [13]),
    .O(\U1/Channel1<13>_MC.D2_PT_0 )
  );
  X_AND16 \U1/Channel1<13>_MC.D2_PT_1_839  (
    .I0(\MSPReset_II/UIM ),
    .I1(\NlwInverterSignal_U1/Channel1<13>_MC.D2_PT_1/IN1 ),
    .I2(\U1/U6/CurrState_Sreg0_FFD3 ),
    .I3(\NlwInverterSignal_U1/Channel1<13>_MC.D2_PT_1/IN3 ),
    .I4(N_PZ_921),
    .I5(\U1/Channel1 [10]),
    .I6(\U1/Channel1 [9]),
    .I7(\NlwInverterSignal_U1/Channel1<13>_MC.D2_PT_1/IN7 ),
    .I8(\U1/Channel1 [11]),
    .I9(\U1/Channel1 [12]),
    .I10(Vcc),
    .I11(Vcc),
    .I12(Vcc),
    .I13(Vcc),
    .I14(Vcc),
    .I15(Vcc),
    .O(\U1/Channel1<13>_MC.D2_PT_1 )
  );
  X_AND16 \U1/Channel1<13>_MC.D2_PT_2_840  (
    .I0(\MSPReset_II/UIM ),
    .I1(\NlwInverterSignal_U1/Channel1<13>_MC.D2_PT_2/IN1 ),
    .I2(\U1/U6/CurrState_Sreg0_FFD3 ),
    .I3(\NlwInverterSignal_U1/Channel1<13>_MC.D2_PT_2/IN3 ),
    .I4(\NlwInverterSignal_U1/Channel1<13>_MC.D2_PT_2/IN4 ),
    .I5(N_PZ_1092),
    .I6(\NlwInverterSignal_U1/Channel1<13>_MC.D2_PT_2/IN6 ),
    .I7(\NlwInverterSignal_U1/Channel1<13>_MC.D2_PT_2/IN7 ),
    .I8(\U1/U5/location_Maddsub__n0000__n0075 [0]),
    .I9(\NlwInverterSignal_U1/Channel1<13>_MC.D2_PT_2/IN9 ),
    .I10(\NlwInverterSignal_U1/Channel1<13>_MC.D2_PT_2/IN10 ),
    .I11(Vcc),
    .I12(Vcc),
    .I13(Vcc),
    .I14(Vcc),
    .I15(Vcc),
    .O(\U1/Channel1<13>_MC.D2_PT_2 )
  );
  X_OR3 \U1/Channel1<13>_MC.D2_841  (
    .I0(\U1/Channel1<13>_MC.D2_PT_0 ),
    .I1(\U1/Channel1<13>_MC.D2_PT_1 ),
    .I2(\U1/Channel1<13>_MC.D2_PT_2 ),
    .O(\U1/Channel1<13>_MC.D2 )
  );
  X_BUF \U1/Channel1<10>  (
    .I(\U1/Channel1<10>_MC.Q ),
    .O(\U1/Channel1 [10])
  );
  X_XOR2 \U1/Channel1<10>_MC_tsimcreated_xor__842  (
    .I0(\U1/Channel1<10>_MC.D ),
    .I1(\U1/Channel1<10>_MC.Q ),
    .O(\U1/Channel1<10>_MC_tsimcreated_xor_ )
  );
  X_FF \U1/Channel1<10>_MC.REG  (
    .I(\U1/Channel1<10>_MC_tsimcreated_xor_ ),
    .CE(Vcc),
    .CLK(\Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\U1/Channel1<10>_MC.Q )
  );
  X_XOR2 \U1/Channel1<10>_MC.D_843  (
    .I0(\U1/Channel1<10>_MC.D1 ),
    .I1(\U1/Channel1<10>_MC.D2 ),
    .O(\U1/Channel1<10>_MC.D )
  );
  X_ZERO \U1/Channel1<10>_MC.D1_844  (
    .O(\U1/Channel1<10>_MC.D1 )
  );
  X_AND2 \U1/Channel1<10>_MC.D2_PT_0_845  (
    .I0(\NlwInverterSignal_U1/Channel1<10>_MC.D2_PT_0/IN0 ),
    .I1(\U1/Channel1 [10]),
    .O(\U1/Channel1<10>_MC.D2_PT_0 )
  );
  X_AND7 \U1/Channel1<10>_MC.D2_PT_1_846  (
    .I0(\MSPReset_II/UIM ),
    .I1(\NlwInverterSignal_U1/Channel1<10>_MC.D2_PT_1/IN1 ),
    .I2(\U1/U6/CurrState_Sreg0_FFD3 ),
    .I3(\NlwInverterSignal_U1/Channel1<10>_MC.D2_PT_1/IN3 ),
    .I4(N_PZ_921),
    .I5(\U1/Channel1 [9]),
    .I6(\NlwInverterSignal_U1/Channel1<10>_MC.D2_PT_1/IN6 ),
    .O(\U1/Channel1<10>_MC.D2_PT_1 )
  );
  X_AND8 \U1/Channel1<10>_MC.D2_PT_2_847  (
    .I0(\MSPReset_II/UIM ),
    .I1(\NlwInverterSignal_U1/Channel1<10>_MC.D2_PT_2/IN1 ),
    .I2(\U1/U6/CurrState_Sreg0_FFD3 ),
    .I3(\NlwInverterSignal_U1/Channel1<10>_MC.D2_PT_2/IN3 ),
    .I4(\NlwInverterSignal_U1/Channel1<10>_MC.D2_PT_2/IN4 ),
    .I5(N_PZ_1092),
    .I6(\NlwInverterSignal_U1/Channel1<10>_MC.D2_PT_2/IN6 ),
    .I7(\U1/U5/location_Maddsub__n0000__n0075 [0]),
    .O(\U1/Channel1<10>_MC.D2_PT_2 )
  );
  X_OR3 \U1/Channel1<10>_MC.D2_848  (
    .I0(\U1/Channel1<10>_MC.D2_PT_0 ),
    .I1(\U1/Channel1<10>_MC.D2_PT_1 ),
    .I2(\U1/Channel1<10>_MC.D2_PT_2 ),
    .O(\U1/Channel1<10>_MC.D2 )
  );
  X_BUF \U1/Channel1<9>  (
    .I(\U1/Channel1<9>_MC.Q ),
    .O(\U1/Channel1 [9])
  );
  X_XOR2 \U1/Channel1<9>_MC_tsimcreated_xor__849  (
    .I0(\U1/Channel1<9>_MC.D ),
    .I1(\U1/Channel1<9>_MC.Q ),
    .O(\U1/Channel1<9>_MC_tsimcreated_xor_ )
  );
  X_FF \U1/Channel1<9>_MC.REG  (
    .I(\U1/Channel1<9>_MC_tsimcreated_xor_ ),
    .CE(Vcc),
    .CLK(\Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\U1/Channel1<9>_MC.Q )
  );
  X_XOR2 \U1/Channel1<9>_MC.D_850  (
    .I0(\U1/Channel1<9>_MC.D1 ),
    .I1(\U1/Channel1<9>_MC.D2 ),
    .O(\U1/Channel1<9>_MC.D )
  );
  X_ZERO \U1/Channel1<9>_MC.D1_851  (
    .O(\U1/Channel1<9>_MC.D1 )
  );
  X_AND2 \U1/Channel1<9>_MC.D2_PT_0_852  (
    .I0(\NlwInverterSignal_U1/Channel1<9>_MC.D2_PT_0/IN0 ),
    .I1(\U1/Channel1 [9]),
    .O(\U1/Channel1<9>_MC.D2_PT_0 )
  );
  X_AND6 \U1/Channel1<9>_MC.D2_PT_1_853  (
    .I0(\MSPReset_II/UIM ),
    .I1(\NlwInverterSignal_U1/Channel1<9>_MC.D2_PT_1/IN1 ),
    .I2(\U1/U6/CurrState_Sreg0_FFD3 ),
    .I3(\NlwInverterSignal_U1/Channel1<9>_MC.D2_PT_1/IN3 ),
    .I4(N_PZ_921),
    .I5(\NlwInverterSignal_U1/Channel1<9>_MC.D2_PT_1/IN5 ),
    .O(\U1/Channel1<9>_MC.D2_PT_1 )
  );
  X_AND7 \U1/Channel1<9>_MC.D2_PT_2_854  (
    .I0(\MSPReset_II/UIM ),
    .I1(\NlwInverterSignal_U1/Channel1<9>_MC.D2_PT_2/IN1 ),
    .I2(\U1/U6/CurrState_Sreg0_FFD3 ),
    .I3(\NlwInverterSignal_U1/Channel1<9>_MC.D2_PT_2/IN3 ),
    .I4(\NlwInverterSignal_U1/Channel1<9>_MC.D2_PT_2/IN4 ),
    .I5(N_PZ_1092),
    .I6(\U1/U5/location_Maddsub__n0000__n0075 [0]),
    .O(\U1/Channel1<9>_MC.D2_PT_2 )
  );
  X_OR3 \U1/Channel1<9>_MC.D2_855  (
    .I0(\U1/Channel1<9>_MC.D2_PT_0 ),
    .I1(\U1/Channel1<9>_MC.D2_PT_1 ),
    .I2(\U1/Channel1<9>_MC.D2_PT_2 ),
    .O(\U1/Channel1<9>_MC.D2 )
  );
  X_BUF \U1/U5/location_Maddsub__n0000__n0075<0>  (
    .I(\U1/U5/location_Maddsub__n0000__n0075<0>_MC.Q ),
    .O(\U1/U5/location_Maddsub__n0000__n0075 [0])
  );
  X_BUF \U1/U5/location_Maddsub__n0000__n0075<0>_MC.Q_856  (
    .I(\U1/U5/location_Maddsub__n0000__n0075<0>_MC.D ),
    .O(\U1/U5/location_Maddsub__n0000__n0075<0>_MC.Q )
  );
  X_XOR2 \U1/U5/location_Maddsub__n0000__n0075<0>_MC.D_857  (
    .I0(\U1/U5/location_Maddsub__n0000__n0075<0>_MC.D1 ),
    .I1(\U1/U5/location_Maddsub__n0000__n0075<0>_MC.D2 ),
    .O(\U1/U5/location_Maddsub__n0000__n0075<0>_MC.D )
  );
  X_AND2 \U1/U5/location_Maddsub__n0000__n0075<0>_MC.D1_858  (
    .I0(N_PZ_944),
    .I1(N_PZ_944),
    .O(\U1/U5/location_Maddsub__n0000__n0075<0>_MC.D1 )
  );
  X_AND6 \U1/U5/location_Maddsub__n0000__n0075<0>_MC.D2_PT_0_859  (
    .I0(\U1/Channel1 [5]),
    .I1(\NlwInverterSignal_U1/U5/location_Maddsub__n0000__n0075<0>_MC.D2_PT_0/IN1 ),
    .I2(N_PZ_944),
    .I3(\U1/Channel1 [6]),
    .I4(\U1/Channel1 [7]),
    .I5(\U1/Channel1 [8]),
    .O(\U1/U5/location_Maddsub__n0000__n0075<0>_MC.D2_PT_0 )
  );
  X_AND6 \U1/U5/location_Maddsub__n0000__n0075<0>_MC.D2_PT_1_860  (
    .I0(\NlwInverterSignal_U1/U5/location_Maddsub__n0000__n0075<0>_MC.D2_PT_1/IN0 ),
    .I1(\U1/U5/location_Maddsub__n0000__n0067 [0]),
    .I2(\NlwInverterSignal_U1/U5/location_Maddsub__n0000__n0075<0>_MC.D2_PT_1/IN2 ),
    .I3(\NlwInverterSignal_U1/U5/location_Maddsub__n0000__n0075<0>_MC.D2_PT_1/IN3 ),
    .I4(\NlwInverterSignal_U1/U5/location_Maddsub__n0000__n0075<0>_MC.D2_PT_1/IN4 ),
    .I5(\NlwInverterSignal_U1/U5/location_Maddsub__n0000__n0075<0>_MC.D2_PT_1/IN5 ),
    .O(\U1/U5/location_Maddsub__n0000__n0075<0>_MC.D2_PT_1 )
  );
  X_OR2 \U1/U5/location_Maddsub__n0000__n0075<0>_MC.D2_861  (
    .I0(\U1/U5/location_Maddsub__n0000__n0075<0>_MC.D2_PT_0 ),
    .I1(\U1/U5/location_Maddsub__n0000__n0075<0>_MC.D2_PT_1 ),
    .O(\U1/U5/location_Maddsub__n0000__n0075<0>_MC.D2 )
  );
  X_BUF \U1/Channel1<6>  (
    .I(\U1/Channel1<6>_MC.Q ),
    .O(\U1/Channel1 [6])
  );
  X_XOR2 \U1/Channel1<6>_MC_tsimcreated_xor__862  (
    .I0(\U1/Channel1<6>_MC.D ),
    .I1(\U1/Channel1<6>_MC.Q ),
    .O(\U1/Channel1<6>_MC_tsimcreated_xor_ )
  );
  X_FF \U1/Channel1<6>_MC.REG  (
    .I(\U1/Channel1<6>_MC_tsimcreated_xor_ ),
    .CE(Vcc),
    .CLK(\Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\U1/Channel1<6>_MC.Q )
  );
  X_XOR2 \U1/Channel1<6>_MC.D_863  (
    .I0(\U1/Channel1<6>_MC.D1 ),
    .I1(\U1/Channel1<6>_MC.D2 ),
    .O(\U1/Channel1<6>_MC.D )
  );
  X_ZERO \U1/Channel1<6>_MC.D1_864  (
    .O(\U1/Channel1<6>_MC.D1 )
  );
  X_AND2 \U1/Channel1<6>_MC.D2_PT_0_865  (
    .I0(\NlwInverterSignal_U1/Channel1<6>_MC.D2_PT_0/IN0 ),
    .I1(\U1/Channel1 [6]),
    .O(\U1/Channel1<6>_MC.D2_PT_0 )
  );
  X_AND7 \U1/Channel1<6>_MC.D2_PT_1_866  (
    .I0(\MSPReset_II/UIM ),
    .I1(\U1/Channel1 [5]),
    .I2(\NlwInverterSignal_U1/Channel1<6>_MC.D2_PT_1/IN2 ),
    .I3(\U1/U6/CurrState_Sreg0_FFD3 ),
    .I4(\NlwInverterSignal_U1/Channel1<6>_MC.D2_PT_1/IN4 ),
    .I5(\NlwInverterSignal_U1/Channel1<6>_MC.D2_PT_1/IN5 ),
    .I6(N_PZ_921),
    .O(\U1/Channel1<6>_MC.D2_PT_1 )
  );
  X_AND8 \U1/Channel1<6>_MC.D2_PT_2_867  (
    .I0(\MSPReset_II/UIM ),
    .I1(\NlwInverterSignal_U1/Channel1<6>_MC.D2_PT_2/IN1 ),
    .I2(\NlwInverterSignal_U1/Channel1<6>_MC.D2_PT_2/IN2 ),
    .I3(\U1/U6/CurrState_Sreg0_FFD3 ),
    .I4(\NlwInverterSignal_U1/Channel1<6>_MC.D2_PT_2/IN4 ),
    .I5(\U1/U5/location_Maddsub__n0000__n0067 [0]),
    .I6(\NlwInverterSignal_U1/Channel1<6>_MC.D2_PT_2/IN6 ),
    .I7(N_PZ_1092),
    .O(\U1/Channel1<6>_MC.D2_PT_2 )
  );
  X_OR3 \U1/Channel1<6>_MC.D2_868  (
    .I0(\U1/Channel1<6>_MC.D2_PT_0 ),
    .I1(\U1/Channel1<6>_MC.D2_PT_1 ),
    .I2(\U1/Channel1<6>_MC.D2_PT_2 ),
    .O(\U1/Channel1<6>_MC.D2 )
  );
  X_BUF \U1/Channel1<7>  (
    .I(\U1/Channel1<7>_MC.Q ),
    .O(\U1/Channel1 [7])
  );
  X_XOR2 \U1/Channel1<7>_MC_tsimcreated_xor__869  (
    .I0(\U1/Channel1<7>_MC.D ),
    .I1(\U1/Channel1<7>_MC.Q ),
    .O(\U1/Channel1<7>_MC_tsimcreated_xor_ )
  );
  X_FF \U1/Channel1<7>_MC.REG  (
    .I(\U1/Channel1<7>_MC_tsimcreated_xor_ ),
    .CE(Vcc),
    .CLK(\Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\U1/Channel1<7>_MC.Q )
  );
  X_XOR2 \U1/Channel1<7>_MC.D_870  (
    .I0(\U1/Channel1<7>_MC.D1 ),
    .I1(\U1/Channel1<7>_MC.D2 ),
    .O(\U1/Channel1<7>_MC.D )
  );
  X_ZERO \U1/Channel1<7>_MC.D1_871  (
    .O(\U1/Channel1<7>_MC.D1 )
  );
  X_AND2 \U1/Channel1<7>_MC.D2_PT_0_872  (
    .I0(\NlwInverterSignal_U1/Channel1<7>_MC.D2_PT_0/IN0 ),
    .I1(\U1/Channel1 [7]),
    .O(\U1/Channel1<7>_MC.D2_PT_0 )
  );
  X_AND8 \U1/Channel1<7>_MC.D2_PT_1_873  (
    .I0(\MSPReset_II/UIM ),
    .I1(\U1/Channel1 [5]),
    .I2(\NlwInverterSignal_U1/Channel1<7>_MC.D2_PT_1/IN2 ),
    .I3(\U1/U6/CurrState_Sreg0_FFD3 ),
    .I4(\NlwInverterSignal_U1/Channel1<7>_MC.D2_PT_1/IN4 ),
    .I5(\NlwInverterSignal_U1/Channel1<7>_MC.D2_PT_1/IN5 ),
    .I6(N_PZ_921),
    .I7(\U1/Channel1 [6]),
    .O(\U1/Channel1<7>_MC.D2_PT_1 )
  );
  X_AND16 \U1/Channel1<7>_MC.D2_PT_2_874  (
    .I0(\MSPReset_II/UIM ),
    .I1(\NlwInverterSignal_U1/Channel1<7>_MC.D2_PT_2/IN1 ),
    .I2(\NlwInverterSignal_U1/Channel1<7>_MC.D2_PT_2/IN2 ),
    .I3(\U1/U6/CurrState_Sreg0_FFD3 ),
    .I4(\NlwInverterSignal_U1/Channel1<7>_MC.D2_PT_2/IN4 ),
    .I5(\U1/U5/location_Maddsub__n0000__n0067 [0]),
    .I6(\NlwInverterSignal_U1/Channel1<7>_MC.D2_PT_2/IN6 ),
    .I7(N_PZ_1092),
    .I8(\NlwInverterSignal_U1/Channel1<7>_MC.D2_PT_2/IN8 ),
    .I9(Vcc),
    .I10(Vcc),
    .I11(Vcc),
    .I12(Vcc),
    .I13(Vcc),
    .I14(Vcc),
    .I15(Vcc),
    .O(\U1/Channel1<7>_MC.D2_PT_2 )
  );
  X_OR3 \U1/Channel1<7>_MC.D2_875  (
    .I0(\U1/Channel1<7>_MC.D2_PT_0 ),
    .I1(\U1/Channel1<7>_MC.D2_PT_1 ),
    .I2(\U1/Channel1<7>_MC.D2_PT_2 ),
    .O(\U1/Channel1<7>_MC.D2 )
  );
  X_BUF \U1/Channel1<8>  (
    .I(\U1/Channel1<8>_MC.Q ),
    .O(\U1/Channel1 [8])
  );
  X_XOR2 \U1/Channel1<8>_MC_tsimcreated_xor__876  (
    .I0(\U1/Channel1<8>_MC.D ),
    .I1(\U1/Channel1<8>_MC.Q ),
    .O(\U1/Channel1<8>_MC_tsimcreated_xor_ )
  );
  X_FF \U1/Channel1<8>_MC.REG  (
    .I(\U1/Channel1<8>_MC_tsimcreated_xor_ ),
    .CE(Vcc),
    .CLK(\Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\U1/Channel1<8>_MC.Q )
  );
  X_XOR2 \U1/Channel1<8>_MC.D_877  (
    .I0(\U1/Channel1<8>_MC.D1 ),
    .I1(\U1/Channel1<8>_MC.D2 ),
    .O(\U1/Channel1<8>_MC.D )
  );
  X_ZERO \U1/Channel1<8>_MC.D1_878  (
    .O(\U1/Channel1<8>_MC.D1 )
  );
  X_AND2 \U1/Channel1<8>_MC.D2_PT_0_879  (
    .I0(\NlwInverterSignal_U1/Channel1<8>_MC.D2_PT_0/IN0 ),
    .I1(\U1/Channel1 [8]),
    .O(\U1/Channel1<8>_MC.D2_PT_0 )
  );
  X_AND6 \U1/Channel1<8>_MC.D2_PT_1_880  (
    .I0(\NlwInverterSignal_U1/Channel1<8>_MC.D2_PT_1/IN0 ),
    .I1(\U1/U6/CurrState_Sreg0_FFD3 ),
    .I2(\NlwInverterSignal_U1/Channel1<8>_MC.D2_PT_1/IN2 ),
    .I3(N_PZ_921),
    .I4(\NlwInverterSignal_U1/Channel1<8>_MC.D2_PT_1/IN4 ),
    .I5(\U1/Channel1 [8]),
    .O(\U1/Channel1<8>_MC.D2_PT_1 )
  );
  X_AND6 \U1/Channel1<8>_MC.D2_PT_2_881  (
    .I0(\U1/U6/CurrState_Sreg0_FFD3 ),
    .I1(\NlwInverterSignal_U1/Channel1<8>_MC.D2_PT_2/IN1 ),
    .I2(\U1/U5/location_Maddsub__n0000__n0067 [0]),
    .I3(N_PZ_921),
    .I4(\NlwInverterSignal_U1/Channel1<8>_MC.D2_PT_2/IN4 ),
    .I5(\U1/Channel1 [8]),
    .O(\U1/Channel1<8>_MC.D2_PT_2 )
  );
  X_AND6 \U1/Channel1<8>_MC.D2_PT_3_882  (
    .I0(\U1/U6/CurrState_Sreg0_FFD3 ),
    .I1(\NlwInverterSignal_U1/Channel1<8>_MC.D2_PT_3/IN1 ),
    .I2(N_PZ_921),
    .I3(\NlwInverterSignal_U1/Channel1<8>_MC.D2_PT_3/IN3 ),
    .I4(\NlwInverterSignal_U1/Channel1<8>_MC.D2_PT_3/IN4 ),
    .I5(\U1/Channel1 [8]),
    .O(\U1/Channel1<8>_MC.D2_PT_3 )
  );
  X_AND6 \U1/Channel1<8>_MC.D2_PT_4_883  (
    .I0(\U1/U6/CurrState_Sreg0_FFD3 ),
    .I1(\NlwInverterSignal_U1/Channel1<8>_MC.D2_PT_4/IN1 ),
    .I2(N_PZ_921),
    .I3(\NlwInverterSignal_U1/Channel1<8>_MC.D2_PT_4/IN3 ),
    .I4(\U1/Channel1 [7]),
    .I5(\U1/Channel1 [8]),
    .O(\U1/Channel1<8>_MC.D2_PT_4 )
  );
  X_AND8 \U1/Channel1<8>_MC.D2_PT_5_884  (
    .I0(\MSPReset_II/UIM ),
    .I1(\NlwInverterSignal_U1/Channel1<8>_MC.D2_PT_5/IN1 ),
    .I2(\U1/U6/CurrState_Sreg0_FFD3 ),
    .I3(\NlwInverterSignal_U1/Channel1<8>_MC.D2_PT_5/IN3 ),
    .I4(\NlwInverterSignal_U1/Channel1<8>_MC.D2_PT_5/IN4 ),
    .I5(N_PZ_1092),
    .I6(\U1/U5/location_Maddsub__n0000__n0075 [0]),
    .I7(\NlwInverterSignal_U1/Channel1<8>_MC.D2_PT_5/IN7 ),
    .O(\U1/Channel1<8>_MC.D2_PT_5 )
  );
  X_AND16 \U1/Channel1<8>_MC.D2_PT_6_885  (
    .I0(\NlwInverterSignal_U1/Channel1<8>_MC.D2_PT_6/IN0 ),
    .I1(\U1/U6/CurrState_Sreg0_FFD3 ),
    .I2(\NlwInverterSignal_U1/Channel1<8>_MC.D2_PT_6/IN2 ),
    .I3(\U1/U5/location_Maddsub__n0000__n0067 [0]),
    .I4(N_PZ_1092),
    .I5(\NlwInverterSignal_U1/Channel1<8>_MC.D2_PT_6/IN5 ),
    .I6(\NlwInverterSignal_U1/Channel1<8>_MC.D2_PT_6/IN6 ),
    .I7(\NlwInverterSignal_U1/Channel1<8>_MC.D2_PT_6/IN7 ),
    .I8(\U1/Channel1 [8]),
    .I9(Vcc),
    .I10(Vcc),
    .I11(Vcc),
    .I12(Vcc),
    .I13(Vcc),
    .I14(Vcc),
    .I15(Vcc),
    .O(\U1/Channel1<8>_MC.D2_PT_6 )
  );
  X_AND16 \U1/Channel1<8>_MC.D2_PT_7_886  (
    .I0(\MSPReset_II/UIM ),
    .I1(\U1/Channel1 [5]),
    .I2(\NlwInverterSignal_U1/Channel1<8>_MC.D2_PT_7/IN2 ),
    .I3(\U1/U6/CurrState_Sreg0_FFD3 ),
    .I4(\NlwInverterSignal_U1/Channel1<8>_MC.D2_PT_7/IN4 ),
    .I5(\NlwInverterSignal_U1/Channel1<8>_MC.D2_PT_7/IN5 ),
    .I6(N_PZ_1092),
    .I7(\U1/U5/location_Maddsub__n0000__n0075 [0]),
    .I8(\U1/Channel1 [6]),
    .I9(\U1/Channel1 [7]),
    .I10(\NlwInverterSignal_U1/Channel1<8>_MC.D2_PT_7/IN10 ),
    .I11(Vcc),
    .I12(Vcc),
    .I13(Vcc),
    .I14(Vcc),
    .I15(Vcc),
    .O(\U1/Channel1<8>_MC.D2_PT_7 )
  );
  X_OR8 \U1/Channel1<8>_MC.D2_887  (
    .I0(\U1/Channel1<8>_MC.D2_PT_0 ),
    .I1(\U1/Channel1<8>_MC.D2_PT_1 ),
    .I2(\U1/Channel1<8>_MC.D2_PT_2 ),
    .I3(\U1/Channel1<8>_MC.D2_PT_3 ),
    .I4(\U1/Channel1<8>_MC.D2_PT_4 ),
    .I5(\U1/Channel1<8>_MC.D2_PT_5 ),
    .I6(\U1/Channel1<8>_MC.D2_PT_6 ),
    .I7(\U1/Channel1<8>_MC.D2_PT_7 ),
    .O(\U1/Channel1<8>_MC.D2 )
  );
  X_BUF \U1/Channel1<11>  (
    .I(\U1/Channel1<11>_MC.Q ),
    .O(\U1/Channel1 [11])
  );
  X_XOR2 \U1/Channel1<11>_MC_tsimcreated_xor__888  (
    .I0(\U1/Channel1<11>_MC.D ),
    .I1(\U1/Channel1<11>_MC.Q ),
    .O(\U1/Channel1<11>_MC_tsimcreated_xor_ )
  );
  X_FF \U1/Channel1<11>_MC.REG  (
    .I(\U1/Channel1<11>_MC_tsimcreated_xor_ ),
    .CE(Vcc),
    .CLK(\Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\U1/Channel1<11>_MC.Q )
  );
  X_XOR2 \U1/Channel1<11>_MC.D_889  (
    .I0(\U1/Channel1<11>_MC.D1 ),
    .I1(\U1/Channel1<11>_MC.D2 ),
    .O(\U1/Channel1<11>_MC.D )
  );
  X_ZERO \U1/Channel1<11>_MC.D1_890  (
    .O(\U1/Channel1<11>_MC.D1 )
  );
  X_AND2 \U1/Channel1<11>_MC.D2_PT_0_891  (
    .I0(\NlwInverterSignal_U1/Channel1<11>_MC.D2_PT_0/IN0 ),
    .I1(\U1/Channel1 [11]),
    .O(\U1/Channel1<11>_MC.D2_PT_0 )
  );
  X_AND8 \U1/Channel1<11>_MC.D2_PT_1_892  (
    .I0(\MSPReset_II/UIM ),
    .I1(\NlwInverterSignal_U1/Channel1<11>_MC.D2_PT_1/IN1 ),
    .I2(\U1/U6/CurrState_Sreg0_FFD3 ),
    .I3(\NlwInverterSignal_U1/Channel1<11>_MC.D2_PT_1/IN3 ),
    .I4(N_PZ_921),
    .I5(\U1/Channel1 [10]),
    .I6(\U1/Channel1 [9]),
    .I7(\NlwInverterSignal_U1/Channel1<11>_MC.D2_PT_1/IN7 ),
    .O(\U1/Channel1<11>_MC.D2_PT_1 )
  );
  X_AND16 \U1/Channel1<11>_MC.D2_PT_2_893  (
    .I0(\MSPReset_II/UIM ),
    .I1(\NlwInverterSignal_U1/Channel1<11>_MC.D2_PT_2/IN1 ),
    .I2(\U1/U6/CurrState_Sreg0_FFD3 ),
    .I3(\NlwInverterSignal_U1/Channel1<11>_MC.D2_PT_2/IN3 ),
    .I4(\NlwInverterSignal_U1/Channel1<11>_MC.D2_PT_2/IN4 ),
    .I5(N_PZ_1092),
    .I6(\NlwInverterSignal_U1/Channel1<11>_MC.D2_PT_2/IN6 ),
    .I7(\NlwInverterSignal_U1/Channel1<11>_MC.D2_PT_2/IN7 ),
    .I8(\U1/U5/location_Maddsub__n0000__n0075 [0]),
    .I9(Vcc),
    .I10(Vcc),
    .I11(Vcc),
    .I12(Vcc),
    .I13(Vcc),
    .I14(Vcc),
    .I15(Vcc),
    .O(\U1/Channel1<11>_MC.D2_PT_2 )
  );
  X_OR3 \U1/Channel1<11>_MC.D2_894  (
    .I0(\U1/Channel1<11>_MC.D2_PT_0 ),
    .I1(\U1/Channel1<11>_MC.D2_PT_1 ),
    .I2(\U1/Channel1<11>_MC.D2_PT_2 ),
    .O(\U1/Channel1<11>_MC.D2 )
  );
  X_BUF \U1/Channel1<12>  (
    .I(\U1/Channel1<12>_MC.Q ),
    .O(\U1/Channel1 [12])
  );
  X_XOR2 \U1/Channel1<12>_MC_tsimcreated_xor__895  (
    .I0(\U1/Channel1<12>_MC.D ),
    .I1(\U1/Channel1<12>_MC.Q ),
    .O(\U1/Channel1<12>_MC_tsimcreated_xor_ )
  );
  X_FF \U1/Channel1<12>_MC.REG  (
    .I(\U1/Channel1<12>_MC_tsimcreated_xor_ ),
    .CE(Vcc),
    .CLK(\Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\U1/Channel1<12>_MC.Q )
  );
  X_XOR2 \U1/Channel1<12>_MC.D_896  (
    .I0(\U1/Channel1<12>_MC.D1 ),
    .I1(\U1/Channel1<12>_MC.D2 ),
    .O(\U1/Channel1<12>_MC.D )
  );
  X_ZERO \U1/Channel1<12>_MC.D1_897  (
    .O(\U1/Channel1<12>_MC.D1 )
  );
  X_AND2 \U1/Channel1<12>_MC.D2_PT_0_898  (
    .I0(\NlwInverterSignal_U1/Channel1<12>_MC.D2_PT_0/IN0 ),
    .I1(\U1/Channel1 [12]),
    .O(\U1/Channel1<12>_MC.D2_PT_0 )
  );
  X_AND16 \U1/Channel1<12>_MC.D2_PT_1_899  (
    .I0(\MSPReset_II/UIM ),
    .I1(\NlwInverterSignal_U1/Channel1<12>_MC.D2_PT_1/IN1 ),
    .I2(\U1/U6/CurrState_Sreg0_FFD3 ),
    .I3(\NlwInverterSignal_U1/Channel1<12>_MC.D2_PT_1/IN3 ),
    .I4(N_PZ_921),
    .I5(\U1/Channel1 [10]),
    .I6(\U1/Channel1 [9]),
    .I7(\NlwInverterSignal_U1/Channel1<12>_MC.D2_PT_1/IN7 ),
    .I8(\U1/Channel1 [11]),
    .I9(Vcc),
    .I10(Vcc),
    .I11(Vcc),
    .I12(Vcc),
    .I13(Vcc),
    .I14(Vcc),
    .I15(Vcc),
    .O(\U1/Channel1<12>_MC.D2_PT_1 )
  );
  X_AND16 \U1/Channel1<12>_MC.D2_PT_2_900  (
    .I0(\MSPReset_II/UIM ),
    .I1(\NlwInverterSignal_U1/Channel1<12>_MC.D2_PT_2/IN1 ),
    .I2(\U1/U6/CurrState_Sreg0_FFD3 ),
    .I3(\NlwInverterSignal_U1/Channel1<12>_MC.D2_PT_2/IN3 ),
    .I4(\NlwInverterSignal_U1/Channel1<12>_MC.D2_PT_2/IN4 ),
    .I5(N_PZ_1092),
    .I6(\NlwInverterSignal_U1/Channel1<12>_MC.D2_PT_2/IN6 ),
    .I7(\NlwInverterSignal_U1/Channel1<12>_MC.D2_PT_2/IN7 ),
    .I8(\U1/U5/location_Maddsub__n0000__n0075 [0]),
    .I9(\NlwInverterSignal_U1/Channel1<12>_MC.D2_PT_2/IN9 ),
    .I10(Vcc),
    .I11(Vcc),
    .I12(Vcc),
    .I13(Vcc),
    .I14(Vcc),
    .I15(Vcc),
    .O(\U1/Channel1<12>_MC.D2_PT_2 )
  );
  X_OR3 \U1/Channel1<12>_MC.D2_901  (
    .I0(\U1/Channel1<12>_MC.D2_PT_0 ),
    .I1(\U1/Channel1<12>_MC.D2_PT_1 ),
    .I2(\U1/Channel1<12>_MC.D2_PT_2 ),
    .O(\U1/Channel1<12>_MC.D2 )
  );
  X_BUF N_PZ_961_902 (
    .I(\N_PZ_961_MC.Q ),
    .O(N_PZ_961)
  );
  X_BUF \N_PZ_961_MC.Q_903  (
    .I(\N_PZ_961_MC.D ),
    .O(\N_PZ_961_MC.Q )
  );
  X_XOR2 \N_PZ_961_MC.D_904  (
    .I0(\N_PZ_961_MC.D1 ),
    .I1(\N_PZ_961_MC.D2 ),
    .O(\N_PZ_961_MC.D )
  );
  X_AND4 \N_PZ_961_MC.D1_905  (
    .I0(\NlwInverterSignal_N_PZ_961_MC.D1/IN0 ),
    .I1(\NlwInverterSignal_N_PZ_961_MC.D1/IN1 ),
    .I2(\NlwInverterSignal_N_PZ_961_MC.D1/IN2 ),
    .I3(\NlwInverterSignal_N_PZ_961_MC.D1/IN3 ),
    .O(\N_PZ_961_MC.D1 )
  );
  X_ZERO \N_PZ_961_MC.D2_906  (
    .O(\N_PZ_961_MC.D2 )
  );
  X_BUF DCOR1CNTHIGHr_907 (
    .I(\DCOR1CNTHIGHr_MC.Q ),
    .O(DCOR1CNTHIGHr)
  );
  X_BUF \DCOR1CNTHIGHr_MC.Q_908  (
    .I(\DCOR1CNTHIGHr_MC.D ),
    .O(\DCOR1CNTHIGHr_MC.Q )
  );
  X_XOR2 \DCOR1CNTHIGHr_MC.D_909  (
    .I0(\DCOR1CNTHIGHr_MC.D1 ),
    .I1(\DCOR1CNTHIGHr_MC.D2 ),
    .O(\DCOR1CNTHIGHr_MC.D )
  );
  X_AND16 \DCOR1CNTHIGHr_MC.D1_910  (
    .I0(\WR_II/UIM ),
    .I1(\NlwInverterSignal_DCOR1CNTHIGHr_MC.D1/IN1 ),
    .I2(U2_ADDR_reg[0]),
    .I3(\NlwInverterSignal_DCOR1CNTHIGHr_MC.D1/IN3 ),
    .I4(\NlwInverterSignal_DCOR1CNTHIGHr_MC.D1/IN4 ),
    .I5(\NlwInverterSignal_DCOR1CNTHIGHr_MC.D1/IN5 ),
    .I6(\NlwInverterSignal_DCOR1CNTHIGHr_MC.D1/IN6 ),
    .I7(\NlwInverterSignal_DCOR1CNTHIGHr_MC.D1/IN7 ),
    .I8(U2_ADDR_reg[1]),
    .I9(U2_ADDR_reg[2]),
    .I10(Vcc),
    .I11(Vcc),
    .I12(Vcc),
    .I13(Vcc),
    .I14(Vcc),
    .I15(Vcc),
    .O(\DCOR1CNTHIGHr_MC.D1 )
  );
  X_ZERO \DCOR1CNTHIGHr_MC.D2_911  (
    .O(\DCOR1CNTHIGHr_MC.D2 )
  );
  X_BUF \outDATA<5>\$WA6.UIM_912  (
    .I(\outDATA<5>\$WA6.UIM_MC.Q ),
    .O(\outDATA<5>\$WA6.UIM )
  );
  X_BUF \outDATA<5>\$WA6.UIM_MC.Q_913  (
    .I(\outDATA<5>\$WA6.UIM_MC.D ),
    .O(\outDATA<5>\$WA6.UIM_MC.Q )
  );
  X_XOR2 \outDATA<5>\$WA6.UIM_MC.D_914  (
    .I0(\outDATA<5>\$WA6.UIM_MC.D1 ),
    .I1(\outDATA<5>\$WA6.UIM_MC.D2 ),
    .O(\outDATA<5>\$WA6.UIM_MC.D )
  );
  X_ZERO \outDATA<5>\$WA6.UIM_MC.D1_915  (
    .O(\outDATA<5>\$WA6.UIM_MC.D1 )
  );
  X_AND2 \outDATA<5>\$WA6.UIM_MC.D2_PT_0_916  (
    .I0(\U1/U4/Latch0r [5]),
    .I1(DCOR0THRESLOWr),
    .O(\outDATA<5>\$WA6.UIM_MC.D2_PT_0 )
  );
  X_AND3 \outDATA<5>\$WA6.UIM_MC.D2_PT_1_917  (
    .I0(\NlwInverterSignal_outDATA<5>\$WA6.UIM_MC.D2_PT_1/IN0 ),
    .I1(NET2501),
    .I2(DCORIFGr),
    .O(\outDATA<5>\$WA6.UIM_MC.D2_PT_1 )
  );
  X_AND4 \outDATA<5>\$WA6.UIM_MC.D2_PT_2_918  (
    .I0(\NlwInverterSignal_outDATA<5>\$WA6.UIM_MC.D2_PT_2/IN0 ),
    .I1(\NlwInverterSignal_outDATA<5>\$WA6.UIM_MC.D2_PT_2/IN1 ),
    .I2(\U1/U4/Latch0r [13]),
    .I3(DCOR0THRESHIGHr),
    .O(\outDATA<5>\$WA6.UIM_MC.D2_PT_2 )
  );
  X_AND5 \outDATA<5>\$WA6.UIM_MC.D2_PT_3_919  (
    .I0(\NlwInverterSignal_outDATA<5>\$WA6.UIM_MC.D2_PT_3/IN0 ),
    .I1(\NlwInverterSignal_outDATA<5>\$WA6.UIM_MC.D2_PT_3/IN1 ),
    .I2(\NlwInverterSignal_outDATA<5>\$WA6.UIM_MC.D2_PT_3/IN2 ),
    .I3(\U1/U4/Latch1r [5]),
    .I4(DCOR1THRESLOWr),
    .O(\outDATA<5>\$WA6.UIM_MC.D2_PT_3 )
  );
  X_AND5 \outDATA<5>\$WA6.UIM_MC.D2_PT_4_920  (
    .I0(\NlwInverterSignal_outDATA<5>\$WA6.UIM_MC.D2_PT_4/IN0 ),
    .I1(\NlwInverterSignal_outDATA<5>\$WA6.UIM_MC.D2_PT_4/IN1 ),
    .I2(\NlwInverterSignal_outDATA<5>\$WA6.UIM_MC.D2_PT_4/IN2 ),
    .I3(\NlwInverterSignal_outDATA<5>\$WA6.UIM_MC.D2_PT_4/IN3 ),
    .I4(\U1/U4/Latch1r [13]),
    .O(\outDATA<5>\$WA6.UIM_MC.D2_PT_4 )
  );
  X_OR5 \outDATA<5>\$WA6.UIM_MC.D2_921  (
    .I0(\outDATA<5>\$WA6.UIM_MC.D2_PT_0 ),
    .I1(\outDATA<5>\$WA6.UIM_MC.D2_PT_1 ),
    .I2(\outDATA<5>\$WA6.UIM_MC.D2_PT_2 ),
    .I3(\outDATA<5>\$WA6.UIM_MC.D2_PT_3 ),
    .I4(\outDATA<5>\$WA6.UIM_MC.D2_PT_4 ),
    .O(\outDATA<5>\$WA6.UIM_MC.D2 )
  );
  X_BUF \U1/U4/Latch0r<5>  (
    .I(\U1/U4/Latch0r<5>_MC.Q ),
    .O(\U1/U4/Latch0r [5])
  );
  X_FF \U1/U4/Latch0r<5>_MC.REG  (
    .I(\U1/U4/Latch0r<5>_MC.D ),
    .CE(Vcc),
    .CLK(\U1/U4/Latch0r<5>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\U1/U4/Latch0r<5>_MC.Q )
  );
  X_INV \U1/U4/Latch0r<5>_MC.REG_tsimcreated_inv_Mclk_II/FCLK_922  (
    .I(\Mclk_II/FCLK ),
    .O(\U1/U4/Latch0r<5>_MC.REG_tsimcreated_inv_Mclk_II/FCLK )
  );
  X_XOR2 \U1/U4/Latch0r<5>_MC.D_923  (
    .I0(\U1/U4/Latch0r<5>_MC.D1 ),
    .I1(\U1/U4/Latch0r<5>_MC.D2 ),
    .O(\U1/U4/Latch0r<5>_MC.D )
  );
  X_ZERO \U1/U4/Latch0r<5>_MC.D1_924  (
    .O(\U1/U4/Latch0r<5>_MC.D1 )
  );
  X_AND3 \U1/U4/Latch0r<5>_MC.D2_PT_0_925  (
    .I0(\MSPReset_II/UIM ),
    .I1(\U1/Channel0 [5]),
    .I2(N_PZ_963),
    .O(\U1/U4/Latch0r<5>_MC.D2_PT_0 )
  );
  X_AND3 \U1/U4/Latch0r<5>_MC.D2_PT_1_926  (
    .I0(\MSPReset_II/UIM ),
    .I1(\U1/U4/Latch0r [5]),
    .I2(\NlwInverterSignal_U1/U4/Latch0r<5>_MC.D2_PT_1/IN2 ),
    .O(\U1/U4/Latch0r<5>_MC.D2_PT_1 )
  );
  X_OR2 \U1/U4/Latch0r<5>_MC.D2_927  (
    .I0(\U1/U4/Latch0r<5>_MC.D2_PT_0 ),
    .I1(\U1/U4/Latch0r<5>_MC.D2_PT_1 ),
    .O(\U1/U4/Latch0r<5>_MC.D2 )
  );
  X_BUF N_PZ_963_928 (
    .I(\N_PZ_963_MC.Q ),
    .O(N_PZ_963)
  );
  X_BUF \N_PZ_963_MC.Q_929  (
    .I(\N_PZ_963_MC.D ),
    .O(\N_PZ_963_MC.Q )
  );
  X_XOR2 \N_PZ_963_MC.D_930  (
    .I0(\N_PZ_963_MC.D1 ),
    .I1(\N_PZ_963_MC.D2 ),
    .O(\N_PZ_963_MC.D )
  );
  X_ZERO \N_PZ_963_MC.D1_931  (
    .O(\N_PZ_963_MC.D1 )
  );
  X_AND6 \N_PZ_963_MC.D2_PT_0_932  (
    .I0(\NlwInverterSignal_N_PZ_963_MC.D2_PT_0/IN0 ),
    .I1(\NlwInverterSignal_N_PZ_963_MC.D2_PT_0/IN1 ),
    .I2(\NlwInverterSignal_N_PZ_963_MC.D2_PT_0/IN2 ),
    .I3(\U1/U4/LatchEdge0r ),
    .I4(\NlwInverterSignal_N_PZ_963_MC.D2_PT_0/IN4 ),
    .I5(\outDATA<6>\$WA1.UIM ),
    .O(\N_PZ_963_MC.D2_PT_0 )
  );
  X_AND6 \N_PZ_963_MC.D2_PT_1_933  (
    .I0(\NlwInverterSignal_N_PZ_963_MC.D2_PT_1/IN0 ),
    .I1(\NlwInverterSignal_N_PZ_963_MC.D2_PT_1/IN1 ),
    .I2(\NlwInverterSignal_N_PZ_963_MC.D2_PT_1/IN2 ),
    .I3(\NlwInverterSignal_N_PZ_963_MC.D2_PT_1/IN3 ),
    .I4(\U1/U4/InEdge0r ),
    .I5(\NlwInverterSignal_N_PZ_963_MC.D2_PT_1/IN5 ),
    .O(\N_PZ_963_MC.D2_PT_1 )
  );
  X_OR2 \N_PZ_963_MC.D2_934  (
    .I0(\N_PZ_963_MC.D2_PT_0 ),
    .I1(\N_PZ_963_MC.D2_PT_1 ),
    .O(\N_PZ_963_MC.D2 )
  );
  X_BUF NET2501_935 (
    .I(\NET2501_MC.Q ),
    .O(NET2501)
  );
  X_XOR2 NET2501_MC_tsimcreated_xor__936 (
    .I0(\NET2501_MC.D ),
    .I1(\NET2501_MC.Q ),
    .O(NET2501_MC_tsimcreated_xor_)
  );
  X_FF \NET2501_MC.REG  (
    .I(NET2501_MC_tsimcreated_xor_),
    .CE(Vcc),
    .CLK(\NET2501_MC.REG_tsimcreated_inv_Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\NET2501_MC.Q )
  );
  X_INV \NET2501_MC.REG_tsimcreated_inv_Mclk_II/FCLK_937  (
    .I(\Mclk_II/FCLK ),
    .O(\NET2501_MC.REG_tsimcreated_inv_Mclk_II/FCLK )
  );
  X_XOR2 \NET2501_MC.D_938  (
    .I0(\NET2501_MC.D1 ),
    .I1(\NET2501_MC.D2 ),
    .O(\NET2501_MC.D )
  );
  X_ZERO \NET2501_MC.D1_939  (
    .O(\NET2501_MC.D1 )
  );
  X_AND2 \NET2501_MC.D2_PT_0_940  (
    .I0(\MSPReset_II/UIM ),
    .I1(N_PZ_963),
    .O(\NET2501_MC.D2_PT_0 )
  );
  X_AND5 \NET2501_MC.D2_PT_1_941  (
    .I0(\MSPReset_II/UIM ),
    .I1(\AD<5>_II/UIM ),
    .I2(DCORIFGw),
    .I3(\NlwInverterSignal_NET2501_MC.D2_PT_1/IN3 ),
    .I4(NET2501),
    .O(\NET2501_MC.D2_PT_1 )
  );
  X_OR2 \NET2501_MC.D2_942  (
    .I0(\NET2501_MC.D2_PT_0 ),
    .I1(\NET2501_MC.D2_PT_1 ),
    .O(\NET2501_MC.D2 )
  );
  X_BUF \U1/U4/LatchEdge0r_943  (
    .I(\U1/U4/LatchEdge0r_MC.Q ),
    .O(\U1/U4/LatchEdge0r )
  );
  X_FF \U1/U4/LatchEdge0r_MC.REG  (
    .I(\U1/U4/LatchEdge0r_MC.D ),
    .CE(Vcc),
    .CLK(\U1/U4/LatchEdge0r_MC.REG_tsimcreated_inv_Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\U1/U4/LatchEdge0r_MC.Q )
  );
  X_INV \U1/U4/LatchEdge0r_MC.REG_tsimcreated_inv_Mclk_II/FCLK_944  (
    .I(\Mclk_II/FCLK ),
    .O(\U1/U4/LatchEdge0r_MC.REG_tsimcreated_inv_Mclk_II/FCLK )
  );
  X_XOR2 \U1/U4/LatchEdge0r_MC.D_945  (
    .I0(\U1/U4/LatchEdge0r_MC.D1 ),
    .I1(\U1/U4/LatchEdge0r_MC.D2 ),
    .O(\U1/U4/LatchEdge0r_MC.D )
  );
  X_ZERO \U1/U4/LatchEdge0r_MC.D1_946  (
    .O(\U1/U4/LatchEdge0r_MC.D1 )
  );
  X_AND3 \U1/U4/LatchEdge0r_MC.D2_PT_0_947  (
    .I0(\MSPReset_II/UIM ),
    .I1(\AD<2>_II/UIM ),
    .I2(DCORENCCTLw),
    .O(\U1/U4/LatchEdge0r_MC.D2_PT_0 )
  );
  X_AND3 \U1/U4/LatchEdge0r_MC.D2_PT_1_948  (
    .I0(\MSPReset_II/UIM ),
    .I1(\NlwInverterSignal_U1/U4/LatchEdge0r_MC.D2_PT_1/IN1 ),
    .I2(\U1/U4/LatchEdge0r ),
    .O(\U1/U4/LatchEdge0r_MC.D2_PT_1 )
  );
  X_OR2 \U1/U4/LatchEdge0r_MC.D2_949  (
    .I0(\U1/U4/LatchEdge0r_MC.D2_PT_0 ),
    .I1(\U1/U4/LatchEdge0r_MC.D2_PT_1 ),
    .O(\U1/U4/LatchEdge0r_MC.D2 )
  );
  X_BUF \outDATA<6>\$WA1.UIM_950  (
    .I(\outDATA<6>\$WA1.UIM_MC.Q ),
    .O(\outDATA<6>\$WA1.UIM )
  );
  X_BUF \outDATA<6>\$WA1.UIM_MC.Q_951  (
    .I(\outDATA<6>\$WA1.UIM_MC.D ),
    .O(\outDATA<6>\$WA1.UIM_MC.Q )
  );
  X_XOR2 \outDATA<6>\$WA1.UIM_MC.D_952  (
    .I0(\outDATA<6>\$WA1.UIM_MC.D1 ),
    .I1(\outDATA<6>\$WA1.UIM_MC.D2 ),
    .O(\outDATA<6>\$WA1.UIM_MC.D )
  );
  X_AND2 \outDATA<6>\$WA1.UIM_MC.D1_953  (
    .I0(\GP_Motor0_0_II/UIM ),
    .I1(\GP_Motor0_0_II/UIM ),
    .O(\outDATA<6>\$WA1.UIM_MC.D1 )
  );
  X_ZERO \outDATA<6>\$WA1.UIM_MC.D2_954  (
    .O(\outDATA<6>\$WA1.UIM_MC.D2 )
  );
  X_BUF DCOR0THRESLOWr_955 (
    .I(\DCOR0THRESLOWr_MC.Q ),
    .O(DCOR0THRESLOWr)
  );
  X_BUF \DCOR0THRESLOWr_MC.Q_956  (
    .I(\DCOR0THRESLOWr_MC.D ),
    .O(\DCOR0THRESLOWr_MC.Q )
  );
  X_XOR2 \DCOR0THRESLOWr_MC.D_957  (
    .I0(\DCOR0THRESLOWr_MC.D1 ),
    .I1(\DCOR0THRESLOWr_MC.D2 ),
    .O(\DCOR0THRESLOWr_MC.D )
  );
  X_AND16 \DCOR0THRESLOWr_MC.D1_958  (
    .I0(\WR_II/UIM ),
    .I1(\NlwInverterSignal_DCOR0THRESLOWr_MC.D1/IN1 ),
    .I2(\NlwInverterSignal_DCOR0THRESLOWr_MC.D1/IN2 ),
    .I3(\NlwInverterSignal_DCOR0THRESLOWr_MC.D1/IN3 ),
    .I4(\NlwInverterSignal_DCOR0THRESLOWr_MC.D1/IN4 ),
    .I5(\NlwInverterSignal_DCOR0THRESLOWr_MC.D1/IN5 ),
    .I6(\NlwInverterSignal_DCOR0THRESLOWr_MC.D1/IN6 ),
    .I7(U2_ADDR_reg[3]),
    .I8(\NlwInverterSignal_DCOR0THRESLOWr_MC.D1/IN8 ),
    .I9(\NlwInverterSignal_DCOR0THRESLOWr_MC.D1/IN9 ),
    .I10(Vcc),
    .I11(Vcc),
    .I12(Vcc),
    .I13(Vcc),
    .I14(Vcc),
    .I15(Vcc),
    .O(\DCOR0THRESLOWr_MC.D1 )
  );
  X_ZERO \DCOR0THRESLOWr_MC.D2_959  (
    .O(\DCOR0THRESLOWr_MC.D2 )
  );
  X_BUF DCORIFGr_960 (
    .I(\DCORIFGr_MC.Q ),
    .O(DCORIFGr)
  );
  X_BUF \DCORIFGr_MC.Q_961  (
    .I(\DCORIFGr_MC.D ),
    .O(\DCORIFGr_MC.Q )
  );
  X_XOR2 \DCORIFGr_MC.D_962  (
    .I0(\DCORIFGr_MC.D1 ),
    .I1(\DCORIFGr_MC.D2 ),
    .O(\DCORIFGr_MC.D )
  );
  X_AND16 \DCORIFGr_MC.D1_963  (
    .I0(\WR_II/UIM ),
    .I1(\NlwInverterSignal_DCORIFGr_MC.D1/IN1 ),
    .I2(U2_ADDR_reg[0]),
    .I3(\NlwInverterSignal_DCORIFGr_MC.D1/IN3 ),
    .I4(\NlwInverterSignal_DCORIFGr_MC.D1/IN4 ),
    .I5(\NlwInverterSignal_DCORIFGr_MC.D1/IN5 ),
    .I6(\NlwInverterSignal_DCORIFGr_MC.D1/IN6 ),
    .I7(\NlwInverterSignal_DCORIFGr_MC.D1/IN7 ),
    .I8(\NlwInverterSignal_DCORIFGr_MC.D1/IN8 ),
    .I9(\NlwInverterSignal_DCORIFGr_MC.D1/IN9 ),
    .I10(Vcc),
    .I11(Vcc),
    .I12(Vcc),
    .I13(Vcc),
    .I14(Vcc),
    .I15(Vcc),
    .O(\DCORIFGr_MC.D1 )
  );
  X_ZERO \DCORIFGr_MC.D2_964  (
    .O(\DCORIFGr_MC.D2 )
  );
  X_BUF \U1/U4/Latch0r<13>  (
    .I(\U1/U4/Latch0r<13>_MC.Q ),
    .O(\U1/U4/Latch0r [13])
  );
  X_FF \U1/U4/Latch0r<13>_MC.REG  (
    .I(\U1/U4/Latch0r<13>_MC.D ),
    .CE(Vcc),
    .CLK(\U1/U4/Latch0r<13>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\U1/U4/Latch0r<13>_MC.Q )
  );
  X_INV \U1/U4/Latch0r<13>_MC.REG_tsimcreated_inv_Mclk_II/FCLK_965  (
    .I(\Mclk_II/FCLK ),
    .O(\U1/U4/Latch0r<13>_MC.REG_tsimcreated_inv_Mclk_II/FCLK )
  );
  X_XOR2 \U1/U4/Latch0r<13>_MC.D_966  (
    .I0(\U1/U4/Latch0r<13>_MC.D1 ),
    .I1(\U1/U4/Latch0r<13>_MC.D2 ),
    .O(\U1/U4/Latch0r<13>_MC.D )
  );
  X_ZERO \U1/U4/Latch0r<13>_MC.D1_967  (
    .O(\U1/U4/Latch0r<13>_MC.D1 )
  );
  X_AND3 \U1/U4/Latch0r<13>_MC.D2_PT_0_968  (
    .I0(\MSPReset_II/UIM ),
    .I1(\U1/Channel0 [13]),
    .I2(N_PZ_963),
    .O(\U1/U4/Latch0r<13>_MC.D2_PT_0 )
  );
  X_AND3 \U1/U4/Latch0r<13>_MC.D2_PT_1_969  (
    .I0(\MSPReset_II/UIM ),
    .I1(\U1/U4/Latch0r [13]),
    .I2(\NlwInverterSignal_U1/U4/Latch0r<13>_MC.D2_PT_1/IN2 ),
    .O(\U1/U4/Latch0r<13>_MC.D2_PT_1 )
  );
  X_OR2 \U1/U4/Latch0r<13>_MC.D2_970  (
    .I0(\U1/U4/Latch0r<13>_MC.D2_PT_0 ),
    .I1(\U1/U4/Latch0r<13>_MC.D2_PT_1 ),
    .O(\U1/U4/Latch0r<13>_MC.D2 )
  );
  X_BUF DCOR0THRESHIGHr_971 (
    .I(\DCOR0THRESHIGHr_MC.Q ),
    .O(DCOR0THRESHIGHr)
  );
  X_BUF \DCOR0THRESHIGHr_MC.Q_972  (
    .I(\DCOR0THRESHIGHr_MC.D ),
    .O(\DCOR0THRESHIGHr_MC.Q )
  );
  X_XOR2 \DCOR0THRESHIGHr_MC.D_973  (
    .I0(\DCOR0THRESHIGHr_MC.D1 ),
    .I1(\DCOR0THRESHIGHr_MC.D2 ),
    .O(\DCOR0THRESHIGHr_MC.D )
  );
  X_AND16 \DCOR0THRESHIGHr_MC.D1_974  (
    .I0(\WR_II/UIM ),
    .I1(\NlwInverterSignal_DCOR0THRESHIGHr_MC.D1/IN1 ),
    .I2(U2_ADDR_reg[0]),
    .I3(\NlwInverterSignal_DCOR0THRESHIGHr_MC.D1/IN3 ),
    .I4(\NlwInverterSignal_DCOR0THRESHIGHr_MC.D1/IN4 ),
    .I5(\NlwInverterSignal_DCOR0THRESHIGHr_MC.D1/IN5 ),
    .I6(\NlwInverterSignal_DCOR0THRESHIGHr_MC.D1/IN6 ),
    .I7(U2_ADDR_reg[3]),
    .I8(\NlwInverterSignal_DCOR0THRESHIGHr_MC.D1/IN8 ),
    .I9(\NlwInverterSignal_DCOR0THRESHIGHr_MC.D1/IN9 ),
    .I10(Vcc),
    .I11(Vcc),
    .I12(Vcc),
    .I13(Vcc),
    .I14(Vcc),
    .I15(Vcc),
    .O(\DCOR0THRESHIGHr_MC.D1 )
  );
  X_ZERO \DCOR0THRESHIGHr_MC.D2_975  (
    .O(\DCOR0THRESHIGHr_MC.D2 )
  );
  X_BUF \U1/U4/Latch1r<5>  (
    .I(\U1/U4/Latch1r<5>_MC.Q ),
    .O(\U1/U4/Latch1r [5])
  );
  X_FF \U1/U4/Latch1r<5>_MC.REG  (
    .I(\U1/U4/Latch1r<5>_MC.D ),
    .CE(Vcc),
    .CLK(\U1/U4/Latch1r<5>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\U1/U4/Latch1r<5>_MC.Q )
  );
  X_INV \U1/U4/Latch1r<5>_MC.REG_tsimcreated_inv_Mclk_II/FCLK_976  (
    .I(\Mclk_II/FCLK ),
    .O(\U1/U4/Latch1r<5>_MC.REG_tsimcreated_inv_Mclk_II/FCLK )
  );
  X_XOR2 \U1/U4/Latch1r<5>_MC.D_977  (
    .I0(\U1/U4/Latch1r<5>_MC.D1 ),
    .I1(\U1/U4/Latch1r<5>_MC.D2 ),
    .O(\U1/U4/Latch1r<5>_MC.D )
  );
  X_ZERO \U1/U4/Latch1r<5>_MC.D1_978  (
    .O(\U1/U4/Latch1r<5>_MC.D1 )
  );
  X_AND3 \U1/U4/Latch1r<5>_MC.D2_PT_0_979  (
    .I0(\MSPReset_II/UIM ),
    .I1(\U1/Channel1 [5]),
    .I2(N_PZ_962),
    .O(\U1/U4/Latch1r<5>_MC.D2_PT_0 )
  );
  X_AND3 \U1/U4/Latch1r<5>_MC.D2_PT_1_980  (
    .I0(\MSPReset_II/UIM ),
    .I1(\U1/U4/Latch1r [5]),
    .I2(\NlwInverterSignal_U1/U4/Latch1r<5>_MC.D2_PT_1/IN2 ),
    .O(\U1/U4/Latch1r<5>_MC.D2_PT_1 )
  );
  X_OR2 \U1/U4/Latch1r<5>_MC.D2_981  (
    .I0(\U1/U4/Latch1r<5>_MC.D2_PT_0 ),
    .I1(\U1/U4/Latch1r<5>_MC.D2_PT_1 ),
    .O(\U1/U4/Latch1r<5>_MC.D2 )
  );
  X_BUF N_PZ_962_982 (
    .I(\N_PZ_962_MC.Q ),
    .O(N_PZ_962)
  );
  X_BUF \N_PZ_962_MC.Q_983  (
    .I(\N_PZ_962_MC.D ),
    .O(\N_PZ_962_MC.Q )
  );
  X_XOR2 \N_PZ_962_MC.D_984  (
    .I0(\N_PZ_962_MC.D1 ),
    .I1(\N_PZ_962_MC.D2 ),
    .O(\N_PZ_962_MC.D )
  );
  X_ZERO \N_PZ_962_MC.D1_985  (
    .O(\N_PZ_962_MC.D1 )
  );
  X_AND6 \N_PZ_962_MC.D2_PT_0_986  (
    .I0(\NlwInverterSignal_N_PZ_962_MC.D2_PT_0/IN0 ),
    .I1(\NlwInverterSignal_N_PZ_962_MC.D2_PT_0/IN1 ),
    .I2(\NlwInverterSignal_N_PZ_962_MC.D2_PT_0/IN2 ),
    .I3(\U1/U4/LatchEdge1r ),
    .I4(\NlwInverterSignal_N_PZ_962_MC.D2_PT_0/IN4 ),
    .I5(\outDATA<7>\$WA1.UIM ),
    .O(\N_PZ_962_MC.D2_PT_0 )
  );
  X_AND6 \N_PZ_962_MC.D2_PT_1_987  (
    .I0(\NlwInverterSignal_N_PZ_962_MC.D2_PT_1/IN0 ),
    .I1(\NlwInverterSignal_N_PZ_962_MC.D2_PT_1/IN1 ),
    .I2(\NlwInverterSignal_N_PZ_962_MC.D2_PT_1/IN2 ),
    .I3(\NlwInverterSignal_N_PZ_962_MC.D2_PT_1/IN3 ),
    .I4(\U1/U4/InEdge1r ),
    .I5(\NlwInverterSignal_N_PZ_962_MC.D2_PT_1/IN5 ),
    .O(\N_PZ_962_MC.D2_PT_1 )
  );
  X_OR2 \N_PZ_962_MC.D2_988  (
    .I0(\N_PZ_962_MC.D2_PT_0 ),
    .I1(\N_PZ_962_MC.D2_PT_1 ),
    .O(\N_PZ_962_MC.D2 )
  );
  X_BUF NET2512_989 (
    .I(\NET2512_MC.Q ),
    .O(NET2512)
  );
  X_XOR2 NET2512_MC_tsimcreated_xor__990 (
    .I0(\NET2512_MC.D ),
    .I1(\NET2512_MC.Q ),
    .O(NET2512_MC_tsimcreated_xor_)
  );
  X_FF \NET2512_MC.REG  (
    .I(NET2512_MC_tsimcreated_xor_),
    .CE(Vcc),
    .CLK(\NET2512_MC.REG_tsimcreated_inv_Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\NET2512_MC.Q )
  );
  X_INV \NET2512_MC.REG_tsimcreated_inv_Mclk_II/FCLK_991  (
    .I(\Mclk_II/FCLK ),
    .O(\NET2512_MC.REG_tsimcreated_inv_Mclk_II/FCLK )
  );
  X_XOR2 \NET2512_MC.D_992  (
    .I0(\NET2512_MC.D1 ),
    .I1(\NET2512_MC.D2 ),
    .O(\NET2512_MC.D )
  );
  X_ZERO \NET2512_MC.D1_993  (
    .O(\NET2512_MC.D1 )
  );
  X_AND2 \NET2512_MC.D2_PT_0_994  (
    .I0(\MSPReset_II/UIM ),
    .I1(N_PZ_962),
    .O(\NET2512_MC.D2_PT_0 )
  );
  X_AND5 \NET2512_MC.D2_PT_1_995  (
    .I0(\MSPReset_II/UIM ),
    .I1(\AD<6>_II/UIM ),
    .I2(DCORIFGw),
    .I3(\NlwInverterSignal_NET2512_MC.D2_PT_1/IN3 ),
    .I4(NET2512),
    .O(\NET2512_MC.D2_PT_1 )
  );
  X_OR2 \NET2512_MC.D2_996  (
    .I0(\NET2512_MC.D2_PT_0 ),
    .I1(\NET2512_MC.D2_PT_1 ),
    .O(\NET2512_MC.D2 )
  );
  X_BUF \U1/U4/LatchEdge1r_997  (
    .I(\U1/U4/LatchEdge1r_MC.Q ),
    .O(\U1/U4/LatchEdge1r )
  );
  X_FF \U1/U4/LatchEdge1r_MC.REG  (
    .I(\U1/U4/LatchEdge1r_MC.D ),
    .CE(Vcc),
    .CLK(\U1/U4/LatchEdge1r_MC.REG_tsimcreated_inv_Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\U1/U4/LatchEdge1r_MC.Q )
  );
  X_INV \U1/U4/LatchEdge1r_MC.REG_tsimcreated_inv_Mclk_II/FCLK_998  (
    .I(\Mclk_II/FCLK ),
    .O(\U1/U4/LatchEdge1r_MC.REG_tsimcreated_inv_Mclk_II/FCLK )
  );
  X_XOR2 \U1/U4/LatchEdge1r_MC.D_999  (
    .I0(\U1/U4/LatchEdge1r_MC.D1 ),
    .I1(\U1/U4/LatchEdge1r_MC.D2 ),
    .O(\U1/U4/LatchEdge1r_MC.D )
  );
  X_ZERO \U1/U4/LatchEdge1r_MC.D1_1000  (
    .O(\U1/U4/LatchEdge1r_MC.D1 )
  );
  X_AND3 \U1/U4/LatchEdge1r_MC.D2_PT_0_1001  (
    .I0(\MSPReset_II/UIM ),
    .I1(\AD<6>_II/UIM ),
    .I2(DCORENCCTLw),
    .O(\U1/U4/LatchEdge1r_MC.D2_PT_0 )
  );
  X_AND3 \U1/U4/LatchEdge1r_MC.D2_PT_1_1002  (
    .I0(\MSPReset_II/UIM ),
    .I1(\NlwInverterSignal_U1/U4/LatchEdge1r_MC.D2_PT_1/IN1 ),
    .I2(\U1/U4/LatchEdge1r ),
    .O(\U1/U4/LatchEdge1r_MC.D2_PT_1 )
  );
  X_OR2 \U1/U4/LatchEdge1r_MC.D2_1003  (
    .I0(\U1/U4/LatchEdge1r_MC.D2_PT_0 ),
    .I1(\U1/U4/LatchEdge1r_MC.D2_PT_1 ),
    .O(\U1/U4/LatchEdge1r_MC.D2 )
  );
  X_BUF \outDATA<7>\$WA1.UIM_1004  (
    .I(\outDATA<7>\$WA1.UIM_MC.Q ),
    .O(\outDATA<7>\$WA1.UIM )
  );
  X_BUF \outDATA<7>\$WA1.UIM_MC.Q_1005  (
    .I(\outDATA<7>\$WA1.UIM_MC.D ),
    .O(\outDATA<7>\$WA1.UIM_MC.Q )
  );
  X_XOR2 \outDATA<7>\$WA1.UIM_MC.D_1006  (
    .I0(\outDATA<7>\$WA1.UIM_MC.D1 ),
    .I1(\outDATA<7>\$WA1.UIM_MC.D2 ),
    .O(\outDATA<7>\$WA1.UIM_MC.D )
  );
  X_AND2 \outDATA<7>\$WA1.UIM_MC.D1_1007  (
    .I0(\GP_Motor1_0_II/UIM ),
    .I1(\GP_Motor1_0_II/UIM ),
    .O(\outDATA<7>\$WA1.UIM_MC.D1 )
  );
  X_ZERO \outDATA<7>\$WA1.UIM_MC.D2_1008  (
    .O(\outDATA<7>\$WA1.UIM_MC.D2 )
  );
  X_BUF DCOR1THRESLOWr_1009 (
    .I(\DCOR1THRESLOWr_MC.Q ),
    .O(DCOR1THRESLOWr)
  );
  X_BUF \DCOR1THRESLOWr_MC.Q_1010  (
    .I(\DCOR1THRESLOWr_MC.D ),
    .O(\DCOR1THRESLOWr_MC.Q )
  );
  X_XOR2 \DCOR1THRESLOWr_MC.D_1011  (
    .I0(\DCOR1THRESLOWr_MC.D1 ),
    .I1(\DCOR1THRESLOWr_MC.D2 ),
    .O(\DCOR1THRESLOWr_MC.D )
  );
  X_AND16 \DCOR1THRESLOWr_MC.D1_1012  (
    .I0(\WR_II/UIM ),
    .I1(\NlwInverterSignal_DCOR1THRESLOWr_MC.D1/IN1 ),
    .I2(\NlwInverterSignal_DCOR1THRESLOWr_MC.D1/IN2 ),
    .I3(\NlwInverterSignal_DCOR1THRESLOWr_MC.D1/IN3 ),
    .I4(\NlwInverterSignal_DCOR1THRESLOWr_MC.D1/IN4 ),
    .I5(\NlwInverterSignal_DCOR1THRESLOWr_MC.D1/IN5 ),
    .I6(\NlwInverterSignal_DCOR1THRESLOWr_MC.D1/IN6 ),
    .I7(U2_ADDR_reg[3]),
    .I8(U2_ADDR_reg[1]),
    .I9(\NlwInverterSignal_DCOR1THRESLOWr_MC.D1/IN9 ),
    .I10(Vcc),
    .I11(Vcc),
    .I12(Vcc),
    .I13(Vcc),
    .I14(Vcc),
    .I15(Vcc),
    .O(\DCOR1THRESLOWr_MC.D1 )
  );
  X_ZERO \DCOR1THRESLOWr_MC.D2_1013  (
    .O(\DCOR1THRESLOWr_MC.D2 )
  );
  X_BUF \U1/U4/Latch1r<13>  (
    .I(\U1/U4/Latch1r<13>_MC.Q ),
    .O(\U1/U4/Latch1r [13])
  );
  X_FF \U1/U4/Latch1r<13>_MC.REG  (
    .I(\U1/U4/Latch1r<13>_MC.D ),
    .CE(Vcc),
    .CLK(\U1/U4/Latch1r<13>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\U1/U4/Latch1r<13>_MC.Q )
  );
  X_INV \U1/U4/Latch1r<13>_MC.REG_tsimcreated_inv_Mclk_II/FCLK_1014  (
    .I(\Mclk_II/FCLK ),
    .O(\U1/U4/Latch1r<13>_MC.REG_tsimcreated_inv_Mclk_II/FCLK )
  );
  X_XOR2 \U1/U4/Latch1r<13>_MC.D_1015  (
    .I0(\U1/U4/Latch1r<13>_MC.D1 ),
    .I1(\U1/U4/Latch1r<13>_MC.D2 ),
    .O(\U1/U4/Latch1r<13>_MC.D )
  );
  X_ZERO \U1/U4/Latch1r<13>_MC.D1_1016  (
    .O(\U1/U4/Latch1r<13>_MC.D1 )
  );
  X_AND3 \U1/U4/Latch1r<13>_MC.D2_PT_0_1017  (
    .I0(\MSPReset_II/UIM ),
    .I1(\U1/Channel1 [13]),
    .I2(N_PZ_962),
    .O(\U1/U4/Latch1r<13>_MC.D2_PT_0 )
  );
  X_AND3 \U1/U4/Latch1r<13>_MC.D2_PT_1_1018  (
    .I0(\MSPReset_II/UIM ),
    .I1(\U1/U4/Latch1r [13]),
    .I2(\NlwInverterSignal_U1/U4/Latch1r<13>_MC.D2_PT_1/IN2 ),
    .O(\U1/U4/Latch1r<13>_MC.D2_PT_1 )
  );
  X_OR2 \U1/U4/Latch1r<13>_MC.D2_1019  (
    .I0(\U1/U4/Latch1r<13>_MC.D2_PT_0 ),
    .I1(\U1/U4/Latch1r<13>_MC.D2_PT_1 ),
    .O(\U1/U4/Latch1r<13>_MC.D2 )
  );
  X_BUF N_PZ_987_1020 (
    .I(\N_PZ_987_MC.Q ),
    .O(N_PZ_987)
  );
  X_BUF \N_PZ_987_MC.Q_1021  (
    .I(\N_PZ_987_MC.D ),
    .O(\N_PZ_987_MC.Q )
  );
  X_XOR2 \N_PZ_987_MC.D_1022  (
    .I0(\N_PZ_987_MC.D1 ),
    .I1(\N_PZ_987_MC.D2 ),
    .O(\N_PZ_987_MC.D )
  );
  X_AND5 \N_PZ_987_MC.D1_1023  (
    .I0(\NlwInverterSignal_N_PZ_987_MC.D1/IN0 ),
    .I1(\NlwInverterSignal_N_PZ_987_MC.D1/IN1 ),
    .I2(\NlwInverterSignal_N_PZ_987_MC.D1/IN2 ),
    .I3(\NlwInverterSignal_N_PZ_987_MC.D1/IN3 ),
    .I4(\NlwInverterSignal_N_PZ_987_MC.D1/IN4 ),
    .O(\N_PZ_987_MC.D1 )
  );
  X_ZERO \N_PZ_987_MC.D2_1024  (
    .O(\N_PZ_987_MC.D2 )
  );
  X_BUF DCOR1THRESHIGHr_1025 (
    .I(\DCOR1THRESHIGHr_MC.Q ),
    .O(DCOR1THRESHIGHr)
  );
  X_BUF \DCOR1THRESHIGHr_MC.Q_1026  (
    .I(\DCOR1THRESHIGHr_MC.D ),
    .O(\DCOR1THRESHIGHr_MC.Q )
  );
  X_XOR2 \DCOR1THRESHIGHr_MC.D_1027  (
    .I0(\DCOR1THRESHIGHr_MC.D1 ),
    .I1(\DCOR1THRESHIGHr_MC.D2 ),
    .O(\DCOR1THRESHIGHr_MC.D )
  );
  X_AND16 \DCOR1THRESHIGHr_MC.D1_1028  (
    .I0(\WR_II/UIM ),
    .I1(\NlwInverterSignal_DCOR1THRESHIGHr_MC.D1/IN1 ),
    .I2(U2_ADDR_reg[0]),
    .I3(\NlwInverterSignal_DCOR1THRESHIGHr_MC.D1/IN3 ),
    .I4(\NlwInverterSignal_DCOR1THRESHIGHr_MC.D1/IN4 ),
    .I5(\NlwInverterSignal_DCOR1THRESHIGHr_MC.D1/IN5 ),
    .I6(\NlwInverterSignal_DCOR1THRESHIGHr_MC.D1/IN6 ),
    .I7(U2_ADDR_reg[3]),
    .I8(U2_ADDR_reg[1]),
    .I9(\NlwInverterSignal_DCOR1THRESHIGHr_MC.D1/IN9 ),
    .I10(Vcc),
    .I11(Vcc),
    .I12(Vcc),
    .I13(Vcc),
    .I14(Vcc),
    .I15(Vcc),
    .O(\DCOR1THRESHIGHr_MC.D1 )
  );
  X_ZERO \DCOR1THRESHIGHr_MC.D2_1029  (
    .O(\DCOR1THRESHIGHr_MC.D2 )
  );
  X_BUF U2_Enable_AD_1030 (
    .I(\U2_Enable_AD_MC.Q ),
    .O(U2_Enable_AD)
  );
  X_BUF \U2_Enable_AD_MC.Q_1031  (
    .I(\U2_Enable_AD_MC.D ),
    .O(\U2_Enable_AD_MC.Q )
  );
  X_XOR2 \U2_Enable_AD_MC.D_1032  (
    .I0(\U2_Enable_AD_MC.D1 ),
    .I1(\U2_Enable_AD_MC.D2 ),
    .O(\U2_Enable_AD_MC.D )
  );
  X_AND6 \U2_Enable_AD_MC.D1_1033  (
    .I0(\WR_II/UIM ),
    .I1(\NlwInverterSignal_U2_Enable_AD_MC.D1/IN1 ),
    .I2(\NlwInverterSignal_U2_Enable_AD_MC.D1/IN2 ),
    .I3(\NlwInverterSignal_U2_Enable_AD_MC.D1/IN3 ),
    .I4(\NlwInverterSignal_U2_Enable_AD_MC.D1/IN4 ),
    .I5(\NlwInverterSignal_U2_Enable_AD_MC.D1/IN5 ),
    .O(\U2_Enable_AD_MC.D1 )
  );
  X_ZERO \U2_Enable_AD_MC.D2_1034  (
    .O(\U2_Enable_AD_MC.D2 )
  );
  X_BUF \Enc033ctrl_MC.Q_1035  (
    .I(\Enc033ctrl_MC.Q_tsimrenamed_net_ ),
    .O(\Enc033ctrl_MC.Q )
  );
  X_BUF \Enc033ctrl_MC.Q_tsimrenamed_net__1036  (
    .I(\Enc033ctrl_MC.D ),
    .O(\Enc033ctrl_MC.Q_tsimrenamed_net_ )
  );
  X_XOR2 \Enc033ctrl_MC.D_1037  (
    .I0(\NlwInverterSignal_Enc033ctrl_MC.D/IN0 ),
    .I1(\Enc033ctrl_MC.D2 ),
    .O(\Enc033ctrl_MC.D )
  );
  X_AND2 \Enc033ctrl_MC.D1_1038  (
    .I0(\U4/ctrlr[2] ),
    .I1(\NlwInverterSignal_Enc033ctrl_MC.D1/IN1 ),
    .O(\Enc033ctrl_MC.D1 )
  );
  X_ZERO \Enc033ctrl_MC.D2_1039  (
    .O(\Enc033ctrl_MC.D2 )
  );
  X_BUF \U4/ctrlr<2>_MC.Q_1040  (
    .I(\U4/ctrlr<2>_MC.D ),
    .O(\U4/ctrlr<2>_MC.Q )
  );
  X_BUF \U4/ctrlr<2>_MC.OE_1041  (
    .I(\U4/ctrlr<2>_MC.BUFOE.OUT ),
    .O(\U4/ctrlr<2>_MC.OE )
  );
  X_BUF \U4/ctrlr<2>_MC.BUFOE.OUT_1042  (
    .I(\FOOBAR1__ctinst/7 ),
    .O(\U4/ctrlr<2>_MC.BUFOE.OUT )
  );
  X_XOR2 \U4/ctrlr<2>_MC.D_1043  (
    .I0(\NlwInverterSignal_U4/ctrlr<2>_MC.D/IN0 ),
    .I1(\U4/ctrlr<2>_MC.D2 ),
    .O(\U4/ctrlr<2>_MC.D )
  );
  X_ZERO \U4/ctrlr<2>_MC.D1_1044  (
    .O(\U4/ctrlr<2>_MC.D1 )
  );
  X_AND2 \U4/ctrlr<2>_MC.D2_PT_0_1045  (
    .I0(DCORI2CCNTr),
    .I1(\NlwInverterSignal_U4/ctrlr<2>_MC.D2_PT_0/IN1 ),
    .O(\U4/ctrlr<2>_MC.D2_PT_0 )
  );
  X_AND2 \U4/ctrlr<2>_MC.D2_PT_1_1046  (
    .I0(DCORCONFIGr),
    .I1(\NlwInverterSignal_U4/ctrlr<2>_MC.D2_PT_1/IN1 ),
    .O(\U4/ctrlr<2>_MC.D2_PT_1 )
  );
  X_AND2 \U4/ctrlr<2>_MC.D2_PT_2_1047  (
    .I0(DCORLIMITSr),
    .I1(\NlwInverterSignal_U4/ctrlr<2>_MC.D2_PT_2/IN1 ),
    .O(\U4/ctrlr<2>_MC.D2_PT_2 )
  );
  X_AND2 \U4/ctrlr<2>_MC.D2_PT_3_1048  (
    .I0(DCORENCPWRr),
    .I1(\NlwInverterSignal_U4/ctrlr<2>_MC.D2_PT_3/IN1 ),
    .O(\U4/ctrlr<2>_MC.D2_PT_3 )
  );
  X_AND2 \U4/ctrlr<2>_MC.D2_PT_4_1049  (
    .I0(\NlwInverterSignal_U4/ctrlr<2>_MC.D2_PT_4/IN0 ),
    .I1(\NlwInverterSignal_U4/ctrlr<2>_MC.D2_PT_4/IN1 ),
    .O(\U4/ctrlr<2>_MC.D2_PT_4 )
  );
  X_AND2 \U4/ctrlr<2>_MC.D2_PT_5_1050  (
    .I0(\NlwInverterSignal_U4/ctrlr<2>_MC.D2_PT_5/IN0 ),
    .I1(\NlwInverterSignal_U4/ctrlr<2>_MC.D2_PT_5/IN1 ),
    .O(\U4/ctrlr<2>_MC.D2_PT_5 )
  );
  X_OR6 \U4/ctrlr<2>_MC.D2_1051  (
    .I0(\U4/ctrlr<2>_MC.D2_PT_0 ),
    .I1(\U4/ctrlr<2>_MC.D2_PT_1 ),
    .I2(\U4/ctrlr<2>_MC.D2_PT_2 ),
    .I3(\U4/ctrlr<2>_MC.D2_PT_3 ),
    .I4(\U4/ctrlr<2>_MC.D2_PT_4 ),
    .I5(\U4/ctrlr<2>_MC.D2_PT_5 ),
    .O(\U4/ctrlr<2>_MC.D2 )
  );
  X_BUF DCORENCPWRw_1052 (
    .I(\DCORENCPWRw_MC.Q ),
    .O(DCORENCPWRw)
  );
  X_BUF \DCORENCPWRw_MC.Q_1053  (
    .I(\DCORENCPWRw_MC.D ),
    .O(\DCORENCPWRw_MC.Q )
  );
  X_XOR2 \DCORENCPWRw_MC.D_1054  (
    .I0(\DCORENCPWRw_MC.D1 ),
    .I1(\DCORENCPWRw_MC.D2 ),
    .O(\DCORENCPWRw_MC.D )
  );
  X_AND16 \DCORENCPWRw_MC.D1_1055  (
    .I0(\NlwInverterSignal_DCORENCPWRw_MC.D1/IN0 ),
    .I1(\RD_II/UIM ),
    .I2(\NlwInverterSignal_DCORENCPWRw_MC.D1/IN2 ),
    .I3(\NlwInverterSignal_DCORENCPWRw_MC.D1/IN3 ),
    .I4(\NlwInverterSignal_DCORENCPWRw_MC.D1/IN4 ),
    .I5(\NlwInverterSignal_DCORENCPWRw_MC.D1/IN5 ),
    .I6(\NlwInverterSignal_DCORENCPWRw_MC.D1/IN6 ),
    .I7(U2_ADDR_reg[3]),
    .I8(U2_ADDR_reg[1]),
    .I9(U2_ADDR_reg[2]),
    .I10(Vcc),
    .I11(Vcc),
    .I12(Vcc),
    .I13(Vcc),
    .I14(Vcc),
    .I15(Vcc),
    .O(\DCORENCPWRw_MC.D1 )
  );
  X_ZERO \DCORENCPWRw_MC.D2_1056  (
    .O(\DCORENCPWRw_MC.D2 )
  );
  X_BUF \U4/ctrlr<3>_MC.Q_1057  (
    .I(\U4/ctrlr<3>_MC.D ),
    .O(\U4/ctrlr<3>_MC.Q )
  );
  X_BUF \U4/ctrlr<3>_MC.OE_1058  (
    .I(\U4/ctrlr<3>_MC.BUFOE.OUT ),
    .O(\U4/ctrlr<3>_MC.OE )
  );
  X_BUF \U4/ctrlr<3>_MC.BUFOE.OUT_1059  (
    .I(\FOOBAR1__ctinst/7 ),
    .O(\U4/ctrlr<3>_MC.BUFOE.OUT )
  );
  X_XOR2 \U4/ctrlr<3>_MC.D_1060  (
    .I0(\NlwInverterSignal_U4/ctrlr<3>_MC.D/IN0 ),
    .I1(\U4/ctrlr<3>_MC.D2 ),
    .O(\U4/ctrlr<3>_MC.D )
  );
  X_ZERO \U4/ctrlr<3>_MC.D1_1061  (
    .O(\U4/ctrlr<3>_MC.D1 )
  );
  X_AND2 \U4/ctrlr<3>_MC.D2_PT_0_1062  (
    .I0(DCORI2CCNTr),
    .I1(\NlwInverterSignal_U4/ctrlr<3>_MC.D2_PT_0/IN1 ),
    .O(\U4/ctrlr<3>_MC.D2_PT_0 )
  );
  X_AND2 \U4/ctrlr<3>_MC.D2_PT_1_1063  (
    .I0(DCORCONFIGr),
    .I1(\NlwInverterSignal_U4/ctrlr<3>_MC.D2_PT_1/IN1 ),
    .O(\U4/ctrlr<3>_MC.D2_PT_1 )
  );
  X_AND2 \U4/ctrlr<3>_MC.D2_PT_2_1064  (
    .I0(DCORLIMITSr),
    .I1(\NlwInverterSignal_U4/ctrlr<3>_MC.D2_PT_2/IN1 ),
    .O(\U4/ctrlr<3>_MC.D2_PT_2 )
  );
  X_AND2 \U4/ctrlr<3>_MC.D2_PT_3_1065  (
    .I0(DCORENCPWRr),
    .I1(\NlwInverterSignal_U4/ctrlr<3>_MC.D2_PT_3/IN1 ),
    .O(\U4/ctrlr<3>_MC.D2_PT_3 )
  );
  X_AND2 \U4/ctrlr<3>_MC.D2_PT_4_1066  (
    .I0(\NlwInverterSignal_U4/ctrlr<3>_MC.D2_PT_4/IN0 ),
    .I1(\NlwInverterSignal_U4/ctrlr<3>_MC.D2_PT_4/IN1 ),
    .O(\U4/ctrlr<3>_MC.D2_PT_4 )
  );
  X_AND2 \U4/ctrlr<3>_MC.D2_PT_5_1067  (
    .I0(\NlwInverterSignal_U4/ctrlr<3>_MC.D2_PT_5/IN0 ),
    .I1(\NlwInverterSignal_U4/ctrlr<3>_MC.D2_PT_5/IN1 ),
    .O(\U4/ctrlr<3>_MC.D2_PT_5 )
  );
  X_OR6 \U4/ctrlr<3>_MC.D2_1068  (
    .I0(\U4/ctrlr<3>_MC.D2_PT_0 ),
    .I1(\U4/ctrlr<3>_MC.D2_PT_1 ),
    .I2(\U4/ctrlr<3>_MC.D2_PT_2 ),
    .I3(\U4/ctrlr<3>_MC.D2_PT_3 ),
    .I4(\U4/ctrlr<3>_MC.D2_PT_4 ),
    .I5(\U4/ctrlr<3>_MC.D2_PT_5 ),
    .O(\U4/ctrlr<3>_MC.D2 )
  );
  X_BUF \Enc05ctrl_MC.Q_1069  (
    .I(\Enc05ctrl_MC.Q_tsimrenamed_net_ ),
    .O(\Enc05ctrl_MC.Q )
  );
  X_BUF \Enc05ctrl_MC.Q_tsimrenamed_net__1070  (
    .I(\Enc05ctrl_MC.D ),
    .O(\Enc05ctrl_MC.Q_tsimrenamed_net_ )
  );
  X_XOR2 \Enc05ctrl_MC.D_1071  (
    .I0(\NlwInverterSignal_Enc05ctrl_MC.D/IN0 ),
    .I1(\Enc05ctrl_MC.D2 ),
    .O(\Enc05ctrl_MC.D )
  );
  X_AND2 \Enc05ctrl_MC.D1_1072  (
    .I0(\NlwInverterSignal_Enc05ctrl_MC.D1/IN0 ),
    .I1(\U4/ctrlr[3] ),
    .O(\Enc05ctrl_MC.D1 )
  );
  X_ZERO \Enc05ctrl_MC.D2_1073  (
    .O(\Enc05ctrl_MC.D2 )
  );
  X_BUF \Enc133ctrl_MC.Q_1074  (
    .I(\Enc133ctrl_MC.Q_tsimrenamed_net_ ),
    .O(\Enc133ctrl_MC.Q )
  );
  X_BUF \Enc133ctrl_MC.Q_tsimrenamed_net__1075  (
    .I(\Enc133ctrl_MC.D ),
    .O(\Enc133ctrl_MC.Q_tsimrenamed_net_ )
  );
  X_XOR2 \Enc133ctrl_MC.D_1076  (
    .I0(\NlwInverterSignal_Enc133ctrl_MC.D/IN0 ),
    .I1(\Enc133ctrl_MC.D2 ),
    .O(\Enc133ctrl_MC.D )
  );
  X_AND2 \Enc133ctrl_MC.D1_1077  (
    .I0(\U4/ctrlr[6] ),
    .I1(\U4/ctrlr[7] ),
    .O(\Enc133ctrl_MC.D1 )
  );
  X_ZERO \Enc133ctrl_MC.D2_1078  (
    .O(\Enc133ctrl_MC.D2 )
  );
  X_BUF \U4/ctrlr<6>_MC.Q_1079  (
    .I(\U4/ctrlr<6>_MC.D ),
    .O(\U4/ctrlr<6>_MC.Q )
  );
  X_BUF \U4/ctrlr<6>_MC.OE_1080  (
    .I(\U4/ctrlr<6>_MC.BUFOE.OUT ),
    .O(\U4/ctrlr<6>_MC.OE )
  );
  X_BUF \U4/ctrlr<6>_MC.BUFOE.OUT_1081  (
    .I(\FOOBAR1__ctinst/7 ),
    .O(\U4/ctrlr<6>_MC.BUFOE.OUT )
  );
  X_XOR2 \U4/ctrlr<6>_MC.D_1082  (
    .I0(\NlwInverterSignal_U4/ctrlr<6>_MC.D/IN0 ),
    .I1(\U4/ctrlr<6>_MC.D2 ),
    .O(\U4/ctrlr<6>_MC.D )
  );
  X_ZERO \U4/ctrlr<6>_MC.D1_1083  (
    .O(\U4/ctrlr<6>_MC.D1 )
  );
  X_AND2 \U4/ctrlr<6>_MC.D2_PT_0_1084  (
    .I0(DCORI2CCNTr),
    .I1(\NlwInverterSignal_U4/ctrlr<6>_MC.D2_PT_0/IN1 ),
    .O(\U4/ctrlr<6>_MC.D2_PT_0 )
  );
  X_AND2 \U4/ctrlr<6>_MC.D2_PT_1_1085  (
    .I0(DCORCONFIGr),
    .I1(\NlwInverterSignal_U4/ctrlr<6>_MC.D2_PT_1/IN1 ),
    .O(\U4/ctrlr<6>_MC.D2_PT_1 )
  );
  X_AND2 \U4/ctrlr<6>_MC.D2_PT_2_1086  (
    .I0(DCORLIMITSr),
    .I1(\NlwInverterSignal_U4/ctrlr<6>_MC.D2_PT_2/IN1 ),
    .O(\U4/ctrlr<6>_MC.D2_PT_2 )
  );
  X_AND2 \U4/ctrlr<6>_MC.D2_PT_3_1087  (
    .I0(DCORENCPWRr),
    .I1(\NlwInverterSignal_U4/ctrlr<6>_MC.D2_PT_3/IN1 ),
    .O(\U4/ctrlr<6>_MC.D2_PT_3 )
  );
  X_AND2 \U4/ctrlr<6>_MC.D2_PT_4_1088  (
    .I0(\NlwInverterSignal_U4/ctrlr<6>_MC.D2_PT_4/IN0 ),
    .I1(\NlwInverterSignal_U4/ctrlr<6>_MC.D2_PT_4/IN1 ),
    .O(\U4/ctrlr<6>_MC.D2_PT_4 )
  );
  X_AND2 \U4/ctrlr<6>_MC.D2_PT_5_1089  (
    .I0(\NlwInverterSignal_U4/ctrlr<6>_MC.D2_PT_5/IN0 ),
    .I1(\NlwInverterSignal_U4/ctrlr<6>_MC.D2_PT_5/IN1 ),
    .O(\U4/ctrlr<6>_MC.D2_PT_5 )
  );
  X_OR6 \U4/ctrlr<6>_MC.D2_1090  (
    .I0(\U4/ctrlr<6>_MC.D2_PT_0 ),
    .I1(\U4/ctrlr<6>_MC.D2_PT_1 ),
    .I2(\U4/ctrlr<6>_MC.D2_PT_2 ),
    .I3(\U4/ctrlr<6>_MC.D2_PT_3 ),
    .I4(\U4/ctrlr<6>_MC.D2_PT_4 ),
    .I5(\U4/ctrlr<6>_MC.D2_PT_5 ),
    .O(\U4/ctrlr<6>_MC.D2 )
  );
  X_BUF \U4/ctrlr<7>_MC.Q_1091  (
    .I(\U4/ctrlr<7>_MC.D ),
    .O(\U4/ctrlr<7>_MC.Q )
  );
  X_BUF \U4/ctrlr<7>_MC.OE_1092  (
    .I(\U4/ctrlr<7>_MC.BUFOE.OUT ),
    .O(\U4/ctrlr<7>_MC.OE )
  );
  X_BUF \U4/ctrlr<7>_MC.BUFOE.OUT_1093  (
    .I(\FOOBAR1__ctinst/7 ),
    .O(\U4/ctrlr<7>_MC.BUFOE.OUT )
  );
  X_XOR2 \U4/ctrlr<7>_MC.D_1094  (
    .I0(\NlwInverterSignal_U4/ctrlr<7>_MC.D/IN0 ),
    .I1(\U4/ctrlr<7>_MC.D2 ),
    .O(\U4/ctrlr<7>_MC.D )
  );
  X_ZERO \U4/ctrlr<7>_MC.D1_1095  (
    .O(\U4/ctrlr<7>_MC.D1 )
  );
  X_AND2 \U4/ctrlr<7>_MC.D2_PT_0_1096  (
    .I0(DCORI2CCNTr),
    .I1(\NlwInverterSignal_U4/ctrlr<7>_MC.D2_PT_0/IN1 ),
    .O(\U4/ctrlr<7>_MC.D2_PT_0 )
  );
  X_AND2 \U4/ctrlr<7>_MC.D2_PT_1_1097  (
    .I0(DCORCONFIGr),
    .I1(\NlwInverterSignal_U4/ctrlr<7>_MC.D2_PT_1/IN1 ),
    .O(\U4/ctrlr<7>_MC.D2_PT_1 )
  );
  X_AND2 \U4/ctrlr<7>_MC.D2_PT_2_1098  (
    .I0(DCORLIMITSr),
    .I1(\NlwInverterSignal_U4/ctrlr<7>_MC.D2_PT_2/IN1 ),
    .O(\U4/ctrlr<7>_MC.D2_PT_2 )
  );
  X_AND2 \U4/ctrlr<7>_MC.D2_PT_3_1099  (
    .I0(DCORENCPWRr),
    .I1(\NlwInverterSignal_U4/ctrlr<7>_MC.D2_PT_3/IN1 ),
    .O(\U4/ctrlr<7>_MC.D2_PT_3 )
  );
  X_AND2 \U4/ctrlr<7>_MC.D2_PT_4_1100  (
    .I0(\NlwInverterSignal_U4/ctrlr<7>_MC.D2_PT_4/IN0 ),
    .I1(\NlwInverterSignal_U4/ctrlr<7>_MC.D2_PT_4/IN1 ),
    .O(\U4/ctrlr<7>_MC.D2_PT_4 )
  );
  X_AND2 \U4/ctrlr<7>_MC.D2_PT_5_1101  (
    .I0(\NlwInverterSignal_U4/ctrlr<7>_MC.D2_PT_5/IN0 ),
    .I1(DCORIFGr),
    .O(\U4/ctrlr<7>_MC.D2_PT_5 )
  );
  X_AND2 \U4/ctrlr<7>_MC.D2_PT_6_1102  (
    .I0(DCOR0THRESLOWr),
    .I1(\NlwInverterSignal_U4/ctrlr<7>_MC.D2_PT_6/IN1 ),
    .O(\U4/ctrlr<7>_MC.D2_PT_6 )
  );
  X_AND3 \U4/ctrlr<7>_MC.D2_PT_7_1103  (
    .I0(\NlwInverterSignal_U4/ctrlr<7>_MC.D2_PT_7/IN0 ),
    .I1(\NlwInverterSignal_U4/ctrlr<7>_MC.D2_PT_7/IN1 ),
    .I2(\NlwInverterSignal_U4/ctrlr<7>_MC.D2_PT_7/IN2 ),
    .O(\U4/ctrlr<7>_MC.D2_PT_7 )
  );
  X_OR8 \U4/ctrlr<7>_MC.D2_1104  (
    .I0(\U4/ctrlr<7>_MC.D2_PT_0 ),
    .I1(\U4/ctrlr<7>_MC.D2_PT_1 ),
    .I2(\U4/ctrlr<7>_MC.D2_PT_2 ),
    .I3(\U4/ctrlr<7>_MC.D2_PT_3 ),
    .I4(\U4/ctrlr<7>_MC.D2_PT_4 ),
    .I5(\U4/ctrlr<7>_MC.D2_PT_5 ),
    .I6(\U4/ctrlr<7>_MC.D2_PT_6 ),
    .I7(\U4/ctrlr<7>_MC.D2_PT_7 ),
    .O(\U4/ctrlr<7>_MC.D2 )
  );
  X_BUF \Enc15ctrl_MC.Q_1105  (
    .I(\Enc15ctrl_MC.Q_tsimrenamed_net_ ),
    .O(\Enc15ctrl_MC.Q )
  );
  X_BUF \Enc15ctrl_MC.Q_tsimrenamed_net__1106  (
    .I(\Enc15ctrl_MC.D ),
    .O(\Enc15ctrl_MC.Q_tsimrenamed_net_ )
  );
  X_XOR2 \Enc15ctrl_MC.D_1107  (
    .I0(\NlwInverterSignal_Enc15ctrl_MC.D/IN0 ),
    .I1(\Enc15ctrl_MC.D2 ),
    .O(\Enc15ctrl_MC.D )
  );
  X_AND2 \Enc15ctrl_MC.D1_1108  (
    .I0(\NlwInverterSignal_Enc15ctrl_MC.D1/IN0 ),
    .I1(\U4/ctrlr[7] ),
    .O(\Enc15ctrl_MC.D1 )
  );
  X_ZERO \Enc15ctrl_MC.D2_1109  (
    .O(\Enc15ctrl_MC.D2 )
  );
  X_BUF \GPIO8_MC.Q_1110  (
    .I(\GPIO8_MC.Q_tsimrenamed_net_ ),
    .O(\GPIO8_MC.Q )
  );
  X_BUF \GPIO8_MC.Q_tsimrenamed_net__1111  (
    .I(\GPIO8_MC.D ),
    .O(\GPIO8_MC.Q_tsimrenamed_net_ )
  );
  X_XOR2 \GPIO8_MC.D_1112  (
    .I0(\GPIO8_MC.D1 ),
    .I1(\GPIO8_MC.D2 ),
    .O(\GPIO8_MC.D )
  );
  X_AND2 \GPIO8_MC.D1_1113  (
    .I0(\PWM5_II/UIM ),
    .I1(\PWM5_II/UIM ),
    .O(\GPIO8_MC.D1 )
  );
  X_ZERO \GPIO8_MC.D2_1114  (
    .O(\GPIO8_MC.D2 )
  );
  X_BUF \GPIO9_MC.Q_1115  (
    .I(\GPIO9_MC.Q_tsimrenamed_net_ ),
    .O(\GPIO9_MC.Q )
  );
  X_BUF \GPIO9_MC.Q_tsimrenamed_net__1116  (
    .I(\GPIO9_MC.D ),
    .O(\GPIO9_MC.Q_tsimrenamed_net_ )
  );
  X_XOR2 \GPIO9_MC.D_1117  (
    .I0(\GPIO9_MC.D1 ),
    .I1(\GPIO9_MC.D2 ),
    .O(\GPIO9_MC.D )
  );
  X_AND2 \GPIO9_MC.D1_1118  (
    .I0(\PWM3_II/UIM ),
    .I1(\PWM3_II/UIM ),
    .O(\GPIO9_MC.D1 )
  );
  X_ZERO \GPIO9_MC.D2_1119  (
    .O(\GPIO9_MC.D2 )
  );
  X_BUF \GP_Motor0_1_MC.Q_1120  (
    .I(\GP_Motor0_1_MC.Q_tsimrenamed_net_ ),
    .O(\GP_Motor0_1_MC.Q )
  );
  X_OR2 GP_Motor0_1_MC_tsimcreated_prld__1121 (
    .I0(\FOOBAR3__ctinst/7 ),
    .I1(PRLD),
    .O(GP_Motor0_1_MC_tsimcreated_prld_)
  );
  X_FF \GP_Motor0_1_MC.REG  (
    .I(\GP_Motor0_1_MC.D ),
    .CE(\FOOBAR8__ctinst/4 ),
    .CLK(\GP_Motor0_1_MC.REG_tsimcreated_inv_Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(GP_Motor0_1_MC_tsimcreated_prld_),
    .O(\GP_Motor0_1_MC.Q_tsimrenamed_net_ )
  );
  X_INV \GP_Motor0_1_MC.REG_tsimcreated_inv_Mclk_II/FCLK_1122  (
    .I(\Mclk_II/FCLK ),
    .O(\GP_Motor0_1_MC.REG_tsimcreated_inv_Mclk_II/FCLK )
  );
  X_XOR2 \GP_Motor0_1_MC.D_1123  (
    .I0(\GP_Motor0_1_MC.D1 ),
    .I1(\GP_Motor0_1_MC.D2 ),
    .O(\GP_Motor0_1_MC.D )
  );
  X_AND2 \GP_Motor0_1_MC.D1_1124  (
    .I0(\AD<6>_II/UIM ),
    .I1(\AD<6>_II/UIM ),
    .O(\GP_Motor0_1_MC.D1 )
  );
  X_ZERO \GP_Motor0_1_MC.D2_1125  (
    .O(\GP_Motor0_1_MC.D2 )
  );
  X_BUF DCOROUTw_1126 (
    .I(\DCOROUTw_MC.Q ),
    .O(DCOROUTw)
  );
  X_BUF \DCOROUTw_MC.Q_1127  (
    .I(\DCOROUTw_MC.D ),
    .O(\DCOROUTw_MC.Q )
  );
  X_XOR2 \DCOROUTw_MC.D_1128  (
    .I0(\DCOROUTw_MC.D1 ),
    .I1(\DCOROUTw_MC.D2 ),
    .O(\DCOROUTw_MC.D )
  );
  X_AND16 \DCOROUTw_MC.D1_1129  (
    .I0(\NlwInverterSignal_DCOROUTw_MC.D1/IN0 ),
    .I1(\RD_II/UIM ),
    .I2(U2_ADDR_reg[0]),
    .I3(\NlwInverterSignal_DCOROUTw_MC.D1/IN3 ),
    .I4(\NlwInverterSignal_DCOROUTw_MC.D1/IN4 ),
    .I5(\NlwInverterSignal_DCOROUTw_MC.D1/IN5 ),
    .I6(\NlwInverterSignal_DCOROUTw_MC.D1/IN6 ),
    .I7(U2_ADDR_reg[3]),
    .I8(U2_ADDR_reg[1]),
    .I9(U2_ADDR_reg[2]),
    .I10(Vcc),
    .I11(Vcc),
    .I12(Vcc),
    .I13(Vcc),
    .I14(Vcc),
    .I15(Vcc),
    .O(\DCOROUTw_MC.D1 )
  );
  X_ZERO \DCOROUTw_MC.D2_1130  (
    .O(\DCOROUTw_MC.D2 )
  );
  X_BUF \GP_Motor1_1_MC.Q_1131  (
    .I(\GP_Motor1_1_MC.Q_tsimrenamed_net_ ),
    .O(\GP_Motor1_1_MC.Q )
  );
  X_OR2 GP_Motor1_1_MC_tsimcreated_prld__1132 (
    .I0(\FOOBAR3__ctinst/7 ),
    .I1(PRLD),
    .O(GP_Motor1_1_MC_tsimcreated_prld_)
  );
  X_FF \GP_Motor1_1_MC.REG  (
    .I(\GP_Motor1_1_MC.D ),
    .CE(\FOOBAR15__ctinst/4 ),
    .CLK(\GP_Motor1_1_MC.REG_tsimcreated_inv_Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(GP_Motor1_1_MC_tsimcreated_prld_),
    .O(\GP_Motor1_1_MC.Q_tsimrenamed_net_ )
  );
  X_INV \GP_Motor1_1_MC.REG_tsimcreated_inv_Mclk_II/FCLK_1133  (
    .I(\Mclk_II/FCLK ),
    .O(\GP_Motor1_1_MC.REG_tsimcreated_inv_Mclk_II/FCLK )
  );
  X_XOR2 \GP_Motor1_1_MC.D_1134  (
    .I0(\GP_Motor1_1_MC.D1 ),
    .I1(\GP_Motor1_1_MC.D2 ),
    .O(\GP_Motor1_1_MC.D )
  );
  X_AND2 \GP_Motor1_1_MC.D1_1135  (
    .I0(\AD<7>_II/UIM ),
    .I1(\AD<7>_II/UIM ),
    .O(\GP_Motor1_1_MC.D1 )
  );
  X_ZERO \GP_Motor1_1_MC.D2_1136  (
    .O(\GP_Motor1_1_MC.D2 )
  );
  X_BUF \HSO_MC.Q_1137  (
    .I(\HSO_MC.Q_tsimrenamed_net_ ),
    .O(\HSO_MC.Q )
  );
  X_BUF \HSO_MC.Q_tsimrenamed_net__1138  (
    .I(\HSO_MC.D ),
    .O(\HSO_MC.Q_tsimrenamed_net_ )
  );
  X_XOR2 \HSO_MC.D_1139  (
    .I0(\HSO_MC.D1 ),
    .I1(\HSO_MC.D2 ),
    .O(\HSO_MC.D )
  );
  X_AND2 \HSO_MC.D1_1140  (
    .I0(\MHSO_II/UIM ),
    .I1(\MHSO_II/UIM ),
    .O(\HSO_MC.D1 )
  );
  X_ZERO \HSO_MC.D2_1141  (
    .O(\HSO_MC.D2 )
  );
  X_BUF \Home033ctrl_MC.Q_1142  (
    .I(\Home033ctrl_MC.Q_tsimrenamed_net_ ),
    .O(\Home033ctrl_MC.Q )
  );
  X_OR2 Home033ctrl_MC_tsimcreated_prld__1143 (
    .I0(\FOOBAR2__ctinst/7 ),
    .I1(PRLD),
    .O(Home033ctrl_MC_tsimcreated_prld_)
  );
  X_FF \Home033ctrl_MC.REG  (
    .I(\Home033ctrl_MC.D ),
    .CE(\Home033ctrl_MC.CE ),
    .CLK(\Home033ctrl_MC.REG_tsimcreated_inv_Mclk_II/FCLK ),
    .SET(Home033ctrl_MC_tsimcreated_prld_),
    .RST(Gnd),
    .O(\Home033ctrl_MC.Q_tsimrenamed_net_ )
  );
  X_INV \Home033ctrl_MC.REG_tsimcreated_inv_Mclk_II/FCLK_1144  (
    .I(\Mclk_II/FCLK ),
    .O(\Home033ctrl_MC.REG_tsimcreated_inv_Mclk_II/FCLK )
  );
  X_XOR2 \Home033ctrl_MC.D_1145  (
    .I0(\NlwInverterSignal_Home033ctrl_MC.D/IN0 ),
    .I1(\Home033ctrl_MC.D2 ),
    .O(\Home033ctrl_MC.D )
  );
  X_AND2 \Home033ctrl_MC.D1_1146  (
    .I0(\AD<0>_II/UIM ),
    .I1(\AD<0>_II/UIM ),
    .O(\Home033ctrl_MC.D1 )
  );
  X_ZERO \Home033ctrl_MC.D2_1147  (
    .O(\Home033ctrl_MC.D2 )
  );
  X_AND2 \Home033ctrl_MC.CE_1148  (
    .I0(DCORENCPWRw),
    .I1(DCORENCPWRw),
    .O(\Home033ctrl_MC.CE )
  );
  X_BUF \Home05ctrl_MC.Q_1149  (
    .I(\Home05ctrl_MC.Q_tsimrenamed_net_ ),
    .O(\Home05ctrl_MC.Q )
  );
  X_OR2 Home05ctrl_MC_tsimcreated_prld__1150 (
    .I0(\FOOBAR2__ctinst/7 ),
    .I1(PRLD),
    .O(Home05ctrl_MC_tsimcreated_prld_)
  );
  X_FF \Home05ctrl_MC.REG  (
    .I(\Home05ctrl_MC.D ),
    .CE(\FOOBAR14__ctinst/4 ),
    .CLK(\Home05ctrl_MC.REG_tsimcreated_inv_Mclk_II/FCLK ),
    .SET(Home05ctrl_MC_tsimcreated_prld_),
    .RST(Gnd),
    .O(\Home05ctrl_MC.Q_tsimrenamed_net_ )
  );
  X_INV \Home05ctrl_MC.REG_tsimcreated_inv_Mclk_II/FCLK_1151  (
    .I(\Mclk_II/FCLK ),
    .O(\Home05ctrl_MC.REG_tsimcreated_inv_Mclk_II/FCLK )
  );
  X_XOR2 \Home05ctrl_MC.D_1152  (
    .I0(\NlwInverterSignal_Home05ctrl_MC.D/IN0 ),
    .I1(\Home05ctrl_MC.D2 ),
    .O(\Home05ctrl_MC.D )
  );
  X_AND2 \Home05ctrl_MC.D1_1153  (
    .I0(\AD<1>_II/UIM ),
    .I1(\AD<1>_II/UIM ),
    .O(\Home05ctrl_MC.D1 )
  );
  X_ZERO \Home05ctrl_MC.D2_1154  (
    .O(\Home05ctrl_MC.D2 )
  );
  X_BUF \Home133ctrl_MC.Q_1155  (
    .I(\Home133ctrl_MC.Q_tsimrenamed_net_ ),
    .O(\Home133ctrl_MC.Q )
  );
  X_OR2 Home133ctrl_MC_tsimcreated_prld__1156 (
    .I0(\FOOBAR2__ctinst/7 ),
    .I1(PRLD),
    .O(Home133ctrl_MC_tsimcreated_prld_)
  );
  X_FF \Home133ctrl_MC.REG  (
    .I(\Home133ctrl_MC.D ),
    .CE(\FOOBAR23__ctinst/4 ),
    .CLK(\Home133ctrl_MC.REG_tsimcreated_inv_Mclk_II/FCLK ),
    .SET(Home133ctrl_MC_tsimcreated_prld_),
    .RST(Gnd),
    .O(\Home133ctrl_MC.Q_tsimrenamed_net_ )
  );
  X_INV \Home133ctrl_MC.REG_tsimcreated_inv_Mclk_II/FCLK_1157  (
    .I(\Mclk_II/FCLK ),
    .O(\Home133ctrl_MC.REG_tsimcreated_inv_Mclk_II/FCLK )
  );
  X_XOR2 \Home133ctrl_MC.D_1158  (
    .I0(\NlwInverterSignal_Home133ctrl_MC.D/IN0 ),
    .I1(\Home133ctrl_MC.D2 ),
    .O(\Home133ctrl_MC.D )
  );
  X_AND2 \Home133ctrl_MC.D1_1159  (
    .I0(\AD<4>_II/UIM ),
    .I1(\AD<4>_II/UIM ),
    .O(\Home133ctrl_MC.D1 )
  );
  X_ZERO \Home133ctrl_MC.D2_1160  (
    .O(\Home133ctrl_MC.D2 )
  );
  X_BUF \Home15ctrl_MC.Q_1161  (
    .I(\Home15ctrl_MC.Q_tsimrenamed_net_ ),
    .O(\Home15ctrl_MC.Q )
  );
  X_OR2 Home15ctrl_MC_tsimcreated_prld__1162 (
    .I0(\FOOBAR2__ctinst/7 ),
    .I1(PRLD),
    .O(Home15ctrl_MC_tsimcreated_prld_)
  );
  X_FF \Home15ctrl_MC.REG  (
    .I(\Home15ctrl_MC.D ),
    .CE(\Home15ctrl_MC.CE ),
    .CLK(\Home15ctrl_MC.REG_tsimcreated_inv_Mclk_II/FCLK ),
    .SET(Home15ctrl_MC_tsimcreated_prld_),
    .RST(Gnd),
    .O(\Home15ctrl_MC.Q_tsimrenamed_net_ )
  );
  X_INV \Home15ctrl_MC.REG_tsimcreated_inv_Mclk_II/FCLK_1163  (
    .I(\Mclk_II/FCLK ),
    .O(\Home15ctrl_MC.REG_tsimcreated_inv_Mclk_II/FCLK )
  );
  X_XOR2 \Home15ctrl_MC.D_1164  (
    .I0(\NlwInverterSignal_Home15ctrl_MC.D/IN0 ),
    .I1(\Home15ctrl_MC.D2 ),
    .O(\Home15ctrl_MC.D )
  );
  X_AND2 \Home15ctrl_MC.D1_1165  (
    .I0(\AD<5>_II/UIM ),
    .I1(\AD<5>_II/UIM ),
    .O(\Home15ctrl_MC.D1 )
  );
  X_ZERO \Home15ctrl_MC.D2_1166  (
    .O(\Home15ctrl_MC.D2 )
  );
  X_AND2 \Home15ctrl_MC.CE_1167  (
    .I0(DCORENCPWRw),
    .I1(DCORENCPWRw),
    .O(\Home15ctrl_MC.CE )
  );
  X_BUF \INT_MC.Q_1168  (
    .I(\INT_MC.Q_tsimrenamed_net_ ),
    .O(\INT_MC.Q )
  );
  X_BUF \INT_MC.Q_tsimrenamed_net__1169  (
    .I(\INT_MC.D ),
    .O(\INT_MC.Q_tsimrenamed_net_ )
  );
  X_XOR2 \INT_MC.D_1170  (
    .I0(\INT_MC.D1 ),
    .I1(\INT_MC.D2 ),
    .O(\INT_MC.D )
  );
  X_ZERO \INT_MC.D1_1171  (
    .O(\INT_MC.D1 )
  );
  X_AND2 \INT_MC.D2_PT_0_1172  (
    .I0(\TP12_MC.UIM ),
    .I1(\U3/DCORIE [7]),
    .O(\INT_MC.D2_PT_0 )
  );
  X_AND2 \INT_MC.D2_PT_1_1173  (
    .I0(NET2528),
    .I1(\U3/DCORIE [1]),
    .O(\INT_MC.D2_PT_1 )
  );
  X_AND2 \INT_MC.D2_PT_2_1174  (
    .I0(NET2482),
    .I1(\U3/DCORIE [2]),
    .O(\INT_MC.D2_PT_2 )
  );
  X_AND2 \INT_MC.D2_PT_3_1175  (
    .I0(NET2493),
    .I1(\U3/DCORIE [3]),
    .O(\INT_MC.D2_PT_3 )
  );
  X_AND2 \INT_MC.D2_PT_4_1176  (
    .I0(NET2501),
    .I1(\U3/DCORIE [5]),
    .O(\INT_MC.D2_PT_4 )
  );
  X_AND2 \INT_MC.D2_PT_5_1177  (
    .I0(NET2512),
    .I1(\U3/DCORIE [6]),
    .O(\INT_MC.D2_PT_5 )
  );
  X_AND2 \INT_MC.D2_PT_6_1178  (
    .I0(\NlwInverterSignal_INT_MC.D2_PT_6/IN0 ),
    .I1(\U3/DCORIE [0]),
    .O(\INT_MC.D2_PT_6 )
  );
  X_AND2 \INT_MC.D2_PT_7_1179  (
    .I0(NET2575),
    .I1(\U3/DCORIE [4]),
    .O(\INT_MC.D2_PT_7 )
  );
  X_OR8 \INT_MC.D2_1180  (
    .I0(\INT_MC.D2_PT_0 ),
    .I1(\INT_MC.D2_PT_1 ),
    .I2(\INT_MC.D2_PT_2 ),
    .I3(\INT_MC.D2_PT_3 ),
    .I4(\INT_MC.D2_PT_4 ),
    .I5(\INT_MC.D2_PT_5 ),
    .I6(\INT_MC.D2_PT_6 ),
    .I7(\INT_MC.D2_PT_7 ),
    .O(\INT_MC.D2 )
  );
  X_BUF \U3/DCORIE<0>  (
    .I(\U3/DCORIE<0>_MC.Q ),
    .O(\U3/DCORIE [0])
  );
  X_FF \U3/DCORIE<0>_MC.REG  (
    .I(\U3/DCORIE<0>_MC.D ),
    .CE(Vcc),
    .CLK(\U3/DCORIE<0>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\U3/DCORIE<0>_MC.Q )
  );
  X_INV \U3/DCORIE<0>_MC.REG_tsimcreated_inv_Mclk_II/FCLK_1181  (
    .I(\Mclk_II/FCLK ),
    .O(\U3/DCORIE<0>_MC.REG_tsimcreated_inv_Mclk_II/FCLK )
  );
  X_XOR2 \U3/DCORIE<0>_MC.D_1182  (
    .I0(\U3/DCORIE<0>_MC.D1 ),
    .I1(\U3/DCORIE<0>_MC.D2 ),
    .O(\U3/DCORIE<0>_MC.D )
  );
  X_ZERO \U3/DCORIE<0>_MC.D1_1183  (
    .O(\U3/DCORIE<0>_MC.D1 )
  );
  X_AND3 \U3/DCORIE<0>_MC.D2_PT_0_1184  (
    .I0(\MSPReset_II/UIM ),
    .I1(\AD<0>_II/UIM ),
    .I2(DCORIEw),
    .O(\U3/DCORIE<0>_MC.D2_PT_0 )
  );
  X_AND3 \U3/DCORIE<0>_MC.D2_PT_1_1185  (
    .I0(\MSPReset_II/UIM ),
    .I1(\U3/DCORIE [0]),
    .I2(\NlwInverterSignal_U3/DCORIE<0>_MC.D2_PT_1/IN2 ),
    .O(\U3/DCORIE<0>_MC.D2_PT_1 )
  );
  X_OR2 \U3/DCORIE<0>_MC.D2_1186  (
    .I0(\U3/DCORIE<0>_MC.D2_PT_0 ),
    .I1(\U3/DCORIE<0>_MC.D2_PT_1 ),
    .O(\U3/DCORIE<0>_MC.D2 )
  );
  X_BUF DCORIEw_1187 (
    .I(\DCORIEw_MC.Q ),
    .O(DCORIEw)
  );
  X_BUF \DCORIEw_MC.Q_1188  (
    .I(\DCORIEw_MC.D ),
    .O(\DCORIEw_MC.Q )
  );
  X_XOR2 \DCORIEw_MC.D_1189  (
    .I0(\DCORIEw_MC.D1 ),
    .I1(\DCORIEw_MC.D2 ),
    .O(\DCORIEw_MC.D )
  );
  X_AND16 \DCORIEw_MC.D1_1190  (
    .I0(\NlwInverterSignal_DCORIEw_MC.D1/IN0 ),
    .I1(\RD_II/UIM ),
    .I2(\NlwInverterSignal_DCORIEw_MC.D1/IN2 ),
    .I3(\NlwInverterSignal_DCORIEw_MC.D1/IN3 ),
    .I4(\NlwInverterSignal_DCORIEw_MC.D1/IN4 ),
    .I5(\NlwInverterSignal_DCORIEw_MC.D1/IN5 ),
    .I6(\NlwInverterSignal_DCORIEw_MC.D1/IN6 ),
    .I7(\NlwInverterSignal_DCORIEw_MC.D1/IN7 ),
    .I8(\NlwInverterSignal_DCORIEw_MC.D1/IN8 ),
    .I9(\NlwInverterSignal_DCORIEw_MC.D1/IN9 ),
    .I10(Vcc),
    .I11(Vcc),
    .I12(Vcc),
    .I13(Vcc),
    .I14(Vcc),
    .I15(Vcc),
    .O(\DCORIEw_MC.D1 )
  );
  X_ZERO \DCORIEw_MC.D2_1191  (
    .O(\DCORIEw_MC.D2 )
  );
  X_BUF \U3/DCORIE<1>  (
    .I(\U3/DCORIE<1>_MC.Q ),
    .O(\U3/DCORIE [1])
  );
  X_FF \U3/DCORIE<1>_MC.REG  (
    .I(\U3/DCORIE<1>_MC.D ),
    .CE(Vcc),
    .CLK(\U3/DCORIE<1>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\U3/DCORIE<1>_MC.Q )
  );
  X_INV \U3/DCORIE<1>_MC.REG_tsimcreated_inv_Mclk_II/FCLK_1192  (
    .I(\Mclk_II/FCLK ),
    .O(\U3/DCORIE<1>_MC.REG_tsimcreated_inv_Mclk_II/FCLK )
  );
  X_XOR2 \U3/DCORIE<1>_MC.D_1193  (
    .I0(\U3/DCORIE<1>_MC.D1 ),
    .I1(\U3/DCORIE<1>_MC.D2 ),
    .O(\U3/DCORIE<1>_MC.D )
  );
  X_ZERO \U3/DCORIE<1>_MC.D1_1194  (
    .O(\U3/DCORIE<1>_MC.D1 )
  );
  X_AND3 \U3/DCORIE<1>_MC.D2_PT_0_1195  (
    .I0(\MSPReset_II/UIM ),
    .I1(\AD<1>_II/UIM ),
    .I2(DCORIEw),
    .O(\U3/DCORIE<1>_MC.D2_PT_0 )
  );
  X_AND3 \U3/DCORIE<1>_MC.D2_PT_1_1196  (
    .I0(\MSPReset_II/UIM ),
    .I1(\U3/DCORIE [1]),
    .I2(\NlwInverterSignal_U3/DCORIE<1>_MC.D2_PT_1/IN2 ),
    .O(\U3/DCORIE<1>_MC.D2_PT_1 )
  );
  X_OR2 \U3/DCORIE<1>_MC.D2_1197  (
    .I0(\U3/DCORIE<1>_MC.D2_PT_0 ),
    .I1(\U3/DCORIE<1>_MC.D2_PT_1 ),
    .O(\U3/DCORIE<1>_MC.D2 )
  );
  X_BUF \U3/DCORIE<2>  (
    .I(\U3/DCORIE<2>_MC.Q ),
    .O(\U3/DCORIE [2])
  );
  X_FF \U3/DCORIE<2>_MC.REG  (
    .I(\U3/DCORIE<2>_MC.D ),
    .CE(Vcc),
    .CLK(\U3/DCORIE<2>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\U3/DCORIE<2>_MC.Q )
  );
  X_INV \U3/DCORIE<2>_MC.REG_tsimcreated_inv_Mclk_II/FCLK_1198  (
    .I(\Mclk_II/FCLK ),
    .O(\U3/DCORIE<2>_MC.REG_tsimcreated_inv_Mclk_II/FCLK )
  );
  X_XOR2 \U3/DCORIE<2>_MC.D_1199  (
    .I0(\U3/DCORIE<2>_MC.D1 ),
    .I1(\U3/DCORIE<2>_MC.D2 ),
    .O(\U3/DCORIE<2>_MC.D )
  );
  X_ZERO \U3/DCORIE<2>_MC.D1_1200  (
    .O(\U3/DCORIE<2>_MC.D1 )
  );
  X_AND3 \U3/DCORIE<2>_MC.D2_PT_0_1201  (
    .I0(\MSPReset_II/UIM ),
    .I1(\AD<2>_II/UIM ),
    .I2(DCORIEw),
    .O(\U3/DCORIE<2>_MC.D2_PT_0 )
  );
  X_AND3 \U3/DCORIE<2>_MC.D2_PT_1_1202  (
    .I0(\MSPReset_II/UIM ),
    .I1(\U3/DCORIE [2]),
    .I2(\NlwInverterSignal_U3/DCORIE<2>_MC.D2_PT_1/IN2 ),
    .O(\U3/DCORIE<2>_MC.D2_PT_1 )
  );
  X_OR2 \U3/DCORIE<2>_MC.D2_1203  (
    .I0(\U3/DCORIE<2>_MC.D2_PT_0 ),
    .I1(\U3/DCORIE<2>_MC.D2_PT_1 ),
    .O(\U3/DCORIE<2>_MC.D2 )
  );
  X_BUF \U3/DCORIE<3>  (
    .I(\U3/DCORIE<3>_MC.Q ),
    .O(\U3/DCORIE [3])
  );
  X_FF \U3/DCORIE<3>_MC.REG  (
    .I(\U3/DCORIE<3>_MC.D ),
    .CE(Vcc),
    .CLK(\U3/DCORIE<3>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\U3/DCORIE<3>_MC.Q )
  );
  X_INV \U3/DCORIE<3>_MC.REG_tsimcreated_inv_Mclk_II/FCLK_1204  (
    .I(\Mclk_II/FCLK ),
    .O(\U3/DCORIE<3>_MC.REG_tsimcreated_inv_Mclk_II/FCLK )
  );
  X_XOR2 \U3/DCORIE<3>_MC.D_1205  (
    .I0(\U3/DCORIE<3>_MC.D1 ),
    .I1(\U3/DCORIE<3>_MC.D2 ),
    .O(\U3/DCORIE<3>_MC.D )
  );
  X_ZERO \U3/DCORIE<3>_MC.D1_1206  (
    .O(\U3/DCORIE<3>_MC.D1 )
  );
  X_AND3 \U3/DCORIE<3>_MC.D2_PT_0_1207  (
    .I0(\MSPReset_II/UIM ),
    .I1(\AD<3>_II/UIM ),
    .I2(DCORIEw),
    .O(\U3/DCORIE<3>_MC.D2_PT_0 )
  );
  X_AND3 \U3/DCORIE<3>_MC.D2_PT_1_1208  (
    .I0(\MSPReset_II/UIM ),
    .I1(\U3/DCORIE [3]),
    .I2(\NlwInverterSignal_U3/DCORIE<3>_MC.D2_PT_1/IN2 ),
    .O(\U3/DCORIE<3>_MC.D2_PT_1 )
  );
  X_OR2 \U3/DCORIE<3>_MC.D2_1209  (
    .I0(\U3/DCORIE<3>_MC.D2_PT_0 ),
    .I1(\U3/DCORIE<3>_MC.D2_PT_1 ),
    .O(\U3/DCORIE<3>_MC.D2 )
  );
  X_BUF NET2575_1210 (
    .I(\NET2575_MC.Q ),
    .O(NET2575)
  );
  X_FF \NET2575_MC.REG  (
    .I(\NET2575_MC.D ),
    .CE(Vcc),
    .CLK(\NET2575_MC.REG_tsimcreated_inv_Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\NET2575_MC.Q )
  );
  X_INV \NET2575_MC.REG_tsimcreated_inv_Mclk_II/FCLK_1211  (
    .I(\Mclk_II/FCLK ),
    .O(\NET2575_MC.REG_tsimcreated_inv_Mclk_II/FCLK )
  );
  X_XOR2 \NET2575_MC.D_1212  (
    .I0(\NET2575_MC.D1 ),
    .I1(\NET2575_MC.D2 ),
    .O(\NET2575_MC.D )
  );
  X_ZERO \NET2575_MC.D1_1213  (
    .O(\NET2575_MC.D1 )
  );
  X_AND3 \NET2575_MC.D2_PT_0_1214  (
    .I0(\MSPReset_II/UIM ),
    .I1(\NlwInverterSignal_NET2575_MC.D2_PT_0/IN1 ),
    .I2(NET2575),
    .O(\NET2575_MC.D2_PT_0 )
  );
  X_AND3 \NET2575_MC.D2_PT_1_1215  (
    .I0(\MSPReset_II/UIM ),
    .I1(\NlwInverterSignal_NET2575_MC.D2_PT_1/IN1 ),
    .I2(\DIR1_II/UIM ),
    .O(\NET2575_MC.D2_PT_1 )
  );
  X_AND3 \NET2575_MC.D2_PT_2_1216  (
    .I0(\MSPReset_II/UIM ),
    .I1(\NlwInverterSignal_NET2575_MC.D2_PT_2/IN1 ),
    .I2(NET2575),
    .O(\NET2575_MC.D2_PT_2 )
  );
  X_AND3 \NET2575_MC.D2_PT_3_1217  (
    .I0(\MSPReset_II/UIM ),
    .I1(\DIR0_II/UIM ),
    .I2(\NlwInverterSignal_NET2575_MC.D2_PT_3/IN2 ),
    .O(\NET2575_MC.D2_PT_3 )
  );
  X_AND3 \NET2575_MC.D2_PT_4_1218  (
    .I0(\MSPReset_II/UIM ),
    .I1(\NlwInverterSignal_NET2575_MC.D2_PT_4/IN1 ),
    .I2(\NlwInverterSignal_NET2575_MC.D2_PT_4/IN2 ),
    .O(\NET2575_MC.D2_PT_4 )
  );
  X_AND3 \NET2575_MC.D2_PT_5_1219  (
    .I0(\MSPReset_II/UIM ),
    .I1(\NlwInverterSignal_NET2575_MC.D2_PT_5/IN1 ),
    .I2(\NlwInverterSignal_NET2575_MC.D2_PT_5/IN2 ),
    .O(\NET2575_MC.D2_PT_5 )
  );
  X_OR6 \NET2575_MC.D2_1220  (
    .I0(\NET2575_MC.D2_PT_0 ),
    .I1(\NET2575_MC.D2_PT_1 ),
    .I2(\NET2575_MC.D2_PT_2 ),
    .I3(\NET2575_MC.D2_PT_3 ),
    .I4(\NET2575_MC.D2_PT_4 ),
    .I5(\NET2575_MC.D2_PT_5 ),
    .O(\NET2575_MC.D2 )
  );
  X_BUF \U3/DCORIE<4>  (
    .I(\U3/DCORIE<4>_MC.Q ),
    .O(\U3/DCORIE [4])
  );
  X_FF \U3/DCORIE<4>_MC.REG  (
    .I(\U3/DCORIE<4>_MC.D ),
    .CE(Vcc),
    .CLK(\U3/DCORIE<4>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\U3/DCORIE<4>_MC.Q )
  );
  X_INV \U3/DCORIE<4>_MC.REG_tsimcreated_inv_Mclk_II/FCLK_1221  (
    .I(\Mclk_II/FCLK ),
    .O(\U3/DCORIE<4>_MC.REG_tsimcreated_inv_Mclk_II/FCLK )
  );
  X_XOR2 \U3/DCORIE<4>_MC.D_1222  (
    .I0(\U3/DCORIE<4>_MC.D1 ),
    .I1(\U3/DCORIE<4>_MC.D2 ),
    .O(\U3/DCORIE<4>_MC.D )
  );
  X_ZERO \U3/DCORIE<4>_MC.D1_1223  (
    .O(\U3/DCORIE<4>_MC.D1 )
  );
  X_AND3 \U3/DCORIE<4>_MC.D2_PT_0_1224  (
    .I0(\MSPReset_II/UIM ),
    .I1(\AD<4>_II/UIM ),
    .I2(DCORIEw),
    .O(\U3/DCORIE<4>_MC.D2_PT_0 )
  );
  X_AND3 \U3/DCORIE<4>_MC.D2_PT_1_1225  (
    .I0(\MSPReset_II/UIM ),
    .I1(\U3/DCORIE [4]),
    .I2(\NlwInverterSignal_U3/DCORIE<4>_MC.D2_PT_1/IN2 ),
    .O(\U3/DCORIE<4>_MC.D2_PT_1 )
  );
  X_OR2 \U3/DCORIE<4>_MC.D2_1226  (
    .I0(\U3/DCORIE<4>_MC.D2_PT_0 ),
    .I1(\U3/DCORIE<4>_MC.D2_PT_1 ),
    .O(\U3/DCORIE<4>_MC.D2 )
  );
  X_BUF \U3/DCORIE<5>  (
    .I(\U3/DCORIE<5>_MC.Q ),
    .O(\U3/DCORIE [5])
  );
  X_FF \U3/DCORIE<5>_MC.REG  (
    .I(\U3/DCORIE<5>_MC.D ),
    .CE(Vcc),
    .CLK(\U3/DCORIE<5>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\U3/DCORIE<5>_MC.Q )
  );
  X_INV \U3/DCORIE<5>_MC.REG_tsimcreated_inv_Mclk_II/FCLK_1227  (
    .I(\Mclk_II/FCLK ),
    .O(\U3/DCORIE<5>_MC.REG_tsimcreated_inv_Mclk_II/FCLK )
  );
  X_XOR2 \U3/DCORIE<5>_MC.D_1228  (
    .I0(\U3/DCORIE<5>_MC.D1 ),
    .I1(\U3/DCORIE<5>_MC.D2 ),
    .O(\U3/DCORIE<5>_MC.D )
  );
  X_ZERO \U3/DCORIE<5>_MC.D1_1229  (
    .O(\U3/DCORIE<5>_MC.D1 )
  );
  X_AND3 \U3/DCORIE<5>_MC.D2_PT_0_1230  (
    .I0(\MSPReset_II/UIM ),
    .I1(\AD<5>_II/UIM ),
    .I2(DCORIEw),
    .O(\U3/DCORIE<5>_MC.D2_PT_0 )
  );
  X_AND3 \U3/DCORIE<5>_MC.D2_PT_1_1231  (
    .I0(\MSPReset_II/UIM ),
    .I1(\U3/DCORIE [5]),
    .I2(\NlwInverterSignal_U3/DCORIE<5>_MC.D2_PT_1/IN2 ),
    .O(\U3/DCORIE<5>_MC.D2_PT_1 )
  );
  X_OR2 \U3/DCORIE<5>_MC.D2_1232  (
    .I0(\U3/DCORIE<5>_MC.D2_PT_0 ),
    .I1(\U3/DCORIE<5>_MC.D2_PT_1 ),
    .O(\U3/DCORIE<5>_MC.D2 )
  );
  X_BUF \U3/DCORIE<6>  (
    .I(\U3/DCORIE<6>_MC.Q ),
    .O(\U3/DCORIE [6])
  );
  X_FF \U3/DCORIE<6>_MC.REG  (
    .I(\U3/DCORIE<6>_MC.D ),
    .CE(Vcc),
    .CLK(\U3/DCORIE<6>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\U3/DCORIE<6>_MC.Q )
  );
  X_INV \U3/DCORIE<6>_MC.REG_tsimcreated_inv_Mclk_II/FCLK_1233  (
    .I(\Mclk_II/FCLK ),
    .O(\U3/DCORIE<6>_MC.REG_tsimcreated_inv_Mclk_II/FCLK )
  );
  X_XOR2 \U3/DCORIE<6>_MC.D_1234  (
    .I0(\U3/DCORIE<6>_MC.D1 ),
    .I1(\U3/DCORIE<6>_MC.D2 ),
    .O(\U3/DCORIE<6>_MC.D )
  );
  X_ZERO \U3/DCORIE<6>_MC.D1_1235  (
    .O(\U3/DCORIE<6>_MC.D1 )
  );
  X_AND3 \U3/DCORIE<6>_MC.D2_PT_0_1236  (
    .I0(\MSPReset_II/UIM ),
    .I1(\AD<6>_II/UIM ),
    .I2(DCORIEw),
    .O(\U3/DCORIE<6>_MC.D2_PT_0 )
  );
  X_AND3 \U3/DCORIE<6>_MC.D2_PT_1_1237  (
    .I0(\MSPReset_II/UIM ),
    .I1(\U3/DCORIE [6]),
    .I2(\NlwInverterSignal_U3/DCORIE<6>_MC.D2_PT_1/IN2 ),
    .O(\U3/DCORIE<6>_MC.D2_PT_1 )
  );
  X_OR2 \U3/DCORIE<6>_MC.D2_1238  (
    .I0(\U3/DCORIE<6>_MC.D2_PT_0 ),
    .I1(\U3/DCORIE<6>_MC.D2_PT_1 ),
    .O(\U3/DCORIE<6>_MC.D2 )
  );
  X_BUF \U3/DCORIE<7>  (
    .I(\U3/DCORIE<7>_MC.Q ),
    .O(\U3/DCORIE [7])
  );
  X_FF \U3/DCORIE<7>_MC.REG  (
    .I(\U3/DCORIE<7>_MC.D ),
    .CE(Vcc),
    .CLK(\U3/DCORIE<7>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\U3/DCORIE<7>_MC.Q )
  );
  X_INV \U3/DCORIE<7>_MC.REG_tsimcreated_inv_Mclk_II/FCLK_1239  (
    .I(\Mclk_II/FCLK ),
    .O(\U3/DCORIE<7>_MC.REG_tsimcreated_inv_Mclk_II/FCLK )
  );
  X_XOR2 \U3/DCORIE<7>_MC.D_1240  (
    .I0(\U3/DCORIE<7>_MC.D1 ),
    .I1(\U3/DCORIE<7>_MC.D2 ),
    .O(\U3/DCORIE<7>_MC.D )
  );
  X_ZERO \U3/DCORIE<7>_MC.D1_1241  (
    .O(\U3/DCORIE<7>_MC.D1 )
  );
  X_AND3 \U3/DCORIE<7>_MC.D2_PT_0_1242  (
    .I0(\MSPReset_II/UIM ),
    .I1(\AD<7>_II/UIM ),
    .I2(DCORIEw),
    .O(\U3/DCORIE<7>_MC.D2_PT_0 )
  );
  X_AND3 \U3/DCORIE<7>_MC.D2_PT_1_1243  (
    .I0(\MSPReset_II/UIM ),
    .I1(\U3/DCORIE [7]),
    .I2(\NlwInverterSignal_U3/DCORIE<7>_MC.D2_PT_1/IN2 ),
    .O(\U3/DCORIE<7>_MC.D2_PT_1 )
  );
  X_OR2 \U3/DCORIE<7>_MC.D2_1244  (
    .I0(\U3/DCORIE<7>_MC.D2_PT_0 ),
    .I1(\U3/DCORIE<7>_MC.D2_PT_1 ),
    .O(\U3/DCORIE<7>_MC.D2 )
  );
  X_BUF \LED1_MC.Q_1245  (
    .I(\LED1_MC.Q_tsimrenamed_net_ ),
    .O(\LED1_MC.Q )
  );
  X_BUF \LED1_MC.Q_tsimrenamed_net__1246  (
    .I(\LED1_MC.D ),
    .O(\LED1_MC.Q_tsimrenamed_net_ )
  );
  X_XOR2 \LED1_MC.D_1247  (
    .I0(\NlwInverterSignal_LED1_MC.D/IN0 ),
    .I1(\LED1_MC.D2 ),
    .O(\LED1_MC.D )
  );
  X_AND2 \LED1_MC.D1_1248  (
    .I0(\LightSense_II/UIM ),
    .I1(\NlwInverterSignal_LED1_MC.D1/IN1 ),
    .O(\LED1_MC.D1 )
  );
  X_ZERO \LED1_MC.D2_1249  (
    .O(\LED1_MC.D2 )
  );
  X_BUF \U9/MISCr<0>_MC.Q_1250  (
    .I(\U9/MISCr<0>_MC.D ),
    .O(\U9/MISCr<0>_MC.Q )
  );
  X_BUF \U9/MISCr<0>_MC.OE_1251  (
    .I(\U9/MISCr<0>_MC.BUFOE.OUT ),
    .O(\U9/MISCr<0>_MC.OE )
  );
  X_BUF \U9/MISCr<0>_MC.BUFOE.OUT_1252  (
    .I(\FOOBAR1__ctinst/7 ),
    .O(\U9/MISCr<0>_MC.BUFOE.OUT )
  );
  X_XOR2 \U9/MISCr<0>_MC.D_1253  (
    .I0(\NlwInverterSignal_U9/MISCr<0>_MC.D/IN0 ),
    .I1(\U9/MISCr<0>_MC.D2 ),
    .O(\U9/MISCr<0>_MC.D )
  );
  X_ZERO \U9/MISCr<0>_MC.D1_1254  (
    .O(\U9/MISCr<0>_MC.D1 )
  );
  X_AND2 \U9/MISCr<0>_MC.D2_PT_0_1255  (
    .I0(DCORI2CCNTr),
    .I1(\NlwInverterSignal_U9/MISCr<0>_MC.D2_PT_0/IN1 ),
    .O(\U9/MISCr<0>_MC.D2_PT_0 )
  );
  X_AND2 \U9/MISCr<0>_MC.D2_PT_1_1256  (
    .I0(DCORCONFIGr),
    .I1(\NlwInverterSignal_U9/MISCr<0>_MC.D2_PT_1/IN1 ),
    .O(\U9/MISCr<0>_MC.D2_PT_1 )
  );
  X_AND2 \U9/MISCr<0>_MC.D2_PT_2_1257  (
    .I0(DCORLIMITSr),
    .I1(\NlwInverterSignal_U9/MISCr<0>_MC.D2_PT_2/IN1 ),
    .O(\U9/MISCr<0>_MC.D2_PT_2 )
  );
  X_AND2 \U9/MISCr<0>_MC.D2_PT_3_1258  (
    .I0(DCORENCPWRr),
    .I1(\NlwInverterSignal_U9/MISCr<0>_MC.D2_PT_3/IN1 ),
    .O(\U9/MISCr<0>_MC.D2_PT_3 )
  );
  X_AND2 \U9/MISCr<0>_MC.D2_PT_4_1259  (
    .I0(\NlwInverterSignal_U9/MISCr<0>_MC.D2_PT_4/IN0 ),
    .I1(\NlwInverterSignal_U9/MISCr<0>_MC.D2_PT_4/IN1 ),
    .O(\U9/MISCr<0>_MC.D2_PT_4 )
  );
  X_AND2 \U9/MISCr<0>_MC.D2_PT_5_1260  (
    .I0(DCOR0THRESLOWr),
    .I1(\NlwInverterSignal_U9/MISCr<0>_MC.D2_PT_5/IN1 ),
    .O(\U9/MISCr<0>_MC.D2_PT_5 )
  );
  X_AND2 \U9/MISCr<0>_MC.D2_PT_6_1261  (
    .I0(DCORIFGr),
    .I1(\NlwInverterSignal_U9/MISCr<0>_MC.D2_PT_6/IN1 ),
    .O(\U9/MISCr<0>_MC.D2_PT_6 )
  );
  X_AND3 \U9/MISCr<0>_MC.D2_PT_7_1262  (
    .I0(\NlwInverterSignal_U9/MISCr<0>_MC.D2_PT_7/IN0 ),
    .I1(\NlwInverterSignal_U9/MISCr<0>_MC.D2_PT_7/IN1 ),
    .I2(\NlwInverterSignal_U9/MISCr<0>_MC.D2_PT_7/IN2 ),
    .O(\U9/MISCr<0>_MC.D2_PT_7 )
  );
  X_OR8 \U9/MISCr<0>_MC.D2_1263  (
    .I0(\U9/MISCr<0>_MC.D2_PT_0 ),
    .I1(\U9/MISCr<0>_MC.D2_PT_1 ),
    .I2(\U9/MISCr<0>_MC.D2_PT_2 ),
    .I3(\U9/MISCr<0>_MC.D2_PT_3 ),
    .I4(\U9/MISCr<0>_MC.D2_PT_4 ),
    .I5(\U9/MISCr<0>_MC.D2_PT_5 ),
    .I6(\U9/MISCr<0>_MC.D2_PT_6 ),
    .I7(\U9/MISCr<0>_MC.D2_PT_7 ),
    .O(\U9/MISCr<0>_MC.D2 )
  );
  X_AND2 \U9/MISCr<0>_MC.CE_1264  (
    .I0(DCOROUTw),
    .I1(DCOROUTw),
    .O(\U9/MISCr<0>_MC.CE )
  );
  X_BUF \LED2_MC.Q_1265  (
    .I(\LED2_MC.Q_tsimrenamed_net_ ),
    .O(\LED2_MC.Q )
  );
  X_BUF \LED2_MC.Q_tsimrenamed_net__1266  (
    .I(\LED2_MC.D ),
    .O(\LED2_MC.Q_tsimrenamed_net_ )
  );
  X_XOR2 \LED2_MC.D_1267  (
    .I0(\NlwInverterSignal_LED2_MC.D/IN0 ),
    .I1(\LED2_MC.D2 ),
    .O(\LED2_MC.D )
  );
  X_AND2 \LED2_MC.D1_1268  (
    .I0(\LightSense_II/UIM ),
    .I1(\NlwInverterSignal_LED2_MC.D1/IN1 ),
    .O(\LED2_MC.D1 )
  );
  X_ZERO \LED2_MC.D2_1269  (
    .O(\LED2_MC.D2 )
  );
  X_BUF \U9/MISCr<1>_MC.Q_1270  (
    .I(\U9/MISCr<1>_MC.D ),
    .O(\U9/MISCr<1>_MC.Q )
  );
  X_BUF \U9/MISCr<1>_MC.OE_1271  (
    .I(\U9/MISCr<1>_MC.BUFOE.OUT ),
    .O(\U9/MISCr<1>_MC.OE )
  );
  X_BUF \U9/MISCr<1>_MC.BUFOE.OUT_1272  (
    .I(\FOOBAR1__ctinst/7 ),
    .O(\U9/MISCr<1>_MC.BUFOE.OUT )
  );
  X_XOR2 \U9/MISCr<1>_MC.D_1273  (
    .I0(\NlwInverterSignal_U9/MISCr<1>_MC.D/IN0 ),
    .I1(\U9/MISCr<1>_MC.D2 ),
    .O(\U9/MISCr<1>_MC.D )
  );
  X_ZERO \U9/MISCr<1>_MC.D1_1274  (
    .O(\U9/MISCr<1>_MC.D1 )
  );
  X_AND2 \U9/MISCr<1>_MC.D2_PT_0_1275  (
    .I0(DCORI2CCNTr),
    .I1(\NlwInverterSignal_U9/MISCr<1>_MC.D2_PT_0/IN1 ),
    .O(\U9/MISCr<1>_MC.D2_PT_0 )
  );
  X_AND2 \U9/MISCr<1>_MC.D2_PT_1_1276  (
    .I0(DCORCONFIGr),
    .I1(\NlwInverterSignal_U9/MISCr<1>_MC.D2_PT_1/IN1 ),
    .O(\U9/MISCr<1>_MC.D2_PT_1 )
  );
  X_AND2 \U9/MISCr<1>_MC.D2_PT_2_1277  (
    .I0(DCORLIMITSr),
    .I1(\NlwInverterSignal_U9/MISCr<1>_MC.D2_PT_2/IN1 ),
    .O(\U9/MISCr<1>_MC.D2_PT_2 )
  );
  X_AND2 \U9/MISCr<1>_MC.D2_PT_3_1278  (
    .I0(DCORENCPWRr),
    .I1(\NlwInverterSignal_U9/MISCr<1>_MC.D2_PT_3/IN1 ),
    .O(\U9/MISCr<1>_MC.D2_PT_3 )
  );
  X_AND2 \U9/MISCr<1>_MC.D2_PT_4_1279  (
    .I0(\NlwInverterSignal_U9/MISCr<1>_MC.D2_PT_4/IN0 ),
    .I1(\NlwInverterSignal_U9/MISCr<1>_MC.D2_PT_4/IN1 ),
    .O(\U9/MISCr<1>_MC.D2_PT_4 )
  );
  X_AND2 \U9/MISCr<1>_MC.D2_PT_5_1280  (
    .I0(DCOR0THRESLOWr),
    .I1(\NlwInverterSignal_U9/MISCr<1>_MC.D2_PT_5/IN1 ),
    .O(\U9/MISCr<1>_MC.D2_PT_5 )
  );
  X_AND2 \U9/MISCr<1>_MC.D2_PT_6_1281  (
    .I0(DCORIFGr),
    .I1(\NlwInverterSignal_U9/MISCr<1>_MC.D2_PT_6/IN1 ),
    .O(\U9/MISCr<1>_MC.D2_PT_6 )
  );
  X_AND3 \U9/MISCr<1>_MC.D2_PT_7_1282  (
    .I0(\NlwInverterSignal_U9/MISCr<1>_MC.D2_PT_7/IN0 ),
    .I1(\NlwInverterSignal_U9/MISCr<1>_MC.D2_PT_7/IN1 ),
    .I2(\NlwInverterSignal_U9/MISCr<1>_MC.D2_PT_7/IN2 ),
    .O(\U9/MISCr<1>_MC.D2_PT_7 )
  );
  X_OR8 \U9/MISCr<1>_MC.D2_1283  (
    .I0(\U9/MISCr<1>_MC.D2_PT_0 ),
    .I1(\U9/MISCr<1>_MC.D2_PT_1 ),
    .I2(\U9/MISCr<1>_MC.D2_PT_2 ),
    .I3(\U9/MISCr<1>_MC.D2_PT_3 ),
    .I4(\U9/MISCr<1>_MC.D2_PT_4 ),
    .I5(\U9/MISCr<1>_MC.D2_PT_5 ),
    .I6(\U9/MISCr<1>_MC.D2_PT_6 ),
    .I7(\U9/MISCr<1>_MC.D2_PT_7 ),
    .O(\U9/MISCr<1>_MC.D2 )
  );
  X_AND2 \U9/MISCr<1>_MC.CE_1284  (
    .I0(DCOROUTw),
    .I1(DCOROUTw),
    .O(\U9/MISCr<1>_MC.CE )
  );
  X_BUF \LED3_MC.Q_1285  (
    .I(\LED3_MC.Q_tsimrenamed_net_ ),
    .O(\LED3_MC.Q )
  );
  X_BUF \LED3_MC.Q_tsimrenamed_net__1286  (
    .I(\LED3_MC.D ),
    .O(\LED3_MC.Q_tsimrenamed_net_ )
  );
  X_XOR2 \LED3_MC.D_1287  (
    .I0(\NlwInverterSignal_LED3_MC.D/IN0 ),
    .I1(\LED3_MC.D2 ),
    .O(\LED3_MC.D )
  );
  X_AND2 \LED3_MC.D1_1288  (
    .I0(\LightSense_II/UIM ),
    .I1(\NlwInverterSignal_LED3_MC.D1/IN1 ),
    .O(\LED3_MC.D1 )
  );
  X_ZERO \LED3_MC.D2_1289  (
    .O(\LED3_MC.D2 )
  );
  X_BUF \U9/MISCr<2>  (
    .I(\U9/MISCr<2>_MC.Q ),
    .O(\U9/MISCr [2])
  );
  X_OR2 \U9/MISCr<2>_MC_tsimcreated_prld__1290  (
    .I0(\FOOBAR3__ctinst/7 ),
    .I1(PRLD),
    .O(\U9/MISCr<2>_MC_tsimcreated_prld_ )
  );
  X_FF \U9/MISCr<2>_MC.REG  (
    .I(\U9/MISCr<2>_MC.D ),
    .CE(\FOOBAR1__ctinst/4 ),
    .CLK(\U9/MISCr<2>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(\U9/MISCr<2>_MC_tsimcreated_prld_ ),
    .O(\U9/MISCr<2>_MC.Q )
  );
  X_INV \U9/MISCr<2>_MC.REG_tsimcreated_inv_Mclk_II/FCLK_1291  (
    .I(\Mclk_II/FCLK ),
    .O(\U9/MISCr<2>_MC.REG_tsimcreated_inv_Mclk_II/FCLK )
  );
  X_XOR2 \U9/MISCr<2>_MC.D_1292  (
    .I0(\U9/MISCr<2>_MC.D1 ),
    .I1(\U9/MISCr<2>_MC.D2 ),
    .O(\U9/MISCr<2>_MC.D )
  );
  X_AND2 \U9/MISCr<2>_MC.D1_1293  (
    .I0(\AD<2>_II/UIM ),
    .I1(\AD<2>_II/UIM ),
    .O(\U9/MISCr<2>_MC.D1 )
  );
  X_ZERO \U9/MISCr<2>_MC.D2_1294  (
    .O(\U9/MISCr<2>_MC.D2 )
  );
  X_BUF \LED4_MC.Q_1295  (
    .I(\LED4_MC.Q_tsimrenamed_net_ ),
    .O(\LED4_MC.Q )
  );
  X_BUF \LED4_MC.Q_tsimrenamed_net__1296  (
    .I(\LED4_MC.D ),
    .O(\LED4_MC.Q_tsimrenamed_net_ )
  );
  X_XOR2 \LED4_MC.D_1297  (
    .I0(\NlwInverterSignal_LED4_MC.D/IN0 ),
    .I1(\LED4_MC.D2 ),
    .O(\LED4_MC.D )
  );
  X_AND2 \LED4_MC.D1_1298  (
    .I0(\LightSense_II/UIM ),
    .I1(\NlwInverterSignal_LED4_MC.D1/IN1 ),
    .O(\LED4_MC.D1 )
  );
  X_ZERO \LED4_MC.D2_1299  (
    .O(\LED4_MC.D2 )
  );
  X_BUF \U9/MISCr<3>  (
    .I(\U9/MISCr<3>_MC.Q ),
    .O(\U9/MISCr [3])
  );
  X_OR2 \U9/MISCr<3>_MC_tsimcreated_prld__1300  (
    .I0(\FOOBAR3__ctinst/7 ),
    .I1(PRLD),
    .O(\U9/MISCr<3>_MC_tsimcreated_prld_ )
  );
  X_FF \U9/MISCr<3>_MC.REG  (
    .I(\U9/MISCr<3>_MC.D ),
    .CE(\FOOBAR1__ctinst/4 ),
    .CLK(\U9/MISCr<3>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(\U9/MISCr<3>_MC_tsimcreated_prld_ ),
    .O(\U9/MISCr<3>_MC.Q )
  );
  X_INV \U9/MISCr<3>_MC.REG_tsimcreated_inv_Mclk_II/FCLK_1301  (
    .I(\Mclk_II/FCLK ),
    .O(\U9/MISCr<3>_MC.REG_tsimcreated_inv_Mclk_II/FCLK )
  );
  X_XOR2 \U9/MISCr<3>_MC.D_1302  (
    .I0(\U9/MISCr<3>_MC.D1 ),
    .I1(\U9/MISCr<3>_MC.D2 ),
    .O(\U9/MISCr<3>_MC.D )
  );
  X_AND2 \U9/MISCr<3>_MC.D1_1303  (
    .I0(\AD<3>_II/UIM ),
    .I1(\AD<3>_II/UIM ),
    .O(\U9/MISCr<3>_MC.D1 )
  );
  X_ZERO \U9/MISCr<3>_MC.D2_1304  (
    .O(\U9/MISCr<3>_MC.D2 )
  );
  X_BUF \LED5_MC.Q_1305  (
    .I(\LED5_MC.Q_tsimrenamed_net_ ),
    .O(\LED5_MC.Q )
  );
  X_BUF \LED5_MC.Q_tsimrenamed_net__1306  (
    .I(\LED5_MC.D ),
    .O(\LED5_MC.Q_tsimrenamed_net_ )
  );
  X_XOR2 \LED5_MC.D_1307  (
    .I0(\NlwInverterSignal_LED5_MC.D/IN0 ),
    .I1(\LED5_MC.D2 ),
    .O(\LED5_MC.D )
  );
  X_AND2 \LED5_MC.D1_1308  (
    .I0(\LightSense_II/UIM ),
    .I1(\NlwInverterSignal_LED5_MC.D1/IN1 ),
    .O(\LED5_MC.D1 )
  );
  X_ZERO \LED5_MC.D2_1309  (
    .O(\LED5_MC.D2 )
  );
  X_BUF \U9/MISCr<4>_MC.Q_1310  (
    .I(\U9/MISCr<4>_MC.D ),
    .O(\U9/MISCr<4>_MC.Q )
  );
  X_BUF \U9/MISCr<4>_MC.OE_1311  (
    .I(\U9/MISCr<4>_MC.BUFOE.OUT ),
    .O(\U9/MISCr<4>_MC.OE )
  );
  X_BUF \U9/MISCr<4>_MC.BUFOE.OUT_1312  (
    .I(\FOOBAR1__ctinst/7 ),
    .O(\U9/MISCr<4>_MC.BUFOE.OUT )
  );
  X_XOR2 \U9/MISCr<4>_MC.D_1313  (
    .I0(\NlwInverterSignal_U9/MISCr<4>_MC.D/IN0 ),
    .I1(\U9/MISCr<4>_MC.D2 ),
    .O(\U9/MISCr<4>_MC.D )
  );
  X_ZERO \U9/MISCr<4>_MC.D1_1314  (
    .O(\U9/MISCr<4>_MC.D1 )
  );
  X_AND2 \U9/MISCr<4>_MC.D2_PT_0_1315  (
    .I0(DCORI2CCNTr),
    .I1(\NlwInverterSignal_U9/MISCr<4>_MC.D2_PT_0/IN1 ),
    .O(\U9/MISCr<4>_MC.D2_PT_0 )
  );
  X_AND2 \U9/MISCr<4>_MC.D2_PT_1_1316  (
    .I0(DCORCONFIGr),
    .I1(\NlwInverterSignal_U9/MISCr<4>_MC.D2_PT_1/IN1 ),
    .O(\U9/MISCr<4>_MC.D2_PT_1 )
  );
  X_AND2 \U9/MISCr<4>_MC.D2_PT_2_1317  (
    .I0(DCORLIMITSr),
    .I1(\NlwInverterSignal_U9/MISCr<4>_MC.D2_PT_2/IN1 ),
    .O(\U9/MISCr<4>_MC.D2_PT_2 )
  );
  X_AND2 \U9/MISCr<4>_MC.D2_PT_3_1318  (
    .I0(DCORENCPWRr),
    .I1(\NlwInverterSignal_U9/MISCr<4>_MC.D2_PT_3/IN1 ),
    .O(\U9/MISCr<4>_MC.D2_PT_3 )
  );
  X_AND2 \U9/MISCr<4>_MC.D2_PT_4_1319  (
    .I0(\NlwInverterSignal_U9/MISCr<4>_MC.D2_PT_4/IN0 ),
    .I1(\NlwInverterSignal_U9/MISCr<4>_MC.D2_PT_4/IN1 ),
    .O(\U9/MISCr<4>_MC.D2_PT_4 )
  );
  X_AND2 \U9/MISCr<4>_MC.D2_PT_5_1320  (
    .I0(DCOR0THRESLOWr),
    .I1(\NlwInverterSignal_U9/MISCr<4>_MC.D2_PT_5/IN1 ),
    .O(\U9/MISCr<4>_MC.D2_PT_5 )
  );
  X_AND2 \U9/MISCr<4>_MC.D2_PT_6_1321  (
    .I0(DCORIFGr),
    .I1(\NlwInverterSignal_U9/MISCr<4>_MC.D2_PT_6/IN1 ),
    .O(\U9/MISCr<4>_MC.D2_PT_6 )
  );
  X_AND3 \U9/MISCr<4>_MC.D2_PT_7_1322  (
    .I0(\NlwInverterSignal_U9/MISCr<4>_MC.D2_PT_7/IN0 ),
    .I1(\NlwInverterSignal_U9/MISCr<4>_MC.D2_PT_7/IN1 ),
    .I2(\NlwInverterSignal_U9/MISCr<4>_MC.D2_PT_7/IN2 ),
    .O(\U9/MISCr<4>_MC.D2_PT_7 )
  );
  X_OR8 \U9/MISCr<4>_MC.D2_1323  (
    .I0(\U9/MISCr<4>_MC.D2_PT_0 ),
    .I1(\U9/MISCr<4>_MC.D2_PT_1 ),
    .I2(\U9/MISCr<4>_MC.D2_PT_2 ),
    .I3(\U9/MISCr<4>_MC.D2_PT_3 ),
    .I4(\U9/MISCr<4>_MC.D2_PT_4 ),
    .I5(\U9/MISCr<4>_MC.D2_PT_5 ),
    .I6(\U9/MISCr<4>_MC.D2_PT_6 ),
    .I7(\U9/MISCr<4>_MC.D2_PT_7 ),
    .O(\U9/MISCr<4>_MC.D2 )
  );
  X_AND2 \U9/MISCr<4>_MC.CE_1324  (
    .I0(DCOROUTw),
    .I1(DCOROUTw),
    .O(\U9/MISCr<4>_MC.CE )
  );
  X_BUF \MHSI_MC.Q_1325  (
    .I(\MHSI_MC.Q_tsimrenamed_net_ ),
    .O(\MHSI_MC.Q )
  );
  X_BUF \MHSI_MC.Q_tsimrenamed_net__1326  (
    .I(\MHSI_MC.D ),
    .O(\MHSI_MC.Q_tsimrenamed_net_ )
  );
  X_XOR2 \MHSI_MC.D_1327  (
    .I0(\MHSI_MC.D1 ),
    .I1(\MHSI_MC.D2 ),
    .O(\MHSI_MC.D )
  );
  X_AND2 \MHSI_MC.D1_1328  (
    .I0(\HSI_II/UIM ),
    .I1(\HSI_II/UIM ),
    .O(\MHSI_MC.D1 )
  );
  X_ZERO \MHSI_MC.D2_1329  (
    .O(\MHSI_MC.D2 )
  );
  X_BUF \MTRpwr_MC.Q_1330  (
    .I(\MTRpwr_MC.Q_tsimrenamed_net_ ),
    .O(\MTRpwr_MC.Q )
  );
  X_OR2 MTRpwr_MC_tsimcreated_prld__1331 (
    .I0(\FOOBAR3__ctinst/7 ),
    .I1(PRLD),
    .O(MTRpwr_MC_tsimcreated_prld_)
  );
  X_FF \MTRpwr_MC.REG  (
    .I(\MTRpwr_MC.D ),
    .CE(\FOOBAR18__ctinst/4 ),
    .CLK(\MTRpwr_MC.REG_tsimcreated_inv_Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(MTRpwr_MC_tsimcreated_prld_),
    .O(\MTRpwr_MC.Q_tsimrenamed_net_ )
  );
  X_INV \MTRpwr_MC.REG_tsimcreated_inv_Mclk_II/FCLK_1332  (
    .I(\Mclk_II/FCLK ),
    .O(\MTRpwr_MC.REG_tsimcreated_inv_Mclk_II/FCLK )
  );
  X_XOR2 \MTRpwr_MC.D_1333  (
    .I0(\MTRpwr_MC.D1 ),
    .I1(\MTRpwr_MC.D2 ),
    .O(\MTRpwr_MC.D )
  );
  X_AND2 \MTRpwr_MC.D1_1334  (
    .I0(\AD<5>_II/UIM ),
    .I1(\AD<5>_II/UIM ),
    .O(\MTRpwr_MC.D1 )
  );
  X_ZERO \MTRpwr_MC.D2_1335  (
    .O(\MTRpwr_MC.D2 )
  );
  X_BUF \MTRpwrn_MC.Q_1336  (
    .I(\MTRpwrn_MC.Q_tsimrenamed_net_ ),
    .O(\MTRpwrn_MC.Q )
  );
  X_OR2 MTRpwrn_MC_tsimcreated_prld__1337 (
    .I0(\FOOBAR2__ctinst/7 ),
    .I1(PRLD),
    .O(MTRpwrn_MC_tsimcreated_prld_)
  );
  X_FF \MTRpwrn_MC.REG  (
    .I(\MTRpwrn_MC.D ),
    .CE(\FOOBAR7__ctinst/4 ),
    .CLK(\MTRpwrn_MC.REG_tsimcreated_inv_Mclk_II/FCLK ),
    .SET(MTRpwrn_MC_tsimcreated_prld_),
    .RST(Gnd),
    .O(\MTRpwrn_MC.Q_tsimrenamed_net_ )
  );
  X_INV \MTRpwrn_MC.REG_tsimcreated_inv_Mclk_II/FCLK_1338  (
    .I(\Mclk_II/FCLK ),
    .O(\MTRpwrn_MC.REG_tsimcreated_inv_Mclk_II/FCLK )
  );
  X_XOR2 \MTRpwrn_MC.D_1339  (
    .I0(\NlwInverterSignal_MTRpwrn_MC.D/IN0 ),
    .I1(\MTRpwrn_MC.D2 ),
    .O(\MTRpwrn_MC.D )
  );
  X_AND2 \MTRpwrn_MC.D1_1340  (
    .I0(\AD<5>_II/UIM ),
    .I1(\AD<5>_II/UIM ),
    .O(\MTRpwrn_MC.D1 )
  );
  X_ZERO \MTRpwrn_MC.D2_1341  (
    .O(\MTRpwrn_MC.D2 )
  );
  X_BUF \MTXI_MC.Q_1342  (
    .I(\MTXI_MC.Q_tsimrenamed_net_ ),
    .O(\MTXI_MC.Q )
  );
  X_BUF \MTXI_MC.Q_tsimrenamed_net__1343  (
    .I(\MTXI_MC.D ),
    .O(\MTXI_MC.Q_tsimrenamed_net_ )
  );
  X_XOR2 \MTXI_MC.D_1344  (
    .I0(\MTXI_MC.D1 ),
    .I1(\MTXI_MC.D2 ),
    .O(\MTXI_MC.D )
  );
  X_AND2 \MTXI_MC.D1_1345  (
    .I0(\TXI_II/UIM ),
    .I1(\TXI_II/UIM ),
    .O(\MTXI_MC.D1 )
  );
  X_ZERO \MTXI_MC.D2_1346  (
    .O(\MTXI_MC.D2 )
  );
  X_BUF \PAH0_MC.Q_1347  (
    .I(\PAH0_MC.Q_tsimrenamed_net_ ),
    .O(\PAH0_MC.Q )
  );
  X_BUF \PAH0_MC.UIM_1348  (
    .I(\PAH0_MC.Q_tsimrenamed_net_ ),
    .O(\PAH0_MC.UIM )
  );
  X_BUF \PAH0_MC.Q_tsimrenamed_net__1349  (
    .I(\PAH0_MC.D ),
    .O(\PAH0_MC.Q_tsimrenamed_net_ )
  );
  X_XOR2 \PAH0_MC.D_1350  (
    .I0(\PAH0_MC.D1 ),
    .I1(\PAH0_MC.D2 ),
    .O(\PAH0_MC.D )
  );
  X_AND4 \PAH0_MC.D1_1351  (
    .I0(\NlwInverterSignal_PAH0_MC.D1/IN0 ),
    .I1(\NlwInverterSignal_PAH0_MC.D1/IN1 ),
    .I2(\PWM1_II/UIM ),
    .I3(\NlwInverterSignal_PAH0_MC.D1/IN3 ),
    .O(\PAH0_MC.D1 )
  );
  X_ZERO \PAH0_MC.D2_1352  (
    .O(\PAH0_MC.D2 )
  );
  X_BUF NET3248_1353 (
    .I(\NET3248_MC.Q ),
    .O(NET3248)
  );
  X_FF \NET3248_MC.REG  (
    .I(\NET3248_MC.D ),
    .CE(Vcc),
    .CLK(\NET3248_MC.REG_tsimcreated_inv_Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\NET3248_MC.Q )
  );
  X_INV \NET3248_MC.REG_tsimcreated_inv_Mclk_II/FCLK_1354  (
    .I(\Mclk_II/FCLK ),
    .O(\NET3248_MC.REG_tsimcreated_inv_Mclk_II/FCLK )
  );
  X_XOR2 \NET3248_MC.D_1355  (
    .I0(\NET3248_MC.D1 ),
    .I1(\NET3248_MC.D2 ),
    .O(\NET3248_MC.D )
  );
  X_ZERO \NET3248_MC.D1_1356  (
    .O(\NET3248_MC.D1 )
  );
  X_AND3 \NET3248_MC.D2_PT_0_1357  (
    .I0(\MSPReset_II/UIM ),
    .I1(\NlwInverterSignal_NET3248_MC.D2_PT_0/IN1 ),
    .I2(NET3248),
    .O(\NET3248_MC.D2_PT_0 )
  );
  X_AND3 \NET3248_MC.D2_PT_1_1358  (
    .I0(\MSPReset_II/UIM ),
    .I1(\DIR0_II/UIM ),
    .I2(\NlwInverterSignal_NET3248_MC.D2_PT_1/IN2 ),
    .O(\NET3248_MC.D2_PT_1 )
  );
  X_AND3 \NET3248_MC.D2_PT_2_1359  (
    .I0(\MSPReset_II/UIM ),
    .I1(\NlwInverterSignal_NET3248_MC.D2_PT_2/IN1 ),
    .I2(\NlwInverterSignal_NET3248_MC.D2_PT_2/IN2 ),
    .O(\NET3248_MC.D2_PT_2 )
  );
  X_OR3 \NET3248_MC.D2_1360  (
    .I0(\NET3248_MC.D2_PT_0 ),
    .I1(\NET3248_MC.D2_PT_1 ),
    .I2(\NET3248_MC.D2_PT_2 ),
    .O(\NET3248_MC.D2 )
  );
  X_BUF \PAH1_MC.Q_1361  (
    .I(\PAH1_MC.Q_tsimrenamed_net_ ),
    .O(\PAH1_MC.Q )
  );
  X_BUF \PAH1_MC.UIM_1362  (
    .I(\PAH1_MC.Q_tsimrenamed_net_ ),
    .O(\PAH1_MC.UIM )
  );
  X_BUF \PAH1_MC.Q_tsimrenamed_net__1363  (
    .I(\PAH1_MC.D ),
    .O(\PAH1_MC.Q_tsimrenamed_net_ )
  );
  X_XOR2 \PAH1_MC.D_1364  (
    .I0(\PAH1_MC.D1 ),
    .I1(\PAH1_MC.D2 ),
    .O(\PAH1_MC.D )
  );
  X_AND4 \PAH1_MC.D1_1365  (
    .I0(\NlwInverterSignal_PAH1_MC.D1/IN0 ),
    .I1(\NlwInverterSignal_PAH1_MC.D1/IN1 ),
    .I2(\PWM2_II/UIM ),
    .I3(\NlwInverterSignal_PAH1_MC.D1/IN3 ),
    .O(\PAH1_MC.D1 )
  );
  X_ZERO \PAH1_MC.D2_1366  (
    .O(\PAH1_MC.D2 )
  );
  X_BUF NET3253_1367 (
    .I(\NET3253_MC.Q ),
    .O(NET3253)
  );
  X_FF \NET3253_MC.REG  (
    .I(\NET3253_MC.D ),
    .CE(Vcc),
    .CLK(\NET3253_MC.REG_tsimcreated_inv_Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\NET3253_MC.Q )
  );
  X_INV \NET3253_MC.REG_tsimcreated_inv_Mclk_II/FCLK_1368  (
    .I(\Mclk_II/FCLK ),
    .O(\NET3253_MC.REG_tsimcreated_inv_Mclk_II/FCLK )
  );
  X_XOR2 \NET3253_MC.D_1369  (
    .I0(\NET3253_MC.D1 ),
    .I1(\NET3253_MC.D2 ),
    .O(\NET3253_MC.D )
  );
  X_ZERO \NET3253_MC.D1_1370  (
    .O(\NET3253_MC.D1 )
  );
  X_AND3 \NET3253_MC.D2_PT_0_1371  (
    .I0(\MSPReset_II/UIM ),
    .I1(\NlwInverterSignal_NET3253_MC.D2_PT_0/IN1 ),
    .I2(\DIR1_II/UIM ),
    .O(\NET3253_MC.D2_PT_0 )
  );
  X_AND3 \NET3253_MC.D2_PT_1_1372  (
    .I0(\MSPReset_II/UIM ),
    .I1(\NlwInverterSignal_NET3253_MC.D2_PT_1/IN1 ),
    .I2(NET3253),
    .O(\NET3253_MC.D2_PT_1 )
  );
  X_AND3 \NET3253_MC.D2_PT_2_1373  (
    .I0(\MSPReset_II/UIM ),
    .I1(\NlwInverterSignal_NET3253_MC.D2_PT_2/IN1 ),
    .I2(\NlwInverterSignal_NET3253_MC.D2_PT_2/IN2 ),
    .O(\NET3253_MC.D2_PT_2 )
  );
  X_OR3 \NET3253_MC.D2_1374  (
    .I0(\NET3253_MC.D2_PT_0 ),
    .I1(\NET3253_MC.D2_PT_1 ),
    .I2(\NET3253_MC.D2_PT_2 ),
    .O(\NET3253_MC.D2 )
  );
  X_BUF \PAL0_MC.Q_1375  (
    .I(\PAL0_MC.Q_tsimrenamed_net_ ),
    .O(\PAL0_MC.Q )
  );
  X_BUF \PAL0_MC.Q_tsimrenamed_net__1376  (
    .I(\PAL0_MC.D ),
    .O(\PAL0_MC.Q_tsimrenamed_net_ )
  );
  X_XOR2 \PAL0_MC.D_1377  (
    .I0(\PAL0_MC.D1 ),
    .I1(\PAL0_MC.D2 ),
    .O(\PAL0_MC.D )
  );
  X_ZERO \PAL0_MC.D1_1378  (
    .O(\PAL0_MC.D1 )
  );
  X_AND2 \PAL0_MC.D2_PT_0_1379  (
    .I0(\PAH0_MC.UIM ),
    .I1(\PAH0_MC.UIM ),
    .O(\PAL0_MC.D2_PT_0 )
  );
  X_AND4 \PAL0_MC.D2_PT_1_1380  (
    .I0(\NlwInverterSignal_PAL0_MC.D2_PT_1/IN0 ),
    .I1(\DIR0_II/UIM ),
    .I2(\NlwInverterSignal_PAL0_MC.D2_PT_1/IN2 ),
    .I3(\NlwInverterSignal_PAL0_MC.D2_PT_1/IN3 ),
    .O(\PAL0_MC.D2_PT_1 )
  );
  X_OR2 \PAL0_MC.D2_1381  (
    .I0(\PAL0_MC.D2_PT_0 ),
    .I1(\PAL0_MC.D2_PT_1 ),
    .O(\PAL0_MC.D2 )
  );
  X_BUF \PAL1_MC.Q_1382  (
    .I(\PAL1_MC.Q_tsimrenamed_net_ ),
    .O(\PAL1_MC.Q )
  );
  X_BUF \PAL1_MC.Q_tsimrenamed_net__1383  (
    .I(\PAL1_MC.D ),
    .O(\PAL1_MC.Q_tsimrenamed_net_ )
  );
  X_XOR2 \PAL1_MC.D_1384  (
    .I0(\PAL1_MC.D1 ),
    .I1(\PAL1_MC.D2 ),
    .O(\PAL1_MC.D )
  );
  X_ZERO \PAL1_MC.D1_1385  (
    .O(\PAL1_MC.D1 )
  );
  X_AND2 \PAL1_MC.D2_PT_0_1386  (
    .I0(\PAH1_MC.UIM ),
    .I1(\PAH1_MC.UIM ),
    .O(\PAL1_MC.D2_PT_0 )
  );
  X_AND4 \PAL1_MC.D2_PT_1_1387  (
    .I0(\NlwInverterSignal_PAL1_MC.D2_PT_1/IN0 ),
    .I1(\DIR1_II/UIM ),
    .I2(\NlwInverterSignal_PAL1_MC.D2_PT_1/IN2 ),
    .I3(\NlwInverterSignal_PAL1_MC.D2_PT_1/IN3 ),
    .O(\PAL1_MC.D2_PT_1 )
  );
  X_OR2 \PAL1_MC.D2_1388  (
    .I0(\PAL1_MC.D2_PT_0 ),
    .I1(\PAL1_MC.D2_PT_1 ),
    .O(\PAL1_MC.D2 )
  );
  X_BUF \PBH0_MC.Q_1389  (
    .I(\PBH0_MC.Q_tsimrenamed_net_ ),
    .O(\PBH0_MC.Q )
  );
  X_BUF \PBH0_MC.UIM_1390  (
    .I(\PBH0_MC.Q_tsimrenamed_net_ ),
    .O(\PBH0_MC.UIM )
  );
  X_BUF \PBH0_MC.Q_tsimrenamed_net__1391  (
    .I(\PBH0_MC.D ),
    .O(\PBH0_MC.Q_tsimrenamed_net_ )
  );
  X_XOR2 \PBH0_MC.D_1392  (
    .I0(\PBH0_MC.D1 ),
    .I1(\PBH0_MC.D2 ),
    .O(\PBH0_MC.D )
  );
  X_AND4 \PBH0_MC.D1_1393  (
    .I0(\NlwInverterSignal_PBH0_MC.D1/IN0 ),
    .I1(\DIR0_II/UIM ),
    .I2(\PWM1_II/UIM ),
    .I3(\NlwInverterSignal_PBH0_MC.D1/IN3 ),
    .O(\PBH0_MC.D1 )
  );
  X_ZERO \PBH0_MC.D2_1394  (
    .O(\PBH0_MC.D2 )
  );
  X_BUF \PBH1_MC.Q_1395  (
    .I(\PBH1_MC.Q_tsimrenamed_net_ ),
    .O(\PBH1_MC.Q )
  );
  X_BUF \PBH1_MC.UIM_1396  (
    .I(\PBH1_MC.Q_tsimrenamed_net_ ),
    .O(\PBH1_MC.UIM )
  );
  X_BUF \PBH1_MC.Q_tsimrenamed_net__1397  (
    .I(\PBH1_MC.D ),
    .O(\PBH1_MC.Q_tsimrenamed_net_ )
  );
  X_XOR2 \PBH1_MC.D_1398  (
    .I0(\PBH1_MC.D1 ),
    .I1(\PBH1_MC.D2 ),
    .O(\PBH1_MC.D )
  );
  X_AND4 \PBH1_MC.D1_1399  (
    .I0(\NlwInverterSignal_PBH1_MC.D1/IN0 ),
    .I1(\DIR1_II/UIM ),
    .I2(\PWM2_II/UIM ),
    .I3(\NlwInverterSignal_PBH1_MC.D1/IN3 ),
    .O(\PBH1_MC.D1 )
  );
  X_ZERO \PBH1_MC.D2_1400  (
    .O(\PBH1_MC.D2 )
  );
  X_BUF \PBL0_MC.Q_1401  (
    .I(\PBL0_MC.Q_tsimrenamed_net_ ),
    .O(\PBL0_MC.Q )
  );
  X_BUF \PBL0_MC.Q_tsimrenamed_net__1402  (
    .I(\PBL0_MC.D ),
    .O(\PBL0_MC.Q_tsimrenamed_net_ )
  );
  X_XOR2 \PBL0_MC.D_1403  (
    .I0(\PBL0_MC.D1 ),
    .I1(\PBL0_MC.D2 ),
    .O(\PBL0_MC.D )
  );
  X_ZERO \PBL0_MC.D1_1404  (
    .O(\PBL0_MC.D1 )
  );
  X_AND2 \PBL0_MC.D2_PT_0_1405  (
    .I0(\PBH0_MC.UIM ),
    .I1(\PBH0_MC.UIM ),
    .O(\PBL0_MC.D2_PT_0 )
  );
  X_AND4 \PBL0_MC.D2_PT_1_1406  (
    .I0(\NlwInverterSignal_PBL0_MC.D2_PT_1/IN0 ),
    .I1(\NlwInverterSignal_PBL0_MC.D2_PT_1/IN1 ),
    .I2(\NlwInverterSignal_PBL0_MC.D2_PT_1/IN2 ),
    .I3(\NlwInverterSignal_PBL0_MC.D2_PT_1/IN3 ),
    .O(\PBL0_MC.D2_PT_1 )
  );
  X_OR2 \PBL0_MC.D2_1407  (
    .I0(\PBL0_MC.D2_PT_0 ),
    .I1(\PBL0_MC.D2_PT_1 ),
    .O(\PBL0_MC.D2 )
  );
  X_BUF \PBL1_MC.Q_1408  (
    .I(\PBL1_MC.Q_tsimrenamed_net_ ),
    .O(\PBL1_MC.Q )
  );
  X_BUF \PBL1_MC.Q_tsimrenamed_net__1409  (
    .I(\PBL1_MC.D ),
    .O(\PBL1_MC.Q_tsimrenamed_net_ )
  );
  X_XOR2 \PBL1_MC.D_1410  (
    .I0(\PBL1_MC.D1 ),
    .I1(\PBL1_MC.D2 ),
    .O(\PBL1_MC.D )
  );
  X_ZERO \PBL1_MC.D1_1411  (
    .O(\PBL1_MC.D1 )
  );
  X_AND2 \PBL1_MC.D2_PT_0_1412  (
    .I0(\PBH1_MC.UIM ),
    .I1(\PBH1_MC.UIM ),
    .O(\PBL1_MC.D2_PT_0 )
  );
  X_AND4 \PBL1_MC.D2_PT_1_1413  (
    .I0(\NlwInverterSignal_PBL1_MC.D2_PT_1/IN0 ),
    .I1(\NlwInverterSignal_PBL1_MC.D2_PT_1/IN1 ),
    .I2(\NlwInverterSignal_PBL1_MC.D2_PT_1/IN2 ),
    .I3(\NlwInverterSignal_PBL1_MC.D2_PT_1/IN3 ),
    .O(\PBL1_MC.D2_PT_1 )
  );
  X_OR2 \PBL1_MC.D2_1414  (
    .I0(\PBL1_MC.D2_PT_0 ),
    .I1(\PBL1_MC.D2_PT_1 ),
    .O(\PBL1_MC.D2 )
  );
  X_BUF \PresEn_MC.Q_1415  (
    .I(\PresEn_MC.Q_tsimrenamed_net_ ),
    .O(\PresEn_MC.Q )
  );
  X_OR2 PresEn_MC_tsimcreated_prld__1416 (
    .I0(\FOOBAR2__ctinst/7 ),
    .I1(PRLD),
    .O(PresEn_MC_tsimcreated_prld_)
  );
  X_FF \PresEn_MC.REG  (
    .I(\PresEn_MC.D ),
    .CE(\FOOBAR19__ctinst/4 ),
    .CLK(\PresEn_MC.REG_tsimcreated_inv_Mclk_II/FCLK ),
    .SET(PresEn_MC_tsimcreated_prld_),
    .RST(Gnd),
    .O(\PresEn_MC.Q_tsimrenamed_net_ )
  );
  X_INV \PresEn_MC.REG_tsimcreated_inv_Mclk_II/FCLK_1417  (
    .I(\Mclk_II/FCLK ),
    .O(\PresEn_MC.REG_tsimcreated_inv_Mclk_II/FCLK )
  );
  X_XOR2 \PresEn_MC.D_1418  (
    .I0(\NlwInverterSignal_PresEn_MC.D/IN0 ),
    .I1(\PresEn_MC.D2 ),
    .O(\PresEn_MC.D )
  );
  X_AND2 \PresEn_MC.D1_1419  (
    .I0(\AD<0>_II/UIM ),
    .I1(\AD<0>_II/UIM ),
    .O(\PresEn_MC.D1 )
  );
  X_ZERO \PresEn_MC.D2_1420  (
    .O(\PresEn_MC.D2 )
  );
  X_BUF DCORSENSORw_1421 (
    .I(\DCORSENSORw_MC.Q ),
    .O(DCORSENSORw)
  );
  X_BUF \DCORSENSORw_MC.Q_1422  (
    .I(\DCORSENSORw_MC.D ),
    .O(\DCORSENSORw_MC.Q )
  );
  X_XOR2 \DCORSENSORw_MC.D_1423  (
    .I0(\DCORSENSORw_MC.D1 ),
    .I1(\DCORSENSORw_MC.D2 ),
    .O(\DCORSENSORw_MC.D )
  );
  X_AND16 \DCORSENSORw_MC.D1_1424  (
    .I0(\NlwInverterSignal_DCORSENSORw_MC.D1/IN0 ),
    .I1(\RD_II/UIM ),
    .I2(\NlwInverterSignal_DCORSENSORw_MC.D1/IN2 ),
    .I3(\NlwInverterSignal_DCORSENSORw_MC.D1/IN3 ),
    .I4(\NlwInverterSignal_DCORSENSORw_MC.D1/IN4 ),
    .I5(\NlwInverterSignal_DCORSENSORw_MC.D1/IN5 ),
    .I6(\NlwInverterSignal_DCORSENSORw_MC.D1/IN6 ),
    .I7(U2_ADDR_reg[3]),
    .I8(\NlwInverterSignal_DCORSENSORw_MC.D1/IN8 ),
    .I9(U2_ADDR_reg[2]),
    .I10(Vcc),
    .I11(Vcc),
    .I12(Vcc),
    .I13(Vcc),
    .I14(Vcc),
    .I15(Vcc),
    .O(\DCORSENSORw_MC.D1 )
  );
  X_ZERO \DCORSENSORw_MC.D2_1425  (
    .O(\DCORSENSORw_MC.D2 )
  );
  X_BUF \PresSlct_MC.Q_1426  (
    .I(\PresSlct_MC.Q_tsimrenamed_net_ ),
    .O(\PresSlct_MC.Q )
  );
  X_OR2 PresSlct_MC_tsimcreated_prld__1427 (
    .I0(\FOOBAR3__ctinst/7 ),
    .I1(PRLD),
    .O(PresSlct_MC_tsimcreated_prld_)
  );
  X_FF \PresSlct_MC.REG  (
    .I(\PresSlct_MC.D ),
    .CE(\FOOBAR19__ctinst/4 ),
    .CLK(\PresSlct_MC.REG_tsimcreated_inv_Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PresSlct_MC_tsimcreated_prld_),
    .O(\PresSlct_MC.Q_tsimrenamed_net_ )
  );
  X_INV \PresSlct_MC.REG_tsimcreated_inv_Mclk_II/FCLK_1428  (
    .I(\Mclk_II/FCLK ),
    .O(\PresSlct_MC.REG_tsimcreated_inv_Mclk_II/FCLK )
  );
  X_XOR2 \PresSlct_MC.D_1429  (
    .I0(\PresSlct_MC.D1 ),
    .I1(\PresSlct_MC.D2 ),
    .O(\PresSlct_MC.D )
  );
  X_AND2 \PresSlct_MC.D1_1430  (
    .I0(\AD<1>_II/UIM ),
    .I1(\AD<1>_II/UIM ),
    .O(\PresSlct_MC.D1 )
  );
  X_ZERO \PresSlct_MC.D2_1431  (
    .O(\PresSlct_MC.D2 )
  );
  X_BUF \SCLout_MC.Q_1432  (
    .I(\SCLout_MC.Q_tsimrenamed_net_ ),
    .O(\SCLout_MC.Q )
  );
  X_BUF \SCLout_MC.Q_tsimrenamed_net__1433  (
    .I(\SCLout_MC.D ),
    .O(\SCLout_MC.Q_tsimrenamed_net_ )
  );
  X_XOR2 \SCLout_MC.D_1434  (
    .I0(\SCLout_MC.D1 ),
    .I1(\SCLout_MC.D2 ),
    .O(\SCLout_MC.D )
  );
  X_AND2 \SCLout_MC.D1_1435  (
    .I0(\SCL_II/UIM ),
    .I1(\SCL_II/UIM ),
    .O(\SCLout_MC.D1 )
  );
  X_ZERO \SCLout_MC.D2_1436  (
    .O(\SCLout_MC.D2 )
  );
  X_BUF \TP10_MC.Q_1437  (
    .I(\TP10_MC.Q_tsimrenamed_net_ ),
    .O(\TP10_MC.Q )
  );
  X_BUF \TP10_MC.Q_tsimrenamed_net__1438  (
    .I(\TP10_MC.D ),
    .O(\TP10_MC.Q_tsimrenamed_net_ )
  );
  X_XOR2 \TP10_MC.D_1439  (
    .I0(\TP10_MC.D1 ),
    .I1(\TP10_MC.D2 ),
    .O(\TP10_MC.D )
  );
  X_AND2 \TP10_MC.D1_1440  (
    .I0(\SCLreset_II/UIM ),
    .I1(\SCLreset_II/UIM ),
    .O(\TP10_MC.D1 )
  );
  X_ZERO \TP10_MC.D2_1441  (
    .O(\TP10_MC.D2 )
  );
  X_BUF \TP11_MC.Q_1442  (
    .I(\TP11_MC.Q_tsimrenamed_net_ ),
    .O(\TP11_MC.Q )
  );
  X_BUF \TP11_MC.Q_tsimrenamed_net__1443  (
    .I(\TP11_MC.D ),
    .O(\TP11_MC.Q_tsimrenamed_net_ )
  );
  X_XOR2 \TP11_MC.D_1444  (
    .I0(\NlwInverterSignal_TP11_MC.D/IN0 ),
    .I1(\TP11_MC.D2 ),
    .O(\TP11_MC.D )
  );
  X_AND2 \TP11_MC.D1_1445  (
    .I0(\MSPReset_II/UIM ),
    .I1(\MSPReset_II/UIM ),
    .O(\TP11_MC.D1 )
  );
  X_ZERO \TP11_MC.D2_1446  (
    .O(\TP11_MC.D2 )
  );
  X_BUF \TmpEn_MC.Q_1447  (
    .I(\TmpEn_MC.Q_tsimrenamed_net_ ),
    .O(\TmpEn_MC.Q )
  );
  X_OR2 TmpEn_MC_tsimcreated_prld__1448 (
    .I0(\FOOBAR2__ctinst/7 ),
    .I1(PRLD),
    .O(TmpEn_MC_tsimcreated_prld_)
  );
  X_FF \TmpEn_MC.REG  (
    .I(\TmpEn_MC.D ),
    .CE(\FOOBAR19__ctinst/4 ),
    .CLK(\TmpEn_MC.REG_tsimcreated_inv_Mclk_II/FCLK ),
    .SET(TmpEn_MC_tsimcreated_prld_),
    .RST(Gnd),
    .O(\TmpEn_MC.Q_tsimrenamed_net_ )
  );
  X_INV \TmpEn_MC.REG_tsimcreated_inv_Mclk_II/FCLK_1449  (
    .I(\Mclk_II/FCLK ),
    .O(\TmpEn_MC.REG_tsimcreated_inv_Mclk_II/FCLK )
  );
  X_XOR2 \TmpEn_MC.D_1450  (
    .I0(\NlwInverterSignal_TmpEn_MC.D/IN0 ),
    .I1(\TmpEn_MC.D2 ),
    .O(\TmpEn_MC.D )
  );
  X_AND2 \TmpEn_MC.D1_1451  (
    .I0(\AD<2>_II/UIM ),
    .I1(\AD<2>_II/UIM ),
    .O(\TmpEn_MC.D1 )
  );
  X_ZERO \TmpEn_MC.D2_1452  (
    .O(\TmpEn_MC.D2 )
  );
  X_BUF \TmpSlct_MC.Q_1453  (
    .I(\TmpSlct_MC.Q_tsimrenamed_net_ ),
    .O(\TmpSlct_MC.Q )
  );
  X_OR2 TmpSlct_MC_tsimcreated_prld__1454 (
    .I0(\FOOBAR3__ctinst/7 ),
    .I1(PRLD),
    .O(TmpSlct_MC_tsimcreated_prld_)
  );
  X_FF \TmpSlct_MC.REG  (
    .I(\TmpSlct_MC.D ),
    .CE(\FOOBAR19__ctinst/4 ),
    .CLK(\TmpSlct_MC.REG_tsimcreated_inv_Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(TmpSlct_MC_tsimcreated_prld_),
    .O(\TmpSlct_MC.Q_tsimrenamed_net_ )
  );
  X_INV \TmpSlct_MC.REG_tsimcreated_inv_Mclk_II/FCLK_1455  (
    .I(\Mclk_II/FCLK ),
    .O(\TmpSlct_MC.REG_tsimcreated_inv_Mclk_II/FCLK )
  );
  X_XOR2 \TmpSlct_MC.D_1456  (
    .I0(\TmpSlct_MC.D1 ),
    .I1(\TmpSlct_MC.D2 ),
    .O(\TmpSlct_MC.D )
  );
  X_AND2 \TmpSlct_MC.D1_1457  (
    .I0(\AD<3>_II/UIM ),
    .I1(\AD<3>_II/UIM ),
    .O(\TmpSlct_MC.D1 )
  );
  X_ZERO \TmpSlct_MC.D2_1458  (
    .O(\TmpSlct_MC.D2 )
  );
  X_BUF \outDATA<2>\$WA0.UIM_1459  (
    .I(\outDATA<2>\$WA0.UIM_MC.Q ),
    .O(\outDATA<2>\$WA0.UIM )
  );
  X_BUF \outDATA<2>\$WA0.UIM_MC.Q_1460  (
    .I(\outDATA<2>\$WA0.UIM_MC.D ),
    .O(\outDATA<2>\$WA0.UIM_MC.Q )
  );
  X_XOR2 \outDATA<2>\$WA0.UIM_MC.D_1461  (
    .I0(\outDATA<2>\$WA0.UIM_MC.D1 ),
    .I1(\outDATA<2>\$WA0.UIM_MC.D2 ),
    .O(\outDATA<2>\$WA0.UIM_MC.D )
  );
  X_AND2 \outDATA<2>\$WA0.UIM_MC.D1_1462  (
    .I0(U11_U3_counterr[2]),
    .I1(U11_U3_counterr[2]),
    .O(\outDATA<2>\$WA0.UIM_MC.D1 )
  );
  X_ZERO \outDATA<2>\$WA0.UIM_MC.D2_1463  (
    .O(\outDATA<2>\$WA0.UIM_MC.D2 )
  );
  X_BUF \outDATA<2>\$WA1.UIM_1464  (
    .I(\outDATA<2>\$WA1.UIM_MC.Q ),
    .O(\outDATA<2>\$WA1.UIM )
  );
  X_BUF \outDATA<2>\$WA1.UIM_MC.Q_1465  (
    .I(\outDATA<2>\$WA1.UIM_MC.D ),
    .O(\outDATA<2>\$WA1.UIM_MC.Q )
  );
  X_XOR2 \outDATA<2>\$WA1.UIM_MC.D_1466  (
    .I0(\outDATA<2>\$WA1.UIM_MC.D1 ),
    .I1(\outDATA<2>\$WA1.UIM_MC.D2 ),
    .O(\outDATA<2>\$WA1.UIM_MC.D )
  );
  X_AND2 \outDATA<2>\$WA1.UIM_MC.D1_1467  (
    .I0(\I2CS<2>_II/UIM ),
    .I1(\I2CS<2>_II/UIM ),
    .O(\outDATA<2>\$WA1.UIM_MC.D1 )
  );
  X_ZERO \outDATA<2>\$WA1.UIM_MC.D2_1468  (
    .O(\outDATA<2>\$WA1.UIM_MC.D2 )
  );
  X_BUF \outDATA<2>\$WA2.UIM_1469  (
    .I(\outDATA<2>\$WA2.UIM_MC.Q ),
    .O(\outDATA<2>\$WA2.UIM )
  );
  X_BUF \outDATA<2>\$WA2.UIM_MC.Q_1470  (
    .I(\outDATA<2>\$WA2.UIM_MC.D ),
    .O(\outDATA<2>\$WA2.UIM_MC.Q )
  );
  X_XOR2 \outDATA<2>\$WA2.UIM_MC.D_1471  (
    .I0(\outDATA<2>\$WA2.UIM_MC.D1 ),
    .I1(\outDATA<2>\$WA2.UIM_MC.D2 ),
    .O(\outDATA<2>\$WA2.UIM_MC.D )
  );
  X_AND2 \outDATA<2>\$WA2.UIM_MC.D1_1472  (
    .I0(\Home0_II/UIM ),
    .I1(\Home0_II/UIM ),
    .O(\outDATA<2>\$WA2.UIM_MC.D1 )
  );
  X_ZERO \outDATA<2>\$WA2.UIM_MC.D2_1473  (
    .O(\outDATA<2>\$WA2.UIM_MC.D2 )
  );
  X_BUF \outDATA<2>\$WA3.UIM_1474  (
    .I(\outDATA<2>\$WA3.UIM_MC.Q ),
    .O(\outDATA<2>\$WA3.UIM )
  );
  X_BUF \outDATA<2>\$WA3.UIM_MC.Q_1475  (
    .I(\outDATA<2>\$WA3.UIM_MC.D ),
    .O(\outDATA<2>\$WA3.UIM_MC.Q )
  );
  X_XOR2 \outDATA<2>\$WA3.UIM_MC.D_1476  (
    .I0(\outDATA<2>\$WA3.UIM_MC.D1 ),
    .I1(\outDATA<2>\$WA3.UIM_MC.D2 ),
    .O(\outDATA<2>\$WA3.UIM_MC.D )
  );
  X_ZERO \outDATA<2>\$WA3.UIM_MC.D1_1477  (
    .O(\outDATA<2>\$WA3.UIM_MC.D1 )
  );
  X_AND2 \outDATA<2>\$WA3.UIM_MC.D2_PT_0_1478  (
    .I0(NET2528),
    .I1(\U4/Flgreg [2]),
    .O(\outDATA<2>\$WA3.UIM_MC.D2_PT_0 )
  );
  X_AND2 \outDATA<2>\$WA3.UIM_MC.D2_PT_1_1479  (
    .I0(\NlwInverterSignal_outDATA<2>\$WA3.UIM_MC.D2_PT_1/IN0 ),
    .I1(\Enc033FLG_II/UIM ),
    .O(\outDATA<2>\$WA3.UIM_MC.D2_PT_1 )
  );
  X_OR2 \outDATA<2>\$WA3.UIM_MC.D2_1480  (
    .I0(\outDATA<2>\$WA3.UIM_MC.D2_PT_0 ),
    .I1(\outDATA<2>\$WA3.UIM_MC.D2_PT_1 ),
    .O(\outDATA<2>\$WA3.UIM_MC.D2 )
  );
  X_BUF \outDATA<2>\$WA5.UIM_1481  (
    .I(\outDATA<2>\$WA5.UIM_MC.Q ),
    .O(\outDATA<2>\$WA5.UIM )
  );
  X_BUF \outDATA<2>\$WA5.UIM_MC.Q_1482  (
    .I(\outDATA<2>\$WA5.UIM_MC.D ),
    .O(\outDATA<2>\$WA5.UIM_MC.Q )
  );
  X_XOR2 \outDATA<2>\$WA5.UIM_MC.D_1483  (
    .I0(\outDATA<2>\$WA5.UIM_MC.D1 ),
    .I1(\outDATA<2>\$WA5.UIM_MC.D2 ),
    .O(\outDATA<2>\$WA5.UIM_MC.D )
  );
  X_ZERO \outDATA<2>\$WA5.UIM_MC.D1_1484  (
    .O(\outDATA<2>\$WA5.UIM_MC.D1 )
  );
  X_AND2 \outDATA<2>\$WA5.UIM_MC.D2_PT_0_1485  (
    .I0(DCOR0CNTLOWr),
    .I1(\U1/U3/holdingreg0 [2]),
    .O(\outDATA<2>\$WA5.UIM_MC.D2_PT_0 )
  );
  X_AND3 \outDATA<2>\$WA5.UIM_MC.D2_PT_1_1486  (
    .I0(\NlwInverterSignal_outDATA<2>\$WA5.UIM_MC.D2_PT_1/IN0 ),
    .I1(DCOR1CNTLOWr),
    .I2(\U1/U3/holdingreg1 [2]),
    .O(\outDATA<2>\$WA5.UIM_MC.D2_PT_1 )
  );
  X_AND4 \outDATA<2>\$WA5.UIM_MC.D2_PT_2_1487  (
    .I0(\NlwInverterSignal_outDATA<2>\$WA5.UIM_MC.D2_PT_2/IN0 ),
    .I1(\NlwInverterSignal_outDATA<2>\$WA5.UIM_MC.D2_PT_2/IN1 ),
    .I2(DCOR0CNTHIGHr),
    .I3(\U1/U3/holdingreg0 [10]),
    .O(\outDATA<2>\$WA5.UIM_MC.D2_PT_2 )
  );
  X_AND4 \outDATA<2>\$WA5.UIM_MC.D2_PT_3_1488  (
    .I0(\NlwInverterSignal_outDATA<2>\$WA5.UIM_MC.D2_PT_3/IN0 ),
    .I1(\NlwInverterSignal_outDATA<2>\$WA5.UIM_MC.D2_PT_3/IN1 ),
    .I2(\NlwInverterSignal_outDATA<2>\$WA5.UIM_MC.D2_PT_3/IN2 ),
    .I3(\U1/U3/holdingreg1 [10]),
    .O(\outDATA<2>\$WA5.UIM_MC.D2_PT_3 )
  );
  X_OR4 \outDATA<2>\$WA5.UIM_MC.D2_1489  (
    .I0(\outDATA<2>\$WA5.UIM_MC.D2_PT_0 ),
    .I1(\outDATA<2>\$WA5.UIM_MC.D2_PT_1 ),
    .I2(\outDATA<2>\$WA5.UIM_MC.D2_PT_2 ),
    .I3(\outDATA<2>\$WA5.UIM_MC.D2_PT_3 ),
    .O(\outDATA<2>\$WA5.UIM_MC.D2 )
  );
  X_BUF \U1/U3/holdingreg0<2>  (
    .I(\U1/U3/holdingreg0<2>_MC.Q ),
    .O(\U1/U3/holdingreg0 [2])
  );
  X_FF \U1/U3/holdingreg0<2>_MC.REG  (
    .I(\U1/U3/holdingreg0<2>_MC.D ),
    .CE(Vcc),
    .CLK(\U1/U3/holdingreg0<2>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\U1/U3/holdingreg0<2>_MC.Q )
  );
  X_INV \U1/U3/holdingreg0<2>_MC.REG_tsimcreated_inv_Mclk_II/FCLK_1490  (
    .I(\Mclk_II/FCLK ),
    .O(\U1/U3/holdingreg0<2>_MC.REG_tsimcreated_inv_Mclk_II/FCLK )
  );
  X_XOR2 \U1/U3/holdingreg0<2>_MC.D_1491  (
    .I0(\U1/U3/holdingreg0<2>_MC.D1 ),
    .I1(\U1/U3/holdingreg0<2>_MC.D2 ),
    .O(\U1/U3/holdingreg0<2>_MC.D )
  );
  X_ZERO \U1/U3/holdingreg0<2>_MC.D1_1492  (
    .O(\U1/U3/holdingreg0<2>_MC.D1 )
  );
  X_AND2 \U1/U3/holdingreg0<2>_MC.D2_PT_0_1493  (
    .I0(N_PZ_938),
    .I1(\U1/U3/holdingreg0 [2]),
    .O(\U1/U3/holdingreg0<2>_MC.D2_PT_0 )
  );
  X_AND4 \U1/U3/holdingreg0<2>_MC.D2_PT_1_1494  (
    .I0(\MSPReset_II/UIM ),
    .I1(\NlwInverterSignal_U1/U3/holdingreg0<2>_MC.D2_PT_1/IN1 ),
    .I2(U2_ASedge),
    .I3(\U1/Channel0 [2]),
    .O(\U1/U3/holdingreg0<2>_MC.D2_PT_1 )
  );
  X_OR2 \U1/U3/holdingreg0<2>_MC.D2_1495  (
    .I0(\U1/U3/holdingreg0<2>_MC.D2_PT_0 ),
    .I1(\U1/U3/holdingreg0<2>_MC.D2_PT_1 ),
    .O(\U1/U3/holdingreg0<2>_MC.D2 )
  );
  X_BUF \U1/U3/holdingreg1<2>  (
    .I(\U1/U3/holdingreg1<2>_MC.Q ),
    .O(\U1/U3/holdingreg1 [2])
  );
  X_FF \U1/U3/holdingreg1<2>_MC.REG  (
    .I(\U1/U3/holdingreg1<2>_MC.D ),
    .CE(Vcc),
    .CLK(\U1/U3/holdingreg1<2>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\U1/U3/holdingreg1<2>_MC.Q )
  );
  X_INV \U1/U3/holdingreg1<2>_MC.REG_tsimcreated_inv_Mclk_II/FCLK_1496  (
    .I(\Mclk_II/FCLK ),
    .O(\U1/U3/holdingreg1<2>_MC.REG_tsimcreated_inv_Mclk_II/FCLK )
  );
  X_XOR2 \U1/U3/holdingreg1<2>_MC.D_1497  (
    .I0(\U1/U3/holdingreg1<2>_MC.D1 ),
    .I1(\U1/U3/holdingreg1<2>_MC.D2 ),
    .O(\U1/U3/holdingreg1<2>_MC.D )
  );
  X_ZERO \U1/U3/holdingreg1<2>_MC.D1_1498  (
    .O(\U1/U3/holdingreg1<2>_MC.D1 )
  );
  X_AND2 \U1/U3/holdingreg1<2>_MC.D2_PT_0_1499  (
    .I0(N_PZ_938),
    .I1(\U1/U3/holdingreg1 [2]),
    .O(\U1/U3/holdingreg1<2>_MC.D2_PT_0 )
  );
  X_AND4 \U1/U3/holdingreg1<2>_MC.D2_PT_1_1500  (
    .I0(\MSPReset_II/UIM ),
    .I1(\NlwInverterSignal_U1/U3/holdingreg1<2>_MC.D2_PT_1/IN1 ),
    .I2(U2_ASedge),
    .I3(\U1/Channel1 [2]),
    .O(\U1/U3/holdingreg1<2>_MC.D2_PT_1 )
  );
  X_OR2 \U1/U3/holdingreg1<2>_MC.D2_1501  (
    .I0(\U1/U3/holdingreg1<2>_MC.D2_PT_0 ),
    .I1(\U1/U3/holdingreg1<2>_MC.D2_PT_1 ),
    .O(\U1/U3/holdingreg1<2>_MC.D2 )
  );
  X_BUF \U1/U3/holdingreg0<10>  (
    .I(\U1/U3/holdingreg0<10>_MC.Q ),
    .O(\U1/U3/holdingreg0 [10])
  );
  X_FF \U1/U3/holdingreg0<10>_MC.REG  (
    .I(\U1/U3/holdingreg0<10>_MC.D ),
    .CE(Vcc),
    .CLK(\U1/U3/holdingreg0<10>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\U1/U3/holdingreg0<10>_MC.Q )
  );
  X_INV \U1/U3/holdingreg0<10>_MC.REG_tsimcreated_inv_Mclk_II/FCLK_1502  (
    .I(\Mclk_II/FCLK ),
    .O(\U1/U3/holdingreg0<10>_MC.REG_tsimcreated_inv_Mclk_II/FCLK )
  );
  X_XOR2 \U1/U3/holdingreg0<10>_MC.D_1503  (
    .I0(\U1/U3/holdingreg0<10>_MC.D1 ),
    .I1(\U1/U3/holdingreg0<10>_MC.D2 ),
    .O(\U1/U3/holdingreg0<10>_MC.D )
  );
  X_ZERO \U1/U3/holdingreg0<10>_MC.D1_1504  (
    .O(\U1/U3/holdingreg0<10>_MC.D1 )
  );
  X_AND2 \U1/U3/holdingreg0<10>_MC.D2_PT_0_1505  (
    .I0(N_PZ_938),
    .I1(\U1/U3/holdingreg0 [10]),
    .O(\U1/U3/holdingreg0<10>_MC.D2_PT_0 )
  );
  X_AND4 \U1/U3/holdingreg0<10>_MC.D2_PT_1_1506  (
    .I0(\MSPReset_II/UIM ),
    .I1(\NlwInverterSignal_U1/U3/holdingreg0<10>_MC.D2_PT_1/IN1 ),
    .I2(U2_ASedge),
    .I3(\U1/Channel0 [10]),
    .O(\U1/U3/holdingreg0<10>_MC.D2_PT_1 )
  );
  X_OR2 \U1/U3/holdingreg0<10>_MC.D2_1507  (
    .I0(\U1/U3/holdingreg0<10>_MC.D2_PT_0 ),
    .I1(\U1/U3/holdingreg0<10>_MC.D2_PT_1 ),
    .O(\U1/U3/holdingreg0<10>_MC.D2 )
  );
  X_BUF \U1/U3/holdingreg1<10>  (
    .I(\U1/U3/holdingreg1<10>_MC.Q ),
    .O(\U1/U3/holdingreg1 [10])
  );
  X_FF \U1/U3/holdingreg1<10>_MC.REG  (
    .I(\U1/U3/holdingreg1<10>_MC.D ),
    .CE(Vcc),
    .CLK(\U1/U3/holdingreg1<10>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\U1/U3/holdingreg1<10>_MC.Q )
  );
  X_INV \U1/U3/holdingreg1<10>_MC.REG_tsimcreated_inv_Mclk_II/FCLK_1508  (
    .I(\Mclk_II/FCLK ),
    .O(\U1/U3/holdingreg1<10>_MC.REG_tsimcreated_inv_Mclk_II/FCLK )
  );
  X_XOR2 \U1/U3/holdingreg1<10>_MC.D_1509  (
    .I0(\U1/U3/holdingreg1<10>_MC.D1 ),
    .I1(\U1/U3/holdingreg1<10>_MC.D2 ),
    .O(\U1/U3/holdingreg1<10>_MC.D )
  );
  X_ZERO \U1/U3/holdingreg1<10>_MC.D1_1510  (
    .O(\U1/U3/holdingreg1<10>_MC.D1 )
  );
  X_AND2 \U1/U3/holdingreg1<10>_MC.D2_PT_0_1511  (
    .I0(N_PZ_938),
    .I1(\U1/U3/holdingreg1 [10]),
    .O(\U1/U3/holdingreg1<10>_MC.D2_PT_0 )
  );
  X_AND4 \U1/U3/holdingreg1<10>_MC.D2_PT_1_1512  (
    .I0(\MSPReset_II/UIM ),
    .I1(\NlwInverterSignal_U1/U3/holdingreg1<10>_MC.D2_PT_1/IN1 ),
    .I2(U2_ASedge),
    .I3(\U1/Channel1 [10]),
    .O(\U1/U3/holdingreg1<10>_MC.D2_PT_1 )
  );
  X_OR2 \U1/U3/holdingreg1<10>_MC.D2_1513  (
    .I0(\U1/U3/holdingreg1<10>_MC.D2_PT_0 ),
    .I1(\U1/U3/holdingreg1<10>_MC.D2_PT_1 ),
    .O(\U1/U3/holdingreg1<10>_MC.D2 )
  );
  X_BUF \outDATA<2>\$WA6.UIM_1514  (
    .I(\outDATA<2>\$WA6.UIM_MC.Q ),
    .O(\outDATA<2>\$WA6.UIM )
  );
  X_BUF \outDATA<2>\$WA6.UIM_MC.Q_1515  (
    .I(\outDATA<2>\$WA6.UIM_MC.D ),
    .O(\outDATA<2>\$WA6.UIM_MC.Q )
  );
  X_XOR2 \outDATA<2>\$WA6.UIM_MC.D_1516  (
    .I0(\outDATA<2>\$WA6.UIM_MC.D1 ),
    .I1(\outDATA<2>\$WA6.UIM_MC.D2 ),
    .O(\outDATA<2>\$WA6.UIM_MC.D )
  );
  X_ZERO \outDATA<2>\$WA6.UIM_MC.D1_1517  (
    .O(\outDATA<2>\$WA6.UIM_MC.D1 )
  );
  X_AND2 \outDATA<2>\$WA6.UIM_MC.D2_PT_0_1518  (
    .I0(DCOR0THRESLOWr),
    .I1(\U1/U4/Latch0r [2]),
    .O(\outDATA<2>\$WA6.UIM_MC.D2_PT_0 )
  );
  X_AND3 \outDATA<2>\$WA6.UIM_MC.D2_PT_1_1519  (
    .I0(NET2482),
    .I1(\NlwInverterSignal_outDATA<2>\$WA6.UIM_MC.D2_PT_1/IN1 ),
    .I2(DCORIFGr),
    .O(\outDATA<2>\$WA6.UIM_MC.D2_PT_1 )
  );
  X_AND4 \outDATA<2>\$WA6.UIM_MC.D2_PT_2_1520  (
    .I0(\NlwInverterSignal_outDATA<2>\$WA6.UIM_MC.D2_PT_2/IN0 ),
    .I1(\NlwInverterSignal_outDATA<2>\$WA6.UIM_MC.D2_PT_2/IN1 ),
    .I2(DCOR0THRESHIGHr),
    .I3(\U1/U4/Latch0r [10]),
    .O(\outDATA<2>\$WA6.UIM_MC.D2_PT_2 )
  );
  X_AND5 \outDATA<2>\$WA6.UIM_MC.D2_PT_3_1521  (
    .I0(\NlwInverterSignal_outDATA<2>\$WA6.UIM_MC.D2_PT_3/IN0 ),
    .I1(\NlwInverterSignal_outDATA<2>\$WA6.UIM_MC.D2_PT_3/IN1 ),
    .I2(\NlwInverterSignal_outDATA<2>\$WA6.UIM_MC.D2_PT_3/IN2 ),
    .I3(DCOR1THRESLOWr),
    .I4(\U1/U4/Latch1r [2]),
    .O(\outDATA<2>\$WA6.UIM_MC.D2_PT_3 )
  );
  X_AND5 \outDATA<2>\$WA6.UIM_MC.D2_PT_4_1522  (
    .I0(\NlwInverterSignal_outDATA<2>\$WA6.UIM_MC.D2_PT_4/IN0 ),
    .I1(\NlwInverterSignal_outDATA<2>\$WA6.UIM_MC.D2_PT_4/IN1 ),
    .I2(\NlwInverterSignal_outDATA<2>\$WA6.UIM_MC.D2_PT_4/IN2 ),
    .I3(\NlwInverterSignal_outDATA<2>\$WA6.UIM_MC.D2_PT_4/IN3 ),
    .I4(\U1/U4/Latch1r [10]),
    .O(\outDATA<2>\$WA6.UIM_MC.D2_PT_4 )
  );
  X_OR5 \outDATA<2>\$WA6.UIM_MC.D2_1523  (
    .I0(\outDATA<2>\$WA6.UIM_MC.D2_PT_0 ),
    .I1(\outDATA<2>\$WA6.UIM_MC.D2_PT_1 ),
    .I2(\outDATA<2>\$WA6.UIM_MC.D2_PT_2 ),
    .I3(\outDATA<2>\$WA6.UIM_MC.D2_PT_3 ),
    .I4(\outDATA<2>\$WA6.UIM_MC.D2_PT_4 ),
    .O(\outDATA<2>\$WA6.UIM_MC.D2 )
  );
  X_BUF \U1/U4/Latch0r<2>  (
    .I(\U1/U4/Latch0r<2>_MC.Q ),
    .O(\U1/U4/Latch0r [2])
  );
  X_FF \U1/U4/Latch0r<2>_MC.REG  (
    .I(\U1/U4/Latch0r<2>_MC.D ),
    .CE(Vcc),
    .CLK(\U1/U4/Latch0r<2>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\U1/U4/Latch0r<2>_MC.Q )
  );
  X_INV \U1/U4/Latch0r<2>_MC.REG_tsimcreated_inv_Mclk_II/FCLK_1524  (
    .I(\Mclk_II/FCLK ),
    .O(\U1/U4/Latch0r<2>_MC.REG_tsimcreated_inv_Mclk_II/FCLK )
  );
  X_XOR2 \U1/U4/Latch0r<2>_MC.D_1525  (
    .I0(\U1/U4/Latch0r<2>_MC.D1 ),
    .I1(\U1/U4/Latch0r<2>_MC.D2 ),
    .O(\U1/U4/Latch0r<2>_MC.D )
  );
  X_ZERO \U1/U4/Latch0r<2>_MC.D1_1526  (
    .O(\U1/U4/Latch0r<2>_MC.D1 )
  );
  X_AND3 \U1/U4/Latch0r<2>_MC.D2_PT_0_1527  (
    .I0(\MSPReset_II/UIM ),
    .I1(\U1/Channel0 [2]),
    .I2(N_PZ_963),
    .O(\U1/U4/Latch0r<2>_MC.D2_PT_0 )
  );
  X_AND3 \U1/U4/Latch0r<2>_MC.D2_PT_1_1528  (
    .I0(\MSPReset_II/UIM ),
    .I1(\NlwInverterSignal_U1/U4/Latch0r<2>_MC.D2_PT_1/IN1 ),
    .I2(\U1/U4/Latch0r [2]),
    .O(\U1/U4/Latch0r<2>_MC.D2_PT_1 )
  );
  X_OR2 \U1/U4/Latch0r<2>_MC.D2_1529  (
    .I0(\U1/U4/Latch0r<2>_MC.D2_PT_0 ),
    .I1(\U1/U4/Latch0r<2>_MC.D2_PT_1 ),
    .O(\U1/U4/Latch0r<2>_MC.D2 )
  );
  X_BUF \U1/U4/Latch0r<10>  (
    .I(\U1/U4/Latch0r<10>_MC.Q ),
    .O(\U1/U4/Latch0r [10])
  );
  X_FF \U1/U4/Latch0r<10>_MC.REG  (
    .I(\U1/U4/Latch0r<10>_MC.D ),
    .CE(Vcc),
    .CLK(\U1/U4/Latch0r<10>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\U1/U4/Latch0r<10>_MC.Q )
  );
  X_INV \U1/U4/Latch0r<10>_MC.REG_tsimcreated_inv_Mclk_II/FCLK_1530  (
    .I(\Mclk_II/FCLK ),
    .O(\U1/U4/Latch0r<10>_MC.REG_tsimcreated_inv_Mclk_II/FCLK )
  );
  X_XOR2 \U1/U4/Latch0r<10>_MC.D_1531  (
    .I0(\U1/U4/Latch0r<10>_MC.D1 ),
    .I1(\U1/U4/Latch0r<10>_MC.D2 ),
    .O(\U1/U4/Latch0r<10>_MC.D )
  );
  X_ZERO \U1/U4/Latch0r<10>_MC.D1_1532  (
    .O(\U1/U4/Latch0r<10>_MC.D1 )
  );
  X_AND3 \U1/U4/Latch0r<10>_MC.D2_PT_0_1533  (
    .I0(\MSPReset_II/UIM ),
    .I1(\U1/Channel0 [10]),
    .I2(N_PZ_963),
    .O(\U1/U4/Latch0r<10>_MC.D2_PT_0 )
  );
  X_AND3 \U1/U4/Latch0r<10>_MC.D2_PT_1_1534  (
    .I0(\MSPReset_II/UIM ),
    .I1(\NlwInverterSignal_U1/U4/Latch0r<10>_MC.D2_PT_1/IN1 ),
    .I2(\U1/U4/Latch0r [10]),
    .O(\U1/U4/Latch0r<10>_MC.D2_PT_1 )
  );
  X_OR2 \U1/U4/Latch0r<10>_MC.D2_1535  (
    .I0(\U1/U4/Latch0r<10>_MC.D2_PT_0 ),
    .I1(\U1/U4/Latch0r<10>_MC.D2_PT_1 ),
    .O(\U1/U4/Latch0r<10>_MC.D2 )
  );
  X_BUF \U1/U4/Latch1r<2>  (
    .I(\U1/U4/Latch1r<2>_MC.Q ),
    .O(\U1/U4/Latch1r [2])
  );
  X_FF \U1/U4/Latch1r<2>_MC.REG  (
    .I(\U1/U4/Latch1r<2>_MC.D ),
    .CE(Vcc),
    .CLK(\U1/U4/Latch1r<2>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\U1/U4/Latch1r<2>_MC.Q )
  );
  X_INV \U1/U4/Latch1r<2>_MC.REG_tsimcreated_inv_Mclk_II/FCLK_1536  (
    .I(\Mclk_II/FCLK ),
    .O(\U1/U4/Latch1r<2>_MC.REG_tsimcreated_inv_Mclk_II/FCLK )
  );
  X_XOR2 \U1/U4/Latch1r<2>_MC.D_1537  (
    .I0(\U1/U4/Latch1r<2>_MC.D1 ),
    .I1(\U1/U4/Latch1r<2>_MC.D2 ),
    .O(\U1/U4/Latch1r<2>_MC.D )
  );
  X_ZERO \U1/U4/Latch1r<2>_MC.D1_1538  (
    .O(\U1/U4/Latch1r<2>_MC.D1 )
  );
  X_AND3 \U1/U4/Latch1r<2>_MC.D2_PT_0_1539  (
    .I0(\MSPReset_II/UIM ),
    .I1(\U1/Channel1 [2]),
    .I2(N_PZ_962),
    .O(\U1/U4/Latch1r<2>_MC.D2_PT_0 )
  );
  X_AND3 \U1/U4/Latch1r<2>_MC.D2_PT_1_1540  (
    .I0(\MSPReset_II/UIM ),
    .I1(\NlwInverterSignal_U1/U4/Latch1r<2>_MC.D2_PT_1/IN1 ),
    .I2(\U1/U4/Latch1r [2]),
    .O(\U1/U4/Latch1r<2>_MC.D2_PT_1 )
  );
  X_OR2 \U1/U4/Latch1r<2>_MC.D2_1541  (
    .I0(\U1/U4/Latch1r<2>_MC.D2_PT_0 ),
    .I1(\U1/U4/Latch1r<2>_MC.D2_PT_1 ),
    .O(\U1/U4/Latch1r<2>_MC.D2 )
  );
  X_BUF \U1/U4/Latch1r<10>  (
    .I(\U1/U4/Latch1r<10>_MC.Q ),
    .O(\U1/U4/Latch1r [10])
  );
  X_FF \U1/U4/Latch1r<10>_MC.REG  (
    .I(\U1/U4/Latch1r<10>_MC.D ),
    .CE(Vcc),
    .CLK(\U1/U4/Latch1r<10>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\U1/U4/Latch1r<10>_MC.Q )
  );
  X_INV \U1/U4/Latch1r<10>_MC.REG_tsimcreated_inv_Mclk_II/FCLK_1542  (
    .I(\Mclk_II/FCLK ),
    .O(\U1/U4/Latch1r<10>_MC.REG_tsimcreated_inv_Mclk_II/FCLK )
  );
  X_XOR2 \U1/U4/Latch1r<10>_MC.D_1543  (
    .I0(\U1/U4/Latch1r<10>_MC.D1 ),
    .I1(\U1/U4/Latch1r<10>_MC.D2 ),
    .O(\U1/U4/Latch1r<10>_MC.D )
  );
  X_ZERO \U1/U4/Latch1r<10>_MC.D1_1544  (
    .O(\U1/U4/Latch1r<10>_MC.D1 )
  );
  X_AND3 \U1/U4/Latch1r<10>_MC.D2_PT_0_1545  (
    .I0(\MSPReset_II/UIM ),
    .I1(\U1/Channel1 [10]),
    .I2(N_PZ_962),
    .O(\U1/U4/Latch1r<10>_MC.D2_PT_0 )
  );
  X_AND3 \U1/U4/Latch1r<10>_MC.D2_PT_1_1546  (
    .I0(\MSPReset_II/UIM ),
    .I1(\NlwInverterSignal_U1/U4/Latch1r<10>_MC.D2_PT_1/IN1 ),
    .I2(\U1/U4/Latch1r [10]),
    .O(\U1/U4/Latch1r<10>_MC.D2_PT_1 )
  );
  X_OR2 \U1/U4/Latch1r<10>_MC.D2_1547  (
    .I0(\U1/U4/Latch1r<10>_MC.D2_PT_0 ),
    .I1(\U1/U4/Latch1r<10>_MC.D2_PT_1 ),
    .O(\U1/U4/Latch1r<10>_MC.D2 )
  );
  X_BUF \outDATA<3>\$WA0.UIM_1548  (
    .I(\outDATA<3>\$WA0.UIM_MC.Q ),
    .O(\outDATA<3>\$WA0.UIM )
  );
  X_BUF \outDATA<3>\$WA0.UIM_MC.Q_1549  (
    .I(\outDATA<3>\$WA0.UIM_MC.D ),
    .O(\outDATA<3>\$WA0.UIM_MC.Q )
  );
  X_XOR2 \outDATA<3>\$WA0.UIM_MC.D_1550  (
    .I0(\outDATA<3>\$WA0.UIM_MC.D1 ),
    .I1(\outDATA<3>\$WA0.UIM_MC.D2 ),
    .O(\outDATA<3>\$WA0.UIM_MC.D )
  );
  X_AND2 \outDATA<3>\$WA0.UIM_MC.D1_1551  (
    .I0(U11_U3_counterr[3]),
    .I1(U11_U3_counterr[3]),
    .O(\outDATA<3>\$WA0.UIM_MC.D1 )
  );
  X_ZERO \outDATA<3>\$WA0.UIM_MC.D2_1552  (
    .O(\outDATA<3>\$WA0.UIM_MC.D2 )
  );
  X_BUF \outDATA<3>\$WA1.UIM_1553  (
    .I(\outDATA<3>\$WA1.UIM_MC.Q ),
    .O(\outDATA<3>\$WA1.UIM )
  );
  X_BUF \outDATA<3>\$WA1.UIM_MC.Q_1554  (
    .I(\outDATA<3>\$WA1.UIM_MC.D ),
    .O(\outDATA<3>\$WA1.UIM_MC.Q )
  );
  X_XOR2 \outDATA<3>\$WA1.UIM_MC.D_1555  (
    .I0(\outDATA<3>\$WA1.UIM_MC.D1 ),
    .I1(\outDATA<3>\$WA1.UIM_MC.D2 ),
    .O(\outDATA<3>\$WA1.UIM_MC.D )
  );
  X_AND2 \outDATA<3>\$WA1.UIM_MC.D1_1556  (
    .I0(\I2CS<3>_II/UIM ),
    .I1(\I2CS<3>_II/UIM ),
    .O(\outDATA<3>\$WA1.UIM_MC.D1 )
  );
  X_ZERO \outDATA<3>\$WA1.UIM_MC.D2_1557  (
    .O(\outDATA<3>\$WA1.UIM_MC.D2 )
  );
  X_BUF \outDATA<3>\$WA2.UIM_1558  (
    .I(\outDATA<3>\$WA2.UIM_MC.Q ),
    .O(\outDATA<3>\$WA2.UIM )
  );
  X_BUF \outDATA<3>\$WA2.UIM_MC.Q_1559  (
    .I(\outDATA<3>\$WA2.UIM_MC.D ),
    .O(\outDATA<3>\$WA2.UIM_MC.Q )
  );
  X_XOR2 \outDATA<3>\$WA2.UIM_MC.D_1560  (
    .I0(\outDATA<3>\$WA2.UIM_MC.D1 ),
    .I1(\outDATA<3>\$WA2.UIM_MC.D2 ),
    .O(\outDATA<3>\$WA2.UIM_MC.D )
  );
  X_AND2 \outDATA<3>\$WA2.UIM_MC.D1_1561  (
    .I0(NET3248),
    .I1(NET3248),
    .O(\outDATA<3>\$WA2.UIM_MC.D1 )
  );
  X_ZERO \outDATA<3>\$WA2.UIM_MC.D2_1562  (
    .O(\outDATA<3>\$WA2.UIM_MC.D2 )
  );
  X_BUF \outDATA<3>\$WA3.UIM_1563  (
    .I(\outDATA<3>\$WA3.UIM_MC.Q ),
    .O(\outDATA<3>\$WA3.UIM )
  );
  X_BUF \outDATA<3>\$WA3.UIM_MC.Q_1564  (
    .I(\outDATA<3>\$WA3.UIM_MC.D ),
    .O(\outDATA<3>\$WA3.UIM_MC.Q )
  );
  X_XOR2 \outDATA<3>\$WA3.UIM_MC.D_1565  (
    .I0(\outDATA<3>\$WA3.UIM_MC.D1 ),
    .I1(\outDATA<3>\$WA3.UIM_MC.D2 ),
    .O(\outDATA<3>\$WA3.UIM_MC.D )
  );
  X_ZERO \outDATA<3>\$WA3.UIM_MC.D1_1566  (
    .O(\outDATA<3>\$WA3.UIM_MC.D1 )
  );
  X_AND2 \outDATA<3>\$WA3.UIM_MC.D2_PT_0_1567  (
    .I0(NET2528),
    .I1(\U4/Flgreg [3]),
    .O(\outDATA<3>\$WA3.UIM_MC.D2_PT_0 )
  );
  X_AND2 \outDATA<3>\$WA3.UIM_MC.D2_PT_1_1568  (
    .I0(\NlwInverterSignal_outDATA<3>\$WA3.UIM_MC.D2_PT_1/IN0 ),
    .I1(\Enc05FLG_II/UIM ),
    .O(\outDATA<3>\$WA3.UIM_MC.D2_PT_1 )
  );
  X_OR2 \outDATA<3>\$WA3.UIM_MC.D2_1569  (
    .I0(\outDATA<3>\$WA3.UIM_MC.D2_PT_0 ),
    .I1(\outDATA<3>\$WA3.UIM_MC.D2_PT_1 ),
    .O(\outDATA<3>\$WA3.UIM_MC.D2 )
  );
  X_BUF \outDATA<3>\$WA5.UIM_1570  (
    .I(\outDATA<3>\$WA5.UIM_MC.Q ),
    .O(\outDATA<3>\$WA5.UIM )
  );
  X_BUF \outDATA<3>\$WA5.UIM_MC.Q_1571  (
    .I(\outDATA<3>\$WA5.UIM_MC.D ),
    .O(\outDATA<3>\$WA5.UIM_MC.Q )
  );
  X_XOR2 \outDATA<3>\$WA5.UIM_MC.D_1572  (
    .I0(\outDATA<3>\$WA5.UIM_MC.D1 ),
    .I1(\outDATA<3>\$WA5.UIM_MC.D2 ),
    .O(\outDATA<3>\$WA5.UIM_MC.D )
  );
  X_ZERO \outDATA<3>\$WA5.UIM_MC.D1_1573  (
    .O(\outDATA<3>\$WA5.UIM_MC.D1 )
  );
  X_AND2 \outDATA<3>\$WA5.UIM_MC.D2_PT_0_1574  (
    .I0(DCOR0CNTLOWr),
    .I1(\U1/U3/holdingreg0 [3]),
    .O(\outDATA<3>\$WA5.UIM_MC.D2_PT_0 )
  );
  X_AND3 \outDATA<3>\$WA5.UIM_MC.D2_PT_1_1575  (
    .I0(\NlwInverterSignal_outDATA<3>\$WA5.UIM_MC.D2_PT_1/IN0 ),
    .I1(DCOR1CNTLOWr),
    .I2(\U1/U3/holdingreg1 [3]),
    .O(\outDATA<3>\$WA5.UIM_MC.D2_PT_1 )
  );
  X_AND4 \outDATA<3>\$WA5.UIM_MC.D2_PT_2_1576  (
    .I0(\NlwInverterSignal_outDATA<3>\$WA5.UIM_MC.D2_PT_2/IN0 ),
    .I1(\NlwInverterSignal_outDATA<3>\$WA5.UIM_MC.D2_PT_2/IN1 ),
    .I2(DCOR0CNTHIGHr),
    .I3(\U1/U3/holdingreg0 [11]),
    .O(\outDATA<3>\$WA5.UIM_MC.D2_PT_2 )
  );
  X_AND4 \outDATA<3>\$WA5.UIM_MC.D2_PT_3_1577  (
    .I0(\NlwInverterSignal_outDATA<3>\$WA5.UIM_MC.D2_PT_3/IN0 ),
    .I1(\NlwInverterSignal_outDATA<3>\$WA5.UIM_MC.D2_PT_3/IN1 ),
    .I2(\NlwInverterSignal_outDATA<3>\$WA5.UIM_MC.D2_PT_3/IN2 ),
    .I3(\U1/U3/holdingreg1 [11]),
    .O(\outDATA<3>\$WA5.UIM_MC.D2_PT_3 )
  );
  X_OR4 \outDATA<3>\$WA5.UIM_MC.D2_1578  (
    .I0(\outDATA<3>\$WA5.UIM_MC.D2_PT_0 ),
    .I1(\outDATA<3>\$WA5.UIM_MC.D2_PT_1 ),
    .I2(\outDATA<3>\$WA5.UIM_MC.D2_PT_2 ),
    .I3(\outDATA<3>\$WA5.UIM_MC.D2_PT_3 ),
    .O(\outDATA<3>\$WA5.UIM_MC.D2 )
  );
  X_BUF \U1/U3/holdingreg0<3>  (
    .I(\U1/U3/holdingreg0<3>_MC.Q ),
    .O(\U1/U3/holdingreg0 [3])
  );
  X_FF \U1/U3/holdingreg0<3>_MC.REG  (
    .I(\U1/U3/holdingreg0<3>_MC.D ),
    .CE(Vcc),
    .CLK(\U1/U3/holdingreg0<3>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\U1/U3/holdingreg0<3>_MC.Q )
  );
  X_INV \U1/U3/holdingreg0<3>_MC.REG_tsimcreated_inv_Mclk_II/FCLK_1579  (
    .I(\Mclk_II/FCLK ),
    .O(\U1/U3/holdingreg0<3>_MC.REG_tsimcreated_inv_Mclk_II/FCLK )
  );
  X_XOR2 \U1/U3/holdingreg0<3>_MC.D_1580  (
    .I0(\U1/U3/holdingreg0<3>_MC.D1 ),
    .I1(\U1/U3/holdingreg0<3>_MC.D2 ),
    .O(\U1/U3/holdingreg0<3>_MC.D )
  );
  X_ZERO \U1/U3/holdingreg0<3>_MC.D1_1581  (
    .O(\U1/U3/holdingreg0<3>_MC.D1 )
  );
  X_AND2 \U1/U3/holdingreg0<3>_MC.D2_PT_0_1582  (
    .I0(N_PZ_938),
    .I1(\U1/U3/holdingreg0 [3]),
    .O(\U1/U3/holdingreg0<3>_MC.D2_PT_0 )
  );
  X_AND4 \U1/U3/holdingreg0<3>_MC.D2_PT_1_1583  (
    .I0(\MSPReset_II/UIM ),
    .I1(\NlwInverterSignal_U1/U3/holdingreg0<3>_MC.D2_PT_1/IN1 ),
    .I2(U2_ASedge),
    .I3(\U1/Channel0 [3]),
    .O(\U1/U3/holdingreg0<3>_MC.D2_PT_1 )
  );
  X_OR2 \U1/U3/holdingreg0<3>_MC.D2_1584  (
    .I0(\U1/U3/holdingreg0<3>_MC.D2_PT_0 ),
    .I1(\U1/U3/holdingreg0<3>_MC.D2_PT_1 ),
    .O(\U1/U3/holdingreg0<3>_MC.D2 )
  );
  X_BUF \U1/U3/holdingreg1<3>  (
    .I(\U1/U3/holdingreg1<3>_MC.Q ),
    .O(\U1/U3/holdingreg1 [3])
  );
  X_FF \U1/U3/holdingreg1<3>_MC.REG  (
    .I(\U1/U3/holdingreg1<3>_MC.D ),
    .CE(Vcc),
    .CLK(\U1/U3/holdingreg1<3>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\U1/U3/holdingreg1<3>_MC.Q )
  );
  X_INV \U1/U3/holdingreg1<3>_MC.REG_tsimcreated_inv_Mclk_II/FCLK_1585  (
    .I(\Mclk_II/FCLK ),
    .O(\U1/U3/holdingreg1<3>_MC.REG_tsimcreated_inv_Mclk_II/FCLK )
  );
  X_XOR2 \U1/U3/holdingreg1<3>_MC.D_1586  (
    .I0(\U1/U3/holdingreg1<3>_MC.D1 ),
    .I1(\U1/U3/holdingreg1<3>_MC.D2 ),
    .O(\U1/U3/holdingreg1<3>_MC.D )
  );
  X_ZERO \U1/U3/holdingreg1<3>_MC.D1_1587  (
    .O(\U1/U3/holdingreg1<3>_MC.D1 )
  );
  X_AND2 \U1/U3/holdingreg1<3>_MC.D2_PT_0_1588  (
    .I0(N_PZ_938),
    .I1(\U1/U3/holdingreg1 [3]),
    .O(\U1/U3/holdingreg1<3>_MC.D2_PT_0 )
  );
  X_AND4 \U1/U3/holdingreg1<3>_MC.D2_PT_1_1589  (
    .I0(\MSPReset_II/UIM ),
    .I1(\NlwInverterSignal_U1/U3/holdingreg1<3>_MC.D2_PT_1/IN1 ),
    .I2(U2_ASedge),
    .I3(\U1/Channel1 [3]),
    .O(\U1/U3/holdingreg1<3>_MC.D2_PT_1 )
  );
  X_OR2 \U1/U3/holdingreg1<3>_MC.D2_1590  (
    .I0(\U1/U3/holdingreg1<3>_MC.D2_PT_0 ),
    .I1(\U1/U3/holdingreg1<3>_MC.D2_PT_1 ),
    .O(\U1/U3/holdingreg1<3>_MC.D2 )
  );
  X_BUF \U1/U3/holdingreg0<11>  (
    .I(\U1/U3/holdingreg0<11>_MC.Q ),
    .O(\U1/U3/holdingreg0 [11])
  );
  X_FF \U1/U3/holdingreg0<11>_MC.REG  (
    .I(\U1/U3/holdingreg0<11>_MC.D ),
    .CE(Vcc),
    .CLK(\U1/U3/holdingreg0<11>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\U1/U3/holdingreg0<11>_MC.Q )
  );
  X_INV \U1/U3/holdingreg0<11>_MC.REG_tsimcreated_inv_Mclk_II/FCLK_1591  (
    .I(\Mclk_II/FCLK ),
    .O(\U1/U3/holdingreg0<11>_MC.REG_tsimcreated_inv_Mclk_II/FCLK )
  );
  X_XOR2 \U1/U3/holdingreg0<11>_MC.D_1592  (
    .I0(\U1/U3/holdingreg0<11>_MC.D1 ),
    .I1(\U1/U3/holdingreg0<11>_MC.D2 ),
    .O(\U1/U3/holdingreg0<11>_MC.D )
  );
  X_ZERO \U1/U3/holdingreg0<11>_MC.D1_1593  (
    .O(\U1/U3/holdingreg0<11>_MC.D1 )
  );
  X_AND2 \U1/U3/holdingreg0<11>_MC.D2_PT_0_1594  (
    .I0(N_PZ_938),
    .I1(\U1/U3/holdingreg0 [11]),
    .O(\U1/U3/holdingreg0<11>_MC.D2_PT_0 )
  );
  X_AND4 \U1/U3/holdingreg0<11>_MC.D2_PT_1_1595  (
    .I0(\MSPReset_II/UIM ),
    .I1(\NlwInverterSignal_U1/U3/holdingreg0<11>_MC.D2_PT_1/IN1 ),
    .I2(U2_ASedge),
    .I3(\U1/Channel0 [11]),
    .O(\U1/U3/holdingreg0<11>_MC.D2_PT_1 )
  );
  X_OR2 \U1/U3/holdingreg0<11>_MC.D2_1596  (
    .I0(\U1/U3/holdingreg0<11>_MC.D2_PT_0 ),
    .I1(\U1/U3/holdingreg0<11>_MC.D2_PT_1 ),
    .O(\U1/U3/holdingreg0<11>_MC.D2 )
  );
  X_BUF \U1/U3/holdingreg1<11>  (
    .I(\U1/U3/holdingreg1<11>_MC.Q ),
    .O(\U1/U3/holdingreg1 [11])
  );
  X_FF \U1/U3/holdingreg1<11>_MC.REG  (
    .I(\U1/U3/holdingreg1<11>_MC.D ),
    .CE(Vcc),
    .CLK(\U1/U3/holdingreg1<11>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\U1/U3/holdingreg1<11>_MC.Q )
  );
  X_INV \U1/U3/holdingreg1<11>_MC.REG_tsimcreated_inv_Mclk_II/FCLK_1597  (
    .I(\Mclk_II/FCLK ),
    .O(\U1/U3/holdingreg1<11>_MC.REG_tsimcreated_inv_Mclk_II/FCLK )
  );
  X_XOR2 \U1/U3/holdingreg1<11>_MC.D_1598  (
    .I0(\U1/U3/holdingreg1<11>_MC.D1 ),
    .I1(\U1/U3/holdingreg1<11>_MC.D2 ),
    .O(\U1/U3/holdingreg1<11>_MC.D )
  );
  X_ZERO \U1/U3/holdingreg1<11>_MC.D1_1599  (
    .O(\U1/U3/holdingreg1<11>_MC.D1 )
  );
  X_AND2 \U1/U3/holdingreg1<11>_MC.D2_PT_0_1600  (
    .I0(N_PZ_938),
    .I1(\U1/U3/holdingreg1 [11]),
    .O(\U1/U3/holdingreg1<11>_MC.D2_PT_0 )
  );
  X_AND4 \U1/U3/holdingreg1<11>_MC.D2_PT_1_1601  (
    .I0(\MSPReset_II/UIM ),
    .I1(\NlwInverterSignal_U1/U3/holdingreg1<11>_MC.D2_PT_1/IN1 ),
    .I2(U2_ASedge),
    .I3(\U1/Channel1 [11]),
    .O(\U1/U3/holdingreg1<11>_MC.D2_PT_1 )
  );
  X_OR2 \U1/U3/holdingreg1<11>_MC.D2_1602  (
    .I0(\U1/U3/holdingreg1<11>_MC.D2_PT_0 ),
    .I1(\U1/U3/holdingreg1<11>_MC.D2_PT_1 ),
    .O(\U1/U3/holdingreg1<11>_MC.D2 )
  );
  X_BUF \outDATA<3>\$WA6.UIM_1603  (
    .I(\outDATA<3>\$WA6.UIM_MC.Q ),
    .O(\outDATA<3>\$WA6.UIM )
  );
  X_BUF \outDATA<3>\$WA6.UIM_MC.Q_1604  (
    .I(\outDATA<3>\$WA6.UIM_MC.D ),
    .O(\outDATA<3>\$WA6.UIM_MC.Q )
  );
  X_XOR2 \outDATA<3>\$WA6.UIM_MC.D_1605  (
    .I0(\outDATA<3>\$WA6.UIM_MC.D1 ),
    .I1(\outDATA<3>\$WA6.UIM_MC.D2 ),
    .O(\outDATA<3>\$WA6.UIM_MC.D )
  );
  X_ZERO \outDATA<3>\$WA6.UIM_MC.D1_1606  (
    .O(\outDATA<3>\$WA6.UIM_MC.D1 )
  );
  X_AND2 \outDATA<3>\$WA6.UIM_MC.D2_PT_0_1607  (
    .I0(DCOR0THRESLOWr),
    .I1(\U1/U4/Latch0r [3]),
    .O(\outDATA<3>\$WA6.UIM_MC.D2_PT_0 )
  );
  X_AND3 \outDATA<3>\$WA6.UIM_MC.D2_PT_1_1608  (
    .I0(NET2493),
    .I1(\NlwInverterSignal_outDATA<3>\$WA6.UIM_MC.D2_PT_1/IN1 ),
    .I2(DCORIFGr),
    .O(\outDATA<3>\$WA6.UIM_MC.D2_PT_1 )
  );
  X_AND4 \outDATA<3>\$WA6.UIM_MC.D2_PT_2_1609  (
    .I0(\NlwInverterSignal_outDATA<3>\$WA6.UIM_MC.D2_PT_2/IN0 ),
    .I1(\NlwInverterSignal_outDATA<3>\$WA6.UIM_MC.D2_PT_2/IN1 ),
    .I2(DCOR0THRESHIGHr),
    .I3(\U1/U4/Latch0r [11]),
    .O(\outDATA<3>\$WA6.UIM_MC.D2_PT_2 )
  );
  X_AND5 \outDATA<3>\$WA6.UIM_MC.D2_PT_3_1610  (
    .I0(\NlwInverterSignal_outDATA<3>\$WA6.UIM_MC.D2_PT_3/IN0 ),
    .I1(\NlwInverterSignal_outDATA<3>\$WA6.UIM_MC.D2_PT_3/IN1 ),
    .I2(\NlwInverterSignal_outDATA<3>\$WA6.UIM_MC.D2_PT_3/IN2 ),
    .I3(DCOR1THRESLOWr),
    .I4(\U1/U4/Latch1r [3]),
    .O(\outDATA<3>\$WA6.UIM_MC.D2_PT_3 )
  );
  X_AND5 \outDATA<3>\$WA6.UIM_MC.D2_PT_4_1611  (
    .I0(\NlwInverterSignal_outDATA<3>\$WA6.UIM_MC.D2_PT_4/IN0 ),
    .I1(\NlwInverterSignal_outDATA<3>\$WA6.UIM_MC.D2_PT_4/IN1 ),
    .I2(\NlwInverterSignal_outDATA<3>\$WA6.UIM_MC.D2_PT_4/IN2 ),
    .I3(\NlwInverterSignal_outDATA<3>\$WA6.UIM_MC.D2_PT_4/IN3 ),
    .I4(\U1/U4/Latch1r [11]),
    .O(\outDATA<3>\$WA6.UIM_MC.D2_PT_4 )
  );
  X_OR5 \outDATA<3>\$WA6.UIM_MC.D2_1612  (
    .I0(\outDATA<3>\$WA6.UIM_MC.D2_PT_0 ),
    .I1(\outDATA<3>\$WA6.UIM_MC.D2_PT_1 ),
    .I2(\outDATA<3>\$WA6.UIM_MC.D2_PT_2 ),
    .I3(\outDATA<3>\$WA6.UIM_MC.D2_PT_3 ),
    .I4(\outDATA<3>\$WA6.UIM_MC.D2_PT_4 ),
    .O(\outDATA<3>\$WA6.UIM_MC.D2 )
  );
  X_BUF \U1/U4/Latch0r<3>  (
    .I(\U1/U4/Latch0r<3>_MC.Q ),
    .O(\U1/U4/Latch0r [3])
  );
  X_FF \U1/U4/Latch0r<3>_MC.REG  (
    .I(\U1/U4/Latch0r<3>_MC.D ),
    .CE(Vcc),
    .CLK(\U1/U4/Latch0r<3>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\U1/U4/Latch0r<3>_MC.Q )
  );
  X_INV \U1/U4/Latch0r<3>_MC.REG_tsimcreated_inv_Mclk_II/FCLK_1613  (
    .I(\Mclk_II/FCLK ),
    .O(\U1/U4/Latch0r<3>_MC.REG_tsimcreated_inv_Mclk_II/FCLK )
  );
  X_XOR2 \U1/U4/Latch0r<3>_MC.D_1614  (
    .I0(\U1/U4/Latch0r<3>_MC.D1 ),
    .I1(\U1/U4/Latch0r<3>_MC.D2 ),
    .O(\U1/U4/Latch0r<3>_MC.D )
  );
  X_ZERO \U1/U4/Latch0r<3>_MC.D1_1615  (
    .O(\U1/U4/Latch0r<3>_MC.D1 )
  );
  X_AND3 \U1/U4/Latch0r<3>_MC.D2_PT_0_1616  (
    .I0(\MSPReset_II/UIM ),
    .I1(\U1/Channel0 [3]),
    .I2(N_PZ_963),
    .O(\U1/U4/Latch0r<3>_MC.D2_PT_0 )
  );
  X_AND3 \U1/U4/Latch0r<3>_MC.D2_PT_1_1617  (
    .I0(\MSPReset_II/UIM ),
    .I1(\NlwInverterSignal_U1/U4/Latch0r<3>_MC.D2_PT_1/IN1 ),
    .I2(\U1/U4/Latch0r [3]),
    .O(\U1/U4/Latch0r<3>_MC.D2_PT_1 )
  );
  X_OR2 \U1/U4/Latch0r<3>_MC.D2_1618  (
    .I0(\U1/U4/Latch0r<3>_MC.D2_PT_0 ),
    .I1(\U1/U4/Latch0r<3>_MC.D2_PT_1 ),
    .O(\U1/U4/Latch0r<3>_MC.D2 )
  );
  X_BUF \U1/U4/Latch0r<11>  (
    .I(\U1/U4/Latch0r<11>_MC.Q ),
    .O(\U1/U4/Latch0r [11])
  );
  X_FF \U1/U4/Latch0r<11>_MC.REG  (
    .I(\U1/U4/Latch0r<11>_MC.D ),
    .CE(Vcc),
    .CLK(\U1/U4/Latch0r<11>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\U1/U4/Latch0r<11>_MC.Q )
  );
  X_INV \U1/U4/Latch0r<11>_MC.REG_tsimcreated_inv_Mclk_II/FCLK_1619  (
    .I(\Mclk_II/FCLK ),
    .O(\U1/U4/Latch0r<11>_MC.REG_tsimcreated_inv_Mclk_II/FCLK )
  );
  X_XOR2 \U1/U4/Latch0r<11>_MC.D_1620  (
    .I0(\U1/U4/Latch0r<11>_MC.D1 ),
    .I1(\U1/U4/Latch0r<11>_MC.D2 ),
    .O(\U1/U4/Latch0r<11>_MC.D )
  );
  X_ZERO \U1/U4/Latch0r<11>_MC.D1_1621  (
    .O(\U1/U4/Latch0r<11>_MC.D1 )
  );
  X_AND3 \U1/U4/Latch0r<11>_MC.D2_PT_0_1622  (
    .I0(\MSPReset_II/UIM ),
    .I1(\U1/Channel0 [11]),
    .I2(N_PZ_963),
    .O(\U1/U4/Latch0r<11>_MC.D2_PT_0 )
  );
  X_AND3 \U1/U4/Latch0r<11>_MC.D2_PT_1_1623  (
    .I0(\MSPReset_II/UIM ),
    .I1(\NlwInverterSignal_U1/U4/Latch0r<11>_MC.D2_PT_1/IN1 ),
    .I2(\U1/U4/Latch0r [11]),
    .O(\U1/U4/Latch0r<11>_MC.D2_PT_1 )
  );
  X_OR2 \U1/U4/Latch0r<11>_MC.D2_1624  (
    .I0(\U1/U4/Latch0r<11>_MC.D2_PT_0 ),
    .I1(\U1/U4/Latch0r<11>_MC.D2_PT_1 ),
    .O(\U1/U4/Latch0r<11>_MC.D2 )
  );
  X_BUF \U1/U4/Latch1r<3>  (
    .I(\U1/U4/Latch1r<3>_MC.Q ),
    .O(\U1/U4/Latch1r [3])
  );
  X_FF \U1/U4/Latch1r<3>_MC.REG  (
    .I(\U1/U4/Latch1r<3>_MC.D ),
    .CE(Vcc),
    .CLK(\U1/U4/Latch1r<3>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\U1/U4/Latch1r<3>_MC.Q )
  );
  X_INV \U1/U4/Latch1r<3>_MC.REG_tsimcreated_inv_Mclk_II/FCLK_1625  (
    .I(\Mclk_II/FCLK ),
    .O(\U1/U4/Latch1r<3>_MC.REG_tsimcreated_inv_Mclk_II/FCLK )
  );
  X_XOR2 \U1/U4/Latch1r<3>_MC.D_1626  (
    .I0(\U1/U4/Latch1r<3>_MC.D1 ),
    .I1(\U1/U4/Latch1r<3>_MC.D2 ),
    .O(\U1/U4/Latch1r<3>_MC.D )
  );
  X_ZERO \U1/U4/Latch1r<3>_MC.D1_1627  (
    .O(\U1/U4/Latch1r<3>_MC.D1 )
  );
  X_AND3 \U1/U4/Latch1r<3>_MC.D2_PT_0_1628  (
    .I0(\MSPReset_II/UIM ),
    .I1(\U1/Channel1 [3]),
    .I2(N_PZ_962),
    .O(\U1/U4/Latch1r<3>_MC.D2_PT_0 )
  );
  X_AND3 \U1/U4/Latch1r<3>_MC.D2_PT_1_1629  (
    .I0(\MSPReset_II/UIM ),
    .I1(\NlwInverterSignal_U1/U4/Latch1r<3>_MC.D2_PT_1/IN1 ),
    .I2(\U1/U4/Latch1r [3]),
    .O(\U1/U4/Latch1r<3>_MC.D2_PT_1 )
  );
  X_OR2 \U1/U4/Latch1r<3>_MC.D2_1630  (
    .I0(\U1/U4/Latch1r<3>_MC.D2_PT_0 ),
    .I1(\U1/U4/Latch1r<3>_MC.D2_PT_1 ),
    .O(\U1/U4/Latch1r<3>_MC.D2 )
  );
  X_BUF \U1/U4/Latch1r<11>  (
    .I(\U1/U4/Latch1r<11>_MC.Q ),
    .O(\U1/U4/Latch1r [11])
  );
  X_FF \U1/U4/Latch1r<11>_MC.REG  (
    .I(\U1/U4/Latch1r<11>_MC.D ),
    .CE(Vcc),
    .CLK(\U1/U4/Latch1r<11>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\U1/U4/Latch1r<11>_MC.Q )
  );
  X_INV \U1/U4/Latch1r<11>_MC.REG_tsimcreated_inv_Mclk_II/FCLK_1631  (
    .I(\Mclk_II/FCLK ),
    .O(\U1/U4/Latch1r<11>_MC.REG_tsimcreated_inv_Mclk_II/FCLK )
  );
  X_XOR2 \U1/U4/Latch1r<11>_MC.D_1632  (
    .I0(\U1/U4/Latch1r<11>_MC.D1 ),
    .I1(\U1/U4/Latch1r<11>_MC.D2 ),
    .O(\U1/U4/Latch1r<11>_MC.D )
  );
  X_ZERO \U1/U4/Latch1r<11>_MC.D1_1633  (
    .O(\U1/U4/Latch1r<11>_MC.D1 )
  );
  X_AND3 \U1/U4/Latch1r<11>_MC.D2_PT_0_1634  (
    .I0(\MSPReset_II/UIM ),
    .I1(\U1/Channel1 [11]),
    .I2(N_PZ_962),
    .O(\U1/U4/Latch1r<11>_MC.D2_PT_0 )
  );
  X_AND3 \U1/U4/Latch1r<11>_MC.D2_PT_1_1635  (
    .I0(\MSPReset_II/UIM ),
    .I1(\NlwInverterSignal_U1/U4/Latch1r<11>_MC.D2_PT_1/IN1 ),
    .I2(\U1/U4/Latch1r [11]),
    .O(\U1/U4/Latch1r<11>_MC.D2_PT_1 )
  );
  X_OR2 \U1/U4/Latch1r<11>_MC.D2_1636  (
    .I0(\U1/U4/Latch1r<11>_MC.D2_PT_0 ),
    .I1(\U1/U4/Latch1r<11>_MC.D2_PT_1 ),
    .O(\U1/U4/Latch1r<11>_MC.D2 )
  );
  X_BUF \outDATA<6>\$WA0.UIM_1637  (
    .I(\outDATA<6>\$WA0.UIM_MC.Q ),
    .O(\outDATA<6>\$WA0.UIM )
  );
  X_BUF \outDATA<6>\$WA0.UIM_MC.Q_1638  (
    .I(\outDATA<6>\$WA0.UIM_MC.D ),
    .O(\outDATA<6>\$WA0.UIM_MC.Q )
  );
  X_XOR2 \outDATA<6>\$WA0.UIM_MC.D_1639  (
    .I0(\outDATA<6>\$WA0.UIM_MC.D1 ),
    .I1(\outDATA<6>\$WA0.UIM_MC.D2 ),
    .O(\outDATA<6>\$WA0.UIM_MC.D )
  );
  X_ZERO \outDATA<6>\$WA0.UIM_MC.D1_1640  (
    .O(\outDATA<6>\$WA0.UIM_MC.D1 )
  );
  X_ZERO \outDATA<6>\$WA0.UIM_MC.D2_1641  (
    .O(\outDATA<6>\$WA0.UIM_MC.D2 )
  );
  X_BUF \outDATA<6>\$WA2.UIM_1642  (
    .I(\outDATA<6>\$WA2.UIM_MC.Q ),
    .O(\outDATA<6>\$WA2.UIM )
  );
  X_BUF \outDATA<6>\$WA2.UIM_MC.Q_1643  (
    .I(\outDATA<6>\$WA2.UIM_MC.D ),
    .O(\outDATA<6>\$WA2.UIM_MC.Q )
  );
  X_XOR2 \outDATA<6>\$WA2.UIM_MC.D_1644  (
    .I0(\outDATA<6>\$WA2.UIM_MC.D1 ),
    .I1(\outDATA<6>\$WA2.UIM_MC.D2 ),
    .O(\outDATA<6>\$WA2.UIM_MC.D )
  );
  X_AND2 \outDATA<6>\$WA2.UIM_MC.D1_1645  (
    .I0(\Home1_II/UIM ),
    .I1(\Home1_II/UIM ),
    .O(\outDATA<6>\$WA2.UIM_MC.D1 )
  );
  X_ZERO \outDATA<6>\$WA2.UIM_MC.D2_1646  (
    .O(\outDATA<6>\$WA2.UIM_MC.D2 )
  );
  X_BUF \outDATA<6>\$WA3.UIM_1647  (
    .I(\outDATA<6>\$WA3.UIM_MC.Q ),
    .O(\outDATA<6>\$WA3.UIM )
  );
  X_BUF \outDATA<6>\$WA3.UIM_MC.Q_1648  (
    .I(\outDATA<6>\$WA3.UIM_MC.D ),
    .O(\outDATA<6>\$WA3.UIM_MC.Q )
  );
  X_XOR2 \outDATA<6>\$WA3.UIM_MC.D_1649  (
    .I0(\outDATA<6>\$WA3.UIM_MC.D1 ),
    .I1(\outDATA<6>\$WA3.UIM_MC.D2 ),
    .O(\outDATA<6>\$WA3.UIM_MC.D )
  );
  X_ZERO \outDATA<6>\$WA3.UIM_MC.D1_1650  (
    .O(\outDATA<6>\$WA3.UIM_MC.D1 )
  );
  X_AND2 \outDATA<6>\$WA3.UIM_MC.D2_PT_0_1651  (
    .I0(NET2528),
    .I1(\U4/Flgreg [6]),
    .O(\outDATA<6>\$WA3.UIM_MC.D2_PT_0 )
  );
  X_AND2 \outDATA<6>\$WA3.UIM_MC.D2_PT_1_1652  (
    .I0(\NlwInverterSignal_outDATA<6>\$WA3.UIM_MC.D2_PT_1/IN0 ),
    .I1(\Enc133FLG_II/UIM ),
    .O(\outDATA<6>\$WA3.UIM_MC.D2_PT_1 )
  );
  X_OR2 \outDATA<6>\$WA3.UIM_MC.D2_1653  (
    .I0(\outDATA<6>\$WA3.UIM_MC.D2_PT_0 ),
    .I1(\outDATA<6>\$WA3.UIM_MC.D2_PT_1 ),
    .O(\outDATA<6>\$WA3.UIM_MC.D2 )
  );
  X_BUF \outDATA<6>\$WA5.UIM_1654  (
    .I(\outDATA<6>\$WA5.UIM_MC.Q ),
    .O(\outDATA<6>\$WA5.UIM )
  );
  X_BUF \outDATA<6>\$WA5.UIM_MC.Q_1655  (
    .I(\outDATA<6>\$WA5.UIM_MC.D ),
    .O(\outDATA<6>\$WA5.UIM_MC.Q )
  );
  X_XOR2 \outDATA<6>\$WA5.UIM_MC.D_1656  (
    .I0(\outDATA<6>\$WA5.UIM_MC.D1 ),
    .I1(\outDATA<6>\$WA5.UIM_MC.D2 ),
    .O(\outDATA<6>\$WA5.UIM_MC.D )
  );
  X_ZERO \outDATA<6>\$WA5.UIM_MC.D1_1657  (
    .O(\outDATA<6>\$WA5.UIM_MC.D1 )
  );
  X_AND2 \outDATA<6>\$WA5.UIM_MC.D2_PT_0_1658  (
    .I0(DCOR0CNTLOWr),
    .I1(\U1/U3/holdingreg0 [6]),
    .O(\outDATA<6>\$WA5.UIM_MC.D2_PT_0 )
  );
  X_AND3 \outDATA<6>\$WA5.UIM_MC.D2_PT_1_1659  (
    .I0(\NlwInverterSignal_outDATA<6>\$WA5.UIM_MC.D2_PT_1/IN0 ),
    .I1(DCOR1CNTLOWr),
    .I2(\U1/U3/holdingreg1 [6]),
    .O(\outDATA<6>\$WA5.UIM_MC.D2_PT_1 )
  );
  X_AND4 \outDATA<6>\$WA5.UIM_MC.D2_PT_2_1660  (
    .I0(\NlwInverterSignal_outDATA<6>\$WA5.UIM_MC.D2_PT_2/IN0 ),
    .I1(\NlwInverterSignal_outDATA<6>\$WA5.UIM_MC.D2_PT_2/IN1 ),
    .I2(DCOR0CNTHIGHr),
    .I3(\U1/U3/holdingreg0 [14]),
    .O(\outDATA<6>\$WA5.UIM_MC.D2_PT_2 )
  );
  X_AND4 \outDATA<6>\$WA5.UIM_MC.D2_PT_3_1661  (
    .I0(\NlwInverterSignal_outDATA<6>\$WA5.UIM_MC.D2_PT_3/IN0 ),
    .I1(\NlwInverterSignal_outDATA<6>\$WA5.UIM_MC.D2_PT_3/IN1 ),
    .I2(\NlwInverterSignal_outDATA<6>\$WA5.UIM_MC.D2_PT_3/IN2 ),
    .I3(\U1/U3/holdingreg1 [14]),
    .O(\outDATA<6>\$WA5.UIM_MC.D2_PT_3 )
  );
  X_OR4 \outDATA<6>\$WA5.UIM_MC.D2_1662  (
    .I0(\outDATA<6>\$WA5.UIM_MC.D2_PT_0 ),
    .I1(\outDATA<6>\$WA5.UIM_MC.D2_PT_1 ),
    .I2(\outDATA<6>\$WA5.UIM_MC.D2_PT_2 ),
    .I3(\outDATA<6>\$WA5.UIM_MC.D2_PT_3 ),
    .O(\outDATA<6>\$WA5.UIM_MC.D2 )
  );
  X_BUF \U1/U3/holdingreg0<6>  (
    .I(\U1/U3/holdingreg0<6>_MC.Q ),
    .O(\U1/U3/holdingreg0 [6])
  );
  X_FF \U1/U3/holdingreg0<6>_MC.REG  (
    .I(\U1/U3/holdingreg0<6>_MC.D ),
    .CE(Vcc),
    .CLK(\U1/U3/holdingreg0<6>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\U1/U3/holdingreg0<6>_MC.Q )
  );
  X_INV \U1/U3/holdingreg0<6>_MC.REG_tsimcreated_inv_Mclk_II/FCLK_1663  (
    .I(\Mclk_II/FCLK ),
    .O(\U1/U3/holdingreg0<6>_MC.REG_tsimcreated_inv_Mclk_II/FCLK )
  );
  X_XOR2 \U1/U3/holdingreg0<6>_MC.D_1664  (
    .I0(\U1/U3/holdingreg0<6>_MC.D1 ),
    .I1(\U1/U3/holdingreg0<6>_MC.D2 ),
    .O(\U1/U3/holdingreg0<6>_MC.D )
  );
  X_ZERO \U1/U3/holdingreg0<6>_MC.D1_1665  (
    .O(\U1/U3/holdingreg0<6>_MC.D1 )
  );
  X_AND2 \U1/U3/holdingreg0<6>_MC.D2_PT_0_1666  (
    .I0(N_PZ_938),
    .I1(\U1/U3/holdingreg0 [6]),
    .O(\U1/U3/holdingreg0<6>_MC.D2_PT_0 )
  );
  X_AND4 \U1/U3/holdingreg0<6>_MC.D2_PT_1_1667  (
    .I0(\MSPReset_II/UIM ),
    .I1(\NlwInverterSignal_U1/U3/holdingreg0<6>_MC.D2_PT_1/IN1 ),
    .I2(U2_ASedge),
    .I3(\U1/Channel0 [6]),
    .O(\U1/U3/holdingreg0<6>_MC.D2_PT_1 )
  );
  X_OR2 \U1/U3/holdingreg0<6>_MC.D2_1668  (
    .I0(\U1/U3/holdingreg0<6>_MC.D2_PT_0 ),
    .I1(\U1/U3/holdingreg0<6>_MC.D2_PT_1 ),
    .O(\U1/U3/holdingreg0<6>_MC.D2 )
  );
  X_BUF \U1/U3/holdingreg1<6>  (
    .I(\U1/U3/holdingreg1<6>_MC.Q ),
    .O(\U1/U3/holdingreg1 [6])
  );
  X_FF \U1/U3/holdingreg1<6>_MC.REG  (
    .I(\U1/U3/holdingreg1<6>_MC.D ),
    .CE(Vcc),
    .CLK(\U1/U3/holdingreg1<6>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\U1/U3/holdingreg1<6>_MC.Q )
  );
  X_INV \U1/U3/holdingreg1<6>_MC.REG_tsimcreated_inv_Mclk_II/FCLK_1669  (
    .I(\Mclk_II/FCLK ),
    .O(\U1/U3/holdingreg1<6>_MC.REG_tsimcreated_inv_Mclk_II/FCLK )
  );
  X_XOR2 \U1/U3/holdingreg1<6>_MC.D_1670  (
    .I0(\U1/U3/holdingreg1<6>_MC.D1 ),
    .I1(\U1/U3/holdingreg1<6>_MC.D2 ),
    .O(\U1/U3/holdingreg1<6>_MC.D )
  );
  X_ZERO \U1/U3/holdingreg1<6>_MC.D1_1671  (
    .O(\U1/U3/holdingreg1<6>_MC.D1 )
  );
  X_AND2 \U1/U3/holdingreg1<6>_MC.D2_PT_0_1672  (
    .I0(N_PZ_938),
    .I1(\U1/U3/holdingreg1 [6]),
    .O(\U1/U3/holdingreg1<6>_MC.D2_PT_0 )
  );
  X_AND4 \U1/U3/holdingreg1<6>_MC.D2_PT_1_1673  (
    .I0(\MSPReset_II/UIM ),
    .I1(\NlwInverterSignal_U1/U3/holdingreg1<6>_MC.D2_PT_1/IN1 ),
    .I2(U2_ASedge),
    .I3(\U1/Channel1 [6]),
    .O(\U1/U3/holdingreg1<6>_MC.D2_PT_1 )
  );
  X_OR2 \U1/U3/holdingreg1<6>_MC.D2_1674  (
    .I0(\U1/U3/holdingreg1<6>_MC.D2_PT_0 ),
    .I1(\U1/U3/holdingreg1<6>_MC.D2_PT_1 ),
    .O(\U1/U3/holdingreg1<6>_MC.D2 )
  );
  X_BUF \U1/U3/holdingreg0<14>  (
    .I(\U1/U3/holdingreg0<14>_MC.Q ),
    .O(\U1/U3/holdingreg0 [14])
  );
  X_FF \U1/U3/holdingreg0<14>_MC.REG  (
    .I(\U1/U3/holdingreg0<14>_MC.D ),
    .CE(Vcc),
    .CLK(\U1/U3/holdingreg0<14>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\U1/U3/holdingreg0<14>_MC.Q )
  );
  X_INV \U1/U3/holdingreg0<14>_MC.REG_tsimcreated_inv_Mclk_II/FCLK_1675  (
    .I(\Mclk_II/FCLK ),
    .O(\U1/U3/holdingreg0<14>_MC.REG_tsimcreated_inv_Mclk_II/FCLK )
  );
  X_XOR2 \U1/U3/holdingreg0<14>_MC.D_1676  (
    .I0(\U1/U3/holdingreg0<14>_MC.D1 ),
    .I1(\U1/U3/holdingreg0<14>_MC.D2 ),
    .O(\U1/U3/holdingreg0<14>_MC.D )
  );
  X_ZERO \U1/U3/holdingreg0<14>_MC.D1_1677  (
    .O(\U1/U3/holdingreg0<14>_MC.D1 )
  );
  X_AND2 \U1/U3/holdingreg0<14>_MC.D2_PT_0_1678  (
    .I0(N_PZ_938),
    .I1(\U1/U3/holdingreg0 [14]),
    .O(\U1/U3/holdingreg0<14>_MC.D2_PT_0 )
  );
  X_AND4 \U1/U3/holdingreg0<14>_MC.D2_PT_1_1679  (
    .I0(\MSPReset_II/UIM ),
    .I1(\NlwInverterSignal_U1/U3/holdingreg0<14>_MC.D2_PT_1/IN1 ),
    .I2(U2_ASedge),
    .I3(\U1/Channel0 [14]),
    .O(\U1/U3/holdingreg0<14>_MC.D2_PT_1 )
  );
  X_OR2 \U1/U3/holdingreg0<14>_MC.D2_1680  (
    .I0(\U1/U3/holdingreg0<14>_MC.D2_PT_0 ),
    .I1(\U1/U3/holdingreg0<14>_MC.D2_PT_1 ),
    .O(\U1/U3/holdingreg0<14>_MC.D2 )
  );
  X_BUF \U1/Channel0<14>  (
    .I(\U1/Channel0<14>_MC.Q ),
    .O(\U1/Channel0 [14])
  );
  X_XOR2 \U1/Channel0<14>_MC_tsimcreated_xor__1681  (
    .I0(\U1/Channel0<14>_MC.D ),
    .I1(\U1/Channel0<14>_MC.Q ),
    .O(\U1/Channel0<14>_MC_tsimcreated_xor_ )
  );
  X_FF \U1/Channel0<14>_MC.REG  (
    .I(\U1/Channel0<14>_MC_tsimcreated_xor_ ),
    .CE(Vcc),
    .CLK(\Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\U1/Channel0<14>_MC.Q )
  );
  X_XOR2 \U1/Channel0<14>_MC.D_1682  (
    .I0(\U1/Channel0<14>_MC.D1 ),
    .I1(\U1/Channel0<14>_MC.D2 ),
    .O(\U1/Channel0<14>_MC.D )
  );
  X_ZERO \U1/Channel0<14>_MC.D1_1683  (
    .O(\U1/Channel0<14>_MC.D1 )
  );
  X_AND2 \U1/Channel0<14>_MC.D2_PT_0_1684  (
    .I0(\NlwInverterSignal_U1/Channel0<14>_MC.D2_PT_0/IN0 ),
    .I1(\U1/Channel0 [14]),
    .O(\U1/Channel0<14>_MC.D2_PT_0 )
  );
  X_AND7 \U1/Channel0<14>_MC.D2_PT_1_1685  (
    .I0(N_PZ_964),
    .I1(\NlwInverterSignal_U1/Channel0<14>_MC.D2_PT_1/IN1 ),
    .I2(\NlwInverterSignal_U1/Channel0<14>_MC.D2_PT_1/IN2 ),
    .I3(\NlwInverterSignal_U1/Channel0<14>_MC.D2_PT_1/IN3 ),
    .I4(\U1/U2/location_Maddsub__n0000__n0075 [0]),
    .I5(\NlwInverterSignal_U1/Channel0<14>_MC.D2_PT_1/IN5 ),
    .I6(\NlwInverterSignal_U1/Channel0<14>_MC.D2_PT_1/IN6 ),
    .O(\U1/Channel0<14>_MC.D2_PT_1 )
  );
  X_AND7 \U1/Channel0<14>_MC.D2_PT_2_1686  (
    .I0(N_PZ_968),
    .I1(\U1/Channel0 [13]),
    .I2(\U1/Channel0 [10]),
    .I3(\U1/Channel0 [9]),
    .I4(\NlwInverterSignal_U1/Channel0<14>_MC.D2_PT_2/IN4 ),
    .I5(\U1/Channel0 [11]),
    .I6(\U1/Channel0 [12]),
    .O(\U1/Channel0<14>_MC.D2_PT_2 )
  );
  X_OR3 \U1/Channel0<14>_MC.D2_1687  (
    .I0(\U1/Channel0<14>_MC.D2_PT_0 ),
    .I1(\U1/Channel0<14>_MC.D2_PT_1 ),
    .I2(\U1/Channel0<14>_MC.D2_PT_2 ),
    .O(\U1/Channel0<14>_MC.D2 )
  );
  X_BUF \U1/U3/holdingreg1<14>  (
    .I(\U1/U3/holdingreg1<14>_MC.Q ),
    .O(\U1/U3/holdingreg1 [14])
  );
  X_FF \U1/U3/holdingreg1<14>_MC.REG  (
    .I(\U1/U3/holdingreg1<14>_MC.D ),
    .CE(Vcc),
    .CLK(\U1/U3/holdingreg1<14>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\U1/U3/holdingreg1<14>_MC.Q )
  );
  X_INV \U1/U3/holdingreg1<14>_MC.REG_tsimcreated_inv_Mclk_II/FCLK_1688  (
    .I(\Mclk_II/FCLK ),
    .O(\U1/U3/holdingreg1<14>_MC.REG_tsimcreated_inv_Mclk_II/FCLK )
  );
  X_XOR2 \U1/U3/holdingreg1<14>_MC.D_1689  (
    .I0(\U1/U3/holdingreg1<14>_MC.D1 ),
    .I1(\U1/U3/holdingreg1<14>_MC.D2 ),
    .O(\U1/U3/holdingreg1<14>_MC.D )
  );
  X_ZERO \U1/U3/holdingreg1<14>_MC.D1_1690  (
    .O(\U1/U3/holdingreg1<14>_MC.D1 )
  );
  X_AND2 \U1/U3/holdingreg1<14>_MC.D2_PT_0_1691  (
    .I0(N_PZ_938),
    .I1(\U1/U3/holdingreg1 [14]),
    .O(\U1/U3/holdingreg1<14>_MC.D2_PT_0 )
  );
  X_AND4 \U1/U3/holdingreg1<14>_MC.D2_PT_1_1692  (
    .I0(\MSPReset_II/UIM ),
    .I1(\NlwInverterSignal_U1/U3/holdingreg1<14>_MC.D2_PT_1/IN1 ),
    .I2(U2_ASedge),
    .I3(\U1/Channel1 [14]),
    .O(\U1/U3/holdingreg1<14>_MC.D2_PT_1 )
  );
  X_OR2 \U1/U3/holdingreg1<14>_MC.D2_1693  (
    .I0(\U1/U3/holdingreg1<14>_MC.D2_PT_0 ),
    .I1(\U1/U3/holdingreg1<14>_MC.D2_PT_1 ),
    .O(\U1/U3/holdingreg1<14>_MC.D2 )
  );
  X_BUF \U1/Channel1<14>  (
    .I(\U1/Channel1<14>_MC.Q ),
    .O(\U1/Channel1 [14])
  );
  X_XOR2 \U1/Channel1<14>_MC_tsimcreated_xor__1694  (
    .I0(\U1/Channel1<14>_MC.D ),
    .I1(\U1/Channel1<14>_MC.Q ),
    .O(\U1/Channel1<14>_MC_tsimcreated_xor_ )
  );
  X_FF \U1/Channel1<14>_MC.REG  (
    .I(\U1/Channel1<14>_MC_tsimcreated_xor_ ),
    .CE(Vcc),
    .CLK(\Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\U1/Channel1<14>_MC.Q )
  );
  X_XOR2 \U1/Channel1<14>_MC.D_1695  (
    .I0(\U1/Channel1<14>_MC.D1 ),
    .I1(\U1/Channel1<14>_MC.D2 ),
    .O(\U1/Channel1<14>_MC.D )
  );
  X_ZERO \U1/Channel1<14>_MC.D1_1696  (
    .O(\U1/Channel1<14>_MC.D1 )
  );
  X_AND2 \U1/Channel1<14>_MC.D2_PT_0_1697  (
    .I0(\NlwInverterSignal_U1/Channel1<14>_MC.D2_PT_0/IN0 ),
    .I1(\U1/Channel1 [14]),
    .O(\U1/Channel1<14>_MC.D2_PT_0 )
  );
  X_AND16 \U1/Channel1<14>_MC.D2_PT_1_1698  (
    .I0(\MSPReset_II/UIM ),
    .I1(\NlwInverterSignal_U1/Channel1<14>_MC.D2_PT_1/IN1 ),
    .I2(\U1/U6/CurrState_Sreg0_FFD3 ),
    .I3(\NlwInverterSignal_U1/Channel1<14>_MC.D2_PT_1/IN3 ),
    .I4(N_PZ_921),
    .I5(\U1/Channel1 [13]),
    .I6(\U1/Channel1 [10]),
    .I7(\U1/Channel1 [9]),
    .I8(\NlwInverterSignal_U1/Channel1<14>_MC.D2_PT_1/IN8 ),
    .I9(\U1/Channel1 [11]),
    .I10(\U1/Channel1 [12]),
    .I11(Vcc),
    .I12(Vcc),
    .I13(Vcc),
    .I14(Vcc),
    .I15(Vcc),
    .O(\U1/Channel1<14>_MC.D2_PT_1 )
  );
  X_AND16 \U1/Channel1<14>_MC.D2_PT_2_1699  (
    .I0(\MSPReset_II/UIM ),
    .I1(\NlwInverterSignal_U1/Channel1<14>_MC.D2_PT_2/IN1 ),
    .I2(\U1/U6/CurrState_Sreg0_FFD3 ),
    .I3(\NlwInverterSignal_U1/Channel1<14>_MC.D2_PT_2/IN3 ),
    .I4(\NlwInverterSignal_U1/Channel1<14>_MC.D2_PT_2/IN4 ),
    .I5(N_PZ_1092),
    .I6(\NlwInverterSignal_U1/Channel1<14>_MC.D2_PT_2/IN6 ),
    .I7(\NlwInverterSignal_U1/Channel1<14>_MC.D2_PT_2/IN7 ),
    .I8(\NlwInverterSignal_U1/Channel1<14>_MC.D2_PT_2/IN8 ),
    .I9(\U1/U5/location_Maddsub__n0000__n0075 [0]),
    .I10(\NlwInverterSignal_U1/Channel1<14>_MC.D2_PT_2/IN10 ),
    .I11(\NlwInverterSignal_U1/Channel1<14>_MC.D2_PT_2/IN11 ),
    .I12(Vcc),
    .I13(Vcc),
    .I14(Vcc),
    .I15(Vcc),
    .O(\U1/Channel1<14>_MC.D2_PT_2 )
  );
  X_OR3 \U1/Channel1<14>_MC.D2_1700  (
    .I0(\U1/Channel1<14>_MC.D2_PT_0 ),
    .I1(\U1/Channel1<14>_MC.D2_PT_1 ),
    .I2(\U1/Channel1<14>_MC.D2_PT_2 ),
    .O(\U1/Channel1<14>_MC.D2 )
  );
  X_BUF \outDATA<6>\$WA6.UIM_1701  (
    .I(\outDATA<6>\$WA6.UIM_MC.Q ),
    .O(\outDATA<6>\$WA6.UIM )
  );
  X_BUF \outDATA<6>\$WA6.UIM_MC.Q_1702  (
    .I(\outDATA<6>\$WA6.UIM_MC.D ),
    .O(\outDATA<6>\$WA6.UIM_MC.Q )
  );
  X_XOR2 \outDATA<6>\$WA6.UIM_MC.D_1703  (
    .I0(\outDATA<6>\$WA6.UIM_MC.D1 ),
    .I1(\outDATA<6>\$WA6.UIM_MC.D2 ),
    .O(\outDATA<6>\$WA6.UIM_MC.D )
  );
  X_ZERO \outDATA<6>\$WA6.UIM_MC.D1_1704  (
    .O(\outDATA<6>\$WA6.UIM_MC.D1 )
  );
  X_AND2 \outDATA<6>\$WA6.UIM_MC.D2_PT_0_1705  (
    .I0(DCOR0THRESLOWr),
    .I1(\U1/U4/Latch0r [6]),
    .O(\outDATA<6>\$WA6.UIM_MC.D2_PT_0 )
  );
  X_AND3 \outDATA<6>\$WA6.UIM_MC.D2_PT_1_1706  (
    .I0(\NlwInverterSignal_outDATA<6>\$WA6.UIM_MC.D2_PT_1/IN0 ),
    .I1(DCORIFGr),
    .I2(NET2512),
    .O(\outDATA<6>\$WA6.UIM_MC.D2_PT_1 )
  );
  X_AND4 \outDATA<6>\$WA6.UIM_MC.D2_PT_2_1707  (
    .I0(\NlwInverterSignal_outDATA<6>\$WA6.UIM_MC.D2_PT_2/IN0 ),
    .I1(\NlwInverterSignal_outDATA<6>\$WA6.UIM_MC.D2_PT_2/IN1 ),
    .I2(DCOR0THRESHIGHr),
    .I3(\U1/U4/Latch0r [14]),
    .O(\outDATA<6>\$WA6.UIM_MC.D2_PT_2 )
  );
  X_AND5 \outDATA<6>\$WA6.UIM_MC.D2_PT_3_1708  (
    .I0(\NlwInverterSignal_outDATA<6>\$WA6.UIM_MC.D2_PT_3/IN0 ),
    .I1(\NlwInverterSignal_outDATA<6>\$WA6.UIM_MC.D2_PT_3/IN1 ),
    .I2(\NlwInverterSignal_outDATA<6>\$WA6.UIM_MC.D2_PT_3/IN2 ),
    .I3(DCOR1THRESLOWr),
    .I4(\U1/U4/Latch1r [6]),
    .O(\outDATA<6>\$WA6.UIM_MC.D2_PT_3 )
  );
  X_AND5 \outDATA<6>\$WA6.UIM_MC.D2_PT_4_1709  (
    .I0(\NlwInverterSignal_outDATA<6>\$WA6.UIM_MC.D2_PT_4/IN0 ),
    .I1(\NlwInverterSignal_outDATA<6>\$WA6.UIM_MC.D2_PT_4/IN1 ),
    .I2(\NlwInverterSignal_outDATA<6>\$WA6.UIM_MC.D2_PT_4/IN2 ),
    .I3(\NlwInverterSignal_outDATA<6>\$WA6.UIM_MC.D2_PT_4/IN3 ),
    .I4(\U1/U4/Latch1r [14]),
    .O(\outDATA<6>\$WA6.UIM_MC.D2_PT_4 )
  );
  X_OR5 \outDATA<6>\$WA6.UIM_MC.D2_1710  (
    .I0(\outDATA<6>\$WA6.UIM_MC.D2_PT_0 ),
    .I1(\outDATA<6>\$WA6.UIM_MC.D2_PT_1 ),
    .I2(\outDATA<6>\$WA6.UIM_MC.D2_PT_2 ),
    .I3(\outDATA<6>\$WA6.UIM_MC.D2_PT_3 ),
    .I4(\outDATA<6>\$WA6.UIM_MC.D2_PT_4 ),
    .O(\outDATA<6>\$WA6.UIM_MC.D2 )
  );
  X_BUF \U1/U4/Latch0r<6>  (
    .I(\U1/U4/Latch0r<6>_MC.Q ),
    .O(\U1/U4/Latch0r [6])
  );
  X_FF \U1/U4/Latch0r<6>_MC.REG  (
    .I(\U1/U4/Latch0r<6>_MC.D ),
    .CE(Vcc),
    .CLK(\U1/U4/Latch0r<6>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\U1/U4/Latch0r<6>_MC.Q )
  );
  X_INV \U1/U4/Latch0r<6>_MC.REG_tsimcreated_inv_Mclk_II/FCLK_1711  (
    .I(\Mclk_II/FCLK ),
    .O(\U1/U4/Latch0r<6>_MC.REG_tsimcreated_inv_Mclk_II/FCLK )
  );
  X_XOR2 \U1/U4/Latch0r<6>_MC.D_1712  (
    .I0(\U1/U4/Latch0r<6>_MC.D1 ),
    .I1(\U1/U4/Latch0r<6>_MC.D2 ),
    .O(\U1/U4/Latch0r<6>_MC.D )
  );
  X_ZERO \U1/U4/Latch0r<6>_MC.D1_1713  (
    .O(\U1/U4/Latch0r<6>_MC.D1 )
  );
  X_AND3 \U1/U4/Latch0r<6>_MC.D2_PT_0_1714  (
    .I0(\MSPReset_II/UIM ),
    .I1(\U1/Channel0 [6]),
    .I2(N_PZ_963),
    .O(\U1/U4/Latch0r<6>_MC.D2_PT_0 )
  );
  X_AND3 \U1/U4/Latch0r<6>_MC.D2_PT_1_1715  (
    .I0(\MSPReset_II/UIM ),
    .I1(\NlwInverterSignal_U1/U4/Latch0r<6>_MC.D2_PT_1/IN1 ),
    .I2(\U1/U4/Latch0r [6]),
    .O(\U1/U4/Latch0r<6>_MC.D2_PT_1 )
  );
  X_OR2 \U1/U4/Latch0r<6>_MC.D2_1716  (
    .I0(\U1/U4/Latch0r<6>_MC.D2_PT_0 ),
    .I1(\U1/U4/Latch0r<6>_MC.D2_PT_1 ),
    .O(\U1/U4/Latch0r<6>_MC.D2 )
  );
  X_BUF \U1/U4/Latch0r<14>  (
    .I(\U1/U4/Latch0r<14>_MC.Q ),
    .O(\U1/U4/Latch0r [14])
  );
  X_FF \U1/U4/Latch0r<14>_MC.REG  (
    .I(\U1/U4/Latch0r<14>_MC.D ),
    .CE(Vcc),
    .CLK(\U1/U4/Latch0r<14>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\U1/U4/Latch0r<14>_MC.Q )
  );
  X_INV \U1/U4/Latch0r<14>_MC.REG_tsimcreated_inv_Mclk_II/FCLK_1717  (
    .I(\Mclk_II/FCLK ),
    .O(\U1/U4/Latch0r<14>_MC.REG_tsimcreated_inv_Mclk_II/FCLK )
  );
  X_XOR2 \U1/U4/Latch0r<14>_MC.D_1718  (
    .I0(\U1/U4/Latch0r<14>_MC.D1 ),
    .I1(\U1/U4/Latch0r<14>_MC.D2 ),
    .O(\U1/U4/Latch0r<14>_MC.D )
  );
  X_ZERO \U1/U4/Latch0r<14>_MC.D1_1719  (
    .O(\U1/U4/Latch0r<14>_MC.D1 )
  );
  X_AND3 \U1/U4/Latch0r<14>_MC.D2_PT_0_1720  (
    .I0(\MSPReset_II/UIM ),
    .I1(N_PZ_963),
    .I2(\U1/Channel0 [14]),
    .O(\U1/U4/Latch0r<14>_MC.D2_PT_0 )
  );
  X_AND3 \U1/U4/Latch0r<14>_MC.D2_PT_1_1721  (
    .I0(\MSPReset_II/UIM ),
    .I1(\NlwInverterSignal_U1/U4/Latch0r<14>_MC.D2_PT_1/IN1 ),
    .I2(\U1/U4/Latch0r [14]),
    .O(\U1/U4/Latch0r<14>_MC.D2_PT_1 )
  );
  X_OR2 \U1/U4/Latch0r<14>_MC.D2_1722  (
    .I0(\U1/U4/Latch0r<14>_MC.D2_PT_0 ),
    .I1(\U1/U4/Latch0r<14>_MC.D2_PT_1 ),
    .O(\U1/U4/Latch0r<14>_MC.D2 )
  );
  X_BUF \U1/U4/Latch1r<6>  (
    .I(\U1/U4/Latch1r<6>_MC.Q ),
    .O(\U1/U4/Latch1r [6])
  );
  X_FF \U1/U4/Latch1r<6>_MC.REG  (
    .I(\U1/U4/Latch1r<6>_MC.D ),
    .CE(Vcc),
    .CLK(\U1/U4/Latch1r<6>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\U1/U4/Latch1r<6>_MC.Q )
  );
  X_INV \U1/U4/Latch1r<6>_MC.REG_tsimcreated_inv_Mclk_II/FCLK_1723  (
    .I(\Mclk_II/FCLK ),
    .O(\U1/U4/Latch1r<6>_MC.REG_tsimcreated_inv_Mclk_II/FCLK )
  );
  X_XOR2 \U1/U4/Latch1r<6>_MC.D_1724  (
    .I0(\U1/U4/Latch1r<6>_MC.D1 ),
    .I1(\U1/U4/Latch1r<6>_MC.D2 ),
    .O(\U1/U4/Latch1r<6>_MC.D )
  );
  X_ZERO \U1/U4/Latch1r<6>_MC.D1_1725  (
    .O(\U1/U4/Latch1r<6>_MC.D1 )
  );
  X_AND3 \U1/U4/Latch1r<6>_MC.D2_PT_0_1726  (
    .I0(\MSPReset_II/UIM ),
    .I1(\U1/Channel1 [6]),
    .I2(N_PZ_962),
    .O(\U1/U4/Latch1r<6>_MC.D2_PT_0 )
  );
  X_AND3 \U1/U4/Latch1r<6>_MC.D2_PT_1_1727  (
    .I0(\MSPReset_II/UIM ),
    .I1(\NlwInverterSignal_U1/U4/Latch1r<6>_MC.D2_PT_1/IN1 ),
    .I2(\U1/U4/Latch1r [6]),
    .O(\U1/U4/Latch1r<6>_MC.D2_PT_1 )
  );
  X_OR2 \U1/U4/Latch1r<6>_MC.D2_1728  (
    .I0(\U1/U4/Latch1r<6>_MC.D2_PT_0 ),
    .I1(\U1/U4/Latch1r<6>_MC.D2_PT_1 ),
    .O(\U1/U4/Latch1r<6>_MC.D2 )
  );
  X_BUF \U1/U4/Latch1r<14>  (
    .I(\U1/U4/Latch1r<14>_MC.Q ),
    .O(\U1/U4/Latch1r [14])
  );
  X_FF \U1/U4/Latch1r<14>_MC.REG  (
    .I(\U1/U4/Latch1r<14>_MC.D ),
    .CE(Vcc),
    .CLK(\U1/U4/Latch1r<14>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\U1/U4/Latch1r<14>_MC.Q )
  );
  X_INV \U1/U4/Latch1r<14>_MC.REG_tsimcreated_inv_Mclk_II/FCLK_1729  (
    .I(\Mclk_II/FCLK ),
    .O(\U1/U4/Latch1r<14>_MC.REG_tsimcreated_inv_Mclk_II/FCLK )
  );
  X_XOR2 \U1/U4/Latch1r<14>_MC.D_1730  (
    .I0(\U1/U4/Latch1r<14>_MC.D1 ),
    .I1(\U1/U4/Latch1r<14>_MC.D2 ),
    .O(\U1/U4/Latch1r<14>_MC.D )
  );
  X_ZERO \U1/U4/Latch1r<14>_MC.D1_1731  (
    .O(\U1/U4/Latch1r<14>_MC.D1 )
  );
  X_AND3 \U1/U4/Latch1r<14>_MC.D2_PT_0_1732  (
    .I0(\MSPReset_II/UIM ),
    .I1(N_PZ_962),
    .I2(\U1/Channel1 [14]),
    .O(\U1/U4/Latch1r<14>_MC.D2_PT_0 )
  );
  X_AND3 \U1/U4/Latch1r<14>_MC.D2_PT_1_1733  (
    .I0(\MSPReset_II/UIM ),
    .I1(\NlwInverterSignal_U1/U4/Latch1r<14>_MC.D2_PT_1/IN1 ),
    .I2(\U1/U4/Latch1r [14]),
    .O(\U1/U4/Latch1r<14>_MC.D2_PT_1 )
  );
  X_OR2 \U1/U4/Latch1r<14>_MC.D2_1734  (
    .I0(\U1/U4/Latch1r<14>_MC.D2_PT_0 ),
    .I1(\U1/U4/Latch1r<14>_MC.D2_PT_1 ),
    .O(\U1/U4/Latch1r<14>_MC.D2 )
  );
  X_BUF \outDATA<7>\$WA0.UIM_1735  (
    .I(\outDATA<7>\$WA0.UIM_MC.Q ),
    .O(\outDATA<7>\$WA0.UIM )
  );
  X_BUF \outDATA<7>\$WA0.UIM_MC.Q_1736  (
    .I(\outDATA<7>\$WA0.UIM_MC.D ),
    .O(\outDATA<7>\$WA0.UIM_MC.Q )
  );
  X_XOR2 \outDATA<7>\$WA0.UIM_MC.D_1737  (
    .I0(\outDATA<7>\$WA0.UIM_MC.D1 ),
    .I1(\outDATA<7>\$WA0.UIM_MC.D2 ),
    .O(\outDATA<7>\$WA0.UIM_MC.D )
  );
  X_ZERO \outDATA<7>\$WA0.UIM_MC.D1_1738  (
    .O(\outDATA<7>\$WA0.UIM_MC.D1 )
  );
  X_ZERO \outDATA<7>\$WA0.UIM_MC.D2_1739  (
    .O(\outDATA<7>\$WA0.UIM_MC.D2 )
  );
  X_BUF \outDATA<7>\$WA2.UIM_1740  (
    .I(\outDATA<7>\$WA2.UIM_MC.Q ),
    .O(\outDATA<7>\$WA2.UIM )
  );
  X_BUF \outDATA<7>\$WA2.UIM_MC.Q_1741  (
    .I(\outDATA<7>\$WA2.UIM_MC.D ),
    .O(\outDATA<7>\$WA2.UIM_MC.Q )
  );
  X_XOR2 \outDATA<7>\$WA2.UIM_MC.D_1742  (
    .I0(\outDATA<7>\$WA2.UIM_MC.D1 ),
    .I1(\outDATA<7>\$WA2.UIM_MC.D2 ),
    .O(\outDATA<7>\$WA2.UIM_MC.D )
  );
  X_AND2 \outDATA<7>\$WA2.UIM_MC.D1_1743  (
    .I0(NET3253),
    .I1(NET3253),
    .O(\outDATA<7>\$WA2.UIM_MC.D1 )
  );
  X_ZERO \outDATA<7>\$WA2.UIM_MC.D2_1744  (
    .O(\outDATA<7>\$WA2.UIM_MC.D2 )
  );
  X_BUF \outDATA<7>\$WA3.UIM_1745  (
    .I(\outDATA<7>\$WA3.UIM_MC.Q ),
    .O(\outDATA<7>\$WA3.UIM )
  );
  X_BUF \outDATA<7>\$WA3.UIM_MC.Q_1746  (
    .I(\outDATA<7>\$WA3.UIM_MC.D ),
    .O(\outDATA<7>\$WA3.UIM_MC.Q )
  );
  X_XOR2 \outDATA<7>\$WA3.UIM_MC.D_1747  (
    .I0(\outDATA<7>\$WA3.UIM_MC.D1 ),
    .I1(\outDATA<7>\$WA3.UIM_MC.D2 ),
    .O(\outDATA<7>\$WA3.UIM_MC.D )
  );
  X_ZERO \outDATA<7>\$WA3.UIM_MC.D1_1748  (
    .O(\outDATA<7>\$WA3.UIM_MC.D1 )
  );
  X_AND2 \outDATA<7>\$WA3.UIM_MC.D2_PT_0_1749  (
    .I0(NET2528),
    .I1(\U4/Flgreg [7]),
    .O(\outDATA<7>\$WA3.UIM_MC.D2_PT_0 )
  );
  X_AND2 \outDATA<7>\$WA3.UIM_MC.D2_PT_1_1750  (
    .I0(\NlwInverterSignal_outDATA<7>\$WA3.UIM_MC.D2_PT_1/IN0 ),
    .I1(\Enc15FLG_II/UIM ),
    .O(\outDATA<7>\$WA3.UIM_MC.D2_PT_1 )
  );
  X_OR2 \outDATA<7>\$WA3.UIM_MC.D2_1751  (
    .I0(\outDATA<7>\$WA3.UIM_MC.D2_PT_0 ),
    .I1(\outDATA<7>\$WA3.UIM_MC.D2_PT_1 ),
    .O(\outDATA<7>\$WA3.UIM_MC.D2 )
  );
  X_BUF \outDATA<7>\$WA6.UIM_1752  (
    .I(\outDATA<7>\$WA6.UIM_MC.Q ),
    .O(\outDATA<7>\$WA6.UIM )
  );
  X_BUF \outDATA<7>\$WA6.UIM_MC.Q_1753  (
    .I(\outDATA<7>\$WA6.UIM_MC.D ),
    .O(\outDATA<7>\$WA6.UIM_MC.Q )
  );
  X_XOR2 \outDATA<7>\$WA6.UIM_MC.D_1754  (
    .I0(\outDATA<7>\$WA6.UIM_MC.D1 ),
    .I1(\outDATA<7>\$WA6.UIM_MC.D2 ),
    .O(\outDATA<7>\$WA6.UIM_MC.D )
  );
  X_ZERO \outDATA<7>\$WA6.UIM_MC.D1_1755  (
    .O(\outDATA<7>\$WA6.UIM_MC.D1 )
  );
  X_AND2 \outDATA<7>\$WA6.UIM_MC.D2_PT_0_1756  (
    .I0(DCOR0THRESLOWr),
    .I1(\U1/U4/Latch0r [7]),
    .O(\outDATA<7>\$WA6.UIM_MC.D2_PT_0 )
  );
  X_AND3 \outDATA<7>\$WA6.UIM_MC.D2_PT_1_1757  (
    .I0(\NlwInverterSignal_outDATA<7>\$WA6.UIM_MC.D2_PT_1/IN0 ),
    .I1(DCOR0THRESHIGHr),
    .I2(\U1/U4/Latch0r [15]),
    .O(\outDATA<7>\$WA6.UIM_MC.D2_PT_1 )
  );
  X_AND4 \outDATA<7>\$WA6.UIM_MC.D2_PT_2_1758  (
    .I0(\NlwInverterSignal_outDATA<7>\$WA6.UIM_MC.D2_PT_2/IN0 ),
    .I1(\NlwInverterSignal_outDATA<7>\$WA6.UIM_MC.D2_PT_2/IN1 ),
    .I2(DCOR1THRESLOWr),
    .I3(\U1/U4/Latch1r [7]),
    .O(\outDATA<7>\$WA6.UIM_MC.D2_PT_2 )
  );
  X_AND4 \outDATA<7>\$WA6.UIM_MC.D2_PT_3_1759  (
    .I0(\NlwInverterSignal_outDATA<7>\$WA6.UIM_MC.D2_PT_3/IN0 ),
    .I1(\NlwInverterSignal_outDATA<7>\$WA6.UIM_MC.D2_PT_3/IN1 ),
    .I2(\NlwInverterSignal_outDATA<7>\$WA6.UIM_MC.D2_PT_3/IN2 ),
    .I3(\U1/U4/Latch1r [15]),
    .O(\outDATA<7>\$WA6.UIM_MC.D2_PT_3 )
  );
  X_OR4 \outDATA<7>\$WA6.UIM_MC.D2_1760  (
    .I0(\outDATA<7>\$WA6.UIM_MC.D2_PT_0 ),
    .I1(\outDATA<7>\$WA6.UIM_MC.D2_PT_1 ),
    .I2(\outDATA<7>\$WA6.UIM_MC.D2_PT_2 ),
    .I3(\outDATA<7>\$WA6.UIM_MC.D2_PT_3 ),
    .O(\outDATA<7>\$WA6.UIM_MC.D2 )
  );
  X_BUF \U1/U4/Latch0r<7>  (
    .I(\U1/U4/Latch0r<7>_MC.Q ),
    .O(\U1/U4/Latch0r [7])
  );
  X_FF \U1/U4/Latch0r<7>_MC.REG  (
    .I(\U1/U4/Latch0r<7>_MC.D ),
    .CE(Vcc),
    .CLK(\U1/U4/Latch0r<7>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\U1/U4/Latch0r<7>_MC.Q )
  );
  X_INV \U1/U4/Latch0r<7>_MC.REG_tsimcreated_inv_Mclk_II/FCLK_1761  (
    .I(\Mclk_II/FCLK ),
    .O(\U1/U4/Latch0r<7>_MC.REG_tsimcreated_inv_Mclk_II/FCLK )
  );
  X_XOR2 \U1/U4/Latch0r<7>_MC.D_1762  (
    .I0(\U1/U4/Latch0r<7>_MC.D1 ),
    .I1(\U1/U4/Latch0r<7>_MC.D2 ),
    .O(\U1/U4/Latch0r<7>_MC.D )
  );
  X_ZERO \U1/U4/Latch0r<7>_MC.D1_1763  (
    .O(\U1/U4/Latch0r<7>_MC.D1 )
  );
  X_AND3 \U1/U4/Latch0r<7>_MC.D2_PT_0_1764  (
    .I0(\MSPReset_II/UIM ),
    .I1(\U1/Channel0 [7]),
    .I2(N_PZ_963),
    .O(\U1/U4/Latch0r<7>_MC.D2_PT_0 )
  );
  X_AND3 \U1/U4/Latch0r<7>_MC.D2_PT_1_1765  (
    .I0(\MSPReset_II/UIM ),
    .I1(\NlwInverterSignal_U1/U4/Latch0r<7>_MC.D2_PT_1/IN1 ),
    .I2(\U1/U4/Latch0r [7]),
    .O(\U1/U4/Latch0r<7>_MC.D2_PT_1 )
  );
  X_OR2 \U1/U4/Latch0r<7>_MC.D2_1766  (
    .I0(\U1/U4/Latch0r<7>_MC.D2_PT_0 ),
    .I1(\U1/U4/Latch0r<7>_MC.D2_PT_1 ),
    .O(\U1/U4/Latch0r<7>_MC.D2 )
  );
  X_BUF \U1/U4/Latch0r<15>  (
    .I(\U1/U4/Latch0r<15>_MC.Q ),
    .O(\U1/U4/Latch0r [15])
  );
  X_FF \U1/U4/Latch0r<15>_MC.REG  (
    .I(\U1/U4/Latch0r<15>_MC.D ),
    .CE(Vcc),
    .CLK(\U1/U4/Latch0r<15>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\U1/U4/Latch0r<15>_MC.Q )
  );
  X_INV \U1/U4/Latch0r<15>_MC.REG_tsimcreated_inv_Mclk_II/FCLK_1767  (
    .I(\Mclk_II/FCLK ),
    .O(\U1/U4/Latch0r<15>_MC.REG_tsimcreated_inv_Mclk_II/FCLK )
  );
  X_XOR2 \U1/U4/Latch0r<15>_MC.D_1768  (
    .I0(\U1/U4/Latch0r<15>_MC.D1 ),
    .I1(\U1/U4/Latch0r<15>_MC.D2 ),
    .O(\U1/U4/Latch0r<15>_MC.D )
  );
  X_ZERO \U1/U4/Latch0r<15>_MC.D1_1769  (
    .O(\U1/U4/Latch0r<15>_MC.D1 )
  );
  X_AND3 \U1/U4/Latch0r<15>_MC.D2_PT_0_1770  (
    .I0(\MSPReset_II/UIM ),
    .I1(N_PZ_963),
    .I2(\U1/Channel0 [15]),
    .O(\U1/U4/Latch0r<15>_MC.D2_PT_0 )
  );
  X_AND3 \U1/U4/Latch0r<15>_MC.D2_PT_1_1771  (
    .I0(\MSPReset_II/UIM ),
    .I1(\NlwInverterSignal_U1/U4/Latch0r<15>_MC.D2_PT_1/IN1 ),
    .I2(\U1/U4/Latch0r [15]),
    .O(\U1/U4/Latch0r<15>_MC.D2_PT_1 )
  );
  X_OR2 \U1/U4/Latch0r<15>_MC.D2_1772  (
    .I0(\U1/U4/Latch0r<15>_MC.D2_PT_0 ),
    .I1(\U1/U4/Latch0r<15>_MC.D2_PT_1 ),
    .O(\U1/U4/Latch0r<15>_MC.D2 )
  );
  X_BUF \U1/Channel0<15>  (
    .I(\U1/Channel0<15>_MC.Q ),
    .O(\U1/Channel0 [15])
  );
  X_XOR2 \U1/Channel0<15>_MC_tsimcreated_xor__1773  (
    .I0(\U1/Channel0<15>_MC.D ),
    .I1(\U1/Channel0<15>_MC.Q ),
    .O(\U1/Channel0<15>_MC_tsimcreated_xor_ )
  );
  X_FF \U1/Channel0<15>_MC.REG  (
    .I(\U1/Channel0<15>_MC_tsimcreated_xor_ ),
    .CE(Vcc),
    .CLK(\Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\U1/Channel0<15>_MC.Q )
  );
  X_XOR2 \U1/Channel0<15>_MC.D_1774  (
    .I0(\U1/Channel0<15>_MC.D1 ),
    .I1(\U1/Channel0<15>_MC.D2 ),
    .O(\U1/Channel0<15>_MC.D )
  );
  X_ZERO \U1/Channel0<15>_MC.D1_1775  (
    .O(\U1/Channel0<15>_MC.D1 )
  );
  X_AND2 \U1/Channel0<15>_MC.D2_PT_0_1776  (
    .I0(\NlwInverterSignal_U1/Channel0<15>_MC.D2_PT_0/IN0 ),
    .I1(\U1/Channel0 [15]),
    .O(\U1/Channel0<15>_MC.D2_PT_0 )
  );
  X_AND8 \U1/Channel0<15>_MC.D2_PT_1_1777  (
    .I0(N_PZ_964),
    .I1(\NlwInverterSignal_U1/Channel0<15>_MC.D2_PT_1/IN1 ),
    .I2(\NlwInverterSignal_U1/Channel0<15>_MC.D2_PT_1/IN2 ),
    .I3(\NlwInverterSignal_U1/Channel0<15>_MC.D2_PT_1/IN3 ),
    .I4(\U1/U2/location_Maddsub__n0000__n0075 [0]),
    .I5(\NlwInverterSignal_U1/Channel0<15>_MC.D2_PT_1/IN5 ),
    .I6(\NlwInverterSignal_U1/Channel0<15>_MC.D2_PT_1/IN6 ),
    .I7(\NlwInverterSignal_U1/Channel0<15>_MC.D2_PT_1/IN7 ),
    .O(\U1/Channel0<15>_MC.D2_PT_1 )
  );
  X_AND8 \U1/Channel0<15>_MC.D2_PT_2_1778  (
    .I0(N_PZ_968),
    .I1(\U1/Channel0 [13]),
    .I2(\U1/Channel0 [10]),
    .I3(\U1/Channel0 [9]),
    .I4(\NlwInverterSignal_U1/Channel0<15>_MC.D2_PT_2/IN4 ),
    .I5(\U1/Channel0 [11]),
    .I6(\U1/Channel0 [12]),
    .I7(\U1/Channel0 [14]),
    .O(\U1/Channel0<15>_MC.D2_PT_2 )
  );
  X_OR3 \U1/Channel0<15>_MC.D2_1779  (
    .I0(\U1/Channel0<15>_MC.D2_PT_0 ),
    .I1(\U1/Channel0<15>_MC.D2_PT_1 ),
    .I2(\U1/Channel0<15>_MC.D2_PT_2 ),
    .O(\U1/Channel0<15>_MC.D2 )
  );
  X_BUF \U1/U4/Latch1r<7>  (
    .I(\U1/U4/Latch1r<7>_MC.Q ),
    .O(\U1/U4/Latch1r [7])
  );
  X_FF \U1/U4/Latch1r<7>_MC.REG  (
    .I(\U1/U4/Latch1r<7>_MC.D ),
    .CE(Vcc),
    .CLK(\U1/U4/Latch1r<7>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\U1/U4/Latch1r<7>_MC.Q )
  );
  X_INV \U1/U4/Latch1r<7>_MC.REG_tsimcreated_inv_Mclk_II/FCLK_1780  (
    .I(\Mclk_II/FCLK ),
    .O(\U1/U4/Latch1r<7>_MC.REG_tsimcreated_inv_Mclk_II/FCLK )
  );
  X_XOR2 \U1/U4/Latch1r<7>_MC.D_1781  (
    .I0(\U1/U4/Latch1r<7>_MC.D1 ),
    .I1(\U1/U4/Latch1r<7>_MC.D2 ),
    .O(\U1/U4/Latch1r<7>_MC.D )
  );
  X_ZERO \U1/U4/Latch1r<7>_MC.D1_1782  (
    .O(\U1/U4/Latch1r<7>_MC.D1 )
  );
  X_AND3 \U1/U4/Latch1r<7>_MC.D2_PT_0_1783  (
    .I0(\MSPReset_II/UIM ),
    .I1(\U1/Channel1 [7]),
    .I2(N_PZ_962),
    .O(\U1/U4/Latch1r<7>_MC.D2_PT_0 )
  );
  X_AND3 \U1/U4/Latch1r<7>_MC.D2_PT_1_1784  (
    .I0(\MSPReset_II/UIM ),
    .I1(\NlwInverterSignal_U1/U4/Latch1r<7>_MC.D2_PT_1/IN1 ),
    .I2(\U1/U4/Latch1r [7]),
    .O(\U1/U4/Latch1r<7>_MC.D2_PT_1 )
  );
  X_OR2 \U1/U4/Latch1r<7>_MC.D2_1785  (
    .I0(\U1/U4/Latch1r<7>_MC.D2_PT_0 ),
    .I1(\U1/U4/Latch1r<7>_MC.D2_PT_1 ),
    .O(\U1/U4/Latch1r<7>_MC.D2 )
  );
  X_BUF \U1/U4/Latch1r<15>  (
    .I(\U1/U4/Latch1r<15>_MC.Q ),
    .O(\U1/U4/Latch1r [15])
  );
  X_FF \U1/U4/Latch1r<15>_MC.REG  (
    .I(\U1/U4/Latch1r<15>_MC.D ),
    .CE(Vcc),
    .CLK(\U1/U4/Latch1r<15>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\U1/U4/Latch1r<15>_MC.Q )
  );
  X_INV \U1/U4/Latch1r<15>_MC.REG_tsimcreated_inv_Mclk_II/FCLK_1786  (
    .I(\Mclk_II/FCLK ),
    .O(\U1/U4/Latch1r<15>_MC.REG_tsimcreated_inv_Mclk_II/FCLK )
  );
  X_XOR2 \U1/U4/Latch1r<15>_MC.D_1787  (
    .I0(\U1/U4/Latch1r<15>_MC.D1 ),
    .I1(\U1/U4/Latch1r<15>_MC.D2 ),
    .O(\U1/U4/Latch1r<15>_MC.D )
  );
  X_ZERO \U1/U4/Latch1r<15>_MC.D1_1788  (
    .O(\U1/U4/Latch1r<15>_MC.D1 )
  );
  X_AND3 \U1/U4/Latch1r<15>_MC.D2_PT_0_1789  (
    .I0(\MSPReset_II/UIM ),
    .I1(N_PZ_962),
    .I2(\U1/Channel1 [15]),
    .O(\U1/U4/Latch1r<15>_MC.D2_PT_0 )
  );
  X_AND3 \U1/U4/Latch1r<15>_MC.D2_PT_1_1790  (
    .I0(\MSPReset_II/UIM ),
    .I1(\NlwInverterSignal_U1/U4/Latch1r<15>_MC.D2_PT_1/IN1 ),
    .I2(\U1/U4/Latch1r [15]),
    .O(\U1/U4/Latch1r<15>_MC.D2_PT_1 )
  );
  X_OR2 \U1/U4/Latch1r<15>_MC.D2_1791  (
    .I0(\U1/U4/Latch1r<15>_MC.D2_PT_0 ),
    .I1(\U1/U4/Latch1r<15>_MC.D2_PT_1 ),
    .O(\U1/U4/Latch1r<15>_MC.D2 )
  );
  X_BUF \U1/Channel1<15>  (
    .I(\U1/Channel1<15>_MC.Q ),
    .O(\U1/Channel1 [15])
  );
  X_XOR2 \U1/Channel1<15>_MC_tsimcreated_xor__1792  (
    .I0(\U1/Channel1<15>_MC.D ),
    .I1(\U1/Channel1<15>_MC.Q ),
    .O(\U1/Channel1<15>_MC_tsimcreated_xor_ )
  );
  X_FF \U1/Channel1<15>_MC.REG  (
    .I(\U1/Channel1<15>_MC_tsimcreated_xor_ ),
    .CE(Vcc),
    .CLK(\Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\U1/Channel1<15>_MC.Q )
  );
  X_XOR2 \U1/Channel1<15>_MC.D_1793  (
    .I0(\U1/Channel1<15>_MC.D1 ),
    .I1(\U1/Channel1<15>_MC.D2 ),
    .O(\U1/Channel1<15>_MC.D )
  );
  X_ZERO \U1/Channel1<15>_MC.D1_1794  (
    .O(\U1/Channel1<15>_MC.D1 )
  );
  X_AND2 \U1/Channel1<15>_MC.D2_PT_0_1795  (
    .I0(\NlwInverterSignal_U1/Channel1<15>_MC.D2_PT_0/IN0 ),
    .I1(\U1/Channel1 [15]),
    .O(\U1/Channel1<15>_MC.D2_PT_0 )
  );
  X_AND16 \U1/Channel1<15>_MC.D2_PT_1_1796  (
    .I0(\MSPReset_II/UIM ),
    .I1(\NlwInverterSignal_U1/Channel1<15>_MC.D2_PT_1/IN1 ),
    .I2(\U1/U6/CurrState_Sreg0_FFD3 ),
    .I3(\NlwInverterSignal_U1/Channel1<15>_MC.D2_PT_1/IN3 ),
    .I4(N_PZ_921),
    .I5(\U1/Channel1 [13]),
    .I6(\U1/Channel1 [10]),
    .I7(\U1/Channel1 [9]),
    .I8(\NlwInverterSignal_U1/Channel1<15>_MC.D2_PT_1/IN8 ),
    .I9(\U1/Channel1 [11]),
    .I10(\U1/Channel1 [12]),
    .I11(\U1/Channel1 [14]),
    .I12(Vcc),
    .I13(Vcc),
    .I14(Vcc),
    .I15(Vcc),
    .O(\U1/Channel1<15>_MC.D2_PT_1 )
  );
  X_AND16 \U1/Channel1<15>_MC.D2_PT_2_1797  (
    .I0(\MSPReset_II/UIM ),
    .I1(\NlwInverterSignal_U1/Channel1<15>_MC.D2_PT_2/IN1 ),
    .I2(\U1/U6/CurrState_Sreg0_FFD3 ),
    .I3(\NlwInverterSignal_U1/Channel1<15>_MC.D2_PT_2/IN3 ),
    .I4(\NlwInverterSignal_U1/Channel1<15>_MC.D2_PT_2/IN4 ),
    .I5(N_PZ_1092),
    .I6(\NlwInverterSignal_U1/Channel1<15>_MC.D2_PT_2/IN6 ),
    .I7(\NlwInverterSignal_U1/Channel1<15>_MC.D2_PT_2/IN7 ),
    .I8(\NlwInverterSignal_U1/Channel1<15>_MC.D2_PT_2/IN8 ),
    .I9(\U1/U5/location_Maddsub__n0000__n0075 [0]),
    .I10(\NlwInverterSignal_U1/Channel1<15>_MC.D2_PT_2/IN10 ),
    .I11(\NlwInverterSignal_U1/Channel1<15>_MC.D2_PT_2/IN11 ),
    .I12(\NlwInverterSignal_U1/Channel1<15>_MC.D2_PT_2/IN12 ),
    .I13(Vcc),
    .I14(Vcc),
    .I15(Vcc),
    .O(\U1/Channel1<15>_MC.D2_PT_2 )
  );
  X_OR3 \U1/Channel1<15>_MC.D2_1798  (
    .I0(\U1/Channel1<15>_MC.D2_PT_0 ),
    .I1(\U1/Channel1<15>_MC.D2_PT_1 ),
    .I2(\U1/Channel1<15>_MC.D2_PT_2 ),
    .O(\U1/Channel1<15>_MC.D2 )
  );
  X_BUF \outDATA<7>\$WA5.UIM_1799  (
    .I(\outDATA<7>\$WA5.UIM_MC.Q ),
    .O(\outDATA<7>\$WA5.UIM )
  );
  X_BUF \outDATA<7>\$WA5.UIM_MC.Q_1800  (
    .I(\outDATA<7>\$WA5.UIM_MC.D ),
    .O(\outDATA<7>\$WA5.UIM_MC.Q )
  );
  X_XOR2 \outDATA<7>\$WA5.UIM_MC.D_1801  (
    .I0(\outDATA<7>\$WA5.UIM_MC.D1 ),
    .I1(\outDATA<7>\$WA5.UIM_MC.D2 ),
    .O(\outDATA<7>\$WA5.UIM_MC.D )
  );
  X_ZERO \outDATA<7>\$WA5.UIM_MC.D1_1802  (
    .O(\outDATA<7>\$WA5.UIM_MC.D1 )
  );
  X_AND2 \outDATA<7>\$WA5.UIM_MC.D2_PT_0_1803  (
    .I0(DCOR0CNTLOWr),
    .I1(\U1/U3/holdingreg0 [7]),
    .O(\outDATA<7>\$WA5.UIM_MC.D2_PT_0 )
  );
  X_AND3 \outDATA<7>\$WA5.UIM_MC.D2_PT_1_1804  (
    .I0(\NlwInverterSignal_outDATA<7>\$WA5.UIM_MC.D2_PT_1/IN0 ),
    .I1(DCOR1CNTLOWr),
    .I2(\U1/U3/holdingreg1 [7]),
    .O(\outDATA<7>\$WA5.UIM_MC.D2_PT_1 )
  );
  X_AND4 \outDATA<7>\$WA5.UIM_MC.D2_PT_2_1805  (
    .I0(\NlwInverterSignal_outDATA<7>\$WA5.UIM_MC.D2_PT_2/IN0 ),
    .I1(\NlwInverterSignal_outDATA<7>\$WA5.UIM_MC.D2_PT_2/IN1 ),
    .I2(DCOR0CNTHIGHr),
    .I3(\U1/U3/holdingreg0 [15]),
    .O(\outDATA<7>\$WA5.UIM_MC.D2_PT_2 )
  );
  X_AND4 \outDATA<7>\$WA5.UIM_MC.D2_PT_3_1806  (
    .I0(\NlwInverterSignal_outDATA<7>\$WA5.UIM_MC.D2_PT_3/IN0 ),
    .I1(\NlwInverterSignal_outDATA<7>\$WA5.UIM_MC.D2_PT_3/IN1 ),
    .I2(\NlwInverterSignal_outDATA<7>\$WA5.UIM_MC.D2_PT_3/IN2 ),
    .I3(\U1/U3/holdingreg1 [15]),
    .O(\outDATA<7>\$WA5.UIM_MC.D2_PT_3 )
  );
  X_OR4 \outDATA<7>\$WA5.UIM_MC.D2_1807  (
    .I0(\outDATA<7>\$WA5.UIM_MC.D2_PT_0 ),
    .I1(\outDATA<7>\$WA5.UIM_MC.D2_PT_1 ),
    .I2(\outDATA<7>\$WA5.UIM_MC.D2_PT_2 ),
    .I3(\outDATA<7>\$WA5.UIM_MC.D2_PT_3 ),
    .O(\outDATA<7>\$WA5.UIM_MC.D2 )
  );
  X_BUF \U1/U3/holdingreg0<7>  (
    .I(\U1/U3/holdingreg0<7>_MC.Q ),
    .O(\U1/U3/holdingreg0 [7])
  );
  X_FF \U1/U3/holdingreg0<7>_MC.REG  (
    .I(\U1/U3/holdingreg0<7>_MC.D ),
    .CE(Vcc),
    .CLK(\U1/U3/holdingreg0<7>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\U1/U3/holdingreg0<7>_MC.Q )
  );
  X_INV \U1/U3/holdingreg0<7>_MC.REG_tsimcreated_inv_Mclk_II/FCLK_1808  (
    .I(\Mclk_II/FCLK ),
    .O(\U1/U3/holdingreg0<7>_MC.REG_tsimcreated_inv_Mclk_II/FCLK )
  );
  X_XOR2 \U1/U3/holdingreg0<7>_MC.D_1809  (
    .I0(\U1/U3/holdingreg0<7>_MC.D1 ),
    .I1(\U1/U3/holdingreg0<7>_MC.D2 ),
    .O(\U1/U3/holdingreg0<7>_MC.D )
  );
  X_ZERO \U1/U3/holdingreg0<7>_MC.D1_1810  (
    .O(\U1/U3/holdingreg0<7>_MC.D1 )
  );
  X_AND2 \U1/U3/holdingreg0<7>_MC.D2_PT_0_1811  (
    .I0(N_PZ_938),
    .I1(\U1/U3/holdingreg0 [7]),
    .O(\U1/U3/holdingreg0<7>_MC.D2_PT_0 )
  );
  X_AND4 \U1/U3/holdingreg0<7>_MC.D2_PT_1_1812  (
    .I0(\MSPReset_II/UIM ),
    .I1(\NlwInverterSignal_U1/U3/holdingreg0<7>_MC.D2_PT_1/IN1 ),
    .I2(U2_ASedge),
    .I3(\U1/Channel0 [7]),
    .O(\U1/U3/holdingreg0<7>_MC.D2_PT_1 )
  );
  X_OR2 \U1/U3/holdingreg0<7>_MC.D2_1813  (
    .I0(\U1/U3/holdingreg0<7>_MC.D2_PT_0 ),
    .I1(\U1/U3/holdingreg0<7>_MC.D2_PT_1 ),
    .O(\U1/U3/holdingreg0<7>_MC.D2 )
  );
  X_BUF \U1/U3/holdingreg1<7>  (
    .I(\U1/U3/holdingreg1<7>_MC.Q ),
    .O(\U1/U3/holdingreg1 [7])
  );
  X_FF \U1/U3/holdingreg1<7>_MC.REG  (
    .I(\U1/U3/holdingreg1<7>_MC.D ),
    .CE(Vcc),
    .CLK(\U1/U3/holdingreg1<7>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\U1/U3/holdingreg1<7>_MC.Q )
  );
  X_INV \U1/U3/holdingreg1<7>_MC.REG_tsimcreated_inv_Mclk_II/FCLK_1814  (
    .I(\Mclk_II/FCLK ),
    .O(\U1/U3/holdingreg1<7>_MC.REG_tsimcreated_inv_Mclk_II/FCLK )
  );
  X_XOR2 \U1/U3/holdingreg1<7>_MC.D_1815  (
    .I0(\U1/U3/holdingreg1<7>_MC.D1 ),
    .I1(\U1/U3/holdingreg1<7>_MC.D2 ),
    .O(\U1/U3/holdingreg1<7>_MC.D )
  );
  X_ZERO \U1/U3/holdingreg1<7>_MC.D1_1816  (
    .O(\U1/U3/holdingreg1<7>_MC.D1 )
  );
  X_AND2 \U1/U3/holdingreg1<7>_MC.D2_PT_0_1817  (
    .I0(N_PZ_938),
    .I1(\U1/U3/holdingreg1 [7]),
    .O(\U1/U3/holdingreg1<7>_MC.D2_PT_0 )
  );
  X_AND4 \U1/U3/holdingreg1<7>_MC.D2_PT_1_1818  (
    .I0(\MSPReset_II/UIM ),
    .I1(\NlwInverterSignal_U1/U3/holdingreg1<7>_MC.D2_PT_1/IN1 ),
    .I2(U2_ASedge),
    .I3(\U1/Channel1 [7]),
    .O(\U1/U3/holdingreg1<7>_MC.D2_PT_1 )
  );
  X_OR2 \U1/U3/holdingreg1<7>_MC.D2_1819  (
    .I0(\U1/U3/holdingreg1<7>_MC.D2_PT_0 ),
    .I1(\U1/U3/holdingreg1<7>_MC.D2_PT_1 ),
    .O(\U1/U3/holdingreg1<7>_MC.D2 )
  );
  X_BUF \U1/U3/holdingreg0<15>  (
    .I(\U1/U3/holdingreg0<15>_MC.Q ),
    .O(\U1/U3/holdingreg0 [15])
  );
  X_FF \U1/U3/holdingreg0<15>_MC.REG  (
    .I(\U1/U3/holdingreg0<15>_MC.D ),
    .CE(Vcc),
    .CLK(\U1/U3/holdingreg0<15>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\U1/U3/holdingreg0<15>_MC.Q )
  );
  X_INV \U1/U3/holdingreg0<15>_MC.REG_tsimcreated_inv_Mclk_II/FCLK_1820  (
    .I(\Mclk_II/FCLK ),
    .O(\U1/U3/holdingreg0<15>_MC.REG_tsimcreated_inv_Mclk_II/FCLK )
  );
  X_XOR2 \U1/U3/holdingreg0<15>_MC.D_1821  (
    .I0(\U1/U3/holdingreg0<15>_MC.D1 ),
    .I1(\U1/U3/holdingreg0<15>_MC.D2 ),
    .O(\U1/U3/holdingreg0<15>_MC.D )
  );
  X_ZERO \U1/U3/holdingreg0<15>_MC.D1_1822  (
    .O(\U1/U3/holdingreg0<15>_MC.D1 )
  );
  X_AND2 \U1/U3/holdingreg0<15>_MC.D2_PT_0_1823  (
    .I0(N_PZ_938),
    .I1(\U1/U3/holdingreg0 [15]),
    .O(\U1/U3/holdingreg0<15>_MC.D2_PT_0 )
  );
  X_AND4 \U1/U3/holdingreg0<15>_MC.D2_PT_1_1824  (
    .I0(\MSPReset_II/UIM ),
    .I1(\NlwInverterSignal_U1/U3/holdingreg0<15>_MC.D2_PT_1/IN1 ),
    .I2(U2_ASedge),
    .I3(\U1/Channel0 [15]),
    .O(\U1/U3/holdingreg0<15>_MC.D2_PT_1 )
  );
  X_OR2 \U1/U3/holdingreg0<15>_MC.D2_1825  (
    .I0(\U1/U3/holdingreg0<15>_MC.D2_PT_0 ),
    .I1(\U1/U3/holdingreg0<15>_MC.D2_PT_1 ),
    .O(\U1/U3/holdingreg0<15>_MC.D2 )
  );
  X_BUF \U1/U3/holdingreg1<15>  (
    .I(\U1/U3/holdingreg1<15>_MC.Q ),
    .O(\U1/U3/holdingreg1 [15])
  );
  X_FF \U1/U3/holdingreg1<15>_MC.REG  (
    .I(\U1/U3/holdingreg1<15>_MC.D ),
    .CE(Vcc),
    .CLK(\U1/U3/holdingreg1<15>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\U1/U3/holdingreg1<15>_MC.Q )
  );
  X_INV \U1/U3/holdingreg1<15>_MC.REG_tsimcreated_inv_Mclk_II/FCLK_1826  (
    .I(\Mclk_II/FCLK ),
    .O(\U1/U3/holdingreg1<15>_MC.REG_tsimcreated_inv_Mclk_II/FCLK )
  );
  X_XOR2 \U1/U3/holdingreg1<15>_MC.D_1827  (
    .I0(\U1/U3/holdingreg1<15>_MC.D1 ),
    .I1(\U1/U3/holdingreg1<15>_MC.D2 ),
    .O(\U1/U3/holdingreg1<15>_MC.D )
  );
  X_ZERO \U1/U3/holdingreg1<15>_MC.D1_1828  (
    .O(\U1/U3/holdingreg1<15>_MC.D1 )
  );
  X_AND2 \U1/U3/holdingreg1<15>_MC.D2_PT_0_1829  (
    .I0(N_PZ_938),
    .I1(\U1/U3/holdingreg1 [15]),
    .O(\U1/U3/holdingreg1<15>_MC.D2_PT_0 )
  );
  X_AND4 \U1/U3/holdingreg1<15>_MC.D2_PT_1_1830  (
    .I0(\MSPReset_II/UIM ),
    .I1(\NlwInverterSignal_U1/U3/holdingreg1<15>_MC.D2_PT_1/IN1 ),
    .I2(U2_ASedge),
    .I3(\U1/Channel1 [15]),
    .O(\U1/U3/holdingreg1<15>_MC.D2_PT_1 )
  );
  X_OR2 \U1/U3/holdingreg1<15>_MC.D2_1831  (
    .I0(\U1/U3/holdingreg1<15>_MC.D2_PT_0 ),
    .I1(\U1/U3/holdingreg1<15>_MC.D2_PT_1 ),
    .O(\U1/U3/holdingreg1<15>_MC.D2 )
  );
  X_BUF \outDATA<0>\$WA0.UIM_1832  (
    .I(\outDATA<0>\$WA0.UIM_MC.Q ),
    .O(\outDATA<0>\$WA0.UIM )
  );
  X_BUF \outDATA<0>\$WA0.UIM_MC.Q_1833  (
    .I(\outDATA<0>\$WA0.UIM_MC.D ),
    .O(\outDATA<0>\$WA0.UIM_MC.Q )
  );
  X_XOR2 \outDATA<0>\$WA0.UIM_MC.D_1834  (
    .I0(\outDATA<0>\$WA0.UIM_MC.D1 ),
    .I1(\outDATA<0>\$WA0.UIM_MC.D2 ),
    .O(\outDATA<0>\$WA0.UIM_MC.D )
  );
  X_AND2 \outDATA<0>\$WA0.UIM_MC.D1_1835  (
    .I0(U11_U3_counterr[0]),
    .I1(U11_U3_counterr[0]),
    .O(\outDATA<0>\$WA0.UIM_MC.D1 )
  );
  X_ZERO \outDATA<0>\$WA0.UIM_MC.D2_1836  (
    .O(\outDATA<0>\$WA0.UIM_MC.D2 )
  );
  X_BUF \outDATA<0>\$WA1.UIM_1837  (
    .I(\outDATA<0>\$WA1.UIM_MC.Q ),
    .O(\outDATA<0>\$WA1.UIM )
  );
  X_BUF \outDATA<0>\$WA1.UIM_MC.Q_1838  (
    .I(\outDATA<0>\$WA1.UIM_MC.D ),
    .O(\outDATA<0>\$WA1.UIM_MC.Q )
  );
  X_XOR2 \outDATA<0>\$WA1.UIM_MC.D_1839  (
    .I0(\outDATA<0>\$WA1.UIM_MC.D1 ),
    .I1(\outDATA<0>\$WA1.UIM_MC.D2 ),
    .O(\outDATA<0>\$WA1.UIM_MC.D )
  );
  X_AND2 \outDATA<0>\$WA1.UIM_MC.D1_1840  (
    .I0(\I2CS<0>_II/UIM ),
    .I1(\I2CS<0>_II/UIM ),
    .O(\outDATA<0>\$WA1.UIM_MC.D1 )
  );
  X_ZERO \outDATA<0>\$WA1.UIM_MC.D2_1841  (
    .O(\outDATA<0>\$WA1.UIM_MC.D2 )
  );
  X_BUF \outDATA<0>\$WA2.UIM_1842  (
    .I(\outDATA<0>\$WA2.UIM_MC.Q ),
    .O(\outDATA<0>\$WA2.UIM )
  );
  X_BUF \outDATA<0>\$WA2.UIM_MC.Q_1843  (
    .I(\outDATA<0>\$WA2.UIM_MC.D ),
    .O(\outDATA<0>\$WA2.UIM_MC.Q )
  );
  X_XOR2 \outDATA<0>\$WA2.UIM_MC.D_1844  (
    .I0(\outDATA<0>\$WA2.UIM_MC.D1 ),
    .I1(\outDATA<0>\$WA2.UIM_MC.D2 ),
    .O(\outDATA<0>\$WA2.UIM_MC.D )
  );
  X_AND2 \outDATA<0>\$WA2.UIM_MC.D1_1845  (
    .I0(\RLS0_II/UIM ),
    .I1(\RLS0_II/UIM ),
    .O(\outDATA<0>\$WA2.UIM_MC.D1 )
  );
  X_ZERO \outDATA<0>\$WA2.UIM_MC.D2_1846  (
    .O(\outDATA<0>\$WA2.UIM_MC.D2 )
  );
  X_BUF \outDATA<0>\$WA3.UIM_1847  (
    .I(\outDATA<0>\$WA3.UIM_MC.Q ),
    .O(\outDATA<0>\$WA3.UIM )
  );
  X_BUF \outDATA<0>\$WA3.UIM_MC.Q_1848  (
    .I(\outDATA<0>\$WA3.UIM_MC.D ),
    .O(\outDATA<0>\$WA3.UIM_MC.Q )
  );
  X_XOR2 \outDATA<0>\$WA3.UIM_MC.D_1849  (
    .I0(\outDATA<0>\$WA3.UIM_MC.D1 ),
    .I1(\outDATA<0>\$WA3.UIM_MC.D2 ),
    .O(\outDATA<0>\$WA3.UIM_MC.D )
  );
  X_ZERO \outDATA<0>\$WA3.UIM_MC.D1_1850  (
    .O(\outDATA<0>\$WA3.UIM_MC.D1 )
  );
  X_AND2 \outDATA<0>\$WA3.UIM_MC.D2_PT_0_1851  (
    .I0(NET2528),
    .I1(\U4/Flgreg [0]),
    .O(\outDATA<0>\$WA3.UIM_MC.D2_PT_0 )
  );
  X_AND2 \outDATA<0>\$WA3.UIM_MC.D2_PT_1_1852  (
    .I0(\NlwInverterSignal_outDATA<0>\$WA3.UIM_MC.D2_PT_1/IN0 ),
    .I1(\Home033FLG_II/UIM ),
    .O(\outDATA<0>\$WA3.UIM_MC.D2_PT_1 )
  );
  X_OR2 \outDATA<0>\$WA3.UIM_MC.D2_1853  (
    .I0(\outDATA<0>\$WA3.UIM_MC.D2_PT_0 ),
    .I1(\outDATA<0>\$WA3.UIM_MC.D2_PT_1 ),
    .O(\outDATA<0>\$WA3.UIM_MC.D2 )
  );
  X_BUF \outDATA<0>\$WA4.UIM_1854  (
    .I(\outDATA<0>\$WA4.UIM_MC.Q ),
    .O(\outDATA<0>\$WA4.UIM )
  );
  X_BUF \outDATA<0>\$WA4.UIM_MC.Q_1855  (
    .I(\outDATA<0>\$WA4.UIM_MC.D ),
    .O(\outDATA<0>\$WA4.UIM_MC.Q )
  );
  X_XOR2 \outDATA<0>\$WA4.UIM_MC.D_1856  (
    .I0(\outDATA<0>\$WA4.UIM_MC.D1 ),
    .I1(\outDATA<0>\$WA4.UIM_MC.D2 ),
    .O(\outDATA<0>\$WA4.UIM_MC.D )
  );
  X_AND2 \outDATA<0>\$WA4.UIM_MC.D1_1857  (
    .I0(\INTbus_II/UIM ),
    .I1(\INTbus_II/UIM ),
    .O(\outDATA<0>\$WA4.UIM_MC.D1 )
  );
  X_ZERO \outDATA<0>\$WA4.UIM_MC.D2_1858  (
    .O(\outDATA<0>\$WA4.UIM_MC.D2 )
  );
  X_BUF \outDATA<0>\$WA6.UIM_1859  (
    .I(\outDATA<0>\$WA6.UIM_MC.Q ),
    .O(\outDATA<0>\$WA6.UIM )
  );
  X_BUF \outDATA<0>\$WA6.UIM_MC.Q_1860  (
    .I(\outDATA<0>\$WA6.UIM_MC.D ),
    .O(\outDATA<0>\$WA6.UIM_MC.Q )
  );
  X_XOR2 \outDATA<0>\$WA6.UIM_MC.D_1861  (
    .I0(\outDATA<0>\$WA6.UIM_MC.D1 ),
    .I1(\outDATA<0>\$WA6.UIM_MC.D2 ),
    .O(\outDATA<0>\$WA6.UIM_MC.D )
  );
  X_ZERO \outDATA<0>\$WA6.UIM_MC.D1_1862  (
    .O(\outDATA<0>\$WA6.UIM_MC.D1 )
  );
  X_AND2 \outDATA<0>\$WA6.UIM_MC.D2_PT_0_1863  (
    .I0(DCOR0THRESLOWr),
    .I1(\U1/U4/Latch0r [0]),
    .O(\outDATA<0>\$WA6.UIM_MC.D2_PT_0 )
  );
  X_AND3 \outDATA<0>\$WA6.UIM_MC.D2_PT_1_1864  (
    .I0(\NlwInverterSignal_outDATA<0>\$WA6.UIM_MC.D2_PT_1/IN0 ),
    .I1(DCOR0THRESHIGHr),
    .I2(\U1/U4/Latch0r [8]),
    .O(\outDATA<0>\$WA6.UIM_MC.D2_PT_1 )
  );
  X_AND4 \outDATA<0>\$WA6.UIM_MC.D2_PT_2_1865  (
    .I0(\NlwInverterSignal_outDATA<0>\$WA6.UIM_MC.D2_PT_2/IN0 ),
    .I1(\NlwInverterSignal_outDATA<0>\$WA6.UIM_MC.D2_PT_2/IN1 ),
    .I2(DCOR1THRESLOWr),
    .I3(\U1/U4/Latch1r [0]),
    .O(\outDATA<0>\$WA6.UIM_MC.D2_PT_2 )
  );
  X_AND4 \outDATA<0>\$WA6.UIM_MC.D2_PT_3_1866  (
    .I0(\NlwInverterSignal_outDATA<0>\$WA6.UIM_MC.D2_PT_3/IN0 ),
    .I1(\NlwInverterSignal_outDATA<0>\$WA6.UIM_MC.D2_PT_3/IN1 ),
    .I2(\NlwInverterSignal_outDATA<0>\$WA6.UIM_MC.D2_PT_3/IN2 ),
    .I3(\U1/U4/Latch1r [8]),
    .O(\outDATA<0>\$WA6.UIM_MC.D2_PT_3 )
  );
  X_OR4 \outDATA<0>\$WA6.UIM_MC.D2_1867  (
    .I0(\outDATA<0>\$WA6.UIM_MC.D2_PT_0 ),
    .I1(\outDATA<0>\$WA6.UIM_MC.D2_PT_1 ),
    .I2(\outDATA<0>\$WA6.UIM_MC.D2_PT_2 ),
    .I3(\outDATA<0>\$WA6.UIM_MC.D2_PT_3 ),
    .O(\outDATA<0>\$WA6.UIM_MC.D2 )
  );
  X_BUF \U1/U4/Latch0r<0>  (
    .I(\U1/U4/Latch0r<0>_MC.Q ),
    .O(\U1/U4/Latch0r [0])
  );
  X_FF \U1/U4/Latch0r<0>_MC.REG  (
    .I(\U1/U4/Latch0r<0>_MC.D ),
    .CE(Vcc),
    .CLK(\U1/U4/Latch0r<0>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\U1/U4/Latch0r<0>_MC.Q )
  );
  X_INV \U1/U4/Latch0r<0>_MC.REG_tsimcreated_inv_Mclk_II/FCLK_1868  (
    .I(\Mclk_II/FCLK ),
    .O(\U1/U4/Latch0r<0>_MC.REG_tsimcreated_inv_Mclk_II/FCLK )
  );
  X_XOR2 \U1/U4/Latch0r<0>_MC.D_1869  (
    .I0(\U1/U4/Latch0r<0>_MC.D1 ),
    .I1(\U1/U4/Latch0r<0>_MC.D2 ),
    .O(\U1/U4/Latch0r<0>_MC.D )
  );
  X_ZERO \U1/U4/Latch0r<0>_MC.D1_1870  (
    .O(\U1/U4/Latch0r<0>_MC.D1 )
  );
  X_AND3 \U1/U4/Latch0r<0>_MC.D2_PT_0_1871  (
    .I0(\MSPReset_II/UIM ),
    .I1(\U1/Channel0 [0]),
    .I2(N_PZ_963),
    .O(\U1/U4/Latch0r<0>_MC.D2_PT_0 )
  );
  X_AND3 \U1/U4/Latch0r<0>_MC.D2_PT_1_1872  (
    .I0(\MSPReset_II/UIM ),
    .I1(\NlwInverterSignal_U1/U4/Latch0r<0>_MC.D2_PT_1/IN1 ),
    .I2(\U1/U4/Latch0r [0]),
    .O(\U1/U4/Latch0r<0>_MC.D2_PT_1 )
  );
  X_OR2 \U1/U4/Latch0r<0>_MC.D2_1873  (
    .I0(\U1/U4/Latch0r<0>_MC.D2_PT_0 ),
    .I1(\U1/U4/Latch0r<0>_MC.D2_PT_1 ),
    .O(\U1/U4/Latch0r<0>_MC.D2 )
  );
  X_BUF \U1/U4/Latch0r<8>  (
    .I(\U1/U4/Latch0r<8>_MC.Q ),
    .O(\U1/U4/Latch0r [8])
  );
  X_FF \U1/U4/Latch0r<8>_MC.REG  (
    .I(\U1/U4/Latch0r<8>_MC.D ),
    .CE(Vcc),
    .CLK(\U1/U4/Latch0r<8>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\U1/U4/Latch0r<8>_MC.Q )
  );
  X_INV \U1/U4/Latch0r<8>_MC.REG_tsimcreated_inv_Mclk_II/FCLK_1874  (
    .I(\Mclk_II/FCLK ),
    .O(\U1/U4/Latch0r<8>_MC.REG_tsimcreated_inv_Mclk_II/FCLK )
  );
  X_XOR2 \U1/U4/Latch0r<8>_MC.D_1875  (
    .I0(\U1/U4/Latch0r<8>_MC.D1 ),
    .I1(\U1/U4/Latch0r<8>_MC.D2 ),
    .O(\U1/U4/Latch0r<8>_MC.D )
  );
  X_ZERO \U1/U4/Latch0r<8>_MC.D1_1876  (
    .O(\U1/U4/Latch0r<8>_MC.D1 )
  );
  X_AND3 \U1/U4/Latch0r<8>_MC.D2_PT_0_1877  (
    .I0(\MSPReset_II/UIM ),
    .I1(\U1/Channel0 [8]),
    .I2(N_PZ_963),
    .O(\U1/U4/Latch0r<8>_MC.D2_PT_0 )
  );
  X_AND3 \U1/U4/Latch0r<8>_MC.D2_PT_1_1878  (
    .I0(\MSPReset_II/UIM ),
    .I1(\NlwInverterSignal_U1/U4/Latch0r<8>_MC.D2_PT_1/IN1 ),
    .I2(\U1/U4/Latch0r [8]),
    .O(\U1/U4/Latch0r<8>_MC.D2_PT_1 )
  );
  X_OR2 \U1/U4/Latch0r<8>_MC.D2_1879  (
    .I0(\U1/U4/Latch0r<8>_MC.D2_PT_0 ),
    .I1(\U1/U4/Latch0r<8>_MC.D2_PT_1 ),
    .O(\U1/U4/Latch0r<8>_MC.D2 )
  );
  X_BUF \U1/U4/Latch1r<0>  (
    .I(\U1/U4/Latch1r<0>_MC.Q ),
    .O(\U1/U4/Latch1r [0])
  );
  X_FF \U1/U4/Latch1r<0>_MC.REG  (
    .I(\U1/U4/Latch1r<0>_MC.D ),
    .CE(Vcc),
    .CLK(\U1/U4/Latch1r<0>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\U1/U4/Latch1r<0>_MC.Q )
  );
  X_INV \U1/U4/Latch1r<0>_MC.REG_tsimcreated_inv_Mclk_II/FCLK_1880  (
    .I(\Mclk_II/FCLK ),
    .O(\U1/U4/Latch1r<0>_MC.REG_tsimcreated_inv_Mclk_II/FCLK )
  );
  X_XOR2 \U1/U4/Latch1r<0>_MC.D_1881  (
    .I0(\U1/U4/Latch1r<0>_MC.D1 ),
    .I1(\U1/U4/Latch1r<0>_MC.D2 ),
    .O(\U1/U4/Latch1r<0>_MC.D )
  );
  X_ZERO \U1/U4/Latch1r<0>_MC.D1_1882  (
    .O(\U1/U4/Latch1r<0>_MC.D1 )
  );
  X_AND3 \U1/U4/Latch1r<0>_MC.D2_PT_0_1883  (
    .I0(\MSPReset_II/UIM ),
    .I1(\U1/Channel1 [0]),
    .I2(N_PZ_962),
    .O(\U1/U4/Latch1r<0>_MC.D2_PT_0 )
  );
  X_AND3 \U1/U4/Latch1r<0>_MC.D2_PT_1_1884  (
    .I0(\MSPReset_II/UIM ),
    .I1(\NlwInverterSignal_U1/U4/Latch1r<0>_MC.D2_PT_1/IN1 ),
    .I2(\U1/U4/Latch1r [0]),
    .O(\U1/U4/Latch1r<0>_MC.D2_PT_1 )
  );
  X_OR2 \U1/U4/Latch1r<0>_MC.D2_1885  (
    .I0(\U1/U4/Latch1r<0>_MC.D2_PT_0 ),
    .I1(\U1/U4/Latch1r<0>_MC.D2_PT_1 ),
    .O(\U1/U4/Latch1r<0>_MC.D2 )
  );
  X_BUF \U1/U4/Latch1r<8>  (
    .I(\U1/U4/Latch1r<8>_MC.Q ),
    .O(\U1/U4/Latch1r [8])
  );
  X_FF \U1/U4/Latch1r<8>_MC.REG  (
    .I(\U1/U4/Latch1r<8>_MC.D ),
    .CE(Vcc),
    .CLK(\U1/U4/Latch1r<8>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\U1/U4/Latch1r<8>_MC.Q )
  );
  X_INV \U1/U4/Latch1r<8>_MC.REG_tsimcreated_inv_Mclk_II/FCLK_1886  (
    .I(\Mclk_II/FCLK ),
    .O(\U1/U4/Latch1r<8>_MC.REG_tsimcreated_inv_Mclk_II/FCLK )
  );
  X_XOR2 \U1/U4/Latch1r<8>_MC.D_1887  (
    .I0(\U1/U4/Latch1r<8>_MC.D1 ),
    .I1(\U1/U4/Latch1r<8>_MC.D2 ),
    .O(\U1/U4/Latch1r<8>_MC.D )
  );
  X_ZERO \U1/U4/Latch1r<8>_MC.D1_1888  (
    .O(\U1/U4/Latch1r<8>_MC.D1 )
  );
  X_AND3 \U1/U4/Latch1r<8>_MC.D2_PT_0_1889  (
    .I0(\MSPReset_II/UIM ),
    .I1(\U1/Channel1 [8]),
    .I2(N_PZ_962),
    .O(\U1/U4/Latch1r<8>_MC.D2_PT_0 )
  );
  X_AND3 \U1/U4/Latch1r<8>_MC.D2_PT_1_1890  (
    .I0(\MSPReset_II/UIM ),
    .I1(\NlwInverterSignal_U1/U4/Latch1r<8>_MC.D2_PT_1/IN1 ),
    .I2(\U1/U4/Latch1r [8]),
    .O(\U1/U4/Latch1r<8>_MC.D2_PT_1 )
  );
  X_OR2 \U1/U4/Latch1r<8>_MC.D2_1891  (
    .I0(\U1/U4/Latch1r<8>_MC.D2_PT_0 ),
    .I1(\U1/U4/Latch1r<8>_MC.D2_PT_1 ),
    .O(\U1/U4/Latch1r<8>_MC.D2 )
  );
  X_BUF \outDATA<0>\$WA5.UIM_1892  (
    .I(\outDATA<0>\$WA5.UIM_MC.Q ),
    .O(\outDATA<0>\$WA5.UIM )
  );
  X_BUF \outDATA<0>\$WA5.UIM_MC.Q_1893  (
    .I(\outDATA<0>\$WA5.UIM_MC.D ),
    .O(\outDATA<0>\$WA5.UIM_MC.Q )
  );
  X_XOR2 \outDATA<0>\$WA5.UIM_MC.D_1894  (
    .I0(\outDATA<0>\$WA5.UIM_MC.D1 ),
    .I1(\outDATA<0>\$WA5.UIM_MC.D2 ),
    .O(\outDATA<0>\$WA5.UIM_MC.D )
  );
  X_ZERO \outDATA<0>\$WA5.UIM_MC.D1_1895  (
    .O(\outDATA<0>\$WA5.UIM_MC.D1 )
  );
  X_AND2 \outDATA<0>\$WA5.UIM_MC.D2_PT_0_1896  (
    .I0(DCOR0CNTLOWr),
    .I1(\U1/U3/holdingreg0 [0]),
    .O(\outDATA<0>\$WA5.UIM_MC.D2_PT_0 )
  );
  X_AND3 \outDATA<0>\$WA5.UIM_MC.D2_PT_1_1897  (
    .I0(\NlwInverterSignal_outDATA<0>\$WA5.UIM_MC.D2_PT_1/IN0 ),
    .I1(DCOR1CNTLOWr),
    .I2(\U1/U3/holdingreg1 [0]),
    .O(\outDATA<0>\$WA5.UIM_MC.D2_PT_1 )
  );
  X_AND4 \outDATA<0>\$WA5.UIM_MC.D2_PT_2_1898  (
    .I0(\NlwInverterSignal_outDATA<0>\$WA5.UIM_MC.D2_PT_2/IN0 ),
    .I1(\NlwInverterSignal_outDATA<0>\$WA5.UIM_MC.D2_PT_2/IN1 ),
    .I2(DCOR0CNTHIGHr),
    .I3(\U1/U3/holdingreg0 [8]),
    .O(\outDATA<0>\$WA5.UIM_MC.D2_PT_2 )
  );
  X_AND4 \outDATA<0>\$WA5.UIM_MC.D2_PT_3_1899  (
    .I0(\NlwInverterSignal_outDATA<0>\$WA5.UIM_MC.D2_PT_3/IN0 ),
    .I1(\NlwInverterSignal_outDATA<0>\$WA5.UIM_MC.D2_PT_3/IN1 ),
    .I2(\NlwInverterSignal_outDATA<0>\$WA5.UIM_MC.D2_PT_3/IN2 ),
    .I3(\U1/U3/holdingreg1 [8]),
    .O(\outDATA<0>\$WA5.UIM_MC.D2_PT_3 )
  );
  X_OR4 \outDATA<0>\$WA5.UIM_MC.D2_1900  (
    .I0(\outDATA<0>\$WA5.UIM_MC.D2_PT_0 ),
    .I1(\outDATA<0>\$WA5.UIM_MC.D2_PT_1 ),
    .I2(\outDATA<0>\$WA5.UIM_MC.D2_PT_2 ),
    .I3(\outDATA<0>\$WA5.UIM_MC.D2_PT_3 ),
    .O(\outDATA<0>\$WA5.UIM_MC.D2 )
  );
  X_BUF \U1/U3/holdingreg0<0>  (
    .I(\U1/U3/holdingreg0<0>_MC.Q ),
    .O(\U1/U3/holdingreg0 [0])
  );
  X_FF \U1/U3/holdingreg0<0>_MC.REG  (
    .I(\U1/U3/holdingreg0<0>_MC.D ),
    .CE(Vcc),
    .CLK(\U1/U3/holdingreg0<0>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\U1/U3/holdingreg0<0>_MC.Q )
  );
  X_INV \U1/U3/holdingreg0<0>_MC.REG_tsimcreated_inv_Mclk_II/FCLK_1901  (
    .I(\Mclk_II/FCLK ),
    .O(\U1/U3/holdingreg0<0>_MC.REG_tsimcreated_inv_Mclk_II/FCLK )
  );
  X_XOR2 \U1/U3/holdingreg0<0>_MC.D_1902  (
    .I0(\U1/U3/holdingreg0<0>_MC.D1 ),
    .I1(\U1/U3/holdingreg0<0>_MC.D2 ),
    .O(\U1/U3/holdingreg0<0>_MC.D )
  );
  X_ZERO \U1/U3/holdingreg0<0>_MC.D1_1903  (
    .O(\U1/U3/holdingreg0<0>_MC.D1 )
  );
  X_AND2 \U1/U3/holdingreg0<0>_MC.D2_PT_0_1904  (
    .I0(N_PZ_938),
    .I1(\U1/U3/holdingreg0 [0]),
    .O(\U1/U3/holdingreg0<0>_MC.D2_PT_0 )
  );
  X_AND4 \U1/U3/holdingreg0<0>_MC.D2_PT_1_1905  (
    .I0(\MSPReset_II/UIM ),
    .I1(\NlwInverterSignal_U1/U3/holdingreg0<0>_MC.D2_PT_1/IN1 ),
    .I2(U2_ASedge),
    .I3(\U1/Channel0 [0]),
    .O(\U1/U3/holdingreg0<0>_MC.D2_PT_1 )
  );
  X_OR2 \U1/U3/holdingreg0<0>_MC.D2_1906  (
    .I0(\U1/U3/holdingreg0<0>_MC.D2_PT_0 ),
    .I1(\U1/U3/holdingreg0<0>_MC.D2_PT_1 ),
    .O(\U1/U3/holdingreg0<0>_MC.D2 )
  );
  X_BUF \U1/U3/holdingreg1<0>  (
    .I(\U1/U3/holdingreg1<0>_MC.Q ),
    .O(\U1/U3/holdingreg1 [0])
  );
  X_FF \U1/U3/holdingreg1<0>_MC.REG  (
    .I(\U1/U3/holdingreg1<0>_MC.D ),
    .CE(Vcc),
    .CLK(\U1/U3/holdingreg1<0>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\U1/U3/holdingreg1<0>_MC.Q )
  );
  X_INV \U1/U3/holdingreg1<0>_MC.REG_tsimcreated_inv_Mclk_II/FCLK_1907  (
    .I(\Mclk_II/FCLK ),
    .O(\U1/U3/holdingreg1<0>_MC.REG_tsimcreated_inv_Mclk_II/FCLK )
  );
  X_XOR2 \U1/U3/holdingreg1<0>_MC.D_1908  (
    .I0(\U1/U3/holdingreg1<0>_MC.D1 ),
    .I1(\U1/U3/holdingreg1<0>_MC.D2 ),
    .O(\U1/U3/holdingreg1<0>_MC.D )
  );
  X_ZERO \U1/U3/holdingreg1<0>_MC.D1_1909  (
    .O(\U1/U3/holdingreg1<0>_MC.D1 )
  );
  X_AND2 \U1/U3/holdingreg1<0>_MC.D2_PT_0_1910  (
    .I0(N_PZ_938),
    .I1(\U1/U3/holdingreg1 [0]),
    .O(\U1/U3/holdingreg1<0>_MC.D2_PT_0 )
  );
  X_AND4 \U1/U3/holdingreg1<0>_MC.D2_PT_1_1911  (
    .I0(\MSPReset_II/UIM ),
    .I1(\NlwInverterSignal_U1/U3/holdingreg1<0>_MC.D2_PT_1/IN1 ),
    .I2(U2_ASedge),
    .I3(\U1/Channel1 [0]),
    .O(\U1/U3/holdingreg1<0>_MC.D2_PT_1 )
  );
  X_OR2 \U1/U3/holdingreg1<0>_MC.D2_1912  (
    .I0(\U1/U3/holdingreg1<0>_MC.D2_PT_0 ),
    .I1(\U1/U3/holdingreg1<0>_MC.D2_PT_1 ),
    .O(\U1/U3/holdingreg1<0>_MC.D2 )
  );
  X_BUF \U1/U3/holdingreg0<8>  (
    .I(\U1/U3/holdingreg0<8>_MC.Q ),
    .O(\U1/U3/holdingreg0 [8])
  );
  X_FF \U1/U3/holdingreg0<8>_MC.REG  (
    .I(\U1/U3/holdingreg0<8>_MC.D ),
    .CE(Vcc),
    .CLK(\U1/U3/holdingreg0<8>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\U1/U3/holdingreg0<8>_MC.Q )
  );
  X_INV \U1/U3/holdingreg0<8>_MC.REG_tsimcreated_inv_Mclk_II/FCLK_1913  (
    .I(\Mclk_II/FCLK ),
    .O(\U1/U3/holdingreg0<8>_MC.REG_tsimcreated_inv_Mclk_II/FCLK )
  );
  X_XOR2 \U1/U3/holdingreg0<8>_MC.D_1914  (
    .I0(\U1/U3/holdingreg0<8>_MC.D1 ),
    .I1(\U1/U3/holdingreg0<8>_MC.D2 ),
    .O(\U1/U3/holdingreg0<8>_MC.D )
  );
  X_ZERO \U1/U3/holdingreg0<8>_MC.D1_1915  (
    .O(\U1/U3/holdingreg0<8>_MC.D1 )
  );
  X_AND2 \U1/U3/holdingreg0<8>_MC.D2_PT_0_1916  (
    .I0(N_PZ_938),
    .I1(\U1/U3/holdingreg0 [8]),
    .O(\U1/U3/holdingreg0<8>_MC.D2_PT_0 )
  );
  X_AND4 \U1/U3/holdingreg0<8>_MC.D2_PT_1_1917  (
    .I0(\MSPReset_II/UIM ),
    .I1(\NlwInverterSignal_U1/U3/holdingreg0<8>_MC.D2_PT_1/IN1 ),
    .I2(U2_ASedge),
    .I3(\U1/Channel0 [8]),
    .O(\U1/U3/holdingreg0<8>_MC.D2_PT_1 )
  );
  X_OR2 \U1/U3/holdingreg0<8>_MC.D2_1918  (
    .I0(\U1/U3/holdingreg0<8>_MC.D2_PT_0 ),
    .I1(\U1/U3/holdingreg0<8>_MC.D2_PT_1 ),
    .O(\U1/U3/holdingreg0<8>_MC.D2 )
  );
  X_BUF \U1/U3/holdingreg1<8>  (
    .I(\U1/U3/holdingreg1<8>_MC.Q ),
    .O(\U1/U3/holdingreg1 [8])
  );
  X_FF \U1/U3/holdingreg1<8>_MC.REG  (
    .I(\U1/U3/holdingreg1<8>_MC.D ),
    .CE(Vcc),
    .CLK(\U1/U3/holdingreg1<8>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\U1/U3/holdingreg1<8>_MC.Q )
  );
  X_INV \U1/U3/holdingreg1<8>_MC.REG_tsimcreated_inv_Mclk_II/FCLK_1919  (
    .I(\Mclk_II/FCLK ),
    .O(\U1/U3/holdingreg1<8>_MC.REG_tsimcreated_inv_Mclk_II/FCLK )
  );
  X_XOR2 \U1/U3/holdingreg1<8>_MC.D_1920  (
    .I0(\U1/U3/holdingreg1<8>_MC.D1 ),
    .I1(\U1/U3/holdingreg1<8>_MC.D2 ),
    .O(\U1/U3/holdingreg1<8>_MC.D )
  );
  X_ZERO \U1/U3/holdingreg1<8>_MC.D1_1921  (
    .O(\U1/U3/holdingreg1<8>_MC.D1 )
  );
  X_AND2 \U1/U3/holdingreg1<8>_MC.D2_PT_0_1922  (
    .I0(N_PZ_938),
    .I1(\U1/U3/holdingreg1 [8]),
    .O(\U1/U3/holdingreg1<8>_MC.D2_PT_0 )
  );
  X_AND4 \U1/U3/holdingreg1<8>_MC.D2_PT_1_1923  (
    .I0(\MSPReset_II/UIM ),
    .I1(\NlwInverterSignal_U1/U3/holdingreg1<8>_MC.D2_PT_1/IN1 ),
    .I2(U2_ASedge),
    .I3(\U1/Channel1 [8]),
    .O(\U1/U3/holdingreg1<8>_MC.D2_PT_1 )
  );
  X_OR2 \U1/U3/holdingreg1<8>_MC.D2_1924  (
    .I0(\U1/U3/holdingreg1<8>_MC.D2_PT_0 ),
    .I1(\U1/U3/holdingreg1<8>_MC.D2_PT_1 ),
    .O(\U1/U3/holdingreg1<8>_MC.D2 )
  );
  X_BUF \outDATA<1>\$WA0.UIM_1925  (
    .I(\outDATA<1>\$WA0.UIM_MC.Q ),
    .O(\outDATA<1>\$WA0.UIM )
  );
  X_BUF \outDATA<1>\$WA0.UIM_MC.Q_1926  (
    .I(\outDATA<1>\$WA0.UIM_MC.D ),
    .O(\outDATA<1>\$WA0.UIM_MC.Q )
  );
  X_XOR2 \outDATA<1>\$WA0.UIM_MC.D_1927  (
    .I0(\outDATA<1>\$WA0.UIM_MC.D1 ),
    .I1(\outDATA<1>\$WA0.UIM_MC.D2 ),
    .O(\outDATA<1>\$WA0.UIM_MC.D )
  );
  X_AND2 \outDATA<1>\$WA0.UIM_MC.D1_1928  (
    .I0(U11_U3_counterr[1]),
    .I1(U11_U3_counterr[1]),
    .O(\outDATA<1>\$WA0.UIM_MC.D1 )
  );
  X_ZERO \outDATA<1>\$WA0.UIM_MC.D2_1929  (
    .O(\outDATA<1>\$WA0.UIM_MC.D2 )
  );
  X_BUF \outDATA<1>\$WA1.UIM_1930  (
    .I(\outDATA<1>\$WA1.UIM_MC.Q ),
    .O(\outDATA<1>\$WA1.UIM )
  );
  X_BUF \outDATA<1>\$WA1.UIM_MC.Q_1931  (
    .I(\outDATA<1>\$WA1.UIM_MC.D ),
    .O(\outDATA<1>\$WA1.UIM_MC.Q )
  );
  X_XOR2 \outDATA<1>\$WA1.UIM_MC.D_1932  (
    .I0(\outDATA<1>\$WA1.UIM_MC.D1 ),
    .I1(\outDATA<1>\$WA1.UIM_MC.D2 ),
    .O(\outDATA<1>\$WA1.UIM_MC.D )
  );
  X_AND2 \outDATA<1>\$WA1.UIM_MC.D1_1933  (
    .I0(\I2CS<1>_II/UIM ),
    .I1(\I2CS<1>_II/UIM ),
    .O(\outDATA<1>\$WA1.UIM_MC.D1 )
  );
  X_ZERO \outDATA<1>\$WA1.UIM_MC.D2_1934  (
    .O(\outDATA<1>\$WA1.UIM_MC.D2 )
  );
  X_BUF \outDATA<1>\$WA2.UIM_1935  (
    .I(\outDATA<1>\$WA2.UIM_MC.Q ),
    .O(\outDATA<1>\$WA2.UIM )
  );
  X_BUF \outDATA<1>\$WA2.UIM_MC.Q_1936  (
    .I(\outDATA<1>\$WA2.UIM_MC.D ),
    .O(\outDATA<1>\$WA2.UIM_MC.Q )
  );
  X_XOR2 \outDATA<1>\$WA2.UIM_MC.D_1937  (
    .I0(\outDATA<1>\$WA2.UIM_MC.D1 ),
    .I1(\outDATA<1>\$WA2.UIM_MC.D2 ),
    .O(\outDATA<1>\$WA2.UIM_MC.D )
  );
  X_AND2 \outDATA<1>\$WA2.UIM_MC.D1_1938  (
    .I0(\FLS0_II/UIM ),
    .I1(\FLS0_II/UIM ),
    .O(\outDATA<1>\$WA2.UIM_MC.D1 )
  );
  X_ZERO \outDATA<1>\$WA2.UIM_MC.D2_1939  (
    .O(\outDATA<1>\$WA2.UIM_MC.D2 )
  );
  X_BUF \outDATA<1>\$WA3.UIM_1940  (
    .I(\outDATA<1>\$WA3.UIM_MC.Q ),
    .O(\outDATA<1>\$WA3.UIM )
  );
  X_BUF \outDATA<1>\$WA3.UIM_MC.Q_1941  (
    .I(\outDATA<1>\$WA3.UIM_MC.D ),
    .O(\outDATA<1>\$WA3.UIM_MC.Q )
  );
  X_XOR2 \outDATA<1>\$WA3.UIM_MC.D_1942  (
    .I0(\outDATA<1>\$WA3.UIM_MC.D1 ),
    .I1(\outDATA<1>\$WA3.UIM_MC.D2 ),
    .O(\outDATA<1>\$WA3.UIM_MC.D )
  );
  X_ZERO \outDATA<1>\$WA3.UIM_MC.D1_1943  (
    .O(\outDATA<1>\$WA3.UIM_MC.D1 )
  );
  X_AND2 \outDATA<1>\$WA3.UIM_MC.D2_PT_0_1944  (
    .I0(\NlwInverterSignal_outDATA<1>\$WA3.UIM_MC.D2_PT_0/IN0 ),
    .I1(NET2528),
    .O(\outDATA<1>\$WA3.UIM_MC.D2_PT_0 )
  );
  X_AND2 \outDATA<1>\$WA3.UIM_MC.D2_PT_1_1945  (
    .I0(NET2528),
    .I1(\U4/Flgreg [1]),
    .O(\outDATA<1>\$WA3.UIM_MC.D2_PT_1 )
  );
  X_AND3 \outDATA<1>\$WA3.UIM_MC.D2_PT_2_1946  (
    .I0(DCORENCPWRr),
    .I1(\NlwInverterSignal_outDATA<1>\$WA3.UIM_MC.D2_PT_2/IN1 ),
    .I2(\Home05FLG_II/UIM ),
    .O(\outDATA<1>\$WA3.UIM_MC.D2_PT_2 )
  );
  X_OR3 \outDATA<1>\$WA3.UIM_MC.D2_1947  (
    .I0(\outDATA<1>\$WA3.UIM_MC.D2_PT_0 ),
    .I1(\outDATA<1>\$WA3.UIM_MC.D2_PT_1 ),
    .I2(\outDATA<1>\$WA3.UIM_MC.D2_PT_2 ),
    .O(\outDATA<1>\$WA3.UIM_MC.D2 )
  );
  X_BUF \outDATA<1>\$WA6.UIM_1948  (
    .I(\outDATA<1>\$WA6.UIM_MC.Q ),
    .O(\outDATA<1>\$WA6.UIM )
  );
  X_BUF \outDATA<1>\$WA6.UIM_MC.Q_1949  (
    .I(\outDATA<1>\$WA6.UIM_MC.D ),
    .O(\outDATA<1>\$WA6.UIM_MC.Q )
  );
  X_XOR2 \outDATA<1>\$WA6.UIM_MC.D_1950  (
    .I0(\outDATA<1>\$WA6.UIM_MC.D1 ),
    .I1(\outDATA<1>\$WA6.UIM_MC.D2 ),
    .O(\outDATA<1>\$WA6.UIM_MC.D )
  );
  X_ZERO \outDATA<1>\$WA6.UIM_MC.D1_1951  (
    .O(\outDATA<1>\$WA6.UIM_MC.D1 )
  );
  X_AND2 \outDATA<1>\$WA6.UIM_MC.D2_PT_0_1952  (
    .I0(DCOR0THRESLOWr),
    .I1(\U1/U4/Latch0r [1]),
    .O(\outDATA<1>\$WA6.UIM_MC.D2_PT_0 )
  );
  X_AND3 \outDATA<1>\$WA6.UIM_MC.D2_PT_1_1953  (
    .I0(\NlwInverterSignal_outDATA<1>\$WA6.UIM_MC.D2_PT_1/IN0 ),
    .I1(DCOR0THRESHIGHr),
    .I2(\U1/U4/Latch0r [9]),
    .O(\outDATA<1>\$WA6.UIM_MC.D2_PT_1 )
  );
  X_AND4 \outDATA<1>\$WA6.UIM_MC.D2_PT_2_1954  (
    .I0(\NlwInverterSignal_outDATA<1>\$WA6.UIM_MC.D2_PT_2/IN0 ),
    .I1(\NlwInverterSignal_outDATA<1>\$WA6.UIM_MC.D2_PT_2/IN1 ),
    .I2(DCOR1THRESLOWr),
    .I3(\U1/U4/Latch1r [1]),
    .O(\outDATA<1>\$WA6.UIM_MC.D2_PT_2 )
  );
  X_AND4 \outDATA<1>\$WA6.UIM_MC.D2_PT_3_1955  (
    .I0(\NlwInverterSignal_outDATA<1>\$WA6.UIM_MC.D2_PT_3/IN0 ),
    .I1(\NlwInverterSignal_outDATA<1>\$WA6.UIM_MC.D2_PT_3/IN1 ),
    .I2(\NlwInverterSignal_outDATA<1>\$WA6.UIM_MC.D2_PT_3/IN2 ),
    .I3(\U1/U4/Latch1r [9]),
    .O(\outDATA<1>\$WA6.UIM_MC.D2_PT_3 )
  );
  X_OR4 \outDATA<1>\$WA6.UIM_MC.D2_1956  (
    .I0(\outDATA<1>\$WA6.UIM_MC.D2_PT_0 ),
    .I1(\outDATA<1>\$WA6.UIM_MC.D2_PT_1 ),
    .I2(\outDATA<1>\$WA6.UIM_MC.D2_PT_2 ),
    .I3(\outDATA<1>\$WA6.UIM_MC.D2_PT_3 ),
    .O(\outDATA<1>\$WA6.UIM_MC.D2 )
  );
  X_BUF \U1/U4/Latch0r<1>  (
    .I(\U1/U4/Latch0r<1>_MC.Q ),
    .O(\U1/U4/Latch0r [1])
  );
  X_FF \U1/U4/Latch0r<1>_MC.REG  (
    .I(\U1/U4/Latch0r<1>_MC.D ),
    .CE(Vcc),
    .CLK(\U1/U4/Latch0r<1>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\U1/U4/Latch0r<1>_MC.Q )
  );
  X_INV \U1/U4/Latch0r<1>_MC.REG_tsimcreated_inv_Mclk_II/FCLK_1957  (
    .I(\Mclk_II/FCLK ),
    .O(\U1/U4/Latch0r<1>_MC.REG_tsimcreated_inv_Mclk_II/FCLK )
  );
  X_XOR2 \U1/U4/Latch0r<1>_MC.D_1958  (
    .I0(\U1/U4/Latch0r<1>_MC.D1 ),
    .I1(\U1/U4/Latch0r<1>_MC.D2 ),
    .O(\U1/U4/Latch0r<1>_MC.D )
  );
  X_ZERO \U1/U4/Latch0r<1>_MC.D1_1959  (
    .O(\U1/U4/Latch0r<1>_MC.D1 )
  );
  X_AND3 \U1/U4/Latch0r<1>_MC.D2_PT_0_1960  (
    .I0(\MSPReset_II/UIM ),
    .I1(\U1/Channel0 [1]),
    .I2(N_PZ_963),
    .O(\U1/U4/Latch0r<1>_MC.D2_PT_0 )
  );
  X_AND3 \U1/U4/Latch0r<1>_MC.D2_PT_1_1961  (
    .I0(\MSPReset_II/UIM ),
    .I1(\NlwInverterSignal_U1/U4/Latch0r<1>_MC.D2_PT_1/IN1 ),
    .I2(\U1/U4/Latch0r [1]),
    .O(\U1/U4/Latch0r<1>_MC.D2_PT_1 )
  );
  X_OR2 \U1/U4/Latch0r<1>_MC.D2_1962  (
    .I0(\U1/U4/Latch0r<1>_MC.D2_PT_0 ),
    .I1(\U1/U4/Latch0r<1>_MC.D2_PT_1 ),
    .O(\U1/U4/Latch0r<1>_MC.D2 )
  );
  X_BUF \U1/U4/Latch0r<9>  (
    .I(\U1/U4/Latch0r<9>_MC.Q ),
    .O(\U1/U4/Latch0r [9])
  );
  X_FF \U1/U4/Latch0r<9>_MC.REG  (
    .I(\U1/U4/Latch0r<9>_MC.D ),
    .CE(Vcc),
    .CLK(\U1/U4/Latch0r<9>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\U1/U4/Latch0r<9>_MC.Q )
  );
  X_INV \U1/U4/Latch0r<9>_MC.REG_tsimcreated_inv_Mclk_II/FCLK_1963  (
    .I(\Mclk_II/FCLK ),
    .O(\U1/U4/Latch0r<9>_MC.REG_tsimcreated_inv_Mclk_II/FCLK )
  );
  X_XOR2 \U1/U4/Latch0r<9>_MC.D_1964  (
    .I0(\U1/U4/Latch0r<9>_MC.D1 ),
    .I1(\U1/U4/Latch0r<9>_MC.D2 ),
    .O(\U1/U4/Latch0r<9>_MC.D )
  );
  X_ZERO \U1/U4/Latch0r<9>_MC.D1_1965  (
    .O(\U1/U4/Latch0r<9>_MC.D1 )
  );
  X_AND3 \U1/U4/Latch0r<9>_MC.D2_PT_0_1966  (
    .I0(\MSPReset_II/UIM ),
    .I1(\U1/Channel0 [9]),
    .I2(N_PZ_963),
    .O(\U1/U4/Latch0r<9>_MC.D2_PT_0 )
  );
  X_AND3 \U1/U4/Latch0r<9>_MC.D2_PT_1_1967  (
    .I0(\MSPReset_II/UIM ),
    .I1(\NlwInverterSignal_U1/U4/Latch0r<9>_MC.D2_PT_1/IN1 ),
    .I2(\U1/U4/Latch0r [9]),
    .O(\U1/U4/Latch0r<9>_MC.D2_PT_1 )
  );
  X_OR2 \U1/U4/Latch0r<9>_MC.D2_1968  (
    .I0(\U1/U4/Latch0r<9>_MC.D2_PT_0 ),
    .I1(\U1/U4/Latch0r<9>_MC.D2_PT_1 ),
    .O(\U1/U4/Latch0r<9>_MC.D2 )
  );
  X_BUF \U1/U4/Latch1r<1>  (
    .I(\U1/U4/Latch1r<1>_MC.Q ),
    .O(\U1/U4/Latch1r [1])
  );
  X_FF \U1/U4/Latch1r<1>_MC.REG  (
    .I(\U1/U4/Latch1r<1>_MC.D ),
    .CE(Vcc),
    .CLK(\U1/U4/Latch1r<1>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\U1/U4/Latch1r<1>_MC.Q )
  );
  X_INV \U1/U4/Latch1r<1>_MC.REG_tsimcreated_inv_Mclk_II/FCLK_1969  (
    .I(\Mclk_II/FCLK ),
    .O(\U1/U4/Latch1r<1>_MC.REG_tsimcreated_inv_Mclk_II/FCLK )
  );
  X_XOR2 \U1/U4/Latch1r<1>_MC.D_1970  (
    .I0(\U1/U4/Latch1r<1>_MC.D1 ),
    .I1(\U1/U4/Latch1r<1>_MC.D2 ),
    .O(\U1/U4/Latch1r<1>_MC.D )
  );
  X_ZERO \U1/U4/Latch1r<1>_MC.D1_1971  (
    .O(\U1/U4/Latch1r<1>_MC.D1 )
  );
  X_AND3 \U1/U4/Latch1r<1>_MC.D2_PT_0_1972  (
    .I0(\MSPReset_II/UIM ),
    .I1(\U1/Channel1 [1]),
    .I2(N_PZ_962),
    .O(\U1/U4/Latch1r<1>_MC.D2_PT_0 )
  );
  X_AND3 \U1/U4/Latch1r<1>_MC.D2_PT_1_1973  (
    .I0(\MSPReset_II/UIM ),
    .I1(\NlwInverterSignal_U1/U4/Latch1r<1>_MC.D2_PT_1/IN1 ),
    .I2(\U1/U4/Latch1r [1]),
    .O(\U1/U4/Latch1r<1>_MC.D2_PT_1 )
  );
  X_OR2 \U1/U4/Latch1r<1>_MC.D2_1974  (
    .I0(\U1/U4/Latch1r<1>_MC.D2_PT_0 ),
    .I1(\U1/U4/Latch1r<1>_MC.D2_PT_1 ),
    .O(\U1/U4/Latch1r<1>_MC.D2 )
  );
  X_BUF \U1/U4/Latch1r<9>  (
    .I(\U1/U4/Latch1r<9>_MC.Q ),
    .O(\U1/U4/Latch1r [9])
  );
  X_FF \U1/U4/Latch1r<9>_MC.REG  (
    .I(\U1/U4/Latch1r<9>_MC.D ),
    .CE(Vcc),
    .CLK(\U1/U4/Latch1r<9>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\U1/U4/Latch1r<9>_MC.Q )
  );
  X_INV \U1/U4/Latch1r<9>_MC.REG_tsimcreated_inv_Mclk_II/FCLK_1975  (
    .I(\Mclk_II/FCLK ),
    .O(\U1/U4/Latch1r<9>_MC.REG_tsimcreated_inv_Mclk_II/FCLK )
  );
  X_XOR2 \U1/U4/Latch1r<9>_MC.D_1976  (
    .I0(\U1/U4/Latch1r<9>_MC.D1 ),
    .I1(\U1/U4/Latch1r<9>_MC.D2 ),
    .O(\U1/U4/Latch1r<9>_MC.D )
  );
  X_ZERO \U1/U4/Latch1r<9>_MC.D1_1977  (
    .O(\U1/U4/Latch1r<9>_MC.D1 )
  );
  X_AND3 \U1/U4/Latch1r<9>_MC.D2_PT_0_1978  (
    .I0(\MSPReset_II/UIM ),
    .I1(\U1/Channel1 [9]),
    .I2(N_PZ_962),
    .O(\U1/U4/Latch1r<9>_MC.D2_PT_0 )
  );
  X_AND3 \U1/U4/Latch1r<9>_MC.D2_PT_1_1979  (
    .I0(\MSPReset_II/UIM ),
    .I1(\NlwInverterSignal_U1/U4/Latch1r<9>_MC.D2_PT_1/IN1 ),
    .I2(\U1/U4/Latch1r [9]),
    .O(\U1/U4/Latch1r<9>_MC.D2_PT_1 )
  );
  X_OR2 \U1/U4/Latch1r<9>_MC.D2_1980  (
    .I0(\U1/U4/Latch1r<9>_MC.D2_PT_0 ),
    .I1(\U1/U4/Latch1r<9>_MC.D2_PT_1 ),
    .O(\U1/U4/Latch1r<9>_MC.D2 )
  );
  X_BUF \outDATA<1>\$WA5.UIM_1981  (
    .I(\outDATA<1>\$WA5.UIM_MC.Q ),
    .O(\outDATA<1>\$WA5.UIM )
  );
  X_BUF \outDATA<1>\$WA5.UIM_MC.Q_1982  (
    .I(\outDATA<1>\$WA5.UIM_MC.D ),
    .O(\outDATA<1>\$WA5.UIM_MC.Q )
  );
  X_XOR2 \outDATA<1>\$WA5.UIM_MC.D_1983  (
    .I0(\outDATA<1>\$WA5.UIM_MC.D1 ),
    .I1(\outDATA<1>\$WA5.UIM_MC.D2 ),
    .O(\outDATA<1>\$WA5.UIM_MC.D )
  );
  X_ZERO \outDATA<1>\$WA5.UIM_MC.D1_1984  (
    .O(\outDATA<1>\$WA5.UIM_MC.D1 )
  );
  X_AND2 \outDATA<1>\$WA5.UIM_MC.D2_PT_0_1985  (
    .I0(DCOR0CNTLOWr),
    .I1(\U1/U3/holdingreg0 [1]),
    .O(\outDATA<1>\$WA5.UIM_MC.D2_PT_0 )
  );
  X_AND3 \outDATA<1>\$WA5.UIM_MC.D2_PT_1_1986  (
    .I0(\NlwInverterSignal_outDATA<1>\$WA5.UIM_MC.D2_PT_1/IN0 ),
    .I1(DCOR1CNTLOWr),
    .I2(\U1/U3/holdingreg1 [1]),
    .O(\outDATA<1>\$WA5.UIM_MC.D2_PT_1 )
  );
  X_AND4 \outDATA<1>\$WA5.UIM_MC.D2_PT_2_1987  (
    .I0(\NlwInverterSignal_outDATA<1>\$WA5.UIM_MC.D2_PT_2/IN0 ),
    .I1(\NlwInverterSignal_outDATA<1>\$WA5.UIM_MC.D2_PT_2/IN1 ),
    .I2(DCOR0CNTHIGHr),
    .I3(\U1/U3/holdingreg0 [9]),
    .O(\outDATA<1>\$WA5.UIM_MC.D2_PT_2 )
  );
  X_AND4 \outDATA<1>\$WA5.UIM_MC.D2_PT_3_1988  (
    .I0(\NlwInverterSignal_outDATA<1>\$WA5.UIM_MC.D2_PT_3/IN0 ),
    .I1(\NlwInverterSignal_outDATA<1>\$WA5.UIM_MC.D2_PT_3/IN1 ),
    .I2(\NlwInverterSignal_outDATA<1>\$WA5.UIM_MC.D2_PT_3/IN2 ),
    .I3(\U1/U3/holdingreg1 [9]),
    .O(\outDATA<1>\$WA5.UIM_MC.D2_PT_3 )
  );
  X_OR4 \outDATA<1>\$WA5.UIM_MC.D2_1989  (
    .I0(\outDATA<1>\$WA5.UIM_MC.D2_PT_0 ),
    .I1(\outDATA<1>\$WA5.UIM_MC.D2_PT_1 ),
    .I2(\outDATA<1>\$WA5.UIM_MC.D2_PT_2 ),
    .I3(\outDATA<1>\$WA5.UIM_MC.D2_PT_3 ),
    .O(\outDATA<1>\$WA5.UIM_MC.D2 )
  );
  X_BUF \U1/U3/holdingreg0<1>  (
    .I(\U1/U3/holdingreg0<1>_MC.Q ),
    .O(\U1/U3/holdingreg0 [1])
  );
  X_FF \U1/U3/holdingreg0<1>_MC.REG  (
    .I(\U1/U3/holdingreg0<1>_MC.D ),
    .CE(Vcc),
    .CLK(\U1/U3/holdingreg0<1>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\U1/U3/holdingreg0<1>_MC.Q )
  );
  X_INV \U1/U3/holdingreg0<1>_MC.REG_tsimcreated_inv_Mclk_II/FCLK_1990  (
    .I(\Mclk_II/FCLK ),
    .O(\U1/U3/holdingreg0<1>_MC.REG_tsimcreated_inv_Mclk_II/FCLK )
  );
  X_XOR2 \U1/U3/holdingreg0<1>_MC.D_1991  (
    .I0(\U1/U3/holdingreg0<1>_MC.D1 ),
    .I1(\U1/U3/holdingreg0<1>_MC.D2 ),
    .O(\U1/U3/holdingreg0<1>_MC.D )
  );
  X_ZERO \U1/U3/holdingreg0<1>_MC.D1_1992  (
    .O(\U1/U3/holdingreg0<1>_MC.D1 )
  );
  X_AND2 \U1/U3/holdingreg0<1>_MC.D2_PT_0_1993  (
    .I0(N_PZ_938),
    .I1(\U1/U3/holdingreg0 [1]),
    .O(\U1/U3/holdingreg0<1>_MC.D2_PT_0 )
  );
  X_AND4 \U1/U3/holdingreg0<1>_MC.D2_PT_1_1994  (
    .I0(\MSPReset_II/UIM ),
    .I1(\NlwInverterSignal_U1/U3/holdingreg0<1>_MC.D2_PT_1/IN1 ),
    .I2(U2_ASedge),
    .I3(\U1/Channel0 [1]),
    .O(\U1/U3/holdingreg0<1>_MC.D2_PT_1 )
  );
  X_OR2 \U1/U3/holdingreg0<1>_MC.D2_1995  (
    .I0(\U1/U3/holdingreg0<1>_MC.D2_PT_0 ),
    .I1(\U1/U3/holdingreg0<1>_MC.D2_PT_1 ),
    .O(\U1/U3/holdingreg0<1>_MC.D2 )
  );
  X_BUF \U1/U3/holdingreg1<1>  (
    .I(\U1/U3/holdingreg1<1>_MC.Q ),
    .O(\U1/U3/holdingreg1 [1])
  );
  X_FF \U1/U3/holdingreg1<1>_MC.REG  (
    .I(\U1/U3/holdingreg1<1>_MC.D ),
    .CE(Vcc),
    .CLK(\U1/U3/holdingreg1<1>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\U1/U3/holdingreg1<1>_MC.Q )
  );
  X_INV \U1/U3/holdingreg1<1>_MC.REG_tsimcreated_inv_Mclk_II/FCLK_1996  (
    .I(\Mclk_II/FCLK ),
    .O(\U1/U3/holdingreg1<1>_MC.REG_tsimcreated_inv_Mclk_II/FCLK )
  );
  X_XOR2 \U1/U3/holdingreg1<1>_MC.D_1997  (
    .I0(\U1/U3/holdingreg1<1>_MC.D1 ),
    .I1(\U1/U3/holdingreg1<1>_MC.D2 ),
    .O(\U1/U3/holdingreg1<1>_MC.D )
  );
  X_ZERO \U1/U3/holdingreg1<1>_MC.D1_1998  (
    .O(\U1/U3/holdingreg1<1>_MC.D1 )
  );
  X_AND2 \U1/U3/holdingreg1<1>_MC.D2_PT_0_1999  (
    .I0(N_PZ_938),
    .I1(\U1/U3/holdingreg1 [1]),
    .O(\U1/U3/holdingreg1<1>_MC.D2_PT_0 )
  );
  X_AND4 \U1/U3/holdingreg1<1>_MC.D2_PT_1_2000  (
    .I0(\MSPReset_II/UIM ),
    .I1(\NlwInverterSignal_U1/U3/holdingreg1<1>_MC.D2_PT_1/IN1 ),
    .I2(U2_ASedge),
    .I3(\U1/Channel1 [1]),
    .O(\U1/U3/holdingreg1<1>_MC.D2_PT_1 )
  );
  X_OR2 \U1/U3/holdingreg1<1>_MC.D2_2001  (
    .I0(\U1/U3/holdingreg1<1>_MC.D2_PT_0 ),
    .I1(\U1/U3/holdingreg1<1>_MC.D2_PT_1 ),
    .O(\U1/U3/holdingreg1<1>_MC.D2 )
  );
  X_BUF \U1/U3/holdingreg0<9>  (
    .I(\U1/U3/holdingreg0<9>_MC.Q ),
    .O(\U1/U3/holdingreg0 [9])
  );
  X_FF \U1/U3/holdingreg0<9>_MC.REG  (
    .I(\U1/U3/holdingreg0<9>_MC.D ),
    .CE(Vcc),
    .CLK(\U1/U3/holdingreg0<9>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\U1/U3/holdingreg0<9>_MC.Q )
  );
  X_INV \U1/U3/holdingreg0<9>_MC.REG_tsimcreated_inv_Mclk_II/FCLK_2002  (
    .I(\Mclk_II/FCLK ),
    .O(\U1/U3/holdingreg0<9>_MC.REG_tsimcreated_inv_Mclk_II/FCLK )
  );
  X_XOR2 \U1/U3/holdingreg0<9>_MC.D_2003  (
    .I0(\U1/U3/holdingreg0<9>_MC.D1 ),
    .I1(\U1/U3/holdingreg0<9>_MC.D2 ),
    .O(\U1/U3/holdingreg0<9>_MC.D )
  );
  X_ZERO \U1/U3/holdingreg0<9>_MC.D1_2004  (
    .O(\U1/U3/holdingreg0<9>_MC.D1 )
  );
  X_AND2 \U1/U3/holdingreg0<9>_MC.D2_PT_0_2005  (
    .I0(N_PZ_938),
    .I1(\U1/U3/holdingreg0 [9]),
    .O(\U1/U3/holdingreg0<9>_MC.D2_PT_0 )
  );
  X_AND4 \U1/U3/holdingreg0<9>_MC.D2_PT_1_2006  (
    .I0(\MSPReset_II/UIM ),
    .I1(\NlwInverterSignal_U1/U3/holdingreg0<9>_MC.D2_PT_1/IN1 ),
    .I2(U2_ASedge),
    .I3(\U1/Channel0 [9]),
    .O(\U1/U3/holdingreg0<9>_MC.D2_PT_1 )
  );
  X_OR2 \U1/U3/holdingreg0<9>_MC.D2_2007  (
    .I0(\U1/U3/holdingreg0<9>_MC.D2_PT_0 ),
    .I1(\U1/U3/holdingreg0<9>_MC.D2_PT_1 ),
    .O(\U1/U3/holdingreg0<9>_MC.D2 )
  );
  X_BUF \U1/U3/holdingreg1<9>  (
    .I(\U1/U3/holdingreg1<9>_MC.Q ),
    .O(\U1/U3/holdingreg1 [9])
  );
  X_FF \U1/U3/holdingreg1<9>_MC.REG  (
    .I(\U1/U3/holdingreg1<9>_MC.D ),
    .CE(Vcc),
    .CLK(\U1/U3/holdingreg1<9>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\U1/U3/holdingreg1<9>_MC.Q )
  );
  X_INV \U1/U3/holdingreg1<9>_MC.REG_tsimcreated_inv_Mclk_II/FCLK_2008  (
    .I(\Mclk_II/FCLK ),
    .O(\U1/U3/holdingreg1<9>_MC.REG_tsimcreated_inv_Mclk_II/FCLK )
  );
  X_XOR2 \U1/U3/holdingreg1<9>_MC.D_2009  (
    .I0(\U1/U3/holdingreg1<9>_MC.D1 ),
    .I1(\U1/U3/holdingreg1<9>_MC.D2 ),
    .O(\U1/U3/holdingreg1<9>_MC.D )
  );
  X_ZERO \U1/U3/holdingreg1<9>_MC.D1_2010  (
    .O(\U1/U3/holdingreg1<9>_MC.D1 )
  );
  X_AND2 \U1/U3/holdingreg1<9>_MC.D2_PT_0_2011  (
    .I0(N_PZ_938),
    .I1(\U1/U3/holdingreg1 [9]),
    .O(\U1/U3/holdingreg1<9>_MC.D2_PT_0 )
  );
  X_AND4 \U1/U3/holdingreg1<9>_MC.D2_PT_1_2012  (
    .I0(\MSPReset_II/UIM ),
    .I1(\NlwInverterSignal_U1/U3/holdingreg1<9>_MC.D2_PT_1/IN1 ),
    .I2(U2_ASedge),
    .I3(\U1/Channel1 [9]),
    .O(\U1/U3/holdingreg1<9>_MC.D2_PT_1 )
  );
  X_OR2 \U1/U3/holdingreg1<9>_MC.D2_2013  (
    .I0(\U1/U3/holdingreg1<9>_MC.D2_PT_0 ),
    .I1(\U1/U3/holdingreg1<9>_MC.D2_PT_1 ),
    .O(\U1/U3/holdingreg1<9>_MC.D2 )
  );
  X_BUF \outDATA<4>\$WA0.UIM_2014  (
    .I(\outDATA<4>\$WA0.UIM_MC.Q ),
    .O(\outDATA<4>\$WA0.UIM )
  );
  X_BUF \outDATA<4>\$WA0.UIM_MC.Q_2015  (
    .I(\outDATA<4>\$WA0.UIM_MC.D ),
    .O(\outDATA<4>\$WA0.UIM_MC.Q )
  );
  X_XOR2 \outDATA<4>\$WA0.UIM_MC.D_2016  (
    .I0(\outDATA<4>\$WA0.UIM_MC.D1 ),
    .I1(\outDATA<4>\$WA0.UIM_MC.D2 ),
    .O(\outDATA<4>\$WA0.UIM_MC.D )
  );
  X_AND2 \outDATA<4>\$WA0.UIM_MC.D1_2017  (
    .I0(U11_U3_counterr[4]),
    .I1(U11_U3_counterr[4]),
    .O(\outDATA<4>\$WA0.UIM_MC.D1 )
  );
  X_ZERO \outDATA<4>\$WA0.UIM_MC.D2_2018  (
    .O(\outDATA<4>\$WA0.UIM_MC.D2 )
  );
  X_BUF \outDATA<4>\$WA1.UIM_2019  (
    .I(\outDATA<4>\$WA1.UIM_MC.Q ),
    .O(\outDATA<4>\$WA1.UIM )
  );
  X_BUF \outDATA<4>\$WA1.UIM_MC.Q_2020  (
    .I(\outDATA<4>\$WA1.UIM_MC.D ),
    .O(\outDATA<4>\$WA1.UIM_MC.Q )
  );
  X_XOR2 \outDATA<4>\$WA1.UIM_MC.D_2021  (
    .I0(\outDATA<4>\$WA1.UIM_MC.D1 ),
    .I1(\outDATA<4>\$WA1.UIM_MC.D2 ),
    .O(\outDATA<4>\$WA1.UIM_MC.D )
  );
  X_AND2 \outDATA<4>\$WA1.UIM_MC.D1_2022  (
    .I0(\I2CS<4>_II/UIM ),
    .I1(\I2CS<4>_II/UIM ),
    .O(\outDATA<4>\$WA1.UIM_MC.D1 )
  );
  X_ZERO \outDATA<4>\$WA1.UIM_MC.D2_2023  (
    .O(\outDATA<4>\$WA1.UIM_MC.D2 )
  );
  X_BUF \outDATA<4>\$WA2.UIM_2024  (
    .I(\outDATA<4>\$WA2.UIM_MC.Q ),
    .O(\outDATA<4>\$WA2.UIM )
  );
  X_BUF \outDATA<4>\$WA2.UIM_MC.Q_2025  (
    .I(\outDATA<4>\$WA2.UIM_MC.D ),
    .O(\outDATA<4>\$WA2.UIM_MC.Q )
  );
  X_XOR2 \outDATA<4>\$WA2.UIM_MC.D_2026  (
    .I0(\outDATA<4>\$WA2.UIM_MC.D1 ),
    .I1(\outDATA<4>\$WA2.UIM_MC.D2 ),
    .O(\outDATA<4>\$WA2.UIM_MC.D )
  );
  X_AND2 \outDATA<4>\$WA2.UIM_MC.D1_2027  (
    .I0(\RLS1_II/UIM ),
    .I1(\RLS1_II/UIM ),
    .O(\outDATA<4>\$WA2.UIM_MC.D1 )
  );
  X_ZERO \outDATA<4>\$WA2.UIM_MC.D2_2028  (
    .O(\outDATA<4>\$WA2.UIM_MC.D2 )
  );
  X_BUF \outDATA<4>\$WA3.UIM_2029  (
    .I(\outDATA<4>\$WA3.UIM_MC.Q ),
    .O(\outDATA<4>\$WA3.UIM )
  );
  X_BUF \outDATA<4>\$WA3.UIM_MC.Q_2030  (
    .I(\outDATA<4>\$WA3.UIM_MC.D ),
    .O(\outDATA<4>\$WA3.UIM_MC.Q )
  );
  X_XOR2 \outDATA<4>\$WA3.UIM_MC.D_2031  (
    .I0(\outDATA<4>\$WA3.UIM_MC.D1 ),
    .I1(\outDATA<4>\$WA3.UIM_MC.D2 ),
    .O(\outDATA<4>\$WA3.UIM_MC.D )
  );
  X_ZERO \outDATA<4>\$WA3.UIM_MC.D1_2032  (
    .O(\outDATA<4>\$WA3.UIM_MC.D1 )
  );
  X_AND2 \outDATA<4>\$WA3.UIM_MC.D2_PT_0_2033  (
    .I0(NET2528),
    .I1(\U4/Flgreg [4]),
    .O(\outDATA<4>\$WA3.UIM_MC.D2_PT_0 )
  );
  X_AND2 \outDATA<4>\$WA3.UIM_MC.D2_PT_1_2034  (
    .I0(\NlwInverterSignal_outDATA<4>\$WA3.UIM_MC.D2_PT_1/IN0 ),
    .I1(\Home133FLG_II/UIM ),
    .O(\outDATA<4>\$WA3.UIM_MC.D2_PT_1 )
  );
  X_OR2 \outDATA<4>\$WA3.UIM_MC.D2_2035  (
    .I0(\outDATA<4>\$WA3.UIM_MC.D2_PT_0 ),
    .I1(\outDATA<4>\$WA3.UIM_MC.D2_PT_1 ),
    .O(\outDATA<4>\$WA3.UIM_MC.D2 )
  );
  X_BUF \outDATA<4>\$WA4.UIM_2036  (
    .I(\outDATA<4>\$WA4.UIM_MC.Q ),
    .O(\outDATA<4>\$WA4.UIM )
  );
  X_BUF \outDATA<4>\$WA4.UIM_MC.Q_2037  (
    .I(\outDATA<4>\$WA4.UIM_MC.D ),
    .O(\outDATA<4>\$WA4.UIM_MC.Q )
  );
  X_XOR2 \outDATA<4>\$WA4.UIM_MC.D_2038  (
    .I0(\outDATA<4>\$WA4.UIM_MC.D1 ),
    .I1(\outDATA<4>\$WA4.UIM_MC.D2 ),
    .O(\outDATA<4>\$WA4.UIM_MC.D )
  );
  X_AND2 \outDATA<4>\$WA4.UIM_MC.D1_2039  (
    .I0(NET2575),
    .I1(NET2575),
    .O(\outDATA<4>\$WA4.UIM_MC.D1 )
  );
  X_ZERO \outDATA<4>\$WA4.UIM_MC.D2_2040  (
    .O(\outDATA<4>\$WA4.UIM_MC.D2 )
  );
  X_BUF \outDATA<4>\$WA6.UIM_2041  (
    .I(\outDATA<4>\$WA6.UIM_MC.Q ),
    .O(\outDATA<4>\$WA6.UIM )
  );
  X_BUF \outDATA<4>\$WA6.UIM_MC.Q_2042  (
    .I(\outDATA<4>\$WA6.UIM_MC.D ),
    .O(\outDATA<4>\$WA6.UIM_MC.Q )
  );
  X_XOR2 \outDATA<4>\$WA6.UIM_MC.D_2043  (
    .I0(\outDATA<4>\$WA6.UIM_MC.D1 ),
    .I1(\outDATA<4>\$WA6.UIM_MC.D2 ),
    .O(\outDATA<4>\$WA6.UIM_MC.D )
  );
  X_ZERO \outDATA<4>\$WA6.UIM_MC.D1_2044  (
    .O(\outDATA<4>\$WA6.UIM_MC.D1 )
  );
  X_AND2 \outDATA<4>\$WA6.UIM_MC.D2_PT_0_2045  (
    .I0(DCOR0THRESLOWr),
    .I1(\U1/U4/Latch0r [4]),
    .O(\outDATA<4>\$WA6.UIM_MC.D2_PT_0 )
  );
  X_AND3 \outDATA<4>\$WA6.UIM_MC.D2_PT_1_2046  (
    .I0(\NlwInverterSignal_outDATA<4>\$WA6.UIM_MC.D2_PT_1/IN0 ),
    .I1(DCOR0THRESHIGHr),
    .I2(\U1/U4/Latch0r [12]),
    .O(\outDATA<4>\$WA6.UIM_MC.D2_PT_1 )
  );
  X_AND4 \outDATA<4>\$WA6.UIM_MC.D2_PT_2_2047  (
    .I0(\NlwInverterSignal_outDATA<4>\$WA6.UIM_MC.D2_PT_2/IN0 ),
    .I1(\NlwInverterSignal_outDATA<4>\$WA6.UIM_MC.D2_PT_2/IN1 ),
    .I2(DCOR1THRESLOWr),
    .I3(\U1/U4/Latch1r [4]),
    .O(\outDATA<4>\$WA6.UIM_MC.D2_PT_2 )
  );
  X_AND4 \outDATA<4>\$WA6.UIM_MC.D2_PT_3_2048  (
    .I0(\NlwInverterSignal_outDATA<4>\$WA6.UIM_MC.D2_PT_3/IN0 ),
    .I1(\NlwInverterSignal_outDATA<4>\$WA6.UIM_MC.D2_PT_3/IN1 ),
    .I2(\NlwInverterSignal_outDATA<4>\$WA6.UIM_MC.D2_PT_3/IN2 ),
    .I3(\U1/U4/Latch1r [12]),
    .O(\outDATA<4>\$WA6.UIM_MC.D2_PT_3 )
  );
  X_OR4 \outDATA<4>\$WA6.UIM_MC.D2_2049  (
    .I0(\outDATA<4>\$WA6.UIM_MC.D2_PT_0 ),
    .I1(\outDATA<4>\$WA6.UIM_MC.D2_PT_1 ),
    .I2(\outDATA<4>\$WA6.UIM_MC.D2_PT_2 ),
    .I3(\outDATA<4>\$WA6.UIM_MC.D2_PT_3 ),
    .O(\outDATA<4>\$WA6.UIM_MC.D2 )
  );
  X_BUF \U1/U4/Latch0r<4>  (
    .I(\U1/U4/Latch0r<4>_MC.Q ),
    .O(\U1/U4/Latch0r [4])
  );
  X_FF \U1/U4/Latch0r<4>_MC.REG  (
    .I(\U1/U4/Latch0r<4>_MC.D ),
    .CE(Vcc),
    .CLK(\U1/U4/Latch0r<4>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\U1/U4/Latch0r<4>_MC.Q )
  );
  X_INV \U1/U4/Latch0r<4>_MC.REG_tsimcreated_inv_Mclk_II/FCLK_2050  (
    .I(\Mclk_II/FCLK ),
    .O(\U1/U4/Latch0r<4>_MC.REG_tsimcreated_inv_Mclk_II/FCLK )
  );
  X_XOR2 \U1/U4/Latch0r<4>_MC.D_2051  (
    .I0(\U1/U4/Latch0r<4>_MC.D1 ),
    .I1(\U1/U4/Latch0r<4>_MC.D2 ),
    .O(\U1/U4/Latch0r<4>_MC.D )
  );
  X_ZERO \U1/U4/Latch0r<4>_MC.D1_2052  (
    .O(\U1/U4/Latch0r<4>_MC.D1 )
  );
  X_AND3 \U1/U4/Latch0r<4>_MC.D2_PT_0_2053  (
    .I0(\MSPReset_II/UIM ),
    .I1(\U1/Channel0 [4]),
    .I2(N_PZ_963),
    .O(\U1/U4/Latch0r<4>_MC.D2_PT_0 )
  );
  X_AND3 \U1/U4/Latch0r<4>_MC.D2_PT_1_2054  (
    .I0(\MSPReset_II/UIM ),
    .I1(\NlwInverterSignal_U1/U4/Latch0r<4>_MC.D2_PT_1/IN1 ),
    .I2(\U1/U4/Latch0r [4]),
    .O(\U1/U4/Latch0r<4>_MC.D2_PT_1 )
  );
  X_OR2 \U1/U4/Latch0r<4>_MC.D2_2055  (
    .I0(\U1/U4/Latch0r<4>_MC.D2_PT_0 ),
    .I1(\U1/U4/Latch0r<4>_MC.D2_PT_1 ),
    .O(\U1/U4/Latch0r<4>_MC.D2 )
  );
  X_BUF \U1/U4/Latch0r<12>  (
    .I(\U1/U4/Latch0r<12>_MC.Q ),
    .O(\U1/U4/Latch0r [12])
  );
  X_FF \U1/U4/Latch0r<12>_MC.REG  (
    .I(\U1/U4/Latch0r<12>_MC.D ),
    .CE(Vcc),
    .CLK(\U1/U4/Latch0r<12>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\U1/U4/Latch0r<12>_MC.Q )
  );
  X_INV \U1/U4/Latch0r<12>_MC.REG_tsimcreated_inv_Mclk_II/FCLK_2056  (
    .I(\Mclk_II/FCLK ),
    .O(\U1/U4/Latch0r<12>_MC.REG_tsimcreated_inv_Mclk_II/FCLK )
  );
  X_XOR2 \U1/U4/Latch0r<12>_MC.D_2057  (
    .I0(\U1/U4/Latch0r<12>_MC.D1 ),
    .I1(\U1/U4/Latch0r<12>_MC.D2 ),
    .O(\U1/U4/Latch0r<12>_MC.D )
  );
  X_ZERO \U1/U4/Latch0r<12>_MC.D1_2058  (
    .O(\U1/U4/Latch0r<12>_MC.D1 )
  );
  X_AND3 \U1/U4/Latch0r<12>_MC.D2_PT_0_2059  (
    .I0(\MSPReset_II/UIM ),
    .I1(\U1/Channel0 [12]),
    .I2(N_PZ_963),
    .O(\U1/U4/Latch0r<12>_MC.D2_PT_0 )
  );
  X_AND3 \U1/U4/Latch0r<12>_MC.D2_PT_1_2060  (
    .I0(\MSPReset_II/UIM ),
    .I1(\NlwInverterSignal_U1/U4/Latch0r<12>_MC.D2_PT_1/IN1 ),
    .I2(\U1/U4/Latch0r [12]),
    .O(\U1/U4/Latch0r<12>_MC.D2_PT_1 )
  );
  X_OR2 \U1/U4/Latch0r<12>_MC.D2_2061  (
    .I0(\U1/U4/Latch0r<12>_MC.D2_PT_0 ),
    .I1(\U1/U4/Latch0r<12>_MC.D2_PT_1 ),
    .O(\U1/U4/Latch0r<12>_MC.D2 )
  );
  X_BUF \U1/U4/Latch1r<4>  (
    .I(\U1/U4/Latch1r<4>_MC.Q ),
    .O(\U1/U4/Latch1r [4])
  );
  X_FF \U1/U4/Latch1r<4>_MC.REG  (
    .I(\U1/U4/Latch1r<4>_MC.D ),
    .CE(Vcc),
    .CLK(\U1/U4/Latch1r<4>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\U1/U4/Latch1r<4>_MC.Q )
  );
  X_INV \U1/U4/Latch1r<4>_MC.REG_tsimcreated_inv_Mclk_II/FCLK_2062  (
    .I(\Mclk_II/FCLK ),
    .O(\U1/U4/Latch1r<4>_MC.REG_tsimcreated_inv_Mclk_II/FCLK )
  );
  X_XOR2 \U1/U4/Latch1r<4>_MC.D_2063  (
    .I0(\U1/U4/Latch1r<4>_MC.D1 ),
    .I1(\U1/U4/Latch1r<4>_MC.D2 ),
    .O(\U1/U4/Latch1r<4>_MC.D )
  );
  X_ZERO \U1/U4/Latch1r<4>_MC.D1_2064  (
    .O(\U1/U4/Latch1r<4>_MC.D1 )
  );
  X_AND3 \U1/U4/Latch1r<4>_MC.D2_PT_0_2065  (
    .I0(\MSPReset_II/UIM ),
    .I1(\U1/Channel1 [4]),
    .I2(N_PZ_962),
    .O(\U1/U4/Latch1r<4>_MC.D2_PT_0 )
  );
  X_AND3 \U1/U4/Latch1r<4>_MC.D2_PT_1_2066  (
    .I0(\MSPReset_II/UIM ),
    .I1(\NlwInverterSignal_U1/U4/Latch1r<4>_MC.D2_PT_1/IN1 ),
    .I2(\U1/U4/Latch1r [4]),
    .O(\U1/U4/Latch1r<4>_MC.D2_PT_1 )
  );
  X_OR2 \U1/U4/Latch1r<4>_MC.D2_2067  (
    .I0(\U1/U4/Latch1r<4>_MC.D2_PT_0 ),
    .I1(\U1/U4/Latch1r<4>_MC.D2_PT_1 ),
    .O(\U1/U4/Latch1r<4>_MC.D2 )
  );
  X_BUF \U1/U4/Latch1r<12>  (
    .I(\U1/U4/Latch1r<12>_MC.Q ),
    .O(\U1/U4/Latch1r [12])
  );
  X_FF \U1/U4/Latch1r<12>_MC.REG  (
    .I(\U1/U4/Latch1r<12>_MC.D ),
    .CE(Vcc),
    .CLK(\U1/U4/Latch1r<12>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\U1/U4/Latch1r<12>_MC.Q )
  );
  X_INV \U1/U4/Latch1r<12>_MC.REG_tsimcreated_inv_Mclk_II/FCLK_2068  (
    .I(\Mclk_II/FCLK ),
    .O(\U1/U4/Latch1r<12>_MC.REG_tsimcreated_inv_Mclk_II/FCLK )
  );
  X_XOR2 \U1/U4/Latch1r<12>_MC.D_2069  (
    .I0(\U1/U4/Latch1r<12>_MC.D1 ),
    .I1(\U1/U4/Latch1r<12>_MC.D2 ),
    .O(\U1/U4/Latch1r<12>_MC.D )
  );
  X_ZERO \U1/U4/Latch1r<12>_MC.D1_2070  (
    .O(\U1/U4/Latch1r<12>_MC.D1 )
  );
  X_AND3 \U1/U4/Latch1r<12>_MC.D2_PT_0_2071  (
    .I0(\MSPReset_II/UIM ),
    .I1(\U1/Channel1 [12]),
    .I2(N_PZ_962),
    .O(\U1/U4/Latch1r<12>_MC.D2_PT_0 )
  );
  X_AND3 \U1/U4/Latch1r<12>_MC.D2_PT_1_2072  (
    .I0(\MSPReset_II/UIM ),
    .I1(\NlwInverterSignal_U1/U4/Latch1r<12>_MC.D2_PT_1/IN1 ),
    .I2(\U1/U4/Latch1r [12]),
    .O(\U1/U4/Latch1r<12>_MC.D2_PT_1 )
  );
  X_OR2 \U1/U4/Latch1r<12>_MC.D2_2073  (
    .I0(\U1/U4/Latch1r<12>_MC.D2_PT_0 ),
    .I1(\U1/U4/Latch1r<12>_MC.D2_PT_1 ),
    .O(\U1/U4/Latch1r<12>_MC.D2 )
  );
  X_BUF \outDATA<4>\$WA5.UIM_2074  (
    .I(\outDATA<4>\$WA5.UIM_MC.Q ),
    .O(\outDATA<4>\$WA5.UIM )
  );
  X_BUF \outDATA<4>\$WA5.UIM_MC.Q_2075  (
    .I(\outDATA<4>\$WA5.UIM_MC.D ),
    .O(\outDATA<4>\$WA5.UIM_MC.Q )
  );
  X_XOR2 \outDATA<4>\$WA5.UIM_MC.D_2076  (
    .I0(\outDATA<4>\$WA5.UIM_MC.D1 ),
    .I1(\outDATA<4>\$WA5.UIM_MC.D2 ),
    .O(\outDATA<4>\$WA5.UIM_MC.D )
  );
  X_ZERO \outDATA<4>\$WA5.UIM_MC.D1_2077  (
    .O(\outDATA<4>\$WA5.UIM_MC.D1 )
  );
  X_AND2 \outDATA<4>\$WA5.UIM_MC.D2_PT_0_2078  (
    .I0(DCOR0CNTLOWr),
    .I1(\U1/U3/holdingreg0 [4]),
    .O(\outDATA<4>\$WA5.UIM_MC.D2_PT_0 )
  );
  X_AND3 \outDATA<4>\$WA5.UIM_MC.D2_PT_1_2079  (
    .I0(\NlwInverterSignal_outDATA<4>\$WA5.UIM_MC.D2_PT_1/IN0 ),
    .I1(DCOR1CNTLOWr),
    .I2(\U1/U3/holdingreg1 [4]),
    .O(\outDATA<4>\$WA5.UIM_MC.D2_PT_1 )
  );
  X_AND4 \outDATA<4>\$WA5.UIM_MC.D2_PT_2_2080  (
    .I0(\NlwInverterSignal_outDATA<4>\$WA5.UIM_MC.D2_PT_2/IN0 ),
    .I1(\NlwInverterSignal_outDATA<4>\$WA5.UIM_MC.D2_PT_2/IN1 ),
    .I2(DCOR0CNTHIGHr),
    .I3(\U1/U3/holdingreg0 [12]),
    .O(\outDATA<4>\$WA5.UIM_MC.D2_PT_2 )
  );
  X_AND4 \outDATA<4>\$WA5.UIM_MC.D2_PT_3_2081  (
    .I0(\NlwInverterSignal_outDATA<4>\$WA5.UIM_MC.D2_PT_3/IN0 ),
    .I1(\NlwInverterSignal_outDATA<4>\$WA5.UIM_MC.D2_PT_3/IN1 ),
    .I2(\NlwInverterSignal_outDATA<4>\$WA5.UIM_MC.D2_PT_3/IN2 ),
    .I3(\U1/U3/holdingreg1 [12]),
    .O(\outDATA<4>\$WA5.UIM_MC.D2_PT_3 )
  );
  X_OR4 \outDATA<4>\$WA5.UIM_MC.D2_2082  (
    .I0(\outDATA<4>\$WA5.UIM_MC.D2_PT_0 ),
    .I1(\outDATA<4>\$WA5.UIM_MC.D2_PT_1 ),
    .I2(\outDATA<4>\$WA5.UIM_MC.D2_PT_2 ),
    .I3(\outDATA<4>\$WA5.UIM_MC.D2_PT_3 ),
    .O(\outDATA<4>\$WA5.UIM_MC.D2 )
  );
  X_BUF \U1/U3/holdingreg0<4>  (
    .I(\U1/U3/holdingreg0<4>_MC.Q ),
    .O(\U1/U3/holdingreg0 [4])
  );
  X_FF \U1/U3/holdingreg0<4>_MC.REG  (
    .I(\U1/U3/holdingreg0<4>_MC.D ),
    .CE(Vcc),
    .CLK(\U1/U3/holdingreg0<4>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\U1/U3/holdingreg0<4>_MC.Q )
  );
  X_INV \U1/U3/holdingreg0<4>_MC.REG_tsimcreated_inv_Mclk_II/FCLK_2083  (
    .I(\Mclk_II/FCLK ),
    .O(\U1/U3/holdingreg0<4>_MC.REG_tsimcreated_inv_Mclk_II/FCLK )
  );
  X_XOR2 \U1/U3/holdingreg0<4>_MC.D_2084  (
    .I0(\U1/U3/holdingreg0<4>_MC.D1 ),
    .I1(\U1/U3/holdingreg0<4>_MC.D2 ),
    .O(\U1/U3/holdingreg0<4>_MC.D )
  );
  X_ZERO \U1/U3/holdingreg0<4>_MC.D1_2085  (
    .O(\U1/U3/holdingreg0<4>_MC.D1 )
  );
  X_AND2 \U1/U3/holdingreg0<4>_MC.D2_PT_0_2086  (
    .I0(N_PZ_938),
    .I1(\U1/U3/holdingreg0 [4]),
    .O(\U1/U3/holdingreg0<4>_MC.D2_PT_0 )
  );
  X_AND4 \U1/U3/holdingreg0<4>_MC.D2_PT_1_2087  (
    .I0(\MSPReset_II/UIM ),
    .I1(\NlwInverterSignal_U1/U3/holdingreg0<4>_MC.D2_PT_1/IN1 ),
    .I2(U2_ASedge),
    .I3(\U1/Channel0 [4]),
    .O(\U1/U3/holdingreg0<4>_MC.D2_PT_1 )
  );
  X_OR2 \U1/U3/holdingreg0<4>_MC.D2_2088  (
    .I0(\U1/U3/holdingreg0<4>_MC.D2_PT_0 ),
    .I1(\U1/U3/holdingreg0<4>_MC.D2_PT_1 ),
    .O(\U1/U3/holdingreg0<4>_MC.D2 )
  );
  X_BUF \U1/U3/holdingreg1<4>  (
    .I(\U1/U3/holdingreg1<4>_MC.Q ),
    .O(\U1/U3/holdingreg1 [4])
  );
  X_FF \U1/U3/holdingreg1<4>_MC.REG  (
    .I(\U1/U3/holdingreg1<4>_MC.D ),
    .CE(Vcc),
    .CLK(\U1/U3/holdingreg1<4>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\U1/U3/holdingreg1<4>_MC.Q )
  );
  X_INV \U1/U3/holdingreg1<4>_MC.REG_tsimcreated_inv_Mclk_II/FCLK_2089  (
    .I(\Mclk_II/FCLK ),
    .O(\U1/U3/holdingreg1<4>_MC.REG_tsimcreated_inv_Mclk_II/FCLK )
  );
  X_XOR2 \U1/U3/holdingreg1<4>_MC.D_2090  (
    .I0(\U1/U3/holdingreg1<4>_MC.D1 ),
    .I1(\U1/U3/holdingreg1<4>_MC.D2 ),
    .O(\U1/U3/holdingreg1<4>_MC.D )
  );
  X_ZERO \U1/U3/holdingreg1<4>_MC.D1_2091  (
    .O(\U1/U3/holdingreg1<4>_MC.D1 )
  );
  X_AND2 \U1/U3/holdingreg1<4>_MC.D2_PT_0_2092  (
    .I0(N_PZ_938),
    .I1(\U1/U3/holdingreg1 [4]),
    .O(\U1/U3/holdingreg1<4>_MC.D2_PT_0 )
  );
  X_AND4 \U1/U3/holdingreg1<4>_MC.D2_PT_1_2093  (
    .I0(\MSPReset_II/UIM ),
    .I1(\NlwInverterSignal_U1/U3/holdingreg1<4>_MC.D2_PT_1/IN1 ),
    .I2(U2_ASedge),
    .I3(\U1/Channel1 [4]),
    .O(\U1/U3/holdingreg1<4>_MC.D2_PT_1 )
  );
  X_OR2 \U1/U3/holdingreg1<4>_MC.D2_2094  (
    .I0(\U1/U3/holdingreg1<4>_MC.D2_PT_0 ),
    .I1(\U1/U3/holdingreg1<4>_MC.D2_PT_1 ),
    .O(\U1/U3/holdingreg1<4>_MC.D2 )
  );
  X_BUF \U1/U3/holdingreg0<12>  (
    .I(\U1/U3/holdingreg0<12>_MC.Q ),
    .O(\U1/U3/holdingreg0 [12])
  );
  X_FF \U1/U3/holdingreg0<12>_MC.REG  (
    .I(\U1/U3/holdingreg0<12>_MC.D ),
    .CE(Vcc),
    .CLK(\U1/U3/holdingreg0<12>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\U1/U3/holdingreg0<12>_MC.Q )
  );
  X_INV \U1/U3/holdingreg0<12>_MC.REG_tsimcreated_inv_Mclk_II/FCLK_2095  (
    .I(\Mclk_II/FCLK ),
    .O(\U1/U3/holdingreg0<12>_MC.REG_tsimcreated_inv_Mclk_II/FCLK )
  );
  X_XOR2 \U1/U3/holdingreg0<12>_MC.D_2096  (
    .I0(\U1/U3/holdingreg0<12>_MC.D1 ),
    .I1(\U1/U3/holdingreg0<12>_MC.D2 ),
    .O(\U1/U3/holdingreg0<12>_MC.D )
  );
  X_ZERO \U1/U3/holdingreg0<12>_MC.D1_2097  (
    .O(\U1/U3/holdingreg0<12>_MC.D1 )
  );
  X_AND2 \U1/U3/holdingreg0<12>_MC.D2_PT_0_2098  (
    .I0(N_PZ_938),
    .I1(\U1/U3/holdingreg0 [12]),
    .O(\U1/U3/holdingreg0<12>_MC.D2_PT_0 )
  );
  X_AND4 \U1/U3/holdingreg0<12>_MC.D2_PT_1_2099  (
    .I0(\MSPReset_II/UIM ),
    .I1(\NlwInverterSignal_U1/U3/holdingreg0<12>_MC.D2_PT_1/IN1 ),
    .I2(U2_ASedge),
    .I3(\U1/Channel0 [12]),
    .O(\U1/U3/holdingreg0<12>_MC.D2_PT_1 )
  );
  X_OR2 \U1/U3/holdingreg0<12>_MC.D2_2100  (
    .I0(\U1/U3/holdingreg0<12>_MC.D2_PT_0 ),
    .I1(\U1/U3/holdingreg0<12>_MC.D2_PT_1 ),
    .O(\U1/U3/holdingreg0<12>_MC.D2 )
  );
  X_BUF \U1/U3/holdingreg1<12>  (
    .I(\U1/U3/holdingreg1<12>_MC.Q ),
    .O(\U1/U3/holdingreg1 [12])
  );
  X_FF \U1/U3/holdingreg1<12>_MC.REG  (
    .I(\U1/U3/holdingreg1<12>_MC.D ),
    .CE(Vcc),
    .CLK(\U1/U3/holdingreg1<12>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\U1/U3/holdingreg1<12>_MC.Q )
  );
  X_INV \U1/U3/holdingreg1<12>_MC.REG_tsimcreated_inv_Mclk_II/FCLK_2101  (
    .I(\Mclk_II/FCLK ),
    .O(\U1/U3/holdingreg1<12>_MC.REG_tsimcreated_inv_Mclk_II/FCLK )
  );
  X_XOR2 \U1/U3/holdingreg1<12>_MC.D_2102  (
    .I0(\U1/U3/holdingreg1<12>_MC.D1 ),
    .I1(\U1/U3/holdingreg1<12>_MC.D2 ),
    .O(\U1/U3/holdingreg1<12>_MC.D )
  );
  X_ZERO \U1/U3/holdingreg1<12>_MC.D1_2103  (
    .O(\U1/U3/holdingreg1<12>_MC.D1 )
  );
  X_AND2 \U1/U3/holdingreg1<12>_MC.D2_PT_0_2104  (
    .I0(N_PZ_938),
    .I1(\U1/U3/holdingreg1 [12]),
    .O(\U1/U3/holdingreg1<12>_MC.D2_PT_0 )
  );
  X_AND4 \U1/U3/holdingreg1<12>_MC.D2_PT_1_2105  (
    .I0(\MSPReset_II/UIM ),
    .I1(\NlwInverterSignal_U1/U3/holdingreg1<12>_MC.D2_PT_1/IN1 ),
    .I2(U2_ASedge),
    .I3(\U1/Channel1 [12]),
    .O(\U1/U3/holdingreg1<12>_MC.D2_PT_1 )
  );
  X_OR2 \U1/U3/holdingreg1<12>_MC.D2_2106  (
    .I0(\U1/U3/holdingreg1<12>_MC.D2_PT_0 ),
    .I1(\U1/U3/holdingreg1<12>_MC.D2_PT_1 ),
    .O(\U1/U3/holdingreg1<12>_MC.D2 )
  );
  X_AND2 \FOOBAR1__ctinst/4_2107  (
    .I0(DCOROUTw),
    .I1(DCOROUTw),
    .O(\FOOBAR1__ctinst/4 )
  );
  X_AND2 \FOOBAR1__ctinst/7_2108  (
    .I0(U2_Enable_AD),
    .I1(U2_Enable_AD),
    .O(\FOOBAR1__ctinst/7 )
  );
  X_AND2 \FOOBAR2__ctinst/7_2109  (
    .I0(\MSPReset_II/UIM ),
    .I1(\MSPReset_II/UIM ),
    .O(\NlwInverterSignal_FOOBAR2__ctinst/7/OUT )
  );
  X_AND2 \FOOBAR3__ctinst/7_2110  (
    .I0(\MSPReset_II/UIM ),
    .I1(\MSPReset_II/UIM ),
    .O(\NlwInverterSignal_FOOBAR3__ctinst/7/OUT )
  );
  X_AND2 \FOOBAR4__ctinst/0_2111  (
    .I0(\TP12_MC.UIM ),
    .I1(\TP12_MC.UIM ),
    .O(\FOOBAR4__ctinst/0 )
  );
  X_AND2 \FOOBAR5__ctinst/4_2112  (
    .I0(U2_WRRDedge),
    .I1(\NlwInverterSignal_FOOBAR5__ctinst/4/IN1 ),
    .O(\FOOBAR5__ctinst/4 )
  );
  X_AND2 \FOOBAR7__ctinst/4_2113  (
    .I0(DCOROUTw),
    .I1(DCOROUTw),
    .O(\FOOBAR7__ctinst/4 )
  );
  X_AND2 \FOOBAR8__ctinst/4_2114  (
    .I0(DCOROUTw),
    .I1(DCOROUTw),
    .O(\FOOBAR8__ctinst/4 )
  );
  X_AND2 \FOOBAR9__ctinst/4_2115  (
    .I0(DCORENCPWRw),
    .I1(DCORENCPWRw),
    .O(\FOOBAR9__ctinst/4 )
  );
  X_AND2 \FOOBAR10__ctinst/4_2116  (
    .I0(DCORENCPWRw),
    .I1(DCORENCPWRw),
    .O(\FOOBAR10__ctinst/4 )
  );
  X_AND2 \FOOBAR12__ctinst/4_2117  (
    .I0(DCORENCPWRw),
    .I1(DCORENCPWRw),
    .O(\FOOBAR12__ctinst/4 )
  );
  X_AND2 \FOOBAR14__ctinst/4_2118  (
    .I0(DCORENCPWRw),
    .I1(DCORENCPWRw),
    .O(\FOOBAR14__ctinst/4 )
  );
  X_AND2 \FOOBAR15__ctinst/4_2119  (
    .I0(DCOROUTw),
    .I1(DCOROUTw),
    .O(\FOOBAR15__ctinst/4 )
  );
  X_AND2 \FOOBAR18__ctinst/4_2120  (
    .I0(DCOROUTw),
    .I1(DCOROUTw),
    .O(\FOOBAR18__ctinst/4 )
  );
  X_AND2 \FOOBAR19__ctinst/4_2121  (
    .I0(DCORSENSORw),
    .I1(DCORSENSORw),
    .O(\FOOBAR19__ctinst/4 )
  );
  X_AND2 \FOOBAR21__ctinst/4_2122  (
    .I0(\NlwInverterSignal_FOOBAR21__ctinst/4/IN0 ),
    .I1(\NlwInverterSignal_FOOBAR21__ctinst/4/IN1 ),
    .O(\FOOBAR21__ctinst/4 )
  );
  X_AND2 \FOOBAR23__ctinst/4_2123  (
    .I0(DCORENCPWRw),
    .I1(DCORENCPWRw),
    .O(\FOOBAR23__ctinst/4 )
  );
  X_AND2 \FOOBAR24__ctinst/4_2124  (
    .I0(\NlwInverterSignal_FOOBAR24__ctinst/4/IN0 ),
    .I1(\NlwInverterSignal_FOOBAR24__ctinst/4/IN1 ),
    .O(\FOOBAR24__ctinst/4 )
  );
  X_INV \NlwInverterBlock_AD<5>_MC.D/IN0  (
    .I(\AD<5>_MC.D1 ),
    .O(\NlwInverterSignal_AD<5>_MC.D/IN0 )
  );
  X_INV \NlwInverterBlock_AD<5>_MC.D2_PT_0/IN1  (
    .I(\outDATA<5>\$WA0.UIM ),
    .O(\NlwInverterSignal_AD<5>_MC.D2_PT_0/IN1 )
  );
  X_INV \NlwInverterBlock_AD<5>_MC.D2_PT_1/IN1  (
    .I(\outDATA<5>\$WA1.UIM ),
    .O(\NlwInverterSignal_AD<5>_MC.D2_PT_1/IN1 )
  );
  X_INV \NlwInverterBlock_AD<5>_MC.D2_PT_2/IN1  (
    .I(\outDATA<5>\$WA2.UIM ),
    .O(\NlwInverterSignal_AD<5>_MC.D2_PT_2/IN1 )
  );
  X_INV \NlwInverterBlock_AD<5>_MC.D2_PT_3/IN1  (
    .I(\outDATA<5>\$WA3.UIM ),
    .O(\NlwInverterSignal_AD<5>_MC.D2_PT_3/IN1 )
  );
  X_INV \NlwInverterBlock_AD<5>_MC.D2_PT_4/IN0  (
    .I(\outDATA<5>\$WA5.UIM ),
    .O(\NlwInverterSignal_AD<5>_MC.D2_PT_4/IN0 )
  );
  X_INV \NlwInverterBlock_AD<5>_MC.D2_PT_4/IN1  (
    .I(N_PZ_961),
    .O(\NlwInverterSignal_AD<5>_MC.D2_PT_4/IN1 )
  );
  X_INV \NlwInverterBlock_AD<5>_MC.D2_PT_5/IN0  (
    .I(\outDATA<5>\$WA6.UIM ),
    .O(\NlwInverterSignal_AD<5>_MC.D2_PT_5/IN0 )
  );
  X_INV \NlwInverterBlock_AD<5>_MC.D2_PT_5/IN1  (
    .I(N_PZ_987),
    .O(\NlwInverterSignal_AD<5>_MC.D2_PT_5/IN1 )
  );
  X_INV \NlwInverterBlock_DCORI2CCNTr_MC.D1/IN1  (
    .I(\RD_II/UIM ),
    .O(\NlwInverterSignal_DCORI2CCNTr_MC.D1/IN1 )
  );
  X_INV \NlwInverterBlock_DCORI2CCNTr_MC.D1/IN2  (
    .I(U2_ADDR_reg[0]),
    .O(\NlwInverterSignal_DCORI2CCNTr_MC.D1/IN2 )
  );
  X_INV \NlwInverterBlock_DCORI2CCNTr_MC.D1/IN3  (
    .I(U2_ADDR_reg[4]),
    .O(\NlwInverterSignal_DCORI2CCNTr_MC.D1/IN3 )
  );
  X_INV \NlwInverterBlock_DCORI2CCNTr_MC.D1/IN4  (
    .I(U2_ADDR_reg[5]),
    .O(\NlwInverterSignal_DCORI2CCNTr_MC.D1/IN4 )
  );
  X_INV \NlwInverterBlock_DCORI2CCNTr_MC.D1/IN5  (
    .I(U2_ADDR_reg[6]),
    .O(\NlwInverterSignal_DCORI2CCNTr_MC.D1/IN5 )
  );
  X_INV \NlwInverterBlock_DCORI2CCNTr_MC.D1/IN6  (
    .I(U2_ADDR_reg[7]),
    .O(\NlwInverterSignal_DCORI2CCNTr_MC.D1/IN6 )
  );
  X_INV \NlwInverterBlock_DCORI2CCNTr_MC.D1/IN7  (
    .I(U2_ADDR_reg[3]),
    .O(\NlwInverterSignal_DCORI2CCNTr_MC.D1/IN7 )
  );
  X_INV \NlwInverterBlock_DCORI2CCNTr_MC.D1/IN8  (
    .I(U2_ADDR_reg[1]),
    .O(\NlwInverterSignal_DCORI2CCNTr_MC.D1/IN8 )
  );
  X_INV \NlwInverterBlock_DCORI2CCNTr_MC.D1/IN9  (
    .I(U2_ADDR_reg[2]),
    .O(\NlwInverterSignal_DCORI2CCNTr_MC.D1/IN9 )
  );
  X_INV \NlwInverterBlock_U2_ADDR_reg<0>_MC.D2_PT_0/IN1  (
    .I(\MSPReset_II/UIM ),
    .O(\NlwInverterSignal_U2_ADDR_reg<0>_MC.D2_PT_0/IN1 )
  );
  X_INV \NlwInverterBlock_U2_ADDR_reg<0>_MC.D2_PT_1/IN3  (
    .I(\AD<0>_II/UIM ),
    .O(\NlwInverterSignal_U2_ADDR_reg<0>_MC.D2_PT_1/IN3 )
  );
  X_INV \NlwInverterBlock_U2_ADDR_reg<0>_MC.D2_PT_1/IN4  (
    .I(\AS_II/UIM ),
    .O(\NlwInverterSignal_U2_ADDR_reg<0>_MC.D2_PT_1/IN4 )
  );
  X_INV \NlwInverterBlock_U2_ADDR_reg<0>_MC.D2_PT_2/IN2  (
    .I(U2_ADDR_reg[0]),
    .O(\NlwInverterSignal_U2_ADDR_reg<0>_MC.D2_PT_2/IN2 )
  );
  X_INV \NlwInverterBlock_U2_ADDR_reg<0>_MC.D2_PT_2/IN5  (
    .I(\AS_II/UIM ),
    .O(\NlwInverterSignal_U2_ADDR_reg<0>_MC.D2_PT_2/IN5 )
  );
  X_INV \NlwInverterBlock_U2_ADDR_reg<0>_MC.D2_PT_3/IN2  (
    .I(U2_ADDR_reg[4]),
    .O(\NlwInverterSignal_U2_ADDR_reg<0>_MC.D2_PT_3/IN2 )
  );
  X_INV \NlwInverterBlock_U2_ADDR_reg<0>_MC.D2_PT_3/IN3  (
    .I(U2_ADDR_reg[5]),
    .O(\NlwInverterSignal_U2_ADDR_reg<0>_MC.D2_PT_3/IN3 )
  );
  X_INV \NlwInverterBlock_U2_ADDR_reg<0>_MC.D2_PT_3/IN4  (
    .I(U2_ADDR_reg[6]),
    .O(\NlwInverterSignal_U2_ADDR_reg<0>_MC.D2_PT_3/IN4 )
  );
  X_INV \NlwInverterBlock_U2_ADDR_reg<0>_MC.D2_PT_3/IN5  (
    .I(U2_ADDR_reg[7]),
    .O(\NlwInverterSignal_U2_ADDR_reg<0>_MC.D2_PT_3/IN5 )
  );
  X_INV \NlwInverterBlock_U2_ADDR_reg<0>_MC.D2_PT_3/IN7  (
    .I(U2_WRRDedge),
    .O(\NlwInverterSignal_U2_ADDR_reg<0>_MC.D2_PT_3/IN7 )
  );
  X_INV \NlwInverterBlock_U2_ADDR_reg<4>_MC.D2_PT_0/IN1  (
    .I(\MSPReset_II/UIM ),
    .O(\NlwInverterSignal_U2_ADDR_reg<4>_MC.D2_PT_0/IN1 )
  );
  X_INV \NlwInverterBlock_U2_ADDR_reg<4>_MC.D2_PT_1/IN3  (
    .I(\AS_II/UIM ),
    .O(\NlwInverterSignal_U2_ADDR_reg<4>_MC.D2_PT_1/IN3 )
  );
  X_INV \NlwInverterBlock_U2_ADDR_reg<4>_MC.D2_PT_1/IN5  (
    .I(\AD<4>_II/UIM ),
    .O(\NlwInverterSignal_U2_ADDR_reg<4>_MC.D2_PT_1/IN5 )
  );
  X_INV \NlwInverterBlock_U2_ADDR_reg<4>_MC.D2_PT_2/IN2  (
    .I(U2_ADDR_reg[4]),
    .O(\NlwInverterSignal_U2_ADDR_reg<4>_MC.D2_PT_2/IN2 )
  );
  X_INV \NlwInverterBlock_U2_ADDR_reg<4>_MC.D2_PT_2/IN4  (
    .I(\AS_II/UIM ),
    .O(\NlwInverterSignal_U2_ADDR_reg<4>_MC.D2_PT_2/IN4 )
  );
  X_INV \NlwInverterBlock_U2_ADDR_reg<5>_MC.D2_PT_0/IN1  (
    .I(\MSPReset_II/UIM ),
    .O(\NlwInverterSignal_U2_ADDR_reg<5>_MC.D2_PT_0/IN1 )
  );
  X_INV \NlwInverterBlock_U2_ADDR_reg<5>_MC.D2_PT_1/IN3  (
    .I(\AS_II/UIM ),
    .O(\NlwInverterSignal_U2_ADDR_reg<5>_MC.D2_PT_1/IN3 )
  );
  X_INV \NlwInverterBlock_U2_ADDR_reg<5>_MC.D2_PT_1/IN5  (
    .I(\AD<5>_II/UIM ),
    .O(\NlwInverterSignal_U2_ADDR_reg<5>_MC.D2_PT_1/IN5 )
  );
  X_INV \NlwInverterBlock_U2_ADDR_reg<5>_MC.D2_PT_2/IN2  (
    .I(U2_ADDR_reg[5]),
    .O(\NlwInverterSignal_U2_ADDR_reg<5>_MC.D2_PT_2/IN2 )
  );
  X_INV \NlwInverterBlock_U2_ADDR_reg<5>_MC.D2_PT_2/IN4  (
    .I(\AS_II/UIM ),
    .O(\NlwInverterSignal_U2_ADDR_reg<5>_MC.D2_PT_2/IN4 )
  );
  X_INV \NlwInverterBlock_U2_ADDR_reg<6>_MC.D2_PT_0/IN1  (
    .I(\MSPReset_II/UIM ),
    .O(\NlwInverterSignal_U2_ADDR_reg<6>_MC.D2_PT_0/IN1 )
  );
  X_INV \NlwInverterBlock_U2_ADDR_reg<6>_MC.D2_PT_1/IN3  (
    .I(\AS_II/UIM ),
    .O(\NlwInverterSignal_U2_ADDR_reg<6>_MC.D2_PT_1/IN3 )
  );
  X_INV \NlwInverterBlock_U2_ADDR_reg<6>_MC.D2_PT_1/IN5  (
    .I(\AD<6>_II/UIM ),
    .O(\NlwInverterSignal_U2_ADDR_reg<6>_MC.D2_PT_1/IN5 )
  );
  X_INV \NlwInverterBlock_U2_ADDR_reg<6>_MC.D2_PT_2/IN2  (
    .I(U2_ADDR_reg[6]),
    .O(\NlwInverterSignal_U2_ADDR_reg<6>_MC.D2_PT_2/IN2 )
  );
  X_INV \NlwInverterBlock_U2_ADDR_reg<6>_MC.D2_PT_2/IN4  (
    .I(\AS_II/UIM ),
    .O(\NlwInverterSignal_U2_ADDR_reg<6>_MC.D2_PT_2/IN4 )
  );
  X_INV \NlwInverterBlock_U2_ADDR_reg<7>_MC.D2_PT_0/IN1  (
    .I(\MSPReset_II/UIM ),
    .O(\NlwInverterSignal_U2_ADDR_reg<7>_MC.D2_PT_0/IN1 )
  );
  X_INV \NlwInverterBlock_U2_ADDR_reg<7>_MC.D2_PT_1/IN3  (
    .I(\AS_II/UIM ),
    .O(\NlwInverterSignal_U2_ADDR_reg<7>_MC.D2_PT_1/IN3 )
  );
  X_INV \NlwInverterBlock_U2_ADDR_reg<7>_MC.D2_PT_1/IN5  (
    .I(\AD<7>_II/UIM ),
    .O(\NlwInverterSignal_U2_ADDR_reg<7>_MC.D2_PT_1/IN5 )
  );
  X_INV \NlwInverterBlock_U2_ADDR_reg<7>_MC.D2_PT_2/IN2  (
    .I(U2_ADDR_reg[7]),
    .O(\NlwInverterSignal_U2_ADDR_reg<7>_MC.D2_PT_2/IN2 )
  );
  X_INV \NlwInverterBlock_U2_ADDR_reg<7>_MC.D2_PT_2/IN4  (
    .I(\AS_II/UIM ),
    .O(\NlwInverterSignal_U2_ADDR_reg<7>_MC.D2_PT_2/IN4 )
  );
  X_INV \NlwInverterBlock_U2_AutoInc_MC.D/IN0  (
    .I(\U2_AutoInc_MC.D1 ),
    .O(\NlwInverterSignal_U2_AutoInc_MC.D/IN0 )
  );
  X_INV \NlwInverterBlock_N_PZ_938_MC.D2_PT_1/IN1  (
    .I(U2_ASedge),
    .O(\NlwInverterSignal_N_PZ_938_MC.D2_PT_1/IN1 )
  );
  X_INV \NlwInverterBlock_U2_ADDR_reg<3>_MC.D2_PT_0/IN1  (
    .I(\MSPReset_II/UIM ),
    .O(\NlwInverterSignal_U2_ADDR_reg<3>_MC.D2_PT_0/IN1 )
  );
  X_INV \NlwInverterBlock_U2_ADDR_reg<3>_MC.D2_PT_1/IN3  (
    .I(\AS_II/UIM ),
    .O(\NlwInverterSignal_U2_ADDR_reg<3>_MC.D2_PT_1/IN3 )
  );
  X_INV \NlwInverterBlock_U2_ADDR_reg<3>_MC.D2_PT_1/IN5  (
    .I(\AD<3>_II/UIM ),
    .O(\NlwInverterSignal_U2_ADDR_reg<3>_MC.D2_PT_1/IN5 )
  );
  X_INV \NlwInverterBlock_U2_ADDR_reg<3>_MC.D2_PT_2/IN2  (
    .I(U2_ADDR_reg[3]),
    .O(\NlwInverterSignal_U2_ADDR_reg<3>_MC.D2_PT_2/IN2 )
  );
  X_INV \NlwInverterBlock_U2_ADDR_reg<3>_MC.D2_PT_2/IN4  (
    .I(\AS_II/UIM ),
    .O(\NlwInverterSignal_U2_ADDR_reg<3>_MC.D2_PT_2/IN4 )
  );
  X_INV \NlwInverterBlock_U2_ADDR_reg<3>_MC.D2_PT_3/IN3  (
    .I(U2_ADDR_reg[4]),
    .O(\NlwInverterSignal_U2_ADDR_reg<3>_MC.D2_PT_3/IN3 )
  );
  X_INV \NlwInverterBlock_U2_ADDR_reg<3>_MC.D2_PT_3/IN4  (
    .I(U2_ADDR_reg[5]),
    .O(\NlwInverterSignal_U2_ADDR_reg<3>_MC.D2_PT_3/IN4 )
  );
  X_INV \NlwInverterBlock_U2_ADDR_reg<3>_MC.D2_PT_3/IN5  (
    .I(U2_ADDR_reg[6]),
    .O(\NlwInverterSignal_U2_ADDR_reg<3>_MC.D2_PT_3/IN5 )
  );
  X_INV \NlwInverterBlock_U2_ADDR_reg<3>_MC.D2_PT_3/IN6  (
    .I(U2_ADDR_reg[7]),
    .O(\NlwInverterSignal_U2_ADDR_reg<3>_MC.D2_PT_3/IN6 )
  );
  X_INV \NlwInverterBlock_U2_ADDR_reg<3>_MC.D2_PT_3/IN10  (
    .I(U2_WRRDedge),
    .O(\NlwInverterSignal_U2_ADDR_reg<3>_MC.D2_PT_3/IN10 )
  );
  X_INV \NlwInverterBlock_U2_ADDR_reg<1>_MC.D2_PT_0/IN1  (
    .I(\MSPReset_II/UIM ),
    .O(\NlwInverterSignal_U2_ADDR_reg<1>_MC.D2_PT_0/IN1 )
  );
  X_INV \NlwInverterBlock_U2_ADDR_reg<1>_MC.D2_PT_1/IN3  (
    .I(\AS_II/UIM ),
    .O(\NlwInverterSignal_U2_ADDR_reg<1>_MC.D2_PT_1/IN3 )
  );
  X_INV \NlwInverterBlock_U2_ADDR_reg<1>_MC.D2_PT_1/IN5  (
    .I(\AD<1>_II/UIM ),
    .O(\NlwInverterSignal_U2_ADDR_reg<1>_MC.D2_PT_1/IN5 )
  );
  X_INV \NlwInverterBlock_U2_ADDR_reg<1>_MC.D2_PT_2/IN2  (
    .I(U2_ADDR_reg[1]),
    .O(\NlwInverterSignal_U2_ADDR_reg<1>_MC.D2_PT_2/IN2 )
  );
  X_INV \NlwInverterBlock_U2_ADDR_reg<1>_MC.D2_PT_2/IN4  (
    .I(\AS_II/UIM ),
    .O(\NlwInverterSignal_U2_ADDR_reg<1>_MC.D2_PT_2/IN4 )
  );
  X_INV \NlwInverterBlock_U2_ADDR_reg<1>_MC.D2_PT_3/IN3  (
    .I(U2_ADDR_reg[4]),
    .O(\NlwInverterSignal_U2_ADDR_reg<1>_MC.D2_PT_3/IN3 )
  );
  X_INV \NlwInverterBlock_U2_ADDR_reg<1>_MC.D2_PT_3/IN4  (
    .I(U2_ADDR_reg[5]),
    .O(\NlwInverterSignal_U2_ADDR_reg<1>_MC.D2_PT_3/IN4 )
  );
  X_INV \NlwInverterBlock_U2_ADDR_reg<1>_MC.D2_PT_3/IN5  (
    .I(U2_ADDR_reg[6]),
    .O(\NlwInverterSignal_U2_ADDR_reg<1>_MC.D2_PT_3/IN5 )
  );
  X_INV \NlwInverterBlock_U2_ADDR_reg<1>_MC.D2_PT_3/IN6  (
    .I(U2_ADDR_reg[7]),
    .O(\NlwInverterSignal_U2_ADDR_reg<1>_MC.D2_PT_3/IN6 )
  );
  X_INV \NlwInverterBlock_U2_ADDR_reg<1>_MC.D2_PT_3/IN8  (
    .I(U2_WRRDedge),
    .O(\NlwInverterSignal_U2_ADDR_reg<1>_MC.D2_PT_3/IN8 )
  );
  X_INV \NlwInverterBlock_U2_ADDR_reg<2>_MC.D2_PT_0/IN1  (
    .I(\MSPReset_II/UIM ),
    .O(\NlwInverterSignal_U2_ADDR_reg<2>_MC.D2_PT_0/IN1 )
  );
  X_INV \NlwInverterBlock_U2_ADDR_reg<2>_MC.D2_PT_1/IN3  (
    .I(\AS_II/UIM ),
    .O(\NlwInverterSignal_U2_ADDR_reg<2>_MC.D2_PT_1/IN3 )
  );
  X_INV \NlwInverterBlock_U2_ADDR_reg<2>_MC.D2_PT_1/IN5  (
    .I(\AD<2>_II/UIM ),
    .O(\NlwInverterSignal_U2_ADDR_reg<2>_MC.D2_PT_1/IN5 )
  );
  X_INV \NlwInverterBlock_U2_ADDR_reg<2>_MC.D2_PT_2/IN2  (
    .I(U2_ADDR_reg[2]),
    .O(\NlwInverterSignal_U2_ADDR_reg<2>_MC.D2_PT_2/IN2 )
  );
  X_INV \NlwInverterBlock_U2_ADDR_reg<2>_MC.D2_PT_2/IN4  (
    .I(\AS_II/UIM ),
    .O(\NlwInverterSignal_U2_ADDR_reg<2>_MC.D2_PT_2/IN4 )
  );
  X_INV \NlwInverterBlock_U2_ADDR_reg<2>_MC.D2_PT_3/IN3  (
    .I(U2_ADDR_reg[4]),
    .O(\NlwInverterSignal_U2_ADDR_reg<2>_MC.D2_PT_3/IN3 )
  );
  X_INV \NlwInverterBlock_U2_ADDR_reg<2>_MC.D2_PT_3/IN4  (
    .I(U2_ADDR_reg[5]),
    .O(\NlwInverterSignal_U2_ADDR_reg<2>_MC.D2_PT_3/IN4 )
  );
  X_INV \NlwInverterBlock_U2_ADDR_reg<2>_MC.D2_PT_3/IN5  (
    .I(U2_ADDR_reg[6]),
    .O(\NlwInverterSignal_U2_ADDR_reg<2>_MC.D2_PT_3/IN5 )
  );
  X_INV \NlwInverterBlock_U2_ADDR_reg<2>_MC.D2_PT_3/IN6  (
    .I(U2_ADDR_reg[7]),
    .O(\NlwInverterSignal_U2_ADDR_reg<2>_MC.D2_PT_3/IN6 )
  );
  X_INV \NlwInverterBlock_U2_ADDR_reg<2>_MC.D2_PT_3/IN9  (
    .I(U2_WRRDedge),
    .O(\NlwInverterSignal_U2_ADDR_reg<2>_MC.D2_PT_3/IN9 )
  );
  X_INV \NlwInverterBlock_U11_U3_counterr<5>_MC.D2_PT_1/IN0  (
    .I(N_PZ_1065),
    .O(\NlwInverterSignal_U11_U3_counterr<5>_MC.D2_PT_1/IN0 )
  );
  X_INV \NlwInverterBlock_U11_U3_counterr<5>_MC.D2_PT_2/IN0  (
    .I(N_PZ_1065),
    .O(\NlwInverterSignal_U11_U3_counterr<5>_MC.D2_PT_2/IN0 )
  );
  X_INV \NlwInverterBlock_U11_U3_counterr<5>_MC.D2_PT_2/IN3  (
    .I(U11_SCLdetect),
    .O(\NlwInverterSignal_U11_U3_counterr<5>_MC.D2_PT_2/IN3 )
  );
  X_INV \NlwInverterBlock_U11_U3_counterr<5>_MC.D2_PT_3/IN0  (
    .I(N_PZ_1065),
    .O(\NlwInverterSignal_U11_U3_counterr<5>_MC.D2_PT_3/IN0 )
  );
  X_INV \NlwInverterBlock_U11_U3_counterr<5>_MC.D2_PT_3/IN1  (
    .I(U11_Incdetect),
    .O(\NlwInverterSignal_U11_U3_counterr<5>_MC.D2_PT_3/IN1 )
  );
  X_INV \NlwInverterBlock_U11_U3_counterr<5>_MC.D2_PT_3/IN2  (
    .I(U11_U3_counterr[3]),
    .O(\NlwInverterSignal_U11_U3_counterr<5>_MC.D2_PT_3/IN2 )
  );
  X_INV \NlwInverterBlock_U11_U3_counterr<5>_MC.D2_PT_3/IN3  (
    .I(U11_U3_counterr[4]),
    .O(\NlwInverterSignal_U11_U3_counterr<5>_MC.D2_PT_3/IN3 )
  );
  X_INV \NlwInverterBlock_U11_U3_counterr<5>_MC.D2_PT_3/IN5  (
    .I(U11_U3_counterr[0]),
    .O(\NlwInverterSignal_U11_U3_counterr<5>_MC.D2_PT_3/IN5 )
  );
  X_INV \NlwInverterBlock_U11_U3_counterr<5>_MC.D2_PT_3/IN6  (
    .I(U11_U3_counterr[1]),
    .O(\NlwInverterSignal_U11_U3_counterr<5>_MC.D2_PT_3/IN6 )
  );
  X_INV \NlwInverterBlock_U11_U3_counterr<5>_MC.D2_PT_3/IN7  (
    .I(U11_U3_counterr[2]),
    .O(\NlwInverterSignal_U11_U3_counterr<5>_MC.D2_PT_3/IN7 )
  );
  X_INV \NlwInverterBlock_N_PZ_1065_MC.D2_PT_1/IN1  (
    .I(\SCLinc_II/UIM ),
    .O(\NlwInverterSignal_N_PZ_1065_MC.D2_PT_1/IN1 )
  );
  X_INV \NlwInverterBlock_N_PZ_1065_MC.D2_PT_2/IN0  (
    .I(U11_Incdetect),
    .O(\NlwInverterSignal_N_PZ_1065_MC.D2_PT_2/IN0 )
  );
  X_INV \NlwInverterBlock_U11_Incdetect_MC.D1/IN0  (
    .I(\SCLinc_II/UIM ),
    .O(\NlwInverterSignal_U11_Incdetect_MC.D1/IN0 )
  );
  X_INV \NlwInverterBlock_U11_ResetDetect_MC.D1/IN0  (
    .I(\SCLreset_II/UIM ),
    .O(\NlwInverterSignal_U11_ResetDetect_MC.D1/IN0 )
  );
  X_INV \NlwInverterBlock_U11_SCLdetect_MC.D1/IN0  (
    .I(\SCL_II/UIM ),
    .O(\NlwInverterSignal_U11_SCLdetect_MC.D1/IN0 )
  );
  X_INV \NlwInverterBlock_TP12_MC.D1/IN0  (
    .I(U11_U3_counterr[5]),
    .O(\NlwInverterSignal_TP12_MC.D1/IN0 )
  );
  X_INV \NlwInverterBlock_TP12_MC.D1/IN1  (
    .I(U11_U3_counterr[3]),
    .O(\NlwInverterSignal_TP12_MC.D1/IN1 )
  );
  X_INV \NlwInverterBlock_TP12_MC.D1/IN2  (
    .I(U11_U3_counterr[4]),
    .O(\NlwInverterSignal_TP12_MC.D1/IN2 )
  );
  X_INV \NlwInverterBlock_TP12_MC.D1/IN3  (
    .I(U11_U3_counterr[0]),
    .O(\NlwInverterSignal_TP12_MC.D1/IN3 )
  );
  X_INV \NlwInverterBlock_TP12_MC.D1/IN4  (
    .I(U11_U3_counterr[1]),
    .O(\NlwInverterSignal_TP12_MC.D1/IN4 )
  );
  X_INV \NlwInverterBlock_TP12_MC.D1/IN5  (
    .I(U11_U3_counterr[2]),
    .O(\NlwInverterSignal_TP12_MC.D1/IN5 )
  );
  X_INV \NlwInverterBlock_U11_U3_counterr<3>_MC.D/IN0  (
    .I(\U11_U3_counterr<3>_MC.D1 ),
    .O(\NlwInverterSignal_U11_U3_counterr<3>_MC.D/IN0 )
  );
  X_INV \NlwInverterBlock_U11_U3_counterr<3>_MC.D2_PT_1/IN1  (
    .I(U11_U3_counterr[3]),
    .O(\NlwInverterSignal_U11_U3_counterr<3>_MC.D2_PT_1/IN1 )
  );
  X_INV \NlwInverterBlock_U11_U3_counterr<3>_MC.D2_PT_1/IN2  (
    .I(\SCLreset_II/UIM ),
    .O(\NlwInverterSignal_U11_U3_counterr<3>_MC.D2_PT_1/IN2 )
  );
  X_INV \NlwInverterBlock_U11_U3_counterr<3>_MC.D2_PT_2/IN0  (
    .I(N_PZ_1065),
    .O(\NlwInverterSignal_U11_U3_counterr<3>_MC.D2_PT_2/IN0 )
  );
  X_INV \NlwInverterBlock_U11_U3_counterr<3>_MC.D2_PT_2/IN1  (
    .I(U11_Incdetect),
    .O(\NlwInverterSignal_U11_U3_counterr<3>_MC.D2_PT_2/IN1 )
  );
  X_INV \NlwInverterBlock_U11_U3_counterr<3>_MC.D2_PT_2/IN2  (
    .I(U11_SCLdetect),
    .O(\NlwInverterSignal_U11_U3_counterr<3>_MC.D2_PT_2/IN2 )
  );
  X_INV \NlwInverterBlock_U11_U3_counterr<3>_MC.D2_PT_3/IN0  (
    .I(N_PZ_1065),
    .O(\NlwInverterSignal_U11_U3_counterr<3>_MC.D2_PT_3/IN0 )
  );
  X_INV \NlwInverterBlock_U11_U3_counterr<3>_MC.D2_PT_3/IN1  (
    .I(U11_Incdetect),
    .O(\NlwInverterSignal_U11_U3_counterr<3>_MC.D2_PT_3/IN1 )
  );
  X_INV \NlwInverterBlock_U11_U3_counterr<3>_MC.D2_PT_4/IN0  (
    .I(N_PZ_1065),
    .O(\NlwInverterSignal_U11_U3_counterr<3>_MC.D2_PT_4/IN0 )
  );
  X_INV \NlwInverterBlock_U11_U3_counterr<3>_MC.D2_PT_4/IN1  (
    .I(U11_Incdetect),
    .O(\NlwInverterSignal_U11_U3_counterr<3>_MC.D2_PT_4/IN1 )
  );
  X_INV \NlwInverterBlock_U11_U3_counterr<3>_MC.D2_PT_5/IN0  (
    .I(N_PZ_1065),
    .O(\NlwInverterSignal_U11_U3_counterr<3>_MC.D2_PT_5/IN0 )
  );
  X_INV \NlwInverterBlock_U11_U3_counterr<3>_MC.D2_PT_5/IN1  (
    .I(U11_Incdetect),
    .O(\NlwInverterSignal_U11_U3_counterr<3>_MC.D2_PT_5/IN1 )
  );
  X_INV \NlwInverterBlock_U11_U3_counterr<3>_MC.D2_PT_6/IN0  (
    .I(N_PZ_1065),
    .O(\NlwInverterSignal_U11_U3_counterr<3>_MC.D2_PT_6/IN0 )
  );
  X_INV \NlwInverterBlock_U11_U3_counterr<3>_MC.D2_PT_6/IN1  (
    .I(U11_SCLdetect),
    .O(\NlwInverterSignal_U11_U3_counterr<3>_MC.D2_PT_6/IN1 )
  );
  X_INV \NlwInverterBlock_U11_U3_counterr<0>_MC.D2_PT_1/IN3  (
    .I(\SCLreset_II/UIM ),
    .O(\NlwInverterSignal_U11_U3_counterr<0>_MC.D2_PT_1/IN3 )
  );
  X_INV \NlwInverterBlock_U11_U3_counterr<0>_MC.D2_PT_2/IN1  (
    .I(U11_SCLdetect),
    .O(\NlwInverterSignal_U11_U3_counterr<0>_MC.D2_PT_2/IN1 )
  );
  X_INV \NlwInverterBlock_U11_U3_counterr<0>_MC.D2_PT_2/IN2  (
    .I(U11_U3_counterr[0]),
    .O(\NlwInverterSignal_U11_U3_counterr<0>_MC.D2_PT_2/IN2 )
  );
  X_INV \NlwInverterBlock_U11_U3_counterr<0>_MC.D2_PT_2/IN3  (
    .I(\SCLreset_II/UIM ),
    .O(\NlwInverterSignal_U11_U3_counterr<0>_MC.D2_PT_2/IN3 )
  );
  X_INV \NlwInverterBlock_U11_U3_counterr<0>_MC.D2_PT_3/IN1  (
    .I(\SCLreset_II/UIM ),
    .O(\NlwInverterSignal_U11_U3_counterr<0>_MC.D2_PT_3/IN1 )
  );
  X_INV \NlwInverterBlock_U11_U3_counterr<0>_MC.D2_PT_3/IN2  (
    .I(\SCLinc_II/UIM ),
    .O(\NlwInverterSignal_U11_U3_counterr<0>_MC.D2_PT_3/IN2 )
  );
  X_INV \NlwInverterBlock_U11_U3_counterr<0>_MC.D2_PT_4/IN0  (
    .I(U11_Incdetect),
    .O(\NlwInverterSignal_U11_U3_counterr<0>_MC.D2_PT_4/IN0 )
  );
  X_INV \NlwInverterBlock_U11_U3_counterr<0>_MC.D2_PT_4/IN1  (
    .I(U11_SCLdetect),
    .O(\NlwInverterSignal_U11_U3_counterr<0>_MC.D2_PT_4/IN1 )
  );
  X_INV \NlwInverterBlock_U11_U3_counterr<0>_MC.D2_PT_4/IN3  (
    .I(\SCLreset_II/UIM ),
    .O(\NlwInverterSignal_U11_U3_counterr<0>_MC.D2_PT_4/IN3 )
  );
  X_INV \NlwInverterBlock_U11_U3_counterr<0>_MC.D2_PT_5/IN0  (
    .I(U11_Incdetect),
    .O(\NlwInverterSignal_U11_U3_counterr<0>_MC.D2_PT_5/IN0 )
  );
  X_INV \NlwInverterBlock_U11_U3_counterr<0>_MC.D2_PT_5/IN2  (
    .I(U11_U3_counterr[0]),
    .O(\NlwInverterSignal_U11_U3_counterr<0>_MC.D2_PT_5/IN2 )
  );
  X_INV \NlwInverterBlock_U11_U3_counterr<0>_MC.D2_PT_5/IN3  (
    .I(\SCLreset_II/UIM ),
    .O(\NlwInverterSignal_U11_U3_counterr<0>_MC.D2_PT_5/IN3 )
  );
  X_INV \NlwInverterBlock_U11_U3_counterr<0>_MC.D2_PT_5/IN4  (
    .I(\TP12_MC.UIM ),
    .O(\NlwInverterSignal_U11_U3_counterr<0>_MC.D2_PT_5/IN4 )
  );
  X_INV \NlwInverterBlock_U11_U3_counterr<1>_MC.D2_PT_0/IN2  (
    .I(\SCLinc_II/UIM ),
    .O(\NlwInverterSignal_U11_U3_counterr<1>_MC.D2_PT_0/IN2 )
  );
  X_INV \NlwInverterBlock_U11_U3_counterr<1>_MC.D2_PT_1/IN0  (
    .I(N_PZ_1065),
    .O(\NlwInverterSignal_U11_U3_counterr<1>_MC.D2_PT_1/IN0 )
  );
  X_INV \NlwInverterBlock_U11_U3_counterr<1>_MC.D2_PT_1/IN2  (
    .I(U11_SCLdetect),
    .O(\NlwInverterSignal_U11_U3_counterr<1>_MC.D2_PT_1/IN2 )
  );
  X_INV \NlwInverterBlock_U11_U3_counterr<1>_MC.D2_PT_2/IN0  (
    .I(N_PZ_1065),
    .O(\NlwInverterSignal_U11_U3_counterr<1>_MC.D2_PT_2/IN0 )
  );
  X_INV \NlwInverterBlock_U11_U3_counterr<1>_MC.D2_PT_2/IN1  (
    .I(U11_Incdetect),
    .O(\NlwInverterSignal_U11_U3_counterr<1>_MC.D2_PT_2/IN1 )
  );
  X_INV \NlwInverterBlock_U11_U3_counterr<1>_MC.D2_PT_2/IN3  (
    .I(U11_U3_counterr[0]),
    .O(\NlwInverterSignal_U11_U3_counterr<1>_MC.D2_PT_2/IN3 )
  );
  X_INV \NlwInverterBlock_U11_U3_counterr<2>_MC.D2_PT_1/IN0  (
    .I(N_PZ_1065),
    .O(\NlwInverterSignal_U11_U3_counterr<2>_MC.D2_PT_1/IN0 )
  );
  X_INV \NlwInverterBlock_U11_U3_counterr<2>_MC.D2_PT_1/IN2  (
    .I(U11_SCLdetect),
    .O(\NlwInverterSignal_U11_U3_counterr<2>_MC.D2_PT_1/IN2 )
  );
  X_INV \NlwInverterBlock_U11_U3_counterr<2>_MC.D2_PT_2/IN0  (
    .I(N_PZ_1065),
    .O(\NlwInverterSignal_U11_U3_counterr<2>_MC.D2_PT_2/IN0 )
  );
  X_INV \NlwInverterBlock_U11_U3_counterr<2>_MC.D2_PT_2/IN1  (
    .I(U11_Incdetect),
    .O(\NlwInverterSignal_U11_U3_counterr<2>_MC.D2_PT_2/IN1 )
  );
  X_INV \NlwInverterBlock_U11_U3_counterr<2>_MC.D2_PT_2/IN3  (
    .I(U11_U3_counterr[0]),
    .O(\NlwInverterSignal_U11_U3_counterr<2>_MC.D2_PT_2/IN3 )
  );
  X_INV \NlwInverterBlock_U11_U3_counterr<2>_MC.D2_PT_2/IN4  (
    .I(U11_U3_counterr[1]),
    .O(\NlwInverterSignal_U11_U3_counterr<2>_MC.D2_PT_2/IN4 )
  );
  X_INV \NlwInverterBlock_U11_U3_counterr<4>_MC.D2_PT_1/IN0  (
    .I(N_PZ_1065),
    .O(\NlwInverterSignal_U11_U3_counterr<4>_MC.D2_PT_1/IN0 )
  );
  X_INV \NlwInverterBlock_U11_U3_counterr<4>_MC.D2_PT_2/IN0  (
    .I(N_PZ_1065),
    .O(\NlwInverterSignal_U11_U3_counterr<4>_MC.D2_PT_2/IN0 )
  );
  X_INV \NlwInverterBlock_U11_U3_counterr<4>_MC.D2_PT_2/IN2  (
    .I(U11_SCLdetect),
    .O(\NlwInverterSignal_U11_U3_counterr<4>_MC.D2_PT_2/IN2 )
  );
  X_INV \NlwInverterBlock_U11_U3_counterr<4>_MC.D2_PT_3/IN0  (
    .I(N_PZ_1065),
    .O(\NlwInverterSignal_U11_U3_counterr<4>_MC.D2_PT_3/IN0 )
  );
  X_INV \NlwInverterBlock_U11_U3_counterr<4>_MC.D2_PT_3/IN1  (
    .I(U11_Incdetect),
    .O(\NlwInverterSignal_U11_U3_counterr<4>_MC.D2_PT_3/IN1 )
  );
  X_INV \NlwInverterBlock_U11_U3_counterr<4>_MC.D2_PT_3/IN2  (
    .I(U11_U3_counterr[3]),
    .O(\NlwInverterSignal_U11_U3_counterr<4>_MC.D2_PT_3/IN2 )
  );
  X_INV \NlwInverterBlock_U11_U3_counterr<4>_MC.D2_PT_3/IN4  (
    .I(U11_U3_counterr[0]),
    .O(\NlwInverterSignal_U11_U3_counterr<4>_MC.D2_PT_3/IN4 )
  );
  X_INV \NlwInverterBlock_U11_U3_counterr<4>_MC.D2_PT_3/IN5  (
    .I(U11_U3_counterr[1]),
    .O(\NlwInverterSignal_U11_U3_counterr<4>_MC.D2_PT_3/IN5 )
  );
  X_INV \NlwInverterBlock_U11_U3_counterr<4>_MC.D2_PT_3/IN6  (
    .I(U11_U3_counterr[2]),
    .O(\NlwInverterSignal_U11_U3_counterr<4>_MC.D2_PT_3/IN6 )
  );
  X_INV \NlwInverterBlock_DCORCONFIGr_MC.D1/IN1  (
    .I(\RD_II/UIM ),
    .O(\NlwInverterSignal_DCORCONFIGr_MC.D1/IN1 )
  );
  X_INV \NlwInverterBlock_DCORCONFIGr_MC.D1/IN3  (
    .I(U2_ADDR_reg[4]),
    .O(\NlwInverterSignal_DCORCONFIGr_MC.D1/IN3 )
  );
  X_INV \NlwInverterBlock_DCORCONFIGr_MC.D1/IN4  (
    .I(U2_ADDR_reg[5]),
    .O(\NlwInverterSignal_DCORCONFIGr_MC.D1/IN4 )
  );
  X_INV \NlwInverterBlock_DCORCONFIGr_MC.D1/IN5  (
    .I(U2_ADDR_reg[6]),
    .O(\NlwInverterSignal_DCORCONFIGr_MC.D1/IN5 )
  );
  X_INV \NlwInverterBlock_DCORCONFIGr_MC.D1/IN6  (
    .I(U2_ADDR_reg[7]),
    .O(\NlwInverterSignal_DCORCONFIGr_MC.D1/IN6 )
  );
  X_INV \NlwInverterBlock_DCORLIMITSr_MC.D1/IN1  (
    .I(\RD_II/UIM ),
    .O(\NlwInverterSignal_DCORLIMITSr_MC.D1/IN1 )
  );
  X_INV \NlwInverterBlock_DCORLIMITSr_MC.D1/IN2  (
    .I(U2_ADDR_reg[0]),
    .O(\NlwInverterSignal_DCORLIMITSr_MC.D1/IN2 )
  );
  X_INV \NlwInverterBlock_DCORLIMITSr_MC.D1/IN3  (
    .I(U2_ADDR_reg[4]),
    .O(\NlwInverterSignal_DCORLIMITSr_MC.D1/IN3 )
  );
  X_INV \NlwInverterBlock_DCORLIMITSr_MC.D1/IN4  (
    .I(U2_ADDR_reg[5]),
    .O(\NlwInverterSignal_DCORLIMITSr_MC.D1/IN4 )
  );
  X_INV \NlwInverterBlock_DCORLIMITSr_MC.D1/IN5  (
    .I(U2_ADDR_reg[6]),
    .O(\NlwInverterSignal_DCORLIMITSr_MC.D1/IN5 )
  );
  X_INV \NlwInverterBlock_DCORLIMITSr_MC.D1/IN6  (
    .I(U2_ADDR_reg[7]),
    .O(\NlwInverterSignal_DCORLIMITSr_MC.D1/IN6 )
  );
  X_INV \NlwInverterBlock_DCORLIMITSr_MC.D1/IN7  (
    .I(U2_ADDR_reg[3]),
    .O(\NlwInverterSignal_DCORLIMITSr_MC.D1/IN7 )
  );
  X_INV \NlwInverterBlock_DCORLIMITSr_MC.D1/IN9  (
    .I(U2_ADDR_reg[2]),
    .O(\NlwInverterSignal_DCORLIMITSr_MC.D1/IN9 )
  );
  X_INV \NlwInverterBlock_DCORENCPWRr_MC.D1/IN1  (
    .I(\RD_II/UIM ),
    .O(\NlwInverterSignal_DCORENCPWRr_MC.D1/IN1 )
  );
  X_INV \NlwInverterBlock_DCORENCPWRr_MC.D1/IN2  (
    .I(U2_ADDR_reg[0]),
    .O(\NlwInverterSignal_DCORENCPWRr_MC.D1/IN2 )
  );
  X_INV \NlwInverterBlock_DCORENCPWRr_MC.D1/IN3  (
    .I(U2_ADDR_reg[4]),
    .O(\NlwInverterSignal_DCORENCPWRr_MC.D1/IN3 )
  );
  X_INV \NlwInverterBlock_DCORENCPWRr_MC.D1/IN4  (
    .I(U2_ADDR_reg[5]),
    .O(\NlwInverterSignal_DCORENCPWRr_MC.D1/IN4 )
  );
  X_INV \NlwInverterBlock_DCORENCPWRr_MC.D1/IN5  (
    .I(U2_ADDR_reg[6]),
    .O(\NlwInverterSignal_DCORENCPWRr_MC.D1/IN5 )
  );
  X_INV \NlwInverterBlock_DCORENCPWRr_MC.D1/IN6  (
    .I(U2_ADDR_reg[7]),
    .O(\NlwInverterSignal_DCORENCPWRr_MC.D1/IN6 )
  );
  X_INV \NlwInverterBlock_outDATA<5>\$WA3.UIM_MC.D2_PT_0/IN1  (
    .I(NET2528),
    .O(\NlwInverterSignal_outDATA<5>\$WA3.UIM_MC.D2_PT_0/IN1 )
  );
  X_INV \NlwInverterBlock_NET2528_MC.D1/IN1  (
    .I(DCORIFGw),
    .O(\NlwInverterSignal_NET2528_MC.D1/IN1 )
  );
  X_INV \NlwInverterBlock_NET2528_MC.D2_PT_0/IN1  (
    .I(\AD<1>_II/UIM ),
    .O(\NlwInverterSignal_NET2528_MC.D2_PT_0/IN1 )
  );
  X_INV \NlwInverterBlock_NET2528_MC.D2_PT_1/IN2  (
    .I(NET2528),
    .O(\NlwInverterSignal_NET2528_MC.D2_PT_1/IN2 )
  );
  X_INV \NlwInverterBlock_NET2528_MC.D2_PT_1/IN3  (
    .I(DCORIFGw),
    .O(\NlwInverterSignal_NET2528_MC.D2_PT_1/IN3 )
  );
  X_INV \NlwInverterBlock_DCORIFGw_MC.D1/IN0  (
    .I(\WR_II/UIM ),
    .O(\NlwInverterSignal_DCORIFGw_MC.D1/IN0 )
  );
  X_INV \NlwInverterBlock_DCORIFGw_MC.D1/IN3  (
    .I(U2_ADDR_reg[4]),
    .O(\NlwInverterSignal_DCORIFGw_MC.D1/IN3 )
  );
  X_INV \NlwInverterBlock_DCORIFGw_MC.D1/IN4  (
    .I(U2_ADDR_reg[5]),
    .O(\NlwInverterSignal_DCORIFGw_MC.D1/IN4 )
  );
  X_INV \NlwInverterBlock_DCORIFGw_MC.D1/IN5  (
    .I(U2_ADDR_reg[6]),
    .O(\NlwInverterSignal_DCORIFGw_MC.D1/IN5 )
  );
  X_INV \NlwInverterBlock_DCORIFGw_MC.D1/IN6  (
    .I(U2_ADDR_reg[7]),
    .O(\NlwInverterSignal_DCORIFGw_MC.D1/IN6 )
  );
  X_INV \NlwInverterBlock_DCORIFGw_MC.D1/IN7  (
    .I(U2_ADDR_reg[3]),
    .O(\NlwInverterSignal_DCORIFGw_MC.D1/IN7 )
  );
  X_INV \NlwInverterBlock_DCORIFGw_MC.D1/IN8  (
    .I(U2_ADDR_reg[1]),
    .O(\NlwInverterSignal_DCORIFGw_MC.D1/IN8 )
  );
  X_INV \NlwInverterBlock_DCORIFGw_MC.D1/IN9  (
    .I(U2_ADDR_reg[2]),
    .O(\NlwInverterSignal_DCORIFGw_MC.D1/IN9 )
  );
  X_INV \NlwInverterBlock_outDATA<5>\$WA5.UIM_MC.D2_PT_1/IN0  (
    .I(DCOR0CNTLOWr),
    .O(\NlwInverterSignal_outDATA<5>\$WA5.UIM_MC.D2_PT_1/IN0 )
  );
  X_INV \NlwInverterBlock_outDATA<5>\$WA5.UIM_MC.D2_PT_2/IN0  (
    .I(DCOR0CNTLOWr),
    .O(\NlwInverterSignal_outDATA<5>\$WA5.UIM_MC.D2_PT_2/IN0 )
  );
  X_INV \NlwInverterBlock_outDATA<5>\$WA5.UIM_MC.D2_PT_2/IN1  (
    .I(DCOR1CNTLOWr),
    .O(\NlwInverterSignal_outDATA<5>\$WA5.UIM_MC.D2_PT_2/IN1 )
  );
  X_INV \NlwInverterBlock_outDATA<5>\$WA5.UIM_MC.D2_PT_3/IN0  (
    .I(DCOR0CNTLOWr),
    .O(\NlwInverterSignal_outDATA<5>\$WA5.UIM_MC.D2_PT_3/IN0 )
  );
  X_INV \NlwInverterBlock_outDATA<5>\$WA5.UIM_MC.D2_PT_3/IN1  (
    .I(DCOR1CNTLOWr),
    .O(\NlwInverterSignal_outDATA<5>\$WA5.UIM_MC.D2_PT_3/IN1 )
  );
  X_INV \NlwInverterBlock_outDATA<5>\$WA5.UIM_MC.D2_PT_3/IN2  (
    .I(DCOR0CNTHIGHr),
    .O(\NlwInverterSignal_outDATA<5>\$WA5.UIM_MC.D2_PT_3/IN2 )
  );
  X_INV \NlwInverterBlock_U1/U3/holdingreg0<5>_MC.D2_PT_1/IN1  (
    .I(\AS_II/UIM ),
    .O(\NlwInverterSignal_U1/U3/holdingreg0<5>_MC.D2_PT_1/IN1 )
  );
  X_INV \NlwInverterBlock_U1/Channel0<5>_MC.D2_PT_0/IN1  (
    .I(N_PZ_928),
    .O(\NlwInverterSignal_U1/Channel0<5>_MC.D2_PT_0/IN1 )
  );
  X_INV \NlwInverterBlock_U1/Channel0<5>_MC.D2_PT_2/IN0  (
    .I(\U1/U2/location_Maddsub__n0000__n0067 [0]),
    .O(\NlwInverterSignal_U1/Channel0<5>_MC.D2_PT_2/IN0 )
  );
  X_INV \NlwInverterBlock_N_PZ_928_MC.D1/IN1  (
    .I(\U1/Zero0 ),
    .O(\NlwInverterSignal_N_PZ_928_MC.D1/IN1 )
  );
  X_INV \NlwInverterBlock_U1/Zero0_MC.D2_PT_0/IN0  (
    .I(\MSPReset_II/UIM ),
    .O(\NlwInverterSignal_U1/Zero0_MC.D2_PT_0/IN0 )
  );
  X_INV \NlwInverterBlock_U1/Zero0_MC.D2_PT_3/IN1  (
    .I(DCORIFGw),
    .O(\NlwInverterSignal_U1/Zero0_MC.D2_PT_3/IN1 )
  );
  X_INV \NlwInverterBlock_U1/Zero0_MC.D2_PT_3/IN2  (
    .I(DCORENCCTLw),
    .O(\NlwInverterSignal_U1/Zero0_MC.D2_PT_3/IN2 )
  );
  X_INV \NlwInverterBlock_U1/Zero0_MC.D2_PT_3/IN3  (
    .I(NET2482),
    .O(\NlwInverterSignal_U1/Zero0_MC.D2_PT_3/IN3 )
  );
  X_INV \NlwInverterBlock_U1/Zero0_MC.D2_PT_3/IN7  (
    .I(\U1/U4/HE0statelastr ),
    .O(\NlwInverterSignal_U1/Zero0_MC.D2_PT_3/IN7 )
  );
  X_INV \NlwInverterBlock_U1/Zero0_MC.D2_PT_4/IN1  (
    .I(DCORIFGw),
    .O(\NlwInverterSignal_U1/Zero0_MC.D2_PT_4/IN1 )
  );
  X_INV \NlwInverterBlock_U1/Zero0_MC.D2_PT_4/IN2  (
    .I(DCORENCCTLw),
    .O(\NlwInverterSignal_U1/Zero0_MC.D2_PT_4/IN2 )
  );
  X_INV \NlwInverterBlock_U1/Zero0_MC.D2_PT_4/IN3  (
    .I(NET2482),
    .O(\NlwInverterSignal_U1/Zero0_MC.D2_PT_4/IN3 )
  );
  X_INV \NlwInverterBlock_U1/Zero0_MC.D2_PT_4/IN4  (
    .I(\U1/U4/RF0r ),
    .O(\NlwInverterSignal_U1/Zero0_MC.D2_PT_4/IN4 )
  );
  X_INV \NlwInverterBlock_U1/Zero0_MC.D2_PT_4/IN6  (
    .I(\U1/U4/HE0stater ),
    .O(\NlwInverterSignal_U1/Zero0_MC.D2_PT_4/IN6 )
  );
  X_INV \NlwInverterBlock_DCORENCCTLw_MC.D1/IN0  (
    .I(\WR_II/UIM ),
    .O(\NlwInverterSignal_DCORENCCTLw_MC.D1/IN0 )
  );
  X_INV \NlwInverterBlock_DCORENCCTLw_MC.D1/IN3  (
    .I(U2_ADDR_reg[4]),
    .O(\NlwInverterSignal_DCORENCCTLw_MC.D1/IN3 )
  );
  X_INV \NlwInverterBlock_DCORENCCTLw_MC.D1/IN4  (
    .I(U2_ADDR_reg[5]),
    .O(\NlwInverterSignal_DCORENCCTLw_MC.D1/IN4 )
  );
  X_INV \NlwInverterBlock_DCORENCCTLw_MC.D1/IN5  (
    .I(U2_ADDR_reg[6]),
    .O(\NlwInverterSignal_DCORENCCTLw_MC.D1/IN5 )
  );
  X_INV \NlwInverterBlock_DCORENCCTLw_MC.D1/IN6  (
    .I(U2_ADDR_reg[7]),
    .O(\NlwInverterSignal_DCORENCCTLw_MC.D1/IN6 )
  );
  X_INV \NlwInverterBlock_DCORENCCTLw_MC.D1/IN7  (
    .I(U2_ADDR_reg[3]),
    .O(\NlwInverterSignal_DCORENCCTLw_MC.D1/IN7 )
  );
  X_INV \NlwInverterBlock_DCORENCCTLw_MC.D1/IN9  (
    .I(U2_ADDR_reg[2]),
    .O(\NlwInverterSignal_DCORENCCTLw_MC.D1/IN9 )
  );
  X_INV \NlwInverterBlock_NET2482_MC.D2_PT_0/IN0  (
    .I(\MSPReset_II/UIM ),
    .O(\NlwInverterSignal_NET2482_MC.D2_PT_0/IN0 )
  );
  X_INV \NlwInverterBlock_NET2482_MC.D2_PT_1/IN2  (
    .I(DCORENCCTLw),
    .O(\NlwInverterSignal_NET2482_MC.D2_PT_1/IN2 )
  );
  X_INV \NlwInverterBlock_NET2482_MC.D2_PT_2/IN1  (
    .I(DCORIFGw),
    .O(\NlwInverterSignal_NET2482_MC.D2_PT_2/IN1 )
  );
  X_INV \NlwInverterBlock_NET2482_MC.D2_PT_2/IN2  (
    .I(DCORENCCTLw),
    .O(\NlwInverterSignal_NET2482_MC.D2_PT_2/IN2 )
  );
  X_INV \NlwInverterBlock_NET2482_MC.D2_PT_2/IN3  (
    .I(NET2482),
    .O(\NlwInverterSignal_NET2482_MC.D2_PT_2/IN3 )
  );
  X_INV \NlwInverterBlock_NET2482_MC.D2_PT_2/IN7  (
    .I(\U1/U4/HE0statelastr ),
    .O(\NlwInverterSignal_NET2482_MC.D2_PT_2/IN7 )
  );
  X_INV \NlwInverterBlock_NET2482_MC.D2_PT_3/IN1  (
    .I(DCORIFGw),
    .O(\NlwInverterSignal_NET2482_MC.D2_PT_3/IN1 )
  );
  X_INV \NlwInverterBlock_NET2482_MC.D2_PT_3/IN2  (
    .I(DCORENCCTLw),
    .O(\NlwInverterSignal_NET2482_MC.D2_PT_3/IN2 )
  );
  X_INV \NlwInverterBlock_NET2482_MC.D2_PT_3/IN3  (
    .I(NET2482),
    .O(\NlwInverterSignal_NET2482_MC.D2_PT_3/IN3 )
  );
  X_INV \NlwInverterBlock_NET2482_MC.D2_PT_3/IN4  (
    .I(\U1/U4/RF0r ),
    .O(\NlwInverterSignal_NET2482_MC.D2_PT_3/IN4 )
  );
  X_INV \NlwInverterBlock_NET2482_MC.D2_PT_3/IN6  (
    .I(\U1/U4/HE0stater ),
    .O(\NlwInverterSignal_NET2482_MC.D2_PT_3/IN6 )
  );
  X_INV \NlwInverterBlock_U1/U4/RF0r_MC.D2_PT_1/IN1  (
    .I(DCORENCCTLw),
    .O(\NlwInverterSignal_U1/U4/RF0r_MC.D2_PT_1/IN1 )
  );
  X_INV \NlwInverterBlock_U1/U4/E0r_MC.D2_PT_1/IN1  (
    .I(DCORENCCTLw),
    .O(\NlwInverterSignal_U1/U4/E0r_MC.D2_PT_1/IN1 )
  );
  X_INV \NlwInverterBlock_U1/U2/location_Maddsub__n0000__n0067<0>_MC.D2_PT_1/IN0  (
    .I(N_PZ_943),
    .O(\NlwInverterSignal_U1/U2/location_Maddsub__n0000__n0067<0>_MC.D2_PT_1/IN0 )
  );
  X_INV \NlwInverterBlock_U1/U2/location_Maddsub__n0000__n0067<0>_MC.D2_PT_1/IN1  (
    .I(\U1/Channel0 [0]),
    .O(\NlwInverterSignal_U1/U2/location_Maddsub__n0000__n0067<0>_MC.D2_PT_1/IN1 )
  );
  X_INV \NlwInverterBlock_U1/U2/location_Maddsub__n0000__n0067<0>_MC.D2_PT_1/IN2  (
    .I(\U1/Channel0 [1]),
    .O(\NlwInverterSignal_U1/U2/location_Maddsub__n0000__n0067<0>_MC.D2_PT_1/IN2 )
  );
  X_INV \NlwInverterBlock_U1/U2/location_Maddsub__n0000__n0067<0>_MC.D2_PT_1/IN3  (
    .I(\U1/Channel0 [2]),
    .O(\NlwInverterSignal_U1/U2/location_Maddsub__n0000__n0067<0>_MC.D2_PT_1/IN3 )
  );
  X_INV \NlwInverterBlock_U1/U2/location_Maddsub__n0000__n0067<0>_MC.D2_PT_1/IN4  (
    .I(\U1/Channel0 [3]),
    .O(\NlwInverterSignal_U1/U2/location_Maddsub__n0000__n0067<0>_MC.D2_PT_1/IN4 )
  );
  X_INV \NlwInverterBlock_U1/U2/location_Maddsub__n0000__n0067<0>_MC.D2_PT_1/IN5  (
    .I(\U1/Channel0 [4]),
    .O(\NlwInverterSignal_U1/U2/location_Maddsub__n0000__n0067<0>_MC.D2_PT_1/IN5 )
  );
  X_INV \NlwInverterBlock_N_PZ_943_MC.D2_PT_0/IN0  (
    .I(\U1/U1/CurrState_Sreg0_FFD1 ),
    .O(\NlwInverterSignal_N_PZ_943_MC.D2_PT_0/IN0 )
  );
  X_INV \NlwInverterBlock_N_PZ_943_MC.D2_PT_0/IN2  (
    .I(\U1/U1/CurrState_Sreg0_FFD2 ),
    .O(\NlwInverterSignal_N_PZ_943_MC.D2_PT_0/IN2 )
  );
  X_INV \NlwInverterBlock_N_PZ_943_MC.D2_PT_1/IN0  (
    .I(\U1/U1/CurrState_Sreg0_FFD1 ),
    .O(\NlwInverterSignal_N_PZ_943_MC.D2_PT_1/IN0 )
  );
  X_INV \NlwInverterBlock_N_PZ_943_MC.D2_PT_1/IN2  (
    .I(\U1/U1/CurrState_Sreg0_FFD4 ),
    .O(\NlwInverterSignal_N_PZ_943_MC.D2_PT_1/IN2 )
  );
  X_INV \NlwInverterBlock_U1/NET3721_MC.D2_PT_1/IN1  (
    .I(DCORENCCTLw),
    .O(\NlwInverterSignal_U1/NET3721_MC.D2_PT_1/IN1 )
  );
  X_INV \NlwInverterBlock_U1/U1/CurrState_Sreg0_FFD1_MC.D2_PT_0/IN3  (
    .I(\U1/U1/CurrState_Sreg0_FFD4 ),
    .O(\NlwInverterSignal_U1/U1/CurrState_Sreg0_FFD1_MC.D2_PT_0/IN3 )
  );
  X_INV \NlwInverterBlock_U1/U1/CurrState_Sreg0_FFD1_MC.D2_PT_1/IN2  (
    .I(\U1/U1/CurrState_Sreg0_FFD3 ),
    .O(\NlwInverterSignal_U1/U1/CurrState_Sreg0_FFD1_MC.D2_PT_1/IN2 )
  );
  X_INV \NlwInverterBlock_U1/U1/CurrState_Sreg0_FFD1_MC.D2_PT_1/IN3  (
    .I(\U1/U1/CurrState_Sreg0_FFD4 ),
    .O(\NlwInverterSignal_U1/U1/CurrState_Sreg0_FFD1_MC.D2_PT_1/IN3 )
  );
  X_INV \NlwInverterBlock_U1/U1/CurrState_Sreg0_FFD1_MC.D2_PT_2/IN1  (
    .I(\U1/U1/CurrState_Sreg0_FFD3 ),
    .O(\NlwInverterSignal_U1/U1/CurrState_Sreg0_FFD1_MC.D2_PT_2/IN1 )
  );
  X_INV \NlwInverterBlock_U1/U1/CurrState_Sreg0_FFD1_MC.D2_PT_2/IN2  (
    .I(\U1/U1/CurrState_Sreg0_FFD2 ),
    .O(\NlwInverterSignal_U1/U1/CurrState_Sreg0_FFD1_MC.D2_PT_2/IN2 )
  );
  X_INV \NlwInverterBlock_U1/U1/CurrState_Sreg0_FFD1_MC.D2_PT_2/IN3  (
    .I(\U1/U1/CurrState_Sreg0_FFD4 ),
    .O(\NlwInverterSignal_U1/U1/CurrState_Sreg0_FFD1_MC.D2_PT_2/IN3 )
  );
  X_INV \NlwInverterBlock_U1/U1/CurrState_Sreg0_FFD1_MC.D2_PT_2/IN4  (
    .I(\PhaseA_Encoder0_II/UIM ),
    .O(\NlwInverterSignal_U1/U1/CurrState_Sreg0_FFD1_MC.D2_PT_2/IN4 )
  );
  X_INV \NlwInverterBlock_U1/U1/CurrState_Sreg0_FFD3_MC.D2_PT_0/IN1  (
    .I(\U1/U1/CurrState_Sreg0_FFD1 ),
    .O(\NlwInverterSignal_U1/U1/CurrState_Sreg0_FFD3_MC.D2_PT_0/IN1 )
  );
  X_INV \NlwInverterBlock_U1/U1/CurrState_Sreg0_FFD3_MC.D2_PT_0/IN3  (
    .I(\U1/U1/CurrState_Sreg0_FFD2 ),
    .O(\NlwInverterSignal_U1/U1/CurrState_Sreg0_FFD3_MC.D2_PT_0/IN3 )
  );
  X_INV \NlwInverterBlock_U1/U1/CurrState_Sreg0_FFD3_MC.D2_PT_0/IN4  (
    .I(\U1/U1/CurrState_Sreg0_FFD4 ),
    .O(\NlwInverterSignal_U1/U1/CurrState_Sreg0_FFD3_MC.D2_PT_0/IN4 )
  );
  X_INV \NlwInverterBlock_U1/U1/CurrState_Sreg0_FFD3_MC.D2_PT_1/IN3  (
    .I(\U1/U1/CurrState_Sreg0_FFD4 ),
    .O(\NlwInverterSignal_U1/U1/CurrState_Sreg0_FFD3_MC.D2_PT_1/IN3 )
  );
  X_INV \NlwInverterBlock_U1/U1/CurrState_Sreg0_FFD3_MC.D2_PT_1/IN4  (
    .I(\PhaseA_Encoder0_II/UIM ),
    .O(\NlwInverterSignal_U1/U1/CurrState_Sreg0_FFD3_MC.D2_PT_1/IN4 )
  );
  X_INV \NlwInverterBlock_U1/U1/CurrState_Sreg0_FFD3_MC.D2_PT_2/IN3  (
    .I(\U1/U1/CurrState_Sreg0_FFD4 ),
    .O(\NlwInverterSignal_U1/U1/CurrState_Sreg0_FFD3_MC.D2_PT_2/IN3 )
  );
  X_INV \NlwInverterBlock_U1/U1/CurrState_Sreg0_FFD3_MC.D2_PT_2/IN5  (
    .I(\PhaseB_Encoder0_II/UIM ),
    .O(\NlwInverterSignal_U1/U1/CurrState_Sreg0_FFD3_MC.D2_PT_2/IN5 )
  );
  X_INV \NlwInverterBlock_U1/U1/CurrState_Sreg0_FFD3_MC.D2_PT_3/IN1  (
    .I(\U1/U1/CurrState_Sreg0_FFD1 ),
    .O(\NlwInverterSignal_U1/U1/CurrState_Sreg0_FFD3_MC.D2_PT_3/IN1 )
  );
  X_INV \NlwInverterBlock_U1/U1/CurrState_Sreg0_FFD3_MC.D2_PT_3/IN3  (
    .I(\U1/U1/CurrState_Sreg0_FFD4 ),
    .O(\NlwInverterSignal_U1/U1/CurrState_Sreg0_FFD3_MC.D2_PT_3/IN3 )
  );
  X_INV \NlwInverterBlock_U1/U1/CurrState_Sreg0_FFD2_MC.D2_PT_0/IN4  (
    .I(\U1/U1/CurrState_Sreg0_FFD4 ),
    .O(\NlwInverterSignal_U1/U1/CurrState_Sreg0_FFD2_MC.D2_PT_0/IN4 )
  );
  X_INV \NlwInverterBlock_U1/U1/CurrState_Sreg0_FFD2_MC.D2_PT_1/IN2  (
    .I(\U1/U1/CurrState_Sreg0_FFD3 ),
    .O(\NlwInverterSignal_U1/U1/CurrState_Sreg0_FFD2_MC.D2_PT_1/IN2 )
  );
  X_INV \NlwInverterBlock_U1/U1/CurrState_Sreg0_FFD2_MC.D2_PT_1/IN4  (
    .I(\U1/U1/CurrState_Sreg0_FFD4 ),
    .O(\NlwInverterSignal_U1/U1/CurrState_Sreg0_FFD2_MC.D2_PT_1/IN4 )
  );
  X_INV \NlwInverterBlock_U1/U1/CurrState_Sreg0_FFD2_MC.D2_PT_1/IN5  (
    .I(\PhaseB_Encoder0_II/UIM ),
    .O(\NlwInverterSignal_U1/U1/CurrState_Sreg0_FFD2_MC.D2_PT_1/IN5 )
  );
  X_INV \NlwInverterBlock_U1/U1/CurrState_Sreg0_FFD2_MC.D2_PT_2/IN2  (
    .I(\U1/U1/CurrState_Sreg0_FFD3 ),
    .O(\NlwInverterSignal_U1/U1/CurrState_Sreg0_FFD2_MC.D2_PT_2/IN2 )
  );
  X_INV \NlwInverterBlock_U1/U1/CurrState_Sreg0_FFD2_MC.D2_PT_2/IN3  (
    .I(\U1/U1/CurrState_Sreg0_FFD4 ),
    .O(\NlwInverterSignal_U1/U1/CurrState_Sreg0_FFD2_MC.D2_PT_2/IN3 )
  );
  X_INV \NlwInverterBlock_U1/U1/CurrState_Sreg0_FFD2_MC.D2_PT_3/IN3  (
    .I(\U1/U1/CurrState_Sreg0_FFD4 ),
    .O(\NlwInverterSignal_U1/U1/CurrState_Sreg0_FFD2_MC.D2_PT_3/IN3 )
  );
  X_INV \NlwInverterBlock_U1/U1/CurrState_Sreg0_FFD2_MC.D2_PT_3/IN5  (
    .I(\PhaseB_Encoder0_II/UIM ),
    .O(\NlwInverterSignal_U1/U1/CurrState_Sreg0_FFD2_MC.D2_PT_3/IN5 )
  );
  X_INV \NlwInverterBlock_U1/U1/CurrState_Sreg0_FFD2_MC.D2_PT_4/IN1  (
    .I(\U1/U1/CurrState_Sreg0_FFD1 ),
    .O(\NlwInverterSignal_U1/U1/CurrState_Sreg0_FFD2_MC.D2_PT_4/IN1 )
  );
  X_INV \NlwInverterBlock_U1/U1/CurrState_Sreg0_FFD2_MC.D2_PT_4/IN4  (
    .I(\U1/U1/CurrState_Sreg0_FFD4 ),
    .O(\NlwInverterSignal_U1/U1/CurrState_Sreg0_FFD2_MC.D2_PT_4/IN4 )
  );
  X_INV \NlwInverterBlock_U1/U1/CurrState_Sreg0_FFD2_MC.D2_PT_4/IN5  (
    .I(\PhaseB_Encoder0_II/UIM ),
    .O(\NlwInverterSignal_U1/U1/CurrState_Sreg0_FFD2_MC.D2_PT_4/IN5 )
  );
  X_INV \NlwInverterBlock_U1/U1/CurrState_Sreg0_FFD2_MC.D2_PT_5/IN1  (
    .I(\U1/U1/CurrState_Sreg0_FFD1 ),
    .O(\NlwInverterSignal_U1/U1/CurrState_Sreg0_FFD2_MC.D2_PT_5/IN1 )
  );
  X_INV \NlwInverterBlock_U1/U1/CurrState_Sreg0_FFD2_MC.D2_PT_5/IN3  (
    .I(\U1/U1/CurrState_Sreg0_FFD4 ),
    .O(\NlwInverterSignal_U1/U1/CurrState_Sreg0_FFD2_MC.D2_PT_5/IN3 )
  );
  X_INV \NlwInverterBlock_U1/U1/CurrState_Sreg0_FFD2_MC.D2_PT_6/IN1  (
    .I(\U1/U1/CurrState_Sreg0_FFD1 ),
    .O(\NlwInverterSignal_U1/U1/CurrState_Sreg0_FFD2_MC.D2_PT_6/IN1 )
  );
  X_INV \NlwInverterBlock_U1/U1/CurrState_Sreg0_FFD2_MC.D2_PT_6/IN2  (
    .I(\U1/U1/CurrState_Sreg0_FFD3 ),
    .O(\NlwInverterSignal_U1/U1/CurrState_Sreg0_FFD2_MC.D2_PT_6/IN2 )
  );
  X_INV \NlwInverterBlock_U1/U1/CurrState_Sreg0_FFD2_MC.D2_PT_6/IN4  (
    .I(\U1/U1/CurrState_Sreg0_FFD4 ),
    .O(\NlwInverterSignal_U1/U1/CurrState_Sreg0_FFD2_MC.D2_PT_6/IN4 )
  );
  X_INV \NlwInverterBlock_U1/U1/CurrState_Sreg0_FFD2_MC.D2_PT_7/IN1  (
    .I(\U1/U1/CurrState_Sreg0_FFD1 ),
    .O(\NlwInverterSignal_U1/U1/CurrState_Sreg0_FFD2_MC.D2_PT_7/IN1 )
  );
  X_INV \NlwInverterBlock_U1/U1/CurrState_Sreg0_FFD2_MC.D2_PT_7/IN2  (
    .I(\U1/U1/CurrState_Sreg0_FFD3 ),
    .O(\NlwInverterSignal_U1/U1/CurrState_Sreg0_FFD2_MC.D2_PT_7/IN2 )
  );
  X_INV \NlwInverterBlock_U1/U1/CurrState_Sreg0_FFD2_MC.D2_PT_7/IN3  (
    .I(\U1/U1/CurrState_Sreg0_FFD4 ),
    .O(\NlwInverterSignal_U1/U1/CurrState_Sreg0_FFD2_MC.D2_PT_7/IN3 )
  );
  X_INV \NlwInverterBlock_U1/U1/CurrState_Sreg0_FFD2_MC.D2_PT_7/IN5  (
    .I(\PhaseB_Encoder0_II/UIM ),
    .O(\NlwInverterSignal_U1/U1/CurrState_Sreg0_FFD2_MC.D2_PT_7/IN5 )
  );
  X_INV \NlwInverterBlock_U1/U1/CurrState_Sreg0_FFD4_MC.D1/IN1  (
    .I(\U1/U1/CurrState_Sreg0_FFD1 ),
    .O(\NlwInverterSignal_U1/U1/CurrState_Sreg0_FFD4_MC.D1/IN1 )
  );
  X_INV \NlwInverterBlock_U1/U1/CurrState_Sreg0_FFD4_MC.D1/IN3  (
    .I(\U1/U1/CurrState_Sreg0_FFD2 ),
    .O(\NlwInverterSignal_U1/U1/CurrState_Sreg0_FFD4_MC.D1/IN3 )
  );
  X_INV \NlwInverterBlock_U1/U1/CurrState_Sreg0_FFD4_MC.D1/IN4  (
    .I(\U1/U1/CurrState_Sreg0_FFD4 ),
    .O(\NlwInverterSignal_U1/U1/CurrState_Sreg0_FFD4_MC.D1/IN4 )
  );
  X_INV \NlwInverterBlock_U1/U1/CurrState_Sreg0_FFD4_MC.D1/IN5  (
    .I(\PhaseA_Encoder0_II/UIM ),
    .O(\NlwInverterSignal_U1/U1/CurrState_Sreg0_FFD4_MC.D1/IN5 )
  );
  X_INV \NlwInverterBlock_U1/U1/CurrState_Sreg0_FFD4_MC.D1/IN6  (
    .I(\PhaseB_Encoder0_II/UIM ),
    .O(\NlwInverterSignal_U1/U1/CurrState_Sreg0_FFD4_MC.D1/IN6 )
  );
  X_INV \NlwInverterBlock_U1/Channel0<0>_MC.D2_PT_0/IN0  (
    .I(N_PZ_928),
    .O(\NlwInverterSignal_U1/Channel0<0>_MC.D2_PT_0/IN0 )
  );
  X_INV \NlwInverterBlock_U1/Channel0<0>_MC.D2_PT_1/IN1  (
    .I(\U1/Zero0 ),
    .O(\NlwInverterSignal_U1/Channel0<0>_MC.D2_PT_1/IN1 )
  );
  X_INV \NlwInverterBlock_U1/Channel0<0>_MC.D2_PT_1/IN4  (
    .I(\U1/U1/CurrState_Sreg0_FFD2 ),
    .O(\NlwInverterSignal_U1/Channel0<0>_MC.D2_PT_1/IN4 )
  );
  X_INV \NlwInverterBlock_U1/Channel0<0>_MC.D2_PT_1/IN5  (
    .I(\U1/U1/CurrState_Sreg0_FFD4 ),
    .O(\NlwInverterSignal_U1/Channel0<0>_MC.D2_PT_1/IN5 )
  );
  X_INV \NlwInverterBlock_U1/Channel0<0>_MC.D2_PT_2/IN1  (
    .I(\U1/Zero0 ),
    .O(\NlwInverterSignal_U1/Channel0<0>_MC.D2_PT_2/IN1 )
  );
  X_INV \NlwInverterBlock_U1/Channel0<0>_MC.D2_PT_2/IN2  (
    .I(\U1/U1/CurrState_Sreg0_FFD1 ),
    .O(\NlwInverterSignal_U1/Channel0<0>_MC.D2_PT_2/IN2 )
  );
  X_INV \NlwInverterBlock_U1/Channel0<0>_MC.D2_PT_2/IN4  (
    .I(\U1/U1/CurrState_Sreg0_FFD2 ),
    .O(\NlwInverterSignal_U1/Channel0<0>_MC.D2_PT_2/IN4 )
  );
  X_INV \NlwInverterBlock_U1/Channel0<1>_MC.D2_PT_0/IN0  (
    .I(N_PZ_928),
    .O(\NlwInverterSignal_U1/Channel0<1>_MC.D2_PT_0/IN0 )
  );
  X_INV \NlwInverterBlock_U1/Channel0<1>_MC.D2_PT_1/IN1  (
    .I(\U1/Channel0 [0]),
    .O(\NlwInverterSignal_U1/Channel0<1>_MC.D2_PT_1/IN1 )
  );
  X_INV \NlwInverterBlock_N_PZ_964_MC.D2_PT_0/IN1  (
    .I(\U1/Zero0 ),
    .O(\NlwInverterSignal_N_PZ_964_MC.D2_PT_0/IN1 )
  );
  X_INV \NlwInverterBlock_N_PZ_964_MC.D2_PT_0/IN3  (
    .I(\U1/U1/CurrState_Sreg0_FFD1 ),
    .O(\NlwInverterSignal_N_PZ_964_MC.D2_PT_0/IN3 )
  );
  X_INV \NlwInverterBlock_N_PZ_964_MC.D2_PT_0/IN5  (
    .I(\U1/U1/CurrState_Sreg0_FFD2 ),
    .O(\NlwInverterSignal_N_PZ_964_MC.D2_PT_0/IN5 )
  );
  X_INV \NlwInverterBlock_N_PZ_964_MC.D2_PT_1/IN1  (
    .I(\U1/Zero0 ),
    .O(\NlwInverterSignal_N_PZ_964_MC.D2_PT_1/IN1 )
  );
  X_INV \NlwInverterBlock_N_PZ_964_MC.D2_PT_1/IN2  (
    .I(\U1/NET3721 ),
    .O(\NlwInverterSignal_N_PZ_964_MC.D2_PT_1/IN2 )
  );
  X_INV \NlwInverterBlock_N_PZ_964_MC.D2_PT_1/IN5  (
    .I(\U1/U1/CurrState_Sreg0_FFD2 ),
    .O(\NlwInverterSignal_N_PZ_964_MC.D2_PT_1/IN5 )
  );
  X_INV \NlwInverterBlock_N_PZ_964_MC.D2_PT_1/IN6  (
    .I(\U1/U1/CurrState_Sreg0_FFD4 ),
    .O(\NlwInverterSignal_N_PZ_964_MC.D2_PT_1/IN6 )
  );
  X_INV \NlwInverterBlock_N_PZ_968_MC.D2_PT_0/IN1  (
    .I(\U1/Zero0 ),
    .O(\NlwInverterSignal_N_PZ_968_MC.D2_PT_0/IN1 )
  );
  X_INV \NlwInverterBlock_N_PZ_968_MC.D2_PT_0/IN5  (
    .I(\U1/U1/CurrState_Sreg0_FFD2 ),
    .O(\NlwInverterSignal_N_PZ_968_MC.D2_PT_0/IN5 )
  );
  X_INV \NlwInverterBlock_N_PZ_968_MC.D2_PT_0/IN6  (
    .I(\U1/U1/CurrState_Sreg0_FFD4 ),
    .O(\NlwInverterSignal_N_PZ_968_MC.D2_PT_0/IN6 )
  );
  X_INV \NlwInverterBlock_N_PZ_968_MC.D2_PT_1/IN1  (
    .I(\U1/Zero0 ),
    .O(\NlwInverterSignal_N_PZ_968_MC.D2_PT_1/IN1 )
  );
  X_INV \NlwInverterBlock_N_PZ_968_MC.D2_PT_1/IN2  (
    .I(\U1/NET3721 ),
    .O(\NlwInverterSignal_N_PZ_968_MC.D2_PT_1/IN2 )
  );
  X_INV \NlwInverterBlock_N_PZ_968_MC.D2_PT_1/IN3  (
    .I(\U1/U1/CurrState_Sreg0_FFD1 ),
    .O(\NlwInverterSignal_N_PZ_968_MC.D2_PT_1/IN3 )
  );
  X_INV \NlwInverterBlock_N_PZ_968_MC.D2_PT_1/IN5  (
    .I(\U1/U1/CurrState_Sreg0_FFD2 ),
    .O(\NlwInverterSignal_N_PZ_968_MC.D2_PT_1/IN5 )
  );
  X_INV \NlwInverterBlock_U1/Channel0<2>_MC.D2_PT_0/IN0  (
    .I(N_PZ_928),
    .O(\NlwInverterSignal_U1/Channel0<2>_MC.D2_PT_0/IN0 )
  );
  X_INV \NlwInverterBlock_U1/Channel0<2>_MC.D2_PT_1/IN1  (
    .I(\U1/Channel0 [0]),
    .O(\NlwInverterSignal_U1/Channel0<2>_MC.D2_PT_1/IN1 )
  );
  X_INV \NlwInverterBlock_U1/Channel0<2>_MC.D2_PT_1/IN2  (
    .I(\U1/Channel0 [1]),
    .O(\NlwInverterSignal_U1/Channel0<2>_MC.D2_PT_1/IN2 )
  );
  X_INV \NlwInverterBlock_U1/Channel0<3>_MC.D2_PT_0/IN0  (
    .I(N_PZ_928),
    .O(\NlwInverterSignal_U1/Channel0<3>_MC.D2_PT_0/IN0 )
  );
  X_INV \NlwInverterBlock_U1/Channel0<3>_MC.D2_PT_1/IN1  (
    .I(\U1/Channel0 [0]),
    .O(\NlwInverterSignal_U1/Channel0<3>_MC.D2_PT_1/IN1 )
  );
  X_INV \NlwInverterBlock_U1/Channel0<3>_MC.D2_PT_1/IN2  (
    .I(\U1/Channel0 [1]),
    .O(\NlwInverterSignal_U1/Channel0<3>_MC.D2_PT_1/IN2 )
  );
  X_INV \NlwInverterBlock_U1/Channel0<3>_MC.D2_PT_1/IN3  (
    .I(\U1/Channel0 [2]),
    .O(\NlwInverterSignal_U1/Channel0<3>_MC.D2_PT_1/IN3 )
  );
  X_INV \NlwInverterBlock_U1/Channel0<4>_MC.D1/IN0  (
    .I(\U1/U2/location_Maddsub__n0000__n0067 [0]),
    .O(\NlwInverterSignal_U1/Channel0<4>_MC.D1/IN0 )
  );
  X_INV \NlwInverterBlock_U1/Channel0<4>_MC.D2_PT_0/IN0  (
    .I(N_PZ_928),
    .O(\NlwInverterSignal_U1/Channel0<4>_MC.D2_PT_0/IN0 )
  );
  X_INV \NlwInverterBlock_U1/Channel0<4>_MC.D2_PT_1/IN0  (
    .I(N_PZ_928),
    .O(\NlwInverterSignal_U1/Channel0<4>_MC.D2_PT_1/IN0 )
  );
  X_INV \NlwInverterBlock_U1/Channel0<4>_MC.D2_PT_1/IN1  (
    .I(N_PZ_968),
    .O(\NlwInverterSignal_U1/Channel0<4>_MC.D2_PT_1/IN1 )
  );
  X_INV \NlwInverterBlock_U1/Channel0<4>_MC.D2_PT_2/IN2  (
    .I(\U1/Channel0 [4]),
    .O(\NlwInverterSignal_U1/Channel0<4>_MC.D2_PT_2/IN2 )
  );
  X_INV \NlwInverterBlock_U1/Channel0<4>_MC.D2_PT_3/IN6  (
    .I(\U1/Channel0 [4]),
    .O(\NlwInverterSignal_U1/Channel0<4>_MC.D2_PT_3/IN6 )
  );
  X_INV \NlwInverterBlock_U1/Channel0<4>_MC.D2_PT_4/IN0  (
    .I(\U1/U2/location_Maddsub__n0000__n0067 [0]),
    .O(\NlwInverterSignal_U1/Channel0<4>_MC.D2_PT_4/IN0 )
  );
  X_INV \NlwInverterBlock_U1/Channel0<4>_MC.D2_PT_4/IN2  (
    .I(N_PZ_968),
    .O(\NlwInverterSignal_U1/Channel0<4>_MC.D2_PT_4/IN2 )
  );
  X_INV \NlwInverterBlock_U1/Channel0<4>_MC.D2_PT_4/IN3  (
    .I(\U1/Channel0 [0]),
    .O(\NlwInverterSignal_U1/Channel0<4>_MC.D2_PT_4/IN3 )
  );
  X_INV \NlwInverterBlock_U1/Channel0<4>_MC.D2_PT_4/IN4  (
    .I(\U1/Channel0 [1]),
    .O(\NlwInverterSignal_U1/Channel0<4>_MC.D2_PT_4/IN4 )
  );
  X_INV \NlwInverterBlock_U1/Channel0<4>_MC.D2_PT_4/IN5  (
    .I(\U1/Channel0 [2]),
    .O(\NlwInverterSignal_U1/Channel0<4>_MC.D2_PT_4/IN5 )
  );
  X_INV \NlwInverterBlock_U1/Channel0<4>_MC.D2_PT_4/IN6  (
    .I(\U1/Channel0 [3]),
    .O(\NlwInverterSignal_U1/Channel0<4>_MC.D2_PT_4/IN6 )
  );
  X_INV \NlwInverterBlock_U1/Channel0<4>_MC.D2_PT_5/IN1  (
    .I(\U1/U2/location_Maddsub__n0000__n0067 [0]),
    .O(\NlwInverterSignal_U1/Channel0<4>_MC.D2_PT_5/IN1 )
  );
  X_INV \NlwInverterBlock_U1/Channel0<4>_MC.D2_PT_5/IN3  (
    .I(\U1/Zero0 ),
    .O(\NlwInverterSignal_U1/Channel0<4>_MC.D2_PT_5/IN3 )
  );
  X_INV \NlwInverterBlock_U1/Channel0<4>_MC.D2_PT_5/IN7  (
    .I(\U1/Channel0 [3]),
    .O(\NlwInverterSignal_U1/Channel0<4>_MC.D2_PT_5/IN7 )
  );
  X_INV \NlwInverterBlock_DCOR0CNTLOWr_MC.D1/IN1  (
    .I(\RD_II/UIM ),
    .O(\NlwInverterSignal_DCOR0CNTLOWr_MC.D1/IN1 )
  );
  X_INV \NlwInverterBlock_DCOR0CNTLOWr_MC.D1/IN2  (
    .I(U2_ADDR_reg[0]),
    .O(\NlwInverterSignal_DCOR0CNTLOWr_MC.D1/IN2 )
  );
  X_INV \NlwInverterBlock_DCOR0CNTLOWr_MC.D1/IN3  (
    .I(U2_ADDR_reg[4]),
    .O(\NlwInverterSignal_DCOR0CNTLOWr_MC.D1/IN3 )
  );
  X_INV \NlwInverterBlock_DCOR0CNTLOWr_MC.D1/IN4  (
    .I(U2_ADDR_reg[5]),
    .O(\NlwInverterSignal_DCOR0CNTLOWr_MC.D1/IN4 )
  );
  X_INV \NlwInverterBlock_DCOR0CNTLOWr_MC.D1/IN5  (
    .I(U2_ADDR_reg[6]),
    .O(\NlwInverterSignal_DCOR0CNTLOWr_MC.D1/IN5 )
  );
  X_INV \NlwInverterBlock_DCOR0CNTLOWr_MC.D1/IN6  (
    .I(U2_ADDR_reg[7]),
    .O(\NlwInverterSignal_DCOR0CNTLOWr_MC.D1/IN6 )
  );
  X_INV \NlwInverterBlock_DCOR0CNTLOWr_MC.D1/IN7  (
    .I(U2_ADDR_reg[3]),
    .O(\NlwInverterSignal_DCOR0CNTLOWr_MC.D1/IN7 )
  );
  X_INV \NlwInverterBlock_DCOR0CNTLOWr_MC.D1/IN8  (
    .I(U2_ADDR_reg[1]),
    .O(\NlwInverterSignal_DCOR0CNTLOWr_MC.D1/IN8 )
  );
  X_INV \NlwInverterBlock_U1/U3/holdingreg1<5>_MC.D2_PT_1/IN1  (
    .I(\AS_II/UIM ),
    .O(\NlwInverterSignal_U1/U3/holdingreg1<5>_MC.D2_PT_1/IN1 )
  );
  X_INV \NlwInverterBlock_U1/Channel1<5>_MC.D2_PT_0/IN1  (
    .I(N_PZ_929),
    .O(\NlwInverterSignal_U1/Channel1<5>_MC.D2_PT_0/IN1 )
  );
  X_INV \NlwInverterBlock_U1/Channel1<5>_MC.D2_PT_1/IN1  (
    .I(\U1/Zero1 ),
    .O(\NlwInverterSignal_U1/Channel1<5>_MC.D2_PT_1/IN1 )
  );
  X_INV \NlwInverterBlock_U1/Channel1<5>_MC.D2_PT_1/IN3  (
    .I(\U1/U6/CurrState_Sreg0_FFD2 ),
    .O(\NlwInverterSignal_U1/Channel1<5>_MC.D2_PT_1/IN3 )
  );
  X_INV \NlwInverterBlock_U1/Channel1<5>_MC.D2_PT_1/IN4  (
    .I(\U1/U5/location_Maddsub__n0000__n0067 [0]),
    .O(\NlwInverterSignal_U1/Channel1<5>_MC.D2_PT_1/IN4 )
  );
  X_INV \NlwInverterBlock_U1/Channel1<5>_MC.D2_PT_2/IN1  (
    .I(\U1/Zero1 ),
    .O(\NlwInverterSignal_U1/Channel1<5>_MC.D2_PT_2/IN1 )
  );
  X_INV \NlwInverterBlock_U1/Channel1<5>_MC.D2_PT_2/IN3  (
    .I(\U1/U6/CurrState_Sreg0_FFD2 ),
    .O(\NlwInverterSignal_U1/Channel1<5>_MC.D2_PT_2/IN3 )
  );
  X_INV \NlwInverterBlock_U1/Channel1<5>_MC.D2_PT_2/IN5  (
    .I(N_PZ_921),
    .O(\NlwInverterSignal_U1/Channel1<5>_MC.D2_PT_2/IN5 )
  );
  X_INV \NlwInverterBlock_N_PZ_929_MC.D1/IN1  (
    .I(\U1/Zero1 ),
    .O(\NlwInverterSignal_N_PZ_929_MC.D1/IN1 )
  );
  X_INV \NlwInverterBlock_U1/Zero1_MC.D2_PT_0/IN0  (
    .I(\MSPReset_II/UIM ),
    .O(\NlwInverterSignal_U1/Zero1_MC.D2_PT_0/IN0 )
  );
  X_INV \NlwInverterBlock_U1/Zero1_MC.D2_PT_3/IN1  (
    .I(DCORIFGw),
    .O(\NlwInverterSignal_U1/Zero1_MC.D2_PT_3/IN1 )
  );
  X_INV \NlwInverterBlock_U1/Zero1_MC.D2_PT_3/IN2  (
    .I(DCORENCCTLw),
    .O(\NlwInverterSignal_U1/Zero1_MC.D2_PT_3/IN2 )
  );
  X_INV \NlwInverterBlock_U1/Zero1_MC.D2_PT_3/IN3  (
    .I(NET2493),
    .O(\NlwInverterSignal_U1/Zero1_MC.D2_PT_3/IN3 )
  );
  X_INV \NlwInverterBlock_U1/Zero1_MC.D2_PT_3/IN7  (
    .I(\U1/U4/HE1statelastr ),
    .O(\NlwInverterSignal_U1/Zero1_MC.D2_PT_3/IN7 )
  );
  X_INV \NlwInverterBlock_U1/Zero1_MC.D2_PT_4/IN1  (
    .I(DCORIFGw),
    .O(\NlwInverterSignal_U1/Zero1_MC.D2_PT_4/IN1 )
  );
  X_INV \NlwInverterBlock_U1/Zero1_MC.D2_PT_4/IN2  (
    .I(DCORENCCTLw),
    .O(\NlwInverterSignal_U1/Zero1_MC.D2_PT_4/IN2 )
  );
  X_INV \NlwInverterBlock_U1/Zero1_MC.D2_PT_4/IN3  (
    .I(NET2493),
    .O(\NlwInverterSignal_U1/Zero1_MC.D2_PT_4/IN3 )
  );
  X_INV \NlwInverterBlock_U1/Zero1_MC.D2_PT_4/IN4  (
    .I(\U1/U4/RF1r ),
    .O(\NlwInverterSignal_U1/Zero1_MC.D2_PT_4/IN4 )
  );
  X_INV \NlwInverterBlock_U1/Zero1_MC.D2_PT_4/IN6  (
    .I(\U1/U4/HE1stater ),
    .O(\NlwInverterSignal_U1/Zero1_MC.D2_PT_4/IN6 )
  );
  X_INV \NlwInverterBlock_NET2493_MC.D2_PT_0/IN0  (
    .I(\MSPReset_II/UIM ),
    .O(\NlwInverterSignal_NET2493_MC.D2_PT_0/IN0 )
  );
  X_INV \NlwInverterBlock_NET2493_MC.D2_PT_1/IN2  (
    .I(DCORENCCTLw),
    .O(\NlwInverterSignal_NET2493_MC.D2_PT_1/IN2 )
  );
  X_INV \NlwInverterBlock_NET2493_MC.D2_PT_2/IN1  (
    .I(DCORIFGw),
    .O(\NlwInverterSignal_NET2493_MC.D2_PT_2/IN1 )
  );
  X_INV \NlwInverterBlock_NET2493_MC.D2_PT_2/IN2  (
    .I(DCORENCCTLw),
    .O(\NlwInverterSignal_NET2493_MC.D2_PT_2/IN2 )
  );
  X_INV \NlwInverterBlock_NET2493_MC.D2_PT_2/IN3  (
    .I(NET2493),
    .O(\NlwInverterSignal_NET2493_MC.D2_PT_2/IN3 )
  );
  X_INV \NlwInverterBlock_NET2493_MC.D2_PT_2/IN7  (
    .I(\U1/U4/HE1statelastr ),
    .O(\NlwInverterSignal_NET2493_MC.D2_PT_2/IN7 )
  );
  X_INV \NlwInverterBlock_NET2493_MC.D2_PT_3/IN1  (
    .I(DCORIFGw),
    .O(\NlwInverterSignal_NET2493_MC.D2_PT_3/IN1 )
  );
  X_INV \NlwInverterBlock_NET2493_MC.D2_PT_3/IN2  (
    .I(DCORENCCTLw),
    .O(\NlwInverterSignal_NET2493_MC.D2_PT_3/IN2 )
  );
  X_INV \NlwInverterBlock_NET2493_MC.D2_PT_3/IN3  (
    .I(NET2493),
    .O(\NlwInverterSignal_NET2493_MC.D2_PT_3/IN3 )
  );
  X_INV \NlwInverterBlock_NET2493_MC.D2_PT_3/IN4  (
    .I(\U1/U4/RF1r ),
    .O(\NlwInverterSignal_NET2493_MC.D2_PT_3/IN4 )
  );
  X_INV \NlwInverterBlock_NET2493_MC.D2_PT_3/IN6  (
    .I(\U1/U4/HE1stater ),
    .O(\NlwInverterSignal_NET2493_MC.D2_PT_3/IN6 )
  );
  X_INV \NlwInverterBlock_U1/U4/RF1r_MC.D2_PT_1/IN1  (
    .I(DCORENCCTLw),
    .O(\NlwInverterSignal_U1/U4/RF1r_MC.D2_PT_1/IN1 )
  );
  X_INV \NlwInverterBlock_U1/U4/E1r_MC.D2_PT_1/IN1  (
    .I(DCORENCCTLw),
    .O(\NlwInverterSignal_U1/U4/E1r_MC.D2_PT_1/IN1 )
  );
  X_INV \NlwInverterBlock_U1/U6/CurrState_Sreg0_FFD3_MC.D2_PT_0/IN3  (
    .I(\PhaseA_Encoder1_II/UIM ),
    .O(\NlwInverterSignal_U1/U6/CurrState_Sreg0_FFD3_MC.D2_PT_0/IN3 )
  );
  X_INV \NlwInverterBlock_U1/U6/CurrState_Sreg0_FFD3_MC.D2_PT_0/IN4  (
    .I(\U1/U6/CurrState_Sreg0_FFD4 ),
    .O(\NlwInverterSignal_U1/U6/CurrState_Sreg0_FFD3_MC.D2_PT_0/IN4 )
  );
  X_INV \NlwInverterBlock_U1/U6/CurrState_Sreg0_FFD3_MC.D2_PT_1/IN2  (
    .I(\U1/U6/CurrState_Sreg0_FFD2 ),
    .O(\NlwInverterSignal_U1/U6/CurrState_Sreg0_FFD3_MC.D2_PT_1/IN2 )
  );
  X_INV \NlwInverterBlock_U1/U6/CurrState_Sreg0_FFD3_MC.D2_PT_1/IN3  (
    .I(\U1/U6/CurrState_Sreg0_FFD4 ),
    .O(\NlwInverterSignal_U1/U6/CurrState_Sreg0_FFD3_MC.D2_PT_1/IN3 )
  );
  X_INV \NlwInverterBlock_U1/U6/CurrState_Sreg0_FFD3_MC.D2_PT_1/IN4  (
    .I(\U1/U6/CurrState_Sreg0_FFD1 ),
    .O(\NlwInverterSignal_U1/U6/CurrState_Sreg0_FFD3_MC.D2_PT_1/IN4 )
  );
  X_INV \NlwInverterBlock_U1/U6/CurrState_Sreg0_FFD3_MC.D2_PT_2/IN3  (
    .I(\U1/U6/CurrState_Sreg0_FFD4 ),
    .O(\NlwInverterSignal_U1/U6/CurrState_Sreg0_FFD3_MC.D2_PT_2/IN3 )
  );
  X_INV \NlwInverterBlock_U1/U6/CurrState_Sreg0_FFD3_MC.D2_PT_2/IN5  (
    .I(\PhaseB_Encoder1_II/UIM ),
    .O(\NlwInverterSignal_U1/U6/CurrState_Sreg0_FFD3_MC.D2_PT_2/IN5 )
  );
  X_INV \NlwInverterBlock_U1/U6/CurrState_Sreg0_FFD3_MC.D2_PT_3/IN3  (
    .I(\U1/U6/CurrState_Sreg0_FFD4 ),
    .O(\NlwInverterSignal_U1/U6/CurrState_Sreg0_FFD3_MC.D2_PT_3/IN3 )
  );
  X_INV \NlwInverterBlock_U1/U6/CurrState_Sreg0_FFD3_MC.D2_PT_3/IN4  (
    .I(\U1/U6/CurrState_Sreg0_FFD1 ),
    .O(\NlwInverterSignal_U1/U6/CurrState_Sreg0_FFD3_MC.D2_PT_3/IN4 )
  );
  X_INV \NlwInverterBlock_U1/U6/CurrState_Sreg0_FFD1_MC.D2_PT_0/IN2  (
    .I(\U1/U6/CurrState_Sreg0_FFD4 ),
    .O(\NlwInverterSignal_U1/U6/CurrState_Sreg0_FFD1_MC.D2_PT_0/IN2 )
  );
  X_INV \NlwInverterBlock_U1/U6/CurrState_Sreg0_FFD1_MC.D2_PT_1/IN1  (
    .I(\U1/U6/CurrState_Sreg0_FFD3 ),
    .O(\NlwInverterSignal_U1/U6/CurrState_Sreg0_FFD1_MC.D2_PT_1/IN1 )
  );
  X_INV \NlwInverterBlock_U1/U6/CurrState_Sreg0_FFD1_MC.D2_PT_1/IN3  (
    .I(\U1/U6/CurrState_Sreg0_FFD4 ),
    .O(\NlwInverterSignal_U1/U6/CurrState_Sreg0_FFD1_MC.D2_PT_1/IN3 )
  );
  X_INV \NlwInverterBlock_U1/U6/CurrState_Sreg0_FFD1_MC.D2_PT_2/IN1  (
    .I(\U1/U6/CurrState_Sreg0_FFD3 ),
    .O(\NlwInverterSignal_U1/U6/CurrState_Sreg0_FFD1_MC.D2_PT_2/IN1 )
  );
  X_INV \NlwInverterBlock_U1/U6/CurrState_Sreg0_FFD1_MC.D2_PT_2/IN2  (
    .I(\U1/U6/CurrState_Sreg0_FFD2 ),
    .O(\NlwInverterSignal_U1/U6/CurrState_Sreg0_FFD1_MC.D2_PT_2/IN2 )
  );
  X_INV \NlwInverterBlock_U1/U6/CurrState_Sreg0_FFD1_MC.D2_PT_2/IN3  (
    .I(\PhaseA_Encoder1_II/UIM ),
    .O(\NlwInverterSignal_U1/U6/CurrState_Sreg0_FFD1_MC.D2_PT_2/IN3 )
  );
  X_INV \NlwInverterBlock_U1/U6/CurrState_Sreg0_FFD1_MC.D2_PT_2/IN4  (
    .I(\U1/U6/CurrState_Sreg0_FFD4 ),
    .O(\NlwInverterSignal_U1/U6/CurrState_Sreg0_FFD1_MC.D2_PT_2/IN4 )
  );
  X_INV \NlwInverterBlock_U1/U6/CurrState_Sreg0_FFD4_MC.D1/IN2  (
    .I(\U1/U6/CurrState_Sreg0_FFD2 ),
    .O(\NlwInverterSignal_U1/U6/CurrState_Sreg0_FFD4_MC.D1/IN2 )
  );
  X_INV \NlwInverterBlock_U1/U6/CurrState_Sreg0_FFD4_MC.D1/IN3  (
    .I(\PhaseA_Encoder1_II/UIM ),
    .O(\NlwInverterSignal_U1/U6/CurrState_Sreg0_FFD4_MC.D1/IN3 )
  );
  X_INV \NlwInverterBlock_U1/U6/CurrState_Sreg0_FFD4_MC.D1/IN4  (
    .I(\U1/U6/CurrState_Sreg0_FFD4 ),
    .O(\NlwInverterSignal_U1/U6/CurrState_Sreg0_FFD4_MC.D1/IN4 )
  );
  X_INV \NlwInverterBlock_U1/U6/CurrState_Sreg0_FFD4_MC.D1/IN5  (
    .I(\U1/U6/CurrState_Sreg0_FFD1 ),
    .O(\NlwInverterSignal_U1/U6/CurrState_Sreg0_FFD4_MC.D1/IN5 )
  );
  X_INV \NlwInverterBlock_U1/U6/CurrState_Sreg0_FFD4_MC.D1/IN6  (
    .I(\PhaseB_Encoder1_II/UIM ),
    .O(\NlwInverterSignal_U1/U6/CurrState_Sreg0_FFD4_MC.D1/IN6 )
  );
  X_INV \NlwInverterBlock_U1/U6/CurrState_Sreg0_FFD2_MC.D2_PT_0/IN3  (
    .I(\U1/U6/CurrState_Sreg0_FFD4 ),
    .O(\NlwInverterSignal_U1/U6/CurrState_Sreg0_FFD2_MC.D2_PT_0/IN3 )
  );
  X_INV \NlwInverterBlock_U1/U6/CurrState_Sreg0_FFD2_MC.D2_PT_1/IN3  (
    .I(\U1/U6/CurrState_Sreg0_FFD4 ),
    .O(\NlwInverterSignal_U1/U6/CurrState_Sreg0_FFD2_MC.D2_PT_1/IN3 )
  );
  X_INV \NlwInverterBlock_U1/U6/CurrState_Sreg0_FFD2_MC.D2_PT_1/IN4  (
    .I(\U1/U6/CurrState_Sreg0_FFD1 ),
    .O(\NlwInverterSignal_U1/U6/CurrState_Sreg0_FFD2_MC.D2_PT_1/IN4 )
  );
  X_INV \NlwInverterBlock_U1/U6/CurrState_Sreg0_FFD2_MC.D2_PT_1/IN5  (
    .I(\PhaseB_Encoder1_II/UIM ),
    .O(\NlwInverterSignal_U1/U6/CurrState_Sreg0_FFD2_MC.D2_PT_1/IN5 )
  );
  X_INV \NlwInverterBlock_U1/U6/CurrState_Sreg0_FFD2_MC.D2_PT_2/IN3  (
    .I(\U1/U6/CurrState_Sreg0_FFD4 ),
    .O(\NlwInverterSignal_U1/U6/CurrState_Sreg0_FFD2_MC.D2_PT_2/IN3 )
  );
  X_INV \NlwInverterBlock_U1/U6/CurrState_Sreg0_FFD2_MC.D2_PT_2/IN4  (
    .I(\U1/U6/CurrState_Sreg0_FFD1 ),
    .O(\NlwInverterSignal_U1/U6/CurrState_Sreg0_FFD2_MC.D2_PT_2/IN4 )
  );
  X_INV \NlwInverterBlock_U1/U6/CurrState_Sreg0_FFD2_MC.D2_PT_3/IN1  (
    .I(\U1/U6/CurrState_Sreg0_FFD3 ),
    .O(\NlwInverterSignal_U1/U6/CurrState_Sreg0_FFD2_MC.D2_PT_3/IN1 )
  );
  X_INV \NlwInverterBlock_U1/U6/CurrState_Sreg0_FFD2_MC.D2_PT_3/IN3  (
    .I(\U1/U6/CurrState_Sreg0_FFD4 ),
    .O(\NlwInverterSignal_U1/U6/CurrState_Sreg0_FFD2_MC.D2_PT_3/IN3 )
  );
  X_INV \NlwInverterBlock_U1/U6/CurrState_Sreg0_FFD2_MC.D2_PT_3/IN5  (
    .I(\PhaseB_Encoder1_II/UIM ),
    .O(\NlwInverterSignal_U1/U6/CurrState_Sreg0_FFD2_MC.D2_PT_3/IN5 )
  );
  X_INV \NlwInverterBlock_U1/U6/CurrState_Sreg0_FFD2_MC.D2_PT_4/IN1  (
    .I(\U1/U6/CurrState_Sreg0_FFD3 ),
    .O(\NlwInverterSignal_U1/U6/CurrState_Sreg0_FFD2_MC.D2_PT_4/IN1 )
  );
  X_INV \NlwInverterBlock_U1/U6/CurrState_Sreg0_FFD2_MC.D2_PT_4/IN3  (
    .I(\U1/U6/CurrState_Sreg0_FFD4 ),
    .O(\NlwInverterSignal_U1/U6/CurrState_Sreg0_FFD2_MC.D2_PT_4/IN3 )
  );
  X_INV \NlwInverterBlock_U1/U6/CurrState_Sreg0_FFD2_MC.D2_PT_4/IN4  (
    .I(\U1/U6/CurrState_Sreg0_FFD1 ),
    .O(\NlwInverterSignal_U1/U6/CurrState_Sreg0_FFD2_MC.D2_PT_4/IN4 )
  );
  X_INV \NlwInverterBlock_U1/U6/CurrState_Sreg0_FFD2_MC.D2_PT_5/IN1  (
    .I(\U1/U6/CurrState_Sreg0_FFD3 ),
    .O(\NlwInverterSignal_U1/U6/CurrState_Sreg0_FFD2_MC.D2_PT_5/IN1 )
  );
  X_INV \NlwInverterBlock_U1/U6/CurrState_Sreg0_FFD2_MC.D2_PT_5/IN3  (
    .I(\U1/U6/CurrState_Sreg0_FFD4 ),
    .O(\NlwInverterSignal_U1/U6/CurrState_Sreg0_FFD2_MC.D2_PT_5/IN3 )
  );
  X_INV \NlwInverterBlock_U1/U6/CurrState_Sreg0_FFD2_MC.D2_PT_6/IN1  (
    .I(\U1/U6/CurrState_Sreg0_FFD3 ),
    .O(\NlwInverterSignal_U1/U6/CurrState_Sreg0_FFD2_MC.D2_PT_6/IN1 )
  );
  X_INV \NlwInverterBlock_U1/U6/CurrState_Sreg0_FFD2_MC.D2_PT_6/IN3  (
    .I(\U1/U6/CurrState_Sreg0_FFD4 ),
    .O(\NlwInverterSignal_U1/U6/CurrState_Sreg0_FFD2_MC.D2_PT_6/IN3 )
  );
  X_INV \NlwInverterBlock_U1/U6/CurrState_Sreg0_FFD2_MC.D2_PT_6/IN4  (
    .I(\U1/U6/CurrState_Sreg0_FFD1 ),
    .O(\NlwInverterSignal_U1/U6/CurrState_Sreg0_FFD2_MC.D2_PT_6/IN4 )
  );
  X_INV \NlwInverterBlock_U1/U6/CurrState_Sreg0_FFD2_MC.D2_PT_6/IN5  (
    .I(\PhaseB_Encoder1_II/UIM ),
    .O(\NlwInverterSignal_U1/U6/CurrState_Sreg0_FFD2_MC.D2_PT_6/IN5 )
  );
  X_INV \NlwInverterBlock_U1/U6/CurrState_Sreg0_FFD2_MC.D2_PT_7/IN3  (
    .I(\U1/U6/CurrState_Sreg0_FFD4 ),
    .O(\NlwInverterSignal_U1/U6/CurrState_Sreg0_FFD2_MC.D2_PT_7/IN3 )
  );
  X_INV \NlwInverterBlock_U1/U6/CurrState_Sreg0_FFD2_MC.D2_PT_7/IN5  (
    .I(\PhaseB_Encoder1_II/UIM ),
    .O(\NlwInverterSignal_U1/U6/CurrState_Sreg0_FFD2_MC.D2_PT_7/IN5 )
  );
  X_INV \NlwInverterBlock_U1/U5/location_Maddsub__n0000__n0067<0>_MC.D2_PT_1/IN0  (
    .I(N_PZ_944),
    .O(\NlwInverterSignal_U1/U5/location_Maddsub__n0000__n0067<0>_MC.D2_PT_1/IN0 )
  );
  X_INV \NlwInverterBlock_U1/U5/location_Maddsub__n0000__n0067<0>_MC.D2_PT_1/IN1  (
    .I(\U1/Channel1 [0]),
    .O(\NlwInverterSignal_U1/U5/location_Maddsub__n0000__n0067<0>_MC.D2_PT_1/IN1 )
  );
  X_INV \NlwInverterBlock_U1/U5/location_Maddsub__n0000__n0067<0>_MC.D2_PT_1/IN2  (
    .I(\U1/Channel1 [1]),
    .O(\NlwInverterSignal_U1/U5/location_Maddsub__n0000__n0067<0>_MC.D2_PT_1/IN2 )
  );
  X_INV \NlwInverterBlock_U1/U5/location_Maddsub__n0000__n0067<0>_MC.D2_PT_1/IN3  (
    .I(\U1/Channel1 [2]),
    .O(\NlwInverterSignal_U1/U5/location_Maddsub__n0000__n0067<0>_MC.D2_PT_1/IN3 )
  );
  X_INV \NlwInverterBlock_U1/U5/location_Maddsub__n0000__n0067<0>_MC.D2_PT_1/IN4  (
    .I(\U1/Channel1 [3]),
    .O(\NlwInverterSignal_U1/U5/location_Maddsub__n0000__n0067<0>_MC.D2_PT_1/IN4 )
  );
  X_INV \NlwInverterBlock_U1/U5/location_Maddsub__n0000__n0067<0>_MC.D2_PT_1/IN5  (
    .I(\U1/Channel1 [4]),
    .O(\NlwInverterSignal_U1/U5/location_Maddsub__n0000__n0067<0>_MC.D2_PT_1/IN5 )
  );
  X_INV \NlwInverterBlock_N_PZ_944_MC.D2_PT_0/IN1  (
    .I(\U1/U6/CurrState_Sreg0_FFD2 ),
    .O(\NlwInverterSignal_N_PZ_944_MC.D2_PT_0/IN1 )
  );
  X_INV \NlwInverterBlock_N_PZ_944_MC.D2_PT_0/IN2  (
    .I(\U1/U6/CurrState_Sreg0_FFD1 ),
    .O(\NlwInverterSignal_N_PZ_944_MC.D2_PT_0/IN2 )
  );
  X_INV \NlwInverterBlock_N_PZ_944_MC.D2_PT_1/IN1  (
    .I(\U1/U6/CurrState_Sreg0_FFD4 ),
    .O(\NlwInverterSignal_N_PZ_944_MC.D2_PT_1/IN1 )
  );
  X_INV \NlwInverterBlock_N_PZ_944_MC.D2_PT_1/IN2  (
    .I(\U1/U6/CurrState_Sreg0_FFD1 ),
    .O(\NlwInverterSignal_N_PZ_944_MC.D2_PT_1/IN2 )
  );
  X_INV \NlwInverterBlock_U1/NET3720_MC.D2_PT_1/IN1  (
    .I(DCORENCCTLw),
    .O(\NlwInverterSignal_U1/NET3720_MC.D2_PT_1/IN1 )
  );
  X_INV \NlwInverterBlock_U1/Channel1<0>_MC.D2_PT_0/IN0  (
    .I(N_PZ_929),
    .O(\NlwInverterSignal_U1/Channel1<0>_MC.D2_PT_0/IN0 )
  );
  X_INV \NlwInverterBlock_U1/Channel1<0>_MC.D2_PT_1/IN1  (
    .I(\U1/Zero1 ),
    .O(\NlwInverterSignal_U1/Channel1<0>_MC.D2_PT_1/IN1 )
  );
  X_INV \NlwInverterBlock_U1/Channel1<0>_MC.D2_PT_1/IN3  (
    .I(\U1/U6/CurrState_Sreg0_FFD2 ),
    .O(\NlwInverterSignal_U1/Channel1<0>_MC.D2_PT_1/IN3 )
  );
  X_INV \NlwInverterBlock_N_PZ_1092_MC.D2_PT_0/IN1  (
    .I(\U1/U6/CurrState_Sreg0_FFD1 ),
    .O(\NlwInverterSignal_N_PZ_1092_MC.D2_PT_0/IN1 )
  );
  X_INV \NlwInverterBlock_N_PZ_1092_MC.D2_PT_1/IN0  (
    .I(\U1/U6/CurrState_Sreg0_FFD4 ),
    .O(\NlwInverterSignal_N_PZ_1092_MC.D2_PT_1/IN0 )
  );
  X_INV \NlwInverterBlock_U1/Channel1<1>_MC.D2_PT_0/IN0  (
    .I(N_PZ_929),
    .O(\NlwInverterSignal_U1/Channel1<1>_MC.D2_PT_0/IN0 )
  );
  X_INV \NlwInverterBlock_U1/Channel1<1>_MC.D2_PT_1/IN1  (
    .I(\U1/Zero1 ),
    .O(\NlwInverterSignal_U1/Channel1<1>_MC.D2_PT_1/IN1 )
  );
  X_INV \NlwInverterBlock_U1/Channel1<1>_MC.D2_PT_1/IN3  (
    .I(\U1/U6/CurrState_Sreg0_FFD2 ),
    .O(\NlwInverterSignal_U1/Channel1<1>_MC.D2_PT_1/IN3 )
  );
  X_INV \NlwInverterBlock_U1/Channel1<1>_MC.D2_PT_2/IN1  (
    .I(\U1/Zero1 ),
    .O(\NlwInverterSignal_U1/Channel1<1>_MC.D2_PT_2/IN1 )
  );
  X_INV \NlwInverterBlock_U1/Channel1<1>_MC.D2_PT_2/IN3  (
    .I(\U1/U6/CurrState_Sreg0_FFD2 ),
    .O(\NlwInverterSignal_U1/Channel1<1>_MC.D2_PT_2/IN3 )
  );
  X_INV \NlwInverterBlock_U1/Channel1<1>_MC.D2_PT_2/IN4  (
    .I(N_PZ_921),
    .O(\NlwInverterSignal_U1/Channel1<1>_MC.D2_PT_2/IN4 )
  );
  X_INV \NlwInverterBlock_U1/Channel1<1>_MC.D2_PT_2/IN6  (
    .I(\U1/Channel1 [0]),
    .O(\NlwInverterSignal_U1/Channel1<1>_MC.D2_PT_2/IN6 )
  );
  X_INV \NlwInverterBlock_N_PZ_921_MC.D2_PT_0/IN1  (
    .I(\U1/U6/CurrState_Sreg0_FFD1 ),
    .O(\NlwInverterSignal_N_PZ_921_MC.D2_PT_0/IN1 )
  );
  X_INV \NlwInverterBlock_N_PZ_921_MC.D2_PT_0/IN2  (
    .I(\U1/NET3720 ),
    .O(\NlwInverterSignal_N_PZ_921_MC.D2_PT_0/IN2 )
  );
  X_INV \NlwInverterBlock_N_PZ_921_MC.D2_PT_1/IN0  (
    .I(\U1/U6/CurrState_Sreg0_FFD4 ),
    .O(\NlwInverterSignal_N_PZ_921_MC.D2_PT_1/IN0 )
  );
  X_INV \NlwInverterBlock_U1/Channel1<2>_MC.D2_PT_0/IN0  (
    .I(N_PZ_929),
    .O(\NlwInverterSignal_U1/Channel1<2>_MC.D2_PT_0/IN0 )
  );
  X_INV \NlwInverterBlock_U1/Channel1<2>_MC.D2_PT_1/IN1  (
    .I(\U1/Zero1 ),
    .O(\NlwInverterSignal_U1/Channel1<2>_MC.D2_PT_1/IN1 )
  );
  X_INV \NlwInverterBlock_U1/Channel1<2>_MC.D2_PT_1/IN3  (
    .I(\U1/U6/CurrState_Sreg0_FFD2 ),
    .O(\NlwInverterSignal_U1/Channel1<2>_MC.D2_PT_1/IN3 )
  );
  X_INV \NlwInverterBlock_U1/Channel1<2>_MC.D2_PT_2/IN1  (
    .I(\U1/Zero1 ),
    .O(\NlwInverterSignal_U1/Channel1<2>_MC.D2_PT_2/IN1 )
  );
  X_INV \NlwInverterBlock_U1/Channel1<2>_MC.D2_PT_2/IN3  (
    .I(\U1/U6/CurrState_Sreg0_FFD2 ),
    .O(\NlwInverterSignal_U1/Channel1<2>_MC.D2_PT_2/IN3 )
  );
  X_INV \NlwInverterBlock_U1/Channel1<2>_MC.D2_PT_2/IN4  (
    .I(N_PZ_921),
    .O(\NlwInverterSignal_U1/Channel1<2>_MC.D2_PT_2/IN4 )
  );
  X_INV \NlwInverterBlock_U1/Channel1<2>_MC.D2_PT_2/IN6  (
    .I(\U1/Channel1 [0]),
    .O(\NlwInverterSignal_U1/Channel1<2>_MC.D2_PT_2/IN6 )
  );
  X_INV \NlwInverterBlock_U1/Channel1<2>_MC.D2_PT_2/IN7  (
    .I(\U1/Channel1 [1]),
    .O(\NlwInverterSignal_U1/Channel1<2>_MC.D2_PT_2/IN7 )
  );
  X_INV \NlwInverterBlock_U1/Channel1<3>_MC.D2_PT_0/IN0  (
    .I(N_PZ_929),
    .O(\NlwInverterSignal_U1/Channel1<3>_MC.D2_PT_0/IN0 )
  );
  X_INV \NlwInverterBlock_U1/Channel1<3>_MC.D2_PT_1/IN1  (
    .I(\U1/Zero1 ),
    .O(\NlwInverterSignal_U1/Channel1<3>_MC.D2_PT_1/IN1 )
  );
  X_INV \NlwInverterBlock_U1/Channel1<3>_MC.D2_PT_1/IN3  (
    .I(\U1/U6/CurrState_Sreg0_FFD2 ),
    .O(\NlwInverterSignal_U1/Channel1<3>_MC.D2_PT_1/IN3 )
  );
  X_INV \NlwInverterBlock_U1/Channel1<3>_MC.D2_PT_2/IN1  (
    .I(\U1/Zero1 ),
    .O(\NlwInverterSignal_U1/Channel1<3>_MC.D2_PT_2/IN1 )
  );
  X_INV \NlwInverterBlock_U1/Channel1<3>_MC.D2_PT_2/IN3  (
    .I(\U1/U6/CurrState_Sreg0_FFD2 ),
    .O(\NlwInverterSignal_U1/Channel1<3>_MC.D2_PT_2/IN3 )
  );
  X_INV \NlwInverterBlock_U1/Channel1<3>_MC.D2_PT_2/IN4  (
    .I(N_PZ_921),
    .O(\NlwInverterSignal_U1/Channel1<3>_MC.D2_PT_2/IN4 )
  );
  X_INV \NlwInverterBlock_U1/Channel1<3>_MC.D2_PT_2/IN6  (
    .I(\U1/Channel1 [0]),
    .O(\NlwInverterSignal_U1/Channel1<3>_MC.D2_PT_2/IN6 )
  );
  X_INV \NlwInverterBlock_U1/Channel1<3>_MC.D2_PT_2/IN7  (
    .I(\U1/Channel1 [1]),
    .O(\NlwInverterSignal_U1/Channel1<3>_MC.D2_PT_2/IN7 )
  );
  X_INV \NlwInverterBlock_U1/Channel1<3>_MC.D2_PT_2/IN8  (
    .I(\U1/Channel1 [2]),
    .O(\NlwInverterSignal_U1/Channel1<3>_MC.D2_PT_2/IN8 )
  );
  X_INV \NlwInverterBlock_U1/Channel1<4>_MC.D2_PT_0/IN0  (
    .I(N_PZ_929),
    .O(\NlwInverterSignal_U1/Channel1<4>_MC.D2_PT_0/IN0 )
  );
  X_INV \NlwInverterBlock_U1/Channel1<4>_MC.D2_PT_1/IN1  (
    .I(\U1/U6/CurrState_Sreg0_FFD2 ),
    .O(\NlwInverterSignal_U1/Channel1<4>_MC.D2_PT_1/IN1 )
  );
  X_INV \NlwInverterBlock_U1/Channel1<4>_MC.D2_PT_1/IN2  (
    .I(\U1/U5/location_Maddsub__n0000__n0067 [0]),
    .O(\NlwInverterSignal_U1/Channel1<4>_MC.D2_PT_1/IN2 )
  );
  X_INV \NlwInverterBlock_U1/Channel1<4>_MC.D2_PT_1/IN4  (
    .I(\U1/Channel1 [0]),
    .O(\NlwInverterSignal_U1/Channel1<4>_MC.D2_PT_1/IN4 )
  );
  X_INV \NlwInverterBlock_U1/Channel1<4>_MC.D2_PT_2/IN1  (
    .I(\U1/U6/CurrState_Sreg0_FFD2 ),
    .O(\NlwInverterSignal_U1/Channel1<4>_MC.D2_PT_2/IN1 )
  );
  X_INV \NlwInverterBlock_U1/Channel1<4>_MC.D2_PT_2/IN2  (
    .I(\U1/U5/location_Maddsub__n0000__n0067 [0]),
    .O(\NlwInverterSignal_U1/Channel1<4>_MC.D2_PT_2/IN2 )
  );
  X_INV \NlwInverterBlock_U1/Channel1<4>_MC.D2_PT_2/IN4  (
    .I(\U1/Channel1 [1]),
    .O(\NlwInverterSignal_U1/Channel1<4>_MC.D2_PT_2/IN4 )
  );
  X_INV \NlwInverterBlock_U1/Channel1<4>_MC.D2_PT_3/IN1  (
    .I(\U1/U6/CurrState_Sreg0_FFD2 ),
    .O(\NlwInverterSignal_U1/Channel1<4>_MC.D2_PT_3/IN1 )
  );
  X_INV \NlwInverterBlock_U1/Channel1<4>_MC.D2_PT_3/IN2  (
    .I(\U1/U5/location_Maddsub__n0000__n0067 [0]),
    .O(\NlwInverterSignal_U1/Channel1<4>_MC.D2_PT_3/IN2 )
  );
  X_INV \NlwInverterBlock_U1/Channel1<4>_MC.D2_PT_3/IN4  (
    .I(\U1/Channel1 [2]),
    .O(\NlwInverterSignal_U1/Channel1<4>_MC.D2_PT_3/IN4 )
  );
  X_INV \NlwInverterBlock_U1/Channel1<4>_MC.D2_PT_4/IN1  (
    .I(\U1/U6/CurrState_Sreg0_FFD2 ),
    .O(\NlwInverterSignal_U1/Channel1<4>_MC.D2_PT_4/IN1 )
  );
  X_INV \NlwInverterBlock_U1/Channel1<4>_MC.D2_PT_4/IN2  (
    .I(\U1/U5/location_Maddsub__n0000__n0067 [0]),
    .O(\NlwInverterSignal_U1/Channel1<4>_MC.D2_PT_4/IN2 )
  );
  X_INV \NlwInverterBlock_U1/Channel1<4>_MC.D2_PT_5/IN1  (
    .I(\U1/Zero1 ),
    .O(\NlwInverterSignal_U1/Channel1<4>_MC.D2_PT_5/IN1 )
  );
  X_INV \NlwInverterBlock_U1/Channel1<4>_MC.D2_PT_5/IN3  (
    .I(\U1/U6/CurrState_Sreg0_FFD2 ),
    .O(\NlwInverterSignal_U1/Channel1<4>_MC.D2_PT_5/IN3 )
  );
  X_INV \NlwInverterBlock_U1/Channel1<4>_MC.D2_PT_5/IN5  (
    .I(N_PZ_921),
    .O(\NlwInverterSignal_U1/Channel1<4>_MC.D2_PT_5/IN5 )
  );
  X_INV \NlwInverterBlock_U1/Channel1<4>_MC.D2_PT_5/IN7  (
    .I(\U1/Channel1 [4]),
    .O(\NlwInverterSignal_U1/Channel1<4>_MC.D2_PT_5/IN7 )
  );
  X_INV \NlwInverterBlock_U1/Channel1<4>_MC.D2_PT_6/IN1  (
    .I(\U1/U6/CurrState_Sreg0_FFD2 ),
    .O(\NlwInverterSignal_U1/Channel1<4>_MC.D2_PT_6/IN1 )
  );
  X_INV \NlwInverterBlock_U1/Channel1<4>_MC.D2_PT_6/IN2  (
    .I(\U1/U5/location_Maddsub__n0000__n0067 [0]),
    .O(\NlwInverterSignal_U1/Channel1<4>_MC.D2_PT_6/IN2 )
  );
  X_INV \NlwInverterBlock_U1/Channel1<4>_MC.D2_PT_6/IN4  (
    .I(\U1/Channel1 [0]),
    .O(\NlwInverterSignal_U1/Channel1<4>_MC.D2_PT_6/IN4 )
  );
  X_INV \NlwInverterBlock_U1/Channel1<4>_MC.D2_PT_6/IN5  (
    .I(\U1/Channel1 [1]),
    .O(\NlwInverterSignal_U1/Channel1<4>_MC.D2_PT_6/IN5 )
  );
  X_INV \NlwInverterBlock_U1/Channel1<4>_MC.D2_PT_6/IN6  (
    .I(\U1/Channel1 [2]),
    .O(\NlwInverterSignal_U1/Channel1<4>_MC.D2_PT_6/IN6 )
  );
  X_INV \NlwInverterBlock_U1/Channel1<4>_MC.D2_PT_6/IN7  (
    .I(\U1/Channel1 [3]),
    .O(\NlwInverterSignal_U1/Channel1<4>_MC.D2_PT_6/IN7 )
  );
  X_INV \NlwInverterBlock_U1/Channel1<4>_MC.D2_PT_7/IN1  (
    .I(\U1/Zero1 ),
    .O(\NlwInverterSignal_U1/Channel1<4>_MC.D2_PT_7/IN1 )
  );
  X_INV \NlwInverterBlock_U1/Channel1<4>_MC.D2_PT_7/IN3  (
    .I(\U1/U6/CurrState_Sreg0_FFD2 ),
    .O(\NlwInverterSignal_U1/Channel1<4>_MC.D2_PT_7/IN3 )
  );
  X_INV \NlwInverterBlock_U1/Channel1<4>_MC.D2_PT_7/IN10  (
    .I(\U1/Channel1 [4]),
    .O(\NlwInverterSignal_U1/Channel1<4>_MC.D2_PT_7/IN10 )
  );
  X_INV \NlwInverterBlock_DCOR1CNTLOWr_MC.D1/IN1  (
    .I(\RD_II/UIM ),
    .O(\NlwInverterSignal_DCOR1CNTLOWr_MC.D1/IN1 )
  );
  X_INV \NlwInverterBlock_DCOR1CNTLOWr_MC.D1/IN2  (
    .I(U2_ADDR_reg[0]),
    .O(\NlwInverterSignal_DCOR1CNTLOWr_MC.D1/IN2 )
  );
  X_INV \NlwInverterBlock_DCOR1CNTLOWr_MC.D1/IN3  (
    .I(U2_ADDR_reg[4]),
    .O(\NlwInverterSignal_DCOR1CNTLOWr_MC.D1/IN3 )
  );
  X_INV \NlwInverterBlock_DCOR1CNTLOWr_MC.D1/IN4  (
    .I(U2_ADDR_reg[5]),
    .O(\NlwInverterSignal_DCOR1CNTLOWr_MC.D1/IN4 )
  );
  X_INV \NlwInverterBlock_DCOR1CNTLOWr_MC.D1/IN5  (
    .I(U2_ADDR_reg[6]),
    .O(\NlwInverterSignal_DCOR1CNTLOWr_MC.D1/IN5 )
  );
  X_INV \NlwInverterBlock_DCOR1CNTLOWr_MC.D1/IN6  (
    .I(U2_ADDR_reg[7]),
    .O(\NlwInverterSignal_DCOR1CNTLOWr_MC.D1/IN6 )
  );
  X_INV \NlwInverterBlock_DCOR1CNTLOWr_MC.D1/IN7  (
    .I(U2_ADDR_reg[3]),
    .O(\NlwInverterSignal_DCOR1CNTLOWr_MC.D1/IN7 )
  );
  X_INV \NlwInverterBlock_U1/U3/holdingreg0<13>_MC.D2_PT_1/IN1  (
    .I(\AS_II/UIM ),
    .O(\NlwInverterSignal_U1/U3/holdingreg0<13>_MC.D2_PT_1/IN1 )
  );
  X_INV \NlwInverterBlock_U1/Channel0<13>_MC.D2_PT_0/IN0  (
    .I(N_PZ_928),
    .O(\NlwInverterSignal_U1/Channel0<13>_MC.D2_PT_0/IN0 )
  );
  X_INV \NlwInverterBlock_U1/Channel0<13>_MC.D2_PT_1/IN1  (
    .I(\U1/Channel0 [10]),
    .O(\NlwInverterSignal_U1/Channel0<13>_MC.D2_PT_1/IN1 )
  );
  X_INV \NlwInverterBlock_U1/Channel0<13>_MC.D2_PT_1/IN2  (
    .I(\U1/Channel0 [9]),
    .O(\NlwInverterSignal_U1/Channel0<13>_MC.D2_PT_1/IN2 )
  );
  X_INV \NlwInverterBlock_U1/Channel0<13>_MC.D2_PT_1/IN4  (
    .I(\U1/Channel0 [11]),
    .O(\NlwInverterSignal_U1/Channel0<13>_MC.D2_PT_1/IN4 )
  );
  X_INV \NlwInverterBlock_U1/Channel0<13>_MC.D2_PT_1/IN5  (
    .I(\U1/Channel0 [12]),
    .O(\NlwInverterSignal_U1/Channel0<13>_MC.D2_PT_1/IN5 )
  );
  X_INV \NlwInverterBlock_U1/Channel0<13>_MC.D2_PT_2/IN3  (
    .I(\U1/U2/location_Maddsub__n0000__n0075 [0]),
    .O(\NlwInverterSignal_U1/Channel0<13>_MC.D2_PT_2/IN3 )
  );
  X_INV \NlwInverterBlock_U1/Channel0<10>_MC.D2_PT_0/IN0  (
    .I(N_PZ_928),
    .O(\NlwInverterSignal_U1/Channel0<10>_MC.D2_PT_0/IN0 )
  );
  X_INV \NlwInverterBlock_U1/Channel0<10>_MC.D2_PT_1/IN1  (
    .I(\U1/Channel0 [9]),
    .O(\NlwInverterSignal_U1/Channel0<10>_MC.D2_PT_1/IN1 )
  );
  X_INV \NlwInverterBlock_U1/Channel0<10>_MC.D2_PT_2/IN2  (
    .I(\U1/U2/location_Maddsub__n0000__n0075 [0]),
    .O(\NlwInverterSignal_U1/Channel0<10>_MC.D2_PT_2/IN2 )
  );
  X_INV \NlwInverterBlock_U1/Channel0<9>_MC.D2_PT_0/IN0  (
    .I(N_PZ_928),
    .O(\NlwInverterSignal_U1/Channel0<9>_MC.D2_PT_0/IN0 )
  );
  X_INV \NlwInverterBlock_U1/Channel0<9>_MC.D2_PT_2/IN1  (
    .I(\U1/U2/location_Maddsub__n0000__n0075 [0]),
    .O(\NlwInverterSignal_U1/Channel0<9>_MC.D2_PT_2/IN1 )
  );
  X_INV \NlwInverterBlock_U1/U2/location_Maddsub__n0000__n0075<0>_MC.D2_PT_0/IN1  (
    .I(\U1/U2/location_Maddsub__n0000__n0067 [0]),
    .O(\NlwInverterSignal_U1/U2/location_Maddsub__n0000__n0075<0>_MC.D2_PT_0/IN1 )
  );
  X_INV \NlwInverterBlock_U1/U2/location_Maddsub__n0000__n0075<0>_MC.D2_PT_1/IN0  (
    .I(\U1/Channel0 [5]),
    .O(\NlwInverterSignal_U1/U2/location_Maddsub__n0000__n0075<0>_MC.D2_PT_1/IN0 )
  );
  X_INV \NlwInverterBlock_U1/U2/location_Maddsub__n0000__n0075<0>_MC.D2_PT_1/IN2  (
    .I(N_PZ_943),
    .O(\NlwInverterSignal_U1/U2/location_Maddsub__n0000__n0075<0>_MC.D2_PT_1/IN2 )
  );
  X_INV \NlwInverterBlock_U1/U2/location_Maddsub__n0000__n0075<0>_MC.D2_PT_1/IN3  (
    .I(\U1/Channel0 [6]),
    .O(\NlwInverterSignal_U1/U2/location_Maddsub__n0000__n0075<0>_MC.D2_PT_1/IN3 )
  );
  X_INV \NlwInverterBlock_U1/U2/location_Maddsub__n0000__n0075<0>_MC.D2_PT_1/IN4  (
    .I(\U1/Channel0 [7]),
    .O(\NlwInverterSignal_U1/U2/location_Maddsub__n0000__n0075<0>_MC.D2_PT_1/IN4 )
  );
  X_INV \NlwInverterBlock_U1/U2/location_Maddsub__n0000__n0075<0>_MC.D2_PT_1/IN5  (
    .I(\U1/Channel0 [8]),
    .O(\NlwInverterSignal_U1/U2/location_Maddsub__n0000__n0075<0>_MC.D2_PT_1/IN5 )
  );
  X_INV \NlwInverterBlock_U1/Channel0<6>_MC.D2_PT_0/IN0  (
    .I(N_PZ_928),
    .O(\NlwInverterSignal_U1/Channel0<6>_MC.D2_PT_0/IN0 )
  );
  X_INV \NlwInverterBlock_U1/Channel0<6>_MC.D2_PT_1/IN1  (
    .I(\U1/U2/location_Maddsub__n0000__n0067 [0]),
    .O(\NlwInverterSignal_U1/Channel0<6>_MC.D2_PT_1/IN1 )
  );
  X_INV \NlwInverterBlock_U1/Channel0<6>_MC.D2_PT_2/IN0  (
    .I(\U1/Channel0 [5]),
    .O(\NlwInverterSignal_U1/Channel0<6>_MC.D2_PT_2/IN0 )
  );
  X_INV \NlwInverterBlock_U1/Channel0<7>_MC.D2_PT_0/IN0  (
    .I(N_PZ_928),
    .O(\NlwInverterSignal_U1/Channel0<7>_MC.D2_PT_0/IN0 )
  );
  X_INV \NlwInverterBlock_U1/Channel0<7>_MC.D2_PT_1/IN1  (
    .I(\U1/U2/location_Maddsub__n0000__n0067 [0]),
    .O(\NlwInverterSignal_U1/Channel0<7>_MC.D2_PT_1/IN1 )
  );
  X_INV \NlwInverterBlock_U1/Channel0<7>_MC.D2_PT_2/IN0  (
    .I(\U1/Channel0 [5]),
    .O(\NlwInverterSignal_U1/Channel0<7>_MC.D2_PT_2/IN0 )
  );
  X_INV \NlwInverterBlock_U1/Channel0<7>_MC.D2_PT_2/IN3  (
    .I(\U1/Channel0 [6]),
    .O(\NlwInverterSignal_U1/Channel0<7>_MC.D2_PT_2/IN3 )
  );
  X_INV \NlwInverterBlock_U1/Channel0<8>_MC.D1/IN1  (
    .I(\U1/U2/location_Maddsub__n0000__n0075 [0]),
    .O(\NlwInverterSignal_U1/Channel0<8>_MC.D1/IN1 )
  );
  X_INV \NlwInverterBlock_U1/Channel0<8>_MC.D2_PT_0/IN0  (
    .I(N_PZ_928),
    .O(\NlwInverterSignal_U1/Channel0<8>_MC.D2_PT_0/IN0 )
  );
  X_INV \NlwInverterBlock_U1/Channel0<8>_MC.D2_PT_0/IN1  (
    .I(N_PZ_968),
    .O(\NlwInverterSignal_U1/Channel0<8>_MC.D2_PT_0/IN1 )
  );
  X_INV \NlwInverterBlock_U1/Channel0<8>_MC.D2_PT_1/IN0  (
    .I(N_PZ_928),
    .O(\NlwInverterSignal_U1/Channel0<8>_MC.D2_PT_1/IN0 )
  );
  X_INV \NlwInverterBlock_U1/Channel0<8>_MC.D2_PT_2/IN2  (
    .I(\U1/Channel0 [8]),
    .O(\NlwInverterSignal_U1/Channel0<8>_MC.D2_PT_2/IN2 )
  );
  X_INV \NlwInverterBlock_U1/Channel0<8>_MC.D2_PT_3/IN1  (
    .I(\U1/U2/location_Maddsub__n0000__n0067 [0]),
    .O(\NlwInverterSignal_U1/Channel0<8>_MC.D2_PT_3/IN1 )
  );
  X_INV \NlwInverterBlock_U1/Channel0<8>_MC.D2_PT_3/IN6  (
    .I(\U1/Channel0 [8]),
    .O(\NlwInverterSignal_U1/Channel0<8>_MC.D2_PT_3/IN6 )
  );
  X_INV \NlwInverterBlock_U1/Channel0<8>_MC.D2_PT_4/IN0  (
    .I(\U1/Channel0 [5]),
    .O(\NlwInverterSignal_U1/Channel0<8>_MC.D2_PT_4/IN0 )
  );
  X_INV \NlwInverterBlock_U1/Channel0<8>_MC.D2_PT_4/IN3  (
    .I(N_PZ_968),
    .O(\NlwInverterSignal_U1/Channel0<8>_MC.D2_PT_4/IN3 )
  );
  X_INV \NlwInverterBlock_U1/Channel0<8>_MC.D2_PT_4/IN4  (
    .I(\U1/U2/location_Maddsub__n0000__n0075 [0]),
    .O(\NlwInverterSignal_U1/Channel0<8>_MC.D2_PT_4/IN4 )
  );
  X_INV \NlwInverterBlock_U1/Channel0<8>_MC.D2_PT_4/IN5  (
    .I(\U1/Channel0 [6]),
    .O(\NlwInverterSignal_U1/Channel0<8>_MC.D2_PT_4/IN5 )
  );
  X_INV \NlwInverterBlock_U1/Channel0<8>_MC.D2_PT_4/IN6  (
    .I(\U1/Channel0 [7]),
    .O(\NlwInverterSignal_U1/Channel0<8>_MC.D2_PT_4/IN6 )
  );
  X_INV \NlwInverterBlock_U1/Channel0<8>_MC.D2_PT_5/IN2  (
    .I(\U1/U2/location_Maddsub__n0000__n0067 [0]),
    .O(\NlwInverterSignal_U1/Channel0<8>_MC.D2_PT_5/IN2 )
  );
  X_INV \NlwInverterBlock_U1/Channel0<8>_MC.D2_PT_5/IN4  (
    .I(\U1/Zero0 ),
    .O(\NlwInverterSignal_U1/Channel0<8>_MC.D2_PT_5/IN4 )
  );
  X_INV \NlwInverterBlock_U1/Channel0<8>_MC.D2_PT_5/IN5  (
    .I(\U1/U2/location_Maddsub__n0000__n0075 [0]),
    .O(\NlwInverterSignal_U1/Channel0<8>_MC.D2_PT_5/IN5 )
  );
  X_INV \NlwInverterBlock_U1/Channel0<8>_MC.D2_PT_5/IN7  (
    .I(\U1/Channel0 [7]),
    .O(\NlwInverterSignal_U1/Channel0<8>_MC.D2_PT_5/IN7 )
  );
  X_INV \NlwInverterBlock_U1/Channel0<11>_MC.D2_PT_0/IN0  (
    .I(N_PZ_928),
    .O(\NlwInverterSignal_U1/Channel0<11>_MC.D2_PT_0/IN0 )
  );
  X_INV \NlwInverterBlock_U1/Channel0<11>_MC.D2_PT_1/IN1  (
    .I(\U1/Channel0 [10]),
    .O(\NlwInverterSignal_U1/Channel0<11>_MC.D2_PT_1/IN1 )
  );
  X_INV \NlwInverterBlock_U1/Channel0<11>_MC.D2_PT_1/IN2  (
    .I(\U1/Channel0 [9]),
    .O(\NlwInverterSignal_U1/Channel0<11>_MC.D2_PT_1/IN2 )
  );
  X_INV \NlwInverterBlock_U1/Channel0<11>_MC.D2_PT_2/IN3  (
    .I(\U1/U2/location_Maddsub__n0000__n0075 [0]),
    .O(\NlwInverterSignal_U1/Channel0<11>_MC.D2_PT_2/IN3 )
  );
  X_INV \NlwInverterBlock_U1/Channel0<12>_MC.D2_PT_0/IN0  (
    .I(N_PZ_928),
    .O(\NlwInverterSignal_U1/Channel0<12>_MC.D2_PT_0/IN0 )
  );
  X_INV \NlwInverterBlock_U1/Channel0<12>_MC.D2_PT_1/IN1  (
    .I(\U1/Channel0 [10]),
    .O(\NlwInverterSignal_U1/Channel0<12>_MC.D2_PT_1/IN1 )
  );
  X_INV \NlwInverterBlock_U1/Channel0<12>_MC.D2_PT_1/IN2  (
    .I(\U1/Channel0 [9]),
    .O(\NlwInverterSignal_U1/Channel0<12>_MC.D2_PT_1/IN2 )
  );
  X_INV \NlwInverterBlock_U1/Channel0<12>_MC.D2_PT_1/IN4  (
    .I(\U1/Channel0 [11]),
    .O(\NlwInverterSignal_U1/Channel0<12>_MC.D2_PT_1/IN4 )
  );
  X_INV \NlwInverterBlock_U1/Channel0<12>_MC.D2_PT_2/IN3  (
    .I(\U1/U2/location_Maddsub__n0000__n0075 [0]),
    .O(\NlwInverterSignal_U1/Channel0<12>_MC.D2_PT_2/IN3 )
  );
  X_INV \NlwInverterBlock_DCOR0CNTHIGHr_MC.D1/IN1  (
    .I(\RD_II/UIM ),
    .O(\NlwInverterSignal_DCOR0CNTHIGHr_MC.D1/IN1 )
  );
  X_INV \NlwInverterBlock_DCOR0CNTHIGHr_MC.D1/IN3  (
    .I(U2_ADDR_reg[4]),
    .O(\NlwInverterSignal_DCOR0CNTHIGHr_MC.D1/IN3 )
  );
  X_INV \NlwInverterBlock_DCOR0CNTHIGHr_MC.D1/IN4  (
    .I(U2_ADDR_reg[5]),
    .O(\NlwInverterSignal_DCOR0CNTHIGHr_MC.D1/IN4 )
  );
  X_INV \NlwInverterBlock_DCOR0CNTHIGHr_MC.D1/IN5  (
    .I(U2_ADDR_reg[6]),
    .O(\NlwInverterSignal_DCOR0CNTHIGHr_MC.D1/IN5 )
  );
  X_INV \NlwInverterBlock_DCOR0CNTHIGHr_MC.D1/IN6  (
    .I(U2_ADDR_reg[7]),
    .O(\NlwInverterSignal_DCOR0CNTHIGHr_MC.D1/IN6 )
  );
  X_INV \NlwInverterBlock_DCOR0CNTHIGHr_MC.D1/IN7  (
    .I(U2_ADDR_reg[3]),
    .O(\NlwInverterSignal_DCOR0CNTHIGHr_MC.D1/IN7 )
  );
  X_INV \NlwInverterBlock_DCOR0CNTHIGHr_MC.D1/IN8  (
    .I(U2_ADDR_reg[1]),
    .O(\NlwInverterSignal_DCOR0CNTHIGHr_MC.D1/IN8 )
  );
  X_INV \NlwInverterBlock_U1/U3/holdingreg1<13>_MC.D2_PT_1/IN1  (
    .I(\AS_II/UIM ),
    .O(\NlwInverterSignal_U1/U3/holdingreg1<13>_MC.D2_PT_1/IN1 )
  );
  X_INV \NlwInverterBlock_U1/Channel1<13>_MC.D2_PT_0/IN0  (
    .I(N_PZ_929),
    .O(\NlwInverterSignal_U1/Channel1<13>_MC.D2_PT_0/IN0 )
  );
  X_INV \NlwInverterBlock_U1/Channel1<13>_MC.D2_PT_1/IN1  (
    .I(\U1/Zero1 ),
    .O(\NlwInverterSignal_U1/Channel1<13>_MC.D2_PT_1/IN1 )
  );
  X_INV \NlwInverterBlock_U1/Channel1<13>_MC.D2_PT_1/IN3  (
    .I(\U1/U6/CurrState_Sreg0_FFD2 ),
    .O(\NlwInverterSignal_U1/Channel1<13>_MC.D2_PT_1/IN3 )
  );
  X_INV \NlwInverterBlock_U1/Channel1<13>_MC.D2_PT_1/IN7  (
    .I(\U1/U5/location_Maddsub__n0000__n0075 [0]),
    .O(\NlwInverterSignal_U1/Channel1<13>_MC.D2_PT_1/IN7 )
  );
  X_INV \NlwInverterBlock_U1/Channel1<13>_MC.D2_PT_2/IN1  (
    .I(\U1/Zero1 ),
    .O(\NlwInverterSignal_U1/Channel1<13>_MC.D2_PT_2/IN1 )
  );
  X_INV \NlwInverterBlock_U1/Channel1<13>_MC.D2_PT_2/IN3  (
    .I(\U1/U6/CurrState_Sreg0_FFD2 ),
    .O(\NlwInverterSignal_U1/Channel1<13>_MC.D2_PT_2/IN3 )
  );
  X_INV \NlwInverterBlock_U1/Channel1<13>_MC.D2_PT_2/IN4  (
    .I(N_PZ_921),
    .O(\NlwInverterSignal_U1/Channel1<13>_MC.D2_PT_2/IN4 )
  );
  X_INV \NlwInverterBlock_U1/Channel1<13>_MC.D2_PT_2/IN6  (
    .I(\U1/Channel1 [10]),
    .O(\NlwInverterSignal_U1/Channel1<13>_MC.D2_PT_2/IN6 )
  );
  X_INV \NlwInverterBlock_U1/Channel1<13>_MC.D2_PT_2/IN7  (
    .I(\U1/Channel1 [9]),
    .O(\NlwInverterSignal_U1/Channel1<13>_MC.D2_PT_2/IN7 )
  );
  X_INV \NlwInverterBlock_U1/Channel1<13>_MC.D2_PT_2/IN9  (
    .I(\U1/Channel1 [11]),
    .O(\NlwInverterSignal_U1/Channel1<13>_MC.D2_PT_2/IN9 )
  );
  X_INV \NlwInverterBlock_U1/Channel1<13>_MC.D2_PT_2/IN10  (
    .I(\U1/Channel1 [12]),
    .O(\NlwInverterSignal_U1/Channel1<13>_MC.D2_PT_2/IN10 )
  );
  X_INV \NlwInverterBlock_U1/Channel1<10>_MC.D2_PT_0/IN0  (
    .I(N_PZ_929),
    .O(\NlwInverterSignal_U1/Channel1<10>_MC.D2_PT_0/IN0 )
  );
  X_INV \NlwInverterBlock_U1/Channel1<10>_MC.D2_PT_1/IN1  (
    .I(\U1/Zero1 ),
    .O(\NlwInverterSignal_U1/Channel1<10>_MC.D2_PT_1/IN1 )
  );
  X_INV \NlwInverterBlock_U1/Channel1<10>_MC.D2_PT_1/IN3  (
    .I(\U1/U6/CurrState_Sreg0_FFD2 ),
    .O(\NlwInverterSignal_U1/Channel1<10>_MC.D2_PT_1/IN3 )
  );
  X_INV \NlwInverterBlock_U1/Channel1<10>_MC.D2_PT_1/IN6  (
    .I(\U1/U5/location_Maddsub__n0000__n0075 [0]),
    .O(\NlwInverterSignal_U1/Channel1<10>_MC.D2_PT_1/IN6 )
  );
  X_INV \NlwInverterBlock_U1/Channel1<10>_MC.D2_PT_2/IN1  (
    .I(\U1/Zero1 ),
    .O(\NlwInverterSignal_U1/Channel1<10>_MC.D2_PT_2/IN1 )
  );
  X_INV \NlwInverterBlock_U1/Channel1<10>_MC.D2_PT_2/IN3  (
    .I(\U1/U6/CurrState_Sreg0_FFD2 ),
    .O(\NlwInverterSignal_U1/Channel1<10>_MC.D2_PT_2/IN3 )
  );
  X_INV \NlwInverterBlock_U1/Channel1<10>_MC.D2_PT_2/IN4  (
    .I(N_PZ_921),
    .O(\NlwInverterSignal_U1/Channel1<10>_MC.D2_PT_2/IN4 )
  );
  X_INV \NlwInverterBlock_U1/Channel1<10>_MC.D2_PT_2/IN6  (
    .I(\U1/Channel1 [9]),
    .O(\NlwInverterSignal_U1/Channel1<10>_MC.D2_PT_2/IN6 )
  );
  X_INV \NlwInverterBlock_U1/Channel1<9>_MC.D2_PT_0/IN0  (
    .I(N_PZ_929),
    .O(\NlwInverterSignal_U1/Channel1<9>_MC.D2_PT_0/IN0 )
  );
  X_INV \NlwInverterBlock_U1/Channel1<9>_MC.D2_PT_1/IN1  (
    .I(\U1/Zero1 ),
    .O(\NlwInverterSignal_U1/Channel1<9>_MC.D2_PT_1/IN1 )
  );
  X_INV \NlwInverterBlock_U1/Channel1<9>_MC.D2_PT_1/IN3  (
    .I(\U1/U6/CurrState_Sreg0_FFD2 ),
    .O(\NlwInverterSignal_U1/Channel1<9>_MC.D2_PT_1/IN3 )
  );
  X_INV \NlwInverterBlock_U1/Channel1<9>_MC.D2_PT_1/IN5  (
    .I(\U1/U5/location_Maddsub__n0000__n0075 [0]),
    .O(\NlwInverterSignal_U1/Channel1<9>_MC.D2_PT_1/IN5 )
  );
  X_INV \NlwInverterBlock_U1/Channel1<9>_MC.D2_PT_2/IN1  (
    .I(\U1/Zero1 ),
    .O(\NlwInverterSignal_U1/Channel1<9>_MC.D2_PT_2/IN1 )
  );
  X_INV \NlwInverterBlock_U1/Channel1<9>_MC.D2_PT_2/IN3  (
    .I(\U1/U6/CurrState_Sreg0_FFD2 ),
    .O(\NlwInverterSignal_U1/Channel1<9>_MC.D2_PT_2/IN3 )
  );
  X_INV \NlwInverterBlock_U1/Channel1<9>_MC.D2_PT_2/IN4  (
    .I(N_PZ_921),
    .O(\NlwInverterSignal_U1/Channel1<9>_MC.D2_PT_2/IN4 )
  );
  X_INV \NlwInverterBlock_U1/U5/location_Maddsub__n0000__n0075<0>_MC.D2_PT_0/IN1  (
    .I(\U1/U5/location_Maddsub__n0000__n0067 [0]),
    .O(\NlwInverterSignal_U1/U5/location_Maddsub__n0000__n0075<0>_MC.D2_PT_0/IN1 )
  );
  X_INV \NlwInverterBlock_U1/U5/location_Maddsub__n0000__n0075<0>_MC.D2_PT_1/IN0  (
    .I(\U1/Channel1 [5]),
    .O(\NlwInverterSignal_U1/U5/location_Maddsub__n0000__n0075<0>_MC.D2_PT_1/IN0 )
  );
  X_INV \NlwInverterBlock_U1/U5/location_Maddsub__n0000__n0075<0>_MC.D2_PT_1/IN2  (
    .I(N_PZ_944),
    .O(\NlwInverterSignal_U1/U5/location_Maddsub__n0000__n0075<0>_MC.D2_PT_1/IN2 )
  );
  X_INV \NlwInverterBlock_U1/U5/location_Maddsub__n0000__n0075<0>_MC.D2_PT_1/IN3  (
    .I(\U1/Channel1 [6]),
    .O(\NlwInverterSignal_U1/U5/location_Maddsub__n0000__n0075<0>_MC.D2_PT_1/IN3 )
  );
  X_INV \NlwInverterBlock_U1/U5/location_Maddsub__n0000__n0075<0>_MC.D2_PT_1/IN4  (
    .I(\U1/Channel1 [7]),
    .O(\NlwInverterSignal_U1/U5/location_Maddsub__n0000__n0075<0>_MC.D2_PT_1/IN4 )
  );
  X_INV \NlwInverterBlock_U1/U5/location_Maddsub__n0000__n0075<0>_MC.D2_PT_1/IN5  (
    .I(\U1/Channel1 [8]),
    .O(\NlwInverterSignal_U1/U5/location_Maddsub__n0000__n0075<0>_MC.D2_PT_1/IN5 )
  );
  X_INV \NlwInverterBlock_U1/Channel1<6>_MC.D2_PT_0/IN0  (
    .I(N_PZ_929),
    .O(\NlwInverterSignal_U1/Channel1<6>_MC.D2_PT_0/IN0 )
  );
  X_INV \NlwInverterBlock_U1/Channel1<6>_MC.D2_PT_1/IN2  (
    .I(\U1/Zero1 ),
    .O(\NlwInverterSignal_U1/Channel1<6>_MC.D2_PT_1/IN2 )
  );
  X_INV \NlwInverterBlock_U1/Channel1<6>_MC.D2_PT_1/IN4  (
    .I(\U1/U6/CurrState_Sreg0_FFD2 ),
    .O(\NlwInverterSignal_U1/Channel1<6>_MC.D2_PT_1/IN4 )
  );
  X_INV \NlwInverterBlock_U1/Channel1<6>_MC.D2_PT_1/IN5  (
    .I(\U1/U5/location_Maddsub__n0000__n0067 [0]),
    .O(\NlwInverterSignal_U1/Channel1<6>_MC.D2_PT_1/IN5 )
  );
  X_INV \NlwInverterBlock_U1/Channel1<6>_MC.D2_PT_2/IN1  (
    .I(\U1/Channel1 [5]),
    .O(\NlwInverterSignal_U1/Channel1<6>_MC.D2_PT_2/IN1 )
  );
  X_INV \NlwInverterBlock_U1/Channel1<6>_MC.D2_PT_2/IN2  (
    .I(\U1/Zero1 ),
    .O(\NlwInverterSignal_U1/Channel1<6>_MC.D2_PT_2/IN2 )
  );
  X_INV \NlwInverterBlock_U1/Channel1<6>_MC.D2_PT_2/IN4  (
    .I(\U1/U6/CurrState_Sreg0_FFD2 ),
    .O(\NlwInverterSignal_U1/Channel1<6>_MC.D2_PT_2/IN4 )
  );
  X_INV \NlwInverterBlock_U1/Channel1<6>_MC.D2_PT_2/IN6  (
    .I(N_PZ_921),
    .O(\NlwInverterSignal_U1/Channel1<6>_MC.D2_PT_2/IN6 )
  );
  X_INV \NlwInverterBlock_U1/Channel1<7>_MC.D2_PT_0/IN0  (
    .I(N_PZ_929),
    .O(\NlwInverterSignal_U1/Channel1<7>_MC.D2_PT_0/IN0 )
  );
  X_INV \NlwInverterBlock_U1/Channel1<7>_MC.D2_PT_1/IN2  (
    .I(\U1/Zero1 ),
    .O(\NlwInverterSignal_U1/Channel1<7>_MC.D2_PT_1/IN2 )
  );
  X_INV \NlwInverterBlock_U1/Channel1<7>_MC.D2_PT_1/IN4  (
    .I(\U1/U6/CurrState_Sreg0_FFD2 ),
    .O(\NlwInverterSignal_U1/Channel1<7>_MC.D2_PT_1/IN4 )
  );
  X_INV \NlwInverterBlock_U1/Channel1<7>_MC.D2_PT_1/IN5  (
    .I(\U1/U5/location_Maddsub__n0000__n0067 [0]),
    .O(\NlwInverterSignal_U1/Channel1<7>_MC.D2_PT_1/IN5 )
  );
  X_INV \NlwInverterBlock_U1/Channel1<7>_MC.D2_PT_2/IN1  (
    .I(\U1/Channel1 [5]),
    .O(\NlwInverterSignal_U1/Channel1<7>_MC.D2_PT_2/IN1 )
  );
  X_INV \NlwInverterBlock_U1/Channel1<7>_MC.D2_PT_2/IN2  (
    .I(\U1/Zero1 ),
    .O(\NlwInverterSignal_U1/Channel1<7>_MC.D2_PT_2/IN2 )
  );
  X_INV \NlwInverterBlock_U1/Channel1<7>_MC.D2_PT_2/IN4  (
    .I(\U1/U6/CurrState_Sreg0_FFD2 ),
    .O(\NlwInverterSignal_U1/Channel1<7>_MC.D2_PT_2/IN4 )
  );
  X_INV \NlwInverterBlock_U1/Channel1<7>_MC.D2_PT_2/IN6  (
    .I(N_PZ_921),
    .O(\NlwInverterSignal_U1/Channel1<7>_MC.D2_PT_2/IN6 )
  );
  X_INV \NlwInverterBlock_U1/Channel1<7>_MC.D2_PT_2/IN8  (
    .I(\U1/Channel1 [6]),
    .O(\NlwInverterSignal_U1/Channel1<7>_MC.D2_PT_2/IN8 )
  );
  X_INV \NlwInverterBlock_U1/Channel1<8>_MC.D2_PT_0/IN0  (
    .I(N_PZ_929),
    .O(\NlwInverterSignal_U1/Channel1<8>_MC.D2_PT_0/IN0 )
  );
  X_INV \NlwInverterBlock_U1/Channel1<8>_MC.D2_PT_1/IN0  (
    .I(\U1/Channel1 [5]),
    .O(\NlwInverterSignal_U1/Channel1<8>_MC.D2_PT_1/IN0 )
  );
  X_INV \NlwInverterBlock_U1/Channel1<8>_MC.D2_PT_1/IN2  (
    .I(\U1/U6/CurrState_Sreg0_FFD2 ),
    .O(\NlwInverterSignal_U1/Channel1<8>_MC.D2_PT_1/IN2 )
  );
  X_INV \NlwInverterBlock_U1/Channel1<8>_MC.D2_PT_1/IN4  (
    .I(\U1/U5/location_Maddsub__n0000__n0075 [0]),
    .O(\NlwInverterSignal_U1/Channel1<8>_MC.D2_PT_1/IN4 )
  );
  X_INV \NlwInverterBlock_U1/Channel1<8>_MC.D2_PT_2/IN1  (
    .I(\U1/U6/CurrState_Sreg0_FFD2 ),
    .O(\NlwInverterSignal_U1/Channel1<8>_MC.D2_PT_2/IN1 )
  );
  X_INV \NlwInverterBlock_U1/Channel1<8>_MC.D2_PT_2/IN4  (
    .I(\U1/U5/location_Maddsub__n0000__n0075 [0]),
    .O(\NlwInverterSignal_U1/Channel1<8>_MC.D2_PT_2/IN4 )
  );
  X_INV \NlwInverterBlock_U1/Channel1<8>_MC.D2_PT_3/IN1  (
    .I(\U1/U6/CurrState_Sreg0_FFD2 ),
    .O(\NlwInverterSignal_U1/Channel1<8>_MC.D2_PT_3/IN1 )
  );
  X_INV \NlwInverterBlock_U1/Channel1<8>_MC.D2_PT_3/IN3  (
    .I(\U1/U5/location_Maddsub__n0000__n0075 [0]),
    .O(\NlwInverterSignal_U1/Channel1<8>_MC.D2_PT_3/IN3 )
  );
  X_INV \NlwInverterBlock_U1/Channel1<8>_MC.D2_PT_3/IN4  (
    .I(\U1/Channel1 [6]),
    .O(\NlwInverterSignal_U1/Channel1<8>_MC.D2_PT_3/IN4 )
  );
  X_INV \NlwInverterBlock_U1/Channel1<8>_MC.D2_PT_4/IN1  (
    .I(\U1/U6/CurrState_Sreg0_FFD2 ),
    .O(\NlwInverterSignal_U1/Channel1<8>_MC.D2_PT_4/IN1 )
  );
  X_INV \NlwInverterBlock_U1/Channel1<8>_MC.D2_PT_4/IN3  (
    .I(\U1/U5/location_Maddsub__n0000__n0075 [0]),
    .O(\NlwInverterSignal_U1/Channel1<8>_MC.D2_PT_4/IN3 )
  );
  X_INV \NlwInverterBlock_U1/Channel1<8>_MC.D2_PT_5/IN1  (
    .I(\U1/Zero1 ),
    .O(\NlwInverterSignal_U1/Channel1<8>_MC.D2_PT_5/IN1 )
  );
  X_INV \NlwInverterBlock_U1/Channel1<8>_MC.D2_PT_5/IN3  (
    .I(\U1/U6/CurrState_Sreg0_FFD2 ),
    .O(\NlwInverterSignal_U1/Channel1<8>_MC.D2_PT_5/IN3 )
  );
  X_INV \NlwInverterBlock_U1/Channel1<8>_MC.D2_PT_5/IN4  (
    .I(N_PZ_921),
    .O(\NlwInverterSignal_U1/Channel1<8>_MC.D2_PT_5/IN4 )
  );
  X_INV \NlwInverterBlock_U1/Channel1<8>_MC.D2_PT_5/IN7  (
    .I(\U1/Channel1 [8]),
    .O(\NlwInverterSignal_U1/Channel1<8>_MC.D2_PT_5/IN7 )
  );
  X_INV \NlwInverterBlock_U1/Channel1<8>_MC.D2_PT_6/IN0  (
    .I(\U1/Channel1 [5]),
    .O(\NlwInverterSignal_U1/Channel1<8>_MC.D2_PT_6/IN0 )
  );
  X_INV \NlwInverterBlock_U1/Channel1<8>_MC.D2_PT_6/IN2  (
    .I(\U1/U6/CurrState_Sreg0_FFD2 ),
    .O(\NlwInverterSignal_U1/Channel1<8>_MC.D2_PT_6/IN2 )
  );
  X_INV \NlwInverterBlock_U1/Channel1<8>_MC.D2_PT_6/IN5  (
    .I(\U1/U5/location_Maddsub__n0000__n0075 [0]),
    .O(\NlwInverterSignal_U1/Channel1<8>_MC.D2_PT_6/IN5 )
  );
  X_INV \NlwInverterBlock_U1/Channel1<8>_MC.D2_PT_6/IN6  (
    .I(\U1/Channel1 [6]),
    .O(\NlwInverterSignal_U1/Channel1<8>_MC.D2_PT_6/IN6 )
  );
  X_INV \NlwInverterBlock_U1/Channel1<8>_MC.D2_PT_6/IN7  (
    .I(\U1/Channel1 [7]),
    .O(\NlwInverterSignal_U1/Channel1<8>_MC.D2_PT_6/IN7 )
  );
  X_INV \NlwInverterBlock_U1/Channel1<8>_MC.D2_PT_7/IN2  (
    .I(\U1/Zero1 ),
    .O(\NlwInverterSignal_U1/Channel1<8>_MC.D2_PT_7/IN2 )
  );
  X_INV \NlwInverterBlock_U1/Channel1<8>_MC.D2_PT_7/IN4  (
    .I(\U1/U6/CurrState_Sreg0_FFD2 ),
    .O(\NlwInverterSignal_U1/Channel1<8>_MC.D2_PT_7/IN4 )
  );
  X_INV \NlwInverterBlock_U1/Channel1<8>_MC.D2_PT_7/IN5  (
    .I(\U1/U5/location_Maddsub__n0000__n0067 [0]),
    .O(\NlwInverterSignal_U1/Channel1<8>_MC.D2_PT_7/IN5 )
  );
  X_INV \NlwInverterBlock_U1/Channel1<8>_MC.D2_PT_7/IN10  (
    .I(\U1/Channel1 [8]),
    .O(\NlwInverterSignal_U1/Channel1<8>_MC.D2_PT_7/IN10 )
  );
  X_INV \NlwInverterBlock_U1/Channel1<11>_MC.D2_PT_0/IN0  (
    .I(N_PZ_929),
    .O(\NlwInverterSignal_U1/Channel1<11>_MC.D2_PT_0/IN0 )
  );
  X_INV \NlwInverterBlock_U1/Channel1<11>_MC.D2_PT_1/IN1  (
    .I(\U1/Zero1 ),
    .O(\NlwInverterSignal_U1/Channel1<11>_MC.D2_PT_1/IN1 )
  );
  X_INV \NlwInverterBlock_U1/Channel1<11>_MC.D2_PT_1/IN3  (
    .I(\U1/U6/CurrState_Sreg0_FFD2 ),
    .O(\NlwInverterSignal_U1/Channel1<11>_MC.D2_PT_1/IN3 )
  );
  X_INV \NlwInverterBlock_U1/Channel1<11>_MC.D2_PT_1/IN7  (
    .I(\U1/U5/location_Maddsub__n0000__n0075 [0]),
    .O(\NlwInverterSignal_U1/Channel1<11>_MC.D2_PT_1/IN7 )
  );
  X_INV \NlwInverterBlock_U1/Channel1<11>_MC.D2_PT_2/IN1  (
    .I(\U1/Zero1 ),
    .O(\NlwInverterSignal_U1/Channel1<11>_MC.D2_PT_2/IN1 )
  );
  X_INV \NlwInverterBlock_U1/Channel1<11>_MC.D2_PT_2/IN3  (
    .I(\U1/U6/CurrState_Sreg0_FFD2 ),
    .O(\NlwInverterSignal_U1/Channel1<11>_MC.D2_PT_2/IN3 )
  );
  X_INV \NlwInverterBlock_U1/Channel1<11>_MC.D2_PT_2/IN4  (
    .I(N_PZ_921),
    .O(\NlwInverterSignal_U1/Channel1<11>_MC.D2_PT_2/IN4 )
  );
  X_INV \NlwInverterBlock_U1/Channel1<11>_MC.D2_PT_2/IN6  (
    .I(\U1/Channel1 [10]),
    .O(\NlwInverterSignal_U1/Channel1<11>_MC.D2_PT_2/IN6 )
  );
  X_INV \NlwInverterBlock_U1/Channel1<11>_MC.D2_PT_2/IN7  (
    .I(\U1/Channel1 [9]),
    .O(\NlwInverterSignal_U1/Channel1<11>_MC.D2_PT_2/IN7 )
  );
  X_INV \NlwInverterBlock_U1/Channel1<12>_MC.D2_PT_0/IN0  (
    .I(N_PZ_929),
    .O(\NlwInverterSignal_U1/Channel1<12>_MC.D2_PT_0/IN0 )
  );
  X_INV \NlwInverterBlock_U1/Channel1<12>_MC.D2_PT_1/IN1  (
    .I(\U1/Zero1 ),
    .O(\NlwInverterSignal_U1/Channel1<12>_MC.D2_PT_1/IN1 )
  );
  X_INV \NlwInverterBlock_U1/Channel1<12>_MC.D2_PT_1/IN3  (
    .I(\U1/U6/CurrState_Sreg0_FFD2 ),
    .O(\NlwInverterSignal_U1/Channel1<12>_MC.D2_PT_1/IN3 )
  );
  X_INV \NlwInverterBlock_U1/Channel1<12>_MC.D2_PT_1/IN7  (
    .I(\U1/U5/location_Maddsub__n0000__n0075 [0]),
    .O(\NlwInverterSignal_U1/Channel1<12>_MC.D2_PT_1/IN7 )
  );
  X_INV \NlwInverterBlock_U1/Channel1<12>_MC.D2_PT_2/IN1  (
    .I(\U1/Zero1 ),
    .O(\NlwInverterSignal_U1/Channel1<12>_MC.D2_PT_2/IN1 )
  );
  X_INV \NlwInverterBlock_U1/Channel1<12>_MC.D2_PT_2/IN3  (
    .I(\U1/U6/CurrState_Sreg0_FFD2 ),
    .O(\NlwInverterSignal_U1/Channel1<12>_MC.D2_PT_2/IN3 )
  );
  X_INV \NlwInverterBlock_U1/Channel1<12>_MC.D2_PT_2/IN4  (
    .I(N_PZ_921),
    .O(\NlwInverterSignal_U1/Channel1<12>_MC.D2_PT_2/IN4 )
  );
  X_INV \NlwInverterBlock_U1/Channel1<12>_MC.D2_PT_2/IN6  (
    .I(\U1/Channel1 [10]),
    .O(\NlwInverterSignal_U1/Channel1<12>_MC.D2_PT_2/IN6 )
  );
  X_INV \NlwInverterBlock_U1/Channel1<12>_MC.D2_PT_2/IN7  (
    .I(\U1/Channel1 [9]),
    .O(\NlwInverterSignal_U1/Channel1<12>_MC.D2_PT_2/IN7 )
  );
  X_INV \NlwInverterBlock_U1/Channel1<12>_MC.D2_PT_2/IN9  (
    .I(\U1/Channel1 [11]),
    .O(\NlwInverterSignal_U1/Channel1<12>_MC.D2_PT_2/IN9 )
  );
  X_INV \NlwInverterBlock_N_PZ_961_MC.D1/IN0  (
    .I(DCOR0CNTLOWr),
    .O(\NlwInverterSignal_N_PZ_961_MC.D1/IN0 )
  );
  X_INV \NlwInverterBlock_N_PZ_961_MC.D1/IN1  (
    .I(DCOR1CNTLOWr),
    .O(\NlwInverterSignal_N_PZ_961_MC.D1/IN1 )
  );
  X_INV \NlwInverterBlock_N_PZ_961_MC.D1/IN2  (
    .I(DCOR0CNTHIGHr),
    .O(\NlwInverterSignal_N_PZ_961_MC.D1/IN2 )
  );
  X_INV \NlwInverterBlock_N_PZ_961_MC.D1/IN3  (
    .I(DCOR1CNTHIGHr),
    .O(\NlwInverterSignal_N_PZ_961_MC.D1/IN3 )
  );
  X_INV \NlwInverterBlock_DCOR1CNTHIGHr_MC.D1/IN1  (
    .I(\RD_II/UIM ),
    .O(\NlwInverterSignal_DCOR1CNTHIGHr_MC.D1/IN1 )
  );
  X_INV \NlwInverterBlock_DCOR1CNTHIGHr_MC.D1/IN3  (
    .I(U2_ADDR_reg[4]),
    .O(\NlwInverterSignal_DCOR1CNTHIGHr_MC.D1/IN3 )
  );
  X_INV \NlwInverterBlock_DCOR1CNTHIGHr_MC.D1/IN4  (
    .I(U2_ADDR_reg[5]),
    .O(\NlwInverterSignal_DCOR1CNTHIGHr_MC.D1/IN4 )
  );
  X_INV \NlwInverterBlock_DCOR1CNTHIGHr_MC.D1/IN5  (
    .I(U2_ADDR_reg[6]),
    .O(\NlwInverterSignal_DCOR1CNTHIGHr_MC.D1/IN5 )
  );
  X_INV \NlwInverterBlock_DCOR1CNTHIGHr_MC.D1/IN6  (
    .I(U2_ADDR_reg[7]),
    .O(\NlwInverterSignal_DCOR1CNTHIGHr_MC.D1/IN6 )
  );
  X_INV \NlwInverterBlock_DCOR1CNTHIGHr_MC.D1/IN7  (
    .I(U2_ADDR_reg[3]),
    .O(\NlwInverterSignal_DCOR1CNTHIGHr_MC.D1/IN7 )
  );
  X_INV \NlwInverterBlock_outDATA<5>\$WA6.UIM_MC.D2_PT_1/IN0  (
    .I(DCOR0THRESLOWr),
    .O(\NlwInverterSignal_outDATA<5>\$WA6.UIM_MC.D2_PT_1/IN0 )
  );
  X_INV \NlwInverterBlock_outDATA<5>\$WA6.UIM_MC.D2_PT_2/IN0  (
    .I(DCOR0THRESLOWr),
    .O(\NlwInverterSignal_outDATA<5>\$WA6.UIM_MC.D2_PT_2/IN0 )
  );
  X_INV \NlwInverterBlock_outDATA<5>\$WA6.UIM_MC.D2_PT_2/IN1  (
    .I(DCORIFGr),
    .O(\NlwInverterSignal_outDATA<5>\$WA6.UIM_MC.D2_PT_2/IN1 )
  );
  X_INV \NlwInverterBlock_outDATA<5>\$WA6.UIM_MC.D2_PT_3/IN0  (
    .I(DCOR0THRESLOWr),
    .O(\NlwInverterSignal_outDATA<5>\$WA6.UIM_MC.D2_PT_3/IN0 )
  );
  X_INV \NlwInverterBlock_outDATA<5>\$WA6.UIM_MC.D2_PT_3/IN1  (
    .I(DCORIFGr),
    .O(\NlwInverterSignal_outDATA<5>\$WA6.UIM_MC.D2_PT_3/IN1 )
  );
  X_INV \NlwInverterBlock_outDATA<5>\$WA6.UIM_MC.D2_PT_3/IN2  (
    .I(DCOR0THRESHIGHr),
    .O(\NlwInverterSignal_outDATA<5>\$WA6.UIM_MC.D2_PT_3/IN2 )
  );
  X_INV \NlwInverterBlock_outDATA<5>\$WA6.UIM_MC.D2_PT_4/IN0  (
    .I(DCOR0THRESLOWr),
    .O(\NlwInverterSignal_outDATA<5>\$WA6.UIM_MC.D2_PT_4/IN0 )
  );
  X_INV \NlwInverterBlock_outDATA<5>\$WA6.UIM_MC.D2_PT_4/IN1  (
    .I(DCORIFGr),
    .O(\NlwInverterSignal_outDATA<5>\$WA6.UIM_MC.D2_PT_4/IN1 )
  );
  X_INV \NlwInverterBlock_outDATA<5>\$WA6.UIM_MC.D2_PT_4/IN2  (
    .I(DCOR0THRESHIGHr),
    .O(\NlwInverterSignal_outDATA<5>\$WA6.UIM_MC.D2_PT_4/IN2 )
  );
  X_INV \NlwInverterBlock_outDATA<5>\$WA6.UIM_MC.D2_PT_4/IN3  (
    .I(DCOR1THRESLOWr),
    .O(\NlwInverterSignal_outDATA<5>\$WA6.UIM_MC.D2_PT_4/IN3 )
  );
  X_INV \NlwInverterBlock_U1/U4/Latch0r<5>_MC.D2_PT_1/IN2  (
    .I(N_PZ_963),
    .O(\NlwInverterSignal_U1/U4/Latch0r<5>_MC.D2_PT_1/IN2 )
  );
  X_INV \NlwInverterBlock_N_PZ_963_MC.D2_PT_0/IN0  (
    .I(DCORIFGw),
    .O(\NlwInverterSignal_N_PZ_963_MC.D2_PT_0/IN0 )
  );
  X_INV \NlwInverterBlock_N_PZ_963_MC.D2_PT_0/IN1  (
    .I(DCORENCCTLw),
    .O(\NlwInverterSignal_N_PZ_963_MC.D2_PT_0/IN1 )
  );
  X_INV \NlwInverterBlock_N_PZ_963_MC.D2_PT_0/IN2  (
    .I(NET2501),
    .O(\NlwInverterSignal_N_PZ_963_MC.D2_PT_0/IN2 )
  );
  X_INV \NlwInverterBlock_N_PZ_963_MC.D2_PT_0/IN4  (
    .I(\U1/U4/InEdge0r ),
    .O(\NlwInverterSignal_N_PZ_963_MC.D2_PT_0/IN4 )
  );
  X_INV \NlwInverterBlock_N_PZ_963_MC.D2_PT_1/IN0  (
    .I(DCORIFGw),
    .O(\NlwInverterSignal_N_PZ_963_MC.D2_PT_1/IN0 )
  );
  X_INV \NlwInverterBlock_N_PZ_963_MC.D2_PT_1/IN1  (
    .I(DCORENCCTLw),
    .O(\NlwInverterSignal_N_PZ_963_MC.D2_PT_1/IN1 )
  );
  X_INV \NlwInverterBlock_N_PZ_963_MC.D2_PT_1/IN2  (
    .I(NET2501),
    .O(\NlwInverterSignal_N_PZ_963_MC.D2_PT_1/IN2 )
  );
  X_INV \NlwInverterBlock_N_PZ_963_MC.D2_PT_1/IN3  (
    .I(\U1/U4/LatchEdge0r ),
    .O(\NlwInverterSignal_N_PZ_963_MC.D2_PT_1/IN3 )
  );
  X_INV \NlwInverterBlock_N_PZ_963_MC.D2_PT_1/IN5  (
    .I(\outDATA<6>\$WA1.UIM ),
    .O(\NlwInverterSignal_N_PZ_963_MC.D2_PT_1/IN5 )
  );
  X_INV \NlwInverterBlock_NET2501_MC.D2_PT_1/IN3  (
    .I(DCORENCCTLw),
    .O(\NlwInverterSignal_NET2501_MC.D2_PT_1/IN3 )
  );
  X_INV \NlwInverterBlock_U1/U4/LatchEdge0r_MC.D2_PT_1/IN1  (
    .I(DCORENCCTLw),
    .O(\NlwInverterSignal_U1/U4/LatchEdge0r_MC.D2_PT_1/IN1 )
  );
  X_INV \NlwInverterBlock_DCOR0THRESLOWr_MC.D1/IN1  (
    .I(\RD_II/UIM ),
    .O(\NlwInverterSignal_DCOR0THRESLOWr_MC.D1/IN1 )
  );
  X_INV \NlwInverterBlock_DCOR0THRESLOWr_MC.D1/IN2  (
    .I(U2_ADDR_reg[0]),
    .O(\NlwInverterSignal_DCOR0THRESLOWr_MC.D1/IN2 )
  );
  X_INV \NlwInverterBlock_DCOR0THRESLOWr_MC.D1/IN3  (
    .I(U2_ADDR_reg[4]),
    .O(\NlwInverterSignal_DCOR0THRESLOWr_MC.D1/IN3 )
  );
  X_INV \NlwInverterBlock_DCOR0THRESLOWr_MC.D1/IN4  (
    .I(U2_ADDR_reg[5]),
    .O(\NlwInverterSignal_DCOR0THRESLOWr_MC.D1/IN4 )
  );
  X_INV \NlwInverterBlock_DCOR0THRESLOWr_MC.D1/IN5  (
    .I(U2_ADDR_reg[6]),
    .O(\NlwInverterSignal_DCOR0THRESLOWr_MC.D1/IN5 )
  );
  X_INV \NlwInverterBlock_DCOR0THRESLOWr_MC.D1/IN6  (
    .I(U2_ADDR_reg[7]),
    .O(\NlwInverterSignal_DCOR0THRESLOWr_MC.D1/IN6 )
  );
  X_INV \NlwInverterBlock_DCOR0THRESLOWr_MC.D1/IN8  (
    .I(U2_ADDR_reg[1]),
    .O(\NlwInverterSignal_DCOR0THRESLOWr_MC.D1/IN8 )
  );
  X_INV \NlwInverterBlock_DCOR0THRESLOWr_MC.D1/IN9  (
    .I(U2_ADDR_reg[2]),
    .O(\NlwInverterSignal_DCOR0THRESLOWr_MC.D1/IN9 )
  );
  X_INV \NlwInverterBlock_DCORIFGr_MC.D1/IN1  (
    .I(\RD_II/UIM ),
    .O(\NlwInverterSignal_DCORIFGr_MC.D1/IN1 )
  );
  X_INV \NlwInverterBlock_DCORIFGr_MC.D1/IN3  (
    .I(U2_ADDR_reg[4]),
    .O(\NlwInverterSignal_DCORIFGr_MC.D1/IN3 )
  );
  X_INV \NlwInverterBlock_DCORIFGr_MC.D1/IN4  (
    .I(U2_ADDR_reg[5]),
    .O(\NlwInverterSignal_DCORIFGr_MC.D1/IN4 )
  );
  X_INV \NlwInverterBlock_DCORIFGr_MC.D1/IN5  (
    .I(U2_ADDR_reg[6]),
    .O(\NlwInverterSignal_DCORIFGr_MC.D1/IN5 )
  );
  X_INV \NlwInverterBlock_DCORIFGr_MC.D1/IN6  (
    .I(U2_ADDR_reg[7]),
    .O(\NlwInverterSignal_DCORIFGr_MC.D1/IN6 )
  );
  X_INV \NlwInverterBlock_DCORIFGr_MC.D1/IN7  (
    .I(U2_ADDR_reg[3]),
    .O(\NlwInverterSignal_DCORIFGr_MC.D1/IN7 )
  );
  X_INV \NlwInverterBlock_DCORIFGr_MC.D1/IN8  (
    .I(U2_ADDR_reg[1]),
    .O(\NlwInverterSignal_DCORIFGr_MC.D1/IN8 )
  );
  X_INV \NlwInverterBlock_DCORIFGr_MC.D1/IN9  (
    .I(U2_ADDR_reg[2]),
    .O(\NlwInverterSignal_DCORIFGr_MC.D1/IN9 )
  );
  X_INV \NlwInverterBlock_U1/U4/Latch0r<13>_MC.D2_PT_1/IN2  (
    .I(N_PZ_963),
    .O(\NlwInverterSignal_U1/U4/Latch0r<13>_MC.D2_PT_1/IN2 )
  );
  X_INV \NlwInverterBlock_DCOR0THRESHIGHr_MC.D1/IN1  (
    .I(\RD_II/UIM ),
    .O(\NlwInverterSignal_DCOR0THRESHIGHr_MC.D1/IN1 )
  );
  X_INV \NlwInverterBlock_DCOR0THRESHIGHr_MC.D1/IN3  (
    .I(U2_ADDR_reg[4]),
    .O(\NlwInverterSignal_DCOR0THRESHIGHr_MC.D1/IN3 )
  );
  X_INV \NlwInverterBlock_DCOR0THRESHIGHr_MC.D1/IN4  (
    .I(U2_ADDR_reg[5]),
    .O(\NlwInverterSignal_DCOR0THRESHIGHr_MC.D1/IN4 )
  );
  X_INV \NlwInverterBlock_DCOR0THRESHIGHr_MC.D1/IN5  (
    .I(U2_ADDR_reg[6]),
    .O(\NlwInverterSignal_DCOR0THRESHIGHr_MC.D1/IN5 )
  );
  X_INV \NlwInverterBlock_DCOR0THRESHIGHr_MC.D1/IN6  (
    .I(U2_ADDR_reg[7]),
    .O(\NlwInverterSignal_DCOR0THRESHIGHr_MC.D1/IN6 )
  );
  X_INV \NlwInverterBlock_DCOR0THRESHIGHr_MC.D1/IN8  (
    .I(U2_ADDR_reg[1]),
    .O(\NlwInverterSignal_DCOR0THRESHIGHr_MC.D1/IN8 )
  );
  X_INV \NlwInverterBlock_DCOR0THRESHIGHr_MC.D1/IN9  (
    .I(U2_ADDR_reg[2]),
    .O(\NlwInverterSignal_DCOR0THRESHIGHr_MC.D1/IN9 )
  );
  X_INV \NlwInverterBlock_U1/U4/Latch1r<5>_MC.D2_PT_1/IN2  (
    .I(N_PZ_962),
    .O(\NlwInverterSignal_U1/U4/Latch1r<5>_MC.D2_PT_1/IN2 )
  );
  X_INV \NlwInverterBlock_N_PZ_962_MC.D2_PT_0/IN0  (
    .I(DCORIFGw),
    .O(\NlwInverterSignal_N_PZ_962_MC.D2_PT_0/IN0 )
  );
  X_INV \NlwInverterBlock_N_PZ_962_MC.D2_PT_0/IN1  (
    .I(DCORENCCTLw),
    .O(\NlwInverterSignal_N_PZ_962_MC.D2_PT_0/IN1 )
  );
  X_INV \NlwInverterBlock_N_PZ_962_MC.D2_PT_0/IN2  (
    .I(NET2512),
    .O(\NlwInverterSignal_N_PZ_962_MC.D2_PT_0/IN2 )
  );
  X_INV \NlwInverterBlock_N_PZ_962_MC.D2_PT_0/IN4  (
    .I(\U1/U4/InEdge1r ),
    .O(\NlwInverterSignal_N_PZ_962_MC.D2_PT_0/IN4 )
  );
  X_INV \NlwInverterBlock_N_PZ_962_MC.D2_PT_1/IN0  (
    .I(DCORIFGw),
    .O(\NlwInverterSignal_N_PZ_962_MC.D2_PT_1/IN0 )
  );
  X_INV \NlwInverterBlock_N_PZ_962_MC.D2_PT_1/IN1  (
    .I(DCORENCCTLw),
    .O(\NlwInverterSignal_N_PZ_962_MC.D2_PT_1/IN1 )
  );
  X_INV \NlwInverterBlock_N_PZ_962_MC.D2_PT_1/IN2  (
    .I(NET2512),
    .O(\NlwInverterSignal_N_PZ_962_MC.D2_PT_1/IN2 )
  );
  X_INV \NlwInverterBlock_N_PZ_962_MC.D2_PT_1/IN3  (
    .I(\U1/U4/LatchEdge1r ),
    .O(\NlwInverterSignal_N_PZ_962_MC.D2_PT_1/IN3 )
  );
  X_INV \NlwInverterBlock_N_PZ_962_MC.D2_PT_1/IN5  (
    .I(\outDATA<7>\$WA1.UIM ),
    .O(\NlwInverterSignal_N_PZ_962_MC.D2_PT_1/IN5 )
  );
  X_INV \NlwInverterBlock_NET2512_MC.D2_PT_1/IN3  (
    .I(DCORENCCTLw),
    .O(\NlwInverterSignal_NET2512_MC.D2_PT_1/IN3 )
  );
  X_INV \NlwInverterBlock_U1/U4/LatchEdge1r_MC.D2_PT_1/IN1  (
    .I(DCORENCCTLw),
    .O(\NlwInverterSignal_U1/U4/LatchEdge1r_MC.D2_PT_1/IN1 )
  );
  X_INV \NlwInverterBlock_DCOR1THRESLOWr_MC.D1/IN1  (
    .I(\RD_II/UIM ),
    .O(\NlwInverterSignal_DCOR1THRESLOWr_MC.D1/IN1 )
  );
  X_INV \NlwInverterBlock_DCOR1THRESLOWr_MC.D1/IN2  (
    .I(U2_ADDR_reg[0]),
    .O(\NlwInverterSignal_DCOR1THRESLOWr_MC.D1/IN2 )
  );
  X_INV \NlwInverterBlock_DCOR1THRESLOWr_MC.D1/IN3  (
    .I(U2_ADDR_reg[4]),
    .O(\NlwInverterSignal_DCOR1THRESLOWr_MC.D1/IN3 )
  );
  X_INV \NlwInverterBlock_DCOR1THRESLOWr_MC.D1/IN4  (
    .I(U2_ADDR_reg[5]),
    .O(\NlwInverterSignal_DCOR1THRESLOWr_MC.D1/IN4 )
  );
  X_INV \NlwInverterBlock_DCOR1THRESLOWr_MC.D1/IN5  (
    .I(U2_ADDR_reg[6]),
    .O(\NlwInverterSignal_DCOR1THRESLOWr_MC.D1/IN5 )
  );
  X_INV \NlwInverterBlock_DCOR1THRESLOWr_MC.D1/IN6  (
    .I(U2_ADDR_reg[7]),
    .O(\NlwInverterSignal_DCOR1THRESLOWr_MC.D1/IN6 )
  );
  X_INV \NlwInverterBlock_DCOR1THRESLOWr_MC.D1/IN9  (
    .I(U2_ADDR_reg[2]),
    .O(\NlwInverterSignal_DCOR1THRESLOWr_MC.D1/IN9 )
  );
  X_INV \NlwInverterBlock_U1/U4/Latch1r<13>_MC.D2_PT_1/IN2  (
    .I(N_PZ_962),
    .O(\NlwInverterSignal_U1/U4/Latch1r<13>_MC.D2_PT_1/IN2 )
  );
  X_INV \NlwInverterBlock_N_PZ_987_MC.D1/IN0  (
    .I(DCOR0THRESLOWr),
    .O(\NlwInverterSignal_N_PZ_987_MC.D1/IN0 )
  );
  X_INV \NlwInverterBlock_N_PZ_987_MC.D1/IN1  (
    .I(DCORIFGr),
    .O(\NlwInverterSignal_N_PZ_987_MC.D1/IN1 )
  );
  X_INV \NlwInverterBlock_N_PZ_987_MC.D1/IN2  (
    .I(DCOR0THRESHIGHr),
    .O(\NlwInverterSignal_N_PZ_987_MC.D1/IN2 )
  );
  X_INV \NlwInverterBlock_N_PZ_987_MC.D1/IN3  (
    .I(DCOR1THRESLOWr),
    .O(\NlwInverterSignal_N_PZ_987_MC.D1/IN3 )
  );
  X_INV \NlwInverterBlock_N_PZ_987_MC.D1/IN4  (
    .I(DCOR1THRESHIGHr),
    .O(\NlwInverterSignal_N_PZ_987_MC.D1/IN4 )
  );
  X_INV \NlwInverterBlock_DCOR1THRESHIGHr_MC.D1/IN1  (
    .I(\RD_II/UIM ),
    .O(\NlwInverterSignal_DCOR1THRESHIGHr_MC.D1/IN1 )
  );
  X_INV \NlwInverterBlock_DCOR1THRESHIGHr_MC.D1/IN3  (
    .I(U2_ADDR_reg[4]),
    .O(\NlwInverterSignal_DCOR1THRESHIGHr_MC.D1/IN3 )
  );
  X_INV \NlwInverterBlock_DCOR1THRESHIGHr_MC.D1/IN4  (
    .I(U2_ADDR_reg[5]),
    .O(\NlwInverterSignal_DCOR1THRESHIGHr_MC.D1/IN4 )
  );
  X_INV \NlwInverterBlock_DCOR1THRESHIGHr_MC.D1/IN5  (
    .I(U2_ADDR_reg[6]),
    .O(\NlwInverterSignal_DCOR1THRESHIGHr_MC.D1/IN5 )
  );
  X_INV \NlwInverterBlock_DCOR1THRESHIGHr_MC.D1/IN6  (
    .I(U2_ADDR_reg[7]),
    .O(\NlwInverterSignal_DCOR1THRESHIGHr_MC.D1/IN6 )
  );
  X_INV \NlwInverterBlock_DCOR1THRESHIGHr_MC.D1/IN9  (
    .I(U2_ADDR_reg[2]),
    .O(\NlwInverterSignal_DCOR1THRESHIGHr_MC.D1/IN9 )
  );
  X_INV \NlwInverterBlock_U2_Enable_AD_MC.D1/IN1  (
    .I(\RD_II/UIM ),
    .O(\NlwInverterSignal_U2_Enable_AD_MC.D1/IN1 )
  );
  X_INV \NlwInverterBlock_U2_Enable_AD_MC.D1/IN2  (
    .I(U2_ADDR_reg[4]),
    .O(\NlwInverterSignal_U2_Enable_AD_MC.D1/IN2 )
  );
  X_INV \NlwInverterBlock_U2_Enable_AD_MC.D1/IN3  (
    .I(U2_ADDR_reg[5]),
    .O(\NlwInverterSignal_U2_Enable_AD_MC.D1/IN3 )
  );
  X_INV \NlwInverterBlock_U2_Enable_AD_MC.D1/IN4  (
    .I(U2_ADDR_reg[6]),
    .O(\NlwInverterSignal_U2_Enable_AD_MC.D1/IN4 )
  );
  X_INV \NlwInverterBlock_U2_Enable_AD_MC.D1/IN5  (
    .I(U2_ADDR_reg[7]),
    .O(\NlwInverterSignal_U2_Enable_AD_MC.D1/IN5 )
  );
  X_INV \NlwInverterBlock_Enc033ctrl_MC.D/IN0  (
    .I(\Enc033ctrl_MC.D1 ),
    .O(\NlwInverterSignal_Enc033ctrl_MC.D/IN0 )
  );
  X_INV \NlwInverterBlock_Enc033ctrl_MC.D1/IN1  (
    .I(\U4/ctrlr[3] ),
    .O(\NlwInverterSignal_Enc033ctrl_MC.D1/IN1 )
  );
  X_INV \NlwInverterBlock_U4/ctrlr<2>_MC.D/IN0  (
    .I(\U4/ctrlr<2>_MC.D1 ),
    .O(\NlwInverterSignal_U4/ctrlr<2>_MC.D/IN0 )
  );
  X_INV \NlwInverterBlock_U4/ctrlr<2>_MC.D2_PT_0/IN1  (
    .I(\outDATA<2>\$WA0.UIM ),
    .O(\NlwInverterSignal_U4/ctrlr<2>_MC.D2_PT_0/IN1 )
  );
  X_INV \NlwInverterBlock_U4/ctrlr<2>_MC.D2_PT_1/IN1  (
    .I(\outDATA<2>\$WA1.UIM ),
    .O(\NlwInverterSignal_U4/ctrlr<2>_MC.D2_PT_1/IN1 )
  );
  X_INV \NlwInverterBlock_U4/ctrlr<2>_MC.D2_PT_2/IN1  (
    .I(\outDATA<2>\$WA2.UIM ),
    .O(\NlwInverterSignal_U4/ctrlr<2>_MC.D2_PT_2/IN1 )
  );
  X_INV \NlwInverterBlock_U4/ctrlr<2>_MC.D2_PT_3/IN1  (
    .I(\outDATA<2>\$WA3.UIM ),
    .O(\NlwInverterSignal_U4/ctrlr<2>_MC.D2_PT_3/IN1 )
  );
  X_INV \NlwInverterBlock_U4/ctrlr<2>_MC.D2_PT_4/IN0  (
    .I(N_PZ_961),
    .O(\NlwInverterSignal_U4/ctrlr<2>_MC.D2_PT_4/IN0 )
  );
  X_INV \NlwInverterBlock_U4/ctrlr<2>_MC.D2_PT_4/IN1  (
    .I(\outDATA<2>\$WA5.UIM ),
    .O(\NlwInverterSignal_U4/ctrlr<2>_MC.D2_PT_4/IN1 )
  );
  X_INV \NlwInverterBlock_U4/ctrlr<2>_MC.D2_PT_5/IN0  (
    .I(N_PZ_987),
    .O(\NlwInverterSignal_U4/ctrlr<2>_MC.D2_PT_5/IN0 )
  );
  X_INV \NlwInverterBlock_U4/ctrlr<2>_MC.D2_PT_5/IN1  (
    .I(\outDATA<2>\$WA6.UIM ),
    .O(\NlwInverterSignal_U4/ctrlr<2>_MC.D2_PT_5/IN1 )
  );
  X_INV \NlwInverterBlock_DCORENCPWRw_MC.D1/IN0  (
    .I(\WR_II/UIM ),
    .O(\NlwInverterSignal_DCORENCPWRw_MC.D1/IN0 )
  );
  X_INV \NlwInverterBlock_DCORENCPWRw_MC.D1/IN2  (
    .I(U2_ADDR_reg[0]),
    .O(\NlwInverterSignal_DCORENCPWRw_MC.D1/IN2 )
  );
  X_INV \NlwInverterBlock_DCORENCPWRw_MC.D1/IN3  (
    .I(U2_ADDR_reg[4]),
    .O(\NlwInverterSignal_DCORENCPWRw_MC.D1/IN3 )
  );
  X_INV \NlwInverterBlock_DCORENCPWRw_MC.D1/IN4  (
    .I(U2_ADDR_reg[5]),
    .O(\NlwInverterSignal_DCORENCPWRw_MC.D1/IN4 )
  );
  X_INV \NlwInverterBlock_DCORENCPWRw_MC.D1/IN5  (
    .I(U2_ADDR_reg[6]),
    .O(\NlwInverterSignal_DCORENCPWRw_MC.D1/IN5 )
  );
  X_INV \NlwInverterBlock_DCORENCPWRw_MC.D1/IN6  (
    .I(U2_ADDR_reg[7]),
    .O(\NlwInverterSignal_DCORENCPWRw_MC.D1/IN6 )
  );
  X_INV \NlwInverterBlock_U4/ctrlr<3>_MC.D/IN0  (
    .I(\U4/ctrlr<3>_MC.D1 ),
    .O(\NlwInverterSignal_U4/ctrlr<3>_MC.D/IN0 )
  );
  X_INV \NlwInverterBlock_U4/ctrlr<3>_MC.D2_PT_0/IN1  (
    .I(\outDATA<3>\$WA0.UIM ),
    .O(\NlwInverterSignal_U4/ctrlr<3>_MC.D2_PT_0/IN1 )
  );
  X_INV \NlwInverterBlock_U4/ctrlr<3>_MC.D2_PT_1/IN1  (
    .I(\outDATA<3>\$WA1.UIM ),
    .O(\NlwInverterSignal_U4/ctrlr<3>_MC.D2_PT_1/IN1 )
  );
  X_INV \NlwInverterBlock_U4/ctrlr<3>_MC.D2_PT_2/IN1  (
    .I(\outDATA<3>\$WA2.UIM ),
    .O(\NlwInverterSignal_U4/ctrlr<3>_MC.D2_PT_2/IN1 )
  );
  X_INV \NlwInverterBlock_U4/ctrlr<3>_MC.D2_PT_3/IN1  (
    .I(\outDATA<3>\$WA3.UIM ),
    .O(\NlwInverterSignal_U4/ctrlr<3>_MC.D2_PT_3/IN1 )
  );
  X_INV \NlwInverterBlock_U4/ctrlr<3>_MC.D2_PT_4/IN0  (
    .I(N_PZ_961),
    .O(\NlwInverterSignal_U4/ctrlr<3>_MC.D2_PT_4/IN0 )
  );
  X_INV \NlwInverterBlock_U4/ctrlr<3>_MC.D2_PT_4/IN1  (
    .I(\outDATA<3>\$WA5.UIM ),
    .O(\NlwInverterSignal_U4/ctrlr<3>_MC.D2_PT_4/IN1 )
  );
  X_INV \NlwInverterBlock_U4/ctrlr<3>_MC.D2_PT_5/IN0  (
    .I(N_PZ_987),
    .O(\NlwInverterSignal_U4/ctrlr<3>_MC.D2_PT_5/IN0 )
  );
  X_INV \NlwInverterBlock_U4/ctrlr<3>_MC.D2_PT_5/IN1  (
    .I(\outDATA<3>\$WA6.UIM ),
    .O(\NlwInverterSignal_U4/ctrlr<3>_MC.D2_PT_5/IN1 )
  );
  X_INV \NlwInverterBlock_Enc05ctrl_MC.D/IN0  (
    .I(\Enc05ctrl_MC.D1 ),
    .O(\NlwInverterSignal_Enc05ctrl_MC.D/IN0 )
  );
  X_INV \NlwInverterBlock_Enc05ctrl_MC.D1/IN0  (
    .I(\U4/ctrlr[2] ),
    .O(\NlwInverterSignal_Enc05ctrl_MC.D1/IN0 )
  );
  X_INV \NlwInverterBlock_Enc133ctrl_MC.D/IN0  (
    .I(\Enc133ctrl_MC.D1 ),
    .O(\NlwInverterSignal_Enc133ctrl_MC.D/IN0 )
  );
  X_INV \NlwInverterBlock_U4/ctrlr<6>_MC.D/IN0  (
    .I(\U4/ctrlr<6>_MC.D1 ),
    .O(\NlwInverterSignal_U4/ctrlr<6>_MC.D/IN0 )
  );
  X_INV \NlwInverterBlock_U4/ctrlr<6>_MC.D2_PT_0/IN1  (
    .I(\outDATA<6>\$WA0.UIM ),
    .O(\NlwInverterSignal_U4/ctrlr<6>_MC.D2_PT_0/IN1 )
  );
  X_INV \NlwInverterBlock_U4/ctrlr<6>_MC.D2_PT_1/IN1  (
    .I(\outDATA<6>\$WA1.UIM ),
    .O(\NlwInverterSignal_U4/ctrlr<6>_MC.D2_PT_1/IN1 )
  );
  X_INV \NlwInverterBlock_U4/ctrlr<6>_MC.D2_PT_2/IN1  (
    .I(\outDATA<6>\$WA2.UIM ),
    .O(\NlwInverterSignal_U4/ctrlr<6>_MC.D2_PT_2/IN1 )
  );
  X_INV \NlwInverterBlock_U4/ctrlr<6>_MC.D2_PT_3/IN1  (
    .I(\outDATA<6>\$WA3.UIM ),
    .O(\NlwInverterSignal_U4/ctrlr<6>_MC.D2_PT_3/IN1 )
  );
  X_INV \NlwInverterBlock_U4/ctrlr<6>_MC.D2_PT_4/IN0  (
    .I(N_PZ_961),
    .O(\NlwInverterSignal_U4/ctrlr<6>_MC.D2_PT_4/IN0 )
  );
  X_INV \NlwInverterBlock_U4/ctrlr<6>_MC.D2_PT_4/IN1  (
    .I(\outDATA<6>\$WA5.UIM ),
    .O(\NlwInverterSignal_U4/ctrlr<6>_MC.D2_PT_4/IN1 )
  );
  X_INV \NlwInverterBlock_U4/ctrlr<6>_MC.D2_PT_5/IN0  (
    .I(N_PZ_987),
    .O(\NlwInverterSignal_U4/ctrlr<6>_MC.D2_PT_5/IN0 )
  );
  X_INV \NlwInverterBlock_U4/ctrlr<6>_MC.D2_PT_5/IN1  (
    .I(\outDATA<6>\$WA6.UIM ),
    .O(\NlwInverterSignal_U4/ctrlr<6>_MC.D2_PT_5/IN1 )
  );
  X_INV \NlwInverterBlock_U4/ctrlr<7>_MC.D/IN0  (
    .I(\U4/ctrlr<7>_MC.D1 ),
    .O(\NlwInverterSignal_U4/ctrlr<7>_MC.D/IN0 )
  );
  X_INV \NlwInverterBlock_U4/ctrlr<7>_MC.D2_PT_0/IN1  (
    .I(\outDATA<7>\$WA0.UIM ),
    .O(\NlwInverterSignal_U4/ctrlr<7>_MC.D2_PT_0/IN1 )
  );
  X_INV \NlwInverterBlock_U4/ctrlr<7>_MC.D2_PT_1/IN1  (
    .I(\outDATA<7>\$WA1.UIM ),
    .O(\NlwInverterSignal_U4/ctrlr<7>_MC.D2_PT_1/IN1 )
  );
  X_INV \NlwInverterBlock_U4/ctrlr<7>_MC.D2_PT_2/IN1  (
    .I(\outDATA<7>\$WA2.UIM ),
    .O(\NlwInverterSignal_U4/ctrlr<7>_MC.D2_PT_2/IN1 )
  );
  X_INV \NlwInverterBlock_U4/ctrlr<7>_MC.D2_PT_3/IN1  (
    .I(\outDATA<7>\$WA3.UIM ),
    .O(\NlwInverterSignal_U4/ctrlr<7>_MC.D2_PT_3/IN1 )
  );
  X_INV \NlwInverterBlock_U4/ctrlr<7>_MC.D2_PT_4/IN0  (
    .I(N_PZ_961),
    .O(\NlwInverterSignal_U4/ctrlr<7>_MC.D2_PT_4/IN0 )
  );
  X_INV \NlwInverterBlock_U4/ctrlr<7>_MC.D2_PT_4/IN1  (
    .I(\outDATA<7>\$WA5.UIM ),
    .O(\NlwInverterSignal_U4/ctrlr<7>_MC.D2_PT_4/IN1 )
  );
  X_INV \NlwInverterBlock_U4/ctrlr<7>_MC.D2_PT_5/IN0  (
    .I(\outDATA<7>\$WA4.UIM ),
    .O(\NlwInverterSignal_U4/ctrlr<7>_MC.D2_PT_5/IN0 )
  );
  X_INV \NlwInverterBlock_U4/ctrlr<7>_MC.D2_PT_6/IN1  (
    .I(\outDATA<7>\$WA6.UIM ),
    .O(\NlwInverterSignal_U4/ctrlr<7>_MC.D2_PT_6/IN1 )
  );
  X_INV \NlwInverterBlock_U4/ctrlr<7>_MC.D2_PT_7/IN0  (
    .I(N_PZ_987),
    .O(\NlwInverterSignal_U4/ctrlr<7>_MC.D2_PT_7/IN0 )
  );
  X_INV \NlwInverterBlock_U4/ctrlr<7>_MC.D2_PT_7/IN1  (
    .I(DCORIFGr),
    .O(\NlwInverterSignal_U4/ctrlr<7>_MC.D2_PT_7/IN1 )
  );
  X_INV \NlwInverterBlock_U4/ctrlr<7>_MC.D2_PT_7/IN2  (
    .I(\outDATA<7>\$WA6.UIM ),
    .O(\NlwInverterSignal_U4/ctrlr<7>_MC.D2_PT_7/IN2 )
  );
  X_INV \NlwInverterBlock_Enc15ctrl_MC.D/IN0  (
    .I(\Enc15ctrl_MC.D1 ),
    .O(\NlwInverterSignal_Enc15ctrl_MC.D/IN0 )
  );
  X_INV \NlwInverterBlock_Enc15ctrl_MC.D1/IN0  (
    .I(\U4/ctrlr[6] ),
    .O(\NlwInverterSignal_Enc15ctrl_MC.D1/IN0 )
  );
  X_INV \NlwInverterBlock_DCOROUTw_MC.D1/IN0  (
    .I(\WR_II/UIM ),
    .O(\NlwInverterSignal_DCOROUTw_MC.D1/IN0 )
  );
  X_INV \NlwInverterBlock_DCOROUTw_MC.D1/IN3  (
    .I(U2_ADDR_reg[4]),
    .O(\NlwInverterSignal_DCOROUTw_MC.D1/IN3 )
  );
  X_INV \NlwInverterBlock_DCOROUTw_MC.D1/IN4  (
    .I(U2_ADDR_reg[5]),
    .O(\NlwInverterSignal_DCOROUTw_MC.D1/IN4 )
  );
  X_INV \NlwInverterBlock_DCOROUTw_MC.D1/IN5  (
    .I(U2_ADDR_reg[6]),
    .O(\NlwInverterSignal_DCOROUTw_MC.D1/IN5 )
  );
  X_INV \NlwInverterBlock_DCOROUTw_MC.D1/IN6  (
    .I(U2_ADDR_reg[7]),
    .O(\NlwInverterSignal_DCOROUTw_MC.D1/IN6 )
  );
  X_INV \NlwInverterBlock_Home033ctrl_MC.D/IN0  (
    .I(\Home033ctrl_MC.D1 ),
    .O(\NlwInverterSignal_Home033ctrl_MC.D/IN0 )
  );
  X_INV \NlwInverterBlock_Home05ctrl_MC.D/IN0  (
    .I(\Home05ctrl_MC.D1 ),
    .O(\NlwInverterSignal_Home05ctrl_MC.D/IN0 )
  );
  X_INV \NlwInverterBlock_Home133ctrl_MC.D/IN0  (
    .I(\Home133ctrl_MC.D1 ),
    .O(\NlwInverterSignal_Home133ctrl_MC.D/IN0 )
  );
  X_INV \NlwInverterBlock_Home15ctrl_MC.D/IN0  (
    .I(\Home15ctrl_MC.D1 ),
    .O(\NlwInverterSignal_Home15ctrl_MC.D/IN0 )
  );
  X_INV \NlwInverterBlock_INT_MC.D2_PT_6/IN0  (
    .I(\INTbus_II/UIM ),
    .O(\NlwInverterSignal_INT_MC.D2_PT_6/IN0 )
  );
  X_INV \NlwInverterBlock_U3/DCORIE<0>_MC.D2_PT_1/IN2  (
    .I(DCORIEw),
    .O(\NlwInverterSignal_U3/DCORIE<0>_MC.D2_PT_1/IN2 )
  );
  X_INV \NlwInverterBlock_DCORIEw_MC.D1/IN0  (
    .I(\WR_II/UIM ),
    .O(\NlwInverterSignal_DCORIEw_MC.D1/IN0 )
  );
  X_INV \NlwInverterBlock_DCORIEw_MC.D1/IN2  (
    .I(U2_ADDR_reg[0]),
    .O(\NlwInverterSignal_DCORIEw_MC.D1/IN2 )
  );
  X_INV \NlwInverterBlock_DCORIEw_MC.D1/IN3  (
    .I(U2_ADDR_reg[4]),
    .O(\NlwInverterSignal_DCORIEw_MC.D1/IN3 )
  );
  X_INV \NlwInverterBlock_DCORIEw_MC.D1/IN4  (
    .I(U2_ADDR_reg[5]),
    .O(\NlwInverterSignal_DCORIEw_MC.D1/IN4 )
  );
  X_INV \NlwInverterBlock_DCORIEw_MC.D1/IN5  (
    .I(U2_ADDR_reg[6]),
    .O(\NlwInverterSignal_DCORIEw_MC.D1/IN5 )
  );
  X_INV \NlwInverterBlock_DCORIEw_MC.D1/IN6  (
    .I(U2_ADDR_reg[7]),
    .O(\NlwInverterSignal_DCORIEw_MC.D1/IN6 )
  );
  X_INV \NlwInverterBlock_DCORIEw_MC.D1/IN7  (
    .I(U2_ADDR_reg[3]),
    .O(\NlwInverterSignal_DCORIEw_MC.D1/IN7 )
  );
  X_INV \NlwInverterBlock_DCORIEw_MC.D1/IN8  (
    .I(U2_ADDR_reg[1]),
    .O(\NlwInverterSignal_DCORIEw_MC.D1/IN8 )
  );
  X_INV \NlwInverterBlock_DCORIEw_MC.D1/IN9  (
    .I(U2_ADDR_reg[2]),
    .O(\NlwInverterSignal_DCORIEw_MC.D1/IN9 )
  );
  X_INV \NlwInverterBlock_U3/DCORIE<1>_MC.D2_PT_1/IN2  (
    .I(DCORIEw),
    .O(\NlwInverterSignal_U3/DCORIE<1>_MC.D2_PT_1/IN2 )
  );
  X_INV \NlwInverterBlock_U3/DCORIE<2>_MC.D2_PT_1/IN2  (
    .I(DCORIEw),
    .O(\NlwInverterSignal_U3/DCORIE<2>_MC.D2_PT_1/IN2 )
  );
  X_INV \NlwInverterBlock_U3/DCORIE<3>_MC.D2_PT_1/IN2  (
    .I(DCORIEw),
    .O(\NlwInverterSignal_U3/DCORIE<3>_MC.D2_PT_1/IN2 )
  );
  X_INV \NlwInverterBlock_NET2575_MC.D2_PT_0/IN1  (
    .I(\AD<4>_II/UIM ),
    .O(\NlwInverterSignal_NET2575_MC.D2_PT_0/IN1 )
  );
  X_INV \NlwInverterBlock_NET2575_MC.D2_PT_1/IN1  (
    .I(\FLS1_II/UIM ),
    .O(\NlwInverterSignal_NET2575_MC.D2_PT_1/IN1 )
  );
  X_INV \NlwInverterBlock_NET2575_MC.D2_PT_2/IN1  (
    .I(DCORIFGw),
    .O(\NlwInverterSignal_NET2575_MC.D2_PT_2/IN1 )
  );
  X_INV \NlwInverterBlock_NET2575_MC.D2_PT_3/IN2  (
    .I(\FLS0_II/UIM ),
    .O(\NlwInverterSignal_NET2575_MC.D2_PT_3/IN2 )
  );
  X_INV \NlwInverterBlock_NET2575_MC.D2_PT_4/IN1  (
    .I(\DIR0_II/UIM ),
    .O(\NlwInverterSignal_NET2575_MC.D2_PT_4/IN1 )
  );
  X_INV \NlwInverterBlock_NET2575_MC.D2_PT_4/IN2  (
    .I(\RLS0_II/UIM ),
    .O(\NlwInverterSignal_NET2575_MC.D2_PT_4/IN2 )
  );
  X_INV \NlwInverterBlock_NET2575_MC.D2_PT_5/IN1  (
    .I(\DIR1_II/UIM ),
    .O(\NlwInverterSignal_NET2575_MC.D2_PT_5/IN1 )
  );
  X_INV \NlwInverterBlock_NET2575_MC.D2_PT_5/IN2  (
    .I(\RLS1_II/UIM ),
    .O(\NlwInverterSignal_NET2575_MC.D2_PT_5/IN2 )
  );
  X_INV \NlwInverterBlock_U3/DCORIE<4>_MC.D2_PT_1/IN2  (
    .I(DCORIEw),
    .O(\NlwInverterSignal_U3/DCORIE<4>_MC.D2_PT_1/IN2 )
  );
  X_INV \NlwInverterBlock_U3/DCORIE<5>_MC.D2_PT_1/IN2  (
    .I(DCORIEw),
    .O(\NlwInverterSignal_U3/DCORIE<5>_MC.D2_PT_1/IN2 )
  );
  X_INV \NlwInverterBlock_U3/DCORIE<6>_MC.D2_PT_1/IN2  (
    .I(DCORIEw),
    .O(\NlwInverterSignal_U3/DCORIE<6>_MC.D2_PT_1/IN2 )
  );
  X_INV \NlwInverterBlock_U3/DCORIE<7>_MC.D2_PT_1/IN2  (
    .I(DCORIEw),
    .O(\NlwInverterSignal_U3/DCORIE<7>_MC.D2_PT_1/IN2 )
  );
  X_INV \NlwInverterBlock_LED1_MC.D/IN0  (
    .I(\LED1_MC.D1 ),
    .O(\NlwInverterSignal_LED1_MC.D/IN0 )
  );
  X_INV \NlwInverterBlock_LED1_MC.D1/IN1  (
    .I(\U9/MISCr [0]),
    .O(\NlwInverterSignal_LED1_MC.D1/IN1 )
  );
  X_INV \NlwInverterBlock_U9/MISCr<0>_MC.D/IN0  (
    .I(\U9/MISCr<0>_MC.D1 ),
    .O(\NlwInverterSignal_U9/MISCr<0>_MC.D/IN0 )
  );
  X_INV \NlwInverterBlock_U9/MISCr<0>_MC.D2_PT_0/IN1  (
    .I(\outDATA<0>\$WA0.UIM ),
    .O(\NlwInverterSignal_U9/MISCr<0>_MC.D2_PT_0/IN1 )
  );
  X_INV \NlwInverterBlock_U9/MISCr<0>_MC.D2_PT_1/IN1  (
    .I(\outDATA<0>\$WA1.UIM ),
    .O(\NlwInverterSignal_U9/MISCr<0>_MC.D2_PT_1/IN1 )
  );
  X_INV \NlwInverterBlock_U9/MISCr<0>_MC.D2_PT_2/IN1  (
    .I(\outDATA<0>\$WA2.UIM ),
    .O(\NlwInverterSignal_U9/MISCr<0>_MC.D2_PT_2/IN1 )
  );
  X_INV \NlwInverterBlock_U9/MISCr<0>_MC.D2_PT_3/IN1  (
    .I(\outDATA<0>\$WA3.UIM ),
    .O(\NlwInverterSignal_U9/MISCr<0>_MC.D2_PT_3/IN1 )
  );
  X_INV \NlwInverterBlock_U9/MISCr<0>_MC.D2_PT_4/IN0  (
    .I(N_PZ_961),
    .O(\NlwInverterSignal_U9/MISCr<0>_MC.D2_PT_4/IN0 )
  );
  X_INV \NlwInverterBlock_U9/MISCr<0>_MC.D2_PT_4/IN1  (
    .I(\outDATA<0>\$WA5.UIM ),
    .O(\NlwInverterSignal_U9/MISCr<0>_MC.D2_PT_4/IN1 )
  );
  X_INV \NlwInverterBlock_U9/MISCr<0>_MC.D2_PT_5/IN1  (
    .I(\outDATA<0>\$WA6.UIM ),
    .O(\NlwInverterSignal_U9/MISCr<0>_MC.D2_PT_5/IN1 )
  );
  X_INV \NlwInverterBlock_U9/MISCr<0>_MC.D2_PT_6/IN1  (
    .I(\outDATA<0>\$WA4.UIM ),
    .O(\NlwInverterSignal_U9/MISCr<0>_MC.D2_PT_6/IN1 )
  );
  X_INV \NlwInverterBlock_U9/MISCr<0>_MC.D2_PT_7/IN0  (
    .I(N_PZ_987),
    .O(\NlwInverterSignal_U9/MISCr<0>_MC.D2_PT_7/IN0 )
  );
  X_INV \NlwInverterBlock_U9/MISCr<0>_MC.D2_PT_7/IN1  (
    .I(DCORIFGr),
    .O(\NlwInverterSignal_U9/MISCr<0>_MC.D2_PT_7/IN1 )
  );
  X_INV \NlwInverterBlock_U9/MISCr<0>_MC.D2_PT_7/IN2  (
    .I(\outDATA<0>\$WA6.UIM ),
    .O(\NlwInverterSignal_U9/MISCr<0>_MC.D2_PT_7/IN2 )
  );
  X_INV \NlwInverterBlock_LED2_MC.D/IN0  (
    .I(\LED2_MC.D1 ),
    .O(\NlwInverterSignal_LED2_MC.D/IN0 )
  );
  X_INV \NlwInverterBlock_LED2_MC.D1/IN1  (
    .I(\U9/MISCr [1]),
    .O(\NlwInverterSignal_LED2_MC.D1/IN1 )
  );
  X_INV \NlwInverterBlock_U9/MISCr<1>_MC.D/IN0  (
    .I(\U9/MISCr<1>_MC.D1 ),
    .O(\NlwInverterSignal_U9/MISCr<1>_MC.D/IN0 )
  );
  X_INV \NlwInverterBlock_U9/MISCr<1>_MC.D2_PT_0/IN1  (
    .I(\outDATA<1>\$WA0.UIM ),
    .O(\NlwInverterSignal_U9/MISCr<1>_MC.D2_PT_0/IN1 )
  );
  X_INV \NlwInverterBlock_U9/MISCr<1>_MC.D2_PT_1/IN1  (
    .I(\outDATA<1>\$WA1.UIM ),
    .O(\NlwInverterSignal_U9/MISCr<1>_MC.D2_PT_1/IN1 )
  );
  X_INV \NlwInverterBlock_U9/MISCr<1>_MC.D2_PT_2/IN1  (
    .I(\outDATA<1>\$WA2.UIM ),
    .O(\NlwInverterSignal_U9/MISCr<1>_MC.D2_PT_2/IN1 )
  );
  X_INV \NlwInverterBlock_U9/MISCr<1>_MC.D2_PT_3/IN1  (
    .I(\outDATA<1>\$WA3.UIM ),
    .O(\NlwInverterSignal_U9/MISCr<1>_MC.D2_PT_3/IN1 )
  );
  X_INV \NlwInverterBlock_U9/MISCr<1>_MC.D2_PT_4/IN0  (
    .I(N_PZ_961),
    .O(\NlwInverterSignal_U9/MISCr<1>_MC.D2_PT_4/IN0 )
  );
  X_INV \NlwInverterBlock_U9/MISCr<1>_MC.D2_PT_4/IN1  (
    .I(\outDATA<1>\$WA5.UIM ),
    .O(\NlwInverterSignal_U9/MISCr<1>_MC.D2_PT_4/IN1 )
  );
  X_INV \NlwInverterBlock_U9/MISCr<1>_MC.D2_PT_5/IN1  (
    .I(\outDATA<1>\$WA6.UIM ),
    .O(\NlwInverterSignal_U9/MISCr<1>_MC.D2_PT_5/IN1 )
  );
  X_INV \NlwInverterBlock_U9/MISCr<1>_MC.D2_PT_6/IN1  (
    .I(\outDATA<1>\$WA3.UIM ),
    .O(\NlwInverterSignal_U9/MISCr<1>_MC.D2_PT_6/IN1 )
  );
  X_INV \NlwInverterBlock_U9/MISCr<1>_MC.D2_PT_7/IN0  (
    .I(N_PZ_987),
    .O(\NlwInverterSignal_U9/MISCr<1>_MC.D2_PT_7/IN0 )
  );
  X_INV \NlwInverterBlock_U9/MISCr<1>_MC.D2_PT_7/IN1  (
    .I(DCORIFGr),
    .O(\NlwInverterSignal_U9/MISCr<1>_MC.D2_PT_7/IN1 )
  );
  X_INV \NlwInverterBlock_U9/MISCr<1>_MC.D2_PT_7/IN2  (
    .I(\outDATA<1>\$WA6.UIM ),
    .O(\NlwInverterSignal_U9/MISCr<1>_MC.D2_PT_7/IN2 )
  );
  X_INV \NlwInverterBlock_LED3_MC.D/IN0  (
    .I(\LED3_MC.D1 ),
    .O(\NlwInverterSignal_LED3_MC.D/IN0 )
  );
  X_INV \NlwInverterBlock_LED3_MC.D1/IN1  (
    .I(\U9/MISCr [2]),
    .O(\NlwInverterSignal_LED3_MC.D1/IN1 )
  );
  X_INV \NlwInverterBlock_LED4_MC.D/IN0  (
    .I(\LED4_MC.D1 ),
    .O(\NlwInverterSignal_LED4_MC.D/IN0 )
  );
  X_INV \NlwInverterBlock_LED4_MC.D1/IN1  (
    .I(\U9/MISCr [3]),
    .O(\NlwInverterSignal_LED4_MC.D1/IN1 )
  );
  X_INV \NlwInverterBlock_LED5_MC.D/IN0  (
    .I(\LED5_MC.D1 ),
    .O(\NlwInverterSignal_LED5_MC.D/IN0 )
  );
  X_INV \NlwInverterBlock_LED5_MC.D1/IN1  (
    .I(\U9/MISCr [4]),
    .O(\NlwInverterSignal_LED5_MC.D1/IN1 )
  );
  X_INV \NlwInverterBlock_U9/MISCr<4>_MC.D/IN0  (
    .I(\U9/MISCr<4>_MC.D1 ),
    .O(\NlwInverterSignal_U9/MISCr<4>_MC.D/IN0 )
  );
  X_INV \NlwInverterBlock_U9/MISCr<4>_MC.D2_PT_0/IN1  (
    .I(\outDATA<4>\$WA0.UIM ),
    .O(\NlwInverterSignal_U9/MISCr<4>_MC.D2_PT_0/IN1 )
  );
  X_INV \NlwInverterBlock_U9/MISCr<4>_MC.D2_PT_1/IN1  (
    .I(\outDATA<4>\$WA1.UIM ),
    .O(\NlwInverterSignal_U9/MISCr<4>_MC.D2_PT_1/IN1 )
  );
  X_INV \NlwInverterBlock_U9/MISCr<4>_MC.D2_PT_2/IN1  (
    .I(\outDATA<4>\$WA2.UIM ),
    .O(\NlwInverterSignal_U9/MISCr<4>_MC.D2_PT_2/IN1 )
  );
  X_INV \NlwInverterBlock_U9/MISCr<4>_MC.D2_PT_3/IN1  (
    .I(\outDATA<4>\$WA3.UIM ),
    .O(\NlwInverterSignal_U9/MISCr<4>_MC.D2_PT_3/IN1 )
  );
  X_INV \NlwInverterBlock_U9/MISCr<4>_MC.D2_PT_4/IN0  (
    .I(N_PZ_961),
    .O(\NlwInverterSignal_U9/MISCr<4>_MC.D2_PT_4/IN0 )
  );
  X_INV \NlwInverterBlock_U9/MISCr<4>_MC.D2_PT_4/IN1  (
    .I(\outDATA<4>\$WA5.UIM ),
    .O(\NlwInverterSignal_U9/MISCr<4>_MC.D2_PT_4/IN1 )
  );
  X_INV \NlwInverterBlock_U9/MISCr<4>_MC.D2_PT_5/IN1  (
    .I(\outDATA<4>\$WA6.UIM ),
    .O(\NlwInverterSignal_U9/MISCr<4>_MC.D2_PT_5/IN1 )
  );
  X_INV \NlwInverterBlock_U9/MISCr<4>_MC.D2_PT_6/IN1  (
    .I(\outDATA<4>\$WA4.UIM ),
    .O(\NlwInverterSignal_U9/MISCr<4>_MC.D2_PT_6/IN1 )
  );
  X_INV \NlwInverterBlock_U9/MISCr<4>_MC.D2_PT_7/IN0  (
    .I(N_PZ_987),
    .O(\NlwInverterSignal_U9/MISCr<4>_MC.D2_PT_7/IN0 )
  );
  X_INV \NlwInverterBlock_U9/MISCr<4>_MC.D2_PT_7/IN1  (
    .I(DCORIFGr),
    .O(\NlwInverterSignal_U9/MISCr<4>_MC.D2_PT_7/IN1 )
  );
  X_INV \NlwInverterBlock_U9/MISCr<4>_MC.D2_PT_7/IN2  (
    .I(\outDATA<4>\$WA6.UIM ),
    .O(\NlwInverterSignal_U9/MISCr<4>_MC.D2_PT_7/IN2 )
  );
  X_INV \NlwInverterBlock_MTRpwrn_MC.D/IN0  (
    .I(\MTRpwrn_MC.D1 ),
    .O(\NlwInverterSignal_MTRpwrn_MC.D/IN0 )
  );
  X_INV \NlwInverterBlock_PAH0_MC.D1/IN0  (
    .I(\Brake0_II/UIM ),
    .O(\NlwInverterSignal_PAH0_MC.D1/IN0 )
  );
  X_INV \NlwInverterBlock_PAH0_MC.D1/IN1  (
    .I(\DIR0_II/UIM ),
    .O(\NlwInverterSignal_PAH0_MC.D1/IN1 )
  );
  X_INV \NlwInverterBlock_PAH0_MC.D1/IN3  (
    .I(NET3248),
    .O(\NlwInverterSignal_PAH0_MC.D1/IN3 )
  );
  X_INV \NlwInverterBlock_NET3248_MC.D2_PT_0/IN1  (
    .I(\Brake0_II/UIM ),
    .O(\NlwInverterSignal_NET3248_MC.D2_PT_0/IN1 )
  );
  X_INV \NlwInverterBlock_NET3248_MC.D2_PT_1/IN2  (
    .I(\FLS0_II/UIM ),
    .O(\NlwInverterSignal_NET3248_MC.D2_PT_1/IN2 )
  );
  X_INV \NlwInverterBlock_NET3248_MC.D2_PT_2/IN1  (
    .I(\DIR0_II/UIM ),
    .O(\NlwInverterSignal_NET3248_MC.D2_PT_2/IN1 )
  );
  X_INV \NlwInverterBlock_NET3248_MC.D2_PT_2/IN2  (
    .I(\RLS0_II/UIM ),
    .O(\NlwInverterSignal_NET3248_MC.D2_PT_2/IN2 )
  );
  X_INV \NlwInverterBlock_PAH1_MC.D1/IN0  (
    .I(\Brake1_II/UIM ),
    .O(\NlwInverterSignal_PAH1_MC.D1/IN0 )
  );
  X_INV \NlwInverterBlock_PAH1_MC.D1/IN1  (
    .I(\DIR1_II/UIM ),
    .O(\NlwInverterSignal_PAH1_MC.D1/IN1 )
  );
  X_INV \NlwInverterBlock_PAH1_MC.D1/IN3  (
    .I(NET3253),
    .O(\NlwInverterSignal_PAH1_MC.D1/IN3 )
  );
  X_INV \NlwInverterBlock_NET3253_MC.D2_PT_0/IN1  (
    .I(\FLS1_II/UIM ),
    .O(\NlwInverterSignal_NET3253_MC.D2_PT_0/IN1 )
  );
  X_INV \NlwInverterBlock_NET3253_MC.D2_PT_1/IN1  (
    .I(\Brake1_II/UIM ),
    .O(\NlwInverterSignal_NET3253_MC.D2_PT_1/IN1 )
  );
  X_INV \NlwInverterBlock_NET3253_MC.D2_PT_2/IN1  (
    .I(\DIR1_II/UIM ),
    .O(\NlwInverterSignal_NET3253_MC.D2_PT_2/IN1 )
  );
  X_INV \NlwInverterBlock_NET3253_MC.D2_PT_2/IN2  (
    .I(\RLS1_II/UIM ),
    .O(\NlwInverterSignal_NET3253_MC.D2_PT_2/IN2 )
  );
  X_INV \NlwInverterBlock_PAL0_MC.D2_PT_1/IN0  (
    .I(\Brake0_II/UIM ),
    .O(\NlwInverterSignal_PAL0_MC.D2_PT_1/IN0 )
  );
  X_INV \NlwInverterBlock_PAL0_MC.D2_PT_1/IN2  (
    .I(\PWM1_II/UIM ),
    .O(\NlwInverterSignal_PAL0_MC.D2_PT_1/IN2 )
  );
  X_INV \NlwInverterBlock_PAL0_MC.D2_PT_1/IN3  (
    .I(NET3248),
    .O(\NlwInverterSignal_PAL0_MC.D2_PT_1/IN3 )
  );
  X_INV \NlwInverterBlock_PAL1_MC.D2_PT_1/IN0  (
    .I(\Brake1_II/UIM ),
    .O(\NlwInverterSignal_PAL1_MC.D2_PT_1/IN0 )
  );
  X_INV \NlwInverterBlock_PAL1_MC.D2_PT_1/IN2  (
    .I(\PWM2_II/UIM ),
    .O(\NlwInverterSignal_PAL1_MC.D2_PT_1/IN2 )
  );
  X_INV \NlwInverterBlock_PAL1_MC.D2_PT_1/IN3  (
    .I(NET3253),
    .O(\NlwInverterSignal_PAL1_MC.D2_PT_1/IN3 )
  );
  X_INV \NlwInverterBlock_PBH0_MC.D1/IN0  (
    .I(\Brake0_II/UIM ),
    .O(\NlwInverterSignal_PBH0_MC.D1/IN0 )
  );
  X_INV \NlwInverterBlock_PBH0_MC.D1/IN3  (
    .I(NET3248),
    .O(\NlwInverterSignal_PBH0_MC.D1/IN3 )
  );
  X_INV \NlwInverterBlock_PBH1_MC.D1/IN0  (
    .I(\Brake1_II/UIM ),
    .O(\NlwInverterSignal_PBH1_MC.D1/IN0 )
  );
  X_INV \NlwInverterBlock_PBH1_MC.D1/IN3  (
    .I(NET3253),
    .O(\NlwInverterSignal_PBH1_MC.D1/IN3 )
  );
  X_INV \NlwInverterBlock_PBL0_MC.D2_PT_1/IN0  (
    .I(\Brake0_II/UIM ),
    .O(\NlwInverterSignal_PBL0_MC.D2_PT_1/IN0 )
  );
  X_INV \NlwInverterBlock_PBL0_MC.D2_PT_1/IN1  (
    .I(\DIR0_II/UIM ),
    .O(\NlwInverterSignal_PBL0_MC.D2_PT_1/IN1 )
  );
  X_INV \NlwInverterBlock_PBL0_MC.D2_PT_1/IN2  (
    .I(\PWM1_II/UIM ),
    .O(\NlwInverterSignal_PBL0_MC.D2_PT_1/IN2 )
  );
  X_INV \NlwInverterBlock_PBL0_MC.D2_PT_1/IN3  (
    .I(NET3248),
    .O(\NlwInverterSignal_PBL0_MC.D2_PT_1/IN3 )
  );
  X_INV \NlwInverterBlock_PBL1_MC.D2_PT_1/IN0  (
    .I(\Brake1_II/UIM ),
    .O(\NlwInverterSignal_PBL1_MC.D2_PT_1/IN0 )
  );
  X_INV \NlwInverterBlock_PBL1_MC.D2_PT_1/IN1  (
    .I(\DIR1_II/UIM ),
    .O(\NlwInverterSignal_PBL1_MC.D2_PT_1/IN1 )
  );
  X_INV \NlwInverterBlock_PBL1_MC.D2_PT_1/IN2  (
    .I(\PWM2_II/UIM ),
    .O(\NlwInverterSignal_PBL1_MC.D2_PT_1/IN2 )
  );
  X_INV \NlwInverterBlock_PBL1_MC.D2_PT_1/IN3  (
    .I(NET3253),
    .O(\NlwInverterSignal_PBL1_MC.D2_PT_1/IN3 )
  );
  X_INV \NlwInverterBlock_PresEn_MC.D/IN0  (
    .I(\PresEn_MC.D1 ),
    .O(\NlwInverterSignal_PresEn_MC.D/IN0 )
  );
  X_INV \NlwInverterBlock_DCORSENSORw_MC.D1/IN0  (
    .I(\WR_II/UIM ),
    .O(\NlwInverterSignal_DCORSENSORw_MC.D1/IN0 )
  );
  X_INV \NlwInverterBlock_DCORSENSORw_MC.D1/IN2  (
    .I(U2_ADDR_reg[0]),
    .O(\NlwInverterSignal_DCORSENSORw_MC.D1/IN2 )
  );
  X_INV \NlwInverterBlock_DCORSENSORw_MC.D1/IN3  (
    .I(U2_ADDR_reg[4]),
    .O(\NlwInverterSignal_DCORSENSORw_MC.D1/IN3 )
  );
  X_INV \NlwInverterBlock_DCORSENSORw_MC.D1/IN4  (
    .I(U2_ADDR_reg[5]),
    .O(\NlwInverterSignal_DCORSENSORw_MC.D1/IN4 )
  );
  X_INV \NlwInverterBlock_DCORSENSORw_MC.D1/IN5  (
    .I(U2_ADDR_reg[6]),
    .O(\NlwInverterSignal_DCORSENSORw_MC.D1/IN5 )
  );
  X_INV \NlwInverterBlock_DCORSENSORw_MC.D1/IN6  (
    .I(U2_ADDR_reg[7]),
    .O(\NlwInverterSignal_DCORSENSORw_MC.D1/IN6 )
  );
  X_INV \NlwInverterBlock_DCORSENSORw_MC.D1/IN8  (
    .I(U2_ADDR_reg[1]),
    .O(\NlwInverterSignal_DCORSENSORw_MC.D1/IN8 )
  );
  X_INV \NlwInverterBlock_TP11_MC.D/IN0  (
    .I(\TP11_MC.D1 ),
    .O(\NlwInverterSignal_TP11_MC.D/IN0 )
  );
  X_INV \NlwInverterBlock_TmpEn_MC.D/IN0  (
    .I(\TmpEn_MC.D1 ),
    .O(\NlwInverterSignal_TmpEn_MC.D/IN0 )
  );
  X_INV \NlwInverterBlock_outDATA<2>\$WA3.UIM_MC.D2_PT_1/IN0  (
    .I(NET2528),
    .O(\NlwInverterSignal_outDATA<2>\$WA3.UIM_MC.D2_PT_1/IN0 )
  );
  X_INV \NlwInverterBlock_outDATA<2>\$WA5.UIM_MC.D2_PT_1/IN0  (
    .I(DCOR0CNTLOWr),
    .O(\NlwInverterSignal_outDATA<2>\$WA5.UIM_MC.D2_PT_1/IN0 )
  );
  X_INV \NlwInverterBlock_outDATA<2>\$WA5.UIM_MC.D2_PT_2/IN0  (
    .I(DCOR0CNTLOWr),
    .O(\NlwInverterSignal_outDATA<2>\$WA5.UIM_MC.D2_PT_2/IN0 )
  );
  X_INV \NlwInverterBlock_outDATA<2>\$WA5.UIM_MC.D2_PT_2/IN1  (
    .I(DCOR1CNTLOWr),
    .O(\NlwInverterSignal_outDATA<2>\$WA5.UIM_MC.D2_PT_2/IN1 )
  );
  X_INV \NlwInverterBlock_outDATA<2>\$WA5.UIM_MC.D2_PT_3/IN0  (
    .I(DCOR0CNTLOWr),
    .O(\NlwInverterSignal_outDATA<2>\$WA5.UIM_MC.D2_PT_3/IN0 )
  );
  X_INV \NlwInverterBlock_outDATA<2>\$WA5.UIM_MC.D2_PT_3/IN1  (
    .I(DCOR1CNTLOWr),
    .O(\NlwInverterSignal_outDATA<2>\$WA5.UIM_MC.D2_PT_3/IN1 )
  );
  X_INV \NlwInverterBlock_outDATA<2>\$WA5.UIM_MC.D2_PT_3/IN2  (
    .I(DCOR0CNTHIGHr),
    .O(\NlwInverterSignal_outDATA<2>\$WA5.UIM_MC.D2_PT_3/IN2 )
  );
  X_INV \NlwInverterBlock_U1/U3/holdingreg0<2>_MC.D2_PT_1/IN1  (
    .I(\AS_II/UIM ),
    .O(\NlwInverterSignal_U1/U3/holdingreg0<2>_MC.D2_PT_1/IN1 )
  );
  X_INV \NlwInverterBlock_U1/U3/holdingreg1<2>_MC.D2_PT_1/IN1  (
    .I(\AS_II/UIM ),
    .O(\NlwInverterSignal_U1/U3/holdingreg1<2>_MC.D2_PT_1/IN1 )
  );
  X_INV \NlwInverterBlock_U1/U3/holdingreg0<10>_MC.D2_PT_1/IN1  (
    .I(\AS_II/UIM ),
    .O(\NlwInverterSignal_U1/U3/holdingreg0<10>_MC.D2_PT_1/IN1 )
  );
  X_INV \NlwInverterBlock_U1/U3/holdingreg1<10>_MC.D2_PT_1/IN1  (
    .I(\AS_II/UIM ),
    .O(\NlwInverterSignal_U1/U3/holdingreg1<10>_MC.D2_PT_1/IN1 )
  );
  X_INV \NlwInverterBlock_outDATA<2>\$WA6.UIM_MC.D2_PT_1/IN1  (
    .I(DCOR0THRESLOWr),
    .O(\NlwInverterSignal_outDATA<2>\$WA6.UIM_MC.D2_PT_1/IN1 )
  );
  X_INV \NlwInverterBlock_outDATA<2>\$WA6.UIM_MC.D2_PT_2/IN0  (
    .I(DCOR0THRESLOWr),
    .O(\NlwInverterSignal_outDATA<2>\$WA6.UIM_MC.D2_PT_2/IN0 )
  );
  X_INV \NlwInverterBlock_outDATA<2>\$WA6.UIM_MC.D2_PT_2/IN1  (
    .I(DCORIFGr),
    .O(\NlwInverterSignal_outDATA<2>\$WA6.UIM_MC.D2_PT_2/IN1 )
  );
  X_INV \NlwInverterBlock_outDATA<2>\$WA6.UIM_MC.D2_PT_3/IN0  (
    .I(DCOR0THRESLOWr),
    .O(\NlwInverterSignal_outDATA<2>\$WA6.UIM_MC.D2_PT_3/IN0 )
  );
  X_INV \NlwInverterBlock_outDATA<2>\$WA6.UIM_MC.D2_PT_3/IN1  (
    .I(DCORIFGr),
    .O(\NlwInverterSignal_outDATA<2>\$WA6.UIM_MC.D2_PT_3/IN1 )
  );
  X_INV \NlwInverterBlock_outDATA<2>\$WA6.UIM_MC.D2_PT_3/IN2  (
    .I(DCOR0THRESHIGHr),
    .O(\NlwInverterSignal_outDATA<2>\$WA6.UIM_MC.D2_PT_3/IN2 )
  );
  X_INV \NlwInverterBlock_outDATA<2>\$WA6.UIM_MC.D2_PT_4/IN0  (
    .I(DCOR0THRESLOWr),
    .O(\NlwInverterSignal_outDATA<2>\$WA6.UIM_MC.D2_PT_4/IN0 )
  );
  X_INV \NlwInverterBlock_outDATA<2>\$WA6.UIM_MC.D2_PT_4/IN1  (
    .I(DCORIFGr),
    .O(\NlwInverterSignal_outDATA<2>\$WA6.UIM_MC.D2_PT_4/IN1 )
  );
  X_INV \NlwInverterBlock_outDATA<2>\$WA6.UIM_MC.D2_PT_4/IN2  (
    .I(DCOR0THRESHIGHr),
    .O(\NlwInverterSignal_outDATA<2>\$WA6.UIM_MC.D2_PT_4/IN2 )
  );
  X_INV \NlwInverterBlock_outDATA<2>\$WA6.UIM_MC.D2_PT_4/IN3  (
    .I(DCOR1THRESLOWr),
    .O(\NlwInverterSignal_outDATA<2>\$WA6.UIM_MC.D2_PT_4/IN3 )
  );
  X_INV \NlwInverterBlock_U1/U4/Latch0r<2>_MC.D2_PT_1/IN1  (
    .I(N_PZ_963),
    .O(\NlwInverterSignal_U1/U4/Latch0r<2>_MC.D2_PT_1/IN1 )
  );
  X_INV \NlwInverterBlock_U1/U4/Latch0r<10>_MC.D2_PT_1/IN1  (
    .I(N_PZ_963),
    .O(\NlwInverterSignal_U1/U4/Latch0r<10>_MC.D2_PT_1/IN1 )
  );
  X_INV \NlwInverterBlock_U1/U4/Latch1r<2>_MC.D2_PT_1/IN1  (
    .I(N_PZ_962),
    .O(\NlwInverterSignal_U1/U4/Latch1r<2>_MC.D2_PT_1/IN1 )
  );
  X_INV \NlwInverterBlock_U1/U4/Latch1r<10>_MC.D2_PT_1/IN1  (
    .I(N_PZ_962),
    .O(\NlwInverterSignal_U1/U4/Latch1r<10>_MC.D2_PT_1/IN1 )
  );
  X_INV \NlwInverterBlock_outDATA<3>\$WA3.UIM_MC.D2_PT_1/IN0  (
    .I(NET2528),
    .O(\NlwInverterSignal_outDATA<3>\$WA3.UIM_MC.D2_PT_1/IN0 )
  );
  X_INV \NlwInverterBlock_outDATA<3>\$WA5.UIM_MC.D2_PT_1/IN0  (
    .I(DCOR0CNTLOWr),
    .O(\NlwInverterSignal_outDATA<3>\$WA5.UIM_MC.D2_PT_1/IN0 )
  );
  X_INV \NlwInverterBlock_outDATA<3>\$WA5.UIM_MC.D2_PT_2/IN0  (
    .I(DCOR0CNTLOWr),
    .O(\NlwInverterSignal_outDATA<3>\$WA5.UIM_MC.D2_PT_2/IN0 )
  );
  X_INV \NlwInverterBlock_outDATA<3>\$WA5.UIM_MC.D2_PT_2/IN1  (
    .I(DCOR1CNTLOWr),
    .O(\NlwInverterSignal_outDATA<3>\$WA5.UIM_MC.D2_PT_2/IN1 )
  );
  X_INV \NlwInverterBlock_outDATA<3>\$WA5.UIM_MC.D2_PT_3/IN0  (
    .I(DCOR0CNTLOWr),
    .O(\NlwInverterSignal_outDATA<3>\$WA5.UIM_MC.D2_PT_3/IN0 )
  );
  X_INV \NlwInverterBlock_outDATA<3>\$WA5.UIM_MC.D2_PT_3/IN1  (
    .I(DCOR1CNTLOWr),
    .O(\NlwInverterSignal_outDATA<3>\$WA5.UIM_MC.D2_PT_3/IN1 )
  );
  X_INV \NlwInverterBlock_outDATA<3>\$WA5.UIM_MC.D2_PT_3/IN2  (
    .I(DCOR0CNTHIGHr),
    .O(\NlwInverterSignal_outDATA<3>\$WA5.UIM_MC.D2_PT_3/IN2 )
  );
  X_INV \NlwInverterBlock_U1/U3/holdingreg0<3>_MC.D2_PT_1/IN1  (
    .I(\AS_II/UIM ),
    .O(\NlwInverterSignal_U1/U3/holdingreg0<3>_MC.D2_PT_1/IN1 )
  );
  X_INV \NlwInverterBlock_U1/U3/holdingreg1<3>_MC.D2_PT_1/IN1  (
    .I(\AS_II/UIM ),
    .O(\NlwInverterSignal_U1/U3/holdingreg1<3>_MC.D2_PT_1/IN1 )
  );
  X_INV \NlwInverterBlock_U1/U3/holdingreg0<11>_MC.D2_PT_1/IN1  (
    .I(\AS_II/UIM ),
    .O(\NlwInverterSignal_U1/U3/holdingreg0<11>_MC.D2_PT_1/IN1 )
  );
  X_INV \NlwInverterBlock_U1/U3/holdingreg1<11>_MC.D2_PT_1/IN1  (
    .I(\AS_II/UIM ),
    .O(\NlwInverterSignal_U1/U3/holdingreg1<11>_MC.D2_PT_1/IN1 )
  );
  X_INV \NlwInverterBlock_outDATA<3>\$WA6.UIM_MC.D2_PT_1/IN1  (
    .I(DCOR0THRESLOWr),
    .O(\NlwInverterSignal_outDATA<3>\$WA6.UIM_MC.D2_PT_1/IN1 )
  );
  X_INV \NlwInverterBlock_outDATA<3>\$WA6.UIM_MC.D2_PT_2/IN0  (
    .I(DCOR0THRESLOWr),
    .O(\NlwInverterSignal_outDATA<3>\$WA6.UIM_MC.D2_PT_2/IN0 )
  );
  X_INV \NlwInverterBlock_outDATA<3>\$WA6.UIM_MC.D2_PT_2/IN1  (
    .I(DCORIFGr),
    .O(\NlwInverterSignal_outDATA<3>\$WA6.UIM_MC.D2_PT_2/IN1 )
  );
  X_INV \NlwInverterBlock_outDATA<3>\$WA6.UIM_MC.D2_PT_3/IN0  (
    .I(DCOR0THRESLOWr),
    .O(\NlwInverterSignal_outDATA<3>\$WA6.UIM_MC.D2_PT_3/IN0 )
  );
  X_INV \NlwInverterBlock_outDATA<3>\$WA6.UIM_MC.D2_PT_3/IN1  (
    .I(DCORIFGr),
    .O(\NlwInverterSignal_outDATA<3>\$WA6.UIM_MC.D2_PT_3/IN1 )
  );
  X_INV \NlwInverterBlock_outDATA<3>\$WA6.UIM_MC.D2_PT_3/IN2  (
    .I(DCOR0THRESHIGHr),
    .O(\NlwInverterSignal_outDATA<3>\$WA6.UIM_MC.D2_PT_3/IN2 )
  );
  X_INV \NlwInverterBlock_outDATA<3>\$WA6.UIM_MC.D2_PT_4/IN0  (
    .I(DCOR0THRESLOWr),
    .O(\NlwInverterSignal_outDATA<3>\$WA6.UIM_MC.D2_PT_4/IN0 )
  );
  X_INV \NlwInverterBlock_outDATA<3>\$WA6.UIM_MC.D2_PT_4/IN1  (
    .I(DCORIFGr),
    .O(\NlwInverterSignal_outDATA<3>\$WA6.UIM_MC.D2_PT_4/IN1 )
  );
  X_INV \NlwInverterBlock_outDATA<3>\$WA6.UIM_MC.D2_PT_4/IN2  (
    .I(DCOR0THRESHIGHr),
    .O(\NlwInverterSignal_outDATA<3>\$WA6.UIM_MC.D2_PT_4/IN2 )
  );
  X_INV \NlwInverterBlock_outDATA<3>\$WA6.UIM_MC.D2_PT_4/IN3  (
    .I(DCOR1THRESLOWr),
    .O(\NlwInverterSignal_outDATA<3>\$WA6.UIM_MC.D2_PT_4/IN3 )
  );
  X_INV \NlwInverterBlock_U1/U4/Latch0r<3>_MC.D2_PT_1/IN1  (
    .I(N_PZ_963),
    .O(\NlwInverterSignal_U1/U4/Latch0r<3>_MC.D2_PT_1/IN1 )
  );
  X_INV \NlwInverterBlock_U1/U4/Latch0r<11>_MC.D2_PT_1/IN1  (
    .I(N_PZ_963),
    .O(\NlwInverterSignal_U1/U4/Latch0r<11>_MC.D2_PT_1/IN1 )
  );
  X_INV \NlwInverterBlock_U1/U4/Latch1r<3>_MC.D2_PT_1/IN1  (
    .I(N_PZ_962),
    .O(\NlwInverterSignal_U1/U4/Latch1r<3>_MC.D2_PT_1/IN1 )
  );
  X_INV \NlwInverterBlock_U1/U4/Latch1r<11>_MC.D2_PT_1/IN1  (
    .I(N_PZ_962),
    .O(\NlwInverterSignal_U1/U4/Latch1r<11>_MC.D2_PT_1/IN1 )
  );
  X_INV \NlwInverterBlock_outDATA<6>\$WA3.UIM_MC.D2_PT_1/IN0  (
    .I(NET2528),
    .O(\NlwInverterSignal_outDATA<6>\$WA3.UIM_MC.D2_PT_1/IN0 )
  );
  X_INV \NlwInverterBlock_outDATA<6>\$WA5.UIM_MC.D2_PT_1/IN0  (
    .I(DCOR0CNTLOWr),
    .O(\NlwInverterSignal_outDATA<6>\$WA5.UIM_MC.D2_PT_1/IN0 )
  );
  X_INV \NlwInverterBlock_outDATA<6>\$WA5.UIM_MC.D2_PT_2/IN0  (
    .I(DCOR0CNTLOWr),
    .O(\NlwInverterSignal_outDATA<6>\$WA5.UIM_MC.D2_PT_2/IN0 )
  );
  X_INV \NlwInverterBlock_outDATA<6>\$WA5.UIM_MC.D2_PT_2/IN1  (
    .I(DCOR1CNTLOWr),
    .O(\NlwInverterSignal_outDATA<6>\$WA5.UIM_MC.D2_PT_2/IN1 )
  );
  X_INV \NlwInverterBlock_outDATA<6>\$WA5.UIM_MC.D2_PT_3/IN0  (
    .I(DCOR0CNTLOWr),
    .O(\NlwInverterSignal_outDATA<6>\$WA5.UIM_MC.D2_PT_3/IN0 )
  );
  X_INV \NlwInverterBlock_outDATA<6>\$WA5.UIM_MC.D2_PT_3/IN1  (
    .I(DCOR1CNTLOWr),
    .O(\NlwInverterSignal_outDATA<6>\$WA5.UIM_MC.D2_PT_3/IN1 )
  );
  X_INV \NlwInverterBlock_outDATA<6>\$WA5.UIM_MC.D2_PT_3/IN2  (
    .I(DCOR0CNTHIGHr),
    .O(\NlwInverterSignal_outDATA<6>\$WA5.UIM_MC.D2_PT_3/IN2 )
  );
  X_INV \NlwInverterBlock_U1/U3/holdingreg0<6>_MC.D2_PT_1/IN1  (
    .I(\AS_II/UIM ),
    .O(\NlwInverterSignal_U1/U3/holdingreg0<6>_MC.D2_PT_1/IN1 )
  );
  X_INV \NlwInverterBlock_U1/U3/holdingreg1<6>_MC.D2_PT_1/IN1  (
    .I(\AS_II/UIM ),
    .O(\NlwInverterSignal_U1/U3/holdingreg1<6>_MC.D2_PT_1/IN1 )
  );
  X_INV \NlwInverterBlock_U1/U3/holdingreg0<14>_MC.D2_PT_1/IN1  (
    .I(\AS_II/UIM ),
    .O(\NlwInverterSignal_U1/U3/holdingreg0<14>_MC.D2_PT_1/IN1 )
  );
  X_INV \NlwInverterBlock_U1/Channel0<14>_MC.D2_PT_0/IN0  (
    .I(N_PZ_928),
    .O(\NlwInverterSignal_U1/Channel0<14>_MC.D2_PT_0/IN0 )
  );
  X_INV \NlwInverterBlock_U1/Channel0<14>_MC.D2_PT_1/IN1  (
    .I(\U1/Channel0 [13]),
    .O(\NlwInverterSignal_U1/Channel0<14>_MC.D2_PT_1/IN1 )
  );
  X_INV \NlwInverterBlock_U1/Channel0<14>_MC.D2_PT_1/IN2  (
    .I(\U1/Channel0 [10]),
    .O(\NlwInverterSignal_U1/Channel0<14>_MC.D2_PT_1/IN2 )
  );
  X_INV \NlwInverterBlock_U1/Channel0<14>_MC.D2_PT_1/IN3  (
    .I(\U1/Channel0 [9]),
    .O(\NlwInverterSignal_U1/Channel0<14>_MC.D2_PT_1/IN3 )
  );
  X_INV \NlwInverterBlock_U1/Channel0<14>_MC.D2_PT_1/IN5  (
    .I(\U1/Channel0 [11]),
    .O(\NlwInverterSignal_U1/Channel0<14>_MC.D2_PT_1/IN5 )
  );
  X_INV \NlwInverterBlock_U1/Channel0<14>_MC.D2_PT_1/IN6  (
    .I(\U1/Channel0 [12]),
    .O(\NlwInverterSignal_U1/Channel0<14>_MC.D2_PT_1/IN6 )
  );
  X_INV \NlwInverterBlock_U1/Channel0<14>_MC.D2_PT_2/IN4  (
    .I(\U1/U2/location_Maddsub__n0000__n0075 [0]),
    .O(\NlwInverterSignal_U1/Channel0<14>_MC.D2_PT_2/IN4 )
  );
  X_INV \NlwInverterBlock_U1/U3/holdingreg1<14>_MC.D2_PT_1/IN1  (
    .I(\AS_II/UIM ),
    .O(\NlwInverterSignal_U1/U3/holdingreg1<14>_MC.D2_PT_1/IN1 )
  );
  X_INV \NlwInverterBlock_U1/Channel1<14>_MC.D2_PT_0/IN0  (
    .I(N_PZ_929),
    .O(\NlwInverterSignal_U1/Channel1<14>_MC.D2_PT_0/IN0 )
  );
  X_INV \NlwInverterBlock_U1/Channel1<14>_MC.D2_PT_1/IN1  (
    .I(\U1/Zero1 ),
    .O(\NlwInverterSignal_U1/Channel1<14>_MC.D2_PT_1/IN1 )
  );
  X_INV \NlwInverterBlock_U1/Channel1<14>_MC.D2_PT_1/IN3  (
    .I(\U1/U6/CurrState_Sreg0_FFD2 ),
    .O(\NlwInverterSignal_U1/Channel1<14>_MC.D2_PT_1/IN3 )
  );
  X_INV \NlwInverterBlock_U1/Channel1<14>_MC.D2_PT_1/IN8  (
    .I(\U1/U5/location_Maddsub__n0000__n0075 [0]),
    .O(\NlwInverterSignal_U1/Channel1<14>_MC.D2_PT_1/IN8 )
  );
  X_INV \NlwInverterBlock_U1/Channel1<14>_MC.D2_PT_2/IN1  (
    .I(\U1/Zero1 ),
    .O(\NlwInverterSignal_U1/Channel1<14>_MC.D2_PT_2/IN1 )
  );
  X_INV \NlwInverterBlock_U1/Channel1<14>_MC.D2_PT_2/IN3  (
    .I(\U1/U6/CurrState_Sreg0_FFD2 ),
    .O(\NlwInverterSignal_U1/Channel1<14>_MC.D2_PT_2/IN3 )
  );
  X_INV \NlwInverterBlock_U1/Channel1<14>_MC.D2_PT_2/IN4  (
    .I(N_PZ_921),
    .O(\NlwInverterSignal_U1/Channel1<14>_MC.D2_PT_2/IN4 )
  );
  X_INV \NlwInverterBlock_U1/Channel1<14>_MC.D2_PT_2/IN6  (
    .I(\U1/Channel1 [13]),
    .O(\NlwInverterSignal_U1/Channel1<14>_MC.D2_PT_2/IN6 )
  );
  X_INV \NlwInverterBlock_U1/Channel1<14>_MC.D2_PT_2/IN7  (
    .I(\U1/Channel1 [10]),
    .O(\NlwInverterSignal_U1/Channel1<14>_MC.D2_PT_2/IN7 )
  );
  X_INV \NlwInverterBlock_U1/Channel1<14>_MC.D2_PT_2/IN8  (
    .I(\U1/Channel1 [9]),
    .O(\NlwInverterSignal_U1/Channel1<14>_MC.D2_PT_2/IN8 )
  );
  X_INV \NlwInverterBlock_U1/Channel1<14>_MC.D2_PT_2/IN10  (
    .I(\U1/Channel1 [11]),
    .O(\NlwInverterSignal_U1/Channel1<14>_MC.D2_PT_2/IN10 )
  );
  X_INV \NlwInverterBlock_U1/Channel1<14>_MC.D2_PT_2/IN11  (
    .I(\U1/Channel1 [12]),
    .O(\NlwInverterSignal_U1/Channel1<14>_MC.D2_PT_2/IN11 )
  );
  X_INV \NlwInverterBlock_outDATA<6>\$WA6.UIM_MC.D2_PT_1/IN0  (
    .I(DCOR0THRESLOWr),
    .O(\NlwInverterSignal_outDATA<6>\$WA6.UIM_MC.D2_PT_1/IN0 )
  );
  X_INV \NlwInverterBlock_outDATA<6>\$WA6.UIM_MC.D2_PT_2/IN0  (
    .I(DCOR0THRESLOWr),
    .O(\NlwInverterSignal_outDATA<6>\$WA6.UIM_MC.D2_PT_2/IN0 )
  );
  X_INV \NlwInverterBlock_outDATA<6>\$WA6.UIM_MC.D2_PT_2/IN1  (
    .I(DCORIFGr),
    .O(\NlwInverterSignal_outDATA<6>\$WA6.UIM_MC.D2_PT_2/IN1 )
  );
  X_INV \NlwInverterBlock_outDATA<6>\$WA6.UIM_MC.D2_PT_3/IN0  (
    .I(DCOR0THRESLOWr),
    .O(\NlwInverterSignal_outDATA<6>\$WA6.UIM_MC.D2_PT_3/IN0 )
  );
  X_INV \NlwInverterBlock_outDATA<6>\$WA6.UIM_MC.D2_PT_3/IN1  (
    .I(DCORIFGr),
    .O(\NlwInverterSignal_outDATA<6>\$WA6.UIM_MC.D2_PT_3/IN1 )
  );
  X_INV \NlwInverterBlock_outDATA<6>\$WA6.UIM_MC.D2_PT_3/IN2  (
    .I(DCOR0THRESHIGHr),
    .O(\NlwInverterSignal_outDATA<6>\$WA6.UIM_MC.D2_PT_3/IN2 )
  );
  X_INV \NlwInverterBlock_outDATA<6>\$WA6.UIM_MC.D2_PT_4/IN0  (
    .I(DCOR0THRESLOWr),
    .O(\NlwInverterSignal_outDATA<6>\$WA6.UIM_MC.D2_PT_4/IN0 )
  );
  X_INV \NlwInverterBlock_outDATA<6>\$WA6.UIM_MC.D2_PT_4/IN1  (
    .I(DCORIFGr),
    .O(\NlwInverterSignal_outDATA<6>\$WA6.UIM_MC.D2_PT_4/IN1 )
  );
  X_INV \NlwInverterBlock_outDATA<6>\$WA6.UIM_MC.D2_PT_4/IN2  (
    .I(DCOR0THRESHIGHr),
    .O(\NlwInverterSignal_outDATA<6>\$WA6.UIM_MC.D2_PT_4/IN2 )
  );
  X_INV \NlwInverterBlock_outDATA<6>\$WA6.UIM_MC.D2_PT_4/IN3  (
    .I(DCOR1THRESLOWr),
    .O(\NlwInverterSignal_outDATA<6>\$WA6.UIM_MC.D2_PT_4/IN3 )
  );
  X_INV \NlwInverterBlock_U1/U4/Latch0r<6>_MC.D2_PT_1/IN1  (
    .I(N_PZ_963),
    .O(\NlwInverterSignal_U1/U4/Latch0r<6>_MC.D2_PT_1/IN1 )
  );
  X_INV \NlwInverterBlock_U1/U4/Latch0r<14>_MC.D2_PT_1/IN1  (
    .I(N_PZ_963),
    .O(\NlwInverterSignal_U1/U4/Latch0r<14>_MC.D2_PT_1/IN1 )
  );
  X_INV \NlwInverterBlock_U1/U4/Latch1r<6>_MC.D2_PT_1/IN1  (
    .I(N_PZ_962),
    .O(\NlwInverterSignal_U1/U4/Latch1r<6>_MC.D2_PT_1/IN1 )
  );
  X_INV \NlwInverterBlock_U1/U4/Latch1r<14>_MC.D2_PT_1/IN1  (
    .I(N_PZ_962),
    .O(\NlwInverterSignal_U1/U4/Latch1r<14>_MC.D2_PT_1/IN1 )
  );
  X_INV \NlwInverterBlock_outDATA<7>\$WA3.UIM_MC.D2_PT_1/IN0  (
    .I(NET2528),
    .O(\NlwInverterSignal_outDATA<7>\$WA3.UIM_MC.D2_PT_1/IN0 )
  );
  X_INV \NlwInverterBlock_outDATA<7>\$WA6.UIM_MC.D2_PT_1/IN0  (
    .I(DCOR0THRESLOWr),
    .O(\NlwInverterSignal_outDATA<7>\$WA6.UIM_MC.D2_PT_1/IN0 )
  );
  X_INV \NlwInverterBlock_outDATA<7>\$WA6.UIM_MC.D2_PT_2/IN0  (
    .I(DCOR0THRESLOWr),
    .O(\NlwInverterSignal_outDATA<7>\$WA6.UIM_MC.D2_PT_2/IN0 )
  );
  X_INV \NlwInverterBlock_outDATA<7>\$WA6.UIM_MC.D2_PT_2/IN1  (
    .I(DCOR0THRESHIGHr),
    .O(\NlwInverterSignal_outDATA<7>\$WA6.UIM_MC.D2_PT_2/IN1 )
  );
  X_INV \NlwInverterBlock_outDATA<7>\$WA6.UIM_MC.D2_PT_3/IN0  (
    .I(DCOR0THRESLOWr),
    .O(\NlwInverterSignal_outDATA<7>\$WA6.UIM_MC.D2_PT_3/IN0 )
  );
  X_INV \NlwInverterBlock_outDATA<7>\$WA6.UIM_MC.D2_PT_3/IN1  (
    .I(DCOR0THRESHIGHr),
    .O(\NlwInverterSignal_outDATA<7>\$WA6.UIM_MC.D2_PT_3/IN1 )
  );
  X_INV \NlwInverterBlock_outDATA<7>\$WA6.UIM_MC.D2_PT_3/IN2  (
    .I(DCOR1THRESLOWr),
    .O(\NlwInverterSignal_outDATA<7>\$WA6.UIM_MC.D2_PT_3/IN2 )
  );
  X_INV \NlwInverterBlock_U1/U4/Latch0r<7>_MC.D2_PT_1/IN1  (
    .I(N_PZ_963),
    .O(\NlwInverterSignal_U1/U4/Latch0r<7>_MC.D2_PT_1/IN1 )
  );
  X_INV \NlwInverterBlock_U1/U4/Latch0r<15>_MC.D2_PT_1/IN1  (
    .I(N_PZ_963),
    .O(\NlwInverterSignal_U1/U4/Latch0r<15>_MC.D2_PT_1/IN1 )
  );
  X_INV \NlwInverterBlock_U1/Channel0<15>_MC.D2_PT_0/IN0  (
    .I(N_PZ_928),
    .O(\NlwInverterSignal_U1/Channel0<15>_MC.D2_PT_0/IN0 )
  );
  X_INV \NlwInverterBlock_U1/Channel0<15>_MC.D2_PT_1/IN1  (
    .I(\U1/Channel0 [13]),
    .O(\NlwInverterSignal_U1/Channel0<15>_MC.D2_PT_1/IN1 )
  );
  X_INV \NlwInverterBlock_U1/Channel0<15>_MC.D2_PT_1/IN2  (
    .I(\U1/Channel0 [10]),
    .O(\NlwInverterSignal_U1/Channel0<15>_MC.D2_PT_1/IN2 )
  );
  X_INV \NlwInverterBlock_U1/Channel0<15>_MC.D2_PT_1/IN3  (
    .I(\U1/Channel0 [9]),
    .O(\NlwInverterSignal_U1/Channel0<15>_MC.D2_PT_1/IN3 )
  );
  X_INV \NlwInverterBlock_U1/Channel0<15>_MC.D2_PT_1/IN5  (
    .I(\U1/Channel0 [11]),
    .O(\NlwInverterSignal_U1/Channel0<15>_MC.D2_PT_1/IN5 )
  );
  X_INV \NlwInverterBlock_U1/Channel0<15>_MC.D2_PT_1/IN6  (
    .I(\U1/Channel0 [12]),
    .O(\NlwInverterSignal_U1/Channel0<15>_MC.D2_PT_1/IN6 )
  );
  X_INV \NlwInverterBlock_U1/Channel0<15>_MC.D2_PT_1/IN7  (
    .I(\U1/Channel0 [14]),
    .O(\NlwInverterSignal_U1/Channel0<15>_MC.D2_PT_1/IN7 )
  );
  X_INV \NlwInverterBlock_U1/Channel0<15>_MC.D2_PT_2/IN4  (
    .I(\U1/U2/location_Maddsub__n0000__n0075 [0]),
    .O(\NlwInverterSignal_U1/Channel0<15>_MC.D2_PT_2/IN4 )
  );
  X_INV \NlwInverterBlock_U1/U4/Latch1r<7>_MC.D2_PT_1/IN1  (
    .I(N_PZ_962),
    .O(\NlwInverterSignal_U1/U4/Latch1r<7>_MC.D2_PT_1/IN1 )
  );
  X_INV \NlwInverterBlock_U1/U4/Latch1r<15>_MC.D2_PT_1/IN1  (
    .I(N_PZ_962),
    .O(\NlwInverterSignal_U1/U4/Latch1r<15>_MC.D2_PT_1/IN1 )
  );
  X_INV \NlwInverterBlock_U1/Channel1<15>_MC.D2_PT_0/IN0  (
    .I(N_PZ_929),
    .O(\NlwInverterSignal_U1/Channel1<15>_MC.D2_PT_0/IN0 )
  );
  X_INV \NlwInverterBlock_U1/Channel1<15>_MC.D2_PT_1/IN1  (
    .I(\U1/Zero1 ),
    .O(\NlwInverterSignal_U1/Channel1<15>_MC.D2_PT_1/IN1 )
  );
  X_INV \NlwInverterBlock_U1/Channel1<15>_MC.D2_PT_1/IN3  (
    .I(\U1/U6/CurrState_Sreg0_FFD2 ),
    .O(\NlwInverterSignal_U1/Channel1<15>_MC.D2_PT_1/IN3 )
  );
  X_INV \NlwInverterBlock_U1/Channel1<15>_MC.D2_PT_1/IN8  (
    .I(\U1/U5/location_Maddsub__n0000__n0075 [0]),
    .O(\NlwInverterSignal_U1/Channel1<15>_MC.D2_PT_1/IN8 )
  );
  X_INV \NlwInverterBlock_U1/Channel1<15>_MC.D2_PT_2/IN1  (
    .I(\U1/Zero1 ),
    .O(\NlwInverterSignal_U1/Channel1<15>_MC.D2_PT_2/IN1 )
  );
  X_INV \NlwInverterBlock_U1/Channel1<15>_MC.D2_PT_2/IN3  (
    .I(\U1/U6/CurrState_Sreg0_FFD2 ),
    .O(\NlwInverterSignal_U1/Channel1<15>_MC.D2_PT_2/IN3 )
  );
  X_INV \NlwInverterBlock_U1/Channel1<15>_MC.D2_PT_2/IN4  (
    .I(N_PZ_921),
    .O(\NlwInverterSignal_U1/Channel1<15>_MC.D2_PT_2/IN4 )
  );
  X_INV \NlwInverterBlock_U1/Channel1<15>_MC.D2_PT_2/IN6  (
    .I(\U1/Channel1 [13]),
    .O(\NlwInverterSignal_U1/Channel1<15>_MC.D2_PT_2/IN6 )
  );
  X_INV \NlwInverterBlock_U1/Channel1<15>_MC.D2_PT_2/IN7  (
    .I(\U1/Channel1 [10]),
    .O(\NlwInverterSignal_U1/Channel1<15>_MC.D2_PT_2/IN7 )
  );
  X_INV \NlwInverterBlock_U1/Channel1<15>_MC.D2_PT_2/IN8  (
    .I(\U1/Channel1 [9]),
    .O(\NlwInverterSignal_U1/Channel1<15>_MC.D2_PT_2/IN8 )
  );
  X_INV \NlwInverterBlock_U1/Channel1<15>_MC.D2_PT_2/IN10  (
    .I(\U1/Channel1 [11]),
    .O(\NlwInverterSignal_U1/Channel1<15>_MC.D2_PT_2/IN10 )
  );
  X_INV \NlwInverterBlock_U1/Channel1<15>_MC.D2_PT_2/IN11  (
    .I(\U1/Channel1 [12]),
    .O(\NlwInverterSignal_U1/Channel1<15>_MC.D2_PT_2/IN11 )
  );
  X_INV \NlwInverterBlock_U1/Channel1<15>_MC.D2_PT_2/IN12  (
    .I(\U1/Channel1 [14]),
    .O(\NlwInverterSignal_U1/Channel1<15>_MC.D2_PT_2/IN12 )
  );
  X_INV \NlwInverterBlock_outDATA<7>\$WA5.UIM_MC.D2_PT_1/IN0  (
    .I(DCOR0CNTLOWr),
    .O(\NlwInverterSignal_outDATA<7>\$WA5.UIM_MC.D2_PT_1/IN0 )
  );
  X_INV \NlwInverterBlock_outDATA<7>\$WA5.UIM_MC.D2_PT_2/IN0  (
    .I(DCOR0CNTLOWr),
    .O(\NlwInverterSignal_outDATA<7>\$WA5.UIM_MC.D2_PT_2/IN0 )
  );
  X_INV \NlwInverterBlock_outDATA<7>\$WA5.UIM_MC.D2_PT_2/IN1  (
    .I(DCOR1CNTLOWr),
    .O(\NlwInverterSignal_outDATA<7>\$WA5.UIM_MC.D2_PT_2/IN1 )
  );
  X_INV \NlwInverterBlock_outDATA<7>\$WA5.UIM_MC.D2_PT_3/IN0  (
    .I(DCOR0CNTLOWr),
    .O(\NlwInverterSignal_outDATA<7>\$WA5.UIM_MC.D2_PT_3/IN0 )
  );
  X_INV \NlwInverterBlock_outDATA<7>\$WA5.UIM_MC.D2_PT_3/IN1  (
    .I(DCOR1CNTLOWr),
    .O(\NlwInverterSignal_outDATA<7>\$WA5.UIM_MC.D2_PT_3/IN1 )
  );
  X_INV \NlwInverterBlock_outDATA<7>\$WA5.UIM_MC.D2_PT_3/IN2  (
    .I(DCOR0CNTHIGHr),
    .O(\NlwInverterSignal_outDATA<7>\$WA5.UIM_MC.D2_PT_3/IN2 )
  );
  X_INV \NlwInverterBlock_U1/U3/holdingreg0<7>_MC.D2_PT_1/IN1  (
    .I(\AS_II/UIM ),
    .O(\NlwInverterSignal_U1/U3/holdingreg0<7>_MC.D2_PT_1/IN1 )
  );
  X_INV \NlwInverterBlock_U1/U3/holdingreg1<7>_MC.D2_PT_1/IN1  (
    .I(\AS_II/UIM ),
    .O(\NlwInverterSignal_U1/U3/holdingreg1<7>_MC.D2_PT_1/IN1 )
  );
  X_INV \NlwInverterBlock_U1/U3/holdingreg0<15>_MC.D2_PT_1/IN1  (
    .I(\AS_II/UIM ),
    .O(\NlwInverterSignal_U1/U3/holdingreg0<15>_MC.D2_PT_1/IN1 )
  );
  X_INV \NlwInverterBlock_U1/U3/holdingreg1<15>_MC.D2_PT_1/IN1  (
    .I(\AS_II/UIM ),
    .O(\NlwInverterSignal_U1/U3/holdingreg1<15>_MC.D2_PT_1/IN1 )
  );
  X_INV \NlwInverterBlock_outDATA<0>\$WA3.UIM_MC.D2_PT_1/IN0  (
    .I(NET2528),
    .O(\NlwInverterSignal_outDATA<0>\$WA3.UIM_MC.D2_PT_1/IN0 )
  );
  X_INV \NlwInverterBlock_outDATA<0>\$WA6.UIM_MC.D2_PT_1/IN0  (
    .I(DCOR0THRESLOWr),
    .O(\NlwInverterSignal_outDATA<0>\$WA6.UIM_MC.D2_PT_1/IN0 )
  );
  X_INV \NlwInverterBlock_outDATA<0>\$WA6.UIM_MC.D2_PT_2/IN0  (
    .I(DCOR0THRESLOWr),
    .O(\NlwInverterSignal_outDATA<0>\$WA6.UIM_MC.D2_PT_2/IN0 )
  );
  X_INV \NlwInverterBlock_outDATA<0>\$WA6.UIM_MC.D2_PT_2/IN1  (
    .I(DCOR0THRESHIGHr),
    .O(\NlwInverterSignal_outDATA<0>\$WA6.UIM_MC.D2_PT_2/IN1 )
  );
  X_INV \NlwInverterBlock_outDATA<0>\$WA6.UIM_MC.D2_PT_3/IN0  (
    .I(DCOR0THRESLOWr),
    .O(\NlwInverterSignal_outDATA<0>\$WA6.UIM_MC.D2_PT_3/IN0 )
  );
  X_INV \NlwInverterBlock_outDATA<0>\$WA6.UIM_MC.D2_PT_3/IN1  (
    .I(DCOR0THRESHIGHr),
    .O(\NlwInverterSignal_outDATA<0>\$WA6.UIM_MC.D2_PT_3/IN1 )
  );
  X_INV \NlwInverterBlock_outDATA<0>\$WA6.UIM_MC.D2_PT_3/IN2  (
    .I(DCOR1THRESLOWr),
    .O(\NlwInverterSignal_outDATA<0>\$WA6.UIM_MC.D2_PT_3/IN2 )
  );
  X_INV \NlwInverterBlock_U1/U4/Latch0r<0>_MC.D2_PT_1/IN1  (
    .I(N_PZ_963),
    .O(\NlwInverterSignal_U1/U4/Latch0r<0>_MC.D2_PT_1/IN1 )
  );
  X_INV \NlwInverterBlock_U1/U4/Latch0r<8>_MC.D2_PT_1/IN1  (
    .I(N_PZ_963),
    .O(\NlwInverterSignal_U1/U4/Latch0r<8>_MC.D2_PT_1/IN1 )
  );
  X_INV \NlwInverterBlock_U1/U4/Latch1r<0>_MC.D2_PT_1/IN1  (
    .I(N_PZ_962),
    .O(\NlwInverterSignal_U1/U4/Latch1r<0>_MC.D2_PT_1/IN1 )
  );
  X_INV \NlwInverterBlock_U1/U4/Latch1r<8>_MC.D2_PT_1/IN1  (
    .I(N_PZ_962),
    .O(\NlwInverterSignal_U1/U4/Latch1r<8>_MC.D2_PT_1/IN1 )
  );
  X_INV \NlwInverterBlock_outDATA<0>\$WA5.UIM_MC.D2_PT_1/IN0  (
    .I(DCOR0CNTLOWr),
    .O(\NlwInverterSignal_outDATA<0>\$WA5.UIM_MC.D2_PT_1/IN0 )
  );
  X_INV \NlwInverterBlock_outDATA<0>\$WA5.UIM_MC.D2_PT_2/IN0  (
    .I(DCOR0CNTLOWr),
    .O(\NlwInverterSignal_outDATA<0>\$WA5.UIM_MC.D2_PT_2/IN0 )
  );
  X_INV \NlwInverterBlock_outDATA<0>\$WA5.UIM_MC.D2_PT_2/IN1  (
    .I(DCOR1CNTLOWr),
    .O(\NlwInverterSignal_outDATA<0>\$WA5.UIM_MC.D2_PT_2/IN1 )
  );
  X_INV \NlwInverterBlock_outDATA<0>\$WA5.UIM_MC.D2_PT_3/IN0  (
    .I(DCOR0CNTLOWr),
    .O(\NlwInverterSignal_outDATA<0>\$WA5.UIM_MC.D2_PT_3/IN0 )
  );
  X_INV \NlwInverterBlock_outDATA<0>\$WA5.UIM_MC.D2_PT_3/IN1  (
    .I(DCOR1CNTLOWr),
    .O(\NlwInverterSignal_outDATA<0>\$WA5.UIM_MC.D2_PT_3/IN1 )
  );
  X_INV \NlwInverterBlock_outDATA<0>\$WA5.UIM_MC.D2_PT_3/IN2  (
    .I(DCOR0CNTHIGHr),
    .O(\NlwInverterSignal_outDATA<0>\$WA5.UIM_MC.D2_PT_3/IN2 )
  );
  X_INV \NlwInverterBlock_U1/U3/holdingreg0<0>_MC.D2_PT_1/IN1  (
    .I(\AS_II/UIM ),
    .O(\NlwInverterSignal_U1/U3/holdingreg0<0>_MC.D2_PT_1/IN1 )
  );
  X_INV \NlwInverterBlock_U1/U3/holdingreg1<0>_MC.D2_PT_1/IN1  (
    .I(\AS_II/UIM ),
    .O(\NlwInverterSignal_U1/U3/holdingreg1<0>_MC.D2_PT_1/IN1 )
  );
  X_INV \NlwInverterBlock_U1/U3/holdingreg0<8>_MC.D2_PT_1/IN1  (
    .I(\AS_II/UIM ),
    .O(\NlwInverterSignal_U1/U3/holdingreg0<8>_MC.D2_PT_1/IN1 )
  );
  X_INV \NlwInverterBlock_U1/U3/holdingreg1<8>_MC.D2_PT_1/IN1  (
    .I(\AS_II/UIM ),
    .O(\NlwInverterSignal_U1/U3/holdingreg1<8>_MC.D2_PT_1/IN1 )
  );
  X_INV \NlwInverterBlock_outDATA<1>\$WA3.UIM_MC.D2_PT_0/IN0  (
    .I(DCORENCPWRr),
    .O(\NlwInverterSignal_outDATA<1>\$WA3.UIM_MC.D2_PT_0/IN0 )
  );
  X_INV \NlwInverterBlock_outDATA<1>\$WA3.UIM_MC.D2_PT_2/IN1  (
    .I(NET2528),
    .O(\NlwInverterSignal_outDATA<1>\$WA3.UIM_MC.D2_PT_2/IN1 )
  );
  X_INV \NlwInverterBlock_outDATA<1>\$WA6.UIM_MC.D2_PT_1/IN0  (
    .I(DCOR0THRESLOWr),
    .O(\NlwInverterSignal_outDATA<1>\$WA6.UIM_MC.D2_PT_1/IN0 )
  );
  X_INV \NlwInverterBlock_outDATA<1>\$WA6.UIM_MC.D2_PT_2/IN0  (
    .I(DCOR0THRESLOWr),
    .O(\NlwInverterSignal_outDATA<1>\$WA6.UIM_MC.D2_PT_2/IN0 )
  );
  X_INV \NlwInverterBlock_outDATA<1>\$WA6.UIM_MC.D2_PT_2/IN1  (
    .I(DCOR0THRESHIGHr),
    .O(\NlwInverterSignal_outDATA<1>\$WA6.UIM_MC.D2_PT_2/IN1 )
  );
  X_INV \NlwInverterBlock_outDATA<1>\$WA6.UIM_MC.D2_PT_3/IN0  (
    .I(DCOR0THRESLOWr),
    .O(\NlwInverterSignal_outDATA<1>\$WA6.UIM_MC.D2_PT_3/IN0 )
  );
  X_INV \NlwInverterBlock_outDATA<1>\$WA6.UIM_MC.D2_PT_3/IN1  (
    .I(DCOR0THRESHIGHr),
    .O(\NlwInverterSignal_outDATA<1>\$WA6.UIM_MC.D2_PT_3/IN1 )
  );
  X_INV \NlwInverterBlock_outDATA<1>\$WA6.UIM_MC.D2_PT_3/IN2  (
    .I(DCOR1THRESLOWr),
    .O(\NlwInverterSignal_outDATA<1>\$WA6.UIM_MC.D2_PT_3/IN2 )
  );
  X_INV \NlwInverterBlock_U1/U4/Latch0r<1>_MC.D2_PT_1/IN1  (
    .I(N_PZ_963),
    .O(\NlwInverterSignal_U1/U4/Latch0r<1>_MC.D2_PT_1/IN1 )
  );
  X_INV \NlwInverterBlock_U1/U4/Latch0r<9>_MC.D2_PT_1/IN1  (
    .I(N_PZ_963),
    .O(\NlwInverterSignal_U1/U4/Latch0r<9>_MC.D2_PT_1/IN1 )
  );
  X_INV \NlwInverterBlock_U1/U4/Latch1r<1>_MC.D2_PT_1/IN1  (
    .I(N_PZ_962),
    .O(\NlwInverterSignal_U1/U4/Latch1r<1>_MC.D2_PT_1/IN1 )
  );
  X_INV \NlwInverterBlock_U1/U4/Latch1r<9>_MC.D2_PT_1/IN1  (
    .I(N_PZ_962),
    .O(\NlwInverterSignal_U1/U4/Latch1r<9>_MC.D2_PT_1/IN1 )
  );
  X_INV \NlwInverterBlock_outDATA<1>\$WA5.UIM_MC.D2_PT_1/IN0  (
    .I(DCOR0CNTLOWr),
    .O(\NlwInverterSignal_outDATA<1>\$WA5.UIM_MC.D2_PT_1/IN0 )
  );
  X_INV \NlwInverterBlock_outDATA<1>\$WA5.UIM_MC.D2_PT_2/IN0  (
    .I(DCOR0CNTLOWr),
    .O(\NlwInverterSignal_outDATA<1>\$WA5.UIM_MC.D2_PT_2/IN0 )
  );
  X_INV \NlwInverterBlock_outDATA<1>\$WA5.UIM_MC.D2_PT_2/IN1  (
    .I(DCOR1CNTLOWr),
    .O(\NlwInverterSignal_outDATA<1>\$WA5.UIM_MC.D2_PT_2/IN1 )
  );
  X_INV \NlwInverterBlock_outDATA<1>\$WA5.UIM_MC.D2_PT_3/IN0  (
    .I(DCOR0CNTLOWr),
    .O(\NlwInverterSignal_outDATA<1>\$WA5.UIM_MC.D2_PT_3/IN0 )
  );
  X_INV \NlwInverterBlock_outDATA<1>\$WA5.UIM_MC.D2_PT_3/IN1  (
    .I(DCOR1CNTLOWr),
    .O(\NlwInverterSignal_outDATA<1>\$WA5.UIM_MC.D2_PT_3/IN1 )
  );
  X_INV \NlwInverterBlock_outDATA<1>\$WA5.UIM_MC.D2_PT_3/IN2  (
    .I(DCOR0CNTHIGHr),
    .O(\NlwInverterSignal_outDATA<1>\$WA5.UIM_MC.D2_PT_3/IN2 )
  );
  X_INV \NlwInverterBlock_U1/U3/holdingreg0<1>_MC.D2_PT_1/IN1  (
    .I(\AS_II/UIM ),
    .O(\NlwInverterSignal_U1/U3/holdingreg0<1>_MC.D2_PT_1/IN1 )
  );
  X_INV \NlwInverterBlock_U1/U3/holdingreg1<1>_MC.D2_PT_1/IN1  (
    .I(\AS_II/UIM ),
    .O(\NlwInverterSignal_U1/U3/holdingreg1<1>_MC.D2_PT_1/IN1 )
  );
  X_INV \NlwInverterBlock_U1/U3/holdingreg0<9>_MC.D2_PT_1/IN1  (
    .I(\AS_II/UIM ),
    .O(\NlwInverterSignal_U1/U3/holdingreg0<9>_MC.D2_PT_1/IN1 )
  );
  X_INV \NlwInverterBlock_U1/U3/holdingreg1<9>_MC.D2_PT_1/IN1  (
    .I(\AS_II/UIM ),
    .O(\NlwInverterSignal_U1/U3/holdingreg1<9>_MC.D2_PT_1/IN1 )
  );
  X_INV \NlwInverterBlock_outDATA<4>\$WA3.UIM_MC.D2_PT_1/IN0  (
    .I(NET2528),
    .O(\NlwInverterSignal_outDATA<4>\$WA3.UIM_MC.D2_PT_1/IN0 )
  );
  X_INV \NlwInverterBlock_outDATA<4>\$WA6.UIM_MC.D2_PT_1/IN0  (
    .I(DCOR0THRESLOWr),
    .O(\NlwInverterSignal_outDATA<4>\$WA6.UIM_MC.D2_PT_1/IN0 )
  );
  X_INV \NlwInverterBlock_outDATA<4>\$WA6.UIM_MC.D2_PT_2/IN0  (
    .I(DCOR0THRESLOWr),
    .O(\NlwInverterSignal_outDATA<4>\$WA6.UIM_MC.D2_PT_2/IN0 )
  );
  X_INV \NlwInverterBlock_outDATA<4>\$WA6.UIM_MC.D2_PT_2/IN1  (
    .I(DCOR0THRESHIGHr),
    .O(\NlwInverterSignal_outDATA<4>\$WA6.UIM_MC.D2_PT_2/IN1 )
  );
  X_INV \NlwInverterBlock_outDATA<4>\$WA6.UIM_MC.D2_PT_3/IN0  (
    .I(DCOR0THRESLOWr),
    .O(\NlwInverterSignal_outDATA<4>\$WA6.UIM_MC.D2_PT_3/IN0 )
  );
  X_INV \NlwInverterBlock_outDATA<4>\$WA6.UIM_MC.D2_PT_3/IN1  (
    .I(DCOR0THRESHIGHr),
    .O(\NlwInverterSignal_outDATA<4>\$WA6.UIM_MC.D2_PT_3/IN1 )
  );
  X_INV \NlwInverterBlock_outDATA<4>\$WA6.UIM_MC.D2_PT_3/IN2  (
    .I(DCOR1THRESLOWr),
    .O(\NlwInverterSignal_outDATA<4>\$WA6.UIM_MC.D2_PT_3/IN2 )
  );
  X_INV \NlwInverterBlock_U1/U4/Latch0r<4>_MC.D2_PT_1/IN1  (
    .I(N_PZ_963),
    .O(\NlwInverterSignal_U1/U4/Latch0r<4>_MC.D2_PT_1/IN1 )
  );
  X_INV \NlwInverterBlock_U1/U4/Latch0r<12>_MC.D2_PT_1/IN1  (
    .I(N_PZ_963),
    .O(\NlwInverterSignal_U1/U4/Latch0r<12>_MC.D2_PT_1/IN1 )
  );
  X_INV \NlwInverterBlock_U1/U4/Latch1r<4>_MC.D2_PT_1/IN1  (
    .I(N_PZ_962),
    .O(\NlwInverterSignal_U1/U4/Latch1r<4>_MC.D2_PT_1/IN1 )
  );
  X_INV \NlwInverterBlock_U1/U4/Latch1r<12>_MC.D2_PT_1/IN1  (
    .I(N_PZ_962),
    .O(\NlwInverterSignal_U1/U4/Latch1r<12>_MC.D2_PT_1/IN1 )
  );
  X_INV \NlwInverterBlock_outDATA<4>\$WA5.UIM_MC.D2_PT_1/IN0  (
    .I(DCOR0CNTLOWr),
    .O(\NlwInverterSignal_outDATA<4>\$WA5.UIM_MC.D2_PT_1/IN0 )
  );
  X_INV \NlwInverterBlock_outDATA<4>\$WA5.UIM_MC.D2_PT_2/IN0  (
    .I(DCOR0CNTLOWr),
    .O(\NlwInverterSignal_outDATA<4>\$WA5.UIM_MC.D2_PT_2/IN0 )
  );
  X_INV \NlwInverterBlock_outDATA<4>\$WA5.UIM_MC.D2_PT_2/IN1  (
    .I(DCOR1CNTLOWr),
    .O(\NlwInverterSignal_outDATA<4>\$WA5.UIM_MC.D2_PT_2/IN1 )
  );
  X_INV \NlwInverterBlock_outDATA<4>\$WA5.UIM_MC.D2_PT_3/IN0  (
    .I(DCOR0CNTLOWr),
    .O(\NlwInverterSignal_outDATA<4>\$WA5.UIM_MC.D2_PT_3/IN0 )
  );
  X_INV \NlwInverterBlock_outDATA<4>\$WA5.UIM_MC.D2_PT_3/IN1  (
    .I(DCOR1CNTLOWr),
    .O(\NlwInverterSignal_outDATA<4>\$WA5.UIM_MC.D2_PT_3/IN1 )
  );
  X_INV \NlwInverterBlock_outDATA<4>\$WA5.UIM_MC.D2_PT_3/IN2  (
    .I(DCOR0CNTHIGHr),
    .O(\NlwInverterSignal_outDATA<4>\$WA5.UIM_MC.D2_PT_3/IN2 )
  );
  X_INV \NlwInverterBlock_U1/U3/holdingreg0<4>_MC.D2_PT_1/IN1  (
    .I(\AS_II/UIM ),
    .O(\NlwInverterSignal_U1/U3/holdingreg0<4>_MC.D2_PT_1/IN1 )
  );
  X_INV \NlwInverterBlock_U1/U3/holdingreg1<4>_MC.D2_PT_1/IN1  (
    .I(\AS_II/UIM ),
    .O(\NlwInverterSignal_U1/U3/holdingreg1<4>_MC.D2_PT_1/IN1 )
  );
  X_INV \NlwInverterBlock_U1/U3/holdingreg0<12>_MC.D2_PT_1/IN1  (
    .I(\AS_II/UIM ),
    .O(\NlwInverterSignal_U1/U3/holdingreg0<12>_MC.D2_PT_1/IN1 )
  );
  X_INV \NlwInverterBlock_U1/U3/holdingreg1<12>_MC.D2_PT_1/IN1  (
    .I(\AS_II/UIM ),
    .O(\NlwInverterSignal_U1/U3/holdingreg1<12>_MC.D2_PT_1/IN1 )
  );
  X_INV \NlwInverterBlock_FOOBAR2__ctinst/7/OUT  (
    .I(\NlwInverterSignal_FOOBAR2__ctinst/7/OUT ),
    .O(\FOOBAR2__ctinst/7 )
  );
  X_INV \NlwInverterBlock_FOOBAR3__ctinst/7/OUT  (
    .I(\NlwInverterSignal_FOOBAR3__ctinst/7/OUT ),
    .O(\FOOBAR3__ctinst/7 )
  );
  X_INV \NlwInverterBlock_FOOBAR5__ctinst/4/IN1  (
    .I(N_PZ_953),
    .O(\NlwInverterSignal_FOOBAR5__ctinst/4/IN1 )
  );
  X_INV \NlwInverterBlock_FOOBAR21__ctinst/4/IN0  (
    .I(NET2528),
    .O(\NlwInverterSignal_FOOBAR21__ctinst/4/IN0 )
  );
  X_INV \NlwInverterBlock_FOOBAR21__ctinst/4/IN1  (
    .I(\U4/orFLGs ),
    .O(\NlwInverterSignal_FOOBAR21__ctinst/4/IN1 )
  );
  X_INV \NlwInverterBlock_FOOBAR24__ctinst/4/IN0  (
    .I(NET2528),
    .O(\NlwInverterSignal_FOOBAR24__ctinst/4/IN0 )
  );
  X_INV \NlwInverterBlock_FOOBAR24__ctinst/4/IN1  (
    .I(\U4/orFLGs ),
    .O(\NlwInverterSignal_FOOBAR24__ctinst/4/IN1 )
  );
endmodule

