//--------------------------------------------------------------------------------------------------
//
// Title       : PwrCtrl
// Design      : U4
// Author      : mbari###
// Company     : MBARI
//
//-------------------------------------------------------------------------------------------------
//
// File        : c:\Projects\genosensor\2g\CPLDs\Core\U4\src\PwrCtrl.v
// Generated   : Thu Dec 18 09:05:49 2003
// From        : interface description file
// By          : Itf2Vhdl ver. 1.20
//
//-------------------------------------------------------------------------------------------------
//
// Description : 
//
//-------------------------------------------------------------------------------------------------
`timescale 1ps / 1ps

//{{ Section below this comment is automatically maintained
//   and may be overwritten
//{module {PwrCtrl}}
module PwrCtrl ( Enc5ctrl ,Reset ,Home33ctrl ,Enc5FLG ,Mclk ,Home33FLG ,WR ,RDslct ,inDATA ,Enc33ctrl ,outDATA ,Home5ctrl ,AS ,Enc33FLG ,RD ,Home5FLG ,ADDR ,WRslct );

input [3:0] inDATA ;
wire [3:0] inDATA ;
input Reset ;
wire Reset ;
input Enc5FLG ;
wire Enc5FLG ;
input AS ;
wire AS ;
input Enc33FLG ;
wire Enc33FLG ;
input RD ;
wire RD ;
input Home5FLG ;
wire Home5FLG ;
input Mclk ;
wire Mclk ;
input Home33FLG ;
wire Home33FLG ;
input WR ;
wire WR ;
input [7:0] ADDR ;
wire [7:0] ADDR ;
input RDslct ;
wire RDslct ;
input WRslct ;
wire WRslct ;

output Enc5ctrl ;
wire Enc5ctrl ;
output Enc33ctrl ;
wire Enc33ctrl ;
output [3:0] outDATA ;
wire [3:0] outDATA ;
output Home5ctrl ;
wire Home5ctrl ;
output Home33ctrl ;
wire Home33ctrl ;

//}} End of automatically maintained section

// -- Enter your statements here -- //


//assign RDslct = (!AS & RD & !WR & (ADDR == 8'h05));
reg [3:0] ctrlr;

assign outDATA = (RDslct) ? {Enc5FLG, Enc33FLG, Home5FLG, Home33FLG} : 4'bz;
assign Enc5ctrl = !ctrlr[3] | (ctrlr[2] & ctrlr[3]);	   //this is reguired since the register power up low
assign Enc33ctrl = !ctrlr[2] | (ctrlr[2] & ctrlr[3]);     //this will cause the output to begin high and power off!
assign Home5ctrl = !ctrlr[1] | (ctrlr[1] & ctrlr[0]);    //this forces both off if both are tried to turn on
assign Home33ctrl = !ctrlr[0] | (ctrlr[1] & ctrlr[0]);   //not a good condition if both are on at the same time!

always @ (posedge Mclk)
	begin
		if (Reset) ctrlr <= 4'b0;
		else if (WRslct) ctrlr <= {inDATA[3], inDATA[2], inDATA[1], inDATA[0]};
	end
endmodule
