//--------------------------------------------------------------------------------------------------
//
// Title       : AddDecode
// Design      : U4
// Author      : mbari###
// Company     : MBARI
//
//-------------------------------------------------------------------------------------------------
//
// File        : c:\Projects\genosensor\2g\CPLDs\Core\U4\src\AddDecode.v
// Generated   : Fri Jan 23 09:20:32 2004
// From        : interface description file
// By          : Itf2Vhdl ver. 1.20
//
//-------------------------------------------------------------------------------------------------
//
// Description : 
//
//-------------------------------------------------------------------------------------------------
`timescale 1ps / 1ps

//{{ Section below this comment is automatically maintained
//   and may be overwritten
//{module {AddDecode}}
module AddDecode ( Wslctd ,Wslct6 ,Wslct7 ,AS ,Wslct9 ,RD ,Rslct0 ,Rslct1 ,Rslcta ,WR ,Rslct2 ,Rslctb ,Rslct3 ,ADDR ,Rslct4 ,Rslct5 ,Wslcta ,Rslct7 );

input WR ;
wire WR ;
input [7:0] ADDR ;
wire [7:0] ADDR ;
input AS ;
wire AS ;
input RD ;
wire RD ;

output Wslctd ;
wire Wslctd ;
output Wslct6 ;
wire Wslct6 ;
output Wslct7 ;
wire Wslct7 ;
output Wslct9 ;
wire Wslct9 ;
output Rslct0 ;
wire Rslct0 ;
output Rslct1 ;
wire Rslct1 ;
output Rslcta ;
wire Rslcta ;
output Rslct2 ;
wire Rslct2 ;
output Rslctb ;
wire Rslctb ;
output Rslct3 ;
wire Rslct3 ;
output Rslct4 ;
wire Rslct4 ;
output Rslct5 ;
wire Rslct5 ;
output Wslcta ;
wire Wslcta ;
output Rslct7 ;
wire Rslct7 ;

//}} End of automatically maintained section

// -- Enter your statements here -- //
//All of these select signals should have a matching
//keep statement for synthesis

//synthesis attribute KEEP of Rslctb is TRUE;
assign Rslctb = (!AS & !RD &WR & (ADDR == 8'h0b));
//synthesis attribute KEEP of Wslcta is TRUE;
assign Wslcta = (!AS & RD & !WR & (ADDR == 8'h0a));
//synthesis attribute KEEP of Rslct4 is TRUE;
assign Rslct4 = (!AS & RD & !WR & (ADDR == 8'h04));
//synthesis attribute KEEP of Rslct5 is TRUE;
assign Rslct5 = (!AS & RD & !WR & (ADDR == 8'h05));
//synthesis attribute KEEP of Wslct6 is TRUE;
assign Wslct6 = (!AS & !RD & WR & (ADDR == 8'h06));
//synthesis attribute KEEP of RslctA is TRUE;
assign Rslcta = (!AS & RD & !WR & (ADDR == 8'h0a));
//synthesis attribute KEEP of Wslct9 is TRUE;
assign Wslct9 = (!AS & !RD & WR & (ADDR == 8'h09));	
//synthesis attribute KEEP of Wslctd is TRUE;
assign Wslctd = (!AS & !RD & WR & (ADDR == 8'h0d));	  
//synthesis attribute KEEP of Rslct0 is TRUE;
assign Rslct0 = (!AS & RD & !WR & (ADDR == 8'h00));
//synthesis attribute KEEP of Rslct1 is TRUE;
assign Rslct1 = (!AS & RD & !WR & (ADDR == 8'h01));
//synthesis attribute KEEP of Rslct2 is TRUE;
assign Rslct2 = (!AS & RD & !WR & (ADDR == 8'h02));
//synthesis attribute KEEP of Rslct3 is TRUE;
assign Rslct3 = (!AS & RD & !WR & (ADDR == 8'h03));
//synthesis attribute KEEP of Rslct7 is TRUE;
assign Rslct7 = (!AS & RD & !WR & (ADDR == 8'h07));
//synthesis attribute KEEP of Wslct7 is TRUE;
assign Wslct7 = (!AS & !RD & WR & (ADDR == 8'h07));

endmodule
