//--------------------------------------------------------------------------------------------------
//
// Title       : U4 TestBench
// Design      : U4
// Author      : mbari###
// Company     : MBARI
//
//-------------------------------------------------------------------------------------------------
//
// File        : C:\Projects\genosensor\2g\CPLDs\Core\U21\restore\U4\compile\U4_TB.v
// Generated   : Fri Mar  5 13:59:35 2004
// From        : C:\Projects\genosensor\2g\CPLDs\Core\U21\restore\U4\src\U4_TB.bde
// By          : Bde2Verilog ver. 2.01
//
//-------------------------------------------------------------------------------------------------
//
// Description : 
//
//-------------------------------------------------------------------------------------------------

// synopsys translate_off
`ifdef _VCP
`else
`define library(a,b)
`endif
// synopsys translate_on


// ---------- Design Unit Header ---------- //
`timescale 1ps / 1ps

module U4_TB (Enc133FLG,Enc15FLG,FLS1,FLS2,Home1,Home133FLG,Home15FLG,Home2,PhaseA_Encoder1,PhaseB_Encoder1,
RLS1,RLS2,Reset,Enc133ctrl,Enc15ctrl,Home133ctrl,Home15ctrl) ;

// ------------ Port declarations --------- //
input Enc133FLG;
wire Enc133FLG;
input Enc15FLG;
wire Enc15FLG;
input FLS1;
wire FLS1;
input FLS2;
wire FLS2;
input Home1;
wire Home1;
input Home133FLG;
wire Home133FLG;
input Home15FLG;
wire Home15FLG;
input Home2;
wire Home2;
input PhaseA_Encoder1;
wire PhaseA_Encoder1;
input PhaseB_Encoder1;
wire PhaseB_Encoder1;
input RLS1;
wire RLS1;
input RLS2;
wire RLS2;
input Reset;
wire Reset;
output Enc133ctrl;
wire Enc133ctrl;
output Enc15ctrl;
wire Enc15ctrl;
output Home133ctrl;
wire Home133ctrl;
output Home15ctrl;
wire Home15ctrl;

// ----------- Signal declarations -------- //
wire AS;
wire Mclk;
wire RD;
wire WR;
wire [7:0] AD;

// -------- Component instantiations -------//

U4 U1
(
	.AD(AD),
	.AS(AS),
	.Aclk(Mclk),
	.Enc133FLG(Enc133FLG),
	.Enc133ctrl(Enc133ctrl),
	.Enc15FLG(Enc15FLG),
	.Enc15ctrl(Enc15ctrl),
	.FLS1(FLS1),
	.FLS2(FLS2),
	.Home1(Home1),
	.Home133FLG(Home133FLG),
	.Home133ctrl(Home133ctrl),
	.Home15FLG(Home15FLG),
	.Home15ctrl(Home15ctrl),
	.Home2(Home2),
	.Mclk(Mclk),
	.PhaseA_Encoder1(PhaseA_Encoder1),
	.PhaseB_Encoder1(PhaseB_Encoder1),
	.RD(RD),
	.RLS1(RLS1),
	.RLS2(RLS2),
	.Reset(Reset),
	.SMclk(Mclk),
	.WR(WR)
);



MSP U2
(
	.AD(AD),
	.AS(AS),
	.Mclk(Mclk),
	.RD(RD),
	.WR(WR)
);



endmodule 
