//--------------------------------------------------------------------------------------------------
//
// Title       : IntControl
// Design      : U4
// Author      : mbari###
// Company     : MBARI
//
//-------------------------------------------------------------------------------------------------
//
// File        : c:\Projects\genosensor\2g\CPLDs\Core\U4\src\IntControl.v
// Generated   : Mon Dec 22 13:08:10 2003
// From        : interface description file
// By          : Itf2Vhdl ver. 1.20
//
//-------------------------------------------------------------------------------------------------
//
// Description : 
//
//-------------------------------------------------------------------------------------------------
`timescale 1ps / 1ps

//{{ Section below this comment is automatically maintained
//   and may be overwritten
//{module {IntControl}}
module IntControl ( WRslct1 ,WRslct2 ,inDATA ,outDATA ,Reset ,AS ,PWRflgs ,fBRK1 ,RD ,fBRK2 ,Mclk ,WR ,INT ,ADDR ,RDslct );

input WRslct1 ;
wire WRslct1 ;
input WRslct2 ;
wire WRslct2 ;
input [7:0] inDATA ;
wire [7:0] inDATA ;
input Reset ;
wire Reset ;
input AS ;
wire AS ;
input [7:0] PWRflgs ;
wire [7:0] PWRflgs ;
input fBRK1 ;
wire fBRK1 ;
input RD ;
wire RD ;
input fBRK2 ;
wire fBRK2 ;
input Mclk ;
wire Mclk ;
input WR ;
wire WR ;
input [7:0] ADDR ;
wire [7:0] ADDR ;
input RDslct ;
wire RDslct ;

output [7:0] outDATA ;
wire [7:0] outDATA ;
output INT ;
wire INT ;

//}} End of automatically maintained section

// -- Enter your statements here -- //

reg [7:0] INTreg;				  
reg [7:0] INTenabler;

wire pullINT;				  
wire globalINT;

assign outDATA = (RDslct) ? INTreg : 8'bz; //read which bits are set initial interrupt register

assign globalINT = (INTreg[7] & INTenabler[7]);
assign INT = (globalINT) ? 1'b0 : 1'bz;

always @ (posedge Mclk)
	begin
		if (Reset) {INTreg, INTenabler}  <= 16'b0;  //reset everything to 0
		else
			begin						  
				if (WRslct1) INTenabler <= inDATA;  //write the enable bits
				if (WRslct2) INTreg <= (!inDATA & INTreg); //reset only the bits which are 1 in the inDATA
				else 
					begin
						if (fBRK1) INTreg[5] <= 1'b1;  //if BRK line high signal it
						else INTreg[5] <= INTreg[5];
						if (fBRK2) INTreg[6] <= 1'b1;  //if BRK line high signal it
						else INTreg[6] <= INTreg[6];
						if (INTreg[0] | INTreg[1] | INTreg[2] | INTreg[3] | INTreg[4] | INTreg[5] | INTreg[6]) INTreg[7] <= 1'b1; //global interrupt
						else INTreg[7] <= INTreg[7];
						if (!PWRflgs[0] | !PWRflgs[1] | !PWRflgs[2] | !PWRflgs[3]) INTreg[1] <= 1'b1; //power flags, channel 1
						else INTreg[1] <= INTreg[1];
						if (!PWRflgs[4] | !PWRflgs[5] | !PWRflgs[6] | !PWRflgs[7]) INTreg[2] <= 1'b1; //power flags, channel 2
						else INTreg[2] <= INTreg[2];
							
					end
			end
	end
endmodule
