//--------------------------------------------------------------------------------------------------
//
// Title       : No Title
// Design      : 
// Author      : 
// Company     : 
//
//-------------------------------------------------------------------------------------------------
//
// File        : C:\Projects\genosensor\2g\CPLDs\Core\U21\restore\U4\compile\Qdecode.v
// Generated   : 03/05/04 13:59:34
// From        : C:\Projects\genosensor\2g\CPLDs\Core\U21\restore\U4\src\Qdecode.asf
// By          : FSM2VHDL ver. 4.0.3.8
//
//-------------------------------------------------------------------------------------------------
//
// Description : 
//
//-------------------------------------------------------------------------------------------------

`timescale 1ns / 1ps

module Decode (Reset, Sclk, ce, phaseA, phaseB, updown);
input   Reset;
input   Sclk;
input   phaseA;
input   phaseB;
inout   ce;
inout   updown;

wire    Reset;
wire    Sclk;
wire    ce;
reg     ino_ce;
wire    phaseA;
wire    phaseB;
wire    updown;
reg     ino_updown;

// USER DEFINED ENCODED state machine: Sreg0
// State codes definitions:
`define S1 4'b0000
`define S2 4'b1000
`define S4 4'b0001
`define S5 4'b0010
`define S3 4'b1001
`define S6 4'b1010
`define S7 4'b0011
`define S8 4'b0100
`define S9 4'b1100

reg [3:0] CurrState_Sreg0;
reg [3:0] NextState_Sreg0;

// Diagram actions (continuous assignments allowed only: assign ...)
assign updown = CurrState_Sreg0[3];
assign ce = CurrState_Sreg0[2];


//--------------------------------------------------------------------
// Machine: Sreg0
//--------------------------------------------------------------------
//----------------------------------
// NextState logic (combinatorial)
//----------------------------------
always @ (phaseA or phaseB or CurrState_Sreg0)
begin : Sreg0_NextState
	NextState_Sreg0 <= CurrState_Sreg0;
	// Set default values for outputs and signals
	// ... 
	case (CurrState_Sreg0) // synopsys parallel_case full_case
		`S1:
			if ((phaseA == 1'b1)&&
				(phaseB == 1'b0))	
				NextState_Sreg0 <= `S2;
			else if ((phaseA == 1'b0)&&
				(phaseB == 1'b1))	
				NextState_Sreg0 <= `S4;
		`S2:
			if ((phaseA == 1'b1)&&
				(phaseB == 1'b0))	
				NextState_Sreg0 <= `S2;
			else if ((phaseA == 1'b0)&&
				(phaseB == 1'b0))	
				NextState_Sreg0 <= `S1;
			else if ((phaseA == 1'b1)&&
				(phaseB == 1'b1))	
				NextState_Sreg0 <= `S3;
		`S4:
			if ((phaseA == 1'b1)&&
				(phaseB == 1'b1))	
				NextState_Sreg0 <= `S5;
			else if ((phaseA == 1'b0)&&
				(phaseB == 1'b1))	
				NextState_Sreg0 <= `S4;
			else if ((phaseA == 1'b0)&&
				(phaseB == 1'b0))	
				NextState_Sreg0 <= `S1;
		`S5:
			if ((phaseA == 1'b1)&&
				(phaseB == 1'b0))	
				NextState_Sreg0 <= `S7;
			else if ((phaseA == 1'b1)&&
				(phaseB == 1'b1))	
				NextState_Sreg0 <= `S5;
			else if ((phaseA == 1'b0)&&
				(phaseB == 1'b1))	
				NextState_Sreg0 <= `S4;
		`S3:
			if ((phaseA == 1'b0)&&
				(phaseB == 1'b1))	
				NextState_Sreg0 <= `S6;
			else if ((phaseA == 1'b1)&&
				(phaseB == 1'b1))	
				NextState_Sreg0 <= `S3;
			else if ((phaseA == 1'b1)&&
				(phaseB == 1'b0))	
				NextState_Sreg0 <= `S2;
		`S6:
			if ((phaseA == 1'b0)&&
				(phaseB == 1'b0))	
				NextState_Sreg0 <= `S9;
			else if ((phaseA == 1'b0)&&
				(phaseB == 1'b1))	
				NextState_Sreg0 <= `S6;
			else if ((phaseA == 1'b1)&&
				(phaseB == 1'b1))	
				NextState_Sreg0 <= `S3;
		`S7:
			if ((phaseA == 1'b0)&&
				(phaseB == 1'b0))	
				NextState_Sreg0 <= `S8;
			else if ((phaseA == 1'b1)&&
				(phaseB == 1'b0))	
				NextState_Sreg0 <= `S7;
			else if ((phaseA == 1'b1)&&
				(phaseB == 1'b1))	
				NextState_Sreg0 <= `S5;
		`S8:
			NextState_Sreg0 <= `S1;
		`S9:
			NextState_Sreg0 <= `S1;
	endcase
end

//----------------------------------
// Current State Logic (sequential)
//----------------------------------
always @ (posedge Sclk)
begin : Sreg0_CurrentState
	if (Reset)	
		CurrState_Sreg0 <= `S1;
	else
		CurrState_Sreg0 <= NextState_Sreg0;
end

endmodule