// Xilinx Verilog netlist produced by netgen application (version G.26)
// Command      : -sim -ofmt verilog -sdf_path c:\Projects\genosensor\2g\CPLDs\Core\U21\implement U21.nga c:\Projects\genosensor\2g\CPLDs\Core\U21\implement\ver0\rev2\time_sim.v 
// Input file   : U21.nga
// Output file  : c:/Projects/genosensor/2g/CPLDs/Core/U21/implement/ver0/rev2/time_sim.v
// Design name  : U21.nga
// # of Modules : 1
// Xilinx       : C:/Xilinx
// Device       : XCR3384XL-7-TQ144 (Speed File: Version 6.0)

// This verilog netlist is a simulation model and uses simulation 
// primitives which may not represent the true implementation of the 
// device, however the netlist is functionally correct and should not 
// be modified. This file cannot be synthesized and should only be used 
// with supported simulation tools.

`timescale 1 ns/1 ps

module U21 (
  Brake0, Brake1, DIR0, DIR1, WR, RD, MSPReset, AS, Mclk, FLS0, FLS1, PWM5, PWM3, HSI, MHSO, INTbus, Home15FLG, Home133FLG, Home05FLG, Home033FLG, 
Enc15FLG, Enc133FLG, Enc05FLG, Enc033FLG, RLS0, RLS1, GP_Motor0_0, GP_Motor1_0, SCLreset, SCLinc, LightSense, TXI, PWM1, PWM2, PhaseA_Encoder0, 
PhaseA_Encoder1, PhaseB_Encoder0, PhaseB_Encoder1, Home0, Home1, Enc033ctrl, Enc05ctrl, Enc133ctrl, Enc15ctrl, GPIO8, GPIO9, GP_Motor0_1, GP_Motor1_1
, HSO, Home033ctrl, Home05ctrl, Home133ctrl, Home15ctrl, INT, LED1, LED2, LED3, LED4, LED5, MHSI, MTRpwr, MTRpwrn, MTXI, PAH0, PAH1, PAL0, PAL1, PBH0
, PBH1, PBL0, PBL1, PresEn, PresSlct, SCLout, TP10, TP11, TP12, TmpEn, TmpSlct, SCL, I2CS, AD
);
  input Brake0;
  input Brake1;
  input DIR0;
  input DIR1;
  input WR;
  input RD;
  input MSPReset;
  input AS;
  input Mclk;
  input FLS0;
  input FLS1;
  input PWM5;
  input PWM3;
  input HSI;
  input MHSO;
  input INTbus;
  input Home15FLG;
  input Home133FLG;
  input Home05FLG;
  input Home033FLG;
  input Enc15FLG;
  input Enc133FLG;
  input Enc05FLG;
  input Enc033FLG;
  input RLS0;
  input RLS1;
  input GP_Motor0_0;
  input GP_Motor1_0;
  input SCLreset;
  input SCLinc;
  input LightSense;
  input TXI;
  input PWM1;
  input PWM2;
  input PhaseA_Encoder0;
  input PhaseA_Encoder1;
  input PhaseB_Encoder0;
  input PhaseB_Encoder1;
  input Home0;
  input Home1;
  output Enc033ctrl;
  output Enc05ctrl;
  output Enc133ctrl;
  output Enc15ctrl;
  output GPIO8;
  output GPIO9;
  output GP_Motor0_1;
  output GP_Motor1_1;
  output HSO;
  output Home033ctrl;
  output Home05ctrl;
  output Home133ctrl;
  output Home15ctrl;
  output INT;
  output LED1;
  output LED2;
  output LED3;
  output LED4;
  output LED5;
  output MHSI;
  output MTRpwr;
  output MTRpwrn;
  output MTXI;
  output PAH0;
  output PAH1;
  output PAL0;
  output PAL1;
  output PBH0;
  output PBH1;
  output PBL0;
  output PBL1;
  output PresEn;
  output PresSlct;
  output SCLout;
  output TP10;
  output TP11;
  output TP12;
  output TmpEn;
  output TmpSlct;
  inout SCL;
  input [5 : 0] I2CS;
  inout [7 : 0] AD;
  wire \Brake0_II/UIM ;
  wire \Brake1_II/UIM ;
  wire \DIR0_II/UIM ;
  wire \DIR1_II/UIM ;
  wire NlwRenamedSig_IO_WR;
  wire \WR_II/UIM ;
  wire NlwRenamedSig_IO_RD;
  wire \RD_II/UIM ;
  wire \MSPReset_II/UIM ;
  wire \AD<0>_II/UIM ;
  wire \AD<0>_II/IREG ;
  wire \FOOBAR3__ctinst/7 ;
  wire PRLD = glbl.PRLD;
  wire \U4/ctrlr<0>_MC_tsimcreated_prld_ ;
  wire \Mclk_II/FCLK ;
  wire \U4/ctrlr<0>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ;
  wire Gnd;
  wire \FOOBAR12__ctinst/4 ;
  wire NlwRenamedSig_IO_AS;
  wire \AS_II/UIM ;
  wire U2_ASedge;
  wire \AS_II/IREG ;
  wire \U2_ASedge_MC.REG_tsimcreated_inv_Mclk_II/FCLK ;
  wire Vcc;
  wire \AD<4>_II/UIM ;
  wire \AD<4>_II/IREG ;
  wire \U4/ctrlr<4>_MC_tsimcreated_prld_ ;
  wire \U4/ctrlr<4>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ;
  wire \FOOBAR10__ctinst/4 ;
  wire \AD<5>_II/UIM ;
  wire \AD<5>_II/IREG ;
  wire \U4/ctrlr<5>_MC_tsimcreated_prld_ ;
  wire \U4/ctrlr<5>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ;
  wire \AD<6>_II/UIM ;
  wire \AD<6>_II/IREG ;
  wire \U4/ctrlr<6>_MC_tsimcreated_prld_ ;
  wire \U4/ctrlr<6>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ;
  wire \AD<7>_II/UIM ;
  wire \AD<7>_II/IREG ;
  wire \U4/ctrlr<7>_MC_tsimcreated_prld_ ;
  wire \U4/ctrlr<7>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ;
  wire \FOOBAR9__ctinst/4 ;
  wire \AD<3>_II/UIM ;
  wire \AD<3>_II/IREG ;
  wire \U4/ctrlr<3>_MC_tsimcreated_prld_ ;
  wire \U4/ctrlr<3>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ;
  wire \AD<1>_II/UIM ;
  wire \AD<1>_II/IREG ;
  wire \U4/ctrlr<1>_MC_tsimcreated_prld_ ;
  wire \U4/ctrlr<1>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ;
  wire \AD<2>_II/UIM ;
  wire \AD<2>_II/IREG ;
  wire \U4/ctrlr<2>_MC_tsimcreated_prld_ ;
  wire \U4/ctrlr<2>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ;
  wire \FLS0_II/UIM ;
  wire \FLS1_II/UIM ;
  wire \PWM5_II/UIM ;
  wire \PWM3_II/UIM ;
  wire \HSI_II/UIM ;
  wire \MHSO_II/UIM ;
  wire \I2CS<0>_II/UIM ;
  wire \I2CS<1>_II/UIM ;
  wire \I2CS<2>_II/UIM ;
  wire \I2CS<3>_II/UIM ;
  wire \I2CS<4>_II/UIM ;
  wire \I2CS<5>_II/UIM ;
  wire \INTbus_II/UIM ;
  wire NlwRenamedSig_IO_Home15FLG;
  wire \Home15FLG_II/UIM ;
  wire \Home15FLG_II/IREG ;
  wire \U4/Flgreg<5>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ;
  wire \FOOBAR21__ctinst/4 ;
  wire NlwRenamedSig_IO_Home133FLG;
  wire \Home133FLG_II/UIM ;
  wire \Home133FLG_II/IREG ;
  wire \U4/Flgreg<4>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ;
  wire NlwRenamedSig_IO_Home05FLG;
  wire \Home05FLG_II/UIM ;
  wire \Home05FLG_II/IREG ;
  wire \U4/Flgreg<1>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ;
  wire NlwRenamedSig_IO_Home033FLG;
  wire \Home033FLG_II/UIM ;
  wire \Home033FLG_II/IREG ;
  wire \U4/Flgreg<0>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ;
  wire NlwRenamedSig_IO_Enc15FLG;
  wire \Enc15FLG_II/UIM ;
  wire \Enc15FLG_II/IREG ;
  wire \U4/Flgreg<7>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ;
  wire \FOOBAR24__ctinst/4 ;
  wire NlwRenamedSig_IO_Enc133FLG;
  wire \Enc133FLG_II/UIM ;
  wire \Enc133FLG_II/IREG ;
  wire \U4/Flgreg<6>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ;
  wire NlwRenamedSig_IO_Enc05FLG;
  wire \Enc05FLG_II/UIM ;
  wire \Enc05FLG_II/IREG ;
  wire \U4/Flgreg<3>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ;
  wire NlwRenamedSig_IO_Enc033FLG;
  wire \Enc033FLG_II/UIM ;
  wire \Enc033FLG_II/IREG ;
  wire \U4/Flgreg<2>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ;
  wire \RLS0_II/UIM ;
  wire \RLS1_II/UIM ;
  wire \GP_Motor0_0_II/UIM ;
  wire \U1/U4/InEdge0r ;
  wire \GP_Motor0_0_II/IREG ;
  wire \U1/U4/InEdge0r_MC.REG_tsimcreated_inv_Mclk_II/FCLK ;
  wire \GP_Motor1_0_II/UIM ;
  wire \U1/U4/InEdge1r ;
  wire \GP_Motor1_0_II/IREG ;
  wire \U1/U4/InEdge1r_MC.REG_tsimcreated_inv_Mclk_II/FCLK ;
  wire \SCLreset_II/UIM ;
  wire \U11_U4/Line_last ;
  wire \SCLreset_II/IREG ;
  wire \U11_U4/Line_last_MC.REG_tsimcreated_inv_Mclk_II/FCLK ;
  wire \SCLinc_II/UIM ;
  wire \U11_U1/Line_last ;
  wire \SCLinc_II/IREG ;
  wire \U11_U1/Line_last_MC.REG_tsimcreated_inv_Mclk_II/FCLK ;
  wire \SCL_II/UIM ;
  wire \U11_U2/Line_last ;
  wire \SCL_II/IREG ;
  wire \U11_U2/Line_last_MC.REG_tsimcreated_inv_Mclk_II/FCLK ;
  wire \LightSense_II/UIM ;
  wire \TXI_II/UIM ;
  wire \PWM1_II/UIM ;
  wire \PWM2_II/UIM ;
  wire \PhaseA_Encoder0_II/UIM ;
  wire \PhaseA_Encoder1_II/UIM ;
  wire \PhaseB_Encoder0_II/UIM ;
  wire \PhaseB_Encoder1_II/UIM ;
  wire \Home0_II/UIM ;
  wire \U1/U4/HE0stater ;
  wire \Home0_II/IREG ;
  wire \U1/U4/HE0stater_MC.REG_tsimcreated_inv_Mclk_II/FCLK ;
  wire \Home1_II/UIM ;
  wire \U1/U4/HE1stater ;
  wire \Home1_II/IREG ;
  wire \U1/U4/HE1stater_MC.REG_tsimcreated_inv_Mclk_II/FCLK ;
  wire \Enc033ctrl_MC.Q ;
  wire \Enc05ctrl_MC.Q ;
  wire \Enc133ctrl_MC.Q ;
  wire \Enc15ctrl_MC.Q ;
  wire \GPIO8_MC.Q ;
  wire \GPIO9_MC.Q ;
  wire \GP_Motor0_1_MC.Q ;
  wire \GP_Motor1_1_MC.Q ;
  wire \HSO_MC.Q ;
  wire \Home033ctrl_MC.Q ;
  wire \Home05ctrl_MC.Q ;
  wire \Home133ctrl_MC.Q ;
  wire \Home15ctrl_MC.Q ;
  wire \INT_MC.Q ;
  wire \LED1_MC.Q ;
  wire \LED2_MC.Q ;
  wire \LED3_MC.Q ;
  wire \LED4_MC.Q ;
  wire \LED5_MC.Q ;
  wire \MHSI_MC.Q ;
  wire \MTRpwr_MC.Q ;
  wire \MTRpwrn_MC.Q ;
  wire \MTXI_MC.Q ;
  wire \PAH0_MC.Q ;
  wire \PAH1_MC.Q ;
  wire \PAL0_MC.Q ;
  wire \PAL1_MC.Q ;
  wire \PBH0_MC.Q ;
  wire \PBH1_MC.Q ;
  wire \PBL0_MC.Q ;
  wire \PBL1_MC.Q ;
  wire \PresEn_MC.Q ;
  wire \PresSlct_MC.Q ;
  wire \SCLout_MC.Q ;
  wire \TP10_MC.Q ;
  wire \TP11_MC.Q ;
  wire \TP12_MC.Q ;
  wire \TmpEn_MC.Q ;
  wire \TmpSlct_MC.Q ;
  wire \U11_U2/Line_last_MC.Q ;
  wire \U11_U2/Line_last_MC.OE ;
  wire \U4/ctrlr<0>_MC.Q ;
  wire \U4/ctrlr<0>_MC.OE ;
  wire \U4/ctrlr<1>_MC.Q ;
  wire \U4/ctrlr<1>_MC.OE ;
  wire \U4/ctrlr<2>_MC.Q ;
  wire \U4/ctrlr<2>_MC.OE ;
  wire \U4/ctrlr<3>_MC.Q ;
  wire \U4/ctrlr<3>_MC.OE ;
  wire \U4/ctrlr<4>_MC.Q ;
  wire \U4/ctrlr<4>_MC.OE ;
  wire \U4/ctrlr<5>_MC.Q ;
  wire \U4/ctrlr<5>_MC.OE ;
  wire \U4/ctrlr<6>_MC.Q ;
  wire \U4/ctrlr<6>_MC.OE ;
  wire \U4/ctrlr<7>_MC.Q ;
  wire \U4/ctrlr<7>_MC.OE ;
  wire \Enc033ctrl_MC.Q_tsimrenamed_net_ ;
  wire \Enc033ctrl_MC.D ;
  wire \Enc033ctrl_MC.D1 ;
  wire \Enc033ctrl_MC.D2 ;
  wire \U4/ctrlr<2>_MC.D ;
  wire \U4/ctrlr<2>_MC.BUFOE.OUT ;
  wire \FOOBAR1__ctinst/7 ;
  wire \U4/ctrlr<2>_MC.D1 ;
  wire \U4/ctrlr<2>_MC.D2 ;
  wire DCORI2CCNTr;
  wire \outDATA<2>\$WA0.UIM ;
  wire \U4/ctrlr<2>_MC.D2_PT_0 ;
  wire DCORCONFIGr;
  wire \outDATA<2>\$WA1.UIM ;
  wire \U4/ctrlr<2>_MC.D2_PT_1 ;
  wire DCORLIMITSr;
  wire \outDATA<2>\$WA2.UIM ;
  wire \U4/ctrlr<2>_MC.D2_PT_2 ;
  wire DCORENCPWRr;
  wire \outDATA<2>\$WA3.UIM ;
  wire \U4/ctrlr<2>_MC.D2_PT_3 ;
  wire N_PZ_963;
  wire \outDATA<2>\$WA5.UIM ;
  wire \U4/ctrlr<2>_MC.D2_PT_4 ;
  wire N_PZ_980;
  wire \outDATA<2>\$WA6.UIM ;
  wire \U4/ctrlr<2>_MC.D2_PT_5 ;
  wire \DCORENCPWRw_MC.Q ;
  wire DCORENCPWRw;
  wire \DCORENCPWRw_MC.D ;
  wire \DCORENCPWRw_MC.D1 ;
  wire \DCORENCPWRw_MC.D2 ;
  wire \U2_ADDR_reg<0>_MC.Q ;
  wire \U2_ADDR_reg<0>_MC.D ;
  wire \U2_ADDR_reg<0>_MC_tsimcreated_xor_ ;
  wire \U2_ADDR_reg<0>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ;
  wire \U2_ADDR_reg<0>_MC.D1 ;
  wire \U2_ADDR_reg<0>_MC.D2 ;
  wire \U2_ADDR_reg<0>_MC.D2_PT_0 ;
  wire \U2_ADDR_reg<0>_MC.D2_PT_1 ;
  wire \U2_ADDR_reg<0>_MC.D2_PT_2 ;
  wire U2_AutoInc;
  wire U2_WRRDedge;
  wire N_PZ_941;
  wire \U2_ADDR_reg<0>_MC.D2_PT_3 ;
  wire \U2_ADDR_reg<4>_MC.Q ;
  wire \U2_ADDR_reg<4>_MC.D ;
  wire \U2_ADDR_reg<4>_MC_tsimcreated_xor_ ;
  wire \U2_ADDR_reg<4>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ;
  wire \U2_ADDR_reg<4>_MC.D1 ;
  wire \U2_ADDR_reg<4>_MC.D2 ;
  wire \U2_ADDR_reg<4>_MC.D2_PT_0 ;
  wire \U2_ADDR_reg<4>_MC.D2_PT_1 ;
  wire \U2_ADDR_reg<4>_MC.D2_PT_2 ;
  wire \U2_ADDR_reg<5>_MC.Q ;
  wire \U2_ADDR_reg<5>_MC.D ;
  wire \U2_ADDR_reg<5>_MC_tsimcreated_xor_ ;
  wire \U2_ADDR_reg<5>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ;
  wire \U2_ADDR_reg<5>_MC.D1 ;
  wire \U2_ADDR_reg<5>_MC.D2 ;
  wire \U2_ADDR_reg<5>_MC.D2_PT_0 ;
  wire \U2_ADDR_reg<5>_MC.D2_PT_1 ;
  wire \U2_ADDR_reg<5>_MC.D2_PT_2 ;
  wire \U2_ADDR_reg<6>_MC.Q ;
  wire \U2_ADDR_reg<6>_MC.D ;
  wire \U2_ADDR_reg<6>_MC_tsimcreated_xor_ ;
  wire \U2_ADDR_reg<6>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ;
  wire \U2_ADDR_reg<6>_MC.D1 ;
  wire \U2_ADDR_reg<6>_MC.D2 ;
  wire \U2_ADDR_reg<6>_MC.D2_PT_0 ;
  wire \U2_ADDR_reg<6>_MC.D2_PT_1 ;
  wire \U2_ADDR_reg<6>_MC.D2_PT_2 ;
  wire \U2_ADDR_reg<7>_MC.Q ;
  wire \U2_ADDR_reg<7>_MC.D ;
  wire \U2_ADDR_reg<7>_MC_tsimcreated_xor_ ;
  wire \U2_ADDR_reg<7>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ;
  wire \U2_ADDR_reg<7>_MC.D1 ;
  wire \U2_ADDR_reg<7>_MC.D2 ;
  wire \U2_ADDR_reg<7>_MC.D2_PT_0 ;
  wire \U2_ADDR_reg<7>_MC.D2_PT_1 ;
  wire \U2_ADDR_reg<7>_MC.D2_PT_2 ;
  wire \U2_AutoInc_MC.Q ;
  wire \U2_AutoInc_MC.D ;
  wire \U2_AutoInc_MC.REG_tsimcreated_inv_Mclk_II/FCLK ;
  wire \FOOBAR8__ctinst/4 ;
  wire \U2_AutoInc_MC.D1 ;
  wire \U2_AutoInc_MC.D2 ;
  wire \U2_WRRDedge_MC.Q ;
  wire \U2_WRRDedge_MC.D ;
  wire \U2_WRRDedge_MC.REG_tsimcreated_inv_Mclk_II/FCLK ;
  wire \U2_WRRDedge_MC.D1 ;
  wire \U2_WRRDedge_MC.D2 ;
  wire \N_PZ_955_MC.Q ;
  wire N_PZ_955;
  wire \N_PZ_955_MC.D ;
  wire \N_PZ_955_MC.D1 ;
  wire \N_PZ_955_MC.D2 ;
  wire \N_PZ_941_MC.Q ;
  wire \N_PZ_941_MC.D ;
  wire \N_PZ_941_MC.D1 ;
  wire \N_PZ_941_MC.D2 ;
  wire \N_PZ_941_MC.D2_PT_0 ;
  wire \N_PZ_941_MC.D2_PT_1 ;
  wire \U2_ADDR_reg<3>_MC.Q ;
  wire \U2_ADDR_reg<3>_MC.D ;
  wire \U2_ADDR_reg<3>_MC_tsimcreated_xor_ ;
  wire \U2_ADDR_reg<3>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ;
  wire \U2_ADDR_reg<3>_MC.D1 ;
  wire \U2_ADDR_reg<3>_MC.D2 ;
  wire \U2_ADDR_reg<3>_MC.D2_PT_0 ;
  wire \U2_ADDR_reg<3>_MC.D2_PT_1 ;
  wire \U2_ADDR_reg<3>_MC.D2_PT_2 ;
  wire \U2_ADDR_reg<3>_MC.D2_PT_3 ;
  wire \U2_ADDR_reg<1>_MC.Q ;
  wire \U2_ADDR_reg<1>_MC.D ;
  wire \U2_ADDR_reg<1>_MC_tsimcreated_xor_ ;
  wire \U2_ADDR_reg<1>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ;
  wire \U2_ADDR_reg<1>_MC.D1 ;
  wire \U2_ADDR_reg<1>_MC.D2 ;
  wire \U2_ADDR_reg<1>_MC.D2_PT_0 ;
  wire \U2_ADDR_reg<1>_MC.D2_PT_1 ;
  wire \U2_ADDR_reg<1>_MC.D2_PT_2 ;
  wire \U2_ADDR_reg<1>_MC.D2_PT_3 ;
  wire \U2_ADDR_reg<2>_MC.Q ;
  wire \U2_ADDR_reg<2>_MC.D ;
  wire \U2_ADDR_reg<2>_MC_tsimcreated_xor_ ;
  wire \U2_ADDR_reg<2>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ;
  wire \U2_ADDR_reg<2>_MC.D1 ;
  wire \U2_ADDR_reg<2>_MC.D2 ;
  wire \U2_ADDR_reg<2>_MC.D2_PT_0 ;
  wire \U2_ADDR_reg<2>_MC.D2_PT_1 ;
  wire \U2_ADDR_reg<2>_MC.D2_PT_2 ;
  wire \U2_ADDR_reg<2>_MC.D2_PT_3 ;
  wire \U2_Enable_AD_MC.Q ;
  wire U2_Enable_AD;
  wire \U2_Enable_AD_MC.D ;
  wire \U2_Enable_AD_MC.D1 ;
  wire \U2_Enable_AD_MC.D2 ;
  wire \U4/ctrlr<3>_MC.D ;
  wire \U4/ctrlr<3>_MC.BUFOE.OUT ;
  wire \U4/ctrlr<3>_MC.D1 ;
  wire \U4/ctrlr<3>_MC.D2 ;
  wire \outDATA<3>\$WA0.UIM ;
  wire \U4/ctrlr<3>_MC.D2_PT_0 ;
  wire \outDATA<3>\$WA1.UIM ;
  wire \U4/ctrlr<3>_MC.D2_PT_1 ;
  wire \outDATA<3>\$WA2.UIM ;
  wire \U4/ctrlr<3>_MC.D2_PT_2 ;
  wire \outDATA<3>\$WA3.UIM ;
  wire \U4/ctrlr<3>_MC.D2_PT_3 ;
  wire \outDATA<3>\$WA5.UIM ;
  wire \U4/ctrlr<3>_MC.D2_PT_4 ;
  wire \outDATA<3>\$WA6.UIM ;
  wire \U4/ctrlr<3>_MC.D2_PT_5 ;
  wire \Enc05ctrl_MC.Q_tsimrenamed_net_ ;
  wire \Enc05ctrl_MC.D ;
  wire \Enc05ctrl_MC.D1 ;
  wire \Enc05ctrl_MC.D2 ;
  wire \Enc133ctrl_MC.Q_tsimrenamed_net_ ;
  wire \Enc133ctrl_MC.D ;
  wire \Enc133ctrl_MC.D1 ;
  wire \Enc133ctrl_MC.D2 ;
  wire \U4/ctrlr<6>_MC.D ;
  wire \U4/ctrlr<6>_MC.BUFOE.OUT ;
  wire \U4/ctrlr<6>_MC.D1 ;
  wire \U4/ctrlr<6>_MC.D2 ;
  wire \outDATA<6>\$WA0.UIM ;
  wire \U4/ctrlr<6>_MC.D2_PT_0 ;
  wire \outDATA<6>\$WA1.UIM ;
  wire \U4/ctrlr<6>_MC.D2_PT_1 ;
  wire \outDATA<6>\$WA2.UIM ;
  wire \U4/ctrlr<6>_MC.D2_PT_2 ;
  wire \outDATA<6>\$WA3.UIM ;
  wire \U4/ctrlr<6>_MC.D2_PT_3 ;
  wire \outDATA<6>\$WA5.UIM ;
  wire \U4/ctrlr<6>_MC.D2_PT_4 ;
  wire \outDATA<6>\$WA6.UIM ;
  wire \U4/ctrlr<6>_MC.D2_PT_5 ;
  wire \U4/ctrlr<7>_MC.D ;
  wire \U4/ctrlr<7>_MC.BUFOE.OUT ;
  wire \U4/ctrlr<7>_MC.D1 ;
  wire \U4/ctrlr<7>_MC.D2 ;
  wire \outDATA<7>\$WA0.UIM ;
  wire \U4/ctrlr<7>_MC.D2_PT_0 ;
  wire \outDATA<7>\$WA1.UIM ;
  wire \U4/ctrlr<7>_MC.D2_PT_1 ;
  wire \outDATA<7>\$WA2.UIM ;
  wire \U4/ctrlr<7>_MC.D2_PT_2 ;
  wire \outDATA<7>\$WA3.UIM ;
  wire \U4/ctrlr<7>_MC.D2_PT_3 ;
  wire \outDATA<7>\$WA5.UIM ;
  wire \U4/ctrlr<7>_MC.D2_PT_4 ;
  wire \outDATA<7>\$WA4.UIM ;
  wire DCORIFGr;
  wire \U4/ctrlr<7>_MC.D2_PT_5 ;
  wire DCOR0THRESLOWr;
  wire \outDATA<7>\$WA6.UIM ;
  wire \U4/ctrlr<7>_MC.D2_PT_6 ;
  wire \U4/ctrlr<7>_MC.D2_PT_7 ;
  wire \Enc15ctrl_MC.Q_tsimrenamed_net_ ;
  wire \Enc15ctrl_MC.D ;
  wire \Enc15ctrl_MC.D1 ;
  wire \Enc15ctrl_MC.D2 ;
  wire \GPIO8_MC.Q_tsimrenamed_net_ ;
  wire \GPIO8_MC.D ;
  wire \GPIO8_MC.D1 ;
  wire \GPIO8_MC.D2 ;
  wire \GPIO9_MC.Q_tsimrenamed_net_ ;
  wire \GPIO9_MC.D ;
  wire \GPIO9_MC.D1 ;
  wire \GPIO9_MC.D2 ;
  wire \GP_Motor0_1_MC.Q_tsimrenamed_net_ ;
  wire GP_Motor0_1_MC_tsimcreated_prld_;
  wire \GP_Motor0_1_MC.D ;
  wire \GP_Motor0_1_MC.REG_tsimcreated_inv_Mclk_II/FCLK ;
  wire \GP_Motor0_1_MC.CE ;
  wire \GP_Motor0_1_MC.D1 ;
  wire \GP_Motor0_1_MC.D2 ;
  wire DCOROUTw;
  wire \DCOROUTw_MC.Q ;
  wire \DCOROUTw_MC.D ;
  wire \DCOROUTw_MC.D1 ;
  wire \DCOROUTw_MC.D2 ;
  wire \GP_Motor1_1_MC.Q_tsimrenamed_net_ ;
  wire GP_Motor1_1_MC_tsimcreated_prld_;
  wire \GP_Motor1_1_MC.D ;
  wire \GP_Motor1_1_MC.REG_tsimcreated_inv_Mclk_II/FCLK ;
  wire \FOOBAR15__ctinst/4 ;
  wire \GP_Motor1_1_MC.D1 ;
  wire \GP_Motor1_1_MC.D2 ;
  wire \HSO_MC.Q_tsimrenamed_net_ ;
  wire \HSO_MC.D ;
  wire \HSO_MC.D1 ;
  wire \HSO_MC.D2 ;
  wire \Home033ctrl_MC.Q_tsimrenamed_net_ ;
  wire \Home033ctrl_MC.D ;
  wire \Home033ctrl_MC.D1 ;
  wire \Home033ctrl_MC.D2 ;
  wire \U4/ctrlr<0>_MC.D ;
  wire \U4/ctrlr<0>_MC.BUFOE.OUT ;
  wire \U4/ctrlr<0>_MC.D1 ;
  wire \U4/ctrlr<0>_MC.D2 ;
  wire \outDATA<0>\$WA0.UIM ;
  wire \U4/ctrlr<0>_MC.D2_PT_0 ;
  wire \outDATA<0>\$WA1.UIM ;
  wire \U4/ctrlr<0>_MC.D2_PT_1 ;
  wire \outDATA<0>\$WA2.UIM ;
  wire \U4/ctrlr<0>_MC.D2_PT_2 ;
  wire \outDATA<0>\$WA3.UIM ;
  wire \U4/ctrlr<0>_MC.D2_PT_3 ;
  wire \outDATA<0>\$WA5.UIM ;
  wire \U4/ctrlr<0>_MC.D2_PT_4 ;
  wire \outDATA<0>\$WA4.UIM ;
  wire \U4/ctrlr<0>_MC.D2_PT_5 ;
  wire \outDATA<0>\$WA6.UIM ;
  wire \U4/ctrlr<0>_MC.D2_PT_6 ;
  wire \U4/ctrlr<0>_MC.D2_PT_7 ;
  wire \U4/ctrlr<1>_MC.D ;
  wire \U4/ctrlr<1>_MC.BUFOE.OUT ;
  wire \U4/ctrlr<1>_MC.D1 ;
  wire \U4/ctrlr<1>_MC.D2 ;
  wire \outDATA<1>\$WA0.UIM ;
  wire \U4/ctrlr<1>_MC.D2_PT_0 ;
  wire \outDATA<1>\$WA1.UIM ;
  wire \U4/ctrlr<1>_MC.D2_PT_1 ;
  wire \outDATA<1>\$WA2.UIM ;
  wire \U4/ctrlr<1>_MC.D2_PT_2 ;
  wire \outDATA<1>\$WA3.UIM ;
  wire \U4/ctrlr<1>_MC.D2_PT_3 ;
  wire \outDATA<1>\$WA5.UIM ;
  wire \U4/ctrlr<1>_MC.D2_PT_4 ;
  wire \U4/ctrlr<1>_MC.D2_PT_5 ;
  wire \outDATA<1>\$WA6.UIM ;
  wire \U4/ctrlr<1>_MC.D2_PT_6 ;
  wire \U4/ctrlr<1>_MC.D2_PT_7 ;
  wire \Home05ctrl_MC.Q_tsimrenamed_net_ ;
  wire \Home05ctrl_MC.D ;
  wire \Home05ctrl_MC.D1 ;
  wire \Home05ctrl_MC.D2 ;
  wire \Home133ctrl_MC.Q_tsimrenamed_net_ ;
  wire \Home133ctrl_MC.D ;
  wire \Home133ctrl_MC.D1 ;
  wire \Home133ctrl_MC.D2 ;
  wire \U4/ctrlr<4>_MC.D ;
  wire \U4/ctrlr<4>_MC.BUFOE.OUT ;
  wire \U4/ctrlr<4>_MC.D1 ;
  wire \U4/ctrlr<4>_MC.D2 ;
  wire \outDATA<4>\$WA0.UIM ;
  wire \U4/ctrlr<4>_MC.D2_PT_0 ;
  wire \outDATA<4>\$WA1.UIM ;
  wire \U4/ctrlr<4>_MC.D2_PT_1 ;
  wire \outDATA<4>\$WA2.UIM ;
  wire \U4/ctrlr<4>_MC.D2_PT_2 ;
  wire \outDATA<4>\$WA3.UIM ;
  wire \U4/ctrlr<4>_MC.D2_PT_3 ;
  wire \outDATA<4>\$WA5.UIM ;
  wire \U4/ctrlr<4>_MC.D2_PT_4 ;
  wire \outDATA<4>\$WA4.UIM ;
  wire \U4/ctrlr<4>_MC.D2_PT_5 ;
  wire \outDATA<4>\$WA6.UIM ;
  wire \U4/ctrlr<4>_MC.D2_PT_6 ;
  wire \U4/ctrlr<4>_MC.D2_PT_7 ;
  wire \U4/ctrlr<5>_MC.D ;
  wire \U4/ctrlr<5>_MC.BUFOE.OUT ;
  wire \U4/ctrlr<5>_MC.D1 ;
  wire \U4/ctrlr<5>_MC.D2 ;
  wire \outDATA<5>\$WA0.UIM ;
  wire \U4/ctrlr<5>_MC.D2_PT_0 ;
  wire \outDATA<5>\$WA1.UIM ;
  wire \U4/ctrlr<5>_MC.D2_PT_1 ;
  wire \outDATA<5>\$WA2.UIM ;
  wire \U4/ctrlr<5>_MC.D2_PT_2 ;
  wire \outDATA<5>\$WA3.UIM ;
  wire \U4/ctrlr<5>_MC.D2_PT_3 ;
  wire \outDATA<5>\$WA5.UIM ;
  wire \U4/ctrlr<5>_MC.D2_PT_4 ;
  wire \outDATA<5>\$WA6.UIM ;
  wire \U4/ctrlr<5>_MC.D2_PT_5 ;
  wire \Home15ctrl_MC.Q_tsimrenamed_net_ ;
  wire \Home15ctrl_MC.D ;
  wire \Home15ctrl_MC.D1 ;
  wire \Home15ctrl_MC.D2 ;
  wire \INT_MC.Q_tsimrenamed_net_ ;
  wire \INT_MC.D ;
  wire \INT_MC.D1 ;
  wire \INT_MC.D2 ;
  wire \INT_MC.D2_PT_0 ;
  wire NET2528;
  wire \INT_MC.D2_PT_1 ;
  wire NET2482;
  wire \INT_MC.D2_PT_2 ;
  wire NET2493;
  wire \INT_MC.D2_PT_3 ;
  wire NET2575;
  wire \INT_MC.D2_PT_4 ;
  wire NET2501;
  wire \INT_MC.D2_PT_5 ;
  wire NET2512;
  wire \INT_MC.D2_PT_6 ;
  wire \TP12_MC.UIM ;
  wire \INT_MC.D2_PT_7 ;
  wire \U3/DCORIE<0>_MC.Q ;
  wire \U3/DCORIE<0>_MC.D ;
  wire \U3/DCORIE<0>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ;
  wire \U3/DCORIE<0>_MC.D1 ;
  wire \U3/DCORIE<0>_MC.D2 ;
  wire DCORIEw;
  wire \U3/DCORIE<0>_MC.D2_PT_0 ;
  wire \U3/DCORIE<0>_MC.D2_PT_1 ;
  wire \DCORIEw_MC.Q ;
  wire \DCORIEw_MC.D ;
  wire \DCORIEw_MC.D1 ;
  wire \DCORIEw_MC.D2 ;
  wire \NET2528_MC.Q ;
  wire \NET2528_MC.D ;
  wire \NET2528_MC.REG_tsimcreated_inv_Mclk_II/FCLK ;
  wire \NET2528_MC.D1 ;
  wire \NET2528_MC.D2 ;
  wire DCORIFGw;
  wire \NET2528_MC.D2_PT_0 ;
  wire \NET2528_MC.D2_PT_1 ;
  wire \DCORIFGw_MC.Q ;
  wire \DCORIFGw_MC.D ;
  wire \DCORIFGw_MC.D1 ;
  wire \DCORIFGw_MC.D2 ;
  wire \U3/DCORIE<1>_MC.Q ;
  wire \U3/DCORIE<1>_MC.D ;
  wire \U3/DCORIE<1>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ;
  wire \U3/DCORIE<1>_MC.D1 ;
  wire \U3/DCORIE<1>_MC.D2 ;
  wire \U3/DCORIE<1>_MC.D2_PT_0 ;
  wire \U3/DCORIE<1>_MC.D2_PT_1 ;
  wire \NET2482_MC.Q ;
  wire \NET2482_MC.D ;
  wire NET2482_MC_tsimcreated_xor_;
  wire \NET2482_MC.REG_tsimcreated_inv_Mclk_II/FCLK ;
  wire \NET2482_MC.D1 ;
  wire \NET2482_MC.D2 ;
  wire \NET2482_MC.D2_PT_0 ;
  wire DCORENCCTLw;
  wire \NET2482_MC.D2_PT_1 ;
  wire \U1/U4/RF0r ;
  wire \U1/U4/E0r ;
  wire \U1/U4/HE0statelastr ;
  wire \NET2482_MC.D2_PT_2 ;
  wire \NET2482_MC.D2_PT_3 ;
  wire \DCORENCCTLw_MC.Q ;
  wire \DCORENCCTLw_MC.D ;
  wire \DCORENCCTLw_MC.D1 ;
  wire \DCORENCCTLw_MC.D2 ;
  wire \U1/U4/RF0r_MC.Q ;
  wire \U1/U4/RF0r_MC.D ;
  wire \U1/U4/RF0r_MC.REG_tsimcreated_inv_Mclk_II/FCLK ;
  wire \U1/U4/RF0r_MC.D1 ;
  wire \U1/U4/RF0r_MC.D2 ;
  wire \U1/U4/RF0r_MC.D2_PT_0 ;
  wire \U1/U4/RF0r_MC.D2_PT_1 ;
  wire \U1/U4/E0r_MC.Q ;
  wire \U1/U4/E0r_MC.D ;
  wire \U1/U4/E0r_MC.REG_tsimcreated_inv_Mclk_II/FCLK ;
  wire \U1/U4/E0r_MC.D1 ;
  wire \U1/U4/E0r_MC.D2 ;
  wire \U1/U4/E0r_MC.D2_PT_0 ;
  wire \U1/U4/E0r_MC.D2_PT_1 ;
  wire \U1/U4/HE0statelastr_MC.Q ;
  wire \U1/U4/HE0statelastr_MC.D ;
  wire \U1/U4/HE0statelastr_MC.REG_tsimcreated_inv_Mclk_II/FCLK ;
  wire \U1/U4/HE0statelastr_MC.D1 ;
  wire \U1/U4/HE0statelastr_MC.D2 ;
  wire \U3/DCORIE<2>_MC.Q ;
  wire \U3/DCORIE<2>_MC.D ;
  wire \U3/DCORIE<2>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ;
  wire \U3/DCORIE<2>_MC.D1 ;
  wire \U3/DCORIE<2>_MC.D2 ;
  wire \U3/DCORIE<2>_MC.D2_PT_0 ;
  wire \U3/DCORIE<2>_MC.D2_PT_1 ;
  wire \NET2493_MC.Q ;
  wire \NET2493_MC.D ;
  wire NET2493_MC_tsimcreated_xor_;
  wire \NET2493_MC.REG_tsimcreated_inv_Mclk_II/FCLK ;
  wire \NET2493_MC.D1 ;
  wire \NET2493_MC.D2 ;
  wire \NET2493_MC.D2_PT_0 ;
  wire \NET2493_MC.D2_PT_1 ;
  wire \U1/U4/RF1r ;
  wire \U1/U4/E1r ;
  wire \U1/U4/HE1statelastr ;
  wire \NET2493_MC.D2_PT_2 ;
  wire \NET2493_MC.D2_PT_3 ;
  wire \U1/U4/RF1r_MC.Q ;
  wire \U1/U4/RF1r_MC.D ;
  wire \U1/U4/RF1r_MC.REG_tsimcreated_inv_Mclk_II/FCLK ;
  wire \U1/U4/RF1r_MC.D1 ;
  wire \U1/U4/RF1r_MC.D2 ;
  wire \U1/U4/RF1r_MC.D2_PT_0 ;
  wire \U1/U4/RF1r_MC.D2_PT_1 ;
  wire \U1/U4/E1r_MC.Q ;
  wire \U1/U4/E1r_MC.D ;
  wire \U1/U4/E1r_MC.REG_tsimcreated_inv_Mclk_II/FCLK ;
  wire \U1/U4/E1r_MC.D1 ;
  wire \U1/U4/E1r_MC.D2 ;
  wire \U1/U4/E1r_MC.D2_PT_0 ;
  wire \U1/U4/E1r_MC.D2_PT_1 ;
  wire \U1/U4/HE1statelastr_MC.Q ;
  wire \U1/U4/HE1statelastr_MC.D ;
  wire \U1/U4/HE1statelastr_MC.REG_tsimcreated_inv_Mclk_II/FCLK ;
  wire \U1/U4/HE1statelastr_MC.D1 ;
  wire \U1/U4/HE1statelastr_MC.D2 ;
  wire \U3/DCORIE<3>_MC.Q ;
  wire \U3/DCORIE<3>_MC.D ;
  wire \U3/DCORIE<3>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ;
  wire \U3/DCORIE<3>_MC.D1 ;
  wire \U3/DCORIE<3>_MC.D2 ;
  wire \U3/DCORIE<3>_MC.D2_PT_0 ;
  wire \U3/DCORIE<3>_MC.D2_PT_1 ;
  wire \NET2575_MC.Q ;
  wire \NET2575_MC.D ;
  wire \NET2575_MC.REG_tsimcreated_inv_Mclk_II/FCLK ;
  wire \NET2575_MC.D1 ;
  wire \NET2575_MC.D2 ;
  wire \NET2575_MC.D2_PT_0 ;
  wire \NET2575_MC.D2_PT_1 ;
  wire \NET2575_MC.D2_PT_2 ;
  wire \NET2575_MC.D2_PT_3 ;
  wire \NET2575_MC.D2_PT_4 ;
  wire \NET2575_MC.D2_PT_5 ;
  wire \U3/DCORIE<4>_MC.Q ;
  wire \U3/DCORIE<4>_MC.D ;
  wire \U3/DCORIE<4>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ;
  wire \U3/DCORIE<4>_MC.D1 ;
  wire \U3/DCORIE<4>_MC.D2 ;
  wire \U3/DCORIE<4>_MC.D2_PT_0 ;
  wire \U3/DCORIE<4>_MC.D2_PT_1 ;
  wire \NET2501_MC.Q ;
  wire \NET2501_MC.D ;
  wire NET2501_MC_tsimcreated_xor_;
  wire \NET2501_MC.REG_tsimcreated_inv_Mclk_II/FCLK ;
  wire \NET2501_MC.D1 ;
  wire \NET2501_MC.D2 ;
  wire N_PZ_965;
  wire \NET2501_MC.D2_PT_0 ;
  wire \NET2501_MC.D2_PT_1 ;
  wire \N_PZ_965_MC.Q ;
  wire \N_PZ_965_MC.D ;
  wire \N_PZ_965_MC.D1 ;
  wire \N_PZ_965_MC.D2 ;
  wire \U1/U4/LatchEdge0r ;
  wire \N_PZ_965_MC.D2_PT_0 ;
  wire \N_PZ_965_MC.D2_PT_1 ;
  wire \U1/U4/LatchEdge0r_MC.Q ;
  wire \U1/U4/LatchEdge0r_MC.D ;
  wire \U1/U4/LatchEdge0r_MC.REG_tsimcreated_inv_Mclk_II/FCLK ;
  wire \U1/U4/LatchEdge0r_MC.D1 ;
  wire \U1/U4/LatchEdge0r_MC.D2 ;
  wire \U1/U4/LatchEdge0r_MC.D2_PT_0 ;
  wire \U1/U4/LatchEdge0r_MC.D2_PT_1 ;
  wire \outDATA<6>\$WA1.UIM_MC.Q ;
  wire \outDATA<6>\$WA1.UIM_MC.D ;
  wire \outDATA<6>\$WA1.UIM_MC.D1 ;
  wire \outDATA<6>\$WA1.UIM_MC.D2 ;
  wire \U3/DCORIE<5>_MC.Q ;
  wire \U3/DCORIE<5>_MC.D ;
  wire \U3/DCORIE<5>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ;
  wire \U3/DCORIE<5>_MC.D1 ;
  wire \U3/DCORIE<5>_MC.D2 ;
  wire \U3/DCORIE<5>_MC.D2_PT_0 ;
  wire \U3/DCORIE<5>_MC.D2_PT_1 ;
  wire \NET2512_MC.Q ;
  wire \NET2512_MC.D ;
  wire NET2512_MC_tsimcreated_xor_;
  wire \NET2512_MC.REG_tsimcreated_inv_Mclk_II/FCLK ;
  wire \NET2512_MC.D1 ;
  wire \NET2512_MC.D2 ;
  wire \NET2512_MC.D2_PT_0 ;
  wire \U1/U4/LatchEdge1r ;
  wire \NET2512_MC.D2_PT_1 ;
  wire \NET2512_MC.D2_PT_2 ;
  wire \U1/U4/LatchEdge1r_MC.Q ;
  wire \U1/U4/LatchEdge1r_MC.D ;
  wire \U1/U4/LatchEdge1r_MC.REG_tsimcreated_inv_Mclk_II/FCLK ;
  wire \U1/U4/LatchEdge1r_MC.D1 ;
  wire \U1/U4/LatchEdge1r_MC.D2 ;
  wire \U1/U4/LatchEdge1r_MC.D2_PT_0 ;
  wire \U1/U4/LatchEdge1r_MC.D2_PT_1 ;
  wire \U3/DCORIE<6>_MC.Q ;
  wire \U3/DCORIE<6>_MC.D ;
  wire \U3/DCORIE<6>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ;
  wire \U3/DCORIE<6>_MC.D1 ;
  wire \U3/DCORIE<6>_MC.D2 ;
  wire \U3/DCORIE<6>_MC.D2_PT_0 ;
  wire \U3/DCORIE<6>_MC.D2_PT_1 ;
  wire \U3/DCORIE<7>_MC.Q ;
  wire \U3/DCORIE<7>_MC.D ;
  wire \U3/DCORIE<7>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ;
  wire \U3/DCORIE<7>_MC.D1 ;
  wire \U3/DCORIE<7>_MC.D2 ;
  wire \U3/DCORIE<7>_MC.D2_PT_0 ;
  wire \U3/DCORIE<7>_MC.D2_PT_1 ;
  wire \TP12_MC.Q_tsimrenamed_net_ ;
  wire \TP12_MC.D ;
  wire \TP12_MC.D1 ;
  wire \TP12_MC.D2 ;
  wire \U11_U3_counterr<3>_MC.Q ;
  wire \U11_U3_counterr<3>_MC.D ;
  wire \U11_U3_counterr<3>_MC_tsimcreated_xor_ ;
  wire \U11_U3_counterr<3>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ;
  wire \U11_U3_counterr<3>_MC.D1 ;
  wire \U11_U3_counterr<3>_MC.D2 ;
  wire \U11_U3_counterr<3>_MC.D2_PT_0 ;
  wire N_PZ_1071;
  wire \U11_U3_counterr<3>_MC.D2_PT_1 ;
  wire U11_Incdetect;
  wire \U11_U3_counterr<3>_MC.D2_PT_2 ;
  wire \U11_U3_counterr<3>_MC.D2_PT_3 ;
  wire \U11_U3_counterr<3>_MC.D2_PT_4 ;
  wire U11_SCLdetect;
  wire \U11_U3_counterr<3>_MC.D2_PT_5 ;
  wire \U11_U3_counterr<3>_MC.D2_PT_6 ;
  wire \N_PZ_1071_MC.Q ;
  wire \N_PZ_1071_MC.D ;
  wire \N_PZ_1071_MC.D1 ;
  wire \N_PZ_1071_MC.D2 ;
  wire \N_PZ_1071_MC.D2_PT_0 ;
  wire \N_PZ_1071_MC.D2_PT_1 ;
  wire U11_ResetDetect;
  wire \N_PZ_1071_MC.D2_PT_2 ;
  wire \U11_Incdetect_MC.Q ;
  wire \U11_Incdetect_MC.D ;
  wire \U11_Incdetect_MC.REG_tsimcreated_inv_Mclk_II/FCLK ;
  wire \U11_Incdetect_MC.D1 ;
  wire \U11_Incdetect_MC.D2 ;
  wire \U11_ResetDetect_MC.Q ;
  wire \U11_ResetDetect_MC.D ;
  wire \U11_ResetDetect_MC.REG_tsimcreated_inv_Mclk_II/FCLK ;
  wire \U11_ResetDetect_MC.D1 ;
  wire \U11_ResetDetect_MC.D2 ;
  wire \U11_SCLdetect_MC.Q ;
  wire \U11_SCLdetect_MC.D ;
  wire \U11_SCLdetect_MC.REG_tsimcreated_inv_Mclk_II/FCLK ;
  wire \U11_SCLdetect_MC.D1 ;
  wire \U11_SCLdetect_MC.D2 ;
  wire \U11_U2/Line_last_MC.D ;
  wire \U11_U2/Line_last_MC.BUFOE.OUT ;
  wire \FOOBAR4__ctinst/0 ;
  wire \U11_U2/Line_last_MC.D1 ;
  wire \U11_U2/Line_last_MC.D2 ;
  wire \outDATA<7>\$WA4.UIM_MC.Q ;
  wire \outDATA<7>\$WA4.UIM_MC.D ;
  wire \outDATA<7>\$WA4.UIM_MC.D1 ;
  wire \outDATA<7>\$WA4.UIM_MC.D2 ;
  wire \U11_U3_counterr<0>_MC.Q ;
  wire \U11_U3_counterr<0>_MC.D ;
  wire \U11_U3_counterr<0>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ;
  wire \U11_U3_counterr<0>_MC.D1 ;
  wire \U11_U3_counterr<0>_MC.D2 ;
  wire \U11_U3_counterr<0>_MC.D2_PT_0 ;
  wire \U11_U3_counterr<0>_MC.D2_PT_1 ;
  wire \U11_U3_counterr<0>_MC.D2_PT_2 ;
  wire \U11_U3_counterr<0>_MC.D2_PT_3 ;
  wire \U11_U3_counterr<0>_MC.D2_PT_4 ;
  wire \U11_U3_counterr<0>_MC.D2_PT_5 ;
  wire \U11_U3_counterr<1>_MC.Q ;
  wire \U11_U3_counterr<1>_MC.D ;
  wire \U11_U3_counterr<1>_MC_tsimcreated_xor_ ;
  wire \U11_U3_counterr<1>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ;
  wire \U11_U3_counterr<1>_MC.D1 ;
  wire \U11_U3_counterr<1>_MC.D2 ;
  wire \U11_U3_counterr<1>_MC.D2_PT_0 ;
  wire \U11_U3_counterr<1>_MC.D2_PT_1 ;
  wire \U11_U3_counterr<1>_MC.D2_PT_2 ;
  wire \U11_U3_counterr<2>_MC.Q ;
  wire \U11_U3_counterr<2>_MC.D ;
  wire \U11_U3_counterr<2>_MC_tsimcreated_xor_ ;
  wire \U11_U3_counterr<2>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ;
  wire \U11_U3_counterr<2>_MC.D1 ;
  wire \U11_U3_counterr<2>_MC.D2 ;
  wire \U11_U3_counterr<2>_MC.D2_PT_0 ;
  wire \U11_U3_counterr<2>_MC.D2_PT_1 ;
  wire \U11_U3_counterr<2>_MC.D2_PT_2 ;
  wire \U11_U3_counterr<4>_MC.Q ;
  wire \U11_U3_counterr<4>_MC.D ;
  wire \U11_U3_counterr<4>_MC_tsimcreated_xor_ ;
  wire \U11_U3_counterr<4>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ;
  wire \U11_U3_counterr<4>_MC.D1 ;
  wire \U11_U3_counterr<4>_MC.D2 ;
  wire \U11_U3_counterr<4>_MC.D2_PT_0 ;
  wire N_PZ_1145;
  wire N_PZ_1125;
  wire \U11_U3_counterr<4>_MC.D2_PT_1 ;
  wire \U11_U3_counterr<4>_MC.D2_PT_2 ;
  wire \N_PZ_1145_MC.Q ;
  wire \N_PZ_1145_MC.D ;
  wire \N_PZ_1145_MC.D1 ;
  wire \N_PZ_1145_MC.D2 ;
  wire \N_PZ_1145_MC.D2_PT_0 ;
  wire \N_PZ_1145_MC.D2_PT_1 ;
  wire \N_PZ_1145_MC.D2_PT_2 ;
  wire \N_PZ_1145_MC.D2_PT_3 ;
  wire \N_PZ_1125_MC.Q ;
  wire \N_PZ_1125_MC.D ;
  wire \N_PZ_1125_MC.D1 ;
  wire \N_PZ_1125_MC.D2 ;
  wire \N_PZ_1125_MC.D2_PT_0 ;
  wire \N_PZ_1125_MC.D2_PT_1 ;
  wire \U11_U3_counterr<5>_MC.Q ;
  wire \U11_U3_counterr<5>_MC.D ;
  wire \U11_U3_counterr<5>_MC_tsimcreated_xor_ ;
  wire \U11_U3_counterr<5>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ;
  wire \U11_U3_counterr<5>_MC.D1 ;
  wire \U11_U3_counterr<5>_MC.D2 ;
  wire \U11_U3_counterr<5>_MC.D2_PT_0 ;
  wire \U11_U3_counterr<5>_MC.D2_PT_1 ;
  wire \U11_U3_counterr<5>_MC.D2_PT_2 ;
  wire \U11_U3_counterr<5>_MC.D2_PT_3 ;
  wire \LED1_MC.Q_tsimrenamed_net_ ;
  wire \LED1_MC.D ;
  wire \LED1_MC.D1 ;
  wire \LED1_MC.D2 ;
  wire \U9/MISCr<0>_MC.Q ;
  wire \U9/MISCr<0>_MC_tsimcreated_prld_ ;
  wire \U9/MISCr<0>_MC.D ;
  wire \U9/MISCr<0>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ;
  wire \FOOBAR1__ctinst/4 ;
  wire \U9/MISCr<0>_MC.D1 ;
  wire \U9/MISCr<0>_MC.D2 ;
  wire \LED2_MC.Q_tsimrenamed_net_ ;
  wire \LED2_MC.D ;
  wire \LED2_MC.D1 ;
  wire \LED2_MC.D2 ;
  wire \U9/MISCr<1>_MC.Q ;
  wire \U9/MISCr<1>_MC_tsimcreated_prld_ ;
  wire \U9/MISCr<1>_MC.D ;
  wire \U9/MISCr<1>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ;
  wire \U9/MISCr<1>_MC.D1 ;
  wire \U9/MISCr<1>_MC.D2 ;
  wire \LED3_MC.Q_tsimrenamed_net_ ;
  wire \LED3_MC.D ;
  wire \LED3_MC.D1 ;
  wire \LED3_MC.D2 ;
  wire \U9/MISCr<2>_MC.Q ;
  wire \U9/MISCr<2>_MC_tsimcreated_prld_ ;
  wire \U9/MISCr<2>_MC.D ;
  wire \U9/MISCr<2>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ;
  wire \U9/MISCr<2>_MC.D1 ;
  wire \U9/MISCr<2>_MC.D2 ;
  wire \LED4_MC.Q_tsimrenamed_net_ ;
  wire \LED4_MC.D ;
  wire \LED4_MC.D1 ;
  wire \LED4_MC.D2 ;
  wire \U9/MISCr<3>_MC.Q ;
  wire \U9/MISCr<3>_MC_tsimcreated_prld_ ;
  wire \U9/MISCr<3>_MC.D ;
  wire \U9/MISCr<3>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ;
  wire \U9/MISCr<3>_MC.D1 ;
  wire \U9/MISCr<3>_MC.D2 ;
  wire \LED5_MC.Q_tsimrenamed_net_ ;
  wire \LED5_MC.D ;
  wire \LED5_MC.D1 ;
  wire \LED5_MC.D2 ;
  wire \U9/MISCr<4>_MC.Q ;
  wire \U9/MISCr<4>_MC_tsimcreated_prld_ ;
  wire \U9/MISCr<4>_MC.D ;
  wire \U9/MISCr<4>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ;
  wire \U9/MISCr<4>_MC.D1 ;
  wire \U9/MISCr<4>_MC.D2 ;
  wire \MHSI_MC.Q_tsimrenamed_net_ ;
  wire \MHSI_MC.D ;
  wire \MHSI_MC.D1 ;
  wire \MHSI_MC.D2 ;
  wire \MTRpwr_MC.Q_tsimrenamed_net_ ;
  wire MTRpwr_MC_tsimcreated_prld_;
  wire \MTRpwr_MC.D ;
  wire \MTRpwr_MC.REG_tsimcreated_inv_Mclk_II/FCLK ;
  wire \FOOBAR18__ctinst/4 ;
  wire \MTRpwr_MC.D1 ;
  wire \MTRpwr_MC.D2 ;
  wire \MTRpwrn_MC.Q_tsimrenamed_net_ ;
  wire \FOOBAR2__ctinst/7 ;
  wire MTRpwrn_MC_tsimcreated_prld_;
  wire \MTRpwrn_MC.D ;
  wire \MTRpwrn_MC.REG_tsimcreated_inv_Mclk_II/FCLK ;
  wire \FOOBAR7__ctinst/4 ;
  wire \MTRpwrn_MC.D1 ;
  wire \MTRpwrn_MC.D2 ;
  wire \MTXI_MC.Q_tsimrenamed_net_ ;
  wire \MTXI_MC.D ;
  wire \MTXI_MC.D1 ;
  wire \MTXI_MC.D2 ;
  wire \PAH0_MC.Q_tsimrenamed_net_ ;
  wire \PAH0_MC.UIM ;
  wire \PAH0_MC.D ;
  wire \PAH0_MC.D1 ;
  wire \PAH0_MC.D2 ;
  wire NET3248;
  wire \NET3248_MC.Q ;
  wire \NET3248_MC.D ;
  wire \NET3248_MC.REG_tsimcreated_inv_Mclk_II/FCLK ;
  wire \NET3248_MC.D1 ;
  wire \NET3248_MC.D2 ;
  wire \NET3248_MC.D2_PT_0 ;
  wire \NET3248_MC.D2_PT_1 ;
  wire \NET3248_MC.D2_PT_2 ;
  wire \PAH1_MC.Q_tsimrenamed_net_ ;
  wire \PAH1_MC.UIM ;
  wire \PAH1_MC.D ;
  wire \PAH1_MC.D1 ;
  wire \PAH1_MC.D2 ;
  wire NET3253;
  wire \NET3253_MC.Q ;
  wire \NET3253_MC.D ;
  wire \NET3253_MC.REG_tsimcreated_inv_Mclk_II/FCLK ;
  wire \NET3253_MC.D1 ;
  wire \NET3253_MC.D2 ;
  wire \NET3253_MC.D2_PT_0 ;
  wire \NET3253_MC.D2_PT_1 ;
  wire \NET3253_MC.D2_PT_2 ;
  wire \PAL0_MC.Q_tsimrenamed_net_ ;
  wire \PAL0_MC.D ;
  wire \PAL0_MC.D1 ;
  wire \PAL0_MC.D2 ;
  wire \PAL0_MC.D2_PT_0 ;
  wire \PAL0_MC.D2_PT_1 ;
  wire \PAL1_MC.Q_tsimrenamed_net_ ;
  wire \PAL1_MC.D ;
  wire \PAL1_MC.D1 ;
  wire \PAL1_MC.D2 ;
  wire \PAL1_MC.D2_PT_0 ;
  wire \PAL1_MC.D2_PT_1 ;
  wire \PBH0_MC.Q_tsimrenamed_net_ ;
  wire \PBH0_MC.UIM ;
  wire \PBH0_MC.D ;
  wire \PBH0_MC.D1 ;
  wire \PBH0_MC.D2 ;
  wire \PBH1_MC.Q_tsimrenamed_net_ ;
  wire \PBH1_MC.UIM ;
  wire \PBH1_MC.D ;
  wire \PBH1_MC.D1 ;
  wire \PBH1_MC.D2 ;
  wire \PBL0_MC.Q_tsimrenamed_net_ ;
  wire \PBL0_MC.D ;
  wire \PBL0_MC.D1 ;
  wire \PBL0_MC.D2 ;
  wire \PBL0_MC.D2_PT_0 ;
  wire \PBL0_MC.D2_PT_1 ;
  wire \PBL1_MC.Q_tsimrenamed_net_ ;
  wire \PBL1_MC.D ;
  wire \PBL1_MC.D1 ;
  wire \PBL1_MC.D2 ;
  wire \PBL1_MC.D2_PT_0 ;
  wire \PBL1_MC.D2_PT_1 ;
  wire \PresEn_MC.Q_tsimrenamed_net_ ;
  wire PresEn_MC_tsimcreated_prld_;
  wire \PresEn_MC.D ;
  wire \PresEn_MC.REG_tsimcreated_inv_Mclk_II/FCLK ;
  wire \FOOBAR19__ctinst/4 ;
  wire \PresEn_MC.D1 ;
  wire \PresEn_MC.D2 ;
  wire \DCORSENSORw_MC.Q ;
  wire DCORSENSORw;
  wire \DCORSENSORw_MC.D ;
  wire \DCORSENSORw_MC.D1 ;
  wire \DCORSENSORw_MC.D2 ;
  wire \PresSlct_MC.Q_tsimrenamed_net_ ;
  wire PresSlct_MC_tsimcreated_prld_;
  wire \PresSlct_MC.D ;
  wire \PresSlct_MC.REG_tsimcreated_inv_Mclk_II/FCLK ;
  wire \PresSlct_MC.D1 ;
  wire \PresSlct_MC.D2 ;
  wire \SCLout_MC.Q_tsimrenamed_net_ ;
  wire \SCLout_MC.D ;
  wire \SCLout_MC.D1 ;
  wire \SCLout_MC.D2 ;
  wire \TP10_MC.Q_tsimrenamed_net_ ;
  wire \TP10_MC.D ;
  wire \TP10_MC.D1 ;
  wire \TP10_MC.D2 ;
  wire \TP11_MC.Q_tsimrenamed_net_ ;
  wire \TP11_MC.D ;
  wire \TP11_MC.D1 ;
  wire \TP11_MC.D2 ;
  wire \TmpEn_MC.Q_tsimrenamed_net_ ;
  wire TmpEn_MC_tsimcreated_prld_;
  wire \TmpEn_MC.D ;
  wire \TmpEn_MC.REG_tsimcreated_inv_Mclk_II/FCLK ;
  wire \TmpEn_MC.D1 ;
  wire \TmpEn_MC.D2 ;
  wire \TmpSlct_MC.Q_tsimrenamed_net_ ;
  wire TmpSlct_MC_tsimcreated_prld_;
  wire \TmpSlct_MC.D ;
  wire \TmpSlct_MC.REG_tsimcreated_inv_Mclk_II/FCLK ;
  wire \TmpSlct_MC.D1 ;
  wire \TmpSlct_MC.D2 ;
  wire \U4/orFLGs_MC.Q ;
  wire \U4/orFLGs ;
  wire \U4/orFLGs_MC.D ;
  wire \U4/orFLGs_MC.D1 ;
  wire \U4/orFLGs_MC.D2 ;
  wire \DCORI2CCNTr_MC.Q ;
  wire \DCORI2CCNTr_MC.D ;
  wire \DCORI2CCNTr_MC.D1 ;
  wire \DCORI2CCNTr_MC.D2 ;
  wire \outDATA<0>\$WA0.UIM_MC.Q ;
  wire \outDATA<0>\$WA0.UIM_MC.D ;
  wire \outDATA<0>\$WA0.UIM_MC.D1 ;
  wire \outDATA<0>\$WA0.UIM_MC.D2 ;
  wire \DCORCONFIGr_MC.Q ;
  wire \DCORCONFIGr_MC.D ;
  wire \DCORCONFIGr_MC.D1 ;
  wire \DCORCONFIGr_MC.D2 ;
  wire \outDATA<0>\$WA1.UIM_MC.Q ;
  wire \outDATA<0>\$WA1.UIM_MC.D ;
  wire \outDATA<0>\$WA1.UIM_MC.D1 ;
  wire \outDATA<0>\$WA1.UIM_MC.D2 ;
  wire \DCORLIMITSr_MC.Q ;
  wire \DCORLIMITSr_MC.D ;
  wire \DCORLIMITSr_MC.D1 ;
  wire \DCORLIMITSr_MC.D2 ;
  wire \outDATA<0>\$WA2.UIM_MC.Q ;
  wire \outDATA<0>\$WA2.UIM_MC.D ;
  wire \outDATA<0>\$WA2.UIM_MC.D1 ;
  wire \outDATA<0>\$WA2.UIM_MC.D2 ;
  wire \DCORENCPWRr_MC.Q ;
  wire \DCORENCPWRr_MC.D ;
  wire \DCORENCPWRr_MC.D1 ;
  wire \DCORENCPWRr_MC.D2 ;
  wire \outDATA<0>\$WA3.UIM_MC.Q ;
  wire \outDATA<0>\$WA3.UIM_MC.D ;
  wire \outDATA<0>\$WA3.UIM_MC.D1 ;
  wire \outDATA<0>\$WA3.UIM_MC.D2 ;
  wire \outDATA<0>\$WA3.UIM_MC.D2_PT_0 ;
  wire \outDATA<0>\$WA3.UIM_MC.D2_PT_1 ;
  wire \DCORIFGr_MC.Q ;
  wire \DCORIFGr_MC.D ;
  wire \DCORIFGr_MC.D1 ;
  wire \DCORIFGr_MC.D2 ;
  wire \outDATA<0>\$WA4.UIM_MC.Q ;
  wire \outDATA<0>\$WA4.UIM_MC.D ;
  wire \outDATA<0>\$WA4.UIM_MC.D1 ;
  wire \outDATA<0>\$WA4.UIM_MC.D2 ;
  wire \DCOR0THRESLOWr_MC.Q ;
  wire \DCOR0THRESLOWr_MC.D ;
  wire \DCOR0THRESLOWr_MC.D1 ;
  wire \DCOR0THRESLOWr_MC.D2 ;
  wire \outDATA<0>\$WA6.UIM_MC.Q ;
  wire \outDATA<0>\$WA6.UIM_MC.D ;
  wire \outDATA<0>\$WA6.UIM_MC.D1 ;
  wire \outDATA<0>\$WA6.UIM_MC.D2 ;
  wire \outDATA<0>\$WA6.UIM_MC.D2_PT_0 ;
  wire DCOR0THRESHIGHr;
  wire \outDATA<0>\$WA6.UIM_MC.D2_PT_1 ;
  wire DCOR1THRESLOWr;
  wire \outDATA<0>\$WA6.UIM_MC.D2_PT_2 ;
  wire \outDATA<0>\$WA6.UIM_MC.D2_PT_3 ;
  wire \U1/U4/Latch0r<0>_MC.Q ;
  wire \U1/U4/Latch0r<0>_MC.D ;
  wire \U1/U4/Latch0r<0>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ;
  wire \U1/U4/Latch0r<0>_MC.D1 ;
  wire \U1/U4/Latch0r<0>_MC.D2 ;
  wire \U1/U4/Latch0r<0>_MC.D2_PT_0 ;
  wire \U1/U4/Latch0r<0>_MC.D2_PT_1 ;
  wire \U1/Channel0<0>_MC.Q ;
  wire \U1/Channel0<0>_MC.D ;
  wire \U1/Channel0<0>_MC_tsimcreated_xor_ ;
  wire \U1/Channel0<0>_MC.D1 ;
  wire \U1/Channel0<0>_MC.D2 ;
  wire N_PZ_931;
  wire \U1/Channel0<0>_MC.D2_PT_0 ;
  wire \U1/Zero0 ;
  wire \U1/U1/CurrState_Sreg0_FFD1 ;
  wire \U1/U1/CurrState_Sreg0_FFD3 ;
  wire \U1/U1/CurrState_Sreg0_FFD2 ;
  wire \U1/U1/CurrState_Sreg0_FFD4 ;
  wire \U1/Channel0<0>_MC.D2_PT_1 ;
  wire \U1/Channel0<0>_MC.D2_PT_2 ;
  wire \U1/Zero0_MC.Q ;
  wire \U1/Zero0_MC.D ;
  wire \U1/Zero0_MC.REG_tsimcreated_inv_Mclk_II/FCLK ;
  wire \U1/Zero0_MC.D1 ;
  wire \U1/Zero0_MC.D2 ;
  wire \U1/Zero0_MC.D2_PT_0 ;
  wire N_PZ_964;
  wire \U1/Zero0_MC.D2_PT_1 ;
  wire \U1/Zero0_MC.D2_PT_2 ;
  wire \U1/Zero0_MC.D2_PT_3 ;
  wire \N_PZ_964_MC.Q ;
  wire \N_PZ_964_MC.D ;
  wire \N_PZ_964_MC.D1 ;
  wire \N_PZ_964_MC.D2 ;
  wire \N_PZ_964_MC.D2_PT_0 ;
  wire \N_PZ_964_MC.D2_PT_1 ;
  wire \N_PZ_931_MC.Q ;
  wire \N_PZ_931_MC.D ;
  wire \N_PZ_931_MC.D1 ;
  wire \N_PZ_931_MC.D2 ;
  wire \U1/U1/CurrState_Sreg0_FFD1_MC.Q ;
  wire \U1/U1/CurrState_Sreg0_FFD1_MC.D ;
  wire \U1/U1/CurrState_Sreg0_FFD1_MC.D1 ;
  wire \U1/U1/CurrState_Sreg0_FFD1_MC.D2 ;
  wire \U1/U1/CurrState_Sreg0_FFD1_MC.D2_PT_0 ;
  wire \U1/U1/CurrState_Sreg0_FFD1_MC.D2_PT_1 ;
  wire \U1/U1/CurrState_Sreg0_FFD1_MC.D2_PT_2 ;
  wire \U1/U1/CurrState_Sreg0_FFD3_MC.Q ;
  wire \U1/U1/CurrState_Sreg0_FFD3_MC.D ;
  wire \U1/U1/CurrState_Sreg0_FFD3_MC.D1 ;
  wire \U1/U1/CurrState_Sreg0_FFD3_MC.D2 ;
  wire \U1/U1/CurrState_Sreg0_FFD3_MC.D2_PT_0 ;
  wire \U1/U1/CurrState_Sreg0_FFD3_MC.D2_PT_1 ;
  wire \U1/U1/CurrState_Sreg0_FFD3_MC.D2_PT_2 ;
  wire \U1/U1/CurrState_Sreg0_FFD3_MC.D2_PT_3 ;
  wire \U1/U1/CurrState_Sreg0_FFD2_MC.Q ;
  wire \U1/U1/CurrState_Sreg0_FFD2_MC.D ;
  wire \U1/U1/CurrState_Sreg0_FFD2_MC.D1 ;
  wire \U1/U1/CurrState_Sreg0_FFD2_MC.D2 ;
  wire \U1/U1/CurrState_Sreg0_FFD2_MC.D2_PT_0 ;
  wire \U1/U1/CurrState_Sreg0_FFD2_MC.D2_PT_1 ;
  wire \U1/U1/CurrState_Sreg0_FFD2_MC.D2_PT_2 ;
  wire \U1/U1/CurrState_Sreg0_FFD2_MC.D2_PT_3 ;
  wire \U1/U1/CurrState_Sreg0_FFD2_MC.D2_PT_4 ;
  wire \U1/U1/CurrState_Sreg0_FFD2_MC.D2_PT_5 ;
  wire \U1/U1/CurrState_Sreg0_FFD2_MC.D2_PT_6 ;
  wire \U1/U1/CurrState_Sreg0_FFD2_MC.D2_PT_7 ;
  wire \U1/U1/CurrState_Sreg0_FFD4_MC.Q ;
  wire \U1/U1/CurrState_Sreg0_FFD4_MC.D ;
  wire \U1/U1/CurrState_Sreg0_FFD4_MC.D1 ;
  wire \U1/U1/CurrState_Sreg0_FFD4_MC.D2 ;
  wire \U1/U4/Latch0r<8>_MC.Q ;
  wire \U1/U4/Latch0r<8>_MC.D ;
  wire \U1/U4/Latch0r<8>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ;
  wire \U1/U4/Latch0r<8>_MC.D1 ;
  wire \U1/U4/Latch0r<8>_MC.D2 ;
  wire \U1/U4/Latch0r<8>_MC.D2_PT_0 ;
  wire \U1/U4/Latch0r<8>_MC.D2_PT_1 ;
  wire \U1/Channel0<8>_MC.Q ;
  wire \U1/Channel0<8>_MC.D ;
  wire \U1/Channel0<8>_MC_tsimcreated_xor_ ;
  wire \U1/Channel0<8>_MC.D1 ;
  wire \U1/Channel0<8>_MC.D2 ;
  wire \U1/Channel0<8>_MC.D2_PT_0 ;
  wire N_PZ_966;
  wire \U1/Channel0<8>_MC.D2_PT_1 ;
  wire N_PZ_969;
  wire \U1/Channel0<8>_MC.D2_PT_2 ;
  wire \U1/Channel0<8>_MC.D2_PT_3 ;
  wire \U1/Channel0<8>_MC.D2_PT_4 ;
  wire \U1/Channel0<8>_MC.D2_PT_5 ;
  wire \U1/U2/location_Maddsub__n0000__n0075<0>_MC.Q ;
  wire \U1/U2/location_Maddsub__n0000__n0075<0>_MC.D ;
  wire \U1/U2/location_Maddsub__n0000__n0075<0>_MC.D1 ;
  wire \U1/U2/location_Maddsub__n0000__n0075<0>_MC.D2 ;
  wire N_PZ_945;
  wire \U1/U2/location_Maddsub__n0000__n0075<0>_MC.D2_PT_0 ;
  wire \U1/U2/location_Maddsub__n0000__n0075<0>_MC.D2_PT_1 ;
  wire \N_PZ_945_MC.Q ;
  wire \N_PZ_945_MC.D ;
  wire \N_PZ_945_MC.D1 ;
  wire \N_PZ_945_MC.D2 ;
  wire \U1/NET3721 ;
  wire \N_PZ_945_MC.D2_PT_0 ;
  wire \N_PZ_945_MC.D2_PT_1 ;
  wire \U1/NET3721_MC.Q ;
  wire \U1/NET3721_MC.D ;
  wire \U1/NET3721_MC.REG_tsimcreated_inv_Mclk_II/FCLK ;
  wire \U1/NET3721_MC.D1 ;
  wire \U1/NET3721_MC.D2 ;
  wire \U1/NET3721_MC.D2_PT_0 ;
  wire \U1/NET3721_MC.D2_PT_1 ;
  wire \U1/Channel0<5>_MC.Q ;
  wire \U1/Channel0<5>_MC.D ;
  wire \U1/Channel0<5>_MC_tsimcreated_xor_ ;
  wire \U1/Channel0<5>_MC.D1 ;
  wire \U1/Channel0<5>_MC.D2 ;
  wire \U1/Channel0<5>_MC.D2_PT_0 ;
  wire \U1/Channel0<5>_MC.D2_PT_1 ;
  wire \U1/Channel0<5>_MC.D2_PT_2 ;
  wire \U1/U2/location_Maddsub__n0000__n0067<0>_MC.Q ;
  wire \U1/U2/location_Maddsub__n0000__n0067<0>_MC.D ;
  wire \U1/U2/location_Maddsub__n0000__n0067<0>_MC.D1 ;
  wire \U1/U2/location_Maddsub__n0000__n0067<0>_MC.D2 ;
  wire \U1/U2/location_Maddsub__n0000__n0067<0>_MC.D2_PT_0 ;
  wire \U1/U2/location_Maddsub__n0000__n0067<0>_MC.D2_PT_1 ;
  wire \U1/Channel0<1>_MC.Q ;
  wire \U1/Channel0<1>_MC.D ;
  wire \U1/Channel0<1>_MC_tsimcreated_xor_ ;
  wire \U1/Channel0<1>_MC.D1 ;
  wire \U1/Channel0<1>_MC.D2 ;
  wire \U1/Channel0<1>_MC.D2_PT_0 ;
  wire \U1/Channel0<1>_MC.D2_PT_1 ;
  wire \U1/Channel0<1>_MC.D2_PT_2 ;
  wire \N_PZ_966_MC.Q ;
  wire \N_PZ_966_MC.D ;
  wire \N_PZ_966_MC.D1 ;
  wire \N_PZ_966_MC.D2 ;
  wire \N_PZ_966_MC.D2_PT_0 ;
  wire \N_PZ_966_MC.D2_PT_1 ;
  wire \N_PZ_969_MC.Q ;
  wire \N_PZ_969_MC.D ;
  wire \N_PZ_969_MC.D1 ;
  wire \N_PZ_969_MC.D2 ;
  wire \N_PZ_969_MC.D2_PT_0 ;
  wire \N_PZ_969_MC.D2_PT_1 ;
  wire \U1/Channel0<2>_MC.Q ;
  wire \U1/Channel0<2>_MC.D ;
  wire \U1/Channel0<2>_MC_tsimcreated_xor_ ;
  wire \U1/Channel0<2>_MC.D1 ;
  wire \U1/Channel0<2>_MC.D2 ;
  wire \U1/Channel0<2>_MC.D2_PT_0 ;
  wire \U1/Channel0<2>_MC.D2_PT_1 ;
  wire \U1/Channel0<2>_MC.D2_PT_2 ;
  wire \U1/Channel0<3>_MC.Q ;
  wire \U1/Channel0<3>_MC.D ;
  wire \U1/Channel0<3>_MC_tsimcreated_xor_ ;
  wire \U1/Channel0<3>_MC.D1 ;
  wire \U1/Channel0<3>_MC.D2 ;
  wire \U1/Channel0<3>_MC.D2_PT_0 ;
  wire \U1/Channel0<3>_MC.D2_PT_1 ;
  wire \U1/Channel0<3>_MC.D2_PT_2 ;
  wire \U1/Channel0<4>_MC.Q ;
  wire \U1/Channel0<4>_MC.D ;
  wire \U1/Channel0<4>_MC_tsimcreated_xor_ ;
  wire \U1/Channel0<4>_MC.D1 ;
  wire \U1/Channel0<4>_MC.D2 ;
  wire \U1/Channel0<4>_MC.D2_PT_0 ;
  wire \U1/Channel0<4>_MC.D2_PT_1 ;
  wire \U1/Channel0<4>_MC.D2_PT_2 ;
  wire \U1/Channel0<4>_MC.D2_PT_3 ;
  wire \U1/Channel0<4>_MC.D2_PT_4 ;
  wire \U1/Channel0<4>_MC.D2_PT_5 ;
  wire \U1/Channel0<6>_MC.Q ;
  wire \U1/Channel0<6>_MC.D ;
  wire \U1/Channel0<6>_MC_tsimcreated_xor_ ;
  wire \U1/Channel0<6>_MC.D1 ;
  wire \U1/Channel0<6>_MC.D2 ;
  wire \U1/Channel0<6>_MC.D2_PT_0 ;
  wire \U1/Channel0<6>_MC.D2_PT_1 ;
  wire \U1/Channel0<6>_MC.D2_PT_2 ;
  wire \U1/Channel0<7>_MC.Q ;
  wire \U1/Channel0<7>_MC.D ;
  wire \U1/Channel0<7>_MC_tsimcreated_xor_ ;
  wire \U1/Channel0<7>_MC.D1 ;
  wire \U1/Channel0<7>_MC.D2 ;
  wire \U1/Channel0<7>_MC.D2_PT_0 ;
  wire \U1/Channel0<7>_MC.D2_PT_1 ;
  wire \U1/Channel0<7>_MC.D2_PT_2 ;
  wire \DCOR0THRESHIGHr_MC.Q ;
  wire \DCOR0THRESHIGHr_MC.D ;
  wire \DCOR0THRESHIGHr_MC.D1 ;
  wire \DCOR0THRESHIGHr_MC.D2 ;
  wire \U1/U4/Latch1r<0>_MC.Q ;
  wire \U1/U4/Latch1r<0>_MC.D ;
  wire \U1/U4/Latch1r<0>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ;
  wire \U1/U4/Latch1r<0>_MC.D1 ;
  wire \U1/U4/Latch1r<0>_MC.D2 ;
  wire \U1/U4/Latch1r<0>_MC.D2_PT_0 ;
  wire \U1/U4/Latch1r<0>_MC.D2_PT_1 ;
  wire \U1/Channel1<0>_MC.Q ;
  wire \U1/Channel1<0>_MC.D ;
  wire \U1/Channel1<0>_MC.D1 ;
  wire \U1/Channel1<0>_MC.D2 ;
  wire \U1/Zero1 ;
  wire N_PZ_1155;
  wire \U1/Channel1<0>_MC.D2_PT_0 ;
  wire \U1/Channel1<0>_MC.D2_PT_1 ;
  wire \U1/Zero1_MC.Q ;
  wire \U1/Zero1_MC.D ;
  wire \U1/Zero1_MC.REG_tsimcreated_inv_Mclk_II/FCLK ;
  wire \U1/Zero1_MC.D1 ;
  wire \U1/Zero1_MC.D2 ;
  wire \U1/Zero1_MC.D2_PT_0 ;
  wire N_PZ_933;
  wire \U1/Zero1_MC.D2_PT_1 ;
  wire \U1/Zero1_MC.D2_PT_2 ;
  wire \U1/Zero1_MC.D2_PT_3 ;
  wire \N_PZ_933_MC.Q ;
  wire \N_PZ_933_MC.D ;
  wire \N_PZ_933_MC.D1 ;
  wire \N_PZ_933_MC.D2 ;
  wire \N_PZ_1155_MC.Q ;
  wire \N_PZ_1155_MC.D ;
  wire \N_PZ_1155_MC.D1 ;
  wire \N_PZ_1155_MC.D2 ;
  wire \U1/U6/CurrState_Sreg0_FFD1 ;
  wire \U1/U6/CurrState_Sreg0_FFD3 ;
  wire \U1/U6/CurrState_Sreg0_FFD2 ;
  wire \U1/U6/CurrState_Sreg0_FFD4 ;
  wire \N_PZ_1155_MC.D2_PT_0 ;
  wire \N_PZ_1155_MC.D2_PT_1 ;
  wire \U1/U6/CurrState_Sreg0_FFD1_MC.Q ;
  wire \U1/U6/CurrState_Sreg0_FFD1_MC.D ;
  wire \U1/U6/CurrState_Sreg0_FFD1_MC.D1 ;
  wire \U1/U6/CurrState_Sreg0_FFD1_MC.D2 ;
  wire \U1/U6/CurrState_Sreg0_FFD1_MC.D2_PT_0 ;
  wire \U1/U6/CurrState_Sreg0_FFD1_MC.D2_PT_1 ;
  wire \U1/U6/CurrState_Sreg0_FFD1_MC.D2_PT_2 ;
  wire \U1/U6/CurrState_Sreg0_FFD3_MC.Q ;
  wire \U1/U6/CurrState_Sreg0_FFD3_MC.D ;
  wire \U1/U6/CurrState_Sreg0_FFD3_MC.D1 ;
  wire \U1/U6/CurrState_Sreg0_FFD3_MC.D2 ;
  wire N_PZ_1107;
  wire \U1/U6/CurrState_Sreg0_FFD3_MC.D2_PT_0 ;
  wire \U1/U6/CurrState_Sreg0_FFD3_MC.D2_PT_1 ;
  wire \U1/U6/CurrState_Sreg0_FFD3_MC.D2_PT_2 ;
  wire \U1/U6/CurrState_Sreg0_FFD2_MC.Q ;
  wire \U1/U6/CurrState_Sreg0_FFD2_MC.D ;
  wire \U1/U6/CurrState_Sreg0_FFD2_MC.D1 ;
  wire \U1/U6/CurrState_Sreg0_FFD2_MC.D2 ;
  wire \U1/U6/CurrState_Sreg0_FFD2_MC.D2_PT_0 ;
  wire \U1/U6/CurrState_Sreg0_FFD2_MC.D2_PT_1 ;
  wire \U1/U6/CurrState_Sreg0_FFD2_MC.D2_PT_2 ;
  wire \U1/U6/CurrState_Sreg0_FFD2_MC.D2_PT_3 ;
  wire \U1/U6/CurrState_Sreg0_FFD4_MC.Q ;
  wire \U1/U6/CurrState_Sreg0_FFD4_MC.D ;
  wire \U1/U6/CurrState_Sreg0_FFD4_MC.D1 ;
  wire \U1/U6/CurrState_Sreg0_FFD4_MC.D2 ;
  wire \N_PZ_1107_MC.Q ;
  wire \N_PZ_1107_MC.D ;
  wire \N_PZ_1107_MC.D1 ;
  wire \N_PZ_1107_MC.D2 ;
  wire \N_PZ_1107_MC.D2_PT_0 ;
  wire \N_PZ_1107_MC.D2_PT_1 ;
  wire \DCOR1THRESLOWr_MC.Q ;
  wire \DCOR1THRESLOWr_MC.D ;
  wire \DCOR1THRESLOWr_MC.D1 ;
  wire \DCOR1THRESLOWr_MC.D2 ;
  wire \U1/U4/Latch1r<8>_MC.Q ;
  wire \U1/U4/Latch1r<8>_MC.D ;
  wire \U1/U4/Latch1r<8>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ;
  wire \U1/U4/Latch1r<8>_MC.D1 ;
  wire \U1/U4/Latch1r<8>_MC.D2 ;
  wire \U1/U4/Latch1r<8>_MC.D2_PT_0 ;
  wire \U1/U4/Latch1r<8>_MC.D2_PT_1 ;
  wire \U1/Channel1<8>_MC.Q ;
  wire \U1/Channel1<8>_MC.D ;
  wire \U1/Channel1<8>_MC_tsimcreated_xor_ ;
  wire \U1/Channel1<8>_MC.D1 ;
  wire \U1/Channel1<8>_MC.D2 ;
  wire \U1/Channel1<8>_MC.D2_PT_0 ;
  wire N_PZ_1016;
  wire \U1/Channel1<8>_MC.D2_PT_1 ;
  wire \U1/Channel1<8>_MC.D2_PT_2 ;
  wire \U1/Channel1<8>_MC.D2_PT_3 ;
  wire \U1/Channel1<8>_MC.D2_PT_4 ;
  wire \U1/Channel1<8>_MC.D2_PT_5 ;
  wire \U1/Channel1<5>_MC.Q ;
  wire \U1/Channel1<5>_MC.D ;
  wire \U1/Channel1<5>_MC_tsimcreated_xor_ ;
  wire \U1/Channel1<5>_MC.D1 ;
  wire \U1/Channel1<5>_MC.D2 ;
  wire \U1/Channel1<5>_MC.D2_PT_0 ;
  wire \U1/Channel1<5>_MC.D2_PT_1 ;
  wire \U1/Channel1<5>_MC.D2_PT_2 ;
  wire \U1/U5/location_Maddsub__n0000__n0067<0>_MC.Q ;
  wire \U1/U5/location_Maddsub__n0000__n0067<0>_MC.D ;
  wire \U1/U5/location_Maddsub__n0000__n0067<0>_MC.D1 ;
  wire \U1/U5/location_Maddsub__n0000__n0067<0>_MC.D2 ;
  wire N_PZ_946;
  wire \U1/U5/location_Maddsub__n0000__n0067<0>_MC.D2_PT_0 ;
  wire \U1/U5/location_Maddsub__n0000__n0067<0>_MC.D2_PT_1 ;
  wire \N_PZ_946_MC.Q ;
  wire \N_PZ_946_MC.D ;
  wire \N_PZ_946_MC.D1 ;
  wire \N_PZ_946_MC.D2 ;
  wire \U1/NET3720 ;
  wire \N_PZ_946_MC.D2_PT_0 ;
  wire \N_PZ_946_MC.D2_PT_1 ;
  wire \U1/NET3720_MC.Q ;
  wire \U1/NET3720_MC.D ;
  wire \U1/NET3720_MC.REG_tsimcreated_inv_Mclk_II/FCLK ;
  wire \U1/NET3720_MC.D1 ;
  wire \U1/NET3720_MC.D2 ;
  wire \U1/NET3720_MC.D2_PT_0 ;
  wire \U1/NET3720_MC.D2_PT_1 ;
  wire \U1/Channel1<1>_MC.Q ;
  wire \U1/Channel1<1>_MC.D ;
  wire \U1/Channel1<1>_MC_tsimcreated_xor_ ;
  wire \U1/Channel1<1>_MC.D1 ;
  wire \U1/Channel1<1>_MC.D2 ;
  wire \U1/Channel1<1>_MC.D2_PT_0 ;
  wire \U1/Channel1<1>_MC.D2_PT_1 ;
  wire \U1/Channel1<1>_MC.D2_PT_2 ;
  wire \N_PZ_1016_MC.Q ;
  wire \N_PZ_1016_MC.D ;
  wire \N_PZ_1016_MC.D1 ;
  wire \N_PZ_1016_MC.D2 ;
  wire \N_PZ_1016_MC.D2_PT_0 ;
  wire \N_PZ_1016_MC.D2_PT_1 ;
  wire \U1/Channel1<2>_MC.Q ;
  wire \U1/Channel1<2>_MC.D ;
  wire \U1/Channel1<2>_MC_tsimcreated_xor_ ;
  wire \U1/Channel1<2>_MC.D1 ;
  wire \U1/Channel1<2>_MC.D2 ;
  wire \U1/Channel1<2>_MC.D2_PT_0 ;
  wire \U1/Channel1<2>_MC.D2_PT_1 ;
  wire \U1/Channel1<2>_MC.D2_PT_2 ;
  wire \U1/Channel1<3>_MC.Q ;
  wire \U1/Channel1<3>_MC.D ;
  wire \U1/Channel1<3>_MC_tsimcreated_xor_ ;
  wire \U1/Channel1<3>_MC.D1 ;
  wire \U1/Channel1<3>_MC.D2 ;
  wire \U1/Channel1<3>_MC.D2_PT_0 ;
  wire \U1/Channel1<3>_MC.D2_PT_1 ;
  wire \U1/Channel1<3>_MC.D2_PT_2 ;
  wire \U1/Channel1<4>_MC.Q ;
  wire \U1/Channel1<4>_MC.D ;
  wire \U1/Channel1<4>_MC_tsimcreated_xor_ ;
  wire \U1/Channel1<4>_MC.D1 ;
  wire \U1/Channel1<4>_MC.D2 ;
  wire \U1/Channel1<4>_MC.D2_PT_0 ;
  wire \U1/Channel1<4>_MC.D2_PT_1 ;
  wire \U1/Channel1<4>_MC.D2_PT_2 ;
  wire \U1/Channel1<4>_MC.D2_PT_3 ;
  wire \U1/Channel1<4>_MC.D2_PT_4 ;
  wire \U1/Channel1<4>_MC.D2_PT_5 ;
  wire \U1/Channel1<6>_MC.Q ;
  wire \U1/Channel1<6>_MC.D ;
  wire \U1/Channel1<6>_MC_tsimcreated_xor_ ;
  wire \U1/Channel1<6>_MC.D1 ;
  wire \U1/Channel1<6>_MC.D2 ;
  wire \U1/Channel1<6>_MC.D2_PT_0 ;
  wire \U1/Channel1<6>_MC.D2_PT_1 ;
  wire \U1/Channel1<6>_MC.D2_PT_2 ;
  wire \U1/Channel1<7>_MC.Q ;
  wire \U1/Channel1<7>_MC.D ;
  wire \U1/Channel1<7>_MC_tsimcreated_xor_ ;
  wire \U1/Channel1<7>_MC.D1 ;
  wire \U1/Channel1<7>_MC.D2 ;
  wire \U1/Channel1<7>_MC.D2_PT_0 ;
  wire \U1/Channel1<7>_MC.D2_PT_1 ;
  wire \U1/Channel1<7>_MC.D2_PT_2 ;
  wire \U1/U5/location_Maddsub__n0000__n0075<0>_MC.Q ;
  wire \U1/U5/location_Maddsub__n0000__n0075<0>_MC.D ;
  wire \U1/U5/location_Maddsub__n0000__n0075<0>_MC.D1 ;
  wire \U1/U5/location_Maddsub__n0000__n0075<0>_MC.D2 ;
  wire \U1/U5/location_Maddsub__n0000__n0075<0>_MC.D2_PT_0 ;
  wire \U1/U5/location_Maddsub__n0000__n0075<0>_MC.D2_PT_1 ;
  wire \outDATA<0>\$WA5.UIM_MC.Q ;
  wire \outDATA<0>\$WA5.UIM_MC.D ;
  wire \outDATA<0>\$WA5.UIM_MC.D1 ;
  wire \outDATA<0>\$WA5.UIM_MC.D2 ;
  wire DCOR0CNTLOWr;
  wire \outDATA<0>\$WA5.UIM_MC.D2_PT_0 ;
  wire DCOR1CNTLOWr;
  wire \outDATA<0>\$WA5.UIM_MC.D2_PT_1 ;
  wire DCOR0CNTHIGHr;
  wire \outDATA<0>\$WA5.UIM_MC.D2_PT_2 ;
  wire \outDATA<0>\$WA5.UIM_MC.D2_PT_3 ;
  wire \U1/U3/holdingreg0<0>_MC.Q ;
  wire \U1/U3/holdingreg0<0>_MC.D ;
  wire \U1/U3/holdingreg0<0>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ;
  wire \U1/U3/holdingreg0<0>_MC.D1 ;
  wire \U1/U3/holdingreg0<0>_MC.D2 ;
  wire \U1/U3/holdingreg0<0>_MC.D2_PT_0 ;
  wire \U1/U3/holdingreg0<0>_MC.D2_PT_1 ;
  wire \DCOR0CNTLOWr_MC.Q ;
  wire \DCOR0CNTLOWr_MC.D ;
  wire \DCOR0CNTLOWr_MC.D1 ;
  wire \DCOR0CNTLOWr_MC.D2 ;
  wire \U1/U3/holdingreg1<0>_MC.Q ;
  wire \U1/U3/holdingreg1<0>_MC.D ;
  wire \U1/U3/holdingreg1<0>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ;
  wire \U1/U3/holdingreg1<0>_MC.D1 ;
  wire \U1/U3/holdingreg1<0>_MC.D2 ;
  wire \U1/U3/holdingreg1<0>_MC.D2_PT_0 ;
  wire \U1/U3/holdingreg1<0>_MC.D2_PT_1 ;
  wire \DCOR1CNTLOWr_MC.Q ;
  wire \DCOR1CNTLOWr_MC.D ;
  wire \DCOR1CNTLOWr_MC.D1 ;
  wire \DCOR1CNTLOWr_MC.D2 ;
  wire \U1/U3/holdingreg0<8>_MC.Q ;
  wire \U1/U3/holdingreg0<8>_MC.D ;
  wire \U1/U3/holdingreg0<8>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ;
  wire \U1/U3/holdingreg0<8>_MC.D1 ;
  wire \U1/U3/holdingreg0<8>_MC.D2 ;
  wire \U1/U3/holdingreg0<8>_MC.D2_PT_0 ;
  wire \U1/U3/holdingreg0<8>_MC.D2_PT_1 ;
  wire \DCOR0CNTHIGHr_MC.Q ;
  wire \DCOR0CNTHIGHr_MC.D ;
  wire \DCOR0CNTHIGHr_MC.D1 ;
  wire \DCOR0CNTHIGHr_MC.D2 ;
  wire \U1/U3/holdingreg1<8>_MC.Q ;
  wire \U1/U3/holdingreg1<8>_MC.D ;
  wire \U1/U3/holdingreg1<8>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ;
  wire \U1/U3/holdingreg1<8>_MC.D1 ;
  wire \U1/U3/holdingreg1<8>_MC.D2 ;
  wire \U1/U3/holdingreg1<8>_MC.D2_PT_0 ;
  wire \U1/U3/holdingreg1<8>_MC.D2_PT_1 ;
  wire \N_PZ_963_MC.Q ;
  wire \N_PZ_963_MC.D ;
  wire \N_PZ_963_MC.D1 ;
  wire \N_PZ_963_MC.D2 ;
  wire DCOR1CNTHIGHr;
  wire \DCOR1CNTHIGHr_MC.Q ;
  wire \DCOR1CNTHIGHr_MC.D ;
  wire \DCOR1CNTHIGHr_MC.D1 ;
  wire \DCOR1CNTHIGHr_MC.D2 ;
  wire \N_PZ_980_MC.Q ;
  wire \N_PZ_980_MC.D ;
  wire \N_PZ_980_MC.D1 ;
  wire \N_PZ_980_MC.D2 ;
  wire DCOR1THRESHIGHr;
  wire \DCOR1THRESHIGHr_MC.Q ;
  wire \DCOR1THRESHIGHr_MC.D ;
  wire \DCOR1THRESHIGHr_MC.D1 ;
  wire \DCOR1THRESHIGHr_MC.D2 ;
  wire \outDATA<1>\$WA0.UIM_MC.Q ;
  wire \outDATA<1>\$WA0.UIM_MC.D ;
  wire \outDATA<1>\$WA0.UIM_MC.D1 ;
  wire \outDATA<1>\$WA0.UIM_MC.D2 ;
  wire \outDATA<1>\$WA1.UIM_MC.Q ;
  wire \outDATA<1>\$WA1.UIM_MC.D ;
  wire \outDATA<1>\$WA1.UIM_MC.D1 ;
  wire \outDATA<1>\$WA1.UIM_MC.D2 ;
  wire \outDATA<1>\$WA2.UIM_MC.Q ;
  wire \outDATA<1>\$WA2.UIM_MC.D ;
  wire \outDATA<1>\$WA2.UIM_MC.D1 ;
  wire \outDATA<1>\$WA2.UIM_MC.D2 ;
  wire \outDATA<1>\$WA3.UIM_MC.Q ;
  wire \outDATA<1>\$WA3.UIM_MC.D ;
  wire \outDATA<1>\$WA3.UIM_MC.D1 ;
  wire \outDATA<1>\$WA3.UIM_MC.D2 ;
  wire \outDATA<1>\$WA3.UIM_MC.D2_PT_0 ;
  wire \outDATA<1>\$WA3.UIM_MC.D2_PT_1 ;
  wire \outDATA<1>\$WA3.UIM_MC.D2_PT_2 ;
  wire \outDATA<1>\$WA6.UIM_MC.Q ;
  wire \outDATA<1>\$WA6.UIM_MC.D ;
  wire \outDATA<1>\$WA6.UIM_MC.D1 ;
  wire \outDATA<1>\$WA6.UIM_MC.D2 ;
  wire \outDATA<1>\$WA6.UIM_MC.D2_PT_0 ;
  wire \outDATA<1>\$WA6.UIM_MC.D2_PT_1 ;
  wire \outDATA<1>\$WA6.UIM_MC.D2_PT_2 ;
  wire \outDATA<1>\$WA6.UIM_MC.D2_PT_3 ;
  wire \U1/U4/Latch0r<1>_MC.Q ;
  wire \U1/U4/Latch0r<1>_MC.D ;
  wire \U1/U4/Latch0r<1>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ;
  wire \U1/U4/Latch0r<1>_MC.D1 ;
  wire \U1/U4/Latch0r<1>_MC.D2 ;
  wire \U1/U4/Latch0r<1>_MC.D2_PT_0 ;
  wire \U1/U4/Latch0r<1>_MC.D2_PT_1 ;
  wire \U1/U4/Latch0r<9>_MC.Q ;
  wire \U1/U4/Latch0r<9>_MC.D ;
  wire \U1/U4/Latch0r<9>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ;
  wire \U1/U4/Latch0r<9>_MC.D1 ;
  wire \U1/U4/Latch0r<9>_MC.D2 ;
  wire \U1/U4/Latch0r<9>_MC.D2_PT_0 ;
  wire \U1/U4/Latch0r<9>_MC.D2_PT_1 ;
  wire \U1/Channel0<9>_MC.Q ;
  wire \U1/Channel0<9>_MC.D ;
  wire \U1/Channel0<9>_MC_tsimcreated_xor_ ;
  wire \U1/Channel0<9>_MC.D1 ;
  wire \U1/Channel0<9>_MC.D2 ;
  wire \U1/Channel0<9>_MC.D2_PT_0 ;
  wire \U1/Channel0<9>_MC.D2_PT_1 ;
  wire \U1/Channel0<9>_MC.D2_PT_2 ;
  wire \U1/U4/Latch1r<1>_MC.Q ;
  wire \U1/U4/Latch1r<1>_MC.D ;
  wire \U1/U4/Latch1r<1>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ;
  wire \U1/U4/Latch1r<1>_MC.D1 ;
  wire \U1/U4/Latch1r<1>_MC.D2 ;
  wire \U1/U4/Latch1r<1>_MC.D2_PT_0 ;
  wire \U1/U4/Latch1r<1>_MC.D2_PT_1 ;
  wire \U1/U4/Latch1r<9>_MC.Q ;
  wire \U1/U4/Latch1r<9>_MC.D ;
  wire \U1/U4/Latch1r<9>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ;
  wire \U1/U4/Latch1r<9>_MC.D1 ;
  wire \U1/U4/Latch1r<9>_MC.D2 ;
  wire \U1/U4/Latch1r<9>_MC.D2_PT_0 ;
  wire \U1/U4/Latch1r<9>_MC.D2_PT_1 ;
  wire \U1/Channel1<9>_MC.Q ;
  wire \U1/Channel1<9>_MC.D ;
  wire \U1/Channel1<9>_MC_tsimcreated_xor_ ;
  wire \U1/Channel1<9>_MC.D1 ;
  wire \U1/Channel1<9>_MC.D2 ;
  wire \U1/Channel1<9>_MC.D2_PT_0 ;
  wire \U1/Channel1<9>_MC.D2_PT_1 ;
  wire \U1/Channel1<9>_MC.D2_PT_2 ;
  wire \outDATA<1>\$WA5.UIM_MC.Q ;
  wire \outDATA<1>\$WA5.UIM_MC.D ;
  wire \outDATA<1>\$WA5.UIM_MC.D1 ;
  wire \outDATA<1>\$WA5.UIM_MC.D2 ;
  wire \outDATA<1>\$WA5.UIM_MC.D2_PT_0 ;
  wire \outDATA<1>\$WA5.UIM_MC.D2_PT_1 ;
  wire \outDATA<1>\$WA5.UIM_MC.D2_PT_2 ;
  wire \outDATA<1>\$WA5.UIM_MC.D2_PT_3 ;
  wire \U1/U3/holdingreg0<1>_MC.Q ;
  wire \U1/U3/holdingreg0<1>_MC.D ;
  wire \U1/U3/holdingreg0<1>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ;
  wire \U1/U3/holdingreg0<1>_MC.D1 ;
  wire \U1/U3/holdingreg0<1>_MC.D2 ;
  wire \U1/U3/holdingreg0<1>_MC.D2_PT_0 ;
  wire \U1/U3/holdingreg0<1>_MC.D2_PT_1 ;
  wire \U1/U3/holdingreg1<1>_MC.Q ;
  wire \U1/U3/holdingreg1<1>_MC.D ;
  wire \U1/U3/holdingreg1<1>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ;
  wire \U1/U3/holdingreg1<1>_MC.D1 ;
  wire \U1/U3/holdingreg1<1>_MC.D2 ;
  wire \U1/U3/holdingreg1<1>_MC.D2_PT_0 ;
  wire \U1/U3/holdingreg1<1>_MC.D2_PT_1 ;
  wire \U1/U3/holdingreg0<9>_MC.Q ;
  wire \U1/U3/holdingreg0<9>_MC.D ;
  wire \U1/U3/holdingreg0<9>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ;
  wire \U1/U3/holdingreg0<9>_MC.D1 ;
  wire \U1/U3/holdingreg0<9>_MC.D2 ;
  wire \U1/U3/holdingreg0<9>_MC.D2_PT_0 ;
  wire \U1/U3/holdingreg0<9>_MC.D2_PT_1 ;
  wire \U1/U3/holdingreg1<9>_MC.Q ;
  wire \U1/U3/holdingreg1<9>_MC.D ;
  wire \U1/U3/holdingreg1<9>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ;
  wire \U1/U3/holdingreg1<9>_MC.D1 ;
  wire \U1/U3/holdingreg1<9>_MC.D2 ;
  wire \U1/U3/holdingreg1<9>_MC.D2_PT_0 ;
  wire \U1/U3/holdingreg1<9>_MC.D2_PT_1 ;
  wire \outDATA<2>\$WA0.UIM_MC.Q ;
  wire \outDATA<2>\$WA0.UIM_MC.D ;
  wire \outDATA<2>\$WA0.UIM_MC.D1 ;
  wire \outDATA<2>\$WA0.UIM_MC.D2 ;
  wire \outDATA<2>\$WA1.UIM_MC.Q ;
  wire \outDATA<2>\$WA1.UIM_MC.D ;
  wire \outDATA<2>\$WA1.UIM_MC.D1 ;
  wire \outDATA<2>\$WA1.UIM_MC.D2 ;
  wire \outDATA<2>\$WA2.UIM_MC.Q ;
  wire \outDATA<2>\$WA2.UIM_MC.D ;
  wire \outDATA<2>\$WA2.UIM_MC.D1 ;
  wire \outDATA<2>\$WA2.UIM_MC.D2 ;
  wire \outDATA<2>\$WA3.UIM_MC.Q ;
  wire \outDATA<2>\$WA3.UIM_MC.D ;
  wire \outDATA<2>\$WA3.UIM_MC.D1 ;
  wire \outDATA<2>\$WA3.UIM_MC.D2 ;
  wire \outDATA<2>\$WA3.UIM_MC.D2_PT_0 ;
  wire \outDATA<2>\$WA3.UIM_MC.D2_PT_1 ;
  wire \outDATA<2>\$WA5.UIM_MC.Q ;
  wire \outDATA<2>\$WA5.UIM_MC.D ;
  wire \outDATA<2>\$WA5.UIM_MC.D1 ;
  wire \outDATA<2>\$WA5.UIM_MC.D2 ;
  wire \outDATA<2>\$WA5.UIM_MC.D2_PT_0 ;
  wire \outDATA<2>\$WA5.UIM_MC.D2_PT_1 ;
  wire \outDATA<2>\$WA5.UIM_MC.D2_PT_2 ;
  wire \outDATA<2>\$WA5.UIM_MC.D2_PT_3 ;
  wire \U1/U3/holdingreg0<2>_MC.Q ;
  wire \U1/U3/holdingreg0<2>_MC.D ;
  wire \U1/U3/holdingreg0<2>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ;
  wire \U1/U3/holdingreg0<2>_MC.D1 ;
  wire \U1/U3/holdingreg0<2>_MC.D2 ;
  wire \U1/U3/holdingreg0<2>_MC.D2_PT_0 ;
  wire \U1/U3/holdingreg0<2>_MC.D2_PT_1 ;
  wire \U1/U3/holdingreg1<2>_MC.Q ;
  wire \U1/U3/holdingreg1<2>_MC.D ;
  wire \U1/U3/holdingreg1<2>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ;
  wire \U1/U3/holdingreg1<2>_MC.D1 ;
  wire \U1/U3/holdingreg1<2>_MC.D2 ;
  wire \U1/U3/holdingreg1<2>_MC.D2_PT_0 ;
  wire \U1/U3/holdingreg1<2>_MC.D2_PT_1 ;
  wire \U1/U3/holdingreg0<10>_MC.Q ;
  wire \U1/U3/holdingreg0<10>_MC.D ;
  wire \U1/U3/holdingreg0<10>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ;
  wire \U1/U3/holdingreg0<10>_MC.D1 ;
  wire \U1/U3/holdingreg0<10>_MC.D2 ;
  wire \U1/U3/holdingreg0<10>_MC.D2_PT_0 ;
  wire \U1/U3/holdingreg0<10>_MC.D2_PT_1 ;
  wire \U1/Channel0<10>_MC.Q ;
  wire \U1/Channel0<10>_MC.D ;
  wire \U1/Channel0<10>_MC_tsimcreated_xor_ ;
  wire \U1/Channel0<10>_MC.D1 ;
  wire \U1/Channel0<10>_MC.D2 ;
  wire \U1/Channel0<10>_MC.D2_PT_0 ;
  wire \U1/Channel0<10>_MC.D2_PT_1 ;
  wire \U1/Channel0<10>_MC.D2_PT_2 ;
  wire \U1/U3/holdingreg1<10>_MC.Q ;
  wire \U1/U3/holdingreg1<10>_MC.D ;
  wire \U1/U3/holdingreg1<10>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ;
  wire \U1/U3/holdingreg1<10>_MC.D1 ;
  wire \U1/U3/holdingreg1<10>_MC.D2 ;
  wire \U1/U3/holdingreg1<10>_MC.D2_PT_0 ;
  wire \U1/U3/holdingreg1<10>_MC.D2_PT_1 ;
  wire \U1/Channel1<10>_MC.Q ;
  wire \U1/Channel1<10>_MC.D ;
  wire \U1/Channel1<10>_MC_tsimcreated_xor_ ;
  wire \U1/Channel1<10>_MC.D1 ;
  wire \U1/Channel1<10>_MC.D2 ;
  wire \U1/Channel1<10>_MC.D2_PT_0 ;
  wire \U1/Channel1<10>_MC.D2_PT_1 ;
  wire \U1/Channel1<10>_MC.D2_PT_2 ;
  wire \outDATA<2>\$WA6.UIM_MC.Q ;
  wire \outDATA<2>\$WA6.UIM_MC.D ;
  wire \outDATA<2>\$WA6.UIM_MC.D1 ;
  wire \outDATA<2>\$WA6.UIM_MC.D2 ;
  wire \outDATA<2>\$WA6.UIM_MC.D2_PT_0 ;
  wire \outDATA<2>\$WA6.UIM_MC.D2_PT_1 ;
  wire \outDATA<2>\$WA6.UIM_MC.D2_PT_2 ;
  wire \outDATA<2>\$WA6.UIM_MC.D2_PT_3 ;
  wire \outDATA<2>\$WA6.UIM_MC.D2_PT_4 ;
  wire \U1/U4/Latch0r<2>_MC.Q ;
  wire \U1/U4/Latch0r<2>_MC.D ;
  wire \U1/U4/Latch0r<2>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ;
  wire \U1/U4/Latch0r<2>_MC.D1 ;
  wire \U1/U4/Latch0r<2>_MC.D2 ;
  wire \U1/U4/Latch0r<2>_MC.D2_PT_0 ;
  wire \U1/U4/Latch0r<2>_MC.D2_PT_1 ;
  wire \U1/U4/Latch0r<10>_MC.Q ;
  wire \U1/U4/Latch0r<10>_MC.D ;
  wire \U1/U4/Latch0r<10>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ;
  wire \U1/U4/Latch0r<10>_MC.D1 ;
  wire \U1/U4/Latch0r<10>_MC.D2 ;
  wire \U1/U4/Latch0r<10>_MC.D2_PT_0 ;
  wire \U1/U4/Latch0r<10>_MC.D2_PT_1 ;
  wire \U1/U4/Latch1r<2>_MC.Q ;
  wire \U1/U4/Latch1r<2>_MC.D ;
  wire \U1/U4/Latch1r<2>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ;
  wire \U1/U4/Latch1r<2>_MC.D1 ;
  wire \U1/U4/Latch1r<2>_MC.D2 ;
  wire \U1/U4/Latch1r<2>_MC.D2_PT_0 ;
  wire \U1/U4/Latch1r<2>_MC.D2_PT_1 ;
  wire \U1/U4/Latch1r<10>_MC.Q ;
  wire \U1/U4/Latch1r<10>_MC.D ;
  wire \U1/U4/Latch1r<10>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ;
  wire \U1/U4/Latch1r<10>_MC.D1 ;
  wire \U1/U4/Latch1r<10>_MC.D2 ;
  wire \U1/U4/Latch1r<10>_MC.D2_PT_0 ;
  wire \U1/U4/Latch1r<10>_MC.D2_PT_1 ;
  wire \outDATA<3>\$WA0.UIM_MC.Q ;
  wire \outDATA<3>\$WA0.UIM_MC.D ;
  wire \outDATA<3>\$WA0.UIM_MC.D1 ;
  wire \outDATA<3>\$WA0.UIM_MC.D2 ;
  wire \outDATA<3>\$WA1.UIM_MC.Q ;
  wire \outDATA<3>\$WA1.UIM_MC.D ;
  wire \outDATA<3>\$WA1.UIM_MC.D1 ;
  wire \outDATA<3>\$WA1.UIM_MC.D2 ;
  wire \outDATA<3>\$WA2.UIM_MC.Q ;
  wire \outDATA<3>\$WA2.UIM_MC.D ;
  wire \outDATA<3>\$WA2.UIM_MC.D1 ;
  wire \outDATA<3>\$WA2.UIM_MC.D2 ;
  wire \outDATA<3>\$WA3.UIM_MC.Q ;
  wire \outDATA<3>\$WA3.UIM_MC.D ;
  wire \outDATA<3>\$WA3.UIM_MC.D1 ;
  wire \outDATA<3>\$WA3.UIM_MC.D2 ;
  wire \outDATA<3>\$WA3.UIM_MC.D2_PT_0 ;
  wire \outDATA<3>\$WA3.UIM_MC.D2_PT_1 ;
  wire \outDATA<3>\$WA5.UIM_MC.Q ;
  wire \outDATA<3>\$WA5.UIM_MC.D ;
  wire \outDATA<3>\$WA5.UIM_MC.D1 ;
  wire \outDATA<3>\$WA5.UIM_MC.D2 ;
  wire \outDATA<3>\$WA5.UIM_MC.D2_PT_0 ;
  wire \outDATA<3>\$WA5.UIM_MC.D2_PT_1 ;
  wire \outDATA<3>\$WA5.UIM_MC.D2_PT_2 ;
  wire \outDATA<3>\$WA5.UIM_MC.D2_PT_3 ;
  wire \U1/U3/holdingreg0<3>_MC.Q ;
  wire \U1/U3/holdingreg0<3>_MC.D ;
  wire \U1/U3/holdingreg0<3>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ;
  wire \U1/U3/holdingreg0<3>_MC.D1 ;
  wire \U1/U3/holdingreg0<3>_MC.D2 ;
  wire \U1/U3/holdingreg0<3>_MC.D2_PT_0 ;
  wire \U1/U3/holdingreg0<3>_MC.D2_PT_1 ;
  wire \U1/U3/holdingreg1<3>_MC.Q ;
  wire \U1/U3/holdingreg1<3>_MC.D ;
  wire \U1/U3/holdingreg1<3>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ;
  wire \U1/U3/holdingreg1<3>_MC.D1 ;
  wire \U1/U3/holdingreg1<3>_MC.D2 ;
  wire \U1/U3/holdingreg1<3>_MC.D2_PT_0 ;
  wire \U1/U3/holdingreg1<3>_MC.D2_PT_1 ;
  wire \U1/U3/holdingreg0<11>_MC.Q ;
  wire \U1/U3/holdingreg0<11>_MC.D ;
  wire \U1/U3/holdingreg0<11>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ;
  wire \U1/U3/holdingreg0<11>_MC.D1 ;
  wire \U1/U3/holdingreg0<11>_MC.D2 ;
  wire \U1/U3/holdingreg0<11>_MC.D2_PT_0 ;
  wire \U1/U3/holdingreg0<11>_MC.D2_PT_1 ;
  wire \U1/Channel0<11>_MC.Q ;
  wire \U1/Channel0<11>_MC.D ;
  wire \U1/Channel0<11>_MC_tsimcreated_xor_ ;
  wire \U1/Channel0<11>_MC.D1 ;
  wire \U1/Channel0<11>_MC.D2 ;
  wire \U1/Channel0<11>_MC.D2_PT_0 ;
  wire \U1/Channel0<11>_MC.D2_PT_1 ;
  wire \U1/Channel0<11>_MC.D2_PT_2 ;
  wire \U1/U3/holdingreg1<11>_MC.Q ;
  wire \U1/U3/holdingreg1<11>_MC.D ;
  wire \U1/U3/holdingreg1<11>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ;
  wire \U1/U3/holdingreg1<11>_MC.D1 ;
  wire \U1/U3/holdingreg1<11>_MC.D2 ;
  wire \U1/U3/holdingreg1<11>_MC.D2_PT_0 ;
  wire \U1/U3/holdingreg1<11>_MC.D2_PT_1 ;
  wire \U1/Channel1<11>_MC.Q ;
  wire \U1/Channel1<11>_MC.D ;
  wire \U1/Channel1<11>_MC_tsimcreated_xor_ ;
  wire \U1/Channel1<11>_MC.D1 ;
  wire \U1/Channel1<11>_MC.D2 ;
  wire \U1/Channel1<11>_MC.D2_PT_0 ;
  wire \U1/Channel1<11>_MC.D2_PT_1 ;
  wire \U1/Channel1<11>_MC.D2_PT_2 ;
  wire \outDATA<3>\$WA6.UIM_MC.Q ;
  wire \outDATA<3>\$WA6.UIM_MC.D ;
  wire \outDATA<3>\$WA6.UIM_MC.D1 ;
  wire \outDATA<3>\$WA6.UIM_MC.D2 ;
  wire \outDATA<3>\$WA6.UIM_MC.D2_PT_0 ;
  wire \outDATA<3>\$WA6.UIM_MC.D2_PT_1 ;
  wire \outDATA<3>\$WA6.UIM_MC.D2_PT_2 ;
  wire \outDATA<3>\$WA6.UIM_MC.D2_PT_3 ;
  wire \outDATA<3>\$WA6.UIM_MC.D2_PT_4 ;
  wire \U1/U4/Latch0r<3>_MC.Q ;
  wire \U1/U4/Latch0r<3>_MC.D ;
  wire \U1/U4/Latch0r<3>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ;
  wire \U1/U4/Latch0r<3>_MC.D1 ;
  wire \U1/U4/Latch0r<3>_MC.D2 ;
  wire \U1/U4/Latch0r<3>_MC.D2_PT_0 ;
  wire \U1/U4/Latch0r<3>_MC.D2_PT_1 ;
  wire \U1/U4/Latch0r<11>_MC.Q ;
  wire \U1/U4/Latch0r<11>_MC.D ;
  wire \U1/U4/Latch0r<11>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ;
  wire \U1/U4/Latch0r<11>_MC.D1 ;
  wire \U1/U4/Latch0r<11>_MC.D2 ;
  wire \U1/U4/Latch0r<11>_MC.D2_PT_0 ;
  wire \U1/U4/Latch0r<11>_MC.D2_PT_1 ;
  wire \U1/U4/Latch1r<3>_MC.Q ;
  wire \U1/U4/Latch1r<3>_MC.D ;
  wire \U1/U4/Latch1r<3>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ;
  wire \U1/U4/Latch1r<3>_MC.D1 ;
  wire \U1/U4/Latch1r<3>_MC.D2 ;
  wire \U1/U4/Latch1r<3>_MC.D2_PT_0 ;
  wire \U1/U4/Latch1r<3>_MC.D2_PT_1 ;
  wire \U1/U4/Latch1r<11>_MC.Q ;
  wire \U1/U4/Latch1r<11>_MC.D ;
  wire \U1/U4/Latch1r<11>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ;
  wire \U1/U4/Latch1r<11>_MC.D1 ;
  wire \U1/U4/Latch1r<11>_MC.D2 ;
  wire \U1/U4/Latch1r<11>_MC.D2_PT_0 ;
  wire \U1/U4/Latch1r<11>_MC.D2_PT_1 ;
  wire \outDATA<4>\$WA0.UIM_MC.Q ;
  wire \outDATA<4>\$WA0.UIM_MC.D ;
  wire \outDATA<4>\$WA0.UIM_MC.D1 ;
  wire \outDATA<4>\$WA0.UIM_MC.D2 ;
  wire \outDATA<4>\$WA1.UIM_MC.Q ;
  wire \outDATA<4>\$WA1.UIM_MC.D ;
  wire \outDATA<4>\$WA1.UIM_MC.D1 ;
  wire \outDATA<4>\$WA1.UIM_MC.D2 ;
  wire \outDATA<4>\$WA2.UIM_MC.Q ;
  wire \outDATA<4>\$WA2.UIM_MC.D ;
  wire \outDATA<4>\$WA2.UIM_MC.D1 ;
  wire \outDATA<4>\$WA2.UIM_MC.D2 ;
  wire \outDATA<4>\$WA3.UIM_MC.Q ;
  wire \outDATA<4>\$WA3.UIM_MC.D ;
  wire \outDATA<4>\$WA3.UIM_MC.D1 ;
  wire \outDATA<4>\$WA3.UIM_MC.D2 ;
  wire \outDATA<4>\$WA3.UIM_MC.D2_PT_0 ;
  wire \outDATA<4>\$WA3.UIM_MC.D2_PT_1 ;
  wire \outDATA<4>\$WA4.UIM_MC.Q ;
  wire \outDATA<4>\$WA4.UIM_MC.D ;
  wire \outDATA<4>\$WA4.UIM_MC.D1 ;
  wire \outDATA<4>\$WA4.UIM_MC.D2 ;
  wire \outDATA<4>\$WA6.UIM_MC.Q ;
  wire \outDATA<4>\$WA6.UIM_MC.D ;
  wire \outDATA<4>\$WA6.UIM_MC.D1 ;
  wire \outDATA<4>\$WA6.UIM_MC.D2 ;
  wire \outDATA<4>\$WA6.UIM_MC.D2_PT_0 ;
  wire \outDATA<4>\$WA6.UIM_MC.D2_PT_1 ;
  wire \outDATA<4>\$WA6.UIM_MC.D2_PT_2 ;
  wire \outDATA<4>\$WA6.UIM_MC.D2_PT_3 ;
  wire \U1/U4/Latch0r<4>_MC.Q ;
  wire \U1/U4/Latch0r<4>_MC.D ;
  wire \U1/U4/Latch0r<4>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ;
  wire \U1/U4/Latch0r<4>_MC.D1 ;
  wire \U1/U4/Latch0r<4>_MC.D2 ;
  wire \U1/U4/Latch0r<4>_MC.D2_PT_0 ;
  wire \U1/U4/Latch0r<4>_MC.D2_PT_1 ;
  wire \U1/U4/Latch0r<12>_MC.Q ;
  wire \U1/U4/Latch0r<12>_MC.D ;
  wire \U1/U4/Latch0r<12>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ;
  wire \U1/U4/Latch0r<12>_MC.D1 ;
  wire \U1/U4/Latch0r<12>_MC.D2 ;
  wire \U1/U4/Latch0r<12>_MC.D2_PT_0 ;
  wire \U1/U4/Latch0r<12>_MC.D2_PT_1 ;
  wire \U1/Channel0<12>_MC.Q ;
  wire \U1/Channel0<12>_MC.D ;
  wire \U1/Channel0<12>_MC_tsimcreated_xor_ ;
  wire \U1/Channel0<12>_MC.D1 ;
  wire \U1/Channel0<12>_MC.D2 ;
  wire \U1/Channel0<12>_MC.D2_PT_0 ;
  wire \U1/Channel0<12>_MC.D2_PT_1 ;
  wire \U1/Channel0<12>_MC.D2_PT_2 ;
  wire \U1/U4/Latch1r<4>_MC.Q ;
  wire \U1/U4/Latch1r<4>_MC.D ;
  wire \U1/U4/Latch1r<4>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ;
  wire \U1/U4/Latch1r<4>_MC.D1 ;
  wire \U1/U4/Latch1r<4>_MC.D2 ;
  wire \U1/U4/Latch1r<4>_MC.D2_PT_0 ;
  wire \U1/U4/Latch1r<4>_MC.D2_PT_1 ;
  wire \U1/U4/Latch1r<12>_MC.Q ;
  wire \U1/U4/Latch1r<12>_MC.D ;
  wire \U1/U4/Latch1r<12>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ;
  wire \U1/U4/Latch1r<12>_MC.D1 ;
  wire \U1/U4/Latch1r<12>_MC.D2 ;
  wire \U1/U4/Latch1r<12>_MC.D2_PT_0 ;
  wire \U1/U4/Latch1r<12>_MC.D2_PT_1 ;
  wire \U1/Channel1<12>_MC.Q ;
  wire \U1/Channel1<12>_MC.D ;
  wire \U1/Channel1<12>_MC_tsimcreated_xor_ ;
  wire \U1/Channel1<12>_MC.D1 ;
  wire \U1/Channel1<12>_MC.D2 ;
  wire \U1/Channel1<12>_MC.D2_PT_0 ;
  wire \U1/Channel1<12>_MC.D2_PT_1 ;
  wire \U1/Channel1<12>_MC.D2_PT_2 ;
  wire \outDATA<4>\$WA5.UIM_MC.Q ;
  wire \outDATA<4>\$WA5.UIM_MC.D ;
  wire \outDATA<4>\$WA5.UIM_MC.D1 ;
  wire \outDATA<4>\$WA5.UIM_MC.D2 ;
  wire \outDATA<4>\$WA5.UIM_MC.D2_PT_0 ;
  wire \outDATA<4>\$WA5.UIM_MC.D2_PT_1 ;
  wire \outDATA<4>\$WA5.UIM_MC.D2_PT_2 ;
  wire \outDATA<4>\$WA5.UIM_MC.D2_PT_3 ;
  wire \U1/U3/holdingreg0<4>_MC.Q ;
  wire \U1/U3/holdingreg0<4>_MC.D ;
  wire \U1/U3/holdingreg0<4>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ;
  wire \U1/U3/holdingreg0<4>_MC.D1 ;
  wire \U1/U3/holdingreg0<4>_MC.D2 ;
  wire \U1/U3/holdingreg0<4>_MC.D2_PT_0 ;
  wire \U1/U3/holdingreg0<4>_MC.D2_PT_1 ;
  wire \U1/U3/holdingreg1<4>_MC.Q ;
  wire \U1/U3/holdingreg1<4>_MC.D ;
  wire \U1/U3/holdingreg1<4>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ;
  wire \U1/U3/holdingreg1<4>_MC.D1 ;
  wire \U1/U3/holdingreg1<4>_MC.D2 ;
  wire \U1/U3/holdingreg1<4>_MC.D2_PT_0 ;
  wire \U1/U3/holdingreg1<4>_MC.D2_PT_1 ;
  wire \U1/U3/holdingreg0<12>_MC.Q ;
  wire \U1/U3/holdingreg0<12>_MC.D ;
  wire \U1/U3/holdingreg0<12>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ;
  wire \U1/U3/holdingreg0<12>_MC.D1 ;
  wire \U1/U3/holdingreg0<12>_MC.D2 ;
  wire \U1/U3/holdingreg0<12>_MC.D2_PT_0 ;
  wire \U1/U3/holdingreg0<12>_MC.D2_PT_1 ;
  wire \U1/U3/holdingreg1<12>_MC.Q ;
  wire \U1/U3/holdingreg1<12>_MC.D ;
  wire \U1/U3/holdingreg1<12>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ;
  wire \U1/U3/holdingreg1<12>_MC.D1 ;
  wire \U1/U3/holdingreg1<12>_MC.D2 ;
  wire \U1/U3/holdingreg1<12>_MC.D2_PT_0 ;
  wire \U1/U3/holdingreg1<12>_MC.D2_PT_1 ;
  wire \outDATA<5>\$WA0.UIM_MC.Q ;
  wire \outDATA<5>\$WA0.UIM_MC.D ;
  wire \outDATA<5>\$WA0.UIM_MC.D1 ;
  wire \outDATA<5>\$WA0.UIM_MC.D2 ;
  wire \outDATA<5>\$WA1.UIM_MC.Q ;
  wire \outDATA<5>\$WA1.UIM_MC.D ;
  wire \outDATA<5>\$WA1.UIM_MC.D1 ;
  wire \outDATA<5>\$WA1.UIM_MC.D2 ;
  wire \outDATA<5>\$WA2.UIM_MC.Q ;
  wire \outDATA<5>\$WA2.UIM_MC.D ;
  wire \outDATA<5>\$WA2.UIM_MC.D1 ;
  wire \outDATA<5>\$WA2.UIM_MC.D2 ;
  wire \outDATA<5>\$WA3.UIM_MC.Q ;
  wire \outDATA<5>\$WA3.UIM_MC.D ;
  wire \outDATA<5>\$WA3.UIM_MC.D1 ;
  wire \outDATA<5>\$WA3.UIM_MC.D2 ;
  wire \outDATA<5>\$WA3.UIM_MC.D2_PT_0 ;
  wire \outDATA<5>\$WA3.UIM_MC.D2_PT_1 ;
  wire \outDATA<5>\$WA5.UIM_MC.Q ;
  wire \outDATA<5>\$WA5.UIM_MC.D ;
  wire \outDATA<5>\$WA5.UIM_MC.D1 ;
  wire \outDATA<5>\$WA5.UIM_MC.D2 ;
  wire \outDATA<5>\$WA5.UIM_MC.D2_PT_0 ;
  wire \outDATA<5>\$WA5.UIM_MC.D2_PT_1 ;
  wire \outDATA<5>\$WA5.UIM_MC.D2_PT_2 ;
  wire \outDATA<5>\$WA5.UIM_MC.D2_PT_3 ;
  wire \U1/U3/holdingreg0<5>_MC.Q ;
  wire \U1/U3/holdingreg0<5>_MC.D ;
  wire \U1/U3/holdingreg0<5>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ;
  wire \U1/U3/holdingreg0<5>_MC.D1 ;
  wire \U1/U3/holdingreg0<5>_MC.D2 ;
  wire \U1/U3/holdingreg0<5>_MC.D2_PT_0 ;
  wire \U1/U3/holdingreg0<5>_MC.D2_PT_1 ;
  wire \U1/U3/holdingreg1<5>_MC.Q ;
  wire \U1/U3/holdingreg1<5>_MC.D ;
  wire \U1/U3/holdingreg1<5>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ;
  wire \U1/U3/holdingreg1<5>_MC.D1 ;
  wire \U1/U3/holdingreg1<5>_MC.D2 ;
  wire \U1/U3/holdingreg1<5>_MC.D2_PT_0 ;
  wire \U1/U3/holdingreg1<5>_MC.D2_PT_1 ;
  wire \U1/U3/holdingreg0<13>_MC.Q ;
  wire \U1/U3/holdingreg0<13>_MC.D ;
  wire \U1/U3/holdingreg0<13>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ;
  wire \U1/U3/holdingreg0<13>_MC.D1 ;
  wire \U1/U3/holdingreg0<13>_MC.D2 ;
  wire \U1/U3/holdingreg0<13>_MC.D2_PT_0 ;
  wire \U1/U3/holdingreg0<13>_MC.D2_PT_1 ;
  wire \U1/Channel0<13>_MC.Q ;
  wire \U1/Channel0<13>_MC.D ;
  wire \U1/Channel0<13>_MC_tsimcreated_xor_ ;
  wire \U1/Channel0<13>_MC.D1 ;
  wire \U1/Channel0<13>_MC.D2 ;
  wire \U1/Channel0<13>_MC.D2_PT_0 ;
  wire \U1/Channel0<13>_MC.D2_PT_1 ;
  wire \U1/Channel0<13>_MC.D2_PT_2 ;
  wire \U1/U3/holdingreg1<13>_MC.Q ;
  wire \U1/U3/holdingreg1<13>_MC.D ;
  wire \U1/U3/holdingreg1<13>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ;
  wire \U1/U3/holdingreg1<13>_MC.D1 ;
  wire \U1/U3/holdingreg1<13>_MC.D2 ;
  wire \U1/U3/holdingreg1<13>_MC.D2_PT_0 ;
  wire \U1/U3/holdingreg1<13>_MC.D2_PT_1 ;
  wire \U1/Channel1<13>_MC.Q ;
  wire \U1/Channel1<13>_MC.D ;
  wire \U1/Channel1<13>_MC_tsimcreated_xor_ ;
  wire \U1/Channel1<13>_MC.D1 ;
  wire \U1/Channel1<13>_MC.D2 ;
  wire \U1/Channel1<13>_MC.D2_PT_0 ;
  wire \U1/Channel1<13>_MC.D2_PT_1 ;
  wire \U1/Channel1<13>_MC.D2_PT_2 ;
  wire \outDATA<5>\$WA6.UIM_MC.Q ;
  wire \outDATA<5>\$WA6.UIM_MC.D ;
  wire \outDATA<5>\$WA6.UIM_MC.D1 ;
  wire \outDATA<5>\$WA6.UIM_MC.D2 ;
  wire \outDATA<5>\$WA6.UIM_MC.D2_PT_0 ;
  wire \outDATA<5>\$WA6.UIM_MC.D2_PT_1 ;
  wire \outDATA<5>\$WA6.UIM_MC.D2_PT_2 ;
  wire \outDATA<5>\$WA6.UIM_MC.D2_PT_3 ;
  wire \outDATA<5>\$WA6.UIM_MC.D2_PT_4 ;
  wire \U1/U4/Latch0r<5>_MC.Q ;
  wire \U1/U4/Latch0r<5>_MC.D ;
  wire \U1/U4/Latch0r<5>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ;
  wire \U1/U4/Latch0r<5>_MC.D1 ;
  wire \U1/U4/Latch0r<5>_MC.D2 ;
  wire \U1/U4/Latch0r<5>_MC.D2_PT_0 ;
  wire \U1/U4/Latch0r<5>_MC.D2_PT_1 ;
  wire \U1/U4/Latch0r<13>_MC.Q ;
  wire \U1/U4/Latch0r<13>_MC.D ;
  wire \U1/U4/Latch0r<13>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ;
  wire \U1/U4/Latch0r<13>_MC.D1 ;
  wire \U1/U4/Latch0r<13>_MC.D2 ;
  wire \U1/U4/Latch0r<13>_MC.D2_PT_0 ;
  wire \U1/U4/Latch0r<13>_MC.D2_PT_1 ;
  wire \U1/U4/Latch1r<5>_MC.Q ;
  wire \U1/U4/Latch1r<5>_MC.D ;
  wire \U1/U4/Latch1r<5>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ;
  wire \U1/U4/Latch1r<5>_MC.D1 ;
  wire \U1/U4/Latch1r<5>_MC.D2 ;
  wire \U1/U4/Latch1r<5>_MC.D2_PT_0 ;
  wire \U1/U4/Latch1r<5>_MC.D2_PT_1 ;
  wire \U1/U4/Latch1r<13>_MC.Q ;
  wire \U1/U4/Latch1r<13>_MC.D ;
  wire \U1/U4/Latch1r<13>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ;
  wire \U1/U4/Latch1r<13>_MC.D1 ;
  wire \U1/U4/Latch1r<13>_MC.D2 ;
  wire \U1/U4/Latch1r<13>_MC.D2_PT_0 ;
  wire \U1/U4/Latch1r<13>_MC.D2_PT_1 ;
  wire \outDATA<6>\$WA0.UIM_MC.Q ;
  wire \outDATA<6>\$WA0.UIM_MC.D ;
  wire \outDATA<6>\$WA0.UIM_MC.D1 ;
  wire \outDATA<6>\$WA0.UIM_MC.D2 ;
  wire \outDATA<6>\$WA2.UIM_MC.Q ;
  wire \outDATA<6>\$WA2.UIM_MC.D ;
  wire \outDATA<6>\$WA2.UIM_MC.D1 ;
  wire \outDATA<6>\$WA2.UIM_MC.D2 ;
  wire \outDATA<6>\$WA3.UIM_MC.Q ;
  wire \outDATA<6>\$WA3.UIM_MC.D ;
  wire \outDATA<6>\$WA3.UIM_MC.D1 ;
  wire \outDATA<6>\$WA3.UIM_MC.D2 ;
  wire \outDATA<6>\$WA3.UIM_MC.D2_PT_0 ;
  wire \outDATA<6>\$WA3.UIM_MC.D2_PT_1 ;
  wire \outDATA<6>\$WA5.UIM_MC.Q ;
  wire \outDATA<6>\$WA5.UIM_MC.D ;
  wire \outDATA<6>\$WA5.UIM_MC.D1 ;
  wire \outDATA<6>\$WA5.UIM_MC.D2 ;
  wire \outDATA<6>\$WA5.UIM_MC.D2_PT_0 ;
  wire \outDATA<6>\$WA5.UIM_MC.D2_PT_1 ;
  wire \outDATA<6>\$WA5.UIM_MC.D2_PT_2 ;
  wire \outDATA<6>\$WA5.UIM_MC.D2_PT_3 ;
  wire \U1/U3/holdingreg0<6>_MC.Q ;
  wire \U1/U3/holdingreg0<6>_MC.D ;
  wire \U1/U3/holdingreg0<6>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ;
  wire \U1/U3/holdingreg0<6>_MC.D1 ;
  wire \U1/U3/holdingreg0<6>_MC.D2 ;
  wire \U1/U3/holdingreg0<6>_MC.D2_PT_0 ;
  wire \U1/U3/holdingreg0<6>_MC.D2_PT_1 ;
  wire \U1/U3/holdingreg1<6>_MC.Q ;
  wire \U1/U3/holdingreg1<6>_MC.D ;
  wire \U1/U3/holdingreg1<6>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ;
  wire \U1/U3/holdingreg1<6>_MC.D1 ;
  wire \U1/U3/holdingreg1<6>_MC.D2 ;
  wire \U1/U3/holdingreg1<6>_MC.D2_PT_0 ;
  wire \U1/U3/holdingreg1<6>_MC.D2_PT_1 ;
  wire \U1/U3/holdingreg0<14>_MC.Q ;
  wire \U1/U3/holdingreg0<14>_MC.D ;
  wire \U1/U3/holdingreg0<14>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ;
  wire \U1/U3/holdingreg0<14>_MC.D1 ;
  wire \U1/U3/holdingreg0<14>_MC.D2 ;
  wire \U1/U3/holdingreg0<14>_MC.D2_PT_0 ;
  wire \U1/U3/holdingreg0<14>_MC.D2_PT_1 ;
  wire \U1/Channel0<14>_MC.Q ;
  wire \U1/Channel0<14>_MC.D ;
  wire \U1/Channel0<14>_MC_tsimcreated_xor_ ;
  wire \U1/Channel0<14>_MC.D1 ;
  wire \U1/Channel0<14>_MC.D2 ;
  wire \U1/Channel0<14>_MC.D2_PT_0 ;
  wire \U1/Channel0<14>_MC.D2_PT_1 ;
  wire \U1/Channel0<14>_MC.D2_PT_2 ;
  wire \U1/U3/holdingreg1<14>_MC.Q ;
  wire \U1/U3/holdingreg1<14>_MC.D ;
  wire \U1/U3/holdingreg1<14>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ;
  wire \U1/U3/holdingreg1<14>_MC.D1 ;
  wire \U1/U3/holdingreg1<14>_MC.D2 ;
  wire \U1/U3/holdingreg1<14>_MC.D2_PT_0 ;
  wire \U1/U3/holdingreg1<14>_MC.D2_PT_1 ;
  wire \U1/Channel1<14>_MC.Q ;
  wire \U1/Channel1<14>_MC.D ;
  wire \U1/Channel1<14>_MC_tsimcreated_xor_ ;
  wire \U1/Channel1<14>_MC.D1 ;
  wire \U1/Channel1<14>_MC.D2 ;
  wire \U1/Channel1<14>_MC.D2_PT_0 ;
  wire \U1/Channel1<14>_MC.D2_PT_1 ;
  wire \U1/Channel1<14>_MC.D2_PT_2 ;
  wire \outDATA<6>\$WA6.UIM_MC.Q ;
  wire \outDATA<6>\$WA6.UIM_MC.D ;
  wire \outDATA<6>\$WA6.UIM_MC.D1 ;
  wire \outDATA<6>\$WA6.UIM_MC.D2 ;
  wire \outDATA<6>\$WA6.UIM_MC.D2_PT_0 ;
  wire \outDATA<6>\$WA6.UIM_MC.D2_PT_1 ;
  wire \outDATA<6>\$WA6.UIM_MC.D2_PT_2 ;
  wire \outDATA<6>\$WA6.UIM_MC.D2_PT_3 ;
  wire \outDATA<6>\$WA6.UIM_MC.D2_PT_4 ;
  wire \U1/U4/Latch0r<6>_MC.Q ;
  wire \U1/U4/Latch0r<6>_MC.D ;
  wire \U1/U4/Latch0r<6>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ;
  wire \U1/U4/Latch0r<6>_MC.D1 ;
  wire \U1/U4/Latch0r<6>_MC.D2 ;
  wire \U1/U4/Latch0r<6>_MC.D2_PT_0 ;
  wire \U1/U4/Latch0r<6>_MC.D2_PT_1 ;
  wire \U1/U4/Latch0r<14>_MC.Q ;
  wire \U1/U4/Latch0r<14>_MC.D ;
  wire \U1/U4/Latch0r<14>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ;
  wire \U1/U4/Latch0r<14>_MC.D1 ;
  wire \U1/U4/Latch0r<14>_MC.D2 ;
  wire \U1/U4/Latch0r<14>_MC.D2_PT_0 ;
  wire \U1/U4/Latch0r<14>_MC.D2_PT_1 ;
  wire \U1/U4/Latch1r<6>_MC.Q ;
  wire \U1/U4/Latch1r<6>_MC.D ;
  wire \U1/U4/Latch1r<6>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ;
  wire \U1/U4/Latch1r<6>_MC.D1 ;
  wire \U1/U4/Latch1r<6>_MC.D2 ;
  wire \U1/U4/Latch1r<6>_MC.D2_PT_0 ;
  wire \U1/U4/Latch1r<6>_MC.D2_PT_1 ;
  wire \U1/U4/Latch1r<14>_MC.Q ;
  wire \U1/U4/Latch1r<14>_MC.D ;
  wire \U1/U4/Latch1r<14>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ;
  wire \U1/U4/Latch1r<14>_MC.D1 ;
  wire \U1/U4/Latch1r<14>_MC.D2 ;
  wire \U1/U4/Latch1r<14>_MC.D2_PT_0 ;
  wire \U1/U4/Latch1r<14>_MC.D2_PT_1 ;
  wire \outDATA<7>\$WA0.UIM_MC.Q ;
  wire \outDATA<7>\$WA0.UIM_MC.D ;
  wire \outDATA<7>\$WA0.UIM_MC.D1 ;
  wire \outDATA<7>\$WA0.UIM_MC.D2 ;
  wire \outDATA<7>\$WA1.UIM_MC.Q ;
  wire \outDATA<7>\$WA1.UIM_MC.D ;
  wire \outDATA<7>\$WA1.UIM_MC.D1 ;
  wire \outDATA<7>\$WA1.UIM_MC.D2 ;
  wire \outDATA<7>\$WA2.UIM_MC.Q ;
  wire \outDATA<7>\$WA2.UIM_MC.D ;
  wire \outDATA<7>\$WA2.UIM_MC.D1 ;
  wire \outDATA<7>\$WA2.UIM_MC.D2 ;
  wire \outDATA<7>\$WA3.UIM_MC.Q ;
  wire \outDATA<7>\$WA3.UIM_MC.D ;
  wire \outDATA<7>\$WA3.UIM_MC.D1 ;
  wire \outDATA<7>\$WA3.UIM_MC.D2 ;
  wire \outDATA<7>\$WA3.UIM_MC.D2_PT_0 ;
  wire \outDATA<7>\$WA3.UIM_MC.D2_PT_1 ;
  wire \outDATA<7>\$WA6.UIM_MC.Q ;
  wire \outDATA<7>\$WA6.UIM_MC.D ;
  wire \outDATA<7>\$WA6.UIM_MC.D1 ;
  wire \outDATA<7>\$WA6.UIM_MC.D2 ;
  wire \outDATA<7>\$WA6.UIM_MC.D2_PT_0 ;
  wire \outDATA<7>\$WA6.UIM_MC.D2_PT_1 ;
  wire \outDATA<7>\$WA6.UIM_MC.D2_PT_2 ;
  wire \outDATA<7>\$WA6.UIM_MC.D2_PT_3 ;
  wire \U1/U4/Latch0r<7>_MC.Q ;
  wire \U1/U4/Latch0r<7>_MC.D ;
  wire \U1/U4/Latch0r<7>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ;
  wire \U1/U4/Latch0r<7>_MC.D1 ;
  wire \U1/U4/Latch0r<7>_MC.D2 ;
  wire \U1/U4/Latch0r<7>_MC.D2_PT_0 ;
  wire \U1/U4/Latch0r<7>_MC.D2_PT_1 ;
  wire \U1/U4/Latch0r<15>_MC.Q ;
  wire \U1/U4/Latch0r<15>_MC.D ;
  wire \U1/U4/Latch0r<15>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ;
  wire \U1/U4/Latch0r<15>_MC.D1 ;
  wire \U1/U4/Latch0r<15>_MC.D2 ;
  wire \U1/U4/Latch0r<15>_MC.D2_PT_0 ;
  wire \U1/U4/Latch0r<15>_MC.D2_PT_1 ;
  wire \U1/Channel0<15>_MC.Q ;
  wire \U1/Channel0<15>_MC.D ;
  wire \U1/Channel0<15>_MC_tsimcreated_xor_ ;
  wire \U1/Channel0<15>_MC.D1 ;
  wire \U1/Channel0<15>_MC.D2 ;
  wire \U1/Channel0<15>_MC.D2_PT_0 ;
  wire \U1/Channel0<15>_MC.D2_PT_1 ;
  wire \U1/Channel0<15>_MC.D2_PT_2 ;
  wire \U1/U4/Latch1r<7>_MC.Q ;
  wire \U1/U4/Latch1r<7>_MC.D ;
  wire \U1/U4/Latch1r<7>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ;
  wire \U1/U4/Latch1r<7>_MC.D1 ;
  wire \U1/U4/Latch1r<7>_MC.D2 ;
  wire \U1/U4/Latch1r<7>_MC.D2_PT_0 ;
  wire \U1/U4/Latch1r<7>_MC.D2_PT_1 ;
  wire \U1/U4/Latch1r<15>_MC.Q ;
  wire \U1/U4/Latch1r<15>_MC.D ;
  wire \U1/U4/Latch1r<15>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ;
  wire \U1/U4/Latch1r<15>_MC.D1 ;
  wire \U1/U4/Latch1r<15>_MC.D2 ;
  wire \U1/U4/Latch1r<15>_MC.D2_PT_0 ;
  wire \U1/U4/Latch1r<15>_MC.D2_PT_1 ;
  wire \U1/Channel1<15>_MC.Q ;
  wire \U1/Channel1<15>_MC.D ;
  wire \U1/Channel1<15>_MC_tsimcreated_xor_ ;
  wire \U1/Channel1<15>_MC.D1 ;
  wire \U1/Channel1<15>_MC.D2 ;
  wire \U1/Channel1<15>_MC.D2_PT_0 ;
  wire \U1/Channel1<15>_MC.D2_PT_1 ;
  wire \U1/Channel1<15>_MC.D2_PT_2 ;
  wire \outDATA<7>\$WA5.UIM_MC.Q ;
  wire \outDATA<7>\$WA5.UIM_MC.D ;
  wire \outDATA<7>\$WA5.UIM_MC.D1 ;
  wire \outDATA<7>\$WA5.UIM_MC.D2 ;
  wire \outDATA<7>\$WA5.UIM_MC.D2_PT_0 ;
  wire \outDATA<7>\$WA5.UIM_MC.D2_PT_1 ;
  wire \outDATA<7>\$WA5.UIM_MC.D2_PT_2 ;
  wire \outDATA<7>\$WA5.UIM_MC.D2_PT_3 ;
  wire \U1/U3/holdingreg0<7>_MC.Q ;
  wire \U1/U3/holdingreg0<7>_MC.D ;
  wire \U1/U3/holdingreg0<7>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ;
  wire \U1/U3/holdingreg0<7>_MC.D1 ;
  wire \U1/U3/holdingreg0<7>_MC.D2 ;
  wire \U1/U3/holdingreg0<7>_MC.D2_PT_0 ;
  wire \U1/U3/holdingreg0<7>_MC.D2_PT_1 ;
  wire \U1/U3/holdingreg1<7>_MC.Q ;
  wire \U1/U3/holdingreg1<7>_MC.D ;
  wire \U1/U3/holdingreg1<7>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ;
  wire \U1/U3/holdingreg1<7>_MC.D1 ;
  wire \U1/U3/holdingreg1<7>_MC.D2 ;
  wire \U1/U3/holdingreg1<7>_MC.D2_PT_0 ;
  wire \U1/U3/holdingreg1<7>_MC.D2_PT_1 ;
  wire \U1/U3/holdingreg0<15>_MC.Q ;
  wire \U1/U3/holdingreg0<15>_MC.D ;
  wire \U1/U3/holdingreg0<15>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ;
  wire \U1/U3/holdingreg0<15>_MC.D1 ;
  wire \U1/U3/holdingreg0<15>_MC.D2 ;
  wire \U1/U3/holdingreg0<15>_MC.D2_PT_0 ;
  wire \U1/U3/holdingreg0<15>_MC.D2_PT_1 ;
  wire \U1/U3/holdingreg1<15>_MC.Q ;
  wire \U1/U3/holdingreg1<15>_MC.D ;
  wire \U1/U3/holdingreg1<15>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ;
  wire \U1/U3/holdingreg1<15>_MC.D1 ;
  wire \U1/U3/holdingreg1<15>_MC.D2 ;
  wire \U1/U3/holdingreg1<15>_MC.D2_PT_0 ;
  wire \U1/U3/holdingreg1<15>_MC.D2_PT_1 ;
  wire \NlwInverterSignal_Enc033ctrl_MC.D/IN0 ;
  wire \NlwInverterSignal_Enc033ctrl_MC.D1/IN1 ;
  wire \NlwInverterSignal_U4/ctrlr<2>_MC.D/IN0 ;
  wire \NlwInverterSignal_U4/ctrlr<2>_MC.D2_PT_0/IN1 ;
  wire \NlwInverterSignal_U4/ctrlr<2>_MC.D2_PT_1/IN1 ;
  wire \NlwInverterSignal_U4/ctrlr<2>_MC.D2_PT_2/IN1 ;
  wire \NlwInverterSignal_U4/ctrlr<2>_MC.D2_PT_3/IN1 ;
  wire \NlwInverterSignal_U4/ctrlr<2>_MC.D2_PT_4/IN0 ;
  wire \NlwInverterSignal_U4/ctrlr<2>_MC.D2_PT_4/IN1 ;
  wire \NlwInverterSignal_U4/ctrlr<2>_MC.D2_PT_5/IN0 ;
  wire \NlwInverterSignal_U4/ctrlr<2>_MC.D2_PT_5/IN1 ;
  wire \NlwInverterSignal_DCORENCPWRw_MC.D1/IN0 ;
  wire \NlwInverterSignal_DCORENCPWRw_MC.D1/IN2 ;
  wire \NlwInverterSignal_DCORENCPWRw_MC.D1/IN3 ;
  wire \NlwInverterSignal_DCORENCPWRw_MC.D1/IN4 ;
  wire \NlwInverterSignal_DCORENCPWRw_MC.D1/IN5 ;
  wire \NlwInverterSignal_DCORENCPWRw_MC.D1/IN6 ;
  wire \NlwInverterSignal_U2_ADDR_reg<0>_MC.D2_PT_0/IN1 ;
  wire \NlwInverterSignal_U2_ADDR_reg<0>_MC.D2_PT_1/IN3 ;
  wire \NlwInverterSignal_U2_ADDR_reg<0>_MC.D2_PT_1/IN4 ;
  wire \NlwInverterSignal_U2_ADDR_reg<0>_MC.D2_PT_2/IN2 ;
  wire \NlwInverterSignal_U2_ADDR_reg<0>_MC.D2_PT_2/IN5 ;
  wire \NlwInverterSignal_U2_ADDR_reg<0>_MC.D2_PT_3/IN2 ;
  wire \NlwInverterSignal_U2_ADDR_reg<0>_MC.D2_PT_3/IN3 ;
  wire \NlwInverterSignal_U2_ADDR_reg<0>_MC.D2_PT_3/IN4 ;
  wire \NlwInverterSignal_U2_ADDR_reg<0>_MC.D2_PT_3/IN5 ;
  wire \NlwInverterSignal_U2_ADDR_reg<0>_MC.D2_PT_3/IN7 ;
  wire \NlwInverterSignal_U2_ADDR_reg<4>_MC.D2_PT_0/IN1 ;
  wire \NlwInverterSignal_U2_ADDR_reg<4>_MC.D2_PT_1/IN3 ;
  wire \NlwInverterSignal_U2_ADDR_reg<4>_MC.D2_PT_1/IN5 ;
  wire \NlwInverterSignal_U2_ADDR_reg<4>_MC.D2_PT_2/IN2 ;
  wire \NlwInverterSignal_U2_ADDR_reg<4>_MC.D2_PT_2/IN4 ;
  wire \NlwInverterSignal_U2_ADDR_reg<5>_MC.D2_PT_0/IN1 ;
  wire \NlwInverterSignal_U2_ADDR_reg<5>_MC.D2_PT_1/IN3 ;
  wire \NlwInverterSignal_U2_ADDR_reg<5>_MC.D2_PT_1/IN5 ;
  wire \NlwInverterSignal_U2_ADDR_reg<5>_MC.D2_PT_2/IN2 ;
  wire \NlwInverterSignal_U2_ADDR_reg<5>_MC.D2_PT_2/IN4 ;
  wire \NlwInverterSignal_U2_ADDR_reg<6>_MC.D2_PT_0/IN1 ;
  wire \NlwInverterSignal_U2_ADDR_reg<6>_MC.D2_PT_1/IN3 ;
  wire \NlwInverterSignal_U2_ADDR_reg<6>_MC.D2_PT_1/IN5 ;
  wire \NlwInverterSignal_U2_ADDR_reg<6>_MC.D2_PT_2/IN2 ;
  wire \NlwInverterSignal_U2_ADDR_reg<6>_MC.D2_PT_2/IN4 ;
  wire \NlwInverterSignal_U2_ADDR_reg<7>_MC.D2_PT_0/IN1 ;
  wire \NlwInverterSignal_U2_ADDR_reg<7>_MC.D2_PT_1/IN3 ;
  wire \NlwInverterSignal_U2_ADDR_reg<7>_MC.D2_PT_1/IN5 ;
  wire \NlwInverterSignal_U2_ADDR_reg<7>_MC.D2_PT_2/IN2 ;
  wire \NlwInverterSignal_U2_ADDR_reg<7>_MC.D2_PT_2/IN4 ;
  wire \NlwInverterSignal_U2_AutoInc_MC.D/IN0 ;
  wire \NlwInverterSignal_N_PZ_941_MC.D2_PT_1/IN1 ;
  wire \NlwInverterSignal_U2_ADDR_reg<3>_MC.D2_PT_0/IN1 ;
  wire \NlwInverterSignal_U2_ADDR_reg<3>_MC.D2_PT_1/IN3 ;
  wire \NlwInverterSignal_U2_ADDR_reg<3>_MC.D2_PT_1/IN5 ;
  wire \NlwInverterSignal_U2_ADDR_reg<3>_MC.D2_PT_2/IN2 ;
  wire \NlwInverterSignal_U2_ADDR_reg<3>_MC.D2_PT_2/IN4 ;
  wire \NlwInverterSignal_U2_ADDR_reg<3>_MC.D2_PT_3/IN3 ;
  wire \NlwInverterSignal_U2_ADDR_reg<3>_MC.D2_PT_3/IN4 ;
  wire \NlwInverterSignal_U2_ADDR_reg<3>_MC.D2_PT_3/IN5 ;
  wire \NlwInverterSignal_U2_ADDR_reg<3>_MC.D2_PT_3/IN6 ;
  wire \NlwInverterSignal_U2_ADDR_reg<3>_MC.D2_PT_3/IN10 ;
  wire \NlwInverterSignal_U2_ADDR_reg<1>_MC.D2_PT_0/IN1 ;
  wire \NlwInverterSignal_U2_ADDR_reg<1>_MC.D2_PT_1/IN3 ;
  wire \NlwInverterSignal_U2_ADDR_reg<1>_MC.D2_PT_1/IN5 ;
  wire \NlwInverterSignal_U2_ADDR_reg<1>_MC.D2_PT_2/IN2 ;
  wire \NlwInverterSignal_U2_ADDR_reg<1>_MC.D2_PT_2/IN4 ;
  wire \NlwInverterSignal_U2_ADDR_reg<1>_MC.D2_PT_3/IN3 ;
  wire \NlwInverterSignal_U2_ADDR_reg<1>_MC.D2_PT_3/IN4 ;
  wire \NlwInverterSignal_U2_ADDR_reg<1>_MC.D2_PT_3/IN5 ;
  wire \NlwInverterSignal_U2_ADDR_reg<1>_MC.D2_PT_3/IN6 ;
  wire \NlwInverterSignal_U2_ADDR_reg<1>_MC.D2_PT_3/IN8 ;
  wire \NlwInverterSignal_U2_ADDR_reg<2>_MC.D2_PT_0/IN1 ;
  wire \NlwInverterSignal_U2_ADDR_reg<2>_MC.D2_PT_1/IN3 ;
  wire \NlwInverterSignal_U2_ADDR_reg<2>_MC.D2_PT_1/IN5 ;
  wire \NlwInverterSignal_U2_ADDR_reg<2>_MC.D2_PT_2/IN2 ;
  wire \NlwInverterSignal_U2_ADDR_reg<2>_MC.D2_PT_2/IN4 ;
  wire \NlwInverterSignal_U2_ADDR_reg<2>_MC.D2_PT_3/IN3 ;
  wire \NlwInverterSignal_U2_ADDR_reg<2>_MC.D2_PT_3/IN4 ;
  wire \NlwInverterSignal_U2_ADDR_reg<2>_MC.D2_PT_3/IN5 ;
  wire \NlwInverterSignal_U2_ADDR_reg<2>_MC.D2_PT_3/IN6 ;
  wire \NlwInverterSignal_U2_ADDR_reg<2>_MC.D2_PT_3/IN9 ;
  wire \NlwInverterSignal_U2_Enable_AD_MC.D1/IN1 ;
  wire \NlwInverterSignal_U2_Enable_AD_MC.D1/IN2 ;
  wire \NlwInverterSignal_U2_Enable_AD_MC.D1/IN3 ;
  wire \NlwInverterSignal_U2_Enable_AD_MC.D1/IN4 ;
  wire \NlwInverterSignal_U2_Enable_AD_MC.D1/IN5 ;
  wire \NlwInverterSignal_U4/ctrlr<3>_MC.D/IN0 ;
  wire \NlwInverterSignal_U4/ctrlr<3>_MC.D2_PT_0/IN1 ;
  wire \NlwInverterSignal_U4/ctrlr<3>_MC.D2_PT_1/IN1 ;
  wire \NlwInverterSignal_U4/ctrlr<3>_MC.D2_PT_2/IN1 ;
  wire \NlwInverterSignal_U4/ctrlr<3>_MC.D2_PT_3/IN1 ;
  wire \NlwInverterSignal_U4/ctrlr<3>_MC.D2_PT_4/IN0 ;
  wire \NlwInverterSignal_U4/ctrlr<3>_MC.D2_PT_4/IN1 ;
  wire \NlwInverterSignal_U4/ctrlr<3>_MC.D2_PT_5/IN0 ;
  wire \NlwInverterSignal_U4/ctrlr<3>_MC.D2_PT_5/IN1 ;
  wire \NlwInverterSignal_Enc05ctrl_MC.D/IN0 ;
  wire \NlwInverterSignal_Enc05ctrl_MC.D1/IN0 ;
  wire \NlwInverterSignal_Enc133ctrl_MC.D/IN0 ;
  wire \NlwInverterSignal_U4/ctrlr<6>_MC.D/IN0 ;
  wire \NlwInverterSignal_U4/ctrlr<6>_MC.D2_PT_0/IN1 ;
  wire \NlwInverterSignal_U4/ctrlr<6>_MC.D2_PT_1/IN1 ;
  wire \NlwInverterSignal_U4/ctrlr<6>_MC.D2_PT_2/IN1 ;
  wire \NlwInverterSignal_U4/ctrlr<6>_MC.D2_PT_3/IN1 ;
  wire \NlwInverterSignal_U4/ctrlr<6>_MC.D2_PT_4/IN0 ;
  wire \NlwInverterSignal_U4/ctrlr<6>_MC.D2_PT_4/IN1 ;
  wire \NlwInverterSignal_U4/ctrlr<6>_MC.D2_PT_5/IN0 ;
  wire \NlwInverterSignal_U4/ctrlr<6>_MC.D2_PT_5/IN1 ;
  wire \NlwInverterSignal_U4/ctrlr<7>_MC.D/IN0 ;
  wire \NlwInverterSignal_U4/ctrlr<7>_MC.D2_PT_0/IN1 ;
  wire \NlwInverterSignal_U4/ctrlr<7>_MC.D2_PT_1/IN1 ;
  wire \NlwInverterSignal_U4/ctrlr<7>_MC.D2_PT_2/IN1 ;
  wire \NlwInverterSignal_U4/ctrlr<7>_MC.D2_PT_3/IN1 ;
  wire \NlwInverterSignal_U4/ctrlr<7>_MC.D2_PT_4/IN0 ;
  wire \NlwInverterSignal_U4/ctrlr<7>_MC.D2_PT_4/IN1 ;
  wire \NlwInverterSignal_U4/ctrlr<7>_MC.D2_PT_5/IN0 ;
  wire \NlwInverterSignal_U4/ctrlr<7>_MC.D2_PT_6/IN1 ;
  wire \NlwInverterSignal_U4/ctrlr<7>_MC.D2_PT_7/IN0 ;
  wire \NlwInverterSignal_U4/ctrlr<7>_MC.D2_PT_7/IN1 ;
  wire \NlwInverterSignal_U4/ctrlr<7>_MC.D2_PT_7/IN2 ;
  wire \NlwInverterSignal_Enc15ctrl_MC.D/IN0 ;
  wire \NlwInverterSignal_Enc15ctrl_MC.D1/IN0 ;
  wire \NlwInverterSignal_DCOROUTw_MC.D1/IN0 ;
  wire \NlwInverterSignal_DCOROUTw_MC.D1/IN3 ;
  wire \NlwInverterSignal_DCOROUTw_MC.D1/IN4 ;
  wire \NlwInverterSignal_DCOROUTw_MC.D1/IN5 ;
  wire \NlwInverterSignal_DCOROUTw_MC.D1/IN6 ;
  wire \NlwInverterSignal_Home033ctrl_MC.D/IN0 ;
  wire \NlwInverterSignal_Home033ctrl_MC.D1/IN1 ;
  wire \NlwInverterSignal_U4/ctrlr<0>_MC.D/IN0 ;
  wire \NlwInverterSignal_U4/ctrlr<0>_MC.D2_PT_0/IN1 ;
  wire \NlwInverterSignal_U4/ctrlr<0>_MC.D2_PT_1/IN1 ;
  wire \NlwInverterSignal_U4/ctrlr<0>_MC.D2_PT_2/IN1 ;
  wire \NlwInverterSignal_U4/ctrlr<0>_MC.D2_PT_3/IN1 ;
  wire \NlwInverterSignal_U4/ctrlr<0>_MC.D2_PT_4/IN0 ;
  wire \NlwInverterSignal_U4/ctrlr<0>_MC.D2_PT_4/IN1 ;
  wire \NlwInverterSignal_U4/ctrlr<0>_MC.D2_PT_5/IN1 ;
  wire \NlwInverterSignal_U4/ctrlr<0>_MC.D2_PT_6/IN1 ;
  wire \NlwInverterSignal_U4/ctrlr<0>_MC.D2_PT_7/IN0 ;
  wire \NlwInverterSignal_U4/ctrlr<0>_MC.D2_PT_7/IN1 ;
  wire \NlwInverterSignal_U4/ctrlr<0>_MC.D2_PT_7/IN2 ;
  wire \NlwInverterSignal_U4/ctrlr<1>_MC.D/IN0 ;
  wire \NlwInverterSignal_U4/ctrlr<1>_MC.D2_PT_0/IN1 ;
  wire \NlwInverterSignal_U4/ctrlr<1>_MC.D2_PT_1/IN1 ;
  wire \NlwInverterSignal_U4/ctrlr<1>_MC.D2_PT_2/IN1 ;
  wire \NlwInverterSignal_U4/ctrlr<1>_MC.D2_PT_3/IN1 ;
  wire \NlwInverterSignal_U4/ctrlr<1>_MC.D2_PT_4/IN0 ;
  wire \NlwInverterSignal_U4/ctrlr<1>_MC.D2_PT_4/IN1 ;
  wire \NlwInverterSignal_U4/ctrlr<1>_MC.D2_PT_5/IN1 ;
  wire \NlwInverterSignal_U4/ctrlr<1>_MC.D2_PT_6/IN1 ;
  wire \NlwInverterSignal_U4/ctrlr<1>_MC.D2_PT_7/IN0 ;
  wire \NlwInverterSignal_U4/ctrlr<1>_MC.D2_PT_7/IN1 ;
  wire \NlwInverterSignal_U4/ctrlr<1>_MC.D2_PT_7/IN2 ;
  wire \NlwInverterSignal_Home05ctrl_MC.D/IN0 ;
  wire \NlwInverterSignal_Home05ctrl_MC.D1/IN0 ;
  wire \NlwInverterSignal_Home133ctrl_MC.D/IN0 ;
  wire \NlwInverterSignal_Home133ctrl_MC.D1/IN1 ;
  wire \NlwInverterSignal_U4/ctrlr<4>_MC.D/IN0 ;
  wire \NlwInverterSignal_U4/ctrlr<4>_MC.D2_PT_0/IN1 ;
  wire \NlwInverterSignal_U4/ctrlr<4>_MC.D2_PT_1/IN1 ;
  wire \NlwInverterSignal_U4/ctrlr<4>_MC.D2_PT_2/IN1 ;
  wire \NlwInverterSignal_U4/ctrlr<4>_MC.D2_PT_3/IN1 ;
  wire \NlwInverterSignal_U4/ctrlr<4>_MC.D2_PT_4/IN0 ;
  wire \NlwInverterSignal_U4/ctrlr<4>_MC.D2_PT_4/IN1 ;
  wire \NlwInverterSignal_U4/ctrlr<4>_MC.D2_PT_5/IN1 ;
  wire \NlwInverterSignal_U4/ctrlr<4>_MC.D2_PT_6/IN1 ;
  wire \NlwInverterSignal_U4/ctrlr<4>_MC.D2_PT_7/IN0 ;
  wire \NlwInverterSignal_U4/ctrlr<4>_MC.D2_PT_7/IN1 ;
  wire \NlwInverterSignal_U4/ctrlr<4>_MC.D2_PT_7/IN2 ;
  wire \NlwInverterSignal_U4/ctrlr<5>_MC.D/IN0 ;
  wire \NlwInverterSignal_U4/ctrlr<5>_MC.D2_PT_0/IN1 ;
  wire \NlwInverterSignal_U4/ctrlr<5>_MC.D2_PT_1/IN1 ;
  wire \NlwInverterSignal_U4/ctrlr<5>_MC.D2_PT_2/IN1 ;
  wire \NlwInverterSignal_U4/ctrlr<5>_MC.D2_PT_3/IN1 ;
  wire \NlwInverterSignal_U4/ctrlr<5>_MC.D2_PT_4/IN0 ;
  wire \NlwInverterSignal_U4/ctrlr<5>_MC.D2_PT_4/IN1 ;
  wire \NlwInverterSignal_U4/ctrlr<5>_MC.D2_PT_5/IN0 ;
  wire \NlwInverterSignal_U4/ctrlr<5>_MC.D2_PT_5/IN1 ;
  wire \NlwInverterSignal_Home15ctrl_MC.D/IN0 ;
  wire \NlwInverterSignal_Home15ctrl_MC.D1/IN0 ;
  wire \NlwInverterSignal_INT_MC.D2_PT_0/IN0 ;
  wire \NlwInverterSignal_U3/DCORIE<0>_MC.D2_PT_1/IN2 ;
  wire \NlwInverterSignal_DCORIEw_MC.D1/IN0 ;
  wire \NlwInverterSignal_DCORIEw_MC.D1/IN2 ;
  wire \NlwInverterSignal_DCORIEw_MC.D1/IN3 ;
  wire \NlwInverterSignal_DCORIEw_MC.D1/IN4 ;
  wire \NlwInverterSignal_DCORIEw_MC.D1/IN5 ;
  wire \NlwInverterSignal_DCORIEw_MC.D1/IN6 ;
  wire \NlwInverterSignal_DCORIEw_MC.D1/IN7 ;
  wire \NlwInverterSignal_DCORIEw_MC.D1/IN8 ;
  wire \NlwInverterSignal_DCORIEw_MC.D1/IN9 ;
  wire \NlwInverterSignal_NET2528_MC.D1/IN1 ;
  wire \NlwInverterSignal_NET2528_MC.D2_PT_0/IN1 ;
  wire \NlwInverterSignal_NET2528_MC.D2_PT_1/IN1 ;
  wire \NlwInverterSignal_NET2528_MC.D2_PT_1/IN2 ;
  wire \NlwInverterSignal_DCORIFGw_MC.D1/IN0 ;
  wire \NlwInverterSignal_DCORIFGw_MC.D1/IN3 ;
  wire \NlwInverterSignal_DCORIFGw_MC.D1/IN4 ;
  wire \NlwInverterSignal_DCORIFGw_MC.D1/IN5 ;
  wire \NlwInverterSignal_DCORIFGw_MC.D1/IN6 ;
  wire \NlwInverterSignal_DCORIFGw_MC.D1/IN7 ;
  wire \NlwInverterSignal_DCORIFGw_MC.D1/IN8 ;
  wire \NlwInverterSignal_DCORIFGw_MC.D1/IN9 ;
  wire \NlwInverterSignal_U3/DCORIE<1>_MC.D2_PT_1/IN2 ;
  wire \NlwInverterSignal_NET2482_MC.D2_PT_0/IN0 ;
  wire \NlwInverterSignal_NET2482_MC.D2_PT_1/IN3 ;
  wire \NlwInverterSignal_NET2482_MC.D2_PT_2/IN1 ;
  wire \NlwInverterSignal_NET2482_MC.D2_PT_2/IN2 ;
  wire \NlwInverterSignal_NET2482_MC.D2_PT_2/IN3 ;
  wire \NlwInverterSignal_NET2482_MC.D2_PT_2/IN7 ;
  wire \NlwInverterSignal_NET2482_MC.D2_PT_3/IN1 ;
  wire \NlwInverterSignal_NET2482_MC.D2_PT_3/IN2 ;
  wire \NlwInverterSignal_NET2482_MC.D2_PT_3/IN3 ;
  wire \NlwInverterSignal_NET2482_MC.D2_PT_3/IN4 ;
  wire \NlwInverterSignal_NET2482_MC.D2_PT_3/IN6 ;
  wire \NlwInverterSignal_DCORENCCTLw_MC.D1/IN0 ;
  wire \NlwInverterSignal_DCORENCCTLw_MC.D1/IN3 ;
  wire \NlwInverterSignal_DCORENCCTLw_MC.D1/IN4 ;
  wire \NlwInverterSignal_DCORENCCTLw_MC.D1/IN5 ;
  wire \NlwInverterSignal_DCORENCCTLw_MC.D1/IN6 ;
  wire \NlwInverterSignal_DCORENCCTLw_MC.D1/IN7 ;
  wire \NlwInverterSignal_DCORENCCTLw_MC.D1/IN9 ;
  wire \NlwInverterSignal_U1/U4/RF0r_MC.D2_PT_1/IN1 ;
  wire \NlwInverterSignal_U1/U4/E0r_MC.D2_PT_1/IN1 ;
  wire \NlwInverterSignal_U3/DCORIE<2>_MC.D2_PT_1/IN2 ;
  wire \NlwInverterSignal_NET2493_MC.D2_PT_0/IN0 ;
  wire \NlwInverterSignal_NET2493_MC.D2_PT_1/IN3 ;
  wire \NlwInverterSignal_NET2493_MC.D2_PT_2/IN1 ;
  wire \NlwInverterSignal_NET2493_MC.D2_PT_2/IN2 ;
  wire \NlwInverterSignal_NET2493_MC.D2_PT_2/IN3 ;
  wire \NlwInverterSignal_NET2493_MC.D2_PT_2/IN7 ;
  wire \NlwInverterSignal_NET2493_MC.D2_PT_3/IN1 ;
  wire \NlwInverterSignal_NET2493_MC.D2_PT_3/IN2 ;
  wire \NlwInverterSignal_NET2493_MC.D2_PT_3/IN3 ;
  wire \NlwInverterSignal_NET2493_MC.D2_PT_3/IN4 ;
  wire \NlwInverterSignal_NET2493_MC.D2_PT_3/IN6 ;
  wire \NlwInverterSignal_U1/U4/RF1r_MC.D2_PT_1/IN1 ;
  wire \NlwInverterSignal_U1/U4/E1r_MC.D2_PT_1/IN1 ;
  wire \NlwInverterSignal_U3/DCORIE<3>_MC.D2_PT_1/IN2 ;
  wire \NlwInverterSignal_NET2575_MC.D2_PT_0/IN2 ;
  wire \NlwInverterSignal_NET2575_MC.D2_PT_1/IN0 ;
  wire \NlwInverterSignal_NET2575_MC.D2_PT_1/IN2 ;
  wire \NlwInverterSignal_NET2575_MC.D2_PT_2/IN2 ;
  wire \NlwInverterSignal_NET2575_MC.D2_PT_3/IN0 ;
  wire \NlwInverterSignal_NET2575_MC.D2_PT_3/IN2 ;
  wire \NlwInverterSignal_NET2575_MC.D2_PT_4/IN1 ;
  wire \NlwInverterSignal_NET2575_MC.D2_PT_5/IN2 ;
  wire \NlwInverterSignal_U3/DCORIE<4>_MC.D2_PT_1/IN2 ;
  wire \NlwInverterSignal_NET2501_MC.D2_PT_1/IN4 ;
  wire \NlwInverterSignal_N_PZ_965_MC.D2_PT_0/IN1 ;
  wire \NlwInverterSignal_N_PZ_965_MC.D2_PT_0/IN2 ;
  wire \NlwInverterSignal_N_PZ_965_MC.D2_PT_0/IN3 ;
  wire \NlwInverterSignal_N_PZ_965_MC.D2_PT_0/IN5 ;
  wire \NlwInverterSignal_N_PZ_965_MC.D2_PT_1/IN0 ;
  wire \NlwInverterSignal_N_PZ_965_MC.D2_PT_1/IN1 ;
  wire \NlwInverterSignal_N_PZ_965_MC.D2_PT_1/IN2 ;
  wire \NlwInverterSignal_N_PZ_965_MC.D2_PT_1/IN3 ;
  wire \NlwInverterSignal_N_PZ_965_MC.D2_PT_1/IN4 ;
  wire \NlwInverterSignal_U1/U4/LatchEdge0r_MC.D2_PT_1/IN1 ;
  wire \NlwInverterSignal_U3/DCORIE<5>_MC.D2_PT_1/IN2 ;
  wire \NlwInverterSignal_NET2512_MC.D2_PT_0/IN4 ;
  wire \NlwInverterSignal_NET2512_MC.D2_PT_1/IN1 ;
  wire \NlwInverterSignal_NET2512_MC.D2_PT_1/IN2 ;
  wire \NlwInverterSignal_NET2512_MC.D2_PT_1/IN3 ;
  wire \NlwInverterSignal_NET2512_MC.D2_PT_1/IN6 ;
  wire \NlwInverterSignal_NET2512_MC.D2_PT_2/IN1 ;
  wire \NlwInverterSignal_NET2512_MC.D2_PT_2/IN2 ;
  wire \NlwInverterSignal_NET2512_MC.D2_PT_2/IN3 ;
  wire \NlwInverterSignal_NET2512_MC.D2_PT_2/IN4 ;
  wire \NlwInverterSignal_NET2512_MC.D2_PT_2/IN5 ;
  wire \NlwInverterSignal_U1/U4/LatchEdge1r_MC.D2_PT_1/IN1 ;
  wire \NlwInverterSignal_U3/DCORIE<6>_MC.D2_PT_1/IN2 ;
  wire \NlwInverterSignal_U3/DCORIE<7>_MC.D2_PT_1/IN2 ;
  wire \NlwInverterSignal_TP12_MC.D1/IN0 ;
  wire \NlwInverterSignal_TP12_MC.D1/IN1 ;
  wire \NlwInverterSignal_TP12_MC.D1/IN2 ;
  wire \NlwInverterSignal_TP12_MC.D1/IN3 ;
  wire \NlwInverterSignal_TP12_MC.D1/IN4 ;
  wire \NlwInverterSignal_TP12_MC.D1/IN5 ;
  wire \NlwInverterSignal_U11_U3_counterr<3>_MC.D/IN0 ;
  wire \NlwInverterSignal_U11_U3_counterr<3>_MC.D2_PT_1/IN0 ;
  wire \NlwInverterSignal_U11_U3_counterr<3>_MC.D2_PT_1/IN1 ;
  wire \NlwInverterSignal_U11_U3_counterr<3>_MC.D2_PT_2/IN1 ;
  wire \NlwInverterSignal_U11_U3_counterr<3>_MC.D2_PT_2/IN2 ;
  wire \NlwInverterSignal_U11_U3_counterr<3>_MC.D2_PT_3/IN1 ;
  wire \NlwInverterSignal_U11_U3_counterr<3>_MC.D2_PT_3/IN2 ;
  wire \NlwInverterSignal_U11_U3_counterr<3>_MC.D2_PT_4/IN1 ;
  wire \NlwInverterSignal_U11_U3_counterr<3>_MC.D2_PT_4/IN2 ;
  wire \NlwInverterSignal_U11_U3_counterr<3>_MC.D2_PT_5/IN0 ;
  wire \NlwInverterSignal_U11_U3_counterr<3>_MC.D2_PT_5/IN1 ;
  wire \NlwInverterSignal_U11_U3_counterr<3>_MC.D2_PT_5/IN2 ;
  wire \NlwInverterSignal_U11_U3_counterr<3>_MC.D2_PT_6/IN3 ;
  wire \NlwInverterSignal_U11_U3_counterr<3>_MC.D2_PT_6/IN4 ;
  wire \NlwInverterSignal_N_PZ_1071_MC.D2_PT_1/IN1 ;
  wire \NlwInverterSignal_N_PZ_1071_MC.D2_PT_2/IN1 ;
  wire \NlwInverterSignal_U11_Incdetect_MC.D1/IN0 ;
  wire \NlwInverterSignal_U11_ResetDetect_MC.D1/IN0 ;
  wire \NlwInverterSignal_U11_SCLdetect_MC.D1/IN0 ;
  wire \NlwInverterSignal_U11_U3_counterr<0>_MC.D2_PT_1/IN1 ;
  wire \NlwInverterSignal_U11_U3_counterr<0>_MC.D2_PT_2/IN1 ;
  wire \NlwInverterSignal_U11_U3_counterr<0>_MC.D2_PT_2/IN2 ;
  wire \NlwInverterSignal_U11_U3_counterr<0>_MC.D2_PT_2/IN3 ;
  wire \NlwInverterSignal_U11_U3_counterr<0>_MC.D2_PT_3/IN0 ;
  wire \NlwInverterSignal_U11_U3_counterr<0>_MC.D2_PT_3/IN1 ;
  wire \NlwInverterSignal_U11_U3_counterr<0>_MC.D2_PT_3/IN3 ;
  wire \NlwInverterSignal_U11_U3_counterr<0>_MC.D2_PT_4/IN0 ;
  wire \NlwInverterSignal_U11_U3_counterr<0>_MC.D2_PT_4/IN2 ;
  wire \NlwInverterSignal_U11_U3_counterr<0>_MC.D2_PT_5/IN0 ;
  wire \NlwInverterSignal_U11_U3_counterr<0>_MC.D2_PT_5/IN1 ;
  wire \NlwInverterSignal_U11_U3_counterr<0>_MC.D2_PT_5/IN2 ;
  wire \NlwInverterSignal_U11_U3_counterr<0>_MC.D2_PT_5/IN3 ;
  wire \NlwInverterSignal_U11_U3_counterr<1>_MC.D2_PT_0/IN2 ;
  wire \NlwInverterSignal_U11_U3_counterr<1>_MC.D2_PT_1/IN1 ;
  wire \NlwInverterSignal_U11_U3_counterr<1>_MC.D2_PT_1/IN3 ;
  wire \NlwInverterSignal_U11_U3_counterr<1>_MC.D2_PT_2/IN0 ;
  wire \NlwInverterSignal_U11_U3_counterr<1>_MC.D2_PT_2/IN1 ;
  wire \NlwInverterSignal_U11_U3_counterr<1>_MC.D2_PT_2/IN2 ;
  wire \NlwInverterSignal_U11_U3_counterr<2>_MC.D2_PT_1/IN2 ;
  wire \NlwInverterSignal_U11_U3_counterr<2>_MC.D2_PT_1/IN4 ;
  wire \NlwInverterSignal_U11_U3_counterr<2>_MC.D2_PT_2/IN0 ;
  wire \NlwInverterSignal_U11_U3_counterr<2>_MC.D2_PT_2/IN1 ;
  wire \NlwInverterSignal_U11_U3_counterr<2>_MC.D2_PT_2/IN2 ;
  wire \NlwInverterSignal_U11_U3_counterr<2>_MC.D2_PT_2/IN3 ;
  wire \NlwInverterSignal_U11_U3_counterr<4>_MC.D2_PT_1/IN0 ;
  wire \NlwInverterSignal_U11_U3_counterr<4>_MC.D2_PT_1/IN1 ;
  wire \NlwInverterSignal_U11_U3_counterr<4>_MC.D2_PT_2/IN0 ;
  wire \NlwInverterSignal_U11_U3_counterr<4>_MC.D2_PT_2/IN1 ;
  wire \NlwInverterSignal_U11_U3_counterr<4>_MC.D2_PT_2/IN2 ;
  wire \NlwInverterSignal_U11_U3_counterr<4>_MC.D2_PT_2/IN3 ;
  wire \NlwInverterSignal_N_PZ_1145_MC.D2_PT_0/IN1 ;
  wire \NlwInverterSignal_N_PZ_1145_MC.D2_PT_1/IN1 ;
  wire \NlwInverterSignal_N_PZ_1145_MC.D2_PT_2/IN1 ;
  wire \NlwInverterSignal_N_PZ_1145_MC.D2_PT_3/IN0 ;
  wire \NlwInverterSignal_N_PZ_1145_MC.D2_PT_3/IN1 ;
  wire \NlwInverterSignal_N_PZ_1145_MC.D2_PT_3/IN2 ;
  wire \NlwInverterSignal_N_PZ_1125_MC.D2_PT_1/IN3 ;
  wire \NlwInverterSignal_U11_U3_counterr<5>_MC.D2_PT_1/IN1 ;
  wire \NlwInverterSignal_U11_U3_counterr<5>_MC.D2_PT_1/IN2 ;
  wire \NlwInverterSignal_U11_U3_counterr<5>_MC.D2_PT_2/IN0 ;
  wire \NlwInverterSignal_U11_U3_counterr<5>_MC.D2_PT_2/IN1 ;
  wire \NlwInverterSignal_U11_U3_counterr<5>_MC.D2_PT_2/IN2 ;
  wire \NlwInverterSignal_U11_U3_counterr<5>_MC.D2_PT_2/IN3 ;
  wire \NlwInverterSignal_U11_U3_counterr<5>_MC.D2_PT_2/IN4 ;
  wire \NlwInverterSignal_U11_U3_counterr<5>_MC.D2_PT_3/IN0 ;
  wire \NlwInverterSignal_U11_U3_counterr<5>_MC.D2_PT_3/IN1 ;
  wire \NlwInverterSignal_U11_U3_counterr<5>_MC.D2_PT_3/IN2 ;
  wire \NlwInverterSignal_U11_U3_counterr<5>_MC.D2_PT_3/IN3 ;
  wire \NlwInverterSignal_LED1_MC.D/IN0 ;
  wire \NlwInverterSignal_LED1_MC.D1/IN1 ;
  wire \NlwInverterSignal_LED2_MC.D/IN0 ;
  wire \NlwInverterSignal_LED2_MC.D1/IN1 ;
  wire \NlwInverterSignal_LED3_MC.D/IN0 ;
  wire \NlwInverterSignal_LED3_MC.D1/IN1 ;
  wire \NlwInverterSignal_LED4_MC.D/IN0 ;
  wire \NlwInverterSignal_LED4_MC.D1/IN1 ;
  wire \NlwInverterSignal_LED5_MC.D/IN0 ;
  wire \NlwInverterSignal_LED5_MC.D1/IN1 ;
  wire \NlwInverterSignal_MTRpwrn_MC.D/IN0 ;
  wire \NlwInverterSignal_PAH0_MC.D1/IN0 ;
  wire \NlwInverterSignal_PAH0_MC.D1/IN1 ;
  wire \NlwInverterSignal_PAH0_MC.D1/IN3 ;
  wire \NlwInverterSignal_NET3248_MC.D2_PT_0/IN0 ;
  wire \NlwInverterSignal_NET3248_MC.D2_PT_1/IN2 ;
  wire \NlwInverterSignal_NET3248_MC.D2_PT_2/IN0 ;
  wire \NlwInverterSignal_NET3248_MC.D2_PT_2/IN2 ;
  wire \NlwInverterSignal_PAH1_MC.D1/IN0 ;
  wire \NlwInverterSignal_PAH1_MC.D1/IN1 ;
  wire \NlwInverterSignal_PAH1_MC.D1/IN3 ;
  wire \NlwInverterSignal_NET3253_MC.D2_PT_0/IN0 ;
  wire \NlwInverterSignal_NET3253_MC.D2_PT_1/IN2 ;
  wire \NlwInverterSignal_NET3253_MC.D2_PT_2/IN0 ;
  wire \NlwInverterSignal_NET3253_MC.D2_PT_2/IN2 ;
  wire \NlwInverterSignal_PAL0_MC.D2_PT_1/IN0 ;
  wire \NlwInverterSignal_PAL0_MC.D2_PT_1/IN2 ;
  wire \NlwInverterSignal_PAL0_MC.D2_PT_1/IN3 ;
  wire \NlwInverterSignal_PAL1_MC.D2_PT_1/IN0 ;
  wire \NlwInverterSignal_PAL1_MC.D2_PT_1/IN2 ;
  wire \NlwInverterSignal_PAL1_MC.D2_PT_1/IN3 ;
  wire \NlwInverterSignal_PBH0_MC.D1/IN0 ;
  wire \NlwInverterSignal_PBH0_MC.D1/IN3 ;
  wire \NlwInverterSignal_PBH1_MC.D1/IN0 ;
  wire \NlwInverterSignal_PBH1_MC.D1/IN3 ;
  wire \NlwInverterSignal_PBL0_MC.D2_PT_1/IN0 ;
  wire \NlwInverterSignal_PBL0_MC.D2_PT_1/IN1 ;
  wire \NlwInverterSignal_PBL0_MC.D2_PT_1/IN2 ;
  wire \NlwInverterSignal_PBL0_MC.D2_PT_1/IN3 ;
  wire \NlwInverterSignal_PBL1_MC.D2_PT_1/IN0 ;
  wire \NlwInverterSignal_PBL1_MC.D2_PT_1/IN1 ;
  wire \NlwInverterSignal_PBL1_MC.D2_PT_1/IN2 ;
  wire \NlwInverterSignal_PBL1_MC.D2_PT_1/IN3 ;
  wire \NlwInverterSignal_PresEn_MC.D/IN0 ;
  wire \NlwInverterSignal_DCORSENSORw_MC.D1/IN0 ;
  wire \NlwInverterSignal_DCORSENSORw_MC.D1/IN2 ;
  wire \NlwInverterSignal_DCORSENSORw_MC.D1/IN3 ;
  wire \NlwInverterSignal_DCORSENSORw_MC.D1/IN4 ;
  wire \NlwInverterSignal_DCORSENSORw_MC.D1/IN5 ;
  wire \NlwInverterSignal_DCORSENSORw_MC.D1/IN6 ;
  wire \NlwInverterSignal_DCORSENSORw_MC.D1/IN8 ;
  wire \NlwInverterSignal_TP11_MC.D/IN0 ;
  wire \NlwInverterSignal_TmpEn_MC.D/IN0 ;
  wire \NlwInverterSignal_DCORI2CCNTr_MC.D1/IN1 ;
  wire \NlwInverterSignal_DCORI2CCNTr_MC.D1/IN2 ;
  wire \NlwInverterSignal_DCORI2CCNTr_MC.D1/IN3 ;
  wire \NlwInverterSignal_DCORI2CCNTr_MC.D1/IN4 ;
  wire \NlwInverterSignal_DCORI2CCNTr_MC.D1/IN5 ;
  wire \NlwInverterSignal_DCORI2CCNTr_MC.D1/IN6 ;
  wire \NlwInverterSignal_DCORI2CCNTr_MC.D1/IN7 ;
  wire \NlwInverterSignal_DCORI2CCNTr_MC.D1/IN8 ;
  wire \NlwInverterSignal_DCORI2CCNTr_MC.D1/IN9 ;
  wire \NlwInverterSignal_DCORCONFIGr_MC.D1/IN1 ;
  wire \NlwInverterSignal_DCORCONFIGr_MC.D1/IN3 ;
  wire \NlwInverterSignal_DCORCONFIGr_MC.D1/IN4 ;
  wire \NlwInverterSignal_DCORCONFIGr_MC.D1/IN5 ;
  wire \NlwInverterSignal_DCORCONFIGr_MC.D1/IN6 ;
  wire \NlwInverterSignal_DCORLIMITSr_MC.D1/IN1 ;
  wire \NlwInverterSignal_DCORLIMITSr_MC.D1/IN2 ;
  wire \NlwInverterSignal_DCORLIMITSr_MC.D1/IN3 ;
  wire \NlwInverterSignal_DCORLIMITSr_MC.D1/IN4 ;
  wire \NlwInverterSignal_DCORLIMITSr_MC.D1/IN5 ;
  wire \NlwInverterSignal_DCORLIMITSr_MC.D1/IN6 ;
  wire \NlwInverterSignal_DCORLIMITSr_MC.D1/IN7 ;
  wire \NlwInverterSignal_DCORLIMITSr_MC.D1/IN9 ;
  wire \NlwInverterSignal_DCORENCPWRr_MC.D1/IN1 ;
  wire \NlwInverterSignal_DCORENCPWRr_MC.D1/IN2 ;
  wire \NlwInverterSignal_DCORENCPWRr_MC.D1/IN3 ;
  wire \NlwInverterSignal_DCORENCPWRr_MC.D1/IN4 ;
  wire \NlwInverterSignal_DCORENCPWRr_MC.D1/IN5 ;
  wire \NlwInverterSignal_DCORENCPWRr_MC.D1/IN6 ;
  wire \NlwInverterSignal_outDATA<0>\$WA3.UIM_MC.D2_PT_1/IN0 ;
  wire \NlwInverterSignal_DCORIFGr_MC.D1/IN1 ;
  wire \NlwInverterSignal_DCORIFGr_MC.D1/IN3 ;
  wire \NlwInverterSignal_DCORIFGr_MC.D1/IN4 ;
  wire \NlwInverterSignal_DCORIFGr_MC.D1/IN5 ;
  wire \NlwInverterSignal_DCORIFGr_MC.D1/IN6 ;
  wire \NlwInverterSignal_DCORIFGr_MC.D1/IN7 ;
  wire \NlwInverterSignal_DCORIFGr_MC.D1/IN8 ;
  wire \NlwInverterSignal_DCORIFGr_MC.D1/IN9 ;
  wire \NlwInverterSignal_DCOR0THRESLOWr_MC.D1/IN1 ;
  wire \NlwInverterSignal_DCOR0THRESLOWr_MC.D1/IN2 ;
  wire \NlwInverterSignal_DCOR0THRESLOWr_MC.D1/IN3 ;
  wire \NlwInverterSignal_DCOR0THRESLOWr_MC.D1/IN4 ;
  wire \NlwInverterSignal_DCOR0THRESLOWr_MC.D1/IN5 ;
  wire \NlwInverterSignal_DCOR0THRESLOWr_MC.D1/IN6 ;
  wire \NlwInverterSignal_DCOR0THRESLOWr_MC.D1/IN8 ;
  wire \NlwInverterSignal_DCOR0THRESLOWr_MC.D1/IN9 ;
  wire \NlwInverterSignal_outDATA<0>\$WA6.UIM_MC.D2_PT_1/IN0 ;
  wire \NlwInverterSignal_outDATA<0>\$WA6.UIM_MC.D2_PT_2/IN0 ;
  wire \NlwInverterSignal_outDATA<0>\$WA6.UIM_MC.D2_PT_2/IN1 ;
  wire \NlwInverterSignal_outDATA<0>\$WA6.UIM_MC.D2_PT_3/IN0 ;
  wire \NlwInverterSignal_outDATA<0>\$WA6.UIM_MC.D2_PT_3/IN1 ;
  wire \NlwInverterSignal_outDATA<0>\$WA6.UIM_MC.D2_PT_3/IN2 ;
  wire \NlwInverterSignal_U1/U4/Latch0r<0>_MC.D2_PT_1/IN1 ;
  wire \NlwInverterSignal_U1/Channel0<0>_MC.D2_PT_0/IN1 ;
  wire \NlwInverterSignal_U1/Channel0<0>_MC.D2_PT_1/IN1 ;
  wire \NlwInverterSignal_U1/Channel0<0>_MC.D2_PT_1/IN4 ;
  wire \NlwInverterSignal_U1/Channel0<0>_MC.D2_PT_1/IN5 ;
  wire \NlwInverterSignal_U1/Channel0<0>_MC.D2_PT_2/IN1 ;
  wire \NlwInverterSignal_U1/Channel0<0>_MC.D2_PT_2/IN2 ;
  wire \NlwInverterSignal_U1/Channel0<0>_MC.D2_PT_2/IN4 ;
  wire \NlwInverterSignal_U1/Zero0_MC.D2_PT_0/IN0 ;
  wire \NlwInverterSignal_U1/Zero0_MC.D2_PT_1/IN0 ;
  wire \NlwInverterSignal_U1/Zero0_MC.D2_PT_2/IN1 ;
  wire \NlwInverterSignal_U1/Zero0_MC.D2_PT_2/IN5 ;
  wire \NlwInverterSignal_U1/Zero0_MC.D2_PT_2/IN6 ;
  wire \NlwInverterSignal_U1/Zero0_MC.D2_PT_3/IN1 ;
  wire \NlwInverterSignal_U1/Zero0_MC.D2_PT_3/IN2 ;
  wire \NlwInverterSignal_U1/Zero0_MC.D2_PT_3/IN4 ;
  wire \NlwInverterSignal_U1/Zero0_MC.D2_PT_3/IN6 ;
  wire \NlwInverterSignal_N_PZ_931_MC.D1/IN1 ;
  wire \NlwInverterSignal_U1/U1/CurrState_Sreg0_FFD1_MC.D2_PT_0/IN3 ;
  wire \NlwInverterSignal_U1/U1/CurrState_Sreg0_FFD1_MC.D2_PT_1/IN3 ;
  wire \NlwInverterSignal_U1/U1/CurrState_Sreg0_FFD1_MC.D2_PT_1/IN4 ;
  wire \NlwInverterSignal_U1/U1/CurrState_Sreg0_FFD1_MC.D2_PT_2/IN1 ;
  wire \NlwInverterSignal_U1/U1/CurrState_Sreg0_FFD1_MC.D2_PT_2/IN3 ;
  wire \NlwInverterSignal_U1/U1/CurrState_Sreg0_FFD1_MC.D2_PT_2/IN4 ;
  wire \NlwInverterSignal_U1/U1/CurrState_Sreg0_FFD1_MC.D2_PT_2/IN5 ;
  wire \NlwInverterSignal_U1/U1/CurrState_Sreg0_FFD3_MC.D2_PT_0/IN1 ;
  wire \NlwInverterSignal_U1/U1/CurrState_Sreg0_FFD3_MC.D2_PT_0/IN4 ;
  wire \NlwInverterSignal_U1/U1/CurrState_Sreg0_FFD3_MC.D2_PT_1/IN1 ;
  wire \NlwInverterSignal_U1/U1/CurrState_Sreg0_FFD3_MC.D2_PT_1/IN3 ;
  wire \NlwInverterSignal_U1/U1/CurrState_Sreg0_FFD3_MC.D2_PT_1/IN4 ;
  wire \NlwInverterSignal_U1/U1/CurrState_Sreg0_FFD3_MC.D2_PT_2/IN3 ;
  wire \NlwInverterSignal_U1/U1/CurrState_Sreg0_FFD3_MC.D2_PT_2/IN5 ;
  wire \NlwInverterSignal_U1/U1/CurrState_Sreg0_FFD3_MC.D2_PT_3/IN2 ;
  wire \NlwInverterSignal_U1/U1/CurrState_Sreg0_FFD3_MC.D2_PT_3/IN5 ;
  wire \NlwInverterSignal_U1/U1/CurrState_Sreg0_FFD2_MC.D2_PT_0/IN4 ;
  wire \NlwInverterSignal_U1/U1/CurrState_Sreg0_FFD2_MC.D2_PT_0/IN5 ;
  wire \NlwInverterSignal_U1/U1/CurrState_Sreg0_FFD2_MC.D2_PT_1/IN3 ;
  wire \NlwInverterSignal_U1/U1/CurrState_Sreg0_FFD2_MC.D2_PT_1/IN5 ;
  wire \NlwInverterSignal_U1/U1/CurrState_Sreg0_FFD2_MC.D2_PT_2/IN2 ;
  wire \NlwInverterSignal_U1/U1/CurrState_Sreg0_FFD2_MC.D2_PT_2/IN5 ;
  wire \NlwInverterSignal_U1/U1/CurrState_Sreg0_FFD2_MC.D2_PT_3/IN2 ;
  wire \NlwInverterSignal_U1/U1/CurrState_Sreg0_FFD2_MC.D2_PT_3/IN3 ;
  wire \NlwInverterSignal_U1/U1/CurrState_Sreg0_FFD2_MC.D2_PT_3/IN4 ;
  wire \NlwInverterSignal_U1/U1/CurrState_Sreg0_FFD2_MC.D2_PT_3/IN5 ;
  wire \NlwInverterSignal_U1/U1/CurrState_Sreg0_FFD2_MC.D2_PT_4/IN5 ;
  wire \NlwInverterSignal_U1/U1/CurrState_Sreg0_FFD2_MC.D2_PT_5/IN2 ;
  wire \NlwInverterSignal_U1/U1/CurrState_Sreg0_FFD2_MC.D2_PT_5/IN3 ;
  wire \NlwInverterSignal_U1/U1/CurrState_Sreg0_FFD2_MC.D2_PT_5/IN5 ;
  wire \NlwInverterSignal_U1/U1/CurrState_Sreg0_FFD2_MC.D2_PT_6/IN1 ;
  wire \NlwInverterSignal_U1/U1/CurrState_Sreg0_FFD2_MC.D2_PT_6/IN3 ;
  wire \NlwInverterSignal_U1/U1/CurrState_Sreg0_FFD2_MC.D2_PT_6/IN5 ;
  wire \NlwInverterSignal_U1/U1/CurrState_Sreg0_FFD2_MC.D2_PT_7/IN1 ;
  wire \NlwInverterSignal_U1/U1/CurrState_Sreg0_FFD2_MC.D2_PT_7/IN2 ;
  wire \NlwInverterSignal_U1/U1/CurrState_Sreg0_FFD2_MC.D2_PT_7/IN5 ;
  wire \NlwInverterSignal_U1/U1/CurrState_Sreg0_FFD4_MC.D1/IN1 ;
  wire \NlwInverterSignal_U1/U1/CurrState_Sreg0_FFD4_MC.D1/IN2 ;
  wire \NlwInverterSignal_U1/U1/CurrState_Sreg0_FFD4_MC.D1/IN3 ;
  wire \NlwInverterSignal_U1/U1/CurrState_Sreg0_FFD4_MC.D1/IN5 ;
  wire \NlwInverterSignal_U1/U1/CurrState_Sreg0_FFD4_MC.D1/IN6 ;
  wire \NlwInverterSignal_U1/U4/Latch0r<8>_MC.D2_PT_1/IN1 ;
  wire \NlwInverterSignal_U1/Channel0<8>_MC.D2_PT_0/IN0 ;
  wire \NlwInverterSignal_U1/Channel0<8>_MC.D2_PT_1/IN0 ;
  wire \NlwInverterSignal_U1/Channel0<8>_MC.D2_PT_2/IN1 ;
  wire \NlwInverterSignal_U1/Channel0<8>_MC.D2_PT_2/IN3 ;
  wire \NlwInverterSignal_U1/Channel0<8>_MC.D2_PT_3/IN1 ;
  wire \NlwInverterSignal_U1/Channel0<8>_MC.D2_PT_3/IN4 ;
  wire \NlwInverterSignal_U1/Channel0<8>_MC.D2_PT_4/IN1 ;
  wire \NlwInverterSignal_U1/Channel0<8>_MC.D2_PT_4/IN3 ;
  wire \NlwInverterSignal_U1/Channel0<8>_MC.D2_PT_4/IN4 ;
  wire \NlwInverterSignal_U1/Channel0<8>_MC.D2_PT_4/IN6 ;
  wire \NlwInverterSignal_U1/Channel0<8>_MC.D2_PT_5/IN0 ;
  wire \NlwInverterSignal_U1/Channel0<8>_MC.D2_PT_5/IN5 ;
  wire \NlwInverterSignal_U1/U2/location_Maddsub__n0000__n0075<0>_MC.D2_PT_0/IN3 ;
  wire \NlwInverterSignal_U1/U2/location_Maddsub__n0000__n0075<0>_MC.D2_PT_1/IN0 ;
  wire \NlwInverterSignal_U1/U2/location_Maddsub__n0000__n0075<0>_MC.D2_PT_1/IN1 ;
  wire \NlwInverterSignal_U1/U2/location_Maddsub__n0000__n0075<0>_MC.D2_PT_1/IN2 ;
  wire \NlwInverterSignal_U1/U2/location_Maddsub__n0000__n0075<0>_MC.D2_PT_1/IN4 ;
  wire \NlwInverterSignal_U1/U2/location_Maddsub__n0000__n0075<0>_MC.D2_PT_1/IN5 ;
  wire \NlwInverterSignal_N_PZ_945_MC.D2_PT_0/IN0 ;
  wire \NlwInverterSignal_N_PZ_945_MC.D2_PT_0/IN2 ;
  wire \NlwInverterSignal_N_PZ_945_MC.D2_PT_1/IN0 ;
  wire \NlwInverterSignal_N_PZ_945_MC.D2_PT_1/IN2 ;
  wire \NlwInverterSignal_U1/NET3721_MC.D2_PT_1/IN1 ;
  wire \NlwInverterSignal_U1/Channel0<5>_MC.D2_PT_0/IN0 ;
  wire \NlwInverterSignal_U1/Channel0<5>_MC.D2_PT_2/IN1 ;
  wire \NlwInverterSignal_U1/U2/location_Maddsub__n0000__n0067<0>_MC.D2_PT_1/IN0 ;
  wire \NlwInverterSignal_U1/U2/location_Maddsub__n0000__n0067<0>_MC.D2_PT_1/IN1 ;
  wire \NlwInverterSignal_U1/U2/location_Maddsub__n0000__n0067<0>_MC.D2_PT_1/IN2 ;
  wire \NlwInverterSignal_U1/U2/location_Maddsub__n0000__n0067<0>_MC.D2_PT_1/IN3 ;
  wire \NlwInverterSignal_U1/U2/location_Maddsub__n0000__n0067<0>_MC.D2_PT_1/IN4 ;
  wire \NlwInverterSignal_U1/U2/location_Maddsub__n0000__n0067<0>_MC.D2_PT_1/IN5 ;
  wire \NlwInverterSignal_U1/Channel0<1>_MC.D2_PT_1/IN0 ;
  wire \NlwInverterSignal_U1/Channel0<1>_MC.D2_PT_2/IN0 ;
  wire \NlwInverterSignal_N_PZ_966_MC.D2_PT_0/IN1 ;
  wire \NlwInverterSignal_N_PZ_966_MC.D2_PT_0/IN4 ;
  wire \NlwInverterSignal_N_PZ_966_MC.D2_PT_0/IN5 ;
  wire \NlwInverterSignal_N_PZ_966_MC.D2_PT_0/IN6 ;
  wire \NlwInverterSignal_N_PZ_966_MC.D2_PT_1/IN1 ;
  wire \NlwInverterSignal_N_PZ_966_MC.D2_PT_1/IN2 ;
  wire \NlwInverterSignal_N_PZ_966_MC.D2_PT_1/IN4 ;
  wire \NlwInverterSignal_N_PZ_969_MC.D2_PT_0/IN1 ;
  wire \NlwInverterSignal_N_PZ_969_MC.D2_PT_0/IN4 ;
  wire \NlwInverterSignal_N_PZ_969_MC.D2_PT_0/IN5 ;
  wire \NlwInverterSignal_N_PZ_969_MC.D2_PT_1/IN1 ;
  wire \NlwInverterSignal_N_PZ_969_MC.D2_PT_1/IN2 ;
  wire \NlwInverterSignal_N_PZ_969_MC.D2_PT_1/IN4 ;
  wire \NlwInverterSignal_N_PZ_969_MC.D2_PT_1/IN6 ;
  wire \NlwInverterSignal_U1/Channel0<2>_MC.D2_PT_0/IN0 ;
  wire \NlwInverterSignal_U1/Channel0<2>_MC.D2_PT_2/IN0 ;
  wire \NlwInverterSignal_U1/Channel0<2>_MC.D2_PT_2/IN2 ;
  wire \NlwInverterSignal_U1/Channel0<3>_MC.D2_PT_0/IN0 ;
  wire \NlwInverterSignal_U1/Channel0<3>_MC.D2_PT_2/IN0 ;
  wire \NlwInverterSignal_U1/Channel0<3>_MC.D2_PT_2/IN2 ;
  wire \NlwInverterSignal_U1/Channel0<3>_MC.D2_PT_2/IN3 ;
  wire \NlwInverterSignal_U1/Channel0<4>_MC.D2_PT_0/IN0 ;
  wire \NlwInverterSignal_U1/Channel0<4>_MC.D2_PT_1/IN2 ;
  wire \NlwInverterSignal_U1/Channel0<4>_MC.D2_PT_2/IN1 ;
  wire \NlwInverterSignal_U1/Channel0<4>_MC.D2_PT_2/IN2 ;
  wire \NlwInverterSignal_U1/Channel0<4>_MC.D2_PT_3/IN2 ;
  wire \NlwInverterSignal_U1/Channel0<4>_MC.D2_PT_4/IN6 ;
  wire \NlwInverterSignal_U1/Channel0<4>_MC.D2_PT_5/IN0 ;
  wire \NlwInverterSignal_U1/Channel0<4>_MC.D2_PT_5/IN2 ;
  wire \NlwInverterSignal_U1/Channel0<4>_MC.D2_PT_5/IN3 ;
  wire \NlwInverterSignal_U1/Channel0<4>_MC.D2_PT_5/IN4 ;
  wire \NlwInverterSignal_U1/Channel0<4>_MC.D2_PT_5/IN5 ;
  wire \NlwInverterSignal_U1/Channel0<6>_MC.D2_PT_0/IN0 ;
  wire \NlwInverterSignal_U1/Channel0<6>_MC.D2_PT_1/IN1 ;
  wire \NlwInverterSignal_U1/Channel0<6>_MC.D2_PT_2/IN2 ;
  wire \NlwInverterSignal_U1/Channel0<7>_MC.D2_PT_0/IN0 ;
  wire \NlwInverterSignal_U1/Channel0<7>_MC.D2_PT_1/IN1 ;
  wire \NlwInverterSignal_U1/Channel0<7>_MC.D2_PT_1/IN3 ;
  wire \NlwInverterSignal_U1/Channel0<7>_MC.D2_PT_2/IN2 ;
  wire \NlwInverterSignal_DCOR0THRESHIGHr_MC.D1/IN1 ;
  wire \NlwInverterSignal_DCOR0THRESHIGHr_MC.D1/IN3 ;
  wire \NlwInverterSignal_DCOR0THRESHIGHr_MC.D1/IN4 ;
  wire \NlwInverterSignal_DCOR0THRESHIGHr_MC.D1/IN5 ;
  wire \NlwInverterSignal_DCOR0THRESHIGHr_MC.D1/IN6 ;
  wire \NlwInverterSignal_DCOR0THRESHIGHr_MC.D1/IN8 ;
  wire \NlwInverterSignal_DCOR0THRESHIGHr_MC.D1/IN9 ;
  wire \NlwInverterSignal_U1/U4/Latch1r<0>_MC.D2_PT_1/IN1 ;
  wire \NlwInverterSignal_U1/U4/Latch1r<0>_MC.D2_PT_1/IN2 ;
  wire \NlwInverterSignal_U1/Channel1<0>_MC.D2_PT_0/IN2 ;
  wire \NlwInverterSignal_U1/Channel1<0>_MC.D2_PT_0/IN3 ;
  wire \NlwInverterSignal_U1/Channel1<0>_MC.D2_PT_1/IN1 ;
  wire \NlwInverterSignal_U1/Channel1<0>_MC.D2_PT_1/IN2 ;
  wire \NlwInverterSignal_U1/Zero1_MC.D2_PT_0/IN0 ;
  wire \NlwInverterSignal_U1/Zero1_MC.D2_PT_1/IN1 ;
  wire \NlwInverterSignal_U1/Zero1_MC.D2_PT_2/IN1 ;
  wire \NlwInverterSignal_U1/Zero1_MC.D2_PT_2/IN5 ;
  wire \NlwInverterSignal_U1/Zero1_MC.D2_PT_2/IN6 ;
  wire \NlwInverterSignal_U1/Zero1_MC.D2_PT_3/IN1 ;
  wire \NlwInverterSignal_U1/Zero1_MC.D2_PT_3/IN2 ;
  wire \NlwInverterSignal_U1/Zero1_MC.D2_PT_3/IN4 ;
  wire \NlwInverterSignal_U1/Zero1_MC.D2_PT_3/IN6 ;
  wire \NlwInverterSignal_N_PZ_933_MC.D1/IN1 ;
  wire \NlwInverterSignal_N_PZ_1155_MC.D2_PT_0/IN2 ;
  wire \NlwInverterSignal_N_PZ_1155_MC.D2_PT_0/IN3 ;
  wire \NlwInverterSignal_N_PZ_1155_MC.D2_PT_1/IN0 ;
  wire \NlwInverterSignal_N_PZ_1155_MC.D2_PT_1/IN2 ;
  wire \NlwInverterSignal_U1/U6/CurrState_Sreg0_FFD1_MC.D2_PT_0/IN3 ;
  wire \NlwInverterSignal_U1/U6/CurrState_Sreg0_FFD1_MC.D2_PT_1/IN3 ;
  wire \NlwInverterSignal_U1/U6/CurrState_Sreg0_FFD1_MC.D2_PT_1/IN4 ;
  wire \NlwInverterSignal_U1/U6/CurrState_Sreg0_FFD1_MC.D2_PT_2/IN1 ;
  wire \NlwInverterSignal_U1/U6/CurrState_Sreg0_FFD1_MC.D2_PT_2/IN3 ;
  wire \NlwInverterSignal_U1/U6/CurrState_Sreg0_FFD1_MC.D2_PT_2/IN4 ;
  wire \NlwInverterSignal_U1/U6/CurrState_Sreg0_FFD1_MC.D2_PT_2/IN5 ;
  wire \NlwInverterSignal_U1/U6/CurrState_Sreg0_FFD3_MC.D2_PT_0/IN3 ;
  wire \NlwInverterSignal_U1/U6/CurrState_Sreg0_FFD3_MC.D2_PT_1/IN1 ;
  wire \NlwInverterSignal_U1/U6/CurrState_Sreg0_FFD3_MC.D2_PT_1/IN4 ;
  wire \NlwInverterSignal_U1/U6/CurrState_Sreg0_FFD3_MC.D2_PT_2/IN1 ;
  wire \NlwInverterSignal_U1/U6/CurrState_Sreg0_FFD3_MC.D2_PT_2/IN3 ;
  wire \NlwInverterSignal_U1/U6/CurrState_Sreg0_FFD3_MC.D2_PT_2/IN4 ;
  wire \NlwInverterSignal_U1/U6/CurrState_Sreg0_FFD2_MC.D2_PT_0/IN2 ;
  wire \NlwInverterSignal_U1/U6/CurrState_Sreg0_FFD2_MC.D2_PT_0/IN3 ;
  wire \NlwInverterSignal_U1/U6/CurrState_Sreg0_FFD2_MC.D2_PT_0/IN4 ;
  wire \NlwInverterSignal_U1/U6/CurrState_Sreg0_FFD2_MC.D2_PT_1/IN3 ;
  wire \NlwInverterSignal_U1/U6/CurrState_Sreg0_FFD2_MC.D2_PT_1/IN4 ;
  wire \NlwInverterSignal_U1/U6/CurrState_Sreg0_FFD2_MC.D2_PT_2/IN1 ;
  wire \NlwInverterSignal_U1/U6/CurrState_Sreg0_FFD2_MC.D2_PT_2/IN3 ;
  wire \NlwInverterSignal_U1/U6/CurrState_Sreg0_FFD2_MC.D2_PT_3/IN2 ;
  wire \NlwInverterSignal_U1/U6/CurrState_Sreg0_FFD2_MC.D2_PT_3/IN4 ;
  wire \NlwInverterSignal_U1/U6/CurrState_Sreg0_FFD4_MC.D1/IN1 ;
  wire \NlwInverterSignal_U1/U6/CurrState_Sreg0_FFD4_MC.D1/IN2 ;
  wire \NlwInverterSignal_U1/U6/CurrState_Sreg0_FFD4_MC.D1/IN3 ;
  wire \NlwInverterSignal_U1/U6/CurrState_Sreg0_FFD4_MC.D1/IN5 ;
  wire \NlwInverterSignal_U1/U6/CurrState_Sreg0_FFD4_MC.D1/IN6 ;
  wire \NlwInverterSignal_N_PZ_1107_MC.D2_PT_0/IN1 ;
  wire \NlwInverterSignal_N_PZ_1107_MC.D2_PT_1/IN0 ;
  wire \NlwInverterSignal_DCOR1THRESLOWr_MC.D1/IN1 ;
  wire \NlwInverterSignal_DCOR1THRESLOWr_MC.D1/IN2 ;
  wire \NlwInverterSignal_DCOR1THRESLOWr_MC.D1/IN3 ;
  wire \NlwInverterSignal_DCOR1THRESLOWr_MC.D1/IN4 ;
  wire \NlwInverterSignal_DCOR1THRESLOWr_MC.D1/IN5 ;
  wire \NlwInverterSignal_DCOR1THRESLOWr_MC.D1/IN6 ;
  wire \NlwInverterSignal_DCOR1THRESLOWr_MC.D1/IN9 ;
  wire \NlwInverterSignal_U1/U4/Latch1r<8>_MC.D2_PT_1/IN1 ;
  wire \NlwInverterSignal_U1/U4/Latch1r<8>_MC.D2_PT_1/IN2 ;
  wire \NlwInverterSignal_U1/Channel1<8>_MC.D2_PT_0/IN0 ;
  wire \NlwInverterSignal_U1/Channel1<8>_MC.D2_PT_1/IN2 ;
  wire \NlwInverterSignal_U1/Channel1<8>_MC.D2_PT_1/IN3 ;
  wire \NlwInverterSignal_U1/Channel1<8>_MC.D2_PT_2/IN1 ;
  wire \NlwInverterSignal_U1/Channel1<8>_MC.D2_PT_2/IN3 ;
  wire \NlwInverterSignal_U1/Channel1<8>_MC.D2_PT_2/IN4 ;
  wire \NlwInverterSignal_U1/Channel1<8>_MC.D2_PT_3/IN2 ;
  wire \NlwInverterSignal_U1/Channel1<8>_MC.D2_PT_3/IN4 ;
  wire \NlwInverterSignal_U1/Channel1<8>_MC.D2_PT_4/IN2 ;
  wire \NlwInverterSignal_U1/Channel1<8>_MC.D2_PT_4/IN3 ;
  wire \NlwInverterSignal_U1/Channel1<8>_MC.D2_PT_4/IN4 ;
  wire \NlwInverterSignal_U1/Channel1<8>_MC.D2_PT_4/IN6 ;
  wire \NlwInverterSignal_U1/Channel1<8>_MC.D2_PT_5/IN1 ;
  wire \NlwInverterSignal_U1/Channel1<8>_MC.D2_PT_5/IN3 ;
  wire \NlwInverterSignal_U1/Channel1<8>_MC.D2_PT_5/IN7 ;
  wire \NlwInverterSignal_U1/Channel1<5>_MC.D2_PT_0/IN0 ;
  wire \NlwInverterSignal_U1/Channel1<5>_MC.D2_PT_1/IN1 ;
  wire \NlwInverterSignal_U1/Channel1<5>_MC.D2_PT_1/IN3 ;
  wire \NlwInverterSignal_U1/Channel1<5>_MC.D2_PT_2/IN1 ;
  wire \NlwInverterSignal_U1/Channel1<5>_MC.D2_PT_2/IN3 ;
  wire \NlwInverterSignal_U1/U5/location_Maddsub__n0000__n0067<0>_MC.D2_PT_1/IN0 ;
  wire \NlwInverterSignal_U1/U5/location_Maddsub__n0000__n0067<0>_MC.D2_PT_1/IN1 ;
  wire \NlwInverterSignal_U1/U5/location_Maddsub__n0000__n0067<0>_MC.D2_PT_1/IN2 ;
  wire \NlwInverterSignal_U1/U5/location_Maddsub__n0000__n0067<0>_MC.D2_PT_1/IN3 ;
  wire \NlwInverterSignal_U1/U5/location_Maddsub__n0000__n0067<0>_MC.D2_PT_1/IN4 ;
  wire \NlwInverterSignal_U1/U5/location_Maddsub__n0000__n0067<0>_MC.D2_PT_1/IN5 ;
  wire \NlwInverterSignal_N_PZ_946_MC.D2_PT_0/IN0 ;
  wire \NlwInverterSignal_N_PZ_946_MC.D2_PT_0/IN2 ;
  wire \NlwInverterSignal_N_PZ_946_MC.D2_PT_1/IN0 ;
  wire \NlwInverterSignal_N_PZ_946_MC.D2_PT_1/IN2 ;
  wire \NlwInverterSignal_U1/NET3720_MC.D2_PT_1/IN1 ;
  wire \NlwInverterSignal_U1/Channel1<1>_MC.D2_PT_0/IN0 ;
  wire \NlwInverterSignal_U1/Channel1<1>_MC.D2_PT_1/IN2 ;
  wire \NlwInverterSignal_U1/Channel1<1>_MC.D2_PT_2/IN1 ;
  wire \NlwInverterSignal_U1/Channel1<1>_MC.D2_PT_2/IN2 ;
  wire \NlwInverterSignal_U1/Channel1<1>_MC.D2_PT_2/IN4 ;
  wire \NlwInverterSignal_N_PZ_1016_MC.D2_PT_0/IN2 ;
  wire \NlwInverterSignal_N_PZ_1016_MC.D2_PT_0/IN3 ;
  wire \NlwInverterSignal_N_PZ_1016_MC.D2_PT_1/IN0 ;
  wire \NlwInverterSignal_N_PZ_1016_MC.D2_PT_1/IN2 ;
  wire \NlwInverterSignal_N_PZ_1016_MC.D2_PT_1/IN4 ;
  wire \NlwInverterSignal_U1/Channel1<2>_MC.D2_PT_0/IN0 ;
  wire \NlwInverterSignal_U1/Channel1<2>_MC.D2_PT_1/IN2 ;
  wire \NlwInverterSignal_U1/Channel1<2>_MC.D2_PT_2/IN1 ;
  wire \NlwInverterSignal_U1/Channel1<2>_MC.D2_PT_2/IN2 ;
  wire \NlwInverterSignal_U1/Channel1<2>_MC.D2_PT_2/IN4 ;
  wire \NlwInverterSignal_U1/Channel1<2>_MC.D2_PT_2/IN5 ;
  wire \NlwInverterSignal_U1/Channel1<3>_MC.D2_PT_0/IN0 ;
  wire \NlwInverterSignal_U1/Channel1<3>_MC.D2_PT_1/IN2 ;
  wire \NlwInverterSignal_U1/Channel1<3>_MC.D2_PT_2/IN1 ;
  wire \NlwInverterSignal_U1/Channel1<3>_MC.D2_PT_2/IN2 ;
  wire \NlwInverterSignal_U1/Channel1<3>_MC.D2_PT_2/IN4 ;
  wire \NlwInverterSignal_U1/Channel1<3>_MC.D2_PT_2/IN5 ;
  wire \NlwInverterSignal_U1/Channel1<3>_MC.D2_PT_2/IN6 ;
  wire \NlwInverterSignal_U1/Channel1<4>_MC.D2_PT_0/IN0 ;
  wire \NlwInverterSignal_U1/Channel1<4>_MC.D2_PT_1/IN1 ;
  wire \NlwInverterSignal_U1/Channel1<4>_MC.D2_PT_1/IN2 ;
  wire \NlwInverterSignal_U1/Channel1<4>_MC.D2_PT_2/IN1 ;
  wire \NlwInverterSignal_U1/Channel1<4>_MC.D2_PT_2/IN3 ;
  wire \NlwInverterSignal_U1/Channel1<4>_MC.D2_PT_2/IN5 ;
  wire \NlwInverterSignal_U1/Channel1<4>_MC.D2_PT_3/IN2 ;
  wire \NlwInverterSignal_U1/Channel1<4>_MC.D2_PT_4/IN0 ;
  wire \NlwInverterSignal_U1/Channel1<4>_MC.D2_PT_4/IN2 ;
  wire \NlwInverterSignal_U1/Channel1<4>_MC.D2_PT_4/IN3 ;
  wire \NlwInverterSignal_U1/Channel1<4>_MC.D2_PT_4/IN4 ;
  wire \NlwInverterSignal_U1/Channel1<4>_MC.D2_PT_4/IN5 ;
  wire \NlwInverterSignal_U1/Channel1<4>_MC.D2_PT_5/IN2 ;
  wire \NlwInverterSignal_U1/Channel1<4>_MC.D2_PT_5/IN8 ;
  wire \NlwInverterSignal_U1/Channel1<6>_MC.D2_PT_0/IN0 ;
  wire \NlwInverterSignal_U1/Channel1<6>_MC.D2_PT_1/IN1 ;
  wire \NlwInverterSignal_U1/Channel1<6>_MC.D2_PT_1/IN4 ;
  wire \NlwInverterSignal_U1/Channel1<6>_MC.D2_PT_2/IN1 ;
  wire \NlwInverterSignal_U1/Channel1<6>_MC.D2_PT_2/IN3 ;
  wire \NlwInverterSignal_U1/Channel1<6>_MC.D2_PT_2/IN4 ;
  wire \NlwInverterSignal_U1/Channel1<7>_MC.D2_PT_0/IN0 ;
  wire \NlwInverterSignal_U1/Channel1<7>_MC.D2_PT_1/IN1 ;
  wire \NlwInverterSignal_U1/Channel1<7>_MC.D2_PT_1/IN4 ;
  wire \NlwInverterSignal_U1/Channel1<7>_MC.D2_PT_2/IN1 ;
  wire \NlwInverterSignal_U1/Channel1<7>_MC.D2_PT_2/IN3 ;
  wire \NlwInverterSignal_U1/Channel1<7>_MC.D2_PT_2/IN4 ;
  wire \NlwInverterSignal_U1/Channel1<7>_MC.D2_PT_2/IN6 ;
  wire \NlwInverterSignal_U1/U5/location_Maddsub__n0000__n0075<0>_MC.D2_PT_0/IN3 ;
  wire \NlwInverterSignal_U1/U5/location_Maddsub__n0000__n0075<0>_MC.D2_PT_1/IN0 ;
  wire \NlwInverterSignal_U1/U5/location_Maddsub__n0000__n0075<0>_MC.D2_PT_1/IN1 ;
  wire \NlwInverterSignal_U1/U5/location_Maddsub__n0000__n0075<0>_MC.D2_PT_1/IN2 ;
  wire \NlwInverterSignal_U1/U5/location_Maddsub__n0000__n0075<0>_MC.D2_PT_1/IN4 ;
  wire \NlwInverterSignal_U1/U5/location_Maddsub__n0000__n0075<0>_MC.D2_PT_1/IN5 ;
  wire \NlwInverterSignal_outDATA<0>\$WA5.UIM_MC.D2_PT_1/IN0 ;
  wire \NlwInverterSignal_outDATA<0>\$WA5.UIM_MC.D2_PT_2/IN0 ;
  wire \NlwInverterSignal_outDATA<0>\$WA5.UIM_MC.D2_PT_2/IN1 ;
  wire \NlwInverterSignal_outDATA<0>\$WA5.UIM_MC.D2_PT_3/IN0 ;
  wire \NlwInverterSignal_outDATA<0>\$WA5.UIM_MC.D2_PT_3/IN1 ;
  wire \NlwInverterSignal_outDATA<0>\$WA5.UIM_MC.D2_PT_3/IN2 ;
  wire \NlwInverterSignal_U1/U3/holdingreg0<0>_MC.D2_PT_1/IN1 ;
  wire \NlwInverterSignal_DCOR0CNTLOWr_MC.D1/IN1 ;
  wire \NlwInverterSignal_DCOR0CNTLOWr_MC.D1/IN2 ;
  wire \NlwInverterSignal_DCOR0CNTLOWr_MC.D1/IN3 ;
  wire \NlwInverterSignal_DCOR0CNTLOWr_MC.D1/IN4 ;
  wire \NlwInverterSignal_DCOR0CNTLOWr_MC.D1/IN5 ;
  wire \NlwInverterSignal_DCOR0CNTLOWr_MC.D1/IN6 ;
  wire \NlwInverterSignal_DCOR0CNTLOWr_MC.D1/IN7 ;
  wire \NlwInverterSignal_DCOR0CNTLOWr_MC.D1/IN8 ;
  wire \NlwInverterSignal_U1/U3/holdingreg1<0>_MC.D2_PT_1/IN1 ;
  wire \NlwInverterSignal_DCOR1CNTLOWr_MC.D1/IN1 ;
  wire \NlwInverterSignal_DCOR1CNTLOWr_MC.D1/IN2 ;
  wire \NlwInverterSignal_DCOR1CNTLOWr_MC.D1/IN3 ;
  wire \NlwInverterSignal_DCOR1CNTLOWr_MC.D1/IN4 ;
  wire \NlwInverterSignal_DCOR1CNTLOWr_MC.D1/IN5 ;
  wire \NlwInverterSignal_DCOR1CNTLOWr_MC.D1/IN6 ;
  wire \NlwInverterSignal_DCOR1CNTLOWr_MC.D1/IN7 ;
  wire \NlwInverterSignal_U1/U3/holdingreg0<8>_MC.D2_PT_1/IN1 ;
  wire \NlwInverterSignal_DCOR0CNTHIGHr_MC.D1/IN1 ;
  wire \NlwInverterSignal_DCOR0CNTHIGHr_MC.D1/IN3 ;
  wire \NlwInverterSignal_DCOR0CNTHIGHr_MC.D1/IN4 ;
  wire \NlwInverterSignal_DCOR0CNTHIGHr_MC.D1/IN5 ;
  wire \NlwInverterSignal_DCOR0CNTHIGHr_MC.D1/IN6 ;
  wire \NlwInverterSignal_DCOR0CNTHIGHr_MC.D1/IN7 ;
  wire \NlwInverterSignal_DCOR0CNTHIGHr_MC.D1/IN8 ;
  wire \NlwInverterSignal_U1/U3/holdingreg1<8>_MC.D2_PT_1/IN1 ;
  wire \NlwInverterSignal_N_PZ_963_MC.D1/IN0 ;
  wire \NlwInverterSignal_N_PZ_963_MC.D1/IN1 ;
  wire \NlwInverterSignal_N_PZ_963_MC.D1/IN2 ;
  wire \NlwInverterSignal_N_PZ_963_MC.D1/IN3 ;
  wire \NlwInverterSignal_DCOR1CNTHIGHr_MC.D1/IN1 ;
  wire \NlwInverterSignal_DCOR1CNTHIGHr_MC.D1/IN3 ;
  wire \NlwInverterSignal_DCOR1CNTHIGHr_MC.D1/IN4 ;
  wire \NlwInverterSignal_DCOR1CNTHIGHr_MC.D1/IN5 ;
  wire \NlwInverterSignal_DCOR1CNTHIGHr_MC.D1/IN6 ;
  wire \NlwInverterSignal_DCOR1CNTHIGHr_MC.D1/IN7 ;
  wire \NlwInverterSignal_N_PZ_980_MC.D1/IN0 ;
  wire \NlwInverterSignal_N_PZ_980_MC.D1/IN1 ;
  wire \NlwInverterSignal_N_PZ_980_MC.D1/IN2 ;
  wire \NlwInverterSignal_N_PZ_980_MC.D1/IN3 ;
  wire \NlwInverterSignal_N_PZ_980_MC.D1/IN4 ;
  wire \NlwInverterSignal_DCOR1THRESHIGHr_MC.D1/IN1 ;
  wire \NlwInverterSignal_DCOR1THRESHIGHr_MC.D1/IN3 ;
  wire \NlwInverterSignal_DCOR1THRESHIGHr_MC.D1/IN4 ;
  wire \NlwInverterSignal_DCOR1THRESHIGHr_MC.D1/IN5 ;
  wire \NlwInverterSignal_DCOR1THRESHIGHr_MC.D1/IN6 ;
  wire \NlwInverterSignal_DCOR1THRESHIGHr_MC.D1/IN9 ;
  wire \NlwInverterSignal_outDATA<1>\$WA3.UIM_MC.D2_PT_0/IN0 ;
  wire \NlwInverterSignal_outDATA<1>\$WA3.UIM_MC.D2_PT_2/IN1 ;
  wire \NlwInverterSignal_outDATA<1>\$WA6.UIM_MC.D2_PT_1/IN0 ;
  wire \NlwInverterSignal_outDATA<1>\$WA6.UIM_MC.D2_PT_2/IN0 ;
  wire \NlwInverterSignal_outDATA<1>\$WA6.UIM_MC.D2_PT_2/IN1 ;
  wire \NlwInverterSignal_outDATA<1>\$WA6.UIM_MC.D2_PT_3/IN0 ;
  wire \NlwInverterSignal_outDATA<1>\$WA6.UIM_MC.D2_PT_3/IN1 ;
  wire \NlwInverterSignal_outDATA<1>\$WA6.UIM_MC.D2_PT_3/IN2 ;
  wire \NlwInverterSignal_U1/U4/Latch0r<1>_MC.D2_PT_1/IN1 ;
  wire \NlwInverterSignal_U1/U4/Latch0r<9>_MC.D2_PT_1/IN1 ;
  wire \NlwInverterSignal_U1/Channel0<9>_MC.D2_PT_0/IN0 ;
  wire \NlwInverterSignal_U1/Channel0<9>_MC.D2_PT_2/IN0 ;
  wire \NlwInverterSignal_U1/U4/Latch1r<1>_MC.D2_PT_1/IN1 ;
  wire \NlwInverterSignal_U1/U4/Latch1r<1>_MC.D2_PT_1/IN2 ;
  wire \NlwInverterSignal_U1/U4/Latch1r<9>_MC.D2_PT_1/IN1 ;
  wire \NlwInverterSignal_U1/U4/Latch1r<9>_MC.D2_PT_1/IN2 ;
  wire \NlwInverterSignal_U1/Channel1<9>_MC.D2_PT_0/IN0 ;
  wire \NlwInverterSignal_U1/Channel1<9>_MC.D2_PT_1/IN1 ;
  wire \NlwInverterSignal_U1/Channel1<9>_MC.D2_PT_1/IN3 ;
  wire \NlwInverterSignal_U1/Channel1<9>_MC.D2_PT_2/IN1 ;
  wire \NlwInverterSignal_U1/Channel1<9>_MC.D2_PT_2/IN3 ;
  wire \NlwInverterSignal_outDATA<1>\$WA5.UIM_MC.D2_PT_1/IN0 ;
  wire \NlwInverterSignal_outDATA<1>\$WA5.UIM_MC.D2_PT_2/IN0 ;
  wire \NlwInverterSignal_outDATA<1>\$WA5.UIM_MC.D2_PT_2/IN1 ;
  wire \NlwInverterSignal_outDATA<1>\$WA5.UIM_MC.D2_PT_3/IN0 ;
  wire \NlwInverterSignal_outDATA<1>\$WA5.UIM_MC.D2_PT_3/IN1 ;
  wire \NlwInverterSignal_outDATA<1>\$WA5.UIM_MC.D2_PT_3/IN2 ;
  wire \NlwInverterSignal_U1/U3/holdingreg0<1>_MC.D2_PT_1/IN1 ;
  wire \NlwInverterSignal_U1/U3/holdingreg1<1>_MC.D2_PT_1/IN1 ;
  wire \NlwInverterSignal_U1/U3/holdingreg0<9>_MC.D2_PT_1/IN1 ;
  wire \NlwInverterSignal_U1/U3/holdingreg1<9>_MC.D2_PT_1/IN1 ;
  wire \NlwInverterSignal_outDATA<2>\$WA3.UIM_MC.D2_PT_1/IN0 ;
  wire \NlwInverterSignal_outDATA<2>\$WA5.UIM_MC.D2_PT_1/IN0 ;
  wire \NlwInverterSignal_outDATA<2>\$WA5.UIM_MC.D2_PT_2/IN0 ;
  wire \NlwInverterSignal_outDATA<2>\$WA5.UIM_MC.D2_PT_2/IN1 ;
  wire \NlwInverterSignal_outDATA<2>\$WA5.UIM_MC.D2_PT_3/IN0 ;
  wire \NlwInverterSignal_outDATA<2>\$WA5.UIM_MC.D2_PT_3/IN1 ;
  wire \NlwInverterSignal_outDATA<2>\$WA5.UIM_MC.D2_PT_3/IN2 ;
  wire \NlwInverterSignal_U1/U3/holdingreg0<2>_MC.D2_PT_1/IN1 ;
  wire \NlwInverterSignal_U1/U3/holdingreg1<2>_MC.D2_PT_1/IN1 ;
  wire \NlwInverterSignal_U1/U3/holdingreg0<10>_MC.D2_PT_1/IN1 ;
  wire \NlwInverterSignal_U1/Channel0<10>_MC.D2_PT_0/IN0 ;
  wire \NlwInverterSignal_U1/Channel0<10>_MC.D2_PT_1/IN2 ;
  wire \NlwInverterSignal_U1/Channel0<10>_MC.D2_PT_2/IN0 ;
  wire \NlwInverterSignal_U1/U3/holdingreg1<10>_MC.D2_PT_1/IN1 ;
  wire \NlwInverterSignal_U1/Channel1<10>_MC.D2_PT_0/IN0 ;
  wire \NlwInverterSignal_U1/Channel1<10>_MC.D2_PT_1/IN1 ;
  wire \NlwInverterSignal_U1/Channel1<10>_MC.D2_PT_1/IN3 ;
  wire \NlwInverterSignal_U1/Channel1<10>_MC.D2_PT_2/IN1 ;
  wire \NlwInverterSignal_U1/Channel1<10>_MC.D2_PT_2/IN3 ;
  wire \NlwInverterSignal_U1/Channel1<10>_MC.D2_PT_2/IN5 ;
  wire \NlwInverterSignal_outDATA<2>\$WA6.UIM_MC.D2_PT_1/IN1 ;
  wire \NlwInverterSignal_outDATA<2>\$WA6.UIM_MC.D2_PT_2/IN0 ;
  wire \NlwInverterSignal_outDATA<2>\$WA6.UIM_MC.D2_PT_2/IN1 ;
  wire \NlwInverterSignal_outDATA<2>\$WA6.UIM_MC.D2_PT_3/IN0 ;
  wire \NlwInverterSignal_outDATA<2>\$WA6.UIM_MC.D2_PT_3/IN1 ;
  wire \NlwInverterSignal_outDATA<2>\$WA6.UIM_MC.D2_PT_3/IN2 ;
  wire \NlwInverterSignal_outDATA<2>\$WA6.UIM_MC.D2_PT_4/IN0 ;
  wire \NlwInverterSignal_outDATA<2>\$WA6.UIM_MC.D2_PT_4/IN1 ;
  wire \NlwInverterSignal_outDATA<2>\$WA6.UIM_MC.D2_PT_4/IN2 ;
  wire \NlwInverterSignal_outDATA<2>\$WA6.UIM_MC.D2_PT_4/IN3 ;
  wire \NlwInverterSignal_U1/U4/Latch0r<2>_MC.D2_PT_1/IN1 ;
  wire \NlwInverterSignal_U1/U4/Latch0r<10>_MC.D2_PT_1/IN1 ;
  wire \NlwInverterSignal_U1/U4/Latch1r<2>_MC.D2_PT_1/IN1 ;
  wire \NlwInverterSignal_U1/U4/Latch1r<2>_MC.D2_PT_1/IN2 ;
  wire \NlwInverterSignal_U1/U4/Latch1r<10>_MC.D2_PT_1/IN1 ;
  wire \NlwInverterSignal_U1/U4/Latch1r<10>_MC.D2_PT_1/IN2 ;
  wire \NlwInverterSignal_outDATA<3>\$WA3.UIM_MC.D2_PT_1/IN0 ;
  wire \NlwInverterSignal_outDATA<3>\$WA5.UIM_MC.D2_PT_1/IN0 ;
  wire \NlwInverterSignal_outDATA<3>\$WA5.UIM_MC.D2_PT_2/IN0 ;
  wire \NlwInverterSignal_outDATA<3>\$WA5.UIM_MC.D2_PT_2/IN1 ;
  wire \NlwInverterSignal_outDATA<3>\$WA5.UIM_MC.D2_PT_3/IN0 ;
  wire \NlwInverterSignal_outDATA<3>\$WA5.UIM_MC.D2_PT_3/IN1 ;
  wire \NlwInverterSignal_outDATA<3>\$WA5.UIM_MC.D2_PT_3/IN2 ;
  wire \NlwInverterSignal_U1/U3/holdingreg0<3>_MC.D2_PT_1/IN1 ;
  wire \NlwInverterSignal_U1/U3/holdingreg1<3>_MC.D2_PT_1/IN1 ;
  wire \NlwInverterSignal_U1/U3/holdingreg0<11>_MC.D2_PT_1/IN1 ;
  wire \NlwInverterSignal_U1/Channel0<11>_MC.D2_PT_0/IN0 ;
  wire \NlwInverterSignal_U1/Channel0<11>_MC.D2_PT_1/IN2 ;
  wire \NlwInverterSignal_U1/Channel0<11>_MC.D2_PT_1/IN3 ;
  wire \NlwInverterSignal_U1/Channel0<11>_MC.D2_PT_2/IN0 ;
  wire \NlwInverterSignal_U1/U3/holdingreg1<11>_MC.D2_PT_1/IN1 ;
  wire \NlwInverterSignal_U1/Channel1<11>_MC.D2_PT_0/IN0 ;
  wire \NlwInverterSignal_U1/Channel1<11>_MC.D2_PT_1/IN1 ;
  wire \NlwInverterSignal_U1/Channel1<11>_MC.D2_PT_1/IN3 ;
  wire \NlwInverterSignal_U1/Channel1<11>_MC.D2_PT_2/IN1 ;
  wire \NlwInverterSignal_U1/Channel1<11>_MC.D2_PT_2/IN3 ;
  wire \NlwInverterSignal_U1/Channel1<11>_MC.D2_PT_2/IN5 ;
  wire \NlwInverterSignal_U1/Channel1<11>_MC.D2_PT_2/IN6 ;
  wire \NlwInverterSignal_outDATA<3>\$WA6.UIM_MC.D2_PT_1/IN1 ;
  wire \NlwInverterSignal_outDATA<3>\$WA6.UIM_MC.D2_PT_2/IN0 ;
  wire \NlwInverterSignal_outDATA<3>\$WA6.UIM_MC.D2_PT_2/IN1 ;
  wire \NlwInverterSignal_outDATA<3>\$WA6.UIM_MC.D2_PT_3/IN0 ;
  wire \NlwInverterSignal_outDATA<3>\$WA6.UIM_MC.D2_PT_3/IN1 ;
  wire \NlwInverterSignal_outDATA<3>\$WA6.UIM_MC.D2_PT_3/IN2 ;
  wire \NlwInverterSignal_outDATA<3>\$WA6.UIM_MC.D2_PT_4/IN0 ;
  wire \NlwInverterSignal_outDATA<3>\$WA6.UIM_MC.D2_PT_4/IN1 ;
  wire \NlwInverterSignal_outDATA<3>\$WA6.UIM_MC.D2_PT_4/IN2 ;
  wire \NlwInverterSignal_outDATA<3>\$WA6.UIM_MC.D2_PT_4/IN3 ;
  wire \NlwInverterSignal_U1/U4/Latch0r<3>_MC.D2_PT_1/IN1 ;
  wire \NlwInverterSignal_U1/U4/Latch0r<11>_MC.D2_PT_1/IN1 ;
  wire \NlwInverterSignal_U1/U4/Latch1r<3>_MC.D2_PT_1/IN1 ;
  wire \NlwInverterSignal_U1/U4/Latch1r<3>_MC.D2_PT_1/IN2 ;
  wire \NlwInverterSignal_U1/U4/Latch1r<11>_MC.D2_PT_1/IN1 ;
  wire \NlwInverterSignal_U1/U4/Latch1r<11>_MC.D2_PT_1/IN2 ;
  wire \NlwInverterSignal_outDATA<4>\$WA3.UIM_MC.D2_PT_1/IN0 ;
  wire \NlwInverterSignal_outDATA<4>\$WA6.UIM_MC.D2_PT_1/IN0 ;
  wire \NlwInverterSignal_outDATA<4>\$WA6.UIM_MC.D2_PT_2/IN0 ;
  wire \NlwInverterSignal_outDATA<4>\$WA6.UIM_MC.D2_PT_2/IN1 ;
  wire \NlwInverterSignal_outDATA<4>\$WA6.UIM_MC.D2_PT_3/IN0 ;
  wire \NlwInverterSignal_outDATA<4>\$WA6.UIM_MC.D2_PT_3/IN1 ;
  wire \NlwInverterSignal_outDATA<4>\$WA6.UIM_MC.D2_PT_3/IN2 ;
  wire \NlwInverterSignal_U1/U4/Latch0r<4>_MC.D2_PT_1/IN1 ;
  wire \NlwInverterSignal_U1/U4/Latch0r<12>_MC.D2_PT_1/IN1 ;
  wire \NlwInverterSignal_U1/Channel0<12>_MC.D2_PT_0/IN0 ;
  wire \NlwInverterSignal_U1/Channel0<12>_MC.D2_PT_1/IN2 ;
  wire \NlwInverterSignal_U1/Channel0<12>_MC.D2_PT_1/IN3 ;
  wire \NlwInverterSignal_U1/Channel0<12>_MC.D2_PT_1/IN4 ;
  wire \NlwInverterSignal_U1/Channel0<12>_MC.D2_PT_2/IN0 ;
  wire \NlwInverterSignal_U1/U4/Latch1r<4>_MC.D2_PT_1/IN1 ;
  wire \NlwInverterSignal_U1/U4/Latch1r<4>_MC.D2_PT_1/IN2 ;
  wire \NlwInverterSignal_U1/U4/Latch1r<12>_MC.D2_PT_1/IN1 ;
  wire \NlwInverterSignal_U1/U4/Latch1r<12>_MC.D2_PT_1/IN2 ;
  wire \NlwInverterSignal_U1/Channel1<12>_MC.D2_PT_0/IN0 ;
  wire \NlwInverterSignal_U1/Channel1<12>_MC.D2_PT_1/IN1 ;
  wire \NlwInverterSignal_U1/Channel1<12>_MC.D2_PT_1/IN4 ;
  wire \NlwInverterSignal_U1/Channel1<12>_MC.D2_PT_2/IN1 ;
  wire \NlwInverterSignal_U1/Channel1<12>_MC.D2_PT_2/IN3 ;
  wire \NlwInverterSignal_U1/Channel1<12>_MC.D2_PT_2/IN5 ;
  wire \NlwInverterSignal_U1/Channel1<12>_MC.D2_PT_2/IN6 ;
  wire \NlwInverterSignal_U1/Channel1<12>_MC.D2_PT_2/IN7 ;
  wire \NlwInverterSignal_outDATA<4>\$WA5.UIM_MC.D2_PT_1/IN0 ;
  wire \NlwInverterSignal_outDATA<4>\$WA5.UIM_MC.D2_PT_2/IN0 ;
  wire \NlwInverterSignal_outDATA<4>\$WA5.UIM_MC.D2_PT_2/IN1 ;
  wire \NlwInverterSignal_outDATA<4>\$WA5.UIM_MC.D2_PT_3/IN0 ;
  wire \NlwInverterSignal_outDATA<4>\$WA5.UIM_MC.D2_PT_3/IN1 ;
  wire \NlwInverterSignal_outDATA<4>\$WA5.UIM_MC.D2_PT_3/IN2 ;
  wire \NlwInverterSignal_U1/U3/holdingreg0<4>_MC.D2_PT_1/IN1 ;
  wire \NlwInverterSignal_U1/U3/holdingreg1<4>_MC.D2_PT_1/IN1 ;
  wire \NlwInverterSignal_U1/U3/holdingreg0<12>_MC.D2_PT_1/IN1 ;
  wire \NlwInverterSignal_U1/U3/holdingreg1<12>_MC.D2_PT_1/IN1 ;
  wire \NlwInverterSignal_outDATA<5>\$WA3.UIM_MC.D2_PT_1/IN0 ;
  wire \NlwInverterSignal_outDATA<5>\$WA5.UIM_MC.D2_PT_1/IN0 ;
  wire \NlwInverterSignal_outDATA<5>\$WA5.UIM_MC.D2_PT_2/IN0 ;
  wire \NlwInverterSignal_outDATA<5>\$WA5.UIM_MC.D2_PT_2/IN1 ;
  wire \NlwInverterSignal_outDATA<5>\$WA5.UIM_MC.D2_PT_3/IN0 ;
  wire \NlwInverterSignal_outDATA<5>\$WA5.UIM_MC.D2_PT_3/IN1 ;
  wire \NlwInverterSignal_outDATA<5>\$WA5.UIM_MC.D2_PT_3/IN2 ;
  wire \NlwInverterSignal_U1/U3/holdingreg0<5>_MC.D2_PT_1/IN1 ;
  wire \NlwInverterSignal_U1/U3/holdingreg1<5>_MC.D2_PT_1/IN1 ;
  wire \NlwInverterSignal_U1/U3/holdingreg0<13>_MC.D2_PT_1/IN1 ;
  wire \NlwInverterSignal_U1/Channel0<13>_MC.D2_PT_0/IN0 ;
  wire \NlwInverterSignal_U1/Channel0<13>_MC.D2_PT_1/IN2 ;
  wire \NlwInverterSignal_U1/Channel0<13>_MC.D2_PT_1/IN3 ;
  wire \NlwInverterSignal_U1/Channel0<13>_MC.D2_PT_1/IN4 ;
  wire \NlwInverterSignal_U1/Channel0<13>_MC.D2_PT_1/IN5 ;
  wire \NlwInverterSignal_U1/Channel0<13>_MC.D2_PT_2/IN0 ;
  wire \NlwInverterSignal_U1/U3/holdingreg1<13>_MC.D2_PT_1/IN1 ;
  wire \NlwInverterSignal_U1/Channel1<13>_MC.D2_PT_0/IN0 ;
  wire \NlwInverterSignal_U1/Channel1<13>_MC.D2_PT_1/IN1 ;
  wire \NlwInverterSignal_U1/Channel1<13>_MC.D2_PT_1/IN4 ;
  wire \NlwInverterSignal_U1/Channel1<13>_MC.D2_PT_2/IN1 ;
  wire \NlwInverterSignal_U1/Channel1<13>_MC.D2_PT_2/IN3 ;
  wire \NlwInverterSignal_U1/Channel1<13>_MC.D2_PT_2/IN5 ;
  wire \NlwInverterSignal_U1/Channel1<13>_MC.D2_PT_2/IN6 ;
  wire \NlwInverterSignal_U1/Channel1<13>_MC.D2_PT_2/IN7 ;
  wire \NlwInverterSignal_U1/Channel1<13>_MC.D2_PT_2/IN8 ;
  wire \NlwInverterSignal_outDATA<5>\$WA6.UIM_MC.D2_PT_1/IN1 ;
  wire \NlwInverterSignal_outDATA<5>\$WA6.UIM_MC.D2_PT_2/IN0 ;
  wire \NlwInverterSignal_outDATA<5>\$WA6.UIM_MC.D2_PT_2/IN1 ;
  wire \NlwInverterSignal_outDATA<5>\$WA6.UIM_MC.D2_PT_3/IN0 ;
  wire \NlwInverterSignal_outDATA<5>\$WA6.UIM_MC.D2_PT_3/IN1 ;
  wire \NlwInverterSignal_outDATA<5>\$WA6.UIM_MC.D2_PT_3/IN2 ;
  wire \NlwInverterSignal_outDATA<5>\$WA6.UIM_MC.D2_PT_4/IN0 ;
  wire \NlwInverterSignal_outDATA<5>\$WA6.UIM_MC.D2_PT_4/IN1 ;
  wire \NlwInverterSignal_outDATA<5>\$WA6.UIM_MC.D2_PT_4/IN2 ;
  wire \NlwInverterSignal_outDATA<5>\$WA6.UIM_MC.D2_PT_4/IN3 ;
  wire \NlwInverterSignal_U1/U4/Latch0r<5>_MC.D2_PT_1/IN1 ;
  wire \NlwInverterSignal_U1/U4/Latch0r<13>_MC.D2_PT_1/IN1 ;
  wire \NlwInverterSignal_U1/U4/Latch1r<5>_MC.D2_PT_1/IN1 ;
  wire \NlwInverterSignal_U1/U4/Latch1r<5>_MC.D2_PT_1/IN2 ;
  wire \NlwInverterSignal_U1/U4/Latch1r<13>_MC.D2_PT_1/IN1 ;
  wire \NlwInverterSignal_U1/U4/Latch1r<13>_MC.D2_PT_1/IN2 ;
  wire \NlwInverterSignal_outDATA<6>\$WA3.UIM_MC.D2_PT_1/IN0 ;
  wire \NlwInverterSignal_outDATA<6>\$WA5.UIM_MC.D2_PT_1/IN0 ;
  wire \NlwInverterSignal_outDATA<6>\$WA5.UIM_MC.D2_PT_2/IN0 ;
  wire \NlwInverterSignal_outDATA<6>\$WA5.UIM_MC.D2_PT_2/IN1 ;
  wire \NlwInverterSignal_outDATA<6>\$WA5.UIM_MC.D2_PT_3/IN0 ;
  wire \NlwInverterSignal_outDATA<6>\$WA5.UIM_MC.D2_PT_3/IN1 ;
  wire \NlwInverterSignal_outDATA<6>\$WA5.UIM_MC.D2_PT_3/IN2 ;
  wire \NlwInverterSignal_U1/U3/holdingreg0<6>_MC.D2_PT_1/IN1 ;
  wire \NlwInverterSignal_U1/U3/holdingreg1<6>_MC.D2_PT_1/IN1 ;
  wire \NlwInverterSignal_U1/U3/holdingreg0<14>_MC.D2_PT_1/IN1 ;
  wire \NlwInverterSignal_U1/Channel0<14>_MC.D2_PT_0/IN0 ;
  wire \NlwInverterSignal_U1/Channel0<14>_MC.D2_PT_1/IN2 ;
  wire \NlwInverterSignal_U1/Channel0<14>_MC.D2_PT_1/IN3 ;
  wire \NlwInverterSignal_U1/Channel0<14>_MC.D2_PT_1/IN4 ;
  wire \NlwInverterSignal_U1/Channel0<14>_MC.D2_PT_1/IN5 ;
  wire \NlwInverterSignal_U1/Channel0<14>_MC.D2_PT_1/IN6 ;
  wire \NlwInverterSignal_U1/Channel0<14>_MC.D2_PT_2/IN0 ;
  wire \NlwInverterSignal_U1/U3/holdingreg1<14>_MC.D2_PT_1/IN1 ;
  wire \NlwInverterSignal_U1/Channel1<14>_MC.D2_PT_0/IN0 ;
  wire \NlwInverterSignal_U1/Channel1<14>_MC.D2_PT_1/IN1 ;
  wire \NlwInverterSignal_U1/Channel1<14>_MC.D2_PT_1/IN3 ;
  wire \NlwInverterSignal_U1/Channel1<14>_MC.D2_PT_2/IN1 ;
  wire \NlwInverterSignal_U1/Channel1<14>_MC.D2_PT_2/IN3 ;
  wire \NlwInverterSignal_U1/Channel1<14>_MC.D2_PT_2/IN5 ;
  wire \NlwInverterSignal_U1/Channel1<14>_MC.D2_PT_2/IN6 ;
  wire \NlwInverterSignal_U1/Channel1<14>_MC.D2_PT_2/IN7 ;
  wire \NlwInverterSignal_U1/Channel1<14>_MC.D2_PT_2/IN8 ;
  wire \NlwInverterSignal_U1/Channel1<14>_MC.D2_PT_2/IN9 ;
  wire \NlwInverterSignal_outDATA<6>\$WA6.UIM_MC.D2_PT_1/IN1 ;
  wire \NlwInverterSignal_outDATA<6>\$WA6.UIM_MC.D2_PT_2/IN0 ;
  wire \NlwInverterSignal_outDATA<6>\$WA6.UIM_MC.D2_PT_2/IN1 ;
  wire \NlwInverterSignal_outDATA<6>\$WA6.UIM_MC.D2_PT_3/IN0 ;
  wire \NlwInverterSignal_outDATA<6>\$WA6.UIM_MC.D2_PT_3/IN1 ;
  wire \NlwInverterSignal_outDATA<6>\$WA6.UIM_MC.D2_PT_3/IN2 ;
  wire \NlwInverterSignal_outDATA<6>\$WA6.UIM_MC.D2_PT_4/IN0 ;
  wire \NlwInverterSignal_outDATA<6>\$WA6.UIM_MC.D2_PT_4/IN1 ;
  wire \NlwInverterSignal_outDATA<6>\$WA6.UIM_MC.D2_PT_4/IN2 ;
  wire \NlwInverterSignal_outDATA<6>\$WA6.UIM_MC.D2_PT_4/IN3 ;
  wire \NlwInverterSignal_U1/U4/Latch0r<6>_MC.D2_PT_1/IN1 ;
  wire \NlwInverterSignal_U1/U4/Latch0r<14>_MC.D2_PT_1/IN1 ;
  wire \NlwInverterSignal_U1/U4/Latch1r<6>_MC.D2_PT_1/IN1 ;
  wire \NlwInverterSignal_U1/U4/Latch1r<6>_MC.D2_PT_1/IN2 ;
  wire \NlwInverterSignal_U1/U4/Latch1r<14>_MC.D2_PT_1/IN1 ;
  wire \NlwInverterSignal_U1/U4/Latch1r<14>_MC.D2_PT_1/IN2 ;
  wire \NlwInverterSignal_outDATA<7>\$WA3.UIM_MC.D2_PT_1/IN0 ;
  wire \NlwInverterSignal_outDATA<7>\$WA6.UIM_MC.D2_PT_1/IN0 ;
  wire \NlwInverterSignal_outDATA<7>\$WA6.UIM_MC.D2_PT_2/IN0 ;
  wire \NlwInverterSignal_outDATA<7>\$WA6.UIM_MC.D2_PT_2/IN1 ;
  wire \NlwInverterSignal_outDATA<7>\$WA6.UIM_MC.D2_PT_3/IN0 ;
  wire \NlwInverterSignal_outDATA<7>\$WA6.UIM_MC.D2_PT_3/IN1 ;
  wire \NlwInverterSignal_outDATA<7>\$WA6.UIM_MC.D2_PT_3/IN2 ;
  wire \NlwInverterSignal_U1/U4/Latch0r<7>_MC.D2_PT_1/IN1 ;
  wire \NlwInverterSignal_U1/U4/Latch0r<15>_MC.D2_PT_1/IN1 ;
  wire \NlwInverterSignal_U1/Channel0<15>_MC.D2_PT_0/IN0 ;
  wire \NlwInverterSignal_U1/Channel0<15>_MC.D2_PT_1/IN2 ;
  wire \NlwInverterSignal_U1/Channel0<15>_MC.D2_PT_1/IN3 ;
  wire \NlwInverterSignal_U1/Channel0<15>_MC.D2_PT_1/IN4 ;
  wire \NlwInverterSignal_U1/Channel0<15>_MC.D2_PT_1/IN5 ;
  wire \NlwInverterSignal_U1/Channel0<15>_MC.D2_PT_1/IN6 ;
  wire \NlwInverterSignal_U1/Channel0<15>_MC.D2_PT_1/IN7 ;
  wire \NlwInverterSignal_U1/Channel0<15>_MC.D2_PT_2/IN0 ;
  wire \NlwInverterSignal_U1/U4/Latch1r<7>_MC.D2_PT_1/IN1 ;
  wire \NlwInverterSignal_U1/U4/Latch1r<7>_MC.D2_PT_1/IN2 ;
  wire \NlwInverterSignal_U1/U4/Latch1r<15>_MC.D2_PT_1/IN1 ;
  wire \NlwInverterSignal_U1/U4/Latch1r<15>_MC.D2_PT_1/IN2 ;
  wire \NlwInverterSignal_U1/Channel1<15>_MC.D2_PT_0/IN0 ;
  wire \NlwInverterSignal_U1/Channel1<15>_MC.D2_PT_1/IN1 ;
  wire \NlwInverterSignal_U1/Channel1<15>_MC.D2_PT_1/IN3 ;
  wire \NlwInverterSignal_U1/Channel1<15>_MC.D2_PT_2/IN1 ;
  wire \NlwInverterSignal_U1/Channel1<15>_MC.D2_PT_2/IN3 ;
  wire \NlwInverterSignal_U1/Channel1<15>_MC.D2_PT_2/IN5 ;
  wire \NlwInverterSignal_U1/Channel1<15>_MC.D2_PT_2/IN6 ;
  wire \NlwInverterSignal_U1/Channel1<15>_MC.D2_PT_2/IN7 ;
  wire \NlwInverterSignal_U1/Channel1<15>_MC.D2_PT_2/IN8 ;
  wire \NlwInverterSignal_U1/Channel1<15>_MC.D2_PT_2/IN9 ;
  wire \NlwInverterSignal_U1/Channel1<15>_MC.D2_PT_2/IN10 ;
  wire \NlwInverterSignal_outDATA<7>\$WA5.UIM_MC.D2_PT_1/IN0 ;
  wire \NlwInverterSignal_outDATA<7>\$WA5.UIM_MC.D2_PT_2/IN0 ;
  wire \NlwInverterSignal_outDATA<7>\$WA5.UIM_MC.D2_PT_2/IN1 ;
  wire \NlwInverterSignal_outDATA<7>\$WA5.UIM_MC.D2_PT_3/IN0 ;
  wire \NlwInverterSignal_outDATA<7>\$WA5.UIM_MC.D2_PT_3/IN1 ;
  wire \NlwInverterSignal_outDATA<7>\$WA5.UIM_MC.D2_PT_3/IN2 ;
  wire \NlwInverterSignal_U1/U3/holdingreg0<7>_MC.D2_PT_1/IN1 ;
  wire \NlwInverterSignal_U1/U3/holdingreg1<7>_MC.D2_PT_1/IN1 ;
  wire \NlwInverterSignal_U1/U3/holdingreg0<15>_MC.D2_PT_1/IN1 ;
  wire \NlwInverterSignal_U1/U3/holdingreg1<15>_MC.D2_PT_1/IN1 ;
  wire \NlwInverterSignal_FOOBAR2__ctinst/7/OUT ;
  wire \NlwInverterSignal_FOOBAR3__ctinst/7/OUT ;
  wire \NlwInverterSignal_FOOBAR8__ctinst/4/IN1 ;
  wire \NlwInverterSignal_FOOBAR21__ctinst/4/IN0 ;
  wire \NlwInverterSignal_FOOBAR21__ctinst/4/IN1 ;
  wire \NlwInverterSignal_FOOBAR24__ctinst/4/IN0 ;
  wire \NlwInverterSignal_FOOBAR24__ctinst/4/IN1 ;
  wire [7 : 0] \U4/ctrlr ;
  wire [7 : 0] \U4/Flgreg ;
  wire [7 : 0] U2_ADDR_reg;
  wire [7 : 0] \U3/DCORIE ;
  wire [5 : 0] U11_U3_counterr;
  wire [4 : 0] \U9/MISCr ;
  wire [15 : 0] \U1/U4/Latch0r ;
  wire [15 : 0] \U1/U4/Latch1r ;
  wire [15 : 0] \U1/Channel0 ;
  wire [0 : 0] \U1/U2/location_Maddsub__n0000__n0075 ;
  wire [0 : 0] \U1/U2/location_Maddsub__n0000__n0067 ;
  wire [15 : 0] \U1/Channel1 ;
  wire [0 : 0] \U1/U5/location_Maddsub__n0000__n0075 ;
  wire [0 : 0] \U1/U5/location_Maddsub__n0000__n0067 ;
  wire [15 : 0] \U1/U3/holdingreg0 ;
  wire [15 : 0] \U1/U3/holdingreg1 ;
  assign
    NlwRenamedSig_IO_WR = WR,
    NlwRenamedSig_IO_RD = RD,
    NlwRenamedSig_IO_AS = AS,
    NlwRenamedSig_IO_Home15FLG = Home15FLG,
    NlwRenamedSig_IO_Home133FLG = Home133FLG,
    NlwRenamedSig_IO_Home05FLG = Home05FLG,
    NlwRenamedSig_IO_Home033FLG = Home033FLG,
    NlwRenamedSig_IO_Enc15FLG = Enc15FLG,
    NlwRenamedSig_IO_Enc133FLG = Enc133FLG,
    NlwRenamedSig_IO_Enc05FLG = Enc05FLG,
    NlwRenamedSig_IO_Enc033FLG = Enc033FLG;
  initial $sdf_annotate("c:/projects/genosensor/2g/cplds/core/u21/implement/time_sim.sdf");
  X_IPAD \Brake0.PAD  (
    .PAD(Brake0)
  );
  X_BUF \Brake0_II/UIM_0  (
    .I(Brake0),
    .O(\Brake0_II/UIM )
  );
  X_IPAD \Brake1.PAD  (
    .PAD(Brake1)
  );
  X_BUF \Brake1_II/UIM_1  (
    .I(Brake1),
    .O(\Brake1_II/UIM )
  );
  X_IPAD \DIR0.PAD  (
    .PAD(DIR0)
  );
  X_BUF \DIR0_II/UIM_2  (
    .I(DIR0),
    .O(\DIR0_II/UIM )
  );
  X_IPAD \DIR1.PAD  (
    .PAD(DIR1)
  );
  X_BUF \DIR1_II/UIM_3  (
    .I(DIR1),
    .O(\DIR1_II/UIM )
  );
  X_IPAD \WR.PAD  (
    .PAD(NlwRenamedSig_IO_WR)
  );
  X_PU WR_tsimcreated__pullup_ (
    .O(NlwRenamedSig_IO_WR)
  );
  X_BUF \WR_II/UIM_4  (
    .I(NlwRenamedSig_IO_WR),
    .O(\WR_II/UIM )
  );
  X_IPAD \RD.PAD  (
    .PAD(NlwRenamedSig_IO_RD)
  );
  X_PU RD_tsimcreated__pullup_ (
    .O(NlwRenamedSig_IO_RD)
  );
  X_BUF \RD_II/UIM_5  (
    .I(NlwRenamedSig_IO_RD),
    .O(\RD_II/UIM )
  );
  X_IPAD \MSPReset.PAD  (
    .PAD(MSPReset)
  );
  X_BUF \MSPReset_II/UIM_6  (
    .I(MSPReset),
    .O(\MSPReset_II/UIM )
  );
  X_BUF \AD<0>_II/UIM_7  (
    .I(AD[0]),
    .O(\AD<0>_II/UIM )
  );
  X_BUF \AD<0>_II/IREG_8  (
    .I(\U4/ctrlr [0]),
    .O(\AD<0>_II/IREG )
  );
  X_OR2 \U4/ctrlr<0>_MC_tsimcreated_prld__9  (
    .I0(\FOOBAR3__ctinst/7 ),
    .I1(PRLD),
    .O(\U4/ctrlr<0>_MC_tsimcreated_prld_ )
  );
  X_FF \U4/ctrlr<0>_MC.REG  (
    .I(AD[0]),
    .CE(\FOOBAR12__ctinst/4 ),
    .CLK(\U4/ctrlr<0>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(\U4/ctrlr<0>_MC_tsimcreated_prld_ ),
    .O(\U4/ctrlr [0])
  );
  X_INV \U4/ctrlr<0>_MC.REG_tsimcreated_inv_Mclk_II/FCLK_10  (
    .I(\Mclk_II/FCLK ),
    .O(\U4/ctrlr<0>_MC.REG_tsimcreated_inv_Mclk_II/FCLK )
  );
  X_ZERO Gnd_11 (
    .O(Gnd)
  );
  X_IPAD \AS.PAD  (
    .PAD(NlwRenamedSig_IO_AS)
  );
  X_PU AS_tsimcreated__pullup_ (
    .O(NlwRenamedSig_IO_AS)
  );
  X_BUF \AS_II/UIM_12  (
    .I(NlwRenamedSig_IO_AS),
    .O(\AS_II/UIM )
  );
  X_BUF \AS_II/IREG_13  (
    .I(U2_ASedge),
    .O(\AS_II/IREG )
  );
  X_FF \U2_ASedge_MC.REG  (
    .I(NlwRenamedSig_IO_AS),
    .CE(Vcc),
    .CLK(\U2_ASedge_MC.REG_tsimcreated_inv_Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(U2_ASedge)
  );
  X_INV \U2_ASedge_MC.REG_tsimcreated_inv_Mclk_II/FCLK_14  (
    .I(\Mclk_II/FCLK ),
    .O(\U2_ASedge_MC.REG_tsimcreated_inv_Mclk_II/FCLK )
  );
  X_ONE Vcc_15 (
    .O(Vcc)
  );
  X_IPAD \Mclk.PAD  (
    .PAD(Mclk)
  );
  X_BUF \Mclk_II/FCLK_16  (
    .I(Mclk),
    .O(\Mclk_II/FCLK )
  );
  X_BUF \AD<4>_II/UIM_17  (
    .I(AD[4]),
    .O(\AD<4>_II/UIM )
  );
  X_BUF \AD<4>_II/IREG_18  (
    .I(\U4/ctrlr [4]),
    .O(\AD<4>_II/IREG )
  );
  X_OR2 \U4/ctrlr<4>_MC_tsimcreated_prld__19  (
    .I0(\FOOBAR3__ctinst/7 ),
    .I1(PRLD),
    .O(\U4/ctrlr<4>_MC_tsimcreated_prld_ )
  );
  X_FF \U4/ctrlr<4>_MC.REG  (
    .I(AD[4]),
    .CE(\FOOBAR10__ctinst/4 ),
    .CLK(\U4/ctrlr<4>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(\U4/ctrlr<4>_MC_tsimcreated_prld_ ),
    .O(\U4/ctrlr [4])
  );
  X_INV \U4/ctrlr<4>_MC.REG_tsimcreated_inv_Mclk_II/FCLK_20  (
    .I(\Mclk_II/FCLK ),
    .O(\U4/ctrlr<4>_MC.REG_tsimcreated_inv_Mclk_II/FCLK )
  );
  X_BUF \AD<5>_II/UIM_21  (
    .I(AD[5]),
    .O(\AD<5>_II/UIM )
  );
  X_BUF \AD<5>_II/IREG_22  (
    .I(\U4/ctrlr [5]),
    .O(\AD<5>_II/IREG )
  );
  X_OR2 \U4/ctrlr<5>_MC_tsimcreated_prld__23  (
    .I0(\FOOBAR3__ctinst/7 ),
    .I1(PRLD),
    .O(\U4/ctrlr<5>_MC_tsimcreated_prld_ )
  );
  X_FF \U4/ctrlr<5>_MC.REG  (
    .I(AD[5]),
    .CE(\FOOBAR10__ctinst/4 ),
    .CLK(\U4/ctrlr<5>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(\U4/ctrlr<5>_MC_tsimcreated_prld_ ),
    .O(\U4/ctrlr [5])
  );
  X_INV \U4/ctrlr<5>_MC.REG_tsimcreated_inv_Mclk_II/FCLK_24  (
    .I(\Mclk_II/FCLK ),
    .O(\U4/ctrlr<5>_MC.REG_tsimcreated_inv_Mclk_II/FCLK )
  );
  X_BUF \AD<6>_II/UIM_25  (
    .I(AD[6]),
    .O(\AD<6>_II/UIM )
  );
  X_BUF \AD<6>_II/IREG_26  (
    .I(\U4/ctrlr [6]),
    .O(\AD<6>_II/IREG )
  );
  X_OR2 \U4/ctrlr<6>_MC_tsimcreated_prld__27  (
    .I0(\FOOBAR3__ctinst/7 ),
    .I1(PRLD),
    .O(\U4/ctrlr<6>_MC_tsimcreated_prld_ )
  );
  X_FF \U4/ctrlr<6>_MC.REG  (
    .I(AD[6]),
    .CE(\FOOBAR10__ctinst/4 ),
    .CLK(\U4/ctrlr<6>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(\U4/ctrlr<6>_MC_tsimcreated_prld_ ),
    .O(\U4/ctrlr [6])
  );
  X_INV \U4/ctrlr<6>_MC.REG_tsimcreated_inv_Mclk_II/FCLK_28  (
    .I(\Mclk_II/FCLK ),
    .O(\U4/ctrlr<6>_MC.REG_tsimcreated_inv_Mclk_II/FCLK )
  );
  X_BUF \AD<7>_II/UIM_29  (
    .I(AD[7]),
    .O(\AD<7>_II/UIM )
  );
  X_BUF \AD<7>_II/IREG_30  (
    .I(\U4/ctrlr [7]),
    .O(\AD<7>_II/IREG )
  );
  X_OR2 \U4/ctrlr<7>_MC_tsimcreated_prld__31  (
    .I0(\FOOBAR3__ctinst/7 ),
    .I1(PRLD),
    .O(\U4/ctrlr<7>_MC_tsimcreated_prld_ )
  );
  X_FF \U4/ctrlr<7>_MC.REG  (
    .I(AD[7]),
    .CE(\FOOBAR9__ctinst/4 ),
    .CLK(\U4/ctrlr<7>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(\U4/ctrlr<7>_MC_tsimcreated_prld_ ),
    .O(\U4/ctrlr [7])
  );
  X_INV \U4/ctrlr<7>_MC.REG_tsimcreated_inv_Mclk_II/FCLK_32  (
    .I(\Mclk_II/FCLK ),
    .O(\U4/ctrlr<7>_MC.REG_tsimcreated_inv_Mclk_II/FCLK )
  );
  X_BUF \AD<3>_II/UIM_33  (
    .I(AD[3]),
    .O(\AD<3>_II/UIM )
  );
  X_BUF \AD<3>_II/IREG_34  (
    .I(\U4/ctrlr [3]),
    .O(\AD<3>_II/IREG )
  );
  X_OR2 \U4/ctrlr<3>_MC_tsimcreated_prld__35  (
    .I0(\FOOBAR3__ctinst/7 ),
    .I1(PRLD),
    .O(\U4/ctrlr<3>_MC_tsimcreated_prld_ )
  );
  X_FF \U4/ctrlr<3>_MC.REG  (
    .I(AD[3]),
    .CE(\FOOBAR12__ctinst/4 ),
    .CLK(\U4/ctrlr<3>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(\U4/ctrlr<3>_MC_tsimcreated_prld_ ),
    .O(\U4/ctrlr [3])
  );
  X_INV \U4/ctrlr<3>_MC.REG_tsimcreated_inv_Mclk_II/FCLK_36  (
    .I(\Mclk_II/FCLK ),
    .O(\U4/ctrlr<3>_MC.REG_tsimcreated_inv_Mclk_II/FCLK )
  );
  X_BUF \AD<1>_II/UIM_37  (
    .I(AD[1]),
    .O(\AD<1>_II/UIM )
  );
  X_BUF \AD<1>_II/IREG_38  (
    .I(\U4/ctrlr [1]),
    .O(\AD<1>_II/IREG )
  );
  X_OR2 \U4/ctrlr<1>_MC_tsimcreated_prld__39  (
    .I0(\FOOBAR3__ctinst/7 ),
    .I1(PRLD),
    .O(\U4/ctrlr<1>_MC_tsimcreated_prld_ )
  );
  X_FF \U4/ctrlr<1>_MC.REG  (
    .I(AD[1]),
    .CE(\FOOBAR12__ctinst/4 ),
    .CLK(\U4/ctrlr<1>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(\U4/ctrlr<1>_MC_tsimcreated_prld_ ),
    .O(\U4/ctrlr [1])
  );
  X_INV \U4/ctrlr<1>_MC.REG_tsimcreated_inv_Mclk_II/FCLK_40  (
    .I(\Mclk_II/FCLK ),
    .O(\U4/ctrlr<1>_MC.REG_tsimcreated_inv_Mclk_II/FCLK )
  );
  X_BUF \AD<2>_II/UIM_41  (
    .I(AD[2]),
    .O(\AD<2>_II/UIM )
  );
  X_BUF \AD<2>_II/IREG_42  (
    .I(\U4/ctrlr [2]),
    .O(\AD<2>_II/IREG )
  );
  X_OR2 \U4/ctrlr<2>_MC_tsimcreated_prld__43  (
    .I0(\FOOBAR3__ctinst/7 ),
    .I1(PRLD),
    .O(\U4/ctrlr<2>_MC_tsimcreated_prld_ )
  );
  X_FF \U4/ctrlr<2>_MC.REG  (
    .I(AD[2]),
    .CE(\FOOBAR12__ctinst/4 ),
    .CLK(\U4/ctrlr<2>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(\U4/ctrlr<2>_MC_tsimcreated_prld_ ),
    .O(\U4/ctrlr [2])
  );
  X_INV \U4/ctrlr<2>_MC.REG_tsimcreated_inv_Mclk_II/FCLK_44  (
    .I(\Mclk_II/FCLK ),
    .O(\U4/ctrlr<2>_MC.REG_tsimcreated_inv_Mclk_II/FCLK )
  );
  X_IPAD \FLS0.PAD  (
    .PAD(FLS0)
  );
  X_BUF \FLS0_II/UIM_45  (
    .I(FLS0),
    .O(\FLS0_II/UIM )
  );
  X_IPAD \FLS1.PAD  (
    .PAD(FLS1)
  );
  X_BUF \FLS1_II/UIM_46  (
    .I(FLS1),
    .O(\FLS1_II/UIM )
  );
  X_IPAD \PWM5.PAD  (
    .PAD(PWM5)
  );
  X_BUF \PWM5_II/UIM_47  (
    .I(PWM5),
    .O(\PWM5_II/UIM )
  );
  X_IPAD \PWM3.PAD  (
    .PAD(PWM3)
  );
  X_BUF \PWM3_II/UIM_48  (
    .I(PWM3),
    .O(\PWM3_II/UIM )
  );
  X_IPAD \HSI.PAD  (
    .PAD(HSI)
  );
  X_BUF \HSI_II/UIM_49  (
    .I(HSI),
    .O(\HSI_II/UIM )
  );
  X_IPAD \MHSO.PAD  (
    .PAD(MHSO)
  );
  X_BUF \MHSO_II/UIM_50  (
    .I(MHSO),
    .O(\MHSO_II/UIM )
  );
  X_IPAD \I2CS<0>.PAD  (
    .PAD(I2CS[0])
  );
  X_BUF \I2CS<0>_II/UIM_51  (
    .I(I2CS[0]),
    .O(\I2CS<0>_II/UIM )
  );
  X_IPAD \I2CS<1>.PAD  (
    .PAD(I2CS[1])
  );
  X_BUF \I2CS<1>_II/UIM_52  (
    .I(I2CS[1]),
    .O(\I2CS<1>_II/UIM )
  );
  X_IPAD \I2CS<2>.PAD  (
    .PAD(I2CS[2])
  );
  X_BUF \I2CS<2>_II/UIM_53  (
    .I(I2CS[2]),
    .O(\I2CS<2>_II/UIM )
  );
  X_IPAD \I2CS<3>.PAD  (
    .PAD(I2CS[3])
  );
  X_BUF \I2CS<3>_II/UIM_54  (
    .I(I2CS[3]),
    .O(\I2CS<3>_II/UIM )
  );
  X_IPAD \I2CS<4>.PAD  (
    .PAD(I2CS[4])
  );
  X_BUF \I2CS<4>_II/UIM_55  (
    .I(I2CS[4]),
    .O(\I2CS<4>_II/UIM )
  );
  X_IPAD \I2CS<5>.PAD  (
    .PAD(I2CS[5])
  );
  X_BUF \I2CS<5>_II/UIM_56  (
    .I(I2CS[5]),
    .O(\I2CS<5>_II/UIM )
  );
  X_IPAD \INTbus.PAD  (
    .PAD(INTbus)
  );
  X_BUF \INTbus_II/UIM_57  (
    .I(INTbus),
    .O(\INTbus_II/UIM )
  );
  X_IPAD \Home15FLG.PAD  (
    .PAD(NlwRenamedSig_IO_Home15FLG)
  );
  X_PU Home15FLG_tsimcreated__pullup_ (
    .O(NlwRenamedSig_IO_Home15FLG)
  );
  X_BUF \Home15FLG_II/UIM_58  (
    .I(NlwRenamedSig_IO_Home15FLG),
    .O(\Home15FLG_II/UIM )
  );
  X_BUF \Home15FLG_II/IREG_59  (
    .I(\U4/Flgreg [5]),
    .O(\Home15FLG_II/IREG )
  );
  X_FF \U4/Flgreg<5>_MC.REG  (
    .I(NlwRenamedSig_IO_Home15FLG),
    .CE(\FOOBAR21__ctinst/4 ),
    .CLK(\U4/Flgreg<5>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\U4/Flgreg [5])
  );
  X_INV \U4/Flgreg<5>_MC.REG_tsimcreated_inv_Mclk_II/FCLK_60  (
    .I(\Mclk_II/FCLK ),
    .O(\U4/Flgreg<5>_MC.REG_tsimcreated_inv_Mclk_II/FCLK )
  );
  X_IPAD \Home133FLG.PAD  (
    .PAD(NlwRenamedSig_IO_Home133FLG)
  );
  X_PU Home133FLG_tsimcreated__pullup_ (
    .O(NlwRenamedSig_IO_Home133FLG)
  );
  X_BUF \Home133FLG_II/UIM_61  (
    .I(NlwRenamedSig_IO_Home133FLG),
    .O(\Home133FLG_II/UIM )
  );
  X_BUF \Home133FLG_II/IREG_62  (
    .I(\U4/Flgreg [4]),
    .O(\Home133FLG_II/IREG )
  );
  X_FF \U4/Flgreg<4>_MC.REG  (
    .I(NlwRenamedSig_IO_Home133FLG),
    .CE(\FOOBAR21__ctinst/4 ),
    .CLK(\U4/Flgreg<4>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\U4/Flgreg [4])
  );
  X_INV \U4/Flgreg<4>_MC.REG_tsimcreated_inv_Mclk_II/FCLK_63  (
    .I(\Mclk_II/FCLK ),
    .O(\U4/Flgreg<4>_MC.REG_tsimcreated_inv_Mclk_II/FCLK )
  );
  X_IPAD \Home05FLG.PAD  (
    .PAD(NlwRenamedSig_IO_Home05FLG)
  );
  X_PU Home05FLG_tsimcreated__pullup_ (
    .O(NlwRenamedSig_IO_Home05FLG)
  );
  X_BUF \Home05FLG_II/UIM_64  (
    .I(NlwRenamedSig_IO_Home05FLG),
    .O(\Home05FLG_II/UIM )
  );
  X_BUF \Home05FLG_II/IREG_65  (
    .I(\U4/Flgreg [1]),
    .O(\Home05FLG_II/IREG )
  );
  X_FF \U4/Flgreg<1>_MC.REG  (
    .I(NlwRenamedSig_IO_Home05FLG),
    .CE(\FOOBAR21__ctinst/4 ),
    .CLK(\U4/Flgreg<1>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\U4/Flgreg [1])
  );
  X_INV \U4/Flgreg<1>_MC.REG_tsimcreated_inv_Mclk_II/FCLK_66  (
    .I(\Mclk_II/FCLK ),
    .O(\U4/Flgreg<1>_MC.REG_tsimcreated_inv_Mclk_II/FCLK )
  );
  X_IPAD \Home033FLG.PAD  (
    .PAD(NlwRenamedSig_IO_Home033FLG)
  );
  X_PU Home033FLG_tsimcreated__pullup_ (
    .O(NlwRenamedSig_IO_Home033FLG)
  );
  X_BUF \Home033FLG_II/UIM_67  (
    .I(NlwRenamedSig_IO_Home033FLG),
    .O(\Home033FLG_II/UIM )
  );
  X_BUF \Home033FLG_II/IREG_68  (
    .I(\U4/Flgreg [0]),
    .O(\Home033FLG_II/IREG )
  );
  X_FF \U4/Flgreg<0>_MC.REG  (
    .I(NlwRenamedSig_IO_Home033FLG),
    .CE(\FOOBAR21__ctinst/4 ),
    .CLK(\U4/Flgreg<0>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\U4/Flgreg [0])
  );
  X_INV \U4/Flgreg<0>_MC.REG_tsimcreated_inv_Mclk_II/FCLK_69  (
    .I(\Mclk_II/FCLK ),
    .O(\U4/Flgreg<0>_MC.REG_tsimcreated_inv_Mclk_II/FCLK )
  );
  X_IPAD \Enc15FLG.PAD  (
    .PAD(NlwRenamedSig_IO_Enc15FLG)
  );
  X_PU Enc15FLG_tsimcreated__pullup_ (
    .O(NlwRenamedSig_IO_Enc15FLG)
  );
  X_BUF \Enc15FLG_II/UIM_70  (
    .I(NlwRenamedSig_IO_Enc15FLG),
    .O(\Enc15FLG_II/UIM )
  );
  X_BUF \Enc15FLG_II/IREG_71  (
    .I(\U4/Flgreg [7]),
    .O(\Enc15FLG_II/IREG )
  );
  X_FF \U4/Flgreg<7>_MC.REG  (
    .I(NlwRenamedSig_IO_Enc15FLG),
    .CE(\FOOBAR24__ctinst/4 ),
    .CLK(\U4/Flgreg<7>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\U4/Flgreg [7])
  );
  X_INV \U4/Flgreg<7>_MC.REG_tsimcreated_inv_Mclk_II/FCLK_72  (
    .I(\Mclk_II/FCLK ),
    .O(\U4/Flgreg<7>_MC.REG_tsimcreated_inv_Mclk_II/FCLK )
  );
  X_IPAD \Enc133FLG.PAD  (
    .PAD(NlwRenamedSig_IO_Enc133FLG)
  );
  X_PU Enc133FLG_tsimcreated__pullup_ (
    .O(NlwRenamedSig_IO_Enc133FLG)
  );
  X_BUF \Enc133FLG_II/UIM_73  (
    .I(NlwRenamedSig_IO_Enc133FLG),
    .O(\Enc133FLG_II/UIM )
  );
  X_BUF \Enc133FLG_II/IREG_74  (
    .I(\U4/Flgreg [6]),
    .O(\Enc133FLG_II/IREG )
  );
  X_FF \U4/Flgreg<6>_MC.REG  (
    .I(NlwRenamedSig_IO_Enc133FLG),
    .CE(\FOOBAR24__ctinst/4 ),
    .CLK(\U4/Flgreg<6>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\U4/Flgreg [6])
  );
  X_INV \U4/Flgreg<6>_MC.REG_tsimcreated_inv_Mclk_II/FCLK_75  (
    .I(\Mclk_II/FCLK ),
    .O(\U4/Flgreg<6>_MC.REG_tsimcreated_inv_Mclk_II/FCLK )
  );
  X_IPAD \Enc05FLG.PAD  (
    .PAD(NlwRenamedSig_IO_Enc05FLG)
  );
  X_PU Enc05FLG_tsimcreated__pullup_ (
    .O(NlwRenamedSig_IO_Enc05FLG)
  );
  X_BUF \Enc05FLG_II/UIM_76  (
    .I(NlwRenamedSig_IO_Enc05FLG),
    .O(\Enc05FLG_II/UIM )
  );
  X_BUF \Enc05FLG_II/IREG_77  (
    .I(\U4/Flgreg [3]),
    .O(\Enc05FLG_II/IREG )
  );
  X_FF \U4/Flgreg<3>_MC.REG  (
    .I(NlwRenamedSig_IO_Enc05FLG),
    .CE(\FOOBAR24__ctinst/4 ),
    .CLK(\U4/Flgreg<3>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\U4/Flgreg [3])
  );
  X_INV \U4/Flgreg<3>_MC.REG_tsimcreated_inv_Mclk_II/FCLK_78  (
    .I(\Mclk_II/FCLK ),
    .O(\U4/Flgreg<3>_MC.REG_tsimcreated_inv_Mclk_II/FCLK )
  );
  X_IPAD \Enc033FLG.PAD  (
    .PAD(NlwRenamedSig_IO_Enc033FLG)
  );
  X_PU Enc033FLG_tsimcreated__pullup_ (
    .O(NlwRenamedSig_IO_Enc033FLG)
  );
  X_BUF \Enc033FLG_II/UIM_79  (
    .I(NlwRenamedSig_IO_Enc033FLG),
    .O(\Enc033FLG_II/UIM )
  );
  X_BUF \Enc033FLG_II/IREG_80  (
    .I(\U4/Flgreg [2]),
    .O(\Enc033FLG_II/IREG )
  );
  X_FF \U4/Flgreg<2>_MC.REG  (
    .I(NlwRenamedSig_IO_Enc033FLG),
    .CE(\FOOBAR24__ctinst/4 ),
    .CLK(\U4/Flgreg<2>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\U4/Flgreg [2])
  );
  X_INV \U4/Flgreg<2>_MC.REG_tsimcreated_inv_Mclk_II/FCLK_81  (
    .I(\Mclk_II/FCLK ),
    .O(\U4/Flgreg<2>_MC.REG_tsimcreated_inv_Mclk_II/FCLK )
  );
  X_IPAD \RLS0.PAD  (
    .PAD(RLS0)
  );
  X_BUF \RLS0_II/UIM_82  (
    .I(RLS0),
    .O(\RLS0_II/UIM )
  );
  X_IPAD \RLS1.PAD  (
    .PAD(RLS1)
  );
  X_BUF \RLS1_II/UIM_83  (
    .I(RLS1),
    .O(\RLS1_II/UIM )
  );
  X_IPAD \GP_Motor0_0.PAD  (
    .PAD(GP_Motor0_0)
  );
  X_BUF \GP_Motor0_0_II/UIM_84  (
    .I(GP_Motor0_0),
    .O(\GP_Motor0_0_II/UIM )
  );
  X_BUF \GP_Motor0_0_II/IREG_85  (
    .I(\U1/U4/InEdge0r ),
    .O(\GP_Motor0_0_II/IREG )
  );
  X_FF \U1/U4/InEdge0r_MC.REG  (
    .I(GP_Motor0_0),
    .CE(Vcc),
    .CLK(\U1/U4/InEdge0r_MC.REG_tsimcreated_inv_Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\U1/U4/InEdge0r )
  );
  X_INV \U1/U4/InEdge0r_MC.REG_tsimcreated_inv_Mclk_II/FCLK_86  (
    .I(\Mclk_II/FCLK ),
    .O(\U1/U4/InEdge0r_MC.REG_tsimcreated_inv_Mclk_II/FCLK )
  );
  X_IPAD \GP_Motor1_0.PAD  (
    .PAD(GP_Motor1_0)
  );
  X_BUF \GP_Motor1_0_II/UIM_87  (
    .I(GP_Motor1_0),
    .O(\GP_Motor1_0_II/UIM )
  );
  X_BUF \GP_Motor1_0_II/IREG_88  (
    .I(\U1/U4/InEdge1r ),
    .O(\GP_Motor1_0_II/IREG )
  );
  X_FF \U1/U4/InEdge1r_MC.REG  (
    .I(GP_Motor1_0),
    .CE(Vcc),
    .CLK(\U1/U4/InEdge1r_MC.REG_tsimcreated_inv_Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\U1/U4/InEdge1r )
  );
  X_INV \U1/U4/InEdge1r_MC.REG_tsimcreated_inv_Mclk_II/FCLK_89  (
    .I(\Mclk_II/FCLK ),
    .O(\U1/U4/InEdge1r_MC.REG_tsimcreated_inv_Mclk_II/FCLK )
  );
  X_IPAD \SCLreset.PAD  (
    .PAD(SCLreset)
  );
  X_BUF \SCLreset_II/UIM_90  (
    .I(SCLreset),
    .O(\SCLreset_II/UIM )
  );
  X_BUF \SCLreset_II/IREG_91  (
    .I(\U11_U4/Line_last ),
    .O(\SCLreset_II/IREG )
  );
  X_FF \U11_U4/Line_last_MC.REG  (
    .I(SCLreset),
    .CE(Vcc),
    .CLK(\U11_U4/Line_last_MC.REG_tsimcreated_inv_Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\U11_U4/Line_last )
  );
  X_INV \U11_U4/Line_last_MC.REG_tsimcreated_inv_Mclk_II/FCLK_92  (
    .I(\Mclk_II/FCLK ),
    .O(\U11_U4/Line_last_MC.REG_tsimcreated_inv_Mclk_II/FCLK )
  );
  X_IPAD \SCLinc.PAD  (
    .PAD(SCLinc)
  );
  X_BUF \SCLinc_II/UIM_93  (
    .I(SCLinc),
    .O(\SCLinc_II/UIM )
  );
  X_BUF \SCLinc_II/IREG_94  (
    .I(\U11_U1/Line_last ),
    .O(\SCLinc_II/IREG )
  );
  X_FF \U11_U1/Line_last_MC.REG  (
    .I(SCLinc),
    .CE(Vcc),
    .CLK(\U11_U1/Line_last_MC.REG_tsimcreated_inv_Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\U11_U1/Line_last )
  );
  X_INV \U11_U1/Line_last_MC.REG_tsimcreated_inv_Mclk_II/FCLK_95  (
    .I(\Mclk_II/FCLK ),
    .O(\U11_U1/Line_last_MC.REG_tsimcreated_inv_Mclk_II/FCLK )
  );
  X_BUF \SCL_II/UIM_96  (
    .I(SCL),
    .O(\SCL_II/UIM )
  );
  X_BUF \SCL_II/IREG_97  (
    .I(\U11_U2/Line_last ),
    .O(\SCL_II/IREG )
  );
  X_FF \U11_U2/Line_last_MC.REG  (
    .I(SCL),
    .CE(Vcc),
    .CLK(\U11_U2/Line_last_MC.REG_tsimcreated_inv_Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\U11_U2/Line_last )
  );
  X_INV \U11_U2/Line_last_MC.REG_tsimcreated_inv_Mclk_II/FCLK_98  (
    .I(\Mclk_II/FCLK ),
    .O(\U11_U2/Line_last_MC.REG_tsimcreated_inv_Mclk_II/FCLK )
  );
  X_IPAD \LightSense.PAD  (
    .PAD(LightSense)
  );
  X_BUF \LightSense_II/UIM_99  (
    .I(LightSense),
    .O(\LightSense_II/UIM )
  );
  X_IPAD \TXI.PAD  (
    .PAD(TXI)
  );
  X_BUF \TXI_II/UIM_100  (
    .I(TXI),
    .O(\TXI_II/UIM )
  );
  X_IPAD \PWM1.PAD  (
    .PAD(PWM1)
  );
  X_BUF \PWM1_II/UIM_101  (
    .I(PWM1),
    .O(\PWM1_II/UIM )
  );
  X_IPAD \PWM2.PAD  (
    .PAD(PWM2)
  );
  X_BUF \PWM2_II/UIM_102  (
    .I(PWM2),
    .O(\PWM2_II/UIM )
  );
  X_IPAD \PhaseA_Encoder0.PAD  (
    .PAD(PhaseA_Encoder0)
  );
  X_BUF \PhaseA_Encoder0_II/UIM_103  (
    .I(PhaseA_Encoder0),
    .O(\PhaseA_Encoder0_II/UIM )
  );
  X_IPAD \PhaseA_Encoder1.PAD  (
    .PAD(PhaseA_Encoder1)
  );
  X_BUF \PhaseA_Encoder1_II/UIM_104  (
    .I(PhaseA_Encoder1),
    .O(\PhaseA_Encoder1_II/UIM )
  );
  X_IPAD \PhaseB_Encoder0.PAD  (
    .PAD(PhaseB_Encoder0)
  );
  X_BUF \PhaseB_Encoder0_II/UIM_105  (
    .I(PhaseB_Encoder0),
    .O(\PhaseB_Encoder0_II/UIM )
  );
  X_IPAD \PhaseB_Encoder1.PAD  (
    .PAD(PhaseB_Encoder1)
  );
  X_BUF \PhaseB_Encoder1_II/UIM_106  (
    .I(PhaseB_Encoder1),
    .O(\PhaseB_Encoder1_II/UIM )
  );
  X_IPAD \Home0.PAD  (
    .PAD(Home0)
  );
  X_BUF \Home0_II/UIM_107  (
    .I(Home0),
    .O(\Home0_II/UIM )
  );
  X_BUF \Home0_II/IREG_108  (
    .I(\U1/U4/HE0stater ),
    .O(\Home0_II/IREG )
  );
  X_FF \U1/U4/HE0stater_MC.REG  (
    .I(Home0),
    .CE(Vcc),
    .CLK(\U1/U4/HE0stater_MC.REG_tsimcreated_inv_Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\U1/U4/HE0stater )
  );
  X_INV \U1/U4/HE0stater_MC.REG_tsimcreated_inv_Mclk_II/FCLK_109  (
    .I(\Mclk_II/FCLK ),
    .O(\U1/U4/HE0stater_MC.REG_tsimcreated_inv_Mclk_II/FCLK )
  );
  X_IPAD \Home1.PAD  (
    .PAD(Home1)
  );
  X_BUF \Home1_II/UIM_110  (
    .I(Home1),
    .O(\Home1_II/UIM )
  );
  X_BUF \Home1_II/IREG_111  (
    .I(\U1/U4/HE1stater ),
    .O(\Home1_II/IREG )
  );
  X_FF \U1/U4/HE1stater_MC.REG  (
    .I(Home1),
    .CE(Vcc),
    .CLK(\U1/U4/HE1stater_MC.REG_tsimcreated_inv_Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\U1/U4/HE1stater )
  );
  X_INV \U1/U4/HE1stater_MC.REG_tsimcreated_inv_Mclk_II/FCLK_112  (
    .I(\Mclk_II/FCLK ),
    .O(\U1/U4/HE1stater_MC.REG_tsimcreated_inv_Mclk_II/FCLK )
  );
  X_OPAD \Enc033ctrl.PAD  (
    .PAD(Enc033ctrl)
  );
  X_BUF Enc033ctrl_113 (
    .I(\Enc033ctrl_MC.Q ),
    .O(Enc033ctrl)
  );
  X_OPAD \Enc05ctrl.PAD  (
    .PAD(Enc05ctrl)
  );
  X_BUF Enc05ctrl_114 (
    .I(\Enc05ctrl_MC.Q ),
    .O(Enc05ctrl)
  );
  X_OPAD \Enc133ctrl.PAD  (
    .PAD(Enc133ctrl)
  );
  X_BUF Enc133ctrl_115 (
    .I(\Enc133ctrl_MC.Q ),
    .O(Enc133ctrl)
  );
  X_OPAD \Enc15ctrl.PAD  (
    .PAD(Enc15ctrl)
  );
  X_BUF Enc15ctrl_116 (
    .I(\Enc15ctrl_MC.Q ),
    .O(Enc15ctrl)
  );
  X_OPAD \GPIO8.PAD  (
    .PAD(GPIO8)
  );
  X_BUF GPIO8_117 (
    .I(\GPIO8_MC.Q ),
    .O(GPIO8)
  );
  X_OPAD \GPIO9.PAD  (
    .PAD(GPIO9)
  );
  X_BUF GPIO9_118 (
    .I(\GPIO9_MC.Q ),
    .O(GPIO9)
  );
  X_OPAD \GP_Motor0_1.PAD  (
    .PAD(GP_Motor0_1)
  );
  X_BUF GP_Motor0_1_119 (
    .I(\GP_Motor0_1_MC.Q ),
    .O(GP_Motor0_1)
  );
  X_OPAD \GP_Motor1_1.PAD  (
    .PAD(GP_Motor1_1)
  );
  X_BUF GP_Motor1_1_120 (
    .I(\GP_Motor1_1_MC.Q ),
    .O(GP_Motor1_1)
  );
  X_OPAD \HSO.PAD  (
    .PAD(HSO)
  );
  X_BUF HSO_121 (
    .I(\HSO_MC.Q ),
    .O(HSO)
  );
  X_OPAD \Home033ctrl.PAD  (
    .PAD(Home033ctrl)
  );
  X_BUF Home033ctrl_122 (
    .I(\Home033ctrl_MC.Q ),
    .O(Home033ctrl)
  );
  X_OPAD \Home05ctrl.PAD  (
    .PAD(Home05ctrl)
  );
  X_BUF Home05ctrl_123 (
    .I(\Home05ctrl_MC.Q ),
    .O(Home05ctrl)
  );
  X_OPAD \Home133ctrl.PAD  (
    .PAD(Home133ctrl)
  );
  X_BUF Home133ctrl_124 (
    .I(\Home133ctrl_MC.Q ),
    .O(Home133ctrl)
  );
  X_OPAD \Home15ctrl.PAD  (
    .PAD(Home15ctrl)
  );
  X_BUF Home15ctrl_125 (
    .I(\Home15ctrl_MC.Q ),
    .O(Home15ctrl)
  );
  X_OPAD \INT.PAD  (
    .PAD(INT)
  );
  X_BUF INT_126 (
    .I(\INT_MC.Q ),
    .O(INT)
  );
  X_OPAD \LED1.PAD  (
    .PAD(LED1)
  );
  X_BUF LED1_127 (
    .I(\LED1_MC.Q ),
    .O(LED1)
  );
  X_OPAD \LED2.PAD  (
    .PAD(LED2)
  );
  X_BUF LED2_128 (
    .I(\LED2_MC.Q ),
    .O(LED2)
  );
  X_OPAD \LED3.PAD  (
    .PAD(LED3)
  );
  X_BUF LED3_129 (
    .I(\LED3_MC.Q ),
    .O(LED3)
  );
  X_OPAD \LED4.PAD  (
    .PAD(LED4)
  );
  X_BUF LED4_130 (
    .I(\LED4_MC.Q ),
    .O(LED4)
  );
  X_OPAD \LED5.PAD  (
    .PAD(LED5)
  );
  X_BUF LED5_131 (
    .I(\LED5_MC.Q ),
    .O(LED5)
  );
  X_OPAD \MHSI.PAD  (
    .PAD(MHSI)
  );
  X_BUF MHSI_132 (
    .I(\MHSI_MC.Q ),
    .O(MHSI)
  );
  X_OPAD \MTRpwr.PAD  (
    .PAD(MTRpwr)
  );
  X_BUF MTRpwr_133 (
    .I(\MTRpwr_MC.Q ),
    .O(MTRpwr)
  );
  X_OPAD \MTRpwrn.PAD  (
    .PAD(MTRpwrn)
  );
  X_BUF MTRpwrn_134 (
    .I(\MTRpwrn_MC.Q ),
    .O(MTRpwrn)
  );
  X_OPAD \MTXI.PAD  (
    .PAD(MTXI)
  );
  X_BUF MTXI_135 (
    .I(\MTXI_MC.Q ),
    .O(MTXI)
  );
  X_OPAD \PAH0.PAD  (
    .PAD(PAH0)
  );
  X_BUF PAH0_136 (
    .I(\PAH0_MC.Q ),
    .O(PAH0)
  );
  X_OPAD \PAH1.PAD  (
    .PAD(PAH1)
  );
  X_BUF PAH1_137 (
    .I(\PAH1_MC.Q ),
    .O(PAH1)
  );
  X_OPAD \PAL0.PAD  (
    .PAD(PAL0)
  );
  X_BUF PAL0_138 (
    .I(\PAL0_MC.Q ),
    .O(PAL0)
  );
  X_OPAD \PAL1.PAD  (
    .PAD(PAL1)
  );
  X_BUF PAL1_139 (
    .I(\PAL1_MC.Q ),
    .O(PAL1)
  );
  X_OPAD \PBH0.PAD  (
    .PAD(PBH0)
  );
  X_BUF PBH0_140 (
    .I(\PBH0_MC.Q ),
    .O(PBH0)
  );
  X_OPAD \PBH1.PAD  (
    .PAD(PBH1)
  );
  X_BUF PBH1_141 (
    .I(\PBH1_MC.Q ),
    .O(PBH1)
  );
  X_OPAD \PBL0.PAD  (
    .PAD(PBL0)
  );
  X_BUF PBL0_142 (
    .I(\PBL0_MC.Q ),
    .O(PBL0)
  );
  X_OPAD \PBL1.PAD  (
    .PAD(PBL1)
  );
  X_BUF PBL1_143 (
    .I(\PBL1_MC.Q ),
    .O(PBL1)
  );
  X_OPAD \PresEn.PAD  (
    .PAD(PresEn)
  );
  X_BUF PresEn_144 (
    .I(\PresEn_MC.Q ),
    .O(PresEn)
  );
  X_OPAD \PresSlct.PAD  (
    .PAD(PresSlct)
  );
  X_BUF PresSlct_145 (
    .I(\PresSlct_MC.Q ),
    .O(PresSlct)
  );
  X_OPAD \SCLout.PAD  (
    .PAD(SCLout)
  );
  X_BUF SCLout_146 (
    .I(\SCLout_MC.Q ),
    .O(SCLout)
  );
  X_OPAD \TP10.PAD  (
    .PAD(TP10)
  );
  X_BUF TP10_147 (
    .I(\TP10_MC.Q ),
    .O(TP10)
  );
  X_OPAD \TP11.PAD  (
    .PAD(TP11)
  );
  X_BUF TP11_148 (
    .I(\TP11_MC.Q ),
    .O(TP11)
  );
  X_OPAD \TP12.PAD  (
    .PAD(TP12)
  );
  X_BUF TP12_149 (
    .I(\TP12_MC.Q ),
    .O(TP12)
  );
  X_OPAD \TmpEn.PAD  (
    .PAD(TmpEn)
  );
  X_BUF TmpEn_150 (
    .I(\TmpEn_MC.Q ),
    .O(TmpEn)
  );
  X_OPAD \TmpSlct.PAD  (
    .PAD(TmpSlct)
  );
  X_BUF TmpSlct_151 (
    .I(\TmpSlct_MC.Q ),
    .O(TmpSlct)
  );
  X_BPAD \SCL.PAD  (
    .PAD(SCL)
  );
  X_TRI SCL_152 (
    .I(\U11_U2/Line_last_MC.Q ),
    .CTL(\U11_U2/Line_last_MC.OE ),
    .O(SCL)
  );
  X_BPAD \AD<0>.PAD  (
    .PAD(AD[0])
  );
  X_TRI \AD<0>  (
    .I(\U4/ctrlr<0>_MC.Q ),
    .CTL(\U4/ctrlr<0>_MC.OE ),
    .O(AD[0])
  );
  X_BPAD \AD<1>.PAD  (
    .PAD(AD[1])
  );
  X_TRI \AD<1>  (
    .I(\U4/ctrlr<1>_MC.Q ),
    .CTL(\U4/ctrlr<1>_MC.OE ),
    .O(AD[1])
  );
  X_BPAD \AD<2>.PAD  (
    .PAD(AD[2])
  );
  X_TRI \AD<2>  (
    .I(\U4/ctrlr<2>_MC.Q ),
    .CTL(\U4/ctrlr<2>_MC.OE ),
    .O(AD[2])
  );
  X_BPAD \AD<3>.PAD  (
    .PAD(AD[3])
  );
  X_TRI \AD<3>  (
    .I(\U4/ctrlr<3>_MC.Q ),
    .CTL(\U4/ctrlr<3>_MC.OE ),
    .O(AD[3])
  );
  X_BPAD \AD<4>.PAD  (
    .PAD(AD[4])
  );
  X_TRI \AD<4>  (
    .I(\U4/ctrlr<4>_MC.Q ),
    .CTL(\U4/ctrlr<4>_MC.OE ),
    .O(AD[4])
  );
  X_BPAD \AD<5>.PAD  (
    .PAD(AD[5])
  );
  X_TRI \AD<5>  (
    .I(\U4/ctrlr<5>_MC.Q ),
    .CTL(\U4/ctrlr<5>_MC.OE ),
    .O(AD[5])
  );
  X_BPAD \AD<6>.PAD  (
    .PAD(AD[6])
  );
  X_TRI \AD<6>  (
    .I(\U4/ctrlr<6>_MC.Q ),
    .CTL(\U4/ctrlr<6>_MC.OE ),
    .O(AD[6])
  );
  X_BPAD \AD<7>.PAD  (
    .PAD(AD[7])
  );
  X_TRI \AD<7>  (
    .I(\U4/ctrlr<7>_MC.Q ),
    .CTL(\U4/ctrlr<7>_MC.OE ),
    .O(AD[7])
  );
  X_BUF \Enc033ctrl_MC.Q_153  (
    .I(\Enc033ctrl_MC.Q_tsimrenamed_net_ ),
    .O(\Enc033ctrl_MC.Q )
  );
  X_BUF \Enc033ctrl_MC.Q_tsimrenamed_net__154  (
    .I(\Enc033ctrl_MC.D ),
    .O(\Enc033ctrl_MC.Q_tsimrenamed_net_ )
  );
  X_XOR2 \Enc033ctrl_MC.D_155  (
    .I0(\NlwInverterSignal_Enc033ctrl_MC.D/IN0 ),
    .I1(\Enc033ctrl_MC.D2 ),
    .O(\Enc033ctrl_MC.D )
  );
  X_AND2 \Enc033ctrl_MC.D1_156  (
    .I0(\U4/ctrlr [2]),
    .I1(\NlwInverterSignal_Enc033ctrl_MC.D1/IN1 ),
    .O(\Enc033ctrl_MC.D1 )
  );
  X_ZERO \Enc033ctrl_MC.D2_157  (
    .O(\Enc033ctrl_MC.D2 )
  );
  X_BUF \U4/ctrlr<2>_MC.Q_158  (
    .I(\U4/ctrlr<2>_MC.D ),
    .O(\U4/ctrlr<2>_MC.Q )
  );
  X_BUF \U4/ctrlr<2>_MC.OE_159  (
    .I(\U4/ctrlr<2>_MC.BUFOE.OUT ),
    .O(\U4/ctrlr<2>_MC.OE )
  );
  X_BUF \U4/ctrlr<2>_MC.BUFOE.OUT_160  (
    .I(\FOOBAR1__ctinst/7 ),
    .O(\U4/ctrlr<2>_MC.BUFOE.OUT )
  );
  X_XOR2 \U4/ctrlr<2>_MC.D_161  (
    .I0(\NlwInverterSignal_U4/ctrlr<2>_MC.D/IN0 ),
    .I1(\U4/ctrlr<2>_MC.D2 ),
    .O(\U4/ctrlr<2>_MC.D )
  );
  X_ZERO \U4/ctrlr<2>_MC.D1_162  (
    .O(\U4/ctrlr<2>_MC.D1 )
  );
  X_AND2 \U4/ctrlr<2>_MC.D2_PT_0_163  (
    .I0(DCORI2CCNTr),
    .I1(\NlwInverterSignal_U4/ctrlr<2>_MC.D2_PT_0/IN1 ),
    .O(\U4/ctrlr<2>_MC.D2_PT_0 )
  );
  X_AND2 \U4/ctrlr<2>_MC.D2_PT_1_164  (
    .I0(DCORCONFIGr),
    .I1(\NlwInverterSignal_U4/ctrlr<2>_MC.D2_PT_1/IN1 ),
    .O(\U4/ctrlr<2>_MC.D2_PT_1 )
  );
  X_AND2 \U4/ctrlr<2>_MC.D2_PT_2_165  (
    .I0(DCORLIMITSr),
    .I1(\NlwInverterSignal_U4/ctrlr<2>_MC.D2_PT_2/IN1 ),
    .O(\U4/ctrlr<2>_MC.D2_PT_2 )
  );
  X_AND2 \U4/ctrlr<2>_MC.D2_PT_3_166  (
    .I0(DCORENCPWRr),
    .I1(\NlwInverterSignal_U4/ctrlr<2>_MC.D2_PT_3/IN1 ),
    .O(\U4/ctrlr<2>_MC.D2_PT_3 )
  );
  X_AND2 \U4/ctrlr<2>_MC.D2_PT_4_167  (
    .I0(\NlwInverterSignal_U4/ctrlr<2>_MC.D2_PT_4/IN0 ),
    .I1(\NlwInverterSignal_U4/ctrlr<2>_MC.D2_PT_4/IN1 ),
    .O(\U4/ctrlr<2>_MC.D2_PT_4 )
  );
  X_AND2 \U4/ctrlr<2>_MC.D2_PT_5_168  (
    .I0(\NlwInverterSignal_U4/ctrlr<2>_MC.D2_PT_5/IN0 ),
    .I1(\NlwInverterSignal_U4/ctrlr<2>_MC.D2_PT_5/IN1 ),
    .O(\U4/ctrlr<2>_MC.D2_PT_5 )
  );
  X_OR6 \U4/ctrlr<2>_MC.D2_169  (
    .I0(\U4/ctrlr<2>_MC.D2_PT_0 ),
    .I1(\U4/ctrlr<2>_MC.D2_PT_1 ),
    .I2(\U4/ctrlr<2>_MC.D2_PT_2 ),
    .I3(\U4/ctrlr<2>_MC.D2_PT_3 ),
    .I4(\U4/ctrlr<2>_MC.D2_PT_4 ),
    .I5(\U4/ctrlr<2>_MC.D2_PT_5 ),
    .O(\U4/ctrlr<2>_MC.D2 )
  );
  X_BUF DCORENCPWRw_170 (
    .I(\DCORENCPWRw_MC.Q ),
    .O(DCORENCPWRw)
  );
  X_BUF \DCORENCPWRw_MC.Q_171  (
    .I(\DCORENCPWRw_MC.D ),
    .O(\DCORENCPWRw_MC.Q )
  );
  X_XOR2 \DCORENCPWRw_MC.D_172  (
    .I0(\DCORENCPWRw_MC.D1 ),
    .I1(\DCORENCPWRw_MC.D2 ),
    .O(\DCORENCPWRw_MC.D )
  );
  X_AND16 \DCORENCPWRw_MC.D1_173  (
    .I0(\NlwInverterSignal_DCORENCPWRw_MC.D1/IN0 ),
    .I1(\RD_II/UIM ),
    .I2(\NlwInverterSignal_DCORENCPWRw_MC.D1/IN2 ),
    .I3(\NlwInverterSignal_DCORENCPWRw_MC.D1/IN3 ),
    .I4(\NlwInverterSignal_DCORENCPWRw_MC.D1/IN4 ),
    .I5(\NlwInverterSignal_DCORENCPWRw_MC.D1/IN5 ),
    .I6(\NlwInverterSignal_DCORENCPWRw_MC.D1/IN6 ),
    .I7(U2_ADDR_reg[3]),
    .I8(U2_ADDR_reg[1]),
    .I9(U2_ADDR_reg[2]),
    .I10(Vcc),
    .I11(Vcc),
    .I12(Vcc),
    .I13(Vcc),
    .I14(Vcc),
    .I15(Vcc),
    .O(\DCORENCPWRw_MC.D1 )
  );
  X_ZERO \DCORENCPWRw_MC.D2_174  (
    .O(\DCORENCPWRw_MC.D2 )
  );
  X_BUF \U2_ADDR_reg<0>  (
    .I(\U2_ADDR_reg<0>_MC.Q ),
    .O(U2_ADDR_reg[0])
  );
  X_XOR2 \U2_ADDR_reg<0>_MC_tsimcreated_xor__175  (
    .I0(\U2_ADDR_reg<0>_MC.D ),
    .I1(\U2_ADDR_reg<0>_MC.Q ),
    .O(\U2_ADDR_reg<0>_MC_tsimcreated_xor_ )
  );
  X_FF \U2_ADDR_reg<0>_MC.REG  (
    .I(\U2_ADDR_reg<0>_MC_tsimcreated_xor_ ),
    .CE(Vcc),
    .CLK(\U2_ADDR_reg<0>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\U2_ADDR_reg<0>_MC.Q )
  );
  X_INV \U2_ADDR_reg<0>_MC.REG_tsimcreated_inv_Mclk_II/FCLK_176  (
    .I(\Mclk_II/FCLK ),
    .O(\U2_ADDR_reg<0>_MC.REG_tsimcreated_inv_Mclk_II/FCLK )
  );
  X_XOR2 \U2_ADDR_reg<0>_MC.D_177  (
    .I0(\U2_ADDR_reg<0>_MC.D1 ),
    .I1(\U2_ADDR_reg<0>_MC.D2 ),
    .O(\U2_ADDR_reg<0>_MC.D )
  );
  X_ZERO \U2_ADDR_reg<0>_MC.D1_178  (
    .O(\U2_ADDR_reg<0>_MC.D1 )
  );
  X_AND2 \U2_ADDR_reg<0>_MC.D2_PT_0_179  (
    .I0(U2_ADDR_reg[0]),
    .I1(\NlwInverterSignal_U2_ADDR_reg<0>_MC.D2_PT_0/IN1 ),
    .O(\U2_ADDR_reg<0>_MC.D2_PT_0 )
  );
  X_AND6 \U2_ADDR_reg<0>_MC.D2_PT_1_180  (
    .I0(\WR_II/UIM ),
    .I1(\RD_II/UIM ),
    .I2(U2_ADDR_reg[0]),
    .I3(\NlwInverterSignal_U2_ADDR_reg<0>_MC.D2_PT_1/IN3 ),
    .I4(\NlwInverterSignal_U2_ADDR_reg<0>_MC.D2_PT_1/IN4 ),
    .I5(U2_ASedge),
    .O(\U2_ADDR_reg<0>_MC.D2_PT_1 )
  );
  X_AND7 \U2_ADDR_reg<0>_MC.D2_PT_2_181  (
    .I0(\WR_II/UIM ),
    .I1(\RD_II/UIM ),
    .I2(\NlwInverterSignal_U2_ADDR_reg<0>_MC.D2_PT_2/IN2 ),
    .I3(\MSPReset_II/UIM ),
    .I4(\AD<0>_II/UIM ),
    .I5(\NlwInverterSignal_U2_ADDR_reg<0>_MC.D2_PT_2/IN5 ),
    .I6(U2_ASedge),
    .O(\U2_ADDR_reg<0>_MC.D2_PT_2 )
  );
  X_AND16 \U2_ADDR_reg<0>_MC.D2_PT_3_182  (
    .I0(\WR_II/UIM ),
    .I1(\RD_II/UIM ),
    .I2(\NlwInverterSignal_U2_ADDR_reg<0>_MC.D2_PT_3/IN2 ),
    .I3(\NlwInverterSignal_U2_ADDR_reg<0>_MC.D2_PT_3/IN3 ),
    .I4(\NlwInverterSignal_U2_ADDR_reg<0>_MC.D2_PT_3/IN4 ),
    .I5(\NlwInverterSignal_U2_ADDR_reg<0>_MC.D2_PT_3/IN5 ),
    .I6(U2_AutoInc),
    .I7(\NlwInverterSignal_U2_ADDR_reg<0>_MC.D2_PT_3/IN7 ),
    .I8(N_PZ_941),
    .I9(Vcc),
    .I10(Vcc),
    .I11(Vcc),
    .I12(Vcc),
    .I13(Vcc),
    .I14(Vcc),
    .I15(Vcc),
    .O(\U2_ADDR_reg<0>_MC.D2_PT_3 )
  );
  X_OR4 \U2_ADDR_reg<0>_MC.D2_183  (
    .I0(\U2_ADDR_reg<0>_MC.D2_PT_0 ),
    .I1(\U2_ADDR_reg<0>_MC.D2_PT_1 ),
    .I2(\U2_ADDR_reg<0>_MC.D2_PT_2 ),
    .I3(\U2_ADDR_reg<0>_MC.D2_PT_3 ),
    .O(\U2_ADDR_reg<0>_MC.D2 )
  );
  X_BUF \U2_ADDR_reg<4>  (
    .I(\U2_ADDR_reg<4>_MC.Q ),
    .O(U2_ADDR_reg[4])
  );
  X_XOR2 \U2_ADDR_reg<4>_MC_tsimcreated_xor__184  (
    .I0(\U2_ADDR_reg<4>_MC.D ),
    .I1(\U2_ADDR_reg<4>_MC.Q ),
    .O(\U2_ADDR_reg<4>_MC_tsimcreated_xor_ )
  );
  X_FF \U2_ADDR_reg<4>_MC.REG  (
    .I(\U2_ADDR_reg<4>_MC_tsimcreated_xor_ ),
    .CE(Vcc),
    .CLK(\U2_ADDR_reg<4>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\U2_ADDR_reg<4>_MC.Q )
  );
  X_INV \U2_ADDR_reg<4>_MC.REG_tsimcreated_inv_Mclk_II/FCLK_185  (
    .I(\Mclk_II/FCLK ),
    .O(\U2_ADDR_reg<4>_MC.REG_tsimcreated_inv_Mclk_II/FCLK )
  );
  X_XOR2 \U2_ADDR_reg<4>_MC.D_186  (
    .I0(\U2_ADDR_reg<4>_MC.D1 ),
    .I1(\U2_ADDR_reg<4>_MC.D2 ),
    .O(\U2_ADDR_reg<4>_MC.D )
  );
  X_ZERO \U2_ADDR_reg<4>_MC.D1_187  (
    .O(\U2_ADDR_reg<4>_MC.D1 )
  );
  X_AND2 \U2_ADDR_reg<4>_MC.D2_PT_0_188  (
    .I0(U2_ADDR_reg[4]),
    .I1(\NlwInverterSignal_U2_ADDR_reg<4>_MC.D2_PT_0/IN1 ),
    .O(\U2_ADDR_reg<4>_MC.D2_PT_0 )
  );
  X_AND6 \U2_ADDR_reg<4>_MC.D2_PT_1_189  (
    .I0(\WR_II/UIM ),
    .I1(\RD_II/UIM ),
    .I2(U2_ADDR_reg[4]),
    .I3(\NlwInverterSignal_U2_ADDR_reg<4>_MC.D2_PT_1/IN3 ),
    .I4(U2_ASedge),
    .I5(\NlwInverterSignal_U2_ADDR_reg<4>_MC.D2_PT_1/IN5 ),
    .O(\U2_ADDR_reg<4>_MC.D2_PT_1 )
  );
  X_AND7 \U2_ADDR_reg<4>_MC.D2_PT_2_190  (
    .I0(\WR_II/UIM ),
    .I1(\RD_II/UIM ),
    .I2(\NlwInverterSignal_U2_ADDR_reg<4>_MC.D2_PT_2/IN2 ),
    .I3(\MSPReset_II/UIM ),
    .I4(\NlwInverterSignal_U2_ADDR_reg<4>_MC.D2_PT_2/IN4 ),
    .I5(U2_ASedge),
    .I6(\AD<4>_II/UIM ),
    .O(\U2_ADDR_reg<4>_MC.D2_PT_2 )
  );
  X_OR3 \U2_ADDR_reg<4>_MC.D2_191  (
    .I0(\U2_ADDR_reg<4>_MC.D2_PT_0 ),
    .I1(\U2_ADDR_reg<4>_MC.D2_PT_1 ),
    .I2(\U2_ADDR_reg<4>_MC.D2_PT_2 ),
    .O(\U2_ADDR_reg<4>_MC.D2 )
  );
  X_BUF \U2_ADDR_reg<5>  (
    .I(\U2_ADDR_reg<5>_MC.Q ),
    .O(U2_ADDR_reg[5])
  );
  X_XOR2 \U2_ADDR_reg<5>_MC_tsimcreated_xor__192  (
    .I0(\U2_ADDR_reg<5>_MC.D ),
    .I1(\U2_ADDR_reg<5>_MC.Q ),
    .O(\U2_ADDR_reg<5>_MC_tsimcreated_xor_ )
  );
  X_FF \U2_ADDR_reg<5>_MC.REG  (
    .I(\U2_ADDR_reg<5>_MC_tsimcreated_xor_ ),
    .CE(Vcc),
    .CLK(\U2_ADDR_reg<5>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\U2_ADDR_reg<5>_MC.Q )
  );
  X_INV \U2_ADDR_reg<5>_MC.REG_tsimcreated_inv_Mclk_II/FCLK_193  (
    .I(\Mclk_II/FCLK ),
    .O(\U2_ADDR_reg<5>_MC.REG_tsimcreated_inv_Mclk_II/FCLK )
  );
  X_XOR2 \U2_ADDR_reg<5>_MC.D_194  (
    .I0(\U2_ADDR_reg<5>_MC.D1 ),
    .I1(\U2_ADDR_reg<5>_MC.D2 ),
    .O(\U2_ADDR_reg<5>_MC.D )
  );
  X_ZERO \U2_ADDR_reg<5>_MC.D1_195  (
    .O(\U2_ADDR_reg<5>_MC.D1 )
  );
  X_AND2 \U2_ADDR_reg<5>_MC.D2_PT_0_196  (
    .I0(U2_ADDR_reg[5]),
    .I1(\NlwInverterSignal_U2_ADDR_reg<5>_MC.D2_PT_0/IN1 ),
    .O(\U2_ADDR_reg<5>_MC.D2_PT_0 )
  );
  X_AND6 \U2_ADDR_reg<5>_MC.D2_PT_1_197  (
    .I0(\WR_II/UIM ),
    .I1(\RD_II/UIM ),
    .I2(U2_ADDR_reg[5]),
    .I3(\NlwInverterSignal_U2_ADDR_reg<5>_MC.D2_PT_1/IN3 ),
    .I4(U2_ASedge),
    .I5(\NlwInverterSignal_U2_ADDR_reg<5>_MC.D2_PT_1/IN5 ),
    .O(\U2_ADDR_reg<5>_MC.D2_PT_1 )
  );
  X_AND7 \U2_ADDR_reg<5>_MC.D2_PT_2_198  (
    .I0(\WR_II/UIM ),
    .I1(\RD_II/UIM ),
    .I2(\NlwInverterSignal_U2_ADDR_reg<5>_MC.D2_PT_2/IN2 ),
    .I3(\MSPReset_II/UIM ),
    .I4(\NlwInverterSignal_U2_ADDR_reg<5>_MC.D2_PT_2/IN4 ),
    .I5(U2_ASedge),
    .I6(\AD<5>_II/UIM ),
    .O(\U2_ADDR_reg<5>_MC.D2_PT_2 )
  );
  X_OR3 \U2_ADDR_reg<5>_MC.D2_199  (
    .I0(\U2_ADDR_reg<5>_MC.D2_PT_0 ),
    .I1(\U2_ADDR_reg<5>_MC.D2_PT_1 ),
    .I2(\U2_ADDR_reg<5>_MC.D2_PT_2 ),
    .O(\U2_ADDR_reg<5>_MC.D2 )
  );
  X_BUF \U2_ADDR_reg<6>  (
    .I(\U2_ADDR_reg<6>_MC.Q ),
    .O(U2_ADDR_reg[6])
  );
  X_XOR2 \U2_ADDR_reg<6>_MC_tsimcreated_xor__200  (
    .I0(\U2_ADDR_reg<6>_MC.D ),
    .I1(\U2_ADDR_reg<6>_MC.Q ),
    .O(\U2_ADDR_reg<6>_MC_tsimcreated_xor_ )
  );
  X_FF \U2_ADDR_reg<6>_MC.REG  (
    .I(\U2_ADDR_reg<6>_MC_tsimcreated_xor_ ),
    .CE(Vcc),
    .CLK(\U2_ADDR_reg<6>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\U2_ADDR_reg<6>_MC.Q )
  );
  X_INV \U2_ADDR_reg<6>_MC.REG_tsimcreated_inv_Mclk_II/FCLK_201  (
    .I(\Mclk_II/FCLK ),
    .O(\U2_ADDR_reg<6>_MC.REG_tsimcreated_inv_Mclk_II/FCLK )
  );
  X_XOR2 \U2_ADDR_reg<6>_MC.D_202  (
    .I0(\U2_ADDR_reg<6>_MC.D1 ),
    .I1(\U2_ADDR_reg<6>_MC.D2 ),
    .O(\U2_ADDR_reg<6>_MC.D )
  );
  X_ZERO \U2_ADDR_reg<6>_MC.D1_203  (
    .O(\U2_ADDR_reg<6>_MC.D1 )
  );
  X_AND2 \U2_ADDR_reg<6>_MC.D2_PT_0_204  (
    .I0(U2_ADDR_reg[6]),
    .I1(\NlwInverterSignal_U2_ADDR_reg<6>_MC.D2_PT_0/IN1 ),
    .O(\U2_ADDR_reg<6>_MC.D2_PT_0 )
  );
  X_AND6 \U2_ADDR_reg<6>_MC.D2_PT_1_205  (
    .I0(\WR_II/UIM ),
    .I1(\RD_II/UIM ),
    .I2(U2_ADDR_reg[6]),
    .I3(\NlwInverterSignal_U2_ADDR_reg<6>_MC.D2_PT_1/IN3 ),
    .I4(U2_ASedge),
    .I5(\NlwInverterSignal_U2_ADDR_reg<6>_MC.D2_PT_1/IN5 ),
    .O(\U2_ADDR_reg<6>_MC.D2_PT_1 )
  );
  X_AND7 \U2_ADDR_reg<6>_MC.D2_PT_2_206  (
    .I0(\WR_II/UIM ),
    .I1(\RD_II/UIM ),
    .I2(\NlwInverterSignal_U2_ADDR_reg<6>_MC.D2_PT_2/IN2 ),
    .I3(\MSPReset_II/UIM ),
    .I4(\NlwInverterSignal_U2_ADDR_reg<6>_MC.D2_PT_2/IN4 ),
    .I5(U2_ASedge),
    .I6(\AD<6>_II/UIM ),
    .O(\U2_ADDR_reg<6>_MC.D2_PT_2 )
  );
  X_OR3 \U2_ADDR_reg<6>_MC.D2_207  (
    .I0(\U2_ADDR_reg<6>_MC.D2_PT_0 ),
    .I1(\U2_ADDR_reg<6>_MC.D2_PT_1 ),
    .I2(\U2_ADDR_reg<6>_MC.D2_PT_2 ),
    .O(\U2_ADDR_reg<6>_MC.D2 )
  );
  X_BUF \U2_ADDR_reg<7>  (
    .I(\U2_ADDR_reg<7>_MC.Q ),
    .O(U2_ADDR_reg[7])
  );
  X_XOR2 \U2_ADDR_reg<7>_MC_tsimcreated_xor__208  (
    .I0(\U2_ADDR_reg<7>_MC.D ),
    .I1(\U2_ADDR_reg<7>_MC.Q ),
    .O(\U2_ADDR_reg<7>_MC_tsimcreated_xor_ )
  );
  X_FF \U2_ADDR_reg<7>_MC.REG  (
    .I(\U2_ADDR_reg<7>_MC_tsimcreated_xor_ ),
    .CE(Vcc),
    .CLK(\U2_ADDR_reg<7>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\U2_ADDR_reg<7>_MC.Q )
  );
  X_INV \U2_ADDR_reg<7>_MC.REG_tsimcreated_inv_Mclk_II/FCLK_209  (
    .I(\Mclk_II/FCLK ),
    .O(\U2_ADDR_reg<7>_MC.REG_tsimcreated_inv_Mclk_II/FCLK )
  );
  X_XOR2 \U2_ADDR_reg<7>_MC.D_210  (
    .I0(\U2_ADDR_reg<7>_MC.D1 ),
    .I1(\U2_ADDR_reg<7>_MC.D2 ),
    .O(\U2_ADDR_reg<7>_MC.D )
  );
  X_ZERO \U2_ADDR_reg<7>_MC.D1_211  (
    .O(\U2_ADDR_reg<7>_MC.D1 )
  );
  X_AND2 \U2_ADDR_reg<7>_MC.D2_PT_0_212  (
    .I0(U2_ADDR_reg[7]),
    .I1(\NlwInverterSignal_U2_ADDR_reg<7>_MC.D2_PT_0/IN1 ),
    .O(\U2_ADDR_reg<7>_MC.D2_PT_0 )
  );
  X_AND6 \U2_ADDR_reg<7>_MC.D2_PT_1_213  (
    .I0(\WR_II/UIM ),
    .I1(\RD_II/UIM ),
    .I2(U2_ADDR_reg[7]),
    .I3(\NlwInverterSignal_U2_ADDR_reg<7>_MC.D2_PT_1/IN3 ),
    .I4(U2_ASedge),
    .I5(\NlwInverterSignal_U2_ADDR_reg<7>_MC.D2_PT_1/IN5 ),
    .O(\U2_ADDR_reg<7>_MC.D2_PT_1 )
  );
  X_AND7 \U2_ADDR_reg<7>_MC.D2_PT_2_214  (
    .I0(\WR_II/UIM ),
    .I1(\RD_II/UIM ),
    .I2(\NlwInverterSignal_U2_ADDR_reg<7>_MC.D2_PT_2/IN2 ),
    .I3(\MSPReset_II/UIM ),
    .I4(\NlwInverterSignal_U2_ADDR_reg<7>_MC.D2_PT_2/IN4 ),
    .I5(U2_ASedge),
    .I6(\AD<7>_II/UIM ),
    .O(\U2_ADDR_reg<7>_MC.D2_PT_2 )
  );
  X_OR3 \U2_ADDR_reg<7>_MC.D2_215  (
    .I0(\U2_ADDR_reg<7>_MC.D2_PT_0 ),
    .I1(\U2_ADDR_reg<7>_MC.D2_PT_1 ),
    .I2(\U2_ADDR_reg<7>_MC.D2_PT_2 ),
    .O(\U2_ADDR_reg<7>_MC.D2 )
  );
  X_BUF U2_AutoInc_216 (
    .I(\U2_AutoInc_MC.Q ),
    .O(U2_AutoInc)
  );
  X_FF \U2_AutoInc_MC.REG  (
    .I(\U2_AutoInc_MC.D ),
    .CE(\FOOBAR8__ctinst/4 ),
    .CLK(\U2_AutoInc_MC.REG_tsimcreated_inv_Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\U2_AutoInc_MC.Q )
  );
  X_INV \U2_AutoInc_MC.REG_tsimcreated_inv_Mclk_II/FCLK_217  (
    .I(\Mclk_II/FCLK ),
    .O(\U2_AutoInc_MC.REG_tsimcreated_inv_Mclk_II/FCLK )
  );
  X_XOR2 \U2_AutoInc_MC.D_218  (
    .I0(\NlwInverterSignal_U2_AutoInc_MC.D/IN0 ),
    .I1(\U2_AutoInc_MC.D2 ),
    .O(\U2_AutoInc_MC.D )
  );
  X_AND2 \U2_AutoInc_MC.D1_219  (
    .I0(\AS_II/UIM ),
    .I1(\AS_II/UIM ),
    .O(\U2_AutoInc_MC.D1 )
  );
  X_ZERO \U2_AutoInc_MC.D2_220  (
    .O(\U2_AutoInc_MC.D2 )
  );
  X_BUF U2_WRRDedge_221 (
    .I(\U2_WRRDedge_MC.Q ),
    .O(U2_WRRDedge)
  );
  X_FF \U2_WRRDedge_MC.REG  (
    .I(\U2_WRRDedge_MC.D ),
    .CE(Vcc),
    .CLK(\U2_WRRDedge_MC.REG_tsimcreated_inv_Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\U2_WRRDedge_MC.Q )
  );
  X_INV \U2_WRRDedge_MC.REG_tsimcreated_inv_Mclk_II/FCLK_222  (
    .I(\Mclk_II/FCLK ),
    .O(\U2_WRRDedge_MC.REG_tsimcreated_inv_Mclk_II/FCLK )
  );
  X_XOR2 \U2_WRRDedge_MC.D_223  (
    .I0(\U2_WRRDedge_MC.D1 ),
    .I1(\U2_WRRDedge_MC.D2 ),
    .O(\U2_WRRDedge_MC.D )
  );
  X_AND2 \U2_WRRDedge_MC.D1_224  (
    .I0(\WR_II/UIM ),
    .I1(\RD_II/UIM ),
    .O(\U2_WRRDedge_MC.D1 )
  );
  X_ZERO \U2_WRRDedge_MC.D2_225  (
    .O(\U2_WRRDedge_MC.D2 )
  );
  X_BUF N_PZ_955_226 (
    .I(\N_PZ_955_MC.Q ),
    .O(N_PZ_955)
  );
  X_BUF \N_PZ_955_MC.Q_227  (
    .I(\N_PZ_955_MC.D ),
    .O(\N_PZ_955_MC.Q )
  );
  X_XOR2 \N_PZ_955_MC.D_228  (
    .I0(\N_PZ_955_MC.D1 ),
    .I1(\N_PZ_955_MC.D2 ),
    .O(\N_PZ_955_MC.D )
  );
  X_AND2 \N_PZ_955_MC.D1_229  (
    .I0(\WR_II/UIM ),
    .I1(\RD_II/UIM ),
    .O(\N_PZ_955_MC.D1 )
  );
  X_ZERO \N_PZ_955_MC.D2_230  (
    .O(\N_PZ_955_MC.D2 )
  );
  X_BUF N_PZ_941_231 (
    .I(\N_PZ_941_MC.Q ),
    .O(N_PZ_941)
  );
  X_BUF \N_PZ_941_MC.Q_232  (
    .I(\N_PZ_941_MC.D ),
    .O(\N_PZ_941_MC.Q )
  );
  X_XOR2 \N_PZ_941_MC.D_233  (
    .I0(\N_PZ_941_MC.D1 ),
    .I1(\N_PZ_941_MC.D2 ),
    .O(\N_PZ_941_MC.D )
  );
  X_ZERO \N_PZ_941_MC.D1_234  (
    .O(\N_PZ_941_MC.D1 )
  );
  X_AND2 \N_PZ_941_MC.D2_PT_0_235  (
    .I0(\MSPReset_II/UIM ),
    .I1(\AS_II/UIM ),
    .O(\N_PZ_941_MC.D2_PT_0 )
  );
  X_AND2 \N_PZ_941_MC.D2_PT_1_236  (
    .I0(\MSPReset_II/UIM ),
    .I1(\NlwInverterSignal_N_PZ_941_MC.D2_PT_1/IN1 ),
    .O(\N_PZ_941_MC.D2_PT_1 )
  );
  X_OR2 \N_PZ_941_MC.D2_237  (
    .I0(\N_PZ_941_MC.D2_PT_0 ),
    .I1(\N_PZ_941_MC.D2_PT_1 ),
    .O(\N_PZ_941_MC.D2 )
  );
  X_BUF \U2_ADDR_reg<3>  (
    .I(\U2_ADDR_reg<3>_MC.Q ),
    .O(U2_ADDR_reg[3])
  );
  X_XOR2 \U2_ADDR_reg<3>_MC_tsimcreated_xor__238  (
    .I0(\U2_ADDR_reg<3>_MC.D ),
    .I1(\U2_ADDR_reg<3>_MC.Q ),
    .O(\U2_ADDR_reg<3>_MC_tsimcreated_xor_ )
  );
  X_FF \U2_ADDR_reg<3>_MC.REG  (
    .I(\U2_ADDR_reg<3>_MC_tsimcreated_xor_ ),
    .CE(Vcc),
    .CLK(\U2_ADDR_reg<3>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\U2_ADDR_reg<3>_MC.Q )
  );
  X_INV \U2_ADDR_reg<3>_MC.REG_tsimcreated_inv_Mclk_II/FCLK_239  (
    .I(\Mclk_II/FCLK ),
    .O(\U2_ADDR_reg<3>_MC.REG_tsimcreated_inv_Mclk_II/FCLK )
  );
  X_XOR2 \U2_ADDR_reg<3>_MC.D_240  (
    .I0(\U2_ADDR_reg<3>_MC.D1 ),
    .I1(\U2_ADDR_reg<3>_MC.D2 ),
    .O(\U2_ADDR_reg<3>_MC.D )
  );
  X_ZERO \U2_ADDR_reg<3>_MC.D1_241  (
    .O(\U2_ADDR_reg<3>_MC.D1 )
  );
  X_AND2 \U2_ADDR_reg<3>_MC.D2_PT_0_242  (
    .I0(U2_ADDR_reg[3]),
    .I1(\NlwInverterSignal_U2_ADDR_reg<3>_MC.D2_PT_0/IN1 ),
    .O(\U2_ADDR_reg<3>_MC.D2_PT_0 )
  );
  X_AND6 \U2_ADDR_reg<3>_MC.D2_PT_1_243  (
    .I0(\WR_II/UIM ),
    .I1(\RD_II/UIM ),
    .I2(U2_ADDR_reg[3]),
    .I3(\NlwInverterSignal_U2_ADDR_reg<3>_MC.D2_PT_1/IN3 ),
    .I4(U2_ASedge),
    .I5(\NlwInverterSignal_U2_ADDR_reg<3>_MC.D2_PT_1/IN5 ),
    .O(\U2_ADDR_reg<3>_MC.D2_PT_1 )
  );
  X_AND7 \U2_ADDR_reg<3>_MC.D2_PT_2_244  (
    .I0(\WR_II/UIM ),
    .I1(\RD_II/UIM ),
    .I2(\NlwInverterSignal_U2_ADDR_reg<3>_MC.D2_PT_2/IN2 ),
    .I3(\MSPReset_II/UIM ),
    .I4(\NlwInverterSignal_U2_ADDR_reg<3>_MC.D2_PT_2/IN4 ),
    .I5(U2_ASedge),
    .I6(\AD<3>_II/UIM ),
    .O(\U2_ADDR_reg<3>_MC.D2_PT_2 )
  );
  X_AND16 \U2_ADDR_reg<3>_MC.D2_PT_3_245  (
    .I0(\WR_II/UIM ),
    .I1(\RD_II/UIM ),
    .I2(U2_ADDR_reg[0]),
    .I3(\NlwInverterSignal_U2_ADDR_reg<3>_MC.D2_PT_3/IN3 ),
    .I4(\NlwInverterSignal_U2_ADDR_reg<3>_MC.D2_PT_3/IN4 ),
    .I5(\NlwInverterSignal_U2_ADDR_reg<3>_MC.D2_PT_3/IN5 ),
    .I6(\NlwInverterSignal_U2_ADDR_reg<3>_MC.D2_PT_3/IN6 ),
    .I7(U2_ADDR_reg[1]),
    .I8(U2_ADDR_reg[2]),
    .I9(U2_AutoInc),
    .I10(\NlwInverterSignal_U2_ADDR_reg<3>_MC.D2_PT_3/IN10 ),
    .I11(N_PZ_941),
    .I12(Vcc),
    .I13(Vcc),
    .I14(Vcc),
    .I15(Vcc),
    .O(\U2_ADDR_reg<3>_MC.D2_PT_3 )
  );
  X_OR4 \U2_ADDR_reg<3>_MC.D2_246  (
    .I0(\U2_ADDR_reg<3>_MC.D2_PT_0 ),
    .I1(\U2_ADDR_reg<3>_MC.D2_PT_1 ),
    .I2(\U2_ADDR_reg<3>_MC.D2_PT_2 ),
    .I3(\U2_ADDR_reg<3>_MC.D2_PT_3 ),
    .O(\U2_ADDR_reg<3>_MC.D2 )
  );
  X_BUF \U2_ADDR_reg<1>  (
    .I(\U2_ADDR_reg<1>_MC.Q ),
    .O(U2_ADDR_reg[1])
  );
  X_XOR2 \U2_ADDR_reg<1>_MC_tsimcreated_xor__247  (
    .I0(\U2_ADDR_reg<1>_MC.D ),
    .I1(\U2_ADDR_reg<1>_MC.Q ),
    .O(\U2_ADDR_reg<1>_MC_tsimcreated_xor_ )
  );
  X_FF \U2_ADDR_reg<1>_MC.REG  (
    .I(\U2_ADDR_reg<1>_MC_tsimcreated_xor_ ),
    .CE(Vcc),
    .CLK(\U2_ADDR_reg<1>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\U2_ADDR_reg<1>_MC.Q )
  );
  X_INV \U2_ADDR_reg<1>_MC.REG_tsimcreated_inv_Mclk_II/FCLK_248  (
    .I(\Mclk_II/FCLK ),
    .O(\U2_ADDR_reg<1>_MC.REG_tsimcreated_inv_Mclk_II/FCLK )
  );
  X_XOR2 \U2_ADDR_reg<1>_MC.D_249  (
    .I0(\U2_ADDR_reg<1>_MC.D1 ),
    .I1(\U2_ADDR_reg<1>_MC.D2 ),
    .O(\U2_ADDR_reg<1>_MC.D )
  );
  X_ZERO \U2_ADDR_reg<1>_MC.D1_250  (
    .O(\U2_ADDR_reg<1>_MC.D1 )
  );
  X_AND2 \U2_ADDR_reg<1>_MC.D2_PT_0_251  (
    .I0(U2_ADDR_reg[1]),
    .I1(\NlwInverterSignal_U2_ADDR_reg<1>_MC.D2_PT_0/IN1 ),
    .O(\U2_ADDR_reg<1>_MC.D2_PT_0 )
  );
  X_AND6 \U2_ADDR_reg<1>_MC.D2_PT_1_252  (
    .I0(\WR_II/UIM ),
    .I1(\RD_II/UIM ),
    .I2(U2_ADDR_reg[1]),
    .I3(\NlwInverterSignal_U2_ADDR_reg<1>_MC.D2_PT_1/IN3 ),
    .I4(U2_ASedge),
    .I5(\NlwInverterSignal_U2_ADDR_reg<1>_MC.D2_PT_1/IN5 ),
    .O(\U2_ADDR_reg<1>_MC.D2_PT_1 )
  );
  X_AND7 \U2_ADDR_reg<1>_MC.D2_PT_2_253  (
    .I0(\WR_II/UIM ),
    .I1(\RD_II/UIM ),
    .I2(\NlwInverterSignal_U2_ADDR_reg<1>_MC.D2_PT_2/IN2 ),
    .I3(\MSPReset_II/UIM ),
    .I4(\NlwInverterSignal_U2_ADDR_reg<1>_MC.D2_PT_2/IN4 ),
    .I5(U2_ASedge),
    .I6(\AD<1>_II/UIM ),
    .O(\U2_ADDR_reg<1>_MC.D2_PT_2 )
  );
  X_AND16 \U2_ADDR_reg<1>_MC.D2_PT_3_254  (
    .I0(\WR_II/UIM ),
    .I1(\RD_II/UIM ),
    .I2(U2_ADDR_reg[0]),
    .I3(\NlwInverterSignal_U2_ADDR_reg<1>_MC.D2_PT_3/IN3 ),
    .I4(\NlwInverterSignal_U2_ADDR_reg<1>_MC.D2_PT_3/IN4 ),
    .I5(\NlwInverterSignal_U2_ADDR_reg<1>_MC.D2_PT_3/IN5 ),
    .I6(\NlwInverterSignal_U2_ADDR_reg<1>_MC.D2_PT_3/IN6 ),
    .I7(U2_AutoInc),
    .I8(\NlwInverterSignal_U2_ADDR_reg<1>_MC.D2_PT_3/IN8 ),
    .I9(N_PZ_941),
    .I10(Vcc),
    .I11(Vcc),
    .I12(Vcc),
    .I13(Vcc),
    .I14(Vcc),
    .I15(Vcc),
    .O(\U2_ADDR_reg<1>_MC.D2_PT_3 )
  );
  X_OR4 \U2_ADDR_reg<1>_MC.D2_255  (
    .I0(\U2_ADDR_reg<1>_MC.D2_PT_0 ),
    .I1(\U2_ADDR_reg<1>_MC.D2_PT_1 ),
    .I2(\U2_ADDR_reg<1>_MC.D2_PT_2 ),
    .I3(\U2_ADDR_reg<1>_MC.D2_PT_3 ),
    .O(\U2_ADDR_reg<1>_MC.D2 )
  );
  X_BUF \U2_ADDR_reg<2>  (
    .I(\U2_ADDR_reg<2>_MC.Q ),
    .O(U2_ADDR_reg[2])
  );
  X_XOR2 \U2_ADDR_reg<2>_MC_tsimcreated_xor__256  (
    .I0(\U2_ADDR_reg<2>_MC.D ),
    .I1(\U2_ADDR_reg<2>_MC.Q ),
    .O(\U2_ADDR_reg<2>_MC_tsimcreated_xor_ )
  );
  X_FF \U2_ADDR_reg<2>_MC.REG  (
    .I(\U2_ADDR_reg<2>_MC_tsimcreated_xor_ ),
    .CE(Vcc),
    .CLK(\U2_ADDR_reg<2>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\U2_ADDR_reg<2>_MC.Q )
  );
  X_INV \U2_ADDR_reg<2>_MC.REG_tsimcreated_inv_Mclk_II/FCLK_257  (
    .I(\Mclk_II/FCLK ),
    .O(\U2_ADDR_reg<2>_MC.REG_tsimcreated_inv_Mclk_II/FCLK )
  );
  X_XOR2 \U2_ADDR_reg<2>_MC.D_258  (
    .I0(\U2_ADDR_reg<2>_MC.D1 ),
    .I1(\U2_ADDR_reg<2>_MC.D2 ),
    .O(\U2_ADDR_reg<2>_MC.D )
  );
  X_ZERO \U2_ADDR_reg<2>_MC.D1_259  (
    .O(\U2_ADDR_reg<2>_MC.D1 )
  );
  X_AND2 \U2_ADDR_reg<2>_MC.D2_PT_0_260  (
    .I0(U2_ADDR_reg[2]),
    .I1(\NlwInverterSignal_U2_ADDR_reg<2>_MC.D2_PT_0/IN1 ),
    .O(\U2_ADDR_reg<2>_MC.D2_PT_0 )
  );
  X_AND6 \U2_ADDR_reg<2>_MC.D2_PT_1_261  (
    .I0(\WR_II/UIM ),
    .I1(\RD_II/UIM ),
    .I2(U2_ADDR_reg[2]),
    .I3(\NlwInverterSignal_U2_ADDR_reg<2>_MC.D2_PT_1/IN3 ),
    .I4(U2_ASedge),
    .I5(\NlwInverterSignal_U2_ADDR_reg<2>_MC.D2_PT_1/IN5 ),
    .O(\U2_ADDR_reg<2>_MC.D2_PT_1 )
  );
  X_AND7 \U2_ADDR_reg<2>_MC.D2_PT_2_262  (
    .I0(\WR_II/UIM ),
    .I1(\RD_II/UIM ),
    .I2(\NlwInverterSignal_U2_ADDR_reg<2>_MC.D2_PT_2/IN2 ),
    .I3(\MSPReset_II/UIM ),
    .I4(\NlwInverterSignal_U2_ADDR_reg<2>_MC.D2_PT_2/IN4 ),
    .I5(U2_ASedge),
    .I6(\AD<2>_II/UIM ),
    .O(\U2_ADDR_reg<2>_MC.D2_PT_2 )
  );
  X_AND16 \U2_ADDR_reg<2>_MC.D2_PT_3_263  (
    .I0(\WR_II/UIM ),
    .I1(\RD_II/UIM ),
    .I2(U2_ADDR_reg[0]),
    .I3(\NlwInverterSignal_U2_ADDR_reg<2>_MC.D2_PT_3/IN3 ),
    .I4(\NlwInverterSignal_U2_ADDR_reg<2>_MC.D2_PT_3/IN4 ),
    .I5(\NlwInverterSignal_U2_ADDR_reg<2>_MC.D2_PT_3/IN5 ),
    .I6(\NlwInverterSignal_U2_ADDR_reg<2>_MC.D2_PT_3/IN6 ),
    .I7(U2_ADDR_reg[1]),
    .I8(U2_AutoInc),
    .I9(\NlwInverterSignal_U2_ADDR_reg<2>_MC.D2_PT_3/IN9 ),
    .I10(N_PZ_941),
    .I11(Vcc),
    .I12(Vcc),
    .I13(Vcc),
    .I14(Vcc),
    .I15(Vcc),
    .O(\U2_ADDR_reg<2>_MC.D2_PT_3 )
  );
  X_OR4 \U2_ADDR_reg<2>_MC.D2_264  (
    .I0(\U2_ADDR_reg<2>_MC.D2_PT_0 ),
    .I1(\U2_ADDR_reg<2>_MC.D2_PT_1 ),
    .I2(\U2_ADDR_reg<2>_MC.D2_PT_2 ),
    .I3(\U2_ADDR_reg<2>_MC.D2_PT_3 ),
    .O(\U2_ADDR_reg<2>_MC.D2 )
  );
  X_BUF U2_Enable_AD_265 (
    .I(\U2_Enable_AD_MC.Q ),
    .O(U2_Enable_AD)
  );
  X_BUF \U2_Enable_AD_MC.Q_266  (
    .I(\U2_Enable_AD_MC.D ),
    .O(\U2_Enable_AD_MC.Q )
  );
  X_XOR2 \U2_Enable_AD_MC.D_267  (
    .I0(\U2_Enable_AD_MC.D1 ),
    .I1(\U2_Enable_AD_MC.D2 ),
    .O(\U2_Enable_AD_MC.D )
  );
  X_AND6 \U2_Enable_AD_MC.D1_268  (
    .I0(\WR_II/UIM ),
    .I1(\NlwInverterSignal_U2_Enable_AD_MC.D1/IN1 ),
    .I2(\NlwInverterSignal_U2_Enable_AD_MC.D1/IN2 ),
    .I3(\NlwInverterSignal_U2_Enable_AD_MC.D1/IN3 ),
    .I4(\NlwInverterSignal_U2_Enable_AD_MC.D1/IN4 ),
    .I5(\NlwInverterSignal_U2_Enable_AD_MC.D1/IN5 ),
    .O(\U2_Enable_AD_MC.D1 )
  );
  X_ZERO \U2_Enable_AD_MC.D2_269  (
    .O(\U2_Enable_AD_MC.D2 )
  );
  X_BUF \U4/ctrlr<3>_MC.Q_270  (
    .I(\U4/ctrlr<3>_MC.D ),
    .O(\U4/ctrlr<3>_MC.Q )
  );
  X_BUF \U4/ctrlr<3>_MC.OE_271  (
    .I(\U4/ctrlr<3>_MC.BUFOE.OUT ),
    .O(\U4/ctrlr<3>_MC.OE )
  );
  X_BUF \U4/ctrlr<3>_MC.BUFOE.OUT_272  (
    .I(\FOOBAR1__ctinst/7 ),
    .O(\U4/ctrlr<3>_MC.BUFOE.OUT )
  );
  X_XOR2 \U4/ctrlr<3>_MC.D_273  (
    .I0(\NlwInverterSignal_U4/ctrlr<3>_MC.D/IN0 ),
    .I1(\U4/ctrlr<3>_MC.D2 ),
    .O(\U4/ctrlr<3>_MC.D )
  );
  X_ZERO \U4/ctrlr<3>_MC.D1_274  (
    .O(\U4/ctrlr<3>_MC.D1 )
  );
  X_AND2 \U4/ctrlr<3>_MC.D2_PT_0_275  (
    .I0(DCORI2CCNTr),
    .I1(\NlwInverterSignal_U4/ctrlr<3>_MC.D2_PT_0/IN1 ),
    .O(\U4/ctrlr<3>_MC.D2_PT_0 )
  );
  X_AND2 \U4/ctrlr<3>_MC.D2_PT_1_276  (
    .I0(DCORCONFIGr),
    .I1(\NlwInverterSignal_U4/ctrlr<3>_MC.D2_PT_1/IN1 ),
    .O(\U4/ctrlr<3>_MC.D2_PT_1 )
  );
  X_AND2 \U4/ctrlr<3>_MC.D2_PT_2_277  (
    .I0(DCORLIMITSr),
    .I1(\NlwInverterSignal_U4/ctrlr<3>_MC.D2_PT_2/IN1 ),
    .O(\U4/ctrlr<3>_MC.D2_PT_2 )
  );
  X_AND2 \U4/ctrlr<3>_MC.D2_PT_3_278  (
    .I0(DCORENCPWRr),
    .I1(\NlwInverterSignal_U4/ctrlr<3>_MC.D2_PT_3/IN1 ),
    .O(\U4/ctrlr<3>_MC.D2_PT_3 )
  );
  X_AND2 \U4/ctrlr<3>_MC.D2_PT_4_279  (
    .I0(\NlwInverterSignal_U4/ctrlr<3>_MC.D2_PT_4/IN0 ),
    .I1(\NlwInverterSignal_U4/ctrlr<3>_MC.D2_PT_4/IN1 ),
    .O(\U4/ctrlr<3>_MC.D2_PT_4 )
  );
  X_AND2 \U4/ctrlr<3>_MC.D2_PT_5_280  (
    .I0(\NlwInverterSignal_U4/ctrlr<3>_MC.D2_PT_5/IN0 ),
    .I1(\NlwInverterSignal_U4/ctrlr<3>_MC.D2_PT_5/IN1 ),
    .O(\U4/ctrlr<3>_MC.D2_PT_5 )
  );
  X_OR6 \U4/ctrlr<3>_MC.D2_281  (
    .I0(\U4/ctrlr<3>_MC.D2_PT_0 ),
    .I1(\U4/ctrlr<3>_MC.D2_PT_1 ),
    .I2(\U4/ctrlr<3>_MC.D2_PT_2 ),
    .I3(\U4/ctrlr<3>_MC.D2_PT_3 ),
    .I4(\U4/ctrlr<3>_MC.D2_PT_4 ),
    .I5(\U4/ctrlr<3>_MC.D2_PT_5 ),
    .O(\U4/ctrlr<3>_MC.D2 )
  );
  X_BUF \Enc05ctrl_MC.Q_282  (
    .I(\Enc05ctrl_MC.Q_tsimrenamed_net_ ),
    .O(\Enc05ctrl_MC.Q )
  );
  X_BUF \Enc05ctrl_MC.Q_tsimrenamed_net__283  (
    .I(\Enc05ctrl_MC.D ),
    .O(\Enc05ctrl_MC.Q_tsimrenamed_net_ )
  );
  X_XOR2 \Enc05ctrl_MC.D_284  (
    .I0(\NlwInverterSignal_Enc05ctrl_MC.D/IN0 ),
    .I1(\Enc05ctrl_MC.D2 ),
    .O(\Enc05ctrl_MC.D )
  );
  X_AND2 \Enc05ctrl_MC.D1_285  (
    .I0(\NlwInverterSignal_Enc05ctrl_MC.D1/IN0 ),
    .I1(\U4/ctrlr [3]),
    .O(\Enc05ctrl_MC.D1 )
  );
  X_ZERO \Enc05ctrl_MC.D2_286  (
    .O(\Enc05ctrl_MC.D2 )
  );
  X_BUF \Enc133ctrl_MC.Q_287  (
    .I(\Enc133ctrl_MC.Q_tsimrenamed_net_ ),
    .O(\Enc133ctrl_MC.Q )
  );
  X_BUF \Enc133ctrl_MC.Q_tsimrenamed_net__288  (
    .I(\Enc133ctrl_MC.D ),
    .O(\Enc133ctrl_MC.Q_tsimrenamed_net_ )
  );
  X_XOR2 \Enc133ctrl_MC.D_289  (
    .I0(\NlwInverterSignal_Enc133ctrl_MC.D/IN0 ),
    .I1(\Enc133ctrl_MC.D2 ),
    .O(\Enc133ctrl_MC.D )
  );
  X_AND2 \Enc133ctrl_MC.D1_290  (
    .I0(\U4/ctrlr [6]),
    .I1(\U4/ctrlr [7]),
    .O(\Enc133ctrl_MC.D1 )
  );
  X_ZERO \Enc133ctrl_MC.D2_291  (
    .O(\Enc133ctrl_MC.D2 )
  );
  X_BUF \U4/ctrlr<6>_MC.Q_292  (
    .I(\U4/ctrlr<6>_MC.D ),
    .O(\U4/ctrlr<6>_MC.Q )
  );
  X_BUF \U4/ctrlr<6>_MC.OE_293  (
    .I(\U4/ctrlr<6>_MC.BUFOE.OUT ),
    .O(\U4/ctrlr<6>_MC.OE )
  );
  X_BUF \U4/ctrlr<6>_MC.BUFOE.OUT_294  (
    .I(\FOOBAR1__ctinst/7 ),
    .O(\U4/ctrlr<6>_MC.BUFOE.OUT )
  );
  X_XOR2 \U4/ctrlr<6>_MC.D_295  (
    .I0(\NlwInverterSignal_U4/ctrlr<6>_MC.D/IN0 ),
    .I1(\U4/ctrlr<6>_MC.D2 ),
    .O(\U4/ctrlr<6>_MC.D )
  );
  X_ZERO \U4/ctrlr<6>_MC.D1_296  (
    .O(\U4/ctrlr<6>_MC.D1 )
  );
  X_AND2 \U4/ctrlr<6>_MC.D2_PT_0_297  (
    .I0(DCORI2CCNTr),
    .I1(\NlwInverterSignal_U4/ctrlr<6>_MC.D2_PT_0/IN1 ),
    .O(\U4/ctrlr<6>_MC.D2_PT_0 )
  );
  X_AND2 \U4/ctrlr<6>_MC.D2_PT_1_298  (
    .I0(DCORCONFIGr),
    .I1(\NlwInverterSignal_U4/ctrlr<6>_MC.D2_PT_1/IN1 ),
    .O(\U4/ctrlr<6>_MC.D2_PT_1 )
  );
  X_AND2 \U4/ctrlr<6>_MC.D2_PT_2_299  (
    .I0(DCORLIMITSr),
    .I1(\NlwInverterSignal_U4/ctrlr<6>_MC.D2_PT_2/IN1 ),
    .O(\U4/ctrlr<6>_MC.D2_PT_2 )
  );
  X_AND2 \U4/ctrlr<6>_MC.D2_PT_3_300  (
    .I0(DCORENCPWRr),
    .I1(\NlwInverterSignal_U4/ctrlr<6>_MC.D2_PT_3/IN1 ),
    .O(\U4/ctrlr<6>_MC.D2_PT_3 )
  );
  X_AND2 \U4/ctrlr<6>_MC.D2_PT_4_301  (
    .I0(\NlwInverterSignal_U4/ctrlr<6>_MC.D2_PT_4/IN0 ),
    .I1(\NlwInverterSignal_U4/ctrlr<6>_MC.D2_PT_4/IN1 ),
    .O(\U4/ctrlr<6>_MC.D2_PT_4 )
  );
  X_AND2 \U4/ctrlr<6>_MC.D2_PT_5_302  (
    .I0(\NlwInverterSignal_U4/ctrlr<6>_MC.D2_PT_5/IN0 ),
    .I1(\NlwInverterSignal_U4/ctrlr<6>_MC.D2_PT_5/IN1 ),
    .O(\U4/ctrlr<6>_MC.D2_PT_5 )
  );
  X_OR6 \U4/ctrlr<6>_MC.D2_303  (
    .I0(\U4/ctrlr<6>_MC.D2_PT_0 ),
    .I1(\U4/ctrlr<6>_MC.D2_PT_1 ),
    .I2(\U4/ctrlr<6>_MC.D2_PT_2 ),
    .I3(\U4/ctrlr<6>_MC.D2_PT_3 ),
    .I4(\U4/ctrlr<6>_MC.D2_PT_4 ),
    .I5(\U4/ctrlr<6>_MC.D2_PT_5 ),
    .O(\U4/ctrlr<6>_MC.D2 )
  );
  X_BUF \U4/ctrlr<7>_MC.Q_304  (
    .I(\U4/ctrlr<7>_MC.D ),
    .O(\U4/ctrlr<7>_MC.Q )
  );
  X_BUF \U4/ctrlr<7>_MC.OE_305  (
    .I(\U4/ctrlr<7>_MC.BUFOE.OUT ),
    .O(\U4/ctrlr<7>_MC.OE )
  );
  X_BUF \U4/ctrlr<7>_MC.BUFOE.OUT_306  (
    .I(\FOOBAR1__ctinst/7 ),
    .O(\U4/ctrlr<7>_MC.BUFOE.OUT )
  );
  X_XOR2 \U4/ctrlr<7>_MC.D_307  (
    .I0(\NlwInverterSignal_U4/ctrlr<7>_MC.D/IN0 ),
    .I1(\U4/ctrlr<7>_MC.D2 ),
    .O(\U4/ctrlr<7>_MC.D )
  );
  X_ZERO \U4/ctrlr<7>_MC.D1_308  (
    .O(\U4/ctrlr<7>_MC.D1 )
  );
  X_AND2 \U4/ctrlr<7>_MC.D2_PT_0_309  (
    .I0(DCORI2CCNTr),
    .I1(\NlwInverterSignal_U4/ctrlr<7>_MC.D2_PT_0/IN1 ),
    .O(\U4/ctrlr<7>_MC.D2_PT_0 )
  );
  X_AND2 \U4/ctrlr<7>_MC.D2_PT_1_310  (
    .I0(DCORCONFIGr),
    .I1(\NlwInverterSignal_U4/ctrlr<7>_MC.D2_PT_1/IN1 ),
    .O(\U4/ctrlr<7>_MC.D2_PT_1 )
  );
  X_AND2 \U4/ctrlr<7>_MC.D2_PT_2_311  (
    .I0(DCORLIMITSr),
    .I1(\NlwInverterSignal_U4/ctrlr<7>_MC.D2_PT_2/IN1 ),
    .O(\U4/ctrlr<7>_MC.D2_PT_2 )
  );
  X_AND2 \U4/ctrlr<7>_MC.D2_PT_3_312  (
    .I0(DCORENCPWRr),
    .I1(\NlwInverterSignal_U4/ctrlr<7>_MC.D2_PT_3/IN1 ),
    .O(\U4/ctrlr<7>_MC.D2_PT_3 )
  );
  X_AND2 \U4/ctrlr<7>_MC.D2_PT_4_313  (
    .I0(\NlwInverterSignal_U4/ctrlr<7>_MC.D2_PT_4/IN0 ),
    .I1(\NlwInverterSignal_U4/ctrlr<7>_MC.D2_PT_4/IN1 ),
    .O(\U4/ctrlr<7>_MC.D2_PT_4 )
  );
  X_AND2 \U4/ctrlr<7>_MC.D2_PT_5_314  (
    .I0(\NlwInverterSignal_U4/ctrlr<7>_MC.D2_PT_5/IN0 ),
    .I1(DCORIFGr),
    .O(\U4/ctrlr<7>_MC.D2_PT_5 )
  );
  X_AND2 \U4/ctrlr<7>_MC.D2_PT_6_315  (
    .I0(DCOR0THRESLOWr),
    .I1(\NlwInverterSignal_U4/ctrlr<7>_MC.D2_PT_6/IN1 ),
    .O(\U4/ctrlr<7>_MC.D2_PT_6 )
  );
  X_AND3 \U4/ctrlr<7>_MC.D2_PT_7_316  (
    .I0(\NlwInverterSignal_U4/ctrlr<7>_MC.D2_PT_7/IN0 ),
    .I1(\NlwInverterSignal_U4/ctrlr<7>_MC.D2_PT_7/IN1 ),
    .I2(\NlwInverterSignal_U4/ctrlr<7>_MC.D2_PT_7/IN2 ),
    .O(\U4/ctrlr<7>_MC.D2_PT_7 )
  );
  X_OR8 \U4/ctrlr<7>_MC.D2_317  (
    .I0(\U4/ctrlr<7>_MC.D2_PT_0 ),
    .I1(\U4/ctrlr<7>_MC.D2_PT_1 ),
    .I2(\U4/ctrlr<7>_MC.D2_PT_2 ),
    .I3(\U4/ctrlr<7>_MC.D2_PT_3 ),
    .I4(\U4/ctrlr<7>_MC.D2_PT_4 ),
    .I5(\U4/ctrlr<7>_MC.D2_PT_5 ),
    .I6(\U4/ctrlr<7>_MC.D2_PT_6 ),
    .I7(\U4/ctrlr<7>_MC.D2_PT_7 ),
    .O(\U4/ctrlr<7>_MC.D2 )
  );
  X_BUF \Enc15ctrl_MC.Q_318  (
    .I(\Enc15ctrl_MC.Q_tsimrenamed_net_ ),
    .O(\Enc15ctrl_MC.Q )
  );
  X_BUF \Enc15ctrl_MC.Q_tsimrenamed_net__319  (
    .I(\Enc15ctrl_MC.D ),
    .O(\Enc15ctrl_MC.Q_tsimrenamed_net_ )
  );
  X_XOR2 \Enc15ctrl_MC.D_320  (
    .I0(\NlwInverterSignal_Enc15ctrl_MC.D/IN0 ),
    .I1(\Enc15ctrl_MC.D2 ),
    .O(\Enc15ctrl_MC.D )
  );
  X_AND2 \Enc15ctrl_MC.D1_321  (
    .I0(\NlwInverterSignal_Enc15ctrl_MC.D1/IN0 ),
    .I1(\U4/ctrlr [7]),
    .O(\Enc15ctrl_MC.D1 )
  );
  X_ZERO \Enc15ctrl_MC.D2_322  (
    .O(\Enc15ctrl_MC.D2 )
  );
  X_BUF \GPIO8_MC.Q_323  (
    .I(\GPIO8_MC.Q_tsimrenamed_net_ ),
    .O(\GPIO8_MC.Q )
  );
  X_BUF \GPIO8_MC.Q_tsimrenamed_net__324  (
    .I(\GPIO8_MC.D ),
    .O(\GPIO8_MC.Q_tsimrenamed_net_ )
  );
  X_XOR2 \GPIO8_MC.D_325  (
    .I0(\GPIO8_MC.D1 ),
    .I1(\GPIO8_MC.D2 ),
    .O(\GPIO8_MC.D )
  );
  X_AND2 \GPIO8_MC.D1_326  (
    .I0(\PWM5_II/UIM ),
    .I1(\PWM5_II/UIM ),
    .O(\GPIO8_MC.D1 )
  );
  X_ZERO \GPIO8_MC.D2_327  (
    .O(\GPIO8_MC.D2 )
  );
  X_BUF \GPIO9_MC.Q_328  (
    .I(\GPIO9_MC.Q_tsimrenamed_net_ ),
    .O(\GPIO9_MC.Q )
  );
  X_BUF \GPIO9_MC.Q_tsimrenamed_net__329  (
    .I(\GPIO9_MC.D ),
    .O(\GPIO9_MC.Q_tsimrenamed_net_ )
  );
  X_XOR2 \GPIO9_MC.D_330  (
    .I0(\GPIO9_MC.D1 ),
    .I1(\GPIO9_MC.D2 ),
    .O(\GPIO9_MC.D )
  );
  X_AND2 \GPIO9_MC.D1_331  (
    .I0(\PWM3_II/UIM ),
    .I1(\PWM3_II/UIM ),
    .O(\GPIO9_MC.D1 )
  );
  X_ZERO \GPIO9_MC.D2_332  (
    .O(\GPIO9_MC.D2 )
  );
  X_BUF \GP_Motor0_1_MC.Q_333  (
    .I(\GP_Motor0_1_MC.Q_tsimrenamed_net_ ),
    .O(\GP_Motor0_1_MC.Q )
  );
  X_OR2 GP_Motor0_1_MC_tsimcreated_prld__334 (
    .I0(\FOOBAR3__ctinst/7 ),
    .I1(PRLD),
    .O(GP_Motor0_1_MC_tsimcreated_prld_)
  );
  X_FF \GP_Motor0_1_MC.REG  (
    .I(\GP_Motor0_1_MC.D ),
    .CE(\GP_Motor0_1_MC.CE ),
    .CLK(\GP_Motor0_1_MC.REG_tsimcreated_inv_Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(GP_Motor0_1_MC_tsimcreated_prld_),
    .O(\GP_Motor0_1_MC.Q_tsimrenamed_net_ )
  );
  X_INV \GP_Motor0_1_MC.REG_tsimcreated_inv_Mclk_II/FCLK_335  (
    .I(\Mclk_II/FCLK ),
    .O(\GP_Motor0_1_MC.REG_tsimcreated_inv_Mclk_II/FCLK )
  );
  X_XOR2 \GP_Motor0_1_MC.D_336  (
    .I0(\GP_Motor0_1_MC.D1 ),
    .I1(\GP_Motor0_1_MC.D2 ),
    .O(\GP_Motor0_1_MC.D )
  );
  X_AND2 \GP_Motor0_1_MC.D1_337  (
    .I0(\AD<6>_II/UIM ),
    .I1(\AD<6>_II/UIM ),
    .O(\GP_Motor0_1_MC.D1 )
  );
  X_ZERO \GP_Motor0_1_MC.D2_338  (
    .O(\GP_Motor0_1_MC.D2 )
  );
  X_AND2 \GP_Motor0_1_MC.CE_339  (
    .I0(DCOROUTw),
    .I1(DCOROUTw),
    .O(\GP_Motor0_1_MC.CE )
  );
  X_BUF DCOROUTw_340 (
    .I(\DCOROUTw_MC.Q ),
    .O(DCOROUTw)
  );
  X_BUF \DCOROUTw_MC.Q_341  (
    .I(\DCOROUTw_MC.D ),
    .O(\DCOROUTw_MC.Q )
  );
  X_XOR2 \DCOROUTw_MC.D_342  (
    .I0(\DCOROUTw_MC.D1 ),
    .I1(\DCOROUTw_MC.D2 ),
    .O(\DCOROUTw_MC.D )
  );
  X_AND16 \DCOROUTw_MC.D1_343  (
    .I0(\NlwInverterSignal_DCOROUTw_MC.D1/IN0 ),
    .I1(\RD_II/UIM ),
    .I2(U2_ADDR_reg[0]),
    .I3(\NlwInverterSignal_DCOROUTw_MC.D1/IN3 ),
    .I4(\NlwInverterSignal_DCOROUTw_MC.D1/IN4 ),
    .I5(\NlwInverterSignal_DCOROUTw_MC.D1/IN5 ),
    .I6(\NlwInverterSignal_DCOROUTw_MC.D1/IN6 ),
    .I7(U2_ADDR_reg[3]),
    .I8(U2_ADDR_reg[1]),
    .I9(U2_ADDR_reg[2]),
    .I10(Vcc),
    .I11(Vcc),
    .I12(Vcc),
    .I13(Vcc),
    .I14(Vcc),
    .I15(Vcc),
    .O(\DCOROUTw_MC.D1 )
  );
  X_ZERO \DCOROUTw_MC.D2_344  (
    .O(\DCOROUTw_MC.D2 )
  );
  X_BUF \GP_Motor1_1_MC.Q_345  (
    .I(\GP_Motor1_1_MC.Q_tsimrenamed_net_ ),
    .O(\GP_Motor1_1_MC.Q )
  );
  X_OR2 GP_Motor1_1_MC_tsimcreated_prld__346 (
    .I0(\FOOBAR3__ctinst/7 ),
    .I1(PRLD),
    .O(GP_Motor1_1_MC_tsimcreated_prld_)
  );
  X_FF \GP_Motor1_1_MC.REG  (
    .I(\GP_Motor1_1_MC.D ),
    .CE(\FOOBAR15__ctinst/4 ),
    .CLK(\GP_Motor1_1_MC.REG_tsimcreated_inv_Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(GP_Motor1_1_MC_tsimcreated_prld_),
    .O(\GP_Motor1_1_MC.Q_tsimrenamed_net_ )
  );
  X_INV \GP_Motor1_1_MC.REG_tsimcreated_inv_Mclk_II/FCLK_347  (
    .I(\Mclk_II/FCLK ),
    .O(\GP_Motor1_1_MC.REG_tsimcreated_inv_Mclk_II/FCLK )
  );
  X_XOR2 \GP_Motor1_1_MC.D_348  (
    .I0(\GP_Motor1_1_MC.D1 ),
    .I1(\GP_Motor1_1_MC.D2 ),
    .O(\GP_Motor1_1_MC.D )
  );
  X_AND2 \GP_Motor1_1_MC.D1_349  (
    .I0(\AD<7>_II/UIM ),
    .I1(\AD<7>_II/UIM ),
    .O(\GP_Motor1_1_MC.D1 )
  );
  X_ZERO \GP_Motor1_1_MC.D2_350  (
    .O(\GP_Motor1_1_MC.D2 )
  );
  X_BUF \HSO_MC.Q_351  (
    .I(\HSO_MC.Q_tsimrenamed_net_ ),
    .O(\HSO_MC.Q )
  );
  X_BUF \HSO_MC.Q_tsimrenamed_net__352  (
    .I(\HSO_MC.D ),
    .O(\HSO_MC.Q_tsimrenamed_net_ )
  );
  X_XOR2 \HSO_MC.D_353  (
    .I0(\HSO_MC.D1 ),
    .I1(\HSO_MC.D2 ),
    .O(\HSO_MC.D )
  );
  X_AND2 \HSO_MC.D1_354  (
    .I0(\MHSO_II/UIM ),
    .I1(\MHSO_II/UIM ),
    .O(\HSO_MC.D1 )
  );
  X_ZERO \HSO_MC.D2_355  (
    .O(\HSO_MC.D2 )
  );
  X_BUF \Home033ctrl_MC.Q_356  (
    .I(\Home033ctrl_MC.Q_tsimrenamed_net_ ),
    .O(\Home033ctrl_MC.Q )
  );
  X_BUF \Home033ctrl_MC.Q_tsimrenamed_net__357  (
    .I(\Home033ctrl_MC.D ),
    .O(\Home033ctrl_MC.Q_tsimrenamed_net_ )
  );
  X_XOR2 \Home033ctrl_MC.D_358  (
    .I0(\NlwInverterSignal_Home033ctrl_MC.D/IN0 ),
    .I1(\Home033ctrl_MC.D2 ),
    .O(\Home033ctrl_MC.D )
  );
  X_AND2 \Home033ctrl_MC.D1_359  (
    .I0(\U4/ctrlr [0]),
    .I1(\NlwInverterSignal_Home033ctrl_MC.D1/IN1 ),
    .O(\Home033ctrl_MC.D1 )
  );
  X_ZERO \Home033ctrl_MC.D2_360  (
    .O(\Home033ctrl_MC.D2 )
  );
  X_BUF \U4/ctrlr<0>_MC.Q_361  (
    .I(\U4/ctrlr<0>_MC.D ),
    .O(\U4/ctrlr<0>_MC.Q )
  );
  X_BUF \U4/ctrlr<0>_MC.OE_362  (
    .I(\U4/ctrlr<0>_MC.BUFOE.OUT ),
    .O(\U4/ctrlr<0>_MC.OE )
  );
  X_BUF \U4/ctrlr<0>_MC.BUFOE.OUT_363  (
    .I(\FOOBAR1__ctinst/7 ),
    .O(\U4/ctrlr<0>_MC.BUFOE.OUT )
  );
  X_XOR2 \U4/ctrlr<0>_MC.D_364  (
    .I0(\NlwInverterSignal_U4/ctrlr<0>_MC.D/IN0 ),
    .I1(\U4/ctrlr<0>_MC.D2 ),
    .O(\U4/ctrlr<0>_MC.D )
  );
  X_ZERO \U4/ctrlr<0>_MC.D1_365  (
    .O(\U4/ctrlr<0>_MC.D1 )
  );
  X_AND2 \U4/ctrlr<0>_MC.D2_PT_0_366  (
    .I0(DCORI2CCNTr),
    .I1(\NlwInverterSignal_U4/ctrlr<0>_MC.D2_PT_0/IN1 ),
    .O(\U4/ctrlr<0>_MC.D2_PT_0 )
  );
  X_AND2 \U4/ctrlr<0>_MC.D2_PT_1_367  (
    .I0(DCORCONFIGr),
    .I1(\NlwInverterSignal_U4/ctrlr<0>_MC.D2_PT_1/IN1 ),
    .O(\U4/ctrlr<0>_MC.D2_PT_1 )
  );
  X_AND2 \U4/ctrlr<0>_MC.D2_PT_2_368  (
    .I0(DCORLIMITSr),
    .I1(\NlwInverterSignal_U4/ctrlr<0>_MC.D2_PT_2/IN1 ),
    .O(\U4/ctrlr<0>_MC.D2_PT_2 )
  );
  X_AND2 \U4/ctrlr<0>_MC.D2_PT_3_369  (
    .I0(DCORENCPWRr),
    .I1(\NlwInverterSignal_U4/ctrlr<0>_MC.D2_PT_3/IN1 ),
    .O(\U4/ctrlr<0>_MC.D2_PT_3 )
  );
  X_AND2 \U4/ctrlr<0>_MC.D2_PT_4_370  (
    .I0(\NlwInverterSignal_U4/ctrlr<0>_MC.D2_PT_4/IN0 ),
    .I1(\NlwInverterSignal_U4/ctrlr<0>_MC.D2_PT_4/IN1 ),
    .O(\U4/ctrlr<0>_MC.D2_PT_4 )
  );
  X_AND2 \U4/ctrlr<0>_MC.D2_PT_5_371  (
    .I0(DCORIFGr),
    .I1(\NlwInverterSignal_U4/ctrlr<0>_MC.D2_PT_5/IN1 ),
    .O(\U4/ctrlr<0>_MC.D2_PT_5 )
  );
  X_AND2 \U4/ctrlr<0>_MC.D2_PT_6_372  (
    .I0(DCOR0THRESLOWr),
    .I1(\NlwInverterSignal_U4/ctrlr<0>_MC.D2_PT_6/IN1 ),
    .O(\U4/ctrlr<0>_MC.D2_PT_6 )
  );
  X_AND3 \U4/ctrlr<0>_MC.D2_PT_7_373  (
    .I0(\NlwInverterSignal_U4/ctrlr<0>_MC.D2_PT_7/IN0 ),
    .I1(\NlwInverterSignal_U4/ctrlr<0>_MC.D2_PT_7/IN1 ),
    .I2(\NlwInverterSignal_U4/ctrlr<0>_MC.D2_PT_7/IN2 ),
    .O(\U4/ctrlr<0>_MC.D2_PT_7 )
  );
  X_OR8 \U4/ctrlr<0>_MC.D2_374  (
    .I0(\U4/ctrlr<0>_MC.D2_PT_0 ),
    .I1(\U4/ctrlr<0>_MC.D2_PT_1 ),
    .I2(\U4/ctrlr<0>_MC.D2_PT_2 ),
    .I3(\U4/ctrlr<0>_MC.D2_PT_3 ),
    .I4(\U4/ctrlr<0>_MC.D2_PT_4 ),
    .I5(\U4/ctrlr<0>_MC.D2_PT_5 ),
    .I6(\U4/ctrlr<0>_MC.D2_PT_6 ),
    .I7(\U4/ctrlr<0>_MC.D2_PT_7 ),
    .O(\U4/ctrlr<0>_MC.D2 )
  );
  X_BUF \U4/ctrlr<1>_MC.Q_375  (
    .I(\U4/ctrlr<1>_MC.D ),
    .O(\U4/ctrlr<1>_MC.Q )
  );
  X_BUF \U4/ctrlr<1>_MC.OE_376  (
    .I(\U4/ctrlr<1>_MC.BUFOE.OUT ),
    .O(\U4/ctrlr<1>_MC.OE )
  );
  X_BUF \U4/ctrlr<1>_MC.BUFOE.OUT_377  (
    .I(\FOOBAR1__ctinst/7 ),
    .O(\U4/ctrlr<1>_MC.BUFOE.OUT )
  );
  X_XOR2 \U4/ctrlr<1>_MC.D_378  (
    .I0(\NlwInverterSignal_U4/ctrlr<1>_MC.D/IN0 ),
    .I1(\U4/ctrlr<1>_MC.D2 ),
    .O(\U4/ctrlr<1>_MC.D )
  );
  X_ZERO \U4/ctrlr<1>_MC.D1_379  (
    .O(\U4/ctrlr<1>_MC.D1 )
  );
  X_AND2 \U4/ctrlr<1>_MC.D2_PT_0_380  (
    .I0(DCORI2CCNTr),
    .I1(\NlwInverterSignal_U4/ctrlr<1>_MC.D2_PT_0/IN1 ),
    .O(\U4/ctrlr<1>_MC.D2_PT_0 )
  );
  X_AND2 \U4/ctrlr<1>_MC.D2_PT_1_381  (
    .I0(DCORCONFIGr),
    .I1(\NlwInverterSignal_U4/ctrlr<1>_MC.D2_PT_1/IN1 ),
    .O(\U4/ctrlr<1>_MC.D2_PT_1 )
  );
  X_AND2 \U4/ctrlr<1>_MC.D2_PT_2_382  (
    .I0(DCORLIMITSr),
    .I1(\NlwInverterSignal_U4/ctrlr<1>_MC.D2_PT_2/IN1 ),
    .O(\U4/ctrlr<1>_MC.D2_PT_2 )
  );
  X_AND2 \U4/ctrlr<1>_MC.D2_PT_3_383  (
    .I0(DCORENCPWRr),
    .I1(\NlwInverterSignal_U4/ctrlr<1>_MC.D2_PT_3/IN1 ),
    .O(\U4/ctrlr<1>_MC.D2_PT_3 )
  );
  X_AND2 \U4/ctrlr<1>_MC.D2_PT_4_384  (
    .I0(\NlwInverterSignal_U4/ctrlr<1>_MC.D2_PT_4/IN0 ),
    .I1(\NlwInverterSignal_U4/ctrlr<1>_MC.D2_PT_4/IN1 ),
    .O(\U4/ctrlr<1>_MC.D2_PT_4 )
  );
  X_AND2 \U4/ctrlr<1>_MC.D2_PT_5_385  (
    .I0(DCORIFGr),
    .I1(\NlwInverterSignal_U4/ctrlr<1>_MC.D2_PT_5/IN1 ),
    .O(\U4/ctrlr<1>_MC.D2_PT_5 )
  );
  X_AND2 \U4/ctrlr<1>_MC.D2_PT_6_386  (
    .I0(DCOR0THRESLOWr),
    .I1(\NlwInverterSignal_U4/ctrlr<1>_MC.D2_PT_6/IN1 ),
    .O(\U4/ctrlr<1>_MC.D2_PT_6 )
  );
  X_AND3 \U4/ctrlr<1>_MC.D2_PT_7_387  (
    .I0(\NlwInverterSignal_U4/ctrlr<1>_MC.D2_PT_7/IN0 ),
    .I1(\NlwInverterSignal_U4/ctrlr<1>_MC.D2_PT_7/IN1 ),
    .I2(\NlwInverterSignal_U4/ctrlr<1>_MC.D2_PT_7/IN2 ),
    .O(\U4/ctrlr<1>_MC.D2_PT_7 )
  );
  X_OR8 \U4/ctrlr<1>_MC.D2_388  (
    .I0(\U4/ctrlr<1>_MC.D2_PT_0 ),
    .I1(\U4/ctrlr<1>_MC.D2_PT_1 ),
    .I2(\U4/ctrlr<1>_MC.D2_PT_2 ),
    .I3(\U4/ctrlr<1>_MC.D2_PT_3 ),
    .I4(\U4/ctrlr<1>_MC.D2_PT_4 ),
    .I5(\U4/ctrlr<1>_MC.D2_PT_5 ),
    .I6(\U4/ctrlr<1>_MC.D2_PT_6 ),
    .I7(\U4/ctrlr<1>_MC.D2_PT_7 ),
    .O(\U4/ctrlr<1>_MC.D2 )
  );
  X_BUF \Home05ctrl_MC.Q_389  (
    .I(\Home05ctrl_MC.Q_tsimrenamed_net_ ),
    .O(\Home05ctrl_MC.Q )
  );
  X_BUF \Home05ctrl_MC.Q_tsimrenamed_net__390  (
    .I(\Home05ctrl_MC.D ),
    .O(\Home05ctrl_MC.Q_tsimrenamed_net_ )
  );
  X_XOR2 \Home05ctrl_MC.D_391  (
    .I0(\NlwInverterSignal_Home05ctrl_MC.D/IN0 ),
    .I1(\Home05ctrl_MC.D2 ),
    .O(\Home05ctrl_MC.D )
  );
  X_AND2 \Home05ctrl_MC.D1_392  (
    .I0(\NlwInverterSignal_Home05ctrl_MC.D1/IN0 ),
    .I1(\U4/ctrlr [1]),
    .O(\Home05ctrl_MC.D1 )
  );
  X_ZERO \Home05ctrl_MC.D2_393  (
    .O(\Home05ctrl_MC.D2 )
  );
  X_BUF \Home133ctrl_MC.Q_394  (
    .I(\Home133ctrl_MC.Q_tsimrenamed_net_ ),
    .O(\Home133ctrl_MC.Q )
  );
  X_BUF \Home133ctrl_MC.Q_tsimrenamed_net__395  (
    .I(\Home133ctrl_MC.D ),
    .O(\Home133ctrl_MC.Q_tsimrenamed_net_ )
  );
  X_XOR2 \Home133ctrl_MC.D_396  (
    .I0(\NlwInverterSignal_Home133ctrl_MC.D/IN0 ),
    .I1(\Home133ctrl_MC.D2 ),
    .O(\Home133ctrl_MC.D )
  );
  X_AND2 \Home133ctrl_MC.D1_397  (
    .I0(\U4/ctrlr [4]),
    .I1(\NlwInverterSignal_Home133ctrl_MC.D1/IN1 ),
    .O(\Home133ctrl_MC.D1 )
  );
  X_ZERO \Home133ctrl_MC.D2_398  (
    .O(\Home133ctrl_MC.D2 )
  );
  X_BUF \U4/ctrlr<4>_MC.Q_399  (
    .I(\U4/ctrlr<4>_MC.D ),
    .O(\U4/ctrlr<4>_MC.Q )
  );
  X_BUF \U4/ctrlr<4>_MC.OE_400  (
    .I(\U4/ctrlr<4>_MC.BUFOE.OUT ),
    .O(\U4/ctrlr<4>_MC.OE )
  );
  X_BUF \U4/ctrlr<4>_MC.BUFOE.OUT_401  (
    .I(\FOOBAR1__ctinst/7 ),
    .O(\U4/ctrlr<4>_MC.BUFOE.OUT )
  );
  X_XOR2 \U4/ctrlr<4>_MC.D_402  (
    .I0(\NlwInverterSignal_U4/ctrlr<4>_MC.D/IN0 ),
    .I1(\U4/ctrlr<4>_MC.D2 ),
    .O(\U4/ctrlr<4>_MC.D )
  );
  X_ZERO \U4/ctrlr<4>_MC.D1_403  (
    .O(\U4/ctrlr<4>_MC.D1 )
  );
  X_AND2 \U4/ctrlr<4>_MC.D2_PT_0_404  (
    .I0(DCORI2CCNTr),
    .I1(\NlwInverterSignal_U4/ctrlr<4>_MC.D2_PT_0/IN1 ),
    .O(\U4/ctrlr<4>_MC.D2_PT_0 )
  );
  X_AND2 \U4/ctrlr<4>_MC.D2_PT_1_405  (
    .I0(DCORCONFIGr),
    .I1(\NlwInverterSignal_U4/ctrlr<4>_MC.D2_PT_1/IN1 ),
    .O(\U4/ctrlr<4>_MC.D2_PT_1 )
  );
  X_AND2 \U4/ctrlr<4>_MC.D2_PT_2_406  (
    .I0(DCORLIMITSr),
    .I1(\NlwInverterSignal_U4/ctrlr<4>_MC.D2_PT_2/IN1 ),
    .O(\U4/ctrlr<4>_MC.D2_PT_2 )
  );
  X_AND2 \U4/ctrlr<4>_MC.D2_PT_3_407  (
    .I0(DCORENCPWRr),
    .I1(\NlwInverterSignal_U4/ctrlr<4>_MC.D2_PT_3/IN1 ),
    .O(\U4/ctrlr<4>_MC.D2_PT_3 )
  );
  X_AND2 \U4/ctrlr<4>_MC.D2_PT_4_408  (
    .I0(\NlwInverterSignal_U4/ctrlr<4>_MC.D2_PT_4/IN0 ),
    .I1(\NlwInverterSignal_U4/ctrlr<4>_MC.D2_PT_4/IN1 ),
    .O(\U4/ctrlr<4>_MC.D2_PT_4 )
  );
  X_AND2 \U4/ctrlr<4>_MC.D2_PT_5_409  (
    .I0(DCORIFGr),
    .I1(\NlwInverterSignal_U4/ctrlr<4>_MC.D2_PT_5/IN1 ),
    .O(\U4/ctrlr<4>_MC.D2_PT_5 )
  );
  X_AND2 \U4/ctrlr<4>_MC.D2_PT_6_410  (
    .I0(DCOR0THRESLOWr),
    .I1(\NlwInverterSignal_U4/ctrlr<4>_MC.D2_PT_6/IN1 ),
    .O(\U4/ctrlr<4>_MC.D2_PT_6 )
  );
  X_AND3 \U4/ctrlr<4>_MC.D2_PT_7_411  (
    .I0(\NlwInverterSignal_U4/ctrlr<4>_MC.D2_PT_7/IN0 ),
    .I1(\NlwInverterSignal_U4/ctrlr<4>_MC.D2_PT_7/IN1 ),
    .I2(\NlwInverterSignal_U4/ctrlr<4>_MC.D2_PT_7/IN2 ),
    .O(\U4/ctrlr<4>_MC.D2_PT_7 )
  );
  X_OR8 \U4/ctrlr<4>_MC.D2_412  (
    .I0(\U4/ctrlr<4>_MC.D2_PT_0 ),
    .I1(\U4/ctrlr<4>_MC.D2_PT_1 ),
    .I2(\U4/ctrlr<4>_MC.D2_PT_2 ),
    .I3(\U4/ctrlr<4>_MC.D2_PT_3 ),
    .I4(\U4/ctrlr<4>_MC.D2_PT_4 ),
    .I5(\U4/ctrlr<4>_MC.D2_PT_5 ),
    .I6(\U4/ctrlr<4>_MC.D2_PT_6 ),
    .I7(\U4/ctrlr<4>_MC.D2_PT_7 ),
    .O(\U4/ctrlr<4>_MC.D2 )
  );
  X_BUF \U4/ctrlr<5>_MC.Q_413  (
    .I(\U4/ctrlr<5>_MC.D ),
    .O(\U4/ctrlr<5>_MC.Q )
  );
  X_BUF \U4/ctrlr<5>_MC.OE_414  (
    .I(\U4/ctrlr<5>_MC.BUFOE.OUT ),
    .O(\U4/ctrlr<5>_MC.OE )
  );
  X_BUF \U4/ctrlr<5>_MC.BUFOE.OUT_415  (
    .I(\FOOBAR1__ctinst/7 ),
    .O(\U4/ctrlr<5>_MC.BUFOE.OUT )
  );
  X_XOR2 \U4/ctrlr<5>_MC.D_416  (
    .I0(\NlwInverterSignal_U4/ctrlr<5>_MC.D/IN0 ),
    .I1(\U4/ctrlr<5>_MC.D2 ),
    .O(\U4/ctrlr<5>_MC.D )
  );
  X_ZERO \U4/ctrlr<5>_MC.D1_417  (
    .O(\U4/ctrlr<5>_MC.D1 )
  );
  X_AND2 \U4/ctrlr<5>_MC.D2_PT_0_418  (
    .I0(DCORI2CCNTr),
    .I1(\NlwInverterSignal_U4/ctrlr<5>_MC.D2_PT_0/IN1 ),
    .O(\U4/ctrlr<5>_MC.D2_PT_0 )
  );
  X_AND2 \U4/ctrlr<5>_MC.D2_PT_1_419  (
    .I0(DCORCONFIGr),
    .I1(\NlwInverterSignal_U4/ctrlr<5>_MC.D2_PT_1/IN1 ),
    .O(\U4/ctrlr<5>_MC.D2_PT_1 )
  );
  X_AND2 \U4/ctrlr<5>_MC.D2_PT_2_420  (
    .I0(DCORLIMITSr),
    .I1(\NlwInverterSignal_U4/ctrlr<5>_MC.D2_PT_2/IN1 ),
    .O(\U4/ctrlr<5>_MC.D2_PT_2 )
  );
  X_AND2 \U4/ctrlr<5>_MC.D2_PT_3_421  (
    .I0(DCORENCPWRr),
    .I1(\NlwInverterSignal_U4/ctrlr<5>_MC.D2_PT_3/IN1 ),
    .O(\U4/ctrlr<5>_MC.D2_PT_3 )
  );
  X_AND2 \U4/ctrlr<5>_MC.D2_PT_4_422  (
    .I0(\NlwInverterSignal_U4/ctrlr<5>_MC.D2_PT_4/IN0 ),
    .I1(\NlwInverterSignal_U4/ctrlr<5>_MC.D2_PT_4/IN1 ),
    .O(\U4/ctrlr<5>_MC.D2_PT_4 )
  );
  X_AND2 \U4/ctrlr<5>_MC.D2_PT_5_423  (
    .I0(\NlwInverterSignal_U4/ctrlr<5>_MC.D2_PT_5/IN0 ),
    .I1(\NlwInverterSignal_U4/ctrlr<5>_MC.D2_PT_5/IN1 ),
    .O(\U4/ctrlr<5>_MC.D2_PT_5 )
  );
  X_OR6 \U4/ctrlr<5>_MC.D2_424  (
    .I0(\U4/ctrlr<5>_MC.D2_PT_0 ),
    .I1(\U4/ctrlr<5>_MC.D2_PT_1 ),
    .I2(\U4/ctrlr<5>_MC.D2_PT_2 ),
    .I3(\U4/ctrlr<5>_MC.D2_PT_3 ),
    .I4(\U4/ctrlr<5>_MC.D2_PT_4 ),
    .I5(\U4/ctrlr<5>_MC.D2_PT_5 ),
    .O(\U4/ctrlr<5>_MC.D2 )
  );
  X_BUF \Home15ctrl_MC.Q_425  (
    .I(\Home15ctrl_MC.Q_tsimrenamed_net_ ),
    .O(\Home15ctrl_MC.Q )
  );
  X_BUF \Home15ctrl_MC.Q_tsimrenamed_net__426  (
    .I(\Home15ctrl_MC.D ),
    .O(\Home15ctrl_MC.Q_tsimrenamed_net_ )
  );
  X_XOR2 \Home15ctrl_MC.D_427  (
    .I0(\NlwInverterSignal_Home15ctrl_MC.D/IN0 ),
    .I1(\Home15ctrl_MC.D2 ),
    .O(\Home15ctrl_MC.D )
  );
  X_AND2 \Home15ctrl_MC.D1_428  (
    .I0(\NlwInverterSignal_Home15ctrl_MC.D1/IN0 ),
    .I1(\U4/ctrlr [5]),
    .O(\Home15ctrl_MC.D1 )
  );
  X_ZERO \Home15ctrl_MC.D2_429  (
    .O(\Home15ctrl_MC.D2 )
  );
  X_BUF \INT_MC.Q_430  (
    .I(\INT_MC.Q_tsimrenamed_net_ ),
    .O(\INT_MC.Q )
  );
  X_BUF \INT_MC.Q_tsimrenamed_net__431  (
    .I(\INT_MC.D ),
    .O(\INT_MC.Q_tsimrenamed_net_ )
  );
  X_XOR2 \INT_MC.D_432  (
    .I0(\INT_MC.D1 ),
    .I1(\INT_MC.D2 ),
    .O(\INT_MC.D )
  );
  X_ZERO \INT_MC.D1_433  (
    .O(\INT_MC.D1 )
  );
  X_AND2 \INT_MC.D2_PT_0_434  (
    .I0(\NlwInverterSignal_INT_MC.D2_PT_0/IN0 ),
    .I1(\U3/DCORIE [0]),
    .O(\INT_MC.D2_PT_0 )
  );
  X_AND2 \INT_MC.D2_PT_1_435  (
    .I0(NET2528),
    .I1(\U3/DCORIE [1]),
    .O(\INT_MC.D2_PT_1 )
  );
  X_AND2 \INT_MC.D2_PT_2_436  (
    .I0(NET2482),
    .I1(\U3/DCORIE [2]),
    .O(\INT_MC.D2_PT_2 )
  );
  X_AND2 \INT_MC.D2_PT_3_437  (
    .I0(NET2493),
    .I1(\U3/DCORIE [3]),
    .O(\INT_MC.D2_PT_3 )
  );
  X_AND2 \INT_MC.D2_PT_4_438  (
    .I0(NET2575),
    .I1(\U3/DCORIE [4]),
    .O(\INT_MC.D2_PT_4 )
  );
  X_AND2 \INT_MC.D2_PT_5_439  (
    .I0(NET2501),
    .I1(\U3/DCORIE [5]),
    .O(\INT_MC.D2_PT_5 )
  );
  X_AND2 \INT_MC.D2_PT_6_440  (
    .I0(NET2512),
    .I1(\U3/DCORIE [6]),
    .O(\INT_MC.D2_PT_6 )
  );
  X_AND2 \INT_MC.D2_PT_7_441  (
    .I0(\U3/DCORIE [7]),
    .I1(\TP12_MC.UIM ),
    .O(\INT_MC.D2_PT_7 )
  );
  X_OR8 \INT_MC.D2_442  (
    .I0(\INT_MC.D2_PT_0 ),
    .I1(\INT_MC.D2_PT_1 ),
    .I2(\INT_MC.D2_PT_2 ),
    .I3(\INT_MC.D2_PT_3 ),
    .I4(\INT_MC.D2_PT_4 ),
    .I5(\INT_MC.D2_PT_5 ),
    .I6(\INT_MC.D2_PT_6 ),
    .I7(\INT_MC.D2_PT_7 ),
    .O(\INT_MC.D2 )
  );
  X_BUF \U3/DCORIE<0>  (
    .I(\U3/DCORIE<0>_MC.Q ),
    .O(\U3/DCORIE [0])
  );
  X_FF \U3/DCORIE<0>_MC.REG  (
    .I(\U3/DCORIE<0>_MC.D ),
    .CE(Vcc),
    .CLK(\U3/DCORIE<0>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\U3/DCORIE<0>_MC.Q )
  );
  X_INV \U3/DCORIE<0>_MC.REG_tsimcreated_inv_Mclk_II/FCLK_443  (
    .I(\Mclk_II/FCLK ),
    .O(\U3/DCORIE<0>_MC.REG_tsimcreated_inv_Mclk_II/FCLK )
  );
  X_XOR2 \U3/DCORIE<0>_MC.D_444  (
    .I0(\U3/DCORIE<0>_MC.D1 ),
    .I1(\U3/DCORIE<0>_MC.D2 ),
    .O(\U3/DCORIE<0>_MC.D )
  );
  X_ZERO \U3/DCORIE<0>_MC.D1_445  (
    .O(\U3/DCORIE<0>_MC.D1 )
  );
  X_AND3 \U3/DCORIE<0>_MC.D2_PT_0_446  (
    .I0(\MSPReset_II/UIM ),
    .I1(\AD<0>_II/UIM ),
    .I2(DCORIEw),
    .O(\U3/DCORIE<0>_MC.D2_PT_0 )
  );
  X_AND3 \U3/DCORIE<0>_MC.D2_PT_1_447  (
    .I0(\MSPReset_II/UIM ),
    .I1(\U3/DCORIE [0]),
    .I2(\NlwInverterSignal_U3/DCORIE<0>_MC.D2_PT_1/IN2 ),
    .O(\U3/DCORIE<0>_MC.D2_PT_1 )
  );
  X_OR2 \U3/DCORIE<0>_MC.D2_448  (
    .I0(\U3/DCORIE<0>_MC.D2_PT_0 ),
    .I1(\U3/DCORIE<0>_MC.D2_PT_1 ),
    .O(\U3/DCORIE<0>_MC.D2 )
  );
  X_BUF DCORIEw_449 (
    .I(\DCORIEw_MC.Q ),
    .O(DCORIEw)
  );
  X_BUF \DCORIEw_MC.Q_450  (
    .I(\DCORIEw_MC.D ),
    .O(\DCORIEw_MC.Q )
  );
  X_XOR2 \DCORIEw_MC.D_451  (
    .I0(\DCORIEw_MC.D1 ),
    .I1(\DCORIEw_MC.D2 ),
    .O(\DCORIEw_MC.D )
  );
  X_AND16 \DCORIEw_MC.D1_452  (
    .I0(\NlwInverterSignal_DCORIEw_MC.D1/IN0 ),
    .I1(\RD_II/UIM ),
    .I2(\NlwInverterSignal_DCORIEw_MC.D1/IN2 ),
    .I3(\NlwInverterSignal_DCORIEw_MC.D1/IN3 ),
    .I4(\NlwInverterSignal_DCORIEw_MC.D1/IN4 ),
    .I5(\NlwInverterSignal_DCORIEw_MC.D1/IN5 ),
    .I6(\NlwInverterSignal_DCORIEw_MC.D1/IN6 ),
    .I7(\NlwInverterSignal_DCORIEw_MC.D1/IN7 ),
    .I8(\NlwInverterSignal_DCORIEw_MC.D1/IN8 ),
    .I9(\NlwInverterSignal_DCORIEw_MC.D1/IN9 ),
    .I10(Vcc),
    .I11(Vcc),
    .I12(Vcc),
    .I13(Vcc),
    .I14(Vcc),
    .I15(Vcc),
    .O(\DCORIEw_MC.D1 )
  );
  X_ZERO \DCORIEw_MC.D2_453  (
    .O(\DCORIEw_MC.D2 )
  );
  X_BUF NET2528_454 (
    .I(\NET2528_MC.Q ),
    .O(NET2528)
  );
  X_FF \NET2528_MC.REG  (
    .I(\NET2528_MC.D ),
    .CE(Vcc),
    .CLK(\NET2528_MC.REG_tsimcreated_inv_Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\NET2528_MC.Q )
  );
  X_INV \NET2528_MC.REG_tsimcreated_inv_Mclk_II/FCLK_455  (
    .I(\Mclk_II/FCLK ),
    .O(\NET2528_MC.REG_tsimcreated_inv_Mclk_II/FCLK )
  );
  X_XOR2 \NET2528_MC.D_456  (
    .I0(\NET2528_MC.D1 ),
    .I1(\NET2528_MC.D2 ),
    .O(\NET2528_MC.D )
  );
  X_AND2 \NET2528_MC.D1_457  (
    .I0(\MSPReset_II/UIM ),
    .I1(\NlwInverterSignal_NET2528_MC.D1/IN1 ),
    .O(\NET2528_MC.D1 )
  );
  X_AND4 \NET2528_MC.D2_PT_0_458  (
    .I0(\MSPReset_II/UIM ),
    .I1(\NlwInverterSignal_NET2528_MC.D2_PT_0/IN1 ),
    .I2(NET2528),
    .I3(DCORIFGw),
    .O(\NET2528_MC.D2_PT_0 )
  );
  X_AND16 \NET2528_MC.D2_PT_1_459  (
    .I0(\MSPReset_II/UIM ),
    .I1(\NlwInverterSignal_NET2528_MC.D2_PT_1/IN1 ),
    .I2(\NlwInverterSignal_NET2528_MC.D2_PT_1/IN2 ),
    .I3(\Home15FLG_II/UIM ),
    .I4(\Home133FLG_II/UIM ),
    .I5(\Home05FLG_II/UIM ),
    .I6(\Home033FLG_II/UIM ),
    .I7(\Enc15FLG_II/UIM ),
    .I8(\Enc133FLG_II/UIM ),
    .I9(\Enc05FLG_II/UIM ),
    .I10(\Enc033FLG_II/UIM ),
    .I11(Vcc),
    .I12(Vcc),
    .I13(Vcc),
    .I14(Vcc),
    .I15(Vcc),
    .O(\NET2528_MC.D2_PT_1 )
  );
  X_OR2 \NET2528_MC.D2_460  (
    .I0(\NET2528_MC.D2_PT_0 ),
    .I1(\NET2528_MC.D2_PT_1 ),
    .O(\NET2528_MC.D2 )
  );
  X_BUF DCORIFGw_461 (
    .I(\DCORIFGw_MC.Q ),
    .O(DCORIFGw)
  );
  X_BUF \DCORIFGw_MC.Q_462  (
    .I(\DCORIFGw_MC.D ),
    .O(\DCORIFGw_MC.Q )
  );
  X_XOR2 \DCORIFGw_MC.D_463  (
    .I0(\DCORIFGw_MC.D1 ),
    .I1(\DCORIFGw_MC.D2 ),
    .O(\DCORIFGw_MC.D )
  );
  X_AND16 \DCORIFGw_MC.D1_464  (
    .I0(\NlwInverterSignal_DCORIFGw_MC.D1/IN0 ),
    .I1(\RD_II/UIM ),
    .I2(U2_ADDR_reg[0]),
    .I3(\NlwInverterSignal_DCORIFGw_MC.D1/IN3 ),
    .I4(\NlwInverterSignal_DCORIFGw_MC.D1/IN4 ),
    .I5(\NlwInverterSignal_DCORIFGw_MC.D1/IN5 ),
    .I6(\NlwInverterSignal_DCORIFGw_MC.D1/IN6 ),
    .I7(\NlwInverterSignal_DCORIFGw_MC.D1/IN7 ),
    .I8(\NlwInverterSignal_DCORIFGw_MC.D1/IN8 ),
    .I9(\NlwInverterSignal_DCORIFGw_MC.D1/IN9 ),
    .I10(Vcc),
    .I11(Vcc),
    .I12(Vcc),
    .I13(Vcc),
    .I14(Vcc),
    .I15(Vcc),
    .O(\DCORIFGw_MC.D1 )
  );
  X_ZERO \DCORIFGw_MC.D2_465  (
    .O(\DCORIFGw_MC.D2 )
  );
  X_BUF \U3/DCORIE<1>  (
    .I(\U3/DCORIE<1>_MC.Q ),
    .O(\U3/DCORIE [1])
  );
  X_FF \U3/DCORIE<1>_MC.REG  (
    .I(\U3/DCORIE<1>_MC.D ),
    .CE(Vcc),
    .CLK(\U3/DCORIE<1>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\U3/DCORIE<1>_MC.Q )
  );
  X_INV \U3/DCORIE<1>_MC.REG_tsimcreated_inv_Mclk_II/FCLK_466  (
    .I(\Mclk_II/FCLK ),
    .O(\U3/DCORIE<1>_MC.REG_tsimcreated_inv_Mclk_II/FCLK )
  );
  X_XOR2 \U3/DCORIE<1>_MC.D_467  (
    .I0(\U3/DCORIE<1>_MC.D1 ),
    .I1(\U3/DCORIE<1>_MC.D2 ),
    .O(\U3/DCORIE<1>_MC.D )
  );
  X_ZERO \U3/DCORIE<1>_MC.D1_468  (
    .O(\U3/DCORIE<1>_MC.D1 )
  );
  X_AND3 \U3/DCORIE<1>_MC.D2_PT_0_469  (
    .I0(\MSPReset_II/UIM ),
    .I1(\AD<1>_II/UIM ),
    .I2(DCORIEw),
    .O(\U3/DCORIE<1>_MC.D2_PT_0 )
  );
  X_AND3 \U3/DCORIE<1>_MC.D2_PT_1_470  (
    .I0(\MSPReset_II/UIM ),
    .I1(\U3/DCORIE [1]),
    .I2(\NlwInverterSignal_U3/DCORIE<1>_MC.D2_PT_1/IN2 ),
    .O(\U3/DCORIE<1>_MC.D2_PT_1 )
  );
  X_OR2 \U3/DCORIE<1>_MC.D2_471  (
    .I0(\U3/DCORIE<1>_MC.D2_PT_0 ),
    .I1(\U3/DCORIE<1>_MC.D2_PT_1 ),
    .O(\U3/DCORIE<1>_MC.D2 )
  );
  X_BUF NET2482_472 (
    .I(\NET2482_MC.Q ),
    .O(NET2482)
  );
  X_XOR2 NET2482_MC_tsimcreated_xor__473 (
    .I0(\NET2482_MC.D ),
    .I1(\NET2482_MC.Q ),
    .O(NET2482_MC_tsimcreated_xor_)
  );
  X_FF \NET2482_MC.REG  (
    .I(NET2482_MC_tsimcreated_xor_),
    .CE(Vcc),
    .CLK(\NET2482_MC.REG_tsimcreated_inv_Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\NET2482_MC.Q )
  );
  X_INV \NET2482_MC.REG_tsimcreated_inv_Mclk_II/FCLK_474  (
    .I(\Mclk_II/FCLK ),
    .O(\NET2482_MC.REG_tsimcreated_inv_Mclk_II/FCLK )
  );
  X_XOR2 \NET2482_MC.D_475  (
    .I0(\NET2482_MC.D1 ),
    .I1(\NET2482_MC.D2 ),
    .O(\NET2482_MC.D )
  );
  X_ZERO \NET2482_MC.D1_476  (
    .O(\NET2482_MC.D1 )
  );
  X_AND2 \NET2482_MC.D2_PT_0_477  (
    .I0(\NlwInverterSignal_NET2482_MC.D2_PT_0/IN0 ),
    .I1(NET2482),
    .O(\NET2482_MC.D2_PT_0 )
  );
  X_AND4 \NET2482_MC.D2_PT_1_478  (
    .I0(\AD<2>_II/UIM ),
    .I1(NET2482),
    .I2(DCORIFGw),
    .I3(\NlwInverterSignal_NET2482_MC.D2_PT_1/IN3 ),
    .O(\NET2482_MC.D2_PT_1 )
  );
  X_AND8 \NET2482_MC.D2_PT_2_479  (
    .I0(\MSPReset_II/UIM ),
    .I1(\NlwInverterSignal_NET2482_MC.D2_PT_2/IN1 ),
    .I2(\NlwInverterSignal_NET2482_MC.D2_PT_2/IN2 ),
    .I3(\NlwInverterSignal_NET2482_MC.D2_PT_2/IN3 ),
    .I4(\U1/U4/RF0r ),
    .I5(\U1/U4/E0r ),
    .I6(\U1/U4/HE0stater ),
    .I7(\NlwInverterSignal_NET2482_MC.D2_PT_2/IN7 ),
    .O(\NET2482_MC.D2_PT_2 )
  );
  X_AND8 \NET2482_MC.D2_PT_3_480  (
    .I0(\MSPReset_II/UIM ),
    .I1(\NlwInverterSignal_NET2482_MC.D2_PT_3/IN1 ),
    .I2(\NlwInverterSignal_NET2482_MC.D2_PT_3/IN2 ),
    .I3(\NlwInverterSignal_NET2482_MC.D2_PT_3/IN3 ),
    .I4(\NlwInverterSignal_NET2482_MC.D2_PT_3/IN4 ),
    .I5(\U1/U4/E0r ),
    .I6(\NlwInverterSignal_NET2482_MC.D2_PT_3/IN6 ),
    .I7(\U1/U4/HE0statelastr ),
    .O(\NET2482_MC.D2_PT_3 )
  );
  X_OR4 \NET2482_MC.D2_481  (
    .I0(\NET2482_MC.D2_PT_0 ),
    .I1(\NET2482_MC.D2_PT_1 ),
    .I2(\NET2482_MC.D2_PT_2 ),
    .I3(\NET2482_MC.D2_PT_3 ),
    .O(\NET2482_MC.D2 )
  );
  X_BUF DCORENCCTLw_482 (
    .I(\DCORENCCTLw_MC.Q ),
    .O(DCORENCCTLw)
  );
  X_BUF \DCORENCCTLw_MC.Q_483  (
    .I(\DCORENCCTLw_MC.D ),
    .O(\DCORENCCTLw_MC.Q )
  );
  X_XOR2 \DCORENCCTLw_MC.D_484  (
    .I0(\DCORENCCTLw_MC.D1 ),
    .I1(\DCORENCCTLw_MC.D2 ),
    .O(\DCORENCCTLw_MC.D )
  );
  X_AND16 \DCORENCCTLw_MC.D1_485  (
    .I0(\NlwInverterSignal_DCORENCCTLw_MC.D1/IN0 ),
    .I1(\RD_II/UIM ),
    .I2(U2_ADDR_reg[0]),
    .I3(\NlwInverterSignal_DCORENCCTLw_MC.D1/IN3 ),
    .I4(\NlwInverterSignal_DCORENCCTLw_MC.D1/IN4 ),
    .I5(\NlwInverterSignal_DCORENCCTLw_MC.D1/IN5 ),
    .I6(\NlwInverterSignal_DCORENCCTLw_MC.D1/IN6 ),
    .I7(\NlwInverterSignal_DCORENCCTLw_MC.D1/IN7 ),
    .I8(U2_ADDR_reg[1]),
    .I9(\NlwInverterSignal_DCORENCCTLw_MC.D1/IN9 ),
    .I10(Vcc),
    .I11(Vcc),
    .I12(Vcc),
    .I13(Vcc),
    .I14(Vcc),
    .I15(Vcc),
    .O(\DCORENCCTLw_MC.D1 )
  );
  X_ZERO \DCORENCCTLw_MC.D2_486  (
    .O(\DCORENCCTLw_MC.D2 )
  );
  X_BUF \U1/U4/RF0r_487  (
    .I(\U1/U4/RF0r_MC.Q ),
    .O(\U1/U4/RF0r )
  );
  X_FF \U1/U4/RF0r_MC.REG  (
    .I(\U1/U4/RF0r_MC.D ),
    .CE(Vcc),
    .CLK(\U1/U4/RF0r_MC.REG_tsimcreated_inv_Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\U1/U4/RF0r_MC.Q )
  );
  X_INV \U1/U4/RF0r_MC.REG_tsimcreated_inv_Mclk_II/FCLK_488  (
    .I(\Mclk_II/FCLK ),
    .O(\U1/U4/RF0r_MC.REG_tsimcreated_inv_Mclk_II/FCLK )
  );
  X_XOR2 \U1/U4/RF0r_MC.D_489  (
    .I0(\U1/U4/RF0r_MC.D1 ),
    .I1(\U1/U4/RF0r_MC.D2 ),
    .O(\U1/U4/RF0r_MC.D )
  );
  X_ZERO \U1/U4/RF0r_MC.D1_490  (
    .O(\U1/U4/RF0r_MC.D1 )
  );
  X_AND3 \U1/U4/RF0r_MC.D2_PT_0_491  (
    .I0(\MSPReset_II/UIM ),
    .I1(\AD<0>_II/UIM ),
    .I2(DCORENCCTLw),
    .O(\U1/U4/RF0r_MC.D2_PT_0 )
  );
  X_AND3 \U1/U4/RF0r_MC.D2_PT_1_492  (
    .I0(\MSPReset_II/UIM ),
    .I1(\NlwInverterSignal_U1/U4/RF0r_MC.D2_PT_1/IN1 ),
    .I2(\U1/U4/RF0r ),
    .O(\U1/U4/RF0r_MC.D2_PT_1 )
  );
  X_OR2 \U1/U4/RF0r_MC.D2_493  (
    .I0(\U1/U4/RF0r_MC.D2_PT_0 ),
    .I1(\U1/U4/RF0r_MC.D2_PT_1 ),
    .O(\U1/U4/RF0r_MC.D2 )
  );
  X_BUF \U1/U4/E0r_494  (
    .I(\U1/U4/E0r_MC.Q ),
    .O(\U1/U4/E0r )
  );
  X_FF \U1/U4/E0r_MC.REG  (
    .I(\U1/U4/E0r_MC.D ),
    .CE(Vcc),
    .CLK(\U1/U4/E0r_MC.REG_tsimcreated_inv_Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\U1/U4/E0r_MC.Q )
  );
  X_INV \U1/U4/E0r_MC.REG_tsimcreated_inv_Mclk_II/FCLK_495  (
    .I(\Mclk_II/FCLK ),
    .O(\U1/U4/E0r_MC.REG_tsimcreated_inv_Mclk_II/FCLK )
  );
  X_XOR2 \U1/U4/E0r_MC.D_496  (
    .I0(\U1/U4/E0r_MC.D1 ),
    .I1(\U1/U4/E0r_MC.D2 ),
    .O(\U1/U4/E0r_MC.D )
  );
  X_ZERO \U1/U4/E0r_MC.D1_497  (
    .O(\U1/U4/E0r_MC.D1 )
  );
  X_AND3 \U1/U4/E0r_MC.D2_PT_0_498  (
    .I0(\MSPReset_II/UIM ),
    .I1(\AD<1>_II/UIM ),
    .I2(DCORENCCTLw),
    .O(\U1/U4/E0r_MC.D2_PT_0 )
  );
  X_AND3 \U1/U4/E0r_MC.D2_PT_1_499  (
    .I0(\MSPReset_II/UIM ),
    .I1(\NlwInverterSignal_U1/U4/E0r_MC.D2_PT_1/IN1 ),
    .I2(\U1/U4/E0r ),
    .O(\U1/U4/E0r_MC.D2_PT_1 )
  );
  X_OR2 \U1/U4/E0r_MC.D2_500  (
    .I0(\U1/U4/E0r_MC.D2_PT_0 ),
    .I1(\U1/U4/E0r_MC.D2_PT_1 ),
    .O(\U1/U4/E0r_MC.D2 )
  );
  X_BUF \U1/U4/HE0statelastr_501  (
    .I(\U1/U4/HE0statelastr_MC.Q ),
    .O(\U1/U4/HE0statelastr )
  );
  X_FF \U1/U4/HE0statelastr_MC.REG  (
    .I(\U1/U4/HE0statelastr_MC.D ),
    .CE(Vcc),
    .CLK(\U1/U4/HE0statelastr_MC.REG_tsimcreated_inv_Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\U1/U4/HE0statelastr_MC.Q )
  );
  X_INV \U1/U4/HE0statelastr_MC.REG_tsimcreated_inv_Mclk_II/FCLK_502  (
    .I(\Mclk_II/FCLK ),
    .O(\U1/U4/HE0statelastr_MC.REG_tsimcreated_inv_Mclk_II/FCLK )
  );
  X_XOR2 \U1/U4/HE0statelastr_MC.D_503  (
    .I0(\U1/U4/HE0statelastr_MC.D1 ),
    .I1(\U1/U4/HE0statelastr_MC.D2 ),
    .O(\U1/U4/HE0statelastr_MC.D )
  );
  X_AND2 \U1/U4/HE0statelastr_MC.D1_504  (
    .I0(\U1/U4/HE0stater ),
    .I1(\U1/U4/HE0stater ),
    .O(\U1/U4/HE0statelastr_MC.D1 )
  );
  X_ZERO \U1/U4/HE0statelastr_MC.D2_505  (
    .O(\U1/U4/HE0statelastr_MC.D2 )
  );
  X_BUF \U3/DCORIE<2>  (
    .I(\U3/DCORIE<2>_MC.Q ),
    .O(\U3/DCORIE [2])
  );
  X_FF \U3/DCORIE<2>_MC.REG  (
    .I(\U3/DCORIE<2>_MC.D ),
    .CE(Vcc),
    .CLK(\U3/DCORIE<2>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\U3/DCORIE<2>_MC.Q )
  );
  X_INV \U3/DCORIE<2>_MC.REG_tsimcreated_inv_Mclk_II/FCLK_506  (
    .I(\Mclk_II/FCLK ),
    .O(\U3/DCORIE<2>_MC.REG_tsimcreated_inv_Mclk_II/FCLK )
  );
  X_XOR2 \U3/DCORIE<2>_MC.D_507  (
    .I0(\U3/DCORIE<2>_MC.D1 ),
    .I1(\U3/DCORIE<2>_MC.D2 ),
    .O(\U3/DCORIE<2>_MC.D )
  );
  X_ZERO \U3/DCORIE<2>_MC.D1_508  (
    .O(\U3/DCORIE<2>_MC.D1 )
  );
  X_AND3 \U3/DCORIE<2>_MC.D2_PT_0_509  (
    .I0(\MSPReset_II/UIM ),
    .I1(\AD<2>_II/UIM ),
    .I2(DCORIEw),
    .O(\U3/DCORIE<2>_MC.D2_PT_0 )
  );
  X_AND3 \U3/DCORIE<2>_MC.D2_PT_1_510  (
    .I0(\MSPReset_II/UIM ),
    .I1(\U3/DCORIE [2]),
    .I2(\NlwInverterSignal_U3/DCORIE<2>_MC.D2_PT_1/IN2 ),
    .O(\U3/DCORIE<2>_MC.D2_PT_1 )
  );
  X_OR2 \U3/DCORIE<2>_MC.D2_511  (
    .I0(\U3/DCORIE<2>_MC.D2_PT_0 ),
    .I1(\U3/DCORIE<2>_MC.D2_PT_1 ),
    .O(\U3/DCORIE<2>_MC.D2 )
  );
  X_BUF NET2493_512 (
    .I(\NET2493_MC.Q ),
    .O(NET2493)
  );
  X_XOR2 NET2493_MC_tsimcreated_xor__513 (
    .I0(\NET2493_MC.D ),
    .I1(\NET2493_MC.Q ),
    .O(NET2493_MC_tsimcreated_xor_)
  );
  X_FF \NET2493_MC.REG  (
    .I(NET2493_MC_tsimcreated_xor_),
    .CE(Vcc),
    .CLK(\NET2493_MC.REG_tsimcreated_inv_Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\NET2493_MC.Q )
  );
  X_INV \NET2493_MC.REG_tsimcreated_inv_Mclk_II/FCLK_514  (
    .I(\Mclk_II/FCLK ),
    .O(\NET2493_MC.REG_tsimcreated_inv_Mclk_II/FCLK )
  );
  X_XOR2 \NET2493_MC.D_515  (
    .I0(\NET2493_MC.D1 ),
    .I1(\NET2493_MC.D2 ),
    .O(\NET2493_MC.D )
  );
  X_ZERO \NET2493_MC.D1_516  (
    .O(\NET2493_MC.D1 )
  );
  X_AND2 \NET2493_MC.D2_PT_0_517  (
    .I0(\NlwInverterSignal_NET2493_MC.D2_PT_0/IN0 ),
    .I1(NET2493),
    .O(\NET2493_MC.D2_PT_0 )
  );
  X_AND4 \NET2493_MC.D2_PT_1_518  (
    .I0(\AD<3>_II/UIM ),
    .I1(NET2493),
    .I2(DCORIFGw),
    .I3(\NlwInverterSignal_NET2493_MC.D2_PT_1/IN3 ),
    .O(\NET2493_MC.D2_PT_1 )
  );
  X_AND8 \NET2493_MC.D2_PT_2_519  (
    .I0(\MSPReset_II/UIM ),
    .I1(\NlwInverterSignal_NET2493_MC.D2_PT_2/IN1 ),
    .I2(\NlwInverterSignal_NET2493_MC.D2_PT_2/IN2 ),
    .I3(\NlwInverterSignal_NET2493_MC.D2_PT_2/IN3 ),
    .I4(\U1/U4/RF1r ),
    .I5(\U1/U4/E1r ),
    .I6(\U1/U4/HE1stater ),
    .I7(\NlwInverterSignal_NET2493_MC.D2_PT_2/IN7 ),
    .O(\NET2493_MC.D2_PT_2 )
  );
  X_AND8 \NET2493_MC.D2_PT_3_520  (
    .I0(\MSPReset_II/UIM ),
    .I1(\NlwInverterSignal_NET2493_MC.D2_PT_3/IN1 ),
    .I2(\NlwInverterSignal_NET2493_MC.D2_PT_3/IN2 ),
    .I3(\NlwInverterSignal_NET2493_MC.D2_PT_3/IN3 ),
    .I4(\NlwInverterSignal_NET2493_MC.D2_PT_3/IN4 ),
    .I5(\U1/U4/E1r ),
    .I6(\NlwInverterSignal_NET2493_MC.D2_PT_3/IN6 ),
    .I7(\U1/U4/HE1statelastr ),
    .O(\NET2493_MC.D2_PT_3 )
  );
  X_OR4 \NET2493_MC.D2_521  (
    .I0(\NET2493_MC.D2_PT_0 ),
    .I1(\NET2493_MC.D2_PT_1 ),
    .I2(\NET2493_MC.D2_PT_2 ),
    .I3(\NET2493_MC.D2_PT_3 ),
    .O(\NET2493_MC.D2 )
  );
  X_BUF \U1/U4/RF1r_522  (
    .I(\U1/U4/RF1r_MC.Q ),
    .O(\U1/U4/RF1r )
  );
  X_FF \U1/U4/RF1r_MC.REG  (
    .I(\U1/U4/RF1r_MC.D ),
    .CE(Vcc),
    .CLK(\U1/U4/RF1r_MC.REG_tsimcreated_inv_Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\U1/U4/RF1r_MC.Q )
  );
  X_INV \U1/U4/RF1r_MC.REG_tsimcreated_inv_Mclk_II/FCLK_523  (
    .I(\Mclk_II/FCLK ),
    .O(\U1/U4/RF1r_MC.REG_tsimcreated_inv_Mclk_II/FCLK )
  );
  X_XOR2 \U1/U4/RF1r_MC.D_524  (
    .I0(\U1/U4/RF1r_MC.D1 ),
    .I1(\U1/U4/RF1r_MC.D2 ),
    .O(\U1/U4/RF1r_MC.D )
  );
  X_ZERO \U1/U4/RF1r_MC.D1_525  (
    .O(\U1/U4/RF1r_MC.D1 )
  );
  X_AND3 \U1/U4/RF1r_MC.D2_PT_0_526  (
    .I0(\MSPReset_II/UIM ),
    .I1(\AD<4>_II/UIM ),
    .I2(DCORENCCTLw),
    .O(\U1/U4/RF1r_MC.D2_PT_0 )
  );
  X_AND3 \U1/U4/RF1r_MC.D2_PT_1_527  (
    .I0(\MSPReset_II/UIM ),
    .I1(\NlwInverterSignal_U1/U4/RF1r_MC.D2_PT_1/IN1 ),
    .I2(\U1/U4/RF1r ),
    .O(\U1/U4/RF1r_MC.D2_PT_1 )
  );
  X_OR2 \U1/U4/RF1r_MC.D2_528  (
    .I0(\U1/U4/RF1r_MC.D2_PT_0 ),
    .I1(\U1/U4/RF1r_MC.D2_PT_1 ),
    .O(\U1/U4/RF1r_MC.D2 )
  );
  X_BUF \U1/U4/E1r_529  (
    .I(\U1/U4/E1r_MC.Q ),
    .O(\U1/U4/E1r )
  );
  X_FF \U1/U4/E1r_MC.REG  (
    .I(\U1/U4/E1r_MC.D ),
    .CE(Vcc),
    .CLK(\U1/U4/E1r_MC.REG_tsimcreated_inv_Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\U1/U4/E1r_MC.Q )
  );
  X_INV \U1/U4/E1r_MC.REG_tsimcreated_inv_Mclk_II/FCLK_530  (
    .I(\Mclk_II/FCLK ),
    .O(\U1/U4/E1r_MC.REG_tsimcreated_inv_Mclk_II/FCLK )
  );
  X_XOR2 \U1/U4/E1r_MC.D_531  (
    .I0(\U1/U4/E1r_MC.D1 ),
    .I1(\U1/U4/E1r_MC.D2 ),
    .O(\U1/U4/E1r_MC.D )
  );
  X_ZERO \U1/U4/E1r_MC.D1_532  (
    .O(\U1/U4/E1r_MC.D1 )
  );
  X_AND3 \U1/U4/E1r_MC.D2_PT_0_533  (
    .I0(\MSPReset_II/UIM ),
    .I1(\AD<5>_II/UIM ),
    .I2(DCORENCCTLw),
    .O(\U1/U4/E1r_MC.D2_PT_0 )
  );
  X_AND3 \U1/U4/E1r_MC.D2_PT_1_534  (
    .I0(\MSPReset_II/UIM ),
    .I1(\NlwInverterSignal_U1/U4/E1r_MC.D2_PT_1/IN1 ),
    .I2(\U1/U4/E1r ),
    .O(\U1/U4/E1r_MC.D2_PT_1 )
  );
  X_OR2 \U1/U4/E1r_MC.D2_535  (
    .I0(\U1/U4/E1r_MC.D2_PT_0 ),
    .I1(\U1/U4/E1r_MC.D2_PT_1 ),
    .O(\U1/U4/E1r_MC.D2 )
  );
  X_BUF \U1/U4/HE1statelastr_536  (
    .I(\U1/U4/HE1statelastr_MC.Q ),
    .O(\U1/U4/HE1statelastr )
  );
  X_FF \U1/U4/HE1statelastr_MC.REG  (
    .I(\U1/U4/HE1statelastr_MC.D ),
    .CE(Vcc),
    .CLK(\U1/U4/HE1statelastr_MC.REG_tsimcreated_inv_Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\U1/U4/HE1statelastr_MC.Q )
  );
  X_INV \U1/U4/HE1statelastr_MC.REG_tsimcreated_inv_Mclk_II/FCLK_537  (
    .I(\Mclk_II/FCLK ),
    .O(\U1/U4/HE1statelastr_MC.REG_tsimcreated_inv_Mclk_II/FCLK )
  );
  X_XOR2 \U1/U4/HE1statelastr_MC.D_538  (
    .I0(\U1/U4/HE1statelastr_MC.D1 ),
    .I1(\U1/U4/HE1statelastr_MC.D2 ),
    .O(\U1/U4/HE1statelastr_MC.D )
  );
  X_AND2 \U1/U4/HE1statelastr_MC.D1_539  (
    .I0(\U1/U4/HE1stater ),
    .I1(\U1/U4/HE1stater ),
    .O(\U1/U4/HE1statelastr_MC.D1 )
  );
  X_ZERO \U1/U4/HE1statelastr_MC.D2_540  (
    .O(\U1/U4/HE1statelastr_MC.D2 )
  );
  X_BUF \U3/DCORIE<3>  (
    .I(\U3/DCORIE<3>_MC.Q ),
    .O(\U3/DCORIE [3])
  );
  X_FF \U3/DCORIE<3>_MC.REG  (
    .I(\U3/DCORIE<3>_MC.D ),
    .CE(Vcc),
    .CLK(\U3/DCORIE<3>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\U3/DCORIE<3>_MC.Q )
  );
  X_INV \U3/DCORIE<3>_MC.REG_tsimcreated_inv_Mclk_II/FCLK_541  (
    .I(\Mclk_II/FCLK ),
    .O(\U3/DCORIE<3>_MC.REG_tsimcreated_inv_Mclk_II/FCLK )
  );
  X_XOR2 \U3/DCORIE<3>_MC.D_542  (
    .I0(\U3/DCORIE<3>_MC.D1 ),
    .I1(\U3/DCORIE<3>_MC.D2 ),
    .O(\U3/DCORIE<3>_MC.D )
  );
  X_ZERO \U3/DCORIE<3>_MC.D1_543  (
    .O(\U3/DCORIE<3>_MC.D1 )
  );
  X_AND3 \U3/DCORIE<3>_MC.D2_PT_0_544  (
    .I0(\MSPReset_II/UIM ),
    .I1(\AD<3>_II/UIM ),
    .I2(DCORIEw),
    .O(\U3/DCORIE<3>_MC.D2_PT_0 )
  );
  X_AND3 \U3/DCORIE<3>_MC.D2_PT_1_545  (
    .I0(\MSPReset_II/UIM ),
    .I1(\U3/DCORIE [3]),
    .I2(\NlwInverterSignal_U3/DCORIE<3>_MC.D2_PT_1/IN2 ),
    .O(\U3/DCORIE<3>_MC.D2_PT_1 )
  );
  X_OR2 \U3/DCORIE<3>_MC.D2_546  (
    .I0(\U3/DCORIE<3>_MC.D2_PT_0 ),
    .I1(\U3/DCORIE<3>_MC.D2_PT_1 ),
    .O(\U3/DCORIE<3>_MC.D2 )
  );
  X_BUF NET2575_547 (
    .I(\NET2575_MC.Q ),
    .O(NET2575)
  );
  X_FF \NET2575_MC.REG  (
    .I(\NET2575_MC.D ),
    .CE(Vcc),
    .CLK(\NET2575_MC.REG_tsimcreated_inv_Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\NET2575_MC.Q )
  );
  X_INV \NET2575_MC.REG_tsimcreated_inv_Mclk_II/FCLK_548  (
    .I(\Mclk_II/FCLK ),
    .O(\NET2575_MC.REG_tsimcreated_inv_Mclk_II/FCLK )
  );
  X_XOR2 \NET2575_MC.D_549  (
    .I0(\NET2575_MC.D1 ),
    .I1(\NET2575_MC.D2 ),
    .O(\NET2575_MC.D )
  );
  X_ZERO \NET2575_MC.D1_550  (
    .O(\NET2575_MC.D1 )
  );
  X_AND3 \NET2575_MC.D2_PT_0_551  (
    .I0(\DIR0_II/UIM ),
    .I1(\MSPReset_II/UIM ),
    .I2(\NlwInverterSignal_NET2575_MC.D2_PT_0/IN2 ),
    .O(\NET2575_MC.D2_PT_0 )
  );
  X_AND3 \NET2575_MC.D2_PT_1_552  (
    .I0(\NlwInverterSignal_NET2575_MC.D2_PT_1/IN0 ),
    .I1(\MSPReset_II/UIM ),
    .I2(\NlwInverterSignal_NET2575_MC.D2_PT_1/IN2 ),
    .O(\NET2575_MC.D2_PT_1 )
  );
  X_AND3 \NET2575_MC.D2_PT_2_553  (
    .I0(\DIR1_II/UIM ),
    .I1(\MSPReset_II/UIM ),
    .I2(\NlwInverterSignal_NET2575_MC.D2_PT_2/IN2 ),
    .O(\NET2575_MC.D2_PT_2 )
  );
  X_AND3 \NET2575_MC.D2_PT_3_554  (
    .I0(\NlwInverterSignal_NET2575_MC.D2_PT_3/IN0 ),
    .I1(\MSPReset_II/UIM ),
    .I2(\NlwInverterSignal_NET2575_MC.D2_PT_3/IN2 ),
    .O(\NET2575_MC.D2_PT_3 )
  );
  X_AND3 \NET2575_MC.D2_PT_4_555  (
    .I0(\MSPReset_II/UIM ),
    .I1(\NlwInverterSignal_NET2575_MC.D2_PT_4/IN1 ),
    .I2(NET2575),
    .O(\NET2575_MC.D2_PT_4 )
  );
  X_AND3 \NET2575_MC.D2_PT_5_556  (
    .I0(\MSPReset_II/UIM ),
    .I1(NET2575),
    .I2(\NlwInverterSignal_NET2575_MC.D2_PT_5/IN2 ),
    .O(\NET2575_MC.D2_PT_5 )
  );
  X_OR6 \NET2575_MC.D2_557  (
    .I0(\NET2575_MC.D2_PT_0 ),
    .I1(\NET2575_MC.D2_PT_1 ),
    .I2(\NET2575_MC.D2_PT_2 ),
    .I3(\NET2575_MC.D2_PT_3 ),
    .I4(\NET2575_MC.D2_PT_4 ),
    .I5(\NET2575_MC.D2_PT_5 ),
    .O(\NET2575_MC.D2 )
  );
  X_BUF \U3/DCORIE<4>  (
    .I(\U3/DCORIE<4>_MC.Q ),
    .O(\U3/DCORIE [4])
  );
  X_FF \U3/DCORIE<4>_MC.REG  (
    .I(\U3/DCORIE<4>_MC.D ),
    .CE(Vcc),
    .CLK(\U3/DCORIE<4>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\U3/DCORIE<4>_MC.Q )
  );
  X_INV \U3/DCORIE<4>_MC.REG_tsimcreated_inv_Mclk_II/FCLK_558  (
    .I(\Mclk_II/FCLK ),
    .O(\U3/DCORIE<4>_MC.REG_tsimcreated_inv_Mclk_II/FCLK )
  );
  X_XOR2 \U3/DCORIE<4>_MC.D_559  (
    .I0(\U3/DCORIE<4>_MC.D1 ),
    .I1(\U3/DCORIE<4>_MC.D2 ),
    .O(\U3/DCORIE<4>_MC.D )
  );
  X_ZERO \U3/DCORIE<4>_MC.D1_560  (
    .O(\U3/DCORIE<4>_MC.D1 )
  );
  X_AND3 \U3/DCORIE<4>_MC.D2_PT_0_561  (
    .I0(\MSPReset_II/UIM ),
    .I1(\AD<4>_II/UIM ),
    .I2(DCORIEw),
    .O(\U3/DCORIE<4>_MC.D2_PT_0 )
  );
  X_AND3 \U3/DCORIE<4>_MC.D2_PT_1_562  (
    .I0(\MSPReset_II/UIM ),
    .I1(\U3/DCORIE [4]),
    .I2(\NlwInverterSignal_U3/DCORIE<4>_MC.D2_PT_1/IN2 ),
    .O(\U3/DCORIE<4>_MC.D2_PT_1 )
  );
  X_OR2 \U3/DCORIE<4>_MC.D2_563  (
    .I0(\U3/DCORIE<4>_MC.D2_PT_0 ),
    .I1(\U3/DCORIE<4>_MC.D2_PT_1 ),
    .O(\U3/DCORIE<4>_MC.D2 )
  );
  X_BUF NET2501_564 (
    .I(\NET2501_MC.Q ),
    .O(NET2501)
  );
  X_XOR2 NET2501_MC_tsimcreated_xor__565 (
    .I0(\NET2501_MC.D ),
    .I1(\NET2501_MC.Q ),
    .O(NET2501_MC_tsimcreated_xor_)
  );
  X_FF \NET2501_MC.REG  (
    .I(NET2501_MC_tsimcreated_xor_),
    .CE(Vcc),
    .CLK(\NET2501_MC.REG_tsimcreated_inv_Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\NET2501_MC.Q )
  );
  X_INV \NET2501_MC.REG_tsimcreated_inv_Mclk_II/FCLK_566  (
    .I(\Mclk_II/FCLK ),
    .O(\NET2501_MC.REG_tsimcreated_inv_Mclk_II/FCLK )
  );
  X_XOR2 \NET2501_MC.D_567  (
    .I0(\NET2501_MC.D1 ),
    .I1(\NET2501_MC.D2 ),
    .O(\NET2501_MC.D )
  );
  X_ZERO \NET2501_MC.D1_568  (
    .O(\NET2501_MC.D1 )
  );
  X_AND2 \NET2501_MC.D2_PT_0_569  (
    .I0(\MSPReset_II/UIM ),
    .I1(N_PZ_965),
    .O(\NET2501_MC.D2_PT_0 )
  );
  X_AND5 \NET2501_MC.D2_PT_1_570  (
    .I0(\MSPReset_II/UIM ),
    .I1(\AD<5>_II/UIM ),
    .I2(NET2501),
    .I3(DCORIFGw),
    .I4(\NlwInverterSignal_NET2501_MC.D2_PT_1/IN4 ),
    .O(\NET2501_MC.D2_PT_1 )
  );
  X_OR2 \NET2501_MC.D2_571  (
    .I0(\NET2501_MC.D2_PT_0 ),
    .I1(\NET2501_MC.D2_PT_1 ),
    .O(\NET2501_MC.D2 )
  );
  X_BUF N_PZ_965_572 (
    .I(\N_PZ_965_MC.Q ),
    .O(N_PZ_965)
  );
  X_BUF \N_PZ_965_MC.Q_573  (
    .I(\N_PZ_965_MC.D ),
    .O(\N_PZ_965_MC.Q )
  );
  X_XOR2 \N_PZ_965_MC.D_574  (
    .I0(\N_PZ_965_MC.D1 ),
    .I1(\N_PZ_965_MC.D2 ),
    .O(\N_PZ_965_MC.D )
  );
  X_ZERO \N_PZ_965_MC.D1_575  (
    .O(\N_PZ_965_MC.D1 )
  );
  X_AND6 \N_PZ_965_MC.D2_PT_0_576  (
    .I0(\outDATA<6>\$WA1.UIM ),
    .I1(\NlwInverterSignal_N_PZ_965_MC.D2_PT_0/IN1 ),
    .I2(\NlwInverterSignal_N_PZ_965_MC.D2_PT_0/IN2 ),
    .I3(\NlwInverterSignal_N_PZ_965_MC.D2_PT_0/IN3 ),
    .I4(\U1/U4/LatchEdge0r ),
    .I5(\NlwInverterSignal_N_PZ_965_MC.D2_PT_0/IN5 ),
    .O(\N_PZ_965_MC.D2_PT_0 )
  );
  X_AND6 \N_PZ_965_MC.D2_PT_1_577  (
    .I0(\NlwInverterSignal_N_PZ_965_MC.D2_PT_1/IN0 ),
    .I1(\NlwInverterSignal_N_PZ_965_MC.D2_PT_1/IN1 ),
    .I2(\NlwInverterSignal_N_PZ_965_MC.D2_PT_1/IN2 ),
    .I3(\NlwInverterSignal_N_PZ_965_MC.D2_PT_1/IN3 ),
    .I4(\NlwInverterSignal_N_PZ_965_MC.D2_PT_1/IN4 ),
    .I5(\U1/U4/InEdge0r ),
    .O(\N_PZ_965_MC.D2_PT_1 )
  );
  X_OR2 \N_PZ_965_MC.D2_578  (
    .I0(\N_PZ_965_MC.D2_PT_0 ),
    .I1(\N_PZ_965_MC.D2_PT_1 ),
    .O(\N_PZ_965_MC.D2 )
  );
  X_BUF \U1/U4/LatchEdge0r_579  (
    .I(\U1/U4/LatchEdge0r_MC.Q ),
    .O(\U1/U4/LatchEdge0r )
  );
  X_FF \U1/U4/LatchEdge0r_MC.REG  (
    .I(\U1/U4/LatchEdge0r_MC.D ),
    .CE(Vcc),
    .CLK(\U1/U4/LatchEdge0r_MC.REG_tsimcreated_inv_Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\U1/U4/LatchEdge0r_MC.Q )
  );
  X_INV \U1/U4/LatchEdge0r_MC.REG_tsimcreated_inv_Mclk_II/FCLK_580  (
    .I(\Mclk_II/FCLK ),
    .O(\U1/U4/LatchEdge0r_MC.REG_tsimcreated_inv_Mclk_II/FCLK )
  );
  X_XOR2 \U1/U4/LatchEdge0r_MC.D_581  (
    .I0(\U1/U4/LatchEdge0r_MC.D1 ),
    .I1(\U1/U4/LatchEdge0r_MC.D2 ),
    .O(\U1/U4/LatchEdge0r_MC.D )
  );
  X_ZERO \U1/U4/LatchEdge0r_MC.D1_582  (
    .O(\U1/U4/LatchEdge0r_MC.D1 )
  );
  X_AND3 \U1/U4/LatchEdge0r_MC.D2_PT_0_583  (
    .I0(\MSPReset_II/UIM ),
    .I1(\AD<2>_II/UIM ),
    .I2(DCORENCCTLw),
    .O(\U1/U4/LatchEdge0r_MC.D2_PT_0 )
  );
  X_AND3 \U1/U4/LatchEdge0r_MC.D2_PT_1_584  (
    .I0(\MSPReset_II/UIM ),
    .I1(\NlwInverterSignal_U1/U4/LatchEdge0r_MC.D2_PT_1/IN1 ),
    .I2(\U1/U4/LatchEdge0r ),
    .O(\U1/U4/LatchEdge0r_MC.D2_PT_1 )
  );
  X_OR2 \U1/U4/LatchEdge0r_MC.D2_585  (
    .I0(\U1/U4/LatchEdge0r_MC.D2_PT_0 ),
    .I1(\U1/U4/LatchEdge0r_MC.D2_PT_1 ),
    .O(\U1/U4/LatchEdge0r_MC.D2 )
  );
  X_BUF \outDATA<6>\$WA1.UIM_586  (
    .I(\outDATA<6>\$WA1.UIM_MC.Q ),
    .O(\outDATA<6>\$WA1.UIM )
  );
  X_BUF \outDATA<6>\$WA1.UIM_MC.Q_587  (
    .I(\outDATA<6>\$WA1.UIM_MC.D ),
    .O(\outDATA<6>\$WA1.UIM_MC.Q )
  );
  X_XOR2 \outDATA<6>\$WA1.UIM_MC.D_588  (
    .I0(\outDATA<6>\$WA1.UIM_MC.D1 ),
    .I1(\outDATA<6>\$WA1.UIM_MC.D2 ),
    .O(\outDATA<6>\$WA1.UIM_MC.D )
  );
  X_AND2 \outDATA<6>\$WA1.UIM_MC.D1_589  (
    .I0(\GP_Motor0_0_II/UIM ),
    .I1(\GP_Motor0_0_II/UIM ),
    .O(\outDATA<6>\$WA1.UIM_MC.D1 )
  );
  X_ZERO \outDATA<6>\$WA1.UIM_MC.D2_590  (
    .O(\outDATA<6>\$WA1.UIM_MC.D2 )
  );
  X_BUF \U3/DCORIE<5>  (
    .I(\U3/DCORIE<5>_MC.Q ),
    .O(\U3/DCORIE [5])
  );
  X_FF \U3/DCORIE<5>_MC.REG  (
    .I(\U3/DCORIE<5>_MC.D ),
    .CE(Vcc),
    .CLK(\U3/DCORIE<5>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\U3/DCORIE<5>_MC.Q )
  );
  X_INV \U3/DCORIE<5>_MC.REG_tsimcreated_inv_Mclk_II/FCLK_591  (
    .I(\Mclk_II/FCLK ),
    .O(\U3/DCORIE<5>_MC.REG_tsimcreated_inv_Mclk_II/FCLK )
  );
  X_XOR2 \U3/DCORIE<5>_MC.D_592  (
    .I0(\U3/DCORIE<5>_MC.D1 ),
    .I1(\U3/DCORIE<5>_MC.D2 ),
    .O(\U3/DCORIE<5>_MC.D )
  );
  X_ZERO \U3/DCORIE<5>_MC.D1_593  (
    .O(\U3/DCORIE<5>_MC.D1 )
  );
  X_AND3 \U3/DCORIE<5>_MC.D2_PT_0_594  (
    .I0(\MSPReset_II/UIM ),
    .I1(\AD<5>_II/UIM ),
    .I2(DCORIEw),
    .O(\U3/DCORIE<5>_MC.D2_PT_0 )
  );
  X_AND3 \U3/DCORIE<5>_MC.D2_PT_1_595  (
    .I0(\MSPReset_II/UIM ),
    .I1(\U3/DCORIE [5]),
    .I2(\NlwInverterSignal_U3/DCORIE<5>_MC.D2_PT_1/IN2 ),
    .O(\U3/DCORIE<5>_MC.D2_PT_1 )
  );
  X_OR2 \U3/DCORIE<5>_MC.D2_596  (
    .I0(\U3/DCORIE<5>_MC.D2_PT_0 ),
    .I1(\U3/DCORIE<5>_MC.D2_PT_1 ),
    .O(\U3/DCORIE<5>_MC.D2 )
  );
  X_BUF NET2512_597 (
    .I(\NET2512_MC.Q ),
    .O(NET2512)
  );
  X_XOR2 NET2512_MC_tsimcreated_xor__598 (
    .I0(\NET2512_MC.D ),
    .I1(\NET2512_MC.Q ),
    .O(NET2512_MC_tsimcreated_xor_)
  );
  X_FF \NET2512_MC.REG  (
    .I(NET2512_MC_tsimcreated_xor_),
    .CE(Vcc),
    .CLK(\NET2512_MC.REG_tsimcreated_inv_Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\NET2512_MC.Q )
  );
  X_INV \NET2512_MC.REG_tsimcreated_inv_Mclk_II/FCLK_599  (
    .I(\Mclk_II/FCLK ),
    .O(\NET2512_MC.REG_tsimcreated_inv_Mclk_II/FCLK )
  );
  X_XOR2 \NET2512_MC.D_600  (
    .I0(\NET2512_MC.D1 ),
    .I1(\NET2512_MC.D2 ),
    .O(\NET2512_MC.D )
  );
  X_ZERO \NET2512_MC.D1_601  (
    .O(\NET2512_MC.D1 )
  );
  X_AND5 \NET2512_MC.D2_PT_0_602  (
    .I0(\MSPReset_II/UIM ),
    .I1(\AD<6>_II/UIM ),
    .I2(NET2512),
    .I3(DCORIFGw),
    .I4(\NlwInverterSignal_NET2512_MC.D2_PT_0/IN4 ),
    .O(\NET2512_MC.D2_PT_0 )
  );
  X_AND7 \NET2512_MC.D2_PT_1_603  (
    .I0(\MSPReset_II/UIM ),
    .I1(\NlwInverterSignal_NET2512_MC.D2_PT_1/IN1 ),
    .I2(\NlwInverterSignal_NET2512_MC.D2_PT_1/IN2 ),
    .I3(\NlwInverterSignal_NET2512_MC.D2_PT_1/IN3 ),
    .I4(\GP_Motor1_0_II/UIM ),
    .I5(\U1/U4/LatchEdge1r ),
    .I6(\NlwInverterSignal_NET2512_MC.D2_PT_1/IN6 ),
    .O(\NET2512_MC.D2_PT_1 )
  );
  X_AND7 \NET2512_MC.D2_PT_2_604  (
    .I0(\MSPReset_II/UIM ),
    .I1(\NlwInverterSignal_NET2512_MC.D2_PT_2/IN1 ),
    .I2(\NlwInverterSignal_NET2512_MC.D2_PT_2/IN2 ),
    .I3(\NlwInverterSignal_NET2512_MC.D2_PT_2/IN3 ),
    .I4(\NlwInverterSignal_NET2512_MC.D2_PT_2/IN4 ),
    .I5(\NlwInverterSignal_NET2512_MC.D2_PT_2/IN5 ),
    .I6(\U1/U4/InEdge1r ),
    .O(\NET2512_MC.D2_PT_2 )
  );
  X_OR3 \NET2512_MC.D2_605  (
    .I0(\NET2512_MC.D2_PT_0 ),
    .I1(\NET2512_MC.D2_PT_1 ),
    .I2(\NET2512_MC.D2_PT_2 ),
    .O(\NET2512_MC.D2 )
  );
  X_BUF \U1/U4/LatchEdge1r_606  (
    .I(\U1/U4/LatchEdge1r_MC.Q ),
    .O(\U1/U4/LatchEdge1r )
  );
  X_FF \U1/U4/LatchEdge1r_MC.REG  (
    .I(\U1/U4/LatchEdge1r_MC.D ),
    .CE(Vcc),
    .CLK(\U1/U4/LatchEdge1r_MC.REG_tsimcreated_inv_Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\U1/U4/LatchEdge1r_MC.Q )
  );
  X_INV \U1/U4/LatchEdge1r_MC.REG_tsimcreated_inv_Mclk_II/FCLK_607  (
    .I(\Mclk_II/FCLK ),
    .O(\U1/U4/LatchEdge1r_MC.REG_tsimcreated_inv_Mclk_II/FCLK )
  );
  X_XOR2 \U1/U4/LatchEdge1r_MC.D_608  (
    .I0(\U1/U4/LatchEdge1r_MC.D1 ),
    .I1(\U1/U4/LatchEdge1r_MC.D2 ),
    .O(\U1/U4/LatchEdge1r_MC.D )
  );
  X_ZERO \U1/U4/LatchEdge1r_MC.D1_609  (
    .O(\U1/U4/LatchEdge1r_MC.D1 )
  );
  X_AND3 \U1/U4/LatchEdge1r_MC.D2_PT_0_610  (
    .I0(\MSPReset_II/UIM ),
    .I1(\AD<6>_II/UIM ),
    .I2(DCORENCCTLw),
    .O(\U1/U4/LatchEdge1r_MC.D2_PT_0 )
  );
  X_AND3 \U1/U4/LatchEdge1r_MC.D2_PT_1_611  (
    .I0(\MSPReset_II/UIM ),
    .I1(\NlwInverterSignal_U1/U4/LatchEdge1r_MC.D2_PT_1/IN1 ),
    .I2(\U1/U4/LatchEdge1r ),
    .O(\U1/U4/LatchEdge1r_MC.D2_PT_1 )
  );
  X_OR2 \U1/U4/LatchEdge1r_MC.D2_612  (
    .I0(\U1/U4/LatchEdge1r_MC.D2_PT_0 ),
    .I1(\U1/U4/LatchEdge1r_MC.D2_PT_1 ),
    .O(\U1/U4/LatchEdge1r_MC.D2 )
  );
  X_BUF \U3/DCORIE<6>  (
    .I(\U3/DCORIE<6>_MC.Q ),
    .O(\U3/DCORIE [6])
  );
  X_FF \U3/DCORIE<6>_MC.REG  (
    .I(\U3/DCORIE<6>_MC.D ),
    .CE(Vcc),
    .CLK(\U3/DCORIE<6>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\U3/DCORIE<6>_MC.Q )
  );
  X_INV \U3/DCORIE<6>_MC.REG_tsimcreated_inv_Mclk_II/FCLK_613  (
    .I(\Mclk_II/FCLK ),
    .O(\U3/DCORIE<6>_MC.REG_tsimcreated_inv_Mclk_II/FCLK )
  );
  X_XOR2 \U3/DCORIE<6>_MC.D_614  (
    .I0(\U3/DCORIE<6>_MC.D1 ),
    .I1(\U3/DCORIE<6>_MC.D2 ),
    .O(\U3/DCORIE<6>_MC.D )
  );
  X_ZERO \U3/DCORIE<6>_MC.D1_615  (
    .O(\U3/DCORIE<6>_MC.D1 )
  );
  X_AND3 \U3/DCORIE<6>_MC.D2_PT_0_616  (
    .I0(\MSPReset_II/UIM ),
    .I1(\AD<6>_II/UIM ),
    .I2(DCORIEw),
    .O(\U3/DCORIE<6>_MC.D2_PT_0 )
  );
  X_AND3 \U3/DCORIE<6>_MC.D2_PT_1_617  (
    .I0(\MSPReset_II/UIM ),
    .I1(\U3/DCORIE [6]),
    .I2(\NlwInverterSignal_U3/DCORIE<6>_MC.D2_PT_1/IN2 ),
    .O(\U3/DCORIE<6>_MC.D2_PT_1 )
  );
  X_OR2 \U3/DCORIE<6>_MC.D2_618  (
    .I0(\U3/DCORIE<6>_MC.D2_PT_0 ),
    .I1(\U3/DCORIE<6>_MC.D2_PT_1 ),
    .O(\U3/DCORIE<6>_MC.D2 )
  );
  X_BUF \U3/DCORIE<7>  (
    .I(\U3/DCORIE<7>_MC.Q ),
    .O(\U3/DCORIE [7])
  );
  X_FF \U3/DCORIE<7>_MC.REG  (
    .I(\U3/DCORIE<7>_MC.D ),
    .CE(Vcc),
    .CLK(\U3/DCORIE<7>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\U3/DCORIE<7>_MC.Q )
  );
  X_INV \U3/DCORIE<7>_MC.REG_tsimcreated_inv_Mclk_II/FCLK_619  (
    .I(\Mclk_II/FCLK ),
    .O(\U3/DCORIE<7>_MC.REG_tsimcreated_inv_Mclk_II/FCLK )
  );
  X_XOR2 \U3/DCORIE<7>_MC.D_620  (
    .I0(\U3/DCORIE<7>_MC.D1 ),
    .I1(\U3/DCORIE<7>_MC.D2 ),
    .O(\U3/DCORIE<7>_MC.D )
  );
  X_ZERO \U3/DCORIE<7>_MC.D1_621  (
    .O(\U3/DCORIE<7>_MC.D1 )
  );
  X_AND3 \U3/DCORIE<7>_MC.D2_PT_0_622  (
    .I0(\MSPReset_II/UIM ),
    .I1(\AD<7>_II/UIM ),
    .I2(DCORIEw),
    .O(\U3/DCORIE<7>_MC.D2_PT_0 )
  );
  X_AND3 \U3/DCORIE<7>_MC.D2_PT_1_623  (
    .I0(\MSPReset_II/UIM ),
    .I1(\U3/DCORIE [7]),
    .I2(\NlwInverterSignal_U3/DCORIE<7>_MC.D2_PT_1/IN2 ),
    .O(\U3/DCORIE<7>_MC.D2_PT_1 )
  );
  X_OR2 \U3/DCORIE<7>_MC.D2_624  (
    .I0(\U3/DCORIE<7>_MC.D2_PT_0 ),
    .I1(\U3/DCORIE<7>_MC.D2_PT_1 ),
    .O(\U3/DCORIE<7>_MC.D2 )
  );
  X_BUF \TP12_MC.Q_625  (
    .I(\TP12_MC.Q_tsimrenamed_net_ ),
    .O(\TP12_MC.Q )
  );
  X_BUF \TP12_MC.UIM_626  (
    .I(\TP12_MC.Q_tsimrenamed_net_ ),
    .O(\TP12_MC.UIM )
  );
  X_BUF \TP12_MC.Q_tsimrenamed_net__627  (
    .I(\TP12_MC.D ),
    .O(\TP12_MC.Q_tsimrenamed_net_ )
  );
  X_XOR2 \TP12_MC.D_628  (
    .I0(\TP12_MC.D1 ),
    .I1(\TP12_MC.D2 ),
    .O(\TP12_MC.D )
  );
  X_AND6 \TP12_MC.D1_629  (
    .I0(\NlwInverterSignal_TP12_MC.D1/IN0 ),
    .I1(\NlwInverterSignal_TP12_MC.D1/IN1 ),
    .I2(\NlwInverterSignal_TP12_MC.D1/IN2 ),
    .I3(\NlwInverterSignal_TP12_MC.D1/IN3 ),
    .I4(\NlwInverterSignal_TP12_MC.D1/IN4 ),
    .I5(\NlwInverterSignal_TP12_MC.D1/IN5 ),
    .O(\TP12_MC.D1 )
  );
  X_ZERO \TP12_MC.D2_630  (
    .O(\TP12_MC.D2 )
  );
  X_BUF \U11_U3_counterr<3>  (
    .I(\U11_U3_counterr<3>_MC.Q ),
    .O(U11_U3_counterr[3])
  );
  X_XOR2 \U11_U3_counterr<3>_MC_tsimcreated_xor__631  (
    .I0(\U11_U3_counterr<3>_MC.D ),
    .I1(\U11_U3_counterr<3>_MC.Q ),
    .O(\U11_U3_counterr<3>_MC_tsimcreated_xor_ )
  );
  X_FF \U11_U3_counterr<3>_MC.REG  (
    .I(\U11_U3_counterr<3>_MC_tsimcreated_xor_ ),
    .CE(Vcc),
    .CLK(\U11_U3_counterr<3>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\U11_U3_counterr<3>_MC.Q )
  );
  X_INV \U11_U3_counterr<3>_MC.REG_tsimcreated_inv_Mclk_II/FCLK_632  (
    .I(\Mclk_II/FCLK ),
    .O(\U11_U3_counterr<3>_MC.REG_tsimcreated_inv_Mclk_II/FCLK )
  );
  X_XOR2 \U11_U3_counterr<3>_MC.D_633  (
    .I0(\NlwInverterSignal_U11_U3_counterr<3>_MC.D/IN0 ),
    .I1(\U11_U3_counterr<3>_MC.D2 ),
    .O(\U11_U3_counterr<3>_MC.D )
  );
  X_ZERO \U11_U3_counterr<3>_MC.D1_634  (
    .O(\U11_U3_counterr<3>_MC.D1 )
  );
  X_AND2 \U11_U3_counterr<3>_MC.D2_PT_0_635  (
    .I0(U11_U3_counterr[3]),
    .I1(\SCLreset_II/UIM ),
    .O(\U11_U3_counterr<3>_MC.D2_PT_0 )
  );
  X_AND3 \U11_U3_counterr<3>_MC.D2_PT_1_636  (
    .I0(\NlwInverterSignal_U11_U3_counterr<3>_MC.D2_PT_1/IN0 ),
    .I1(\NlwInverterSignal_U11_U3_counterr<3>_MC.D2_PT_1/IN1 ),
    .I2(N_PZ_1071),
    .O(\U11_U3_counterr<3>_MC.D2_PT_1 )
  );
  X_AND3 \U11_U3_counterr<3>_MC.D2_PT_2_637  (
    .I0(U11_U3_counterr[0]),
    .I1(\NlwInverterSignal_U11_U3_counterr<3>_MC.D2_PT_2/IN1 ),
    .I2(\NlwInverterSignal_U11_U3_counterr<3>_MC.D2_PT_2/IN2 ),
    .O(\U11_U3_counterr<3>_MC.D2_PT_2 )
  );
  X_AND3 \U11_U3_counterr<3>_MC.D2_PT_3_638  (
    .I0(U11_U3_counterr[1]),
    .I1(\NlwInverterSignal_U11_U3_counterr<3>_MC.D2_PT_3/IN1 ),
    .I2(\NlwInverterSignal_U11_U3_counterr<3>_MC.D2_PT_3/IN2 ),
    .O(\U11_U3_counterr<3>_MC.D2_PT_3 )
  );
  X_AND3 \U11_U3_counterr<3>_MC.D2_PT_4_639  (
    .I0(U11_U3_counterr[2]),
    .I1(\NlwInverterSignal_U11_U3_counterr<3>_MC.D2_PT_4/IN1 ),
    .I2(\NlwInverterSignal_U11_U3_counterr<3>_MC.D2_PT_4/IN2 ),
    .O(\U11_U3_counterr<3>_MC.D2_PT_4 )
  );
  X_AND3 \U11_U3_counterr<3>_MC.D2_PT_5_640  (
    .I0(\NlwInverterSignal_U11_U3_counterr<3>_MC.D2_PT_5/IN0 ),
    .I1(\NlwInverterSignal_U11_U3_counterr<3>_MC.D2_PT_5/IN1 ),
    .I2(\NlwInverterSignal_U11_U3_counterr<3>_MC.D2_PT_5/IN2 ),
    .O(\U11_U3_counterr<3>_MC.D2_PT_5 )
  );
  X_AND5 \U11_U3_counterr<3>_MC.D2_PT_6_641  (
    .I0(U11_U3_counterr[0]),
    .I1(U11_U3_counterr[1]),
    .I2(U11_U3_counterr[2]),
    .I3(\NlwInverterSignal_U11_U3_counterr<3>_MC.D2_PT_6/IN3 ),
    .I4(\NlwInverterSignal_U11_U3_counterr<3>_MC.D2_PT_6/IN4 ),
    .O(\U11_U3_counterr<3>_MC.D2_PT_6 )
  );
  X_OR7 \U11_U3_counterr<3>_MC.D2_642  (
    .I0(\U11_U3_counterr<3>_MC.D2_PT_0 ),
    .I1(\U11_U3_counterr<3>_MC.D2_PT_1 ),
    .I2(\U11_U3_counterr<3>_MC.D2_PT_2 ),
    .I3(\U11_U3_counterr<3>_MC.D2_PT_3 ),
    .I4(\U11_U3_counterr<3>_MC.D2_PT_4 ),
    .I5(\U11_U3_counterr<3>_MC.D2_PT_5 ),
    .I6(\U11_U3_counterr<3>_MC.D2_PT_6 ),
    .O(\U11_U3_counterr<3>_MC.D2 )
  );
  X_BUF N_PZ_1071_643 (
    .I(\N_PZ_1071_MC.Q ),
    .O(N_PZ_1071)
  );
  X_BUF \N_PZ_1071_MC.Q_644  (
    .I(\N_PZ_1071_MC.D ),
    .O(\N_PZ_1071_MC.Q )
  );
  X_XOR2 \N_PZ_1071_MC.D_645  (
    .I0(\N_PZ_1071_MC.D1 ),
    .I1(\N_PZ_1071_MC.D2 ),
    .O(\N_PZ_1071_MC.D )
  );
  X_ZERO \N_PZ_1071_MC.D1_646  (
    .O(\N_PZ_1071_MC.D1 )
  );
  X_AND2 \N_PZ_1071_MC.D2_PT_0_647  (
    .I0(\SCLreset_II/UIM ),
    .I1(\SCLreset_II/UIM ),
    .O(\N_PZ_1071_MC.D2_PT_0 )
  );
  X_AND3 \N_PZ_1071_MC.D2_PT_1_648  (
    .I0(\outDATA<7>\$WA4.UIM ),
    .I1(\NlwInverterSignal_N_PZ_1071_MC.D2_PT_1/IN1 ),
    .I2(U11_SCLdetect),
    .O(\N_PZ_1071_MC.D2_PT_1 )
  );
  X_AND3 \N_PZ_1071_MC.D2_PT_2_649  (
    .I0(U11_Incdetect),
    .I1(\NlwInverterSignal_N_PZ_1071_MC.D2_PT_2/IN1 ),
    .I2(U11_ResetDetect),
    .O(\N_PZ_1071_MC.D2_PT_2 )
  );
  X_OR3 \N_PZ_1071_MC.D2_650  (
    .I0(\N_PZ_1071_MC.D2_PT_0 ),
    .I1(\N_PZ_1071_MC.D2_PT_1 ),
    .I2(\N_PZ_1071_MC.D2_PT_2 ),
    .O(\N_PZ_1071_MC.D2 )
  );
  X_BUF U11_Incdetect_651 (
    .I(\U11_Incdetect_MC.Q ),
    .O(U11_Incdetect)
  );
  X_FF \U11_Incdetect_MC.REG  (
    .I(\U11_Incdetect_MC.D ),
    .CE(Vcc),
    .CLK(\U11_Incdetect_MC.REG_tsimcreated_inv_Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\U11_Incdetect_MC.Q )
  );
  X_INV \U11_Incdetect_MC.REG_tsimcreated_inv_Mclk_II/FCLK_652  (
    .I(\Mclk_II/FCLK ),
    .O(\U11_Incdetect_MC.REG_tsimcreated_inv_Mclk_II/FCLK )
  );
  X_XOR2 \U11_Incdetect_MC.D_653  (
    .I0(\U11_Incdetect_MC.D1 ),
    .I1(\U11_Incdetect_MC.D2 ),
    .O(\U11_Incdetect_MC.D )
  );
  X_AND2 \U11_Incdetect_MC.D1_654  (
    .I0(\NlwInverterSignal_U11_Incdetect_MC.D1/IN0 ),
    .I1(\U11_U1/Line_last ),
    .O(\U11_Incdetect_MC.D1 )
  );
  X_ZERO \U11_Incdetect_MC.D2_655  (
    .O(\U11_Incdetect_MC.D2 )
  );
  X_BUF U11_ResetDetect_656 (
    .I(\U11_ResetDetect_MC.Q ),
    .O(U11_ResetDetect)
  );
  X_FF \U11_ResetDetect_MC.REG  (
    .I(\U11_ResetDetect_MC.D ),
    .CE(Vcc),
    .CLK(\U11_ResetDetect_MC.REG_tsimcreated_inv_Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\U11_ResetDetect_MC.Q )
  );
  X_INV \U11_ResetDetect_MC.REG_tsimcreated_inv_Mclk_II/FCLK_657  (
    .I(\Mclk_II/FCLK ),
    .O(\U11_ResetDetect_MC.REG_tsimcreated_inv_Mclk_II/FCLK )
  );
  X_XOR2 \U11_ResetDetect_MC.D_658  (
    .I0(\U11_ResetDetect_MC.D1 ),
    .I1(\U11_ResetDetect_MC.D2 ),
    .O(\U11_ResetDetect_MC.D )
  );
  X_AND2 \U11_ResetDetect_MC.D1_659  (
    .I0(\NlwInverterSignal_U11_ResetDetect_MC.D1/IN0 ),
    .I1(\U11_U4/Line_last ),
    .O(\U11_ResetDetect_MC.D1 )
  );
  X_ZERO \U11_ResetDetect_MC.D2_660  (
    .O(\U11_ResetDetect_MC.D2 )
  );
  X_BUF U11_SCLdetect_661 (
    .I(\U11_SCLdetect_MC.Q ),
    .O(U11_SCLdetect)
  );
  X_FF \U11_SCLdetect_MC.REG  (
    .I(\U11_SCLdetect_MC.D ),
    .CE(Vcc),
    .CLK(\U11_SCLdetect_MC.REG_tsimcreated_inv_Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\U11_SCLdetect_MC.Q )
  );
  X_INV \U11_SCLdetect_MC.REG_tsimcreated_inv_Mclk_II/FCLK_662  (
    .I(\Mclk_II/FCLK ),
    .O(\U11_SCLdetect_MC.REG_tsimcreated_inv_Mclk_II/FCLK )
  );
  X_XOR2 \U11_SCLdetect_MC.D_663  (
    .I0(\U11_SCLdetect_MC.D1 ),
    .I1(\U11_SCLdetect_MC.D2 ),
    .O(\U11_SCLdetect_MC.D )
  );
  X_AND2 \U11_SCLdetect_MC.D1_664  (
    .I0(\NlwInverterSignal_U11_SCLdetect_MC.D1/IN0 ),
    .I1(\U11_U2/Line_last ),
    .O(\U11_SCLdetect_MC.D1 )
  );
  X_ZERO \U11_SCLdetect_MC.D2_665  (
    .O(\U11_SCLdetect_MC.D2 )
  );
  X_BUF \U11_U2/Line_last_MC.Q_666  (
    .I(\U11_U2/Line_last_MC.D ),
    .O(\U11_U2/Line_last_MC.Q )
  );
  X_BUF \U11_U2/Line_last_MC.OE_667  (
    .I(\U11_U2/Line_last_MC.BUFOE.OUT ),
    .O(\U11_U2/Line_last_MC.OE )
  );
  X_BUF \U11_U2/Line_last_MC.BUFOE.OUT_668  (
    .I(\FOOBAR4__ctinst/0 ),
    .O(\U11_U2/Line_last_MC.BUFOE.OUT )
  );
  X_XOR2 \U11_U2/Line_last_MC.D_669  (
    .I0(\U11_U2/Line_last_MC.D1 ),
    .I1(\U11_U2/Line_last_MC.D2 ),
    .O(\U11_U2/Line_last_MC.D )
  );
  X_ZERO \U11_U2/Line_last_MC.D1_670  (
    .O(\U11_U2/Line_last_MC.D1 )
  );
  X_ZERO \U11_U2/Line_last_MC.D2_671  (
    .O(\U11_U2/Line_last_MC.D2 )
  );
  X_BUF \outDATA<7>\$WA4.UIM_672  (
    .I(\outDATA<7>\$WA4.UIM_MC.Q ),
    .O(\outDATA<7>\$WA4.UIM )
  );
  X_BUF \outDATA<7>\$WA4.UIM_MC.Q_673  (
    .I(\outDATA<7>\$WA4.UIM_MC.D ),
    .O(\outDATA<7>\$WA4.UIM_MC.Q )
  );
  X_XOR2 \outDATA<7>\$WA4.UIM_MC.D_674  (
    .I0(\outDATA<7>\$WA4.UIM_MC.D1 ),
    .I1(\outDATA<7>\$WA4.UIM_MC.D2 ),
    .O(\outDATA<7>\$WA4.UIM_MC.D )
  );
  X_AND2 \outDATA<7>\$WA4.UIM_MC.D1_675  (
    .I0(\TP12_MC.UIM ),
    .I1(\TP12_MC.UIM ),
    .O(\outDATA<7>\$WA4.UIM_MC.D1 )
  );
  X_ZERO \outDATA<7>\$WA4.UIM_MC.D2_676  (
    .O(\outDATA<7>\$WA4.UIM_MC.D2 )
  );
  X_BUF \U11_U3_counterr<0>  (
    .I(\U11_U3_counterr<0>_MC.Q ),
    .O(U11_U3_counterr[0])
  );
  X_FF \U11_U3_counterr<0>_MC.REG  (
    .I(\U11_U3_counterr<0>_MC.D ),
    .CE(Vcc),
    .CLK(\U11_U3_counterr<0>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\U11_U3_counterr<0>_MC.Q )
  );
  X_INV \U11_U3_counterr<0>_MC.REG_tsimcreated_inv_Mclk_II/FCLK_677  (
    .I(\Mclk_II/FCLK ),
    .O(\U11_U3_counterr<0>_MC.REG_tsimcreated_inv_Mclk_II/FCLK )
  );
  X_XOR2 \U11_U3_counterr<0>_MC.D_678  (
    .I0(\U11_U3_counterr<0>_MC.D1 ),
    .I1(\U11_U3_counterr<0>_MC.D2 ),
    .O(\U11_U3_counterr<0>_MC.D )
  );
  X_ZERO \U11_U3_counterr<0>_MC.D1_679  (
    .O(\U11_U3_counterr<0>_MC.D1 )
  );
  X_AND2 \U11_U3_counterr<0>_MC.D2_PT_0_680  (
    .I0(\SCLreset_II/UIM ),
    .I1(\SCLinc_II/UIM ),
    .O(\U11_U3_counterr<0>_MC.D2_PT_0 )
  );
  X_AND4 \U11_U3_counterr<0>_MC.D2_PT_1_681  (
    .I0(U11_U3_counterr[0]),
    .I1(\NlwInverterSignal_U11_U3_counterr<0>_MC.D2_PT_1/IN1 ),
    .I2(U11_Incdetect),
    .I3(U11_SCLdetect),
    .O(\U11_U3_counterr<0>_MC.D2_PT_1 )
  );
  X_AND4 \U11_U3_counterr<0>_MC.D2_PT_2_682  (
    .I0(U11_U3_counterr[0]),
    .I1(\NlwInverterSignal_U11_U3_counterr<0>_MC.D2_PT_2/IN1 ),
    .I2(\NlwInverterSignal_U11_U3_counterr<0>_MC.D2_PT_2/IN2 ),
    .I3(\NlwInverterSignal_U11_U3_counterr<0>_MC.D2_PT_2/IN3 ),
    .O(\U11_U3_counterr<0>_MC.D2_PT_2 )
  );
  X_AND4 \U11_U3_counterr<0>_MC.D2_PT_3_683  (
    .I0(\NlwInverterSignal_U11_U3_counterr<0>_MC.D2_PT_3/IN0 ),
    .I1(\NlwInverterSignal_U11_U3_counterr<0>_MC.D2_PT_3/IN1 ),
    .I2(U11_Incdetect),
    .I3(\NlwInverterSignal_U11_U3_counterr<0>_MC.D2_PT_3/IN3 ),
    .O(\U11_U3_counterr<0>_MC.D2_PT_3 )
  );
  X_AND4 \U11_U3_counterr<0>_MC.D2_PT_4_684  (
    .I0(\NlwInverterSignal_U11_U3_counterr<0>_MC.D2_PT_4/IN0 ),
    .I1(U11_Incdetect),
    .I2(\NlwInverterSignal_U11_U3_counterr<0>_MC.D2_PT_4/IN2 ),
    .I3(U11_ResetDetect),
    .O(\U11_U3_counterr<0>_MC.D2_PT_4 )
  );
  X_AND5 \U11_U3_counterr<0>_MC.D2_PT_5_685  (
    .I0(\NlwInverterSignal_U11_U3_counterr<0>_MC.D2_PT_5/IN0 ),
    .I1(\NlwInverterSignal_U11_U3_counterr<0>_MC.D2_PT_5/IN1 ),
    .I2(\NlwInverterSignal_U11_U3_counterr<0>_MC.D2_PT_5/IN2 ),
    .I3(\NlwInverterSignal_U11_U3_counterr<0>_MC.D2_PT_5/IN3 ),
    .I4(U11_SCLdetect),
    .O(\U11_U3_counterr<0>_MC.D2_PT_5 )
  );
  X_OR6 \U11_U3_counterr<0>_MC.D2_686  (
    .I0(\U11_U3_counterr<0>_MC.D2_PT_0 ),
    .I1(\U11_U3_counterr<0>_MC.D2_PT_1 ),
    .I2(\U11_U3_counterr<0>_MC.D2_PT_2 ),
    .I3(\U11_U3_counterr<0>_MC.D2_PT_3 ),
    .I4(\U11_U3_counterr<0>_MC.D2_PT_4 ),
    .I5(\U11_U3_counterr<0>_MC.D2_PT_5 ),
    .O(\U11_U3_counterr<0>_MC.D2 )
  );
  X_BUF \U11_U3_counterr<1>  (
    .I(\U11_U3_counterr<1>_MC.Q ),
    .O(U11_U3_counterr[1])
  );
  X_XOR2 \U11_U3_counterr<1>_MC_tsimcreated_xor__687  (
    .I0(\U11_U3_counterr<1>_MC.D ),
    .I1(\U11_U3_counterr<1>_MC.Q ),
    .O(\U11_U3_counterr<1>_MC_tsimcreated_xor_ )
  );
  X_FF \U11_U3_counterr<1>_MC.REG  (
    .I(\U11_U3_counterr<1>_MC_tsimcreated_xor_ ),
    .CE(Vcc),
    .CLK(\U11_U3_counterr<1>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\U11_U3_counterr<1>_MC.Q )
  );
  X_INV \U11_U3_counterr<1>_MC.REG_tsimcreated_inv_Mclk_II/FCLK_688  (
    .I(\Mclk_II/FCLK ),
    .O(\U11_U3_counterr<1>_MC.REG_tsimcreated_inv_Mclk_II/FCLK )
  );
  X_XOR2 \U11_U3_counterr<1>_MC.D_689  (
    .I0(\U11_U3_counterr<1>_MC.D1 ),
    .I1(\U11_U3_counterr<1>_MC.D2 ),
    .O(\U11_U3_counterr<1>_MC.D )
  );
  X_AND2 \U11_U3_counterr<1>_MC.D1_690  (
    .I0(U11_U3_counterr[1]),
    .I1(N_PZ_1071),
    .O(\U11_U3_counterr<1>_MC.D1 )
  );
  X_AND3 \U11_U3_counterr<1>_MC.D2_PT_0_691  (
    .I0(\SCLreset_II/UIM ),
    .I1(N_PZ_1071),
    .I2(\NlwInverterSignal_U11_U3_counterr<1>_MC.D2_PT_0/IN2 ),
    .O(\U11_U3_counterr<1>_MC.D2_PT_0 )
  );
  X_AND4 \U11_U3_counterr<1>_MC.D2_PT_1_692  (
    .I0(U11_U3_counterr[0]),
    .I1(\NlwInverterSignal_U11_U3_counterr<1>_MC.D2_PT_1/IN1 ),
    .I2(U11_Incdetect),
    .I3(\NlwInverterSignal_U11_U3_counterr<1>_MC.D2_PT_1/IN3 ),
    .O(\U11_U3_counterr<1>_MC.D2_PT_1 )
  );
  X_AND4 \U11_U3_counterr<1>_MC.D2_PT_2_693  (
    .I0(\NlwInverterSignal_U11_U3_counterr<1>_MC.D2_PT_2/IN0 ),
    .I1(\NlwInverterSignal_U11_U3_counterr<1>_MC.D2_PT_2/IN1 ),
    .I2(\NlwInverterSignal_U11_U3_counterr<1>_MC.D2_PT_2/IN2 ),
    .I3(U11_SCLdetect),
    .O(\U11_U3_counterr<1>_MC.D2_PT_2 )
  );
  X_OR3 \U11_U3_counterr<1>_MC.D2_694  (
    .I0(\U11_U3_counterr<1>_MC.D2_PT_0 ),
    .I1(\U11_U3_counterr<1>_MC.D2_PT_1 ),
    .I2(\U11_U3_counterr<1>_MC.D2_PT_2 ),
    .O(\U11_U3_counterr<1>_MC.D2 )
  );
  X_BUF \U11_U3_counterr<2>  (
    .I(\U11_U3_counterr<2>_MC.Q ),
    .O(U11_U3_counterr[2])
  );
  X_XOR2 \U11_U3_counterr<2>_MC_tsimcreated_xor__695  (
    .I0(\U11_U3_counterr<2>_MC.D ),
    .I1(\U11_U3_counterr<2>_MC.Q ),
    .O(\U11_U3_counterr<2>_MC_tsimcreated_xor_ )
  );
  X_FF \U11_U3_counterr<2>_MC.REG  (
    .I(\U11_U3_counterr<2>_MC_tsimcreated_xor_ ),
    .CE(Vcc),
    .CLK(\U11_U3_counterr<2>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\U11_U3_counterr<2>_MC.Q )
  );
  X_INV \U11_U3_counterr<2>_MC.REG_tsimcreated_inv_Mclk_II/FCLK_696  (
    .I(\Mclk_II/FCLK ),
    .O(\U11_U3_counterr<2>_MC.REG_tsimcreated_inv_Mclk_II/FCLK )
  );
  X_XOR2 \U11_U3_counterr<2>_MC.D_697  (
    .I0(\U11_U3_counterr<2>_MC.D1 ),
    .I1(\U11_U3_counterr<2>_MC.D2 ),
    .O(\U11_U3_counterr<2>_MC.D )
  );
  X_ZERO \U11_U3_counterr<2>_MC.D1_698  (
    .O(\U11_U3_counterr<2>_MC.D1 )
  );
  X_AND2 \U11_U3_counterr<2>_MC.D2_PT_0_699  (
    .I0(U11_U3_counterr[2]),
    .I1(N_PZ_1071),
    .O(\U11_U3_counterr<2>_MC.D2_PT_0 )
  );
  X_AND5 \U11_U3_counterr<2>_MC.D2_PT_1_700  (
    .I0(U11_U3_counterr[0]),
    .I1(U11_U3_counterr[1]),
    .I2(\NlwInverterSignal_U11_U3_counterr<2>_MC.D2_PT_1/IN2 ),
    .I3(U11_Incdetect),
    .I4(\NlwInverterSignal_U11_U3_counterr<2>_MC.D2_PT_1/IN4 ),
    .O(\U11_U3_counterr<2>_MC.D2_PT_1 )
  );
  X_AND5 \U11_U3_counterr<2>_MC.D2_PT_2_701  (
    .I0(\NlwInverterSignal_U11_U3_counterr<2>_MC.D2_PT_2/IN0 ),
    .I1(\NlwInverterSignal_U11_U3_counterr<2>_MC.D2_PT_2/IN1 ),
    .I2(\NlwInverterSignal_U11_U3_counterr<2>_MC.D2_PT_2/IN2 ),
    .I3(\NlwInverterSignal_U11_U3_counterr<2>_MC.D2_PT_2/IN3 ),
    .I4(U11_SCLdetect),
    .O(\U11_U3_counterr<2>_MC.D2_PT_2 )
  );
  X_OR3 \U11_U3_counterr<2>_MC.D2_702  (
    .I0(\U11_U3_counterr<2>_MC.D2_PT_0 ),
    .I1(\U11_U3_counterr<2>_MC.D2_PT_1 ),
    .I2(\U11_U3_counterr<2>_MC.D2_PT_2 ),
    .O(\U11_U3_counterr<2>_MC.D2 )
  );
  X_BUF \U11_U3_counterr<4>  (
    .I(\U11_U3_counterr<4>_MC.Q ),
    .O(U11_U3_counterr[4])
  );
  X_XOR2 \U11_U3_counterr<4>_MC_tsimcreated_xor__703  (
    .I0(\U11_U3_counterr<4>_MC.D ),
    .I1(\U11_U3_counterr<4>_MC.Q ),
    .O(\U11_U3_counterr<4>_MC_tsimcreated_xor_ )
  );
  X_FF \U11_U3_counterr<4>_MC.REG  (
    .I(\U11_U3_counterr<4>_MC_tsimcreated_xor_ ),
    .CE(Vcc),
    .CLK(\U11_U3_counterr<4>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\U11_U3_counterr<4>_MC.Q )
  );
  X_INV \U11_U3_counterr<4>_MC.REG_tsimcreated_inv_Mclk_II/FCLK_704  (
    .I(\Mclk_II/FCLK ),
    .O(\U11_U3_counterr<4>_MC.REG_tsimcreated_inv_Mclk_II/FCLK )
  );
  X_XOR2 \U11_U3_counterr<4>_MC.D_705  (
    .I0(\U11_U3_counterr<4>_MC.D1 ),
    .I1(\U11_U3_counterr<4>_MC.D2 ),
    .O(\U11_U3_counterr<4>_MC.D )
  );
  X_ZERO \U11_U3_counterr<4>_MC.D1_706  (
    .O(\U11_U3_counterr<4>_MC.D1 )
  );
  X_AND2 \U11_U3_counterr<4>_MC.D2_PT_0_707  (
    .I0(U11_U3_counterr[4]),
    .I1(N_PZ_1071),
    .O(\U11_U3_counterr<4>_MC.D2_PT_0 )
  );
  X_AND3 \U11_U3_counterr<4>_MC.D2_PT_1_708  (
    .I0(\NlwInverterSignal_U11_U3_counterr<4>_MC.D2_PT_1/IN0 ),
    .I1(\NlwInverterSignal_U11_U3_counterr<4>_MC.D2_PT_1/IN1 ),
    .I2(N_PZ_1125),
    .O(\U11_U3_counterr<4>_MC.D2_PT_1 )
  );
  X_AND4 \U11_U3_counterr<4>_MC.D2_PT_2_709  (
    .I0(\NlwInverterSignal_U11_U3_counterr<4>_MC.D2_PT_2/IN0 ),
    .I1(\NlwInverterSignal_U11_U3_counterr<4>_MC.D2_PT_2/IN1 ),
    .I2(\NlwInverterSignal_U11_U3_counterr<4>_MC.D2_PT_2/IN2 ),
    .I3(\NlwInverterSignal_U11_U3_counterr<4>_MC.D2_PT_2/IN3 ),
    .O(\U11_U3_counterr<4>_MC.D2_PT_2 )
  );
  X_OR3 \U11_U3_counterr<4>_MC.D2_710  (
    .I0(\U11_U3_counterr<4>_MC.D2_PT_0 ),
    .I1(\U11_U3_counterr<4>_MC.D2_PT_1 ),
    .I2(\U11_U3_counterr<4>_MC.D2_PT_2 ),
    .O(\U11_U3_counterr<4>_MC.D2 )
  );
  X_BUF N_PZ_1145_711 (
    .I(\N_PZ_1145_MC.Q ),
    .O(N_PZ_1145)
  );
  X_BUF \N_PZ_1145_MC.Q_712  (
    .I(\N_PZ_1145_MC.D ),
    .O(\N_PZ_1145_MC.Q )
  );
  X_XOR2 \N_PZ_1145_MC.D_713  (
    .I0(\N_PZ_1145_MC.D1 ),
    .I1(\N_PZ_1145_MC.D2 ),
    .O(\N_PZ_1145_MC.D )
  );
  X_ZERO \N_PZ_1145_MC.D1_714  (
    .O(\N_PZ_1145_MC.D1 )
  );
  X_AND2 \N_PZ_1145_MC.D2_PT_0_715  (
    .I0(U11_U3_counterr[3]),
    .I1(\NlwInverterSignal_N_PZ_1145_MC.D2_PT_0/IN1 ),
    .O(\N_PZ_1145_MC.D2_PT_0 )
  );
  X_AND2 \N_PZ_1145_MC.D2_PT_1_716  (
    .I0(U11_U3_counterr[0]),
    .I1(\NlwInverterSignal_N_PZ_1145_MC.D2_PT_1/IN1 ),
    .O(\N_PZ_1145_MC.D2_PT_1 )
  );
  X_AND2 \N_PZ_1145_MC.D2_PT_2_717  (
    .I0(U11_U3_counterr[1]),
    .I1(\NlwInverterSignal_N_PZ_1145_MC.D2_PT_2/IN1 ),
    .O(\N_PZ_1145_MC.D2_PT_2 )
  );
  X_AND3 \N_PZ_1145_MC.D2_PT_3_718  (
    .I0(\NlwInverterSignal_N_PZ_1145_MC.D2_PT_3/IN0 ),
    .I1(\NlwInverterSignal_N_PZ_1145_MC.D2_PT_3/IN1 ),
    .I2(\NlwInverterSignal_N_PZ_1145_MC.D2_PT_3/IN2 ),
    .O(\N_PZ_1145_MC.D2_PT_3 )
  );
  X_OR4 \N_PZ_1145_MC.D2_719  (
    .I0(\N_PZ_1145_MC.D2_PT_0 ),
    .I1(\N_PZ_1145_MC.D2_PT_1 ),
    .I2(\N_PZ_1145_MC.D2_PT_2 ),
    .I3(\N_PZ_1145_MC.D2_PT_3 ),
    .O(\N_PZ_1145_MC.D2 )
  );
  X_BUF N_PZ_1125_720 (
    .I(\N_PZ_1125_MC.Q ),
    .O(N_PZ_1125)
  );
  X_BUF \N_PZ_1125_MC.Q_721  (
    .I(\N_PZ_1125_MC.D ),
    .O(\N_PZ_1125_MC.Q )
  );
  X_XOR2 \N_PZ_1125_MC.D_722  (
    .I0(\N_PZ_1125_MC.D1 ),
    .I1(\N_PZ_1125_MC.D2 ),
    .O(\N_PZ_1125_MC.D )
  );
  X_ZERO \N_PZ_1125_MC.D1_723  (
    .O(\N_PZ_1125_MC.D1 )
  );
  X_AND2 \N_PZ_1125_MC.D2_PT_0_724  (
    .I0(U11_U3_counterr[3]),
    .I1(U11_U3_counterr[3]),
    .O(\N_PZ_1125_MC.D2_PT_0 )
  );
  X_AND4 \N_PZ_1125_MC.D2_PT_1_725  (
    .I0(U11_U3_counterr[0]),
    .I1(U11_U3_counterr[1]),
    .I2(U11_U3_counterr[2]),
    .I3(\NlwInverterSignal_N_PZ_1125_MC.D2_PT_1/IN3 ),
    .O(\N_PZ_1125_MC.D2_PT_1 )
  );
  X_OR2 \N_PZ_1125_MC.D2_726  (
    .I0(\N_PZ_1125_MC.D2_PT_0 ),
    .I1(\N_PZ_1125_MC.D2_PT_1 ),
    .O(\N_PZ_1125_MC.D2 )
  );
  X_BUF \U11_U3_counterr<5>  (
    .I(\U11_U3_counterr<5>_MC.Q ),
    .O(U11_U3_counterr[5])
  );
  X_XOR2 \U11_U3_counterr<5>_MC_tsimcreated_xor__727  (
    .I0(\U11_U3_counterr<5>_MC.D ),
    .I1(\U11_U3_counterr<5>_MC.Q ),
    .O(\U11_U3_counterr<5>_MC_tsimcreated_xor_ )
  );
  X_FF \U11_U3_counterr<5>_MC.REG  (
    .I(\U11_U3_counterr<5>_MC_tsimcreated_xor_ ),
    .CE(Vcc),
    .CLK(\U11_U3_counterr<5>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\U11_U3_counterr<5>_MC.Q )
  );
  X_INV \U11_U3_counterr<5>_MC.REG_tsimcreated_inv_Mclk_II/FCLK_728  (
    .I(\Mclk_II/FCLK ),
    .O(\U11_U3_counterr<5>_MC.REG_tsimcreated_inv_Mclk_II/FCLK )
  );
  X_XOR2 \U11_U3_counterr<5>_MC.D_729  (
    .I0(\U11_U3_counterr<5>_MC.D1 ),
    .I1(\U11_U3_counterr<5>_MC.D2 ),
    .O(\U11_U3_counterr<5>_MC.D )
  );
  X_ZERO \U11_U3_counterr<5>_MC.D1_730  (
    .O(\U11_U3_counterr<5>_MC.D1 )
  );
  X_AND2 \U11_U3_counterr<5>_MC.D2_PT_0_731  (
    .I0(U11_U3_counterr[5]),
    .I1(N_PZ_1071),
    .O(\U11_U3_counterr<5>_MC.D2_PT_0 )
  );
  X_AND4 \U11_U3_counterr<5>_MC.D2_PT_1_732  (
    .I0(U11_U3_counterr[4]),
    .I1(\NlwInverterSignal_U11_U3_counterr<5>_MC.D2_PT_1/IN1 ),
    .I2(\NlwInverterSignal_U11_U3_counterr<5>_MC.D2_PT_1/IN2 ),
    .I3(N_PZ_1125),
    .O(\U11_U3_counterr<5>_MC.D2_PT_1 )
  );
  X_AND5 \U11_U3_counterr<5>_MC.D2_PT_2_733  (
    .I0(\NlwInverterSignal_U11_U3_counterr<5>_MC.D2_PT_2/IN0 ),
    .I1(\NlwInverterSignal_U11_U3_counterr<5>_MC.D2_PT_2/IN1 ),
    .I2(\NlwInverterSignal_U11_U3_counterr<5>_MC.D2_PT_2/IN2 ),
    .I3(\NlwInverterSignal_U11_U3_counterr<5>_MC.D2_PT_2/IN3 ),
    .I4(\NlwInverterSignal_U11_U3_counterr<5>_MC.D2_PT_2/IN4 ),
    .O(\U11_U3_counterr<5>_MC.D2_PT_2 )
  );
  X_AND5 \U11_U3_counterr<5>_MC.D2_PT_3_734  (
    .I0(\NlwInverterSignal_U11_U3_counterr<5>_MC.D2_PT_3/IN0 ),
    .I1(\NlwInverterSignal_U11_U3_counterr<5>_MC.D2_PT_3/IN1 ),
    .I2(\NlwInverterSignal_U11_U3_counterr<5>_MC.D2_PT_3/IN2 ),
    .I3(\NlwInverterSignal_U11_U3_counterr<5>_MC.D2_PT_3/IN3 ),
    .I4(N_PZ_1125),
    .O(\U11_U3_counterr<5>_MC.D2_PT_3 )
  );
  X_OR4 \U11_U3_counterr<5>_MC.D2_735  (
    .I0(\U11_U3_counterr<5>_MC.D2_PT_0 ),
    .I1(\U11_U3_counterr<5>_MC.D2_PT_1 ),
    .I2(\U11_U3_counterr<5>_MC.D2_PT_2 ),
    .I3(\U11_U3_counterr<5>_MC.D2_PT_3 ),
    .O(\U11_U3_counterr<5>_MC.D2 )
  );
  X_BUF \LED1_MC.Q_736  (
    .I(\LED1_MC.Q_tsimrenamed_net_ ),
    .O(\LED1_MC.Q )
  );
  X_BUF \LED1_MC.Q_tsimrenamed_net__737  (
    .I(\LED1_MC.D ),
    .O(\LED1_MC.Q_tsimrenamed_net_ )
  );
  X_XOR2 \LED1_MC.D_738  (
    .I0(\NlwInverterSignal_LED1_MC.D/IN0 ),
    .I1(\LED1_MC.D2 ),
    .O(\LED1_MC.D )
  );
  X_AND2 \LED1_MC.D1_739  (
    .I0(\LightSense_II/UIM ),
    .I1(\NlwInverterSignal_LED1_MC.D1/IN1 ),
    .O(\LED1_MC.D1 )
  );
  X_ZERO \LED1_MC.D2_740  (
    .O(\LED1_MC.D2 )
  );
  X_BUF \U9/MISCr<0>  (
    .I(\U9/MISCr<0>_MC.Q ),
    .O(\U9/MISCr [0])
  );
  X_OR2 \U9/MISCr<0>_MC_tsimcreated_prld__741  (
    .I0(\FOOBAR3__ctinst/7 ),
    .I1(PRLD),
    .O(\U9/MISCr<0>_MC_tsimcreated_prld_ )
  );
  X_FF \U9/MISCr<0>_MC.REG  (
    .I(\U9/MISCr<0>_MC.D ),
    .CE(\FOOBAR1__ctinst/4 ),
    .CLK(\U9/MISCr<0>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(\U9/MISCr<0>_MC_tsimcreated_prld_ ),
    .O(\U9/MISCr<0>_MC.Q )
  );
  X_INV \U9/MISCr<0>_MC.REG_tsimcreated_inv_Mclk_II/FCLK_742  (
    .I(\Mclk_II/FCLK ),
    .O(\U9/MISCr<0>_MC.REG_tsimcreated_inv_Mclk_II/FCLK )
  );
  X_XOR2 \U9/MISCr<0>_MC.D_743  (
    .I0(\U9/MISCr<0>_MC.D1 ),
    .I1(\U9/MISCr<0>_MC.D2 ),
    .O(\U9/MISCr<0>_MC.D )
  );
  X_AND2 \U9/MISCr<0>_MC.D1_744  (
    .I0(\AD<0>_II/UIM ),
    .I1(\AD<0>_II/UIM ),
    .O(\U9/MISCr<0>_MC.D1 )
  );
  X_ZERO \U9/MISCr<0>_MC.D2_745  (
    .O(\U9/MISCr<0>_MC.D2 )
  );
  X_BUF \LED2_MC.Q_746  (
    .I(\LED2_MC.Q_tsimrenamed_net_ ),
    .O(\LED2_MC.Q )
  );
  X_BUF \LED2_MC.Q_tsimrenamed_net__747  (
    .I(\LED2_MC.D ),
    .O(\LED2_MC.Q_tsimrenamed_net_ )
  );
  X_XOR2 \LED2_MC.D_748  (
    .I0(\NlwInverterSignal_LED2_MC.D/IN0 ),
    .I1(\LED2_MC.D2 ),
    .O(\LED2_MC.D )
  );
  X_AND2 \LED2_MC.D1_749  (
    .I0(\LightSense_II/UIM ),
    .I1(\NlwInverterSignal_LED2_MC.D1/IN1 ),
    .O(\LED2_MC.D1 )
  );
  X_ZERO \LED2_MC.D2_750  (
    .O(\LED2_MC.D2 )
  );
  X_BUF \U9/MISCr<1>  (
    .I(\U9/MISCr<1>_MC.Q ),
    .O(\U9/MISCr [1])
  );
  X_OR2 \U9/MISCr<1>_MC_tsimcreated_prld__751  (
    .I0(\FOOBAR3__ctinst/7 ),
    .I1(PRLD),
    .O(\U9/MISCr<1>_MC_tsimcreated_prld_ )
  );
  X_FF \U9/MISCr<1>_MC.REG  (
    .I(\U9/MISCr<1>_MC.D ),
    .CE(\FOOBAR1__ctinst/4 ),
    .CLK(\U9/MISCr<1>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(\U9/MISCr<1>_MC_tsimcreated_prld_ ),
    .O(\U9/MISCr<1>_MC.Q )
  );
  X_INV \U9/MISCr<1>_MC.REG_tsimcreated_inv_Mclk_II/FCLK_752  (
    .I(\Mclk_II/FCLK ),
    .O(\U9/MISCr<1>_MC.REG_tsimcreated_inv_Mclk_II/FCLK )
  );
  X_XOR2 \U9/MISCr<1>_MC.D_753  (
    .I0(\U9/MISCr<1>_MC.D1 ),
    .I1(\U9/MISCr<1>_MC.D2 ),
    .O(\U9/MISCr<1>_MC.D )
  );
  X_AND2 \U9/MISCr<1>_MC.D1_754  (
    .I0(\AD<1>_II/UIM ),
    .I1(\AD<1>_II/UIM ),
    .O(\U9/MISCr<1>_MC.D1 )
  );
  X_ZERO \U9/MISCr<1>_MC.D2_755  (
    .O(\U9/MISCr<1>_MC.D2 )
  );
  X_BUF \LED3_MC.Q_756  (
    .I(\LED3_MC.Q_tsimrenamed_net_ ),
    .O(\LED3_MC.Q )
  );
  X_BUF \LED3_MC.Q_tsimrenamed_net__757  (
    .I(\LED3_MC.D ),
    .O(\LED3_MC.Q_tsimrenamed_net_ )
  );
  X_XOR2 \LED3_MC.D_758  (
    .I0(\NlwInverterSignal_LED3_MC.D/IN0 ),
    .I1(\LED3_MC.D2 ),
    .O(\LED3_MC.D )
  );
  X_AND2 \LED3_MC.D1_759  (
    .I0(\LightSense_II/UIM ),
    .I1(\NlwInverterSignal_LED3_MC.D1/IN1 ),
    .O(\LED3_MC.D1 )
  );
  X_ZERO \LED3_MC.D2_760  (
    .O(\LED3_MC.D2 )
  );
  X_BUF \U9/MISCr<2>  (
    .I(\U9/MISCr<2>_MC.Q ),
    .O(\U9/MISCr [2])
  );
  X_OR2 \U9/MISCr<2>_MC_tsimcreated_prld__761  (
    .I0(\FOOBAR3__ctinst/7 ),
    .I1(PRLD),
    .O(\U9/MISCr<2>_MC_tsimcreated_prld_ )
  );
  X_FF \U9/MISCr<2>_MC.REG  (
    .I(\U9/MISCr<2>_MC.D ),
    .CE(\FOOBAR1__ctinst/4 ),
    .CLK(\U9/MISCr<2>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(\U9/MISCr<2>_MC_tsimcreated_prld_ ),
    .O(\U9/MISCr<2>_MC.Q )
  );
  X_INV \U9/MISCr<2>_MC.REG_tsimcreated_inv_Mclk_II/FCLK_762  (
    .I(\Mclk_II/FCLK ),
    .O(\U9/MISCr<2>_MC.REG_tsimcreated_inv_Mclk_II/FCLK )
  );
  X_XOR2 \U9/MISCr<2>_MC.D_763  (
    .I0(\U9/MISCr<2>_MC.D1 ),
    .I1(\U9/MISCr<2>_MC.D2 ),
    .O(\U9/MISCr<2>_MC.D )
  );
  X_AND2 \U9/MISCr<2>_MC.D1_764  (
    .I0(\AD<2>_II/UIM ),
    .I1(\AD<2>_II/UIM ),
    .O(\U9/MISCr<2>_MC.D1 )
  );
  X_ZERO \U9/MISCr<2>_MC.D2_765  (
    .O(\U9/MISCr<2>_MC.D2 )
  );
  X_BUF \LED4_MC.Q_766  (
    .I(\LED4_MC.Q_tsimrenamed_net_ ),
    .O(\LED4_MC.Q )
  );
  X_BUF \LED4_MC.Q_tsimrenamed_net__767  (
    .I(\LED4_MC.D ),
    .O(\LED4_MC.Q_tsimrenamed_net_ )
  );
  X_XOR2 \LED4_MC.D_768  (
    .I0(\NlwInverterSignal_LED4_MC.D/IN0 ),
    .I1(\LED4_MC.D2 ),
    .O(\LED4_MC.D )
  );
  X_AND2 \LED4_MC.D1_769  (
    .I0(\LightSense_II/UIM ),
    .I1(\NlwInverterSignal_LED4_MC.D1/IN1 ),
    .O(\LED4_MC.D1 )
  );
  X_ZERO \LED4_MC.D2_770  (
    .O(\LED4_MC.D2 )
  );
  X_BUF \U9/MISCr<3>  (
    .I(\U9/MISCr<3>_MC.Q ),
    .O(\U9/MISCr [3])
  );
  X_OR2 \U9/MISCr<3>_MC_tsimcreated_prld__771  (
    .I0(\FOOBAR3__ctinst/7 ),
    .I1(PRLD),
    .O(\U9/MISCr<3>_MC_tsimcreated_prld_ )
  );
  X_FF \U9/MISCr<3>_MC.REG  (
    .I(\U9/MISCr<3>_MC.D ),
    .CE(\FOOBAR1__ctinst/4 ),
    .CLK(\U9/MISCr<3>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(\U9/MISCr<3>_MC_tsimcreated_prld_ ),
    .O(\U9/MISCr<3>_MC.Q )
  );
  X_INV \U9/MISCr<3>_MC.REG_tsimcreated_inv_Mclk_II/FCLK_772  (
    .I(\Mclk_II/FCLK ),
    .O(\U9/MISCr<3>_MC.REG_tsimcreated_inv_Mclk_II/FCLK )
  );
  X_XOR2 \U9/MISCr<3>_MC.D_773  (
    .I0(\U9/MISCr<3>_MC.D1 ),
    .I1(\U9/MISCr<3>_MC.D2 ),
    .O(\U9/MISCr<3>_MC.D )
  );
  X_AND2 \U9/MISCr<3>_MC.D1_774  (
    .I0(\AD<3>_II/UIM ),
    .I1(\AD<3>_II/UIM ),
    .O(\U9/MISCr<3>_MC.D1 )
  );
  X_ZERO \U9/MISCr<3>_MC.D2_775  (
    .O(\U9/MISCr<3>_MC.D2 )
  );
  X_BUF \LED5_MC.Q_776  (
    .I(\LED5_MC.Q_tsimrenamed_net_ ),
    .O(\LED5_MC.Q )
  );
  X_BUF \LED5_MC.Q_tsimrenamed_net__777  (
    .I(\LED5_MC.D ),
    .O(\LED5_MC.Q_tsimrenamed_net_ )
  );
  X_XOR2 \LED5_MC.D_778  (
    .I0(\NlwInverterSignal_LED5_MC.D/IN0 ),
    .I1(\LED5_MC.D2 ),
    .O(\LED5_MC.D )
  );
  X_AND2 \LED5_MC.D1_779  (
    .I0(\LightSense_II/UIM ),
    .I1(\NlwInverterSignal_LED5_MC.D1/IN1 ),
    .O(\LED5_MC.D1 )
  );
  X_ZERO \LED5_MC.D2_780  (
    .O(\LED5_MC.D2 )
  );
  X_BUF \U9/MISCr<4>  (
    .I(\U9/MISCr<4>_MC.Q ),
    .O(\U9/MISCr [4])
  );
  X_OR2 \U9/MISCr<4>_MC_tsimcreated_prld__781  (
    .I0(\FOOBAR3__ctinst/7 ),
    .I1(PRLD),
    .O(\U9/MISCr<4>_MC_tsimcreated_prld_ )
  );
  X_FF \U9/MISCr<4>_MC.REG  (
    .I(\U9/MISCr<4>_MC.D ),
    .CE(\FOOBAR1__ctinst/4 ),
    .CLK(\U9/MISCr<4>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(\U9/MISCr<4>_MC_tsimcreated_prld_ ),
    .O(\U9/MISCr<4>_MC.Q )
  );
  X_INV \U9/MISCr<4>_MC.REG_tsimcreated_inv_Mclk_II/FCLK_782  (
    .I(\Mclk_II/FCLK ),
    .O(\U9/MISCr<4>_MC.REG_tsimcreated_inv_Mclk_II/FCLK )
  );
  X_XOR2 \U9/MISCr<4>_MC.D_783  (
    .I0(\U9/MISCr<4>_MC.D1 ),
    .I1(\U9/MISCr<4>_MC.D2 ),
    .O(\U9/MISCr<4>_MC.D )
  );
  X_AND2 \U9/MISCr<4>_MC.D1_784  (
    .I0(\AD<4>_II/UIM ),
    .I1(\AD<4>_II/UIM ),
    .O(\U9/MISCr<4>_MC.D1 )
  );
  X_ZERO \U9/MISCr<4>_MC.D2_785  (
    .O(\U9/MISCr<4>_MC.D2 )
  );
  X_BUF \MHSI_MC.Q_786  (
    .I(\MHSI_MC.Q_tsimrenamed_net_ ),
    .O(\MHSI_MC.Q )
  );
  X_BUF \MHSI_MC.Q_tsimrenamed_net__787  (
    .I(\MHSI_MC.D ),
    .O(\MHSI_MC.Q_tsimrenamed_net_ )
  );
  X_XOR2 \MHSI_MC.D_788  (
    .I0(\MHSI_MC.D1 ),
    .I1(\MHSI_MC.D2 ),
    .O(\MHSI_MC.D )
  );
  X_AND2 \MHSI_MC.D1_789  (
    .I0(\HSI_II/UIM ),
    .I1(\HSI_II/UIM ),
    .O(\MHSI_MC.D1 )
  );
  X_ZERO \MHSI_MC.D2_790  (
    .O(\MHSI_MC.D2 )
  );
  X_BUF \MTRpwr_MC.Q_791  (
    .I(\MTRpwr_MC.Q_tsimrenamed_net_ ),
    .O(\MTRpwr_MC.Q )
  );
  X_OR2 MTRpwr_MC_tsimcreated_prld__792 (
    .I0(\FOOBAR3__ctinst/7 ),
    .I1(PRLD),
    .O(MTRpwr_MC_tsimcreated_prld_)
  );
  X_FF \MTRpwr_MC.REG  (
    .I(\MTRpwr_MC.D ),
    .CE(\FOOBAR18__ctinst/4 ),
    .CLK(\MTRpwr_MC.REG_tsimcreated_inv_Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(MTRpwr_MC_tsimcreated_prld_),
    .O(\MTRpwr_MC.Q_tsimrenamed_net_ )
  );
  X_INV \MTRpwr_MC.REG_tsimcreated_inv_Mclk_II/FCLK_793  (
    .I(\Mclk_II/FCLK ),
    .O(\MTRpwr_MC.REG_tsimcreated_inv_Mclk_II/FCLK )
  );
  X_XOR2 \MTRpwr_MC.D_794  (
    .I0(\MTRpwr_MC.D1 ),
    .I1(\MTRpwr_MC.D2 ),
    .O(\MTRpwr_MC.D )
  );
  X_AND2 \MTRpwr_MC.D1_795  (
    .I0(\AD<5>_II/UIM ),
    .I1(\AD<5>_II/UIM ),
    .O(\MTRpwr_MC.D1 )
  );
  X_ZERO \MTRpwr_MC.D2_796  (
    .O(\MTRpwr_MC.D2 )
  );
  X_BUF \MTRpwrn_MC.Q_797  (
    .I(\MTRpwrn_MC.Q_tsimrenamed_net_ ),
    .O(\MTRpwrn_MC.Q )
  );
  X_OR2 MTRpwrn_MC_tsimcreated_prld__798 (
    .I0(\FOOBAR2__ctinst/7 ),
    .I1(PRLD),
    .O(MTRpwrn_MC_tsimcreated_prld_)
  );
  X_FF \MTRpwrn_MC.REG  (
    .I(\MTRpwrn_MC.D ),
    .CE(\FOOBAR7__ctinst/4 ),
    .CLK(\MTRpwrn_MC.REG_tsimcreated_inv_Mclk_II/FCLK ),
    .SET(MTRpwrn_MC_tsimcreated_prld_),
    .RST(Gnd),
    .O(\MTRpwrn_MC.Q_tsimrenamed_net_ )
  );
  X_INV \MTRpwrn_MC.REG_tsimcreated_inv_Mclk_II/FCLK_799  (
    .I(\Mclk_II/FCLK ),
    .O(\MTRpwrn_MC.REG_tsimcreated_inv_Mclk_II/FCLK )
  );
  X_XOR2 \MTRpwrn_MC.D_800  (
    .I0(\NlwInverterSignal_MTRpwrn_MC.D/IN0 ),
    .I1(\MTRpwrn_MC.D2 ),
    .O(\MTRpwrn_MC.D )
  );
  X_AND2 \MTRpwrn_MC.D1_801  (
    .I0(\AD<5>_II/UIM ),
    .I1(\AD<5>_II/UIM ),
    .O(\MTRpwrn_MC.D1 )
  );
  X_ZERO \MTRpwrn_MC.D2_802  (
    .O(\MTRpwrn_MC.D2 )
  );
  X_BUF \MTXI_MC.Q_803  (
    .I(\MTXI_MC.Q_tsimrenamed_net_ ),
    .O(\MTXI_MC.Q )
  );
  X_BUF \MTXI_MC.Q_tsimrenamed_net__804  (
    .I(\MTXI_MC.D ),
    .O(\MTXI_MC.Q_tsimrenamed_net_ )
  );
  X_XOR2 \MTXI_MC.D_805  (
    .I0(\MTXI_MC.D1 ),
    .I1(\MTXI_MC.D2 ),
    .O(\MTXI_MC.D )
  );
  X_AND2 \MTXI_MC.D1_806  (
    .I0(\TXI_II/UIM ),
    .I1(\TXI_II/UIM ),
    .O(\MTXI_MC.D1 )
  );
  X_ZERO \MTXI_MC.D2_807  (
    .O(\MTXI_MC.D2 )
  );
  X_BUF \PAH0_MC.Q_808  (
    .I(\PAH0_MC.Q_tsimrenamed_net_ ),
    .O(\PAH0_MC.Q )
  );
  X_BUF \PAH0_MC.UIM_809  (
    .I(\PAH0_MC.Q_tsimrenamed_net_ ),
    .O(\PAH0_MC.UIM )
  );
  X_BUF \PAH0_MC.Q_tsimrenamed_net__810  (
    .I(\PAH0_MC.D ),
    .O(\PAH0_MC.Q_tsimrenamed_net_ )
  );
  X_XOR2 \PAH0_MC.D_811  (
    .I0(\PAH0_MC.D1 ),
    .I1(\PAH0_MC.D2 ),
    .O(\PAH0_MC.D )
  );
  X_AND4 \PAH0_MC.D1_812  (
    .I0(\NlwInverterSignal_PAH0_MC.D1/IN0 ),
    .I1(\NlwInverterSignal_PAH0_MC.D1/IN1 ),
    .I2(\PWM1_II/UIM ),
    .I3(\NlwInverterSignal_PAH0_MC.D1/IN3 ),
    .O(\PAH0_MC.D1 )
  );
  X_ZERO \PAH0_MC.D2_813  (
    .O(\PAH0_MC.D2 )
  );
  X_BUF NET3248_814 (
    .I(\NET3248_MC.Q ),
    .O(NET3248)
  );
  X_FF \NET3248_MC.REG  (
    .I(\NET3248_MC.D ),
    .CE(Vcc),
    .CLK(\NET3248_MC.REG_tsimcreated_inv_Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\NET3248_MC.Q )
  );
  X_INV \NET3248_MC.REG_tsimcreated_inv_Mclk_II/FCLK_815  (
    .I(\Mclk_II/FCLK ),
    .O(\NET3248_MC.REG_tsimcreated_inv_Mclk_II/FCLK )
  );
  X_XOR2 \NET3248_MC.D_816  (
    .I0(\NET3248_MC.D1 ),
    .I1(\NET3248_MC.D2 ),
    .O(\NET3248_MC.D )
  );
  X_ZERO \NET3248_MC.D1_817  (
    .O(\NET3248_MC.D1 )
  );
  X_AND3 \NET3248_MC.D2_PT_0_818  (
    .I0(\NlwInverterSignal_NET3248_MC.D2_PT_0/IN0 ),
    .I1(\MSPReset_II/UIM ),
    .I2(NET3248),
    .O(\NET3248_MC.D2_PT_0 )
  );
  X_AND3 \NET3248_MC.D2_PT_1_819  (
    .I0(\DIR0_II/UIM ),
    .I1(\MSPReset_II/UIM ),
    .I2(\NlwInverterSignal_NET3248_MC.D2_PT_1/IN2 ),
    .O(\NET3248_MC.D2_PT_1 )
  );
  X_AND3 \NET3248_MC.D2_PT_2_820  (
    .I0(\NlwInverterSignal_NET3248_MC.D2_PT_2/IN0 ),
    .I1(\MSPReset_II/UIM ),
    .I2(\NlwInverterSignal_NET3248_MC.D2_PT_2/IN2 ),
    .O(\NET3248_MC.D2_PT_2 )
  );
  X_OR3 \NET3248_MC.D2_821  (
    .I0(\NET3248_MC.D2_PT_0 ),
    .I1(\NET3248_MC.D2_PT_1 ),
    .I2(\NET3248_MC.D2_PT_2 ),
    .O(\NET3248_MC.D2 )
  );
  X_BUF \PAH1_MC.Q_822  (
    .I(\PAH1_MC.Q_tsimrenamed_net_ ),
    .O(\PAH1_MC.Q )
  );
  X_BUF \PAH1_MC.UIM_823  (
    .I(\PAH1_MC.Q_tsimrenamed_net_ ),
    .O(\PAH1_MC.UIM )
  );
  X_BUF \PAH1_MC.Q_tsimrenamed_net__824  (
    .I(\PAH1_MC.D ),
    .O(\PAH1_MC.Q_tsimrenamed_net_ )
  );
  X_XOR2 \PAH1_MC.D_825  (
    .I0(\PAH1_MC.D1 ),
    .I1(\PAH1_MC.D2 ),
    .O(\PAH1_MC.D )
  );
  X_AND4 \PAH1_MC.D1_826  (
    .I0(\NlwInverterSignal_PAH1_MC.D1/IN0 ),
    .I1(\NlwInverterSignal_PAH1_MC.D1/IN1 ),
    .I2(\PWM2_II/UIM ),
    .I3(\NlwInverterSignal_PAH1_MC.D1/IN3 ),
    .O(\PAH1_MC.D1 )
  );
  X_ZERO \PAH1_MC.D2_827  (
    .O(\PAH1_MC.D2 )
  );
  X_BUF NET3253_828 (
    .I(\NET3253_MC.Q ),
    .O(NET3253)
  );
  X_FF \NET3253_MC.REG  (
    .I(\NET3253_MC.D ),
    .CE(Vcc),
    .CLK(\NET3253_MC.REG_tsimcreated_inv_Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\NET3253_MC.Q )
  );
  X_INV \NET3253_MC.REG_tsimcreated_inv_Mclk_II/FCLK_829  (
    .I(\Mclk_II/FCLK ),
    .O(\NET3253_MC.REG_tsimcreated_inv_Mclk_II/FCLK )
  );
  X_XOR2 \NET3253_MC.D_830  (
    .I0(\NET3253_MC.D1 ),
    .I1(\NET3253_MC.D2 ),
    .O(\NET3253_MC.D )
  );
  X_ZERO \NET3253_MC.D1_831  (
    .O(\NET3253_MC.D1 )
  );
  X_AND3 \NET3253_MC.D2_PT_0_832  (
    .I0(\NlwInverterSignal_NET3253_MC.D2_PT_0/IN0 ),
    .I1(\MSPReset_II/UIM ),
    .I2(NET3253),
    .O(\NET3253_MC.D2_PT_0 )
  );
  X_AND3 \NET3253_MC.D2_PT_1_833  (
    .I0(\DIR1_II/UIM ),
    .I1(\MSPReset_II/UIM ),
    .I2(\NlwInverterSignal_NET3253_MC.D2_PT_1/IN2 ),
    .O(\NET3253_MC.D2_PT_1 )
  );
  X_AND3 \NET3253_MC.D2_PT_2_834  (
    .I0(\NlwInverterSignal_NET3253_MC.D2_PT_2/IN0 ),
    .I1(\MSPReset_II/UIM ),
    .I2(\NlwInverterSignal_NET3253_MC.D2_PT_2/IN2 ),
    .O(\NET3253_MC.D2_PT_2 )
  );
  X_OR3 \NET3253_MC.D2_835  (
    .I0(\NET3253_MC.D2_PT_0 ),
    .I1(\NET3253_MC.D2_PT_1 ),
    .I2(\NET3253_MC.D2_PT_2 ),
    .O(\NET3253_MC.D2 )
  );
  X_BUF \PAL0_MC.Q_836  (
    .I(\PAL0_MC.Q_tsimrenamed_net_ ),
    .O(\PAL0_MC.Q )
  );
  X_BUF \PAL0_MC.Q_tsimrenamed_net__837  (
    .I(\PAL0_MC.D ),
    .O(\PAL0_MC.Q_tsimrenamed_net_ )
  );
  X_XOR2 \PAL0_MC.D_838  (
    .I0(\PAL0_MC.D1 ),
    .I1(\PAL0_MC.D2 ),
    .O(\PAL0_MC.D )
  );
  X_ZERO \PAL0_MC.D1_839  (
    .O(\PAL0_MC.D1 )
  );
  X_AND2 \PAL0_MC.D2_PT_0_840  (
    .I0(\PAH0_MC.UIM ),
    .I1(\PAH0_MC.UIM ),
    .O(\PAL0_MC.D2_PT_0 )
  );
  X_AND4 \PAL0_MC.D2_PT_1_841  (
    .I0(\NlwInverterSignal_PAL0_MC.D2_PT_1/IN0 ),
    .I1(\DIR0_II/UIM ),
    .I2(\NlwInverterSignal_PAL0_MC.D2_PT_1/IN2 ),
    .I3(\NlwInverterSignal_PAL0_MC.D2_PT_1/IN3 ),
    .O(\PAL0_MC.D2_PT_1 )
  );
  X_OR2 \PAL0_MC.D2_842  (
    .I0(\PAL0_MC.D2_PT_0 ),
    .I1(\PAL0_MC.D2_PT_1 ),
    .O(\PAL0_MC.D2 )
  );
  X_BUF \PAL1_MC.Q_843  (
    .I(\PAL1_MC.Q_tsimrenamed_net_ ),
    .O(\PAL1_MC.Q )
  );
  X_BUF \PAL1_MC.Q_tsimrenamed_net__844  (
    .I(\PAL1_MC.D ),
    .O(\PAL1_MC.Q_tsimrenamed_net_ )
  );
  X_XOR2 \PAL1_MC.D_845  (
    .I0(\PAL1_MC.D1 ),
    .I1(\PAL1_MC.D2 ),
    .O(\PAL1_MC.D )
  );
  X_ZERO \PAL1_MC.D1_846  (
    .O(\PAL1_MC.D1 )
  );
  X_AND2 \PAL1_MC.D2_PT_0_847  (
    .I0(\PAH1_MC.UIM ),
    .I1(\PAH1_MC.UIM ),
    .O(\PAL1_MC.D2_PT_0 )
  );
  X_AND4 \PAL1_MC.D2_PT_1_848  (
    .I0(\NlwInverterSignal_PAL1_MC.D2_PT_1/IN0 ),
    .I1(\DIR1_II/UIM ),
    .I2(\NlwInverterSignal_PAL1_MC.D2_PT_1/IN2 ),
    .I3(\NlwInverterSignal_PAL1_MC.D2_PT_1/IN3 ),
    .O(\PAL1_MC.D2_PT_1 )
  );
  X_OR2 \PAL1_MC.D2_849  (
    .I0(\PAL1_MC.D2_PT_0 ),
    .I1(\PAL1_MC.D2_PT_1 ),
    .O(\PAL1_MC.D2 )
  );
  X_BUF \PBH0_MC.Q_850  (
    .I(\PBH0_MC.Q_tsimrenamed_net_ ),
    .O(\PBH0_MC.Q )
  );
  X_BUF \PBH0_MC.UIM_851  (
    .I(\PBH0_MC.Q_tsimrenamed_net_ ),
    .O(\PBH0_MC.UIM )
  );
  X_BUF \PBH0_MC.Q_tsimrenamed_net__852  (
    .I(\PBH0_MC.D ),
    .O(\PBH0_MC.Q_tsimrenamed_net_ )
  );
  X_XOR2 \PBH0_MC.D_853  (
    .I0(\PBH0_MC.D1 ),
    .I1(\PBH0_MC.D2 ),
    .O(\PBH0_MC.D )
  );
  X_AND4 \PBH0_MC.D1_854  (
    .I0(\NlwInverterSignal_PBH0_MC.D1/IN0 ),
    .I1(\DIR0_II/UIM ),
    .I2(\PWM1_II/UIM ),
    .I3(\NlwInverterSignal_PBH0_MC.D1/IN3 ),
    .O(\PBH0_MC.D1 )
  );
  X_ZERO \PBH0_MC.D2_855  (
    .O(\PBH0_MC.D2 )
  );
  X_BUF \PBH1_MC.Q_856  (
    .I(\PBH1_MC.Q_tsimrenamed_net_ ),
    .O(\PBH1_MC.Q )
  );
  X_BUF \PBH1_MC.UIM_857  (
    .I(\PBH1_MC.Q_tsimrenamed_net_ ),
    .O(\PBH1_MC.UIM )
  );
  X_BUF \PBH1_MC.Q_tsimrenamed_net__858  (
    .I(\PBH1_MC.D ),
    .O(\PBH1_MC.Q_tsimrenamed_net_ )
  );
  X_XOR2 \PBH1_MC.D_859  (
    .I0(\PBH1_MC.D1 ),
    .I1(\PBH1_MC.D2 ),
    .O(\PBH1_MC.D )
  );
  X_AND4 \PBH1_MC.D1_860  (
    .I0(\NlwInverterSignal_PBH1_MC.D1/IN0 ),
    .I1(\DIR1_II/UIM ),
    .I2(\PWM2_II/UIM ),
    .I3(\NlwInverterSignal_PBH1_MC.D1/IN3 ),
    .O(\PBH1_MC.D1 )
  );
  X_ZERO \PBH1_MC.D2_861  (
    .O(\PBH1_MC.D2 )
  );
  X_BUF \PBL0_MC.Q_862  (
    .I(\PBL0_MC.Q_tsimrenamed_net_ ),
    .O(\PBL0_MC.Q )
  );
  X_BUF \PBL0_MC.Q_tsimrenamed_net__863  (
    .I(\PBL0_MC.D ),
    .O(\PBL0_MC.Q_tsimrenamed_net_ )
  );
  X_XOR2 \PBL0_MC.D_864  (
    .I0(\PBL0_MC.D1 ),
    .I1(\PBL0_MC.D2 ),
    .O(\PBL0_MC.D )
  );
  X_ZERO \PBL0_MC.D1_865  (
    .O(\PBL0_MC.D1 )
  );
  X_AND2 \PBL0_MC.D2_PT_0_866  (
    .I0(\PBH0_MC.UIM ),
    .I1(\PBH0_MC.UIM ),
    .O(\PBL0_MC.D2_PT_0 )
  );
  X_AND4 \PBL0_MC.D2_PT_1_867  (
    .I0(\NlwInverterSignal_PBL0_MC.D2_PT_1/IN0 ),
    .I1(\NlwInverterSignal_PBL0_MC.D2_PT_1/IN1 ),
    .I2(\NlwInverterSignal_PBL0_MC.D2_PT_1/IN2 ),
    .I3(\NlwInverterSignal_PBL0_MC.D2_PT_1/IN3 ),
    .O(\PBL0_MC.D2_PT_1 )
  );
  X_OR2 \PBL0_MC.D2_868  (
    .I0(\PBL0_MC.D2_PT_0 ),
    .I1(\PBL0_MC.D2_PT_1 ),
    .O(\PBL0_MC.D2 )
  );
  X_BUF \PBL1_MC.Q_869  (
    .I(\PBL1_MC.Q_tsimrenamed_net_ ),
    .O(\PBL1_MC.Q )
  );
  X_BUF \PBL1_MC.Q_tsimrenamed_net__870  (
    .I(\PBL1_MC.D ),
    .O(\PBL1_MC.Q_tsimrenamed_net_ )
  );
  X_XOR2 \PBL1_MC.D_871  (
    .I0(\PBL1_MC.D1 ),
    .I1(\PBL1_MC.D2 ),
    .O(\PBL1_MC.D )
  );
  X_ZERO \PBL1_MC.D1_872  (
    .O(\PBL1_MC.D1 )
  );
  X_AND2 \PBL1_MC.D2_PT_0_873  (
    .I0(\PBH1_MC.UIM ),
    .I1(\PBH1_MC.UIM ),
    .O(\PBL1_MC.D2_PT_0 )
  );
  X_AND4 \PBL1_MC.D2_PT_1_874  (
    .I0(\NlwInverterSignal_PBL1_MC.D2_PT_1/IN0 ),
    .I1(\NlwInverterSignal_PBL1_MC.D2_PT_1/IN1 ),
    .I2(\NlwInverterSignal_PBL1_MC.D2_PT_1/IN2 ),
    .I3(\NlwInverterSignal_PBL1_MC.D2_PT_1/IN3 ),
    .O(\PBL1_MC.D2_PT_1 )
  );
  X_OR2 \PBL1_MC.D2_875  (
    .I0(\PBL1_MC.D2_PT_0 ),
    .I1(\PBL1_MC.D2_PT_1 ),
    .O(\PBL1_MC.D2 )
  );
  X_BUF \PresEn_MC.Q_876  (
    .I(\PresEn_MC.Q_tsimrenamed_net_ ),
    .O(\PresEn_MC.Q )
  );
  X_OR2 PresEn_MC_tsimcreated_prld__877 (
    .I0(\FOOBAR2__ctinst/7 ),
    .I1(PRLD),
    .O(PresEn_MC_tsimcreated_prld_)
  );
  X_FF \PresEn_MC.REG  (
    .I(\PresEn_MC.D ),
    .CE(\FOOBAR19__ctinst/4 ),
    .CLK(\PresEn_MC.REG_tsimcreated_inv_Mclk_II/FCLK ),
    .SET(PresEn_MC_tsimcreated_prld_),
    .RST(Gnd),
    .O(\PresEn_MC.Q_tsimrenamed_net_ )
  );
  X_INV \PresEn_MC.REG_tsimcreated_inv_Mclk_II/FCLK_878  (
    .I(\Mclk_II/FCLK ),
    .O(\PresEn_MC.REG_tsimcreated_inv_Mclk_II/FCLK )
  );
  X_XOR2 \PresEn_MC.D_879  (
    .I0(\NlwInverterSignal_PresEn_MC.D/IN0 ),
    .I1(\PresEn_MC.D2 ),
    .O(\PresEn_MC.D )
  );
  X_AND2 \PresEn_MC.D1_880  (
    .I0(\AD<0>_II/UIM ),
    .I1(\AD<0>_II/UIM ),
    .O(\PresEn_MC.D1 )
  );
  X_ZERO \PresEn_MC.D2_881  (
    .O(\PresEn_MC.D2 )
  );
  X_BUF DCORSENSORw_882 (
    .I(\DCORSENSORw_MC.Q ),
    .O(DCORSENSORw)
  );
  X_BUF \DCORSENSORw_MC.Q_883  (
    .I(\DCORSENSORw_MC.D ),
    .O(\DCORSENSORw_MC.Q )
  );
  X_XOR2 \DCORSENSORw_MC.D_884  (
    .I0(\DCORSENSORw_MC.D1 ),
    .I1(\DCORSENSORw_MC.D2 ),
    .O(\DCORSENSORw_MC.D )
  );
  X_AND16 \DCORSENSORw_MC.D1_885  (
    .I0(\NlwInverterSignal_DCORSENSORw_MC.D1/IN0 ),
    .I1(\RD_II/UIM ),
    .I2(\NlwInverterSignal_DCORSENSORw_MC.D1/IN2 ),
    .I3(\NlwInverterSignal_DCORSENSORw_MC.D1/IN3 ),
    .I4(\NlwInverterSignal_DCORSENSORw_MC.D1/IN4 ),
    .I5(\NlwInverterSignal_DCORSENSORw_MC.D1/IN5 ),
    .I6(\NlwInverterSignal_DCORSENSORw_MC.D1/IN6 ),
    .I7(U2_ADDR_reg[3]),
    .I8(\NlwInverterSignal_DCORSENSORw_MC.D1/IN8 ),
    .I9(U2_ADDR_reg[2]),
    .I10(Vcc),
    .I11(Vcc),
    .I12(Vcc),
    .I13(Vcc),
    .I14(Vcc),
    .I15(Vcc),
    .O(\DCORSENSORw_MC.D1 )
  );
  X_ZERO \DCORSENSORw_MC.D2_886  (
    .O(\DCORSENSORw_MC.D2 )
  );
  X_BUF \PresSlct_MC.Q_887  (
    .I(\PresSlct_MC.Q_tsimrenamed_net_ ),
    .O(\PresSlct_MC.Q )
  );
  X_OR2 PresSlct_MC_tsimcreated_prld__888 (
    .I0(\FOOBAR3__ctinst/7 ),
    .I1(PRLD),
    .O(PresSlct_MC_tsimcreated_prld_)
  );
  X_FF \PresSlct_MC.REG  (
    .I(\PresSlct_MC.D ),
    .CE(\FOOBAR19__ctinst/4 ),
    .CLK(\PresSlct_MC.REG_tsimcreated_inv_Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PresSlct_MC_tsimcreated_prld_),
    .O(\PresSlct_MC.Q_tsimrenamed_net_ )
  );
  X_INV \PresSlct_MC.REG_tsimcreated_inv_Mclk_II/FCLK_889  (
    .I(\Mclk_II/FCLK ),
    .O(\PresSlct_MC.REG_tsimcreated_inv_Mclk_II/FCLK )
  );
  X_XOR2 \PresSlct_MC.D_890  (
    .I0(\PresSlct_MC.D1 ),
    .I1(\PresSlct_MC.D2 ),
    .O(\PresSlct_MC.D )
  );
  X_AND2 \PresSlct_MC.D1_891  (
    .I0(\AD<1>_II/UIM ),
    .I1(\AD<1>_II/UIM ),
    .O(\PresSlct_MC.D1 )
  );
  X_ZERO \PresSlct_MC.D2_892  (
    .O(\PresSlct_MC.D2 )
  );
  X_BUF \SCLout_MC.Q_893  (
    .I(\SCLout_MC.Q_tsimrenamed_net_ ),
    .O(\SCLout_MC.Q )
  );
  X_BUF \SCLout_MC.Q_tsimrenamed_net__894  (
    .I(\SCLout_MC.D ),
    .O(\SCLout_MC.Q_tsimrenamed_net_ )
  );
  X_XOR2 \SCLout_MC.D_895  (
    .I0(\SCLout_MC.D1 ),
    .I1(\SCLout_MC.D2 ),
    .O(\SCLout_MC.D )
  );
  X_AND2 \SCLout_MC.D1_896  (
    .I0(\SCL_II/UIM ),
    .I1(\SCL_II/UIM ),
    .O(\SCLout_MC.D1 )
  );
  X_ZERO \SCLout_MC.D2_897  (
    .O(\SCLout_MC.D2 )
  );
  X_BUF \TP10_MC.Q_898  (
    .I(\TP10_MC.Q_tsimrenamed_net_ ),
    .O(\TP10_MC.Q )
  );
  X_BUF \TP10_MC.Q_tsimrenamed_net__899  (
    .I(\TP10_MC.D ),
    .O(\TP10_MC.Q_tsimrenamed_net_ )
  );
  X_XOR2 \TP10_MC.D_900  (
    .I0(\TP10_MC.D1 ),
    .I1(\TP10_MC.D2 ),
    .O(\TP10_MC.D )
  );
  X_AND2 \TP10_MC.D1_901  (
    .I0(\SCLreset_II/UIM ),
    .I1(\SCLreset_II/UIM ),
    .O(\TP10_MC.D1 )
  );
  X_ZERO \TP10_MC.D2_902  (
    .O(\TP10_MC.D2 )
  );
  X_BUF \TP11_MC.Q_903  (
    .I(\TP11_MC.Q_tsimrenamed_net_ ),
    .O(\TP11_MC.Q )
  );
  X_BUF \TP11_MC.Q_tsimrenamed_net__904  (
    .I(\TP11_MC.D ),
    .O(\TP11_MC.Q_tsimrenamed_net_ )
  );
  X_XOR2 \TP11_MC.D_905  (
    .I0(\NlwInverterSignal_TP11_MC.D/IN0 ),
    .I1(\TP11_MC.D2 ),
    .O(\TP11_MC.D )
  );
  X_AND2 \TP11_MC.D1_906  (
    .I0(\MSPReset_II/UIM ),
    .I1(\MSPReset_II/UIM ),
    .O(\TP11_MC.D1 )
  );
  X_ZERO \TP11_MC.D2_907  (
    .O(\TP11_MC.D2 )
  );
  X_BUF \TmpEn_MC.Q_908  (
    .I(\TmpEn_MC.Q_tsimrenamed_net_ ),
    .O(\TmpEn_MC.Q )
  );
  X_OR2 TmpEn_MC_tsimcreated_prld__909 (
    .I0(\FOOBAR2__ctinst/7 ),
    .I1(PRLD),
    .O(TmpEn_MC_tsimcreated_prld_)
  );
  X_FF \TmpEn_MC.REG  (
    .I(\TmpEn_MC.D ),
    .CE(\FOOBAR19__ctinst/4 ),
    .CLK(\TmpEn_MC.REG_tsimcreated_inv_Mclk_II/FCLK ),
    .SET(TmpEn_MC_tsimcreated_prld_),
    .RST(Gnd),
    .O(\TmpEn_MC.Q_tsimrenamed_net_ )
  );
  X_INV \TmpEn_MC.REG_tsimcreated_inv_Mclk_II/FCLK_910  (
    .I(\Mclk_II/FCLK ),
    .O(\TmpEn_MC.REG_tsimcreated_inv_Mclk_II/FCLK )
  );
  X_XOR2 \TmpEn_MC.D_911  (
    .I0(\NlwInverterSignal_TmpEn_MC.D/IN0 ),
    .I1(\TmpEn_MC.D2 ),
    .O(\TmpEn_MC.D )
  );
  X_AND2 \TmpEn_MC.D1_912  (
    .I0(\AD<2>_II/UIM ),
    .I1(\AD<2>_II/UIM ),
    .O(\TmpEn_MC.D1 )
  );
  X_ZERO \TmpEn_MC.D2_913  (
    .O(\TmpEn_MC.D2 )
  );
  X_BUF \TmpSlct_MC.Q_914  (
    .I(\TmpSlct_MC.Q_tsimrenamed_net_ ),
    .O(\TmpSlct_MC.Q )
  );
  X_OR2 TmpSlct_MC_tsimcreated_prld__915 (
    .I0(\FOOBAR3__ctinst/7 ),
    .I1(PRLD),
    .O(TmpSlct_MC_tsimcreated_prld_)
  );
  X_FF \TmpSlct_MC.REG  (
    .I(\TmpSlct_MC.D ),
    .CE(\FOOBAR19__ctinst/4 ),
    .CLK(\TmpSlct_MC.REG_tsimcreated_inv_Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(TmpSlct_MC_tsimcreated_prld_),
    .O(\TmpSlct_MC.Q_tsimrenamed_net_ )
  );
  X_INV \TmpSlct_MC.REG_tsimcreated_inv_Mclk_II/FCLK_916  (
    .I(\Mclk_II/FCLK ),
    .O(\TmpSlct_MC.REG_tsimcreated_inv_Mclk_II/FCLK )
  );
  X_XOR2 \TmpSlct_MC.D_917  (
    .I0(\TmpSlct_MC.D1 ),
    .I1(\TmpSlct_MC.D2 ),
    .O(\TmpSlct_MC.D )
  );
  X_AND2 \TmpSlct_MC.D1_918  (
    .I0(\AD<3>_II/UIM ),
    .I1(\AD<3>_II/UIM ),
    .O(\TmpSlct_MC.D1 )
  );
  X_ZERO \TmpSlct_MC.D2_919  (
    .O(\TmpSlct_MC.D2 )
  );
  X_BUF \U4/orFLGs_920  (
    .I(\U4/orFLGs_MC.Q ),
    .O(\U4/orFLGs )
  );
  X_BUF \U4/orFLGs_MC.Q_921  (
    .I(\U4/orFLGs_MC.D ),
    .O(\U4/orFLGs_MC.Q )
  );
  X_XOR2 \U4/orFLGs_MC.D_922  (
    .I0(\U4/orFLGs_MC.D1 ),
    .I1(\U4/orFLGs_MC.D2 ),
    .O(\U4/orFLGs_MC.D )
  );
  X_AND8 \U4/orFLGs_MC.D1_923  (
    .I0(\Home15FLG_II/UIM ),
    .I1(\Home133FLG_II/UIM ),
    .I2(\Home05FLG_II/UIM ),
    .I3(\Home033FLG_II/UIM ),
    .I4(\Enc15FLG_II/UIM ),
    .I5(\Enc133FLG_II/UIM ),
    .I6(\Enc05FLG_II/UIM ),
    .I7(\Enc033FLG_II/UIM ),
    .O(\U4/orFLGs_MC.D1 )
  );
  X_ZERO \U4/orFLGs_MC.D2_924  (
    .O(\U4/orFLGs_MC.D2 )
  );
  X_BUF DCORI2CCNTr_925 (
    .I(\DCORI2CCNTr_MC.Q ),
    .O(DCORI2CCNTr)
  );
  X_BUF \DCORI2CCNTr_MC.Q_926  (
    .I(\DCORI2CCNTr_MC.D ),
    .O(\DCORI2CCNTr_MC.Q )
  );
  X_XOR2 \DCORI2CCNTr_MC.D_927  (
    .I0(\DCORI2CCNTr_MC.D1 ),
    .I1(\DCORI2CCNTr_MC.D2 ),
    .O(\DCORI2CCNTr_MC.D )
  );
  X_AND16 \DCORI2CCNTr_MC.D1_928  (
    .I0(\WR_II/UIM ),
    .I1(\NlwInverterSignal_DCORI2CCNTr_MC.D1/IN1 ),
    .I2(\NlwInverterSignal_DCORI2CCNTr_MC.D1/IN2 ),
    .I3(\NlwInverterSignal_DCORI2CCNTr_MC.D1/IN3 ),
    .I4(\NlwInverterSignal_DCORI2CCNTr_MC.D1/IN4 ),
    .I5(\NlwInverterSignal_DCORI2CCNTr_MC.D1/IN5 ),
    .I6(\NlwInverterSignal_DCORI2CCNTr_MC.D1/IN6 ),
    .I7(\NlwInverterSignal_DCORI2CCNTr_MC.D1/IN7 ),
    .I8(\NlwInverterSignal_DCORI2CCNTr_MC.D1/IN8 ),
    .I9(\NlwInverterSignal_DCORI2CCNTr_MC.D1/IN9 ),
    .I10(Vcc),
    .I11(Vcc),
    .I12(Vcc),
    .I13(Vcc),
    .I14(Vcc),
    .I15(Vcc),
    .O(\DCORI2CCNTr_MC.D1 )
  );
  X_ZERO \DCORI2CCNTr_MC.D2_929  (
    .O(\DCORI2CCNTr_MC.D2 )
  );
  X_BUF \outDATA<0>\$WA0.UIM_930  (
    .I(\outDATA<0>\$WA0.UIM_MC.Q ),
    .O(\outDATA<0>\$WA0.UIM )
  );
  X_BUF \outDATA<0>\$WA0.UIM_MC.Q_931  (
    .I(\outDATA<0>\$WA0.UIM_MC.D ),
    .O(\outDATA<0>\$WA0.UIM_MC.Q )
  );
  X_XOR2 \outDATA<0>\$WA0.UIM_MC.D_932  (
    .I0(\outDATA<0>\$WA0.UIM_MC.D1 ),
    .I1(\outDATA<0>\$WA0.UIM_MC.D2 ),
    .O(\outDATA<0>\$WA0.UIM_MC.D )
  );
  X_AND2 \outDATA<0>\$WA0.UIM_MC.D1_933  (
    .I0(U11_U3_counterr[0]),
    .I1(U11_U3_counterr[0]),
    .O(\outDATA<0>\$WA0.UIM_MC.D1 )
  );
  X_ZERO \outDATA<0>\$WA0.UIM_MC.D2_934  (
    .O(\outDATA<0>\$WA0.UIM_MC.D2 )
  );
  X_BUF DCORCONFIGr_935 (
    .I(\DCORCONFIGr_MC.Q ),
    .O(DCORCONFIGr)
  );
  X_BUF \DCORCONFIGr_MC.Q_936  (
    .I(\DCORCONFIGr_MC.D ),
    .O(\DCORCONFIGr_MC.Q )
  );
  X_XOR2 \DCORCONFIGr_MC.D_937  (
    .I0(\DCORCONFIGr_MC.D1 ),
    .I1(\DCORCONFIGr_MC.D2 ),
    .O(\DCORCONFIGr_MC.D )
  );
  X_AND16 \DCORCONFIGr_MC.D1_938  (
    .I0(\WR_II/UIM ),
    .I1(\NlwInverterSignal_DCORCONFIGr_MC.D1/IN1 ),
    .I2(U2_ADDR_reg[0]),
    .I3(\NlwInverterSignal_DCORCONFIGr_MC.D1/IN3 ),
    .I4(\NlwInverterSignal_DCORCONFIGr_MC.D1/IN4 ),
    .I5(\NlwInverterSignal_DCORCONFIGr_MC.D1/IN5 ),
    .I6(\NlwInverterSignal_DCORCONFIGr_MC.D1/IN6 ),
    .I7(U2_ADDR_reg[3]),
    .I8(U2_ADDR_reg[1]),
    .I9(U2_ADDR_reg[2]),
    .I10(Vcc),
    .I11(Vcc),
    .I12(Vcc),
    .I13(Vcc),
    .I14(Vcc),
    .I15(Vcc),
    .O(\DCORCONFIGr_MC.D1 )
  );
  X_ZERO \DCORCONFIGr_MC.D2_939  (
    .O(\DCORCONFIGr_MC.D2 )
  );
  X_BUF \outDATA<0>\$WA1.UIM_940  (
    .I(\outDATA<0>\$WA1.UIM_MC.Q ),
    .O(\outDATA<0>\$WA1.UIM )
  );
  X_BUF \outDATA<0>\$WA1.UIM_MC.Q_941  (
    .I(\outDATA<0>\$WA1.UIM_MC.D ),
    .O(\outDATA<0>\$WA1.UIM_MC.Q )
  );
  X_XOR2 \outDATA<0>\$WA1.UIM_MC.D_942  (
    .I0(\outDATA<0>\$WA1.UIM_MC.D1 ),
    .I1(\outDATA<0>\$WA1.UIM_MC.D2 ),
    .O(\outDATA<0>\$WA1.UIM_MC.D )
  );
  X_AND2 \outDATA<0>\$WA1.UIM_MC.D1_943  (
    .I0(\I2CS<0>_II/UIM ),
    .I1(\I2CS<0>_II/UIM ),
    .O(\outDATA<0>\$WA1.UIM_MC.D1 )
  );
  X_ZERO \outDATA<0>\$WA1.UIM_MC.D2_944  (
    .O(\outDATA<0>\$WA1.UIM_MC.D2 )
  );
  X_BUF DCORLIMITSr_945 (
    .I(\DCORLIMITSr_MC.Q ),
    .O(DCORLIMITSr)
  );
  X_BUF \DCORLIMITSr_MC.Q_946  (
    .I(\DCORLIMITSr_MC.D ),
    .O(\DCORLIMITSr_MC.Q )
  );
  X_XOR2 \DCORLIMITSr_MC.D_947  (
    .I0(\DCORLIMITSr_MC.D1 ),
    .I1(\DCORLIMITSr_MC.D2 ),
    .O(\DCORLIMITSr_MC.D )
  );
  X_AND16 \DCORLIMITSr_MC.D1_948  (
    .I0(\WR_II/UIM ),
    .I1(\NlwInverterSignal_DCORLIMITSr_MC.D1/IN1 ),
    .I2(\NlwInverterSignal_DCORLIMITSr_MC.D1/IN2 ),
    .I3(\NlwInverterSignal_DCORLIMITSr_MC.D1/IN3 ),
    .I4(\NlwInverterSignal_DCORLIMITSr_MC.D1/IN4 ),
    .I5(\NlwInverterSignal_DCORLIMITSr_MC.D1/IN5 ),
    .I6(\NlwInverterSignal_DCORLIMITSr_MC.D1/IN6 ),
    .I7(\NlwInverterSignal_DCORLIMITSr_MC.D1/IN7 ),
    .I8(U2_ADDR_reg[1]),
    .I9(\NlwInverterSignal_DCORLIMITSr_MC.D1/IN9 ),
    .I10(Vcc),
    .I11(Vcc),
    .I12(Vcc),
    .I13(Vcc),
    .I14(Vcc),
    .I15(Vcc),
    .O(\DCORLIMITSr_MC.D1 )
  );
  X_ZERO \DCORLIMITSr_MC.D2_949  (
    .O(\DCORLIMITSr_MC.D2 )
  );
  X_BUF \outDATA<0>\$WA2.UIM_950  (
    .I(\outDATA<0>\$WA2.UIM_MC.Q ),
    .O(\outDATA<0>\$WA2.UIM )
  );
  X_BUF \outDATA<0>\$WA2.UIM_MC.Q_951  (
    .I(\outDATA<0>\$WA2.UIM_MC.D ),
    .O(\outDATA<0>\$WA2.UIM_MC.Q )
  );
  X_XOR2 \outDATA<0>\$WA2.UIM_MC.D_952  (
    .I0(\outDATA<0>\$WA2.UIM_MC.D1 ),
    .I1(\outDATA<0>\$WA2.UIM_MC.D2 ),
    .O(\outDATA<0>\$WA2.UIM_MC.D )
  );
  X_AND2 \outDATA<0>\$WA2.UIM_MC.D1_953  (
    .I0(\RLS0_II/UIM ),
    .I1(\RLS0_II/UIM ),
    .O(\outDATA<0>\$WA2.UIM_MC.D1 )
  );
  X_ZERO \outDATA<0>\$WA2.UIM_MC.D2_954  (
    .O(\outDATA<0>\$WA2.UIM_MC.D2 )
  );
  X_BUF DCORENCPWRr_955 (
    .I(\DCORENCPWRr_MC.Q ),
    .O(DCORENCPWRr)
  );
  X_BUF \DCORENCPWRr_MC.Q_956  (
    .I(\DCORENCPWRr_MC.D ),
    .O(\DCORENCPWRr_MC.Q )
  );
  X_XOR2 \DCORENCPWRr_MC.D_957  (
    .I0(\DCORENCPWRr_MC.D1 ),
    .I1(\DCORENCPWRr_MC.D2 ),
    .O(\DCORENCPWRr_MC.D )
  );
  X_AND16 \DCORENCPWRr_MC.D1_958  (
    .I0(\WR_II/UIM ),
    .I1(\NlwInverterSignal_DCORENCPWRr_MC.D1/IN1 ),
    .I2(\NlwInverterSignal_DCORENCPWRr_MC.D1/IN2 ),
    .I3(\NlwInverterSignal_DCORENCPWRr_MC.D1/IN3 ),
    .I4(\NlwInverterSignal_DCORENCPWRr_MC.D1/IN4 ),
    .I5(\NlwInverterSignal_DCORENCPWRr_MC.D1/IN5 ),
    .I6(\NlwInverterSignal_DCORENCPWRr_MC.D1/IN6 ),
    .I7(U2_ADDR_reg[3]),
    .I8(U2_ADDR_reg[1]),
    .I9(U2_ADDR_reg[2]),
    .I10(Vcc),
    .I11(Vcc),
    .I12(Vcc),
    .I13(Vcc),
    .I14(Vcc),
    .I15(Vcc),
    .O(\DCORENCPWRr_MC.D1 )
  );
  X_ZERO \DCORENCPWRr_MC.D2_959  (
    .O(\DCORENCPWRr_MC.D2 )
  );
  X_BUF \outDATA<0>\$WA3.UIM_960  (
    .I(\outDATA<0>\$WA3.UIM_MC.Q ),
    .O(\outDATA<0>\$WA3.UIM )
  );
  X_BUF \outDATA<0>\$WA3.UIM_MC.Q_961  (
    .I(\outDATA<0>\$WA3.UIM_MC.D ),
    .O(\outDATA<0>\$WA3.UIM_MC.Q )
  );
  X_XOR2 \outDATA<0>\$WA3.UIM_MC.D_962  (
    .I0(\outDATA<0>\$WA3.UIM_MC.D1 ),
    .I1(\outDATA<0>\$WA3.UIM_MC.D2 ),
    .O(\outDATA<0>\$WA3.UIM_MC.D )
  );
  X_ZERO \outDATA<0>\$WA3.UIM_MC.D1_963  (
    .O(\outDATA<0>\$WA3.UIM_MC.D1 )
  );
  X_AND2 \outDATA<0>\$WA3.UIM_MC.D2_PT_0_964  (
    .I0(NET2528),
    .I1(\U4/Flgreg [0]),
    .O(\outDATA<0>\$WA3.UIM_MC.D2_PT_0 )
  );
  X_AND2 \outDATA<0>\$WA3.UIM_MC.D2_PT_1_965  (
    .I0(\NlwInverterSignal_outDATA<0>\$WA3.UIM_MC.D2_PT_1/IN0 ),
    .I1(\Home033FLG_II/UIM ),
    .O(\outDATA<0>\$WA3.UIM_MC.D2_PT_1 )
  );
  X_OR2 \outDATA<0>\$WA3.UIM_MC.D2_966  (
    .I0(\outDATA<0>\$WA3.UIM_MC.D2_PT_0 ),
    .I1(\outDATA<0>\$WA3.UIM_MC.D2_PT_1 ),
    .O(\outDATA<0>\$WA3.UIM_MC.D2 )
  );
  X_BUF DCORIFGr_967 (
    .I(\DCORIFGr_MC.Q ),
    .O(DCORIFGr)
  );
  X_BUF \DCORIFGr_MC.Q_968  (
    .I(\DCORIFGr_MC.D ),
    .O(\DCORIFGr_MC.Q )
  );
  X_XOR2 \DCORIFGr_MC.D_969  (
    .I0(\DCORIFGr_MC.D1 ),
    .I1(\DCORIFGr_MC.D2 ),
    .O(\DCORIFGr_MC.D )
  );
  X_AND16 \DCORIFGr_MC.D1_970  (
    .I0(\WR_II/UIM ),
    .I1(\NlwInverterSignal_DCORIFGr_MC.D1/IN1 ),
    .I2(U2_ADDR_reg[0]),
    .I3(\NlwInverterSignal_DCORIFGr_MC.D1/IN3 ),
    .I4(\NlwInverterSignal_DCORIFGr_MC.D1/IN4 ),
    .I5(\NlwInverterSignal_DCORIFGr_MC.D1/IN5 ),
    .I6(\NlwInverterSignal_DCORIFGr_MC.D1/IN6 ),
    .I7(\NlwInverterSignal_DCORIFGr_MC.D1/IN7 ),
    .I8(\NlwInverterSignal_DCORIFGr_MC.D1/IN8 ),
    .I9(\NlwInverterSignal_DCORIFGr_MC.D1/IN9 ),
    .I10(Vcc),
    .I11(Vcc),
    .I12(Vcc),
    .I13(Vcc),
    .I14(Vcc),
    .I15(Vcc),
    .O(\DCORIFGr_MC.D1 )
  );
  X_ZERO \DCORIFGr_MC.D2_971  (
    .O(\DCORIFGr_MC.D2 )
  );
  X_BUF \outDATA<0>\$WA4.UIM_972  (
    .I(\outDATA<0>\$WA4.UIM_MC.Q ),
    .O(\outDATA<0>\$WA4.UIM )
  );
  X_BUF \outDATA<0>\$WA4.UIM_MC.Q_973  (
    .I(\outDATA<0>\$WA4.UIM_MC.D ),
    .O(\outDATA<0>\$WA4.UIM_MC.Q )
  );
  X_XOR2 \outDATA<0>\$WA4.UIM_MC.D_974  (
    .I0(\outDATA<0>\$WA4.UIM_MC.D1 ),
    .I1(\outDATA<0>\$WA4.UIM_MC.D2 ),
    .O(\outDATA<0>\$WA4.UIM_MC.D )
  );
  X_AND2 \outDATA<0>\$WA4.UIM_MC.D1_975  (
    .I0(\INTbus_II/UIM ),
    .I1(\INTbus_II/UIM ),
    .O(\outDATA<0>\$WA4.UIM_MC.D1 )
  );
  X_ZERO \outDATA<0>\$WA4.UIM_MC.D2_976  (
    .O(\outDATA<0>\$WA4.UIM_MC.D2 )
  );
  X_BUF DCOR0THRESLOWr_977 (
    .I(\DCOR0THRESLOWr_MC.Q ),
    .O(DCOR0THRESLOWr)
  );
  X_BUF \DCOR0THRESLOWr_MC.Q_978  (
    .I(\DCOR0THRESLOWr_MC.D ),
    .O(\DCOR0THRESLOWr_MC.Q )
  );
  X_XOR2 \DCOR0THRESLOWr_MC.D_979  (
    .I0(\DCOR0THRESLOWr_MC.D1 ),
    .I1(\DCOR0THRESLOWr_MC.D2 ),
    .O(\DCOR0THRESLOWr_MC.D )
  );
  X_AND16 \DCOR0THRESLOWr_MC.D1_980  (
    .I0(\WR_II/UIM ),
    .I1(\NlwInverterSignal_DCOR0THRESLOWr_MC.D1/IN1 ),
    .I2(\NlwInverterSignal_DCOR0THRESLOWr_MC.D1/IN2 ),
    .I3(\NlwInverterSignal_DCOR0THRESLOWr_MC.D1/IN3 ),
    .I4(\NlwInverterSignal_DCOR0THRESLOWr_MC.D1/IN4 ),
    .I5(\NlwInverterSignal_DCOR0THRESLOWr_MC.D1/IN5 ),
    .I6(\NlwInverterSignal_DCOR0THRESLOWr_MC.D1/IN6 ),
    .I7(U2_ADDR_reg[3]),
    .I8(\NlwInverterSignal_DCOR0THRESLOWr_MC.D1/IN8 ),
    .I9(\NlwInverterSignal_DCOR0THRESLOWr_MC.D1/IN9 ),
    .I10(Vcc),
    .I11(Vcc),
    .I12(Vcc),
    .I13(Vcc),
    .I14(Vcc),
    .I15(Vcc),
    .O(\DCOR0THRESLOWr_MC.D1 )
  );
  X_ZERO \DCOR0THRESLOWr_MC.D2_981  (
    .O(\DCOR0THRESLOWr_MC.D2 )
  );
  X_BUF \outDATA<0>\$WA6.UIM_982  (
    .I(\outDATA<0>\$WA6.UIM_MC.Q ),
    .O(\outDATA<0>\$WA6.UIM )
  );
  X_BUF \outDATA<0>\$WA6.UIM_MC.Q_983  (
    .I(\outDATA<0>\$WA6.UIM_MC.D ),
    .O(\outDATA<0>\$WA6.UIM_MC.Q )
  );
  X_XOR2 \outDATA<0>\$WA6.UIM_MC.D_984  (
    .I0(\outDATA<0>\$WA6.UIM_MC.D1 ),
    .I1(\outDATA<0>\$WA6.UIM_MC.D2 ),
    .O(\outDATA<0>\$WA6.UIM_MC.D )
  );
  X_ZERO \outDATA<0>\$WA6.UIM_MC.D1_985  (
    .O(\outDATA<0>\$WA6.UIM_MC.D1 )
  );
  X_AND2 \outDATA<0>\$WA6.UIM_MC.D2_PT_0_986  (
    .I0(DCOR0THRESLOWr),
    .I1(\U1/U4/Latch0r [0]),
    .O(\outDATA<0>\$WA6.UIM_MC.D2_PT_0 )
  );
  X_AND3 \outDATA<0>\$WA6.UIM_MC.D2_PT_1_987  (
    .I0(\NlwInverterSignal_outDATA<0>\$WA6.UIM_MC.D2_PT_1/IN0 ),
    .I1(\U1/U4/Latch0r [8]),
    .I2(DCOR0THRESHIGHr),
    .O(\outDATA<0>\$WA6.UIM_MC.D2_PT_1 )
  );
  X_AND4 \outDATA<0>\$WA6.UIM_MC.D2_PT_2_988  (
    .I0(\NlwInverterSignal_outDATA<0>\$WA6.UIM_MC.D2_PT_2/IN0 ),
    .I1(\NlwInverterSignal_outDATA<0>\$WA6.UIM_MC.D2_PT_2/IN1 ),
    .I2(\U1/U4/Latch1r [0]),
    .I3(DCOR1THRESLOWr),
    .O(\outDATA<0>\$WA6.UIM_MC.D2_PT_2 )
  );
  X_AND4 \outDATA<0>\$WA6.UIM_MC.D2_PT_3_989  (
    .I0(\NlwInverterSignal_outDATA<0>\$WA6.UIM_MC.D2_PT_3/IN0 ),
    .I1(\NlwInverterSignal_outDATA<0>\$WA6.UIM_MC.D2_PT_3/IN1 ),
    .I2(\NlwInverterSignal_outDATA<0>\$WA6.UIM_MC.D2_PT_3/IN2 ),
    .I3(\U1/U4/Latch1r [8]),
    .O(\outDATA<0>\$WA6.UIM_MC.D2_PT_3 )
  );
  X_OR4 \outDATA<0>\$WA6.UIM_MC.D2_990  (
    .I0(\outDATA<0>\$WA6.UIM_MC.D2_PT_0 ),
    .I1(\outDATA<0>\$WA6.UIM_MC.D2_PT_1 ),
    .I2(\outDATA<0>\$WA6.UIM_MC.D2_PT_2 ),
    .I3(\outDATA<0>\$WA6.UIM_MC.D2_PT_3 ),
    .O(\outDATA<0>\$WA6.UIM_MC.D2 )
  );
  X_BUF \U1/U4/Latch0r<0>  (
    .I(\U1/U4/Latch0r<0>_MC.Q ),
    .O(\U1/U4/Latch0r [0])
  );
  X_FF \U1/U4/Latch0r<0>_MC.REG  (
    .I(\U1/U4/Latch0r<0>_MC.D ),
    .CE(Vcc),
    .CLK(\U1/U4/Latch0r<0>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\U1/U4/Latch0r<0>_MC.Q )
  );
  X_INV \U1/U4/Latch0r<0>_MC.REG_tsimcreated_inv_Mclk_II/FCLK_991  (
    .I(\Mclk_II/FCLK ),
    .O(\U1/U4/Latch0r<0>_MC.REG_tsimcreated_inv_Mclk_II/FCLK )
  );
  X_XOR2 \U1/U4/Latch0r<0>_MC.D_992  (
    .I0(\U1/U4/Latch0r<0>_MC.D1 ),
    .I1(\U1/U4/Latch0r<0>_MC.D2 ),
    .O(\U1/U4/Latch0r<0>_MC.D )
  );
  X_ZERO \U1/U4/Latch0r<0>_MC.D1_993  (
    .O(\U1/U4/Latch0r<0>_MC.D1 )
  );
  X_AND3 \U1/U4/Latch0r<0>_MC.D2_PT_0_994  (
    .I0(\MSPReset_II/UIM ),
    .I1(N_PZ_965),
    .I2(\U1/Channel0 [0]),
    .O(\U1/U4/Latch0r<0>_MC.D2_PT_0 )
  );
  X_AND3 \U1/U4/Latch0r<0>_MC.D2_PT_1_995  (
    .I0(\MSPReset_II/UIM ),
    .I1(\NlwInverterSignal_U1/U4/Latch0r<0>_MC.D2_PT_1/IN1 ),
    .I2(\U1/U4/Latch0r [0]),
    .O(\U1/U4/Latch0r<0>_MC.D2_PT_1 )
  );
  X_OR2 \U1/U4/Latch0r<0>_MC.D2_996  (
    .I0(\U1/U4/Latch0r<0>_MC.D2_PT_0 ),
    .I1(\U1/U4/Latch0r<0>_MC.D2_PT_1 ),
    .O(\U1/U4/Latch0r<0>_MC.D2 )
  );
  X_BUF \U1/Channel0<0>  (
    .I(\U1/Channel0<0>_MC.Q ),
    .O(\U1/Channel0 [0])
  );
  X_XOR2 \U1/Channel0<0>_MC_tsimcreated_xor__997  (
    .I0(\U1/Channel0<0>_MC.D ),
    .I1(\U1/Channel0<0>_MC.Q ),
    .O(\U1/Channel0<0>_MC_tsimcreated_xor_ )
  );
  X_FF \U1/Channel0<0>_MC.REG  (
    .I(\U1/Channel0<0>_MC_tsimcreated_xor_ ),
    .CE(Vcc),
    .CLK(\Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\U1/Channel0<0>_MC.Q )
  );
  X_XOR2 \U1/Channel0<0>_MC.D_998  (
    .I0(\U1/Channel0<0>_MC.D1 ),
    .I1(\U1/Channel0<0>_MC.D2 ),
    .O(\U1/Channel0<0>_MC.D )
  );
  X_ZERO \U1/Channel0<0>_MC.D1_999  (
    .O(\U1/Channel0<0>_MC.D1 )
  );
  X_AND2 \U1/Channel0<0>_MC.D2_PT_0_1000  (
    .I0(\U1/Channel0 [0]),
    .I1(\NlwInverterSignal_U1/Channel0<0>_MC.D2_PT_0/IN1 ),
    .O(\U1/Channel0<0>_MC.D2_PT_0 )
  );
  X_AND6 \U1/Channel0<0>_MC.D2_PT_1_1001  (
    .I0(\MSPReset_II/UIM ),
    .I1(\NlwInverterSignal_U1/Channel0<0>_MC.D2_PT_1/IN1 ),
    .I2(\U1/U1/CurrState_Sreg0_FFD1 ),
    .I3(\U1/U1/CurrState_Sreg0_FFD3 ),
    .I4(\NlwInverterSignal_U1/Channel0<0>_MC.D2_PT_1/IN4 ),
    .I5(\NlwInverterSignal_U1/Channel0<0>_MC.D2_PT_1/IN5 ),
    .O(\U1/Channel0<0>_MC.D2_PT_1 )
  );
  X_AND6 \U1/Channel0<0>_MC.D2_PT_2_1002  (
    .I0(\MSPReset_II/UIM ),
    .I1(\NlwInverterSignal_U1/Channel0<0>_MC.D2_PT_2/IN1 ),
    .I2(\NlwInverterSignal_U1/Channel0<0>_MC.D2_PT_2/IN2 ),
    .I3(\U1/U1/CurrState_Sreg0_FFD3 ),
    .I4(\NlwInverterSignal_U1/Channel0<0>_MC.D2_PT_2/IN4 ),
    .I5(\U1/U1/CurrState_Sreg0_FFD4 ),
    .O(\U1/Channel0<0>_MC.D2_PT_2 )
  );
  X_OR3 \U1/Channel0<0>_MC.D2_1003  (
    .I0(\U1/Channel0<0>_MC.D2_PT_0 ),
    .I1(\U1/Channel0<0>_MC.D2_PT_1 ),
    .I2(\U1/Channel0<0>_MC.D2_PT_2 ),
    .O(\U1/Channel0<0>_MC.D2 )
  );
  X_BUF \U1/Zero0_1004  (
    .I(\U1/Zero0_MC.Q ),
    .O(\U1/Zero0 )
  );
  X_FF \U1/Zero0_MC.REG  (
    .I(\U1/Zero0_MC.D ),
    .CE(Vcc),
    .CLK(\U1/Zero0_MC.REG_tsimcreated_inv_Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\U1/Zero0_MC.Q )
  );
  X_INV \U1/Zero0_MC.REG_tsimcreated_inv_Mclk_II/FCLK_1005  (
    .I(\Mclk_II/FCLK ),
    .O(\U1/Zero0_MC.REG_tsimcreated_inv_Mclk_II/FCLK )
  );
  X_XOR2 \U1/Zero0_MC.D_1006  (
    .I0(\U1/Zero0_MC.D1 ),
    .I1(\U1/Zero0_MC.D2 ),
    .O(\U1/Zero0_MC.D )
  );
  X_ZERO \U1/Zero0_MC.D1_1007  (
    .O(\U1/Zero0_MC.D1 )
  );
  X_AND2 \U1/Zero0_MC.D2_PT_0_1008  (
    .I0(\NlwInverterSignal_U1/Zero0_MC.D2_PT_0/IN0 ),
    .I1(\U1/Zero0 ),
    .O(\U1/Zero0_MC.D2_PT_0 )
  );
  X_AND2 \U1/Zero0_MC.D2_PT_1_1009  (
    .I0(\NlwInverterSignal_U1/Zero0_MC.D2_PT_1/IN0 ),
    .I1(N_PZ_964),
    .O(\U1/Zero0_MC.D2_PT_1 )
  );
  X_AND7 \U1/Zero0_MC.D2_PT_2_1010  (
    .I0(\MSPReset_II/UIM ),
    .I1(\NlwInverterSignal_U1/Zero0_MC.D2_PT_2/IN1 ),
    .I2(\U1/U4/RF0r ),
    .I3(\U1/U4/E0r ),
    .I4(\U1/U4/HE0stater ),
    .I5(\NlwInverterSignal_U1/Zero0_MC.D2_PT_2/IN5 ),
    .I6(\NlwInverterSignal_U1/Zero0_MC.D2_PT_2/IN6 ),
    .O(\U1/Zero0_MC.D2_PT_2 )
  );
  X_AND7 \U1/Zero0_MC.D2_PT_3_1011  (
    .I0(\MSPReset_II/UIM ),
    .I1(\NlwInverterSignal_U1/Zero0_MC.D2_PT_3/IN1 ),
    .I2(\NlwInverterSignal_U1/Zero0_MC.D2_PT_3/IN2 ),
    .I3(\U1/U4/E0r ),
    .I4(\NlwInverterSignal_U1/Zero0_MC.D2_PT_3/IN4 ),
    .I5(\U1/U4/HE0statelastr ),
    .I6(\NlwInverterSignal_U1/Zero0_MC.D2_PT_3/IN6 ),
    .O(\U1/Zero0_MC.D2_PT_3 )
  );
  X_OR4 \U1/Zero0_MC.D2_1012  (
    .I0(\U1/Zero0_MC.D2_PT_0 ),
    .I1(\U1/Zero0_MC.D2_PT_1 ),
    .I2(\U1/Zero0_MC.D2_PT_2 ),
    .I3(\U1/Zero0_MC.D2_PT_3 ),
    .O(\U1/Zero0_MC.D2 )
  );
  X_BUF N_PZ_964_1013 (
    .I(\N_PZ_964_MC.Q ),
    .O(N_PZ_964)
  );
  X_BUF \N_PZ_964_MC.Q_1014  (
    .I(\N_PZ_964_MC.D ),
    .O(\N_PZ_964_MC.Q )
  );
  X_XOR2 \N_PZ_964_MC.D_1015  (
    .I0(\N_PZ_964_MC.D1 ),
    .I1(\N_PZ_964_MC.D2 ),
    .O(\N_PZ_964_MC.D )
  );
  X_ZERO \N_PZ_964_MC.D1_1016  (
    .O(\N_PZ_964_MC.D1 )
  );
  X_AND2 \N_PZ_964_MC.D2_PT_0_1017  (
    .I0(\MSPReset_II/UIM ),
    .I1(DCORIFGw),
    .O(\N_PZ_964_MC.D2_PT_0 )
  );
  X_AND2 \N_PZ_964_MC.D2_PT_1_1018  (
    .I0(\MSPReset_II/UIM ),
    .I1(DCORENCCTLw),
    .O(\N_PZ_964_MC.D2_PT_1 )
  );
  X_OR2 \N_PZ_964_MC.D2_1019  (
    .I0(\N_PZ_964_MC.D2_PT_0 ),
    .I1(\N_PZ_964_MC.D2_PT_1 ),
    .O(\N_PZ_964_MC.D2 )
  );
  X_BUF N_PZ_931_1020 (
    .I(\N_PZ_931_MC.Q ),
    .O(N_PZ_931)
  );
  X_BUF \N_PZ_931_MC.Q_1021  (
    .I(\N_PZ_931_MC.D ),
    .O(\N_PZ_931_MC.Q )
  );
  X_XOR2 \N_PZ_931_MC.D_1022  (
    .I0(\N_PZ_931_MC.D1 ),
    .I1(\N_PZ_931_MC.D2 ),
    .O(\N_PZ_931_MC.D )
  );
  X_AND2 \N_PZ_931_MC.D1_1023  (
    .I0(\MSPReset_II/UIM ),
    .I1(\NlwInverterSignal_N_PZ_931_MC.D1/IN1 ),
    .O(\N_PZ_931_MC.D1 )
  );
  X_ZERO \N_PZ_931_MC.D2_1024  (
    .O(\N_PZ_931_MC.D2 )
  );
  X_BUF \U1/U1/CurrState_Sreg0_FFD1_1025  (
    .I(\U1/U1/CurrState_Sreg0_FFD1_MC.Q ),
    .O(\U1/U1/CurrState_Sreg0_FFD1 )
  );
  X_FF \U1/U1/CurrState_Sreg0_FFD1_MC.REG  (
    .I(\U1/U1/CurrState_Sreg0_FFD1_MC.D ),
    .CE(Vcc),
    .CLK(\Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\U1/U1/CurrState_Sreg0_FFD1_MC.Q )
  );
  X_XOR2 \U1/U1/CurrState_Sreg0_FFD1_MC.D_1026  (
    .I0(\U1/U1/CurrState_Sreg0_FFD1_MC.D1 ),
    .I1(\U1/U1/CurrState_Sreg0_FFD1_MC.D2 ),
    .O(\U1/U1/CurrState_Sreg0_FFD1_MC.D )
  );
  X_ZERO \U1/U1/CurrState_Sreg0_FFD1_MC.D1_1027  (
    .O(\U1/U1/CurrState_Sreg0_FFD1_MC.D1 )
  );
  X_AND4 \U1/U1/CurrState_Sreg0_FFD1_MC.D2_PT_0_1028  (
    .I0(\MSPReset_II/UIM ),
    .I1(\U1/U1/CurrState_Sreg0_FFD1 ),
    .I2(\U1/U1/CurrState_Sreg0_FFD2 ),
    .I3(\NlwInverterSignal_U1/U1/CurrState_Sreg0_FFD1_MC.D2_PT_0/IN3 ),
    .O(\U1/U1/CurrState_Sreg0_FFD1_MC.D2_PT_0 )
  );
  X_AND5 \U1/U1/CurrState_Sreg0_FFD1_MC.D2_PT_1_1029  (
    .I0(\MSPReset_II/UIM ),
    .I1(\PhaseA_Encoder0_II/UIM ),
    .I2(\U1/U1/CurrState_Sreg0_FFD1 ),
    .I3(\NlwInverterSignal_U1/U1/CurrState_Sreg0_FFD1_MC.D2_PT_1/IN3 ),
    .I4(\NlwInverterSignal_U1/U1/CurrState_Sreg0_FFD1_MC.D2_PT_1/IN4 ),
    .O(\U1/U1/CurrState_Sreg0_FFD1_MC.D2_PT_1 )
  );
  X_AND6 \U1/U1/CurrState_Sreg0_FFD1_MC.D2_PT_2_1030  (
    .I0(\MSPReset_II/UIM ),
    .I1(\NlwInverterSignal_U1/U1/CurrState_Sreg0_FFD1_MC.D2_PT_2/IN1 ),
    .I2(\PhaseB_Encoder0_II/UIM ),
    .I3(\NlwInverterSignal_U1/U1/CurrState_Sreg0_FFD1_MC.D2_PT_2/IN3 ),
    .I4(\NlwInverterSignal_U1/U1/CurrState_Sreg0_FFD1_MC.D2_PT_2/IN4 ),
    .I5(\NlwInverterSignal_U1/U1/CurrState_Sreg0_FFD1_MC.D2_PT_2/IN5 ),
    .O(\U1/U1/CurrState_Sreg0_FFD1_MC.D2_PT_2 )
  );
  X_OR3 \U1/U1/CurrState_Sreg0_FFD1_MC.D2_1031  (
    .I0(\U1/U1/CurrState_Sreg0_FFD1_MC.D2_PT_0 ),
    .I1(\U1/U1/CurrState_Sreg0_FFD1_MC.D2_PT_1 ),
    .I2(\U1/U1/CurrState_Sreg0_FFD1_MC.D2_PT_2 ),
    .O(\U1/U1/CurrState_Sreg0_FFD1_MC.D2 )
  );
  X_BUF \U1/U1/CurrState_Sreg0_FFD3_1032  (
    .I(\U1/U1/CurrState_Sreg0_FFD3_MC.Q ),
    .O(\U1/U1/CurrState_Sreg0_FFD3 )
  );
  X_FF \U1/U1/CurrState_Sreg0_FFD3_MC.REG  (
    .I(\U1/U1/CurrState_Sreg0_FFD3_MC.D ),
    .CE(Vcc),
    .CLK(\Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\U1/U1/CurrState_Sreg0_FFD3_MC.Q )
  );
  X_XOR2 \U1/U1/CurrState_Sreg0_FFD3_MC.D_1033  (
    .I0(\U1/U1/CurrState_Sreg0_FFD3_MC.D1 ),
    .I1(\U1/U1/CurrState_Sreg0_FFD3_MC.D2 ),
    .O(\U1/U1/CurrState_Sreg0_FFD3_MC.D )
  );
  X_ZERO \U1/U1/CurrState_Sreg0_FFD3_MC.D1_1034  (
    .O(\U1/U1/CurrState_Sreg0_FFD3_MC.D1 )
  );
  X_AND5 \U1/U1/CurrState_Sreg0_FFD3_MC.D2_PT_0_1035  (
    .I0(\MSPReset_II/UIM ),
    .I1(\NlwInverterSignal_U1/U1/CurrState_Sreg0_FFD3_MC.D2_PT_0/IN1 ),
    .I2(\U1/U1/CurrState_Sreg0_FFD3 ),
    .I3(\U1/U1/CurrState_Sreg0_FFD2 ),
    .I4(\NlwInverterSignal_U1/U1/CurrState_Sreg0_FFD3_MC.D2_PT_0/IN4 ),
    .O(\U1/U1/CurrState_Sreg0_FFD3_MC.D2_PT_0 )
  );
  X_AND5 \U1/U1/CurrState_Sreg0_FFD3_MC.D2_PT_1_1036  (
    .I0(\MSPReset_II/UIM ),
    .I1(\NlwInverterSignal_U1/U1/CurrState_Sreg0_FFD3_MC.D2_PT_1/IN1 ),
    .I2(\U1/U1/CurrState_Sreg0_FFD3 ),
    .I3(\NlwInverterSignal_U1/U1/CurrState_Sreg0_FFD3_MC.D2_PT_1/IN3 ),
    .I4(\NlwInverterSignal_U1/U1/CurrState_Sreg0_FFD3_MC.D2_PT_1/IN4 ),
    .O(\U1/U1/CurrState_Sreg0_FFD3_MC.D2_PT_1 )
  );
  X_AND6 \U1/U1/CurrState_Sreg0_FFD3_MC.D2_PT_2_1037  (
    .I0(\MSPReset_II/UIM ),
    .I1(\PhaseA_Encoder0_II/UIM ),
    .I2(\PhaseB_Encoder0_II/UIM ),
    .I3(\NlwInverterSignal_U1/U1/CurrState_Sreg0_FFD3_MC.D2_PT_2/IN3 ),
    .I4(\U1/U1/CurrState_Sreg0_FFD2 ),
    .I5(\NlwInverterSignal_U1/U1/CurrState_Sreg0_FFD3_MC.D2_PT_2/IN5 ),
    .O(\U1/U1/CurrState_Sreg0_FFD3_MC.D2_PT_2 )
  );
  X_AND6 \U1/U1/CurrState_Sreg0_FFD3_MC.D2_PT_3_1038  (
    .I0(\MSPReset_II/UIM ),
    .I1(\PhaseA_Encoder0_II/UIM ),
    .I2(\NlwInverterSignal_U1/U1/CurrState_Sreg0_FFD3_MC.D2_PT_3/IN2 ),
    .I3(\U1/U1/CurrState_Sreg0_FFD1 ),
    .I4(\U1/U1/CurrState_Sreg0_FFD2 ),
    .I5(\NlwInverterSignal_U1/U1/CurrState_Sreg0_FFD3_MC.D2_PT_3/IN5 ),
    .O(\U1/U1/CurrState_Sreg0_FFD3_MC.D2_PT_3 )
  );
  X_OR4 \U1/U1/CurrState_Sreg0_FFD3_MC.D2_1039  (
    .I0(\U1/U1/CurrState_Sreg0_FFD3_MC.D2_PT_0 ),
    .I1(\U1/U1/CurrState_Sreg0_FFD3_MC.D2_PT_1 ),
    .I2(\U1/U1/CurrState_Sreg0_FFD3_MC.D2_PT_2 ),
    .I3(\U1/U1/CurrState_Sreg0_FFD3_MC.D2_PT_3 ),
    .O(\U1/U1/CurrState_Sreg0_FFD3_MC.D2 )
  );
  X_BUF \U1/U1/CurrState_Sreg0_FFD2_1040  (
    .I(\U1/U1/CurrState_Sreg0_FFD2_MC.Q ),
    .O(\U1/U1/CurrState_Sreg0_FFD2 )
  );
  X_FF \U1/U1/CurrState_Sreg0_FFD2_MC.REG  (
    .I(\U1/U1/CurrState_Sreg0_FFD2_MC.D ),
    .CE(Vcc),
    .CLK(\Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\U1/U1/CurrState_Sreg0_FFD2_MC.Q )
  );
  X_XOR2 \U1/U1/CurrState_Sreg0_FFD2_MC.D_1041  (
    .I0(\U1/U1/CurrState_Sreg0_FFD2_MC.D1 ),
    .I1(\U1/U1/CurrState_Sreg0_FFD2_MC.D2 ),
    .O(\U1/U1/CurrState_Sreg0_FFD2_MC.D )
  );
  X_ZERO \U1/U1/CurrState_Sreg0_FFD2_MC.D1_1042  (
    .O(\U1/U1/CurrState_Sreg0_FFD2_MC.D1 )
  );
  X_AND6 \U1/U1/CurrState_Sreg0_FFD2_MC.D2_PT_0_1043  (
    .I0(\MSPReset_II/UIM ),
    .I1(\PhaseA_Encoder0_II/UIM ),
    .I2(\PhaseB_Encoder0_II/UIM ),
    .I3(\U1/U1/CurrState_Sreg0_FFD1 ),
    .I4(\NlwInverterSignal_U1/U1/CurrState_Sreg0_FFD2_MC.D2_PT_0/IN4 ),
    .I5(\NlwInverterSignal_U1/U1/CurrState_Sreg0_FFD2_MC.D2_PT_0/IN5 ),
    .O(\U1/U1/CurrState_Sreg0_FFD2_MC.D2_PT_0 )
  );
  X_AND6 \U1/U1/CurrState_Sreg0_FFD2_MC.D2_PT_1_1044  (
    .I0(\MSPReset_II/UIM ),
    .I1(\PhaseA_Encoder0_II/UIM ),
    .I2(\PhaseB_Encoder0_II/UIM ),
    .I3(\NlwInverterSignal_U1/U1/CurrState_Sreg0_FFD2_MC.D2_PT_1/IN3 ),
    .I4(\U1/U1/CurrState_Sreg0_FFD3 ),
    .I5(\NlwInverterSignal_U1/U1/CurrState_Sreg0_FFD2_MC.D2_PT_1/IN5 ),
    .O(\U1/U1/CurrState_Sreg0_FFD2_MC.D2_PT_1 )
  );
  X_AND6 \U1/U1/CurrState_Sreg0_FFD2_MC.D2_PT_2_1045  (
    .I0(\MSPReset_II/UIM ),
    .I1(\PhaseA_Encoder0_II/UIM ),
    .I2(\NlwInverterSignal_U1/U1/CurrState_Sreg0_FFD2_MC.D2_PT_2/IN2 ),
    .I3(\U1/U1/CurrState_Sreg0_FFD1 ),
    .I4(\U1/U1/CurrState_Sreg0_FFD2 ),
    .I5(\NlwInverterSignal_U1/U1/CurrState_Sreg0_FFD2_MC.D2_PT_2/IN5 ),
    .O(\U1/U1/CurrState_Sreg0_FFD2_MC.D2_PT_2 )
  );
  X_AND6 \U1/U1/CurrState_Sreg0_FFD2_MC.D2_PT_3_1046  (
    .I0(\MSPReset_II/UIM ),
    .I1(\PhaseA_Encoder0_II/UIM ),
    .I2(\NlwInverterSignal_U1/U1/CurrState_Sreg0_FFD2_MC.D2_PT_3/IN2 ),
    .I3(\NlwInverterSignal_U1/U1/CurrState_Sreg0_FFD2_MC.D2_PT_3/IN3 ),
    .I4(\NlwInverterSignal_U1/U1/CurrState_Sreg0_FFD2_MC.D2_PT_3/IN4 ),
    .I5(\NlwInverterSignal_U1/U1/CurrState_Sreg0_FFD2_MC.D2_PT_3/IN5 ),
    .O(\U1/U1/CurrState_Sreg0_FFD2_MC.D2_PT_3 )
  );
  X_AND6 \U1/U1/CurrState_Sreg0_FFD2_MC.D2_PT_4_1047  (
    .I0(\MSPReset_II/UIM ),
    .I1(\PhaseB_Encoder0_II/UIM ),
    .I2(\U1/U1/CurrState_Sreg0_FFD1 ),
    .I3(\U1/U1/CurrState_Sreg0_FFD3 ),
    .I4(\U1/U1/CurrState_Sreg0_FFD2 ),
    .I5(\NlwInverterSignal_U1/U1/CurrState_Sreg0_FFD2_MC.D2_PT_4/IN5 ),
    .O(\U1/U1/CurrState_Sreg0_FFD2_MC.D2_PT_4 )
  );
  X_AND6 \U1/U1/CurrState_Sreg0_FFD2_MC.D2_PT_5_1048  (
    .I0(\MSPReset_II/UIM ),
    .I1(\PhaseB_Encoder0_II/UIM ),
    .I2(\NlwInverterSignal_U1/U1/CurrState_Sreg0_FFD2_MC.D2_PT_5/IN2 ),
    .I3(\NlwInverterSignal_U1/U1/CurrState_Sreg0_FFD2_MC.D2_PT_5/IN3 ),
    .I4(\U1/U1/CurrState_Sreg0_FFD2 ),
    .I5(\NlwInverterSignal_U1/U1/CurrState_Sreg0_FFD2_MC.D2_PT_5/IN5 ),
    .O(\U1/U1/CurrState_Sreg0_FFD2_MC.D2_PT_5 )
  );
  X_AND6 \U1/U1/CurrState_Sreg0_FFD2_MC.D2_PT_6_1049  (
    .I0(\MSPReset_II/UIM ),
    .I1(\NlwInverterSignal_U1/U1/CurrState_Sreg0_FFD2_MC.D2_PT_6/IN1 ),
    .I2(\U1/U1/CurrState_Sreg0_FFD1 ),
    .I3(\NlwInverterSignal_U1/U1/CurrState_Sreg0_FFD2_MC.D2_PT_6/IN3 ),
    .I4(\U1/U1/CurrState_Sreg0_FFD2 ),
    .I5(\NlwInverterSignal_U1/U1/CurrState_Sreg0_FFD2_MC.D2_PT_6/IN5 ),
    .O(\U1/U1/CurrState_Sreg0_FFD2_MC.D2_PT_6 )
  );
  X_AND6 \U1/U1/CurrState_Sreg0_FFD2_MC.D2_PT_7_1050  (
    .I0(\MSPReset_II/UIM ),
    .I1(\NlwInverterSignal_U1/U1/CurrState_Sreg0_FFD2_MC.D2_PT_7/IN1 ),
    .I2(\NlwInverterSignal_U1/U1/CurrState_Sreg0_FFD2_MC.D2_PT_7/IN2 ),
    .I3(\U1/U1/CurrState_Sreg0_FFD3 ),
    .I4(\U1/U1/CurrState_Sreg0_FFD2 ),
    .I5(\NlwInverterSignal_U1/U1/CurrState_Sreg0_FFD2_MC.D2_PT_7/IN5 ),
    .O(\U1/U1/CurrState_Sreg0_FFD2_MC.D2_PT_7 )
  );
  X_OR8 \U1/U1/CurrState_Sreg0_FFD2_MC.D2_1051  (
    .I0(\U1/U1/CurrState_Sreg0_FFD2_MC.D2_PT_0 ),
    .I1(\U1/U1/CurrState_Sreg0_FFD2_MC.D2_PT_1 ),
    .I2(\U1/U1/CurrState_Sreg0_FFD2_MC.D2_PT_2 ),
    .I3(\U1/U1/CurrState_Sreg0_FFD2_MC.D2_PT_3 ),
    .I4(\U1/U1/CurrState_Sreg0_FFD2_MC.D2_PT_4 ),
    .I5(\U1/U1/CurrState_Sreg0_FFD2_MC.D2_PT_5 ),
    .I6(\U1/U1/CurrState_Sreg0_FFD2_MC.D2_PT_6 ),
    .I7(\U1/U1/CurrState_Sreg0_FFD2_MC.D2_PT_7 ),
    .O(\U1/U1/CurrState_Sreg0_FFD2_MC.D2 )
  );
  X_BUF \U1/U1/CurrState_Sreg0_FFD4_1052  (
    .I(\U1/U1/CurrState_Sreg0_FFD4_MC.Q ),
    .O(\U1/U1/CurrState_Sreg0_FFD4 )
  );
  X_FF \U1/U1/CurrState_Sreg0_FFD4_MC.REG  (
    .I(\U1/U1/CurrState_Sreg0_FFD4_MC.D ),
    .CE(Vcc),
    .CLK(\Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\U1/U1/CurrState_Sreg0_FFD4_MC.Q )
  );
  X_XOR2 \U1/U1/CurrState_Sreg0_FFD4_MC.D_1053  (
    .I0(\U1/U1/CurrState_Sreg0_FFD4_MC.D1 ),
    .I1(\U1/U1/CurrState_Sreg0_FFD4_MC.D2 ),
    .O(\U1/U1/CurrState_Sreg0_FFD4_MC.D )
  );
  X_AND7 \U1/U1/CurrState_Sreg0_FFD4_MC.D1_1054  (
    .I0(\MSPReset_II/UIM ),
    .I1(\NlwInverterSignal_U1/U1/CurrState_Sreg0_FFD4_MC.D1/IN1 ),
    .I2(\NlwInverterSignal_U1/U1/CurrState_Sreg0_FFD4_MC.D1/IN2 ),
    .I3(\NlwInverterSignal_U1/U1/CurrState_Sreg0_FFD4_MC.D1/IN3 ),
    .I4(\U1/U1/CurrState_Sreg0_FFD3 ),
    .I5(\NlwInverterSignal_U1/U1/CurrState_Sreg0_FFD4_MC.D1/IN5 ),
    .I6(\NlwInverterSignal_U1/U1/CurrState_Sreg0_FFD4_MC.D1/IN6 ),
    .O(\U1/U1/CurrState_Sreg0_FFD4_MC.D1 )
  );
  X_ZERO \U1/U1/CurrState_Sreg0_FFD4_MC.D2_1055  (
    .O(\U1/U1/CurrState_Sreg0_FFD4_MC.D2 )
  );
  X_BUF \U1/U4/Latch0r<8>  (
    .I(\U1/U4/Latch0r<8>_MC.Q ),
    .O(\U1/U4/Latch0r [8])
  );
  X_FF \U1/U4/Latch0r<8>_MC.REG  (
    .I(\U1/U4/Latch0r<8>_MC.D ),
    .CE(Vcc),
    .CLK(\U1/U4/Latch0r<8>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\U1/U4/Latch0r<8>_MC.Q )
  );
  X_INV \U1/U4/Latch0r<8>_MC.REG_tsimcreated_inv_Mclk_II/FCLK_1056  (
    .I(\Mclk_II/FCLK ),
    .O(\U1/U4/Latch0r<8>_MC.REG_tsimcreated_inv_Mclk_II/FCLK )
  );
  X_XOR2 \U1/U4/Latch0r<8>_MC.D_1057  (
    .I0(\U1/U4/Latch0r<8>_MC.D1 ),
    .I1(\U1/U4/Latch0r<8>_MC.D2 ),
    .O(\U1/U4/Latch0r<8>_MC.D )
  );
  X_ZERO \U1/U4/Latch0r<8>_MC.D1_1058  (
    .O(\U1/U4/Latch0r<8>_MC.D1 )
  );
  X_AND3 \U1/U4/Latch0r<8>_MC.D2_PT_0_1059  (
    .I0(\MSPReset_II/UIM ),
    .I1(N_PZ_965),
    .I2(\U1/Channel0 [8]),
    .O(\U1/U4/Latch0r<8>_MC.D2_PT_0 )
  );
  X_AND3 \U1/U4/Latch0r<8>_MC.D2_PT_1_1060  (
    .I0(\MSPReset_II/UIM ),
    .I1(\NlwInverterSignal_U1/U4/Latch0r<8>_MC.D2_PT_1/IN1 ),
    .I2(\U1/U4/Latch0r [8]),
    .O(\U1/U4/Latch0r<8>_MC.D2_PT_1 )
  );
  X_OR2 \U1/U4/Latch0r<8>_MC.D2_1061  (
    .I0(\U1/U4/Latch0r<8>_MC.D2_PT_0 ),
    .I1(\U1/U4/Latch0r<8>_MC.D2_PT_1 ),
    .O(\U1/U4/Latch0r<8>_MC.D2 )
  );
  X_BUF \U1/Channel0<8>  (
    .I(\U1/Channel0<8>_MC.Q ),
    .O(\U1/Channel0 [8])
  );
  X_XOR2 \U1/Channel0<8>_MC_tsimcreated_xor__1062  (
    .I0(\U1/Channel0<8>_MC.D ),
    .I1(\U1/Channel0<8>_MC.Q ),
    .O(\U1/Channel0<8>_MC_tsimcreated_xor_ )
  );
  X_FF \U1/Channel0<8>_MC.REG  (
    .I(\U1/Channel0<8>_MC_tsimcreated_xor_ ),
    .CE(Vcc),
    .CLK(\Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\U1/Channel0<8>_MC.Q )
  );
  X_XOR2 \U1/Channel0<8>_MC.D_1063  (
    .I0(\U1/Channel0<8>_MC.D1 ),
    .I1(\U1/Channel0<8>_MC.D2 ),
    .O(\U1/Channel0<8>_MC.D )
  );
  X_ZERO \U1/Channel0<8>_MC.D1_1064  (
    .O(\U1/Channel0<8>_MC.D1 )
  );
  X_AND2 \U1/Channel0<8>_MC.D2_PT_0_1065  (
    .I0(\NlwInverterSignal_U1/Channel0<8>_MC.D2_PT_0/IN0 ),
    .I1(\U1/Channel0 [8]),
    .O(\U1/Channel0<8>_MC.D2_PT_0 )
  );
  X_AND3 \U1/Channel0<8>_MC.D2_PT_1_1066  (
    .I0(\NlwInverterSignal_U1/Channel0<8>_MC.D2_PT_1/IN0 ),
    .I1(\U1/U2/location_Maddsub__n0000__n0075 [0]),
    .I2(N_PZ_966),
    .O(\U1/Channel0<8>_MC.D2_PT_1 )
  );
  X_AND4 \U1/Channel0<8>_MC.D2_PT_2_1067  (
    .I0(\U1/Channel0 [8]),
    .I1(\NlwInverterSignal_U1/Channel0<8>_MC.D2_PT_2/IN1 ),
    .I2(N_PZ_969),
    .I3(\NlwInverterSignal_U1/Channel0<8>_MC.D2_PT_2/IN3 ),
    .O(\U1/Channel0<8>_MC.D2_PT_2 )
  );
  X_AND6 \U1/Channel0<8>_MC.D2_PT_3_1068  (
    .I0(\U1/Channel0 [8]),
    .I1(\NlwInverterSignal_U1/Channel0<8>_MC.D2_PT_3/IN1 ),
    .I2(N_PZ_969),
    .I3(\U1/Channel0 [5]),
    .I4(\NlwInverterSignal_U1/Channel0<8>_MC.D2_PT_3/IN4 ),
    .I5(\U1/Channel0 [6]),
    .O(\U1/Channel0<8>_MC.D2_PT_3 )
  );
  X_AND7 \U1/Channel0<8>_MC.D2_PT_4_1069  (
    .I0(\U1/Channel0 [8]),
    .I1(\NlwInverterSignal_U1/Channel0<8>_MC.D2_PT_4/IN1 ),
    .I2(N_PZ_966),
    .I3(\NlwInverterSignal_U1/Channel0<8>_MC.D2_PT_4/IN3 ),
    .I4(\NlwInverterSignal_U1/Channel0<8>_MC.D2_PT_4/IN4 ),
    .I5(\U1/U2/location_Maddsub__n0000__n0067 [0]),
    .I6(\NlwInverterSignal_U1/Channel0<8>_MC.D2_PT_4/IN6 ),
    .O(\U1/Channel0<8>_MC.D2_PT_4 )
  );
  X_AND7 \U1/Channel0<8>_MC.D2_PT_5_1070  (
    .I0(\NlwInverterSignal_U1/Channel0<8>_MC.D2_PT_5/IN0 ),
    .I1(\U1/U2/location_Maddsub__n0000__n0075 [0]),
    .I2(N_PZ_969),
    .I3(\U1/Channel0 [7]),
    .I4(\U1/Channel0 [5]),
    .I5(\NlwInverterSignal_U1/Channel0<8>_MC.D2_PT_5/IN5 ),
    .I6(\U1/Channel0 [6]),
    .O(\U1/Channel0<8>_MC.D2_PT_5 )
  );
  X_OR6 \U1/Channel0<8>_MC.D2_1071  (
    .I0(\U1/Channel0<8>_MC.D2_PT_0 ),
    .I1(\U1/Channel0<8>_MC.D2_PT_1 ),
    .I2(\U1/Channel0<8>_MC.D2_PT_2 ),
    .I3(\U1/Channel0<8>_MC.D2_PT_3 ),
    .I4(\U1/Channel0<8>_MC.D2_PT_4 ),
    .I5(\U1/Channel0<8>_MC.D2_PT_5 ),
    .O(\U1/Channel0<8>_MC.D2 )
  );
  X_BUF \U1/U2/location_Maddsub__n0000__n0075<0>  (
    .I(\U1/U2/location_Maddsub__n0000__n0075<0>_MC.Q ),
    .O(\U1/U2/location_Maddsub__n0000__n0075 [0])
  );
  X_BUF \U1/U2/location_Maddsub__n0000__n0075<0>_MC.Q_1072  (
    .I(\U1/U2/location_Maddsub__n0000__n0075<0>_MC.D ),
    .O(\U1/U2/location_Maddsub__n0000__n0075<0>_MC.Q )
  );
  X_XOR2 \U1/U2/location_Maddsub__n0000__n0075<0>_MC.D_1073  (
    .I0(\U1/U2/location_Maddsub__n0000__n0075<0>_MC.D1 ),
    .I1(\U1/U2/location_Maddsub__n0000__n0075<0>_MC.D2 ),
    .O(\U1/U2/location_Maddsub__n0000__n0075<0>_MC.D )
  );
  X_AND2 \U1/U2/location_Maddsub__n0000__n0075<0>_MC.D1_1074  (
    .I0(N_PZ_945),
    .I1(N_PZ_945),
    .O(\U1/U2/location_Maddsub__n0000__n0075<0>_MC.D1 )
  );
  X_AND6 \U1/U2/location_Maddsub__n0000__n0075<0>_MC.D2_PT_0_1075  (
    .I0(\U1/Channel0 [8]),
    .I1(\U1/Channel0 [7]),
    .I2(\U1/Channel0 [5]),
    .I3(\NlwInverterSignal_U1/U2/location_Maddsub__n0000__n0075<0>_MC.D2_PT_0/IN3 ),
    .I4(\U1/Channel0 [6]),
    .I5(N_PZ_945),
    .O(\U1/U2/location_Maddsub__n0000__n0075<0>_MC.D2_PT_0 )
  );
  X_AND6 \U1/U2/location_Maddsub__n0000__n0075<0>_MC.D2_PT_1_1076  (
    .I0(\NlwInverterSignal_U1/U2/location_Maddsub__n0000__n0075<0>_MC.D2_PT_1/IN0 ),
    .I1(\NlwInverterSignal_U1/U2/location_Maddsub__n0000__n0075<0>_MC.D2_PT_1/IN1 ),
    .I2(\NlwInverterSignal_U1/U2/location_Maddsub__n0000__n0075<0>_MC.D2_PT_1/IN2 ),
    .I3(\U1/U2/location_Maddsub__n0000__n0067 [0]),
    .I4(\NlwInverterSignal_U1/U2/location_Maddsub__n0000__n0075<0>_MC.D2_PT_1/IN4 ),
    .I5(\NlwInverterSignal_U1/U2/location_Maddsub__n0000__n0075<0>_MC.D2_PT_1/IN5 ),
    .O(\U1/U2/location_Maddsub__n0000__n0075<0>_MC.D2_PT_1 )
  );
  X_OR2 \U1/U2/location_Maddsub__n0000__n0075<0>_MC.D2_1077  (
    .I0(\U1/U2/location_Maddsub__n0000__n0075<0>_MC.D2_PT_0 ),
    .I1(\U1/U2/location_Maddsub__n0000__n0075<0>_MC.D2_PT_1 ),
    .O(\U1/U2/location_Maddsub__n0000__n0075<0>_MC.D2 )
  );
  X_BUF N_PZ_945_1078 (
    .I(\N_PZ_945_MC.Q ),
    .O(N_PZ_945)
  );
  X_BUF \N_PZ_945_MC.Q_1079  (
    .I(\N_PZ_945_MC.D ),
    .O(\N_PZ_945_MC.Q )
  );
  X_XOR2 \N_PZ_945_MC.D_1080  (
    .I0(\N_PZ_945_MC.D1 ),
    .I1(\N_PZ_945_MC.D2 ),
    .O(\N_PZ_945_MC.D )
  );
  X_AND2 \N_PZ_945_MC.D1_1081  (
    .I0(\U1/NET3721 ),
    .I1(\U1/NET3721 ),
    .O(\N_PZ_945_MC.D1 )
  );
  X_AND3 \N_PZ_945_MC.D2_PT_0_1082  (
    .I0(\NlwInverterSignal_N_PZ_945_MC.D2_PT_0/IN0 ),
    .I1(\U1/U1/CurrState_Sreg0_FFD3 ),
    .I2(\NlwInverterSignal_N_PZ_945_MC.D2_PT_0/IN2 ),
    .O(\N_PZ_945_MC.D2_PT_0 )
  );
  X_AND3 \N_PZ_945_MC.D2_PT_1_1083  (
    .I0(\NlwInverterSignal_N_PZ_945_MC.D2_PT_1/IN0 ),
    .I1(\U1/U1/CurrState_Sreg0_FFD2 ),
    .I2(\NlwInverterSignal_N_PZ_945_MC.D2_PT_1/IN2 ),
    .O(\N_PZ_945_MC.D2_PT_1 )
  );
  X_OR2 \N_PZ_945_MC.D2_1084  (
    .I0(\N_PZ_945_MC.D2_PT_0 ),
    .I1(\N_PZ_945_MC.D2_PT_1 ),
    .O(\N_PZ_945_MC.D2 )
  );
  X_BUF \U1/NET3721_1085  (
    .I(\U1/NET3721_MC.Q ),
    .O(\U1/NET3721 )
  );
  X_FF \U1/NET3721_MC.REG  (
    .I(\U1/NET3721_MC.D ),
    .CE(Vcc),
    .CLK(\U1/NET3721_MC.REG_tsimcreated_inv_Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\U1/NET3721_MC.Q )
  );
  X_INV \U1/NET3721_MC.REG_tsimcreated_inv_Mclk_II/FCLK_1086  (
    .I(\Mclk_II/FCLK ),
    .O(\U1/NET3721_MC.REG_tsimcreated_inv_Mclk_II/FCLK )
  );
  X_XOR2 \U1/NET3721_MC.D_1087  (
    .I0(\U1/NET3721_MC.D1 ),
    .I1(\U1/NET3721_MC.D2 ),
    .O(\U1/NET3721_MC.D )
  );
  X_ZERO \U1/NET3721_MC.D1_1088  (
    .O(\U1/NET3721_MC.D1 )
  );
  X_AND3 \U1/NET3721_MC.D2_PT_0_1089  (
    .I0(\MSPReset_II/UIM ),
    .I1(\AD<3>_II/UIM ),
    .I2(DCORENCCTLw),
    .O(\U1/NET3721_MC.D2_PT_0 )
  );
  X_AND3 \U1/NET3721_MC.D2_PT_1_1090  (
    .I0(\MSPReset_II/UIM ),
    .I1(\NlwInverterSignal_U1/NET3721_MC.D2_PT_1/IN1 ),
    .I2(\U1/NET3721 ),
    .O(\U1/NET3721_MC.D2_PT_1 )
  );
  X_OR2 \U1/NET3721_MC.D2_1091  (
    .I0(\U1/NET3721_MC.D2_PT_0 ),
    .I1(\U1/NET3721_MC.D2_PT_1 ),
    .O(\U1/NET3721_MC.D2 )
  );
  X_BUF \U1/Channel0<5>  (
    .I(\U1/Channel0<5>_MC.Q ),
    .O(\U1/Channel0 [5])
  );
  X_XOR2 \U1/Channel0<5>_MC_tsimcreated_xor__1092  (
    .I0(\U1/Channel0<5>_MC.D ),
    .I1(\U1/Channel0<5>_MC.Q ),
    .O(\U1/Channel0<5>_MC_tsimcreated_xor_ )
  );
  X_FF \U1/Channel0<5>_MC.REG  (
    .I(\U1/Channel0<5>_MC_tsimcreated_xor_ ),
    .CE(Vcc),
    .CLK(\Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\U1/Channel0<5>_MC.Q )
  );
  X_XOR2 \U1/Channel0<5>_MC.D_1093  (
    .I0(\U1/Channel0<5>_MC.D1 ),
    .I1(\U1/Channel0<5>_MC.D2 ),
    .O(\U1/Channel0<5>_MC.D )
  );
  X_ZERO \U1/Channel0<5>_MC.D1_1094  (
    .O(\U1/Channel0<5>_MC.D1 )
  );
  X_AND2 \U1/Channel0<5>_MC.D2_PT_0_1095  (
    .I0(\NlwInverterSignal_U1/Channel0<5>_MC.D2_PT_0/IN0 ),
    .I1(\U1/Channel0 [5]),
    .O(\U1/Channel0<5>_MC.D2_PT_0 )
  );
  X_AND2 \U1/Channel0<5>_MC.D2_PT_1_1096  (
    .I0(N_PZ_966),
    .I1(\U1/U2/location_Maddsub__n0000__n0067 [0]),
    .O(\U1/Channel0<5>_MC.D2_PT_1 )
  );
  X_AND2 \U1/Channel0<5>_MC.D2_PT_2_1097  (
    .I0(N_PZ_969),
    .I1(\NlwInverterSignal_U1/Channel0<5>_MC.D2_PT_2/IN1 ),
    .O(\U1/Channel0<5>_MC.D2_PT_2 )
  );
  X_OR3 \U1/Channel0<5>_MC.D2_1098  (
    .I0(\U1/Channel0<5>_MC.D2_PT_0 ),
    .I1(\U1/Channel0<5>_MC.D2_PT_1 ),
    .I2(\U1/Channel0<5>_MC.D2_PT_2 ),
    .O(\U1/Channel0<5>_MC.D2 )
  );
  X_BUF \U1/U2/location_Maddsub__n0000__n0067<0>  (
    .I(\U1/U2/location_Maddsub__n0000__n0067<0>_MC.Q ),
    .O(\U1/U2/location_Maddsub__n0000__n0067 [0])
  );
  X_BUF \U1/U2/location_Maddsub__n0000__n0067<0>_MC.Q_1099  (
    .I(\U1/U2/location_Maddsub__n0000__n0067<0>_MC.D ),
    .O(\U1/U2/location_Maddsub__n0000__n0067<0>_MC.Q )
  );
  X_XOR2 \U1/U2/location_Maddsub__n0000__n0067<0>_MC.D_1100  (
    .I0(\U1/U2/location_Maddsub__n0000__n0067<0>_MC.D1 ),
    .I1(\U1/U2/location_Maddsub__n0000__n0067<0>_MC.D2 ),
    .O(\U1/U2/location_Maddsub__n0000__n0067<0>_MC.D )
  );
  X_AND2 \U1/U2/location_Maddsub__n0000__n0067<0>_MC.D1_1101  (
    .I0(N_PZ_945),
    .I1(N_PZ_945),
    .O(\U1/U2/location_Maddsub__n0000__n0067<0>_MC.D1 )
  );
  X_AND6 \U1/U2/location_Maddsub__n0000__n0067<0>_MC.D2_PT_0_1102  (
    .I0(\U1/Channel0 [0]),
    .I1(N_PZ_945),
    .I2(\U1/Channel0 [1]),
    .I3(\U1/Channel0 [2]),
    .I4(\U1/Channel0 [3]),
    .I5(\U1/Channel0 [4]),
    .O(\U1/U2/location_Maddsub__n0000__n0067<0>_MC.D2_PT_0 )
  );
  X_AND6 \U1/U2/location_Maddsub__n0000__n0067<0>_MC.D2_PT_1_1103  (
    .I0(\NlwInverterSignal_U1/U2/location_Maddsub__n0000__n0067<0>_MC.D2_PT_1/IN0 ),
    .I1(\NlwInverterSignal_U1/U2/location_Maddsub__n0000__n0067<0>_MC.D2_PT_1/IN1 ),
    .I2(\NlwInverterSignal_U1/U2/location_Maddsub__n0000__n0067<0>_MC.D2_PT_1/IN2 ),
    .I3(\NlwInverterSignal_U1/U2/location_Maddsub__n0000__n0067<0>_MC.D2_PT_1/IN3 ),
    .I4(\NlwInverterSignal_U1/U2/location_Maddsub__n0000__n0067<0>_MC.D2_PT_1/IN4 ),
    .I5(\NlwInverterSignal_U1/U2/location_Maddsub__n0000__n0067<0>_MC.D2_PT_1/IN5 ),
    .O(\U1/U2/location_Maddsub__n0000__n0067<0>_MC.D2_PT_1 )
  );
  X_OR2 \U1/U2/location_Maddsub__n0000__n0067<0>_MC.D2_1104  (
    .I0(\U1/U2/location_Maddsub__n0000__n0067<0>_MC.D2_PT_0 ),
    .I1(\U1/U2/location_Maddsub__n0000__n0067<0>_MC.D2_PT_1 ),
    .O(\U1/U2/location_Maddsub__n0000__n0067<0>_MC.D2 )
  );
  X_BUF \U1/Channel0<1>  (
    .I(\U1/Channel0<1>_MC.Q ),
    .O(\U1/Channel0 [1])
  );
  X_XOR2 \U1/Channel0<1>_MC_tsimcreated_xor__1105  (
    .I0(\U1/Channel0<1>_MC.D ),
    .I1(\U1/Channel0<1>_MC.Q ),
    .O(\U1/Channel0<1>_MC_tsimcreated_xor_ )
  );
  X_FF \U1/Channel0<1>_MC.REG  (
    .I(\U1/Channel0<1>_MC_tsimcreated_xor_ ),
    .CE(Vcc),
    .CLK(\Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\U1/Channel0<1>_MC.Q )
  );
  X_XOR2 \U1/Channel0<1>_MC.D_1106  (
    .I0(\U1/Channel0<1>_MC.D1 ),
    .I1(\U1/Channel0<1>_MC.D2 ),
    .O(\U1/Channel0<1>_MC.D )
  );
  X_ZERO \U1/Channel0<1>_MC.D1_1107  (
    .O(\U1/Channel0<1>_MC.D1 )
  );
  X_AND2 \U1/Channel0<1>_MC.D2_PT_0_1108  (
    .I0(\U1/Channel0 [0]),
    .I1(N_PZ_969),
    .O(\U1/Channel0<1>_MC.D2_PT_0 )
  );
  X_AND2 \U1/Channel0<1>_MC.D2_PT_1_1109  (
    .I0(\NlwInverterSignal_U1/Channel0<1>_MC.D2_PT_1/IN0 ),
    .I1(N_PZ_966),
    .O(\U1/Channel0<1>_MC.D2_PT_1 )
  );
  X_AND2 \U1/Channel0<1>_MC.D2_PT_2_1110  (
    .I0(\NlwInverterSignal_U1/Channel0<1>_MC.D2_PT_2/IN0 ),
    .I1(\U1/Channel0 [1]),
    .O(\U1/Channel0<1>_MC.D2_PT_2 )
  );
  X_OR3 \U1/Channel0<1>_MC.D2_1111  (
    .I0(\U1/Channel0<1>_MC.D2_PT_0 ),
    .I1(\U1/Channel0<1>_MC.D2_PT_1 ),
    .I2(\U1/Channel0<1>_MC.D2_PT_2 ),
    .O(\U1/Channel0<1>_MC.D2 )
  );
  X_BUF N_PZ_966_1112 (
    .I(\N_PZ_966_MC.Q ),
    .O(N_PZ_966)
  );
  X_BUF \N_PZ_966_MC.Q_1113  (
    .I(\N_PZ_966_MC.D ),
    .O(\N_PZ_966_MC.Q )
  );
  X_XOR2 \N_PZ_966_MC.D_1114  (
    .I0(\N_PZ_966_MC.D1 ),
    .I1(\N_PZ_966_MC.D2 ),
    .O(\N_PZ_966_MC.D )
  );
  X_ZERO \N_PZ_966_MC.D1_1115  (
    .O(\N_PZ_966_MC.D1 )
  );
  X_AND7 \N_PZ_966_MC.D2_PT_0_1116  (
    .I0(\MSPReset_II/UIM ),
    .I1(\NlwInverterSignal_N_PZ_966_MC.D2_PT_0/IN1 ),
    .I2(\U1/U1/CurrState_Sreg0_FFD1 ),
    .I3(\U1/U1/CurrState_Sreg0_FFD3 ),
    .I4(\NlwInverterSignal_N_PZ_966_MC.D2_PT_0/IN4 ),
    .I5(\NlwInverterSignal_N_PZ_966_MC.D2_PT_0/IN5 ),
    .I6(\NlwInverterSignal_N_PZ_966_MC.D2_PT_0/IN6 ),
    .O(\N_PZ_966_MC.D2_PT_0 )
  );
  X_AND7 \N_PZ_966_MC.D2_PT_1_1117  (
    .I0(\MSPReset_II/UIM ),
    .I1(\NlwInverterSignal_N_PZ_966_MC.D2_PT_1/IN1 ),
    .I2(\NlwInverterSignal_N_PZ_966_MC.D2_PT_1/IN2 ),
    .I3(\U1/U1/CurrState_Sreg0_FFD3 ),
    .I4(\NlwInverterSignal_N_PZ_966_MC.D2_PT_1/IN4 ),
    .I5(\U1/U1/CurrState_Sreg0_FFD4 ),
    .I6(\U1/NET3721 ),
    .O(\N_PZ_966_MC.D2_PT_1 )
  );
  X_OR2 \N_PZ_966_MC.D2_1118  (
    .I0(\N_PZ_966_MC.D2_PT_0 ),
    .I1(\N_PZ_966_MC.D2_PT_1 ),
    .O(\N_PZ_966_MC.D2 )
  );
  X_BUF N_PZ_969_1119 (
    .I(\N_PZ_969_MC.Q ),
    .O(N_PZ_969)
  );
  X_BUF \N_PZ_969_MC.Q_1120  (
    .I(\N_PZ_969_MC.D ),
    .O(\N_PZ_969_MC.Q )
  );
  X_XOR2 \N_PZ_969_MC.D_1121  (
    .I0(\N_PZ_969_MC.D1 ),
    .I1(\N_PZ_969_MC.D2 ),
    .O(\N_PZ_969_MC.D )
  );
  X_ZERO \N_PZ_969_MC.D1_1122  (
    .O(\N_PZ_969_MC.D1 )
  );
  X_AND7 \N_PZ_969_MC.D2_PT_0_1123  (
    .I0(\MSPReset_II/UIM ),
    .I1(\NlwInverterSignal_N_PZ_969_MC.D2_PT_0/IN1 ),
    .I2(\U1/U1/CurrState_Sreg0_FFD1 ),
    .I3(\U1/U1/CurrState_Sreg0_FFD3 ),
    .I4(\NlwInverterSignal_N_PZ_969_MC.D2_PT_0/IN4 ),
    .I5(\NlwInverterSignal_N_PZ_969_MC.D2_PT_0/IN5 ),
    .I6(\U1/NET3721 ),
    .O(\N_PZ_969_MC.D2_PT_0 )
  );
  X_AND7 \N_PZ_969_MC.D2_PT_1_1124  (
    .I0(\MSPReset_II/UIM ),
    .I1(\NlwInverterSignal_N_PZ_969_MC.D2_PT_1/IN1 ),
    .I2(\NlwInverterSignal_N_PZ_969_MC.D2_PT_1/IN2 ),
    .I3(\U1/U1/CurrState_Sreg0_FFD3 ),
    .I4(\NlwInverterSignal_N_PZ_969_MC.D2_PT_1/IN4 ),
    .I5(\U1/U1/CurrState_Sreg0_FFD4 ),
    .I6(\NlwInverterSignal_N_PZ_969_MC.D2_PT_1/IN6 ),
    .O(\N_PZ_969_MC.D2_PT_1 )
  );
  X_OR2 \N_PZ_969_MC.D2_1125  (
    .I0(\N_PZ_969_MC.D2_PT_0 ),
    .I1(\N_PZ_969_MC.D2_PT_1 ),
    .O(\N_PZ_969_MC.D2 )
  );
  X_BUF \U1/Channel0<2>  (
    .I(\U1/Channel0<2>_MC.Q ),
    .O(\U1/Channel0 [2])
  );
  X_XOR2 \U1/Channel0<2>_MC_tsimcreated_xor__1126  (
    .I0(\U1/Channel0<2>_MC.D ),
    .I1(\U1/Channel0<2>_MC.Q ),
    .O(\U1/Channel0<2>_MC_tsimcreated_xor_ )
  );
  X_FF \U1/Channel0<2>_MC.REG  (
    .I(\U1/Channel0<2>_MC_tsimcreated_xor_ ),
    .CE(Vcc),
    .CLK(\Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\U1/Channel0<2>_MC.Q )
  );
  X_XOR2 \U1/Channel0<2>_MC.D_1127  (
    .I0(\U1/Channel0<2>_MC.D1 ),
    .I1(\U1/Channel0<2>_MC.D2 ),
    .O(\U1/Channel0<2>_MC.D )
  );
  X_ZERO \U1/Channel0<2>_MC.D1_1128  (
    .O(\U1/Channel0<2>_MC.D1 )
  );
  X_AND2 \U1/Channel0<2>_MC.D2_PT_0_1129  (
    .I0(\NlwInverterSignal_U1/Channel0<2>_MC.D2_PT_0/IN0 ),
    .I1(\U1/Channel0 [2]),
    .O(\U1/Channel0<2>_MC.D2_PT_0 )
  );
  X_AND3 \U1/Channel0<2>_MC.D2_PT_1_1130  (
    .I0(\U1/Channel0 [0]),
    .I1(N_PZ_969),
    .I2(\U1/Channel0 [1]),
    .O(\U1/Channel0<2>_MC.D2_PT_1 )
  );
  X_AND3 \U1/Channel0<2>_MC.D2_PT_2_1131  (
    .I0(\NlwInverterSignal_U1/Channel0<2>_MC.D2_PT_2/IN0 ),
    .I1(N_PZ_966),
    .I2(\NlwInverterSignal_U1/Channel0<2>_MC.D2_PT_2/IN2 ),
    .O(\U1/Channel0<2>_MC.D2_PT_2 )
  );
  X_OR3 \U1/Channel0<2>_MC.D2_1132  (
    .I0(\U1/Channel0<2>_MC.D2_PT_0 ),
    .I1(\U1/Channel0<2>_MC.D2_PT_1 ),
    .I2(\U1/Channel0<2>_MC.D2_PT_2 ),
    .O(\U1/Channel0<2>_MC.D2 )
  );
  X_BUF \U1/Channel0<3>  (
    .I(\U1/Channel0<3>_MC.Q ),
    .O(\U1/Channel0 [3])
  );
  X_XOR2 \U1/Channel0<3>_MC_tsimcreated_xor__1133  (
    .I0(\U1/Channel0<3>_MC.D ),
    .I1(\U1/Channel0<3>_MC.Q ),
    .O(\U1/Channel0<3>_MC_tsimcreated_xor_ )
  );
  X_FF \U1/Channel0<3>_MC.REG  (
    .I(\U1/Channel0<3>_MC_tsimcreated_xor_ ),
    .CE(Vcc),
    .CLK(\Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\U1/Channel0<3>_MC.Q )
  );
  X_XOR2 \U1/Channel0<3>_MC.D_1134  (
    .I0(\U1/Channel0<3>_MC.D1 ),
    .I1(\U1/Channel0<3>_MC.D2 ),
    .O(\U1/Channel0<3>_MC.D )
  );
  X_ZERO \U1/Channel0<3>_MC.D1_1135  (
    .O(\U1/Channel0<3>_MC.D1 )
  );
  X_AND2 \U1/Channel0<3>_MC.D2_PT_0_1136  (
    .I0(\NlwInverterSignal_U1/Channel0<3>_MC.D2_PT_0/IN0 ),
    .I1(\U1/Channel0 [3]),
    .O(\U1/Channel0<3>_MC.D2_PT_0 )
  );
  X_AND4 \U1/Channel0<3>_MC.D2_PT_1_1137  (
    .I0(\U1/Channel0 [0]),
    .I1(N_PZ_969),
    .I2(\U1/Channel0 [1]),
    .I3(\U1/Channel0 [2]),
    .O(\U1/Channel0<3>_MC.D2_PT_1 )
  );
  X_AND4 \U1/Channel0<3>_MC.D2_PT_2_1138  (
    .I0(\NlwInverterSignal_U1/Channel0<3>_MC.D2_PT_2/IN0 ),
    .I1(N_PZ_966),
    .I2(\NlwInverterSignal_U1/Channel0<3>_MC.D2_PT_2/IN2 ),
    .I3(\NlwInverterSignal_U1/Channel0<3>_MC.D2_PT_2/IN3 ),
    .O(\U1/Channel0<3>_MC.D2_PT_2 )
  );
  X_OR3 \U1/Channel0<3>_MC.D2_1139  (
    .I0(\U1/Channel0<3>_MC.D2_PT_0 ),
    .I1(\U1/Channel0<3>_MC.D2_PT_1 ),
    .I2(\U1/Channel0<3>_MC.D2_PT_2 ),
    .O(\U1/Channel0<3>_MC.D2 )
  );
  X_BUF \U1/Channel0<4>  (
    .I(\U1/Channel0<4>_MC.Q ),
    .O(\U1/Channel0 [4])
  );
  X_XOR2 \U1/Channel0<4>_MC_tsimcreated_xor__1140  (
    .I0(\U1/Channel0<4>_MC.D ),
    .I1(\U1/Channel0<4>_MC.Q ),
    .O(\U1/Channel0<4>_MC_tsimcreated_xor_ )
  );
  X_FF \U1/Channel0<4>_MC.REG  (
    .I(\U1/Channel0<4>_MC_tsimcreated_xor_ ),
    .CE(Vcc),
    .CLK(\Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\U1/Channel0<4>_MC.Q )
  );
  X_XOR2 \U1/Channel0<4>_MC.D_1141  (
    .I0(\U1/Channel0<4>_MC.D1 ),
    .I1(\U1/Channel0<4>_MC.D2 ),
    .O(\U1/Channel0<4>_MC.D )
  );
  X_ZERO \U1/Channel0<4>_MC.D1_1142  (
    .O(\U1/Channel0<4>_MC.D1 )
  );
  X_AND2 \U1/Channel0<4>_MC.D2_PT_0_1143  (
    .I0(\NlwInverterSignal_U1/Channel0<4>_MC.D2_PT_0/IN0 ),
    .I1(\U1/Channel0 [4]),
    .O(\U1/Channel0<4>_MC.D2_PT_0 )
  );
  X_AND3 \U1/Channel0<4>_MC.D2_PT_1_1144  (
    .I0(N_PZ_966),
    .I1(\U1/U2/location_Maddsub__n0000__n0067 [0]),
    .I2(\NlwInverterSignal_U1/Channel0<4>_MC.D2_PT_1/IN2 ),
    .O(\U1/Channel0<4>_MC.D2_PT_1 )
  );
  X_AND4 \U1/Channel0<4>_MC.D2_PT_2_1145  (
    .I0(N_PZ_969),
    .I1(\NlwInverterSignal_U1/Channel0<4>_MC.D2_PT_2/IN1 ),
    .I2(\NlwInverterSignal_U1/Channel0<4>_MC.D2_PT_2/IN2 ),
    .I3(\U1/Channel0 [4]),
    .O(\U1/Channel0<4>_MC.D2_PT_2 )
  );
  X_AND6 \U1/Channel0<4>_MC.D2_PT_3_1146  (
    .I0(\U1/Channel0 [0]),
    .I1(N_PZ_969),
    .I2(\NlwInverterSignal_U1/Channel0<4>_MC.D2_PT_3/IN2 ),
    .I3(\U1/Channel0 [1]),
    .I4(\U1/Channel0 [2]),
    .I5(\U1/Channel0 [4]),
    .O(\U1/Channel0<4>_MC.D2_PT_3 )
  );
  X_AND7 \U1/Channel0<4>_MC.D2_PT_4_1147  (
    .I0(\U1/Channel0 [0]),
    .I1(N_PZ_969),
    .I2(\U1/U2/location_Maddsub__n0000__n0067 [0]),
    .I3(\U1/Channel0 [1]),
    .I4(\U1/Channel0 [2]),
    .I5(\U1/Channel0 [3]),
    .I6(\NlwInverterSignal_U1/Channel0<4>_MC.D2_PT_4/IN6 ),
    .O(\U1/Channel0<4>_MC.D2_PT_4 )
  );
  X_AND7 \U1/Channel0<4>_MC.D2_PT_5_1148  (
    .I0(\NlwInverterSignal_U1/Channel0<4>_MC.D2_PT_5/IN0 ),
    .I1(N_PZ_966),
    .I2(\NlwInverterSignal_U1/Channel0<4>_MC.D2_PT_5/IN2 ),
    .I3(\NlwInverterSignal_U1/Channel0<4>_MC.D2_PT_5/IN3 ),
    .I4(\NlwInverterSignal_U1/Channel0<4>_MC.D2_PT_5/IN4 ),
    .I5(\NlwInverterSignal_U1/Channel0<4>_MC.D2_PT_5/IN5 ),
    .I6(\U1/Channel0 [4]),
    .O(\U1/Channel0<4>_MC.D2_PT_5 )
  );
  X_OR6 \U1/Channel0<4>_MC.D2_1149  (
    .I0(\U1/Channel0<4>_MC.D2_PT_0 ),
    .I1(\U1/Channel0<4>_MC.D2_PT_1 ),
    .I2(\U1/Channel0<4>_MC.D2_PT_2 ),
    .I3(\U1/Channel0<4>_MC.D2_PT_3 ),
    .I4(\U1/Channel0<4>_MC.D2_PT_4 ),
    .I5(\U1/Channel0<4>_MC.D2_PT_5 ),
    .O(\U1/Channel0<4>_MC.D2 )
  );
  X_BUF \U1/Channel0<6>  (
    .I(\U1/Channel0<6>_MC.Q ),
    .O(\U1/Channel0 [6])
  );
  X_XOR2 \U1/Channel0<6>_MC_tsimcreated_xor__1150  (
    .I0(\U1/Channel0<6>_MC.D ),
    .I1(\U1/Channel0<6>_MC.Q ),
    .O(\U1/Channel0<6>_MC_tsimcreated_xor_ )
  );
  X_FF \U1/Channel0<6>_MC.REG  (
    .I(\U1/Channel0<6>_MC_tsimcreated_xor_ ),
    .CE(Vcc),
    .CLK(\Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\U1/Channel0<6>_MC.Q )
  );
  X_XOR2 \U1/Channel0<6>_MC.D_1151  (
    .I0(\U1/Channel0<6>_MC.D1 ),
    .I1(\U1/Channel0<6>_MC.D2 ),
    .O(\U1/Channel0<6>_MC.D )
  );
  X_ZERO \U1/Channel0<6>_MC.D1_1152  (
    .O(\U1/Channel0<6>_MC.D1 )
  );
  X_AND2 \U1/Channel0<6>_MC.D2_PT_0_1153  (
    .I0(\NlwInverterSignal_U1/Channel0<6>_MC.D2_PT_0/IN0 ),
    .I1(\U1/Channel0 [6]),
    .O(\U1/Channel0<6>_MC.D2_PT_0 )
  );
  X_AND3 \U1/Channel0<6>_MC.D2_PT_1_1154  (
    .I0(N_PZ_966),
    .I1(\NlwInverterSignal_U1/Channel0<6>_MC.D2_PT_1/IN1 ),
    .I2(\U1/U2/location_Maddsub__n0000__n0067 [0]),
    .O(\U1/Channel0<6>_MC.D2_PT_1 )
  );
  X_AND3 \U1/Channel0<6>_MC.D2_PT_2_1155  (
    .I0(N_PZ_969),
    .I1(\U1/Channel0 [5]),
    .I2(\NlwInverterSignal_U1/Channel0<6>_MC.D2_PT_2/IN2 ),
    .O(\U1/Channel0<6>_MC.D2_PT_2 )
  );
  X_OR3 \U1/Channel0<6>_MC.D2_1156  (
    .I0(\U1/Channel0<6>_MC.D2_PT_0 ),
    .I1(\U1/Channel0<6>_MC.D2_PT_1 ),
    .I2(\U1/Channel0<6>_MC.D2_PT_2 ),
    .O(\U1/Channel0<6>_MC.D2 )
  );
  X_BUF \U1/Channel0<7>  (
    .I(\U1/Channel0<7>_MC.Q ),
    .O(\U1/Channel0 [7])
  );
  X_XOR2 \U1/Channel0<7>_MC_tsimcreated_xor__1157  (
    .I0(\U1/Channel0<7>_MC.D ),
    .I1(\U1/Channel0<7>_MC.Q ),
    .O(\U1/Channel0<7>_MC_tsimcreated_xor_ )
  );
  X_FF \U1/Channel0<7>_MC.REG  (
    .I(\U1/Channel0<7>_MC_tsimcreated_xor_ ),
    .CE(Vcc),
    .CLK(\Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\U1/Channel0<7>_MC.Q )
  );
  X_XOR2 \U1/Channel0<7>_MC.D_1158  (
    .I0(\U1/Channel0<7>_MC.D1 ),
    .I1(\U1/Channel0<7>_MC.D2 ),
    .O(\U1/Channel0<7>_MC.D )
  );
  X_ZERO \U1/Channel0<7>_MC.D1_1159  (
    .O(\U1/Channel0<7>_MC.D1 )
  );
  X_AND2 \U1/Channel0<7>_MC.D2_PT_0_1160  (
    .I0(\NlwInverterSignal_U1/Channel0<7>_MC.D2_PT_0/IN0 ),
    .I1(\U1/Channel0 [7]),
    .O(\U1/Channel0<7>_MC.D2_PT_0 )
  );
  X_AND4 \U1/Channel0<7>_MC.D2_PT_1_1161  (
    .I0(N_PZ_966),
    .I1(\NlwInverterSignal_U1/Channel0<7>_MC.D2_PT_1/IN1 ),
    .I2(\U1/U2/location_Maddsub__n0000__n0067 [0]),
    .I3(\NlwInverterSignal_U1/Channel0<7>_MC.D2_PT_1/IN3 ),
    .O(\U1/Channel0<7>_MC.D2_PT_1 )
  );
  X_AND4 \U1/Channel0<7>_MC.D2_PT_2_1162  (
    .I0(N_PZ_969),
    .I1(\U1/Channel0 [5]),
    .I2(\NlwInverterSignal_U1/Channel0<7>_MC.D2_PT_2/IN2 ),
    .I3(\U1/Channel0 [6]),
    .O(\U1/Channel0<7>_MC.D2_PT_2 )
  );
  X_OR3 \U1/Channel0<7>_MC.D2_1163  (
    .I0(\U1/Channel0<7>_MC.D2_PT_0 ),
    .I1(\U1/Channel0<7>_MC.D2_PT_1 ),
    .I2(\U1/Channel0<7>_MC.D2_PT_2 ),
    .O(\U1/Channel0<7>_MC.D2 )
  );
  X_BUF DCOR0THRESHIGHr_1164 (
    .I(\DCOR0THRESHIGHr_MC.Q ),
    .O(DCOR0THRESHIGHr)
  );
  X_BUF \DCOR0THRESHIGHr_MC.Q_1165  (
    .I(\DCOR0THRESHIGHr_MC.D ),
    .O(\DCOR0THRESHIGHr_MC.Q )
  );
  X_XOR2 \DCOR0THRESHIGHr_MC.D_1166  (
    .I0(\DCOR0THRESHIGHr_MC.D1 ),
    .I1(\DCOR0THRESHIGHr_MC.D2 ),
    .O(\DCOR0THRESHIGHr_MC.D )
  );
  X_AND16 \DCOR0THRESHIGHr_MC.D1_1167  (
    .I0(\WR_II/UIM ),
    .I1(\NlwInverterSignal_DCOR0THRESHIGHr_MC.D1/IN1 ),
    .I2(U2_ADDR_reg[0]),
    .I3(\NlwInverterSignal_DCOR0THRESHIGHr_MC.D1/IN3 ),
    .I4(\NlwInverterSignal_DCOR0THRESHIGHr_MC.D1/IN4 ),
    .I5(\NlwInverterSignal_DCOR0THRESHIGHr_MC.D1/IN5 ),
    .I6(\NlwInverterSignal_DCOR0THRESHIGHr_MC.D1/IN6 ),
    .I7(U2_ADDR_reg[3]),
    .I8(\NlwInverterSignal_DCOR0THRESHIGHr_MC.D1/IN8 ),
    .I9(\NlwInverterSignal_DCOR0THRESHIGHr_MC.D1/IN9 ),
    .I10(Vcc),
    .I11(Vcc),
    .I12(Vcc),
    .I13(Vcc),
    .I14(Vcc),
    .I15(Vcc),
    .O(\DCOR0THRESHIGHr_MC.D1 )
  );
  X_ZERO \DCOR0THRESHIGHr_MC.D2_1168  (
    .O(\DCOR0THRESHIGHr_MC.D2 )
  );
  X_BUF \U1/U4/Latch1r<0>  (
    .I(\U1/U4/Latch1r<0>_MC.Q ),
    .O(\U1/U4/Latch1r [0])
  );
  X_FF \U1/U4/Latch1r<0>_MC.REG  (
    .I(\U1/U4/Latch1r<0>_MC.D ),
    .CE(Vcc),
    .CLK(\U1/U4/Latch1r<0>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\U1/U4/Latch1r<0>_MC.Q )
  );
  X_INV \U1/U4/Latch1r<0>_MC.REG_tsimcreated_inv_Mclk_II/FCLK_1169  (
    .I(\Mclk_II/FCLK ),
    .O(\U1/U4/Latch1r<0>_MC.REG_tsimcreated_inv_Mclk_II/FCLK )
  );
  X_XOR2 \U1/U4/Latch1r<0>_MC.D_1170  (
    .I0(\U1/U4/Latch1r<0>_MC.D1 ),
    .I1(\U1/U4/Latch1r<0>_MC.D2 ),
    .O(\U1/U4/Latch1r<0>_MC.D )
  );
  X_ZERO \U1/U4/Latch1r<0>_MC.D1_1171  (
    .O(\U1/U4/Latch1r<0>_MC.D1 )
  );
  X_AND2 \U1/U4/Latch1r<0>_MC.D2_PT_0_1172  (
    .I0(\U1/U4/Latch1r [0]),
    .I1(N_PZ_964),
    .O(\U1/U4/Latch1r<0>_MC.D2_PT_0 )
  );
  X_AND4 \U1/U4/Latch1r<0>_MC.D2_PT_1_1173  (
    .I0(\MSPReset_II/UIM ),
    .I1(\NlwInverterSignal_U1/U4/Latch1r<0>_MC.D2_PT_1/IN1 ),
    .I2(\NlwInverterSignal_U1/U4/Latch1r<0>_MC.D2_PT_1/IN2 ),
    .I3(\U1/Channel1 [0]),
    .O(\U1/U4/Latch1r<0>_MC.D2_PT_1 )
  );
  X_OR2 \U1/U4/Latch1r<0>_MC.D2_1174  (
    .I0(\U1/U4/Latch1r<0>_MC.D2_PT_0 ),
    .I1(\U1/U4/Latch1r<0>_MC.D2_PT_1 ),
    .O(\U1/U4/Latch1r<0>_MC.D2 )
  );
  X_BUF \U1/Channel1<0>  (
    .I(\U1/Channel1<0>_MC.Q ),
    .O(\U1/Channel1 [0])
  );
  X_FF \U1/Channel1<0>_MC.REG  (
    .I(\U1/Channel1<0>_MC.D ),
    .CE(Vcc),
    .CLK(\Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\U1/Channel1<0>_MC.Q )
  );
  X_XOR2 \U1/Channel1<0>_MC.D_1175  (
    .I0(\U1/Channel1<0>_MC.D1 ),
    .I1(\U1/Channel1<0>_MC.D2 ),
    .O(\U1/Channel1<0>_MC.D )
  );
  X_ZERO \U1/Channel1<0>_MC.D1_1176  (
    .O(\U1/Channel1<0>_MC.D1 )
  );
  X_AND4 \U1/Channel1<0>_MC.D2_PT_0_1177  (
    .I0(\MSPReset_II/UIM ),
    .I1(\U1/Channel1 [0]),
    .I2(\NlwInverterSignal_U1/Channel1<0>_MC.D2_PT_0/IN2 ),
    .I3(\NlwInverterSignal_U1/Channel1<0>_MC.D2_PT_0/IN3 ),
    .O(\U1/Channel1<0>_MC.D2_PT_0 )
  );
  X_AND4 \U1/Channel1<0>_MC.D2_PT_1_1178  (
    .I0(\MSPReset_II/UIM ),
    .I1(\NlwInverterSignal_U1/Channel1<0>_MC.D2_PT_1/IN1 ),
    .I2(\NlwInverterSignal_U1/Channel1<0>_MC.D2_PT_1/IN2 ),
    .I3(N_PZ_1155),
    .O(\U1/Channel1<0>_MC.D2_PT_1 )
  );
  X_OR2 \U1/Channel1<0>_MC.D2_1179  (
    .I0(\U1/Channel1<0>_MC.D2_PT_0 ),
    .I1(\U1/Channel1<0>_MC.D2_PT_1 ),
    .O(\U1/Channel1<0>_MC.D2 )
  );
  X_BUF \U1/Zero1_1180  (
    .I(\U1/Zero1_MC.Q ),
    .O(\U1/Zero1 )
  );
  X_FF \U1/Zero1_MC.REG  (
    .I(\U1/Zero1_MC.D ),
    .CE(Vcc),
    .CLK(\U1/Zero1_MC.REG_tsimcreated_inv_Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\U1/Zero1_MC.Q )
  );
  X_INV \U1/Zero1_MC.REG_tsimcreated_inv_Mclk_II/FCLK_1181  (
    .I(\Mclk_II/FCLK ),
    .O(\U1/Zero1_MC.REG_tsimcreated_inv_Mclk_II/FCLK )
  );
  X_XOR2 \U1/Zero1_MC.D_1182  (
    .I0(\U1/Zero1_MC.D1 ),
    .I1(\U1/Zero1_MC.D2 ),
    .O(\U1/Zero1_MC.D )
  );
  X_ZERO \U1/Zero1_MC.D1_1183  (
    .O(\U1/Zero1_MC.D1 )
  );
  X_AND2 \U1/Zero1_MC.D2_PT_0_1184  (
    .I0(\NlwInverterSignal_U1/Zero1_MC.D2_PT_0/IN0 ),
    .I1(\U1/Zero1 ),
    .O(\U1/Zero1_MC.D2_PT_0 )
  );
  X_AND2 \U1/Zero1_MC.D2_PT_1_1185  (
    .I0(N_PZ_964),
    .I1(\NlwInverterSignal_U1/Zero1_MC.D2_PT_1/IN1 ),
    .O(\U1/Zero1_MC.D2_PT_1 )
  );
  X_AND7 \U1/Zero1_MC.D2_PT_2_1186  (
    .I0(\MSPReset_II/UIM ),
    .I1(\NlwInverterSignal_U1/Zero1_MC.D2_PT_2/IN1 ),
    .I2(\U1/U4/RF1r ),
    .I3(\U1/U4/E1r ),
    .I4(\U1/U4/HE1stater ),
    .I5(\NlwInverterSignal_U1/Zero1_MC.D2_PT_2/IN5 ),
    .I6(\NlwInverterSignal_U1/Zero1_MC.D2_PT_2/IN6 ),
    .O(\U1/Zero1_MC.D2_PT_2 )
  );
  X_AND7 \U1/Zero1_MC.D2_PT_3_1187  (
    .I0(\MSPReset_II/UIM ),
    .I1(\NlwInverterSignal_U1/Zero1_MC.D2_PT_3/IN1 ),
    .I2(\NlwInverterSignal_U1/Zero1_MC.D2_PT_3/IN2 ),
    .I3(\U1/U4/E1r ),
    .I4(\NlwInverterSignal_U1/Zero1_MC.D2_PT_3/IN4 ),
    .I5(\U1/U4/HE1statelastr ),
    .I6(\NlwInverterSignal_U1/Zero1_MC.D2_PT_3/IN6 ),
    .O(\U1/Zero1_MC.D2_PT_3 )
  );
  X_OR4 \U1/Zero1_MC.D2_1188  (
    .I0(\U1/Zero1_MC.D2_PT_0 ),
    .I1(\U1/Zero1_MC.D2_PT_1 ),
    .I2(\U1/Zero1_MC.D2_PT_2 ),
    .I3(\U1/Zero1_MC.D2_PT_3 ),
    .O(\U1/Zero1_MC.D2 )
  );
  X_BUF N_PZ_933_1189 (
    .I(\N_PZ_933_MC.Q ),
    .O(N_PZ_933)
  );
  X_BUF \N_PZ_933_MC.Q_1190  (
    .I(\N_PZ_933_MC.D ),
    .O(\N_PZ_933_MC.Q )
  );
  X_XOR2 \N_PZ_933_MC.D_1191  (
    .I0(\N_PZ_933_MC.D1 ),
    .I1(\N_PZ_933_MC.D2 ),
    .O(\N_PZ_933_MC.D )
  );
  X_AND2 \N_PZ_933_MC.D1_1192  (
    .I0(\MSPReset_II/UIM ),
    .I1(\NlwInverterSignal_N_PZ_933_MC.D1/IN1 ),
    .O(\N_PZ_933_MC.D1 )
  );
  X_ZERO \N_PZ_933_MC.D2_1193  (
    .O(\N_PZ_933_MC.D2 )
  );
  X_BUF N_PZ_1155_1194 (
    .I(\N_PZ_1155_MC.Q ),
    .O(N_PZ_1155)
  );
  X_BUF \N_PZ_1155_MC.Q_1195  (
    .I(\N_PZ_1155_MC.D ),
    .O(\N_PZ_1155_MC.Q )
  );
  X_XOR2 \N_PZ_1155_MC.D_1196  (
    .I0(\N_PZ_1155_MC.D1 ),
    .I1(\N_PZ_1155_MC.D2 ),
    .O(\N_PZ_1155_MC.D )
  );
  X_ZERO \N_PZ_1155_MC.D1_1197  (
    .O(\N_PZ_1155_MC.D1 )
  );
  X_AND4 \N_PZ_1155_MC.D2_PT_0_1198  (
    .I0(\U1/U6/CurrState_Sreg0_FFD1 ),
    .I1(\U1/U6/CurrState_Sreg0_FFD3 ),
    .I2(\NlwInverterSignal_N_PZ_1155_MC.D2_PT_0/IN2 ),
    .I3(\NlwInverterSignal_N_PZ_1155_MC.D2_PT_0/IN3 ),
    .O(\N_PZ_1155_MC.D2_PT_0 )
  );
  X_AND4 \N_PZ_1155_MC.D2_PT_1_1199  (
    .I0(\NlwInverterSignal_N_PZ_1155_MC.D2_PT_1/IN0 ),
    .I1(\U1/U6/CurrState_Sreg0_FFD3 ),
    .I2(\NlwInverterSignal_N_PZ_1155_MC.D2_PT_1/IN2 ),
    .I3(\U1/U6/CurrState_Sreg0_FFD4 ),
    .O(\N_PZ_1155_MC.D2_PT_1 )
  );
  X_OR2 \N_PZ_1155_MC.D2_1200  (
    .I0(\N_PZ_1155_MC.D2_PT_0 ),
    .I1(\N_PZ_1155_MC.D2_PT_1 ),
    .O(\N_PZ_1155_MC.D2 )
  );
  X_BUF \U1/U6/CurrState_Sreg0_FFD1_1201  (
    .I(\U1/U6/CurrState_Sreg0_FFD1_MC.Q ),
    .O(\U1/U6/CurrState_Sreg0_FFD1 )
  );
  X_FF \U1/U6/CurrState_Sreg0_FFD1_MC.REG  (
    .I(\U1/U6/CurrState_Sreg0_FFD1_MC.D ),
    .CE(Vcc),
    .CLK(\Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\U1/U6/CurrState_Sreg0_FFD1_MC.Q )
  );
  X_XOR2 \U1/U6/CurrState_Sreg0_FFD1_MC.D_1202  (
    .I0(\U1/U6/CurrState_Sreg0_FFD1_MC.D1 ),
    .I1(\U1/U6/CurrState_Sreg0_FFD1_MC.D2 ),
    .O(\U1/U6/CurrState_Sreg0_FFD1_MC.D )
  );
  X_ZERO \U1/U6/CurrState_Sreg0_FFD1_MC.D1_1203  (
    .O(\U1/U6/CurrState_Sreg0_FFD1_MC.D1 )
  );
  X_AND4 \U1/U6/CurrState_Sreg0_FFD1_MC.D2_PT_0_1204  (
    .I0(\MSPReset_II/UIM ),
    .I1(\U1/U6/CurrState_Sreg0_FFD1 ),
    .I2(\U1/U6/CurrState_Sreg0_FFD2 ),
    .I3(\NlwInverterSignal_U1/U6/CurrState_Sreg0_FFD1_MC.D2_PT_0/IN3 ),
    .O(\U1/U6/CurrState_Sreg0_FFD1_MC.D2_PT_0 )
  );
  X_AND5 \U1/U6/CurrState_Sreg0_FFD1_MC.D2_PT_1_1205  (
    .I0(\MSPReset_II/UIM ),
    .I1(\PhaseA_Encoder1_II/UIM ),
    .I2(\U1/U6/CurrState_Sreg0_FFD1 ),
    .I3(\NlwInverterSignal_U1/U6/CurrState_Sreg0_FFD1_MC.D2_PT_1/IN3 ),
    .I4(\NlwInverterSignal_U1/U6/CurrState_Sreg0_FFD1_MC.D2_PT_1/IN4 ),
    .O(\U1/U6/CurrState_Sreg0_FFD1_MC.D2_PT_1 )
  );
  X_AND6 \U1/U6/CurrState_Sreg0_FFD1_MC.D2_PT_2_1206  (
    .I0(\MSPReset_II/UIM ),
    .I1(\NlwInverterSignal_U1/U6/CurrState_Sreg0_FFD1_MC.D2_PT_2/IN1 ),
    .I2(\PhaseB_Encoder1_II/UIM ),
    .I3(\NlwInverterSignal_U1/U6/CurrState_Sreg0_FFD1_MC.D2_PT_2/IN3 ),
    .I4(\NlwInverterSignal_U1/U6/CurrState_Sreg0_FFD1_MC.D2_PT_2/IN4 ),
    .I5(\NlwInverterSignal_U1/U6/CurrState_Sreg0_FFD1_MC.D2_PT_2/IN5 ),
    .O(\U1/U6/CurrState_Sreg0_FFD1_MC.D2_PT_2 )
  );
  X_OR3 \U1/U6/CurrState_Sreg0_FFD1_MC.D2_1207  (
    .I0(\U1/U6/CurrState_Sreg0_FFD1_MC.D2_PT_0 ),
    .I1(\U1/U6/CurrState_Sreg0_FFD1_MC.D2_PT_1 ),
    .I2(\U1/U6/CurrState_Sreg0_FFD1_MC.D2_PT_2 ),
    .O(\U1/U6/CurrState_Sreg0_FFD1_MC.D2 )
  );
  X_BUF \U1/U6/CurrState_Sreg0_FFD3_1208  (
    .I(\U1/U6/CurrState_Sreg0_FFD3_MC.Q ),
    .O(\U1/U6/CurrState_Sreg0_FFD3 )
  );
  X_FF \U1/U6/CurrState_Sreg0_FFD3_MC.REG  (
    .I(\U1/U6/CurrState_Sreg0_FFD3_MC.D ),
    .CE(Vcc),
    .CLK(\Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\U1/U6/CurrState_Sreg0_FFD3_MC.Q )
  );
  X_XOR2 \U1/U6/CurrState_Sreg0_FFD3_MC.D_1209  (
    .I0(\U1/U6/CurrState_Sreg0_FFD3_MC.D1 ),
    .I1(\U1/U6/CurrState_Sreg0_FFD3_MC.D2 ),
    .O(\U1/U6/CurrState_Sreg0_FFD3_MC.D )
  );
  X_ZERO \U1/U6/CurrState_Sreg0_FFD3_MC.D1_1210  (
    .O(\U1/U6/CurrState_Sreg0_FFD3_MC.D1 )
  );
  X_AND5 \U1/U6/CurrState_Sreg0_FFD3_MC.D2_PT_0_1211  (
    .I0(\MSPReset_II/UIM ),
    .I1(\PhaseA_Encoder1_II/UIM ),
    .I2(\U1/U6/CurrState_Sreg0_FFD2 ),
    .I3(\NlwInverterSignal_U1/U6/CurrState_Sreg0_FFD3_MC.D2_PT_0/IN3 ),
    .I4(N_PZ_1107),
    .O(\U1/U6/CurrState_Sreg0_FFD3_MC.D2_PT_0 )
  );
  X_AND5 \U1/U6/CurrState_Sreg0_FFD3_MC.D2_PT_1_1212  (
    .I0(\MSPReset_II/UIM ),
    .I1(\NlwInverterSignal_U1/U6/CurrState_Sreg0_FFD3_MC.D2_PT_1/IN1 ),
    .I2(\U1/U6/CurrState_Sreg0_FFD3 ),
    .I3(\U1/U6/CurrState_Sreg0_FFD2 ),
    .I4(\NlwInverterSignal_U1/U6/CurrState_Sreg0_FFD3_MC.D2_PT_1/IN4 ),
    .O(\U1/U6/CurrState_Sreg0_FFD3_MC.D2_PT_1 )
  );
  X_AND5 \U1/U6/CurrState_Sreg0_FFD3_MC.D2_PT_2_1213  (
    .I0(\MSPReset_II/UIM ),
    .I1(\NlwInverterSignal_U1/U6/CurrState_Sreg0_FFD3_MC.D2_PT_2/IN1 ),
    .I2(\U1/U6/CurrState_Sreg0_FFD3 ),
    .I3(\NlwInverterSignal_U1/U6/CurrState_Sreg0_FFD3_MC.D2_PT_2/IN3 ),
    .I4(\NlwInverterSignal_U1/U6/CurrState_Sreg0_FFD3_MC.D2_PT_2/IN4 ),
    .O(\U1/U6/CurrState_Sreg0_FFD3_MC.D2_PT_2 )
  );
  X_OR3 \U1/U6/CurrState_Sreg0_FFD3_MC.D2_1214  (
    .I0(\U1/U6/CurrState_Sreg0_FFD3_MC.D2_PT_0 ),
    .I1(\U1/U6/CurrState_Sreg0_FFD3_MC.D2_PT_1 ),
    .I2(\U1/U6/CurrState_Sreg0_FFD3_MC.D2_PT_2 ),
    .O(\U1/U6/CurrState_Sreg0_FFD3_MC.D2 )
  );
  X_BUF \U1/U6/CurrState_Sreg0_FFD2_1215  (
    .I(\U1/U6/CurrState_Sreg0_FFD2_MC.Q ),
    .O(\U1/U6/CurrState_Sreg0_FFD2 )
  );
  X_FF \U1/U6/CurrState_Sreg0_FFD2_MC.REG  (
    .I(\U1/U6/CurrState_Sreg0_FFD2_MC.D ),
    .CE(Vcc),
    .CLK(\Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\U1/U6/CurrState_Sreg0_FFD2_MC.Q )
  );
  X_XOR2 \U1/U6/CurrState_Sreg0_FFD2_MC.D_1216  (
    .I0(\U1/U6/CurrState_Sreg0_FFD2_MC.D1 ),
    .I1(\U1/U6/CurrState_Sreg0_FFD2_MC.D2 ),
    .O(\U1/U6/CurrState_Sreg0_FFD2_MC.D )
  );
  X_ZERO \U1/U6/CurrState_Sreg0_FFD2_MC.D1_1217  (
    .O(\U1/U6/CurrState_Sreg0_FFD2_MC.D1 )
  );
  X_AND5 \U1/U6/CurrState_Sreg0_FFD2_MC.D2_PT_0_1218  (
    .I0(\MSPReset_II/UIM ),
    .I1(\PhaseA_Encoder1_II/UIM ),
    .I2(\NlwInverterSignal_U1/U6/CurrState_Sreg0_FFD2_MC.D2_PT_0/IN2 ),
    .I3(\NlwInverterSignal_U1/U6/CurrState_Sreg0_FFD2_MC.D2_PT_0/IN3 ),
    .I4(\NlwInverterSignal_U1/U6/CurrState_Sreg0_FFD2_MC.D2_PT_0/IN4 ),
    .O(\U1/U6/CurrState_Sreg0_FFD2_MC.D2_PT_0 )
  );
  X_AND5 \U1/U6/CurrState_Sreg0_FFD2_MC.D2_PT_1_1219  (
    .I0(\MSPReset_II/UIM ),
    .I1(\U1/U6/CurrState_Sreg0_FFD3 ),
    .I2(\U1/U6/CurrState_Sreg0_FFD2 ),
    .I3(\NlwInverterSignal_U1/U6/CurrState_Sreg0_FFD2_MC.D2_PT_1/IN3 ),
    .I4(\NlwInverterSignal_U1/U6/CurrState_Sreg0_FFD2_MC.D2_PT_1/IN4 ),
    .O(\U1/U6/CurrState_Sreg0_FFD2_MC.D2_PT_1 )
  );
  X_AND5 \U1/U6/CurrState_Sreg0_FFD2_MC.D2_PT_2_1220  (
    .I0(\MSPReset_II/UIM ),
    .I1(\NlwInverterSignal_U1/U6/CurrState_Sreg0_FFD2_MC.D2_PT_2/IN1 ),
    .I2(\U1/U6/CurrState_Sreg0_FFD2 ),
    .I3(\NlwInverterSignal_U1/U6/CurrState_Sreg0_FFD2_MC.D2_PT_2/IN3 ),
    .I4(N_PZ_1107),
    .O(\U1/U6/CurrState_Sreg0_FFD2_MC.D2_PT_2 )
  );
  X_AND6 \U1/U6/CurrState_Sreg0_FFD2_MC.D2_PT_3_1221  (
    .I0(\MSPReset_II/UIM ),
    .I1(\PhaseA_Encoder1_II/UIM ),
    .I2(\NlwInverterSignal_U1/U6/CurrState_Sreg0_FFD2_MC.D2_PT_3/IN2 ),
    .I3(\U1/U6/CurrState_Sreg0_FFD3 ),
    .I4(\NlwInverterSignal_U1/U6/CurrState_Sreg0_FFD2_MC.D2_PT_3/IN4 ),
    .I5(N_PZ_1107),
    .O(\U1/U6/CurrState_Sreg0_FFD2_MC.D2_PT_3 )
  );
  X_OR4 \U1/U6/CurrState_Sreg0_FFD2_MC.D2_1222  (
    .I0(\U1/U6/CurrState_Sreg0_FFD2_MC.D2_PT_0 ),
    .I1(\U1/U6/CurrState_Sreg0_FFD2_MC.D2_PT_1 ),
    .I2(\U1/U6/CurrState_Sreg0_FFD2_MC.D2_PT_2 ),
    .I3(\U1/U6/CurrState_Sreg0_FFD2_MC.D2_PT_3 ),
    .O(\U1/U6/CurrState_Sreg0_FFD2_MC.D2 )
  );
  X_BUF \U1/U6/CurrState_Sreg0_FFD4_1223  (
    .I(\U1/U6/CurrState_Sreg0_FFD4_MC.Q ),
    .O(\U1/U6/CurrState_Sreg0_FFD4 )
  );
  X_FF \U1/U6/CurrState_Sreg0_FFD4_MC.REG  (
    .I(\U1/U6/CurrState_Sreg0_FFD4_MC.D ),
    .CE(Vcc),
    .CLK(\Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\U1/U6/CurrState_Sreg0_FFD4_MC.Q )
  );
  X_XOR2 \U1/U6/CurrState_Sreg0_FFD4_MC.D_1224  (
    .I0(\U1/U6/CurrState_Sreg0_FFD4_MC.D1 ),
    .I1(\U1/U6/CurrState_Sreg0_FFD4_MC.D2 ),
    .O(\U1/U6/CurrState_Sreg0_FFD4_MC.D )
  );
  X_AND7 \U1/U6/CurrState_Sreg0_FFD4_MC.D1_1225  (
    .I0(\MSPReset_II/UIM ),
    .I1(\NlwInverterSignal_U1/U6/CurrState_Sreg0_FFD4_MC.D1/IN1 ),
    .I2(\NlwInverterSignal_U1/U6/CurrState_Sreg0_FFD4_MC.D1/IN2 ),
    .I3(\NlwInverterSignal_U1/U6/CurrState_Sreg0_FFD4_MC.D1/IN3 ),
    .I4(\U1/U6/CurrState_Sreg0_FFD3 ),
    .I5(\NlwInverterSignal_U1/U6/CurrState_Sreg0_FFD4_MC.D1/IN5 ),
    .I6(\NlwInverterSignal_U1/U6/CurrState_Sreg0_FFD4_MC.D1/IN6 ),
    .O(\U1/U6/CurrState_Sreg0_FFD4_MC.D1 )
  );
  X_ZERO \U1/U6/CurrState_Sreg0_FFD4_MC.D2_1226  (
    .O(\U1/U6/CurrState_Sreg0_FFD4_MC.D2 )
  );
  X_BUF N_PZ_1107_1227 (
    .I(\N_PZ_1107_MC.Q ),
    .O(N_PZ_1107)
  );
  X_BUF \N_PZ_1107_MC.Q_1228  (
    .I(\N_PZ_1107_MC.D ),
    .O(\N_PZ_1107_MC.Q )
  );
  X_XOR2 \N_PZ_1107_MC.D_1229  (
    .I0(\N_PZ_1107_MC.D1 ),
    .I1(\N_PZ_1107_MC.D2 ),
    .O(\N_PZ_1107_MC.D )
  );
  X_ZERO \N_PZ_1107_MC.D1_1230  (
    .O(\N_PZ_1107_MC.D1 )
  );
  X_AND2 \N_PZ_1107_MC.D2_PT_0_1231  (
    .I0(\PhaseB_Encoder1_II/UIM ),
    .I1(\NlwInverterSignal_N_PZ_1107_MC.D2_PT_0/IN1 ),
    .O(\N_PZ_1107_MC.D2_PT_0 )
  );
  X_AND2 \N_PZ_1107_MC.D2_PT_1_1232  (
    .I0(\NlwInverterSignal_N_PZ_1107_MC.D2_PT_1/IN0 ),
    .I1(\U1/U6/CurrState_Sreg0_FFD1 ),
    .O(\N_PZ_1107_MC.D2_PT_1 )
  );
  X_OR2 \N_PZ_1107_MC.D2_1233  (
    .I0(\N_PZ_1107_MC.D2_PT_0 ),
    .I1(\N_PZ_1107_MC.D2_PT_1 ),
    .O(\N_PZ_1107_MC.D2 )
  );
  X_BUF DCOR1THRESLOWr_1234 (
    .I(\DCOR1THRESLOWr_MC.Q ),
    .O(DCOR1THRESLOWr)
  );
  X_BUF \DCOR1THRESLOWr_MC.Q_1235  (
    .I(\DCOR1THRESLOWr_MC.D ),
    .O(\DCOR1THRESLOWr_MC.Q )
  );
  X_XOR2 \DCOR1THRESLOWr_MC.D_1236  (
    .I0(\DCOR1THRESLOWr_MC.D1 ),
    .I1(\DCOR1THRESLOWr_MC.D2 ),
    .O(\DCOR1THRESLOWr_MC.D )
  );
  X_AND16 \DCOR1THRESLOWr_MC.D1_1237  (
    .I0(\WR_II/UIM ),
    .I1(\NlwInverterSignal_DCOR1THRESLOWr_MC.D1/IN1 ),
    .I2(\NlwInverterSignal_DCOR1THRESLOWr_MC.D1/IN2 ),
    .I3(\NlwInverterSignal_DCOR1THRESLOWr_MC.D1/IN3 ),
    .I4(\NlwInverterSignal_DCOR1THRESLOWr_MC.D1/IN4 ),
    .I5(\NlwInverterSignal_DCOR1THRESLOWr_MC.D1/IN5 ),
    .I6(\NlwInverterSignal_DCOR1THRESLOWr_MC.D1/IN6 ),
    .I7(U2_ADDR_reg[3]),
    .I8(U2_ADDR_reg[1]),
    .I9(\NlwInverterSignal_DCOR1THRESLOWr_MC.D1/IN9 ),
    .I10(Vcc),
    .I11(Vcc),
    .I12(Vcc),
    .I13(Vcc),
    .I14(Vcc),
    .I15(Vcc),
    .O(\DCOR1THRESLOWr_MC.D1 )
  );
  X_ZERO \DCOR1THRESLOWr_MC.D2_1238  (
    .O(\DCOR1THRESLOWr_MC.D2 )
  );
  X_BUF \U1/U4/Latch1r<8>  (
    .I(\U1/U4/Latch1r<8>_MC.Q ),
    .O(\U1/U4/Latch1r [8])
  );
  X_FF \U1/U4/Latch1r<8>_MC.REG  (
    .I(\U1/U4/Latch1r<8>_MC.D ),
    .CE(Vcc),
    .CLK(\U1/U4/Latch1r<8>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\U1/U4/Latch1r<8>_MC.Q )
  );
  X_INV \U1/U4/Latch1r<8>_MC.REG_tsimcreated_inv_Mclk_II/FCLK_1239  (
    .I(\Mclk_II/FCLK ),
    .O(\U1/U4/Latch1r<8>_MC.REG_tsimcreated_inv_Mclk_II/FCLK )
  );
  X_XOR2 \U1/U4/Latch1r<8>_MC.D_1240  (
    .I0(\U1/U4/Latch1r<8>_MC.D1 ),
    .I1(\U1/U4/Latch1r<8>_MC.D2 ),
    .O(\U1/U4/Latch1r<8>_MC.D )
  );
  X_ZERO \U1/U4/Latch1r<8>_MC.D1_1241  (
    .O(\U1/U4/Latch1r<8>_MC.D1 )
  );
  X_AND2 \U1/U4/Latch1r<8>_MC.D2_PT_0_1242  (
    .I0(\U1/U4/Latch1r [8]),
    .I1(N_PZ_964),
    .O(\U1/U4/Latch1r<8>_MC.D2_PT_0 )
  );
  X_AND4 \U1/U4/Latch1r<8>_MC.D2_PT_1_1243  (
    .I0(\MSPReset_II/UIM ),
    .I1(\NlwInverterSignal_U1/U4/Latch1r<8>_MC.D2_PT_1/IN1 ),
    .I2(\NlwInverterSignal_U1/U4/Latch1r<8>_MC.D2_PT_1/IN2 ),
    .I3(\U1/Channel1 [8]),
    .O(\U1/U4/Latch1r<8>_MC.D2_PT_1 )
  );
  X_OR2 \U1/U4/Latch1r<8>_MC.D2_1244  (
    .I0(\U1/U4/Latch1r<8>_MC.D2_PT_0 ),
    .I1(\U1/U4/Latch1r<8>_MC.D2_PT_1 ),
    .O(\U1/U4/Latch1r<8>_MC.D2 )
  );
  X_BUF \U1/Channel1<8>  (
    .I(\U1/Channel1<8>_MC.Q ),
    .O(\U1/Channel1 [8])
  );
  X_XOR2 \U1/Channel1<8>_MC_tsimcreated_xor__1245  (
    .I0(\U1/Channel1<8>_MC.D ),
    .I1(\U1/Channel1<8>_MC.Q ),
    .O(\U1/Channel1<8>_MC_tsimcreated_xor_ )
  );
  X_FF \U1/Channel1<8>_MC.REG  (
    .I(\U1/Channel1<8>_MC_tsimcreated_xor_ ),
    .CE(Vcc),
    .CLK(\Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\U1/Channel1<8>_MC.Q )
  );
  X_XOR2 \U1/Channel1<8>_MC.D_1246  (
    .I0(\U1/Channel1<8>_MC.D1 ),
    .I1(\U1/Channel1<8>_MC.D2 ),
    .O(\U1/Channel1<8>_MC.D )
  );
  X_ZERO \U1/Channel1<8>_MC.D1_1247  (
    .O(\U1/Channel1<8>_MC.D1 )
  );
  X_AND2 \U1/Channel1<8>_MC.D2_PT_0_1248  (
    .I0(\NlwInverterSignal_U1/Channel1<8>_MC.D2_PT_0/IN0 ),
    .I1(\U1/Channel1 [8]),
    .O(\U1/Channel1<8>_MC.D2_PT_0 )
  );
  X_AND4 \U1/Channel1<8>_MC.D2_PT_1_1249  (
    .I0(\U1/Channel1 [8]),
    .I1(N_PZ_1016),
    .I2(\NlwInverterSignal_U1/Channel1<8>_MC.D2_PT_1/IN2 ),
    .I3(\NlwInverterSignal_U1/Channel1<8>_MC.D2_PT_1/IN3 ),
    .O(\U1/Channel1<8>_MC.D2_PT_1 )
  );
  X_AND6 \U1/Channel1<8>_MC.D2_PT_2_1250  (
    .I0(\MSPReset_II/UIM ),
    .I1(\NlwInverterSignal_U1/Channel1<8>_MC.D2_PT_2/IN1 ),
    .I2(N_PZ_1155),
    .I3(\NlwInverterSignal_U1/Channel1<8>_MC.D2_PT_2/IN3 ),
    .I4(\NlwInverterSignal_U1/Channel1<8>_MC.D2_PT_2/IN4 ),
    .I5(\U1/U5/location_Maddsub__n0000__n0075 [0]),
    .O(\U1/Channel1<8>_MC.D2_PT_2 )
  );
  X_AND6 \U1/Channel1<8>_MC.D2_PT_3_1251  (
    .I0(\U1/Channel1 [8]),
    .I1(N_PZ_1016),
    .I2(\NlwInverterSignal_U1/Channel1<8>_MC.D2_PT_3/IN2 ),
    .I3(\U1/Channel1 [5]),
    .I4(\NlwInverterSignal_U1/Channel1<8>_MC.D2_PT_3/IN4 ),
    .I5(\U1/Channel1 [6]),
    .O(\U1/Channel1<8>_MC.D2_PT_3 )
  );
  X_AND7 \U1/Channel1<8>_MC.D2_PT_4_1252  (
    .I0(N_PZ_1155),
    .I1(\U1/Channel1 [8]),
    .I2(\NlwInverterSignal_U1/Channel1<8>_MC.D2_PT_4/IN2 ),
    .I3(\NlwInverterSignal_U1/Channel1<8>_MC.D2_PT_4/IN3 ),
    .I4(\NlwInverterSignal_U1/Channel1<8>_MC.D2_PT_4/IN4 ),
    .I5(\U1/U5/location_Maddsub__n0000__n0067 [0]),
    .I6(\NlwInverterSignal_U1/Channel1<8>_MC.D2_PT_4/IN6 ),
    .O(\U1/Channel1<8>_MC.D2_PT_4 )
  );
  X_AND16 \U1/Channel1<8>_MC.D2_PT_5_1253  (
    .I0(\MSPReset_II/UIM ),
    .I1(\NlwInverterSignal_U1/Channel1<8>_MC.D2_PT_5/IN1 ),
    .I2(N_PZ_1155),
    .I3(\NlwInverterSignal_U1/Channel1<8>_MC.D2_PT_5/IN3 ),
    .I4(\U1/Channel1 [7]),
    .I5(\U1/U5/location_Maddsub__n0000__n0075 [0]),
    .I6(\U1/Channel1 [5]),
    .I7(\NlwInverterSignal_U1/Channel1<8>_MC.D2_PT_5/IN7 ),
    .I8(\U1/Channel1 [6]),
    .I9(Vcc),
    .I10(Vcc),
    .I11(Vcc),
    .I12(Vcc),
    .I13(Vcc),
    .I14(Vcc),
    .I15(Vcc),
    .O(\U1/Channel1<8>_MC.D2_PT_5 )
  );
  X_OR6 \U1/Channel1<8>_MC.D2_1254  (
    .I0(\U1/Channel1<8>_MC.D2_PT_0 ),
    .I1(\U1/Channel1<8>_MC.D2_PT_1 ),
    .I2(\U1/Channel1<8>_MC.D2_PT_2 ),
    .I3(\U1/Channel1<8>_MC.D2_PT_3 ),
    .I4(\U1/Channel1<8>_MC.D2_PT_4 ),
    .I5(\U1/Channel1<8>_MC.D2_PT_5 ),
    .O(\U1/Channel1<8>_MC.D2 )
  );
  X_BUF \U1/Channel1<5>  (
    .I(\U1/Channel1<5>_MC.Q ),
    .O(\U1/Channel1 [5])
  );
  X_XOR2 \U1/Channel1<5>_MC_tsimcreated_xor__1255  (
    .I0(\U1/Channel1<5>_MC.D ),
    .I1(\U1/Channel1<5>_MC.Q ),
    .O(\U1/Channel1<5>_MC_tsimcreated_xor_ )
  );
  X_FF \U1/Channel1<5>_MC.REG  (
    .I(\U1/Channel1<5>_MC_tsimcreated_xor_ ),
    .CE(Vcc),
    .CLK(\Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\U1/Channel1<5>_MC.Q )
  );
  X_XOR2 \U1/Channel1<5>_MC.D_1256  (
    .I0(\U1/Channel1<5>_MC.D1 ),
    .I1(\U1/Channel1<5>_MC.D2 ),
    .O(\U1/Channel1<5>_MC.D )
  );
  X_ZERO \U1/Channel1<5>_MC.D1_1257  (
    .O(\U1/Channel1<5>_MC.D1 )
  );
  X_AND2 \U1/Channel1<5>_MC.D2_PT_0_1258  (
    .I0(\NlwInverterSignal_U1/Channel1<5>_MC.D2_PT_0/IN0 ),
    .I1(\U1/Channel1 [5]),
    .O(\U1/Channel1<5>_MC.D2_PT_0 )
  );
  X_AND4 \U1/Channel1<5>_MC.D2_PT_1_1259  (
    .I0(\MSPReset_II/UIM ),
    .I1(\NlwInverterSignal_U1/Channel1<5>_MC.D2_PT_1/IN1 ),
    .I2(N_PZ_1016),
    .I3(\NlwInverterSignal_U1/Channel1<5>_MC.D2_PT_1/IN3 ),
    .O(\U1/Channel1<5>_MC.D2_PT_1 )
  );
  X_AND5 \U1/Channel1<5>_MC.D2_PT_2_1260  (
    .I0(\MSPReset_II/UIM ),
    .I1(\NlwInverterSignal_U1/Channel1<5>_MC.D2_PT_2/IN1 ),
    .I2(N_PZ_1155),
    .I3(\NlwInverterSignal_U1/Channel1<5>_MC.D2_PT_2/IN3 ),
    .I4(\U1/U5/location_Maddsub__n0000__n0067 [0]),
    .O(\U1/Channel1<5>_MC.D2_PT_2 )
  );
  X_OR3 \U1/Channel1<5>_MC.D2_1261  (
    .I0(\U1/Channel1<5>_MC.D2_PT_0 ),
    .I1(\U1/Channel1<5>_MC.D2_PT_1 ),
    .I2(\U1/Channel1<5>_MC.D2_PT_2 ),
    .O(\U1/Channel1<5>_MC.D2 )
  );
  X_BUF \U1/U5/location_Maddsub__n0000__n0067<0>  (
    .I(\U1/U5/location_Maddsub__n0000__n0067<0>_MC.Q ),
    .O(\U1/U5/location_Maddsub__n0000__n0067 [0])
  );
  X_BUF \U1/U5/location_Maddsub__n0000__n0067<0>_MC.Q_1262  (
    .I(\U1/U5/location_Maddsub__n0000__n0067<0>_MC.D ),
    .O(\U1/U5/location_Maddsub__n0000__n0067<0>_MC.Q )
  );
  X_XOR2 \U1/U5/location_Maddsub__n0000__n0067<0>_MC.D_1263  (
    .I0(\U1/U5/location_Maddsub__n0000__n0067<0>_MC.D1 ),
    .I1(\U1/U5/location_Maddsub__n0000__n0067<0>_MC.D2 ),
    .O(\U1/U5/location_Maddsub__n0000__n0067<0>_MC.D )
  );
  X_AND2 \U1/U5/location_Maddsub__n0000__n0067<0>_MC.D1_1264  (
    .I0(N_PZ_946),
    .I1(N_PZ_946),
    .O(\U1/U5/location_Maddsub__n0000__n0067<0>_MC.D1 )
  );
  X_AND6 \U1/U5/location_Maddsub__n0000__n0067<0>_MC.D2_PT_0_1265  (
    .I0(\U1/Channel1 [0]),
    .I1(N_PZ_946),
    .I2(\U1/Channel1 [1]),
    .I3(\U1/Channel1 [2]),
    .I4(\U1/Channel1 [3]),
    .I5(\U1/Channel1 [4]),
    .O(\U1/U5/location_Maddsub__n0000__n0067<0>_MC.D2_PT_0 )
  );
  X_AND6 \U1/U5/location_Maddsub__n0000__n0067<0>_MC.D2_PT_1_1266  (
    .I0(\NlwInverterSignal_U1/U5/location_Maddsub__n0000__n0067<0>_MC.D2_PT_1/IN0 ),
    .I1(\NlwInverterSignal_U1/U5/location_Maddsub__n0000__n0067<0>_MC.D2_PT_1/IN1 ),
    .I2(\NlwInverterSignal_U1/U5/location_Maddsub__n0000__n0067<0>_MC.D2_PT_1/IN2 ),
    .I3(\NlwInverterSignal_U1/U5/location_Maddsub__n0000__n0067<0>_MC.D2_PT_1/IN3 ),
    .I4(\NlwInverterSignal_U1/U5/location_Maddsub__n0000__n0067<0>_MC.D2_PT_1/IN4 ),
    .I5(\NlwInverterSignal_U1/U5/location_Maddsub__n0000__n0067<0>_MC.D2_PT_1/IN5 ),
    .O(\U1/U5/location_Maddsub__n0000__n0067<0>_MC.D2_PT_1 )
  );
  X_OR2 \U1/U5/location_Maddsub__n0000__n0067<0>_MC.D2_1267  (
    .I0(\U1/U5/location_Maddsub__n0000__n0067<0>_MC.D2_PT_0 ),
    .I1(\U1/U5/location_Maddsub__n0000__n0067<0>_MC.D2_PT_1 ),
    .O(\U1/U5/location_Maddsub__n0000__n0067<0>_MC.D2 )
  );
  X_BUF N_PZ_946_1268 (
    .I(\N_PZ_946_MC.Q ),
    .O(N_PZ_946)
  );
  X_BUF \N_PZ_946_MC.Q_1269  (
    .I(\N_PZ_946_MC.D ),
    .O(\N_PZ_946_MC.Q )
  );
  X_XOR2 \N_PZ_946_MC.D_1270  (
    .I0(\N_PZ_946_MC.D1 ),
    .I1(\N_PZ_946_MC.D2 ),
    .O(\N_PZ_946_MC.D )
  );
  X_AND2 \N_PZ_946_MC.D1_1271  (
    .I0(\U1/NET3720 ),
    .I1(\U1/NET3720 ),
    .O(\N_PZ_946_MC.D1 )
  );
  X_AND3 \N_PZ_946_MC.D2_PT_0_1272  (
    .I0(\NlwInverterSignal_N_PZ_946_MC.D2_PT_0/IN0 ),
    .I1(\U1/U6/CurrState_Sreg0_FFD3 ),
    .I2(\NlwInverterSignal_N_PZ_946_MC.D2_PT_0/IN2 ),
    .O(\N_PZ_946_MC.D2_PT_0 )
  );
  X_AND3 \N_PZ_946_MC.D2_PT_1_1273  (
    .I0(\NlwInverterSignal_N_PZ_946_MC.D2_PT_1/IN0 ),
    .I1(\U1/U6/CurrState_Sreg0_FFD2 ),
    .I2(\NlwInverterSignal_N_PZ_946_MC.D2_PT_1/IN2 ),
    .O(\N_PZ_946_MC.D2_PT_1 )
  );
  X_OR2 \N_PZ_946_MC.D2_1274  (
    .I0(\N_PZ_946_MC.D2_PT_0 ),
    .I1(\N_PZ_946_MC.D2_PT_1 ),
    .O(\N_PZ_946_MC.D2 )
  );
  X_BUF \U1/NET3720_1275  (
    .I(\U1/NET3720_MC.Q ),
    .O(\U1/NET3720 )
  );
  X_FF \U1/NET3720_MC.REG  (
    .I(\U1/NET3720_MC.D ),
    .CE(Vcc),
    .CLK(\U1/NET3720_MC.REG_tsimcreated_inv_Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\U1/NET3720_MC.Q )
  );
  X_INV \U1/NET3720_MC.REG_tsimcreated_inv_Mclk_II/FCLK_1276  (
    .I(\Mclk_II/FCLK ),
    .O(\U1/NET3720_MC.REG_tsimcreated_inv_Mclk_II/FCLK )
  );
  X_XOR2 \U1/NET3720_MC.D_1277  (
    .I0(\U1/NET3720_MC.D1 ),
    .I1(\U1/NET3720_MC.D2 ),
    .O(\U1/NET3720_MC.D )
  );
  X_ZERO \U1/NET3720_MC.D1_1278  (
    .O(\U1/NET3720_MC.D1 )
  );
  X_AND3 \U1/NET3720_MC.D2_PT_0_1279  (
    .I0(\MSPReset_II/UIM ),
    .I1(\AD<7>_II/UIM ),
    .I2(DCORENCCTLw),
    .O(\U1/NET3720_MC.D2_PT_0 )
  );
  X_AND3 \U1/NET3720_MC.D2_PT_1_1280  (
    .I0(\MSPReset_II/UIM ),
    .I1(\NlwInverterSignal_U1/NET3720_MC.D2_PT_1/IN1 ),
    .I2(\U1/NET3720 ),
    .O(\U1/NET3720_MC.D2_PT_1 )
  );
  X_OR2 \U1/NET3720_MC.D2_1281  (
    .I0(\U1/NET3720_MC.D2_PT_0 ),
    .I1(\U1/NET3720_MC.D2_PT_1 ),
    .O(\U1/NET3720_MC.D2 )
  );
  X_BUF \U1/Channel1<1>  (
    .I(\U1/Channel1<1>_MC.Q ),
    .O(\U1/Channel1 [1])
  );
  X_XOR2 \U1/Channel1<1>_MC_tsimcreated_xor__1282  (
    .I0(\U1/Channel1<1>_MC.D ),
    .I1(\U1/Channel1<1>_MC.Q ),
    .O(\U1/Channel1<1>_MC_tsimcreated_xor_ )
  );
  X_FF \U1/Channel1<1>_MC.REG  (
    .I(\U1/Channel1<1>_MC_tsimcreated_xor_ ),
    .CE(Vcc),
    .CLK(\Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\U1/Channel1<1>_MC.Q )
  );
  X_XOR2 \U1/Channel1<1>_MC.D_1283  (
    .I0(\U1/Channel1<1>_MC.D1 ),
    .I1(\U1/Channel1<1>_MC.D2 ),
    .O(\U1/Channel1<1>_MC.D )
  );
  X_ZERO \U1/Channel1<1>_MC.D1_1284  (
    .O(\U1/Channel1<1>_MC.D1 )
  );
  X_AND2 \U1/Channel1<1>_MC.D2_PT_0_1285  (
    .I0(\NlwInverterSignal_U1/Channel1<1>_MC.D2_PT_0/IN0 ),
    .I1(\U1/Channel1 [1]),
    .O(\U1/Channel1<1>_MC.D2_PT_0 )
  );
  X_AND4 \U1/Channel1<1>_MC.D2_PT_1_1286  (
    .I0(\MSPReset_II/UIM ),
    .I1(\U1/Channel1 [0]),
    .I2(\NlwInverterSignal_U1/Channel1<1>_MC.D2_PT_1/IN2 ),
    .I3(N_PZ_1016),
    .O(\U1/Channel1<1>_MC.D2_PT_1 )
  );
  X_AND5 \U1/Channel1<1>_MC.D2_PT_2_1287  (
    .I0(\MSPReset_II/UIM ),
    .I1(\NlwInverterSignal_U1/Channel1<1>_MC.D2_PT_2/IN1 ),
    .I2(\NlwInverterSignal_U1/Channel1<1>_MC.D2_PT_2/IN2 ),
    .I3(N_PZ_1155),
    .I4(\NlwInverterSignal_U1/Channel1<1>_MC.D2_PT_2/IN4 ),
    .O(\U1/Channel1<1>_MC.D2_PT_2 )
  );
  X_OR3 \U1/Channel1<1>_MC.D2_1288  (
    .I0(\U1/Channel1<1>_MC.D2_PT_0 ),
    .I1(\U1/Channel1<1>_MC.D2_PT_1 ),
    .I2(\U1/Channel1<1>_MC.D2_PT_2 ),
    .O(\U1/Channel1<1>_MC.D2 )
  );
  X_BUF N_PZ_1016_1289 (
    .I(\N_PZ_1016_MC.Q ),
    .O(N_PZ_1016)
  );
  X_BUF \N_PZ_1016_MC.Q_1290  (
    .I(\N_PZ_1016_MC.D ),
    .O(\N_PZ_1016_MC.Q )
  );
  X_XOR2 \N_PZ_1016_MC.D_1291  (
    .I0(\N_PZ_1016_MC.D1 ),
    .I1(\N_PZ_1016_MC.D2 ),
    .O(\N_PZ_1016_MC.D )
  );
  X_ZERO \N_PZ_1016_MC.D1_1292  (
    .O(\N_PZ_1016_MC.D1 )
  );
  X_AND5 \N_PZ_1016_MC.D2_PT_0_1293  (
    .I0(\U1/U6/CurrState_Sreg0_FFD1 ),
    .I1(\U1/U6/CurrState_Sreg0_FFD3 ),
    .I2(\NlwInverterSignal_N_PZ_1016_MC.D2_PT_0/IN2 ),
    .I3(\NlwInverterSignal_N_PZ_1016_MC.D2_PT_0/IN3 ),
    .I4(\U1/NET3720 ),
    .O(\N_PZ_1016_MC.D2_PT_0 )
  );
  X_AND5 \N_PZ_1016_MC.D2_PT_1_1294  (
    .I0(\NlwInverterSignal_N_PZ_1016_MC.D2_PT_1/IN0 ),
    .I1(\U1/U6/CurrState_Sreg0_FFD3 ),
    .I2(\NlwInverterSignal_N_PZ_1016_MC.D2_PT_1/IN2 ),
    .I3(\U1/U6/CurrState_Sreg0_FFD4 ),
    .I4(\NlwInverterSignal_N_PZ_1016_MC.D2_PT_1/IN4 ),
    .O(\N_PZ_1016_MC.D2_PT_1 )
  );
  X_OR2 \N_PZ_1016_MC.D2_1295  (
    .I0(\N_PZ_1016_MC.D2_PT_0 ),
    .I1(\N_PZ_1016_MC.D2_PT_1 ),
    .O(\N_PZ_1016_MC.D2 )
  );
  X_BUF \U1/Channel1<2>  (
    .I(\U1/Channel1<2>_MC.Q ),
    .O(\U1/Channel1 [2])
  );
  X_XOR2 \U1/Channel1<2>_MC_tsimcreated_xor__1296  (
    .I0(\U1/Channel1<2>_MC.D ),
    .I1(\U1/Channel1<2>_MC.Q ),
    .O(\U1/Channel1<2>_MC_tsimcreated_xor_ )
  );
  X_FF \U1/Channel1<2>_MC.REG  (
    .I(\U1/Channel1<2>_MC_tsimcreated_xor_ ),
    .CE(Vcc),
    .CLK(\Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\U1/Channel1<2>_MC.Q )
  );
  X_XOR2 \U1/Channel1<2>_MC.D_1297  (
    .I0(\U1/Channel1<2>_MC.D1 ),
    .I1(\U1/Channel1<2>_MC.D2 ),
    .O(\U1/Channel1<2>_MC.D )
  );
  X_ZERO \U1/Channel1<2>_MC.D1_1298  (
    .O(\U1/Channel1<2>_MC.D1 )
  );
  X_AND2 \U1/Channel1<2>_MC.D2_PT_0_1299  (
    .I0(\NlwInverterSignal_U1/Channel1<2>_MC.D2_PT_0/IN0 ),
    .I1(\U1/Channel1 [2]),
    .O(\U1/Channel1<2>_MC.D2_PT_0 )
  );
  X_AND5 \U1/Channel1<2>_MC.D2_PT_1_1300  (
    .I0(\MSPReset_II/UIM ),
    .I1(\U1/Channel1 [0]),
    .I2(\NlwInverterSignal_U1/Channel1<2>_MC.D2_PT_1/IN2 ),
    .I3(N_PZ_1016),
    .I4(\U1/Channel1 [1]),
    .O(\U1/Channel1<2>_MC.D2_PT_1 )
  );
  X_AND6 \U1/Channel1<2>_MC.D2_PT_2_1301  (
    .I0(\MSPReset_II/UIM ),
    .I1(\NlwInverterSignal_U1/Channel1<2>_MC.D2_PT_2/IN1 ),
    .I2(\NlwInverterSignal_U1/Channel1<2>_MC.D2_PT_2/IN2 ),
    .I3(N_PZ_1155),
    .I4(\NlwInverterSignal_U1/Channel1<2>_MC.D2_PT_2/IN4 ),
    .I5(\NlwInverterSignal_U1/Channel1<2>_MC.D2_PT_2/IN5 ),
    .O(\U1/Channel1<2>_MC.D2_PT_2 )
  );
  X_OR3 \U1/Channel1<2>_MC.D2_1302  (
    .I0(\U1/Channel1<2>_MC.D2_PT_0 ),
    .I1(\U1/Channel1<2>_MC.D2_PT_1 ),
    .I2(\U1/Channel1<2>_MC.D2_PT_2 ),
    .O(\U1/Channel1<2>_MC.D2 )
  );
  X_BUF \U1/Channel1<3>  (
    .I(\U1/Channel1<3>_MC.Q ),
    .O(\U1/Channel1 [3])
  );
  X_XOR2 \U1/Channel1<3>_MC_tsimcreated_xor__1303  (
    .I0(\U1/Channel1<3>_MC.D ),
    .I1(\U1/Channel1<3>_MC.Q ),
    .O(\U1/Channel1<3>_MC_tsimcreated_xor_ )
  );
  X_FF \U1/Channel1<3>_MC.REG  (
    .I(\U1/Channel1<3>_MC_tsimcreated_xor_ ),
    .CE(Vcc),
    .CLK(\Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\U1/Channel1<3>_MC.Q )
  );
  X_XOR2 \U1/Channel1<3>_MC.D_1304  (
    .I0(\U1/Channel1<3>_MC.D1 ),
    .I1(\U1/Channel1<3>_MC.D2 ),
    .O(\U1/Channel1<3>_MC.D )
  );
  X_ZERO \U1/Channel1<3>_MC.D1_1305  (
    .O(\U1/Channel1<3>_MC.D1 )
  );
  X_AND2 \U1/Channel1<3>_MC.D2_PT_0_1306  (
    .I0(\NlwInverterSignal_U1/Channel1<3>_MC.D2_PT_0/IN0 ),
    .I1(\U1/Channel1 [3]),
    .O(\U1/Channel1<3>_MC.D2_PT_0 )
  );
  X_AND6 \U1/Channel1<3>_MC.D2_PT_1_1307  (
    .I0(\MSPReset_II/UIM ),
    .I1(\U1/Channel1 [0]),
    .I2(\NlwInverterSignal_U1/Channel1<3>_MC.D2_PT_1/IN2 ),
    .I3(N_PZ_1016),
    .I4(\U1/Channel1 [1]),
    .I5(\U1/Channel1 [2]),
    .O(\U1/Channel1<3>_MC.D2_PT_1 )
  );
  X_AND7 \U1/Channel1<3>_MC.D2_PT_2_1308  (
    .I0(\MSPReset_II/UIM ),
    .I1(\NlwInverterSignal_U1/Channel1<3>_MC.D2_PT_2/IN1 ),
    .I2(\NlwInverterSignal_U1/Channel1<3>_MC.D2_PT_2/IN2 ),
    .I3(N_PZ_1155),
    .I4(\NlwInverterSignal_U1/Channel1<3>_MC.D2_PT_2/IN4 ),
    .I5(\NlwInverterSignal_U1/Channel1<3>_MC.D2_PT_2/IN5 ),
    .I6(\NlwInverterSignal_U1/Channel1<3>_MC.D2_PT_2/IN6 ),
    .O(\U1/Channel1<3>_MC.D2_PT_2 )
  );
  X_OR3 \U1/Channel1<3>_MC.D2_1309  (
    .I0(\U1/Channel1<3>_MC.D2_PT_0 ),
    .I1(\U1/Channel1<3>_MC.D2_PT_1 ),
    .I2(\U1/Channel1<3>_MC.D2_PT_2 ),
    .O(\U1/Channel1<3>_MC.D2 )
  );
  X_BUF \U1/Channel1<4>  (
    .I(\U1/Channel1<4>_MC.Q ),
    .O(\U1/Channel1 [4])
  );
  X_XOR2 \U1/Channel1<4>_MC_tsimcreated_xor__1310  (
    .I0(\U1/Channel1<4>_MC.D ),
    .I1(\U1/Channel1<4>_MC.Q ),
    .O(\U1/Channel1<4>_MC_tsimcreated_xor_ )
  );
  X_FF \U1/Channel1<4>_MC.REG  (
    .I(\U1/Channel1<4>_MC_tsimcreated_xor_ ),
    .CE(Vcc),
    .CLK(\Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\U1/Channel1<4>_MC.Q )
  );
  X_XOR2 \U1/Channel1<4>_MC.D_1311  (
    .I0(\U1/Channel1<4>_MC.D1 ),
    .I1(\U1/Channel1<4>_MC.D2 ),
    .O(\U1/Channel1<4>_MC.D )
  );
  X_ZERO \U1/Channel1<4>_MC.D1_1312  (
    .O(\U1/Channel1<4>_MC.D1 )
  );
  X_AND2 \U1/Channel1<4>_MC.D2_PT_0_1313  (
    .I0(\NlwInverterSignal_U1/Channel1<4>_MC.D2_PT_0/IN0 ),
    .I1(\U1/Channel1 [4]),
    .O(\U1/Channel1<4>_MC.D2_PT_0 )
  );
  X_AND4 \U1/Channel1<4>_MC.D2_PT_1_1314  (
    .I0(N_PZ_1016),
    .I1(\NlwInverterSignal_U1/Channel1<4>_MC.D2_PT_1/IN1 ),
    .I2(\NlwInverterSignal_U1/Channel1<4>_MC.D2_PT_1/IN2 ),
    .I3(\U1/Channel1 [4]),
    .O(\U1/Channel1<4>_MC.D2_PT_1 )
  );
  X_AND6 \U1/Channel1<4>_MC.D2_PT_2_1315  (
    .I0(\MSPReset_II/UIM ),
    .I1(\NlwInverterSignal_U1/Channel1<4>_MC.D2_PT_2/IN1 ),
    .I2(N_PZ_1155),
    .I3(\NlwInverterSignal_U1/Channel1<4>_MC.D2_PT_2/IN3 ),
    .I4(\U1/U5/location_Maddsub__n0000__n0067 [0]),
    .I5(\NlwInverterSignal_U1/Channel1<4>_MC.D2_PT_2/IN5 ),
    .O(\U1/Channel1<4>_MC.D2_PT_2 )
  );
  X_AND6 \U1/Channel1<4>_MC.D2_PT_3_1316  (
    .I0(\U1/Channel1 [0]),
    .I1(N_PZ_1016),
    .I2(\NlwInverterSignal_U1/Channel1<4>_MC.D2_PT_3/IN2 ),
    .I3(\U1/Channel1 [1]),
    .I4(\U1/Channel1 [2]),
    .I5(\U1/Channel1 [4]),
    .O(\U1/Channel1<4>_MC.D2_PT_3 )
  );
  X_AND7 \U1/Channel1<4>_MC.D2_PT_4_1317  (
    .I0(\NlwInverterSignal_U1/Channel1<4>_MC.D2_PT_4/IN0 ),
    .I1(N_PZ_1155),
    .I2(\NlwInverterSignal_U1/Channel1<4>_MC.D2_PT_4/IN2 ),
    .I3(\NlwInverterSignal_U1/Channel1<4>_MC.D2_PT_4/IN3 ),
    .I4(\NlwInverterSignal_U1/Channel1<4>_MC.D2_PT_4/IN4 ),
    .I5(\NlwInverterSignal_U1/Channel1<4>_MC.D2_PT_4/IN5 ),
    .I6(\U1/Channel1 [4]),
    .O(\U1/Channel1<4>_MC.D2_PT_4 )
  );
  X_AND16 \U1/Channel1<4>_MC.D2_PT_5_1318  (
    .I0(\MSPReset_II/UIM ),
    .I1(\U1/Channel1 [0]),
    .I2(\NlwInverterSignal_U1/Channel1<4>_MC.D2_PT_5/IN2 ),
    .I3(N_PZ_1155),
    .I4(\U1/U5/location_Maddsub__n0000__n0067 [0]),
    .I5(\U1/Channel1 [1]),
    .I6(\U1/Channel1 [2]),
    .I7(\U1/Channel1 [3]),
    .I8(\NlwInverterSignal_U1/Channel1<4>_MC.D2_PT_5/IN8 ),
    .I9(Vcc),
    .I10(Vcc),
    .I11(Vcc),
    .I12(Vcc),
    .I13(Vcc),
    .I14(Vcc),
    .I15(Vcc),
    .O(\U1/Channel1<4>_MC.D2_PT_5 )
  );
  X_OR6 \U1/Channel1<4>_MC.D2_1319  (
    .I0(\U1/Channel1<4>_MC.D2_PT_0 ),
    .I1(\U1/Channel1<4>_MC.D2_PT_1 ),
    .I2(\U1/Channel1<4>_MC.D2_PT_2 ),
    .I3(\U1/Channel1<4>_MC.D2_PT_3 ),
    .I4(\U1/Channel1<4>_MC.D2_PT_4 ),
    .I5(\U1/Channel1<4>_MC.D2_PT_5 ),
    .O(\U1/Channel1<4>_MC.D2 )
  );
  X_BUF \U1/Channel1<6>  (
    .I(\U1/Channel1<6>_MC.Q ),
    .O(\U1/Channel1 [6])
  );
  X_XOR2 \U1/Channel1<6>_MC_tsimcreated_xor__1320  (
    .I0(\U1/Channel1<6>_MC.D ),
    .I1(\U1/Channel1<6>_MC.Q ),
    .O(\U1/Channel1<6>_MC_tsimcreated_xor_ )
  );
  X_FF \U1/Channel1<6>_MC.REG  (
    .I(\U1/Channel1<6>_MC_tsimcreated_xor_ ),
    .CE(Vcc),
    .CLK(\Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\U1/Channel1<6>_MC.Q )
  );
  X_XOR2 \U1/Channel1<6>_MC.D_1321  (
    .I0(\U1/Channel1<6>_MC.D1 ),
    .I1(\U1/Channel1<6>_MC.D2 ),
    .O(\U1/Channel1<6>_MC.D )
  );
  X_ZERO \U1/Channel1<6>_MC.D1_1322  (
    .O(\U1/Channel1<6>_MC.D1 )
  );
  X_AND2 \U1/Channel1<6>_MC.D2_PT_0_1323  (
    .I0(\NlwInverterSignal_U1/Channel1<6>_MC.D2_PT_0/IN0 ),
    .I1(\U1/Channel1 [6]),
    .O(\U1/Channel1<6>_MC.D2_PT_0 )
  );
  X_AND5 \U1/Channel1<6>_MC.D2_PT_1_1324  (
    .I0(\MSPReset_II/UIM ),
    .I1(\NlwInverterSignal_U1/Channel1<6>_MC.D2_PT_1/IN1 ),
    .I2(N_PZ_1016),
    .I3(\U1/Channel1 [5]),
    .I4(\NlwInverterSignal_U1/Channel1<6>_MC.D2_PT_1/IN4 ),
    .O(\U1/Channel1<6>_MC.D2_PT_1 )
  );
  X_AND6 \U1/Channel1<6>_MC.D2_PT_2_1325  (
    .I0(\MSPReset_II/UIM ),
    .I1(\NlwInverterSignal_U1/Channel1<6>_MC.D2_PT_2/IN1 ),
    .I2(N_PZ_1155),
    .I3(\NlwInverterSignal_U1/Channel1<6>_MC.D2_PT_2/IN3 ),
    .I4(\NlwInverterSignal_U1/Channel1<6>_MC.D2_PT_2/IN4 ),
    .I5(\U1/U5/location_Maddsub__n0000__n0067 [0]),
    .O(\U1/Channel1<6>_MC.D2_PT_2 )
  );
  X_OR3 \U1/Channel1<6>_MC.D2_1326  (
    .I0(\U1/Channel1<6>_MC.D2_PT_0 ),
    .I1(\U1/Channel1<6>_MC.D2_PT_1 ),
    .I2(\U1/Channel1<6>_MC.D2_PT_2 ),
    .O(\U1/Channel1<6>_MC.D2 )
  );
  X_BUF \U1/Channel1<7>  (
    .I(\U1/Channel1<7>_MC.Q ),
    .O(\U1/Channel1 [7])
  );
  X_XOR2 \U1/Channel1<7>_MC_tsimcreated_xor__1327  (
    .I0(\U1/Channel1<7>_MC.D ),
    .I1(\U1/Channel1<7>_MC.Q ),
    .O(\U1/Channel1<7>_MC_tsimcreated_xor_ )
  );
  X_FF \U1/Channel1<7>_MC.REG  (
    .I(\U1/Channel1<7>_MC_tsimcreated_xor_ ),
    .CE(Vcc),
    .CLK(\Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\U1/Channel1<7>_MC.Q )
  );
  X_XOR2 \U1/Channel1<7>_MC.D_1328  (
    .I0(\U1/Channel1<7>_MC.D1 ),
    .I1(\U1/Channel1<7>_MC.D2 ),
    .O(\U1/Channel1<7>_MC.D )
  );
  X_ZERO \U1/Channel1<7>_MC.D1_1329  (
    .O(\U1/Channel1<7>_MC.D1 )
  );
  X_AND2 \U1/Channel1<7>_MC.D2_PT_0_1330  (
    .I0(\NlwInverterSignal_U1/Channel1<7>_MC.D2_PT_0/IN0 ),
    .I1(\U1/Channel1 [7]),
    .O(\U1/Channel1<7>_MC.D2_PT_0 )
  );
  X_AND6 \U1/Channel1<7>_MC.D2_PT_1_1331  (
    .I0(\MSPReset_II/UIM ),
    .I1(\NlwInverterSignal_U1/Channel1<7>_MC.D2_PT_1/IN1 ),
    .I2(N_PZ_1016),
    .I3(\U1/Channel1 [5]),
    .I4(\NlwInverterSignal_U1/Channel1<7>_MC.D2_PT_1/IN4 ),
    .I5(\U1/Channel1 [6]),
    .O(\U1/Channel1<7>_MC.D2_PT_1 )
  );
  X_AND7 \U1/Channel1<7>_MC.D2_PT_2_1332  (
    .I0(\MSPReset_II/UIM ),
    .I1(\NlwInverterSignal_U1/Channel1<7>_MC.D2_PT_2/IN1 ),
    .I2(N_PZ_1155),
    .I3(\NlwInverterSignal_U1/Channel1<7>_MC.D2_PT_2/IN3 ),
    .I4(\NlwInverterSignal_U1/Channel1<7>_MC.D2_PT_2/IN4 ),
    .I5(\U1/U5/location_Maddsub__n0000__n0067 [0]),
    .I6(\NlwInverterSignal_U1/Channel1<7>_MC.D2_PT_2/IN6 ),
    .O(\U1/Channel1<7>_MC.D2_PT_2 )
  );
  X_OR3 \U1/Channel1<7>_MC.D2_1333  (
    .I0(\U1/Channel1<7>_MC.D2_PT_0 ),
    .I1(\U1/Channel1<7>_MC.D2_PT_1 ),
    .I2(\U1/Channel1<7>_MC.D2_PT_2 ),
    .O(\U1/Channel1<7>_MC.D2 )
  );
  X_BUF \U1/U5/location_Maddsub__n0000__n0075<0>  (
    .I(\U1/U5/location_Maddsub__n0000__n0075<0>_MC.Q ),
    .O(\U1/U5/location_Maddsub__n0000__n0075 [0])
  );
  X_BUF \U1/U5/location_Maddsub__n0000__n0075<0>_MC.Q_1334  (
    .I(\U1/U5/location_Maddsub__n0000__n0075<0>_MC.D ),
    .O(\U1/U5/location_Maddsub__n0000__n0075<0>_MC.Q )
  );
  X_XOR2 \U1/U5/location_Maddsub__n0000__n0075<0>_MC.D_1335  (
    .I0(\U1/U5/location_Maddsub__n0000__n0075<0>_MC.D1 ),
    .I1(\U1/U5/location_Maddsub__n0000__n0075<0>_MC.D2 ),
    .O(\U1/U5/location_Maddsub__n0000__n0075<0>_MC.D )
  );
  X_AND2 \U1/U5/location_Maddsub__n0000__n0075<0>_MC.D1_1336  (
    .I0(N_PZ_946),
    .I1(N_PZ_946),
    .O(\U1/U5/location_Maddsub__n0000__n0075<0>_MC.D1 )
  );
  X_AND6 \U1/U5/location_Maddsub__n0000__n0075<0>_MC.D2_PT_0_1337  (
    .I0(\U1/Channel1 [8]),
    .I1(\U1/Channel1 [7]),
    .I2(\U1/Channel1 [5]),
    .I3(\NlwInverterSignal_U1/U5/location_Maddsub__n0000__n0075<0>_MC.D2_PT_0/IN3 ),
    .I4(\U1/Channel1 [6]),
    .I5(N_PZ_946),
    .O(\U1/U5/location_Maddsub__n0000__n0075<0>_MC.D2_PT_0 )
  );
  X_AND6 \U1/U5/location_Maddsub__n0000__n0075<0>_MC.D2_PT_1_1338  (
    .I0(\NlwInverterSignal_U1/U5/location_Maddsub__n0000__n0075<0>_MC.D2_PT_1/IN0 ),
    .I1(\NlwInverterSignal_U1/U5/location_Maddsub__n0000__n0075<0>_MC.D2_PT_1/IN1 ),
    .I2(\NlwInverterSignal_U1/U5/location_Maddsub__n0000__n0075<0>_MC.D2_PT_1/IN2 ),
    .I3(\U1/U5/location_Maddsub__n0000__n0067 [0]),
    .I4(\NlwInverterSignal_U1/U5/location_Maddsub__n0000__n0075<0>_MC.D2_PT_1/IN4 ),
    .I5(\NlwInverterSignal_U1/U5/location_Maddsub__n0000__n0075<0>_MC.D2_PT_1/IN5 ),
    .O(\U1/U5/location_Maddsub__n0000__n0075<0>_MC.D2_PT_1 )
  );
  X_OR2 \U1/U5/location_Maddsub__n0000__n0075<0>_MC.D2_1339  (
    .I0(\U1/U5/location_Maddsub__n0000__n0075<0>_MC.D2_PT_0 ),
    .I1(\U1/U5/location_Maddsub__n0000__n0075<0>_MC.D2_PT_1 ),
    .O(\U1/U5/location_Maddsub__n0000__n0075<0>_MC.D2 )
  );
  X_BUF \outDATA<0>\$WA5.UIM_1340  (
    .I(\outDATA<0>\$WA5.UIM_MC.Q ),
    .O(\outDATA<0>\$WA5.UIM )
  );
  X_BUF \outDATA<0>\$WA5.UIM_MC.Q_1341  (
    .I(\outDATA<0>\$WA5.UIM_MC.D ),
    .O(\outDATA<0>\$WA5.UIM_MC.Q )
  );
  X_XOR2 \outDATA<0>\$WA5.UIM_MC.D_1342  (
    .I0(\outDATA<0>\$WA5.UIM_MC.D1 ),
    .I1(\outDATA<0>\$WA5.UIM_MC.D2 ),
    .O(\outDATA<0>\$WA5.UIM_MC.D )
  );
  X_ZERO \outDATA<0>\$WA5.UIM_MC.D1_1343  (
    .O(\outDATA<0>\$WA5.UIM_MC.D1 )
  );
  X_AND2 \outDATA<0>\$WA5.UIM_MC.D2_PT_0_1344  (
    .I0(\U1/U3/holdingreg0 [0]),
    .I1(DCOR0CNTLOWr),
    .O(\outDATA<0>\$WA5.UIM_MC.D2_PT_0 )
  );
  X_AND3 \outDATA<0>\$WA5.UIM_MC.D2_PT_1_1345  (
    .I0(\NlwInverterSignal_outDATA<0>\$WA5.UIM_MC.D2_PT_1/IN0 ),
    .I1(\U1/U3/holdingreg1 [0]),
    .I2(DCOR1CNTLOWr),
    .O(\outDATA<0>\$WA5.UIM_MC.D2_PT_1 )
  );
  X_AND4 \outDATA<0>\$WA5.UIM_MC.D2_PT_2_1346  (
    .I0(\NlwInverterSignal_outDATA<0>\$WA5.UIM_MC.D2_PT_2/IN0 ),
    .I1(\NlwInverterSignal_outDATA<0>\$WA5.UIM_MC.D2_PT_2/IN1 ),
    .I2(\U1/U3/holdingreg0 [8]),
    .I3(DCOR0CNTHIGHr),
    .O(\outDATA<0>\$WA5.UIM_MC.D2_PT_2 )
  );
  X_AND4 \outDATA<0>\$WA5.UIM_MC.D2_PT_3_1347  (
    .I0(\NlwInverterSignal_outDATA<0>\$WA5.UIM_MC.D2_PT_3/IN0 ),
    .I1(\NlwInverterSignal_outDATA<0>\$WA5.UIM_MC.D2_PT_3/IN1 ),
    .I2(\NlwInverterSignal_outDATA<0>\$WA5.UIM_MC.D2_PT_3/IN2 ),
    .I3(\U1/U3/holdingreg1 [8]),
    .O(\outDATA<0>\$WA5.UIM_MC.D2_PT_3 )
  );
  X_OR4 \outDATA<0>\$WA5.UIM_MC.D2_1348  (
    .I0(\outDATA<0>\$WA5.UIM_MC.D2_PT_0 ),
    .I1(\outDATA<0>\$WA5.UIM_MC.D2_PT_1 ),
    .I2(\outDATA<0>\$WA5.UIM_MC.D2_PT_2 ),
    .I3(\outDATA<0>\$WA5.UIM_MC.D2_PT_3 ),
    .O(\outDATA<0>\$WA5.UIM_MC.D2 )
  );
  X_BUF \U1/U3/holdingreg0<0>  (
    .I(\U1/U3/holdingreg0<0>_MC.Q ),
    .O(\U1/U3/holdingreg0 [0])
  );
  X_FF \U1/U3/holdingreg0<0>_MC.REG  (
    .I(\U1/U3/holdingreg0<0>_MC.D ),
    .CE(Vcc),
    .CLK(\U1/U3/holdingreg0<0>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\U1/U3/holdingreg0<0>_MC.Q )
  );
  X_INV \U1/U3/holdingreg0<0>_MC.REG_tsimcreated_inv_Mclk_II/FCLK_1349  (
    .I(\Mclk_II/FCLK ),
    .O(\U1/U3/holdingreg0<0>_MC.REG_tsimcreated_inv_Mclk_II/FCLK )
  );
  X_XOR2 \U1/U3/holdingreg0<0>_MC.D_1350  (
    .I0(\U1/U3/holdingreg0<0>_MC.D1 ),
    .I1(\U1/U3/holdingreg0<0>_MC.D2 ),
    .O(\U1/U3/holdingreg0<0>_MC.D )
  );
  X_ZERO \U1/U3/holdingreg0<0>_MC.D1_1351  (
    .O(\U1/U3/holdingreg0<0>_MC.D1 )
  );
  X_AND2 \U1/U3/holdingreg0<0>_MC.D2_PT_0_1352  (
    .I0(N_PZ_941),
    .I1(\U1/U3/holdingreg0 [0]),
    .O(\U1/U3/holdingreg0<0>_MC.D2_PT_0 )
  );
  X_AND4 \U1/U3/holdingreg0<0>_MC.D2_PT_1_1353  (
    .I0(\MSPReset_II/UIM ),
    .I1(\NlwInverterSignal_U1/U3/holdingreg0<0>_MC.D2_PT_1/IN1 ),
    .I2(U2_ASedge),
    .I3(\U1/Channel0 [0]),
    .O(\U1/U3/holdingreg0<0>_MC.D2_PT_1 )
  );
  X_OR2 \U1/U3/holdingreg0<0>_MC.D2_1354  (
    .I0(\U1/U3/holdingreg0<0>_MC.D2_PT_0 ),
    .I1(\U1/U3/holdingreg0<0>_MC.D2_PT_1 ),
    .O(\U1/U3/holdingreg0<0>_MC.D2 )
  );
  X_BUF DCOR0CNTLOWr_1355 (
    .I(\DCOR0CNTLOWr_MC.Q ),
    .O(DCOR0CNTLOWr)
  );
  X_BUF \DCOR0CNTLOWr_MC.Q_1356  (
    .I(\DCOR0CNTLOWr_MC.D ),
    .O(\DCOR0CNTLOWr_MC.Q )
  );
  X_XOR2 \DCOR0CNTLOWr_MC.D_1357  (
    .I0(\DCOR0CNTLOWr_MC.D1 ),
    .I1(\DCOR0CNTLOWr_MC.D2 ),
    .O(\DCOR0CNTLOWr_MC.D )
  );
  X_AND16 \DCOR0CNTLOWr_MC.D1_1358  (
    .I0(\WR_II/UIM ),
    .I1(\NlwInverterSignal_DCOR0CNTLOWr_MC.D1/IN1 ),
    .I2(\NlwInverterSignal_DCOR0CNTLOWr_MC.D1/IN2 ),
    .I3(\NlwInverterSignal_DCOR0CNTLOWr_MC.D1/IN3 ),
    .I4(\NlwInverterSignal_DCOR0CNTLOWr_MC.D1/IN4 ),
    .I5(\NlwInverterSignal_DCOR0CNTLOWr_MC.D1/IN5 ),
    .I6(\NlwInverterSignal_DCOR0CNTLOWr_MC.D1/IN6 ),
    .I7(\NlwInverterSignal_DCOR0CNTLOWr_MC.D1/IN7 ),
    .I8(\NlwInverterSignal_DCOR0CNTLOWr_MC.D1/IN8 ),
    .I9(U2_ADDR_reg[2]),
    .I10(Vcc),
    .I11(Vcc),
    .I12(Vcc),
    .I13(Vcc),
    .I14(Vcc),
    .I15(Vcc),
    .O(\DCOR0CNTLOWr_MC.D1 )
  );
  X_ZERO \DCOR0CNTLOWr_MC.D2_1359  (
    .O(\DCOR0CNTLOWr_MC.D2 )
  );
  X_BUF \U1/U3/holdingreg1<0>  (
    .I(\U1/U3/holdingreg1<0>_MC.Q ),
    .O(\U1/U3/holdingreg1 [0])
  );
  X_FF \U1/U3/holdingreg1<0>_MC.REG  (
    .I(\U1/U3/holdingreg1<0>_MC.D ),
    .CE(Vcc),
    .CLK(\U1/U3/holdingreg1<0>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\U1/U3/holdingreg1<0>_MC.Q )
  );
  X_INV \U1/U3/holdingreg1<0>_MC.REG_tsimcreated_inv_Mclk_II/FCLK_1360  (
    .I(\Mclk_II/FCLK ),
    .O(\U1/U3/holdingreg1<0>_MC.REG_tsimcreated_inv_Mclk_II/FCLK )
  );
  X_XOR2 \U1/U3/holdingreg1<0>_MC.D_1361  (
    .I0(\U1/U3/holdingreg1<0>_MC.D1 ),
    .I1(\U1/U3/holdingreg1<0>_MC.D2 ),
    .O(\U1/U3/holdingreg1<0>_MC.D )
  );
  X_ZERO \U1/U3/holdingreg1<0>_MC.D1_1362  (
    .O(\U1/U3/holdingreg1<0>_MC.D1 )
  );
  X_AND2 \U1/U3/holdingreg1<0>_MC.D2_PT_0_1363  (
    .I0(N_PZ_941),
    .I1(\U1/U3/holdingreg1 [0]),
    .O(\U1/U3/holdingreg1<0>_MC.D2_PT_0 )
  );
  X_AND4 \U1/U3/holdingreg1<0>_MC.D2_PT_1_1364  (
    .I0(\MSPReset_II/UIM ),
    .I1(\NlwInverterSignal_U1/U3/holdingreg1<0>_MC.D2_PT_1/IN1 ),
    .I2(U2_ASedge),
    .I3(\U1/Channel1 [0]),
    .O(\U1/U3/holdingreg1<0>_MC.D2_PT_1 )
  );
  X_OR2 \U1/U3/holdingreg1<0>_MC.D2_1365  (
    .I0(\U1/U3/holdingreg1<0>_MC.D2_PT_0 ),
    .I1(\U1/U3/holdingreg1<0>_MC.D2_PT_1 ),
    .O(\U1/U3/holdingreg1<0>_MC.D2 )
  );
  X_BUF DCOR1CNTLOWr_1366 (
    .I(\DCOR1CNTLOWr_MC.Q ),
    .O(DCOR1CNTLOWr)
  );
  X_BUF \DCOR1CNTLOWr_MC.Q_1367  (
    .I(\DCOR1CNTLOWr_MC.D ),
    .O(\DCOR1CNTLOWr_MC.Q )
  );
  X_XOR2 \DCOR1CNTLOWr_MC.D_1368  (
    .I0(\DCOR1CNTLOWr_MC.D1 ),
    .I1(\DCOR1CNTLOWr_MC.D2 ),
    .O(\DCOR1CNTLOWr_MC.D )
  );
  X_AND16 \DCOR1CNTLOWr_MC.D1_1369  (
    .I0(\WR_II/UIM ),
    .I1(\NlwInverterSignal_DCOR1CNTLOWr_MC.D1/IN1 ),
    .I2(\NlwInverterSignal_DCOR1CNTLOWr_MC.D1/IN2 ),
    .I3(\NlwInverterSignal_DCOR1CNTLOWr_MC.D1/IN3 ),
    .I4(\NlwInverterSignal_DCOR1CNTLOWr_MC.D1/IN4 ),
    .I5(\NlwInverterSignal_DCOR1CNTLOWr_MC.D1/IN5 ),
    .I6(\NlwInverterSignal_DCOR1CNTLOWr_MC.D1/IN6 ),
    .I7(\NlwInverterSignal_DCOR1CNTLOWr_MC.D1/IN7 ),
    .I8(U2_ADDR_reg[1]),
    .I9(U2_ADDR_reg[2]),
    .I10(Vcc),
    .I11(Vcc),
    .I12(Vcc),
    .I13(Vcc),
    .I14(Vcc),
    .I15(Vcc),
    .O(\DCOR1CNTLOWr_MC.D1 )
  );
  X_ZERO \DCOR1CNTLOWr_MC.D2_1370  (
    .O(\DCOR1CNTLOWr_MC.D2 )
  );
  X_BUF \U1/U3/holdingreg0<8>  (
    .I(\U1/U3/holdingreg0<8>_MC.Q ),
    .O(\U1/U3/holdingreg0 [8])
  );
  X_FF \U1/U3/holdingreg0<8>_MC.REG  (
    .I(\U1/U3/holdingreg0<8>_MC.D ),
    .CE(Vcc),
    .CLK(\U1/U3/holdingreg0<8>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\U1/U3/holdingreg0<8>_MC.Q )
  );
  X_INV \U1/U3/holdingreg0<8>_MC.REG_tsimcreated_inv_Mclk_II/FCLK_1371  (
    .I(\Mclk_II/FCLK ),
    .O(\U1/U3/holdingreg0<8>_MC.REG_tsimcreated_inv_Mclk_II/FCLK )
  );
  X_XOR2 \U1/U3/holdingreg0<8>_MC.D_1372  (
    .I0(\U1/U3/holdingreg0<8>_MC.D1 ),
    .I1(\U1/U3/holdingreg0<8>_MC.D2 ),
    .O(\U1/U3/holdingreg0<8>_MC.D )
  );
  X_ZERO \U1/U3/holdingreg0<8>_MC.D1_1373  (
    .O(\U1/U3/holdingreg0<8>_MC.D1 )
  );
  X_AND2 \U1/U3/holdingreg0<8>_MC.D2_PT_0_1374  (
    .I0(N_PZ_941),
    .I1(\U1/U3/holdingreg0 [8]),
    .O(\U1/U3/holdingreg0<8>_MC.D2_PT_0 )
  );
  X_AND4 \U1/U3/holdingreg0<8>_MC.D2_PT_1_1375  (
    .I0(\MSPReset_II/UIM ),
    .I1(\NlwInverterSignal_U1/U3/holdingreg0<8>_MC.D2_PT_1/IN1 ),
    .I2(U2_ASedge),
    .I3(\U1/Channel0 [8]),
    .O(\U1/U3/holdingreg0<8>_MC.D2_PT_1 )
  );
  X_OR2 \U1/U3/holdingreg0<8>_MC.D2_1376  (
    .I0(\U1/U3/holdingreg0<8>_MC.D2_PT_0 ),
    .I1(\U1/U3/holdingreg0<8>_MC.D2_PT_1 ),
    .O(\U1/U3/holdingreg0<8>_MC.D2 )
  );
  X_BUF DCOR0CNTHIGHr_1377 (
    .I(\DCOR0CNTHIGHr_MC.Q ),
    .O(DCOR0CNTHIGHr)
  );
  X_BUF \DCOR0CNTHIGHr_MC.Q_1378  (
    .I(\DCOR0CNTHIGHr_MC.D ),
    .O(\DCOR0CNTHIGHr_MC.Q )
  );
  X_XOR2 \DCOR0CNTHIGHr_MC.D_1379  (
    .I0(\DCOR0CNTHIGHr_MC.D1 ),
    .I1(\DCOR0CNTHIGHr_MC.D2 ),
    .O(\DCOR0CNTHIGHr_MC.D )
  );
  X_AND16 \DCOR0CNTHIGHr_MC.D1_1380  (
    .I0(\WR_II/UIM ),
    .I1(\NlwInverterSignal_DCOR0CNTHIGHr_MC.D1/IN1 ),
    .I2(U2_ADDR_reg[0]),
    .I3(\NlwInverterSignal_DCOR0CNTHIGHr_MC.D1/IN3 ),
    .I4(\NlwInverterSignal_DCOR0CNTHIGHr_MC.D1/IN4 ),
    .I5(\NlwInverterSignal_DCOR0CNTHIGHr_MC.D1/IN5 ),
    .I6(\NlwInverterSignal_DCOR0CNTHIGHr_MC.D1/IN6 ),
    .I7(\NlwInverterSignal_DCOR0CNTHIGHr_MC.D1/IN7 ),
    .I8(\NlwInverterSignal_DCOR0CNTHIGHr_MC.D1/IN8 ),
    .I9(U2_ADDR_reg[2]),
    .I10(Vcc),
    .I11(Vcc),
    .I12(Vcc),
    .I13(Vcc),
    .I14(Vcc),
    .I15(Vcc),
    .O(\DCOR0CNTHIGHr_MC.D1 )
  );
  X_ZERO \DCOR0CNTHIGHr_MC.D2_1381  (
    .O(\DCOR0CNTHIGHr_MC.D2 )
  );
  X_BUF \U1/U3/holdingreg1<8>  (
    .I(\U1/U3/holdingreg1<8>_MC.Q ),
    .O(\U1/U3/holdingreg1 [8])
  );
  X_FF \U1/U3/holdingreg1<8>_MC.REG  (
    .I(\U1/U3/holdingreg1<8>_MC.D ),
    .CE(Vcc),
    .CLK(\U1/U3/holdingreg1<8>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\U1/U3/holdingreg1<8>_MC.Q )
  );
  X_INV \U1/U3/holdingreg1<8>_MC.REG_tsimcreated_inv_Mclk_II/FCLK_1382  (
    .I(\Mclk_II/FCLK ),
    .O(\U1/U3/holdingreg1<8>_MC.REG_tsimcreated_inv_Mclk_II/FCLK )
  );
  X_XOR2 \U1/U3/holdingreg1<8>_MC.D_1383  (
    .I0(\U1/U3/holdingreg1<8>_MC.D1 ),
    .I1(\U1/U3/holdingreg1<8>_MC.D2 ),
    .O(\U1/U3/holdingreg1<8>_MC.D )
  );
  X_ZERO \U1/U3/holdingreg1<8>_MC.D1_1384  (
    .O(\U1/U3/holdingreg1<8>_MC.D1 )
  );
  X_AND2 \U1/U3/holdingreg1<8>_MC.D2_PT_0_1385  (
    .I0(N_PZ_941),
    .I1(\U1/U3/holdingreg1 [8]),
    .O(\U1/U3/holdingreg1<8>_MC.D2_PT_0 )
  );
  X_AND4 \U1/U3/holdingreg1<8>_MC.D2_PT_1_1386  (
    .I0(\MSPReset_II/UIM ),
    .I1(\NlwInverterSignal_U1/U3/holdingreg1<8>_MC.D2_PT_1/IN1 ),
    .I2(U2_ASedge),
    .I3(\U1/Channel1 [8]),
    .O(\U1/U3/holdingreg1<8>_MC.D2_PT_1 )
  );
  X_OR2 \U1/U3/holdingreg1<8>_MC.D2_1387  (
    .I0(\U1/U3/holdingreg1<8>_MC.D2_PT_0 ),
    .I1(\U1/U3/holdingreg1<8>_MC.D2_PT_1 ),
    .O(\U1/U3/holdingreg1<8>_MC.D2 )
  );
  X_BUF N_PZ_963_1388 (
    .I(\N_PZ_963_MC.Q ),
    .O(N_PZ_963)
  );
  X_BUF \N_PZ_963_MC.Q_1389  (
    .I(\N_PZ_963_MC.D ),
    .O(\N_PZ_963_MC.Q )
  );
  X_XOR2 \N_PZ_963_MC.D_1390  (
    .I0(\N_PZ_963_MC.D1 ),
    .I1(\N_PZ_963_MC.D2 ),
    .O(\N_PZ_963_MC.D )
  );
  X_AND4 \N_PZ_963_MC.D1_1391  (
    .I0(\NlwInverterSignal_N_PZ_963_MC.D1/IN0 ),
    .I1(\NlwInverterSignal_N_PZ_963_MC.D1/IN1 ),
    .I2(\NlwInverterSignal_N_PZ_963_MC.D1/IN2 ),
    .I3(\NlwInverterSignal_N_PZ_963_MC.D1/IN3 ),
    .O(\N_PZ_963_MC.D1 )
  );
  X_ZERO \N_PZ_963_MC.D2_1392  (
    .O(\N_PZ_963_MC.D2 )
  );
  X_BUF DCOR1CNTHIGHr_1393 (
    .I(\DCOR1CNTHIGHr_MC.Q ),
    .O(DCOR1CNTHIGHr)
  );
  X_BUF \DCOR1CNTHIGHr_MC.Q_1394  (
    .I(\DCOR1CNTHIGHr_MC.D ),
    .O(\DCOR1CNTHIGHr_MC.Q )
  );
  X_XOR2 \DCOR1CNTHIGHr_MC.D_1395  (
    .I0(\DCOR1CNTHIGHr_MC.D1 ),
    .I1(\DCOR1CNTHIGHr_MC.D2 ),
    .O(\DCOR1CNTHIGHr_MC.D )
  );
  X_AND16 \DCOR1CNTHIGHr_MC.D1_1396  (
    .I0(\WR_II/UIM ),
    .I1(\NlwInverterSignal_DCOR1CNTHIGHr_MC.D1/IN1 ),
    .I2(U2_ADDR_reg[0]),
    .I3(\NlwInverterSignal_DCOR1CNTHIGHr_MC.D1/IN3 ),
    .I4(\NlwInverterSignal_DCOR1CNTHIGHr_MC.D1/IN4 ),
    .I5(\NlwInverterSignal_DCOR1CNTHIGHr_MC.D1/IN5 ),
    .I6(\NlwInverterSignal_DCOR1CNTHIGHr_MC.D1/IN6 ),
    .I7(\NlwInverterSignal_DCOR1CNTHIGHr_MC.D1/IN7 ),
    .I8(U2_ADDR_reg[1]),
    .I9(U2_ADDR_reg[2]),
    .I10(Vcc),
    .I11(Vcc),
    .I12(Vcc),
    .I13(Vcc),
    .I14(Vcc),
    .I15(Vcc),
    .O(\DCOR1CNTHIGHr_MC.D1 )
  );
  X_ZERO \DCOR1CNTHIGHr_MC.D2_1397  (
    .O(\DCOR1CNTHIGHr_MC.D2 )
  );
  X_BUF N_PZ_980_1398 (
    .I(\N_PZ_980_MC.Q ),
    .O(N_PZ_980)
  );
  X_BUF \N_PZ_980_MC.Q_1399  (
    .I(\N_PZ_980_MC.D ),
    .O(\N_PZ_980_MC.Q )
  );
  X_XOR2 \N_PZ_980_MC.D_1400  (
    .I0(\N_PZ_980_MC.D1 ),
    .I1(\N_PZ_980_MC.D2 ),
    .O(\N_PZ_980_MC.D )
  );
  X_AND5 \N_PZ_980_MC.D1_1401  (
    .I0(\NlwInverterSignal_N_PZ_980_MC.D1/IN0 ),
    .I1(\NlwInverterSignal_N_PZ_980_MC.D1/IN1 ),
    .I2(\NlwInverterSignal_N_PZ_980_MC.D1/IN2 ),
    .I3(\NlwInverterSignal_N_PZ_980_MC.D1/IN3 ),
    .I4(\NlwInverterSignal_N_PZ_980_MC.D1/IN4 ),
    .O(\N_PZ_980_MC.D1 )
  );
  X_ZERO \N_PZ_980_MC.D2_1402  (
    .O(\N_PZ_980_MC.D2 )
  );
  X_BUF DCOR1THRESHIGHr_1403 (
    .I(\DCOR1THRESHIGHr_MC.Q ),
    .O(DCOR1THRESHIGHr)
  );
  X_BUF \DCOR1THRESHIGHr_MC.Q_1404  (
    .I(\DCOR1THRESHIGHr_MC.D ),
    .O(\DCOR1THRESHIGHr_MC.Q )
  );
  X_XOR2 \DCOR1THRESHIGHr_MC.D_1405  (
    .I0(\DCOR1THRESHIGHr_MC.D1 ),
    .I1(\DCOR1THRESHIGHr_MC.D2 ),
    .O(\DCOR1THRESHIGHr_MC.D )
  );
  X_AND16 \DCOR1THRESHIGHr_MC.D1_1406  (
    .I0(\WR_II/UIM ),
    .I1(\NlwInverterSignal_DCOR1THRESHIGHr_MC.D1/IN1 ),
    .I2(U2_ADDR_reg[0]),
    .I3(\NlwInverterSignal_DCOR1THRESHIGHr_MC.D1/IN3 ),
    .I4(\NlwInverterSignal_DCOR1THRESHIGHr_MC.D1/IN4 ),
    .I5(\NlwInverterSignal_DCOR1THRESHIGHr_MC.D1/IN5 ),
    .I6(\NlwInverterSignal_DCOR1THRESHIGHr_MC.D1/IN6 ),
    .I7(U2_ADDR_reg[3]),
    .I8(U2_ADDR_reg[1]),
    .I9(\NlwInverterSignal_DCOR1THRESHIGHr_MC.D1/IN9 ),
    .I10(Vcc),
    .I11(Vcc),
    .I12(Vcc),
    .I13(Vcc),
    .I14(Vcc),
    .I15(Vcc),
    .O(\DCOR1THRESHIGHr_MC.D1 )
  );
  X_ZERO \DCOR1THRESHIGHr_MC.D2_1407  (
    .O(\DCOR1THRESHIGHr_MC.D2 )
  );
  X_BUF \outDATA<1>\$WA0.UIM_1408  (
    .I(\outDATA<1>\$WA0.UIM_MC.Q ),
    .O(\outDATA<1>\$WA0.UIM )
  );
  X_BUF \outDATA<1>\$WA0.UIM_MC.Q_1409  (
    .I(\outDATA<1>\$WA0.UIM_MC.D ),
    .O(\outDATA<1>\$WA0.UIM_MC.Q )
  );
  X_XOR2 \outDATA<1>\$WA0.UIM_MC.D_1410  (
    .I0(\outDATA<1>\$WA0.UIM_MC.D1 ),
    .I1(\outDATA<1>\$WA0.UIM_MC.D2 ),
    .O(\outDATA<1>\$WA0.UIM_MC.D )
  );
  X_AND2 \outDATA<1>\$WA0.UIM_MC.D1_1411  (
    .I0(U11_U3_counterr[1]),
    .I1(U11_U3_counterr[1]),
    .O(\outDATA<1>\$WA0.UIM_MC.D1 )
  );
  X_ZERO \outDATA<1>\$WA0.UIM_MC.D2_1412  (
    .O(\outDATA<1>\$WA0.UIM_MC.D2 )
  );
  X_BUF \outDATA<1>\$WA1.UIM_1413  (
    .I(\outDATA<1>\$WA1.UIM_MC.Q ),
    .O(\outDATA<1>\$WA1.UIM )
  );
  X_BUF \outDATA<1>\$WA1.UIM_MC.Q_1414  (
    .I(\outDATA<1>\$WA1.UIM_MC.D ),
    .O(\outDATA<1>\$WA1.UIM_MC.Q )
  );
  X_XOR2 \outDATA<1>\$WA1.UIM_MC.D_1415  (
    .I0(\outDATA<1>\$WA1.UIM_MC.D1 ),
    .I1(\outDATA<1>\$WA1.UIM_MC.D2 ),
    .O(\outDATA<1>\$WA1.UIM_MC.D )
  );
  X_AND2 \outDATA<1>\$WA1.UIM_MC.D1_1416  (
    .I0(\I2CS<1>_II/UIM ),
    .I1(\I2CS<1>_II/UIM ),
    .O(\outDATA<1>\$WA1.UIM_MC.D1 )
  );
  X_ZERO \outDATA<1>\$WA1.UIM_MC.D2_1417  (
    .O(\outDATA<1>\$WA1.UIM_MC.D2 )
  );
  X_BUF \outDATA<1>\$WA2.UIM_1418  (
    .I(\outDATA<1>\$WA2.UIM_MC.Q ),
    .O(\outDATA<1>\$WA2.UIM )
  );
  X_BUF \outDATA<1>\$WA2.UIM_MC.Q_1419  (
    .I(\outDATA<1>\$WA2.UIM_MC.D ),
    .O(\outDATA<1>\$WA2.UIM_MC.Q )
  );
  X_XOR2 \outDATA<1>\$WA2.UIM_MC.D_1420  (
    .I0(\outDATA<1>\$WA2.UIM_MC.D1 ),
    .I1(\outDATA<1>\$WA2.UIM_MC.D2 ),
    .O(\outDATA<1>\$WA2.UIM_MC.D )
  );
  X_AND2 \outDATA<1>\$WA2.UIM_MC.D1_1421  (
    .I0(\FLS0_II/UIM ),
    .I1(\FLS0_II/UIM ),
    .O(\outDATA<1>\$WA2.UIM_MC.D1 )
  );
  X_ZERO \outDATA<1>\$WA2.UIM_MC.D2_1422  (
    .O(\outDATA<1>\$WA2.UIM_MC.D2 )
  );
  X_BUF \outDATA<1>\$WA3.UIM_1423  (
    .I(\outDATA<1>\$WA3.UIM_MC.Q ),
    .O(\outDATA<1>\$WA3.UIM )
  );
  X_BUF \outDATA<1>\$WA3.UIM_MC.Q_1424  (
    .I(\outDATA<1>\$WA3.UIM_MC.D ),
    .O(\outDATA<1>\$WA3.UIM_MC.Q )
  );
  X_XOR2 \outDATA<1>\$WA3.UIM_MC.D_1425  (
    .I0(\outDATA<1>\$WA3.UIM_MC.D1 ),
    .I1(\outDATA<1>\$WA3.UIM_MC.D2 ),
    .O(\outDATA<1>\$WA3.UIM_MC.D )
  );
  X_ZERO \outDATA<1>\$WA3.UIM_MC.D1_1426  (
    .O(\outDATA<1>\$WA3.UIM_MC.D1 )
  );
  X_AND2 \outDATA<1>\$WA3.UIM_MC.D2_PT_0_1427  (
    .I0(\NlwInverterSignal_outDATA<1>\$WA3.UIM_MC.D2_PT_0/IN0 ),
    .I1(NET2528),
    .O(\outDATA<1>\$WA3.UIM_MC.D2_PT_0 )
  );
  X_AND2 \outDATA<1>\$WA3.UIM_MC.D2_PT_1_1428  (
    .I0(NET2528),
    .I1(\U4/Flgreg [1]),
    .O(\outDATA<1>\$WA3.UIM_MC.D2_PT_1 )
  );
  X_AND3 \outDATA<1>\$WA3.UIM_MC.D2_PT_2_1429  (
    .I0(DCORENCPWRr),
    .I1(\NlwInverterSignal_outDATA<1>\$WA3.UIM_MC.D2_PT_2/IN1 ),
    .I2(\Home05FLG_II/UIM ),
    .O(\outDATA<1>\$WA3.UIM_MC.D2_PT_2 )
  );
  X_OR3 \outDATA<1>\$WA3.UIM_MC.D2_1430  (
    .I0(\outDATA<1>\$WA3.UIM_MC.D2_PT_0 ),
    .I1(\outDATA<1>\$WA3.UIM_MC.D2_PT_1 ),
    .I2(\outDATA<1>\$WA3.UIM_MC.D2_PT_2 ),
    .O(\outDATA<1>\$WA3.UIM_MC.D2 )
  );
  X_BUF \outDATA<1>\$WA6.UIM_1431  (
    .I(\outDATA<1>\$WA6.UIM_MC.Q ),
    .O(\outDATA<1>\$WA6.UIM )
  );
  X_BUF \outDATA<1>\$WA6.UIM_MC.Q_1432  (
    .I(\outDATA<1>\$WA6.UIM_MC.D ),
    .O(\outDATA<1>\$WA6.UIM_MC.Q )
  );
  X_XOR2 \outDATA<1>\$WA6.UIM_MC.D_1433  (
    .I0(\outDATA<1>\$WA6.UIM_MC.D1 ),
    .I1(\outDATA<1>\$WA6.UIM_MC.D2 ),
    .O(\outDATA<1>\$WA6.UIM_MC.D )
  );
  X_ZERO \outDATA<1>\$WA6.UIM_MC.D1_1434  (
    .O(\outDATA<1>\$WA6.UIM_MC.D1 )
  );
  X_AND2 \outDATA<1>\$WA6.UIM_MC.D2_PT_0_1435  (
    .I0(DCOR0THRESLOWr),
    .I1(\U1/U4/Latch0r [1]),
    .O(\outDATA<1>\$WA6.UIM_MC.D2_PT_0 )
  );
  X_AND3 \outDATA<1>\$WA6.UIM_MC.D2_PT_1_1436  (
    .I0(\NlwInverterSignal_outDATA<1>\$WA6.UIM_MC.D2_PT_1/IN0 ),
    .I1(DCOR0THRESHIGHr),
    .I2(\U1/U4/Latch0r [9]),
    .O(\outDATA<1>\$WA6.UIM_MC.D2_PT_1 )
  );
  X_AND4 \outDATA<1>\$WA6.UIM_MC.D2_PT_2_1437  (
    .I0(\NlwInverterSignal_outDATA<1>\$WA6.UIM_MC.D2_PT_2/IN0 ),
    .I1(\NlwInverterSignal_outDATA<1>\$WA6.UIM_MC.D2_PT_2/IN1 ),
    .I2(DCOR1THRESLOWr),
    .I3(\U1/U4/Latch1r [1]),
    .O(\outDATA<1>\$WA6.UIM_MC.D2_PT_2 )
  );
  X_AND4 \outDATA<1>\$WA6.UIM_MC.D2_PT_3_1438  (
    .I0(\NlwInverterSignal_outDATA<1>\$WA6.UIM_MC.D2_PT_3/IN0 ),
    .I1(\NlwInverterSignal_outDATA<1>\$WA6.UIM_MC.D2_PT_3/IN1 ),
    .I2(\NlwInverterSignal_outDATA<1>\$WA6.UIM_MC.D2_PT_3/IN2 ),
    .I3(\U1/U4/Latch1r [9]),
    .O(\outDATA<1>\$WA6.UIM_MC.D2_PT_3 )
  );
  X_OR4 \outDATA<1>\$WA6.UIM_MC.D2_1439  (
    .I0(\outDATA<1>\$WA6.UIM_MC.D2_PT_0 ),
    .I1(\outDATA<1>\$WA6.UIM_MC.D2_PT_1 ),
    .I2(\outDATA<1>\$WA6.UIM_MC.D2_PT_2 ),
    .I3(\outDATA<1>\$WA6.UIM_MC.D2_PT_3 ),
    .O(\outDATA<1>\$WA6.UIM_MC.D2 )
  );
  X_BUF \U1/U4/Latch0r<1>  (
    .I(\U1/U4/Latch0r<1>_MC.Q ),
    .O(\U1/U4/Latch0r [1])
  );
  X_FF \U1/U4/Latch0r<1>_MC.REG  (
    .I(\U1/U4/Latch0r<1>_MC.D ),
    .CE(Vcc),
    .CLK(\U1/U4/Latch0r<1>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\U1/U4/Latch0r<1>_MC.Q )
  );
  X_INV \U1/U4/Latch0r<1>_MC.REG_tsimcreated_inv_Mclk_II/FCLK_1440  (
    .I(\Mclk_II/FCLK ),
    .O(\U1/U4/Latch0r<1>_MC.REG_tsimcreated_inv_Mclk_II/FCLK )
  );
  X_XOR2 \U1/U4/Latch0r<1>_MC.D_1441  (
    .I0(\U1/U4/Latch0r<1>_MC.D1 ),
    .I1(\U1/U4/Latch0r<1>_MC.D2 ),
    .O(\U1/U4/Latch0r<1>_MC.D )
  );
  X_ZERO \U1/U4/Latch0r<1>_MC.D1_1442  (
    .O(\U1/U4/Latch0r<1>_MC.D1 )
  );
  X_AND3 \U1/U4/Latch0r<1>_MC.D2_PT_0_1443  (
    .I0(\MSPReset_II/UIM ),
    .I1(N_PZ_965),
    .I2(\U1/Channel0 [1]),
    .O(\U1/U4/Latch0r<1>_MC.D2_PT_0 )
  );
  X_AND3 \U1/U4/Latch0r<1>_MC.D2_PT_1_1444  (
    .I0(\MSPReset_II/UIM ),
    .I1(\NlwInverterSignal_U1/U4/Latch0r<1>_MC.D2_PT_1/IN1 ),
    .I2(\U1/U4/Latch0r [1]),
    .O(\U1/U4/Latch0r<1>_MC.D2_PT_1 )
  );
  X_OR2 \U1/U4/Latch0r<1>_MC.D2_1445  (
    .I0(\U1/U4/Latch0r<1>_MC.D2_PT_0 ),
    .I1(\U1/U4/Latch0r<1>_MC.D2_PT_1 ),
    .O(\U1/U4/Latch0r<1>_MC.D2 )
  );
  X_BUF \U1/U4/Latch0r<9>  (
    .I(\U1/U4/Latch0r<9>_MC.Q ),
    .O(\U1/U4/Latch0r [9])
  );
  X_FF \U1/U4/Latch0r<9>_MC.REG  (
    .I(\U1/U4/Latch0r<9>_MC.D ),
    .CE(Vcc),
    .CLK(\U1/U4/Latch0r<9>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\U1/U4/Latch0r<9>_MC.Q )
  );
  X_INV \U1/U4/Latch0r<9>_MC.REG_tsimcreated_inv_Mclk_II/FCLK_1446  (
    .I(\Mclk_II/FCLK ),
    .O(\U1/U4/Latch0r<9>_MC.REG_tsimcreated_inv_Mclk_II/FCLK )
  );
  X_XOR2 \U1/U4/Latch0r<9>_MC.D_1447  (
    .I0(\U1/U4/Latch0r<9>_MC.D1 ),
    .I1(\U1/U4/Latch0r<9>_MC.D2 ),
    .O(\U1/U4/Latch0r<9>_MC.D )
  );
  X_ZERO \U1/U4/Latch0r<9>_MC.D1_1448  (
    .O(\U1/U4/Latch0r<9>_MC.D1 )
  );
  X_AND3 \U1/U4/Latch0r<9>_MC.D2_PT_0_1449  (
    .I0(\MSPReset_II/UIM ),
    .I1(N_PZ_965),
    .I2(\U1/Channel0 [9]),
    .O(\U1/U4/Latch0r<9>_MC.D2_PT_0 )
  );
  X_AND3 \U1/U4/Latch0r<9>_MC.D2_PT_1_1450  (
    .I0(\MSPReset_II/UIM ),
    .I1(\NlwInverterSignal_U1/U4/Latch0r<9>_MC.D2_PT_1/IN1 ),
    .I2(\U1/U4/Latch0r [9]),
    .O(\U1/U4/Latch0r<9>_MC.D2_PT_1 )
  );
  X_OR2 \U1/U4/Latch0r<9>_MC.D2_1451  (
    .I0(\U1/U4/Latch0r<9>_MC.D2_PT_0 ),
    .I1(\U1/U4/Latch0r<9>_MC.D2_PT_1 ),
    .O(\U1/U4/Latch0r<9>_MC.D2 )
  );
  X_BUF \U1/Channel0<9>  (
    .I(\U1/Channel0<9>_MC.Q ),
    .O(\U1/Channel0 [9])
  );
  X_XOR2 \U1/Channel0<9>_MC_tsimcreated_xor__1452  (
    .I0(\U1/Channel0<9>_MC.D ),
    .I1(\U1/Channel0<9>_MC.Q ),
    .O(\U1/Channel0<9>_MC_tsimcreated_xor_ )
  );
  X_FF \U1/Channel0<9>_MC.REG  (
    .I(\U1/Channel0<9>_MC_tsimcreated_xor_ ),
    .CE(Vcc),
    .CLK(\Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\U1/Channel0<9>_MC.Q )
  );
  X_XOR2 \U1/Channel0<9>_MC.D_1453  (
    .I0(\U1/Channel0<9>_MC.D1 ),
    .I1(\U1/Channel0<9>_MC.D2 ),
    .O(\U1/Channel0<9>_MC.D )
  );
  X_ZERO \U1/Channel0<9>_MC.D1_1454  (
    .O(\U1/Channel0<9>_MC.D1 )
  );
  X_AND2 \U1/Channel0<9>_MC.D2_PT_0_1455  (
    .I0(\NlwInverterSignal_U1/Channel0<9>_MC.D2_PT_0/IN0 ),
    .I1(\U1/Channel0 [9]),
    .O(\U1/Channel0<9>_MC.D2_PT_0 )
  );
  X_AND2 \U1/Channel0<9>_MC.D2_PT_1_1456  (
    .I0(\U1/U2/location_Maddsub__n0000__n0075 [0]),
    .I1(N_PZ_966),
    .O(\U1/Channel0<9>_MC.D2_PT_1 )
  );
  X_AND2 \U1/Channel0<9>_MC.D2_PT_2_1457  (
    .I0(\NlwInverterSignal_U1/Channel0<9>_MC.D2_PT_2/IN0 ),
    .I1(N_PZ_969),
    .O(\U1/Channel0<9>_MC.D2_PT_2 )
  );
  X_OR3 \U1/Channel0<9>_MC.D2_1458  (
    .I0(\U1/Channel0<9>_MC.D2_PT_0 ),
    .I1(\U1/Channel0<9>_MC.D2_PT_1 ),
    .I2(\U1/Channel0<9>_MC.D2_PT_2 ),
    .O(\U1/Channel0<9>_MC.D2 )
  );
  X_BUF \U1/U4/Latch1r<1>  (
    .I(\U1/U4/Latch1r<1>_MC.Q ),
    .O(\U1/U4/Latch1r [1])
  );
  X_FF \U1/U4/Latch1r<1>_MC.REG  (
    .I(\U1/U4/Latch1r<1>_MC.D ),
    .CE(Vcc),
    .CLK(\U1/U4/Latch1r<1>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\U1/U4/Latch1r<1>_MC.Q )
  );
  X_INV \U1/U4/Latch1r<1>_MC.REG_tsimcreated_inv_Mclk_II/FCLK_1459  (
    .I(\Mclk_II/FCLK ),
    .O(\U1/U4/Latch1r<1>_MC.REG_tsimcreated_inv_Mclk_II/FCLK )
  );
  X_XOR2 \U1/U4/Latch1r<1>_MC.D_1460  (
    .I0(\U1/U4/Latch1r<1>_MC.D1 ),
    .I1(\U1/U4/Latch1r<1>_MC.D2 ),
    .O(\U1/U4/Latch1r<1>_MC.D )
  );
  X_ZERO \U1/U4/Latch1r<1>_MC.D1_1461  (
    .O(\U1/U4/Latch1r<1>_MC.D1 )
  );
  X_AND2 \U1/U4/Latch1r<1>_MC.D2_PT_0_1462  (
    .I0(N_PZ_964),
    .I1(\U1/U4/Latch1r [1]),
    .O(\U1/U4/Latch1r<1>_MC.D2_PT_0 )
  );
  X_AND4 \U1/U4/Latch1r<1>_MC.D2_PT_1_1463  (
    .I0(\MSPReset_II/UIM ),
    .I1(\NlwInverterSignal_U1/U4/Latch1r<1>_MC.D2_PT_1/IN1 ),
    .I2(\NlwInverterSignal_U1/U4/Latch1r<1>_MC.D2_PT_1/IN2 ),
    .I3(\U1/Channel1 [1]),
    .O(\U1/U4/Latch1r<1>_MC.D2_PT_1 )
  );
  X_OR2 \U1/U4/Latch1r<1>_MC.D2_1464  (
    .I0(\U1/U4/Latch1r<1>_MC.D2_PT_0 ),
    .I1(\U1/U4/Latch1r<1>_MC.D2_PT_1 ),
    .O(\U1/U4/Latch1r<1>_MC.D2 )
  );
  X_BUF \U1/U4/Latch1r<9>  (
    .I(\U1/U4/Latch1r<9>_MC.Q ),
    .O(\U1/U4/Latch1r [9])
  );
  X_FF \U1/U4/Latch1r<9>_MC.REG  (
    .I(\U1/U4/Latch1r<9>_MC.D ),
    .CE(Vcc),
    .CLK(\U1/U4/Latch1r<9>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\U1/U4/Latch1r<9>_MC.Q )
  );
  X_INV \U1/U4/Latch1r<9>_MC.REG_tsimcreated_inv_Mclk_II/FCLK_1465  (
    .I(\Mclk_II/FCLK ),
    .O(\U1/U4/Latch1r<9>_MC.REG_tsimcreated_inv_Mclk_II/FCLK )
  );
  X_XOR2 \U1/U4/Latch1r<9>_MC.D_1466  (
    .I0(\U1/U4/Latch1r<9>_MC.D1 ),
    .I1(\U1/U4/Latch1r<9>_MC.D2 ),
    .O(\U1/U4/Latch1r<9>_MC.D )
  );
  X_ZERO \U1/U4/Latch1r<9>_MC.D1_1467  (
    .O(\U1/U4/Latch1r<9>_MC.D1 )
  );
  X_AND2 \U1/U4/Latch1r<9>_MC.D2_PT_0_1468  (
    .I0(N_PZ_964),
    .I1(\U1/U4/Latch1r [9]),
    .O(\U1/U4/Latch1r<9>_MC.D2_PT_0 )
  );
  X_AND4 \U1/U4/Latch1r<9>_MC.D2_PT_1_1469  (
    .I0(\MSPReset_II/UIM ),
    .I1(\NlwInverterSignal_U1/U4/Latch1r<9>_MC.D2_PT_1/IN1 ),
    .I2(\NlwInverterSignal_U1/U4/Latch1r<9>_MC.D2_PT_1/IN2 ),
    .I3(\U1/Channel1 [9]),
    .O(\U1/U4/Latch1r<9>_MC.D2_PT_1 )
  );
  X_OR2 \U1/U4/Latch1r<9>_MC.D2_1470  (
    .I0(\U1/U4/Latch1r<9>_MC.D2_PT_0 ),
    .I1(\U1/U4/Latch1r<9>_MC.D2_PT_1 ),
    .O(\U1/U4/Latch1r<9>_MC.D2 )
  );
  X_BUF \U1/Channel1<9>  (
    .I(\U1/Channel1<9>_MC.Q ),
    .O(\U1/Channel1 [9])
  );
  X_XOR2 \U1/Channel1<9>_MC_tsimcreated_xor__1471  (
    .I0(\U1/Channel1<9>_MC.D ),
    .I1(\U1/Channel1<9>_MC.Q ),
    .O(\U1/Channel1<9>_MC_tsimcreated_xor_ )
  );
  X_FF \U1/Channel1<9>_MC.REG  (
    .I(\U1/Channel1<9>_MC_tsimcreated_xor_ ),
    .CE(Vcc),
    .CLK(\Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\U1/Channel1<9>_MC.Q )
  );
  X_XOR2 \U1/Channel1<9>_MC.D_1472  (
    .I0(\U1/Channel1<9>_MC.D1 ),
    .I1(\U1/Channel1<9>_MC.D2 ),
    .O(\U1/Channel1<9>_MC.D )
  );
  X_ZERO \U1/Channel1<9>_MC.D1_1473  (
    .O(\U1/Channel1<9>_MC.D1 )
  );
  X_AND2 \U1/Channel1<9>_MC.D2_PT_0_1474  (
    .I0(\NlwInverterSignal_U1/Channel1<9>_MC.D2_PT_0/IN0 ),
    .I1(\U1/Channel1 [9]),
    .O(\U1/Channel1<9>_MC.D2_PT_0 )
  );
  X_AND4 \U1/Channel1<9>_MC.D2_PT_1_1475  (
    .I0(\MSPReset_II/UIM ),
    .I1(\NlwInverterSignal_U1/Channel1<9>_MC.D2_PT_1/IN1 ),
    .I2(N_PZ_1016),
    .I3(\NlwInverterSignal_U1/Channel1<9>_MC.D2_PT_1/IN3 ),
    .O(\U1/Channel1<9>_MC.D2_PT_1 )
  );
  X_AND5 \U1/Channel1<9>_MC.D2_PT_2_1476  (
    .I0(\MSPReset_II/UIM ),
    .I1(\NlwInverterSignal_U1/Channel1<9>_MC.D2_PT_2/IN1 ),
    .I2(N_PZ_1155),
    .I3(\NlwInverterSignal_U1/Channel1<9>_MC.D2_PT_2/IN3 ),
    .I4(\U1/U5/location_Maddsub__n0000__n0075 [0]),
    .O(\U1/Channel1<9>_MC.D2_PT_2 )
  );
  X_OR3 \U1/Channel1<9>_MC.D2_1477  (
    .I0(\U1/Channel1<9>_MC.D2_PT_0 ),
    .I1(\U1/Channel1<9>_MC.D2_PT_1 ),
    .I2(\U1/Channel1<9>_MC.D2_PT_2 ),
    .O(\U1/Channel1<9>_MC.D2 )
  );
  X_BUF \outDATA<1>\$WA5.UIM_1478  (
    .I(\outDATA<1>\$WA5.UIM_MC.Q ),
    .O(\outDATA<1>\$WA5.UIM )
  );
  X_BUF \outDATA<1>\$WA5.UIM_MC.Q_1479  (
    .I(\outDATA<1>\$WA5.UIM_MC.D ),
    .O(\outDATA<1>\$WA5.UIM_MC.Q )
  );
  X_XOR2 \outDATA<1>\$WA5.UIM_MC.D_1480  (
    .I0(\outDATA<1>\$WA5.UIM_MC.D1 ),
    .I1(\outDATA<1>\$WA5.UIM_MC.D2 ),
    .O(\outDATA<1>\$WA5.UIM_MC.D )
  );
  X_ZERO \outDATA<1>\$WA5.UIM_MC.D1_1481  (
    .O(\outDATA<1>\$WA5.UIM_MC.D1 )
  );
  X_AND2 \outDATA<1>\$WA5.UIM_MC.D2_PT_0_1482  (
    .I0(DCOR0CNTLOWr),
    .I1(\U1/U3/holdingreg0 [1]),
    .O(\outDATA<1>\$WA5.UIM_MC.D2_PT_0 )
  );
  X_AND3 \outDATA<1>\$WA5.UIM_MC.D2_PT_1_1483  (
    .I0(\NlwInverterSignal_outDATA<1>\$WA5.UIM_MC.D2_PT_1/IN0 ),
    .I1(DCOR1CNTLOWr),
    .I2(\U1/U3/holdingreg1 [1]),
    .O(\outDATA<1>\$WA5.UIM_MC.D2_PT_1 )
  );
  X_AND4 \outDATA<1>\$WA5.UIM_MC.D2_PT_2_1484  (
    .I0(\NlwInverterSignal_outDATA<1>\$WA5.UIM_MC.D2_PT_2/IN0 ),
    .I1(\NlwInverterSignal_outDATA<1>\$WA5.UIM_MC.D2_PT_2/IN1 ),
    .I2(DCOR0CNTHIGHr),
    .I3(\U1/U3/holdingreg0 [9]),
    .O(\outDATA<1>\$WA5.UIM_MC.D2_PT_2 )
  );
  X_AND4 \outDATA<1>\$WA5.UIM_MC.D2_PT_3_1485  (
    .I0(\NlwInverterSignal_outDATA<1>\$WA5.UIM_MC.D2_PT_3/IN0 ),
    .I1(\NlwInverterSignal_outDATA<1>\$WA5.UIM_MC.D2_PT_3/IN1 ),
    .I2(\NlwInverterSignal_outDATA<1>\$WA5.UIM_MC.D2_PT_3/IN2 ),
    .I3(\U1/U3/holdingreg1 [9]),
    .O(\outDATA<1>\$WA5.UIM_MC.D2_PT_3 )
  );
  X_OR4 \outDATA<1>\$WA5.UIM_MC.D2_1486  (
    .I0(\outDATA<1>\$WA5.UIM_MC.D2_PT_0 ),
    .I1(\outDATA<1>\$WA5.UIM_MC.D2_PT_1 ),
    .I2(\outDATA<1>\$WA5.UIM_MC.D2_PT_2 ),
    .I3(\outDATA<1>\$WA5.UIM_MC.D2_PT_3 ),
    .O(\outDATA<1>\$WA5.UIM_MC.D2 )
  );
  X_BUF \U1/U3/holdingreg0<1>  (
    .I(\U1/U3/holdingreg0<1>_MC.Q ),
    .O(\U1/U3/holdingreg0 [1])
  );
  X_FF \U1/U3/holdingreg0<1>_MC.REG  (
    .I(\U1/U3/holdingreg0<1>_MC.D ),
    .CE(Vcc),
    .CLK(\U1/U3/holdingreg0<1>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\U1/U3/holdingreg0<1>_MC.Q )
  );
  X_INV \U1/U3/holdingreg0<1>_MC.REG_tsimcreated_inv_Mclk_II/FCLK_1487  (
    .I(\Mclk_II/FCLK ),
    .O(\U1/U3/holdingreg0<1>_MC.REG_tsimcreated_inv_Mclk_II/FCLK )
  );
  X_XOR2 \U1/U3/holdingreg0<1>_MC.D_1488  (
    .I0(\U1/U3/holdingreg0<1>_MC.D1 ),
    .I1(\U1/U3/holdingreg0<1>_MC.D2 ),
    .O(\U1/U3/holdingreg0<1>_MC.D )
  );
  X_ZERO \U1/U3/holdingreg0<1>_MC.D1_1489  (
    .O(\U1/U3/holdingreg0<1>_MC.D1 )
  );
  X_AND2 \U1/U3/holdingreg0<1>_MC.D2_PT_0_1490  (
    .I0(N_PZ_941),
    .I1(\U1/U3/holdingreg0 [1]),
    .O(\U1/U3/holdingreg0<1>_MC.D2_PT_0 )
  );
  X_AND4 \U1/U3/holdingreg0<1>_MC.D2_PT_1_1491  (
    .I0(\MSPReset_II/UIM ),
    .I1(\NlwInverterSignal_U1/U3/holdingreg0<1>_MC.D2_PT_1/IN1 ),
    .I2(U2_ASedge),
    .I3(\U1/Channel0 [1]),
    .O(\U1/U3/holdingreg0<1>_MC.D2_PT_1 )
  );
  X_OR2 \U1/U3/holdingreg0<1>_MC.D2_1492  (
    .I0(\U1/U3/holdingreg0<1>_MC.D2_PT_0 ),
    .I1(\U1/U3/holdingreg0<1>_MC.D2_PT_1 ),
    .O(\U1/U3/holdingreg0<1>_MC.D2 )
  );
  X_BUF \U1/U3/holdingreg1<1>  (
    .I(\U1/U3/holdingreg1<1>_MC.Q ),
    .O(\U1/U3/holdingreg1 [1])
  );
  X_FF \U1/U3/holdingreg1<1>_MC.REG  (
    .I(\U1/U3/holdingreg1<1>_MC.D ),
    .CE(Vcc),
    .CLK(\U1/U3/holdingreg1<1>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\U1/U3/holdingreg1<1>_MC.Q )
  );
  X_INV \U1/U3/holdingreg1<1>_MC.REG_tsimcreated_inv_Mclk_II/FCLK_1493  (
    .I(\Mclk_II/FCLK ),
    .O(\U1/U3/holdingreg1<1>_MC.REG_tsimcreated_inv_Mclk_II/FCLK )
  );
  X_XOR2 \U1/U3/holdingreg1<1>_MC.D_1494  (
    .I0(\U1/U3/holdingreg1<1>_MC.D1 ),
    .I1(\U1/U3/holdingreg1<1>_MC.D2 ),
    .O(\U1/U3/holdingreg1<1>_MC.D )
  );
  X_ZERO \U1/U3/holdingreg1<1>_MC.D1_1495  (
    .O(\U1/U3/holdingreg1<1>_MC.D1 )
  );
  X_AND2 \U1/U3/holdingreg1<1>_MC.D2_PT_0_1496  (
    .I0(N_PZ_941),
    .I1(\U1/U3/holdingreg1 [1]),
    .O(\U1/U3/holdingreg1<1>_MC.D2_PT_0 )
  );
  X_AND4 \U1/U3/holdingreg1<1>_MC.D2_PT_1_1497  (
    .I0(\MSPReset_II/UIM ),
    .I1(\NlwInverterSignal_U1/U3/holdingreg1<1>_MC.D2_PT_1/IN1 ),
    .I2(U2_ASedge),
    .I3(\U1/Channel1 [1]),
    .O(\U1/U3/holdingreg1<1>_MC.D2_PT_1 )
  );
  X_OR2 \U1/U3/holdingreg1<1>_MC.D2_1498  (
    .I0(\U1/U3/holdingreg1<1>_MC.D2_PT_0 ),
    .I1(\U1/U3/holdingreg1<1>_MC.D2_PT_1 ),
    .O(\U1/U3/holdingreg1<1>_MC.D2 )
  );
  X_BUF \U1/U3/holdingreg0<9>  (
    .I(\U1/U3/holdingreg0<9>_MC.Q ),
    .O(\U1/U3/holdingreg0 [9])
  );
  X_FF \U1/U3/holdingreg0<9>_MC.REG  (
    .I(\U1/U3/holdingreg0<9>_MC.D ),
    .CE(Vcc),
    .CLK(\U1/U3/holdingreg0<9>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\U1/U3/holdingreg0<9>_MC.Q )
  );
  X_INV \U1/U3/holdingreg0<9>_MC.REG_tsimcreated_inv_Mclk_II/FCLK_1499  (
    .I(\Mclk_II/FCLK ),
    .O(\U1/U3/holdingreg0<9>_MC.REG_tsimcreated_inv_Mclk_II/FCLK )
  );
  X_XOR2 \U1/U3/holdingreg0<9>_MC.D_1500  (
    .I0(\U1/U3/holdingreg0<9>_MC.D1 ),
    .I1(\U1/U3/holdingreg0<9>_MC.D2 ),
    .O(\U1/U3/holdingreg0<9>_MC.D )
  );
  X_ZERO \U1/U3/holdingreg0<9>_MC.D1_1501  (
    .O(\U1/U3/holdingreg0<9>_MC.D1 )
  );
  X_AND2 \U1/U3/holdingreg0<9>_MC.D2_PT_0_1502  (
    .I0(N_PZ_941),
    .I1(\U1/U3/holdingreg0 [9]),
    .O(\U1/U3/holdingreg0<9>_MC.D2_PT_0 )
  );
  X_AND4 \U1/U3/holdingreg0<9>_MC.D2_PT_1_1503  (
    .I0(\MSPReset_II/UIM ),
    .I1(\NlwInverterSignal_U1/U3/holdingreg0<9>_MC.D2_PT_1/IN1 ),
    .I2(U2_ASedge),
    .I3(\U1/Channel0 [9]),
    .O(\U1/U3/holdingreg0<9>_MC.D2_PT_1 )
  );
  X_OR2 \U1/U3/holdingreg0<9>_MC.D2_1504  (
    .I0(\U1/U3/holdingreg0<9>_MC.D2_PT_0 ),
    .I1(\U1/U3/holdingreg0<9>_MC.D2_PT_1 ),
    .O(\U1/U3/holdingreg0<9>_MC.D2 )
  );
  X_BUF \U1/U3/holdingreg1<9>  (
    .I(\U1/U3/holdingreg1<9>_MC.Q ),
    .O(\U1/U3/holdingreg1 [9])
  );
  X_FF \U1/U3/holdingreg1<9>_MC.REG  (
    .I(\U1/U3/holdingreg1<9>_MC.D ),
    .CE(Vcc),
    .CLK(\U1/U3/holdingreg1<9>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\U1/U3/holdingreg1<9>_MC.Q )
  );
  X_INV \U1/U3/holdingreg1<9>_MC.REG_tsimcreated_inv_Mclk_II/FCLK_1505  (
    .I(\Mclk_II/FCLK ),
    .O(\U1/U3/holdingreg1<9>_MC.REG_tsimcreated_inv_Mclk_II/FCLK )
  );
  X_XOR2 \U1/U3/holdingreg1<9>_MC.D_1506  (
    .I0(\U1/U3/holdingreg1<9>_MC.D1 ),
    .I1(\U1/U3/holdingreg1<9>_MC.D2 ),
    .O(\U1/U3/holdingreg1<9>_MC.D )
  );
  X_ZERO \U1/U3/holdingreg1<9>_MC.D1_1507  (
    .O(\U1/U3/holdingreg1<9>_MC.D1 )
  );
  X_AND2 \U1/U3/holdingreg1<9>_MC.D2_PT_0_1508  (
    .I0(N_PZ_941),
    .I1(\U1/U3/holdingreg1 [9]),
    .O(\U1/U3/holdingreg1<9>_MC.D2_PT_0 )
  );
  X_AND4 \U1/U3/holdingreg1<9>_MC.D2_PT_1_1509  (
    .I0(\MSPReset_II/UIM ),
    .I1(\NlwInverterSignal_U1/U3/holdingreg1<9>_MC.D2_PT_1/IN1 ),
    .I2(U2_ASedge),
    .I3(\U1/Channel1 [9]),
    .O(\U1/U3/holdingreg1<9>_MC.D2_PT_1 )
  );
  X_OR2 \U1/U3/holdingreg1<9>_MC.D2_1510  (
    .I0(\U1/U3/holdingreg1<9>_MC.D2_PT_0 ),
    .I1(\U1/U3/holdingreg1<9>_MC.D2_PT_1 ),
    .O(\U1/U3/holdingreg1<9>_MC.D2 )
  );
  X_BUF \outDATA<2>\$WA0.UIM_1511  (
    .I(\outDATA<2>\$WA0.UIM_MC.Q ),
    .O(\outDATA<2>\$WA0.UIM )
  );
  X_BUF \outDATA<2>\$WA0.UIM_MC.Q_1512  (
    .I(\outDATA<2>\$WA0.UIM_MC.D ),
    .O(\outDATA<2>\$WA0.UIM_MC.Q )
  );
  X_XOR2 \outDATA<2>\$WA0.UIM_MC.D_1513  (
    .I0(\outDATA<2>\$WA0.UIM_MC.D1 ),
    .I1(\outDATA<2>\$WA0.UIM_MC.D2 ),
    .O(\outDATA<2>\$WA0.UIM_MC.D )
  );
  X_AND2 \outDATA<2>\$WA0.UIM_MC.D1_1514  (
    .I0(U11_U3_counterr[2]),
    .I1(U11_U3_counterr[2]),
    .O(\outDATA<2>\$WA0.UIM_MC.D1 )
  );
  X_ZERO \outDATA<2>\$WA0.UIM_MC.D2_1515  (
    .O(\outDATA<2>\$WA0.UIM_MC.D2 )
  );
  X_BUF \outDATA<2>\$WA1.UIM_1516  (
    .I(\outDATA<2>\$WA1.UIM_MC.Q ),
    .O(\outDATA<2>\$WA1.UIM )
  );
  X_BUF \outDATA<2>\$WA1.UIM_MC.Q_1517  (
    .I(\outDATA<2>\$WA1.UIM_MC.D ),
    .O(\outDATA<2>\$WA1.UIM_MC.Q )
  );
  X_XOR2 \outDATA<2>\$WA1.UIM_MC.D_1518  (
    .I0(\outDATA<2>\$WA1.UIM_MC.D1 ),
    .I1(\outDATA<2>\$WA1.UIM_MC.D2 ),
    .O(\outDATA<2>\$WA1.UIM_MC.D )
  );
  X_AND2 \outDATA<2>\$WA1.UIM_MC.D1_1519  (
    .I0(\I2CS<2>_II/UIM ),
    .I1(\I2CS<2>_II/UIM ),
    .O(\outDATA<2>\$WA1.UIM_MC.D1 )
  );
  X_ZERO \outDATA<2>\$WA1.UIM_MC.D2_1520  (
    .O(\outDATA<2>\$WA1.UIM_MC.D2 )
  );
  X_BUF \outDATA<2>\$WA2.UIM_1521  (
    .I(\outDATA<2>\$WA2.UIM_MC.Q ),
    .O(\outDATA<2>\$WA2.UIM )
  );
  X_BUF \outDATA<2>\$WA2.UIM_MC.Q_1522  (
    .I(\outDATA<2>\$WA2.UIM_MC.D ),
    .O(\outDATA<2>\$WA2.UIM_MC.Q )
  );
  X_XOR2 \outDATA<2>\$WA2.UIM_MC.D_1523  (
    .I0(\outDATA<2>\$WA2.UIM_MC.D1 ),
    .I1(\outDATA<2>\$WA2.UIM_MC.D2 ),
    .O(\outDATA<2>\$WA2.UIM_MC.D )
  );
  X_AND2 \outDATA<2>\$WA2.UIM_MC.D1_1524  (
    .I0(\Home0_II/UIM ),
    .I1(\Home0_II/UIM ),
    .O(\outDATA<2>\$WA2.UIM_MC.D1 )
  );
  X_ZERO \outDATA<2>\$WA2.UIM_MC.D2_1525  (
    .O(\outDATA<2>\$WA2.UIM_MC.D2 )
  );
  X_BUF \outDATA<2>\$WA3.UIM_1526  (
    .I(\outDATA<2>\$WA3.UIM_MC.Q ),
    .O(\outDATA<2>\$WA3.UIM )
  );
  X_BUF \outDATA<2>\$WA3.UIM_MC.Q_1527  (
    .I(\outDATA<2>\$WA3.UIM_MC.D ),
    .O(\outDATA<2>\$WA3.UIM_MC.Q )
  );
  X_XOR2 \outDATA<2>\$WA3.UIM_MC.D_1528  (
    .I0(\outDATA<2>\$WA3.UIM_MC.D1 ),
    .I1(\outDATA<2>\$WA3.UIM_MC.D2 ),
    .O(\outDATA<2>\$WA3.UIM_MC.D )
  );
  X_ZERO \outDATA<2>\$WA3.UIM_MC.D1_1529  (
    .O(\outDATA<2>\$WA3.UIM_MC.D1 )
  );
  X_AND2 \outDATA<2>\$WA3.UIM_MC.D2_PT_0_1530  (
    .I0(NET2528),
    .I1(\U4/Flgreg [2]),
    .O(\outDATA<2>\$WA3.UIM_MC.D2_PT_0 )
  );
  X_AND2 \outDATA<2>\$WA3.UIM_MC.D2_PT_1_1531  (
    .I0(\NlwInverterSignal_outDATA<2>\$WA3.UIM_MC.D2_PT_1/IN0 ),
    .I1(\Enc033FLG_II/UIM ),
    .O(\outDATA<2>\$WA3.UIM_MC.D2_PT_1 )
  );
  X_OR2 \outDATA<2>\$WA3.UIM_MC.D2_1532  (
    .I0(\outDATA<2>\$WA3.UIM_MC.D2_PT_0 ),
    .I1(\outDATA<2>\$WA3.UIM_MC.D2_PT_1 ),
    .O(\outDATA<2>\$WA3.UIM_MC.D2 )
  );
  X_BUF \outDATA<2>\$WA5.UIM_1533  (
    .I(\outDATA<2>\$WA5.UIM_MC.Q ),
    .O(\outDATA<2>\$WA5.UIM )
  );
  X_BUF \outDATA<2>\$WA5.UIM_MC.Q_1534  (
    .I(\outDATA<2>\$WA5.UIM_MC.D ),
    .O(\outDATA<2>\$WA5.UIM_MC.Q )
  );
  X_XOR2 \outDATA<2>\$WA5.UIM_MC.D_1535  (
    .I0(\outDATA<2>\$WA5.UIM_MC.D1 ),
    .I1(\outDATA<2>\$WA5.UIM_MC.D2 ),
    .O(\outDATA<2>\$WA5.UIM_MC.D )
  );
  X_ZERO \outDATA<2>\$WA5.UIM_MC.D1_1536  (
    .O(\outDATA<2>\$WA5.UIM_MC.D1 )
  );
  X_AND2 \outDATA<2>\$WA5.UIM_MC.D2_PT_0_1537  (
    .I0(DCOR0CNTLOWr),
    .I1(\U1/U3/holdingreg0 [2]),
    .O(\outDATA<2>\$WA5.UIM_MC.D2_PT_0 )
  );
  X_AND3 \outDATA<2>\$WA5.UIM_MC.D2_PT_1_1538  (
    .I0(\NlwInverterSignal_outDATA<2>\$WA5.UIM_MC.D2_PT_1/IN0 ),
    .I1(DCOR1CNTLOWr),
    .I2(\U1/U3/holdingreg1 [2]),
    .O(\outDATA<2>\$WA5.UIM_MC.D2_PT_1 )
  );
  X_AND4 \outDATA<2>\$WA5.UIM_MC.D2_PT_2_1539  (
    .I0(\NlwInverterSignal_outDATA<2>\$WA5.UIM_MC.D2_PT_2/IN0 ),
    .I1(\NlwInverterSignal_outDATA<2>\$WA5.UIM_MC.D2_PT_2/IN1 ),
    .I2(DCOR0CNTHIGHr),
    .I3(\U1/U3/holdingreg0 [10]),
    .O(\outDATA<2>\$WA5.UIM_MC.D2_PT_2 )
  );
  X_AND4 \outDATA<2>\$WA5.UIM_MC.D2_PT_3_1540  (
    .I0(\NlwInverterSignal_outDATA<2>\$WA5.UIM_MC.D2_PT_3/IN0 ),
    .I1(\NlwInverterSignal_outDATA<2>\$WA5.UIM_MC.D2_PT_3/IN1 ),
    .I2(\NlwInverterSignal_outDATA<2>\$WA5.UIM_MC.D2_PT_3/IN2 ),
    .I3(\U1/U3/holdingreg1 [10]),
    .O(\outDATA<2>\$WA5.UIM_MC.D2_PT_3 )
  );
  X_OR4 \outDATA<2>\$WA5.UIM_MC.D2_1541  (
    .I0(\outDATA<2>\$WA5.UIM_MC.D2_PT_0 ),
    .I1(\outDATA<2>\$WA5.UIM_MC.D2_PT_1 ),
    .I2(\outDATA<2>\$WA5.UIM_MC.D2_PT_2 ),
    .I3(\outDATA<2>\$WA5.UIM_MC.D2_PT_3 ),
    .O(\outDATA<2>\$WA5.UIM_MC.D2 )
  );
  X_BUF \U1/U3/holdingreg0<2>  (
    .I(\U1/U3/holdingreg0<2>_MC.Q ),
    .O(\U1/U3/holdingreg0 [2])
  );
  X_FF \U1/U3/holdingreg0<2>_MC.REG  (
    .I(\U1/U3/holdingreg0<2>_MC.D ),
    .CE(Vcc),
    .CLK(\U1/U3/holdingreg0<2>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\U1/U3/holdingreg0<2>_MC.Q )
  );
  X_INV \U1/U3/holdingreg0<2>_MC.REG_tsimcreated_inv_Mclk_II/FCLK_1542  (
    .I(\Mclk_II/FCLK ),
    .O(\U1/U3/holdingreg0<2>_MC.REG_tsimcreated_inv_Mclk_II/FCLK )
  );
  X_XOR2 \U1/U3/holdingreg0<2>_MC.D_1543  (
    .I0(\U1/U3/holdingreg0<2>_MC.D1 ),
    .I1(\U1/U3/holdingreg0<2>_MC.D2 ),
    .O(\U1/U3/holdingreg0<2>_MC.D )
  );
  X_ZERO \U1/U3/holdingreg0<2>_MC.D1_1544  (
    .O(\U1/U3/holdingreg0<2>_MC.D1 )
  );
  X_AND2 \U1/U3/holdingreg0<2>_MC.D2_PT_0_1545  (
    .I0(N_PZ_941),
    .I1(\U1/U3/holdingreg0 [2]),
    .O(\U1/U3/holdingreg0<2>_MC.D2_PT_0 )
  );
  X_AND4 \U1/U3/holdingreg0<2>_MC.D2_PT_1_1546  (
    .I0(\MSPReset_II/UIM ),
    .I1(\NlwInverterSignal_U1/U3/holdingreg0<2>_MC.D2_PT_1/IN1 ),
    .I2(U2_ASedge),
    .I3(\U1/Channel0 [2]),
    .O(\U1/U3/holdingreg0<2>_MC.D2_PT_1 )
  );
  X_OR2 \U1/U3/holdingreg0<2>_MC.D2_1547  (
    .I0(\U1/U3/holdingreg0<2>_MC.D2_PT_0 ),
    .I1(\U1/U3/holdingreg0<2>_MC.D2_PT_1 ),
    .O(\U1/U3/holdingreg0<2>_MC.D2 )
  );
  X_BUF \U1/U3/holdingreg1<2>  (
    .I(\U1/U3/holdingreg1<2>_MC.Q ),
    .O(\U1/U3/holdingreg1 [2])
  );
  X_FF \U1/U3/holdingreg1<2>_MC.REG  (
    .I(\U1/U3/holdingreg1<2>_MC.D ),
    .CE(Vcc),
    .CLK(\U1/U3/holdingreg1<2>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\U1/U3/holdingreg1<2>_MC.Q )
  );
  X_INV \U1/U3/holdingreg1<2>_MC.REG_tsimcreated_inv_Mclk_II/FCLK_1548  (
    .I(\Mclk_II/FCLK ),
    .O(\U1/U3/holdingreg1<2>_MC.REG_tsimcreated_inv_Mclk_II/FCLK )
  );
  X_XOR2 \U1/U3/holdingreg1<2>_MC.D_1549  (
    .I0(\U1/U3/holdingreg1<2>_MC.D1 ),
    .I1(\U1/U3/holdingreg1<2>_MC.D2 ),
    .O(\U1/U3/holdingreg1<2>_MC.D )
  );
  X_ZERO \U1/U3/holdingreg1<2>_MC.D1_1550  (
    .O(\U1/U3/holdingreg1<2>_MC.D1 )
  );
  X_AND2 \U1/U3/holdingreg1<2>_MC.D2_PT_0_1551  (
    .I0(N_PZ_941),
    .I1(\U1/U3/holdingreg1 [2]),
    .O(\U1/U3/holdingreg1<2>_MC.D2_PT_0 )
  );
  X_AND4 \U1/U3/holdingreg1<2>_MC.D2_PT_1_1552  (
    .I0(\MSPReset_II/UIM ),
    .I1(\NlwInverterSignal_U1/U3/holdingreg1<2>_MC.D2_PT_1/IN1 ),
    .I2(U2_ASedge),
    .I3(\U1/Channel1 [2]),
    .O(\U1/U3/holdingreg1<2>_MC.D2_PT_1 )
  );
  X_OR2 \U1/U3/holdingreg1<2>_MC.D2_1553  (
    .I0(\U1/U3/holdingreg1<2>_MC.D2_PT_0 ),
    .I1(\U1/U3/holdingreg1<2>_MC.D2_PT_1 ),
    .O(\U1/U3/holdingreg1<2>_MC.D2 )
  );
  X_BUF \U1/U3/holdingreg0<10>  (
    .I(\U1/U3/holdingreg0<10>_MC.Q ),
    .O(\U1/U3/holdingreg0 [10])
  );
  X_FF \U1/U3/holdingreg0<10>_MC.REG  (
    .I(\U1/U3/holdingreg0<10>_MC.D ),
    .CE(Vcc),
    .CLK(\U1/U3/holdingreg0<10>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\U1/U3/holdingreg0<10>_MC.Q )
  );
  X_INV \U1/U3/holdingreg0<10>_MC.REG_tsimcreated_inv_Mclk_II/FCLK_1554  (
    .I(\Mclk_II/FCLK ),
    .O(\U1/U3/holdingreg0<10>_MC.REG_tsimcreated_inv_Mclk_II/FCLK )
  );
  X_XOR2 \U1/U3/holdingreg0<10>_MC.D_1555  (
    .I0(\U1/U3/holdingreg0<10>_MC.D1 ),
    .I1(\U1/U3/holdingreg0<10>_MC.D2 ),
    .O(\U1/U3/holdingreg0<10>_MC.D )
  );
  X_ZERO \U1/U3/holdingreg0<10>_MC.D1_1556  (
    .O(\U1/U3/holdingreg0<10>_MC.D1 )
  );
  X_AND2 \U1/U3/holdingreg0<10>_MC.D2_PT_0_1557  (
    .I0(N_PZ_941),
    .I1(\U1/U3/holdingreg0 [10]),
    .O(\U1/U3/holdingreg0<10>_MC.D2_PT_0 )
  );
  X_AND4 \U1/U3/holdingreg0<10>_MC.D2_PT_1_1558  (
    .I0(\MSPReset_II/UIM ),
    .I1(\NlwInverterSignal_U1/U3/holdingreg0<10>_MC.D2_PT_1/IN1 ),
    .I2(U2_ASedge),
    .I3(\U1/Channel0 [10]),
    .O(\U1/U3/holdingreg0<10>_MC.D2_PT_1 )
  );
  X_OR2 \U1/U3/holdingreg0<10>_MC.D2_1559  (
    .I0(\U1/U3/holdingreg0<10>_MC.D2_PT_0 ),
    .I1(\U1/U3/holdingreg0<10>_MC.D2_PT_1 ),
    .O(\U1/U3/holdingreg0<10>_MC.D2 )
  );
  X_BUF \U1/Channel0<10>  (
    .I(\U1/Channel0<10>_MC.Q ),
    .O(\U1/Channel0 [10])
  );
  X_XOR2 \U1/Channel0<10>_MC_tsimcreated_xor__1560  (
    .I0(\U1/Channel0<10>_MC.D ),
    .I1(\U1/Channel0<10>_MC.Q ),
    .O(\U1/Channel0<10>_MC_tsimcreated_xor_ )
  );
  X_FF \U1/Channel0<10>_MC.REG  (
    .I(\U1/Channel0<10>_MC_tsimcreated_xor_ ),
    .CE(Vcc),
    .CLK(\Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\U1/Channel0<10>_MC.Q )
  );
  X_XOR2 \U1/Channel0<10>_MC.D_1561  (
    .I0(\U1/Channel0<10>_MC.D1 ),
    .I1(\U1/Channel0<10>_MC.D2 ),
    .O(\U1/Channel0<10>_MC.D )
  );
  X_ZERO \U1/Channel0<10>_MC.D1_1562  (
    .O(\U1/Channel0<10>_MC.D1 )
  );
  X_AND2 \U1/Channel0<10>_MC.D2_PT_0_1563  (
    .I0(\NlwInverterSignal_U1/Channel0<10>_MC.D2_PT_0/IN0 ),
    .I1(\U1/Channel0 [10]),
    .O(\U1/Channel0<10>_MC.D2_PT_0 )
  );
  X_AND3 \U1/Channel0<10>_MC.D2_PT_1_1564  (
    .I0(\U1/U2/location_Maddsub__n0000__n0075 [0]),
    .I1(N_PZ_966),
    .I2(\NlwInverterSignal_U1/Channel0<10>_MC.D2_PT_1/IN2 ),
    .O(\U1/Channel0<10>_MC.D2_PT_1 )
  );
  X_AND3 \U1/Channel0<10>_MC.D2_PT_2_1565  (
    .I0(\NlwInverterSignal_U1/Channel0<10>_MC.D2_PT_2/IN0 ),
    .I1(N_PZ_969),
    .I2(\U1/Channel0 [9]),
    .O(\U1/Channel0<10>_MC.D2_PT_2 )
  );
  X_OR3 \U1/Channel0<10>_MC.D2_1566  (
    .I0(\U1/Channel0<10>_MC.D2_PT_0 ),
    .I1(\U1/Channel0<10>_MC.D2_PT_1 ),
    .I2(\U1/Channel0<10>_MC.D2_PT_2 ),
    .O(\U1/Channel0<10>_MC.D2 )
  );
  X_BUF \U1/U3/holdingreg1<10>  (
    .I(\U1/U3/holdingreg1<10>_MC.Q ),
    .O(\U1/U3/holdingreg1 [10])
  );
  X_FF \U1/U3/holdingreg1<10>_MC.REG  (
    .I(\U1/U3/holdingreg1<10>_MC.D ),
    .CE(Vcc),
    .CLK(\U1/U3/holdingreg1<10>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\U1/U3/holdingreg1<10>_MC.Q )
  );
  X_INV \U1/U3/holdingreg1<10>_MC.REG_tsimcreated_inv_Mclk_II/FCLK_1567  (
    .I(\Mclk_II/FCLK ),
    .O(\U1/U3/holdingreg1<10>_MC.REG_tsimcreated_inv_Mclk_II/FCLK )
  );
  X_XOR2 \U1/U3/holdingreg1<10>_MC.D_1568  (
    .I0(\U1/U3/holdingreg1<10>_MC.D1 ),
    .I1(\U1/U3/holdingreg1<10>_MC.D2 ),
    .O(\U1/U3/holdingreg1<10>_MC.D )
  );
  X_ZERO \U1/U3/holdingreg1<10>_MC.D1_1569  (
    .O(\U1/U3/holdingreg1<10>_MC.D1 )
  );
  X_AND2 \U1/U3/holdingreg1<10>_MC.D2_PT_0_1570  (
    .I0(N_PZ_941),
    .I1(\U1/U3/holdingreg1 [10]),
    .O(\U1/U3/holdingreg1<10>_MC.D2_PT_0 )
  );
  X_AND4 \U1/U3/holdingreg1<10>_MC.D2_PT_1_1571  (
    .I0(\MSPReset_II/UIM ),
    .I1(\NlwInverterSignal_U1/U3/holdingreg1<10>_MC.D2_PT_1/IN1 ),
    .I2(U2_ASedge),
    .I3(\U1/Channel1 [10]),
    .O(\U1/U3/holdingreg1<10>_MC.D2_PT_1 )
  );
  X_OR2 \U1/U3/holdingreg1<10>_MC.D2_1572  (
    .I0(\U1/U3/holdingreg1<10>_MC.D2_PT_0 ),
    .I1(\U1/U3/holdingreg1<10>_MC.D2_PT_1 ),
    .O(\U1/U3/holdingreg1<10>_MC.D2 )
  );
  X_BUF \U1/Channel1<10>  (
    .I(\U1/Channel1<10>_MC.Q ),
    .O(\U1/Channel1 [10])
  );
  X_XOR2 \U1/Channel1<10>_MC_tsimcreated_xor__1573  (
    .I0(\U1/Channel1<10>_MC.D ),
    .I1(\U1/Channel1<10>_MC.Q ),
    .O(\U1/Channel1<10>_MC_tsimcreated_xor_ )
  );
  X_FF \U1/Channel1<10>_MC.REG  (
    .I(\U1/Channel1<10>_MC_tsimcreated_xor_ ),
    .CE(Vcc),
    .CLK(\Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\U1/Channel1<10>_MC.Q )
  );
  X_XOR2 \U1/Channel1<10>_MC.D_1574  (
    .I0(\U1/Channel1<10>_MC.D1 ),
    .I1(\U1/Channel1<10>_MC.D2 ),
    .O(\U1/Channel1<10>_MC.D )
  );
  X_ZERO \U1/Channel1<10>_MC.D1_1575  (
    .O(\U1/Channel1<10>_MC.D1 )
  );
  X_AND2 \U1/Channel1<10>_MC.D2_PT_0_1576  (
    .I0(\NlwInverterSignal_U1/Channel1<10>_MC.D2_PT_0/IN0 ),
    .I1(\U1/Channel1 [10]),
    .O(\U1/Channel1<10>_MC.D2_PT_0 )
  );
  X_AND5 \U1/Channel1<10>_MC.D2_PT_1_1577  (
    .I0(\MSPReset_II/UIM ),
    .I1(\NlwInverterSignal_U1/Channel1<10>_MC.D2_PT_1/IN1 ),
    .I2(N_PZ_1016),
    .I3(\NlwInverterSignal_U1/Channel1<10>_MC.D2_PT_1/IN3 ),
    .I4(\U1/Channel1 [9]),
    .O(\U1/Channel1<10>_MC.D2_PT_1 )
  );
  X_AND6 \U1/Channel1<10>_MC.D2_PT_2_1578  (
    .I0(\MSPReset_II/UIM ),
    .I1(\NlwInverterSignal_U1/Channel1<10>_MC.D2_PT_2/IN1 ),
    .I2(N_PZ_1155),
    .I3(\NlwInverterSignal_U1/Channel1<10>_MC.D2_PT_2/IN3 ),
    .I4(\U1/U5/location_Maddsub__n0000__n0075 [0]),
    .I5(\NlwInverterSignal_U1/Channel1<10>_MC.D2_PT_2/IN5 ),
    .O(\U1/Channel1<10>_MC.D2_PT_2 )
  );
  X_OR3 \U1/Channel1<10>_MC.D2_1579  (
    .I0(\U1/Channel1<10>_MC.D2_PT_0 ),
    .I1(\U1/Channel1<10>_MC.D2_PT_1 ),
    .I2(\U1/Channel1<10>_MC.D2_PT_2 ),
    .O(\U1/Channel1<10>_MC.D2 )
  );
  X_BUF \outDATA<2>\$WA6.UIM_1580  (
    .I(\outDATA<2>\$WA6.UIM_MC.Q ),
    .O(\outDATA<2>\$WA6.UIM )
  );
  X_BUF \outDATA<2>\$WA6.UIM_MC.Q_1581  (
    .I(\outDATA<2>\$WA6.UIM_MC.D ),
    .O(\outDATA<2>\$WA6.UIM_MC.Q )
  );
  X_XOR2 \outDATA<2>\$WA6.UIM_MC.D_1582  (
    .I0(\outDATA<2>\$WA6.UIM_MC.D1 ),
    .I1(\outDATA<2>\$WA6.UIM_MC.D2 ),
    .O(\outDATA<2>\$WA6.UIM_MC.D )
  );
  X_ZERO \outDATA<2>\$WA6.UIM_MC.D1_1583  (
    .O(\outDATA<2>\$WA6.UIM_MC.D1 )
  );
  X_AND2 \outDATA<2>\$WA6.UIM_MC.D2_PT_0_1584  (
    .I0(DCOR0THRESLOWr),
    .I1(\U1/U4/Latch0r [2]),
    .O(\outDATA<2>\$WA6.UIM_MC.D2_PT_0 )
  );
  X_AND3 \outDATA<2>\$WA6.UIM_MC.D2_PT_1_1585  (
    .I0(DCORIFGr),
    .I1(\NlwInverterSignal_outDATA<2>\$WA6.UIM_MC.D2_PT_1/IN1 ),
    .I2(NET2482),
    .O(\outDATA<2>\$WA6.UIM_MC.D2_PT_1 )
  );
  X_AND4 \outDATA<2>\$WA6.UIM_MC.D2_PT_2_1586  (
    .I0(\NlwInverterSignal_outDATA<2>\$WA6.UIM_MC.D2_PT_2/IN0 ),
    .I1(\NlwInverterSignal_outDATA<2>\$WA6.UIM_MC.D2_PT_2/IN1 ),
    .I2(DCOR0THRESHIGHr),
    .I3(\U1/U4/Latch0r [10]),
    .O(\outDATA<2>\$WA6.UIM_MC.D2_PT_2 )
  );
  X_AND5 \outDATA<2>\$WA6.UIM_MC.D2_PT_3_1587  (
    .I0(\NlwInverterSignal_outDATA<2>\$WA6.UIM_MC.D2_PT_3/IN0 ),
    .I1(\NlwInverterSignal_outDATA<2>\$WA6.UIM_MC.D2_PT_3/IN1 ),
    .I2(\NlwInverterSignal_outDATA<2>\$WA6.UIM_MC.D2_PT_3/IN2 ),
    .I3(DCOR1THRESLOWr),
    .I4(\U1/U4/Latch1r [2]),
    .O(\outDATA<2>\$WA6.UIM_MC.D2_PT_3 )
  );
  X_AND5 \outDATA<2>\$WA6.UIM_MC.D2_PT_4_1588  (
    .I0(\NlwInverterSignal_outDATA<2>\$WA6.UIM_MC.D2_PT_4/IN0 ),
    .I1(\NlwInverterSignal_outDATA<2>\$WA6.UIM_MC.D2_PT_4/IN1 ),
    .I2(\NlwInverterSignal_outDATA<2>\$WA6.UIM_MC.D2_PT_4/IN2 ),
    .I3(\NlwInverterSignal_outDATA<2>\$WA6.UIM_MC.D2_PT_4/IN3 ),
    .I4(\U1/U4/Latch1r [10]),
    .O(\outDATA<2>\$WA6.UIM_MC.D2_PT_4 )
  );
  X_OR5 \outDATA<2>\$WA6.UIM_MC.D2_1589  (
    .I0(\outDATA<2>\$WA6.UIM_MC.D2_PT_0 ),
    .I1(\outDATA<2>\$WA6.UIM_MC.D2_PT_1 ),
    .I2(\outDATA<2>\$WA6.UIM_MC.D2_PT_2 ),
    .I3(\outDATA<2>\$WA6.UIM_MC.D2_PT_3 ),
    .I4(\outDATA<2>\$WA6.UIM_MC.D2_PT_4 ),
    .O(\outDATA<2>\$WA6.UIM_MC.D2 )
  );
  X_BUF \U1/U4/Latch0r<2>  (
    .I(\U1/U4/Latch0r<2>_MC.Q ),
    .O(\U1/U4/Latch0r [2])
  );
  X_FF \U1/U4/Latch0r<2>_MC.REG  (
    .I(\U1/U4/Latch0r<2>_MC.D ),
    .CE(Vcc),
    .CLK(\U1/U4/Latch0r<2>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\U1/U4/Latch0r<2>_MC.Q )
  );
  X_INV \U1/U4/Latch0r<2>_MC.REG_tsimcreated_inv_Mclk_II/FCLK_1590  (
    .I(\Mclk_II/FCLK ),
    .O(\U1/U4/Latch0r<2>_MC.REG_tsimcreated_inv_Mclk_II/FCLK )
  );
  X_XOR2 \U1/U4/Latch0r<2>_MC.D_1591  (
    .I0(\U1/U4/Latch0r<2>_MC.D1 ),
    .I1(\U1/U4/Latch0r<2>_MC.D2 ),
    .O(\U1/U4/Latch0r<2>_MC.D )
  );
  X_ZERO \U1/U4/Latch0r<2>_MC.D1_1592  (
    .O(\U1/U4/Latch0r<2>_MC.D1 )
  );
  X_AND3 \U1/U4/Latch0r<2>_MC.D2_PT_0_1593  (
    .I0(\MSPReset_II/UIM ),
    .I1(N_PZ_965),
    .I2(\U1/Channel0 [2]),
    .O(\U1/U4/Latch0r<2>_MC.D2_PT_0 )
  );
  X_AND3 \U1/U4/Latch0r<2>_MC.D2_PT_1_1594  (
    .I0(\MSPReset_II/UIM ),
    .I1(\NlwInverterSignal_U1/U4/Latch0r<2>_MC.D2_PT_1/IN1 ),
    .I2(\U1/U4/Latch0r [2]),
    .O(\U1/U4/Latch0r<2>_MC.D2_PT_1 )
  );
  X_OR2 \U1/U4/Latch0r<2>_MC.D2_1595  (
    .I0(\U1/U4/Latch0r<2>_MC.D2_PT_0 ),
    .I1(\U1/U4/Latch0r<2>_MC.D2_PT_1 ),
    .O(\U1/U4/Latch0r<2>_MC.D2 )
  );
  X_BUF \U1/U4/Latch0r<10>  (
    .I(\U1/U4/Latch0r<10>_MC.Q ),
    .O(\U1/U4/Latch0r [10])
  );
  X_FF \U1/U4/Latch0r<10>_MC.REG  (
    .I(\U1/U4/Latch0r<10>_MC.D ),
    .CE(Vcc),
    .CLK(\U1/U4/Latch0r<10>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\U1/U4/Latch0r<10>_MC.Q )
  );
  X_INV \U1/U4/Latch0r<10>_MC.REG_tsimcreated_inv_Mclk_II/FCLK_1596  (
    .I(\Mclk_II/FCLK ),
    .O(\U1/U4/Latch0r<10>_MC.REG_tsimcreated_inv_Mclk_II/FCLK )
  );
  X_XOR2 \U1/U4/Latch0r<10>_MC.D_1597  (
    .I0(\U1/U4/Latch0r<10>_MC.D1 ),
    .I1(\U1/U4/Latch0r<10>_MC.D2 ),
    .O(\U1/U4/Latch0r<10>_MC.D )
  );
  X_ZERO \U1/U4/Latch0r<10>_MC.D1_1598  (
    .O(\U1/U4/Latch0r<10>_MC.D1 )
  );
  X_AND3 \U1/U4/Latch0r<10>_MC.D2_PT_0_1599  (
    .I0(\MSPReset_II/UIM ),
    .I1(N_PZ_965),
    .I2(\U1/Channel0 [10]),
    .O(\U1/U4/Latch0r<10>_MC.D2_PT_0 )
  );
  X_AND3 \U1/U4/Latch0r<10>_MC.D2_PT_1_1600  (
    .I0(\MSPReset_II/UIM ),
    .I1(\NlwInverterSignal_U1/U4/Latch0r<10>_MC.D2_PT_1/IN1 ),
    .I2(\U1/U4/Latch0r [10]),
    .O(\U1/U4/Latch0r<10>_MC.D2_PT_1 )
  );
  X_OR2 \U1/U4/Latch0r<10>_MC.D2_1601  (
    .I0(\U1/U4/Latch0r<10>_MC.D2_PT_0 ),
    .I1(\U1/U4/Latch0r<10>_MC.D2_PT_1 ),
    .O(\U1/U4/Latch0r<10>_MC.D2 )
  );
  X_BUF \U1/U4/Latch1r<2>  (
    .I(\U1/U4/Latch1r<2>_MC.Q ),
    .O(\U1/U4/Latch1r [2])
  );
  X_FF \U1/U4/Latch1r<2>_MC.REG  (
    .I(\U1/U4/Latch1r<2>_MC.D ),
    .CE(Vcc),
    .CLK(\U1/U4/Latch1r<2>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\U1/U4/Latch1r<2>_MC.Q )
  );
  X_INV \U1/U4/Latch1r<2>_MC.REG_tsimcreated_inv_Mclk_II/FCLK_1602  (
    .I(\Mclk_II/FCLK ),
    .O(\U1/U4/Latch1r<2>_MC.REG_tsimcreated_inv_Mclk_II/FCLK )
  );
  X_XOR2 \U1/U4/Latch1r<2>_MC.D_1603  (
    .I0(\U1/U4/Latch1r<2>_MC.D1 ),
    .I1(\U1/U4/Latch1r<2>_MC.D2 ),
    .O(\U1/U4/Latch1r<2>_MC.D )
  );
  X_ZERO \U1/U4/Latch1r<2>_MC.D1_1604  (
    .O(\U1/U4/Latch1r<2>_MC.D1 )
  );
  X_AND2 \U1/U4/Latch1r<2>_MC.D2_PT_0_1605  (
    .I0(N_PZ_964),
    .I1(\U1/U4/Latch1r [2]),
    .O(\U1/U4/Latch1r<2>_MC.D2_PT_0 )
  );
  X_AND4 \U1/U4/Latch1r<2>_MC.D2_PT_1_1606  (
    .I0(\MSPReset_II/UIM ),
    .I1(\NlwInverterSignal_U1/U4/Latch1r<2>_MC.D2_PT_1/IN1 ),
    .I2(\NlwInverterSignal_U1/U4/Latch1r<2>_MC.D2_PT_1/IN2 ),
    .I3(\U1/Channel1 [2]),
    .O(\U1/U4/Latch1r<2>_MC.D2_PT_1 )
  );
  X_OR2 \U1/U4/Latch1r<2>_MC.D2_1607  (
    .I0(\U1/U4/Latch1r<2>_MC.D2_PT_0 ),
    .I1(\U1/U4/Latch1r<2>_MC.D2_PT_1 ),
    .O(\U1/U4/Latch1r<2>_MC.D2 )
  );
  X_BUF \U1/U4/Latch1r<10>  (
    .I(\U1/U4/Latch1r<10>_MC.Q ),
    .O(\U1/U4/Latch1r [10])
  );
  X_FF \U1/U4/Latch1r<10>_MC.REG  (
    .I(\U1/U4/Latch1r<10>_MC.D ),
    .CE(Vcc),
    .CLK(\U1/U4/Latch1r<10>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\U1/U4/Latch1r<10>_MC.Q )
  );
  X_INV \U1/U4/Latch1r<10>_MC.REG_tsimcreated_inv_Mclk_II/FCLK_1608  (
    .I(\Mclk_II/FCLK ),
    .O(\U1/U4/Latch1r<10>_MC.REG_tsimcreated_inv_Mclk_II/FCLK )
  );
  X_XOR2 \U1/U4/Latch1r<10>_MC.D_1609  (
    .I0(\U1/U4/Latch1r<10>_MC.D1 ),
    .I1(\U1/U4/Latch1r<10>_MC.D2 ),
    .O(\U1/U4/Latch1r<10>_MC.D )
  );
  X_ZERO \U1/U4/Latch1r<10>_MC.D1_1610  (
    .O(\U1/U4/Latch1r<10>_MC.D1 )
  );
  X_AND2 \U1/U4/Latch1r<10>_MC.D2_PT_0_1611  (
    .I0(N_PZ_964),
    .I1(\U1/U4/Latch1r [10]),
    .O(\U1/U4/Latch1r<10>_MC.D2_PT_0 )
  );
  X_AND4 \U1/U4/Latch1r<10>_MC.D2_PT_1_1612  (
    .I0(\MSPReset_II/UIM ),
    .I1(\NlwInverterSignal_U1/U4/Latch1r<10>_MC.D2_PT_1/IN1 ),
    .I2(\NlwInverterSignal_U1/U4/Latch1r<10>_MC.D2_PT_1/IN2 ),
    .I3(\U1/Channel1 [10]),
    .O(\U1/U4/Latch1r<10>_MC.D2_PT_1 )
  );
  X_OR2 \U1/U4/Latch1r<10>_MC.D2_1613  (
    .I0(\U1/U4/Latch1r<10>_MC.D2_PT_0 ),
    .I1(\U1/U4/Latch1r<10>_MC.D2_PT_1 ),
    .O(\U1/U4/Latch1r<10>_MC.D2 )
  );
  X_BUF \outDATA<3>\$WA0.UIM_1614  (
    .I(\outDATA<3>\$WA0.UIM_MC.Q ),
    .O(\outDATA<3>\$WA0.UIM )
  );
  X_BUF \outDATA<3>\$WA0.UIM_MC.Q_1615  (
    .I(\outDATA<3>\$WA0.UIM_MC.D ),
    .O(\outDATA<3>\$WA0.UIM_MC.Q )
  );
  X_XOR2 \outDATA<3>\$WA0.UIM_MC.D_1616  (
    .I0(\outDATA<3>\$WA0.UIM_MC.D1 ),
    .I1(\outDATA<3>\$WA0.UIM_MC.D2 ),
    .O(\outDATA<3>\$WA0.UIM_MC.D )
  );
  X_AND2 \outDATA<3>\$WA0.UIM_MC.D1_1617  (
    .I0(U11_U3_counterr[3]),
    .I1(U11_U3_counterr[3]),
    .O(\outDATA<3>\$WA0.UIM_MC.D1 )
  );
  X_ZERO \outDATA<3>\$WA0.UIM_MC.D2_1618  (
    .O(\outDATA<3>\$WA0.UIM_MC.D2 )
  );
  X_BUF \outDATA<3>\$WA1.UIM_1619  (
    .I(\outDATA<3>\$WA1.UIM_MC.Q ),
    .O(\outDATA<3>\$WA1.UIM )
  );
  X_BUF \outDATA<3>\$WA1.UIM_MC.Q_1620  (
    .I(\outDATA<3>\$WA1.UIM_MC.D ),
    .O(\outDATA<3>\$WA1.UIM_MC.Q )
  );
  X_XOR2 \outDATA<3>\$WA1.UIM_MC.D_1621  (
    .I0(\outDATA<3>\$WA1.UIM_MC.D1 ),
    .I1(\outDATA<3>\$WA1.UIM_MC.D2 ),
    .O(\outDATA<3>\$WA1.UIM_MC.D )
  );
  X_AND2 \outDATA<3>\$WA1.UIM_MC.D1_1622  (
    .I0(\I2CS<3>_II/UIM ),
    .I1(\I2CS<3>_II/UIM ),
    .O(\outDATA<3>\$WA1.UIM_MC.D1 )
  );
  X_ZERO \outDATA<3>\$WA1.UIM_MC.D2_1623  (
    .O(\outDATA<3>\$WA1.UIM_MC.D2 )
  );
  X_BUF \outDATA<3>\$WA2.UIM_1624  (
    .I(\outDATA<3>\$WA2.UIM_MC.Q ),
    .O(\outDATA<3>\$WA2.UIM )
  );
  X_BUF \outDATA<3>\$WA2.UIM_MC.Q_1625  (
    .I(\outDATA<3>\$WA2.UIM_MC.D ),
    .O(\outDATA<3>\$WA2.UIM_MC.Q )
  );
  X_XOR2 \outDATA<3>\$WA2.UIM_MC.D_1626  (
    .I0(\outDATA<3>\$WA2.UIM_MC.D1 ),
    .I1(\outDATA<3>\$WA2.UIM_MC.D2 ),
    .O(\outDATA<3>\$WA2.UIM_MC.D )
  );
  X_AND2 \outDATA<3>\$WA2.UIM_MC.D1_1627  (
    .I0(NET3248),
    .I1(NET3248),
    .O(\outDATA<3>\$WA2.UIM_MC.D1 )
  );
  X_ZERO \outDATA<3>\$WA2.UIM_MC.D2_1628  (
    .O(\outDATA<3>\$WA2.UIM_MC.D2 )
  );
  X_BUF \outDATA<3>\$WA3.UIM_1629  (
    .I(\outDATA<3>\$WA3.UIM_MC.Q ),
    .O(\outDATA<3>\$WA3.UIM )
  );
  X_BUF \outDATA<3>\$WA3.UIM_MC.Q_1630  (
    .I(\outDATA<3>\$WA3.UIM_MC.D ),
    .O(\outDATA<3>\$WA3.UIM_MC.Q )
  );
  X_XOR2 \outDATA<3>\$WA3.UIM_MC.D_1631  (
    .I0(\outDATA<3>\$WA3.UIM_MC.D1 ),
    .I1(\outDATA<3>\$WA3.UIM_MC.D2 ),
    .O(\outDATA<3>\$WA3.UIM_MC.D )
  );
  X_ZERO \outDATA<3>\$WA3.UIM_MC.D1_1632  (
    .O(\outDATA<3>\$WA3.UIM_MC.D1 )
  );
  X_AND2 \outDATA<3>\$WA3.UIM_MC.D2_PT_0_1633  (
    .I0(NET2528),
    .I1(\U4/Flgreg [3]),
    .O(\outDATA<3>\$WA3.UIM_MC.D2_PT_0 )
  );
  X_AND2 \outDATA<3>\$WA3.UIM_MC.D2_PT_1_1634  (
    .I0(\NlwInverterSignal_outDATA<3>\$WA3.UIM_MC.D2_PT_1/IN0 ),
    .I1(\Enc05FLG_II/UIM ),
    .O(\outDATA<3>\$WA3.UIM_MC.D2_PT_1 )
  );
  X_OR2 \outDATA<3>\$WA3.UIM_MC.D2_1635  (
    .I0(\outDATA<3>\$WA3.UIM_MC.D2_PT_0 ),
    .I1(\outDATA<3>\$WA3.UIM_MC.D2_PT_1 ),
    .O(\outDATA<3>\$WA3.UIM_MC.D2 )
  );
  X_BUF \outDATA<3>\$WA5.UIM_1636  (
    .I(\outDATA<3>\$WA5.UIM_MC.Q ),
    .O(\outDATA<3>\$WA5.UIM )
  );
  X_BUF \outDATA<3>\$WA5.UIM_MC.Q_1637  (
    .I(\outDATA<3>\$WA5.UIM_MC.D ),
    .O(\outDATA<3>\$WA5.UIM_MC.Q )
  );
  X_XOR2 \outDATA<3>\$WA5.UIM_MC.D_1638  (
    .I0(\outDATA<3>\$WA5.UIM_MC.D1 ),
    .I1(\outDATA<3>\$WA5.UIM_MC.D2 ),
    .O(\outDATA<3>\$WA5.UIM_MC.D )
  );
  X_ZERO \outDATA<3>\$WA5.UIM_MC.D1_1639  (
    .O(\outDATA<3>\$WA5.UIM_MC.D1 )
  );
  X_AND2 \outDATA<3>\$WA5.UIM_MC.D2_PT_0_1640  (
    .I0(DCOR0CNTLOWr),
    .I1(\U1/U3/holdingreg0 [3]),
    .O(\outDATA<3>\$WA5.UIM_MC.D2_PT_0 )
  );
  X_AND3 \outDATA<3>\$WA5.UIM_MC.D2_PT_1_1641  (
    .I0(\NlwInverterSignal_outDATA<3>\$WA5.UIM_MC.D2_PT_1/IN0 ),
    .I1(DCOR1CNTLOWr),
    .I2(\U1/U3/holdingreg1 [3]),
    .O(\outDATA<3>\$WA5.UIM_MC.D2_PT_1 )
  );
  X_AND4 \outDATA<3>\$WA5.UIM_MC.D2_PT_2_1642  (
    .I0(\NlwInverterSignal_outDATA<3>\$WA5.UIM_MC.D2_PT_2/IN0 ),
    .I1(\NlwInverterSignal_outDATA<3>\$WA5.UIM_MC.D2_PT_2/IN1 ),
    .I2(DCOR0CNTHIGHr),
    .I3(\U1/U3/holdingreg0 [11]),
    .O(\outDATA<3>\$WA5.UIM_MC.D2_PT_2 )
  );
  X_AND4 \outDATA<3>\$WA5.UIM_MC.D2_PT_3_1643  (
    .I0(\NlwInverterSignal_outDATA<3>\$WA5.UIM_MC.D2_PT_3/IN0 ),
    .I1(\NlwInverterSignal_outDATA<3>\$WA5.UIM_MC.D2_PT_3/IN1 ),
    .I2(\NlwInverterSignal_outDATA<3>\$WA5.UIM_MC.D2_PT_3/IN2 ),
    .I3(\U1/U3/holdingreg1 [11]),
    .O(\outDATA<3>\$WA5.UIM_MC.D2_PT_3 )
  );
  X_OR4 \outDATA<3>\$WA5.UIM_MC.D2_1644  (
    .I0(\outDATA<3>\$WA5.UIM_MC.D2_PT_0 ),
    .I1(\outDATA<3>\$WA5.UIM_MC.D2_PT_1 ),
    .I2(\outDATA<3>\$WA5.UIM_MC.D2_PT_2 ),
    .I3(\outDATA<3>\$WA5.UIM_MC.D2_PT_3 ),
    .O(\outDATA<3>\$WA5.UIM_MC.D2 )
  );
  X_BUF \U1/U3/holdingreg0<3>  (
    .I(\U1/U3/holdingreg0<3>_MC.Q ),
    .O(\U1/U3/holdingreg0 [3])
  );
  X_FF \U1/U3/holdingreg0<3>_MC.REG  (
    .I(\U1/U3/holdingreg0<3>_MC.D ),
    .CE(Vcc),
    .CLK(\U1/U3/holdingreg0<3>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\U1/U3/holdingreg0<3>_MC.Q )
  );
  X_INV \U1/U3/holdingreg0<3>_MC.REG_tsimcreated_inv_Mclk_II/FCLK_1645  (
    .I(\Mclk_II/FCLK ),
    .O(\U1/U3/holdingreg0<3>_MC.REG_tsimcreated_inv_Mclk_II/FCLK )
  );
  X_XOR2 \U1/U3/holdingreg0<3>_MC.D_1646  (
    .I0(\U1/U3/holdingreg0<3>_MC.D1 ),
    .I1(\U1/U3/holdingreg0<3>_MC.D2 ),
    .O(\U1/U3/holdingreg0<3>_MC.D )
  );
  X_ZERO \U1/U3/holdingreg0<3>_MC.D1_1647  (
    .O(\U1/U3/holdingreg0<3>_MC.D1 )
  );
  X_AND2 \U1/U3/holdingreg0<3>_MC.D2_PT_0_1648  (
    .I0(N_PZ_941),
    .I1(\U1/U3/holdingreg0 [3]),
    .O(\U1/U3/holdingreg0<3>_MC.D2_PT_0 )
  );
  X_AND4 \U1/U3/holdingreg0<3>_MC.D2_PT_1_1649  (
    .I0(\MSPReset_II/UIM ),
    .I1(\NlwInverterSignal_U1/U3/holdingreg0<3>_MC.D2_PT_1/IN1 ),
    .I2(U2_ASedge),
    .I3(\U1/Channel0 [3]),
    .O(\U1/U3/holdingreg0<3>_MC.D2_PT_1 )
  );
  X_OR2 \U1/U3/holdingreg0<3>_MC.D2_1650  (
    .I0(\U1/U3/holdingreg0<3>_MC.D2_PT_0 ),
    .I1(\U1/U3/holdingreg0<3>_MC.D2_PT_1 ),
    .O(\U1/U3/holdingreg0<3>_MC.D2 )
  );
  X_BUF \U1/U3/holdingreg1<3>  (
    .I(\U1/U3/holdingreg1<3>_MC.Q ),
    .O(\U1/U3/holdingreg1 [3])
  );
  X_FF \U1/U3/holdingreg1<3>_MC.REG  (
    .I(\U1/U3/holdingreg1<3>_MC.D ),
    .CE(Vcc),
    .CLK(\U1/U3/holdingreg1<3>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\U1/U3/holdingreg1<3>_MC.Q )
  );
  X_INV \U1/U3/holdingreg1<3>_MC.REG_tsimcreated_inv_Mclk_II/FCLK_1651  (
    .I(\Mclk_II/FCLK ),
    .O(\U1/U3/holdingreg1<3>_MC.REG_tsimcreated_inv_Mclk_II/FCLK )
  );
  X_XOR2 \U1/U3/holdingreg1<3>_MC.D_1652  (
    .I0(\U1/U3/holdingreg1<3>_MC.D1 ),
    .I1(\U1/U3/holdingreg1<3>_MC.D2 ),
    .O(\U1/U3/holdingreg1<3>_MC.D )
  );
  X_ZERO \U1/U3/holdingreg1<3>_MC.D1_1653  (
    .O(\U1/U3/holdingreg1<3>_MC.D1 )
  );
  X_AND2 \U1/U3/holdingreg1<3>_MC.D2_PT_0_1654  (
    .I0(N_PZ_941),
    .I1(\U1/U3/holdingreg1 [3]),
    .O(\U1/U3/holdingreg1<3>_MC.D2_PT_0 )
  );
  X_AND4 \U1/U3/holdingreg1<3>_MC.D2_PT_1_1655  (
    .I0(\MSPReset_II/UIM ),
    .I1(\NlwInverterSignal_U1/U3/holdingreg1<3>_MC.D2_PT_1/IN1 ),
    .I2(U2_ASedge),
    .I3(\U1/Channel1 [3]),
    .O(\U1/U3/holdingreg1<3>_MC.D2_PT_1 )
  );
  X_OR2 \U1/U3/holdingreg1<3>_MC.D2_1656  (
    .I0(\U1/U3/holdingreg1<3>_MC.D2_PT_0 ),
    .I1(\U1/U3/holdingreg1<3>_MC.D2_PT_1 ),
    .O(\U1/U3/holdingreg1<3>_MC.D2 )
  );
  X_BUF \U1/U3/holdingreg0<11>  (
    .I(\U1/U3/holdingreg0<11>_MC.Q ),
    .O(\U1/U3/holdingreg0 [11])
  );
  X_FF \U1/U3/holdingreg0<11>_MC.REG  (
    .I(\U1/U3/holdingreg0<11>_MC.D ),
    .CE(Vcc),
    .CLK(\U1/U3/holdingreg0<11>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\U1/U3/holdingreg0<11>_MC.Q )
  );
  X_INV \U1/U3/holdingreg0<11>_MC.REG_tsimcreated_inv_Mclk_II/FCLK_1657  (
    .I(\Mclk_II/FCLK ),
    .O(\U1/U3/holdingreg0<11>_MC.REG_tsimcreated_inv_Mclk_II/FCLK )
  );
  X_XOR2 \U1/U3/holdingreg0<11>_MC.D_1658  (
    .I0(\U1/U3/holdingreg0<11>_MC.D1 ),
    .I1(\U1/U3/holdingreg0<11>_MC.D2 ),
    .O(\U1/U3/holdingreg0<11>_MC.D )
  );
  X_ZERO \U1/U3/holdingreg0<11>_MC.D1_1659  (
    .O(\U1/U3/holdingreg0<11>_MC.D1 )
  );
  X_AND2 \U1/U3/holdingreg0<11>_MC.D2_PT_0_1660  (
    .I0(N_PZ_941),
    .I1(\U1/U3/holdingreg0 [11]),
    .O(\U1/U3/holdingreg0<11>_MC.D2_PT_0 )
  );
  X_AND4 \U1/U3/holdingreg0<11>_MC.D2_PT_1_1661  (
    .I0(\MSPReset_II/UIM ),
    .I1(\NlwInverterSignal_U1/U3/holdingreg0<11>_MC.D2_PT_1/IN1 ),
    .I2(U2_ASedge),
    .I3(\U1/Channel0 [11]),
    .O(\U1/U3/holdingreg0<11>_MC.D2_PT_1 )
  );
  X_OR2 \U1/U3/holdingreg0<11>_MC.D2_1662  (
    .I0(\U1/U3/holdingreg0<11>_MC.D2_PT_0 ),
    .I1(\U1/U3/holdingreg0<11>_MC.D2_PT_1 ),
    .O(\U1/U3/holdingreg0<11>_MC.D2 )
  );
  X_BUF \U1/Channel0<11>  (
    .I(\U1/Channel0<11>_MC.Q ),
    .O(\U1/Channel0 [11])
  );
  X_XOR2 \U1/Channel0<11>_MC_tsimcreated_xor__1663  (
    .I0(\U1/Channel0<11>_MC.D ),
    .I1(\U1/Channel0<11>_MC.Q ),
    .O(\U1/Channel0<11>_MC_tsimcreated_xor_ )
  );
  X_FF \U1/Channel0<11>_MC.REG  (
    .I(\U1/Channel0<11>_MC_tsimcreated_xor_ ),
    .CE(Vcc),
    .CLK(\Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\U1/Channel0<11>_MC.Q )
  );
  X_XOR2 \U1/Channel0<11>_MC.D_1664  (
    .I0(\U1/Channel0<11>_MC.D1 ),
    .I1(\U1/Channel0<11>_MC.D2 ),
    .O(\U1/Channel0<11>_MC.D )
  );
  X_ZERO \U1/Channel0<11>_MC.D1_1665  (
    .O(\U1/Channel0<11>_MC.D1 )
  );
  X_AND2 \U1/Channel0<11>_MC.D2_PT_0_1666  (
    .I0(\NlwInverterSignal_U1/Channel0<11>_MC.D2_PT_0/IN0 ),
    .I1(\U1/Channel0 [11]),
    .O(\U1/Channel0<11>_MC.D2_PT_0 )
  );
  X_AND4 \U1/Channel0<11>_MC.D2_PT_1_1667  (
    .I0(\U1/U2/location_Maddsub__n0000__n0075 [0]),
    .I1(N_PZ_966),
    .I2(\NlwInverterSignal_U1/Channel0<11>_MC.D2_PT_1/IN2 ),
    .I3(\NlwInverterSignal_U1/Channel0<11>_MC.D2_PT_1/IN3 ),
    .O(\U1/Channel0<11>_MC.D2_PT_1 )
  );
  X_AND4 \U1/Channel0<11>_MC.D2_PT_2_1668  (
    .I0(\NlwInverterSignal_U1/Channel0<11>_MC.D2_PT_2/IN0 ),
    .I1(N_PZ_969),
    .I2(\U1/Channel0 [9]),
    .I3(\U1/Channel0 [10]),
    .O(\U1/Channel0<11>_MC.D2_PT_2 )
  );
  X_OR3 \U1/Channel0<11>_MC.D2_1669  (
    .I0(\U1/Channel0<11>_MC.D2_PT_0 ),
    .I1(\U1/Channel0<11>_MC.D2_PT_1 ),
    .I2(\U1/Channel0<11>_MC.D2_PT_2 ),
    .O(\U1/Channel0<11>_MC.D2 )
  );
  X_BUF \U1/U3/holdingreg1<11>  (
    .I(\U1/U3/holdingreg1<11>_MC.Q ),
    .O(\U1/U3/holdingreg1 [11])
  );
  X_FF \U1/U3/holdingreg1<11>_MC.REG  (
    .I(\U1/U3/holdingreg1<11>_MC.D ),
    .CE(Vcc),
    .CLK(\U1/U3/holdingreg1<11>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\U1/U3/holdingreg1<11>_MC.Q )
  );
  X_INV \U1/U3/holdingreg1<11>_MC.REG_tsimcreated_inv_Mclk_II/FCLK_1670  (
    .I(\Mclk_II/FCLK ),
    .O(\U1/U3/holdingreg1<11>_MC.REG_tsimcreated_inv_Mclk_II/FCLK )
  );
  X_XOR2 \U1/U3/holdingreg1<11>_MC.D_1671  (
    .I0(\U1/U3/holdingreg1<11>_MC.D1 ),
    .I1(\U1/U3/holdingreg1<11>_MC.D2 ),
    .O(\U1/U3/holdingreg1<11>_MC.D )
  );
  X_ZERO \U1/U3/holdingreg1<11>_MC.D1_1672  (
    .O(\U1/U3/holdingreg1<11>_MC.D1 )
  );
  X_AND2 \U1/U3/holdingreg1<11>_MC.D2_PT_0_1673  (
    .I0(N_PZ_941),
    .I1(\U1/U3/holdingreg1 [11]),
    .O(\U1/U3/holdingreg1<11>_MC.D2_PT_0 )
  );
  X_AND4 \U1/U3/holdingreg1<11>_MC.D2_PT_1_1674  (
    .I0(\MSPReset_II/UIM ),
    .I1(\NlwInverterSignal_U1/U3/holdingreg1<11>_MC.D2_PT_1/IN1 ),
    .I2(U2_ASedge),
    .I3(\U1/Channel1 [11]),
    .O(\U1/U3/holdingreg1<11>_MC.D2_PT_1 )
  );
  X_OR2 \U1/U3/holdingreg1<11>_MC.D2_1675  (
    .I0(\U1/U3/holdingreg1<11>_MC.D2_PT_0 ),
    .I1(\U1/U3/holdingreg1<11>_MC.D2_PT_1 ),
    .O(\U1/U3/holdingreg1<11>_MC.D2 )
  );
  X_BUF \U1/Channel1<11>  (
    .I(\U1/Channel1<11>_MC.Q ),
    .O(\U1/Channel1 [11])
  );
  X_XOR2 \U1/Channel1<11>_MC_tsimcreated_xor__1676  (
    .I0(\U1/Channel1<11>_MC.D ),
    .I1(\U1/Channel1<11>_MC.Q ),
    .O(\U1/Channel1<11>_MC_tsimcreated_xor_ )
  );
  X_FF \U1/Channel1<11>_MC.REG  (
    .I(\U1/Channel1<11>_MC_tsimcreated_xor_ ),
    .CE(Vcc),
    .CLK(\Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\U1/Channel1<11>_MC.Q )
  );
  X_XOR2 \U1/Channel1<11>_MC.D_1677  (
    .I0(\U1/Channel1<11>_MC.D1 ),
    .I1(\U1/Channel1<11>_MC.D2 ),
    .O(\U1/Channel1<11>_MC.D )
  );
  X_ZERO \U1/Channel1<11>_MC.D1_1678  (
    .O(\U1/Channel1<11>_MC.D1 )
  );
  X_AND2 \U1/Channel1<11>_MC.D2_PT_0_1679  (
    .I0(\NlwInverterSignal_U1/Channel1<11>_MC.D2_PT_0/IN0 ),
    .I1(\U1/Channel1 [11]),
    .O(\U1/Channel1<11>_MC.D2_PT_0 )
  );
  X_AND6 \U1/Channel1<11>_MC.D2_PT_1_1680  (
    .I0(\MSPReset_II/UIM ),
    .I1(\NlwInverterSignal_U1/Channel1<11>_MC.D2_PT_1/IN1 ),
    .I2(N_PZ_1016),
    .I3(\NlwInverterSignal_U1/Channel1<11>_MC.D2_PT_1/IN3 ),
    .I4(\U1/Channel1 [9]),
    .I5(\U1/Channel1 [10]),
    .O(\U1/Channel1<11>_MC.D2_PT_1 )
  );
  X_AND7 \U1/Channel1<11>_MC.D2_PT_2_1681  (
    .I0(\MSPReset_II/UIM ),
    .I1(\NlwInverterSignal_U1/Channel1<11>_MC.D2_PT_2/IN1 ),
    .I2(N_PZ_1155),
    .I3(\NlwInverterSignal_U1/Channel1<11>_MC.D2_PT_2/IN3 ),
    .I4(\U1/U5/location_Maddsub__n0000__n0075 [0]),
    .I5(\NlwInverterSignal_U1/Channel1<11>_MC.D2_PT_2/IN5 ),
    .I6(\NlwInverterSignal_U1/Channel1<11>_MC.D2_PT_2/IN6 ),
    .O(\U1/Channel1<11>_MC.D2_PT_2 )
  );
  X_OR3 \U1/Channel1<11>_MC.D2_1682  (
    .I0(\U1/Channel1<11>_MC.D2_PT_0 ),
    .I1(\U1/Channel1<11>_MC.D2_PT_1 ),
    .I2(\U1/Channel1<11>_MC.D2_PT_2 ),
    .O(\U1/Channel1<11>_MC.D2 )
  );
  X_BUF \outDATA<3>\$WA6.UIM_1683  (
    .I(\outDATA<3>\$WA6.UIM_MC.Q ),
    .O(\outDATA<3>\$WA6.UIM )
  );
  X_BUF \outDATA<3>\$WA6.UIM_MC.Q_1684  (
    .I(\outDATA<3>\$WA6.UIM_MC.D ),
    .O(\outDATA<3>\$WA6.UIM_MC.Q )
  );
  X_XOR2 \outDATA<3>\$WA6.UIM_MC.D_1685  (
    .I0(\outDATA<3>\$WA6.UIM_MC.D1 ),
    .I1(\outDATA<3>\$WA6.UIM_MC.D2 ),
    .O(\outDATA<3>\$WA6.UIM_MC.D )
  );
  X_ZERO \outDATA<3>\$WA6.UIM_MC.D1_1686  (
    .O(\outDATA<3>\$WA6.UIM_MC.D1 )
  );
  X_AND2 \outDATA<3>\$WA6.UIM_MC.D2_PT_0_1687  (
    .I0(DCOR0THRESLOWr),
    .I1(\U1/U4/Latch0r [3]),
    .O(\outDATA<3>\$WA6.UIM_MC.D2_PT_0 )
  );
  X_AND3 \outDATA<3>\$WA6.UIM_MC.D2_PT_1_1688  (
    .I0(DCORIFGr),
    .I1(\NlwInverterSignal_outDATA<3>\$WA6.UIM_MC.D2_PT_1/IN1 ),
    .I2(NET2493),
    .O(\outDATA<3>\$WA6.UIM_MC.D2_PT_1 )
  );
  X_AND4 \outDATA<3>\$WA6.UIM_MC.D2_PT_2_1689  (
    .I0(\NlwInverterSignal_outDATA<3>\$WA6.UIM_MC.D2_PT_2/IN0 ),
    .I1(\NlwInverterSignal_outDATA<3>\$WA6.UIM_MC.D2_PT_2/IN1 ),
    .I2(DCOR0THRESHIGHr),
    .I3(\U1/U4/Latch0r [11]),
    .O(\outDATA<3>\$WA6.UIM_MC.D2_PT_2 )
  );
  X_AND5 \outDATA<3>\$WA6.UIM_MC.D2_PT_3_1690  (
    .I0(\NlwInverterSignal_outDATA<3>\$WA6.UIM_MC.D2_PT_3/IN0 ),
    .I1(\NlwInverterSignal_outDATA<3>\$WA6.UIM_MC.D2_PT_3/IN1 ),
    .I2(\NlwInverterSignal_outDATA<3>\$WA6.UIM_MC.D2_PT_3/IN2 ),
    .I3(DCOR1THRESLOWr),
    .I4(\U1/U4/Latch1r [3]),
    .O(\outDATA<3>\$WA6.UIM_MC.D2_PT_3 )
  );
  X_AND5 \outDATA<3>\$WA6.UIM_MC.D2_PT_4_1691  (
    .I0(\NlwInverterSignal_outDATA<3>\$WA6.UIM_MC.D2_PT_4/IN0 ),
    .I1(\NlwInverterSignal_outDATA<3>\$WA6.UIM_MC.D2_PT_4/IN1 ),
    .I2(\NlwInverterSignal_outDATA<3>\$WA6.UIM_MC.D2_PT_4/IN2 ),
    .I3(\NlwInverterSignal_outDATA<3>\$WA6.UIM_MC.D2_PT_4/IN3 ),
    .I4(\U1/U4/Latch1r [11]),
    .O(\outDATA<3>\$WA6.UIM_MC.D2_PT_4 )
  );
  X_OR5 \outDATA<3>\$WA6.UIM_MC.D2_1692  (
    .I0(\outDATA<3>\$WA6.UIM_MC.D2_PT_0 ),
    .I1(\outDATA<3>\$WA6.UIM_MC.D2_PT_1 ),
    .I2(\outDATA<3>\$WA6.UIM_MC.D2_PT_2 ),
    .I3(\outDATA<3>\$WA6.UIM_MC.D2_PT_3 ),
    .I4(\outDATA<3>\$WA6.UIM_MC.D2_PT_4 ),
    .O(\outDATA<3>\$WA6.UIM_MC.D2 )
  );
  X_BUF \U1/U4/Latch0r<3>  (
    .I(\U1/U4/Latch0r<3>_MC.Q ),
    .O(\U1/U4/Latch0r [3])
  );
  X_FF \U1/U4/Latch0r<3>_MC.REG  (
    .I(\U1/U4/Latch0r<3>_MC.D ),
    .CE(Vcc),
    .CLK(\U1/U4/Latch0r<3>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\U1/U4/Latch0r<3>_MC.Q )
  );
  X_INV \U1/U4/Latch0r<3>_MC.REG_tsimcreated_inv_Mclk_II/FCLK_1693  (
    .I(\Mclk_II/FCLK ),
    .O(\U1/U4/Latch0r<3>_MC.REG_tsimcreated_inv_Mclk_II/FCLK )
  );
  X_XOR2 \U1/U4/Latch0r<3>_MC.D_1694  (
    .I0(\U1/U4/Latch0r<3>_MC.D1 ),
    .I1(\U1/U4/Latch0r<3>_MC.D2 ),
    .O(\U1/U4/Latch0r<3>_MC.D )
  );
  X_ZERO \U1/U4/Latch0r<3>_MC.D1_1695  (
    .O(\U1/U4/Latch0r<3>_MC.D1 )
  );
  X_AND3 \U1/U4/Latch0r<3>_MC.D2_PT_0_1696  (
    .I0(\MSPReset_II/UIM ),
    .I1(N_PZ_965),
    .I2(\U1/Channel0 [3]),
    .O(\U1/U4/Latch0r<3>_MC.D2_PT_0 )
  );
  X_AND3 \U1/U4/Latch0r<3>_MC.D2_PT_1_1697  (
    .I0(\MSPReset_II/UIM ),
    .I1(\NlwInverterSignal_U1/U4/Latch0r<3>_MC.D2_PT_1/IN1 ),
    .I2(\U1/U4/Latch0r [3]),
    .O(\U1/U4/Latch0r<3>_MC.D2_PT_1 )
  );
  X_OR2 \U1/U4/Latch0r<3>_MC.D2_1698  (
    .I0(\U1/U4/Latch0r<3>_MC.D2_PT_0 ),
    .I1(\U1/U4/Latch0r<3>_MC.D2_PT_1 ),
    .O(\U1/U4/Latch0r<3>_MC.D2 )
  );
  X_BUF \U1/U4/Latch0r<11>  (
    .I(\U1/U4/Latch0r<11>_MC.Q ),
    .O(\U1/U4/Latch0r [11])
  );
  X_FF \U1/U4/Latch0r<11>_MC.REG  (
    .I(\U1/U4/Latch0r<11>_MC.D ),
    .CE(Vcc),
    .CLK(\U1/U4/Latch0r<11>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\U1/U4/Latch0r<11>_MC.Q )
  );
  X_INV \U1/U4/Latch0r<11>_MC.REG_tsimcreated_inv_Mclk_II/FCLK_1699  (
    .I(\Mclk_II/FCLK ),
    .O(\U1/U4/Latch0r<11>_MC.REG_tsimcreated_inv_Mclk_II/FCLK )
  );
  X_XOR2 \U1/U4/Latch0r<11>_MC.D_1700  (
    .I0(\U1/U4/Latch0r<11>_MC.D1 ),
    .I1(\U1/U4/Latch0r<11>_MC.D2 ),
    .O(\U1/U4/Latch0r<11>_MC.D )
  );
  X_ZERO \U1/U4/Latch0r<11>_MC.D1_1701  (
    .O(\U1/U4/Latch0r<11>_MC.D1 )
  );
  X_AND3 \U1/U4/Latch0r<11>_MC.D2_PT_0_1702  (
    .I0(\MSPReset_II/UIM ),
    .I1(N_PZ_965),
    .I2(\U1/Channel0 [11]),
    .O(\U1/U4/Latch0r<11>_MC.D2_PT_0 )
  );
  X_AND3 \U1/U4/Latch0r<11>_MC.D2_PT_1_1703  (
    .I0(\MSPReset_II/UIM ),
    .I1(\NlwInverterSignal_U1/U4/Latch0r<11>_MC.D2_PT_1/IN1 ),
    .I2(\U1/U4/Latch0r [11]),
    .O(\U1/U4/Latch0r<11>_MC.D2_PT_1 )
  );
  X_OR2 \U1/U4/Latch0r<11>_MC.D2_1704  (
    .I0(\U1/U4/Latch0r<11>_MC.D2_PT_0 ),
    .I1(\U1/U4/Latch0r<11>_MC.D2_PT_1 ),
    .O(\U1/U4/Latch0r<11>_MC.D2 )
  );
  X_BUF \U1/U4/Latch1r<3>  (
    .I(\U1/U4/Latch1r<3>_MC.Q ),
    .O(\U1/U4/Latch1r [3])
  );
  X_FF \U1/U4/Latch1r<3>_MC.REG  (
    .I(\U1/U4/Latch1r<3>_MC.D ),
    .CE(Vcc),
    .CLK(\U1/U4/Latch1r<3>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\U1/U4/Latch1r<3>_MC.Q )
  );
  X_INV \U1/U4/Latch1r<3>_MC.REG_tsimcreated_inv_Mclk_II/FCLK_1705  (
    .I(\Mclk_II/FCLK ),
    .O(\U1/U4/Latch1r<3>_MC.REG_tsimcreated_inv_Mclk_II/FCLK )
  );
  X_XOR2 \U1/U4/Latch1r<3>_MC.D_1706  (
    .I0(\U1/U4/Latch1r<3>_MC.D1 ),
    .I1(\U1/U4/Latch1r<3>_MC.D2 ),
    .O(\U1/U4/Latch1r<3>_MC.D )
  );
  X_ZERO \U1/U4/Latch1r<3>_MC.D1_1707  (
    .O(\U1/U4/Latch1r<3>_MC.D1 )
  );
  X_AND2 \U1/U4/Latch1r<3>_MC.D2_PT_0_1708  (
    .I0(N_PZ_964),
    .I1(\U1/U4/Latch1r [3]),
    .O(\U1/U4/Latch1r<3>_MC.D2_PT_0 )
  );
  X_AND4 \U1/U4/Latch1r<3>_MC.D2_PT_1_1709  (
    .I0(\MSPReset_II/UIM ),
    .I1(\NlwInverterSignal_U1/U4/Latch1r<3>_MC.D2_PT_1/IN1 ),
    .I2(\NlwInverterSignal_U1/U4/Latch1r<3>_MC.D2_PT_1/IN2 ),
    .I3(\U1/Channel1 [3]),
    .O(\U1/U4/Latch1r<3>_MC.D2_PT_1 )
  );
  X_OR2 \U1/U4/Latch1r<3>_MC.D2_1710  (
    .I0(\U1/U4/Latch1r<3>_MC.D2_PT_0 ),
    .I1(\U1/U4/Latch1r<3>_MC.D2_PT_1 ),
    .O(\U1/U4/Latch1r<3>_MC.D2 )
  );
  X_BUF \U1/U4/Latch1r<11>  (
    .I(\U1/U4/Latch1r<11>_MC.Q ),
    .O(\U1/U4/Latch1r [11])
  );
  X_FF \U1/U4/Latch1r<11>_MC.REG  (
    .I(\U1/U4/Latch1r<11>_MC.D ),
    .CE(Vcc),
    .CLK(\U1/U4/Latch1r<11>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\U1/U4/Latch1r<11>_MC.Q )
  );
  X_INV \U1/U4/Latch1r<11>_MC.REG_tsimcreated_inv_Mclk_II/FCLK_1711  (
    .I(\Mclk_II/FCLK ),
    .O(\U1/U4/Latch1r<11>_MC.REG_tsimcreated_inv_Mclk_II/FCLK )
  );
  X_XOR2 \U1/U4/Latch1r<11>_MC.D_1712  (
    .I0(\U1/U4/Latch1r<11>_MC.D1 ),
    .I1(\U1/U4/Latch1r<11>_MC.D2 ),
    .O(\U1/U4/Latch1r<11>_MC.D )
  );
  X_ZERO \U1/U4/Latch1r<11>_MC.D1_1713  (
    .O(\U1/U4/Latch1r<11>_MC.D1 )
  );
  X_AND2 \U1/U4/Latch1r<11>_MC.D2_PT_0_1714  (
    .I0(N_PZ_964),
    .I1(\U1/U4/Latch1r [11]),
    .O(\U1/U4/Latch1r<11>_MC.D2_PT_0 )
  );
  X_AND4 \U1/U4/Latch1r<11>_MC.D2_PT_1_1715  (
    .I0(\MSPReset_II/UIM ),
    .I1(\NlwInverterSignal_U1/U4/Latch1r<11>_MC.D2_PT_1/IN1 ),
    .I2(\NlwInverterSignal_U1/U4/Latch1r<11>_MC.D2_PT_1/IN2 ),
    .I3(\U1/Channel1 [11]),
    .O(\U1/U4/Latch1r<11>_MC.D2_PT_1 )
  );
  X_OR2 \U1/U4/Latch1r<11>_MC.D2_1716  (
    .I0(\U1/U4/Latch1r<11>_MC.D2_PT_0 ),
    .I1(\U1/U4/Latch1r<11>_MC.D2_PT_1 ),
    .O(\U1/U4/Latch1r<11>_MC.D2 )
  );
  X_BUF \outDATA<4>\$WA0.UIM_1717  (
    .I(\outDATA<4>\$WA0.UIM_MC.Q ),
    .O(\outDATA<4>\$WA0.UIM )
  );
  X_BUF \outDATA<4>\$WA0.UIM_MC.Q_1718  (
    .I(\outDATA<4>\$WA0.UIM_MC.D ),
    .O(\outDATA<4>\$WA0.UIM_MC.Q )
  );
  X_XOR2 \outDATA<4>\$WA0.UIM_MC.D_1719  (
    .I0(\outDATA<4>\$WA0.UIM_MC.D1 ),
    .I1(\outDATA<4>\$WA0.UIM_MC.D2 ),
    .O(\outDATA<4>\$WA0.UIM_MC.D )
  );
  X_AND2 \outDATA<4>\$WA0.UIM_MC.D1_1720  (
    .I0(U11_U3_counterr[4]),
    .I1(U11_U3_counterr[4]),
    .O(\outDATA<4>\$WA0.UIM_MC.D1 )
  );
  X_ZERO \outDATA<4>\$WA0.UIM_MC.D2_1721  (
    .O(\outDATA<4>\$WA0.UIM_MC.D2 )
  );
  X_BUF \outDATA<4>\$WA1.UIM_1722  (
    .I(\outDATA<4>\$WA1.UIM_MC.Q ),
    .O(\outDATA<4>\$WA1.UIM )
  );
  X_BUF \outDATA<4>\$WA1.UIM_MC.Q_1723  (
    .I(\outDATA<4>\$WA1.UIM_MC.D ),
    .O(\outDATA<4>\$WA1.UIM_MC.Q )
  );
  X_XOR2 \outDATA<4>\$WA1.UIM_MC.D_1724  (
    .I0(\outDATA<4>\$WA1.UIM_MC.D1 ),
    .I1(\outDATA<4>\$WA1.UIM_MC.D2 ),
    .O(\outDATA<4>\$WA1.UIM_MC.D )
  );
  X_AND2 \outDATA<4>\$WA1.UIM_MC.D1_1725  (
    .I0(\I2CS<4>_II/UIM ),
    .I1(\I2CS<4>_II/UIM ),
    .O(\outDATA<4>\$WA1.UIM_MC.D1 )
  );
  X_ZERO \outDATA<4>\$WA1.UIM_MC.D2_1726  (
    .O(\outDATA<4>\$WA1.UIM_MC.D2 )
  );
  X_BUF \outDATA<4>\$WA2.UIM_1727  (
    .I(\outDATA<4>\$WA2.UIM_MC.Q ),
    .O(\outDATA<4>\$WA2.UIM )
  );
  X_BUF \outDATA<4>\$WA2.UIM_MC.Q_1728  (
    .I(\outDATA<4>\$WA2.UIM_MC.D ),
    .O(\outDATA<4>\$WA2.UIM_MC.Q )
  );
  X_XOR2 \outDATA<4>\$WA2.UIM_MC.D_1729  (
    .I0(\outDATA<4>\$WA2.UIM_MC.D1 ),
    .I1(\outDATA<4>\$WA2.UIM_MC.D2 ),
    .O(\outDATA<4>\$WA2.UIM_MC.D )
  );
  X_AND2 \outDATA<4>\$WA2.UIM_MC.D1_1730  (
    .I0(\RLS1_II/UIM ),
    .I1(\RLS1_II/UIM ),
    .O(\outDATA<4>\$WA2.UIM_MC.D1 )
  );
  X_ZERO \outDATA<4>\$WA2.UIM_MC.D2_1731  (
    .O(\outDATA<4>\$WA2.UIM_MC.D2 )
  );
  X_BUF \outDATA<4>\$WA3.UIM_1732  (
    .I(\outDATA<4>\$WA3.UIM_MC.Q ),
    .O(\outDATA<4>\$WA3.UIM )
  );
  X_BUF \outDATA<4>\$WA3.UIM_MC.Q_1733  (
    .I(\outDATA<4>\$WA3.UIM_MC.D ),
    .O(\outDATA<4>\$WA3.UIM_MC.Q )
  );
  X_XOR2 \outDATA<4>\$WA3.UIM_MC.D_1734  (
    .I0(\outDATA<4>\$WA3.UIM_MC.D1 ),
    .I1(\outDATA<4>\$WA3.UIM_MC.D2 ),
    .O(\outDATA<4>\$WA3.UIM_MC.D )
  );
  X_ZERO \outDATA<4>\$WA3.UIM_MC.D1_1735  (
    .O(\outDATA<4>\$WA3.UIM_MC.D1 )
  );
  X_AND2 \outDATA<4>\$WA3.UIM_MC.D2_PT_0_1736  (
    .I0(NET2528),
    .I1(\U4/Flgreg [4]),
    .O(\outDATA<4>\$WA3.UIM_MC.D2_PT_0 )
  );
  X_AND2 \outDATA<4>\$WA3.UIM_MC.D2_PT_1_1737  (
    .I0(\NlwInverterSignal_outDATA<4>\$WA3.UIM_MC.D2_PT_1/IN0 ),
    .I1(\Home133FLG_II/UIM ),
    .O(\outDATA<4>\$WA3.UIM_MC.D2_PT_1 )
  );
  X_OR2 \outDATA<4>\$WA3.UIM_MC.D2_1738  (
    .I0(\outDATA<4>\$WA3.UIM_MC.D2_PT_0 ),
    .I1(\outDATA<4>\$WA3.UIM_MC.D2_PT_1 ),
    .O(\outDATA<4>\$WA3.UIM_MC.D2 )
  );
  X_BUF \outDATA<4>\$WA4.UIM_1739  (
    .I(\outDATA<4>\$WA4.UIM_MC.Q ),
    .O(\outDATA<4>\$WA4.UIM )
  );
  X_BUF \outDATA<4>\$WA4.UIM_MC.Q_1740  (
    .I(\outDATA<4>\$WA4.UIM_MC.D ),
    .O(\outDATA<4>\$WA4.UIM_MC.Q )
  );
  X_XOR2 \outDATA<4>\$WA4.UIM_MC.D_1741  (
    .I0(\outDATA<4>\$WA4.UIM_MC.D1 ),
    .I1(\outDATA<4>\$WA4.UIM_MC.D2 ),
    .O(\outDATA<4>\$WA4.UIM_MC.D )
  );
  X_AND2 \outDATA<4>\$WA4.UIM_MC.D1_1742  (
    .I0(NET2575),
    .I1(NET2575),
    .O(\outDATA<4>\$WA4.UIM_MC.D1 )
  );
  X_ZERO \outDATA<4>\$WA4.UIM_MC.D2_1743  (
    .O(\outDATA<4>\$WA4.UIM_MC.D2 )
  );
  X_BUF \outDATA<4>\$WA6.UIM_1744  (
    .I(\outDATA<4>\$WA6.UIM_MC.Q ),
    .O(\outDATA<4>\$WA6.UIM )
  );
  X_BUF \outDATA<4>\$WA6.UIM_MC.Q_1745  (
    .I(\outDATA<4>\$WA6.UIM_MC.D ),
    .O(\outDATA<4>\$WA6.UIM_MC.Q )
  );
  X_XOR2 \outDATA<4>\$WA6.UIM_MC.D_1746  (
    .I0(\outDATA<4>\$WA6.UIM_MC.D1 ),
    .I1(\outDATA<4>\$WA6.UIM_MC.D2 ),
    .O(\outDATA<4>\$WA6.UIM_MC.D )
  );
  X_ZERO \outDATA<4>\$WA6.UIM_MC.D1_1747  (
    .O(\outDATA<4>\$WA6.UIM_MC.D1 )
  );
  X_AND2 \outDATA<4>\$WA6.UIM_MC.D2_PT_0_1748  (
    .I0(DCOR0THRESLOWr),
    .I1(\U1/U4/Latch0r [4]),
    .O(\outDATA<4>\$WA6.UIM_MC.D2_PT_0 )
  );
  X_AND3 \outDATA<4>\$WA6.UIM_MC.D2_PT_1_1749  (
    .I0(\NlwInverterSignal_outDATA<4>\$WA6.UIM_MC.D2_PT_1/IN0 ),
    .I1(DCOR0THRESHIGHr),
    .I2(\U1/U4/Latch0r [12]),
    .O(\outDATA<4>\$WA6.UIM_MC.D2_PT_1 )
  );
  X_AND4 \outDATA<4>\$WA6.UIM_MC.D2_PT_2_1750  (
    .I0(\NlwInverterSignal_outDATA<4>\$WA6.UIM_MC.D2_PT_2/IN0 ),
    .I1(\NlwInverterSignal_outDATA<4>\$WA6.UIM_MC.D2_PT_2/IN1 ),
    .I2(DCOR1THRESLOWr),
    .I3(\U1/U4/Latch1r [4]),
    .O(\outDATA<4>\$WA6.UIM_MC.D2_PT_2 )
  );
  X_AND4 \outDATA<4>\$WA6.UIM_MC.D2_PT_3_1751  (
    .I0(\NlwInverterSignal_outDATA<4>\$WA6.UIM_MC.D2_PT_3/IN0 ),
    .I1(\NlwInverterSignal_outDATA<4>\$WA6.UIM_MC.D2_PT_3/IN1 ),
    .I2(\NlwInverterSignal_outDATA<4>\$WA6.UIM_MC.D2_PT_3/IN2 ),
    .I3(\U1/U4/Latch1r [12]),
    .O(\outDATA<4>\$WA6.UIM_MC.D2_PT_3 )
  );
  X_OR4 \outDATA<4>\$WA6.UIM_MC.D2_1752  (
    .I0(\outDATA<4>\$WA6.UIM_MC.D2_PT_0 ),
    .I1(\outDATA<4>\$WA6.UIM_MC.D2_PT_1 ),
    .I2(\outDATA<4>\$WA6.UIM_MC.D2_PT_2 ),
    .I3(\outDATA<4>\$WA6.UIM_MC.D2_PT_3 ),
    .O(\outDATA<4>\$WA6.UIM_MC.D2 )
  );
  X_BUF \U1/U4/Latch0r<4>  (
    .I(\U1/U4/Latch0r<4>_MC.Q ),
    .O(\U1/U4/Latch0r [4])
  );
  X_FF \U1/U4/Latch0r<4>_MC.REG  (
    .I(\U1/U4/Latch0r<4>_MC.D ),
    .CE(Vcc),
    .CLK(\U1/U4/Latch0r<4>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\U1/U4/Latch0r<4>_MC.Q )
  );
  X_INV \U1/U4/Latch0r<4>_MC.REG_tsimcreated_inv_Mclk_II/FCLK_1753  (
    .I(\Mclk_II/FCLK ),
    .O(\U1/U4/Latch0r<4>_MC.REG_tsimcreated_inv_Mclk_II/FCLK )
  );
  X_XOR2 \U1/U4/Latch0r<4>_MC.D_1754  (
    .I0(\U1/U4/Latch0r<4>_MC.D1 ),
    .I1(\U1/U4/Latch0r<4>_MC.D2 ),
    .O(\U1/U4/Latch0r<4>_MC.D )
  );
  X_ZERO \U1/U4/Latch0r<4>_MC.D1_1755  (
    .O(\U1/U4/Latch0r<4>_MC.D1 )
  );
  X_AND3 \U1/U4/Latch0r<4>_MC.D2_PT_0_1756  (
    .I0(\MSPReset_II/UIM ),
    .I1(N_PZ_965),
    .I2(\U1/Channel0 [4]),
    .O(\U1/U4/Latch0r<4>_MC.D2_PT_0 )
  );
  X_AND3 \U1/U4/Latch0r<4>_MC.D2_PT_1_1757  (
    .I0(\MSPReset_II/UIM ),
    .I1(\NlwInverterSignal_U1/U4/Latch0r<4>_MC.D2_PT_1/IN1 ),
    .I2(\U1/U4/Latch0r [4]),
    .O(\U1/U4/Latch0r<4>_MC.D2_PT_1 )
  );
  X_OR2 \U1/U4/Latch0r<4>_MC.D2_1758  (
    .I0(\U1/U4/Latch0r<4>_MC.D2_PT_0 ),
    .I1(\U1/U4/Latch0r<4>_MC.D2_PT_1 ),
    .O(\U1/U4/Latch0r<4>_MC.D2 )
  );
  X_BUF \U1/U4/Latch0r<12>  (
    .I(\U1/U4/Latch0r<12>_MC.Q ),
    .O(\U1/U4/Latch0r [12])
  );
  X_FF \U1/U4/Latch0r<12>_MC.REG  (
    .I(\U1/U4/Latch0r<12>_MC.D ),
    .CE(Vcc),
    .CLK(\U1/U4/Latch0r<12>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\U1/U4/Latch0r<12>_MC.Q )
  );
  X_INV \U1/U4/Latch0r<12>_MC.REG_tsimcreated_inv_Mclk_II/FCLK_1759  (
    .I(\Mclk_II/FCLK ),
    .O(\U1/U4/Latch0r<12>_MC.REG_tsimcreated_inv_Mclk_II/FCLK )
  );
  X_XOR2 \U1/U4/Latch0r<12>_MC.D_1760  (
    .I0(\U1/U4/Latch0r<12>_MC.D1 ),
    .I1(\U1/U4/Latch0r<12>_MC.D2 ),
    .O(\U1/U4/Latch0r<12>_MC.D )
  );
  X_ZERO \U1/U4/Latch0r<12>_MC.D1_1761  (
    .O(\U1/U4/Latch0r<12>_MC.D1 )
  );
  X_AND3 \U1/U4/Latch0r<12>_MC.D2_PT_0_1762  (
    .I0(\MSPReset_II/UIM ),
    .I1(N_PZ_965),
    .I2(\U1/Channel0 [12]),
    .O(\U1/U4/Latch0r<12>_MC.D2_PT_0 )
  );
  X_AND3 \U1/U4/Latch0r<12>_MC.D2_PT_1_1763  (
    .I0(\MSPReset_II/UIM ),
    .I1(\NlwInverterSignal_U1/U4/Latch0r<12>_MC.D2_PT_1/IN1 ),
    .I2(\U1/U4/Latch0r [12]),
    .O(\U1/U4/Latch0r<12>_MC.D2_PT_1 )
  );
  X_OR2 \U1/U4/Latch0r<12>_MC.D2_1764  (
    .I0(\U1/U4/Latch0r<12>_MC.D2_PT_0 ),
    .I1(\U1/U4/Latch0r<12>_MC.D2_PT_1 ),
    .O(\U1/U4/Latch0r<12>_MC.D2 )
  );
  X_BUF \U1/Channel0<12>  (
    .I(\U1/Channel0<12>_MC.Q ),
    .O(\U1/Channel0 [12])
  );
  X_XOR2 \U1/Channel0<12>_MC_tsimcreated_xor__1765  (
    .I0(\U1/Channel0<12>_MC.D ),
    .I1(\U1/Channel0<12>_MC.Q ),
    .O(\U1/Channel0<12>_MC_tsimcreated_xor_ )
  );
  X_FF \U1/Channel0<12>_MC.REG  (
    .I(\U1/Channel0<12>_MC_tsimcreated_xor_ ),
    .CE(Vcc),
    .CLK(\Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\U1/Channel0<12>_MC.Q )
  );
  X_XOR2 \U1/Channel0<12>_MC.D_1766  (
    .I0(\U1/Channel0<12>_MC.D1 ),
    .I1(\U1/Channel0<12>_MC.D2 ),
    .O(\U1/Channel0<12>_MC.D )
  );
  X_ZERO \U1/Channel0<12>_MC.D1_1767  (
    .O(\U1/Channel0<12>_MC.D1 )
  );
  X_AND2 \U1/Channel0<12>_MC.D2_PT_0_1768  (
    .I0(\NlwInverterSignal_U1/Channel0<12>_MC.D2_PT_0/IN0 ),
    .I1(\U1/Channel0 [12]),
    .O(\U1/Channel0<12>_MC.D2_PT_0 )
  );
  X_AND5 \U1/Channel0<12>_MC.D2_PT_1_1769  (
    .I0(\U1/U2/location_Maddsub__n0000__n0075 [0]),
    .I1(N_PZ_966),
    .I2(\NlwInverterSignal_U1/Channel0<12>_MC.D2_PT_1/IN2 ),
    .I3(\NlwInverterSignal_U1/Channel0<12>_MC.D2_PT_1/IN3 ),
    .I4(\NlwInverterSignal_U1/Channel0<12>_MC.D2_PT_1/IN4 ),
    .O(\U1/Channel0<12>_MC.D2_PT_1 )
  );
  X_AND5 \U1/Channel0<12>_MC.D2_PT_2_1770  (
    .I0(\NlwInverterSignal_U1/Channel0<12>_MC.D2_PT_2/IN0 ),
    .I1(N_PZ_969),
    .I2(\U1/Channel0 [9]),
    .I3(\U1/Channel0 [10]),
    .I4(\U1/Channel0 [11]),
    .O(\U1/Channel0<12>_MC.D2_PT_2 )
  );
  X_OR3 \U1/Channel0<12>_MC.D2_1771  (
    .I0(\U1/Channel0<12>_MC.D2_PT_0 ),
    .I1(\U1/Channel0<12>_MC.D2_PT_1 ),
    .I2(\U1/Channel0<12>_MC.D2_PT_2 ),
    .O(\U1/Channel0<12>_MC.D2 )
  );
  X_BUF \U1/U4/Latch1r<4>  (
    .I(\U1/U4/Latch1r<4>_MC.Q ),
    .O(\U1/U4/Latch1r [4])
  );
  X_FF \U1/U4/Latch1r<4>_MC.REG  (
    .I(\U1/U4/Latch1r<4>_MC.D ),
    .CE(Vcc),
    .CLK(\U1/U4/Latch1r<4>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\U1/U4/Latch1r<4>_MC.Q )
  );
  X_INV \U1/U4/Latch1r<4>_MC.REG_tsimcreated_inv_Mclk_II/FCLK_1772  (
    .I(\Mclk_II/FCLK ),
    .O(\U1/U4/Latch1r<4>_MC.REG_tsimcreated_inv_Mclk_II/FCLK )
  );
  X_XOR2 \U1/U4/Latch1r<4>_MC.D_1773  (
    .I0(\U1/U4/Latch1r<4>_MC.D1 ),
    .I1(\U1/U4/Latch1r<4>_MC.D2 ),
    .O(\U1/U4/Latch1r<4>_MC.D )
  );
  X_ZERO \U1/U4/Latch1r<4>_MC.D1_1774  (
    .O(\U1/U4/Latch1r<4>_MC.D1 )
  );
  X_AND2 \U1/U4/Latch1r<4>_MC.D2_PT_0_1775  (
    .I0(N_PZ_964),
    .I1(\U1/U4/Latch1r [4]),
    .O(\U1/U4/Latch1r<4>_MC.D2_PT_0 )
  );
  X_AND4 \U1/U4/Latch1r<4>_MC.D2_PT_1_1776  (
    .I0(\MSPReset_II/UIM ),
    .I1(\NlwInverterSignal_U1/U4/Latch1r<4>_MC.D2_PT_1/IN1 ),
    .I2(\NlwInverterSignal_U1/U4/Latch1r<4>_MC.D2_PT_1/IN2 ),
    .I3(\U1/Channel1 [4]),
    .O(\U1/U4/Latch1r<4>_MC.D2_PT_1 )
  );
  X_OR2 \U1/U4/Latch1r<4>_MC.D2_1777  (
    .I0(\U1/U4/Latch1r<4>_MC.D2_PT_0 ),
    .I1(\U1/U4/Latch1r<4>_MC.D2_PT_1 ),
    .O(\U1/U4/Latch1r<4>_MC.D2 )
  );
  X_BUF \U1/U4/Latch1r<12>  (
    .I(\U1/U4/Latch1r<12>_MC.Q ),
    .O(\U1/U4/Latch1r [12])
  );
  X_FF \U1/U4/Latch1r<12>_MC.REG  (
    .I(\U1/U4/Latch1r<12>_MC.D ),
    .CE(Vcc),
    .CLK(\U1/U4/Latch1r<12>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\U1/U4/Latch1r<12>_MC.Q )
  );
  X_INV \U1/U4/Latch1r<12>_MC.REG_tsimcreated_inv_Mclk_II/FCLK_1778  (
    .I(\Mclk_II/FCLK ),
    .O(\U1/U4/Latch1r<12>_MC.REG_tsimcreated_inv_Mclk_II/FCLK )
  );
  X_XOR2 \U1/U4/Latch1r<12>_MC.D_1779  (
    .I0(\U1/U4/Latch1r<12>_MC.D1 ),
    .I1(\U1/U4/Latch1r<12>_MC.D2 ),
    .O(\U1/U4/Latch1r<12>_MC.D )
  );
  X_ZERO \U1/U4/Latch1r<12>_MC.D1_1780  (
    .O(\U1/U4/Latch1r<12>_MC.D1 )
  );
  X_AND2 \U1/U4/Latch1r<12>_MC.D2_PT_0_1781  (
    .I0(N_PZ_964),
    .I1(\U1/U4/Latch1r [12]),
    .O(\U1/U4/Latch1r<12>_MC.D2_PT_0 )
  );
  X_AND4 \U1/U4/Latch1r<12>_MC.D2_PT_1_1782  (
    .I0(\MSPReset_II/UIM ),
    .I1(\NlwInverterSignal_U1/U4/Latch1r<12>_MC.D2_PT_1/IN1 ),
    .I2(\NlwInverterSignal_U1/U4/Latch1r<12>_MC.D2_PT_1/IN2 ),
    .I3(\U1/Channel1 [12]),
    .O(\U1/U4/Latch1r<12>_MC.D2_PT_1 )
  );
  X_OR2 \U1/U4/Latch1r<12>_MC.D2_1783  (
    .I0(\U1/U4/Latch1r<12>_MC.D2_PT_0 ),
    .I1(\U1/U4/Latch1r<12>_MC.D2_PT_1 ),
    .O(\U1/U4/Latch1r<12>_MC.D2 )
  );
  X_BUF \U1/Channel1<12>  (
    .I(\U1/Channel1<12>_MC.Q ),
    .O(\U1/Channel1 [12])
  );
  X_XOR2 \U1/Channel1<12>_MC_tsimcreated_xor__1784  (
    .I0(\U1/Channel1<12>_MC.D ),
    .I1(\U1/Channel1<12>_MC.Q ),
    .O(\U1/Channel1<12>_MC_tsimcreated_xor_ )
  );
  X_FF \U1/Channel1<12>_MC.REG  (
    .I(\U1/Channel1<12>_MC_tsimcreated_xor_ ),
    .CE(Vcc),
    .CLK(\Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\U1/Channel1<12>_MC.Q )
  );
  X_XOR2 \U1/Channel1<12>_MC.D_1785  (
    .I0(\U1/Channel1<12>_MC.D1 ),
    .I1(\U1/Channel1<12>_MC.D2 ),
    .O(\U1/Channel1<12>_MC.D )
  );
  X_ZERO \U1/Channel1<12>_MC.D1_1786  (
    .O(\U1/Channel1<12>_MC.D1 )
  );
  X_AND2 \U1/Channel1<12>_MC.D2_PT_0_1787  (
    .I0(\NlwInverterSignal_U1/Channel1<12>_MC.D2_PT_0/IN0 ),
    .I1(\U1/Channel1 [12]),
    .O(\U1/Channel1<12>_MC.D2_PT_0 )
  );
  X_AND8 \U1/Channel1<12>_MC.D2_PT_1_1788  (
    .I0(\MSPReset_II/UIM ),
    .I1(\NlwInverterSignal_U1/Channel1<12>_MC.D2_PT_1/IN1 ),
    .I2(N_PZ_1155),
    .I3(N_PZ_1016),
    .I4(\NlwInverterSignal_U1/Channel1<12>_MC.D2_PT_1/IN4 ),
    .I5(\U1/Channel1 [9]),
    .I6(\U1/Channel1 [10]),
    .I7(\U1/Channel1 [11]),
    .O(\U1/Channel1<12>_MC.D2_PT_1 )
  );
  X_AND8 \U1/Channel1<12>_MC.D2_PT_2_1789  (
    .I0(\MSPReset_II/UIM ),
    .I1(\NlwInverterSignal_U1/Channel1<12>_MC.D2_PT_2/IN1 ),
    .I2(N_PZ_1155),
    .I3(\NlwInverterSignal_U1/Channel1<12>_MC.D2_PT_2/IN3 ),
    .I4(\U1/U5/location_Maddsub__n0000__n0075 [0]),
    .I5(\NlwInverterSignal_U1/Channel1<12>_MC.D2_PT_2/IN5 ),
    .I6(\NlwInverterSignal_U1/Channel1<12>_MC.D2_PT_2/IN6 ),
    .I7(\NlwInverterSignal_U1/Channel1<12>_MC.D2_PT_2/IN7 ),
    .O(\U1/Channel1<12>_MC.D2_PT_2 )
  );
  X_OR3 \U1/Channel1<12>_MC.D2_1790  (
    .I0(\U1/Channel1<12>_MC.D2_PT_0 ),
    .I1(\U1/Channel1<12>_MC.D2_PT_1 ),
    .I2(\U1/Channel1<12>_MC.D2_PT_2 ),
    .O(\U1/Channel1<12>_MC.D2 )
  );
  X_BUF \outDATA<4>\$WA5.UIM_1791  (
    .I(\outDATA<4>\$WA5.UIM_MC.Q ),
    .O(\outDATA<4>\$WA5.UIM )
  );
  X_BUF \outDATA<4>\$WA5.UIM_MC.Q_1792  (
    .I(\outDATA<4>\$WA5.UIM_MC.D ),
    .O(\outDATA<4>\$WA5.UIM_MC.Q )
  );
  X_XOR2 \outDATA<4>\$WA5.UIM_MC.D_1793  (
    .I0(\outDATA<4>\$WA5.UIM_MC.D1 ),
    .I1(\outDATA<4>\$WA5.UIM_MC.D2 ),
    .O(\outDATA<4>\$WA5.UIM_MC.D )
  );
  X_ZERO \outDATA<4>\$WA5.UIM_MC.D1_1794  (
    .O(\outDATA<4>\$WA5.UIM_MC.D1 )
  );
  X_AND2 \outDATA<4>\$WA5.UIM_MC.D2_PT_0_1795  (
    .I0(DCOR0CNTLOWr),
    .I1(\U1/U3/holdingreg0 [4]),
    .O(\outDATA<4>\$WA5.UIM_MC.D2_PT_0 )
  );
  X_AND3 \outDATA<4>\$WA5.UIM_MC.D2_PT_1_1796  (
    .I0(\NlwInverterSignal_outDATA<4>\$WA5.UIM_MC.D2_PT_1/IN0 ),
    .I1(DCOR1CNTLOWr),
    .I2(\U1/U3/holdingreg1 [4]),
    .O(\outDATA<4>\$WA5.UIM_MC.D2_PT_1 )
  );
  X_AND4 \outDATA<4>\$WA5.UIM_MC.D2_PT_2_1797  (
    .I0(\NlwInverterSignal_outDATA<4>\$WA5.UIM_MC.D2_PT_2/IN0 ),
    .I1(\NlwInverterSignal_outDATA<4>\$WA5.UIM_MC.D2_PT_2/IN1 ),
    .I2(DCOR0CNTHIGHr),
    .I3(\U1/U3/holdingreg0 [12]),
    .O(\outDATA<4>\$WA5.UIM_MC.D2_PT_2 )
  );
  X_AND4 \outDATA<4>\$WA5.UIM_MC.D2_PT_3_1798  (
    .I0(\NlwInverterSignal_outDATA<4>\$WA5.UIM_MC.D2_PT_3/IN0 ),
    .I1(\NlwInverterSignal_outDATA<4>\$WA5.UIM_MC.D2_PT_3/IN1 ),
    .I2(\NlwInverterSignal_outDATA<4>\$WA5.UIM_MC.D2_PT_3/IN2 ),
    .I3(\U1/U3/holdingreg1 [12]),
    .O(\outDATA<4>\$WA5.UIM_MC.D2_PT_3 )
  );
  X_OR4 \outDATA<4>\$WA5.UIM_MC.D2_1799  (
    .I0(\outDATA<4>\$WA5.UIM_MC.D2_PT_0 ),
    .I1(\outDATA<4>\$WA5.UIM_MC.D2_PT_1 ),
    .I2(\outDATA<4>\$WA5.UIM_MC.D2_PT_2 ),
    .I3(\outDATA<4>\$WA5.UIM_MC.D2_PT_3 ),
    .O(\outDATA<4>\$WA5.UIM_MC.D2 )
  );
  X_BUF \U1/U3/holdingreg0<4>  (
    .I(\U1/U3/holdingreg0<4>_MC.Q ),
    .O(\U1/U3/holdingreg0 [4])
  );
  X_FF \U1/U3/holdingreg0<4>_MC.REG  (
    .I(\U1/U3/holdingreg0<4>_MC.D ),
    .CE(Vcc),
    .CLK(\U1/U3/holdingreg0<4>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\U1/U3/holdingreg0<4>_MC.Q )
  );
  X_INV \U1/U3/holdingreg0<4>_MC.REG_tsimcreated_inv_Mclk_II/FCLK_1800  (
    .I(\Mclk_II/FCLK ),
    .O(\U1/U3/holdingreg0<4>_MC.REG_tsimcreated_inv_Mclk_II/FCLK )
  );
  X_XOR2 \U1/U3/holdingreg0<4>_MC.D_1801  (
    .I0(\U1/U3/holdingreg0<4>_MC.D1 ),
    .I1(\U1/U3/holdingreg0<4>_MC.D2 ),
    .O(\U1/U3/holdingreg0<4>_MC.D )
  );
  X_ZERO \U1/U3/holdingreg0<4>_MC.D1_1802  (
    .O(\U1/U3/holdingreg0<4>_MC.D1 )
  );
  X_AND2 \U1/U3/holdingreg0<4>_MC.D2_PT_0_1803  (
    .I0(N_PZ_941),
    .I1(\U1/U3/holdingreg0 [4]),
    .O(\U1/U3/holdingreg0<4>_MC.D2_PT_0 )
  );
  X_AND4 \U1/U3/holdingreg0<4>_MC.D2_PT_1_1804  (
    .I0(\MSPReset_II/UIM ),
    .I1(\NlwInverterSignal_U1/U3/holdingreg0<4>_MC.D2_PT_1/IN1 ),
    .I2(U2_ASedge),
    .I3(\U1/Channel0 [4]),
    .O(\U1/U3/holdingreg0<4>_MC.D2_PT_1 )
  );
  X_OR2 \U1/U3/holdingreg0<4>_MC.D2_1805  (
    .I0(\U1/U3/holdingreg0<4>_MC.D2_PT_0 ),
    .I1(\U1/U3/holdingreg0<4>_MC.D2_PT_1 ),
    .O(\U1/U3/holdingreg0<4>_MC.D2 )
  );
  X_BUF \U1/U3/holdingreg1<4>  (
    .I(\U1/U3/holdingreg1<4>_MC.Q ),
    .O(\U1/U3/holdingreg1 [4])
  );
  X_FF \U1/U3/holdingreg1<4>_MC.REG  (
    .I(\U1/U3/holdingreg1<4>_MC.D ),
    .CE(Vcc),
    .CLK(\U1/U3/holdingreg1<4>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\U1/U3/holdingreg1<4>_MC.Q )
  );
  X_INV \U1/U3/holdingreg1<4>_MC.REG_tsimcreated_inv_Mclk_II/FCLK_1806  (
    .I(\Mclk_II/FCLK ),
    .O(\U1/U3/holdingreg1<4>_MC.REG_tsimcreated_inv_Mclk_II/FCLK )
  );
  X_XOR2 \U1/U3/holdingreg1<4>_MC.D_1807  (
    .I0(\U1/U3/holdingreg1<4>_MC.D1 ),
    .I1(\U1/U3/holdingreg1<4>_MC.D2 ),
    .O(\U1/U3/holdingreg1<4>_MC.D )
  );
  X_ZERO \U1/U3/holdingreg1<4>_MC.D1_1808  (
    .O(\U1/U3/holdingreg1<4>_MC.D1 )
  );
  X_AND2 \U1/U3/holdingreg1<4>_MC.D2_PT_0_1809  (
    .I0(N_PZ_941),
    .I1(\U1/U3/holdingreg1 [4]),
    .O(\U1/U3/holdingreg1<4>_MC.D2_PT_0 )
  );
  X_AND4 \U1/U3/holdingreg1<4>_MC.D2_PT_1_1810  (
    .I0(\MSPReset_II/UIM ),
    .I1(\NlwInverterSignal_U1/U3/holdingreg1<4>_MC.D2_PT_1/IN1 ),
    .I2(U2_ASedge),
    .I3(\U1/Channel1 [4]),
    .O(\U1/U3/holdingreg1<4>_MC.D2_PT_1 )
  );
  X_OR2 \U1/U3/holdingreg1<4>_MC.D2_1811  (
    .I0(\U1/U3/holdingreg1<4>_MC.D2_PT_0 ),
    .I1(\U1/U3/holdingreg1<4>_MC.D2_PT_1 ),
    .O(\U1/U3/holdingreg1<4>_MC.D2 )
  );
  X_BUF \U1/U3/holdingreg0<12>  (
    .I(\U1/U3/holdingreg0<12>_MC.Q ),
    .O(\U1/U3/holdingreg0 [12])
  );
  X_FF \U1/U3/holdingreg0<12>_MC.REG  (
    .I(\U1/U3/holdingreg0<12>_MC.D ),
    .CE(Vcc),
    .CLK(\U1/U3/holdingreg0<12>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\U1/U3/holdingreg0<12>_MC.Q )
  );
  X_INV \U1/U3/holdingreg0<12>_MC.REG_tsimcreated_inv_Mclk_II/FCLK_1812  (
    .I(\Mclk_II/FCLK ),
    .O(\U1/U3/holdingreg0<12>_MC.REG_tsimcreated_inv_Mclk_II/FCLK )
  );
  X_XOR2 \U1/U3/holdingreg0<12>_MC.D_1813  (
    .I0(\U1/U3/holdingreg0<12>_MC.D1 ),
    .I1(\U1/U3/holdingreg0<12>_MC.D2 ),
    .O(\U1/U3/holdingreg0<12>_MC.D )
  );
  X_ZERO \U1/U3/holdingreg0<12>_MC.D1_1814  (
    .O(\U1/U3/holdingreg0<12>_MC.D1 )
  );
  X_AND2 \U1/U3/holdingreg0<12>_MC.D2_PT_0_1815  (
    .I0(N_PZ_941),
    .I1(\U1/U3/holdingreg0 [12]),
    .O(\U1/U3/holdingreg0<12>_MC.D2_PT_0 )
  );
  X_AND4 \U1/U3/holdingreg0<12>_MC.D2_PT_1_1816  (
    .I0(\MSPReset_II/UIM ),
    .I1(\NlwInverterSignal_U1/U3/holdingreg0<12>_MC.D2_PT_1/IN1 ),
    .I2(U2_ASedge),
    .I3(\U1/Channel0 [12]),
    .O(\U1/U3/holdingreg0<12>_MC.D2_PT_1 )
  );
  X_OR2 \U1/U3/holdingreg0<12>_MC.D2_1817  (
    .I0(\U1/U3/holdingreg0<12>_MC.D2_PT_0 ),
    .I1(\U1/U3/holdingreg0<12>_MC.D2_PT_1 ),
    .O(\U1/U3/holdingreg0<12>_MC.D2 )
  );
  X_BUF \U1/U3/holdingreg1<12>  (
    .I(\U1/U3/holdingreg1<12>_MC.Q ),
    .O(\U1/U3/holdingreg1 [12])
  );
  X_FF \U1/U3/holdingreg1<12>_MC.REG  (
    .I(\U1/U3/holdingreg1<12>_MC.D ),
    .CE(Vcc),
    .CLK(\U1/U3/holdingreg1<12>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\U1/U3/holdingreg1<12>_MC.Q )
  );
  X_INV \U1/U3/holdingreg1<12>_MC.REG_tsimcreated_inv_Mclk_II/FCLK_1818  (
    .I(\Mclk_II/FCLK ),
    .O(\U1/U3/holdingreg1<12>_MC.REG_tsimcreated_inv_Mclk_II/FCLK )
  );
  X_XOR2 \U1/U3/holdingreg1<12>_MC.D_1819  (
    .I0(\U1/U3/holdingreg1<12>_MC.D1 ),
    .I1(\U1/U3/holdingreg1<12>_MC.D2 ),
    .O(\U1/U3/holdingreg1<12>_MC.D )
  );
  X_ZERO \U1/U3/holdingreg1<12>_MC.D1_1820  (
    .O(\U1/U3/holdingreg1<12>_MC.D1 )
  );
  X_AND2 \U1/U3/holdingreg1<12>_MC.D2_PT_0_1821  (
    .I0(N_PZ_941),
    .I1(\U1/U3/holdingreg1 [12]),
    .O(\U1/U3/holdingreg1<12>_MC.D2_PT_0 )
  );
  X_AND4 \U1/U3/holdingreg1<12>_MC.D2_PT_1_1822  (
    .I0(\MSPReset_II/UIM ),
    .I1(\NlwInverterSignal_U1/U3/holdingreg1<12>_MC.D2_PT_1/IN1 ),
    .I2(U2_ASedge),
    .I3(\U1/Channel1 [12]),
    .O(\U1/U3/holdingreg1<12>_MC.D2_PT_1 )
  );
  X_OR2 \U1/U3/holdingreg1<12>_MC.D2_1823  (
    .I0(\U1/U3/holdingreg1<12>_MC.D2_PT_0 ),
    .I1(\U1/U3/holdingreg1<12>_MC.D2_PT_1 ),
    .O(\U1/U3/holdingreg1<12>_MC.D2 )
  );
  X_BUF \outDATA<5>\$WA0.UIM_1824  (
    .I(\outDATA<5>\$WA0.UIM_MC.Q ),
    .O(\outDATA<5>\$WA0.UIM )
  );
  X_BUF \outDATA<5>\$WA0.UIM_MC.Q_1825  (
    .I(\outDATA<5>\$WA0.UIM_MC.D ),
    .O(\outDATA<5>\$WA0.UIM_MC.Q )
  );
  X_XOR2 \outDATA<5>\$WA0.UIM_MC.D_1826  (
    .I0(\outDATA<5>\$WA0.UIM_MC.D1 ),
    .I1(\outDATA<5>\$WA0.UIM_MC.D2 ),
    .O(\outDATA<5>\$WA0.UIM_MC.D )
  );
  X_AND2 \outDATA<5>\$WA0.UIM_MC.D1_1827  (
    .I0(U11_U3_counterr[5]),
    .I1(U11_U3_counterr[5]),
    .O(\outDATA<5>\$WA0.UIM_MC.D1 )
  );
  X_ZERO \outDATA<5>\$WA0.UIM_MC.D2_1828  (
    .O(\outDATA<5>\$WA0.UIM_MC.D2 )
  );
  X_BUF \outDATA<5>\$WA1.UIM_1829  (
    .I(\outDATA<5>\$WA1.UIM_MC.Q ),
    .O(\outDATA<5>\$WA1.UIM )
  );
  X_BUF \outDATA<5>\$WA1.UIM_MC.Q_1830  (
    .I(\outDATA<5>\$WA1.UIM_MC.D ),
    .O(\outDATA<5>\$WA1.UIM_MC.Q )
  );
  X_XOR2 \outDATA<5>\$WA1.UIM_MC.D_1831  (
    .I0(\outDATA<5>\$WA1.UIM_MC.D1 ),
    .I1(\outDATA<5>\$WA1.UIM_MC.D2 ),
    .O(\outDATA<5>\$WA1.UIM_MC.D )
  );
  X_AND2 \outDATA<5>\$WA1.UIM_MC.D1_1832  (
    .I0(\I2CS<5>_II/UIM ),
    .I1(\I2CS<5>_II/UIM ),
    .O(\outDATA<5>\$WA1.UIM_MC.D1 )
  );
  X_ZERO \outDATA<5>\$WA1.UIM_MC.D2_1833  (
    .O(\outDATA<5>\$WA1.UIM_MC.D2 )
  );
  X_BUF \outDATA<5>\$WA2.UIM_1834  (
    .I(\outDATA<5>\$WA2.UIM_MC.Q ),
    .O(\outDATA<5>\$WA2.UIM )
  );
  X_BUF \outDATA<5>\$WA2.UIM_MC.Q_1835  (
    .I(\outDATA<5>\$WA2.UIM_MC.D ),
    .O(\outDATA<5>\$WA2.UIM_MC.Q )
  );
  X_XOR2 \outDATA<5>\$WA2.UIM_MC.D_1836  (
    .I0(\outDATA<5>\$WA2.UIM_MC.D1 ),
    .I1(\outDATA<5>\$WA2.UIM_MC.D2 ),
    .O(\outDATA<5>\$WA2.UIM_MC.D )
  );
  X_AND2 \outDATA<5>\$WA2.UIM_MC.D1_1837  (
    .I0(\FLS1_II/UIM ),
    .I1(\FLS1_II/UIM ),
    .O(\outDATA<5>\$WA2.UIM_MC.D1 )
  );
  X_ZERO \outDATA<5>\$WA2.UIM_MC.D2_1838  (
    .O(\outDATA<5>\$WA2.UIM_MC.D2 )
  );
  X_BUF \outDATA<5>\$WA3.UIM_1839  (
    .I(\outDATA<5>\$WA3.UIM_MC.Q ),
    .O(\outDATA<5>\$WA3.UIM )
  );
  X_BUF \outDATA<5>\$WA3.UIM_MC.Q_1840  (
    .I(\outDATA<5>\$WA3.UIM_MC.D ),
    .O(\outDATA<5>\$WA3.UIM_MC.Q )
  );
  X_XOR2 \outDATA<5>\$WA3.UIM_MC.D_1841  (
    .I0(\outDATA<5>\$WA3.UIM_MC.D1 ),
    .I1(\outDATA<5>\$WA3.UIM_MC.D2 ),
    .O(\outDATA<5>\$WA3.UIM_MC.D )
  );
  X_ZERO \outDATA<5>\$WA3.UIM_MC.D1_1842  (
    .O(\outDATA<5>\$WA3.UIM_MC.D1 )
  );
  X_AND2 \outDATA<5>\$WA3.UIM_MC.D2_PT_0_1843  (
    .I0(NET2528),
    .I1(\U4/Flgreg [5]),
    .O(\outDATA<5>\$WA3.UIM_MC.D2_PT_0 )
  );
  X_AND2 \outDATA<5>\$WA3.UIM_MC.D2_PT_1_1844  (
    .I0(\NlwInverterSignal_outDATA<5>\$WA3.UIM_MC.D2_PT_1/IN0 ),
    .I1(\Home15FLG_II/UIM ),
    .O(\outDATA<5>\$WA3.UIM_MC.D2_PT_1 )
  );
  X_OR2 \outDATA<5>\$WA3.UIM_MC.D2_1845  (
    .I0(\outDATA<5>\$WA3.UIM_MC.D2_PT_0 ),
    .I1(\outDATA<5>\$WA3.UIM_MC.D2_PT_1 ),
    .O(\outDATA<5>\$WA3.UIM_MC.D2 )
  );
  X_BUF \outDATA<5>\$WA5.UIM_1846  (
    .I(\outDATA<5>\$WA5.UIM_MC.Q ),
    .O(\outDATA<5>\$WA5.UIM )
  );
  X_BUF \outDATA<5>\$WA5.UIM_MC.Q_1847  (
    .I(\outDATA<5>\$WA5.UIM_MC.D ),
    .O(\outDATA<5>\$WA5.UIM_MC.Q )
  );
  X_XOR2 \outDATA<5>\$WA5.UIM_MC.D_1848  (
    .I0(\outDATA<5>\$WA5.UIM_MC.D1 ),
    .I1(\outDATA<5>\$WA5.UIM_MC.D2 ),
    .O(\outDATA<5>\$WA5.UIM_MC.D )
  );
  X_ZERO \outDATA<5>\$WA5.UIM_MC.D1_1849  (
    .O(\outDATA<5>\$WA5.UIM_MC.D1 )
  );
  X_AND2 \outDATA<5>\$WA5.UIM_MC.D2_PT_0_1850  (
    .I0(DCOR0CNTLOWr),
    .I1(\U1/U3/holdingreg0 [5]),
    .O(\outDATA<5>\$WA5.UIM_MC.D2_PT_0 )
  );
  X_AND3 \outDATA<5>\$WA5.UIM_MC.D2_PT_1_1851  (
    .I0(\NlwInverterSignal_outDATA<5>\$WA5.UIM_MC.D2_PT_1/IN0 ),
    .I1(DCOR1CNTLOWr),
    .I2(\U1/U3/holdingreg1 [5]),
    .O(\outDATA<5>\$WA5.UIM_MC.D2_PT_1 )
  );
  X_AND4 \outDATA<5>\$WA5.UIM_MC.D2_PT_2_1852  (
    .I0(\NlwInverterSignal_outDATA<5>\$WA5.UIM_MC.D2_PT_2/IN0 ),
    .I1(\NlwInverterSignal_outDATA<5>\$WA5.UIM_MC.D2_PT_2/IN1 ),
    .I2(DCOR0CNTHIGHr),
    .I3(\U1/U3/holdingreg0 [13]),
    .O(\outDATA<5>\$WA5.UIM_MC.D2_PT_2 )
  );
  X_AND4 \outDATA<5>\$WA5.UIM_MC.D2_PT_3_1853  (
    .I0(\NlwInverterSignal_outDATA<5>\$WA5.UIM_MC.D2_PT_3/IN0 ),
    .I1(\NlwInverterSignal_outDATA<5>\$WA5.UIM_MC.D2_PT_3/IN1 ),
    .I2(\NlwInverterSignal_outDATA<5>\$WA5.UIM_MC.D2_PT_3/IN2 ),
    .I3(\U1/U3/holdingreg1 [13]),
    .O(\outDATA<5>\$WA5.UIM_MC.D2_PT_3 )
  );
  X_OR4 \outDATA<5>\$WA5.UIM_MC.D2_1854  (
    .I0(\outDATA<5>\$WA5.UIM_MC.D2_PT_0 ),
    .I1(\outDATA<5>\$WA5.UIM_MC.D2_PT_1 ),
    .I2(\outDATA<5>\$WA5.UIM_MC.D2_PT_2 ),
    .I3(\outDATA<5>\$WA5.UIM_MC.D2_PT_3 ),
    .O(\outDATA<5>\$WA5.UIM_MC.D2 )
  );
  X_BUF \U1/U3/holdingreg0<5>  (
    .I(\U1/U3/holdingreg0<5>_MC.Q ),
    .O(\U1/U3/holdingreg0 [5])
  );
  X_FF \U1/U3/holdingreg0<5>_MC.REG  (
    .I(\U1/U3/holdingreg0<5>_MC.D ),
    .CE(Vcc),
    .CLK(\U1/U3/holdingreg0<5>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\U1/U3/holdingreg0<5>_MC.Q )
  );
  X_INV \U1/U3/holdingreg0<5>_MC.REG_tsimcreated_inv_Mclk_II/FCLK_1855  (
    .I(\Mclk_II/FCLK ),
    .O(\U1/U3/holdingreg0<5>_MC.REG_tsimcreated_inv_Mclk_II/FCLK )
  );
  X_XOR2 \U1/U3/holdingreg0<5>_MC.D_1856  (
    .I0(\U1/U3/holdingreg0<5>_MC.D1 ),
    .I1(\U1/U3/holdingreg0<5>_MC.D2 ),
    .O(\U1/U3/holdingreg0<5>_MC.D )
  );
  X_ZERO \U1/U3/holdingreg0<5>_MC.D1_1857  (
    .O(\U1/U3/holdingreg0<5>_MC.D1 )
  );
  X_AND2 \U1/U3/holdingreg0<5>_MC.D2_PT_0_1858  (
    .I0(N_PZ_941),
    .I1(\U1/U3/holdingreg0 [5]),
    .O(\U1/U3/holdingreg0<5>_MC.D2_PT_0 )
  );
  X_AND4 \U1/U3/holdingreg0<5>_MC.D2_PT_1_1859  (
    .I0(\MSPReset_II/UIM ),
    .I1(\NlwInverterSignal_U1/U3/holdingreg0<5>_MC.D2_PT_1/IN1 ),
    .I2(U2_ASedge),
    .I3(\U1/Channel0 [5]),
    .O(\U1/U3/holdingreg0<5>_MC.D2_PT_1 )
  );
  X_OR2 \U1/U3/holdingreg0<5>_MC.D2_1860  (
    .I0(\U1/U3/holdingreg0<5>_MC.D2_PT_0 ),
    .I1(\U1/U3/holdingreg0<5>_MC.D2_PT_1 ),
    .O(\U1/U3/holdingreg0<5>_MC.D2 )
  );
  X_BUF \U1/U3/holdingreg1<5>  (
    .I(\U1/U3/holdingreg1<5>_MC.Q ),
    .O(\U1/U3/holdingreg1 [5])
  );
  X_FF \U1/U3/holdingreg1<5>_MC.REG  (
    .I(\U1/U3/holdingreg1<5>_MC.D ),
    .CE(Vcc),
    .CLK(\U1/U3/holdingreg1<5>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\U1/U3/holdingreg1<5>_MC.Q )
  );
  X_INV \U1/U3/holdingreg1<5>_MC.REG_tsimcreated_inv_Mclk_II/FCLK_1861  (
    .I(\Mclk_II/FCLK ),
    .O(\U1/U3/holdingreg1<5>_MC.REG_tsimcreated_inv_Mclk_II/FCLK )
  );
  X_XOR2 \U1/U3/holdingreg1<5>_MC.D_1862  (
    .I0(\U1/U3/holdingreg1<5>_MC.D1 ),
    .I1(\U1/U3/holdingreg1<5>_MC.D2 ),
    .O(\U1/U3/holdingreg1<5>_MC.D )
  );
  X_ZERO \U1/U3/holdingreg1<5>_MC.D1_1863  (
    .O(\U1/U3/holdingreg1<5>_MC.D1 )
  );
  X_AND2 \U1/U3/holdingreg1<5>_MC.D2_PT_0_1864  (
    .I0(N_PZ_941),
    .I1(\U1/U3/holdingreg1 [5]),
    .O(\U1/U3/holdingreg1<5>_MC.D2_PT_0 )
  );
  X_AND4 \U1/U3/holdingreg1<5>_MC.D2_PT_1_1865  (
    .I0(\MSPReset_II/UIM ),
    .I1(\NlwInverterSignal_U1/U3/holdingreg1<5>_MC.D2_PT_1/IN1 ),
    .I2(U2_ASedge),
    .I3(\U1/Channel1 [5]),
    .O(\U1/U3/holdingreg1<5>_MC.D2_PT_1 )
  );
  X_OR2 \U1/U3/holdingreg1<5>_MC.D2_1866  (
    .I0(\U1/U3/holdingreg1<5>_MC.D2_PT_0 ),
    .I1(\U1/U3/holdingreg1<5>_MC.D2_PT_1 ),
    .O(\U1/U3/holdingreg1<5>_MC.D2 )
  );
  X_BUF \U1/U3/holdingreg0<13>  (
    .I(\U1/U3/holdingreg0<13>_MC.Q ),
    .O(\U1/U3/holdingreg0 [13])
  );
  X_FF \U1/U3/holdingreg0<13>_MC.REG  (
    .I(\U1/U3/holdingreg0<13>_MC.D ),
    .CE(Vcc),
    .CLK(\U1/U3/holdingreg0<13>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\U1/U3/holdingreg0<13>_MC.Q )
  );
  X_INV \U1/U3/holdingreg0<13>_MC.REG_tsimcreated_inv_Mclk_II/FCLK_1867  (
    .I(\Mclk_II/FCLK ),
    .O(\U1/U3/holdingreg0<13>_MC.REG_tsimcreated_inv_Mclk_II/FCLK )
  );
  X_XOR2 \U1/U3/holdingreg0<13>_MC.D_1868  (
    .I0(\U1/U3/holdingreg0<13>_MC.D1 ),
    .I1(\U1/U3/holdingreg0<13>_MC.D2 ),
    .O(\U1/U3/holdingreg0<13>_MC.D )
  );
  X_ZERO \U1/U3/holdingreg0<13>_MC.D1_1869  (
    .O(\U1/U3/holdingreg0<13>_MC.D1 )
  );
  X_AND2 \U1/U3/holdingreg0<13>_MC.D2_PT_0_1870  (
    .I0(N_PZ_941),
    .I1(\U1/U3/holdingreg0 [13]),
    .O(\U1/U3/holdingreg0<13>_MC.D2_PT_0 )
  );
  X_AND4 \U1/U3/holdingreg0<13>_MC.D2_PT_1_1871  (
    .I0(\MSPReset_II/UIM ),
    .I1(\NlwInverterSignal_U1/U3/holdingreg0<13>_MC.D2_PT_1/IN1 ),
    .I2(U2_ASedge),
    .I3(\U1/Channel0 [13]),
    .O(\U1/U3/holdingreg0<13>_MC.D2_PT_1 )
  );
  X_OR2 \U1/U3/holdingreg0<13>_MC.D2_1872  (
    .I0(\U1/U3/holdingreg0<13>_MC.D2_PT_0 ),
    .I1(\U1/U3/holdingreg0<13>_MC.D2_PT_1 ),
    .O(\U1/U3/holdingreg0<13>_MC.D2 )
  );
  X_BUF \U1/Channel0<13>  (
    .I(\U1/Channel0<13>_MC.Q ),
    .O(\U1/Channel0 [13])
  );
  X_XOR2 \U1/Channel0<13>_MC_tsimcreated_xor__1873  (
    .I0(\U1/Channel0<13>_MC.D ),
    .I1(\U1/Channel0<13>_MC.Q ),
    .O(\U1/Channel0<13>_MC_tsimcreated_xor_ )
  );
  X_FF \U1/Channel0<13>_MC.REG  (
    .I(\U1/Channel0<13>_MC_tsimcreated_xor_ ),
    .CE(Vcc),
    .CLK(\Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\U1/Channel0<13>_MC.Q )
  );
  X_XOR2 \U1/Channel0<13>_MC.D_1874  (
    .I0(\U1/Channel0<13>_MC.D1 ),
    .I1(\U1/Channel0<13>_MC.D2 ),
    .O(\U1/Channel0<13>_MC.D )
  );
  X_ZERO \U1/Channel0<13>_MC.D1_1875  (
    .O(\U1/Channel0<13>_MC.D1 )
  );
  X_AND2 \U1/Channel0<13>_MC.D2_PT_0_1876  (
    .I0(\NlwInverterSignal_U1/Channel0<13>_MC.D2_PT_0/IN0 ),
    .I1(\U1/Channel0 [13]),
    .O(\U1/Channel0<13>_MC.D2_PT_0 )
  );
  X_AND6 \U1/Channel0<13>_MC.D2_PT_1_1877  (
    .I0(\U1/U2/location_Maddsub__n0000__n0075 [0]),
    .I1(N_PZ_966),
    .I2(\NlwInverterSignal_U1/Channel0<13>_MC.D2_PT_1/IN2 ),
    .I3(\NlwInverterSignal_U1/Channel0<13>_MC.D2_PT_1/IN3 ),
    .I4(\NlwInverterSignal_U1/Channel0<13>_MC.D2_PT_1/IN4 ),
    .I5(\NlwInverterSignal_U1/Channel0<13>_MC.D2_PT_1/IN5 ),
    .O(\U1/Channel0<13>_MC.D2_PT_1 )
  );
  X_AND6 \U1/Channel0<13>_MC.D2_PT_2_1878  (
    .I0(\NlwInverterSignal_U1/Channel0<13>_MC.D2_PT_2/IN0 ),
    .I1(N_PZ_969),
    .I2(\U1/Channel0 [9]),
    .I3(\U1/Channel0 [10]),
    .I4(\U1/Channel0 [11]),
    .I5(\U1/Channel0 [12]),
    .O(\U1/Channel0<13>_MC.D2_PT_2 )
  );
  X_OR3 \U1/Channel0<13>_MC.D2_1879  (
    .I0(\U1/Channel0<13>_MC.D2_PT_0 ),
    .I1(\U1/Channel0<13>_MC.D2_PT_1 ),
    .I2(\U1/Channel0<13>_MC.D2_PT_2 ),
    .O(\U1/Channel0<13>_MC.D2 )
  );
  X_BUF \U1/U3/holdingreg1<13>  (
    .I(\U1/U3/holdingreg1<13>_MC.Q ),
    .O(\U1/U3/holdingreg1 [13])
  );
  X_FF \U1/U3/holdingreg1<13>_MC.REG  (
    .I(\U1/U3/holdingreg1<13>_MC.D ),
    .CE(Vcc),
    .CLK(\U1/U3/holdingreg1<13>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\U1/U3/holdingreg1<13>_MC.Q )
  );
  X_INV \U1/U3/holdingreg1<13>_MC.REG_tsimcreated_inv_Mclk_II/FCLK_1880  (
    .I(\Mclk_II/FCLK ),
    .O(\U1/U3/holdingreg1<13>_MC.REG_tsimcreated_inv_Mclk_II/FCLK )
  );
  X_XOR2 \U1/U3/holdingreg1<13>_MC.D_1881  (
    .I0(\U1/U3/holdingreg1<13>_MC.D1 ),
    .I1(\U1/U3/holdingreg1<13>_MC.D2 ),
    .O(\U1/U3/holdingreg1<13>_MC.D )
  );
  X_ZERO \U1/U3/holdingreg1<13>_MC.D1_1882  (
    .O(\U1/U3/holdingreg1<13>_MC.D1 )
  );
  X_AND2 \U1/U3/holdingreg1<13>_MC.D2_PT_0_1883  (
    .I0(N_PZ_941),
    .I1(\U1/U3/holdingreg1 [13]),
    .O(\U1/U3/holdingreg1<13>_MC.D2_PT_0 )
  );
  X_AND4 \U1/U3/holdingreg1<13>_MC.D2_PT_1_1884  (
    .I0(\MSPReset_II/UIM ),
    .I1(\NlwInverterSignal_U1/U3/holdingreg1<13>_MC.D2_PT_1/IN1 ),
    .I2(U2_ASedge),
    .I3(\U1/Channel1 [13]),
    .O(\U1/U3/holdingreg1<13>_MC.D2_PT_1 )
  );
  X_OR2 \U1/U3/holdingreg1<13>_MC.D2_1885  (
    .I0(\U1/U3/holdingreg1<13>_MC.D2_PT_0 ),
    .I1(\U1/U3/holdingreg1<13>_MC.D2_PT_1 ),
    .O(\U1/U3/holdingreg1<13>_MC.D2 )
  );
  X_BUF \U1/Channel1<13>  (
    .I(\U1/Channel1<13>_MC.Q ),
    .O(\U1/Channel1 [13])
  );
  X_XOR2 \U1/Channel1<13>_MC_tsimcreated_xor__1886  (
    .I0(\U1/Channel1<13>_MC.D ),
    .I1(\U1/Channel1<13>_MC.Q ),
    .O(\U1/Channel1<13>_MC_tsimcreated_xor_ )
  );
  X_FF \U1/Channel1<13>_MC.REG  (
    .I(\U1/Channel1<13>_MC_tsimcreated_xor_ ),
    .CE(Vcc),
    .CLK(\Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\U1/Channel1<13>_MC.Q )
  );
  X_XOR2 \U1/Channel1<13>_MC.D_1887  (
    .I0(\U1/Channel1<13>_MC.D1 ),
    .I1(\U1/Channel1<13>_MC.D2 ),
    .O(\U1/Channel1<13>_MC.D )
  );
  X_ZERO \U1/Channel1<13>_MC.D1_1888  (
    .O(\U1/Channel1<13>_MC.D1 )
  );
  X_AND2 \U1/Channel1<13>_MC.D2_PT_0_1889  (
    .I0(\NlwInverterSignal_U1/Channel1<13>_MC.D2_PT_0/IN0 ),
    .I1(\U1/Channel1 [13]),
    .O(\U1/Channel1<13>_MC.D2_PT_0 )
  );
  X_AND16 \U1/Channel1<13>_MC.D2_PT_1_1890  (
    .I0(\MSPReset_II/UIM ),
    .I1(\NlwInverterSignal_U1/Channel1<13>_MC.D2_PT_1/IN1 ),
    .I2(N_PZ_1155),
    .I3(N_PZ_1016),
    .I4(\NlwInverterSignal_U1/Channel1<13>_MC.D2_PT_1/IN4 ),
    .I5(\U1/Channel1 [9]),
    .I6(\U1/Channel1 [10]),
    .I7(\U1/Channel1 [11]),
    .I8(\U1/Channel1 [12]),
    .I9(Vcc),
    .I10(Vcc),
    .I11(Vcc),
    .I12(Vcc),
    .I13(Vcc),
    .I14(Vcc),
    .I15(Vcc),
    .O(\U1/Channel1<13>_MC.D2_PT_1 )
  );
  X_AND16 \U1/Channel1<13>_MC.D2_PT_2_1891  (
    .I0(\MSPReset_II/UIM ),
    .I1(\NlwInverterSignal_U1/Channel1<13>_MC.D2_PT_2/IN1 ),
    .I2(N_PZ_1155),
    .I3(\NlwInverterSignal_U1/Channel1<13>_MC.D2_PT_2/IN3 ),
    .I4(\U1/U5/location_Maddsub__n0000__n0075 [0]),
    .I5(\NlwInverterSignal_U1/Channel1<13>_MC.D2_PT_2/IN5 ),
    .I6(\NlwInverterSignal_U1/Channel1<13>_MC.D2_PT_2/IN6 ),
    .I7(\NlwInverterSignal_U1/Channel1<13>_MC.D2_PT_2/IN7 ),
    .I8(\NlwInverterSignal_U1/Channel1<13>_MC.D2_PT_2/IN8 ),
    .I9(Vcc),
    .I10(Vcc),
    .I11(Vcc),
    .I12(Vcc),
    .I13(Vcc),
    .I14(Vcc),
    .I15(Vcc),
    .O(\U1/Channel1<13>_MC.D2_PT_2 )
  );
  X_OR3 \U1/Channel1<13>_MC.D2_1892  (
    .I0(\U1/Channel1<13>_MC.D2_PT_0 ),
    .I1(\U1/Channel1<13>_MC.D2_PT_1 ),
    .I2(\U1/Channel1<13>_MC.D2_PT_2 ),
    .O(\U1/Channel1<13>_MC.D2 )
  );
  X_BUF \outDATA<5>\$WA6.UIM_1893  (
    .I(\outDATA<5>\$WA6.UIM_MC.Q ),
    .O(\outDATA<5>\$WA6.UIM )
  );
  X_BUF \outDATA<5>\$WA6.UIM_MC.Q_1894  (
    .I(\outDATA<5>\$WA6.UIM_MC.D ),
    .O(\outDATA<5>\$WA6.UIM_MC.Q )
  );
  X_XOR2 \outDATA<5>\$WA6.UIM_MC.D_1895  (
    .I0(\outDATA<5>\$WA6.UIM_MC.D1 ),
    .I1(\outDATA<5>\$WA6.UIM_MC.D2 ),
    .O(\outDATA<5>\$WA6.UIM_MC.D )
  );
  X_ZERO \outDATA<5>\$WA6.UIM_MC.D1_1896  (
    .O(\outDATA<5>\$WA6.UIM_MC.D1 )
  );
  X_AND2 \outDATA<5>\$WA6.UIM_MC.D2_PT_0_1897  (
    .I0(DCOR0THRESLOWr),
    .I1(\U1/U4/Latch0r [5]),
    .O(\outDATA<5>\$WA6.UIM_MC.D2_PT_0 )
  );
  X_AND3 \outDATA<5>\$WA6.UIM_MC.D2_PT_1_1898  (
    .I0(DCORIFGr),
    .I1(\NlwInverterSignal_outDATA<5>\$WA6.UIM_MC.D2_PT_1/IN1 ),
    .I2(NET2501),
    .O(\outDATA<5>\$WA6.UIM_MC.D2_PT_1 )
  );
  X_AND4 \outDATA<5>\$WA6.UIM_MC.D2_PT_2_1899  (
    .I0(\NlwInverterSignal_outDATA<5>\$WA6.UIM_MC.D2_PT_2/IN0 ),
    .I1(\NlwInverterSignal_outDATA<5>\$WA6.UIM_MC.D2_PT_2/IN1 ),
    .I2(DCOR0THRESHIGHr),
    .I3(\U1/U4/Latch0r [13]),
    .O(\outDATA<5>\$WA6.UIM_MC.D2_PT_2 )
  );
  X_AND5 \outDATA<5>\$WA6.UIM_MC.D2_PT_3_1900  (
    .I0(\NlwInverterSignal_outDATA<5>\$WA6.UIM_MC.D2_PT_3/IN0 ),
    .I1(\NlwInverterSignal_outDATA<5>\$WA6.UIM_MC.D2_PT_3/IN1 ),
    .I2(\NlwInverterSignal_outDATA<5>\$WA6.UIM_MC.D2_PT_3/IN2 ),
    .I3(DCOR1THRESLOWr),
    .I4(\U1/U4/Latch1r [5]),
    .O(\outDATA<5>\$WA6.UIM_MC.D2_PT_3 )
  );
  X_AND5 \outDATA<5>\$WA6.UIM_MC.D2_PT_4_1901  (
    .I0(\NlwInverterSignal_outDATA<5>\$WA6.UIM_MC.D2_PT_4/IN0 ),
    .I1(\NlwInverterSignal_outDATA<5>\$WA6.UIM_MC.D2_PT_4/IN1 ),
    .I2(\NlwInverterSignal_outDATA<5>\$WA6.UIM_MC.D2_PT_4/IN2 ),
    .I3(\NlwInverterSignal_outDATA<5>\$WA6.UIM_MC.D2_PT_4/IN3 ),
    .I4(\U1/U4/Latch1r [13]),
    .O(\outDATA<5>\$WA6.UIM_MC.D2_PT_4 )
  );
  X_OR5 \outDATA<5>\$WA6.UIM_MC.D2_1902  (
    .I0(\outDATA<5>\$WA6.UIM_MC.D2_PT_0 ),
    .I1(\outDATA<5>\$WA6.UIM_MC.D2_PT_1 ),
    .I2(\outDATA<5>\$WA6.UIM_MC.D2_PT_2 ),
    .I3(\outDATA<5>\$WA6.UIM_MC.D2_PT_3 ),
    .I4(\outDATA<5>\$WA6.UIM_MC.D2_PT_4 ),
    .O(\outDATA<5>\$WA6.UIM_MC.D2 )
  );
  X_BUF \U1/U4/Latch0r<5>  (
    .I(\U1/U4/Latch0r<5>_MC.Q ),
    .O(\U1/U4/Latch0r [5])
  );
  X_FF \U1/U4/Latch0r<5>_MC.REG  (
    .I(\U1/U4/Latch0r<5>_MC.D ),
    .CE(Vcc),
    .CLK(\U1/U4/Latch0r<5>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\U1/U4/Latch0r<5>_MC.Q )
  );
  X_INV \U1/U4/Latch0r<5>_MC.REG_tsimcreated_inv_Mclk_II/FCLK_1903  (
    .I(\Mclk_II/FCLK ),
    .O(\U1/U4/Latch0r<5>_MC.REG_tsimcreated_inv_Mclk_II/FCLK )
  );
  X_XOR2 \U1/U4/Latch0r<5>_MC.D_1904  (
    .I0(\U1/U4/Latch0r<5>_MC.D1 ),
    .I1(\U1/U4/Latch0r<5>_MC.D2 ),
    .O(\U1/U4/Latch0r<5>_MC.D )
  );
  X_ZERO \U1/U4/Latch0r<5>_MC.D1_1905  (
    .O(\U1/U4/Latch0r<5>_MC.D1 )
  );
  X_AND3 \U1/U4/Latch0r<5>_MC.D2_PT_0_1906  (
    .I0(\MSPReset_II/UIM ),
    .I1(N_PZ_965),
    .I2(\U1/Channel0 [5]),
    .O(\U1/U4/Latch0r<5>_MC.D2_PT_0 )
  );
  X_AND3 \U1/U4/Latch0r<5>_MC.D2_PT_1_1907  (
    .I0(\MSPReset_II/UIM ),
    .I1(\NlwInverterSignal_U1/U4/Latch0r<5>_MC.D2_PT_1/IN1 ),
    .I2(\U1/U4/Latch0r [5]),
    .O(\U1/U4/Latch0r<5>_MC.D2_PT_1 )
  );
  X_OR2 \U1/U4/Latch0r<5>_MC.D2_1908  (
    .I0(\U1/U4/Latch0r<5>_MC.D2_PT_0 ),
    .I1(\U1/U4/Latch0r<5>_MC.D2_PT_1 ),
    .O(\U1/U4/Latch0r<5>_MC.D2 )
  );
  X_BUF \U1/U4/Latch0r<13>  (
    .I(\U1/U4/Latch0r<13>_MC.Q ),
    .O(\U1/U4/Latch0r [13])
  );
  X_FF \U1/U4/Latch0r<13>_MC.REG  (
    .I(\U1/U4/Latch0r<13>_MC.D ),
    .CE(Vcc),
    .CLK(\U1/U4/Latch0r<13>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\U1/U4/Latch0r<13>_MC.Q )
  );
  X_INV \U1/U4/Latch0r<13>_MC.REG_tsimcreated_inv_Mclk_II/FCLK_1909  (
    .I(\Mclk_II/FCLK ),
    .O(\U1/U4/Latch0r<13>_MC.REG_tsimcreated_inv_Mclk_II/FCLK )
  );
  X_XOR2 \U1/U4/Latch0r<13>_MC.D_1910  (
    .I0(\U1/U4/Latch0r<13>_MC.D1 ),
    .I1(\U1/U4/Latch0r<13>_MC.D2 ),
    .O(\U1/U4/Latch0r<13>_MC.D )
  );
  X_ZERO \U1/U4/Latch0r<13>_MC.D1_1911  (
    .O(\U1/U4/Latch0r<13>_MC.D1 )
  );
  X_AND3 \U1/U4/Latch0r<13>_MC.D2_PT_0_1912  (
    .I0(\MSPReset_II/UIM ),
    .I1(N_PZ_965),
    .I2(\U1/Channel0 [13]),
    .O(\U1/U4/Latch0r<13>_MC.D2_PT_0 )
  );
  X_AND3 \U1/U4/Latch0r<13>_MC.D2_PT_1_1913  (
    .I0(\MSPReset_II/UIM ),
    .I1(\NlwInverterSignal_U1/U4/Latch0r<13>_MC.D2_PT_1/IN1 ),
    .I2(\U1/U4/Latch0r [13]),
    .O(\U1/U4/Latch0r<13>_MC.D2_PT_1 )
  );
  X_OR2 \U1/U4/Latch0r<13>_MC.D2_1914  (
    .I0(\U1/U4/Latch0r<13>_MC.D2_PT_0 ),
    .I1(\U1/U4/Latch0r<13>_MC.D2_PT_1 ),
    .O(\U1/U4/Latch0r<13>_MC.D2 )
  );
  X_BUF \U1/U4/Latch1r<5>  (
    .I(\U1/U4/Latch1r<5>_MC.Q ),
    .O(\U1/U4/Latch1r [5])
  );
  X_FF \U1/U4/Latch1r<5>_MC.REG  (
    .I(\U1/U4/Latch1r<5>_MC.D ),
    .CE(Vcc),
    .CLK(\U1/U4/Latch1r<5>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\U1/U4/Latch1r<5>_MC.Q )
  );
  X_INV \U1/U4/Latch1r<5>_MC.REG_tsimcreated_inv_Mclk_II/FCLK_1915  (
    .I(\Mclk_II/FCLK ),
    .O(\U1/U4/Latch1r<5>_MC.REG_tsimcreated_inv_Mclk_II/FCLK )
  );
  X_XOR2 \U1/U4/Latch1r<5>_MC.D_1916  (
    .I0(\U1/U4/Latch1r<5>_MC.D1 ),
    .I1(\U1/U4/Latch1r<5>_MC.D2 ),
    .O(\U1/U4/Latch1r<5>_MC.D )
  );
  X_ZERO \U1/U4/Latch1r<5>_MC.D1_1917  (
    .O(\U1/U4/Latch1r<5>_MC.D1 )
  );
  X_AND2 \U1/U4/Latch1r<5>_MC.D2_PT_0_1918  (
    .I0(N_PZ_964),
    .I1(\U1/U4/Latch1r [5]),
    .O(\U1/U4/Latch1r<5>_MC.D2_PT_0 )
  );
  X_AND4 \U1/U4/Latch1r<5>_MC.D2_PT_1_1919  (
    .I0(\MSPReset_II/UIM ),
    .I1(\NlwInverterSignal_U1/U4/Latch1r<5>_MC.D2_PT_1/IN1 ),
    .I2(\NlwInverterSignal_U1/U4/Latch1r<5>_MC.D2_PT_1/IN2 ),
    .I3(\U1/Channel1 [5]),
    .O(\U1/U4/Latch1r<5>_MC.D2_PT_1 )
  );
  X_OR2 \U1/U4/Latch1r<5>_MC.D2_1920  (
    .I0(\U1/U4/Latch1r<5>_MC.D2_PT_0 ),
    .I1(\U1/U4/Latch1r<5>_MC.D2_PT_1 ),
    .O(\U1/U4/Latch1r<5>_MC.D2 )
  );
  X_BUF \U1/U4/Latch1r<13>  (
    .I(\U1/U4/Latch1r<13>_MC.Q ),
    .O(\U1/U4/Latch1r [13])
  );
  X_FF \U1/U4/Latch1r<13>_MC.REG  (
    .I(\U1/U4/Latch1r<13>_MC.D ),
    .CE(Vcc),
    .CLK(\U1/U4/Latch1r<13>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\U1/U4/Latch1r<13>_MC.Q )
  );
  X_INV \U1/U4/Latch1r<13>_MC.REG_tsimcreated_inv_Mclk_II/FCLK_1921  (
    .I(\Mclk_II/FCLK ),
    .O(\U1/U4/Latch1r<13>_MC.REG_tsimcreated_inv_Mclk_II/FCLK )
  );
  X_XOR2 \U1/U4/Latch1r<13>_MC.D_1922  (
    .I0(\U1/U4/Latch1r<13>_MC.D1 ),
    .I1(\U1/U4/Latch1r<13>_MC.D2 ),
    .O(\U1/U4/Latch1r<13>_MC.D )
  );
  X_ZERO \U1/U4/Latch1r<13>_MC.D1_1923  (
    .O(\U1/U4/Latch1r<13>_MC.D1 )
  );
  X_AND2 \U1/U4/Latch1r<13>_MC.D2_PT_0_1924  (
    .I0(N_PZ_964),
    .I1(\U1/U4/Latch1r [13]),
    .O(\U1/U4/Latch1r<13>_MC.D2_PT_0 )
  );
  X_AND4 \U1/U4/Latch1r<13>_MC.D2_PT_1_1925  (
    .I0(\MSPReset_II/UIM ),
    .I1(\NlwInverterSignal_U1/U4/Latch1r<13>_MC.D2_PT_1/IN1 ),
    .I2(\NlwInverterSignal_U1/U4/Latch1r<13>_MC.D2_PT_1/IN2 ),
    .I3(\U1/Channel1 [13]),
    .O(\U1/U4/Latch1r<13>_MC.D2_PT_1 )
  );
  X_OR2 \U1/U4/Latch1r<13>_MC.D2_1926  (
    .I0(\U1/U4/Latch1r<13>_MC.D2_PT_0 ),
    .I1(\U1/U4/Latch1r<13>_MC.D2_PT_1 ),
    .O(\U1/U4/Latch1r<13>_MC.D2 )
  );
  X_BUF \outDATA<6>\$WA0.UIM_1927  (
    .I(\outDATA<6>\$WA0.UIM_MC.Q ),
    .O(\outDATA<6>\$WA0.UIM )
  );
  X_BUF \outDATA<6>\$WA0.UIM_MC.Q_1928  (
    .I(\outDATA<6>\$WA0.UIM_MC.D ),
    .O(\outDATA<6>\$WA0.UIM_MC.Q )
  );
  X_XOR2 \outDATA<6>\$WA0.UIM_MC.D_1929  (
    .I0(\outDATA<6>\$WA0.UIM_MC.D1 ),
    .I1(\outDATA<6>\$WA0.UIM_MC.D2 ),
    .O(\outDATA<6>\$WA0.UIM_MC.D )
  );
  X_ZERO \outDATA<6>\$WA0.UIM_MC.D1_1930  (
    .O(\outDATA<6>\$WA0.UIM_MC.D1 )
  );
  X_ZERO \outDATA<6>\$WA0.UIM_MC.D2_1931  (
    .O(\outDATA<6>\$WA0.UIM_MC.D2 )
  );
  X_BUF \outDATA<6>\$WA2.UIM_1932  (
    .I(\outDATA<6>\$WA2.UIM_MC.Q ),
    .O(\outDATA<6>\$WA2.UIM )
  );
  X_BUF \outDATA<6>\$WA2.UIM_MC.Q_1933  (
    .I(\outDATA<6>\$WA2.UIM_MC.D ),
    .O(\outDATA<6>\$WA2.UIM_MC.Q )
  );
  X_XOR2 \outDATA<6>\$WA2.UIM_MC.D_1934  (
    .I0(\outDATA<6>\$WA2.UIM_MC.D1 ),
    .I1(\outDATA<6>\$WA2.UIM_MC.D2 ),
    .O(\outDATA<6>\$WA2.UIM_MC.D )
  );
  X_AND2 \outDATA<6>\$WA2.UIM_MC.D1_1935  (
    .I0(\Home1_II/UIM ),
    .I1(\Home1_II/UIM ),
    .O(\outDATA<6>\$WA2.UIM_MC.D1 )
  );
  X_ZERO \outDATA<6>\$WA2.UIM_MC.D2_1936  (
    .O(\outDATA<6>\$WA2.UIM_MC.D2 )
  );
  X_BUF \outDATA<6>\$WA3.UIM_1937  (
    .I(\outDATA<6>\$WA3.UIM_MC.Q ),
    .O(\outDATA<6>\$WA3.UIM )
  );
  X_BUF \outDATA<6>\$WA3.UIM_MC.Q_1938  (
    .I(\outDATA<6>\$WA3.UIM_MC.D ),
    .O(\outDATA<6>\$WA3.UIM_MC.Q )
  );
  X_XOR2 \outDATA<6>\$WA3.UIM_MC.D_1939  (
    .I0(\outDATA<6>\$WA3.UIM_MC.D1 ),
    .I1(\outDATA<6>\$WA3.UIM_MC.D2 ),
    .O(\outDATA<6>\$WA3.UIM_MC.D )
  );
  X_ZERO \outDATA<6>\$WA3.UIM_MC.D1_1940  (
    .O(\outDATA<6>\$WA3.UIM_MC.D1 )
  );
  X_AND2 \outDATA<6>\$WA3.UIM_MC.D2_PT_0_1941  (
    .I0(NET2528),
    .I1(\U4/Flgreg [6]),
    .O(\outDATA<6>\$WA3.UIM_MC.D2_PT_0 )
  );
  X_AND2 \outDATA<6>\$WA3.UIM_MC.D2_PT_1_1942  (
    .I0(\NlwInverterSignal_outDATA<6>\$WA3.UIM_MC.D2_PT_1/IN0 ),
    .I1(\Enc133FLG_II/UIM ),
    .O(\outDATA<6>\$WA3.UIM_MC.D2_PT_1 )
  );
  X_OR2 \outDATA<6>\$WA3.UIM_MC.D2_1943  (
    .I0(\outDATA<6>\$WA3.UIM_MC.D2_PT_0 ),
    .I1(\outDATA<6>\$WA3.UIM_MC.D2_PT_1 ),
    .O(\outDATA<6>\$WA3.UIM_MC.D2 )
  );
  X_BUF \outDATA<6>\$WA5.UIM_1944  (
    .I(\outDATA<6>\$WA5.UIM_MC.Q ),
    .O(\outDATA<6>\$WA5.UIM )
  );
  X_BUF \outDATA<6>\$WA5.UIM_MC.Q_1945  (
    .I(\outDATA<6>\$WA5.UIM_MC.D ),
    .O(\outDATA<6>\$WA5.UIM_MC.Q )
  );
  X_XOR2 \outDATA<6>\$WA5.UIM_MC.D_1946  (
    .I0(\outDATA<6>\$WA5.UIM_MC.D1 ),
    .I1(\outDATA<6>\$WA5.UIM_MC.D2 ),
    .O(\outDATA<6>\$WA5.UIM_MC.D )
  );
  X_ZERO \outDATA<6>\$WA5.UIM_MC.D1_1947  (
    .O(\outDATA<6>\$WA5.UIM_MC.D1 )
  );
  X_AND2 \outDATA<6>\$WA5.UIM_MC.D2_PT_0_1948  (
    .I0(DCOR0CNTLOWr),
    .I1(\U1/U3/holdingreg0 [6]),
    .O(\outDATA<6>\$WA5.UIM_MC.D2_PT_0 )
  );
  X_AND3 \outDATA<6>\$WA5.UIM_MC.D2_PT_1_1949  (
    .I0(\NlwInverterSignal_outDATA<6>\$WA5.UIM_MC.D2_PT_1/IN0 ),
    .I1(DCOR1CNTLOWr),
    .I2(\U1/U3/holdingreg1 [6]),
    .O(\outDATA<6>\$WA5.UIM_MC.D2_PT_1 )
  );
  X_AND4 \outDATA<6>\$WA5.UIM_MC.D2_PT_2_1950  (
    .I0(\NlwInverterSignal_outDATA<6>\$WA5.UIM_MC.D2_PT_2/IN0 ),
    .I1(\NlwInverterSignal_outDATA<6>\$WA5.UIM_MC.D2_PT_2/IN1 ),
    .I2(DCOR0CNTHIGHr),
    .I3(\U1/U3/holdingreg0 [14]),
    .O(\outDATA<6>\$WA5.UIM_MC.D2_PT_2 )
  );
  X_AND4 \outDATA<6>\$WA5.UIM_MC.D2_PT_3_1951  (
    .I0(\NlwInverterSignal_outDATA<6>\$WA5.UIM_MC.D2_PT_3/IN0 ),
    .I1(\NlwInverterSignal_outDATA<6>\$WA5.UIM_MC.D2_PT_3/IN1 ),
    .I2(\NlwInverterSignal_outDATA<6>\$WA5.UIM_MC.D2_PT_3/IN2 ),
    .I3(\U1/U3/holdingreg1 [14]),
    .O(\outDATA<6>\$WA5.UIM_MC.D2_PT_3 )
  );
  X_OR4 \outDATA<6>\$WA5.UIM_MC.D2_1952  (
    .I0(\outDATA<6>\$WA5.UIM_MC.D2_PT_0 ),
    .I1(\outDATA<6>\$WA5.UIM_MC.D2_PT_1 ),
    .I2(\outDATA<6>\$WA5.UIM_MC.D2_PT_2 ),
    .I3(\outDATA<6>\$WA5.UIM_MC.D2_PT_3 ),
    .O(\outDATA<6>\$WA5.UIM_MC.D2 )
  );
  X_BUF \U1/U3/holdingreg0<6>  (
    .I(\U1/U3/holdingreg0<6>_MC.Q ),
    .O(\U1/U3/holdingreg0 [6])
  );
  X_FF \U1/U3/holdingreg0<6>_MC.REG  (
    .I(\U1/U3/holdingreg0<6>_MC.D ),
    .CE(Vcc),
    .CLK(\U1/U3/holdingreg0<6>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\U1/U3/holdingreg0<6>_MC.Q )
  );
  X_INV \U1/U3/holdingreg0<6>_MC.REG_tsimcreated_inv_Mclk_II/FCLK_1953  (
    .I(\Mclk_II/FCLK ),
    .O(\U1/U3/holdingreg0<6>_MC.REG_tsimcreated_inv_Mclk_II/FCLK )
  );
  X_XOR2 \U1/U3/holdingreg0<6>_MC.D_1954  (
    .I0(\U1/U3/holdingreg0<6>_MC.D1 ),
    .I1(\U1/U3/holdingreg0<6>_MC.D2 ),
    .O(\U1/U3/holdingreg0<6>_MC.D )
  );
  X_ZERO \U1/U3/holdingreg0<6>_MC.D1_1955  (
    .O(\U1/U3/holdingreg0<6>_MC.D1 )
  );
  X_AND2 \U1/U3/holdingreg0<6>_MC.D2_PT_0_1956  (
    .I0(N_PZ_941),
    .I1(\U1/U3/holdingreg0 [6]),
    .O(\U1/U3/holdingreg0<6>_MC.D2_PT_0 )
  );
  X_AND4 \U1/U3/holdingreg0<6>_MC.D2_PT_1_1957  (
    .I0(\MSPReset_II/UIM ),
    .I1(\NlwInverterSignal_U1/U3/holdingreg0<6>_MC.D2_PT_1/IN1 ),
    .I2(U2_ASedge),
    .I3(\U1/Channel0 [6]),
    .O(\U1/U3/holdingreg0<6>_MC.D2_PT_1 )
  );
  X_OR2 \U1/U3/holdingreg0<6>_MC.D2_1958  (
    .I0(\U1/U3/holdingreg0<6>_MC.D2_PT_0 ),
    .I1(\U1/U3/holdingreg0<6>_MC.D2_PT_1 ),
    .O(\U1/U3/holdingreg0<6>_MC.D2 )
  );
  X_BUF \U1/U3/holdingreg1<6>  (
    .I(\U1/U3/holdingreg1<6>_MC.Q ),
    .O(\U1/U3/holdingreg1 [6])
  );
  X_FF \U1/U3/holdingreg1<6>_MC.REG  (
    .I(\U1/U3/holdingreg1<6>_MC.D ),
    .CE(Vcc),
    .CLK(\U1/U3/holdingreg1<6>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\U1/U3/holdingreg1<6>_MC.Q )
  );
  X_INV \U1/U3/holdingreg1<6>_MC.REG_tsimcreated_inv_Mclk_II/FCLK_1959  (
    .I(\Mclk_II/FCLK ),
    .O(\U1/U3/holdingreg1<6>_MC.REG_tsimcreated_inv_Mclk_II/FCLK )
  );
  X_XOR2 \U1/U3/holdingreg1<6>_MC.D_1960  (
    .I0(\U1/U3/holdingreg1<6>_MC.D1 ),
    .I1(\U1/U3/holdingreg1<6>_MC.D2 ),
    .O(\U1/U3/holdingreg1<6>_MC.D )
  );
  X_ZERO \U1/U3/holdingreg1<6>_MC.D1_1961  (
    .O(\U1/U3/holdingreg1<6>_MC.D1 )
  );
  X_AND2 \U1/U3/holdingreg1<6>_MC.D2_PT_0_1962  (
    .I0(N_PZ_941),
    .I1(\U1/U3/holdingreg1 [6]),
    .O(\U1/U3/holdingreg1<6>_MC.D2_PT_0 )
  );
  X_AND4 \U1/U3/holdingreg1<6>_MC.D2_PT_1_1963  (
    .I0(\MSPReset_II/UIM ),
    .I1(\NlwInverterSignal_U1/U3/holdingreg1<6>_MC.D2_PT_1/IN1 ),
    .I2(U2_ASedge),
    .I3(\U1/Channel1 [6]),
    .O(\U1/U3/holdingreg1<6>_MC.D2_PT_1 )
  );
  X_OR2 \U1/U3/holdingreg1<6>_MC.D2_1964  (
    .I0(\U1/U3/holdingreg1<6>_MC.D2_PT_0 ),
    .I1(\U1/U3/holdingreg1<6>_MC.D2_PT_1 ),
    .O(\U1/U3/holdingreg1<6>_MC.D2 )
  );
  X_BUF \U1/U3/holdingreg0<14>  (
    .I(\U1/U3/holdingreg0<14>_MC.Q ),
    .O(\U1/U3/holdingreg0 [14])
  );
  X_FF \U1/U3/holdingreg0<14>_MC.REG  (
    .I(\U1/U3/holdingreg0<14>_MC.D ),
    .CE(Vcc),
    .CLK(\U1/U3/holdingreg0<14>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\U1/U3/holdingreg0<14>_MC.Q )
  );
  X_INV \U1/U3/holdingreg0<14>_MC.REG_tsimcreated_inv_Mclk_II/FCLK_1965  (
    .I(\Mclk_II/FCLK ),
    .O(\U1/U3/holdingreg0<14>_MC.REG_tsimcreated_inv_Mclk_II/FCLK )
  );
  X_XOR2 \U1/U3/holdingreg0<14>_MC.D_1966  (
    .I0(\U1/U3/holdingreg0<14>_MC.D1 ),
    .I1(\U1/U3/holdingreg0<14>_MC.D2 ),
    .O(\U1/U3/holdingreg0<14>_MC.D )
  );
  X_ZERO \U1/U3/holdingreg0<14>_MC.D1_1967  (
    .O(\U1/U3/holdingreg0<14>_MC.D1 )
  );
  X_AND2 \U1/U3/holdingreg0<14>_MC.D2_PT_0_1968  (
    .I0(N_PZ_941),
    .I1(\U1/U3/holdingreg0 [14]),
    .O(\U1/U3/holdingreg0<14>_MC.D2_PT_0 )
  );
  X_AND4 \U1/U3/holdingreg0<14>_MC.D2_PT_1_1969  (
    .I0(\MSPReset_II/UIM ),
    .I1(\NlwInverterSignal_U1/U3/holdingreg0<14>_MC.D2_PT_1/IN1 ),
    .I2(U2_ASedge),
    .I3(\U1/Channel0 [14]),
    .O(\U1/U3/holdingreg0<14>_MC.D2_PT_1 )
  );
  X_OR2 \U1/U3/holdingreg0<14>_MC.D2_1970  (
    .I0(\U1/U3/holdingreg0<14>_MC.D2_PT_0 ),
    .I1(\U1/U3/holdingreg0<14>_MC.D2_PT_1 ),
    .O(\U1/U3/holdingreg0<14>_MC.D2 )
  );
  X_BUF \U1/Channel0<14>  (
    .I(\U1/Channel0<14>_MC.Q ),
    .O(\U1/Channel0 [14])
  );
  X_XOR2 \U1/Channel0<14>_MC_tsimcreated_xor__1971  (
    .I0(\U1/Channel0<14>_MC.D ),
    .I1(\U1/Channel0<14>_MC.Q ),
    .O(\U1/Channel0<14>_MC_tsimcreated_xor_ )
  );
  X_FF \U1/Channel0<14>_MC.REG  (
    .I(\U1/Channel0<14>_MC_tsimcreated_xor_ ),
    .CE(Vcc),
    .CLK(\Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\U1/Channel0<14>_MC.Q )
  );
  X_XOR2 \U1/Channel0<14>_MC.D_1972  (
    .I0(\U1/Channel0<14>_MC.D1 ),
    .I1(\U1/Channel0<14>_MC.D2 ),
    .O(\U1/Channel0<14>_MC.D )
  );
  X_ZERO \U1/Channel0<14>_MC.D1_1973  (
    .O(\U1/Channel0<14>_MC.D1 )
  );
  X_AND2 \U1/Channel0<14>_MC.D2_PT_0_1974  (
    .I0(\NlwInverterSignal_U1/Channel0<14>_MC.D2_PT_0/IN0 ),
    .I1(\U1/Channel0 [14]),
    .O(\U1/Channel0<14>_MC.D2_PT_0 )
  );
  X_AND7 \U1/Channel0<14>_MC.D2_PT_1_1975  (
    .I0(\U1/U2/location_Maddsub__n0000__n0075 [0]),
    .I1(N_PZ_966),
    .I2(\NlwInverterSignal_U1/Channel0<14>_MC.D2_PT_1/IN2 ),
    .I3(\NlwInverterSignal_U1/Channel0<14>_MC.D2_PT_1/IN3 ),
    .I4(\NlwInverterSignal_U1/Channel0<14>_MC.D2_PT_1/IN4 ),
    .I5(\NlwInverterSignal_U1/Channel0<14>_MC.D2_PT_1/IN5 ),
    .I6(\NlwInverterSignal_U1/Channel0<14>_MC.D2_PT_1/IN6 ),
    .O(\U1/Channel0<14>_MC.D2_PT_1 )
  );
  X_AND7 \U1/Channel0<14>_MC.D2_PT_2_1976  (
    .I0(\NlwInverterSignal_U1/Channel0<14>_MC.D2_PT_2/IN0 ),
    .I1(N_PZ_969),
    .I2(\U1/Channel0 [9]),
    .I3(\U1/Channel0 [10]),
    .I4(\U1/Channel0 [11]),
    .I5(\U1/Channel0 [12]),
    .I6(\U1/Channel0 [13]),
    .O(\U1/Channel0<14>_MC.D2_PT_2 )
  );
  X_OR3 \U1/Channel0<14>_MC.D2_1977  (
    .I0(\U1/Channel0<14>_MC.D2_PT_0 ),
    .I1(\U1/Channel0<14>_MC.D2_PT_1 ),
    .I2(\U1/Channel0<14>_MC.D2_PT_2 ),
    .O(\U1/Channel0<14>_MC.D2 )
  );
  X_BUF \U1/U3/holdingreg1<14>  (
    .I(\U1/U3/holdingreg1<14>_MC.Q ),
    .O(\U1/U3/holdingreg1 [14])
  );
  X_FF \U1/U3/holdingreg1<14>_MC.REG  (
    .I(\U1/U3/holdingreg1<14>_MC.D ),
    .CE(Vcc),
    .CLK(\U1/U3/holdingreg1<14>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\U1/U3/holdingreg1<14>_MC.Q )
  );
  X_INV \U1/U3/holdingreg1<14>_MC.REG_tsimcreated_inv_Mclk_II/FCLK_1978  (
    .I(\Mclk_II/FCLK ),
    .O(\U1/U3/holdingreg1<14>_MC.REG_tsimcreated_inv_Mclk_II/FCLK )
  );
  X_XOR2 \U1/U3/holdingreg1<14>_MC.D_1979  (
    .I0(\U1/U3/holdingreg1<14>_MC.D1 ),
    .I1(\U1/U3/holdingreg1<14>_MC.D2 ),
    .O(\U1/U3/holdingreg1<14>_MC.D )
  );
  X_ZERO \U1/U3/holdingreg1<14>_MC.D1_1980  (
    .O(\U1/U3/holdingreg1<14>_MC.D1 )
  );
  X_AND2 \U1/U3/holdingreg1<14>_MC.D2_PT_0_1981  (
    .I0(N_PZ_941),
    .I1(\U1/U3/holdingreg1 [14]),
    .O(\U1/U3/holdingreg1<14>_MC.D2_PT_0 )
  );
  X_AND4 \U1/U3/holdingreg1<14>_MC.D2_PT_1_1982  (
    .I0(\MSPReset_II/UIM ),
    .I1(\NlwInverterSignal_U1/U3/holdingreg1<14>_MC.D2_PT_1/IN1 ),
    .I2(U2_ASedge),
    .I3(\U1/Channel1 [14]),
    .O(\U1/U3/holdingreg1<14>_MC.D2_PT_1 )
  );
  X_OR2 \U1/U3/holdingreg1<14>_MC.D2_1983  (
    .I0(\U1/U3/holdingreg1<14>_MC.D2_PT_0 ),
    .I1(\U1/U3/holdingreg1<14>_MC.D2_PT_1 ),
    .O(\U1/U3/holdingreg1<14>_MC.D2 )
  );
  X_BUF \U1/Channel1<14>  (
    .I(\U1/Channel1<14>_MC.Q ),
    .O(\U1/Channel1 [14])
  );
  X_XOR2 \U1/Channel1<14>_MC_tsimcreated_xor__1984  (
    .I0(\U1/Channel1<14>_MC.D ),
    .I1(\U1/Channel1<14>_MC.Q ),
    .O(\U1/Channel1<14>_MC_tsimcreated_xor_ )
  );
  X_FF \U1/Channel1<14>_MC.REG  (
    .I(\U1/Channel1<14>_MC_tsimcreated_xor_ ),
    .CE(Vcc),
    .CLK(\Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\U1/Channel1<14>_MC.Q )
  );
  X_XOR2 \U1/Channel1<14>_MC.D_1985  (
    .I0(\U1/Channel1<14>_MC.D1 ),
    .I1(\U1/Channel1<14>_MC.D2 ),
    .O(\U1/Channel1<14>_MC.D )
  );
  X_ZERO \U1/Channel1<14>_MC.D1_1986  (
    .O(\U1/Channel1<14>_MC.D1 )
  );
  X_AND2 \U1/Channel1<14>_MC.D2_PT_0_1987  (
    .I0(\NlwInverterSignal_U1/Channel1<14>_MC.D2_PT_0/IN0 ),
    .I1(\U1/Channel1 [14]),
    .O(\U1/Channel1<14>_MC.D2_PT_0 )
  );
  X_AND16 \U1/Channel1<14>_MC.D2_PT_1_1988  (
    .I0(\MSPReset_II/UIM ),
    .I1(\NlwInverterSignal_U1/Channel1<14>_MC.D2_PT_1/IN1 ),
    .I2(N_PZ_1016),
    .I3(\NlwInverterSignal_U1/Channel1<14>_MC.D2_PT_1/IN3 ),
    .I4(\U1/Channel1 [9]),
    .I5(\U1/Channel1 [10]),
    .I6(\U1/Channel1 [11]),
    .I7(\U1/Channel1 [12]),
    .I8(\U1/Channel1 [13]),
    .I9(Vcc),
    .I10(Vcc),
    .I11(Vcc),
    .I12(Vcc),
    .I13(Vcc),
    .I14(Vcc),
    .I15(Vcc),
    .O(\U1/Channel1<14>_MC.D2_PT_1 )
  );
  X_AND16 \U1/Channel1<14>_MC.D2_PT_2_1989  (
    .I0(\MSPReset_II/UIM ),
    .I1(\NlwInverterSignal_U1/Channel1<14>_MC.D2_PT_2/IN1 ),
    .I2(N_PZ_1155),
    .I3(\NlwInverterSignal_U1/Channel1<14>_MC.D2_PT_2/IN3 ),
    .I4(\U1/U5/location_Maddsub__n0000__n0075 [0]),
    .I5(\NlwInverterSignal_U1/Channel1<14>_MC.D2_PT_2/IN5 ),
    .I6(\NlwInverterSignal_U1/Channel1<14>_MC.D2_PT_2/IN6 ),
    .I7(\NlwInverterSignal_U1/Channel1<14>_MC.D2_PT_2/IN7 ),
    .I8(\NlwInverterSignal_U1/Channel1<14>_MC.D2_PT_2/IN8 ),
    .I9(\NlwInverterSignal_U1/Channel1<14>_MC.D2_PT_2/IN9 ),
    .I10(Vcc),
    .I11(Vcc),
    .I12(Vcc),
    .I13(Vcc),
    .I14(Vcc),
    .I15(Vcc),
    .O(\U1/Channel1<14>_MC.D2_PT_2 )
  );
  X_OR3 \U1/Channel1<14>_MC.D2_1990  (
    .I0(\U1/Channel1<14>_MC.D2_PT_0 ),
    .I1(\U1/Channel1<14>_MC.D2_PT_1 ),
    .I2(\U1/Channel1<14>_MC.D2_PT_2 ),
    .O(\U1/Channel1<14>_MC.D2 )
  );
  X_BUF \outDATA<6>\$WA6.UIM_1991  (
    .I(\outDATA<6>\$WA6.UIM_MC.Q ),
    .O(\outDATA<6>\$WA6.UIM )
  );
  X_BUF \outDATA<6>\$WA6.UIM_MC.Q_1992  (
    .I(\outDATA<6>\$WA6.UIM_MC.D ),
    .O(\outDATA<6>\$WA6.UIM_MC.Q )
  );
  X_XOR2 \outDATA<6>\$WA6.UIM_MC.D_1993  (
    .I0(\outDATA<6>\$WA6.UIM_MC.D1 ),
    .I1(\outDATA<6>\$WA6.UIM_MC.D2 ),
    .O(\outDATA<6>\$WA6.UIM_MC.D )
  );
  X_ZERO \outDATA<6>\$WA6.UIM_MC.D1_1994  (
    .O(\outDATA<6>\$WA6.UIM_MC.D1 )
  );
  X_AND2 \outDATA<6>\$WA6.UIM_MC.D2_PT_0_1995  (
    .I0(DCOR0THRESLOWr),
    .I1(\U1/U4/Latch0r [6]),
    .O(\outDATA<6>\$WA6.UIM_MC.D2_PT_0 )
  );
  X_AND3 \outDATA<6>\$WA6.UIM_MC.D2_PT_1_1996  (
    .I0(DCORIFGr),
    .I1(\NlwInverterSignal_outDATA<6>\$WA6.UIM_MC.D2_PT_1/IN1 ),
    .I2(NET2512),
    .O(\outDATA<6>\$WA6.UIM_MC.D2_PT_1 )
  );
  X_AND4 \outDATA<6>\$WA6.UIM_MC.D2_PT_2_1997  (
    .I0(\NlwInverterSignal_outDATA<6>\$WA6.UIM_MC.D2_PT_2/IN0 ),
    .I1(\NlwInverterSignal_outDATA<6>\$WA6.UIM_MC.D2_PT_2/IN1 ),
    .I2(DCOR0THRESHIGHr),
    .I3(\U1/U4/Latch0r [14]),
    .O(\outDATA<6>\$WA6.UIM_MC.D2_PT_2 )
  );
  X_AND5 \outDATA<6>\$WA6.UIM_MC.D2_PT_3_1998  (
    .I0(\NlwInverterSignal_outDATA<6>\$WA6.UIM_MC.D2_PT_3/IN0 ),
    .I1(\NlwInverterSignal_outDATA<6>\$WA6.UIM_MC.D2_PT_3/IN1 ),
    .I2(\NlwInverterSignal_outDATA<6>\$WA6.UIM_MC.D2_PT_3/IN2 ),
    .I3(DCOR1THRESLOWr),
    .I4(\U1/U4/Latch1r [6]),
    .O(\outDATA<6>\$WA6.UIM_MC.D2_PT_3 )
  );
  X_AND5 \outDATA<6>\$WA6.UIM_MC.D2_PT_4_1999  (
    .I0(\NlwInverterSignal_outDATA<6>\$WA6.UIM_MC.D2_PT_4/IN0 ),
    .I1(\NlwInverterSignal_outDATA<6>\$WA6.UIM_MC.D2_PT_4/IN1 ),
    .I2(\NlwInverterSignal_outDATA<6>\$WA6.UIM_MC.D2_PT_4/IN2 ),
    .I3(\NlwInverterSignal_outDATA<6>\$WA6.UIM_MC.D2_PT_4/IN3 ),
    .I4(\U1/U4/Latch1r [14]),
    .O(\outDATA<6>\$WA6.UIM_MC.D2_PT_4 )
  );
  X_OR5 \outDATA<6>\$WA6.UIM_MC.D2_2000  (
    .I0(\outDATA<6>\$WA6.UIM_MC.D2_PT_0 ),
    .I1(\outDATA<6>\$WA6.UIM_MC.D2_PT_1 ),
    .I2(\outDATA<6>\$WA6.UIM_MC.D2_PT_2 ),
    .I3(\outDATA<6>\$WA6.UIM_MC.D2_PT_3 ),
    .I4(\outDATA<6>\$WA6.UIM_MC.D2_PT_4 ),
    .O(\outDATA<6>\$WA6.UIM_MC.D2 )
  );
  X_BUF \U1/U4/Latch0r<6>  (
    .I(\U1/U4/Latch0r<6>_MC.Q ),
    .O(\U1/U4/Latch0r [6])
  );
  X_FF \U1/U4/Latch0r<6>_MC.REG  (
    .I(\U1/U4/Latch0r<6>_MC.D ),
    .CE(Vcc),
    .CLK(\U1/U4/Latch0r<6>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\U1/U4/Latch0r<6>_MC.Q )
  );
  X_INV \U1/U4/Latch0r<6>_MC.REG_tsimcreated_inv_Mclk_II/FCLK_2001  (
    .I(\Mclk_II/FCLK ),
    .O(\U1/U4/Latch0r<6>_MC.REG_tsimcreated_inv_Mclk_II/FCLK )
  );
  X_XOR2 \U1/U4/Latch0r<6>_MC.D_2002  (
    .I0(\U1/U4/Latch0r<6>_MC.D1 ),
    .I1(\U1/U4/Latch0r<6>_MC.D2 ),
    .O(\U1/U4/Latch0r<6>_MC.D )
  );
  X_ZERO \U1/U4/Latch0r<6>_MC.D1_2003  (
    .O(\U1/U4/Latch0r<6>_MC.D1 )
  );
  X_AND3 \U1/U4/Latch0r<6>_MC.D2_PT_0_2004  (
    .I0(\MSPReset_II/UIM ),
    .I1(N_PZ_965),
    .I2(\U1/Channel0 [6]),
    .O(\U1/U4/Latch0r<6>_MC.D2_PT_0 )
  );
  X_AND3 \U1/U4/Latch0r<6>_MC.D2_PT_1_2005  (
    .I0(\MSPReset_II/UIM ),
    .I1(\NlwInverterSignal_U1/U4/Latch0r<6>_MC.D2_PT_1/IN1 ),
    .I2(\U1/U4/Latch0r [6]),
    .O(\U1/U4/Latch0r<6>_MC.D2_PT_1 )
  );
  X_OR2 \U1/U4/Latch0r<6>_MC.D2_2006  (
    .I0(\U1/U4/Latch0r<6>_MC.D2_PT_0 ),
    .I1(\U1/U4/Latch0r<6>_MC.D2_PT_1 ),
    .O(\U1/U4/Latch0r<6>_MC.D2 )
  );
  X_BUF \U1/U4/Latch0r<14>  (
    .I(\U1/U4/Latch0r<14>_MC.Q ),
    .O(\U1/U4/Latch0r [14])
  );
  X_FF \U1/U4/Latch0r<14>_MC.REG  (
    .I(\U1/U4/Latch0r<14>_MC.D ),
    .CE(Vcc),
    .CLK(\U1/U4/Latch0r<14>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\U1/U4/Latch0r<14>_MC.Q )
  );
  X_INV \U1/U4/Latch0r<14>_MC.REG_tsimcreated_inv_Mclk_II/FCLK_2007  (
    .I(\Mclk_II/FCLK ),
    .O(\U1/U4/Latch0r<14>_MC.REG_tsimcreated_inv_Mclk_II/FCLK )
  );
  X_XOR2 \U1/U4/Latch0r<14>_MC.D_2008  (
    .I0(\U1/U4/Latch0r<14>_MC.D1 ),
    .I1(\U1/U4/Latch0r<14>_MC.D2 ),
    .O(\U1/U4/Latch0r<14>_MC.D )
  );
  X_ZERO \U1/U4/Latch0r<14>_MC.D1_2009  (
    .O(\U1/U4/Latch0r<14>_MC.D1 )
  );
  X_AND3 \U1/U4/Latch0r<14>_MC.D2_PT_0_2010  (
    .I0(\MSPReset_II/UIM ),
    .I1(N_PZ_965),
    .I2(\U1/Channel0 [14]),
    .O(\U1/U4/Latch0r<14>_MC.D2_PT_0 )
  );
  X_AND3 \U1/U4/Latch0r<14>_MC.D2_PT_1_2011  (
    .I0(\MSPReset_II/UIM ),
    .I1(\NlwInverterSignal_U1/U4/Latch0r<14>_MC.D2_PT_1/IN1 ),
    .I2(\U1/U4/Latch0r [14]),
    .O(\U1/U4/Latch0r<14>_MC.D2_PT_1 )
  );
  X_OR2 \U1/U4/Latch0r<14>_MC.D2_2012  (
    .I0(\U1/U4/Latch0r<14>_MC.D2_PT_0 ),
    .I1(\U1/U4/Latch0r<14>_MC.D2_PT_1 ),
    .O(\U1/U4/Latch0r<14>_MC.D2 )
  );
  X_BUF \U1/U4/Latch1r<6>  (
    .I(\U1/U4/Latch1r<6>_MC.Q ),
    .O(\U1/U4/Latch1r [6])
  );
  X_FF \U1/U4/Latch1r<6>_MC.REG  (
    .I(\U1/U4/Latch1r<6>_MC.D ),
    .CE(Vcc),
    .CLK(\U1/U4/Latch1r<6>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\U1/U4/Latch1r<6>_MC.Q )
  );
  X_INV \U1/U4/Latch1r<6>_MC.REG_tsimcreated_inv_Mclk_II/FCLK_2013  (
    .I(\Mclk_II/FCLK ),
    .O(\U1/U4/Latch1r<6>_MC.REG_tsimcreated_inv_Mclk_II/FCLK )
  );
  X_XOR2 \U1/U4/Latch1r<6>_MC.D_2014  (
    .I0(\U1/U4/Latch1r<6>_MC.D1 ),
    .I1(\U1/U4/Latch1r<6>_MC.D2 ),
    .O(\U1/U4/Latch1r<6>_MC.D )
  );
  X_ZERO \U1/U4/Latch1r<6>_MC.D1_2015  (
    .O(\U1/U4/Latch1r<6>_MC.D1 )
  );
  X_AND2 \U1/U4/Latch1r<6>_MC.D2_PT_0_2016  (
    .I0(N_PZ_964),
    .I1(\U1/U4/Latch1r [6]),
    .O(\U1/U4/Latch1r<6>_MC.D2_PT_0 )
  );
  X_AND4 \U1/U4/Latch1r<6>_MC.D2_PT_1_2017  (
    .I0(\MSPReset_II/UIM ),
    .I1(\NlwInverterSignal_U1/U4/Latch1r<6>_MC.D2_PT_1/IN1 ),
    .I2(\NlwInverterSignal_U1/U4/Latch1r<6>_MC.D2_PT_1/IN2 ),
    .I3(\U1/Channel1 [6]),
    .O(\U1/U4/Latch1r<6>_MC.D2_PT_1 )
  );
  X_OR2 \U1/U4/Latch1r<6>_MC.D2_2018  (
    .I0(\U1/U4/Latch1r<6>_MC.D2_PT_0 ),
    .I1(\U1/U4/Latch1r<6>_MC.D2_PT_1 ),
    .O(\U1/U4/Latch1r<6>_MC.D2 )
  );
  X_BUF \U1/U4/Latch1r<14>  (
    .I(\U1/U4/Latch1r<14>_MC.Q ),
    .O(\U1/U4/Latch1r [14])
  );
  X_FF \U1/U4/Latch1r<14>_MC.REG  (
    .I(\U1/U4/Latch1r<14>_MC.D ),
    .CE(Vcc),
    .CLK(\U1/U4/Latch1r<14>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\U1/U4/Latch1r<14>_MC.Q )
  );
  X_INV \U1/U4/Latch1r<14>_MC.REG_tsimcreated_inv_Mclk_II/FCLK_2019  (
    .I(\Mclk_II/FCLK ),
    .O(\U1/U4/Latch1r<14>_MC.REG_tsimcreated_inv_Mclk_II/FCLK )
  );
  X_XOR2 \U1/U4/Latch1r<14>_MC.D_2020  (
    .I0(\U1/U4/Latch1r<14>_MC.D1 ),
    .I1(\U1/U4/Latch1r<14>_MC.D2 ),
    .O(\U1/U4/Latch1r<14>_MC.D )
  );
  X_ZERO \U1/U4/Latch1r<14>_MC.D1_2021  (
    .O(\U1/U4/Latch1r<14>_MC.D1 )
  );
  X_AND2 \U1/U4/Latch1r<14>_MC.D2_PT_0_2022  (
    .I0(N_PZ_964),
    .I1(\U1/U4/Latch1r [14]),
    .O(\U1/U4/Latch1r<14>_MC.D2_PT_0 )
  );
  X_AND4 \U1/U4/Latch1r<14>_MC.D2_PT_1_2023  (
    .I0(\MSPReset_II/UIM ),
    .I1(\NlwInverterSignal_U1/U4/Latch1r<14>_MC.D2_PT_1/IN1 ),
    .I2(\NlwInverterSignal_U1/U4/Latch1r<14>_MC.D2_PT_1/IN2 ),
    .I3(\U1/Channel1 [14]),
    .O(\U1/U4/Latch1r<14>_MC.D2_PT_1 )
  );
  X_OR2 \U1/U4/Latch1r<14>_MC.D2_2024  (
    .I0(\U1/U4/Latch1r<14>_MC.D2_PT_0 ),
    .I1(\U1/U4/Latch1r<14>_MC.D2_PT_1 ),
    .O(\U1/U4/Latch1r<14>_MC.D2 )
  );
  X_BUF \outDATA<7>\$WA0.UIM_2025  (
    .I(\outDATA<7>\$WA0.UIM_MC.Q ),
    .O(\outDATA<7>\$WA0.UIM )
  );
  X_BUF \outDATA<7>\$WA0.UIM_MC.Q_2026  (
    .I(\outDATA<7>\$WA0.UIM_MC.D ),
    .O(\outDATA<7>\$WA0.UIM_MC.Q )
  );
  X_XOR2 \outDATA<7>\$WA0.UIM_MC.D_2027  (
    .I0(\outDATA<7>\$WA0.UIM_MC.D1 ),
    .I1(\outDATA<7>\$WA0.UIM_MC.D2 ),
    .O(\outDATA<7>\$WA0.UIM_MC.D )
  );
  X_ZERO \outDATA<7>\$WA0.UIM_MC.D1_2028  (
    .O(\outDATA<7>\$WA0.UIM_MC.D1 )
  );
  X_ZERO \outDATA<7>\$WA0.UIM_MC.D2_2029  (
    .O(\outDATA<7>\$WA0.UIM_MC.D2 )
  );
  X_BUF \outDATA<7>\$WA1.UIM_2030  (
    .I(\outDATA<7>\$WA1.UIM_MC.Q ),
    .O(\outDATA<7>\$WA1.UIM )
  );
  X_BUF \outDATA<7>\$WA1.UIM_MC.Q_2031  (
    .I(\outDATA<7>\$WA1.UIM_MC.D ),
    .O(\outDATA<7>\$WA1.UIM_MC.Q )
  );
  X_XOR2 \outDATA<7>\$WA1.UIM_MC.D_2032  (
    .I0(\outDATA<7>\$WA1.UIM_MC.D1 ),
    .I1(\outDATA<7>\$WA1.UIM_MC.D2 ),
    .O(\outDATA<7>\$WA1.UIM_MC.D )
  );
  X_AND2 \outDATA<7>\$WA1.UIM_MC.D1_2033  (
    .I0(\GP_Motor1_0_II/UIM ),
    .I1(\GP_Motor1_0_II/UIM ),
    .O(\outDATA<7>\$WA1.UIM_MC.D1 )
  );
  X_ZERO \outDATA<7>\$WA1.UIM_MC.D2_2034  (
    .O(\outDATA<7>\$WA1.UIM_MC.D2 )
  );
  X_BUF \outDATA<7>\$WA2.UIM_2035  (
    .I(\outDATA<7>\$WA2.UIM_MC.Q ),
    .O(\outDATA<7>\$WA2.UIM )
  );
  X_BUF \outDATA<7>\$WA2.UIM_MC.Q_2036  (
    .I(\outDATA<7>\$WA2.UIM_MC.D ),
    .O(\outDATA<7>\$WA2.UIM_MC.Q )
  );
  X_XOR2 \outDATA<7>\$WA2.UIM_MC.D_2037  (
    .I0(\outDATA<7>\$WA2.UIM_MC.D1 ),
    .I1(\outDATA<7>\$WA2.UIM_MC.D2 ),
    .O(\outDATA<7>\$WA2.UIM_MC.D )
  );
  X_AND2 \outDATA<7>\$WA2.UIM_MC.D1_2038  (
    .I0(NET3253),
    .I1(NET3253),
    .O(\outDATA<7>\$WA2.UIM_MC.D1 )
  );
  X_ZERO \outDATA<7>\$WA2.UIM_MC.D2_2039  (
    .O(\outDATA<7>\$WA2.UIM_MC.D2 )
  );
  X_BUF \outDATA<7>\$WA3.UIM_2040  (
    .I(\outDATA<7>\$WA3.UIM_MC.Q ),
    .O(\outDATA<7>\$WA3.UIM )
  );
  X_BUF \outDATA<7>\$WA3.UIM_MC.Q_2041  (
    .I(\outDATA<7>\$WA3.UIM_MC.D ),
    .O(\outDATA<7>\$WA3.UIM_MC.Q )
  );
  X_XOR2 \outDATA<7>\$WA3.UIM_MC.D_2042  (
    .I0(\outDATA<7>\$WA3.UIM_MC.D1 ),
    .I1(\outDATA<7>\$WA3.UIM_MC.D2 ),
    .O(\outDATA<7>\$WA3.UIM_MC.D )
  );
  X_ZERO \outDATA<7>\$WA3.UIM_MC.D1_2043  (
    .O(\outDATA<7>\$WA3.UIM_MC.D1 )
  );
  X_AND2 \outDATA<7>\$WA3.UIM_MC.D2_PT_0_2044  (
    .I0(NET2528),
    .I1(\U4/Flgreg [7]),
    .O(\outDATA<7>\$WA3.UIM_MC.D2_PT_0 )
  );
  X_AND2 \outDATA<7>\$WA3.UIM_MC.D2_PT_1_2045  (
    .I0(\NlwInverterSignal_outDATA<7>\$WA3.UIM_MC.D2_PT_1/IN0 ),
    .I1(\Enc15FLG_II/UIM ),
    .O(\outDATA<7>\$WA3.UIM_MC.D2_PT_1 )
  );
  X_OR2 \outDATA<7>\$WA3.UIM_MC.D2_2046  (
    .I0(\outDATA<7>\$WA3.UIM_MC.D2_PT_0 ),
    .I1(\outDATA<7>\$WA3.UIM_MC.D2_PT_1 ),
    .O(\outDATA<7>\$WA3.UIM_MC.D2 )
  );
  X_BUF \outDATA<7>\$WA6.UIM_2047  (
    .I(\outDATA<7>\$WA6.UIM_MC.Q ),
    .O(\outDATA<7>\$WA6.UIM )
  );
  X_BUF \outDATA<7>\$WA6.UIM_MC.Q_2048  (
    .I(\outDATA<7>\$WA6.UIM_MC.D ),
    .O(\outDATA<7>\$WA6.UIM_MC.Q )
  );
  X_XOR2 \outDATA<7>\$WA6.UIM_MC.D_2049  (
    .I0(\outDATA<7>\$WA6.UIM_MC.D1 ),
    .I1(\outDATA<7>\$WA6.UIM_MC.D2 ),
    .O(\outDATA<7>\$WA6.UIM_MC.D )
  );
  X_ZERO \outDATA<7>\$WA6.UIM_MC.D1_2050  (
    .O(\outDATA<7>\$WA6.UIM_MC.D1 )
  );
  X_AND2 \outDATA<7>\$WA6.UIM_MC.D2_PT_0_2051  (
    .I0(DCOR0THRESLOWr),
    .I1(\U1/U4/Latch0r [7]),
    .O(\outDATA<7>\$WA6.UIM_MC.D2_PT_0 )
  );
  X_AND3 \outDATA<7>\$WA6.UIM_MC.D2_PT_1_2052  (
    .I0(\NlwInverterSignal_outDATA<7>\$WA6.UIM_MC.D2_PT_1/IN0 ),
    .I1(DCOR0THRESHIGHr),
    .I2(\U1/U4/Latch0r [15]),
    .O(\outDATA<7>\$WA6.UIM_MC.D2_PT_1 )
  );
  X_AND4 \outDATA<7>\$WA6.UIM_MC.D2_PT_2_2053  (
    .I0(\NlwInverterSignal_outDATA<7>\$WA6.UIM_MC.D2_PT_2/IN0 ),
    .I1(\NlwInverterSignal_outDATA<7>\$WA6.UIM_MC.D2_PT_2/IN1 ),
    .I2(DCOR1THRESLOWr),
    .I3(\U1/U4/Latch1r [7]),
    .O(\outDATA<7>\$WA6.UIM_MC.D2_PT_2 )
  );
  X_AND4 \outDATA<7>\$WA6.UIM_MC.D2_PT_3_2054  (
    .I0(\NlwInverterSignal_outDATA<7>\$WA6.UIM_MC.D2_PT_3/IN0 ),
    .I1(\NlwInverterSignal_outDATA<7>\$WA6.UIM_MC.D2_PT_3/IN1 ),
    .I2(\NlwInverterSignal_outDATA<7>\$WA6.UIM_MC.D2_PT_3/IN2 ),
    .I3(\U1/U4/Latch1r [15]),
    .O(\outDATA<7>\$WA6.UIM_MC.D2_PT_3 )
  );
  X_OR4 \outDATA<7>\$WA6.UIM_MC.D2_2055  (
    .I0(\outDATA<7>\$WA6.UIM_MC.D2_PT_0 ),
    .I1(\outDATA<7>\$WA6.UIM_MC.D2_PT_1 ),
    .I2(\outDATA<7>\$WA6.UIM_MC.D2_PT_2 ),
    .I3(\outDATA<7>\$WA6.UIM_MC.D2_PT_3 ),
    .O(\outDATA<7>\$WA6.UIM_MC.D2 )
  );
  X_BUF \U1/U4/Latch0r<7>  (
    .I(\U1/U4/Latch0r<7>_MC.Q ),
    .O(\U1/U4/Latch0r [7])
  );
  X_FF \U1/U4/Latch0r<7>_MC.REG  (
    .I(\U1/U4/Latch0r<7>_MC.D ),
    .CE(Vcc),
    .CLK(\U1/U4/Latch0r<7>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\U1/U4/Latch0r<7>_MC.Q )
  );
  X_INV \U1/U4/Latch0r<7>_MC.REG_tsimcreated_inv_Mclk_II/FCLK_2056  (
    .I(\Mclk_II/FCLK ),
    .O(\U1/U4/Latch0r<7>_MC.REG_tsimcreated_inv_Mclk_II/FCLK )
  );
  X_XOR2 \U1/U4/Latch0r<7>_MC.D_2057  (
    .I0(\U1/U4/Latch0r<7>_MC.D1 ),
    .I1(\U1/U4/Latch0r<7>_MC.D2 ),
    .O(\U1/U4/Latch0r<7>_MC.D )
  );
  X_ZERO \U1/U4/Latch0r<7>_MC.D1_2058  (
    .O(\U1/U4/Latch0r<7>_MC.D1 )
  );
  X_AND3 \U1/U4/Latch0r<7>_MC.D2_PT_0_2059  (
    .I0(\MSPReset_II/UIM ),
    .I1(N_PZ_965),
    .I2(\U1/Channel0 [7]),
    .O(\U1/U4/Latch0r<7>_MC.D2_PT_0 )
  );
  X_AND3 \U1/U4/Latch0r<7>_MC.D2_PT_1_2060  (
    .I0(\MSPReset_II/UIM ),
    .I1(\NlwInverterSignal_U1/U4/Latch0r<7>_MC.D2_PT_1/IN1 ),
    .I2(\U1/U4/Latch0r [7]),
    .O(\U1/U4/Latch0r<7>_MC.D2_PT_1 )
  );
  X_OR2 \U1/U4/Latch0r<7>_MC.D2_2061  (
    .I0(\U1/U4/Latch0r<7>_MC.D2_PT_0 ),
    .I1(\U1/U4/Latch0r<7>_MC.D2_PT_1 ),
    .O(\U1/U4/Latch0r<7>_MC.D2 )
  );
  X_BUF \U1/U4/Latch0r<15>  (
    .I(\U1/U4/Latch0r<15>_MC.Q ),
    .O(\U1/U4/Latch0r [15])
  );
  X_FF \U1/U4/Latch0r<15>_MC.REG  (
    .I(\U1/U4/Latch0r<15>_MC.D ),
    .CE(Vcc),
    .CLK(\U1/U4/Latch0r<15>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\U1/U4/Latch0r<15>_MC.Q )
  );
  X_INV \U1/U4/Latch0r<15>_MC.REG_tsimcreated_inv_Mclk_II/FCLK_2062  (
    .I(\Mclk_II/FCLK ),
    .O(\U1/U4/Latch0r<15>_MC.REG_tsimcreated_inv_Mclk_II/FCLK )
  );
  X_XOR2 \U1/U4/Latch0r<15>_MC.D_2063  (
    .I0(\U1/U4/Latch0r<15>_MC.D1 ),
    .I1(\U1/U4/Latch0r<15>_MC.D2 ),
    .O(\U1/U4/Latch0r<15>_MC.D )
  );
  X_ZERO \U1/U4/Latch0r<15>_MC.D1_2064  (
    .O(\U1/U4/Latch0r<15>_MC.D1 )
  );
  X_AND3 \U1/U4/Latch0r<15>_MC.D2_PT_0_2065  (
    .I0(\MSPReset_II/UIM ),
    .I1(N_PZ_965),
    .I2(\U1/Channel0 [15]),
    .O(\U1/U4/Latch0r<15>_MC.D2_PT_0 )
  );
  X_AND3 \U1/U4/Latch0r<15>_MC.D2_PT_1_2066  (
    .I0(\MSPReset_II/UIM ),
    .I1(\NlwInverterSignal_U1/U4/Latch0r<15>_MC.D2_PT_1/IN1 ),
    .I2(\U1/U4/Latch0r [15]),
    .O(\U1/U4/Latch0r<15>_MC.D2_PT_1 )
  );
  X_OR2 \U1/U4/Latch0r<15>_MC.D2_2067  (
    .I0(\U1/U4/Latch0r<15>_MC.D2_PT_0 ),
    .I1(\U1/U4/Latch0r<15>_MC.D2_PT_1 ),
    .O(\U1/U4/Latch0r<15>_MC.D2 )
  );
  X_BUF \U1/Channel0<15>  (
    .I(\U1/Channel0<15>_MC.Q ),
    .O(\U1/Channel0 [15])
  );
  X_XOR2 \U1/Channel0<15>_MC_tsimcreated_xor__2068  (
    .I0(\U1/Channel0<15>_MC.D ),
    .I1(\U1/Channel0<15>_MC.Q ),
    .O(\U1/Channel0<15>_MC_tsimcreated_xor_ )
  );
  X_FF \U1/Channel0<15>_MC.REG  (
    .I(\U1/Channel0<15>_MC_tsimcreated_xor_ ),
    .CE(Vcc),
    .CLK(\Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\U1/Channel0<15>_MC.Q )
  );
  X_XOR2 \U1/Channel0<15>_MC.D_2069  (
    .I0(\U1/Channel0<15>_MC.D1 ),
    .I1(\U1/Channel0<15>_MC.D2 ),
    .O(\U1/Channel0<15>_MC.D )
  );
  X_ZERO \U1/Channel0<15>_MC.D1_2070  (
    .O(\U1/Channel0<15>_MC.D1 )
  );
  X_AND2 \U1/Channel0<15>_MC.D2_PT_0_2071  (
    .I0(\NlwInverterSignal_U1/Channel0<15>_MC.D2_PT_0/IN0 ),
    .I1(\U1/Channel0 [15]),
    .O(\U1/Channel0<15>_MC.D2_PT_0 )
  );
  X_AND8 \U1/Channel0<15>_MC.D2_PT_1_2072  (
    .I0(\U1/U2/location_Maddsub__n0000__n0075 [0]),
    .I1(N_PZ_966),
    .I2(\NlwInverterSignal_U1/Channel0<15>_MC.D2_PT_1/IN2 ),
    .I3(\NlwInverterSignal_U1/Channel0<15>_MC.D2_PT_1/IN3 ),
    .I4(\NlwInverterSignal_U1/Channel0<15>_MC.D2_PT_1/IN4 ),
    .I5(\NlwInverterSignal_U1/Channel0<15>_MC.D2_PT_1/IN5 ),
    .I6(\NlwInverterSignal_U1/Channel0<15>_MC.D2_PT_1/IN6 ),
    .I7(\NlwInverterSignal_U1/Channel0<15>_MC.D2_PT_1/IN7 ),
    .O(\U1/Channel0<15>_MC.D2_PT_1 )
  );
  X_AND8 \U1/Channel0<15>_MC.D2_PT_2_2073  (
    .I0(\NlwInverterSignal_U1/Channel0<15>_MC.D2_PT_2/IN0 ),
    .I1(N_PZ_969),
    .I2(\U1/Channel0 [9]),
    .I3(\U1/Channel0 [10]),
    .I4(\U1/Channel0 [11]),
    .I5(\U1/Channel0 [12]),
    .I6(\U1/Channel0 [13]),
    .I7(\U1/Channel0 [14]),
    .O(\U1/Channel0<15>_MC.D2_PT_2 )
  );
  X_OR3 \U1/Channel0<15>_MC.D2_2074  (
    .I0(\U1/Channel0<15>_MC.D2_PT_0 ),
    .I1(\U1/Channel0<15>_MC.D2_PT_1 ),
    .I2(\U1/Channel0<15>_MC.D2_PT_2 ),
    .O(\U1/Channel0<15>_MC.D2 )
  );
  X_BUF \U1/U4/Latch1r<7>  (
    .I(\U1/U4/Latch1r<7>_MC.Q ),
    .O(\U1/U4/Latch1r [7])
  );
  X_FF \U1/U4/Latch1r<7>_MC.REG  (
    .I(\U1/U4/Latch1r<7>_MC.D ),
    .CE(Vcc),
    .CLK(\U1/U4/Latch1r<7>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\U1/U4/Latch1r<7>_MC.Q )
  );
  X_INV \U1/U4/Latch1r<7>_MC.REG_tsimcreated_inv_Mclk_II/FCLK_2075  (
    .I(\Mclk_II/FCLK ),
    .O(\U1/U4/Latch1r<7>_MC.REG_tsimcreated_inv_Mclk_II/FCLK )
  );
  X_XOR2 \U1/U4/Latch1r<7>_MC.D_2076  (
    .I0(\U1/U4/Latch1r<7>_MC.D1 ),
    .I1(\U1/U4/Latch1r<7>_MC.D2 ),
    .O(\U1/U4/Latch1r<7>_MC.D )
  );
  X_ZERO \U1/U4/Latch1r<7>_MC.D1_2077  (
    .O(\U1/U4/Latch1r<7>_MC.D1 )
  );
  X_AND2 \U1/U4/Latch1r<7>_MC.D2_PT_0_2078  (
    .I0(N_PZ_964),
    .I1(\U1/U4/Latch1r [7]),
    .O(\U1/U4/Latch1r<7>_MC.D2_PT_0 )
  );
  X_AND4 \U1/U4/Latch1r<7>_MC.D2_PT_1_2079  (
    .I0(\MSPReset_II/UIM ),
    .I1(\NlwInverterSignal_U1/U4/Latch1r<7>_MC.D2_PT_1/IN1 ),
    .I2(\NlwInverterSignal_U1/U4/Latch1r<7>_MC.D2_PT_1/IN2 ),
    .I3(\U1/Channel1 [7]),
    .O(\U1/U4/Latch1r<7>_MC.D2_PT_1 )
  );
  X_OR2 \U1/U4/Latch1r<7>_MC.D2_2080  (
    .I0(\U1/U4/Latch1r<7>_MC.D2_PT_0 ),
    .I1(\U1/U4/Latch1r<7>_MC.D2_PT_1 ),
    .O(\U1/U4/Latch1r<7>_MC.D2 )
  );
  X_BUF \U1/U4/Latch1r<15>  (
    .I(\U1/U4/Latch1r<15>_MC.Q ),
    .O(\U1/U4/Latch1r [15])
  );
  X_FF \U1/U4/Latch1r<15>_MC.REG  (
    .I(\U1/U4/Latch1r<15>_MC.D ),
    .CE(Vcc),
    .CLK(\U1/U4/Latch1r<15>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\U1/U4/Latch1r<15>_MC.Q )
  );
  X_INV \U1/U4/Latch1r<15>_MC.REG_tsimcreated_inv_Mclk_II/FCLK_2081  (
    .I(\Mclk_II/FCLK ),
    .O(\U1/U4/Latch1r<15>_MC.REG_tsimcreated_inv_Mclk_II/FCLK )
  );
  X_XOR2 \U1/U4/Latch1r<15>_MC.D_2082  (
    .I0(\U1/U4/Latch1r<15>_MC.D1 ),
    .I1(\U1/U4/Latch1r<15>_MC.D2 ),
    .O(\U1/U4/Latch1r<15>_MC.D )
  );
  X_ZERO \U1/U4/Latch1r<15>_MC.D1_2083  (
    .O(\U1/U4/Latch1r<15>_MC.D1 )
  );
  X_AND2 \U1/U4/Latch1r<15>_MC.D2_PT_0_2084  (
    .I0(N_PZ_964),
    .I1(\U1/U4/Latch1r [15]),
    .O(\U1/U4/Latch1r<15>_MC.D2_PT_0 )
  );
  X_AND4 \U1/U4/Latch1r<15>_MC.D2_PT_1_2085  (
    .I0(\MSPReset_II/UIM ),
    .I1(\NlwInverterSignal_U1/U4/Latch1r<15>_MC.D2_PT_1/IN1 ),
    .I2(\NlwInverterSignal_U1/U4/Latch1r<15>_MC.D2_PT_1/IN2 ),
    .I3(\U1/Channel1 [15]),
    .O(\U1/U4/Latch1r<15>_MC.D2_PT_1 )
  );
  X_OR2 \U1/U4/Latch1r<15>_MC.D2_2086  (
    .I0(\U1/U4/Latch1r<15>_MC.D2_PT_0 ),
    .I1(\U1/U4/Latch1r<15>_MC.D2_PT_1 ),
    .O(\U1/U4/Latch1r<15>_MC.D2 )
  );
  X_BUF \U1/Channel1<15>  (
    .I(\U1/Channel1<15>_MC.Q ),
    .O(\U1/Channel1 [15])
  );
  X_XOR2 \U1/Channel1<15>_MC_tsimcreated_xor__2087  (
    .I0(\U1/Channel1<15>_MC.D ),
    .I1(\U1/Channel1<15>_MC.Q ),
    .O(\U1/Channel1<15>_MC_tsimcreated_xor_ )
  );
  X_FF \U1/Channel1<15>_MC.REG  (
    .I(\U1/Channel1<15>_MC_tsimcreated_xor_ ),
    .CE(Vcc),
    .CLK(\Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\U1/Channel1<15>_MC.Q )
  );
  X_XOR2 \U1/Channel1<15>_MC.D_2088  (
    .I0(\U1/Channel1<15>_MC.D1 ),
    .I1(\U1/Channel1<15>_MC.D2 ),
    .O(\U1/Channel1<15>_MC.D )
  );
  X_ZERO \U1/Channel1<15>_MC.D1_2089  (
    .O(\U1/Channel1<15>_MC.D1 )
  );
  X_AND2 \U1/Channel1<15>_MC.D2_PT_0_2090  (
    .I0(\NlwInverterSignal_U1/Channel1<15>_MC.D2_PT_0/IN0 ),
    .I1(\U1/Channel1 [15]),
    .O(\U1/Channel1<15>_MC.D2_PT_0 )
  );
  X_AND16 \U1/Channel1<15>_MC.D2_PT_1_2091  (
    .I0(\MSPReset_II/UIM ),
    .I1(\NlwInverterSignal_U1/Channel1<15>_MC.D2_PT_1/IN1 ),
    .I2(N_PZ_1016),
    .I3(\NlwInverterSignal_U1/Channel1<15>_MC.D2_PT_1/IN3 ),
    .I4(\U1/Channel1 [9]),
    .I5(\U1/Channel1 [10]),
    .I6(\U1/Channel1 [11]),
    .I7(\U1/Channel1 [12]),
    .I8(\U1/Channel1 [13]),
    .I9(\U1/Channel1 [14]),
    .I10(Vcc),
    .I11(Vcc),
    .I12(Vcc),
    .I13(Vcc),
    .I14(Vcc),
    .I15(Vcc),
    .O(\U1/Channel1<15>_MC.D2_PT_1 )
  );
  X_AND16 \U1/Channel1<15>_MC.D2_PT_2_2092  (
    .I0(\MSPReset_II/UIM ),
    .I1(\NlwInverterSignal_U1/Channel1<15>_MC.D2_PT_2/IN1 ),
    .I2(N_PZ_1155),
    .I3(\NlwInverterSignal_U1/Channel1<15>_MC.D2_PT_2/IN3 ),
    .I4(\U1/U5/location_Maddsub__n0000__n0075 [0]),
    .I5(\NlwInverterSignal_U1/Channel1<15>_MC.D2_PT_2/IN5 ),
    .I6(\NlwInverterSignal_U1/Channel1<15>_MC.D2_PT_2/IN6 ),
    .I7(\NlwInverterSignal_U1/Channel1<15>_MC.D2_PT_2/IN7 ),
    .I8(\NlwInverterSignal_U1/Channel1<15>_MC.D2_PT_2/IN8 ),
    .I9(\NlwInverterSignal_U1/Channel1<15>_MC.D2_PT_2/IN9 ),
    .I10(\NlwInverterSignal_U1/Channel1<15>_MC.D2_PT_2/IN10 ),
    .I11(Vcc),
    .I12(Vcc),
    .I13(Vcc),
    .I14(Vcc),
    .I15(Vcc),
    .O(\U1/Channel1<15>_MC.D2_PT_2 )
  );
  X_OR3 \U1/Channel1<15>_MC.D2_2093  (
    .I0(\U1/Channel1<15>_MC.D2_PT_0 ),
    .I1(\U1/Channel1<15>_MC.D2_PT_1 ),
    .I2(\U1/Channel1<15>_MC.D2_PT_2 ),
    .O(\U1/Channel1<15>_MC.D2 )
  );
  X_BUF \outDATA<7>\$WA5.UIM_2094  (
    .I(\outDATA<7>\$WA5.UIM_MC.Q ),
    .O(\outDATA<7>\$WA5.UIM )
  );
  X_BUF \outDATA<7>\$WA5.UIM_MC.Q_2095  (
    .I(\outDATA<7>\$WA5.UIM_MC.D ),
    .O(\outDATA<7>\$WA5.UIM_MC.Q )
  );
  X_XOR2 \outDATA<7>\$WA5.UIM_MC.D_2096  (
    .I0(\outDATA<7>\$WA5.UIM_MC.D1 ),
    .I1(\outDATA<7>\$WA5.UIM_MC.D2 ),
    .O(\outDATA<7>\$WA5.UIM_MC.D )
  );
  X_ZERO \outDATA<7>\$WA5.UIM_MC.D1_2097  (
    .O(\outDATA<7>\$WA5.UIM_MC.D1 )
  );
  X_AND2 \outDATA<7>\$WA5.UIM_MC.D2_PT_0_2098  (
    .I0(DCOR0CNTLOWr),
    .I1(\U1/U3/holdingreg0 [7]),
    .O(\outDATA<7>\$WA5.UIM_MC.D2_PT_0 )
  );
  X_AND3 \outDATA<7>\$WA5.UIM_MC.D2_PT_1_2099  (
    .I0(\NlwInverterSignal_outDATA<7>\$WA5.UIM_MC.D2_PT_1/IN0 ),
    .I1(DCOR1CNTLOWr),
    .I2(\U1/U3/holdingreg1 [7]),
    .O(\outDATA<7>\$WA5.UIM_MC.D2_PT_1 )
  );
  X_AND4 \outDATA<7>\$WA5.UIM_MC.D2_PT_2_2100  (
    .I0(\NlwInverterSignal_outDATA<7>\$WA5.UIM_MC.D2_PT_2/IN0 ),
    .I1(\NlwInverterSignal_outDATA<7>\$WA5.UIM_MC.D2_PT_2/IN1 ),
    .I2(DCOR0CNTHIGHr),
    .I3(\U1/U3/holdingreg0 [15]),
    .O(\outDATA<7>\$WA5.UIM_MC.D2_PT_2 )
  );
  X_AND4 \outDATA<7>\$WA5.UIM_MC.D2_PT_3_2101  (
    .I0(\NlwInverterSignal_outDATA<7>\$WA5.UIM_MC.D2_PT_3/IN0 ),
    .I1(\NlwInverterSignal_outDATA<7>\$WA5.UIM_MC.D2_PT_3/IN1 ),
    .I2(\NlwInverterSignal_outDATA<7>\$WA5.UIM_MC.D2_PT_3/IN2 ),
    .I3(\U1/U3/holdingreg1 [15]),
    .O(\outDATA<7>\$WA5.UIM_MC.D2_PT_3 )
  );
  X_OR4 \outDATA<7>\$WA5.UIM_MC.D2_2102  (
    .I0(\outDATA<7>\$WA5.UIM_MC.D2_PT_0 ),
    .I1(\outDATA<7>\$WA5.UIM_MC.D2_PT_1 ),
    .I2(\outDATA<7>\$WA5.UIM_MC.D2_PT_2 ),
    .I3(\outDATA<7>\$WA5.UIM_MC.D2_PT_3 ),
    .O(\outDATA<7>\$WA5.UIM_MC.D2 )
  );
  X_BUF \U1/U3/holdingreg0<7>  (
    .I(\U1/U3/holdingreg0<7>_MC.Q ),
    .O(\U1/U3/holdingreg0 [7])
  );
  X_FF \U1/U3/holdingreg0<7>_MC.REG  (
    .I(\U1/U3/holdingreg0<7>_MC.D ),
    .CE(Vcc),
    .CLK(\U1/U3/holdingreg0<7>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\U1/U3/holdingreg0<7>_MC.Q )
  );
  X_INV \U1/U3/holdingreg0<7>_MC.REG_tsimcreated_inv_Mclk_II/FCLK_2103  (
    .I(\Mclk_II/FCLK ),
    .O(\U1/U3/holdingreg0<7>_MC.REG_tsimcreated_inv_Mclk_II/FCLK )
  );
  X_XOR2 \U1/U3/holdingreg0<7>_MC.D_2104  (
    .I0(\U1/U3/holdingreg0<7>_MC.D1 ),
    .I1(\U1/U3/holdingreg0<7>_MC.D2 ),
    .O(\U1/U3/holdingreg0<7>_MC.D )
  );
  X_ZERO \U1/U3/holdingreg0<7>_MC.D1_2105  (
    .O(\U1/U3/holdingreg0<7>_MC.D1 )
  );
  X_AND2 \U1/U3/holdingreg0<7>_MC.D2_PT_0_2106  (
    .I0(N_PZ_941),
    .I1(\U1/U3/holdingreg0 [7]),
    .O(\U1/U3/holdingreg0<7>_MC.D2_PT_0 )
  );
  X_AND4 \U1/U3/holdingreg0<7>_MC.D2_PT_1_2107  (
    .I0(\MSPReset_II/UIM ),
    .I1(\NlwInverterSignal_U1/U3/holdingreg0<7>_MC.D2_PT_1/IN1 ),
    .I2(U2_ASedge),
    .I3(\U1/Channel0 [7]),
    .O(\U1/U3/holdingreg0<7>_MC.D2_PT_1 )
  );
  X_OR2 \U1/U3/holdingreg0<7>_MC.D2_2108  (
    .I0(\U1/U3/holdingreg0<7>_MC.D2_PT_0 ),
    .I1(\U1/U3/holdingreg0<7>_MC.D2_PT_1 ),
    .O(\U1/U3/holdingreg0<7>_MC.D2 )
  );
  X_BUF \U1/U3/holdingreg1<7>  (
    .I(\U1/U3/holdingreg1<7>_MC.Q ),
    .O(\U1/U3/holdingreg1 [7])
  );
  X_FF \U1/U3/holdingreg1<7>_MC.REG  (
    .I(\U1/U3/holdingreg1<7>_MC.D ),
    .CE(Vcc),
    .CLK(\U1/U3/holdingreg1<7>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\U1/U3/holdingreg1<7>_MC.Q )
  );
  X_INV \U1/U3/holdingreg1<7>_MC.REG_tsimcreated_inv_Mclk_II/FCLK_2109  (
    .I(\Mclk_II/FCLK ),
    .O(\U1/U3/holdingreg1<7>_MC.REG_tsimcreated_inv_Mclk_II/FCLK )
  );
  X_XOR2 \U1/U3/holdingreg1<7>_MC.D_2110  (
    .I0(\U1/U3/holdingreg1<7>_MC.D1 ),
    .I1(\U1/U3/holdingreg1<7>_MC.D2 ),
    .O(\U1/U3/holdingreg1<7>_MC.D )
  );
  X_ZERO \U1/U3/holdingreg1<7>_MC.D1_2111  (
    .O(\U1/U3/holdingreg1<7>_MC.D1 )
  );
  X_AND2 \U1/U3/holdingreg1<7>_MC.D2_PT_0_2112  (
    .I0(N_PZ_941),
    .I1(\U1/U3/holdingreg1 [7]),
    .O(\U1/U3/holdingreg1<7>_MC.D2_PT_0 )
  );
  X_AND4 \U1/U3/holdingreg1<7>_MC.D2_PT_1_2113  (
    .I0(\MSPReset_II/UIM ),
    .I1(\NlwInverterSignal_U1/U3/holdingreg1<7>_MC.D2_PT_1/IN1 ),
    .I2(U2_ASedge),
    .I3(\U1/Channel1 [7]),
    .O(\U1/U3/holdingreg1<7>_MC.D2_PT_1 )
  );
  X_OR2 \U1/U3/holdingreg1<7>_MC.D2_2114  (
    .I0(\U1/U3/holdingreg1<7>_MC.D2_PT_0 ),
    .I1(\U1/U3/holdingreg1<7>_MC.D2_PT_1 ),
    .O(\U1/U3/holdingreg1<7>_MC.D2 )
  );
  X_BUF \U1/U3/holdingreg0<15>  (
    .I(\U1/U3/holdingreg0<15>_MC.Q ),
    .O(\U1/U3/holdingreg0 [15])
  );
  X_FF \U1/U3/holdingreg0<15>_MC.REG  (
    .I(\U1/U3/holdingreg0<15>_MC.D ),
    .CE(Vcc),
    .CLK(\U1/U3/holdingreg0<15>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\U1/U3/holdingreg0<15>_MC.Q )
  );
  X_INV \U1/U3/holdingreg0<15>_MC.REG_tsimcreated_inv_Mclk_II/FCLK_2115  (
    .I(\Mclk_II/FCLK ),
    .O(\U1/U3/holdingreg0<15>_MC.REG_tsimcreated_inv_Mclk_II/FCLK )
  );
  X_XOR2 \U1/U3/holdingreg0<15>_MC.D_2116  (
    .I0(\U1/U3/holdingreg0<15>_MC.D1 ),
    .I1(\U1/U3/holdingreg0<15>_MC.D2 ),
    .O(\U1/U3/holdingreg0<15>_MC.D )
  );
  X_ZERO \U1/U3/holdingreg0<15>_MC.D1_2117  (
    .O(\U1/U3/holdingreg0<15>_MC.D1 )
  );
  X_AND2 \U1/U3/holdingreg0<15>_MC.D2_PT_0_2118  (
    .I0(N_PZ_941),
    .I1(\U1/U3/holdingreg0 [15]),
    .O(\U1/U3/holdingreg0<15>_MC.D2_PT_0 )
  );
  X_AND4 \U1/U3/holdingreg0<15>_MC.D2_PT_1_2119  (
    .I0(\MSPReset_II/UIM ),
    .I1(\NlwInverterSignal_U1/U3/holdingreg0<15>_MC.D2_PT_1/IN1 ),
    .I2(U2_ASedge),
    .I3(\U1/Channel0 [15]),
    .O(\U1/U3/holdingreg0<15>_MC.D2_PT_1 )
  );
  X_OR2 \U1/U3/holdingreg0<15>_MC.D2_2120  (
    .I0(\U1/U3/holdingreg0<15>_MC.D2_PT_0 ),
    .I1(\U1/U3/holdingreg0<15>_MC.D2_PT_1 ),
    .O(\U1/U3/holdingreg0<15>_MC.D2 )
  );
  X_BUF \U1/U3/holdingreg1<15>  (
    .I(\U1/U3/holdingreg1<15>_MC.Q ),
    .O(\U1/U3/holdingreg1 [15])
  );
  X_FF \U1/U3/holdingreg1<15>_MC.REG  (
    .I(\U1/U3/holdingreg1<15>_MC.D ),
    .CE(Vcc),
    .CLK(\U1/U3/holdingreg1<15>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\U1/U3/holdingreg1<15>_MC.Q )
  );
  X_INV \U1/U3/holdingreg1<15>_MC.REG_tsimcreated_inv_Mclk_II/FCLK_2121  (
    .I(\Mclk_II/FCLK ),
    .O(\U1/U3/holdingreg1<15>_MC.REG_tsimcreated_inv_Mclk_II/FCLK )
  );
  X_XOR2 \U1/U3/holdingreg1<15>_MC.D_2122  (
    .I0(\U1/U3/holdingreg1<15>_MC.D1 ),
    .I1(\U1/U3/holdingreg1<15>_MC.D2 ),
    .O(\U1/U3/holdingreg1<15>_MC.D )
  );
  X_ZERO \U1/U3/holdingreg1<15>_MC.D1_2123  (
    .O(\U1/U3/holdingreg1<15>_MC.D1 )
  );
  X_AND2 \U1/U3/holdingreg1<15>_MC.D2_PT_0_2124  (
    .I0(N_PZ_941),
    .I1(\U1/U3/holdingreg1 [15]),
    .O(\U1/U3/holdingreg1<15>_MC.D2_PT_0 )
  );
  X_AND4 \U1/U3/holdingreg1<15>_MC.D2_PT_1_2125  (
    .I0(\MSPReset_II/UIM ),
    .I1(\NlwInverterSignal_U1/U3/holdingreg1<15>_MC.D2_PT_1/IN1 ),
    .I2(U2_ASedge),
    .I3(\U1/Channel1 [15]),
    .O(\U1/U3/holdingreg1<15>_MC.D2_PT_1 )
  );
  X_OR2 \U1/U3/holdingreg1<15>_MC.D2_2126  (
    .I0(\U1/U3/holdingreg1<15>_MC.D2_PT_0 ),
    .I1(\U1/U3/holdingreg1<15>_MC.D2_PT_1 ),
    .O(\U1/U3/holdingreg1<15>_MC.D2 )
  );
  X_AND2 \FOOBAR1__ctinst/4_2127  (
    .I0(DCOROUTw),
    .I1(DCOROUTw),
    .O(\FOOBAR1__ctinst/4 )
  );
  X_AND2 \FOOBAR1__ctinst/7_2128  (
    .I0(U2_Enable_AD),
    .I1(U2_Enable_AD),
    .O(\FOOBAR1__ctinst/7 )
  );
  X_AND2 \FOOBAR2__ctinst/7_2129  (
    .I0(\MSPReset_II/UIM ),
    .I1(\MSPReset_II/UIM ),
    .O(\NlwInverterSignal_FOOBAR2__ctinst/7/OUT )
  );
  X_AND2 \FOOBAR3__ctinst/7_2130  (
    .I0(\MSPReset_II/UIM ),
    .I1(\MSPReset_II/UIM ),
    .O(\NlwInverterSignal_FOOBAR3__ctinst/7/OUT )
  );
  X_AND2 \FOOBAR4__ctinst/0_2131  (
    .I0(\TP12_MC.UIM ),
    .I1(\TP12_MC.UIM ),
    .O(\FOOBAR4__ctinst/0 )
  );
  X_AND2 \FOOBAR7__ctinst/4_2132  (
    .I0(DCOROUTw),
    .I1(DCOROUTw),
    .O(\FOOBAR7__ctinst/4 )
  );
  X_AND2 \FOOBAR8__ctinst/4_2133  (
    .I0(U2_WRRDedge),
    .I1(\NlwInverterSignal_FOOBAR8__ctinst/4/IN1 ),
    .O(\FOOBAR8__ctinst/4 )
  );
  X_AND2 \FOOBAR9__ctinst/4_2134  (
    .I0(DCORENCPWRw),
    .I1(DCORENCPWRw),
    .O(\FOOBAR9__ctinst/4 )
  );
  X_AND2 \FOOBAR10__ctinst/4_2135  (
    .I0(DCORENCPWRw),
    .I1(DCORENCPWRw),
    .O(\FOOBAR10__ctinst/4 )
  );
  X_AND2 \FOOBAR12__ctinst/4_2136  (
    .I0(DCORENCPWRw),
    .I1(DCORENCPWRw),
    .O(\FOOBAR12__ctinst/4 )
  );
  X_AND2 \FOOBAR15__ctinst/4_2137  (
    .I0(DCOROUTw),
    .I1(DCOROUTw),
    .O(\FOOBAR15__ctinst/4 )
  );
  X_AND2 \FOOBAR18__ctinst/4_2138  (
    .I0(DCOROUTw),
    .I1(DCOROUTw),
    .O(\FOOBAR18__ctinst/4 )
  );
  X_AND2 \FOOBAR19__ctinst/4_2139  (
    .I0(DCORSENSORw),
    .I1(DCORSENSORw),
    .O(\FOOBAR19__ctinst/4 )
  );
  X_AND2 \FOOBAR21__ctinst/4_2140  (
    .I0(\NlwInverterSignal_FOOBAR21__ctinst/4/IN0 ),
    .I1(\NlwInverterSignal_FOOBAR21__ctinst/4/IN1 ),
    .O(\FOOBAR21__ctinst/4 )
  );
  X_AND2 \FOOBAR24__ctinst/4_2141  (
    .I0(\NlwInverterSignal_FOOBAR24__ctinst/4/IN0 ),
    .I1(\NlwInverterSignal_FOOBAR24__ctinst/4/IN1 ),
    .O(\FOOBAR24__ctinst/4 )
  );
  X_INV \NlwInverterBlock_Enc033ctrl_MC.D/IN0  (
    .I(\Enc033ctrl_MC.D1 ),
    .O(\NlwInverterSignal_Enc033ctrl_MC.D/IN0 )
  );
  X_INV \NlwInverterBlock_Enc033ctrl_MC.D1/IN1  (
    .I(\U4/ctrlr [3]),
    .O(\NlwInverterSignal_Enc033ctrl_MC.D1/IN1 )
  );
  X_INV \NlwInverterBlock_U4/ctrlr<2>_MC.D/IN0  (
    .I(\U4/ctrlr<2>_MC.D1 ),
    .O(\NlwInverterSignal_U4/ctrlr<2>_MC.D/IN0 )
  );
  X_INV \NlwInverterBlock_U4/ctrlr<2>_MC.D2_PT_0/IN1  (
    .I(\outDATA<2>\$WA0.UIM ),
    .O(\NlwInverterSignal_U4/ctrlr<2>_MC.D2_PT_0/IN1 )
  );
  X_INV \NlwInverterBlock_U4/ctrlr<2>_MC.D2_PT_1/IN1  (
    .I(\outDATA<2>\$WA1.UIM ),
    .O(\NlwInverterSignal_U4/ctrlr<2>_MC.D2_PT_1/IN1 )
  );
  X_INV \NlwInverterBlock_U4/ctrlr<2>_MC.D2_PT_2/IN1  (
    .I(\outDATA<2>\$WA2.UIM ),
    .O(\NlwInverterSignal_U4/ctrlr<2>_MC.D2_PT_2/IN1 )
  );
  X_INV \NlwInverterBlock_U4/ctrlr<2>_MC.D2_PT_3/IN1  (
    .I(\outDATA<2>\$WA3.UIM ),
    .O(\NlwInverterSignal_U4/ctrlr<2>_MC.D2_PT_3/IN1 )
  );
  X_INV \NlwInverterBlock_U4/ctrlr<2>_MC.D2_PT_4/IN0  (
    .I(N_PZ_963),
    .O(\NlwInverterSignal_U4/ctrlr<2>_MC.D2_PT_4/IN0 )
  );
  X_INV \NlwInverterBlock_U4/ctrlr<2>_MC.D2_PT_4/IN1  (
    .I(\outDATA<2>\$WA5.UIM ),
    .O(\NlwInverterSignal_U4/ctrlr<2>_MC.D2_PT_4/IN1 )
  );
  X_INV \NlwInverterBlock_U4/ctrlr<2>_MC.D2_PT_5/IN0  (
    .I(N_PZ_980),
    .O(\NlwInverterSignal_U4/ctrlr<2>_MC.D2_PT_5/IN0 )
  );
  X_INV \NlwInverterBlock_U4/ctrlr<2>_MC.D2_PT_5/IN1  (
    .I(\outDATA<2>\$WA6.UIM ),
    .O(\NlwInverterSignal_U4/ctrlr<2>_MC.D2_PT_5/IN1 )
  );
  X_INV \NlwInverterBlock_DCORENCPWRw_MC.D1/IN0  (
    .I(\WR_II/UIM ),
    .O(\NlwInverterSignal_DCORENCPWRw_MC.D1/IN0 )
  );
  X_INV \NlwInverterBlock_DCORENCPWRw_MC.D1/IN2  (
    .I(U2_ADDR_reg[0]),
    .O(\NlwInverterSignal_DCORENCPWRw_MC.D1/IN2 )
  );
  X_INV \NlwInverterBlock_DCORENCPWRw_MC.D1/IN3  (
    .I(U2_ADDR_reg[4]),
    .O(\NlwInverterSignal_DCORENCPWRw_MC.D1/IN3 )
  );
  X_INV \NlwInverterBlock_DCORENCPWRw_MC.D1/IN4  (
    .I(U2_ADDR_reg[5]),
    .O(\NlwInverterSignal_DCORENCPWRw_MC.D1/IN4 )
  );
  X_INV \NlwInverterBlock_DCORENCPWRw_MC.D1/IN5  (
    .I(U2_ADDR_reg[6]),
    .O(\NlwInverterSignal_DCORENCPWRw_MC.D1/IN5 )
  );
  X_INV \NlwInverterBlock_DCORENCPWRw_MC.D1/IN6  (
    .I(U2_ADDR_reg[7]),
    .O(\NlwInverterSignal_DCORENCPWRw_MC.D1/IN6 )
  );
  X_INV \NlwInverterBlock_U2_ADDR_reg<0>_MC.D2_PT_0/IN1  (
    .I(\MSPReset_II/UIM ),
    .O(\NlwInverterSignal_U2_ADDR_reg<0>_MC.D2_PT_0/IN1 )
  );
  X_INV \NlwInverterBlock_U2_ADDR_reg<0>_MC.D2_PT_1/IN3  (
    .I(\AD<0>_II/UIM ),
    .O(\NlwInverterSignal_U2_ADDR_reg<0>_MC.D2_PT_1/IN3 )
  );
  X_INV \NlwInverterBlock_U2_ADDR_reg<0>_MC.D2_PT_1/IN4  (
    .I(\AS_II/UIM ),
    .O(\NlwInverterSignal_U2_ADDR_reg<0>_MC.D2_PT_1/IN4 )
  );
  X_INV \NlwInverterBlock_U2_ADDR_reg<0>_MC.D2_PT_2/IN2  (
    .I(U2_ADDR_reg[0]),
    .O(\NlwInverterSignal_U2_ADDR_reg<0>_MC.D2_PT_2/IN2 )
  );
  X_INV \NlwInverterBlock_U2_ADDR_reg<0>_MC.D2_PT_2/IN5  (
    .I(\AS_II/UIM ),
    .O(\NlwInverterSignal_U2_ADDR_reg<0>_MC.D2_PT_2/IN5 )
  );
  X_INV \NlwInverterBlock_U2_ADDR_reg<0>_MC.D2_PT_3/IN2  (
    .I(U2_ADDR_reg[4]),
    .O(\NlwInverterSignal_U2_ADDR_reg<0>_MC.D2_PT_3/IN2 )
  );
  X_INV \NlwInverterBlock_U2_ADDR_reg<0>_MC.D2_PT_3/IN3  (
    .I(U2_ADDR_reg[5]),
    .O(\NlwInverterSignal_U2_ADDR_reg<0>_MC.D2_PT_3/IN3 )
  );
  X_INV \NlwInverterBlock_U2_ADDR_reg<0>_MC.D2_PT_3/IN4  (
    .I(U2_ADDR_reg[6]),
    .O(\NlwInverterSignal_U2_ADDR_reg<0>_MC.D2_PT_3/IN4 )
  );
  X_INV \NlwInverterBlock_U2_ADDR_reg<0>_MC.D2_PT_3/IN5  (
    .I(U2_ADDR_reg[7]),
    .O(\NlwInverterSignal_U2_ADDR_reg<0>_MC.D2_PT_3/IN5 )
  );
  X_INV \NlwInverterBlock_U2_ADDR_reg<0>_MC.D2_PT_3/IN7  (
    .I(U2_WRRDedge),
    .O(\NlwInverterSignal_U2_ADDR_reg<0>_MC.D2_PT_3/IN7 )
  );
  X_INV \NlwInverterBlock_U2_ADDR_reg<4>_MC.D2_PT_0/IN1  (
    .I(\MSPReset_II/UIM ),
    .O(\NlwInverterSignal_U2_ADDR_reg<4>_MC.D2_PT_0/IN1 )
  );
  X_INV \NlwInverterBlock_U2_ADDR_reg<4>_MC.D2_PT_1/IN3  (
    .I(\AS_II/UIM ),
    .O(\NlwInverterSignal_U2_ADDR_reg<4>_MC.D2_PT_1/IN3 )
  );
  X_INV \NlwInverterBlock_U2_ADDR_reg<4>_MC.D2_PT_1/IN5  (
    .I(\AD<4>_II/UIM ),
    .O(\NlwInverterSignal_U2_ADDR_reg<4>_MC.D2_PT_1/IN5 )
  );
  X_INV \NlwInverterBlock_U2_ADDR_reg<4>_MC.D2_PT_2/IN2  (
    .I(U2_ADDR_reg[4]),
    .O(\NlwInverterSignal_U2_ADDR_reg<4>_MC.D2_PT_2/IN2 )
  );
  X_INV \NlwInverterBlock_U2_ADDR_reg<4>_MC.D2_PT_2/IN4  (
    .I(\AS_II/UIM ),
    .O(\NlwInverterSignal_U2_ADDR_reg<4>_MC.D2_PT_2/IN4 )
  );
  X_INV \NlwInverterBlock_U2_ADDR_reg<5>_MC.D2_PT_0/IN1  (
    .I(\MSPReset_II/UIM ),
    .O(\NlwInverterSignal_U2_ADDR_reg<5>_MC.D2_PT_0/IN1 )
  );
  X_INV \NlwInverterBlock_U2_ADDR_reg<5>_MC.D2_PT_1/IN3  (
    .I(\AS_II/UIM ),
    .O(\NlwInverterSignal_U2_ADDR_reg<5>_MC.D2_PT_1/IN3 )
  );
  X_INV \NlwInverterBlock_U2_ADDR_reg<5>_MC.D2_PT_1/IN5  (
    .I(\AD<5>_II/UIM ),
    .O(\NlwInverterSignal_U2_ADDR_reg<5>_MC.D2_PT_1/IN5 )
  );
  X_INV \NlwInverterBlock_U2_ADDR_reg<5>_MC.D2_PT_2/IN2  (
    .I(U2_ADDR_reg[5]),
    .O(\NlwInverterSignal_U2_ADDR_reg<5>_MC.D2_PT_2/IN2 )
  );
  X_INV \NlwInverterBlock_U2_ADDR_reg<5>_MC.D2_PT_2/IN4  (
    .I(\AS_II/UIM ),
    .O(\NlwInverterSignal_U2_ADDR_reg<5>_MC.D2_PT_2/IN4 )
  );
  X_INV \NlwInverterBlock_U2_ADDR_reg<6>_MC.D2_PT_0/IN1  (
    .I(\MSPReset_II/UIM ),
    .O(\NlwInverterSignal_U2_ADDR_reg<6>_MC.D2_PT_0/IN1 )
  );
  X_INV \NlwInverterBlock_U2_ADDR_reg<6>_MC.D2_PT_1/IN3  (
    .I(\AS_II/UIM ),
    .O(\NlwInverterSignal_U2_ADDR_reg<6>_MC.D2_PT_1/IN3 )
  );
  X_INV \NlwInverterBlock_U2_ADDR_reg<6>_MC.D2_PT_1/IN5  (
    .I(\AD<6>_II/UIM ),
    .O(\NlwInverterSignal_U2_ADDR_reg<6>_MC.D2_PT_1/IN5 )
  );
  X_INV \NlwInverterBlock_U2_ADDR_reg<6>_MC.D2_PT_2/IN2  (
    .I(U2_ADDR_reg[6]),
    .O(\NlwInverterSignal_U2_ADDR_reg<6>_MC.D2_PT_2/IN2 )
  );
  X_INV \NlwInverterBlock_U2_ADDR_reg<6>_MC.D2_PT_2/IN4  (
    .I(\AS_II/UIM ),
    .O(\NlwInverterSignal_U2_ADDR_reg<6>_MC.D2_PT_2/IN4 )
  );
  X_INV \NlwInverterBlock_U2_ADDR_reg<7>_MC.D2_PT_0/IN1  (
    .I(\MSPReset_II/UIM ),
    .O(\NlwInverterSignal_U2_ADDR_reg<7>_MC.D2_PT_0/IN1 )
  );
  X_INV \NlwInverterBlock_U2_ADDR_reg<7>_MC.D2_PT_1/IN3  (
    .I(\AS_II/UIM ),
    .O(\NlwInverterSignal_U2_ADDR_reg<7>_MC.D2_PT_1/IN3 )
  );
  X_INV \NlwInverterBlock_U2_ADDR_reg<7>_MC.D2_PT_1/IN5  (
    .I(\AD<7>_II/UIM ),
    .O(\NlwInverterSignal_U2_ADDR_reg<7>_MC.D2_PT_1/IN5 )
  );
  X_INV \NlwInverterBlock_U2_ADDR_reg<7>_MC.D2_PT_2/IN2  (
    .I(U2_ADDR_reg[7]),
    .O(\NlwInverterSignal_U2_ADDR_reg<7>_MC.D2_PT_2/IN2 )
  );
  X_INV \NlwInverterBlock_U2_ADDR_reg<7>_MC.D2_PT_2/IN4  (
    .I(\AS_II/UIM ),
    .O(\NlwInverterSignal_U2_ADDR_reg<7>_MC.D2_PT_2/IN4 )
  );
  X_INV \NlwInverterBlock_U2_AutoInc_MC.D/IN0  (
    .I(\U2_AutoInc_MC.D1 ),
    .O(\NlwInverterSignal_U2_AutoInc_MC.D/IN0 )
  );
  X_INV \NlwInverterBlock_N_PZ_941_MC.D2_PT_1/IN1  (
    .I(U2_ASedge),
    .O(\NlwInverterSignal_N_PZ_941_MC.D2_PT_1/IN1 )
  );
  X_INV \NlwInverterBlock_U2_ADDR_reg<3>_MC.D2_PT_0/IN1  (
    .I(\MSPReset_II/UIM ),
    .O(\NlwInverterSignal_U2_ADDR_reg<3>_MC.D2_PT_0/IN1 )
  );
  X_INV \NlwInverterBlock_U2_ADDR_reg<3>_MC.D2_PT_1/IN3  (
    .I(\AS_II/UIM ),
    .O(\NlwInverterSignal_U2_ADDR_reg<3>_MC.D2_PT_1/IN3 )
  );
  X_INV \NlwInverterBlock_U2_ADDR_reg<3>_MC.D2_PT_1/IN5  (
    .I(\AD<3>_II/UIM ),
    .O(\NlwInverterSignal_U2_ADDR_reg<3>_MC.D2_PT_1/IN5 )
  );
  X_INV \NlwInverterBlock_U2_ADDR_reg<3>_MC.D2_PT_2/IN2  (
    .I(U2_ADDR_reg[3]),
    .O(\NlwInverterSignal_U2_ADDR_reg<3>_MC.D2_PT_2/IN2 )
  );
  X_INV \NlwInverterBlock_U2_ADDR_reg<3>_MC.D2_PT_2/IN4  (
    .I(\AS_II/UIM ),
    .O(\NlwInverterSignal_U2_ADDR_reg<3>_MC.D2_PT_2/IN4 )
  );
  X_INV \NlwInverterBlock_U2_ADDR_reg<3>_MC.D2_PT_3/IN3  (
    .I(U2_ADDR_reg[4]),
    .O(\NlwInverterSignal_U2_ADDR_reg<3>_MC.D2_PT_3/IN3 )
  );
  X_INV \NlwInverterBlock_U2_ADDR_reg<3>_MC.D2_PT_3/IN4  (
    .I(U2_ADDR_reg[5]),
    .O(\NlwInverterSignal_U2_ADDR_reg<3>_MC.D2_PT_3/IN4 )
  );
  X_INV \NlwInverterBlock_U2_ADDR_reg<3>_MC.D2_PT_3/IN5  (
    .I(U2_ADDR_reg[6]),
    .O(\NlwInverterSignal_U2_ADDR_reg<3>_MC.D2_PT_3/IN5 )
  );
  X_INV \NlwInverterBlock_U2_ADDR_reg<3>_MC.D2_PT_3/IN6  (
    .I(U2_ADDR_reg[7]),
    .O(\NlwInverterSignal_U2_ADDR_reg<3>_MC.D2_PT_3/IN6 )
  );
  X_INV \NlwInverterBlock_U2_ADDR_reg<3>_MC.D2_PT_3/IN10  (
    .I(U2_WRRDedge),
    .O(\NlwInverterSignal_U2_ADDR_reg<3>_MC.D2_PT_3/IN10 )
  );
  X_INV \NlwInverterBlock_U2_ADDR_reg<1>_MC.D2_PT_0/IN1  (
    .I(\MSPReset_II/UIM ),
    .O(\NlwInverterSignal_U2_ADDR_reg<1>_MC.D2_PT_0/IN1 )
  );
  X_INV \NlwInverterBlock_U2_ADDR_reg<1>_MC.D2_PT_1/IN3  (
    .I(\AS_II/UIM ),
    .O(\NlwInverterSignal_U2_ADDR_reg<1>_MC.D2_PT_1/IN3 )
  );
  X_INV \NlwInverterBlock_U2_ADDR_reg<1>_MC.D2_PT_1/IN5  (
    .I(\AD<1>_II/UIM ),
    .O(\NlwInverterSignal_U2_ADDR_reg<1>_MC.D2_PT_1/IN5 )
  );
  X_INV \NlwInverterBlock_U2_ADDR_reg<1>_MC.D2_PT_2/IN2  (
    .I(U2_ADDR_reg[1]),
    .O(\NlwInverterSignal_U2_ADDR_reg<1>_MC.D2_PT_2/IN2 )
  );
  X_INV \NlwInverterBlock_U2_ADDR_reg<1>_MC.D2_PT_2/IN4  (
    .I(\AS_II/UIM ),
    .O(\NlwInverterSignal_U2_ADDR_reg<1>_MC.D2_PT_2/IN4 )
  );
  X_INV \NlwInverterBlock_U2_ADDR_reg<1>_MC.D2_PT_3/IN3  (
    .I(U2_ADDR_reg[4]),
    .O(\NlwInverterSignal_U2_ADDR_reg<1>_MC.D2_PT_3/IN3 )
  );
  X_INV \NlwInverterBlock_U2_ADDR_reg<1>_MC.D2_PT_3/IN4  (
    .I(U2_ADDR_reg[5]),
    .O(\NlwInverterSignal_U2_ADDR_reg<1>_MC.D2_PT_3/IN4 )
  );
  X_INV \NlwInverterBlock_U2_ADDR_reg<1>_MC.D2_PT_3/IN5  (
    .I(U2_ADDR_reg[6]),
    .O(\NlwInverterSignal_U2_ADDR_reg<1>_MC.D2_PT_3/IN5 )
  );
  X_INV \NlwInverterBlock_U2_ADDR_reg<1>_MC.D2_PT_3/IN6  (
    .I(U2_ADDR_reg[7]),
    .O(\NlwInverterSignal_U2_ADDR_reg<1>_MC.D2_PT_3/IN6 )
  );
  X_INV \NlwInverterBlock_U2_ADDR_reg<1>_MC.D2_PT_3/IN8  (
    .I(U2_WRRDedge),
    .O(\NlwInverterSignal_U2_ADDR_reg<1>_MC.D2_PT_3/IN8 )
  );
  X_INV \NlwInverterBlock_U2_ADDR_reg<2>_MC.D2_PT_0/IN1  (
    .I(\MSPReset_II/UIM ),
    .O(\NlwInverterSignal_U2_ADDR_reg<2>_MC.D2_PT_0/IN1 )
  );
  X_INV \NlwInverterBlock_U2_ADDR_reg<2>_MC.D2_PT_1/IN3  (
    .I(\AS_II/UIM ),
    .O(\NlwInverterSignal_U2_ADDR_reg<2>_MC.D2_PT_1/IN3 )
  );
  X_INV \NlwInverterBlock_U2_ADDR_reg<2>_MC.D2_PT_1/IN5  (
    .I(\AD<2>_II/UIM ),
    .O(\NlwInverterSignal_U2_ADDR_reg<2>_MC.D2_PT_1/IN5 )
  );
  X_INV \NlwInverterBlock_U2_ADDR_reg<2>_MC.D2_PT_2/IN2  (
    .I(U2_ADDR_reg[2]),
    .O(\NlwInverterSignal_U2_ADDR_reg<2>_MC.D2_PT_2/IN2 )
  );
  X_INV \NlwInverterBlock_U2_ADDR_reg<2>_MC.D2_PT_2/IN4  (
    .I(\AS_II/UIM ),
    .O(\NlwInverterSignal_U2_ADDR_reg<2>_MC.D2_PT_2/IN4 )
  );
  X_INV \NlwInverterBlock_U2_ADDR_reg<2>_MC.D2_PT_3/IN3  (
    .I(U2_ADDR_reg[4]),
    .O(\NlwInverterSignal_U2_ADDR_reg<2>_MC.D2_PT_3/IN3 )
  );
  X_INV \NlwInverterBlock_U2_ADDR_reg<2>_MC.D2_PT_3/IN4  (
    .I(U2_ADDR_reg[5]),
    .O(\NlwInverterSignal_U2_ADDR_reg<2>_MC.D2_PT_3/IN4 )
  );
  X_INV \NlwInverterBlock_U2_ADDR_reg<2>_MC.D2_PT_3/IN5  (
    .I(U2_ADDR_reg[6]),
    .O(\NlwInverterSignal_U2_ADDR_reg<2>_MC.D2_PT_3/IN5 )
  );
  X_INV \NlwInverterBlock_U2_ADDR_reg<2>_MC.D2_PT_3/IN6  (
    .I(U2_ADDR_reg[7]),
    .O(\NlwInverterSignal_U2_ADDR_reg<2>_MC.D2_PT_3/IN6 )
  );
  X_INV \NlwInverterBlock_U2_ADDR_reg<2>_MC.D2_PT_3/IN9  (
    .I(U2_WRRDedge),
    .O(\NlwInverterSignal_U2_ADDR_reg<2>_MC.D2_PT_3/IN9 )
  );
  X_INV \NlwInverterBlock_U2_Enable_AD_MC.D1/IN1  (
    .I(\RD_II/UIM ),
    .O(\NlwInverterSignal_U2_Enable_AD_MC.D1/IN1 )
  );
  X_INV \NlwInverterBlock_U2_Enable_AD_MC.D1/IN2  (
    .I(U2_ADDR_reg[4]),
    .O(\NlwInverterSignal_U2_Enable_AD_MC.D1/IN2 )
  );
  X_INV \NlwInverterBlock_U2_Enable_AD_MC.D1/IN3  (
    .I(U2_ADDR_reg[5]),
    .O(\NlwInverterSignal_U2_Enable_AD_MC.D1/IN3 )
  );
  X_INV \NlwInverterBlock_U2_Enable_AD_MC.D1/IN4  (
    .I(U2_ADDR_reg[6]),
    .O(\NlwInverterSignal_U2_Enable_AD_MC.D1/IN4 )
  );
  X_INV \NlwInverterBlock_U2_Enable_AD_MC.D1/IN5  (
    .I(U2_ADDR_reg[7]),
    .O(\NlwInverterSignal_U2_Enable_AD_MC.D1/IN5 )
  );
  X_INV \NlwInverterBlock_U4/ctrlr<3>_MC.D/IN0  (
    .I(\U4/ctrlr<3>_MC.D1 ),
    .O(\NlwInverterSignal_U4/ctrlr<3>_MC.D/IN0 )
  );
  X_INV \NlwInverterBlock_U4/ctrlr<3>_MC.D2_PT_0/IN1  (
    .I(\outDATA<3>\$WA0.UIM ),
    .O(\NlwInverterSignal_U4/ctrlr<3>_MC.D2_PT_0/IN1 )
  );
  X_INV \NlwInverterBlock_U4/ctrlr<3>_MC.D2_PT_1/IN1  (
    .I(\outDATA<3>\$WA1.UIM ),
    .O(\NlwInverterSignal_U4/ctrlr<3>_MC.D2_PT_1/IN1 )
  );
  X_INV \NlwInverterBlock_U4/ctrlr<3>_MC.D2_PT_2/IN1  (
    .I(\outDATA<3>\$WA2.UIM ),
    .O(\NlwInverterSignal_U4/ctrlr<3>_MC.D2_PT_2/IN1 )
  );
  X_INV \NlwInverterBlock_U4/ctrlr<3>_MC.D2_PT_3/IN1  (
    .I(\outDATA<3>\$WA3.UIM ),
    .O(\NlwInverterSignal_U4/ctrlr<3>_MC.D2_PT_3/IN1 )
  );
  X_INV \NlwInverterBlock_U4/ctrlr<3>_MC.D2_PT_4/IN0  (
    .I(N_PZ_963),
    .O(\NlwInverterSignal_U4/ctrlr<3>_MC.D2_PT_4/IN0 )
  );
  X_INV \NlwInverterBlock_U4/ctrlr<3>_MC.D2_PT_4/IN1  (
    .I(\outDATA<3>\$WA5.UIM ),
    .O(\NlwInverterSignal_U4/ctrlr<3>_MC.D2_PT_4/IN1 )
  );
  X_INV \NlwInverterBlock_U4/ctrlr<3>_MC.D2_PT_5/IN0  (
    .I(N_PZ_980),
    .O(\NlwInverterSignal_U4/ctrlr<3>_MC.D2_PT_5/IN0 )
  );
  X_INV \NlwInverterBlock_U4/ctrlr<3>_MC.D2_PT_5/IN1  (
    .I(\outDATA<3>\$WA6.UIM ),
    .O(\NlwInverterSignal_U4/ctrlr<3>_MC.D2_PT_5/IN1 )
  );
  X_INV \NlwInverterBlock_Enc05ctrl_MC.D/IN0  (
    .I(\Enc05ctrl_MC.D1 ),
    .O(\NlwInverterSignal_Enc05ctrl_MC.D/IN0 )
  );
  X_INV \NlwInverterBlock_Enc05ctrl_MC.D1/IN0  (
    .I(\U4/ctrlr [2]),
    .O(\NlwInverterSignal_Enc05ctrl_MC.D1/IN0 )
  );
  X_INV \NlwInverterBlock_Enc133ctrl_MC.D/IN0  (
    .I(\Enc133ctrl_MC.D1 ),
    .O(\NlwInverterSignal_Enc133ctrl_MC.D/IN0 )
  );
  X_INV \NlwInverterBlock_U4/ctrlr<6>_MC.D/IN0  (
    .I(\U4/ctrlr<6>_MC.D1 ),
    .O(\NlwInverterSignal_U4/ctrlr<6>_MC.D/IN0 )
  );
  X_INV \NlwInverterBlock_U4/ctrlr<6>_MC.D2_PT_0/IN1  (
    .I(\outDATA<6>\$WA0.UIM ),
    .O(\NlwInverterSignal_U4/ctrlr<6>_MC.D2_PT_0/IN1 )
  );
  X_INV \NlwInverterBlock_U4/ctrlr<6>_MC.D2_PT_1/IN1  (
    .I(\outDATA<6>\$WA1.UIM ),
    .O(\NlwInverterSignal_U4/ctrlr<6>_MC.D2_PT_1/IN1 )
  );
  X_INV \NlwInverterBlock_U4/ctrlr<6>_MC.D2_PT_2/IN1  (
    .I(\outDATA<6>\$WA2.UIM ),
    .O(\NlwInverterSignal_U4/ctrlr<6>_MC.D2_PT_2/IN1 )
  );
  X_INV \NlwInverterBlock_U4/ctrlr<6>_MC.D2_PT_3/IN1  (
    .I(\outDATA<6>\$WA3.UIM ),
    .O(\NlwInverterSignal_U4/ctrlr<6>_MC.D2_PT_3/IN1 )
  );
  X_INV \NlwInverterBlock_U4/ctrlr<6>_MC.D2_PT_4/IN0  (
    .I(N_PZ_963),
    .O(\NlwInverterSignal_U4/ctrlr<6>_MC.D2_PT_4/IN0 )
  );
  X_INV \NlwInverterBlock_U4/ctrlr<6>_MC.D2_PT_4/IN1  (
    .I(\outDATA<6>\$WA5.UIM ),
    .O(\NlwInverterSignal_U4/ctrlr<6>_MC.D2_PT_4/IN1 )
  );
  X_INV \NlwInverterBlock_U4/ctrlr<6>_MC.D2_PT_5/IN0  (
    .I(N_PZ_980),
    .O(\NlwInverterSignal_U4/ctrlr<6>_MC.D2_PT_5/IN0 )
  );
  X_INV \NlwInverterBlock_U4/ctrlr<6>_MC.D2_PT_5/IN1  (
    .I(\outDATA<6>\$WA6.UIM ),
    .O(\NlwInverterSignal_U4/ctrlr<6>_MC.D2_PT_5/IN1 )
  );
  X_INV \NlwInverterBlock_U4/ctrlr<7>_MC.D/IN0  (
    .I(\U4/ctrlr<7>_MC.D1 ),
    .O(\NlwInverterSignal_U4/ctrlr<7>_MC.D/IN0 )
  );
  X_INV \NlwInverterBlock_U4/ctrlr<7>_MC.D2_PT_0/IN1  (
    .I(\outDATA<7>\$WA0.UIM ),
    .O(\NlwInverterSignal_U4/ctrlr<7>_MC.D2_PT_0/IN1 )
  );
  X_INV \NlwInverterBlock_U4/ctrlr<7>_MC.D2_PT_1/IN1  (
    .I(\outDATA<7>\$WA1.UIM ),
    .O(\NlwInverterSignal_U4/ctrlr<7>_MC.D2_PT_1/IN1 )
  );
  X_INV \NlwInverterBlock_U4/ctrlr<7>_MC.D2_PT_2/IN1  (
    .I(\outDATA<7>\$WA2.UIM ),
    .O(\NlwInverterSignal_U4/ctrlr<7>_MC.D2_PT_2/IN1 )
  );
  X_INV \NlwInverterBlock_U4/ctrlr<7>_MC.D2_PT_3/IN1  (
    .I(\outDATA<7>\$WA3.UIM ),
    .O(\NlwInverterSignal_U4/ctrlr<7>_MC.D2_PT_3/IN1 )
  );
  X_INV \NlwInverterBlock_U4/ctrlr<7>_MC.D2_PT_4/IN0  (
    .I(N_PZ_963),
    .O(\NlwInverterSignal_U4/ctrlr<7>_MC.D2_PT_4/IN0 )
  );
  X_INV \NlwInverterBlock_U4/ctrlr<7>_MC.D2_PT_4/IN1  (
    .I(\outDATA<7>\$WA5.UIM ),
    .O(\NlwInverterSignal_U4/ctrlr<7>_MC.D2_PT_4/IN1 )
  );
  X_INV \NlwInverterBlock_U4/ctrlr<7>_MC.D2_PT_5/IN0  (
    .I(\outDATA<7>\$WA4.UIM ),
    .O(\NlwInverterSignal_U4/ctrlr<7>_MC.D2_PT_5/IN0 )
  );
  X_INV \NlwInverterBlock_U4/ctrlr<7>_MC.D2_PT_6/IN1  (
    .I(\outDATA<7>\$WA6.UIM ),
    .O(\NlwInverterSignal_U4/ctrlr<7>_MC.D2_PT_6/IN1 )
  );
  X_INV \NlwInverterBlock_U4/ctrlr<7>_MC.D2_PT_7/IN0  (
    .I(N_PZ_980),
    .O(\NlwInverterSignal_U4/ctrlr<7>_MC.D2_PT_7/IN0 )
  );
  X_INV \NlwInverterBlock_U4/ctrlr<7>_MC.D2_PT_7/IN1  (
    .I(DCORIFGr),
    .O(\NlwInverterSignal_U4/ctrlr<7>_MC.D2_PT_7/IN1 )
  );
  X_INV \NlwInverterBlock_U4/ctrlr<7>_MC.D2_PT_7/IN2  (
    .I(\outDATA<7>\$WA6.UIM ),
    .O(\NlwInverterSignal_U4/ctrlr<7>_MC.D2_PT_7/IN2 )
  );
  X_INV \NlwInverterBlock_Enc15ctrl_MC.D/IN0  (
    .I(\Enc15ctrl_MC.D1 ),
    .O(\NlwInverterSignal_Enc15ctrl_MC.D/IN0 )
  );
  X_INV \NlwInverterBlock_Enc15ctrl_MC.D1/IN0  (
    .I(\U4/ctrlr [6]),
    .O(\NlwInverterSignal_Enc15ctrl_MC.D1/IN0 )
  );
  X_INV \NlwInverterBlock_DCOROUTw_MC.D1/IN0  (
    .I(\WR_II/UIM ),
    .O(\NlwInverterSignal_DCOROUTw_MC.D1/IN0 )
  );
  X_INV \NlwInverterBlock_DCOROUTw_MC.D1/IN3  (
    .I(U2_ADDR_reg[4]),
    .O(\NlwInverterSignal_DCOROUTw_MC.D1/IN3 )
  );
  X_INV \NlwInverterBlock_DCOROUTw_MC.D1/IN4  (
    .I(U2_ADDR_reg[5]),
    .O(\NlwInverterSignal_DCOROUTw_MC.D1/IN4 )
  );
  X_INV \NlwInverterBlock_DCOROUTw_MC.D1/IN5  (
    .I(U2_ADDR_reg[6]),
    .O(\NlwInverterSignal_DCOROUTw_MC.D1/IN5 )
  );
  X_INV \NlwInverterBlock_DCOROUTw_MC.D1/IN6  (
    .I(U2_ADDR_reg[7]),
    .O(\NlwInverterSignal_DCOROUTw_MC.D1/IN6 )
  );
  X_INV \NlwInverterBlock_Home033ctrl_MC.D/IN0  (
    .I(\Home033ctrl_MC.D1 ),
    .O(\NlwInverterSignal_Home033ctrl_MC.D/IN0 )
  );
  X_INV \NlwInverterBlock_Home033ctrl_MC.D1/IN1  (
    .I(\U4/ctrlr [1]),
    .O(\NlwInverterSignal_Home033ctrl_MC.D1/IN1 )
  );
  X_INV \NlwInverterBlock_U4/ctrlr<0>_MC.D/IN0  (
    .I(\U4/ctrlr<0>_MC.D1 ),
    .O(\NlwInverterSignal_U4/ctrlr<0>_MC.D/IN0 )
  );
  X_INV \NlwInverterBlock_U4/ctrlr<0>_MC.D2_PT_0/IN1  (
    .I(\outDATA<0>\$WA0.UIM ),
    .O(\NlwInverterSignal_U4/ctrlr<0>_MC.D2_PT_0/IN1 )
  );
  X_INV \NlwInverterBlock_U4/ctrlr<0>_MC.D2_PT_1/IN1  (
    .I(\outDATA<0>\$WA1.UIM ),
    .O(\NlwInverterSignal_U4/ctrlr<0>_MC.D2_PT_1/IN1 )
  );
  X_INV \NlwInverterBlock_U4/ctrlr<0>_MC.D2_PT_2/IN1  (
    .I(\outDATA<0>\$WA2.UIM ),
    .O(\NlwInverterSignal_U4/ctrlr<0>_MC.D2_PT_2/IN1 )
  );
  X_INV \NlwInverterBlock_U4/ctrlr<0>_MC.D2_PT_3/IN1  (
    .I(\outDATA<0>\$WA3.UIM ),
    .O(\NlwInverterSignal_U4/ctrlr<0>_MC.D2_PT_3/IN1 )
  );
  X_INV \NlwInverterBlock_U4/ctrlr<0>_MC.D2_PT_4/IN0  (
    .I(N_PZ_963),
    .O(\NlwInverterSignal_U4/ctrlr<0>_MC.D2_PT_4/IN0 )
  );
  X_INV \NlwInverterBlock_U4/ctrlr<0>_MC.D2_PT_4/IN1  (
    .I(\outDATA<0>\$WA5.UIM ),
    .O(\NlwInverterSignal_U4/ctrlr<0>_MC.D2_PT_4/IN1 )
  );
  X_INV \NlwInverterBlock_U4/ctrlr<0>_MC.D2_PT_5/IN1  (
    .I(\outDATA<0>\$WA4.UIM ),
    .O(\NlwInverterSignal_U4/ctrlr<0>_MC.D2_PT_5/IN1 )
  );
  X_INV \NlwInverterBlock_U4/ctrlr<0>_MC.D2_PT_6/IN1  (
    .I(\outDATA<0>\$WA6.UIM ),
    .O(\NlwInverterSignal_U4/ctrlr<0>_MC.D2_PT_6/IN1 )
  );
  X_INV \NlwInverterBlock_U4/ctrlr<0>_MC.D2_PT_7/IN0  (
    .I(N_PZ_980),
    .O(\NlwInverterSignal_U4/ctrlr<0>_MC.D2_PT_7/IN0 )
  );
  X_INV \NlwInverterBlock_U4/ctrlr<0>_MC.D2_PT_7/IN1  (
    .I(DCORIFGr),
    .O(\NlwInverterSignal_U4/ctrlr<0>_MC.D2_PT_7/IN1 )
  );
  X_INV \NlwInverterBlock_U4/ctrlr<0>_MC.D2_PT_7/IN2  (
    .I(\outDATA<0>\$WA6.UIM ),
    .O(\NlwInverterSignal_U4/ctrlr<0>_MC.D2_PT_7/IN2 )
  );
  X_INV \NlwInverterBlock_U4/ctrlr<1>_MC.D/IN0  (
    .I(\U4/ctrlr<1>_MC.D1 ),
    .O(\NlwInverterSignal_U4/ctrlr<1>_MC.D/IN0 )
  );
  X_INV \NlwInverterBlock_U4/ctrlr<1>_MC.D2_PT_0/IN1  (
    .I(\outDATA<1>\$WA0.UIM ),
    .O(\NlwInverterSignal_U4/ctrlr<1>_MC.D2_PT_0/IN1 )
  );
  X_INV \NlwInverterBlock_U4/ctrlr<1>_MC.D2_PT_1/IN1  (
    .I(\outDATA<1>\$WA1.UIM ),
    .O(\NlwInverterSignal_U4/ctrlr<1>_MC.D2_PT_1/IN1 )
  );
  X_INV \NlwInverterBlock_U4/ctrlr<1>_MC.D2_PT_2/IN1  (
    .I(\outDATA<1>\$WA2.UIM ),
    .O(\NlwInverterSignal_U4/ctrlr<1>_MC.D2_PT_2/IN1 )
  );
  X_INV \NlwInverterBlock_U4/ctrlr<1>_MC.D2_PT_3/IN1  (
    .I(\outDATA<1>\$WA3.UIM ),
    .O(\NlwInverterSignal_U4/ctrlr<1>_MC.D2_PT_3/IN1 )
  );
  X_INV \NlwInverterBlock_U4/ctrlr<1>_MC.D2_PT_4/IN0  (
    .I(N_PZ_963),
    .O(\NlwInverterSignal_U4/ctrlr<1>_MC.D2_PT_4/IN0 )
  );
  X_INV \NlwInverterBlock_U4/ctrlr<1>_MC.D2_PT_4/IN1  (
    .I(\outDATA<1>\$WA5.UIM ),
    .O(\NlwInverterSignal_U4/ctrlr<1>_MC.D2_PT_4/IN1 )
  );
  X_INV \NlwInverterBlock_U4/ctrlr<1>_MC.D2_PT_5/IN1  (
    .I(\outDATA<1>\$WA3.UIM ),
    .O(\NlwInverterSignal_U4/ctrlr<1>_MC.D2_PT_5/IN1 )
  );
  X_INV \NlwInverterBlock_U4/ctrlr<1>_MC.D2_PT_6/IN1  (
    .I(\outDATA<1>\$WA6.UIM ),
    .O(\NlwInverterSignal_U4/ctrlr<1>_MC.D2_PT_6/IN1 )
  );
  X_INV \NlwInverterBlock_U4/ctrlr<1>_MC.D2_PT_7/IN0  (
    .I(N_PZ_980),
    .O(\NlwInverterSignal_U4/ctrlr<1>_MC.D2_PT_7/IN0 )
  );
  X_INV \NlwInverterBlock_U4/ctrlr<1>_MC.D2_PT_7/IN1  (
    .I(DCORIFGr),
    .O(\NlwInverterSignal_U4/ctrlr<1>_MC.D2_PT_7/IN1 )
  );
  X_INV \NlwInverterBlock_U4/ctrlr<1>_MC.D2_PT_7/IN2  (
    .I(\outDATA<1>\$WA6.UIM ),
    .O(\NlwInverterSignal_U4/ctrlr<1>_MC.D2_PT_7/IN2 )
  );
  X_INV \NlwInverterBlock_Home05ctrl_MC.D/IN0  (
    .I(\Home05ctrl_MC.D1 ),
    .O(\NlwInverterSignal_Home05ctrl_MC.D/IN0 )
  );
  X_INV \NlwInverterBlock_Home05ctrl_MC.D1/IN0  (
    .I(\U4/ctrlr [0]),
    .O(\NlwInverterSignal_Home05ctrl_MC.D1/IN0 )
  );
  X_INV \NlwInverterBlock_Home133ctrl_MC.D/IN0  (
    .I(\Home133ctrl_MC.D1 ),
    .O(\NlwInverterSignal_Home133ctrl_MC.D/IN0 )
  );
  X_INV \NlwInverterBlock_Home133ctrl_MC.D1/IN1  (
    .I(\U4/ctrlr [5]),
    .O(\NlwInverterSignal_Home133ctrl_MC.D1/IN1 )
  );
  X_INV \NlwInverterBlock_U4/ctrlr<4>_MC.D/IN0  (
    .I(\U4/ctrlr<4>_MC.D1 ),
    .O(\NlwInverterSignal_U4/ctrlr<4>_MC.D/IN0 )
  );
  X_INV \NlwInverterBlock_U4/ctrlr<4>_MC.D2_PT_0/IN1  (
    .I(\outDATA<4>\$WA0.UIM ),
    .O(\NlwInverterSignal_U4/ctrlr<4>_MC.D2_PT_0/IN1 )
  );
  X_INV \NlwInverterBlock_U4/ctrlr<4>_MC.D2_PT_1/IN1  (
    .I(\outDATA<4>\$WA1.UIM ),
    .O(\NlwInverterSignal_U4/ctrlr<4>_MC.D2_PT_1/IN1 )
  );
  X_INV \NlwInverterBlock_U4/ctrlr<4>_MC.D2_PT_2/IN1  (
    .I(\outDATA<4>\$WA2.UIM ),
    .O(\NlwInverterSignal_U4/ctrlr<4>_MC.D2_PT_2/IN1 )
  );
  X_INV \NlwInverterBlock_U4/ctrlr<4>_MC.D2_PT_3/IN1  (
    .I(\outDATA<4>\$WA3.UIM ),
    .O(\NlwInverterSignal_U4/ctrlr<4>_MC.D2_PT_3/IN1 )
  );
  X_INV \NlwInverterBlock_U4/ctrlr<4>_MC.D2_PT_4/IN0  (
    .I(N_PZ_963),
    .O(\NlwInverterSignal_U4/ctrlr<4>_MC.D2_PT_4/IN0 )
  );
  X_INV \NlwInverterBlock_U4/ctrlr<4>_MC.D2_PT_4/IN1  (
    .I(\outDATA<4>\$WA5.UIM ),
    .O(\NlwInverterSignal_U4/ctrlr<4>_MC.D2_PT_4/IN1 )
  );
  X_INV \NlwInverterBlock_U4/ctrlr<4>_MC.D2_PT_5/IN1  (
    .I(\outDATA<4>\$WA4.UIM ),
    .O(\NlwInverterSignal_U4/ctrlr<4>_MC.D2_PT_5/IN1 )
  );
  X_INV \NlwInverterBlock_U4/ctrlr<4>_MC.D2_PT_6/IN1  (
    .I(\outDATA<4>\$WA6.UIM ),
    .O(\NlwInverterSignal_U4/ctrlr<4>_MC.D2_PT_6/IN1 )
  );
  X_INV \NlwInverterBlock_U4/ctrlr<4>_MC.D2_PT_7/IN0  (
    .I(N_PZ_980),
    .O(\NlwInverterSignal_U4/ctrlr<4>_MC.D2_PT_7/IN0 )
  );
  X_INV \NlwInverterBlock_U4/ctrlr<4>_MC.D2_PT_7/IN1  (
    .I(DCORIFGr),
    .O(\NlwInverterSignal_U4/ctrlr<4>_MC.D2_PT_7/IN1 )
  );
  X_INV \NlwInverterBlock_U4/ctrlr<4>_MC.D2_PT_7/IN2  (
    .I(\outDATA<4>\$WA6.UIM ),
    .O(\NlwInverterSignal_U4/ctrlr<4>_MC.D2_PT_7/IN2 )
  );
  X_INV \NlwInverterBlock_U4/ctrlr<5>_MC.D/IN0  (
    .I(\U4/ctrlr<5>_MC.D1 ),
    .O(\NlwInverterSignal_U4/ctrlr<5>_MC.D/IN0 )
  );
  X_INV \NlwInverterBlock_U4/ctrlr<5>_MC.D2_PT_0/IN1  (
    .I(\outDATA<5>\$WA0.UIM ),
    .O(\NlwInverterSignal_U4/ctrlr<5>_MC.D2_PT_0/IN1 )
  );
  X_INV \NlwInverterBlock_U4/ctrlr<5>_MC.D2_PT_1/IN1  (
    .I(\outDATA<5>\$WA1.UIM ),
    .O(\NlwInverterSignal_U4/ctrlr<5>_MC.D2_PT_1/IN1 )
  );
  X_INV \NlwInverterBlock_U4/ctrlr<5>_MC.D2_PT_2/IN1  (
    .I(\outDATA<5>\$WA2.UIM ),
    .O(\NlwInverterSignal_U4/ctrlr<5>_MC.D2_PT_2/IN1 )
  );
  X_INV \NlwInverterBlock_U4/ctrlr<5>_MC.D2_PT_3/IN1  (
    .I(\outDATA<5>\$WA3.UIM ),
    .O(\NlwInverterSignal_U4/ctrlr<5>_MC.D2_PT_3/IN1 )
  );
  X_INV \NlwInverterBlock_U4/ctrlr<5>_MC.D2_PT_4/IN0  (
    .I(N_PZ_963),
    .O(\NlwInverterSignal_U4/ctrlr<5>_MC.D2_PT_4/IN0 )
  );
  X_INV \NlwInverterBlock_U4/ctrlr<5>_MC.D2_PT_4/IN1  (
    .I(\outDATA<5>\$WA5.UIM ),
    .O(\NlwInverterSignal_U4/ctrlr<5>_MC.D2_PT_4/IN1 )
  );
  X_INV \NlwInverterBlock_U4/ctrlr<5>_MC.D2_PT_5/IN0  (
    .I(N_PZ_980),
    .O(\NlwInverterSignal_U4/ctrlr<5>_MC.D2_PT_5/IN0 )
  );
  X_INV \NlwInverterBlock_U4/ctrlr<5>_MC.D2_PT_5/IN1  (
    .I(\outDATA<5>\$WA6.UIM ),
    .O(\NlwInverterSignal_U4/ctrlr<5>_MC.D2_PT_5/IN1 )
  );
  X_INV \NlwInverterBlock_Home15ctrl_MC.D/IN0  (
    .I(\Home15ctrl_MC.D1 ),
    .O(\NlwInverterSignal_Home15ctrl_MC.D/IN0 )
  );
  X_INV \NlwInverterBlock_Home15ctrl_MC.D1/IN0  (
    .I(\U4/ctrlr [4]),
    .O(\NlwInverterSignal_Home15ctrl_MC.D1/IN0 )
  );
  X_INV \NlwInverterBlock_INT_MC.D2_PT_0/IN0  (
    .I(\INTbus_II/UIM ),
    .O(\NlwInverterSignal_INT_MC.D2_PT_0/IN0 )
  );
  X_INV \NlwInverterBlock_U3/DCORIE<0>_MC.D2_PT_1/IN2  (
    .I(DCORIEw),
    .O(\NlwInverterSignal_U3/DCORIE<0>_MC.D2_PT_1/IN2 )
  );
  X_INV \NlwInverterBlock_DCORIEw_MC.D1/IN0  (
    .I(\WR_II/UIM ),
    .O(\NlwInverterSignal_DCORIEw_MC.D1/IN0 )
  );
  X_INV \NlwInverterBlock_DCORIEw_MC.D1/IN2  (
    .I(U2_ADDR_reg[0]),
    .O(\NlwInverterSignal_DCORIEw_MC.D1/IN2 )
  );
  X_INV \NlwInverterBlock_DCORIEw_MC.D1/IN3  (
    .I(U2_ADDR_reg[4]),
    .O(\NlwInverterSignal_DCORIEw_MC.D1/IN3 )
  );
  X_INV \NlwInverterBlock_DCORIEw_MC.D1/IN4  (
    .I(U2_ADDR_reg[5]),
    .O(\NlwInverterSignal_DCORIEw_MC.D1/IN4 )
  );
  X_INV \NlwInverterBlock_DCORIEw_MC.D1/IN5  (
    .I(U2_ADDR_reg[6]),
    .O(\NlwInverterSignal_DCORIEw_MC.D1/IN5 )
  );
  X_INV \NlwInverterBlock_DCORIEw_MC.D1/IN6  (
    .I(U2_ADDR_reg[7]),
    .O(\NlwInverterSignal_DCORIEw_MC.D1/IN6 )
  );
  X_INV \NlwInverterBlock_DCORIEw_MC.D1/IN7  (
    .I(U2_ADDR_reg[3]),
    .O(\NlwInverterSignal_DCORIEw_MC.D1/IN7 )
  );
  X_INV \NlwInverterBlock_DCORIEw_MC.D1/IN8  (
    .I(U2_ADDR_reg[1]),
    .O(\NlwInverterSignal_DCORIEw_MC.D1/IN8 )
  );
  X_INV \NlwInverterBlock_DCORIEw_MC.D1/IN9  (
    .I(U2_ADDR_reg[2]),
    .O(\NlwInverterSignal_DCORIEw_MC.D1/IN9 )
  );
  X_INV \NlwInverterBlock_NET2528_MC.D1/IN1  (
    .I(DCORIFGw),
    .O(\NlwInverterSignal_NET2528_MC.D1/IN1 )
  );
  X_INV \NlwInverterBlock_NET2528_MC.D2_PT_0/IN1  (
    .I(\AD<1>_II/UIM ),
    .O(\NlwInverterSignal_NET2528_MC.D2_PT_0/IN1 )
  );
  X_INV \NlwInverterBlock_NET2528_MC.D2_PT_1/IN1  (
    .I(NET2528),
    .O(\NlwInverterSignal_NET2528_MC.D2_PT_1/IN1 )
  );
  X_INV \NlwInverterBlock_NET2528_MC.D2_PT_1/IN2  (
    .I(DCORIFGw),
    .O(\NlwInverterSignal_NET2528_MC.D2_PT_1/IN2 )
  );
  X_INV \NlwInverterBlock_DCORIFGw_MC.D1/IN0  (
    .I(\WR_II/UIM ),
    .O(\NlwInverterSignal_DCORIFGw_MC.D1/IN0 )
  );
  X_INV \NlwInverterBlock_DCORIFGw_MC.D1/IN3  (
    .I(U2_ADDR_reg[4]),
    .O(\NlwInverterSignal_DCORIFGw_MC.D1/IN3 )
  );
  X_INV \NlwInverterBlock_DCORIFGw_MC.D1/IN4  (
    .I(U2_ADDR_reg[5]),
    .O(\NlwInverterSignal_DCORIFGw_MC.D1/IN4 )
  );
  X_INV \NlwInverterBlock_DCORIFGw_MC.D1/IN5  (
    .I(U2_ADDR_reg[6]),
    .O(\NlwInverterSignal_DCORIFGw_MC.D1/IN5 )
  );
  X_INV \NlwInverterBlock_DCORIFGw_MC.D1/IN6  (
    .I(U2_ADDR_reg[7]),
    .O(\NlwInverterSignal_DCORIFGw_MC.D1/IN6 )
  );
  X_INV \NlwInverterBlock_DCORIFGw_MC.D1/IN7  (
    .I(U2_ADDR_reg[3]),
    .O(\NlwInverterSignal_DCORIFGw_MC.D1/IN7 )
  );
  X_INV \NlwInverterBlock_DCORIFGw_MC.D1/IN8  (
    .I(U2_ADDR_reg[1]),
    .O(\NlwInverterSignal_DCORIFGw_MC.D1/IN8 )
  );
  X_INV \NlwInverterBlock_DCORIFGw_MC.D1/IN9  (
    .I(U2_ADDR_reg[2]),
    .O(\NlwInverterSignal_DCORIFGw_MC.D1/IN9 )
  );
  X_INV \NlwInverterBlock_U3/DCORIE<1>_MC.D2_PT_1/IN2  (
    .I(DCORIEw),
    .O(\NlwInverterSignal_U3/DCORIE<1>_MC.D2_PT_1/IN2 )
  );
  X_INV \NlwInverterBlock_NET2482_MC.D2_PT_0/IN0  (
    .I(\MSPReset_II/UIM ),
    .O(\NlwInverterSignal_NET2482_MC.D2_PT_0/IN0 )
  );
  X_INV \NlwInverterBlock_NET2482_MC.D2_PT_1/IN3  (
    .I(DCORENCCTLw),
    .O(\NlwInverterSignal_NET2482_MC.D2_PT_1/IN3 )
  );
  X_INV \NlwInverterBlock_NET2482_MC.D2_PT_2/IN1  (
    .I(NET2482),
    .O(\NlwInverterSignal_NET2482_MC.D2_PT_2/IN1 )
  );
  X_INV \NlwInverterBlock_NET2482_MC.D2_PT_2/IN2  (
    .I(DCORIFGw),
    .O(\NlwInverterSignal_NET2482_MC.D2_PT_2/IN2 )
  );
  X_INV \NlwInverterBlock_NET2482_MC.D2_PT_2/IN3  (
    .I(DCORENCCTLw),
    .O(\NlwInverterSignal_NET2482_MC.D2_PT_2/IN3 )
  );
  X_INV \NlwInverterBlock_NET2482_MC.D2_PT_2/IN7  (
    .I(\U1/U4/HE0statelastr ),
    .O(\NlwInverterSignal_NET2482_MC.D2_PT_2/IN7 )
  );
  X_INV \NlwInverterBlock_NET2482_MC.D2_PT_3/IN1  (
    .I(NET2482),
    .O(\NlwInverterSignal_NET2482_MC.D2_PT_3/IN1 )
  );
  X_INV \NlwInverterBlock_NET2482_MC.D2_PT_3/IN2  (
    .I(DCORIFGw),
    .O(\NlwInverterSignal_NET2482_MC.D2_PT_3/IN2 )
  );
  X_INV \NlwInverterBlock_NET2482_MC.D2_PT_3/IN3  (
    .I(DCORENCCTLw),
    .O(\NlwInverterSignal_NET2482_MC.D2_PT_3/IN3 )
  );
  X_INV \NlwInverterBlock_NET2482_MC.D2_PT_3/IN4  (
    .I(\U1/U4/RF0r ),
    .O(\NlwInverterSignal_NET2482_MC.D2_PT_3/IN4 )
  );
  X_INV \NlwInverterBlock_NET2482_MC.D2_PT_3/IN6  (
    .I(\U1/U4/HE0stater ),
    .O(\NlwInverterSignal_NET2482_MC.D2_PT_3/IN6 )
  );
  X_INV \NlwInverterBlock_DCORENCCTLw_MC.D1/IN0  (
    .I(\WR_II/UIM ),
    .O(\NlwInverterSignal_DCORENCCTLw_MC.D1/IN0 )
  );
  X_INV \NlwInverterBlock_DCORENCCTLw_MC.D1/IN3  (
    .I(U2_ADDR_reg[4]),
    .O(\NlwInverterSignal_DCORENCCTLw_MC.D1/IN3 )
  );
  X_INV \NlwInverterBlock_DCORENCCTLw_MC.D1/IN4  (
    .I(U2_ADDR_reg[5]),
    .O(\NlwInverterSignal_DCORENCCTLw_MC.D1/IN4 )
  );
  X_INV \NlwInverterBlock_DCORENCCTLw_MC.D1/IN5  (
    .I(U2_ADDR_reg[6]),
    .O(\NlwInverterSignal_DCORENCCTLw_MC.D1/IN5 )
  );
  X_INV \NlwInverterBlock_DCORENCCTLw_MC.D1/IN6  (
    .I(U2_ADDR_reg[7]),
    .O(\NlwInverterSignal_DCORENCCTLw_MC.D1/IN6 )
  );
  X_INV \NlwInverterBlock_DCORENCCTLw_MC.D1/IN7  (
    .I(U2_ADDR_reg[3]),
    .O(\NlwInverterSignal_DCORENCCTLw_MC.D1/IN7 )
  );
  X_INV \NlwInverterBlock_DCORENCCTLw_MC.D1/IN9  (
    .I(U2_ADDR_reg[2]),
    .O(\NlwInverterSignal_DCORENCCTLw_MC.D1/IN9 )
  );
  X_INV \NlwInverterBlock_U1/U4/RF0r_MC.D2_PT_1/IN1  (
    .I(DCORENCCTLw),
    .O(\NlwInverterSignal_U1/U4/RF0r_MC.D2_PT_1/IN1 )
  );
  X_INV \NlwInverterBlock_U1/U4/E0r_MC.D2_PT_1/IN1  (
    .I(DCORENCCTLw),
    .O(\NlwInverterSignal_U1/U4/E0r_MC.D2_PT_1/IN1 )
  );
  X_INV \NlwInverterBlock_U3/DCORIE<2>_MC.D2_PT_1/IN2  (
    .I(DCORIEw),
    .O(\NlwInverterSignal_U3/DCORIE<2>_MC.D2_PT_1/IN2 )
  );
  X_INV \NlwInverterBlock_NET2493_MC.D2_PT_0/IN0  (
    .I(\MSPReset_II/UIM ),
    .O(\NlwInverterSignal_NET2493_MC.D2_PT_0/IN0 )
  );
  X_INV \NlwInverterBlock_NET2493_MC.D2_PT_1/IN3  (
    .I(DCORENCCTLw),
    .O(\NlwInverterSignal_NET2493_MC.D2_PT_1/IN3 )
  );
  X_INV \NlwInverterBlock_NET2493_MC.D2_PT_2/IN1  (
    .I(NET2493),
    .O(\NlwInverterSignal_NET2493_MC.D2_PT_2/IN1 )
  );
  X_INV \NlwInverterBlock_NET2493_MC.D2_PT_2/IN2  (
    .I(DCORIFGw),
    .O(\NlwInverterSignal_NET2493_MC.D2_PT_2/IN2 )
  );
  X_INV \NlwInverterBlock_NET2493_MC.D2_PT_2/IN3  (
    .I(DCORENCCTLw),
    .O(\NlwInverterSignal_NET2493_MC.D2_PT_2/IN3 )
  );
  X_INV \NlwInverterBlock_NET2493_MC.D2_PT_2/IN7  (
    .I(\U1/U4/HE1statelastr ),
    .O(\NlwInverterSignal_NET2493_MC.D2_PT_2/IN7 )
  );
  X_INV \NlwInverterBlock_NET2493_MC.D2_PT_3/IN1  (
    .I(NET2493),
    .O(\NlwInverterSignal_NET2493_MC.D2_PT_3/IN1 )
  );
  X_INV \NlwInverterBlock_NET2493_MC.D2_PT_3/IN2  (
    .I(DCORIFGw),
    .O(\NlwInverterSignal_NET2493_MC.D2_PT_3/IN2 )
  );
  X_INV \NlwInverterBlock_NET2493_MC.D2_PT_3/IN3  (
    .I(DCORENCCTLw),
    .O(\NlwInverterSignal_NET2493_MC.D2_PT_3/IN3 )
  );
  X_INV \NlwInverterBlock_NET2493_MC.D2_PT_3/IN4  (
    .I(\U1/U4/RF1r ),
    .O(\NlwInverterSignal_NET2493_MC.D2_PT_3/IN4 )
  );
  X_INV \NlwInverterBlock_NET2493_MC.D2_PT_3/IN6  (
    .I(\U1/U4/HE1stater ),
    .O(\NlwInverterSignal_NET2493_MC.D2_PT_3/IN6 )
  );
  X_INV \NlwInverterBlock_U1/U4/RF1r_MC.D2_PT_1/IN1  (
    .I(DCORENCCTLw),
    .O(\NlwInverterSignal_U1/U4/RF1r_MC.D2_PT_1/IN1 )
  );
  X_INV \NlwInverterBlock_U1/U4/E1r_MC.D2_PT_1/IN1  (
    .I(DCORENCCTLw),
    .O(\NlwInverterSignal_U1/U4/E1r_MC.D2_PT_1/IN1 )
  );
  X_INV \NlwInverterBlock_U3/DCORIE<3>_MC.D2_PT_1/IN2  (
    .I(DCORIEw),
    .O(\NlwInverterSignal_U3/DCORIE<3>_MC.D2_PT_1/IN2 )
  );
  X_INV \NlwInverterBlock_NET2575_MC.D2_PT_0/IN2  (
    .I(\FLS0_II/UIM ),
    .O(\NlwInverterSignal_NET2575_MC.D2_PT_0/IN2 )
  );
  X_INV \NlwInverterBlock_NET2575_MC.D2_PT_1/IN0  (
    .I(\DIR0_II/UIM ),
    .O(\NlwInverterSignal_NET2575_MC.D2_PT_1/IN0 )
  );
  X_INV \NlwInverterBlock_NET2575_MC.D2_PT_1/IN2  (
    .I(\RLS0_II/UIM ),
    .O(\NlwInverterSignal_NET2575_MC.D2_PT_1/IN2 )
  );
  X_INV \NlwInverterBlock_NET2575_MC.D2_PT_2/IN2  (
    .I(\FLS1_II/UIM ),
    .O(\NlwInverterSignal_NET2575_MC.D2_PT_2/IN2 )
  );
  X_INV \NlwInverterBlock_NET2575_MC.D2_PT_3/IN0  (
    .I(\DIR1_II/UIM ),
    .O(\NlwInverterSignal_NET2575_MC.D2_PT_3/IN0 )
  );
  X_INV \NlwInverterBlock_NET2575_MC.D2_PT_3/IN2  (
    .I(\RLS1_II/UIM ),
    .O(\NlwInverterSignal_NET2575_MC.D2_PT_3/IN2 )
  );
  X_INV \NlwInverterBlock_NET2575_MC.D2_PT_4/IN1  (
    .I(\AD<4>_II/UIM ),
    .O(\NlwInverterSignal_NET2575_MC.D2_PT_4/IN1 )
  );
  X_INV \NlwInverterBlock_NET2575_MC.D2_PT_5/IN2  (
    .I(DCORIFGw),
    .O(\NlwInverterSignal_NET2575_MC.D2_PT_5/IN2 )
  );
  X_INV \NlwInverterBlock_U3/DCORIE<4>_MC.D2_PT_1/IN2  (
    .I(DCORIEw),
    .O(\NlwInverterSignal_U3/DCORIE<4>_MC.D2_PT_1/IN2 )
  );
  X_INV \NlwInverterBlock_NET2501_MC.D2_PT_1/IN4  (
    .I(DCORENCCTLw),
    .O(\NlwInverterSignal_NET2501_MC.D2_PT_1/IN4 )
  );
  X_INV \NlwInverterBlock_N_PZ_965_MC.D2_PT_0/IN1  (
    .I(NET2501),
    .O(\NlwInverterSignal_N_PZ_965_MC.D2_PT_0/IN1 )
  );
  X_INV \NlwInverterBlock_N_PZ_965_MC.D2_PT_0/IN2  (
    .I(DCORIFGw),
    .O(\NlwInverterSignal_N_PZ_965_MC.D2_PT_0/IN2 )
  );
  X_INV \NlwInverterBlock_N_PZ_965_MC.D2_PT_0/IN3  (
    .I(DCORENCCTLw),
    .O(\NlwInverterSignal_N_PZ_965_MC.D2_PT_0/IN3 )
  );
  X_INV \NlwInverterBlock_N_PZ_965_MC.D2_PT_0/IN5  (
    .I(\U1/U4/InEdge0r ),
    .O(\NlwInverterSignal_N_PZ_965_MC.D2_PT_0/IN5 )
  );
  X_INV \NlwInverterBlock_N_PZ_965_MC.D2_PT_1/IN0  (
    .I(\outDATA<6>\$WA1.UIM ),
    .O(\NlwInverterSignal_N_PZ_965_MC.D2_PT_1/IN0 )
  );
  X_INV \NlwInverterBlock_N_PZ_965_MC.D2_PT_1/IN1  (
    .I(NET2501),
    .O(\NlwInverterSignal_N_PZ_965_MC.D2_PT_1/IN1 )
  );
  X_INV \NlwInverterBlock_N_PZ_965_MC.D2_PT_1/IN2  (
    .I(DCORIFGw),
    .O(\NlwInverterSignal_N_PZ_965_MC.D2_PT_1/IN2 )
  );
  X_INV \NlwInverterBlock_N_PZ_965_MC.D2_PT_1/IN3  (
    .I(DCORENCCTLw),
    .O(\NlwInverterSignal_N_PZ_965_MC.D2_PT_1/IN3 )
  );
  X_INV \NlwInverterBlock_N_PZ_965_MC.D2_PT_1/IN4  (
    .I(\U1/U4/LatchEdge0r ),
    .O(\NlwInverterSignal_N_PZ_965_MC.D2_PT_1/IN4 )
  );
  X_INV \NlwInverterBlock_U1/U4/LatchEdge0r_MC.D2_PT_1/IN1  (
    .I(DCORENCCTLw),
    .O(\NlwInverterSignal_U1/U4/LatchEdge0r_MC.D2_PT_1/IN1 )
  );
  X_INV \NlwInverterBlock_U3/DCORIE<5>_MC.D2_PT_1/IN2  (
    .I(DCORIEw),
    .O(\NlwInverterSignal_U3/DCORIE<5>_MC.D2_PT_1/IN2 )
  );
  X_INV \NlwInverterBlock_NET2512_MC.D2_PT_0/IN4  (
    .I(DCORENCCTLw),
    .O(\NlwInverterSignal_NET2512_MC.D2_PT_0/IN4 )
  );
  X_INV \NlwInverterBlock_NET2512_MC.D2_PT_1/IN1  (
    .I(NET2512),
    .O(\NlwInverterSignal_NET2512_MC.D2_PT_1/IN1 )
  );
  X_INV \NlwInverterBlock_NET2512_MC.D2_PT_1/IN2  (
    .I(DCORIFGw),
    .O(\NlwInverterSignal_NET2512_MC.D2_PT_1/IN2 )
  );
  X_INV \NlwInverterBlock_NET2512_MC.D2_PT_1/IN3  (
    .I(DCORENCCTLw),
    .O(\NlwInverterSignal_NET2512_MC.D2_PT_1/IN3 )
  );
  X_INV \NlwInverterBlock_NET2512_MC.D2_PT_1/IN6  (
    .I(\U1/U4/InEdge1r ),
    .O(\NlwInverterSignal_NET2512_MC.D2_PT_1/IN6 )
  );
  X_INV \NlwInverterBlock_NET2512_MC.D2_PT_2/IN1  (
    .I(NET2512),
    .O(\NlwInverterSignal_NET2512_MC.D2_PT_2/IN1 )
  );
  X_INV \NlwInverterBlock_NET2512_MC.D2_PT_2/IN2  (
    .I(DCORIFGw),
    .O(\NlwInverterSignal_NET2512_MC.D2_PT_2/IN2 )
  );
  X_INV \NlwInverterBlock_NET2512_MC.D2_PT_2/IN3  (
    .I(DCORENCCTLw),
    .O(\NlwInverterSignal_NET2512_MC.D2_PT_2/IN3 )
  );
  X_INV \NlwInverterBlock_NET2512_MC.D2_PT_2/IN4  (
    .I(\GP_Motor1_0_II/UIM ),
    .O(\NlwInverterSignal_NET2512_MC.D2_PT_2/IN4 )
  );
  X_INV \NlwInverterBlock_NET2512_MC.D2_PT_2/IN5  (
    .I(\U1/U4/LatchEdge1r ),
    .O(\NlwInverterSignal_NET2512_MC.D2_PT_2/IN5 )
  );
  X_INV \NlwInverterBlock_U1/U4/LatchEdge1r_MC.D2_PT_1/IN1  (
    .I(DCORENCCTLw),
    .O(\NlwInverterSignal_U1/U4/LatchEdge1r_MC.D2_PT_1/IN1 )
  );
  X_INV \NlwInverterBlock_U3/DCORIE<6>_MC.D2_PT_1/IN2  (
    .I(DCORIEw),
    .O(\NlwInverterSignal_U3/DCORIE<6>_MC.D2_PT_1/IN2 )
  );
  X_INV \NlwInverterBlock_U3/DCORIE<7>_MC.D2_PT_1/IN2  (
    .I(DCORIEw),
    .O(\NlwInverterSignal_U3/DCORIE<7>_MC.D2_PT_1/IN2 )
  );
  X_INV \NlwInverterBlock_TP12_MC.D1/IN0  (
    .I(U11_U3_counterr[3]),
    .O(\NlwInverterSignal_TP12_MC.D1/IN0 )
  );
  X_INV \NlwInverterBlock_TP12_MC.D1/IN1  (
    .I(U11_U3_counterr[0]),
    .O(\NlwInverterSignal_TP12_MC.D1/IN1 )
  );
  X_INV \NlwInverterBlock_TP12_MC.D1/IN2  (
    .I(U11_U3_counterr[1]),
    .O(\NlwInverterSignal_TP12_MC.D1/IN2 )
  );
  X_INV \NlwInverterBlock_TP12_MC.D1/IN3  (
    .I(U11_U3_counterr[2]),
    .O(\NlwInverterSignal_TP12_MC.D1/IN3 )
  );
  X_INV \NlwInverterBlock_TP12_MC.D1/IN4  (
    .I(U11_U3_counterr[4]),
    .O(\NlwInverterSignal_TP12_MC.D1/IN4 )
  );
  X_INV \NlwInverterBlock_TP12_MC.D1/IN5  (
    .I(U11_U3_counterr[5]),
    .O(\NlwInverterSignal_TP12_MC.D1/IN5 )
  );
  X_INV \NlwInverterBlock_U11_U3_counterr<3>_MC.D/IN0  (
    .I(\U11_U3_counterr<3>_MC.D1 ),
    .O(\NlwInverterSignal_U11_U3_counterr<3>_MC.D/IN0 )
  );
  X_INV \NlwInverterBlock_U11_U3_counterr<3>_MC.D2_PT_1/IN0  (
    .I(U11_U3_counterr[3]),
    .O(\NlwInverterSignal_U11_U3_counterr<3>_MC.D2_PT_1/IN0 )
  );
  X_INV \NlwInverterBlock_U11_U3_counterr<3>_MC.D2_PT_1/IN1  (
    .I(\SCLreset_II/UIM ),
    .O(\NlwInverterSignal_U11_U3_counterr<3>_MC.D2_PT_1/IN1 )
  );
  X_INV \NlwInverterBlock_U11_U3_counterr<3>_MC.D2_PT_2/IN1  (
    .I(N_PZ_1071),
    .O(\NlwInverterSignal_U11_U3_counterr<3>_MC.D2_PT_2/IN1 )
  );
  X_INV \NlwInverterBlock_U11_U3_counterr<3>_MC.D2_PT_2/IN2  (
    .I(U11_Incdetect),
    .O(\NlwInverterSignal_U11_U3_counterr<3>_MC.D2_PT_2/IN2 )
  );
  X_INV \NlwInverterBlock_U11_U3_counterr<3>_MC.D2_PT_3/IN1  (
    .I(N_PZ_1071),
    .O(\NlwInverterSignal_U11_U3_counterr<3>_MC.D2_PT_3/IN1 )
  );
  X_INV \NlwInverterBlock_U11_U3_counterr<3>_MC.D2_PT_3/IN2  (
    .I(U11_Incdetect),
    .O(\NlwInverterSignal_U11_U3_counterr<3>_MC.D2_PT_3/IN2 )
  );
  X_INV \NlwInverterBlock_U11_U3_counterr<3>_MC.D2_PT_4/IN1  (
    .I(N_PZ_1071),
    .O(\NlwInverterSignal_U11_U3_counterr<3>_MC.D2_PT_4/IN1 )
  );
  X_INV \NlwInverterBlock_U11_U3_counterr<3>_MC.D2_PT_4/IN2  (
    .I(U11_Incdetect),
    .O(\NlwInverterSignal_U11_U3_counterr<3>_MC.D2_PT_4/IN2 )
  );
  X_INV \NlwInverterBlock_U11_U3_counterr<3>_MC.D2_PT_5/IN0  (
    .I(N_PZ_1071),
    .O(\NlwInverterSignal_U11_U3_counterr<3>_MC.D2_PT_5/IN0 )
  );
  X_INV \NlwInverterBlock_U11_U3_counterr<3>_MC.D2_PT_5/IN1  (
    .I(U11_Incdetect),
    .O(\NlwInverterSignal_U11_U3_counterr<3>_MC.D2_PT_5/IN1 )
  );
  X_INV \NlwInverterBlock_U11_U3_counterr<3>_MC.D2_PT_5/IN2  (
    .I(U11_SCLdetect),
    .O(\NlwInverterSignal_U11_U3_counterr<3>_MC.D2_PT_5/IN2 )
  );
  X_INV \NlwInverterBlock_U11_U3_counterr<3>_MC.D2_PT_6/IN3  (
    .I(N_PZ_1071),
    .O(\NlwInverterSignal_U11_U3_counterr<3>_MC.D2_PT_6/IN3 )
  );
  X_INV \NlwInverterBlock_U11_U3_counterr<3>_MC.D2_PT_6/IN4  (
    .I(U11_SCLdetect),
    .O(\NlwInverterSignal_U11_U3_counterr<3>_MC.D2_PT_6/IN4 )
  );
  X_INV \NlwInverterBlock_N_PZ_1071_MC.D2_PT_1/IN1  (
    .I(U11_Incdetect),
    .O(\NlwInverterSignal_N_PZ_1071_MC.D2_PT_1/IN1 )
  );
  X_INV \NlwInverterBlock_N_PZ_1071_MC.D2_PT_2/IN1  (
    .I(\SCLinc_II/UIM ),
    .O(\NlwInverterSignal_N_PZ_1071_MC.D2_PT_2/IN1 )
  );
  X_INV \NlwInverterBlock_U11_Incdetect_MC.D1/IN0  (
    .I(\SCLinc_II/UIM ),
    .O(\NlwInverterSignal_U11_Incdetect_MC.D1/IN0 )
  );
  X_INV \NlwInverterBlock_U11_ResetDetect_MC.D1/IN0  (
    .I(\SCLreset_II/UIM ),
    .O(\NlwInverterSignal_U11_ResetDetect_MC.D1/IN0 )
  );
  X_INV \NlwInverterBlock_U11_SCLdetect_MC.D1/IN0  (
    .I(\SCL_II/UIM ),
    .O(\NlwInverterSignal_U11_SCLdetect_MC.D1/IN0 )
  );
  X_INV \NlwInverterBlock_U11_U3_counterr<0>_MC.D2_PT_1/IN1  (
    .I(\SCLreset_II/UIM ),
    .O(\NlwInverterSignal_U11_U3_counterr<0>_MC.D2_PT_1/IN1 )
  );
  X_INV \NlwInverterBlock_U11_U3_counterr<0>_MC.D2_PT_2/IN1  (
    .I(\SCLreset_II/UIM ),
    .O(\NlwInverterSignal_U11_U3_counterr<0>_MC.D2_PT_2/IN1 )
  );
  X_INV \NlwInverterBlock_U11_U3_counterr<0>_MC.D2_PT_2/IN2  (
    .I(U11_Incdetect),
    .O(\NlwInverterSignal_U11_U3_counterr<0>_MC.D2_PT_2/IN2 )
  );
  X_INV \NlwInverterBlock_U11_U3_counterr<0>_MC.D2_PT_2/IN3  (
    .I(U11_SCLdetect),
    .O(\NlwInverterSignal_U11_U3_counterr<0>_MC.D2_PT_2/IN3 )
  );
  X_INV \NlwInverterBlock_U11_U3_counterr<0>_MC.D2_PT_3/IN0  (
    .I(U11_U3_counterr[0]),
    .O(\NlwInverterSignal_U11_U3_counterr<0>_MC.D2_PT_3/IN0 )
  );
  X_INV \NlwInverterBlock_U11_U3_counterr<0>_MC.D2_PT_3/IN1  (
    .I(\SCLreset_II/UIM ),
    .O(\NlwInverterSignal_U11_U3_counterr<0>_MC.D2_PT_3/IN1 )
  );
  X_INV \NlwInverterBlock_U11_U3_counterr<0>_MC.D2_PT_3/IN3  (
    .I(U11_SCLdetect),
    .O(\NlwInverterSignal_U11_U3_counterr<0>_MC.D2_PT_3/IN3 )
  );
  X_INV \NlwInverterBlock_U11_U3_counterr<0>_MC.D2_PT_4/IN0  (
    .I(\SCLreset_II/UIM ),
    .O(\NlwInverterSignal_U11_U3_counterr<0>_MC.D2_PT_4/IN0 )
  );
  X_INV \NlwInverterBlock_U11_U3_counterr<0>_MC.D2_PT_4/IN2  (
    .I(\SCLinc_II/UIM ),
    .O(\NlwInverterSignal_U11_U3_counterr<0>_MC.D2_PT_4/IN2 )
  );
  X_INV \NlwInverterBlock_U11_U3_counterr<0>_MC.D2_PT_5/IN0  (
    .I(\TP12_MC.UIM ),
    .O(\NlwInverterSignal_U11_U3_counterr<0>_MC.D2_PT_5/IN0 )
  );
  X_INV \NlwInverterBlock_U11_U3_counterr<0>_MC.D2_PT_5/IN1  (
    .I(U11_U3_counterr[0]),
    .O(\NlwInverterSignal_U11_U3_counterr<0>_MC.D2_PT_5/IN1 )
  );
  X_INV \NlwInverterBlock_U11_U3_counterr<0>_MC.D2_PT_5/IN2  (
    .I(\SCLreset_II/UIM ),
    .O(\NlwInverterSignal_U11_U3_counterr<0>_MC.D2_PT_5/IN2 )
  );
  X_INV \NlwInverterBlock_U11_U3_counterr<0>_MC.D2_PT_5/IN3  (
    .I(U11_Incdetect),
    .O(\NlwInverterSignal_U11_U3_counterr<0>_MC.D2_PT_5/IN3 )
  );
  X_INV \NlwInverterBlock_U11_U3_counterr<1>_MC.D2_PT_0/IN2  (
    .I(\SCLinc_II/UIM ),
    .O(\NlwInverterSignal_U11_U3_counterr<1>_MC.D2_PT_0/IN2 )
  );
  X_INV \NlwInverterBlock_U11_U3_counterr<1>_MC.D2_PT_1/IN1  (
    .I(N_PZ_1071),
    .O(\NlwInverterSignal_U11_U3_counterr<1>_MC.D2_PT_1/IN1 )
  );
  X_INV \NlwInverterBlock_U11_U3_counterr<1>_MC.D2_PT_1/IN3  (
    .I(U11_SCLdetect),
    .O(\NlwInverterSignal_U11_U3_counterr<1>_MC.D2_PT_1/IN3 )
  );
  X_INV \NlwInverterBlock_U11_U3_counterr<1>_MC.D2_PT_2/IN0  (
    .I(U11_U3_counterr[0]),
    .O(\NlwInverterSignal_U11_U3_counterr<1>_MC.D2_PT_2/IN0 )
  );
  X_INV \NlwInverterBlock_U11_U3_counterr<1>_MC.D2_PT_2/IN1  (
    .I(N_PZ_1071),
    .O(\NlwInverterSignal_U11_U3_counterr<1>_MC.D2_PT_2/IN1 )
  );
  X_INV \NlwInverterBlock_U11_U3_counterr<1>_MC.D2_PT_2/IN2  (
    .I(U11_Incdetect),
    .O(\NlwInverterSignal_U11_U3_counterr<1>_MC.D2_PT_2/IN2 )
  );
  X_INV \NlwInverterBlock_U11_U3_counterr<2>_MC.D2_PT_1/IN2  (
    .I(N_PZ_1071),
    .O(\NlwInverterSignal_U11_U3_counterr<2>_MC.D2_PT_1/IN2 )
  );
  X_INV \NlwInverterBlock_U11_U3_counterr<2>_MC.D2_PT_1/IN4  (
    .I(U11_SCLdetect),
    .O(\NlwInverterSignal_U11_U3_counterr<2>_MC.D2_PT_1/IN4 )
  );
  X_INV \NlwInverterBlock_U11_U3_counterr<2>_MC.D2_PT_2/IN0  (
    .I(U11_U3_counterr[0]),
    .O(\NlwInverterSignal_U11_U3_counterr<2>_MC.D2_PT_2/IN0 )
  );
  X_INV \NlwInverterBlock_U11_U3_counterr<2>_MC.D2_PT_2/IN1  (
    .I(U11_U3_counterr[1]),
    .O(\NlwInverterSignal_U11_U3_counterr<2>_MC.D2_PT_2/IN1 )
  );
  X_INV \NlwInverterBlock_U11_U3_counterr<2>_MC.D2_PT_2/IN2  (
    .I(N_PZ_1071),
    .O(\NlwInverterSignal_U11_U3_counterr<2>_MC.D2_PT_2/IN2 )
  );
  X_INV \NlwInverterBlock_U11_U3_counterr<2>_MC.D2_PT_2/IN3  (
    .I(U11_Incdetect),
    .O(\NlwInverterSignal_U11_U3_counterr<2>_MC.D2_PT_2/IN3 )
  );
  X_INV \NlwInverterBlock_U11_U3_counterr<4>_MC.D2_PT_1/IN0  (
    .I(N_PZ_1071),
    .O(\NlwInverterSignal_U11_U3_counterr<4>_MC.D2_PT_1/IN0 )
  );
  X_INV \NlwInverterBlock_U11_U3_counterr<4>_MC.D2_PT_1/IN1  (
    .I(N_PZ_1145),
    .O(\NlwInverterSignal_U11_U3_counterr<4>_MC.D2_PT_1/IN1 )
  );
  X_INV \NlwInverterBlock_U11_U3_counterr<4>_MC.D2_PT_2/IN0  (
    .I(U11_U3_counterr[2]),
    .O(\NlwInverterSignal_U11_U3_counterr<4>_MC.D2_PT_2/IN0 )
  );
  X_INV \NlwInverterBlock_U11_U3_counterr<4>_MC.D2_PT_2/IN1  (
    .I(N_PZ_1071),
    .O(\NlwInverterSignal_U11_U3_counterr<4>_MC.D2_PT_2/IN1 )
  );
  X_INV \NlwInverterBlock_U11_U3_counterr<4>_MC.D2_PT_2/IN2  (
    .I(U11_Incdetect),
    .O(\NlwInverterSignal_U11_U3_counterr<4>_MC.D2_PT_2/IN2 )
  );
  X_INV \NlwInverterBlock_U11_U3_counterr<4>_MC.D2_PT_2/IN3  (
    .I(N_PZ_1145),
    .O(\NlwInverterSignal_U11_U3_counterr<4>_MC.D2_PT_2/IN3 )
  );
  X_INV \NlwInverterBlock_N_PZ_1145_MC.D2_PT_0/IN1  (
    .I(U11_Incdetect),
    .O(\NlwInverterSignal_N_PZ_1145_MC.D2_PT_0/IN1 )
  );
  X_INV \NlwInverterBlock_N_PZ_1145_MC.D2_PT_1/IN1  (
    .I(U11_Incdetect),
    .O(\NlwInverterSignal_N_PZ_1145_MC.D2_PT_1/IN1 )
  );
  X_INV \NlwInverterBlock_N_PZ_1145_MC.D2_PT_2/IN1  (
    .I(U11_Incdetect),
    .O(\NlwInverterSignal_N_PZ_1145_MC.D2_PT_2/IN1 )
  );
  X_INV \NlwInverterBlock_N_PZ_1145_MC.D2_PT_3/IN0  (
    .I(U11_U3_counterr[3]),
    .O(\NlwInverterSignal_N_PZ_1145_MC.D2_PT_3/IN0 )
  );
  X_INV \NlwInverterBlock_N_PZ_1145_MC.D2_PT_3/IN1  (
    .I(U11_U3_counterr[2]),
    .O(\NlwInverterSignal_N_PZ_1145_MC.D2_PT_3/IN1 )
  );
  X_INV \NlwInverterBlock_N_PZ_1145_MC.D2_PT_3/IN2  (
    .I(U11_SCLdetect),
    .O(\NlwInverterSignal_N_PZ_1145_MC.D2_PT_3/IN2 )
  );
  X_INV \NlwInverterBlock_N_PZ_1125_MC.D2_PT_1/IN3  (
    .I(U11_SCLdetect),
    .O(\NlwInverterSignal_N_PZ_1125_MC.D2_PT_1/IN3 )
  );
  X_INV \NlwInverterBlock_U11_U3_counterr<5>_MC.D2_PT_1/IN1  (
    .I(N_PZ_1071),
    .O(\NlwInverterSignal_U11_U3_counterr<5>_MC.D2_PT_1/IN1 )
  );
  X_INV \NlwInverterBlock_U11_U3_counterr<5>_MC.D2_PT_1/IN2  (
    .I(N_PZ_1145),
    .O(\NlwInverterSignal_U11_U3_counterr<5>_MC.D2_PT_1/IN2 )
  );
  X_INV \NlwInverterBlock_U11_U3_counterr<5>_MC.D2_PT_2/IN0  (
    .I(U11_U3_counterr[2]),
    .O(\NlwInverterSignal_U11_U3_counterr<5>_MC.D2_PT_2/IN0 )
  );
  X_INV \NlwInverterBlock_U11_U3_counterr<5>_MC.D2_PT_2/IN1  (
    .I(U11_U3_counterr[4]),
    .O(\NlwInverterSignal_U11_U3_counterr<5>_MC.D2_PT_2/IN1 )
  );
  X_INV \NlwInverterBlock_U11_U3_counterr<5>_MC.D2_PT_2/IN2  (
    .I(N_PZ_1071),
    .O(\NlwInverterSignal_U11_U3_counterr<5>_MC.D2_PT_2/IN2 )
  );
  X_INV \NlwInverterBlock_U11_U3_counterr<5>_MC.D2_PT_2/IN3  (
    .I(U11_Incdetect),
    .O(\NlwInverterSignal_U11_U3_counterr<5>_MC.D2_PT_2/IN3 )
  );
  X_INV \NlwInverterBlock_U11_U3_counterr<5>_MC.D2_PT_2/IN4  (
    .I(N_PZ_1145),
    .O(\NlwInverterSignal_U11_U3_counterr<5>_MC.D2_PT_2/IN4 )
  );
  X_INV \NlwInverterBlock_U11_U3_counterr<5>_MC.D2_PT_3/IN0  (
    .I(U11_U3_counterr[5]),
    .O(\NlwInverterSignal_U11_U3_counterr<5>_MC.D2_PT_3/IN0 )
  );
  X_INV \NlwInverterBlock_U11_U3_counterr<5>_MC.D2_PT_3/IN1  (
    .I(N_PZ_1071),
    .O(\NlwInverterSignal_U11_U3_counterr<5>_MC.D2_PT_3/IN1 )
  );
  X_INV \NlwInverterBlock_U11_U3_counterr<5>_MC.D2_PT_3/IN2  (
    .I(U11_Incdetect),
    .O(\NlwInverterSignal_U11_U3_counterr<5>_MC.D2_PT_3/IN2 )
  );
  X_INV \NlwInverterBlock_U11_U3_counterr<5>_MC.D2_PT_3/IN3  (
    .I(N_PZ_1145),
    .O(\NlwInverterSignal_U11_U3_counterr<5>_MC.D2_PT_3/IN3 )
  );
  X_INV \NlwInverterBlock_LED1_MC.D/IN0  (
    .I(\LED1_MC.D1 ),
    .O(\NlwInverterSignal_LED1_MC.D/IN0 )
  );
  X_INV \NlwInverterBlock_LED1_MC.D1/IN1  (
    .I(\U9/MISCr [0]),
    .O(\NlwInverterSignal_LED1_MC.D1/IN1 )
  );
  X_INV \NlwInverterBlock_LED2_MC.D/IN0  (
    .I(\LED2_MC.D1 ),
    .O(\NlwInverterSignal_LED2_MC.D/IN0 )
  );
  X_INV \NlwInverterBlock_LED2_MC.D1/IN1  (
    .I(\U9/MISCr [1]),
    .O(\NlwInverterSignal_LED2_MC.D1/IN1 )
  );
  X_INV \NlwInverterBlock_LED3_MC.D/IN0  (
    .I(\LED3_MC.D1 ),
    .O(\NlwInverterSignal_LED3_MC.D/IN0 )
  );
  X_INV \NlwInverterBlock_LED3_MC.D1/IN1  (
    .I(\U9/MISCr [2]),
    .O(\NlwInverterSignal_LED3_MC.D1/IN1 )
  );
  X_INV \NlwInverterBlock_LED4_MC.D/IN0  (
    .I(\LED4_MC.D1 ),
    .O(\NlwInverterSignal_LED4_MC.D/IN0 )
  );
  X_INV \NlwInverterBlock_LED4_MC.D1/IN1  (
    .I(\U9/MISCr [3]),
    .O(\NlwInverterSignal_LED4_MC.D1/IN1 )
  );
  X_INV \NlwInverterBlock_LED5_MC.D/IN0  (
    .I(\LED5_MC.D1 ),
    .O(\NlwInverterSignal_LED5_MC.D/IN0 )
  );
  X_INV \NlwInverterBlock_LED5_MC.D1/IN1  (
    .I(\U9/MISCr [4]),
    .O(\NlwInverterSignal_LED5_MC.D1/IN1 )
  );
  X_INV \NlwInverterBlock_MTRpwrn_MC.D/IN0  (
    .I(\MTRpwrn_MC.D1 ),
    .O(\NlwInverterSignal_MTRpwrn_MC.D/IN0 )
  );
  X_INV \NlwInverterBlock_PAH0_MC.D1/IN0  (
    .I(\Brake0_II/UIM ),
    .O(\NlwInverterSignal_PAH0_MC.D1/IN0 )
  );
  X_INV \NlwInverterBlock_PAH0_MC.D1/IN1  (
    .I(\DIR0_II/UIM ),
    .O(\NlwInverterSignal_PAH0_MC.D1/IN1 )
  );
  X_INV \NlwInverterBlock_PAH0_MC.D1/IN3  (
    .I(NET3248),
    .O(\NlwInverterSignal_PAH0_MC.D1/IN3 )
  );
  X_INV \NlwInverterBlock_NET3248_MC.D2_PT_0/IN0  (
    .I(\Brake0_II/UIM ),
    .O(\NlwInverterSignal_NET3248_MC.D2_PT_0/IN0 )
  );
  X_INV \NlwInverterBlock_NET3248_MC.D2_PT_1/IN2  (
    .I(\FLS0_II/UIM ),
    .O(\NlwInverterSignal_NET3248_MC.D2_PT_1/IN2 )
  );
  X_INV \NlwInverterBlock_NET3248_MC.D2_PT_2/IN0  (
    .I(\DIR0_II/UIM ),
    .O(\NlwInverterSignal_NET3248_MC.D2_PT_2/IN0 )
  );
  X_INV \NlwInverterBlock_NET3248_MC.D2_PT_2/IN2  (
    .I(\RLS0_II/UIM ),
    .O(\NlwInverterSignal_NET3248_MC.D2_PT_2/IN2 )
  );
  X_INV \NlwInverterBlock_PAH1_MC.D1/IN0  (
    .I(\Brake1_II/UIM ),
    .O(\NlwInverterSignal_PAH1_MC.D1/IN0 )
  );
  X_INV \NlwInverterBlock_PAH1_MC.D1/IN1  (
    .I(\DIR1_II/UIM ),
    .O(\NlwInverterSignal_PAH1_MC.D1/IN1 )
  );
  X_INV \NlwInverterBlock_PAH1_MC.D1/IN3  (
    .I(NET3253),
    .O(\NlwInverterSignal_PAH1_MC.D1/IN3 )
  );
  X_INV \NlwInverterBlock_NET3253_MC.D2_PT_0/IN0  (
    .I(\Brake1_II/UIM ),
    .O(\NlwInverterSignal_NET3253_MC.D2_PT_0/IN0 )
  );
  X_INV \NlwInverterBlock_NET3253_MC.D2_PT_1/IN2  (
    .I(\FLS1_II/UIM ),
    .O(\NlwInverterSignal_NET3253_MC.D2_PT_1/IN2 )
  );
  X_INV \NlwInverterBlock_NET3253_MC.D2_PT_2/IN0  (
    .I(\DIR1_II/UIM ),
    .O(\NlwInverterSignal_NET3253_MC.D2_PT_2/IN0 )
  );
  X_INV \NlwInverterBlock_NET3253_MC.D2_PT_2/IN2  (
    .I(\RLS1_II/UIM ),
    .O(\NlwInverterSignal_NET3253_MC.D2_PT_2/IN2 )
  );
  X_INV \NlwInverterBlock_PAL0_MC.D2_PT_1/IN0  (
    .I(\Brake0_II/UIM ),
    .O(\NlwInverterSignal_PAL0_MC.D2_PT_1/IN0 )
  );
  X_INV \NlwInverterBlock_PAL0_MC.D2_PT_1/IN2  (
    .I(\PWM1_II/UIM ),
    .O(\NlwInverterSignal_PAL0_MC.D2_PT_1/IN2 )
  );
  X_INV \NlwInverterBlock_PAL0_MC.D2_PT_1/IN3  (
    .I(NET3248),
    .O(\NlwInverterSignal_PAL0_MC.D2_PT_1/IN3 )
  );
  X_INV \NlwInverterBlock_PAL1_MC.D2_PT_1/IN0  (
    .I(\Brake1_II/UIM ),
    .O(\NlwInverterSignal_PAL1_MC.D2_PT_1/IN0 )
  );
  X_INV \NlwInverterBlock_PAL1_MC.D2_PT_1/IN2  (
    .I(\PWM2_II/UIM ),
    .O(\NlwInverterSignal_PAL1_MC.D2_PT_1/IN2 )
  );
  X_INV \NlwInverterBlock_PAL1_MC.D2_PT_1/IN3  (
    .I(NET3253),
    .O(\NlwInverterSignal_PAL1_MC.D2_PT_1/IN3 )
  );
  X_INV \NlwInverterBlock_PBH0_MC.D1/IN0  (
    .I(\Brake0_II/UIM ),
    .O(\NlwInverterSignal_PBH0_MC.D1/IN0 )
  );
  X_INV \NlwInverterBlock_PBH0_MC.D1/IN3  (
    .I(NET3248),
    .O(\NlwInverterSignal_PBH0_MC.D1/IN3 )
  );
  X_INV \NlwInverterBlock_PBH1_MC.D1/IN0  (
    .I(\Brake1_II/UIM ),
    .O(\NlwInverterSignal_PBH1_MC.D1/IN0 )
  );
  X_INV \NlwInverterBlock_PBH1_MC.D1/IN3  (
    .I(NET3253),
    .O(\NlwInverterSignal_PBH1_MC.D1/IN3 )
  );
  X_INV \NlwInverterBlock_PBL0_MC.D2_PT_1/IN0  (
    .I(\Brake0_II/UIM ),
    .O(\NlwInverterSignal_PBL0_MC.D2_PT_1/IN0 )
  );
  X_INV \NlwInverterBlock_PBL0_MC.D2_PT_1/IN1  (
    .I(\DIR0_II/UIM ),
    .O(\NlwInverterSignal_PBL0_MC.D2_PT_1/IN1 )
  );
  X_INV \NlwInverterBlock_PBL0_MC.D2_PT_1/IN2  (
    .I(\PWM1_II/UIM ),
    .O(\NlwInverterSignal_PBL0_MC.D2_PT_1/IN2 )
  );
  X_INV \NlwInverterBlock_PBL0_MC.D2_PT_1/IN3  (
    .I(NET3248),
    .O(\NlwInverterSignal_PBL0_MC.D2_PT_1/IN3 )
  );
  X_INV \NlwInverterBlock_PBL1_MC.D2_PT_1/IN0  (
    .I(\Brake1_II/UIM ),
    .O(\NlwInverterSignal_PBL1_MC.D2_PT_1/IN0 )
  );
  X_INV \NlwInverterBlock_PBL1_MC.D2_PT_1/IN1  (
    .I(\DIR1_II/UIM ),
    .O(\NlwInverterSignal_PBL1_MC.D2_PT_1/IN1 )
  );
  X_INV \NlwInverterBlock_PBL1_MC.D2_PT_1/IN2  (
    .I(\PWM2_II/UIM ),
    .O(\NlwInverterSignal_PBL1_MC.D2_PT_1/IN2 )
  );
  X_INV \NlwInverterBlock_PBL1_MC.D2_PT_1/IN3  (
    .I(NET3253),
    .O(\NlwInverterSignal_PBL1_MC.D2_PT_1/IN3 )
  );
  X_INV \NlwInverterBlock_PresEn_MC.D/IN0  (
    .I(\PresEn_MC.D1 ),
    .O(\NlwInverterSignal_PresEn_MC.D/IN0 )
  );
  X_INV \NlwInverterBlock_DCORSENSORw_MC.D1/IN0  (
    .I(\WR_II/UIM ),
    .O(\NlwInverterSignal_DCORSENSORw_MC.D1/IN0 )
  );
  X_INV \NlwInverterBlock_DCORSENSORw_MC.D1/IN2  (
    .I(U2_ADDR_reg[0]),
    .O(\NlwInverterSignal_DCORSENSORw_MC.D1/IN2 )
  );
  X_INV \NlwInverterBlock_DCORSENSORw_MC.D1/IN3  (
    .I(U2_ADDR_reg[4]),
    .O(\NlwInverterSignal_DCORSENSORw_MC.D1/IN3 )
  );
  X_INV \NlwInverterBlock_DCORSENSORw_MC.D1/IN4  (
    .I(U2_ADDR_reg[5]),
    .O(\NlwInverterSignal_DCORSENSORw_MC.D1/IN4 )
  );
  X_INV \NlwInverterBlock_DCORSENSORw_MC.D1/IN5  (
    .I(U2_ADDR_reg[6]),
    .O(\NlwInverterSignal_DCORSENSORw_MC.D1/IN5 )
  );
  X_INV \NlwInverterBlock_DCORSENSORw_MC.D1/IN6  (
    .I(U2_ADDR_reg[7]),
    .O(\NlwInverterSignal_DCORSENSORw_MC.D1/IN6 )
  );
  X_INV \NlwInverterBlock_DCORSENSORw_MC.D1/IN8  (
    .I(U2_ADDR_reg[1]),
    .O(\NlwInverterSignal_DCORSENSORw_MC.D1/IN8 )
  );
  X_INV \NlwInverterBlock_TP11_MC.D/IN0  (
    .I(\TP11_MC.D1 ),
    .O(\NlwInverterSignal_TP11_MC.D/IN0 )
  );
  X_INV \NlwInverterBlock_TmpEn_MC.D/IN0  (
    .I(\TmpEn_MC.D1 ),
    .O(\NlwInverterSignal_TmpEn_MC.D/IN0 )
  );
  X_INV \NlwInverterBlock_DCORI2CCNTr_MC.D1/IN1  (
    .I(\RD_II/UIM ),
    .O(\NlwInverterSignal_DCORI2CCNTr_MC.D1/IN1 )
  );
  X_INV \NlwInverterBlock_DCORI2CCNTr_MC.D1/IN2  (
    .I(U2_ADDR_reg[0]),
    .O(\NlwInverterSignal_DCORI2CCNTr_MC.D1/IN2 )
  );
  X_INV \NlwInverterBlock_DCORI2CCNTr_MC.D1/IN3  (
    .I(U2_ADDR_reg[4]),
    .O(\NlwInverterSignal_DCORI2CCNTr_MC.D1/IN3 )
  );
  X_INV \NlwInverterBlock_DCORI2CCNTr_MC.D1/IN4  (
    .I(U2_ADDR_reg[5]),
    .O(\NlwInverterSignal_DCORI2CCNTr_MC.D1/IN4 )
  );
  X_INV \NlwInverterBlock_DCORI2CCNTr_MC.D1/IN5  (
    .I(U2_ADDR_reg[6]),
    .O(\NlwInverterSignal_DCORI2CCNTr_MC.D1/IN5 )
  );
  X_INV \NlwInverterBlock_DCORI2CCNTr_MC.D1/IN6  (
    .I(U2_ADDR_reg[7]),
    .O(\NlwInverterSignal_DCORI2CCNTr_MC.D1/IN6 )
  );
  X_INV \NlwInverterBlock_DCORI2CCNTr_MC.D1/IN7  (
    .I(U2_ADDR_reg[3]),
    .O(\NlwInverterSignal_DCORI2CCNTr_MC.D1/IN7 )
  );
  X_INV \NlwInverterBlock_DCORI2CCNTr_MC.D1/IN8  (
    .I(U2_ADDR_reg[1]),
    .O(\NlwInverterSignal_DCORI2CCNTr_MC.D1/IN8 )
  );
  X_INV \NlwInverterBlock_DCORI2CCNTr_MC.D1/IN9  (
    .I(U2_ADDR_reg[2]),
    .O(\NlwInverterSignal_DCORI2CCNTr_MC.D1/IN9 )
  );
  X_INV \NlwInverterBlock_DCORCONFIGr_MC.D1/IN1  (
    .I(\RD_II/UIM ),
    .O(\NlwInverterSignal_DCORCONFIGr_MC.D1/IN1 )
  );
  X_INV \NlwInverterBlock_DCORCONFIGr_MC.D1/IN3  (
    .I(U2_ADDR_reg[4]),
    .O(\NlwInverterSignal_DCORCONFIGr_MC.D1/IN3 )
  );
  X_INV \NlwInverterBlock_DCORCONFIGr_MC.D1/IN4  (
    .I(U2_ADDR_reg[5]),
    .O(\NlwInverterSignal_DCORCONFIGr_MC.D1/IN4 )
  );
  X_INV \NlwInverterBlock_DCORCONFIGr_MC.D1/IN5  (
    .I(U2_ADDR_reg[6]),
    .O(\NlwInverterSignal_DCORCONFIGr_MC.D1/IN5 )
  );
  X_INV \NlwInverterBlock_DCORCONFIGr_MC.D1/IN6  (
    .I(U2_ADDR_reg[7]),
    .O(\NlwInverterSignal_DCORCONFIGr_MC.D1/IN6 )
  );
  X_INV \NlwInverterBlock_DCORLIMITSr_MC.D1/IN1  (
    .I(\RD_II/UIM ),
    .O(\NlwInverterSignal_DCORLIMITSr_MC.D1/IN1 )
  );
  X_INV \NlwInverterBlock_DCORLIMITSr_MC.D1/IN2  (
    .I(U2_ADDR_reg[0]),
    .O(\NlwInverterSignal_DCORLIMITSr_MC.D1/IN2 )
  );
  X_INV \NlwInverterBlock_DCORLIMITSr_MC.D1/IN3  (
    .I(U2_ADDR_reg[4]),
    .O(\NlwInverterSignal_DCORLIMITSr_MC.D1/IN3 )
  );
  X_INV \NlwInverterBlock_DCORLIMITSr_MC.D1/IN4  (
    .I(U2_ADDR_reg[5]),
    .O(\NlwInverterSignal_DCORLIMITSr_MC.D1/IN4 )
  );
  X_INV \NlwInverterBlock_DCORLIMITSr_MC.D1/IN5  (
    .I(U2_ADDR_reg[6]),
    .O(\NlwInverterSignal_DCORLIMITSr_MC.D1/IN5 )
  );
  X_INV \NlwInverterBlock_DCORLIMITSr_MC.D1/IN6  (
    .I(U2_ADDR_reg[7]),
    .O(\NlwInverterSignal_DCORLIMITSr_MC.D1/IN6 )
  );
  X_INV \NlwInverterBlock_DCORLIMITSr_MC.D1/IN7  (
    .I(U2_ADDR_reg[3]),
    .O(\NlwInverterSignal_DCORLIMITSr_MC.D1/IN7 )
  );
  X_INV \NlwInverterBlock_DCORLIMITSr_MC.D1/IN9  (
    .I(U2_ADDR_reg[2]),
    .O(\NlwInverterSignal_DCORLIMITSr_MC.D1/IN9 )
  );
  X_INV \NlwInverterBlock_DCORENCPWRr_MC.D1/IN1  (
    .I(\RD_II/UIM ),
    .O(\NlwInverterSignal_DCORENCPWRr_MC.D1/IN1 )
  );
  X_INV \NlwInverterBlock_DCORENCPWRr_MC.D1/IN2  (
    .I(U2_ADDR_reg[0]),
    .O(\NlwInverterSignal_DCORENCPWRr_MC.D1/IN2 )
  );
  X_INV \NlwInverterBlock_DCORENCPWRr_MC.D1/IN3  (
    .I(U2_ADDR_reg[4]),
    .O(\NlwInverterSignal_DCORENCPWRr_MC.D1/IN3 )
  );
  X_INV \NlwInverterBlock_DCORENCPWRr_MC.D1/IN4  (
    .I(U2_ADDR_reg[5]),
    .O(\NlwInverterSignal_DCORENCPWRr_MC.D1/IN4 )
  );
  X_INV \NlwInverterBlock_DCORENCPWRr_MC.D1/IN5  (
    .I(U2_ADDR_reg[6]),
    .O(\NlwInverterSignal_DCORENCPWRr_MC.D1/IN5 )
  );
  X_INV \NlwInverterBlock_DCORENCPWRr_MC.D1/IN6  (
    .I(U2_ADDR_reg[7]),
    .O(\NlwInverterSignal_DCORENCPWRr_MC.D1/IN6 )
  );
  X_INV \NlwInverterBlock_outDATA<0>\$WA3.UIM_MC.D2_PT_1/IN0  (
    .I(NET2528),
    .O(\NlwInverterSignal_outDATA<0>\$WA3.UIM_MC.D2_PT_1/IN0 )
  );
  X_INV \NlwInverterBlock_DCORIFGr_MC.D1/IN1  (
    .I(\RD_II/UIM ),
    .O(\NlwInverterSignal_DCORIFGr_MC.D1/IN1 )
  );
  X_INV \NlwInverterBlock_DCORIFGr_MC.D1/IN3  (
    .I(U2_ADDR_reg[4]),
    .O(\NlwInverterSignal_DCORIFGr_MC.D1/IN3 )
  );
  X_INV \NlwInverterBlock_DCORIFGr_MC.D1/IN4  (
    .I(U2_ADDR_reg[5]),
    .O(\NlwInverterSignal_DCORIFGr_MC.D1/IN4 )
  );
  X_INV \NlwInverterBlock_DCORIFGr_MC.D1/IN5  (
    .I(U2_ADDR_reg[6]),
    .O(\NlwInverterSignal_DCORIFGr_MC.D1/IN5 )
  );
  X_INV \NlwInverterBlock_DCORIFGr_MC.D1/IN6  (
    .I(U2_ADDR_reg[7]),
    .O(\NlwInverterSignal_DCORIFGr_MC.D1/IN6 )
  );
  X_INV \NlwInverterBlock_DCORIFGr_MC.D1/IN7  (
    .I(U2_ADDR_reg[3]),
    .O(\NlwInverterSignal_DCORIFGr_MC.D1/IN7 )
  );
  X_INV \NlwInverterBlock_DCORIFGr_MC.D1/IN8  (
    .I(U2_ADDR_reg[1]),
    .O(\NlwInverterSignal_DCORIFGr_MC.D1/IN8 )
  );
  X_INV \NlwInverterBlock_DCORIFGr_MC.D1/IN9  (
    .I(U2_ADDR_reg[2]),
    .O(\NlwInverterSignal_DCORIFGr_MC.D1/IN9 )
  );
  X_INV \NlwInverterBlock_DCOR0THRESLOWr_MC.D1/IN1  (
    .I(\RD_II/UIM ),
    .O(\NlwInverterSignal_DCOR0THRESLOWr_MC.D1/IN1 )
  );
  X_INV \NlwInverterBlock_DCOR0THRESLOWr_MC.D1/IN2  (
    .I(U2_ADDR_reg[0]),
    .O(\NlwInverterSignal_DCOR0THRESLOWr_MC.D1/IN2 )
  );
  X_INV \NlwInverterBlock_DCOR0THRESLOWr_MC.D1/IN3  (
    .I(U2_ADDR_reg[4]),
    .O(\NlwInverterSignal_DCOR0THRESLOWr_MC.D1/IN3 )
  );
  X_INV \NlwInverterBlock_DCOR0THRESLOWr_MC.D1/IN4  (
    .I(U2_ADDR_reg[5]),
    .O(\NlwInverterSignal_DCOR0THRESLOWr_MC.D1/IN4 )
  );
  X_INV \NlwInverterBlock_DCOR0THRESLOWr_MC.D1/IN5  (
    .I(U2_ADDR_reg[6]),
    .O(\NlwInverterSignal_DCOR0THRESLOWr_MC.D1/IN5 )
  );
  X_INV \NlwInverterBlock_DCOR0THRESLOWr_MC.D1/IN6  (
    .I(U2_ADDR_reg[7]),
    .O(\NlwInverterSignal_DCOR0THRESLOWr_MC.D1/IN6 )
  );
  X_INV \NlwInverterBlock_DCOR0THRESLOWr_MC.D1/IN8  (
    .I(U2_ADDR_reg[1]),
    .O(\NlwInverterSignal_DCOR0THRESLOWr_MC.D1/IN8 )
  );
  X_INV \NlwInverterBlock_DCOR0THRESLOWr_MC.D1/IN9  (
    .I(U2_ADDR_reg[2]),
    .O(\NlwInverterSignal_DCOR0THRESLOWr_MC.D1/IN9 )
  );
  X_INV \NlwInverterBlock_outDATA<0>\$WA6.UIM_MC.D2_PT_1/IN0  (
    .I(DCOR0THRESLOWr),
    .O(\NlwInverterSignal_outDATA<0>\$WA6.UIM_MC.D2_PT_1/IN0 )
  );
  X_INV \NlwInverterBlock_outDATA<0>\$WA6.UIM_MC.D2_PT_2/IN0  (
    .I(DCOR0THRESLOWr),
    .O(\NlwInverterSignal_outDATA<0>\$WA6.UIM_MC.D2_PT_2/IN0 )
  );
  X_INV \NlwInverterBlock_outDATA<0>\$WA6.UIM_MC.D2_PT_2/IN1  (
    .I(DCOR0THRESHIGHr),
    .O(\NlwInverterSignal_outDATA<0>\$WA6.UIM_MC.D2_PT_2/IN1 )
  );
  X_INV \NlwInverterBlock_outDATA<0>\$WA6.UIM_MC.D2_PT_3/IN0  (
    .I(DCOR0THRESLOWr),
    .O(\NlwInverterSignal_outDATA<0>\$WA6.UIM_MC.D2_PT_3/IN0 )
  );
  X_INV \NlwInverterBlock_outDATA<0>\$WA6.UIM_MC.D2_PT_3/IN1  (
    .I(DCOR0THRESHIGHr),
    .O(\NlwInverterSignal_outDATA<0>\$WA6.UIM_MC.D2_PT_3/IN1 )
  );
  X_INV \NlwInverterBlock_outDATA<0>\$WA6.UIM_MC.D2_PT_3/IN2  (
    .I(DCOR1THRESLOWr),
    .O(\NlwInverterSignal_outDATA<0>\$WA6.UIM_MC.D2_PT_3/IN2 )
  );
  X_INV \NlwInverterBlock_U1/U4/Latch0r<0>_MC.D2_PT_1/IN1  (
    .I(N_PZ_965),
    .O(\NlwInverterSignal_U1/U4/Latch0r<0>_MC.D2_PT_1/IN1 )
  );
  X_INV \NlwInverterBlock_U1/Channel0<0>_MC.D2_PT_0/IN1  (
    .I(N_PZ_931),
    .O(\NlwInverterSignal_U1/Channel0<0>_MC.D2_PT_0/IN1 )
  );
  X_INV \NlwInverterBlock_U1/Channel0<0>_MC.D2_PT_1/IN1  (
    .I(\U1/Zero0 ),
    .O(\NlwInverterSignal_U1/Channel0<0>_MC.D2_PT_1/IN1 )
  );
  X_INV \NlwInverterBlock_U1/Channel0<0>_MC.D2_PT_1/IN4  (
    .I(\U1/U1/CurrState_Sreg0_FFD2 ),
    .O(\NlwInverterSignal_U1/Channel0<0>_MC.D2_PT_1/IN4 )
  );
  X_INV \NlwInverterBlock_U1/Channel0<0>_MC.D2_PT_1/IN5  (
    .I(\U1/U1/CurrState_Sreg0_FFD4 ),
    .O(\NlwInverterSignal_U1/Channel0<0>_MC.D2_PT_1/IN5 )
  );
  X_INV \NlwInverterBlock_U1/Channel0<0>_MC.D2_PT_2/IN1  (
    .I(\U1/Zero0 ),
    .O(\NlwInverterSignal_U1/Channel0<0>_MC.D2_PT_2/IN1 )
  );
  X_INV \NlwInverterBlock_U1/Channel0<0>_MC.D2_PT_2/IN2  (
    .I(\U1/U1/CurrState_Sreg0_FFD1 ),
    .O(\NlwInverterSignal_U1/Channel0<0>_MC.D2_PT_2/IN2 )
  );
  X_INV \NlwInverterBlock_U1/Channel0<0>_MC.D2_PT_2/IN4  (
    .I(\U1/U1/CurrState_Sreg0_FFD2 ),
    .O(\NlwInverterSignal_U1/Channel0<0>_MC.D2_PT_2/IN4 )
  );
  X_INV \NlwInverterBlock_U1/Zero0_MC.D2_PT_0/IN0  (
    .I(\MSPReset_II/UIM ),
    .O(\NlwInverterSignal_U1/Zero0_MC.D2_PT_0/IN0 )
  );
  X_INV \NlwInverterBlock_U1/Zero0_MC.D2_PT_1/IN0  (
    .I(N_PZ_931),
    .O(\NlwInverterSignal_U1/Zero0_MC.D2_PT_1/IN0 )
  );
  X_INV \NlwInverterBlock_U1/Zero0_MC.D2_PT_2/IN1  (
    .I(NET2482),
    .O(\NlwInverterSignal_U1/Zero0_MC.D2_PT_2/IN1 )
  );
  X_INV \NlwInverterBlock_U1/Zero0_MC.D2_PT_2/IN5  (
    .I(\U1/U4/HE0statelastr ),
    .O(\NlwInverterSignal_U1/Zero0_MC.D2_PT_2/IN5 )
  );
  X_INV \NlwInverterBlock_U1/Zero0_MC.D2_PT_2/IN6  (
    .I(N_PZ_964),
    .O(\NlwInverterSignal_U1/Zero0_MC.D2_PT_2/IN6 )
  );
  X_INV \NlwInverterBlock_U1/Zero0_MC.D2_PT_3/IN1  (
    .I(NET2482),
    .O(\NlwInverterSignal_U1/Zero0_MC.D2_PT_3/IN1 )
  );
  X_INV \NlwInverterBlock_U1/Zero0_MC.D2_PT_3/IN2  (
    .I(\U1/U4/RF0r ),
    .O(\NlwInverterSignal_U1/Zero0_MC.D2_PT_3/IN2 )
  );
  X_INV \NlwInverterBlock_U1/Zero0_MC.D2_PT_3/IN4  (
    .I(\U1/U4/HE0stater ),
    .O(\NlwInverterSignal_U1/Zero0_MC.D2_PT_3/IN4 )
  );
  X_INV \NlwInverterBlock_U1/Zero0_MC.D2_PT_3/IN6  (
    .I(N_PZ_964),
    .O(\NlwInverterSignal_U1/Zero0_MC.D2_PT_3/IN6 )
  );
  X_INV \NlwInverterBlock_N_PZ_931_MC.D1/IN1  (
    .I(\U1/Zero0 ),
    .O(\NlwInverterSignal_N_PZ_931_MC.D1/IN1 )
  );
  X_INV \NlwInverterBlock_U1/U1/CurrState_Sreg0_FFD1_MC.D2_PT_0/IN3  (
    .I(\U1/U1/CurrState_Sreg0_FFD4 ),
    .O(\NlwInverterSignal_U1/U1/CurrState_Sreg0_FFD1_MC.D2_PT_0/IN3 )
  );
  X_INV \NlwInverterBlock_U1/U1/CurrState_Sreg0_FFD1_MC.D2_PT_1/IN3  (
    .I(\U1/U1/CurrState_Sreg0_FFD3 ),
    .O(\NlwInverterSignal_U1/U1/CurrState_Sreg0_FFD1_MC.D2_PT_1/IN3 )
  );
  X_INV \NlwInverterBlock_U1/U1/CurrState_Sreg0_FFD1_MC.D2_PT_1/IN4  (
    .I(\U1/U1/CurrState_Sreg0_FFD4 ),
    .O(\NlwInverterSignal_U1/U1/CurrState_Sreg0_FFD1_MC.D2_PT_1/IN4 )
  );
  X_INV \NlwInverterBlock_U1/U1/CurrState_Sreg0_FFD1_MC.D2_PT_2/IN1  (
    .I(\PhaseA_Encoder0_II/UIM ),
    .O(\NlwInverterSignal_U1/U1/CurrState_Sreg0_FFD1_MC.D2_PT_2/IN1 )
  );
  X_INV \NlwInverterBlock_U1/U1/CurrState_Sreg0_FFD1_MC.D2_PT_2/IN3  (
    .I(\U1/U1/CurrState_Sreg0_FFD3 ),
    .O(\NlwInverterSignal_U1/U1/CurrState_Sreg0_FFD1_MC.D2_PT_2/IN3 )
  );
  X_INV \NlwInverterBlock_U1/U1/CurrState_Sreg0_FFD1_MC.D2_PT_2/IN4  (
    .I(\U1/U1/CurrState_Sreg0_FFD2 ),
    .O(\NlwInverterSignal_U1/U1/CurrState_Sreg0_FFD1_MC.D2_PT_2/IN4 )
  );
  X_INV \NlwInverterBlock_U1/U1/CurrState_Sreg0_FFD1_MC.D2_PT_2/IN5  (
    .I(\U1/U1/CurrState_Sreg0_FFD4 ),
    .O(\NlwInverterSignal_U1/U1/CurrState_Sreg0_FFD1_MC.D2_PT_2/IN5 )
  );
  X_INV \NlwInverterBlock_U1/U1/CurrState_Sreg0_FFD3_MC.D2_PT_0/IN1  (
    .I(\PhaseA_Encoder0_II/UIM ),
    .O(\NlwInverterSignal_U1/U1/CurrState_Sreg0_FFD3_MC.D2_PT_0/IN1 )
  );
  X_INV \NlwInverterBlock_U1/U1/CurrState_Sreg0_FFD3_MC.D2_PT_0/IN4  (
    .I(\U1/U1/CurrState_Sreg0_FFD4 ),
    .O(\NlwInverterSignal_U1/U1/CurrState_Sreg0_FFD3_MC.D2_PT_0/IN4 )
  );
  X_INV \NlwInverterBlock_U1/U1/CurrState_Sreg0_FFD3_MC.D2_PT_1/IN1  (
    .I(\U1/U1/CurrState_Sreg0_FFD1 ),
    .O(\NlwInverterSignal_U1/U1/CurrState_Sreg0_FFD3_MC.D2_PT_1/IN1 )
  );
  X_INV \NlwInverterBlock_U1/U1/CurrState_Sreg0_FFD3_MC.D2_PT_1/IN3  (
    .I(\U1/U1/CurrState_Sreg0_FFD2 ),
    .O(\NlwInverterSignal_U1/U1/CurrState_Sreg0_FFD3_MC.D2_PT_1/IN3 )
  );
  X_INV \NlwInverterBlock_U1/U1/CurrState_Sreg0_FFD3_MC.D2_PT_1/IN4  (
    .I(\U1/U1/CurrState_Sreg0_FFD4 ),
    .O(\NlwInverterSignal_U1/U1/CurrState_Sreg0_FFD3_MC.D2_PT_1/IN4 )
  );
  X_INV \NlwInverterBlock_U1/U1/CurrState_Sreg0_FFD3_MC.D2_PT_2/IN3  (
    .I(\U1/U1/CurrState_Sreg0_FFD1 ),
    .O(\NlwInverterSignal_U1/U1/CurrState_Sreg0_FFD3_MC.D2_PT_2/IN3 )
  );
  X_INV \NlwInverterBlock_U1/U1/CurrState_Sreg0_FFD3_MC.D2_PT_2/IN5  (
    .I(\U1/U1/CurrState_Sreg0_FFD4 ),
    .O(\NlwInverterSignal_U1/U1/CurrState_Sreg0_FFD3_MC.D2_PT_2/IN5 )
  );
  X_INV \NlwInverterBlock_U1/U1/CurrState_Sreg0_FFD3_MC.D2_PT_3/IN2  (
    .I(\PhaseB_Encoder0_II/UIM ),
    .O(\NlwInverterSignal_U1/U1/CurrState_Sreg0_FFD3_MC.D2_PT_3/IN2 )
  );
  X_INV \NlwInverterBlock_U1/U1/CurrState_Sreg0_FFD3_MC.D2_PT_3/IN5  (
    .I(\U1/U1/CurrState_Sreg0_FFD4 ),
    .O(\NlwInverterSignal_U1/U1/CurrState_Sreg0_FFD3_MC.D2_PT_3/IN5 )
  );
  X_INV \NlwInverterBlock_U1/U1/CurrState_Sreg0_FFD2_MC.D2_PT_0/IN4  (
    .I(\U1/U1/CurrState_Sreg0_FFD3 ),
    .O(\NlwInverterSignal_U1/U1/CurrState_Sreg0_FFD2_MC.D2_PT_0/IN4 )
  );
  X_INV \NlwInverterBlock_U1/U1/CurrState_Sreg0_FFD2_MC.D2_PT_0/IN5  (
    .I(\U1/U1/CurrState_Sreg0_FFD4 ),
    .O(\NlwInverterSignal_U1/U1/CurrState_Sreg0_FFD2_MC.D2_PT_0/IN5 )
  );
  X_INV \NlwInverterBlock_U1/U1/CurrState_Sreg0_FFD2_MC.D2_PT_1/IN3  (
    .I(\U1/U1/CurrState_Sreg0_FFD1 ),
    .O(\NlwInverterSignal_U1/U1/CurrState_Sreg0_FFD2_MC.D2_PT_1/IN3 )
  );
  X_INV \NlwInverterBlock_U1/U1/CurrState_Sreg0_FFD2_MC.D2_PT_1/IN5  (
    .I(\U1/U1/CurrState_Sreg0_FFD4 ),
    .O(\NlwInverterSignal_U1/U1/CurrState_Sreg0_FFD2_MC.D2_PT_1/IN5 )
  );
  X_INV \NlwInverterBlock_U1/U1/CurrState_Sreg0_FFD2_MC.D2_PT_2/IN2  (
    .I(\PhaseB_Encoder0_II/UIM ),
    .O(\NlwInverterSignal_U1/U1/CurrState_Sreg0_FFD2_MC.D2_PT_2/IN2 )
  );
  X_INV \NlwInverterBlock_U1/U1/CurrState_Sreg0_FFD2_MC.D2_PT_2/IN5  (
    .I(\U1/U1/CurrState_Sreg0_FFD4 ),
    .O(\NlwInverterSignal_U1/U1/CurrState_Sreg0_FFD2_MC.D2_PT_2/IN5 )
  );
  X_INV \NlwInverterBlock_U1/U1/CurrState_Sreg0_FFD2_MC.D2_PT_3/IN2  (
    .I(\PhaseB_Encoder0_II/UIM ),
    .O(\NlwInverterSignal_U1/U1/CurrState_Sreg0_FFD2_MC.D2_PT_3/IN2 )
  );
  X_INV \NlwInverterBlock_U1/U1/CurrState_Sreg0_FFD2_MC.D2_PT_3/IN3  (
    .I(\U1/U1/CurrState_Sreg0_FFD1 ),
    .O(\NlwInverterSignal_U1/U1/CurrState_Sreg0_FFD2_MC.D2_PT_3/IN3 )
  );
  X_INV \NlwInverterBlock_U1/U1/CurrState_Sreg0_FFD2_MC.D2_PT_3/IN4  (
    .I(\U1/U1/CurrState_Sreg0_FFD3 ),
    .O(\NlwInverterSignal_U1/U1/CurrState_Sreg0_FFD2_MC.D2_PT_3/IN4 )
  );
  X_INV \NlwInverterBlock_U1/U1/CurrState_Sreg0_FFD2_MC.D2_PT_3/IN5  (
    .I(\U1/U1/CurrState_Sreg0_FFD4 ),
    .O(\NlwInverterSignal_U1/U1/CurrState_Sreg0_FFD2_MC.D2_PT_3/IN5 )
  );
  X_INV \NlwInverterBlock_U1/U1/CurrState_Sreg0_FFD2_MC.D2_PT_4/IN5  (
    .I(\U1/U1/CurrState_Sreg0_FFD4 ),
    .O(\NlwInverterSignal_U1/U1/CurrState_Sreg0_FFD2_MC.D2_PT_4/IN5 )
  );
  X_INV \NlwInverterBlock_U1/U1/CurrState_Sreg0_FFD2_MC.D2_PT_5/IN2  (
    .I(\U1/U1/CurrState_Sreg0_FFD1 ),
    .O(\NlwInverterSignal_U1/U1/CurrState_Sreg0_FFD2_MC.D2_PT_5/IN2 )
  );
  X_INV \NlwInverterBlock_U1/U1/CurrState_Sreg0_FFD2_MC.D2_PT_5/IN3  (
    .I(\U1/U1/CurrState_Sreg0_FFD3 ),
    .O(\NlwInverterSignal_U1/U1/CurrState_Sreg0_FFD2_MC.D2_PT_5/IN3 )
  );
  X_INV \NlwInverterBlock_U1/U1/CurrState_Sreg0_FFD2_MC.D2_PT_5/IN5  (
    .I(\U1/U1/CurrState_Sreg0_FFD4 ),
    .O(\NlwInverterSignal_U1/U1/CurrState_Sreg0_FFD2_MC.D2_PT_5/IN5 )
  );
  X_INV \NlwInverterBlock_U1/U1/CurrState_Sreg0_FFD2_MC.D2_PT_6/IN1  (
    .I(\PhaseB_Encoder0_II/UIM ),
    .O(\NlwInverterSignal_U1/U1/CurrState_Sreg0_FFD2_MC.D2_PT_6/IN1 )
  );
  X_INV \NlwInverterBlock_U1/U1/CurrState_Sreg0_FFD2_MC.D2_PT_6/IN3  (
    .I(\U1/U1/CurrState_Sreg0_FFD3 ),
    .O(\NlwInverterSignal_U1/U1/CurrState_Sreg0_FFD2_MC.D2_PT_6/IN3 )
  );
  X_INV \NlwInverterBlock_U1/U1/CurrState_Sreg0_FFD2_MC.D2_PT_6/IN5  (
    .I(\U1/U1/CurrState_Sreg0_FFD4 ),
    .O(\NlwInverterSignal_U1/U1/CurrState_Sreg0_FFD2_MC.D2_PT_6/IN5 )
  );
  X_INV \NlwInverterBlock_U1/U1/CurrState_Sreg0_FFD2_MC.D2_PT_7/IN1  (
    .I(\PhaseB_Encoder0_II/UIM ),
    .O(\NlwInverterSignal_U1/U1/CurrState_Sreg0_FFD2_MC.D2_PT_7/IN1 )
  );
  X_INV \NlwInverterBlock_U1/U1/CurrState_Sreg0_FFD2_MC.D2_PT_7/IN2  (
    .I(\U1/U1/CurrState_Sreg0_FFD1 ),
    .O(\NlwInverterSignal_U1/U1/CurrState_Sreg0_FFD2_MC.D2_PT_7/IN2 )
  );
  X_INV \NlwInverterBlock_U1/U1/CurrState_Sreg0_FFD2_MC.D2_PT_7/IN5  (
    .I(\U1/U1/CurrState_Sreg0_FFD4 ),
    .O(\NlwInverterSignal_U1/U1/CurrState_Sreg0_FFD2_MC.D2_PT_7/IN5 )
  );
  X_INV \NlwInverterBlock_U1/U1/CurrState_Sreg0_FFD4_MC.D1/IN1  (
    .I(\PhaseA_Encoder0_II/UIM ),
    .O(\NlwInverterSignal_U1/U1/CurrState_Sreg0_FFD4_MC.D1/IN1 )
  );
  X_INV \NlwInverterBlock_U1/U1/CurrState_Sreg0_FFD4_MC.D1/IN2  (
    .I(\PhaseB_Encoder0_II/UIM ),
    .O(\NlwInverterSignal_U1/U1/CurrState_Sreg0_FFD4_MC.D1/IN2 )
  );
  X_INV \NlwInverterBlock_U1/U1/CurrState_Sreg0_FFD4_MC.D1/IN3  (
    .I(\U1/U1/CurrState_Sreg0_FFD1 ),
    .O(\NlwInverterSignal_U1/U1/CurrState_Sreg0_FFD4_MC.D1/IN3 )
  );
  X_INV \NlwInverterBlock_U1/U1/CurrState_Sreg0_FFD4_MC.D1/IN5  (
    .I(\U1/U1/CurrState_Sreg0_FFD2 ),
    .O(\NlwInverterSignal_U1/U1/CurrState_Sreg0_FFD4_MC.D1/IN5 )
  );
  X_INV \NlwInverterBlock_U1/U1/CurrState_Sreg0_FFD4_MC.D1/IN6  (
    .I(\U1/U1/CurrState_Sreg0_FFD4 ),
    .O(\NlwInverterSignal_U1/U1/CurrState_Sreg0_FFD4_MC.D1/IN6 )
  );
  X_INV \NlwInverterBlock_U1/U4/Latch0r<8>_MC.D2_PT_1/IN1  (
    .I(N_PZ_965),
    .O(\NlwInverterSignal_U1/U4/Latch0r<8>_MC.D2_PT_1/IN1 )
  );
  X_INV \NlwInverterBlock_U1/Channel0<8>_MC.D2_PT_0/IN0  (
    .I(N_PZ_931),
    .O(\NlwInverterSignal_U1/Channel0<8>_MC.D2_PT_0/IN0 )
  );
  X_INV \NlwInverterBlock_U1/Channel0<8>_MC.D2_PT_1/IN0  (
    .I(\U1/Channel0 [8]),
    .O(\NlwInverterSignal_U1/Channel0<8>_MC.D2_PT_1/IN0 )
  );
  X_INV \NlwInverterBlock_U1/Channel0<8>_MC.D2_PT_2/IN1  (
    .I(\U1/U2/location_Maddsub__n0000__n0075 [0]),
    .O(\NlwInverterSignal_U1/Channel0<8>_MC.D2_PT_2/IN1 )
  );
  X_INV \NlwInverterBlock_U1/Channel0<8>_MC.D2_PT_2/IN3  (
    .I(\U1/Channel0 [7]),
    .O(\NlwInverterSignal_U1/Channel0<8>_MC.D2_PT_2/IN3 )
  );
  X_INV \NlwInverterBlock_U1/Channel0<8>_MC.D2_PT_3/IN1  (
    .I(\U1/U2/location_Maddsub__n0000__n0075 [0]),
    .O(\NlwInverterSignal_U1/Channel0<8>_MC.D2_PT_3/IN1 )
  );
  X_INV \NlwInverterBlock_U1/Channel0<8>_MC.D2_PT_3/IN4  (
    .I(\U1/U2/location_Maddsub__n0000__n0067 [0]),
    .O(\NlwInverterSignal_U1/Channel0<8>_MC.D2_PT_3/IN4 )
  );
  X_INV \NlwInverterBlock_U1/Channel0<8>_MC.D2_PT_4/IN1  (
    .I(\U1/U2/location_Maddsub__n0000__n0075 [0]),
    .O(\NlwInverterSignal_U1/Channel0<8>_MC.D2_PT_4/IN1 )
  );
  X_INV \NlwInverterBlock_U1/Channel0<8>_MC.D2_PT_4/IN3  (
    .I(\U1/Channel0 [7]),
    .O(\NlwInverterSignal_U1/Channel0<8>_MC.D2_PT_4/IN3 )
  );
  X_INV \NlwInverterBlock_U1/Channel0<8>_MC.D2_PT_4/IN4  (
    .I(\U1/Channel0 [5]),
    .O(\NlwInverterSignal_U1/Channel0<8>_MC.D2_PT_4/IN4 )
  );
  X_INV \NlwInverterBlock_U1/Channel0<8>_MC.D2_PT_4/IN6  (
    .I(\U1/Channel0 [6]),
    .O(\NlwInverterSignal_U1/Channel0<8>_MC.D2_PT_4/IN6 )
  );
  X_INV \NlwInverterBlock_U1/Channel0<8>_MC.D2_PT_5/IN0  (
    .I(\U1/Channel0 [8]),
    .O(\NlwInverterSignal_U1/Channel0<8>_MC.D2_PT_5/IN0 )
  );
  X_INV \NlwInverterBlock_U1/Channel0<8>_MC.D2_PT_5/IN5  (
    .I(\U1/U2/location_Maddsub__n0000__n0067 [0]),
    .O(\NlwInverterSignal_U1/Channel0<8>_MC.D2_PT_5/IN5 )
  );
  X_INV \NlwInverterBlock_U1/U2/location_Maddsub__n0000__n0075<0>_MC.D2_PT_0/IN3  (
    .I(\U1/U2/location_Maddsub__n0000__n0067 [0]),
    .O(\NlwInverterSignal_U1/U2/location_Maddsub__n0000__n0075<0>_MC.D2_PT_0/IN3 )
  );
  X_INV \NlwInverterBlock_U1/U2/location_Maddsub__n0000__n0075<0>_MC.D2_PT_1/IN0  (
    .I(\U1/Channel0 [8]),
    .O(\NlwInverterSignal_U1/U2/location_Maddsub__n0000__n0075<0>_MC.D2_PT_1/IN0 )
  );
  X_INV \NlwInverterBlock_U1/U2/location_Maddsub__n0000__n0075<0>_MC.D2_PT_1/IN1  (
    .I(\U1/Channel0 [7]),
    .O(\NlwInverterSignal_U1/U2/location_Maddsub__n0000__n0075<0>_MC.D2_PT_1/IN1 )
  );
  X_INV \NlwInverterBlock_U1/U2/location_Maddsub__n0000__n0075<0>_MC.D2_PT_1/IN2  (
    .I(\U1/Channel0 [5]),
    .O(\NlwInverterSignal_U1/U2/location_Maddsub__n0000__n0075<0>_MC.D2_PT_1/IN2 )
  );
  X_INV \NlwInverterBlock_U1/U2/location_Maddsub__n0000__n0075<0>_MC.D2_PT_1/IN4  (
    .I(\U1/Channel0 [6]),
    .O(\NlwInverterSignal_U1/U2/location_Maddsub__n0000__n0075<0>_MC.D2_PT_1/IN4 )
  );
  X_INV \NlwInverterBlock_U1/U2/location_Maddsub__n0000__n0075<0>_MC.D2_PT_1/IN5  (
    .I(N_PZ_945),
    .O(\NlwInverterSignal_U1/U2/location_Maddsub__n0000__n0075<0>_MC.D2_PT_1/IN5 )
  );
  X_INV \NlwInverterBlock_N_PZ_945_MC.D2_PT_0/IN0  (
    .I(\U1/U1/CurrState_Sreg0_FFD1 ),
    .O(\NlwInverterSignal_N_PZ_945_MC.D2_PT_0/IN0 )
  );
  X_INV \NlwInverterBlock_N_PZ_945_MC.D2_PT_0/IN2  (
    .I(\U1/U1/CurrState_Sreg0_FFD2 ),
    .O(\NlwInverterSignal_N_PZ_945_MC.D2_PT_0/IN2 )
  );
  X_INV \NlwInverterBlock_N_PZ_945_MC.D2_PT_1/IN0  (
    .I(\U1/U1/CurrState_Sreg0_FFD1 ),
    .O(\NlwInverterSignal_N_PZ_945_MC.D2_PT_1/IN0 )
  );
  X_INV \NlwInverterBlock_N_PZ_945_MC.D2_PT_1/IN2  (
    .I(\U1/U1/CurrState_Sreg0_FFD4 ),
    .O(\NlwInverterSignal_N_PZ_945_MC.D2_PT_1/IN2 )
  );
  X_INV \NlwInverterBlock_U1/NET3721_MC.D2_PT_1/IN1  (
    .I(DCORENCCTLw),
    .O(\NlwInverterSignal_U1/NET3721_MC.D2_PT_1/IN1 )
  );
  X_INV \NlwInverterBlock_U1/Channel0<5>_MC.D2_PT_0/IN0  (
    .I(N_PZ_931),
    .O(\NlwInverterSignal_U1/Channel0<5>_MC.D2_PT_0/IN0 )
  );
  X_INV \NlwInverterBlock_U1/Channel0<5>_MC.D2_PT_2/IN1  (
    .I(\U1/U2/location_Maddsub__n0000__n0067 [0]),
    .O(\NlwInverterSignal_U1/Channel0<5>_MC.D2_PT_2/IN1 )
  );
  X_INV \NlwInverterBlock_U1/U2/location_Maddsub__n0000__n0067<0>_MC.D2_PT_1/IN0  (
    .I(\U1/Channel0 [0]),
    .O(\NlwInverterSignal_U1/U2/location_Maddsub__n0000__n0067<0>_MC.D2_PT_1/IN0 )
  );
  X_INV \NlwInverterBlock_U1/U2/location_Maddsub__n0000__n0067<0>_MC.D2_PT_1/IN1  (
    .I(N_PZ_945),
    .O(\NlwInverterSignal_U1/U2/location_Maddsub__n0000__n0067<0>_MC.D2_PT_1/IN1 )
  );
  X_INV \NlwInverterBlock_U1/U2/location_Maddsub__n0000__n0067<0>_MC.D2_PT_1/IN2  (
    .I(\U1/Channel0 [1]),
    .O(\NlwInverterSignal_U1/U2/location_Maddsub__n0000__n0067<0>_MC.D2_PT_1/IN2 )
  );
  X_INV \NlwInverterBlock_U1/U2/location_Maddsub__n0000__n0067<0>_MC.D2_PT_1/IN3  (
    .I(\U1/Channel0 [2]),
    .O(\NlwInverterSignal_U1/U2/location_Maddsub__n0000__n0067<0>_MC.D2_PT_1/IN3 )
  );
  X_INV \NlwInverterBlock_U1/U2/location_Maddsub__n0000__n0067<0>_MC.D2_PT_1/IN4  (
    .I(\U1/Channel0 [3]),
    .O(\NlwInverterSignal_U1/U2/location_Maddsub__n0000__n0067<0>_MC.D2_PT_1/IN4 )
  );
  X_INV \NlwInverterBlock_U1/U2/location_Maddsub__n0000__n0067<0>_MC.D2_PT_1/IN5  (
    .I(\U1/Channel0 [4]),
    .O(\NlwInverterSignal_U1/U2/location_Maddsub__n0000__n0067<0>_MC.D2_PT_1/IN5 )
  );
  X_INV \NlwInverterBlock_U1/Channel0<1>_MC.D2_PT_1/IN0  (
    .I(\U1/Channel0 [0]),
    .O(\NlwInverterSignal_U1/Channel0<1>_MC.D2_PT_1/IN0 )
  );
  X_INV \NlwInverterBlock_U1/Channel0<1>_MC.D2_PT_2/IN0  (
    .I(N_PZ_931),
    .O(\NlwInverterSignal_U1/Channel0<1>_MC.D2_PT_2/IN0 )
  );
  X_INV \NlwInverterBlock_N_PZ_966_MC.D2_PT_0/IN1  (
    .I(\U1/Zero0 ),
    .O(\NlwInverterSignal_N_PZ_966_MC.D2_PT_0/IN1 )
  );
  X_INV \NlwInverterBlock_N_PZ_966_MC.D2_PT_0/IN4  (
    .I(\U1/U1/CurrState_Sreg0_FFD2 ),
    .O(\NlwInverterSignal_N_PZ_966_MC.D2_PT_0/IN4 )
  );
  X_INV \NlwInverterBlock_N_PZ_966_MC.D2_PT_0/IN5  (
    .I(\U1/U1/CurrState_Sreg0_FFD4 ),
    .O(\NlwInverterSignal_N_PZ_966_MC.D2_PT_0/IN5 )
  );
  X_INV \NlwInverterBlock_N_PZ_966_MC.D2_PT_0/IN6  (
    .I(\U1/NET3721 ),
    .O(\NlwInverterSignal_N_PZ_966_MC.D2_PT_0/IN6 )
  );
  X_INV \NlwInverterBlock_N_PZ_966_MC.D2_PT_1/IN1  (
    .I(\U1/Zero0 ),
    .O(\NlwInverterSignal_N_PZ_966_MC.D2_PT_1/IN1 )
  );
  X_INV \NlwInverterBlock_N_PZ_966_MC.D2_PT_1/IN2  (
    .I(\U1/U1/CurrState_Sreg0_FFD1 ),
    .O(\NlwInverterSignal_N_PZ_966_MC.D2_PT_1/IN2 )
  );
  X_INV \NlwInverterBlock_N_PZ_966_MC.D2_PT_1/IN4  (
    .I(\U1/U1/CurrState_Sreg0_FFD2 ),
    .O(\NlwInverterSignal_N_PZ_966_MC.D2_PT_1/IN4 )
  );
  X_INV \NlwInverterBlock_N_PZ_969_MC.D2_PT_0/IN1  (
    .I(\U1/Zero0 ),
    .O(\NlwInverterSignal_N_PZ_969_MC.D2_PT_0/IN1 )
  );
  X_INV \NlwInverterBlock_N_PZ_969_MC.D2_PT_0/IN4  (
    .I(\U1/U1/CurrState_Sreg0_FFD2 ),
    .O(\NlwInverterSignal_N_PZ_969_MC.D2_PT_0/IN4 )
  );
  X_INV \NlwInverterBlock_N_PZ_969_MC.D2_PT_0/IN5  (
    .I(\U1/U1/CurrState_Sreg0_FFD4 ),
    .O(\NlwInverterSignal_N_PZ_969_MC.D2_PT_0/IN5 )
  );
  X_INV \NlwInverterBlock_N_PZ_969_MC.D2_PT_1/IN1  (
    .I(\U1/Zero0 ),
    .O(\NlwInverterSignal_N_PZ_969_MC.D2_PT_1/IN1 )
  );
  X_INV \NlwInverterBlock_N_PZ_969_MC.D2_PT_1/IN2  (
    .I(\U1/U1/CurrState_Sreg0_FFD1 ),
    .O(\NlwInverterSignal_N_PZ_969_MC.D2_PT_1/IN2 )
  );
  X_INV \NlwInverterBlock_N_PZ_969_MC.D2_PT_1/IN4  (
    .I(\U1/U1/CurrState_Sreg0_FFD2 ),
    .O(\NlwInverterSignal_N_PZ_969_MC.D2_PT_1/IN4 )
  );
  X_INV \NlwInverterBlock_N_PZ_969_MC.D2_PT_1/IN6  (
    .I(\U1/NET3721 ),
    .O(\NlwInverterSignal_N_PZ_969_MC.D2_PT_1/IN6 )
  );
  X_INV \NlwInverterBlock_U1/Channel0<2>_MC.D2_PT_0/IN0  (
    .I(N_PZ_931),
    .O(\NlwInverterSignal_U1/Channel0<2>_MC.D2_PT_0/IN0 )
  );
  X_INV \NlwInverterBlock_U1/Channel0<2>_MC.D2_PT_2/IN0  (
    .I(\U1/Channel0 [0]),
    .O(\NlwInverterSignal_U1/Channel0<2>_MC.D2_PT_2/IN0 )
  );
  X_INV \NlwInverterBlock_U1/Channel0<2>_MC.D2_PT_2/IN2  (
    .I(\U1/Channel0 [1]),
    .O(\NlwInverterSignal_U1/Channel0<2>_MC.D2_PT_2/IN2 )
  );
  X_INV \NlwInverterBlock_U1/Channel0<3>_MC.D2_PT_0/IN0  (
    .I(N_PZ_931),
    .O(\NlwInverterSignal_U1/Channel0<3>_MC.D2_PT_0/IN0 )
  );
  X_INV \NlwInverterBlock_U1/Channel0<3>_MC.D2_PT_2/IN0  (
    .I(\U1/Channel0 [0]),
    .O(\NlwInverterSignal_U1/Channel0<3>_MC.D2_PT_2/IN0 )
  );
  X_INV \NlwInverterBlock_U1/Channel0<3>_MC.D2_PT_2/IN2  (
    .I(\U1/Channel0 [1]),
    .O(\NlwInverterSignal_U1/Channel0<3>_MC.D2_PT_2/IN2 )
  );
  X_INV \NlwInverterBlock_U1/Channel0<3>_MC.D2_PT_2/IN3  (
    .I(\U1/Channel0 [2]),
    .O(\NlwInverterSignal_U1/Channel0<3>_MC.D2_PT_2/IN3 )
  );
  X_INV \NlwInverterBlock_U1/Channel0<4>_MC.D2_PT_0/IN0  (
    .I(N_PZ_931),
    .O(\NlwInverterSignal_U1/Channel0<4>_MC.D2_PT_0/IN0 )
  );
  X_INV \NlwInverterBlock_U1/Channel0<4>_MC.D2_PT_1/IN2  (
    .I(\U1/Channel0 [4]),
    .O(\NlwInverterSignal_U1/Channel0<4>_MC.D2_PT_1/IN2 )
  );
  X_INV \NlwInverterBlock_U1/Channel0<4>_MC.D2_PT_2/IN1  (
    .I(\U1/U2/location_Maddsub__n0000__n0067 [0]),
    .O(\NlwInverterSignal_U1/Channel0<4>_MC.D2_PT_2/IN1 )
  );
  X_INV \NlwInverterBlock_U1/Channel0<4>_MC.D2_PT_2/IN2  (
    .I(\U1/Channel0 [3]),
    .O(\NlwInverterSignal_U1/Channel0<4>_MC.D2_PT_2/IN2 )
  );
  X_INV \NlwInverterBlock_U1/Channel0<4>_MC.D2_PT_3/IN2  (
    .I(\U1/U2/location_Maddsub__n0000__n0067 [0]),
    .O(\NlwInverterSignal_U1/Channel0<4>_MC.D2_PT_3/IN2 )
  );
  X_INV \NlwInverterBlock_U1/Channel0<4>_MC.D2_PT_4/IN6  (
    .I(\U1/Channel0 [4]),
    .O(\NlwInverterSignal_U1/Channel0<4>_MC.D2_PT_4/IN6 )
  );
  X_INV \NlwInverterBlock_U1/Channel0<4>_MC.D2_PT_5/IN0  (
    .I(\U1/Channel0 [0]),
    .O(\NlwInverterSignal_U1/Channel0<4>_MC.D2_PT_5/IN0 )
  );
  X_INV \NlwInverterBlock_U1/Channel0<4>_MC.D2_PT_5/IN2  (
    .I(\U1/U2/location_Maddsub__n0000__n0067 [0]),
    .O(\NlwInverterSignal_U1/Channel0<4>_MC.D2_PT_5/IN2 )
  );
  X_INV \NlwInverterBlock_U1/Channel0<4>_MC.D2_PT_5/IN3  (
    .I(\U1/Channel0 [1]),
    .O(\NlwInverterSignal_U1/Channel0<4>_MC.D2_PT_5/IN3 )
  );
  X_INV \NlwInverterBlock_U1/Channel0<4>_MC.D2_PT_5/IN4  (
    .I(\U1/Channel0 [2]),
    .O(\NlwInverterSignal_U1/Channel0<4>_MC.D2_PT_5/IN4 )
  );
  X_INV \NlwInverterBlock_U1/Channel0<4>_MC.D2_PT_5/IN5  (
    .I(\U1/Channel0 [3]),
    .O(\NlwInverterSignal_U1/Channel0<4>_MC.D2_PT_5/IN5 )
  );
  X_INV \NlwInverterBlock_U1/Channel0<6>_MC.D2_PT_0/IN0  (
    .I(N_PZ_931),
    .O(\NlwInverterSignal_U1/Channel0<6>_MC.D2_PT_0/IN0 )
  );
  X_INV \NlwInverterBlock_U1/Channel0<6>_MC.D2_PT_1/IN1  (
    .I(\U1/Channel0 [5]),
    .O(\NlwInverterSignal_U1/Channel0<6>_MC.D2_PT_1/IN1 )
  );
  X_INV \NlwInverterBlock_U1/Channel0<6>_MC.D2_PT_2/IN2  (
    .I(\U1/U2/location_Maddsub__n0000__n0067 [0]),
    .O(\NlwInverterSignal_U1/Channel0<6>_MC.D2_PT_2/IN2 )
  );
  X_INV \NlwInverterBlock_U1/Channel0<7>_MC.D2_PT_0/IN0  (
    .I(N_PZ_931),
    .O(\NlwInverterSignal_U1/Channel0<7>_MC.D2_PT_0/IN0 )
  );
  X_INV \NlwInverterBlock_U1/Channel0<7>_MC.D2_PT_1/IN1  (
    .I(\U1/Channel0 [5]),
    .O(\NlwInverterSignal_U1/Channel0<7>_MC.D2_PT_1/IN1 )
  );
  X_INV \NlwInverterBlock_U1/Channel0<7>_MC.D2_PT_1/IN3  (
    .I(\U1/Channel0 [6]),
    .O(\NlwInverterSignal_U1/Channel0<7>_MC.D2_PT_1/IN3 )
  );
  X_INV \NlwInverterBlock_U1/Channel0<7>_MC.D2_PT_2/IN2  (
    .I(\U1/U2/location_Maddsub__n0000__n0067 [0]),
    .O(\NlwInverterSignal_U1/Channel0<7>_MC.D2_PT_2/IN2 )
  );
  X_INV \NlwInverterBlock_DCOR0THRESHIGHr_MC.D1/IN1  (
    .I(\RD_II/UIM ),
    .O(\NlwInverterSignal_DCOR0THRESHIGHr_MC.D1/IN1 )
  );
  X_INV \NlwInverterBlock_DCOR0THRESHIGHr_MC.D1/IN3  (
    .I(U2_ADDR_reg[4]),
    .O(\NlwInverterSignal_DCOR0THRESHIGHr_MC.D1/IN3 )
  );
  X_INV \NlwInverterBlock_DCOR0THRESHIGHr_MC.D1/IN4  (
    .I(U2_ADDR_reg[5]),
    .O(\NlwInverterSignal_DCOR0THRESHIGHr_MC.D1/IN4 )
  );
  X_INV \NlwInverterBlock_DCOR0THRESHIGHr_MC.D1/IN5  (
    .I(U2_ADDR_reg[6]),
    .O(\NlwInverterSignal_DCOR0THRESHIGHr_MC.D1/IN5 )
  );
  X_INV \NlwInverterBlock_DCOR0THRESHIGHr_MC.D1/IN6  (
    .I(U2_ADDR_reg[7]),
    .O(\NlwInverterSignal_DCOR0THRESHIGHr_MC.D1/IN6 )
  );
  X_INV \NlwInverterBlock_DCOR0THRESHIGHr_MC.D1/IN8  (
    .I(U2_ADDR_reg[1]),
    .O(\NlwInverterSignal_DCOR0THRESHIGHr_MC.D1/IN8 )
  );
  X_INV \NlwInverterBlock_DCOR0THRESHIGHr_MC.D1/IN9  (
    .I(U2_ADDR_reg[2]),
    .O(\NlwInverterSignal_DCOR0THRESHIGHr_MC.D1/IN9 )
  );
  X_INV \NlwInverterBlock_U1/U4/Latch1r<0>_MC.D2_PT_1/IN1  (
    .I(DCORIFGw),
    .O(\NlwInverterSignal_U1/U4/Latch1r<0>_MC.D2_PT_1/IN1 )
  );
  X_INV \NlwInverterBlock_U1/U4/Latch1r<0>_MC.D2_PT_1/IN2  (
    .I(DCORENCCTLw),
    .O(\NlwInverterSignal_U1/U4/Latch1r<0>_MC.D2_PT_1/IN2 )
  );
  X_INV \NlwInverterBlock_U1/Channel1<0>_MC.D2_PT_0/IN2  (
    .I(\U1/Zero1 ),
    .O(\NlwInverterSignal_U1/Channel1<0>_MC.D2_PT_0/IN2 )
  );
  X_INV \NlwInverterBlock_U1/Channel1<0>_MC.D2_PT_0/IN3  (
    .I(N_PZ_1155),
    .O(\NlwInverterSignal_U1/Channel1<0>_MC.D2_PT_0/IN3 )
  );
  X_INV \NlwInverterBlock_U1/Channel1<0>_MC.D2_PT_1/IN1  (
    .I(\U1/Channel1 [0]),
    .O(\NlwInverterSignal_U1/Channel1<0>_MC.D2_PT_1/IN1 )
  );
  X_INV \NlwInverterBlock_U1/Channel1<0>_MC.D2_PT_1/IN2  (
    .I(\U1/Zero1 ),
    .O(\NlwInverterSignal_U1/Channel1<0>_MC.D2_PT_1/IN2 )
  );
  X_INV \NlwInverterBlock_U1/Zero1_MC.D2_PT_0/IN0  (
    .I(\MSPReset_II/UIM ),
    .O(\NlwInverterSignal_U1/Zero1_MC.D2_PT_0/IN0 )
  );
  X_INV \NlwInverterBlock_U1/Zero1_MC.D2_PT_1/IN1  (
    .I(N_PZ_933),
    .O(\NlwInverterSignal_U1/Zero1_MC.D2_PT_1/IN1 )
  );
  X_INV \NlwInverterBlock_U1/Zero1_MC.D2_PT_2/IN1  (
    .I(NET2493),
    .O(\NlwInverterSignal_U1/Zero1_MC.D2_PT_2/IN1 )
  );
  X_INV \NlwInverterBlock_U1/Zero1_MC.D2_PT_2/IN5  (
    .I(\U1/U4/HE1statelastr ),
    .O(\NlwInverterSignal_U1/Zero1_MC.D2_PT_2/IN5 )
  );
  X_INV \NlwInverterBlock_U1/Zero1_MC.D2_PT_2/IN6  (
    .I(N_PZ_964),
    .O(\NlwInverterSignal_U1/Zero1_MC.D2_PT_2/IN6 )
  );
  X_INV \NlwInverterBlock_U1/Zero1_MC.D2_PT_3/IN1  (
    .I(NET2493),
    .O(\NlwInverterSignal_U1/Zero1_MC.D2_PT_3/IN1 )
  );
  X_INV \NlwInverterBlock_U1/Zero1_MC.D2_PT_3/IN2  (
    .I(\U1/U4/RF1r ),
    .O(\NlwInverterSignal_U1/Zero1_MC.D2_PT_3/IN2 )
  );
  X_INV \NlwInverterBlock_U1/Zero1_MC.D2_PT_3/IN4  (
    .I(\U1/U4/HE1stater ),
    .O(\NlwInverterSignal_U1/Zero1_MC.D2_PT_3/IN4 )
  );
  X_INV \NlwInverterBlock_U1/Zero1_MC.D2_PT_3/IN6  (
    .I(N_PZ_964),
    .O(\NlwInverterSignal_U1/Zero1_MC.D2_PT_3/IN6 )
  );
  X_INV \NlwInverterBlock_N_PZ_933_MC.D1/IN1  (
    .I(\U1/Zero1 ),
    .O(\NlwInverterSignal_N_PZ_933_MC.D1/IN1 )
  );
  X_INV \NlwInverterBlock_N_PZ_1155_MC.D2_PT_0/IN2  (
    .I(\U1/U6/CurrState_Sreg0_FFD2 ),
    .O(\NlwInverterSignal_N_PZ_1155_MC.D2_PT_0/IN2 )
  );
  X_INV \NlwInverterBlock_N_PZ_1155_MC.D2_PT_0/IN3  (
    .I(\U1/U6/CurrState_Sreg0_FFD4 ),
    .O(\NlwInverterSignal_N_PZ_1155_MC.D2_PT_0/IN3 )
  );
  X_INV \NlwInverterBlock_N_PZ_1155_MC.D2_PT_1/IN0  (
    .I(\U1/U6/CurrState_Sreg0_FFD1 ),
    .O(\NlwInverterSignal_N_PZ_1155_MC.D2_PT_1/IN0 )
  );
  X_INV \NlwInverterBlock_N_PZ_1155_MC.D2_PT_1/IN2  (
    .I(\U1/U6/CurrState_Sreg0_FFD2 ),
    .O(\NlwInverterSignal_N_PZ_1155_MC.D2_PT_1/IN2 )
  );
  X_INV \NlwInverterBlock_U1/U6/CurrState_Sreg0_FFD1_MC.D2_PT_0/IN3  (
    .I(\U1/U6/CurrState_Sreg0_FFD4 ),
    .O(\NlwInverterSignal_U1/U6/CurrState_Sreg0_FFD1_MC.D2_PT_0/IN3 )
  );
  X_INV \NlwInverterBlock_U1/U6/CurrState_Sreg0_FFD1_MC.D2_PT_1/IN3  (
    .I(\U1/U6/CurrState_Sreg0_FFD3 ),
    .O(\NlwInverterSignal_U1/U6/CurrState_Sreg0_FFD1_MC.D2_PT_1/IN3 )
  );
  X_INV \NlwInverterBlock_U1/U6/CurrState_Sreg0_FFD1_MC.D2_PT_1/IN4  (
    .I(\U1/U6/CurrState_Sreg0_FFD4 ),
    .O(\NlwInverterSignal_U1/U6/CurrState_Sreg0_FFD1_MC.D2_PT_1/IN4 )
  );
  X_INV \NlwInverterBlock_U1/U6/CurrState_Sreg0_FFD1_MC.D2_PT_2/IN1  (
    .I(\PhaseA_Encoder1_II/UIM ),
    .O(\NlwInverterSignal_U1/U6/CurrState_Sreg0_FFD1_MC.D2_PT_2/IN1 )
  );
  X_INV \NlwInverterBlock_U1/U6/CurrState_Sreg0_FFD1_MC.D2_PT_2/IN3  (
    .I(\U1/U6/CurrState_Sreg0_FFD3 ),
    .O(\NlwInverterSignal_U1/U6/CurrState_Sreg0_FFD1_MC.D2_PT_2/IN3 )
  );
  X_INV \NlwInverterBlock_U1/U6/CurrState_Sreg0_FFD1_MC.D2_PT_2/IN4  (
    .I(\U1/U6/CurrState_Sreg0_FFD2 ),
    .O(\NlwInverterSignal_U1/U6/CurrState_Sreg0_FFD1_MC.D2_PT_2/IN4 )
  );
  X_INV \NlwInverterBlock_U1/U6/CurrState_Sreg0_FFD1_MC.D2_PT_2/IN5  (
    .I(\U1/U6/CurrState_Sreg0_FFD4 ),
    .O(\NlwInverterSignal_U1/U6/CurrState_Sreg0_FFD1_MC.D2_PT_2/IN5 )
  );
  X_INV \NlwInverterBlock_U1/U6/CurrState_Sreg0_FFD3_MC.D2_PT_0/IN3  (
    .I(\U1/U6/CurrState_Sreg0_FFD4 ),
    .O(\NlwInverterSignal_U1/U6/CurrState_Sreg0_FFD3_MC.D2_PT_0/IN3 )
  );
  X_INV \NlwInverterBlock_U1/U6/CurrState_Sreg0_FFD3_MC.D2_PT_1/IN1  (
    .I(\PhaseA_Encoder1_II/UIM ),
    .O(\NlwInverterSignal_U1/U6/CurrState_Sreg0_FFD3_MC.D2_PT_1/IN1 )
  );
  X_INV \NlwInverterBlock_U1/U6/CurrState_Sreg0_FFD3_MC.D2_PT_1/IN4  (
    .I(\U1/U6/CurrState_Sreg0_FFD4 ),
    .O(\NlwInverterSignal_U1/U6/CurrState_Sreg0_FFD3_MC.D2_PT_1/IN4 )
  );
  X_INV \NlwInverterBlock_U1/U6/CurrState_Sreg0_FFD3_MC.D2_PT_2/IN1  (
    .I(\U1/U6/CurrState_Sreg0_FFD1 ),
    .O(\NlwInverterSignal_U1/U6/CurrState_Sreg0_FFD3_MC.D2_PT_2/IN1 )
  );
  X_INV \NlwInverterBlock_U1/U6/CurrState_Sreg0_FFD3_MC.D2_PT_2/IN3  (
    .I(\U1/U6/CurrState_Sreg0_FFD2 ),
    .O(\NlwInverterSignal_U1/U6/CurrState_Sreg0_FFD3_MC.D2_PT_2/IN3 )
  );
  X_INV \NlwInverterBlock_U1/U6/CurrState_Sreg0_FFD3_MC.D2_PT_2/IN4  (
    .I(\U1/U6/CurrState_Sreg0_FFD4 ),
    .O(\NlwInverterSignal_U1/U6/CurrState_Sreg0_FFD3_MC.D2_PT_2/IN4 )
  );
  X_INV \NlwInverterBlock_U1/U6/CurrState_Sreg0_FFD2_MC.D2_PT_0/IN2  (
    .I(\U1/U6/CurrState_Sreg0_FFD3 ),
    .O(\NlwInverterSignal_U1/U6/CurrState_Sreg0_FFD2_MC.D2_PT_0/IN2 )
  );
  X_INV \NlwInverterBlock_U1/U6/CurrState_Sreg0_FFD2_MC.D2_PT_0/IN3  (
    .I(\U1/U6/CurrState_Sreg0_FFD4 ),
    .O(\NlwInverterSignal_U1/U6/CurrState_Sreg0_FFD2_MC.D2_PT_0/IN3 )
  );
  X_INV \NlwInverterBlock_U1/U6/CurrState_Sreg0_FFD2_MC.D2_PT_0/IN4  (
    .I(N_PZ_1107),
    .O(\NlwInverterSignal_U1/U6/CurrState_Sreg0_FFD2_MC.D2_PT_0/IN4 )
  );
  X_INV \NlwInverterBlock_U1/U6/CurrState_Sreg0_FFD2_MC.D2_PT_1/IN3  (
    .I(\U1/U6/CurrState_Sreg0_FFD4 ),
    .O(\NlwInverterSignal_U1/U6/CurrState_Sreg0_FFD2_MC.D2_PT_1/IN3 )
  );
  X_INV \NlwInverterBlock_U1/U6/CurrState_Sreg0_FFD2_MC.D2_PT_1/IN4  (
    .I(N_PZ_1107),
    .O(\NlwInverterSignal_U1/U6/CurrState_Sreg0_FFD2_MC.D2_PT_1/IN4 )
  );
  X_INV \NlwInverterBlock_U1/U6/CurrState_Sreg0_FFD2_MC.D2_PT_2/IN1  (
    .I(\U1/U6/CurrState_Sreg0_FFD3 ),
    .O(\NlwInverterSignal_U1/U6/CurrState_Sreg0_FFD2_MC.D2_PT_2/IN1 )
  );
  X_INV \NlwInverterBlock_U1/U6/CurrState_Sreg0_FFD2_MC.D2_PT_2/IN3  (
    .I(\U1/U6/CurrState_Sreg0_FFD4 ),
    .O(\NlwInverterSignal_U1/U6/CurrState_Sreg0_FFD2_MC.D2_PT_2/IN3 )
  );
  X_INV \NlwInverterBlock_U1/U6/CurrState_Sreg0_FFD2_MC.D2_PT_3/IN2  (
    .I(N_PZ_1155),
    .O(\NlwInverterSignal_U1/U6/CurrState_Sreg0_FFD2_MC.D2_PT_3/IN2 )
  );
  X_INV \NlwInverterBlock_U1/U6/CurrState_Sreg0_FFD2_MC.D2_PT_3/IN4  (
    .I(\U1/U6/CurrState_Sreg0_FFD4 ),
    .O(\NlwInverterSignal_U1/U6/CurrState_Sreg0_FFD2_MC.D2_PT_3/IN4 )
  );
  X_INV \NlwInverterBlock_U1/U6/CurrState_Sreg0_FFD4_MC.D1/IN1  (
    .I(\PhaseA_Encoder1_II/UIM ),
    .O(\NlwInverterSignal_U1/U6/CurrState_Sreg0_FFD4_MC.D1/IN1 )
  );
  X_INV \NlwInverterBlock_U1/U6/CurrState_Sreg0_FFD4_MC.D1/IN2  (
    .I(\PhaseB_Encoder1_II/UIM ),
    .O(\NlwInverterSignal_U1/U6/CurrState_Sreg0_FFD4_MC.D1/IN2 )
  );
  X_INV \NlwInverterBlock_U1/U6/CurrState_Sreg0_FFD4_MC.D1/IN3  (
    .I(\U1/U6/CurrState_Sreg0_FFD1 ),
    .O(\NlwInverterSignal_U1/U6/CurrState_Sreg0_FFD4_MC.D1/IN3 )
  );
  X_INV \NlwInverterBlock_U1/U6/CurrState_Sreg0_FFD4_MC.D1/IN5  (
    .I(\U1/U6/CurrState_Sreg0_FFD2 ),
    .O(\NlwInverterSignal_U1/U6/CurrState_Sreg0_FFD4_MC.D1/IN5 )
  );
  X_INV \NlwInverterBlock_U1/U6/CurrState_Sreg0_FFD4_MC.D1/IN6  (
    .I(\U1/U6/CurrState_Sreg0_FFD4 ),
    .O(\NlwInverterSignal_U1/U6/CurrState_Sreg0_FFD4_MC.D1/IN6 )
  );
  X_INV \NlwInverterBlock_N_PZ_1107_MC.D2_PT_0/IN1  (
    .I(\U1/U6/CurrState_Sreg0_FFD1 ),
    .O(\NlwInverterSignal_N_PZ_1107_MC.D2_PT_0/IN1 )
  );
  X_INV \NlwInverterBlock_N_PZ_1107_MC.D2_PT_1/IN0  (
    .I(\PhaseB_Encoder1_II/UIM ),
    .O(\NlwInverterSignal_N_PZ_1107_MC.D2_PT_1/IN0 )
  );
  X_INV \NlwInverterBlock_DCOR1THRESLOWr_MC.D1/IN1  (
    .I(\RD_II/UIM ),
    .O(\NlwInverterSignal_DCOR1THRESLOWr_MC.D1/IN1 )
  );
  X_INV \NlwInverterBlock_DCOR1THRESLOWr_MC.D1/IN2  (
    .I(U2_ADDR_reg[0]),
    .O(\NlwInverterSignal_DCOR1THRESLOWr_MC.D1/IN2 )
  );
  X_INV \NlwInverterBlock_DCOR1THRESLOWr_MC.D1/IN3  (
    .I(U2_ADDR_reg[4]),
    .O(\NlwInverterSignal_DCOR1THRESLOWr_MC.D1/IN3 )
  );
  X_INV \NlwInverterBlock_DCOR1THRESLOWr_MC.D1/IN4  (
    .I(U2_ADDR_reg[5]),
    .O(\NlwInverterSignal_DCOR1THRESLOWr_MC.D1/IN4 )
  );
  X_INV \NlwInverterBlock_DCOR1THRESLOWr_MC.D1/IN5  (
    .I(U2_ADDR_reg[6]),
    .O(\NlwInverterSignal_DCOR1THRESLOWr_MC.D1/IN5 )
  );
  X_INV \NlwInverterBlock_DCOR1THRESLOWr_MC.D1/IN6  (
    .I(U2_ADDR_reg[7]),
    .O(\NlwInverterSignal_DCOR1THRESLOWr_MC.D1/IN6 )
  );
  X_INV \NlwInverterBlock_DCOR1THRESLOWr_MC.D1/IN9  (
    .I(U2_ADDR_reg[2]),
    .O(\NlwInverterSignal_DCOR1THRESLOWr_MC.D1/IN9 )
  );
  X_INV \NlwInverterBlock_U1/U4/Latch1r<8>_MC.D2_PT_1/IN1  (
    .I(DCORIFGw),
    .O(\NlwInverterSignal_U1/U4/Latch1r<8>_MC.D2_PT_1/IN1 )
  );
  X_INV \NlwInverterBlock_U1/U4/Latch1r<8>_MC.D2_PT_1/IN2  (
    .I(DCORENCCTLw),
    .O(\NlwInverterSignal_U1/U4/Latch1r<8>_MC.D2_PT_1/IN2 )
  );
  X_INV \NlwInverterBlock_U1/Channel1<8>_MC.D2_PT_0/IN0  (
    .I(N_PZ_933),
    .O(\NlwInverterSignal_U1/Channel1<8>_MC.D2_PT_0/IN0 )
  );
  X_INV \NlwInverterBlock_U1/Channel1<8>_MC.D2_PT_1/IN2  (
    .I(\U1/Channel1 [7]),
    .O(\NlwInverterSignal_U1/Channel1<8>_MC.D2_PT_1/IN2 )
  );
  X_INV \NlwInverterBlock_U1/Channel1<8>_MC.D2_PT_1/IN3  (
    .I(\U1/U5/location_Maddsub__n0000__n0075 [0]),
    .O(\NlwInverterSignal_U1/Channel1<8>_MC.D2_PT_1/IN3 )
  );
  X_INV \NlwInverterBlock_U1/Channel1<8>_MC.D2_PT_2/IN1  (
    .I(\U1/Zero1 ),
    .O(\NlwInverterSignal_U1/Channel1<8>_MC.D2_PT_2/IN1 )
  );
  X_INV \NlwInverterBlock_U1/Channel1<8>_MC.D2_PT_2/IN3  (
    .I(\U1/Channel1 [8]),
    .O(\NlwInverterSignal_U1/Channel1<8>_MC.D2_PT_2/IN3 )
  );
  X_INV \NlwInverterBlock_U1/Channel1<8>_MC.D2_PT_2/IN4  (
    .I(N_PZ_1016),
    .O(\NlwInverterSignal_U1/Channel1<8>_MC.D2_PT_2/IN4 )
  );
  X_INV \NlwInverterBlock_U1/Channel1<8>_MC.D2_PT_3/IN2  (
    .I(\U1/U5/location_Maddsub__n0000__n0075 [0]),
    .O(\NlwInverterSignal_U1/Channel1<8>_MC.D2_PT_3/IN2 )
  );
  X_INV \NlwInverterBlock_U1/Channel1<8>_MC.D2_PT_3/IN4  (
    .I(\U1/U5/location_Maddsub__n0000__n0067 [0]),
    .O(\NlwInverterSignal_U1/Channel1<8>_MC.D2_PT_3/IN4 )
  );
  X_INV \NlwInverterBlock_U1/Channel1<8>_MC.D2_PT_4/IN2  (
    .I(\U1/Channel1 [7]),
    .O(\NlwInverterSignal_U1/Channel1<8>_MC.D2_PT_4/IN2 )
  );
  X_INV \NlwInverterBlock_U1/Channel1<8>_MC.D2_PT_4/IN3  (
    .I(\U1/U5/location_Maddsub__n0000__n0075 [0]),
    .O(\NlwInverterSignal_U1/Channel1<8>_MC.D2_PT_4/IN3 )
  );
  X_INV \NlwInverterBlock_U1/Channel1<8>_MC.D2_PT_4/IN4  (
    .I(\U1/Channel1 [5]),
    .O(\NlwInverterSignal_U1/Channel1<8>_MC.D2_PT_4/IN4 )
  );
  X_INV \NlwInverterBlock_U1/Channel1<8>_MC.D2_PT_4/IN6  (
    .I(\U1/Channel1 [6]),
    .O(\NlwInverterSignal_U1/Channel1<8>_MC.D2_PT_4/IN6 )
  );
  X_INV \NlwInverterBlock_U1/Channel1<8>_MC.D2_PT_5/IN1  (
    .I(\U1/Zero1 ),
    .O(\NlwInverterSignal_U1/Channel1<8>_MC.D2_PT_5/IN1 )
  );
  X_INV \NlwInverterBlock_U1/Channel1<8>_MC.D2_PT_5/IN3  (
    .I(\U1/Channel1 [8]),
    .O(\NlwInverterSignal_U1/Channel1<8>_MC.D2_PT_5/IN3 )
  );
  X_INV \NlwInverterBlock_U1/Channel1<8>_MC.D2_PT_5/IN7  (
    .I(\U1/U5/location_Maddsub__n0000__n0067 [0]),
    .O(\NlwInverterSignal_U1/Channel1<8>_MC.D2_PT_5/IN7 )
  );
  X_INV \NlwInverterBlock_U1/Channel1<5>_MC.D2_PT_0/IN0  (
    .I(N_PZ_933),
    .O(\NlwInverterSignal_U1/Channel1<5>_MC.D2_PT_0/IN0 )
  );
  X_INV \NlwInverterBlock_U1/Channel1<5>_MC.D2_PT_1/IN1  (
    .I(\U1/Zero1 ),
    .O(\NlwInverterSignal_U1/Channel1<5>_MC.D2_PT_1/IN1 )
  );
  X_INV \NlwInverterBlock_U1/Channel1<5>_MC.D2_PT_1/IN3  (
    .I(\U1/U5/location_Maddsub__n0000__n0067 [0]),
    .O(\NlwInverterSignal_U1/Channel1<5>_MC.D2_PT_1/IN3 )
  );
  X_INV \NlwInverterBlock_U1/Channel1<5>_MC.D2_PT_2/IN1  (
    .I(\U1/Zero1 ),
    .O(\NlwInverterSignal_U1/Channel1<5>_MC.D2_PT_2/IN1 )
  );
  X_INV \NlwInverterBlock_U1/Channel1<5>_MC.D2_PT_2/IN3  (
    .I(N_PZ_1016),
    .O(\NlwInverterSignal_U1/Channel1<5>_MC.D2_PT_2/IN3 )
  );
  X_INV \NlwInverterBlock_U1/U5/location_Maddsub__n0000__n0067<0>_MC.D2_PT_1/IN0  (
    .I(\U1/Channel1 [0]),
    .O(\NlwInverterSignal_U1/U5/location_Maddsub__n0000__n0067<0>_MC.D2_PT_1/IN0 )
  );
  X_INV \NlwInverterBlock_U1/U5/location_Maddsub__n0000__n0067<0>_MC.D2_PT_1/IN1  (
    .I(N_PZ_946),
    .O(\NlwInverterSignal_U1/U5/location_Maddsub__n0000__n0067<0>_MC.D2_PT_1/IN1 )
  );
  X_INV \NlwInverterBlock_U1/U5/location_Maddsub__n0000__n0067<0>_MC.D2_PT_1/IN2  (
    .I(\U1/Channel1 [1]),
    .O(\NlwInverterSignal_U1/U5/location_Maddsub__n0000__n0067<0>_MC.D2_PT_1/IN2 )
  );
  X_INV \NlwInverterBlock_U1/U5/location_Maddsub__n0000__n0067<0>_MC.D2_PT_1/IN3  (
    .I(\U1/Channel1 [2]),
    .O(\NlwInverterSignal_U1/U5/location_Maddsub__n0000__n0067<0>_MC.D2_PT_1/IN3 )
  );
  X_INV \NlwInverterBlock_U1/U5/location_Maddsub__n0000__n0067<0>_MC.D2_PT_1/IN4  (
    .I(\U1/Channel1 [3]),
    .O(\NlwInverterSignal_U1/U5/location_Maddsub__n0000__n0067<0>_MC.D2_PT_1/IN4 )
  );
  X_INV \NlwInverterBlock_U1/U5/location_Maddsub__n0000__n0067<0>_MC.D2_PT_1/IN5  (
    .I(\U1/Channel1 [4]),
    .O(\NlwInverterSignal_U1/U5/location_Maddsub__n0000__n0067<0>_MC.D2_PT_1/IN5 )
  );
  X_INV \NlwInverterBlock_N_PZ_946_MC.D2_PT_0/IN0  (
    .I(\U1/U6/CurrState_Sreg0_FFD1 ),
    .O(\NlwInverterSignal_N_PZ_946_MC.D2_PT_0/IN0 )
  );
  X_INV \NlwInverterBlock_N_PZ_946_MC.D2_PT_0/IN2  (
    .I(\U1/U6/CurrState_Sreg0_FFD2 ),
    .O(\NlwInverterSignal_N_PZ_946_MC.D2_PT_0/IN2 )
  );
  X_INV \NlwInverterBlock_N_PZ_946_MC.D2_PT_1/IN0  (
    .I(\U1/U6/CurrState_Sreg0_FFD1 ),
    .O(\NlwInverterSignal_N_PZ_946_MC.D2_PT_1/IN0 )
  );
  X_INV \NlwInverterBlock_N_PZ_946_MC.D2_PT_1/IN2  (
    .I(\U1/U6/CurrState_Sreg0_FFD4 ),
    .O(\NlwInverterSignal_N_PZ_946_MC.D2_PT_1/IN2 )
  );
  X_INV \NlwInverterBlock_U1/NET3720_MC.D2_PT_1/IN1  (
    .I(DCORENCCTLw),
    .O(\NlwInverterSignal_U1/NET3720_MC.D2_PT_1/IN1 )
  );
  X_INV \NlwInverterBlock_U1/Channel1<1>_MC.D2_PT_0/IN0  (
    .I(N_PZ_933),
    .O(\NlwInverterSignal_U1/Channel1<1>_MC.D2_PT_0/IN0 )
  );
  X_INV \NlwInverterBlock_U1/Channel1<1>_MC.D2_PT_1/IN2  (
    .I(\U1/Zero1 ),
    .O(\NlwInverterSignal_U1/Channel1<1>_MC.D2_PT_1/IN2 )
  );
  X_INV \NlwInverterBlock_U1/Channel1<1>_MC.D2_PT_2/IN1  (
    .I(\U1/Channel1 [0]),
    .O(\NlwInverterSignal_U1/Channel1<1>_MC.D2_PT_2/IN1 )
  );
  X_INV \NlwInverterBlock_U1/Channel1<1>_MC.D2_PT_2/IN2  (
    .I(\U1/Zero1 ),
    .O(\NlwInverterSignal_U1/Channel1<1>_MC.D2_PT_2/IN2 )
  );
  X_INV \NlwInverterBlock_U1/Channel1<1>_MC.D2_PT_2/IN4  (
    .I(N_PZ_1016),
    .O(\NlwInverterSignal_U1/Channel1<1>_MC.D2_PT_2/IN4 )
  );
  X_INV \NlwInverterBlock_N_PZ_1016_MC.D2_PT_0/IN2  (
    .I(\U1/U6/CurrState_Sreg0_FFD2 ),
    .O(\NlwInverterSignal_N_PZ_1016_MC.D2_PT_0/IN2 )
  );
  X_INV \NlwInverterBlock_N_PZ_1016_MC.D2_PT_0/IN3  (
    .I(\U1/U6/CurrState_Sreg0_FFD4 ),
    .O(\NlwInverterSignal_N_PZ_1016_MC.D2_PT_0/IN3 )
  );
  X_INV \NlwInverterBlock_N_PZ_1016_MC.D2_PT_1/IN0  (
    .I(\U1/U6/CurrState_Sreg0_FFD1 ),
    .O(\NlwInverterSignal_N_PZ_1016_MC.D2_PT_1/IN0 )
  );
  X_INV \NlwInverterBlock_N_PZ_1016_MC.D2_PT_1/IN2  (
    .I(\U1/U6/CurrState_Sreg0_FFD2 ),
    .O(\NlwInverterSignal_N_PZ_1016_MC.D2_PT_1/IN2 )
  );
  X_INV \NlwInverterBlock_N_PZ_1016_MC.D2_PT_1/IN4  (
    .I(\U1/NET3720 ),
    .O(\NlwInverterSignal_N_PZ_1016_MC.D2_PT_1/IN4 )
  );
  X_INV \NlwInverterBlock_U1/Channel1<2>_MC.D2_PT_0/IN0  (
    .I(N_PZ_933),
    .O(\NlwInverterSignal_U1/Channel1<2>_MC.D2_PT_0/IN0 )
  );
  X_INV \NlwInverterBlock_U1/Channel1<2>_MC.D2_PT_1/IN2  (
    .I(\U1/Zero1 ),
    .O(\NlwInverterSignal_U1/Channel1<2>_MC.D2_PT_1/IN2 )
  );
  X_INV \NlwInverterBlock_U1/Channel1<2>_MC.D2_PT_2/IN1  (
    .I(\U1/Channel1 [0]),
    .O(\NlwInverterSignal_U1/Channel1<2>_MC.D2_PT_2/IN1 )
  );
  X_INV \NlwInverterBlock_U1/Channel1<2>_MC.D2_PT_2/IN2  (
    .I(\U1/Zero1 ),
    .O(\NlwInverterSignal_U1/Channel1<2>_MC.D2_PT_2/IN2 )
  );
  X_INV \NlwInverterBlock_U1/Channel1<2>_MC.D2_PT_2/IN4  (
    .I(N_PZ_1016),
    .O(\NlwInverterSignal_U1/Channel1<2>_MC.D2_PT_2/IN4 )
  );
  X_INV \NlwInverterBlock_U1/Channel1<2>_MC.D2_PT_2/IN5  (
    .I(\U1/Channel1 [1]),
    .O(\NlwInverterSignal_U1/Channel1<2>_MC.D2_PT_2/IN5 )
  );
  X_INV \NlwInverterBlock_U1/Channel1<3>_MC.D2_PT_0/IN0  (
    .I(N_PZ_933),
    .O(\NlwInverterSignal_U1/Channel1<3>_MC.D2_PT_0/IN0 )
  );
  X_INV \NlwInverterBlock_U1/Channel1<3>_MC.D2_PT_1/IN2  (
    .I(\U1/Zero1 ),
    .O(\NlwInverterSignal_U1/Channel1<3>_MC.D2_PT_1/IN2 )
  );
  X_INV \NlwInverterBlock_U1/Channel1<3>_MC.D2_PT_2/IN1  (
    .I(\U1/Channel1 [0]),
    .O(\NlwInverterSignal_U1/Channel1<3>_MC.D2_PT_2/IN1 )
  );
  X_INV \NlwInverterBlock_U1/Channel1<3>_MC.D2_PT_2/IN2  (
    .I(\U1/Zero1 ),
    .O(\NlwInverterSignal_U1/Channel1<3>_MC.D2_PT_2/IN2 )
  );
  X_INV \NlwInverterBlock_U1/Channel1<3>_MC.D2_PT_2/IN4  (
    .I(N_PZ_1016),
    .O(\NlwInverterSignal_U1/Channel1<3>_MC.D2_PT_2/IN4 )
  );
  X_INV \NlwInverterBlock_U1/Channel1<3>_MC.D2_PT_2/IN5  (
    .I(\U1/Channel1 [1]),
    .O(\NlwInverterSignal_U1/Channel1<3>_MC.D2_PT_2/IN5 )
  );
  X_INV \NlwInverterBlock_U1/Channel1<3>_MC.D2_PT_2/IN6  (
    .I(\U1/Channel1 [2]),
    .O(\NlwInverterSignal_U1/Channel1<3>_MC.D2_PT_2/IN6 )
  );
  X_INV \NlwInverterBlock_U1/Channel1<4>_MC.D2_PT_0/IN0  (
    .I(N_PZ_933),
    .O(\NlwInverterSignal_U1/Channel1<4>_MC.D2_PT_0/IN0 )
  );
  X_INV \NlwInverterBlock_U1/Channel1<4>_MC.D2_PT_1/IN1  (
    .I(\U1/U5/location_Maddsub__n0000__n0067 [0]),
    .O(\NlwInverterSignal_U1/Channel1<4>_MC.D2_PT_1/IN1 )
  );
  X_INV \NlwInverterBlock_U1/Channel1<4>_MC.D2_PT_1/IN2  (
    .I(\U1/Channel1 [3]),
    .O(\NlwInverterSignal_U1/Channel1<4>_MC.D2_PT_1/IN2 )
  );
  X_INV \NlwInverterBlock_U1/Channel1<4>_MC.D2_PT_2/IN1  (
    .I(\U1/Zero1 ),
    .O(\NlwInverterSignal_U1/Channel1<4>_MC.D2_PT_2/IN1 )
  );
  X_INV \NlwInverterBlock_U1/Channel1<4>_MC.D2_PT_2/IN3  (
    .I(N_PZ_1016),
    .O(\NlwInverterSignal_U1/Channel1<4>_MC.D2_PT_2/IN3 )
  );
  X_INV \NlwInverterBlock_U1/Channel1<4>_MC.D2_PT_2/IN5  (
    .I(\U1/Channel1 [4]),
    .O(\NlwInverterSignal_U1/Channel1<4>_MC.D2_PT_2/IN5 )
  );
  X_INV \NlwInverterBlock_U1/Channel1<4>_MC.D2_PT_3/IN2  (
    .I(\U1/U5/location_Maddsub__n0000__n0067 [0]),
    .O(\NlwInverterSignal_U1/Channel1<4>_MC.D2_PT_3/IN2 )
  );
  X_INV \NlwInverterBlock_U1/Channel1<4>_MC.D2_PT_4/IN0  (
    .I(\U1/Channel1 [0]),
    .O(\NlwInverterSignal_U1/Channel1<4>_MC.D2_PT_4/IN0 )
  );
  X_INV \NlwInverterBlock_U1/Channel1<4>_MC.D2_PT_4/IN2  (
    .I(\U1/U5/location_Maddsub__n0000__n0067 [0]),
    .O(\NlwInverterSignal_U1/Channel1<4>_MC.D2_PT_4/IN2 )
  );
  X_INV \NlwInverterBlock_U1/Channel1<4>_MC.D2_PT_4/IN3  (
    .I(\U1/Channel1 [1]),
    .O(\NlwInverterSignal_U1/Channel1<4>_MC.D2_PT_4/IN3 )
  );
  X_INV \NlwInverterBlock_U1/Channel1<4>_MC.D2_PT_4/IN4  (
    .I(\U1/Channel1 [2]),
    .O(\NlwInverterSignal_U1/Channel1<4>_MC.D2_PT_4/IN4 )
  );
  X_INV \NlwInverterBlock_U1/Channel1<4>_MC.D2_PT_4/IN5  (
    .I(\U1/Channel1 [3]),
    .O(\NlwInverterSignal_U1/Channel1<4>_MC.D2_PT_4/IN5 )
  );
  X_INV \NlwInverterBlock_U1/Channel1<4>_MC.D2_PT_5/IN2  (
    .I(\U1/Zero1 ),
    .O(\NlwInverterSignal_U1/Channel1<4>_MC.D2_PT_5/IN2 )
  );
  X_INV \NlwInverterBlock_U1/Channel1<4>_MC.D2_PT_5/IN8  (
    .I(\U1/Channel1 [4]),
    .O(\NlwInverterSignal_U1/Channel1<4>_MC.D2_PT_5/IN8 )
  );
  X_INV \NlwInverterBlock_U1/Channel1<6>_MC.D2_PT_0/IN0  (
    .I(N_PZ_933),
    .O(\NlwInverterSignal_U1/Channel1<6>_MC.D2_PT_0/IN0 )
  );
  X_INV \NlwInverterBlock_U1/Channel1<6>_MC.D2_PT_1/IN1  (
    .I(\U1/Zero1 ),
    .O(\NlwInverterSignal_U1/Channel1<6>_MC.D2_PT_1/IN1 )
  );
  X_INV \NlwInverterBlock_U1/Channel1<6>_MC.D2_PT_1/IN4  (
    .I(\U1/U5/location_Maddsub__n0000__n0067 [0]),
    .O(\NlwInverterSignal_U1/Channel1<6>_MC.D2_PT_1/IN4 )
  );
  X_INV \NlwInverterBlock_U1/Channel1<6>_MC.D2_PT_2/IN1  (
    .I(\U1/Zero1 ),
    .O(\NlwInverterSignal_U1/Channel1<6>_MC.D2_PT_2/IN1 )
  );
  X_INV \NlwInverterBlock_U1/Channel1<6>_MC.D2_PT_2/IN3  (
    .I(N_PZ_1016),
    .O(\NlwInverterSignal_U1/Channel1<6>_MC.D2_PT_2/IN3 )
  );
  X_INV \NlwInverterBlock_U1/Channel1<6>_MC.D2_PT_2/IN4  (
    .I(\U1/Channel1 [5]),
    .O(\NlwInverterSignal_U1/Channel1<6>_MC.D2_PT_2/IN4 )
  );
  X_INV \NlwInverterBlock_U1/Channel1<7>_MC.D2_PT_0/IN0  (
    .I(N_PZ_933),
    .O(\NlwInverterSignal_U1/Channel1<7>_MC.D2_PT_0/IN0 )
  );
  X_INV \NlwInverterBlock_U1/Channel1<7>_MC.D2_PT_1/IN1  (
    .I(\U1/Zero1 ),
    .O(\NlwInverterSignal_U1/Channel1<7>_MC.D2_PT_1/IN1 )
  );
  X_INV \NlwInverterBlock_U1/Channel1<7>_MC.D2_PT_1/IN4  (
    .I(\U1/U5/location_Maddsub__n0000__n0067 [0]),
    .O(\NlwInverterSignal_U1/Channel1<7>_MC.D2_PT_1/IN4 )
  );
  X_INV \NlwInverterBlock_U1/Channel1<7>_MC.D2_PT_2/IN1  (
    .I(\U1/Zero1 ),
    .O(\NlwInverterSignal_U1/Channel1<7>_MC.D2_PT_2/IN1 )
  );
  X_INV \NlwInverterBlock_U1/Channel1<7>_MC.D2_PT_2/IN3  (
    .I(N_PZ_1016),
    .O(\NlwInverterSignal_U1/Channel1<7>_MC.D2_PT_2/IN3 )
  );
  X_INV \NlwInverterBlock_U1/Channel1<7>_MC.D2_PT_2/IN4  (
    .I(\U1/Channel1 [5]),
    .O(\NlwInverterSignal_U1/Channel1<7>_MC.D2_PT_2/IN4 )
  );
  X_INV \NlwInverterBlock_U1/Channel1<7>_MC.D2_PT_2/IN6  (
    .I(\U1/Channel1 [6]),
    .O(\NlwInverterSignal_U1/Channel1<7>_MC.D2_PT_2/IN6 )
  );
  X_INV \NlwInverterBlock_U1/U5/location_Maddsub__n0000__n0075<0>_MC.D2_PT_0/IN3  (
    .I(\U1/U5/location_Maddsub__n0000__n0067 [0]),
    .O(\NlwInverterSignal_U1/U5/location_Maddsub__n0000__n0075<0>_MC.D2_PT_0/IN3 )
  );
  X_INV \NlwInverterBlock_U1/U5/location_Maddsub__n0000__n0075<0>_MC.D2_PT_1/IN0  (
    .I(\U1/Channel1 [8]),
    .O(\NlwInverterSignal_U1/U5/location_Maddsub__n0000__n0075<0>_MC.D2_PT_1/IN0 )
  );
  X_INV \NlwInverterBlock_U1/U5/location_Maddsub__n0000__n0075<0>_MC.D2_PT_1/IN1  (
    .I(\U1/Channel1 [7]),
    .O(\NlwInverterSignal_U1/U5/location_Maddsub__n0000__n0075<0>_MC.D2_PT_1/IN1 )
  );
  X_INV \NlwInverterBlock_U1/U5/location_Maddsub__n0000__n0075<0>_MC.D2_PT_1/IN2  (
    .I(\U1/Channel1 [5]),
    .O(\NlwInverterSignal_U1/U5/location_Maddsub__n0000__n0075<0>_MC.D2_PT_1/IN2 )
  );
  X_INV \NlwInverterBlock_U1/U5/location_Maddsub__n0000__n0075<0>_MC.D2_PT_1/IN4  (
    .I(\U1/Channel1 [6]),
    .O(\NlwInverterSignal_U1/U5/location_Maddsub__n0000__n0075<0>_MC.D2_PT_1/IN4 )
  );
  X_INV \NlwInverterBlock_U1/U5/location_Maddsub__n0000__n0075<0>_MC.D2_PT_1/IN5  (
    .I(N_PZ_946),
    .O(\NlwInverterSignal_U1/U5/location_Maddsub__n0000__n0075<0>_MC.D2_PT_1/IN5 )
  );
  X_INV \NlwInverterBlock_outDATA<0>\$WA5.UIM_MC.D2_PT_1/IN0  (
    .I(DCOR0CNTLOWr),
    .O(\NlwInverterSignal_outDATA<0>\$WA5.UIM_MC.D2_PT_1/IN0 )
  );
  X_INV \NlwInverterBlock_outDATA<0>\$WA5.UIM_MC.D2_PT_2/IN0  (
    .I(DCOR0CNTLOWr),
    .O(\NlwInverterSignal_outDATA<0>\$WA5.UIM_MC.D2_PT_2/IN0 )
  );
  X_INV \NlwInverterBlock_outDATA<0>\$WA5.UIM_MC.D2_PT_2/IN1  (
    .I(DCOR1CNTLOWr),
    .O(\NlwInverterSignal_outDATA<0>\$WA5.UIM_MC.D2_PT_2/IN1 )
  );
  X_INV \NlwInverterBlock_outDATA<0>\$WA5.UIM_MC.D2_PT_3/IN0  (
    .I(DCOR0CNTLOWr),
    .O(\NlwInverterSignal_outDATA<0>\$WA5.UIM_MC.D2_PT_3/IN0 )
  );
  X_INV \NlwInverterBlock_outDATA<0>\$WA5.UIM_MC.D2_PT_3/IN1  (
    .I(DCOR1CNTLOWr),
    .O(\NlwInverterSignal_outDATA<0>\$WA5.UIM_MC.D2_PT_3/IN1 )
  );
  X_INV \NlwInverterBlock_outDATA<0>\$WA5.UIM_MC.D2_PT_3/IN2  (
    .I(DCOR0CNTHIGHr),
    .O(\NlwInverterSignal_outDATA<0>\$WA5.UIM_MC.D2_PT_3/IN2 )
  );
  X_INV \NlwInverterBlock_U1/U3/holdingreg0<0>_MC.D2_PT_1/IN1  (
    .I(\AS_II/UIM ),
    .O(\NlwInverterSignal_U1/U3/holdingreg0<0>_MC.D2_PT_1/IN1 )
  );
  X_INV \NlwInverterBlock_DCOR0CNTLOWr_MC.D1/IN1  (
    .I(\RD_II/UIM ),
    .O(\NlwInverterSignal_DCOR0CNTLOWr_MC.D1/IN1 )
  );
  X_INV \NlwInverterBlock_DCOR0CNTLOWr_MC.D1/IN2  (
    .I(U2_ADDR_reg[0]),
    .O(\NlwInverterSignal_DCOR0CNTLOWr_MC.D1/IN2 )
  );
  X_INV \NlwInverterBlock_DCOR0CNTLOWr_MC.D1/IN3  (
    .I(U2_ADDR_reg[4]),
    .O(\NlwInverterSignal_DCOR0CNTLOWr_MC.D1/IN3 )
  );
  X_INV \NlwInverterBlock_DCOR0CNTLOWr_MC.D1/IN4  (
    .I(U2_ADDR_reg[5]),
    .O(\NlwInverterSignal_DCOR0CNTLOWr_MC.D1/IN4 )
  );
  X_INV \NlwInverterBlock_DCOR0CNTLOWr_MC.D1/IN5  (
    .I(U2_ADDR_reg[6]),
    .O(\NlwInverterSignal_DCOR0CNTLOWr_MC.D1/IN5 )
  );
  X_INV \NlwInverterBlock_DCOR0CNTLOWr_MC.D1/IN6  (
    .I(U2_ADDR_reg[7]),
    .O(\NlwInverterSignal_DCOR0CNTLOWr_MC.D1/IN6 )
  );
  X_INV \NlwInverterBlock_DCOR0CNTLOWr_MC.D1/IN7  (
    .I(U2_ADDR_reg[3]),
    .O(\NlwInverterSignal_DCOR0CNTLOWr_MC.D1/IN7 )
  );
  X_INV \NlwInverterBlock_DCOR0CNTLOWr_MC.D1/IN8  (
    .I(U2_ADDR_reg[1]),
    .O(\NlwInverterSignal_DCOR0CNTLOWr_MC.D1/IN8 )
  );
  X_INV \NlwInverterBlock_U1/U3/holdingreg1<0>_MC.D2_PT_1/IN1  (
    .I(\AS_II/UIM ),
    .O(\NlwInverterSignal_U1/U3/holdingreg1<0>_MC.D2_PT_1/IN1 )
  );
  X_INV \NlwInverterBlock_DCOR1CNTLOWr_MC.D1/IN1  (
    .I(\RD_II/UIM ),
    .O(\NlwInverterSignal_DCOR1CNTLOWr_MC.D1/IN1 )
  );
  X_INV \NlwInverterBlock_DCOR1CNTLOWr_MC.D1/IN2  (
    .I(U2_ADDR_reg[0]),
    .O(\NlwInverterSignal_DCOR1CNTLOWr_MC.D1/IN2 )
  );
  X_INV \NlwInverterBlock_DCOR1CNTLOWr_MC.D1/IN3  (
    .I(U2_ADDR_reg[4]),
    .O(\NlwInverterSignal_DCOR1CNTLOWr_MC.D1/IN3 )
  );
  X_INV \NlwInverterBlock_DCOR1CNTLOWr_MC.D1/IN4  (
    .I(U2_ADDR_reg[5]),
    .O(\NlwInverterSignal_DCOR1CNTLOWr_MC.D1/IN4 )
  );
  X_INV \NlwInverterBlock_DCOR1CNTLOWr_MC.D1/IN5  (
    .I(U2_ADDR_reg[6]),
    .O(\NlwInverterSignal_DCOR1CNTLOWr_MC.D1/IN5 )
  );
  X_INV \NlwInverterBlock_DCOR1CNTLOWr_MC.D1/IN6  (
    .I(U2_ADDR_reg[7]),
    .O(\NlwInverterSignal_DCOR1CNTLOWr_MC.D1/IN6 )
  );
  X_INV \NlwInverterBlock_DCOR1CNTLOWr_MC.D1/IN7  (
    .I(U2_ADDR_reg[3]),
    .O(\NlwInverterSignal_DCOR1CNTLOWr_MC.D1/IN7 )
  );
  X_INV \NlwInverterBlock_U1/U3/holdingreg0<8>_MC.D2_PT_1/IN1  (
    .I(\AS_II/UIM ),
    .O(\NlwInverterSignal_U1/U3/holdingreg0<8>_MC.D2_PT_1/IN1 )
  );
  X_INV \NlwInverterBlock_DCOR0CNTHIGHr_MC.D1/IN1  (
    .I(\RD_II/UIM ),
    .O(\NlwInverterSignal_DCOR0CNTHIGHr_MC.D1/IN1 )
  );
  X_INV \NlwInverterBlock_DCOR0CNTHIGHr_MC.D1/IN3  (
    .I(U2_ADDR_reg[4]),
    .O(\NlwInverterSignal_DCOR0CNTHIGHr_MC.D1/IN3 )
  );
  X_INV \NlwInverterBlock_DCOR0CNTHIGHr_MC.D1/IN4  (
    .I(U2_ADDR_reg[5]),
    .O(\NlwInverterSignal_DCOR0CNTHIGHr_MC.D1/IN4 )
  );
  X_INV \NlwInverterBlock_DCOR0CNTHIGHr_MC.D1/IN5  (
    .I(U2_ADDR_reg[6]),
    .O(\NlwInverterSignal_DCOR0CNTHIGHr_MC.D1/IN5 )
  );
  X_INV \NlwInverterBlock_DCOR0CNTHIGHr_MC.D1/IN6  (
    .I(U2_ADDR_reg[7]),
    .O(\NlwInverterSignal_DCOR0CNTHIGHr_MC.D1/IN6 )
  );
  X_INV \NlwInverterBlock_DCOR0CNTHIGHr_MC.D1/IN7  (
    .I(U2_ADDR_reg[3]),
    .O(\NlwInverterSignal_DCOR0CNTHIGHr_MC.D1/IN7 )
  );
  X_INV \NlwInverterBlock_DCOR0CNTHIGHr_MC.D1/IN8  (
    .I(U2_ADDR_reg[1]),
    .O(\NlwInverterSignal_DCOR0CNTHIGHr_MC.D1/IN8 )
  );
  X_INV \NlwInverterBlock_U1/U3/holdingreg1<8>_MC.D2_PT_1/IN1  (
    .I(\AS_II/UIM ),
    .O(\NlwInverterSignal_U1/U3/holdingreg1<8>_MC.D2_PT_1/IN1 )
  );
  X_INV \NlwInverterBlock_N_PZ_963_MC.D1/IN0  (
    .I(DCOR0CNTLOWr),
    .O(\NlwInverterSignal_N_PZ_963_MC.D1/IN0 )
  );
  X_INV \NlwInverterBlock_N_PZ_963_MC.D1/IN1  (
    .I(DCOR1CNTLOWr),
    .O(\NlwInverterSignal_N_PZ_963_MC.D1/IN1 )
  );
  X_INV \NlwInverterBlock_N_PZ_963_MC.D1/IN2  (
    .I(DCOR0CNTHIGHr),
    .O(\NlwInverterSignal_N_PZ_963_MC.D1/IN2 )
  );
  X_INV \NlwInverterBlock_N_PZ_963_MC.D1/IN3  (
    .I(DCOR1CNTHIGHr),
    .O(\NlwInverterSignal_N_PZ_963_MC.D1/IN3 )
  );
  X_INV \NlwInverterBlock_DCOR1CNTHIGHr_MC.D1/IN1  (
    .I(\RD_II/UIM ),
    .O(\NlwInverterSignal_DCOR1CNTHIGHr_MC.D1/IN1 )
  );
  X_INV \NlwInverterBlock_DCOR1CNTHIGHr_MC.D1/IN3  (
    .I(U2_ADDR_reg[4]),
    .O(\NlwInverterSignal_DCOR1CNTHIGHr_MC.D1/IN3 )
  );
  X_INV \NlwInverterBlock_DCOR1CNTHIGHr_MC.D1/IN4  (
    .I(U2_ADDR_reg[5]),
    .O(\NlwInverterSignal_DCOR1CNTHIGHr_MC.D1/IN4 )
  );
  X_INV \NlwInverterBlock_DCOR1CNTHIGHr_MC.D1/IN5  (
    .I(U2_ADDR_reg[6]),
    .O(\NlwInverterSignal_DCOR1CNTHIGHr_MC.D1/IN5 )
  );
  X_INV \NlwInverterBlock_DCOR1CNTHIGHr_MC.D1/IN6  (
    .I(U2_ADDR_reg[7]),
    .O(\NlwInverterSignal_DCOR1CNTHIGHr_MC.D1/IN6 )
  );
  X_INV \NlwInverterBlock_DCOR1CNTHIGHr_MC.D1/IN7  (
    .I(U2_ADDR_reg[3]),
    .O(\NlwInverterSignal_DCOR1CNTHIGHr_MC.D1/IN7 )
  );
  X_INV \NlwInverterBlock_N_PZ_980_MC.D1/IN0  (
    .I(DCORIFGr),
    .O(\NlwInverterSignal_N_PZ_980_MC.D1/IN0 )
  );
  X_INV \NlwInverterBlock_N_PZ_980_MC.D1/IN1  (
    .I(DCOR0THRESLOWr),
    .O(\NlwInverterSignal_N_PZ_980_MC.D1/IN1 )
  );
  X_INV \NlwInverterBlock_N_PZ_980_MC.D1/IN2  (
    .I(DCOR0THRESHIGHr),
    .O(\NlwInverterSignal_N_PZ_980_MC.D1/IN2 )
  );
  X_INV \NlwInverterBlock_N_PZ_980_MC.D1/IN3  (
    .I(DCOR1THRESLOWr),
    .O(\NlwInverterSignal_N_PZ_980_MC.D1/IN3 )
  );
  X_INV \NlwInverterBlock_N_PZ_980_MC.D1/IN4  (
    .I(DCOR1THRESHIGHr),
    .O(\NlwInverterSignal_N_PZ_980_MC.D1/IN4 )
  );
  X_INV \NlwInverterBlock_DCOR1THRESHIGHr_MC.D1/IN1  (
    .I(\RD_II/UIM ),
    .O(\NlwInverterSignal_DCOR1THRESHIGHr_MC.D1/IN1 )
  );
  X_INV \NlwInverterBlock_DCOR1THRESHIGHr_MC.D1/IN3  (
    .I(U2_ADDR_reg[4]),
    .O(\NlwInverterSignal_DCOR1THRESHIGHr_MC.D1/IN3 )
  );
  X_INV \NlwInverterBlock_DCOR1THRESHIGHr_MC.D1/IN4  (
    .I(U2_ADDR_reg[5]),
    .O(\NlwInverterSignal_DCOR1THRESHIGHr_MC.D1/IN4 )
  );
  X_INV \NlwInverterBlock_DCOR1THRESHIGHr_MC.D1/IN5  (
    .I(U2_ADDR_reg[6]),
    .O(\NlwInverterSignal_DCOR1THRESHIGHr_MC.D1/IN5 )
  );
  X_INV \NlwInverterBlock_DCOR1THRESHIGHr_MC.D1/IN6  (
    .I(U2_ADDR_reg[7]),
    .O(\NlwInverterSignal_DCOR1THRESHIGHr_MC.D1/IN6 )
  );
  X_INV \NlwInverterBlock_DCOR1THRESHIGHr_MC.D1/IN9  (
    .I(U2_ADDR_reg[2]),
    .O(\NlwInverterSignal_DCOR1THRESHIGHr_MC.D1/IN9 )
  );
  X_INV \NlwInverterBlock_outDATA<1>\$WA3.UIM_MC.D2_PT_0/IN0  (
    .I(DCORENCPWRr),
    .O(\NlwInverterSignal_outDATA<1>\$WA3.UIM_MC.D2_PT_0/IN0 )
  );
  X_INV \NlwInverterBlock_outDATA<1>\$WA3.UIM_MC.D2_PT_2/IN1  (
    .I(NET2528),
    .O(\NlwInverterSignal_outDATA<1>\$WA3.UIM_MC.D2_PT_2/IN1 )
  );
  X_INV \NlwInverterBlock_outDATA<1>\$WA6.UIM_MC.D2_PT_1/IN0  (
    .I(DCOR0THRESLOWr),
    .O(\NlwInverterSignal_outDATA<1>\$WA6.UIM_MC.D2_PT_1/IN0 )
  );
  X_INV \NlwInverterBlock_outDATA<1>\$WA6.UIM_MC.D2_PT_2/IN0  (
    .I(DCOR0THRESLOWr),
    .O(\NlwInverterSignal_outDATA<1>\$WA6.UIM_MC.D2_PT_2/IN0 )
  );
  X_INV \NlwInverterBlock_outDATA<1>\$WA6.UIM_MC.D2_PT_2/IN1  (
    .I(DCOR0THRESHIGHr),
    .O(\NlwInverterSignal_outDATA<1>\$WA6.UIM_MC.D2_PT_2/IN1 )
  );
  X_INV \NlwInverterBlock_outDATA<1>\$WA6.UIM_MC.D2_PT_3/IN0  (
    .I(DCOR0THRESLOWr),
    .O(\NlwInverterSignal_outDATA<1>\$WA6.UIM_MC.D2_PT_3/IN0 )
  );
  X_INV \NlwInverterBlock_outDATA<1>\$WA6.UIM_MC.D2_PT_3/IN1  (
    .I(DCOR0THRESHIGHr),
    .O(\NlwInverterSignal_outDATA<1>\$WA6.UIM_MC.D2_PT_3/IN1 )
  );
  X_INV \NlwInverterBlock_outDATA<1>\$WA6.UIM_MC.D2_PT_3/IN2  (
    .I(DCOR1THRESLOWr),
    .O(\NlwInverterSignal_outDATA<1>\$WA6.UIM_MC.D2_PT_3/IN2 )
  );
  X_INV \NlwInverterBlock_U1/U4/Latch0r<1>_MC.D2_PT_1/IN1  (
    .I(N_PZ_965),
    .O(\NlwInverterSignal_U1/U4/Latch0r<1>_MC.D2_PT_1/IN1 )
  );
  X_INV \NlwInverterBlock_U1/U4/Latch0r<9>_MC.D2_PT_1/IN1  (
    .I(N_PZ_965),
    .O(\NlwInverterSignal_U1/U4/Latch0r<9>_MC.D2_PT_1/IN1 )
  );
  X_INV \NlwInverterBlock_U1/Channel0<9>_MC.D2_PT_0/IN0  (
    .I(N_PZ_931),
    .O(\NlwInverterSignal_U1/Channel0<9>_MC.D2_PT_0/IN0 )
  );
  X_INV \NlwInverterBlock_U1/Channel0<9>_MC.D2_PT_2/IN0  (
    .I(\U1/U2/location_Maddsub__n0000__n0075 [0]),
    .O(\NlwInverterSignal_U1/Channel0<9>_MC.D2_PT_2/IN0 )
  );
  X_INV \NlwInverterBlock_U1/U4/Latch1r<1>_MC.D2_PT_1/IN1  (
    .I(DCORIFGw),
    .O(\NlwInverterSignal_U1/U4/Latch1r<1>_MC.D2_PT_1/IN1 )
  );
  X_INV \NlwInverterBlock_U1/U4/Latch1r<1>_MC.D2_PT_1/IN2  (
    .I(DCORENCCTLw),
    .O(\NlwInverterSignal_U1/U4/Latch1r<1>_MC.D2_PT_1/IN2 )
  );
  X_INV \NlwInverterBlock_U1/U4/Latch1r<9>_MC.D2_PT_1/IN1  (
    .I(DCORIFGw),
    .O(\NlwInverterSignal_U1/U4/Latch1r<9>_MC.D2_PT_1/IN1 )
  );
  X_INV \NlwInverterBlock_U1/U4/Latch1r<9>_MC.D2_PT_1/IN2  (
    .I(DCORENCCTLw),
    .O(\NlwInverterSignal_U1/U4/Latch1r<9>_MC.D2_PT_1/IN2 )
  );
  X_INV \NlwInverterBlock_U1/Channel1<9>_MC.D2_PT_0/IN0  (
    .I(N_PZ_933),
    .O(\NlwInverterSignal_U1/Channel1<9>_MC.D2_PT_0/IN0 )
  );
  X_INV \NlwInverterBlock_U1/Channel1<9>_MC.D2_PT_1/IN1  (
    .I(\U1/Zero1 ),
    .O(\NlwInverterSignal_U1/Channel1<9>_MC.D2_PT_1/IN1 )
  );
  X_INV \NlwInverterBlock_U1/Channel1<9>_MC.D2_PT_1/IN3  (
    .I(\U1/U5/location_Maddsub__n0000__n0075 [0]),
    .O(\NlwInverterSignal_U1/Channel1<9>_MC.D2_PT_1/IN3 )
  );
  X_INV \NlwInverterBlock_U1/Channel1<9>_MC.D2_PT_2/IN1  (
    .I(\U1/Zero1 ),
    .O(\NlwInverterSignal_U1/Channel1<9>_MC.D2_PT_2/IN1 )
  );
  X_INV \NlwInverterBlock_U1/Channel1<9>_MC.D2_PT_2/IN3  (
    .I(N_PZ_1016),
    .O(\NlwInverterSignal_U1/Channel1<9>_MC.D2_PT_2/IN3 )
  );
  X_INV \NlwInverterBlock_outDATA<1>\$WA5.UIM_MC.D2_PT_1/IN0  (
    .I(DCOR0CNTLOWr),
    .O(\NlwInverterSignal_outDATA<1>\$WA5.UIM_MC.D2_PT_1/IN0 )
  );
  X_INV \NlwInverterBlock_outDATA<1>\$WA5.UIM_MC.D2_PT_2/IN0  (
    .I(DCOR0CNTLOWr),
    .O(\NlwInverterSignal_outDATA<1>\$WA5.UIM_MC.D2_PT_2/IN0 )
  );
  X_INV \NlwInverterBlock_outDATA<1>\$WA5.UIM_MC.D2_PT_2/IN1  (
    .I(DCOR1CNTLOWr),
    .O(\NlwInverterSignal_outDATA<1>\$WA5.UIM_MC.D2_PT_2/IN1 )
  );
  X_INV \NlwInverterBlock_outDATA<1>\$WA5.UIM_MC.D2_PT_3/IN0  (
    .I(DCOR0CNTLOWr),
    .O(\NlwInverterSignal_outDATA<1>\$WA5.UIM_MC.D2_PT_3/IN0 )
  );
  X_INV \NlwInverterBlock_outDATA<1>\$WA5.UIM_MC.D2_PT_3/IN1  (
    .I(DCOR1CNTLOWr),
    .O(\NlwInverterSignal_outDATA<1>\$WA5.UIM_MC.D2_PT_3/IN1 )
  );
  X_INV \NlwInverterBlock_outDATA<1>\$WA5.UIM_MC.D2_PT_3/IN2  (
    .I(DCOR0CNTHIGHr),
    .O(\NlwInverterSignal_outDATA<1>\$WA5.UIM_MC.D2_PT_3/IN2 )
  );
  X_INV \NlwInverterBlock_U1/U3/holdingreg0<1>_MC.D2_PT_1/IN1  (
    .I(\AS_II/UIM ),
    .O(\NlwInverterSignal_U1/U3/holdingreg0<1>_MC.D2_PT_1/IN1 )
  );
  X_INV \NlwInverterBlock_U1/U3/holdingreg1<1>_MC.D2_PT_1/IN1  (
    .I(\AS_II/UIM ),
    .O(\NlwInverterSignal_U1/U3/holdingreg1<1>_MC.D2_PT_1/IN1 )
  );
  X_INV \NlwInverterBlock_U1/U3/holdingreg0<9>_MC.D2_PT_1/IN1  (
    .I(\AS_II/UIM ),
    .O(\NlwInverterSignal_U1/U3/holdingreg0<9>_MC.D2_PT_1/IN1 )
  );
  X_INV \NlwInverterBlock_U1/U3/holdingreg1<9>_MC.D2_PT_1/IN1  (
    .I(\AS_II/UIM ),
    .O(\NlwInverterSignal_U1/U3/holdingreg1<9>_MC.D2_PT_1/IN1 )
  );
  X_INV \NlwInverterBlock_outDATA<2>\$WA3.UIM_MC.D2_PT_1/IN0  (
    .I(NET2528),
    .O(\NlwInverterSignal_outDATA<2>\$WA3.UIM_MC.D2_PT_1/IN0 )
  );
  X_INV \NlwInverterBlock_outDATA<2>\$WA5.UIM_MC.D2_PT_1/IN0  (
    .I(DCOR0CNTLOWr),
    .O(\NlwInverterSignal_outDATA<2>\$WA5.UIM_MC.D2_PT_1/IN0 )
  );
  X_INV \NlwInverterBlock_outDATA<2>\$WA5.UIM_MC.D2_PT_2/IN0  (
    .I(DCOR0CNTLOWr),
    .O(\NlwInverterSignal_outDATA<2>\$WA5.UIM_MC.D2_PT_2/IN0 )
  );
  X_INV \NlwInverterBlock_outDATA<2>\$WA5.UIM_MC.D2_PT_2/IN1  (
    .I(DCOR1CNTLOWr),
    .O(\NlwInverterSignal_outDATA<2>\$WA5.UIM_MC.D2_PT_2/IN1 )
  );
  X_INV \NlwInverterBlock_outDATA<2>\$WA5.UIM_MC.D2_PT_3/IN0  (
    .I(DCOR0CNTLOWr),
    .O(\NlwInverterSignal_outDATA<2>\$WA5.UIM_MC.D2_PT_3/IN0 )
  );
  X_INV \NlwInverterBlock_outDATA<2>\$WA5.UIM_MC.D2_PT_3/IN1  (
    .I(DCOR1CNTLOWr),
    .O(\NlwInverterSignal_outDATA<2>\$WA5.UIM_MC.D2_PT_3/IN1 )
  );
  X_INV \NlwInverterBlock_outDATA<2>\$WA5.UIM_MC.D2_PT_3/IN2  (
    .I(DCOR0CNTHIGHr),
    .O(\NlwInverterSignal_outDATA<2>\$WA5.UIM_MC.D2_PT_3/IN2 )
  );
  X_INV \NlwInverterBlock_U1/U3/holdingreg0<2>_MC.D2_PT_1/IN1  (
    .I(\AS_II/UIM ),
    .O(\NlwInverterSignal_U1/U3/holdingreg0<2>_MC.D2_PT_1/IN1 )
  );
  X_INV \NlwInverterBlock_U1/U3/holdingreg1<2>_MC.D2_PT_1/IN1  (
    .I(\AS_II/UIM ),
    .O(\NlwInverterSignal_U1/U3/holdingreg1<2>_MC.D2_PT_1/IN1 )
  );
  X_INV \NlwInverterBlock_U1/U3/holdingreg0<10>_MC.D2_PT_1/IN1  (
    .I(\AS_II/UIM ),
    .O(\NlwInverterSignal_U1/U3/holdingreg0<10>_MC.D2_PT_1/IN1 )
  );
  X_INV \NlwInverterBlock_U1/Channel0<10>_MC.D2_PT_0/IN0  (
    .I(N_PZ_931),
    .O(\NlwInverterSignal_U1/Channel0<10>_MC.D2_PT_0/IN0 )
  );
  X_INV \NlwInverterBlock_U1/Channel0<10>_MC.D2_PT_1/IN2  (
    .I(\U1/Channel0 [9]),
    .O(\NlwInverterSignal_U1/Channel0<10>_MC.D2_PT_1/IN2 )
  );
  X_INV \NlwInverterBlock_U1/Channel0<10>_MC.D2_PT_2/IN0  (
    .I(\U1/U2/location_Maddsub__n0000__n0075 [0]),
    .O(\NlwInverterSignal_U1/Channel0<10>_MC.D2_PT_2/IN0 )
  );
  X_INV \NlwInverterBlock_U1/U3/holdingreg1<10>_MC.D2_PT_1/IN1  (
    .I(\AS_II/UIM ),
    .O(\NlwInverterSignal_U1/U3/holdingreg1<10>_MC.D2_PT_1/IN1 )
  );
  X_INV \NlwInverterBlock_U1/Channel1<10>_MC.D2_PT_0/IN0  (
    .I(N_PZ_933),
    .O(\NlwInverterSignal_U1/Channel1<10>_MC.D2_PT_0/IN0 )
  );
  X_INV \NlwInverterBlock_U1/Channel1<10>_MC.D2_PT_1/IN1  (
    .I(\U1/Zero1 ),
    .O(\NlwInverterSignal_U1/Channel1<10>_MC.D2_PT_1/IN1 )
  );
  X_INV \NlwInverterBlock_U1/Channel1<10>_MC.D2_PT_1/IN3  (
    .I(\U1/U5/location_Maddsub__n0000__n0075 [0]),
    .O(\NlwInverterSignal_U1/Channel1<10>_MC.D2_PT_1/IN3 )
  );
  X_INV \NlwInverterBlock_U1/Channel1<10>_MC.D2_PT_2/IN1  (
    .I(\U1/Zero1 ),
    .O(\NlwInverterSignal_U1/Channel1<10>_MC.D2_PT_2/IN1 )
  );
  X_INV \NlwInverterBlock_U1/Channel1<10>_MC.D2_PT_2/IN3  (
    .I(N_PZ_1016),
    .O(\NlwInverterSignal_U1/Channel1<10>_MC.D2_PT_2/IN3 )
  );
  X_INV \NlwInverterBlock_U1/Channel1<10>_MC.D2_PT_2/IN5  (
    .I(\U1/Channel1 [9]),
    .O(\NlwInverterSignal_U1/Channel1<10>_MC.D2_PT_2/IN5 )
  );
  X_INV \NlwInverterBlock_outDATA<2>\$WA6.UIM_MC.D2_PT_1/IN1  (
    .I(DCOR0THRESLOWr),
    .O(\NlwInverterSignal_outDATA<2>\$WA6.UIM_MC.D2_PT_1/IN1 )
  );
  X_INV \NlwInverterBlock_outDATA<2>\$WA6.UIM_MC.D2_PT_2/IN0  (
    .I(DCORIFGr),
    .O(\NlwInverterSignal_outDATA<2>\$WA6.UIM_MC.D2_PT_2/IN0 )
  );
  X_INV \NlwInverterBlock_outDATA<2>\$WA6.UIM_MC.D2_PT_2/IN1  (
    .I(DCOR0THRESLOWr),
    .O(\NlwInverterSignal_outDATA<2>\$WA6.UIM_MC.D2_PT_2/IN1 )
  );
  X_INV \NlwInverterBlock_outDATA<2>\$WA6.UIM_MC.D2_PT_3/IN0  (
    .I(DCORIFGr),
    .O(\NlwInverterSignal_outDATA<2>\$WA6.UIM_MC.D2_PT_3/IN0 )
  );
  X_INV \NlwInverterBlock_outDATA<2>\$WA6.UIM_MC.D2_PT_3/IN1  (
    .I(DCOR0THRESLOWr),
    .O(\NlwInverterSignal_outDATA<2>\$WA6.UIM_MC.D2_PT_3/IN1 )
  );
  X_INV \NlwInverterBlock_outDATA<2>\$WA6.UIM_MC.D2_PT_3/IN2  (
    .I(DCOR0THRESHIGHr),
    .O(\NlwInverterSignal_outDATA<2>\$WA6.UIM_MC.D2_PT_3/IN2 )
  );
  X_INV \NlwInverterBlock_outDATA<2>\$WA6.UIM_MC.D2_PT_4/IN0  (
    .I(DCORIFGr),
    .O(\NlwInverterSignal_outDATA<2>\$WA6.UIM_MC.D2_PT_4/IN0 )
  );
  X_INV \NlwInverterBlock_outDATA<2>\$WA6.UIM_MC.D2_PT_4/IN1  (
    .I(DCOR0THRESLOWr),
    .O(\NlwInverterSignal_outDATA<2>\$WA6.UIM_MC.D2_PT_4/IN1 )
  );
  X_INV \NlwInverterBlock_outDATA<2>\$WA6.UIM_MC.D2_PT_4/IN2  (
    .I(DCOR0THRESHIGHr),
    .O(\NlwInverterSignal_outDATA<2>\$WA6.UIM_MC.D2_PT_4/IN2 )
  );
  X_INV \NlwInverterBlock_outDATA<2>\$WA6.UIM_MC.D2_PT_4/IN3  (
    .I(DCOR1THRESLOWr),
    .O(\NlwInverterSignal_outDATA<2>\$WA6.UIM_MC.D2_PT_4/IN3 )
  );
  X_INV \NlwInverterBlock_U1/U4/Latch0r<2>_MC.D2_PT_1/IN1  (
    .I(N_PZ_965),
    .O(\NlwInverterSignal_U1/U4/Latch0r<2>_MC.D2_PT_1/IN1 )
  );
  X_INV \NlwInverterBlock_U1/U4/Latch0r<10>_MC.D2_PT_1/IN1  (
    .I(N_PZ_965),
    .O(\NlwInverterSignal_U1/U4/Latch0r<10>_MC.D2_PT_1/IN1 )
  );
  X_INV \NlwInverterBlock_U1/U4/Latch1r<2>_MC.D2_PT_1/IN1  (
    .I(DCORIFGw),
    .O(\NlwInverterSignal_U1/U4/Latch1r<2>_MC.D2_PT_1/IN1 )
  );
  X_INV \NlwInverterBlock_U1/U4/Latch1r<2>_MC.D2_PT_1/IN2  (
    .I(DCORENCCTLw),
    .O(\NlwInverterSignal_U1/U4/Latch1r<2>_MC.D2_PT_1/IN2 )
  );
  X_INV \NlwInverterBlock_U1/U4/Latch1r<10>_MC.D2_PT_1/IN1  (
    .I(DCORIFGw),
    .O(\NlwInverterSignal_U1/U4/Latch1r<10>_MC.D2_PT_1/IN1 )
  );
  X_INV \NlwInverterBlock_U1/U4/Latch1r<10>_MC.D2_PT_1/IN2  (
    .I(DCORENCCTLw),
    .O(\NlwInverterSignal_U1/U4/Latch1r<10>_MC.D2_PT_1/IN2 )
  );
  X_INV \NlwInverterBlock_outDATA<3>\$WA3.UIM_MC.D2_PT_1/IN0  (
    .I(NET2528),
    .O(\NlwInverterSignal_outDATA<3>\$WA3.UIM_MC.D2_PT_1/IN0 )
  );
  X_INV \NlwInverterBlock_outDATA<3>\$WA5.UIM_MC.D2_PT_1/IN0  (
    .I(DCOR0CNTLOWr),
    .O(\NlwInverterSignal_outDATA<3>\$WA5.UIM_MC.D2_PT_1/IN0 )
  );
  X_INV \NlwInverterBlock_outDATA<3>\$WA5.UIM_MC.D2_PT_2/IN0  (
    .I(DCOR0CNTLOWr),
    .O(\NlwInverterSignal_outDATA<3>\$WA5.UIM_MC.D2_PT_2/IN0 )
  );
  X_INV \NlwInverterBlock_outDATA<3>\$WA5.UIM_MC.D2_PT_2/IN1  (
    .I(DCOR1CNTLOWr),
    .O(\NlwInverterSignal_outDATA<3>\$WA5.UIM_MC.D2_PT_2/IN1 )
  );
  X_INV \NlwInverterBlock_outDATA<3>\$WA5.UIM_MC.D2_PT_3/IN0  (
    .I(DCOR0CNTLOWr),
    .O(\NlwInverterSignal_outDATA<3>\$WA5.UIM_MC.D2_PT_3/IN0 )
  );
  X_INV \NlwInverterBlock_outDATA<3>\$WA5.UIM_MC.D2_PT_3/IN1  (
    .I(DCOR1CNTLOWr),
    .O(\NlwInverterSignal_outDATA<3>\$WA5.UIM_MC.D2_PT_3/IN1 )
  );
  X_INV \NlwInverterBlock_outDATA<3>\$WA5.UIM_MC.D2_PT_3/IN2  (
    .I(DCOR0CNTHIGHr),
    .O(\NlwInverterSignal_outDATA<3>\$WA5.UIM_MC.D2_PT_3/IN2 )
  );
  X_INV \NlwInverterBlock_U1/U3/holdingreg0<3>_MC.D2_PT_1/IN1  (
    .I(\AS_II/UIM ),
    .O(\NlwInverterSignal_U1/U3/holdingreg0<3>_MC.D2_PT_1/IN1 )
  );
  X_INV \NlwInverterBlock_U1/U3/holdingreg1<3>_MC.D2_PT_1/IN1  (
    .I(\AS_II/UIM ),
    .O(\NlwInverterSignal_U1/U3/holdingreg1<3>_MC.D2_PT_1/IN1 )
  );
  X_INV \NlwInverterBlock_U1/U3/holdingreg0<11>_MC.D2_PT_1/IN1  (
    .I(\AS_II/UIM ),
    .O(\NlwInverterSignal_U1/U3/holdingreg0<11>_MC.D2_PT_1/IN1 )
  );
  X_INV \NlwInverterBlock_U1/Channel0<11>_MC.D2_PT_0/IN0  (
    .I(N_PZ_931),
    .O(\NlwInverterSignal_U1/Channel0<11>_MC.D2_PT_0/IN0 )
  );
  X_INV \NlwInverterBlock_U1/Channel0<11>_MC.D2_PT_1/IN2  (
    .I(\U1/Channel0 [9]),
    .O(\NlwInverterSignal_U1/Channel0<11>_MC.D2_PT_1/IN2 )
  );
  X_INV \NlwInverterBlock_U1/Channel0<11>_MC.D2_PT_1/IN3  (
    .I(\U1/Channel0 [10]),
    .O(\NlwInverterSignal_U1/Channel0<11>_MC.D2_PT_1/IN3 )
  );
  X_INV \NlwInverterBlock_U1/Channel0<11>_MC.D2_PT_2/IN0  (
    .I(\U1/U2/location_Maddsub__n0000__n0075 [0]),
    .O(\NlwInverterSignal_U1/Channel0<11>_MC.D2_PT_2/IN0 )
  );
  X_INV \NlwInverterBlock_U1/U3/holdingreg1<11>_MC.D2_PT_1/IN1  (
    .I(\AS_II/UIM ),
    .O(\NlwInverterSignal_U1/U3/holdingreg1<11>_MC.D2_PT_1/IN1 )
  );
  X_INV \NlwInverterBlock_U1/Channel1<11>_MC.D2_PT_0/IN0  (
    .I(N_PZ_933),
    .O(\NlwInverterSignal_U1/Channel1<11>_MC.D2_PT_0/IN0 )
  );
  X_INV \NlwInverterBlock_U1/Channel1<11>_MC.D2_PT_1/IN1  (
    .I(\U1/Zero1 ),
    .O(\NlwInverterSignal_U1/Channel1<11>_MC.D2_PT_1/IN1 )
  );
  X_INV \NlwInverterBlock_U1/Channel1<11>_MC.D2_PT_1/IN3  (
    .I(\U1/U5/location_Maddsub__n0000__n0075 [0]),
    .O(\NlwInverterSignal_U1/Channel1<11>_MC.D2_PT_1/IN3 )
  );
  X_INV \NlwInverterBlock_U1/Channel1<11>_MC.D2_PT_2/IN1  (
    .I(\U1/Zero1 ),
    .O(\NlwInverterSignal_U1/Channel1<11>_MC.D2_PT_2/IN1 )
  );
  X_INV \NlwInverterBlock_U1/Channel1<11>_MC.D2_PT_2/IN3  (
    .I(N_PZ_1016),
    .O(\NlwInverterSignal_U1/Channel1<11>_MC.D2_PT_2/IN3 )
  );
  X_INV \NlwInverterBlock_U1/Channel1<11>_MC.D2_PT_2/IN5  (
    .I(\U1/Channel1 [9]),
    .O(\NlwInverterSignal_U1/Channel1<11>_MC.D2_PT_2/IN5 )
  );
  X_INV \NlwInverterBlock_U1/Channel1<11>_MC.D2_PT_2/IN6  (
    .I(\U1/Channel1 [10]),
    .O(\NlwInverterSignal_U1/Channel1<11>_MC.D2_PT_2/IN6 )
  );
  X_INV \NlwInverterBlock_outDATA<3>\$WA6.UIM_MC.D2_PT_1/IN1  (
    .I(DCOR0THRESLOWr),
    .O(\NlwInverterSignal_outDATA<3>\$WA6.UIM_MC.D2_PT_1/IN1 )
  );
  X_INV \NlwInverterBlock_outDATA<3>\$WA6.UIM_MC.D2_PT_2/IN0  (
    .I(DCORIFGr),
    .O(\NlwInverterSignal_outDATA<3>\$WA6.UIM_MC.D2_PT_2/IN0 )
  );
  X_INV \NlwInverterBlock_outDATA<3>\$WA6.UIM_MC.D2_PT_2/IN1  (
    .I(DCOR0THRESLOWr),
    .O(\NlwInverterSignal_outDATA<3>\$WA6.UIM_MC.D2_PT_2/IN1 )
  );
  X_INV \NlwInverterBlock_outDATA<3>\$WA6.UIM_MC.D2_PT_3/IN0  (
    .I(DCORIFGr),
    .O(\NlwInverterSignal_outDATA<3>\$WA6.UIM_MC.D2_PT_3/IN0 )
  );
  X_INV \NlwInverterBlock_outDATA<3>\$WA6.UIM_MC.D2_PT_3/IN1  (
    .I(DCOR0THRESLOWr),
    .O(\NlwInverterSignal_outDATA<3>\$WA6.UIM_MC.D2_PT_3/IN1 )
  );
  X_INV \NlwInverterBlock_outDATA<3>\$WA6.UIM_MC.D2_PT_3/IN2  (
    .I(DCOR0THRESHIGHr),
    .O(\NlwInverterSignal_outDATA<3>\$WA6.UIM_MC.D2_PT_3/IN2 )
  );
  X_INV \NlwInverterBlock_outDATA<3>\$WA6.UIM_MC.D2_PT_4/IN0  (
    .I(DCORIFGr),
    .O(\NlwInverterSignal_outDATA<3>\$WA6.UIM_MC.D2_PT_4/IN0 )
  );
  X_INV \NlwInverterBlock_outDATA<3>\$WA6.UIM_MC.D2_PT_4/IN1  (
    .I(DCOR0THRESLOWr),
    .O(\NlwInverterSignal_outDATA<3>\$WA6.UIM_MC.D2_PT_4/IN1 )
  );
  X_INV \NlwInverterBlock_outDATA<3>\$WA6.UIM_MC.D2_PT_4/IN2  (
    .I(DCOR0THRESHIGHr),
    .O(\NlwInverterSignal_outDATA<3>\$WA6.UIM_MC.D2_PT_4/IN2 )
  );
  X_INV \NlwInverterBlock_outDATA<3>\$WA6.UIM_MC.D2_PT_4/IN3  (
    .I(DCOR1THRESLOWr),
    .O(\NlwInverterSignal_outDATA<3>\$WA6.UIM_MC.D2_PT_4/IN3 )
  );
  X_INV \NlwInverterBlock_U1/U4/Latch0r<3>_MC.D2_PT_1/IN1  (
    .I(N_PZ_965),
    .O(\NlwInverterSignal_U1/U4/Latch0r<3>_MC.D2_PT_1/IN1 )
  );
  X_INV \NlwInverterBlock_U1/U4/Latch0r<11>_MC.D2_PT_1/IN1  (
    .I(N_PZ_965),
    .O(\NlwInverterSignal_U1/U4/Latch0r<11>_MC.D2_PT_1/IN1 )
  );
  X_INV \NlwInverterBlock_U1/U4/Latch1r<3>_MC.D2_PT_1/IN1  (
    .I(DCORIFGw),
    .O(\NlwInverterSignal_U1/U4/Latch1r<3>_MC.D2_PT_1/IN1 )
  );
  X_INV \NlwInverterBlock_U1/U4/Latch1r<3>_MC.D2_PT_1/IN2  (
    .I(DCORENCCTLw),
    .O(\NlwInverterSignal_U1/U4/Latch1r<3>_MC.D2_PT_1/IN2 )
  );
  X_INV \NlwInverterBlock_U1/U4/Latch1r<11>_MC.D2_PT_1/IN1  (
    .I(DCORIFGw),
    .O(\NlwInverterSignal_U1/U4/Latch1r<11>_MC.D2_PT_1/IN1 )
  );
  X_INV \NlwInverterBlock_U1/U4/Latch1r<11>_MC.D2_PT_1/IN2  (
    .I(DCORENCCTLw),
    .O(\NlwInverterSignal_U1/U4/Latch1r<11>_MC.D2_PT_1/IN2 )
  );
  X_INV \NlwInverterBlock_outDATA<4>\$WA3.UIM_MC.D2_PT_1/IN0  (
    .I(NET2528),
    .O(\NlwInverterSignal_outDATA<4>\$WA3.UIM_MC.D2_PT_1/IN0 )
  );
  X_INV \NlwInverterBlock_outDATA<4>\$WA6.UIM_MC.D2_PT_1/IN0  (
    .I(DCOR0THRESLOWr),
    .O(\NlwInverterSignal_outDATA<4>\$WA6.UIM_MC.D2_PT_1/IN0 )
  );
  X_INV \NlwInverterBlock_outDATA<4>\$WA6.UIM_MC.D2_PT_2/IN0  (
    .I(DCOR0THRESLOWr),
    .O(\NlwInverterSignal_outDATA<4>\$WA6.UIM_MC.D2_PT_2/IN0 )
  );
  X_INV \NlwInverterBlock_outDATA<4>\$WA6.UIM_MC.D2_PT_2/IN1  (
    .I(DCOR0THRESHIGHr),
    .O(\NlwInverterSignal_outDATA<4>\$WA6.UIM_MC.D2_PT_2/IN1 )
  );
  X_INV \NlwInverterBlock_outDATA<4>\$WA6.UIM_MC.D2_PT_3/IN0  (
    .I(DCOR0THRESLOWr),
    .O(\NlwInverterSignal_outDATA<4>\$WA6.UIM_MC.D2_PT_3/IN0 )
  );
  X_INV \NlwInverterBlock_outDATA<4>\$WA6.UIM_MC.D2_PT_3/IN1  (
    .I(DCOR0THRESHIGHr),
    .O(\NlwInverterSignal_outDATA<4>\$WA6.UIM_MC.D2_PT_3/IN1 )
  );
  X_INV \NlwInverterBlock_outDATA<4>\$WA6.UIM_MC.D2_PT_3/IN2  (
    .I(DCOR1THRESLOWr),
    .O(\NlwInverterSignal_outDATA<4>\$WA6.UIM_MC.D2_PT_3/IN2 )
  );
  X_INV \NlwInverterBlock_U1/U4/Latch0r<4>_MC.D2_PT_1/IN1  (
    .I(N_PZ_965),
    .O(\NlwInverterSignal_U1/U4/Latch0r<4>_MC.D2_PT_1/IN1 )
  );
  X_INV \NlwInverterBlock_U1/U4/Latch0r<12>_MC.D2_PT_1/IN1  (
    .I(N_PZ_965),
    .O(\NlwInverterSignal_U1/U4/Latch0r<12>_MC.D2_PT_1/IN1 )
  );
  X_INV \NlwInverterBlock_U1/Channel0<12>_MC.D2_PT_0/IN0  (
    .I(N_PZ_931),
    .O(\NlwInverterSignal_U1/Channel0<12>_MC.D2_PT_0/IN0 )
  );
  X_INV \NlwInverterBlock_U1/Channel0<12>_MC.D2_PT_1/IN2  (
    .I(\U1/Channel0 [9]),
    .O(\NlwInverterSignal_U1/Channel0<12>_MC.D2_PT_1/IN2 )
  );
  X_INV \NlwInverterBlock_U1/Channel0<12>_MC.D2_PT_1/IN3  (
    .I(\U1/Channel0 [10]),
    .O(\NlwInverterSignal_U1/Channel0<12>_MC.D2_PT_1/IN3 )
  );
  X_INV \NlwInverterBlock_U1/Channel0<12>_MC.D2_PT_1/IN4  (
    .I(\U1/Channel0 [11]),
    .O(\NlwInverterSignal_U1/Channel0<12>_MC.D2_PT_1/IN4 )
  );
  X_INV \NlwInverterBlock_U1/Channel0<12>_MC.D2_PT_2/IN0  (
    .I(\U1/U2/location_Maddsub__n0000__n0075 [0]),
    .O(\NlwInverterSignal_U1/Channel0<12>_MC.D2_PT_2/IN0 )
  );
  X_INV \NlwInverterBlock_U1/U4/Latch1r<4>_MC.D2_PT_1/IN1  (
    .I(DCORIFGw),
    .O(\NlwInverterSignal_U1/U4/Latch1r<4>_MC.D2_PT_1/IN1 )
  );
  X_INV \NlwInverterBlock_U1/U4/Latch1r<4>_MC.D2_PT_1/IN2  (
    .I(DCORENCCTLw),
    .O(\NlwInverterSignal_U1/U4/Latch1r<4>_MC.D2_PT_1/IN2 )
  );
  X_INV \NlwInverterBlock_U1/U4/Latch1r<12>_MC.D2_PT_1/IN1  (
    .I(DCORIFGw),
    .O(\NlwInverterSignal_U1/U4/Latch1r<12>_MC.D2_PT_1/IN1 )
  );
  X_INV \NlwInverterBlock_U1/U4/Latch1r<12>_MC.D2_PT_1/IN2  (
    .I(DCORENCCTLw),
    .O(\NlwInverterSignal_U1/U4/Latch1r<12>_MC.D2_PT_1/IN2 )
  );
  X_INV \NlwInverterBlock_U1/Channel1<12>_MC.D2_PT_0/IN0  (
    .I(N_PZ_933),
    .O(\NlwInverterSignal_U1/Channel1<12>_MC.D2_PT_0/IN0 )
  );
  X_INV \NlwInverterBlock_U1/Channel1<12>_MC.D2_PT_1/IN1  (
    .I(\U1/Zero1 ),
    .O(\NlwInverterSignal_U1/Channel1<12>_MC.D2_PT_1/IN1 )
  );
  X_INV \NlwInverterBlock_U1/Channel1<12>_MC.D2_PT_1/IN4  (
    .I(\U1/U5/location_Maddsub__n0000__n0075 [0]),
    .O(\NlwInverterSignal_U1/Channel1<12>_MC.D2_PT_1/IN4 )
  );
  X_INV \NlwInverterBlock_U1/Channel1<12>_MC.D2_PT_2/IN1  (
    .I(\U1/Zero1 ),
    .O(\NlwInverterSignal_U1/Channel1<12>_MC.D2_PT_2/IN1 )
  );
  X_INV \NlwInverterBlock_U1/Channel1<12>_MC.D2_PT_2/IN3  (
    .I(N_PZ_1016),
    .O(\NlwInverterSignal_U1/Channel1<12>_MC.D2_PT_2/IN3 )
  );
  X_INV \NlwInverterBlock_U1/Channel1<12>_MC.D2_PT_2/IN5  (
    .I(\U1/Channel1 [9]),
    .O(\NlwInverterSignal_U1/Channel1<12>_MC.D2_PT_2/IN5 )
  );
  X_INV \NlwInverterBlock_U1/Channel1<12>_MC.D2_PT_2/IN6  (
    .I(\U1/Channel1 [10]),
    .O(\NlwInverterSignal_U1/Channel1<12>_MC.D2_PT_2/IN6 )
  );
  X_INV \NlwInverterBlock_U1/Channel1<12>_MC.D2_PT_2/IN7  (
    .I(\U1/Channel1 [11]),
    .O(\NlwInverterSignal_U1/Channel1<12>_MC.D2_PT_2/IN7 )
  );
  X_INV \NlwInverterBlock_outDATA<4>\$WA5.UIM_MC.D2_PT_1/IN0  (
    .I(DCOR0CNTLOWr),
    .O(\NlwInverterSignal_outDATA<4>\$WA5.UIM_MC.D2_PT_1/IN0 )
  );
  X_INV \NlwInverterBlock_outDATA<4>\$WA5.UIM_MC.D2_PT_2/IN0  (
    .I(DCOR0CNTLOWr),
    .O(\NlwInverterSignal_outDATA<4>\$WA5.UIM_MC.D2_PT_2/IN0 )
  );
  X_INV \NlwInverterBlock_outDATA<4>\$WA5.UIM_MC.D2_PT_2/IN1  (
    .I(DCOR1CNTLOWr),
    .O(\NlwInverterSignal_outDATA<4>\$WA5.UIM_MC.D2_PT_2/IN1 )
  );
  X_INV \NlwInverterBlock_outDATA<4>\$WA5.UIM_MC.D2_PT_3/IN0  (
    .I(DCOR0CNTLOWr),
    .O(\NlwInverterSignal_outDATA<4>\$WA5.UIM_MC.D2_PT_3/IN0 )
  );
  X_INV \NlwInverterBlock_outDATA<4>\$WA5.UIM_MC.D2_PT_3/IN1  (
    .I(DCOR1CNTLOWr),
    .O(\NlwInverterSignal_outDATA<4>\$WA5.UIM_MC.D2_PT_3/IN1 )
  );
  X_INV \NlwInverterBlock_outDATA<4>\$WA5.UIM_MC.D2_PT_3/IN2  (
    .I(DCOR0CNTHIGHr),
    .O(\NlwInverterSignal_outDATA<4>\$WA5.UIM_MC.D2_PT_3/IN2 )
  );
  X_INV \NlwInverterBlock_U1/U3/holdingreg0<4>_MC.D2_PT_1/IN1  (
    .I(\AS_II/UIM ),
    .O(\NlwInverterSignal_U1/U3/holdingreg0<4>_MC.D2_PT_1/IN1 )
  );
  X_INV \NlwInverterBlock_U1/U3/holdingreg1<4>_MC.D2_PT_1/IN1  (
    .I(\AS_II/UIM ),
    .O(\NlwInverterSignal_U1/U3/holdingreg1<4>_MC.D2_PT_1/IN1 )
  );
  X_INV \NlwInverterBlock_U1/U3/holdingreg0<12>_MC.D2_PT_1/IN1  (
    .I(\AS_II/UIM ),
    .O(\NlwInverterSignal_U1/U3/holdingreg0<12>_MC.D2_PT_1/IN1 )
  );
  X_INV \NlwInverterBlock_U1/U3/holdingreg1<12>_MC.D2_PT_1/IN1  (
    .I(\AS_II/UIM ),
    .O(\NlwInverterSignal_U1/U3/holdingreg1<12>_MC.D2_PT_1/IN1 )
  );
  X_INV \NlwInverterBlock_outDATA<5>\$WA3.UIM_MC.D2_PT_1/IN0  (
    .I(NET2528),
    .O(\NlwInverterSignal_outDATA<5>\$WA3.UIM_MC.D2_PT_1/IN0 )
  );
  X_INV \NlwInverterBlock_outDATA<5>\$WA5.UIM_MC.D2_PT_1/IN0  (
    .I(DCOR0CNTLOWr),
    .O(\NlwInverterSignal_outDATA<5>\$WA5.UIM_MC.D2_PT_1/IN0 )
  );
  X_INV \NlwInverterBlock_outDATA<5>\$WA5.UIM_MC.D2_PT_2/IN0  (
    .I(DCOR0CNTLOWr),
    .O(\NlwInverterSignal_outDATA<5>\$WA5.UIM_MC.D2_PT_2/IN0 )
  );
  X_INV \NlwInverterBlock_outDATA<5>\$WA5.UIM_MC.D2_PT_2/IN1  (
    .I(DCOR1CNTLOWr),
    .O(\NlwInverterSignal_outDATA<5>\$WA5.UIM_MC.D2_PT_2/IN1 )
  );
  X_INV \NlwInverterBlock_outDATA<5>\$WA5.UIM_MC.D2_PT_3/IN0  (
    .I(DCOR0CNTLOWr),
    .O(\NlwInverterSignal_outDATA<5>\$WA5.UIM_MC.D2_PT_3/IN0 )
  );
  X_INV \NlwInverterBlock_outDATA<5>\$WA5.UIM_MC.D2_PT_3/IN1  (
    .I(DCOR1CNTLOWr),
    .O(\NlwInverterSignal_outDATA<5>\$WA5.UIM_MC.D2_PT_3/IN1 )
  );
  X_INV \NlwInverterBlock_outDATA<5>\$WA5.UIM_MC.D2_PT_3/IN2  (
    .I(DCOR0CNTHIGHr),
    .O(\NlwInverterSignal_outDATA<5>\$WA5.UIM_MC.D2_PT_3/IN2 )
  );
  X_INV \NlwInverterBlock_U1/U3/holdingreg0<5>_MC.D2_PT_1/IN1  (
    .I(\AS_II/UIM ),
    .O(\NlwInverterSignal_U1/U3/holdingreg0<5>_MC.D2_PT_1/IN1 )
  );
  X_INV \NlwInverterBlock_U1/U3/holdingreg1<5>_MC.D2_PT_1/IN1  (
    .I(\AS_II/UIM ),
    .O(\NlwInverterSignal_U1/U3/holdingreg1<5>_MC.D2_PT_1/IN1 )
  );
  X_INV \NlwInverterBlock_U1/U3/holdingreg0<13>_MC.D2_PT_1/IN1  (
    .I(\AS_II/UIM ),
    .O(\NlwInverterSignal_U1/U3/holdingreg0<13>_MC.D2_PT_1/IN1 )
  );
  X_INV \NlwInverterBlock_U1/Channel0<13>_MC.D2_PT_0/IN0  (
    .I(N_PZ_931),
    .O(\NlwInverterSignal_U1/Channel0<13>_MC.D2_PT_0/IN0 )
  );
  X_INV \NlwInverterBlock_U1/Channel0<13>_MC.D2_PT_1/IN2  (
    .I(\U1/Channel0 [9]),
    .O(\NlwInverterSignal_U1/Channel0<13>_MC.D2_PT_1/IN2 )
  );
  X_INV \NlwInverterBlock_U1/Channel0<13>_MC.D2_PT_1/IN3  (
    .I(\U1/Channel0 [10]),
    .O(\NlwInverterSignal_U1/Channel0<13>_MC.D2_PT_1/IN3 )
  );
  X_INV \NlwInverterBlock_U1/Channel0<13>_MC.D2_PT_1/IN4  (
    .I(\U1/Channel0 [11]),
    .O(\NlwInverterSignal_U1/Channel0<13>_MC.D2_PT_1/IN4 )
  );
  X_INV \NlwInverterBlock_U1/Channel0<13>_MC.D2_PT_1/IN5  (
    .I(\U1/Channel0 [12]),
    .O(\NlwInverterSignal_U1/Channel0<13>_MC.D2_PT_1/IN5 )
  );
  X_INV \NlwInverterBlock_U1/Channel0<13>_MC.D2_PT_2/IN0  (
    .I(\U1/U2/location_Maddsub__n0000__n0075 [0]),
    .O(\NlwInverterSignal_U1/Channel0<13>_MC.D2_PT_2/IN0 )
  );
  X_INV \NlwInverterBlock_U1/U3/holdingreg1<13>_MC.D2_PT_1/IN1  (
    .I(\AS_II/UIM ),
    .O(\NlwInverterSignal_U1/U3/holdingreg1<13>_MC.D2_PT_1/IN1 )
  );
  X_INV \NlwInverterBlock_U1/Channel1<13>_MC.D2_PT_0/IN0  (
    .I(N_PZ_933),
    .O(\NlwInverterSignal_U1/Channel1<13>_MC.D2_PT_0/IN0 )
  );
  X_INV \NlwInverterBlock_U1/Channel1<13>_MC.D2_PT_1/IN1  (
    .I(\U1/Zero1 ),
    .O(\NlwInverterSignal_U1/Channel1<13>_MC.D2_PT_1/IN1 )
  );
  X_INV \NlwInverterBlock_U1/Channel1<13>_MC.D2_PT_1/IN4  (
    .I(\U1/U5/location_Maddsub__n0000__n0075 [0]),
    .O(\NlwInverterSignal_U1/Channel1<13>_MC.D2_PT_1/IN4 )
  );
  X_INV \NlwInverterBlock_U1/Channel1<13>_MC.D2_PT_2/IN1  (
    .I(\U1/Zero1 ),
    .O(\NlwInverterSignal_U1/Channel1<13>_MC.D2_PT_2/IN1 )
  );
  X_INV \NlwInverterBlock_U1/Channel1<13>_MC.D2_PT_2/IN3  (
    .I(N_PZ_1016),
    .O(\NlwInverterSignal_U1/Channel1<13>_MC.D2_PT_2/IN3 )
  );
  X_INV \NlwInverterBlock_U1/Channel1<13>_MC.D2_PT_2/IN5  (
    .I(\U1/Channel1 [9]),
    .O(\NlwInverterSignal_U1/Channel1<13>_MC.D2_PT_2/IN5 )
  );
  X_INV \NlwInverterBlock_U1/Channel1<13>_MC.D2_PT_2/IN6  (
    .I(\U1/Channel1 [10]),
    .O(\NlwInverterSignal_U1/Channel1<13>_MC.D2_PT_2/IN6 )
  );
  X_INV \NlwInverterBlock_U1/Channel1<13>_MC.D2_PT_2/IN7  (
    .I(\U1/Channel1 [11]),
    .O(\NlwInverterSignal_U1/Channel1<13>_MC.D2_PT_2/IN7 )
  );
  X_INV \NlwInverterBlock_U1/Channel1<13>_MC.D2_PT_2/IN8  (
    .I(\U1/Channel1 [12]),
    .O(\NlwInverterSignal_U1/Channel1<13>_MC.D2_PT_2/IN8 )
  );
  X_INV \NlwInverterBlock_outDATA<5>\$WA6.UIM_MC.D2_PT_1/IN1  (
    .I(DCOR0THRESLOWr),
    .O(\NlwInverterSignal_outDATA<5>\$WA6.UIM_MC.D2_PT_1/IN1 )
  );
  X_INV \NlwInverterBlock_outDATA<5>\$WA6.UIM_MC.D2_PT_2/IN0  (
    .I(DCORIFGr),
    .O(\NlwInverterSignal_outDATA<5>\$WA6.UIM_MC.D2_PT_2/IN0 )
  );
  X_INV \NlwInverterBlock_outDATA<5>\$WA6.UIM_MC.D2_PT_2/IN1  (
    .I(DCOR0THRESLOWr),
    .O(\NlwInverterSignal_outDATA<5>\$WA6.UIM_MC.D2_PT_2/IN1 )
  );
  X_INV \NlwInverterBlock_outDATA<5>\$WA6.UIM_MC.D2_PT_3/IN0  (
    .I(DCORIFGr),
    .O(\NlwInverterSignal_outDATA<5>\$WA6.UIM_MC.D2_PT_3/IN0 )
  );
  X_INV \NlwInverterBlock_outDATA<5>\$WA6.UIM_MC.D2_PT_3/IN1  (
    .I(DCOR0THRESLOWr),
    .O(\NlwInverterSignal_outDATA<5>\$WA6.UIM_MC.D2_PT_3/IN1 )
  );
  X_INV \NlwInverterBlock_outDATA<5>\$WA6.UIM_MC.D2_PT_3/IN2  (
    .I(DCOR0THRESHIGHr),
    .O(\NlwInverterSignal_outDATA<5>\$WA6.UIM_MC.D2_PT_3/IN2 )
  );
  X_INV \NlwInverterBlock_outDATA<5>\$WA6.UIM_MC.D2_PT_4/IN0  (
    .I(DCORIFGr),
    .O(\NlwInverterSignal_outDATA<5>\$WA6.UIM_MC.D2_PT_4/IN0 )
  );
  X_INV \NlwInverterBlock_outDATA<5>\$WA6.UIM_MC.D2_PT_4/IN1  (
    .I(DCOR0THRESLOWr),
    .O(\NlwInverterSignal_outDATA<5>\$WA6.UIM_MC.D2_PT_4/IN1 )
  );
  X_INV \NlwInverterBlock_outDATA<5>\$WA6.UIM_MC.D2_PT_4/IN2  (
    .I(DCOR0THRESHIGHr),
    .O(\NlwInverterSignal_outDATA<5>\$WA6.UIM_MC.D2_PT_4/IN2 )
  );
  X_INV \NlwInverterBlock_outDATA<5>\$WA6.UIM_MC.D2_PT_4/IN3  (
    .I(DCOR1THRESLOWr),
    .O(\NlwInverterSignal_outDATA<5>\$WA6.UIM_MC.D2_PT_4/IN3 )
  );
  X_INV \NlwInverterBlock_U1/U4/Latch0r<5>_MC.D2_PT_1/IN1  (
    .I(N_PZ_965),
    .O(\NlwInverterSignal_U1/U4/Latch0r<5>_MC.D2_PT_1/IN1 )
  );
  X_INV \NlwInverterBlock_U1/U4/Latch0r<13>_MC.D2_PT_1/IN1  (
    .I(N_PZ_965),
    .O(\NlwInverterSignal_U1/U4/Latch0r<13>_MC.D2_PT_1/IN1 )
  );
  X_INV \NlwInverterBlock_U1/U4/Latch1r<5>_MC.D2_PT_1/IN1  (
    .I(DCORIFGw),
    .O(\NlwInverterSignal_U1/U4/Latch1r<5>_MC.D2_PT_1/IN1 )
  );
  X_INV \NlwInverterBlock_U1/U4/Latch1r<5>_MC.D2_PT_1/IN2  (
    .I(DCORENCCTLw),
    .O(\NlwInverterSignal_U1/U4/Latch1r<5>_MC.D2_PT_1/IN2 )
  );
  X_INV \NlwInverterBlock_U1/U4/Latch1r<13>_MC.D2_PT_1/IN1  (
    .I(DCORIFGw),
    .O(\NlwInverterSignal_U1/U4/Latch1r<13>_MC.D2_PT_1/IN1 )
  );
  X_INV \NlwInverterBlock_U1/U4/Latch1r<13>_MC.D2_PT_1/IN2  (
    .I(DCORENCCTLw),
    .O(\NlwInverterSignal_U1/U4/Latch1r<13>_MC.D2_PT_1/IN2 )
  );
  X_INV \NlwInverterBlock_outDATA<6>\$WA3.UIM_MC.D2_PT_1/IN0  (
    .I(NET2528),
    .O(\NlwInverterSignal_outDATA<6>\$WA3.UIM_MC.D2_PT_1/IN0 )
  );
  X_INV \NlwInverterBlock_outDATA<6>\$WA5.UIM_MC.D2_PT_1/IN0  (
    .I(DCOR0CNTLOWr),
    .O(\NlwInverterSignal_outDATA<6>\$WA5.UIM_MC.D2_PT_1/IN0 )
  );
  X_INV \NlwInverterBlock_outDATA<6>\$WA5.UIM_MC.D2_PT_2/IN0  (
    .I(DCOR0CNTLOWr),
    .O(\NlwInverterSignal_outDATA<6>\$WA5.UIM_MC.D2_PT_2/IN0 )
  );
  X_INV \NlwInverterBlock_outDATA<6>\$WA5.UIM_MC.D2_PT_2/IN1  (
    .I(DCOR1CNTLOWr),
    .O(\NlwInverterSignal_outDATA<6>\$WA5.UIM_MC.D2_PT_2/IN1 )
  );
  X_INV \NlwInverterBlock_outDATA<6>\$WA5.UIM_MC.D2_PT_3/IN0  (
    .I(DCOR0CNTLOWr),
    .O(\NlwInverterSignal_outDATA<6>\$WA5.UIM_MC.D2_PT_3/IN0 )
  );
  X_INV \NlwInverterBlock_outDATA<6>\$WA5.UIM_MC.D2_PT_3/IN1  (
    .I(DCOR1CNTLOWr),
    .O(\NlwInverterSignal_outDATA<6>\$WA5.UIM_MC.D2_PT_3/IN1 )
  );
  X_INV \NlwInverterBlock_outDATA<6>\$WA5.UIM_MC.D2_PT_3/IN2  (
    .I(DCOR0CNTHIGHr),
    .O(\NlwInverterSignal_outDATA<6>\$WA5.UIM_MC.D2_PT_3/IN2 )
  );
  X_INV \NlwInverterBlock_U1/U3/holdingreg0<6>_MC.D2_PT_1/IN1  (
    .I(\AS_II/UIM ),
    .O(\NlwInverterSignal_U1/U3/holdingreg0<6>_MC.D2_PT_1/IN1 )
  );
  X_INV \NlwInverterBlock_U1/U3/holdingreg1<6>_MC.D2_PT_1/IN1  (
    .I(\AS_II/UIM ),
    .O(\NlwInverterSignal_U1/U3/holdingreg1<6>_MC.D2_PT_1/IN1 )
  );
  X_INV \NlwInverterBlock_U1/U3/holdingreg0<14>_MC.D2_PT_1/IN1  (
    .I(\AS_II/UIM ),
    .O(\NlwInverterSignal_U1/U3/holdingreg0<14>_MC.D2_PT_1/IN1 )
  );
  X_INV \NlwInverterBlock_U1/Channel0<14>_MC.D2_PT_0/IN0  (
    .I(N_PZ_931),
    .O(\NlwInverterSignal_U1/Channel0<14>_MC.D2_PT_0/IN0 )
  );
  X_INV \NlwInverterBlock_U1/Channel0<14>_MC.D2_PT_1/IN2  (
    .I(\U1/Channel0 [9]),
    .O(\NlwInverterSignal_U1/Channel0<14>_MC.D2_PT_1/IN2 )
  );
  X_INV \NlwInverterBlock_U1/Channel0<14>_MC.D2_PT_1/IN3  (
    .I(\U1/Channel0 [10]),
    .O(\NlwInverterSignal_U1/Channel0<14>_MC.D2_PT_1/IN3 )
  );
  X_INV \NlwInverterBlock_U1/Channel0<14>_MC.D2_PT_1/IN4  (
    .I(\U1/Channel0 [11]),
    .O(\NlwInverterSignal_U1/Channel0<14>_MC.D2_PT_1/IN4 )
  );
  X_INV \NlwInverterBlock_U1/Channel0<14>_MC.D2_PT_1/IN5  (
    .I(\U1/Channel0 [12]),
    .O(\NlwInverterSignal_U1/Channel0<14>_MC.D2_PT_1/IN5 )
  );
  X_INV \NlwInverterBlock_U1/Channel0<14>_MC.D2_PT_1/IN6  (
    .I(\U1/Channel0 [13]),
    .O(\NlwInverterSignal_U1/Channel0<14>_MC.D2_PT_1/IN6 )
  );
  X_INV \NlwInverterBlock_U1/Channel0<14>_MC.D2_PT_2/IN0  (
    .I(\U1/U2/location_Maddsub__n0000__n0075 [0]),
    .O(\NlwInverterSignal_U1/Channel0<14>_MC.D2_PT_2/IN0 )
  );
  X_INV \NlwInverterBlock_U1/U3/holdingreg1<14>_MC.D2_PT_1/IN1  (
    .I(\AS_II/UIM ),
    .O(\NlwInverterSignal_U1/U3/holdingreg1<14>_MC.D2_PT_1/IN1 )
  );
  X_INV \NlwInverterBlock_U1/Channel1<14>_MC.D2_PT_0/IN0  (
    .I(N_PZ_933),
    .O(\NlwInverterSignal_U1/Channel1<14>_MC.D2_PT_0/IN0 )
  );
  X_INV \NlwInverterBlock_U1/Channel1<14>_MC.D2_PT_1/IN1  (
    .I(\U1/Zero1 ),
    .O(\NlwInverterSignal_U1/Channel1<14>_MC.D2_PT_1/IN1 )
  );
  X_INV \NlwInverterBlock_U1/Channel1<14>_MC.D2_PT_1/IN3  (
    .I(\U1/U5/location_Maddsub__n0000__n0075 [0]),
    .O(\NlwInverterSignal_U1/Channel1<14>_MC.D2_PT_1/IN3 )
  );
  X_INV \NlwInverterBlock_U1/Channel1<14>_MC.D2_PT_2/IN1  (
    .I(\U1/Zero1 ),
    .O(\NlwInverterSignal_U1/Channel1<14>_MC.D2_PT_2/IN1 )
  );
  X_INV \NlwInverterBlock_U1/Channel1<14>_MC.D2_PT_2/IN3  (
    .I(N_PZ_1016),
    .O(\NlwInverterSignal_U1/Channel1<14>_MC.D2_PT_2/IN3 )
  );
  X_INV \NlwInverterBlock_U1/Channel1<14>_MC.D2_PT_2/IN5  (
    .I(\U1/Channel1 [9]),
    .O(\NlwInverterSignal_U1/Channel1<14>_MC.D2_PT_2/IN5 )
  );
  X_INV \NlwInverterBlock_U1/Channel1<14>_MC.D2_PT_2/IN6  (
    .I(\U1/Channel1 [10]),
    .O(\NlwInverterSignal_U1/Channel1<14>_MC.D2_PT_2/IN6 )
  );
  X_INV \NlwInverterBlock_U1/Channel1<14>_MC.D2_PT_2/IN7  (
    .I(\U1/Channel1 [11]),
    .O(\NlwInverterSignal_U1/Channel1<14>_MC.D2_PT_2/IN7 )
  );
  X_INV \NlwInverterBlock_U1/Channel1<14>_MC.D2_PT_2/IN8  (
    .I(\U1/Channel1 [12]),
    .O(\NlwInverterSignal_U1/Channel1<14>_MC.D2_PT_2/IN8 )
  );
  X_INV \NlwInverterBlock_U1/Channel1<14>_MC.D2_PT_2/IN9  (
    .I(\U1/Channel1 [13]),
    .O(\NlwInverterSignal_U1/Channel1<14>_MC.D2_PT_2/IN9 )
  );
  X_INV \NlwInverterBlock_outDATA<6>\$WA6.UIM_MC.D2_PT_1/IN1  (
    .I(DCOR0THRESLOWr),
    .O(\NlwInverterSignal_outDATA<6>\$WA6.UIM_MC.D2_PT_1/IN1 )
  );
  X_INV \NlwInverterBlock_outDATA<6>\$WA6.UIM_MC.D2_PT_2/IN0  (
    .I(DCORIFGr),
    .O(\NlwInverterSignal_outDATA<6>\$WA6.UIM_MC.D2_PT_2/IN0 )
  );
  X_INV \NlwInverterBlock_outDATA<6>\$WA6.UIM_MC.D2_PT_2/IN1  (
    .I(DCOR0THRESLOWr),
    .O(\NlwInverterSignal_outDATA<6>\$WA6.UIM_MC.D2_PT_2/IN1 )
  );
  X_INV \NlwInverterBlock_outDATA<6>\$WA6.UIM_MC.D2_PT_3/IN0  (
    .I(DCORIFGr),
    .O(\NlwInverterSignal_outDATA<6>\$WA6.UIM_MC.D2_PT_3/IN0 )
  );
  X_INV \NlwInverterBlock_outDATA<6>\$WA6.UIM_MC.D2_PT_3/IN1  (
    .I(DCOR0THRESLOWr),
    .O(\NlwInverterSignal_outDATA<6>\$WA6.UIM_MC.D2_PT_3/IN1 )
  );
  X_INV \NlwInverterBlock_outDATA<6>\$WA6.UIM_MC.D2_PT_3/IN2  (
    .I(DCOR0THRESHIGHr),
    .O(\NlwInverterSignal_outDATA<6>\$WA6.UIM_MC.D2_PT_3/IN2 )
  );
  X_INV \NlwInverterBlock_outDATA<6>\$WA6.UIM_MC.D2_PT_4/IN0  (
    .I(DCORIFGr),
    .O(\NlwInverterSignal_outDATA<6>\$WA6.UIM_MC.D2_PT_4/IN0 )
  );
  X_INV \NlwInverterBlock_outDATA<6>\$WA6.UIM_MC.D2_PT_4/IN1  (
    .I(DCOR0THRESLOWr),
    .O(\NlwInverterSignal_outDATA<6>\$WA6.UIM_MC.D2_PT_4/IN1 )
  );
  X_INV \NlwInverterBlock_outDATA<6>\$WA6.UIM_MC.D2_PT_4/IN2  (
    .I(DCOR0THRESHIGHr),
    .O(\NlwInverterSignal_outDATA<6>\$WA6.UIM_MC.D2_PT_4/IN2 )
  );
  X_INV \NlwInverterBlock_outDATA<6>\$WA6.UIM_MC.D2_PT_4/IN3  (
    .I(DCOR1THRESLOWr),
    .O(\NlwInverterSignal_outDATA<6>\$WA6.UIM_MC.D2_PT_4/IN3 )
  );
  X_INV \NlwInverterBlock_U1/U4/Latch0r<6>_MC.D2_PT_1/IN1  (
    .I(N_PZ_965),
    .O(\NlwInverterSignal_U1/U4/Latch0r<6>_MC.D2_PT_1/IN1 )
  );
  X_INV \NlwInverterBlock_U1/U4/Latch0r<14>_MC.D2_PT_1/IN1  (
    .I(N_PZ_965),
    .O(\NlwInverterSignal_U1/U4/Latch0r<14>_MC.D2_PT_1/IN1 )
  );
  X_INV \NlwInverterBlock_U1/U4/Latch1r<6>_MC.D2_PT_1/IN1  (
    .I(DCORIFGw),
    .O(\NlwInverterSignal_U1/U4/Latch1r<6>_MC.D2_PT_1/IN1 )
  );
  X_INV \NlwInverterBlock_U1/U4/Latch1r<6>_MC.D2_PT_1/IN2  (
    .I(DCORENCCTLw),
    .O(\NlwInverterSignal_U1/U4/Latch1r<6>_MC.D2_PT_1/IN2 )
  );
  X_INV \NlwInverterBlock_U1/U4/Latch1r<14>_MC.D2_PT_1/IN1  (
    .I(DCORIFGw),
    .O(\NlwInverterSignal_U1/U4/Latch1r<14>_MC.D2_PT_1/IN1 )
  );
  X_INV \NlwInverterBlock_U1/U4/Latch1r<14>_MC.D2_PT_1/IN2  (
    .I(DCORENCCTLw),
    .O(\NlwInverterSignal_U1/U4/Latch1r<14>_MC.D2_PT_1/IN2 )
  );
  X_INV \NlwInverterBlock_outDATA<7>\$WA3.UIM_MC.D2_PT_1/IN0  (
    .I(NET2528),
    .O(\NlwInverterSignal_outDATA<7>\$WA3.UIM_MC.D2_PT_1/IN0 )
  );
  X_INV \NlwInverterBlock_outDATA<7>\$WA6.UIM_MC.D2_PT_1/IN0  (
    .I(DCOR0THRESLOWr),
    .O(\NlwInverterSignal_outDATA<7>\$WA6.UIM_MC.D2_PT_1/IN0 )
  );
  X_INV \NlwInverterBlock_outDATA<7>\$WA6.UIM_MC.D2_PT_2/IN0  (
    .I(DCOR0THRESLOWr),
    .O(\NlwInverterSignal_outDATA<7>\$WA6.UIM_MC.D2_PT_2/IN0 )
  );
  X_INV \NlwInverterBlock_outDATA<7>\$WA6.UIM_MC.D2_PT_2/IN1  (
    .I(DCOR0THRESHIGHr),
    .O(\NlwInverterSignal_outDATA<7>\$WA6.UIM_MC.D2_PT_2/IN1 )
  );
  X_INV \NlwInverterBlock_outDATA<7>\$WA6.UIM_MC.D2_PT_3/IN0  (
    .I(DCOR0THRESLOWr),
    .O(\NlwInverterSignal_outDATA<7>\$WA6.UIM_MC.D2_PT_3/IN0 )
  );
  X_INV \NlwInverterBlock_outDATA<7>\$WA6.UIM_MC.D2_PT_3/IN1  (
    .I(DCOR0THRESHIGHr),
    .O(\NlwInverterSignal_outDATA<7>\$WA6.UIM_MC.D2_PT_3/IN1 )
  );
  X_INV \NlwInverterBlock_outDATA<7>\$WA6.UIM_MC.D2_PT_3/IN2  (
    .I(DCOR1THRESLOWr),
    .O(\NlwInverterSignal_outDATA<7>\$WA6.UIM_MC.D2_PT_3/IN2 )
  );
  X_INV \NlwInverterBlock_U1/U4/Latch0r<7>_MC.D2_PT_1/IN1  (
    .I(N_PZ_965),
    .O(\NlwInverterSignal_U1/U4/Latch0r<7>_MC.D2_PT_1/IN1 )
  );
  X_INV \NlwInverterBlock_U1/U4/Latch0r<15>_MC.D2_PT_1/IN1  (
    .I(N_PZ_965),
    .O(\NlwInverterSignal_U1/U4/Latch0r<15>_MC.D2_PT_1/IN1 )
  );
  X_INV \NlwInverterBlock_U1/Channel0<15>_MC.D2_PT_0/IN0  (
    .I(N_PZ_931),
    .O(\NlwInverterSignal_U1/Channel0<15>_MC.D2_PT_0/IN0 )
  );
  X_INV \NlwInverterBlock_U1/Channel0<15>_MC.D2_PT_1/IN2  (
    .I(\U1/Channel0 [9]),
    .O(\NlwInverterSignal_U1/Channel0<15>_MC.D2_PT_1/IN2 )
  );
  X_INV \NlwInverterBlock_U1/Channel0<15>_MC.D2_PT_1/IN3  (
    .I(\U1/Channel0 [10]),
    .O(\NlwInverterSignal_U1/Channel0<15>_MC.D2_PT_1/IN3 )
  );
  X_INV \NlwInverterBlock_U1/Channel0<15>_MC.D2_PT_1/IN4  (
    .I(\U1/Channel0 [11]),
    .O(\NlwInverterSignal_U1/Channel0<15>_MC.D2_PT_1/IN4 )
  );
  X_INV \NlwInverterBlock_U1/Channel0<15>_MC.D2_PT_1/IN5  (
    .I(\U1/Channel0 [12]),
    .O(\NlwInverterSignal_U1/Channel0<15>_MC.D2_PT_1/IN5 )
  );
  X_INV \NlwInverterBlock_U1/Channel0<15>_MC.D2_PT_1/IN6  (
    .I(\U1/Channel0 [13]),
    .O(\NlwInverterSignal_U1/Channel0<15>_MC.D2_PT_1/IN6 )
  );
  X_INV \NlwInverterBlock_U1/Channel0<15>_MC.D2_PT_1/IN7  (
    .I(\U1/Channel0 [14]),
    .O(\NlwInverterSignal_U1/Channel0<15>_MC.D2_PT_1/IN7 )
  );
  X_INV \NlwInverterBlock_U1/Channel0<15>_MC.D2_PT_2/IN0  (
    .I(\U1/U2/location_Maddsub__n0000__n0075 [0]),
    .O(\NlwInverterSignal_U1/Channel0<15>_MC.D2_PT_2/IN0 )
  );
  X_INV \NlwInverterBlock_U1/U4/Latch1r<7>_MC.D2_PT_1/IN1  (
    .I(DCORIFGw),
    .O(\NlwInverterSignal_U1/U4/Latch1r<7>_MC.D2_PT_1/IN1 )
  );
  X_INV \NlwInverterBlock_U1/U4/Latch1r<7>_MC.D2_PT_1/IN2  (
    .I(DCORENCCTLw),
    .O(\NlwInverterSignal_U1/U4/Latch1r<7>_MC.D2_PT_1/IN2 )
  );
  X_INV \NlwInverterBlock_U1/U4/Latch1r<15>_MC.D2_PT_1/IN1  (
    .I(DCORIFGw),
    .O(\NlwInverterSignal_U1/U4/Latch1r<15>_MC.D2_PT_1/IN1 )
  );
  X_INV \NlwInverterBlock_U1/U4/Latch1r<15>_MC.D2_PT_1/IN2  (
    .I(DCORENCCTLw),
    .O(\NlwInverterSignal_U1/U4/Latch1r<15>_MC.D2_PT_1/IN2 )
  );
  X_INV \NlwInverterBlock_U1/Channel1<15>_MC.D2_PT_0/IN0  (
    .I(N_PZ_933),
    .O(\NlwInverterSignal_U1/Channel1<15>_MC.D2_PT_0/IN0 )
  );
  X_INV \NlwInverterBlock_U1/Channel1<15>_MC.D2_PT_1/IN1  (
    .I(\U1/Zero1 ),
    .O(\NlwInverterSignal_U1/Channel1<15>_MC.D2_PT_1/IN1 )
  );
  X_INV \NlwInverterBlock_U1/Channel1<15>_MC.D2_PT_1/IN3  (
    .I(\U1/U5/location_Maddsub__n0000__n0075 [0]),
    .O(\NlwInverterSignal_U1/Channel1<15>_MC.D2_PT_1/IN3 )
  );
  X_INV \NlwInverterBlock_U1/Channel1<15>_MC.D2_PT_2/IN1  (
    .I(\U1/Zero1 ),
    .O(\NlwInverterSignal_U1/Channel1<15>_MC.D2_PT_2/IN1 )
  );
  X_INV \NlwInverterBlock_U1/Channel1<15>_MC.D2_PT_2/IN3  (
    .I(N_PZ_1016),
    .O(\NlwInverterSignal_U1/Channel1<15>_MC.D2_PT_2/IN3 )
  );
  X_INV \NlwInverterBlock_U1/Channel1<15>_MC.D2_PT_2/IN5  (
    .I(\U1/Channel1 [9]),
    .O(\NlwInverterSignal_U1/Channel1<15>_MC.D2_PT_2/IN5 )
  );
  X_INV \NlwInverterBlock_U1/Channel1<15>_MC.D2_PT_2/IN6  (
    .I(\U1/Channel1 [10]),
    .O(\NlwInverterSignal_U1/Channel1<15>_MC.D2_PT_2/IN6 )
  );
  X_INV \NlwInverterBlock_U1/Channel1<15>_MC.D2_PT_2/IN7  (
    .I(\U1/Channel1 [11]),
    .O(\NlwInverterSignal_U1/Channel1<15>_MC.D2_PT_2/IN7 )
  );
  X_INV \NlwInverterBlock_U1/Channel1<15>_MC.D2_PT_2/IN8  (
    .I(\U1/Channel1 [12]),
    .O(\NlwInverterSignal_U1/Channel1<15>_MC.D2_PT_2/IN8 )
  );
  X_INV \NlwInverterBlock_U1/Channel1<15>_MC.D2_PT_2/IN9  (
    .I(\U1/Channel1 [13]),
    .O(\NlwInverterSignal_U1/Channel1<15>_MC.D2_PT_2/IN9 )
  );
  X_INV \NlwInverterBlock_U1/Channel1<15>_MC.D2_PT_2/IN10  (
    .I(\U1/Channel1 [14]),
    .O(\NlwInverterSignal_U1/Channel1<15>_MC.D2_PT_2/IN10 )
  );
  X_INV \NlwInverterBlock_outDATA<7>\$WA5.UIM_MC.D2_PT_1/IN0  (
    .I(DCOR0CNTLOWr),
    .O(\NlwInverterSignal_outDATA<7>\$WA5.UIM_MC.D2_PT_1/IN0 )
  );
  X_INV \NlwInverterBlock_outDATA<7>\$WA5.UIM_MC.D2_PT_2/IN0  (
    .I(DCOR0CNTLOWr),
    .O(\NlwInverterSignal_outDATA<7>\$WA5.UIM_MC.D2_PT_2/IN0 )
  );
  X_INV \NlwInverterBlock_outDATA<7>\$WA5.UIM_MC.D2_PT_2/IN1  (
    .I(DCOR1CNTLOWr),
    .O(\NlwInverterSignal_outDATA<7>\$WA5.UIM_MC.D2_PT_2/IN1 )
  );
  X_INV \NlwInverterBlock_outDATA<7>\$WA5.UIM_MC.D2_PT_3/IN0  (
    .I(DCOR0CNTLOWr),
    .O(\NlwInverterSignal_outDATA<7>\$WA5.UIM_MC.D2_PT_3/IN0 )
  );
  X_INV \NlwInverterBlock_outDATA<7>\$WA5.UIM_MC.D2_PT_3/IN1  (
    .I(DCOR1CNTLOWr),
    .O(\NlwInverterSignal_outDATA<7>\$WA5.UIM_MC.D2_PT_3/IN1 )
  );
  X_INV \NlwInverterBlock_outDATA<7>\$WA5.UIM_MC.D2_PT_3/IN2  (
    .I(DCOR0CNTHIGHr),
    .O(\NlwInverterSignal_outDATA<7>\$WA5.UIM_MC.D2_PT_3/IN2 )
  );
  X_INV \NlwInverterBlock_U1/U3/holdingreg0<7>_MC.D2_PT_1/IN1  (
    .I(\AS_II/UIM ),
    .O(\NlwInverterSignal_U1/U3/holdingreg0<7>_MC.D2_PT_1/IN1 )
  );
  X_INV \NlwInverterBlock_U1/U3/holdingreg1<7>_MC.D2_PT_1/IN1  (
    .I(\AS_II/UIM ),
    .O(\NlwInverterSignal_U1/U3/holdingreg1<7>_MC.D2_PT_1/IN1 )
  );
  X_INV \NlwInverterBlock_U1/U3/holdingreg0<15>_MC.D2_PT_1/IN1  (
    .I(\AS_II/UIM ),
    .O(\NlwInverterSignal_U1/U3/holdingreg0<15>_MC.D2_PT_1/IN1 )
  );
  X_INV \NlwInverterBlock_U1/U3/holdingreg1<15>_MC.D2_PT_1/IN1  (
    .I(\AS_II/UIM ),
    .O(\NlwInverterSignal_U1/U3/holdingreg1<15>_MC.D2_PT_1/IN1 )
  );
  X_INV \NlwInverterBlock_FOOBAR2__ctinst/7/OUT  (
    .I(\NlwInverterSignal_FOOBAR2__ctinst/7/OUT ),
    .O(\FOOBAR2__ctinst/7 )
  );
  X_INV \NlwInverterBlock_FOOBAR3__ctinst/7/OUT  (
    .I(\NlwInverterSignal_FOOBAR3__ctinst/7/OUT ),
    .O(\FOOBAR3__ctinst/7 )
  );
  X_INV \NlwInverterBlock_FOOBAR8__ctinst/4/IN1  (
    .I(N_PZ_955),
    .O(\NlwInverterSignal_FOOBAR8__ctinst/4/IN1 )
  );
  X_INV \NlwInverterBlock_FOOBAR21__ctinst/4/IN0  (
    .I(NET2528),
    .O(\NlwInverterSignal_FOOBAR21__ctinst/4/IN0 )
  );
  X_INV \NlwInverterBlock_FOOBAR21__ctinst/4/IN1  (
    .I(\U4/orFLGs ),
    .O(\NlwInverterSignal_FOOBAR21__ctinst/4/IN1 )
  );
  X_INV \NlwInverterBlock_FOOBAR24__ctinst/4/IN0  (
    .I(NET2528),
    .O(\NlwInverterSignal_FOOBAR24__ctinst/4/IN0 )
  );
  X_INV \NlwInverterBlock_FOOBAR24__ctinst/4/IN1  (
    .I(\U4/orFLGs ),
    .O(\NlwInverterSignal_FOOBAR24__ctinst/4/IN1 )
  );
endmodule

