// Xilinx Verilog netlist produced by netgen application (version G.26)
// Command      : -sim -ofmt verilog -sdf_path c:\Projects\genosensor\2g\CPLDs\Core\U21\implement U21.nga c:\Projects\genosensor\2g\CPLDs\Core\U21\implement\ver0\rev5\time_sim.v 
// Input file   : U21.nga
// Output file  : c:/Projects/genosensor/2g/CPLDs/Core/U21/implement/ver0/rev5/time_sim.v
// Design name  : U21.nga
// # of Modules : 1
// Xilinx       : C:/Xilinx
// Device       : XCR3384XL-7-TQ144 (Speed File: Version 6.0)

// This verilog netlist is a simulation model and uses simulation 
// primitives which may not represent the true implementation of the 
// device, however the netlist is functionally correct and should not 
// be modified. This file cannot be synthesized and should only be used 
// with supported simulation tools.

`timescale 1 ns/1 ps

module U21 (
  WR, RD, MSPReset, AS, Mclk, SCLreset, SCLinc, PhaseA_Encoder0, PhaseB_Encoder0, GP_Motor0_0, PhaseB_Encoder1, PhaseA_Encoder1, GP_Motor1_0, 
Home033FLG, Home15FLG, Home133FLG, Home05FLG, Enc15FLG, Enc133FLG, Enc05FLG, Enc033FLG, INTbus, RLS0, DIR0, FLS0, DIR1, FLS1, RLS1, Brake0, Brake1, 
PWM5, PWM3, MReset, HSI, MHSO, LightSense, TXI, PWM1, PWM2, Home0, Home1, Enc033ctrl, Enc05ctrl, Enc133ctrl, Enc15ctrl, GPIO8, GPIO9, GP_Motor0_1, 
GP_Motor1_1, HSO, Home033ctrl, Home05ctrl, Home133ctrl, Home15ctrl, INT, LED1, LED2, LED3, LED4, LED5, MHSI, MTRpwr, MTRpwrn, MTXI, PAH0, PAH1, PAL0, 
PAL1, PBH0, PBH1, PBL0, PBL1, PresEn, PresSlct, SCLout, TP10, TP11, TP12, TmpEn, TmpSlct, SCL, I2CS, AD
);
  input WR;
  input RD;
  input MSPReset;
  input AS;
  input Mclk;
  input SCLreset;
  input SCLinc;
  input PhaseA_Encoder0;
  input PhaseB_Encoder0;
  input GP_Motor0_0;
  input PhaseB_Encoder1;
  input PhaseA_Encoder1;
  input GP_Motor1_0;
  input Home033FLG;
  input Home15FLG;
  input Home133FLG;
  input Home05FLG;
  input Enc15FLG;
  input Enc133FLG;
  input Enc05FLG;
  input Enc033FLG;
  input INTbus;
  input RLS0;
  input DIR0;
  input FLS0;
  input DIR1;
  input FLS1;
  input RLS1;
  input Brake0;
  input Brake1;
  input PWM5;
  input PWM3;
  input MReset;
  input HSI;
  input MHSO;
  input LightSense;
  input TXI;
  input PWM1;
  input PWM2;
  input Home0;
  input Home1;
  output Enc033ctrl;
  output Enc05ctrl;
  output Enc133ctrl;
  output Enc15ctrl;
  output GPIO8;
  output GPIO9;
  output GP_Motor0_1;
  output GP_Motor1_1;
  output HSO;
  output Home033ctrl;
  output Home05ctrl;
  output Home133ctrl;
  output Home15ctrl;
  output INT;
  output LED1;
  output LED2;
  output LED3;
  output LED4;
  output LED5;
  output MHSI;
  output MTRpwr;
  output MTRpwrn;
  output MTXI;
  output PAH0;
  output PAH1;
  output PAL0;
  output PAL1;
  output PBH0;
  output PBH1;
  output PBL0;
  output PBL1;
  output PresEn;
  output PresSlct;
  output SCLout;
  output TP10;
  output TP11;
  output TP12;
  output TmpEn;
  output TmpSlct;
  inout SCL;
  input [5 : 0] I2CS;
  inout [7 : 0] AD;
  wire NlwRenamedSig_IO_WR;
  wire \WR_II/UIM ;
  wire NlwRenamedSig_IO_RD;
  wire \RD_II/UIM ;
  wire \MSPReset_II/UIM ;
  wire \AD<0>_II/UIM ;
  wire NlwRenamedSig_IO_AS;
  wire \AS_II/UIM ;
  wire U2_ASedge;
  wire \AS_II/IREG ;
  wire \Mclk_II/FCLK ;
  wire \U2_ASedge_MC.REG_tsimcreated_inv_Mclk_II/FCLK ;
  wire Gnd;
  wire PRLD = glbl.PRLD;
  wire Vcc;
  wire \AD<4>_II/UIM ;
  wire \AD<5>_II/UIM ;
  wire \AD<6>_II/UIM ;
  wire \U4/ctrlr[6] ;
  wire \AD<6>_II/IREG ;
  wire \FOOBAR10__ctinst/0 ;
  wire \U4/ctrlr<6>_MC_tsimcreated_prld_ ;
  wire \U4/ctrlr<6>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ;
  wire \FOOBAR10__ctinst/4 ;
  wire \AD<7>_II/UIM ;
  wire \U4/ctrlr[7] ;
  wire \AD<7>_II/IREG ;
  wire \FOOBAR9__ctinst/0 ;
  wire \U4/ctrlr<7>_MC_tsimcreated_prld_ ;
  wire \U4/ctrlr<7>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ;
  wire \FOOBAR9__ctinst/4 ;
  wire \AD<3>_II/UIM ;
  wire \U4/ctrlr[3] ;
  wire \AD<3>_II/IREG ;
  wire \FOOBAR12__ctinst/0 ;
  wire \U4/ctrlr<3>_MC_tsimcreated_prld_ ;
  wire \U4/ctrlr<3>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ;
  wire \FOOBAR12__ctinst/4 ;
  wire \AD<1>_II/UIM ;
  wire \AD<2>_II/UIM ;
  wire \U4/ctrlr[2] ;
  wire \AD<2>_II/IREG ;
  wire \U4/ctrlr<2>_MC_tsimcreated_prld_ ;
  wire \U4/ctrlr<2>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ;
  wire \SCLreset_II/UIM ;
  wire \U11_U4/Line_last ;
  wire \SCLreset_II/IREG ;
  wire \U11_U4/Line_last_MC.REG_tsimcreated_inv_Mclk_II/FCLK ;
  wire \SCLinc_II/UIM ;
  wire \U11_U1/Line_last ;
  wire \SCLinc_II/IREG ;
  wire \U11_U1/Line_last_MC.REG_tsimcreated_inv_Mclk_II/FCLK ;
  wire \SCL_II/UIM ;
  wire \U11_U2/Line_last ;
  wire \SCL_II/IREG ;
  wire \U11_U2/Line_last_MC.REG_tsimcreated_inv_Mclk_II/FCLK ;
  wire \PhaseA_Encoder0_II/UIM ;
  wire \PhaseB_Encoder0_II/UIM ;
  wire \GP_Motor0_0_II/UIM ;
  wire \U1/U4/InEdge0r ;
  wire \GP_Motor0_0_II/IREG ;
  wire \U1/U4/InEdge0r_MC.REG_tsimcreated_inv_Mclk_II/FCLK ;
  wire \PhaseB_Encoder1_II/UIM ;
  wire \PhaseA_Encoder1_II/UIM ;
  wire \GP_Motor1_0_II/UIM ;
  wire \U1/U4/InEdge1r ;
  wire \GP_Motor1_0_II/IREG ;
  wire \U1/U4/InEdge1r_MC.REG_tsimcreated_inv_Mclk_II/FCLK ;
  wire \I2CS<0>_II/UIM ;
  wire NlwRenamedSig_IO_Home033FLG;
  wire \Home033FLG_II/UIM ;
  wire \Home033FLG_II/IREG ;
  wire \U4/Flgreg<0>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ;
  wire \FOOBAR21__ctinst/4 ;
  wire NlwRenamedSig_IO_Home15FLG;
  wire \Home15FLG_II/UIM ;
  wire \Home15FLG_II/IREG ;
  wire \U4/Flgreg<5>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ;
  wire NlwRenamedSig_IO_Home133FLG;
  wire \Home133FLG_II/UIM ;
  wire \Home133FLG_II/IREG ;
  wire \U4/Flgreg<4>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ;
  wire NlwRenamedSig_IO_Home05FLG;
  wire \Home05FLG_II/UIM ;
  wire \Home05FLG_II/IREG ;
  wire \U4/Flgreg<1>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ;
  wire NlwRenamedSig_IO_Enc15FLG;
  wire \Enc15FLG_II/UIM ;
  wire \Enc15FLG_II/IREG ;
  wire \U4/Flgreg<7>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ;
  wire \FOOBAR24__ctinst/4 ;
  wire NlwRenamedSig_IO_Enc133FLG;
  wire \Enc133FLG_II/UIM ;
  wire \Enc133FLG_II/IREG ;
  wire \U4/Flgreg<6>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ;
  wire NlwRenamedSig_IO_Enc05FLG;
  wire \Enc05FLG_II/UIM ;
  wire \Enc05FLG_II/IREG ;
  wire \U4/Flgreg<3>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ;
  wire NlwRenamedSig_IO_Enc033FLG;
  wire \Enc033FLG_II/UIM ;
  wire \Enc033FLG_II/IREG ;
  wire \U4/Flgreg<2>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ;
  wire \INTbus_II/UIM ;
  wire \RLS0_II/UIM ;
  wire \DIR0_II/UIM ;
  wire \I2CS<1>_II/UIM ;
  wire \FLS0_II/UIM ;
  wire \I2CS<4>_II/UIM ;
  wire \DIR1_II/UIM ;
  wire \FLS1_II/UIM ;
  wire \RLS1_II/UIM ;
  wire \I2CS<5>_II/UIM ;
  wire \Brake0_II/UIM ;
  wire \Brake1_II/UIM ;
  wire \PWM5_II/UIM ;
  wire \PWM3_II/UIM ;
  wire \MReset_II/UIM ;
  wire \HSI_II/UIM ;
  wire \MHSO_II/UIM ;
  wire \I2CS<2>_II/UIM ;
  wire \I2CS<3>_II/UIM ;
  wire \LightSense_II/UIM ;
  wire \TXI_II/UIM ;
  wire \PWM1_II/UIM ;
  wire \PWM2_II/UIM ;
  wire \Home0_II/UIM ;
  wire \U1/U4/HE0stater ;
  wire \Home0_II/IREG ;
  wire \U1/U4/HE0stater_MC.REG_tsimcreated_inv_Mclk_II/FCLK ;
  wire \Home1_II/UIM ;
  wire \U1/U4/HE1stater ;
  wire \Home1_II/IREG ;
  wire \U1/U4/HE1stater_MC.REG_tsimcreated_inv_Mclk_II/FCLK ;
  wire \AD<0>_MC.Q ;
  wire \AD<0>_MC.OE ;
  wire \AD<1>_MC.Q ;
  wire \AD<1>_MC.OE ;
  wire \AD<4>_MC.Q ;
  wire \AD<4>_MC.OE ;
  wire \AD<5>_MC.Q ;
  wire \AD<5>_MC.OE ;
  wire \Enc033ctrl_MC.Q ;
  wire \Enc05ctrl_MC.Q ;
  wire \Enc133ctrl_MC.Q ;
  wire \Enc15ctrl_MC.Q ;
  wire \GPIO8_MC.Q ;
  wire \GPIO9_MC.Q ;
  wire \GP_Motor0_1_MC.Q ;
  wire \GP_Motor1_1_MC.Q ;
  wire \HSO_MC.Q ;
  wire \Home033ctrl_MC.Q ;
  wire \Home05ctrl_MC.Q ;
  wire \Home133ctrl_MC.Q ;
  wire \Home15ctrl_MC.Q ;
  wire \INT_MC.Q ;
  wire \LED1_MC.Q ;
  wire \LED2_MC.Q ;
  wire \LED3_MC.Q ;
  wire \LED4_MC.Q ;
  wire \LED5_MC.Q ;
  wire \MHSI_MC.Q ;
  wire \MTRpwr_MC.Q ;
  wire \MTRpwrn_MC.Q ;
  wire \MTXI_MC.Q ;
  wire \PAH0_MC.Q ;
  wire \PAH1_MC.Q ;
  wire \PAL0_MC.Q ;
  wire \PAL1_MC.Q ;
  wire \PBH0_MC.Q ;
  wire \PBH1_MC.Q ;
  wire \PBL0_MC.Q ;
  wire \PBL1_MC.Q ;
  wire \PresEn_MC.Q ;
  wire \PresSlct_MC.Q ;
  wire \SCLout_MC.Q ;
  wire \TP10_MC.Q ;
  wire \TP11_MC.Q ;
  wire \TP12_MC.Q ;
  wire \TmpEn_MC.Q ;
  wire \TmpSlct_MC.Q ;
  wire \U11_U2/Line_last_MC.Q ;
  wire \U11_U2/Line_last_MC.OE ;
  wire \U4/ctrlr<2>_MC.Q ;
  wire \U4/ctrlr<2>_MC.OE ;
  wire \U4/ctrlr<3>_MC.Q ;
  wire \U4/ctrlr<3>_MC.OE ;
  wire \U4/ctrlr<6>_MC.Q ;
  wire \U4/ctrlr<6>_MC.OE ;
  wire \U4/ctrlr<7>_MC.Q ;
  wire \U4/ctrlr<7>_MC.OE ;
  wire \AD<0>_MC.Q_tsimrenamed_net_ ;
  wire \AD<0>_MC.BUFOE.OUT ;
  wire \FOOBAR1__ctinst/7 ;
  wire \AD<0>_MC.D ;
  wire \AD<0>_MC.D1 ;
  wire \AD<0>_MC.D2 ;
  wire DCORI2CCNTr;
  wire \outDATA<0>\$WA0.UIM ;
  wire \AD<0>_MC.D2_PT_0 ;
  wire DCOR0THRESLOWr;
  wire \outDATA<0>\$WA2.UIM ;
  wire \AD<0>_MC.D2_PT_1 ;
  wire DCORCONFIGr;
  wire \outDATA<0>\$WA3.UIM ;
  wire \AD<0>_MC.D2_PT_2 ;
  wire DCORENCPWRr;
  wire \outDATA<0>\$WA5.UIM ;
  wire \AD<0>_MC.D2_PT_3 ;
  wire DCORIFGr;
  wire \outDATA<0>\$WA6.UIM ;
  wire \AD<0>_MC.D2_PT_4 ;
  wire \outDATA<0>\$WA4.UIM ;
  wire N_PZ_1016;
  wire \AD<0>_MC.D2_PT_5 ;
  wire \outDATA<0>\$WA1.UIM ;
  wire N_PZ_1017;
  wire \AD<0>_MC.D2_PT_6 ;
  wire N_PZ_1053;
  wire \AD<0>_MC.D2_PT_7 ;
  wire \DCORI2CCNTr_MC.Q ;
  wire \DCORI2CCNTr_MC.D ;
  wire \DCORI2CCNTr_MC.D1 ;
  wire \DCORI2CCNTr_MC.D2 ;
  wire \U2_ADDR_reg<0>_MC.Q ;
  wire \U2_ADDR_reg<0>_MC.D ;
  wire \U2_ADDR_reg<0>_MC_tsimcreated_xor_ ;
  wire \U2_ADDR_reg<0>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ;
  wire \U2_ADDR_reg<0>_MC.D1 ;
  wire \U2_ADDR_reg<0>_MC.D2 ;
  wire \U2_ADDR_reg<0>_MC.D2_PT_0 ;
  wire \U2_ADDR_reg<0>_MC.D2_PT_1 ;
  wire \U2_ADDR_reg<0>_MC.D2_PT_2 ;
  wire U2_AutoInc;
  wire U2_WRRDedge;
  wire N_PZ_992;
  wire \U2_ADDR_reg<0>_MC.D2_PT_3 ;
  wire \U2_ADDR_reg<4>_MC.Q ;
  wire \U2_ADDR_reg<4>_MC.D ;
  wire \U2_ADDR_reg<4>_MC_tsimcreated_xor_ ;
  wire \U2_ADDR_reg<4>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ;
  wire \U2_ADDR_reg<4>_MC.D1 ;
  wire \U2_ADDR_reg<4>_MC.D2 ;
  wire \U2_ADDR_reg<4>_MC.D2_PT_0 ;
  wire \U2_ADDR_reg<4>_MC.D2_PT_1 ;
  wire \U2_ADDR_reg<4>_MC.D2_PT_2 ;
  wire \U2_ADDR_reg<5>_MC.Q ;
  wire \U2_ADDR_reg<5>_MC.D ;
  wire \U2_ADDR_reg<5>_MC_tsimcreated_xor_ ;
  wire \U2_ADDR_reg<5>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ;
  wire \U2_ADDR_reg<5>_MC.D1 ;
  wire \U2_ADDR_reg<5>_MC.D2 ;
  wire \U2_ADDR_reg<5>_MC.D2_PT_0 ;
  wire \U2_ADDR_reg<5>_MC.D2_PT_1 ;
  wire \U2_ADDR_reg<5>_MC.D2_PT_2 ;
  wire \U2_ADDR_reg<6>_MC.Q ;
  wire \U2_ADDR_reg<6>_MC.D ;
  wire \U2_ADDR_reg<6>_MC_tsimcreated_xor_ ;
  wire \U2_ADDR_reg<6>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ;
  wire \U2_ADDR_reg<6>_MC.D1 ;
  wire \U2_ADDR_reg<6>_MC.D2 ;
  wire \U2_ADDR_reg<6>_MC.D2_PT_0 ;
  wire \U2_ADDR_reg<6>_MC.D2_PT_1 ;
  wire \U2_ADDR_reg<6>_MC.D2_PT_2 ;
  wire \U2_ADDR_reg<7>_MC.Q ;
  wire \U2_ADDR_reg<7>_MC.D ;
  wire \U2_ADDR_reg<7>_MC_tsimcreated_xor_ ;
  wire \U2_ADDR_reg<7>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ;
  wire \U2_ADDR_reg<7>_MC.D1 ;
  wire \U2_ADDR_reg<7>_MC.D2 ;
  wire \U2_ADDR_reg<7>_MC.D2_PT_0 ;
  wire \U2_ADDR_reg<7>_MC.D2_PT_1 ;
  wire \U2_ADDR_reg<7>_MC.D2_PT_2 ;
  wire \U2_AutoInc_MC.Q ;
  wire \U2_AutoInc_MC.D ;
  wire \U2_AutoInc_MC.REG_tsimcreated_inv_Mclk_II/FCLK ;
  wire \FOOBAR6__ctinst/4 ;
  wire \U2_AutoInc_MC.D1 ;
  wire \U2_AutoInc_MC.D2 ;
  wire \U2_WRRDedge_MC.Q ;
  wire \U2_WRRDedge_MC.D ;
  wire \U2_WRRDedge_MC.REG_tsimcreated_inv_Mclk_II/FCLK ;
  wire \U2_WRRDedge_MC.D1 ;
  wire \U2_WRRDedge_MC.D2 ;
  wire \N_PZ_1007_MC.Q ;
  wire N_PZ_1007;
  wire \N_PZ_1007_MC.D ;
  wire \N_PZ_1007_MC.D1 ;
  wire \N_PZ_1007_MC.D2 ;
  wire \N_PZ_992_MC.Q ;
  wire \N_PZ_992_MC.D ;
  wire \N_PZ_992_MC.D1 ;
  wire \N_PZ_992_MC.D2 ;
  wire \N_PZ_992_MC.D2_PT_0 ;
  wire \N_PZ_992_MC.D2_PT_1 ;
  wire \U2_ADDR_reg<3>_MC.Q ;
  wire \U2_ADDR_reg<3>_MC.D ;
  wire \U2_ADDR_reg<3>_MC_tsimcreated_xor_ ;
  wire \U2_ADDR_reg<3>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ;
  wire \U2_ADDR_reg<3>_MC.D1 ;
  wire \U2_ADDR_reg<3>_MC.D2 ;
  wire \U2_ADDR_reg<3>_MC.D2_PT_0 ;
  wire \U2_ADDR_reg<3>_MC.D2_PT_1 ;
  wire \U2_ADDR_reg<3>_MC.D2_PT_2 ;
  wire \U2_ADDR_reg<3>_MC.D2_PT_3 ;
  wire \U2_ADDR_reg<1>_MC.Q ;
  wire \U2_ADDR_reg<1>_MC.D ;
  wire \U2_ADDR_reg<1>_MC_tsimcreated_xor_ ;
  wire \U2_ADDR_reg<1>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ;
  wire \U2_ADDR_reg<1>_MC.D1 ;
  wire \U2_ADDR_reg<1>_MC.D2 ;
  wire \U2_ADDR_reg<1>_MC.D2_PT_0 ;
  wire \U2_ADDR_reg<1>_MC.D2_PT_1 ;
  wire \U2_ADDR_reg<1>_MC.D2_PT_2 ;
  wire \U2_ADDR_reg<1>_MC.D2_PT_3 ;
  wire \U2_ADDR_reg<2>_MC.Q ;
  wire \U2_ADDR_reg<2>_MC.D ;
  wire \U2_ADDR_reg<2>_MC_tsimcreated_xor_ ;
  wire \U2_ADDR_reg<2>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ;
  wire \U2_ADDR_reg<2>_MC.D1 ;
  wire \U2_ADDR_reg<2>_MC.D2 ;
  wire \U2_ADDR_reg<2>_MC.D2_PT_0 ;
  wire \U2_ADDR_reg<2>_MC.D2_PT_1 ;
  wire \U2_ADDR_reg<2>_MC.D2_PT_2 ;
  wire \U2_ADDR_reg<2>_MC.D2_PT_3 ;
  wire \outDATA<0>\$WA0.UIM_MC.Q ;
  wire \outDATA<0>\$WA0.UIM_MC.D ;
  wire \outDATA<0>\$WA0.UIM_MC.D1 ;
  wire \outDATA<0>\$WA0.UIM_MC.D2 ;
  wire \U11_U3_counterr<0>_MC.Q ;
  wire \U11_U3_counterr<0>_MC.D ;
  wire \U11_U3_counterr<0>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ;
  wire \U11_U3_counterr<0>_MC.D1 ;
  wire \U11_U3_counterr<0>_MC.D2 ;
  wire \U11_U3_counterr<0>_MC.D2_PT_0 ;
  wire U11_Incdetect;
  wire U11_SCLdetect;
  wire \U11_U3_counterr<0>_MC.D2_PT_1 ;
  wire \U11_U3_counterr<0>_MC.D2_PT_2 ;
  wire \U11_U3_counterr<0>_MC.D2_PT_3 ;
  wire U11_ResetDetect;
  wire \U11_U3_counterr<0>_MC.D2_PT_4 ;
  wire \TP12_MC.UIM ;
  wire \U11_U3_counterr<0>_MC.D2_PT_5 ;
  wire \U11_Incdetect_MC.Q ;
  wire \U11_Incdetect_MC.D ;
  wire \U11_Incdetect_MC.REG_tsimcreated_inv_Mclk_II/FCLK ;
  wire \U11_Incdetect_MC.D1 ;
  wire \U11_Incdetect_MC.D2 ;
  wire \U11_SCLdetect_MC.Q ;
  wire \U11_SCLdetect_MC.D ;
  wire \U11_SCLdetect_MC.REG_tsimcreated_inv_Mclk_II/FCLK ;
  wire \U11_SCLdetect_MC.D1 ;
  wire \U11_SCLdetect_MC.D2 ;
  wire \U11_U2/Line_last_MC.D ;
  wire \U11_U2/Line_last_MC.BUFOE.OUT ;
  wire \FOOBAR4__ctinst/0 ;
  wire \U11_U2/Line_last_MC.D1 ;
  wire \U11_U2/Line_last_MC.D2 ;
  wire \TP12_MC.Q_tsimrenamed_net_ ;
  wire \TP12_MC.D ;
  wire \TP12_MC.D1 ;
  wire \TP12_MC.D2 ;
  wire \U11_U3_counterr<3>_MC.Q ;
  wire \U11_U3_counterr<3>_MC.D ;
  wire \U11_U3_counterr<3>_MC_tsimcreated_xor_ ;
  wire \U11_U3_counterr<3>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ;
  wire \U11_U3_counterr<3>_MC.D1 ;
  wire \U11_U3_counterr<3>_MC.D2 ;
  wire \U11_U3_counterr<3>_MC.D2_PT_0 ;
  wire N_PZ_1128;
  wire \U11_U3_counterr<3>_MC.D2_PT_1 ;
  wire \U11_U3_counterr<3>_MC.D2_PT_2 ;
  wire \U11_U3_counterr<3>_MC.D2_PT_3 ;
  wire \U11_U3_counterr<3>_MC.D2_PT_4 ;
  wire \U11_U3_counterr<3>_MC.D2_PT_5 ;
  wire \U11_U3_counterr<3>_MC.D2_PT_6 ;
  wire \N_PZ_1128_MC.Q ;
  wire \N_PZ_1128_MC.D ;
  wire \N_PZ_1128_MC.D1 ;
  wire \N_PZ_1128_MC.D2 ;
  wire \N_PZ_1128_MC.D2_PT_0 ;
  wire \N_PZ_1128_MC.D2_PT_1 ;
  wire \outDATA<7>\$WA6.UIM ;
  wire \N_PZ_1128_MC.D2_PT_2 ;
  wire \U11_ResetDetect_MC.Q ;
  wire \U11_ResetDetect_MC.D ;
  wire \U11_ResetDetect_MC.REG_tsimcreated_inv_Mclk_II/FCLK ;
  wire \U11_ResetDetect_MC.D1 ;
  wire \U11_ResetDetect_MC.D2 ;
  wire \outDATA<7>\$WA6.UIM_MC.Q ;
  wire \outDATA<7>\$WA6.UIM_MC.D ;
  wire \outDATA<7>\$WA6.UIM_MC.D1 ;
  wire \outDATA<7>\$WA6.UIM_MC.D2 ;
  wire \U11_U3_counterr<1>_MC.Q ;
  wire \U11_U3_counterr<1>_MC.D ;
  wire \U11_U3_counterr<1>_MC_tsimcreated_xor_ ;
  wire \U11_U3_counterr<1>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ;
  wire \U11_U3_counterr<1>_MC.D1 ;
  wire \U11_U3_counterr<1>_MC.D2 ;
  wire \U11_U3_counterr<1>_MC.D2_PT_0 ;
  wire \U11_U3_counterr<1>_MC.D2_PT_1 ;
  wire \U11_U3_counterr<1>_MC.D2_PT_2 ;
  wire \U11_U3_counterr<2>_MC.Q ;
  wire \U11_U3_counterr<2>_MC.D ;
  wire \U11_U3_counterr<2>_MC_tsimcreated_xor_ ;
  wire \U11_U3_counterr<2>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ;
  wire \U11_U3_counterr<2>_MC.D1 ;
  wire \U11_U3_counterr<2>_MC.D2 ;
  wire \U11_U3_counterr<2>_MC.D2_PT_0 ;
  wire \U11_U3_counterr<2>_MC.D2_PT_1 ;
  wire \U11_U3_counterr<2>_MC.D2_PT_2 ;
  wire \U11_U3_counterr<4>_MC.Q ;
  wire \U11_U3_counterr<4>_MC.D ;
  wire \U11_U3_counterr<4>_MC_tsimcreated_xor_ ;
  wire \U11_U3_counterr<4>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ;
  wire \U11_U3_counterr<4>_MC.D1 ;
  wire \U11_U3_counterr<4>_MC.D2 ;
  wire \U11_U3_counterr<4>_MC.D2_PT_0 ;
  wire \U11_U3_counterr<4>_MC.D2_PT_1 ;
  wire \U11_U3_counterr<4>_MC.D2_PT_2 ;
  wire \U11_U3_counterr<4>_MC.D2_PT_3 ;
  wire \U11_U3_counterr<5>_MC.Q ;
  wire \U11_U3_counterr<5>_MC.D ;
  wire \U11_U3_counterr<5>_MC_tsimcreated_xor_ ;
  wire \U11_U3_counterr<5>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ;
  wire \U11_U3_counterr<5>_MC.D1 ;
  wire \U11_U3_counterr<5>_MC.D2 ;
  wire \U11_U3_counterr<5>_MC.D2_PT_0 ;
  wire \U11_U3_counterr<5>_MC.D2_PT_1 ;
  wire \U11_U3_counterr<5>_MC.D2_PT_2 ;
  wire \U11_U3_counterr<5>_MC.D2_PT_3 ;
  wire \DCOR0THRESLOWr_MC.Q ;
  wire \DCOR0THRESLOWr_MC.D ;
  wire \DCOR0THRESLOWr_MC.D1 ;
  wire \DCOR0THRESLOWr_MC.D2 ;
  wire \outDATA<0>\$WA2.UIM_MC.Q ;
  wire \outDATA<0>\$WA2.UIM_MC.D ;
  wire \outDATA<0>\$WA2.UIM_MC.D1 ;
  wire \outDATA<0>\$WA2.UIM_MC.D2 ;
  wire \outDATA<0>\$WA2.UIM_MC.D2_PT_0 ;
  wire DCOR0THRESHIGHr;
  wire \outDATA<0>\$WA2.UIM_MC.D2_PT_1 ;
  wire DCOR1THRESLOWr;
  wire \outDATA<0>\$WA2.UIM_MC.D2_PT_2 ;
  wire \outDATA<0>\$WA2.UIM_MC.D2_PT_3 ;
  wire \U1/U4/Latch0r<0>_MC.Q ;
  wire \U1/U4/Latch0r<0>_MC.D ;
  wire \U1/U4/Latch0r<0>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ;
  wire \U1/U4/Latch0r<0>_MC.D1 ;
  wire \U1/U4/Latch0r<0>_MC.D2 ;
  wire N_PZ_1018;
  wire \U1/U4/Latch0r<0>_MC.D2_PT_0 ;
  wire \U1/U4/Latch0r<0>_MC.D2_PT_1 ;
  wire \U1/Channel0<0>_MC.Q ;
  wire \U1/Channel0<0>_MC.D ;
  wire \U1/Channel0<0>_MC_tsimcreated_xor_ ;
  wire \U1/Channel0<0>_MC.D1 ;
  wire \U1/Channel0<0>_MC.D2 ;
  wire N_PZ_982;
  wire \U1/Channel0<0>_MC.D2_PT_0 ;
  wire \U1/Zero0 ;
  wire \U1/U1/CurrState_Sreg0_FFD1 ;
  wire \U1/U1/CurrState_Sreg0_FFD3 ;
  wire \U1/U1/CurrState_Sreg0_FFD2 ;
  wire \U1/U1/CurrState_Sreg0_FFD4 ;
  wire \U1/Channel0<0>_MC.D2_PT_1 ;
  wire \U1/Channel0<0>_MC.D2_PT_2 ;
  wire \U1/Zero0_MC.Q ;
  wire \U1/Zero0_MC.D ;
  wire \U1/Zero0_MC.REG_tsimcreated_inv_Mclk_II/FCLK ;
  wire \U1/Zero0_MC.D1 ;
  wire \U1/Zero0_MC.D2 ;
  wire \U1/Zero0_MC.D2_PT_0 ;
  wire DCORIFGw;
  wire \U1/Zero0_MC.D2_PT_1 ;
  wire DCORENCCTLw;
  wire \U1/Zero0_MC.D2_PT_2 ;
  wire NET2482;
  wire \U1/U4/RF0r ;
  wire \U1/U4/E0r ;
  wire \U1/U4/HE0statelastr ;
  wire \U1/Zero0_MC.D2_PT_3 ;
  wire \U1/Zero0_MC.D2_PT_4 ;
  wire \DCORIFGw_MC.Q ;
  wire \DCORIFGw_MC.D ;
  wire \DCORIFGw_MC.D1 ;
  wire \DCORIFGw_MC.D2 ;
  wire \DCORENCCTLw_MC.Q ;
  wire \DCORENCCTLw_MC.D ;
  wire \DCORENCCTLw_MC.D1 ;
  wire \DCORENCCTLw_MC.D2 ;
  wire \NET2482_MC.Q ;
  wire \NET2482_MC.D ;
  wire NET2482_MC_tsimcreated_xor_;
  wire \NET2482_MC.REG_tsimcreated_inv_Mclk_II/FCLK ;
  wire \NET2482_MC.D1 ;
  wire \NET2482_MC.D2 ;
  wire \NET2482_MC.D2_PT_0 ;
  wire \NET2482_MC.D2_PT_1 ;
  wire \NET2482_MC.D2_PT_2 ;
  wire \NET2482_MC.D2_PT_3 ;
  wire \U1/U4/RF0r_MC.Q ;
  wire \U1/U4/RF0r_MC.D ;
  wire \U1/U4/RF0r_MC.REG_tsimcreated_inv_Mclk_II/FCLK ;
  wire \U1/U4/RF0r_MC.D1 ;
  wire \U1/U4/RF0r_MC.D2 ;
  wire \U1/U4/RF0r_MC.D2_PT_0 ;
  wire \U1/U4/RF0r_MC.D2_PT_1 ;
  wire \U1/U4/E0r_MC.Q ;
  wire \U1/U4/E0r_MC.D ;
  wire \U1/U4/E0r_MC.REG_tsimcreated_inv_Mclk_II/FCLK ;
  wire \U1/U4/E0r_MC.D1 ;
  wire \U1/U4/E0r_MC.D2 ;
  wire \U1/U4/E0r_MC.D2_PT_0 ;
  wire \U1/U4/E0r_MC.D2_PT_1 ;
  wire \U1/U4/HE0statelastr_MC.Q ;
  wire \U1/U4/HE0statelastr_MC.D ;
  wire \U1/U4/HE0statelastr_MC.REG_tsimcreated_inv_Mclk_II/FCLK ;
  wire \U1/U4/HE0statelastr_MC.D1 ;
  wire \U1/U4/HE0statelastr_MC.D2 ;
  wire \U1/U1/CurrState_Sreg0_FFD1_MC.Q ;
  wire \U1/U1/CurrState_Sreg0_FFD1_MC.D ;
  wire \U1/U1/CurrState_Sreg0_FFD1_MC.D1 ;
  wire \U1/U1/CurrState_Sreg0_FFD1_MC.D2 ;
  wire \U1/U1/CurrState_Sreg0_FFD1_MC.D2_PT_0 ;
  wire \U1/U1/CurrState_Sreg0_FFD1_MC.D2_PT_1 ;
  wire \U1/U1/CurrState_Sreg0_FFD1_MC.D2_PT_2 ;
  wire \U1/U1/CurrState_Sreg0_FFD3_MC.Q ;
  wire \U1/U1/CurrState_Sreg0_FFD3_MC.D ;
  wire \U1/U1/CurrState_Sreg0_FFD3_MC.D1 ;
  wire \U1/U1/CurrState_Sreg0_FFD3_MC.D2 ;
  wire \U1/U1/CurrState_Sreg0_FFD3_MC.D2_PT_0 ;
  wire \U1/U1/CurrState_Sreg0_FFD3_MC.D2_PT_1 ;
  wire \U1/U1/CurrState_Sreg0_FFD3_MC.D2_PT_2 ;
  wire \U1/U1/CurrState_Sreg0_FFD3_MC.D2_PT_3 ;
  wire \U1/U1/CurrState_Sreg0_FFD2_MC.Q ;
  wire \U1/U1/CurrState_Sreg0_FFD2_MC.D ;
  wire \U1/U1/CurrState_Sreg0_FFD2_MC.D1 ;
  wire \U1/U1/CurrState_Sreg0_FFD2_MC.D2 ;
  wire \U1/U1/CurrState_Sreg0_FFD2_MC.D2_PT_0 ;
  wire \U1/U1/CurrState_Sreg0_FFD2_MC.D2_PT_1 ;
  wire \U1/U1/CurrState_Sreg0_FFD2_MC.D2_PT_2 ;
  wire \U1/U1/CurrState_Sreg0_FFD2_MC.D2_PT_3 ;
  wire \U1/U1/CurrState_Sreg0_FFD2_MC.D2_PT_4 ;
  wire \U1/U1/CurrState_Sreg0_FFD2_MC.D2_PT_5 ;
  wire \U1/U1/CurrState_Sreg0_FFD2_MC.D2_PT_6 ;
  wire \U1/U1/CurrState_Sreg0_FFD2_MC.D2_PT_7 ;
  wire \U1/U1/CurrState_Sreg0_FFD4_MC.Q ;
  wire \U1/U1/CurrState_Sreg0_FFD4_MC.D ;
  wire \U1/U1/CurrState_Sreg0_FFD4_MC.D1 ;
  wire \U1/U1/CurrState_Sreg0_FFD4_MC.D2 ;
  wire \N_PZ_982_MC.Q ;
  wire \N_PZ_982_MC.D ;
  wire \N_PZ_982_MC.D1 ;
  wire \N_PZ_982_MC.D2 ;
  wire \N_PZ_1018_MC.Q ;
  wire \N_PZ_1018_MC.D ;
  wire \N_PZ_1018_MC.D1 ;
  wire \N_PZ_1018_MC.D2 ;
  wire NET2501;
  wire \U1/U4/LatchEdge0r ;
  wire \outDATA<6>\$WA3.UIM ;
  wire \N_PZ_1018_MC.D2_PT_0 ;
  wire \N_PZ_1018_MC.D2_PT_1 ;
  wire \NET2501_MC.Q ;
  wire \NET2501_MC.D ;
  wire NET2501_MC_tsimcreated_xor_;
  wire \NET2501_MC.REG_tsimcreated_inv_Mclk_II/FCLK ;
  wire \NET2501_MC.D1 ;
  wire \NET2501_MC.D2 ;
  wire \NET2501_MC.D2_PT_0 ;
  wire \NET2501_MC.D2_PT_1 ;
  wire \U1/U4/LatchEdge0r_MC.Q ;
  wire \U1/U4/LatchEdge0r_MC.D ;
  wire \U1/U4/LatchEdge0r_MC.REG_tsimcreated_inv_Mclk_II/FCLK ;
  wire \U1/U4/LatchEdge0r_MC.D1 ;
  wire \U1/U4/LatchEdge0r_MC.D2 ;
  wire \U1/U4/LatchEdge0r_MC.D2_PT_0 ;
  wire \U1/U4/LatchEdge0r_MC.D2_PT_1 ;
  wire \outDATA<6>\$WA3.UIM_MC.Q ;
  wire \outDATA<6>\$WA3.UIM_MC.D ;
  wire \outDATA<6>\$WA3.UIM_MC.D1 ;
  wire \outDATA<6>\$WA3.UIM_MC.D2 ;
  wire \U1/U4/Latch0r<8>_MC.Q ;
  wire \U1/U4/Latch0r<8>_MC.D ;
  wire \U1/U4/Latch0r<8>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ;
  wire \U1/U4/Latch0r<8>_MC.D1 ;
  wire \U1/U4/Latch0r<8>_MC.D2 ;
  wire \U1/U4/Latch0r<8>_MC.D2_PT_0 ;
  wire \U1/U4/Latch0r<8>_MC.D2_PT_1 ;
  wire \U1/Channel0<8>_MC.Q ;
  wire \U1/Channel0<8>_MC.D ;
  wire \U1/Channel0<8>_MC_tsimcreated_xor_ ;
  wire \U1/Channel0<8>_MC.D1 ;
  wire \U1/Channel0<8>_MC.D2 ;
  wire N_PZ_1024;
  wire \U1/Channel0<8>_MC.D2_PT_0 ;
  wire \U1/Channel0<8>_MC.D2_PT_1 ;
  wire N_PZ_1021;
  wire \U1/Channel0<8>_MC.D2_PT_2 ;
  wire \U1/Channel0<8>_MC.D2_PT_3 ;
  wire \U1/Channel0<8>_MC.D2_PT_4 ;
  wire \U1/Channel0<8>_MC.D2_PT_5 ;
  wire \U1/U2/location_Maddsub__n0000__n0075<0>_MC.Q ;
  wire \U1/U2/location_Maddsub__n0000__n0075<0>_MC.D ;
  wire \U1/U2/location_Maddsub__n0000__n0075<0>_MC.D1 ;
  wire \U1/U2/location_Maddsub__n0000__n0075<0>_MC.D2 ;
  wire N_PZ_997;
  wire \U1/U2/location_Maddsub__n0000__n0075<0>_MC.D2_PT_0 ;
  wire \U1/U2/location_Maddsub__n0000__n0075<0>_MC.D2_PT_1 ;
  wire \N_PZ_997_MC.Q ;
  wire \N_PZ_997_MC.D ;
  wire \N_PZ_997_MC.D1 ;
  wire \N_PZ_997_MC.D2 ;
  wire \U1/NET3721 ;
  wire \N_PZ_997_MC.D2_PT_0 ;
  wire \N_PZ_997_MC.D2_PT_1 ;
  wire \U1/NET3721_MC.Q ;
  wire \U1/NET3721_MC.D ;
  wire \U1/NET3721_MC.REG_tsimcreated_inv_Mclk_II/FCLK ;
  wire \U1/NET3721_MC.D1 ;
  wire \U1/NET3721_MC.D2 ;
  wire \U1/NET3721_MC.D2_PT_0 ;
  wire \U1/NET3721_MC.D2_PT_1 ;
  wire \U1/Channel0<5>_MC.Q ;
  wire \U1/Channel0<5>_MC.D ;
  wire \U1/Channel0<5>_MC_tsimcreated_xor_ ;
  wire \U1/Channel0<5>_MC.D1 ;
  wire \U1/Channel0<5>_MC.D2 ;
  wire \U1/Channel0<5>_MC.D2_PT_0 ;
  wire \U1/Channel0<5>_MC.D2_PT_1 ;
  wire \U1/Channel0<5>_MC.D2_PT_2 ;
  wire \U1/U2/location_Maddsub__n0000__n0067<0>_MC.Q ;
  wire \U1/U2/location_Maddsub__n0000__n0067<0>_MC.D ;
  wire \U1/U2/location_Maddsub__n0000__n0067<0>_MC.D1 ;
  wire \U1/U2/location_Maddsub__n0000__n0067<0>_MC.D2 ;
  wire \U1/U2/location_Maddsub__n0000__n0067<0>_MC.D2_PT_0 ;
  wire \U1/U2/location_Maddsub__n0000__n0067<0>_MC.D2_PT_1 ;
  wire \U1/Channel0<1>_MC.Q ;
  wire \U1/Channel0<1>_MC.D ;
  wire \U1/Channel0<1>_MC_tsimcreated_xor_ ;
  wire \U1/Channel0<1>_MC.D1 ;
  wire \U1/Channel0<1>_MC.D2 ;
  wire \U1/Channel0<1>_MC.D2_PT_0 ;
  wire \U1/Channel0<1>_MC.D2_PT_1 ;
  wire \U1/Channel0<1>_MC.D2_PT_2 ;
  wire \N_PZ_1021_MC.Q ;
  wire \N_PZ_1021_MC.D ;
  wire \N_PZ_1021_MC.D1 ;
  wire \N_PZ_1021_MC.D2 ;
  wire \N_PZ_1021_MC.D2_PT_0 ;
  wire \N_PZ_1021_MC.D2_PT_1 ;
  wire \N_PZ_1024_MC.Q ;
  wire \N_PZ_1024_MC.D ;
  wire \N_PZ_1024_MC.D1 ;
  wire \N_PZ_1024_MC.D2 ;
  wire \N_PZ_1024_MC.D2_PT_0 ;
  wire \N_PZ_1024_MC.D2_PT_1 ;
  wire \U1/Channel0<2>_MC.Q ;
  wire \U1/Channel0<2>_MC.D ;
  wire \U1/Channel0<2>_MC_tsimcreated_xor_ ;
  wire \U1/Channel0<2>_MC.D1 ;
  wire \U1/Channel0<2>_MC.D2 ;
  wire \U1/Channel0<2>_MC.D2_PT_0 ;
  wire \U1/Channel0<2>_MC.D2_PT_1 ;
  wire \U1/Channel0<2>_MC.D2_PT_2 ;
  wire \U1/Channel0<3>_MC.Q ;
  wire \U1/Channel0<3>_MC.D ;
  wire \U1/Channel0<3>_MC_tsimcreated_xor_ ;
  wire \U1/Channel0<3>_MC.D1 ;
  wire \U1/Channel0<3>_MC.D2 ;
  wire \U1/Channel0<3>_MC.D2_PT_0 ;
  wire \U1/Channel0<3>_MC.D2_PT_1 ;
  wire \U1/Channel0<3>_MC.D2_PT_2 ;
  wire \U1/Channel0<4>_MC.Q ;
  wire \U1/Channel0<4>_MC.D ;
  wire \U1/Channel0<4>_MC_tsimcreated_xor_ ;
  wire \U1/Channel0<4>_MC.D1 ;
  wire \U1/Channel0<4>_MC.D2 ;
  wire \U1/Channel0<4>_MC.D2_PT_0 ;
  wire \U1/Channel0<4>_MC.D2_PT_1 ;
  wire \U1/Channel0<4>_MC.D2_PT_2 ;
  wire \U1/Channel0<4>_MC.D2_PT_3 ;
  wire \U1/Channel0<4>_MC.D2_PT_4 ;
  wire \U1/Channel0<4>_MC.D2_PT_5 ;
  wire \U1/Channel0<6>_MC.Q ;
  wire \U1/Channel0<6>_MC.D ;
  wire \U1/Channel0<6>_MC_tsimcreated_xor_ ;
  wire \U1/Channel0<6>_MC.D1 ;
  wire \U1/Channel0<6>_MC.D2 ;
  wire \U1/Channel0<6>_MC.D2_PT_0 ;
  wire \U1/Channel0<6>_MC.D2_PT_1 ;
  wire \U1/Channel0<6>_MC.D2_PT_2 ;
  wire \U1/Channel0<7>_MC.Q ;
  wire \U1/Channel0<7>_MC.D ;
  wire \U1/Channel0<7>_MC_tsimcreated_xor_ ;
  wire \U1/Channel0<7>_MC.D1 ;
  wire \U1/Channel0<7>_MC.D2 ;
  wire \U1/Channel0<7>_MC.D2_PT_0 ;
  wire \U1/Channel0<7>_MC.D2_PT_1 ;
  wire \U1/Channel0<7>_MC.D2_PT_2 ;
  wire \DCOR0THRESHIGHr_MC.Q ;
  wire \DCOR0THRESHIGHr_MC.D ;
  wire \DCOR0THRESHIGHr_MC.D1 ;
  wire \DCOR0THRESHIGHr_MC.D2 ;
  wire \U1/U4/Latch1r<0>_MC.Q ;
  wire \U1/U4/Latch1r<0>_MC.D ;
  wire \U1/U4/Latch1r<0>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ;
  wire \U1/U4/Latch1r<0>_MC.D1 ;
  wire \U1/U4/Latch1r<0>_MC.D2 ;
  wire N_PZ_1019;
  wire \U1/U4/Latch1r<0>_MC.D2_PT_0 ;
  wire \U1/U4/Latch1r<0>_MC.D2_PT_1 ;
  wire \U1/Channel1<0>_MC.Q ;
  wire \U1/Channel1<0>_MC.D ;
  wire \U1/Channel1<0>_MC_tsimcreated_xor_ ;
  wire \U1/Channel1<0>_MC.D1 ;
  wire \U1/Channel1<0>_MC.D2 ;
  wire N_PZ_983;
  wire \U1/Channel1<0>_MC.D2_PT_0 ;
  wire \U1/Zero1 ;
  wire \U1/U6/CurrState_Sreg0_FFD3 ;
  wire \U1/U6/CurrState_Sreg0_FFD2 ;
  wire N_PZ_1154;
  wire \U1/Channel1<0>_MC.D2_PT_1 ;
  wire \N_PZ_983_MC.Q ;
  wire \N_PZ_983_MC.D ;
  wire \N_PZ_983_MC.D1 ;
  wire \N_PZ_983_MC.D2 ;
  wire \U1/Zero1_MC.Q ;
  wire \U1/Zero1_MC.D ;
  wire \U1/Zero1_MC.REG_tsimcreated_inv_Mclk_II/FCLK ;
  wire \U1/Zero1_MC.D1 ;
  wire \U1/Zero1_MC.D2 ;
  wire \U1/Zero1_MC.D2_PT_0 ;
  wire \U1/Zero1_MC.D2_PT_1 ;
  wire \U1/Zero1_MC.D2_PT_2 ;
  wire NET2493;
  wire \U1/U4/RF1r ;
  wire \U1/U4/E1r ;
  wire \U1/U4/HE1statelastr ;
  wire \U1/Zero1_MC.D2_PT_3 ;
  wire \U1/Zero1_MC.D2_PT_4 ;
  wire \NET2493_MC.Q ;
  wire \NET2493_MC.D ;
  wire NET2493_MC_tsimcreated_xor_;
  wire \NET2493_MC.REG_tsimcreated_inv_Mclk_II/FCLK ;
  wire \NET2493_MC.D1 ;
  wire \NET2493_MC.D2 ;
  wire \NET2493_MC.D2_PT_0 ;
  wire \NET2493_MC.D2_PT_1 ;
  wire \NET2493_MC.D2_PT_2 ;
  wire \NET2493_MC.D2_PT_3 ;
  wire \U1/U4/RF1r_MC.Q ;
  wire \U1/U4/RF1r_MC.D ;
  wire \U1/U4/RF1r_MC.REG_tsimcreated_inv_Mclk_II/FCLK ;
  wire \U1/U4/RF1r_MC.D1 ;
  wire \U1/U4/RF1r_MC.D2 ;
  wire \U1/U4/RF1r_MC.D2_PT_0 ;
  wire \U1/U4/RF1r_MC.D2_PT_1 ;
  wire \U1/U4/E1r_MC.Q ;
  wire \U1/U4/E1r_MC.D ;
  wire \U1/U4/E1r_MC.REG_tsimcreated_inv_Mclk_II/FCLK ;
  wire \U1/U4/E1r_MC.D1 ;
  wire \U1/U4/E1r_MC.D2 ;
  wire \U1/U4/E1r_MC.D2_PT_0 ;
  wire \U1/U4/E1r_MC.D2_PT_1 ;
  wire \U1/U4/HE1statelastr_MC.Q ;
  wire \U1/U4/HE1statelastr_MC.D ;
  wire \U1/U4/HE1statelastr_MC.REG_tsimcreated_inv_Mclk_II/FCLK ;
  wire \U1/U4/HE1statelastr_MC.D1 ;
  wire \U1/U4/HE1statelastr_MC.D2 ;
  wire \U1/U6/CurrState_Sreg0_FFD3_MC.Q ;
  wire \U1/U6/CurrState_Sreg0_FFD3_MC.D ;
  wire \U1/U6/CurrState_Sreg0_FFD3_MC.D1 ;
  wire \U1/U6/CurrState_Sreg0_FFD3_MC.D2 ;
  wire \U1/U6/CurrState_Sreg0_FFD4 ;
  wire \U1/U6/CurrState_Sreg0_FFD3_MC.D2_PT_0 ;
  wire \U1/U6/CurrState_Sreg0_FFD1 ;
  wire \U1/U6/CurrState_Sreg0_FFD3_MC.D2_PT_1 ;
  wire \U1/U6/CurrState_Sreg0_FFD3_MC.D2_PT_2 ;
  wire \U1/U6/CurrState_Sreg0_FFD3_MC.D2_PT_3 ;
  wire \U1/U6/CurrState_Sreg0_FFD1_MC.Q ;
  wire \U1/U6/CurrState_Sreg0_FFD1_MC.D ;
  wire \U1/U6/CurrState_Sreg0_FFD1_MC.D1 ;
  wire \U1/U6/CurrState_Sreg0_FFD1_MC.D2 ;
  wire \U1/U6/CurrState_Sreg0_FFD1_MC.D2_PT_0 ;
  wire \U1/U6/CurrState_Sreg0_FFD1_MC.D2_PT_1 ;
  wire \U1/U6/CurrState_Sreg0_FFD1_MC.D2_PT_2 ;
  wire \U1/U6/CurrState_Sreg0_FFD4_MC.Q ;
  wire \U1/U6/CurrState_Sreg0_FFD4_MC.D ;
  wire \U1/U6/CurrState_Sreg0_FFD4_MC.D1 ;
  wire \U1/U6/CurrState_Sreg0_FFD4_MC.D2 ;
  wire \U1/U6/CurrState_Sreg0_FFD2_MC.Q ;
  wire \U1/U6/CurrState_Sreg0_FFD2_MC.D ;
  wire \U1/U6/CurrState_Sreg0_FFD2_MC.D1 ;
  wire \U1/U6/CurrState_Sreg0_FFD2_MC.D2 ;
  wire \U1/U6/CurrState_Sreg0_FFD2_MC.D2_PT_0 ;
  wire \U1/U6/CurrState_Sreg0_FFD2_MC.D2_PT_1 ;
  wire \U1/U6/CurrState_Sreg0_FFD2_MC.D2_PT_2 ;
  wire \U1/U6/CurrState_Sreg0_FFD2_MC.D2_PT_3 ;
  wire \U1/U6/CurrState_Sreg0_FFD2_MC.D2_PT_4 ;
  wire \U1/U6/CurrState_Sreg0_FFD2_MC.D2_PT_5 ;
  wire \U1/U6/CurrState_Sreg0_FFD2_MC.D2_PT_6 ;
  wire \U1/U6/CurrState_Sreg0_FFD2_MC.D2_PT_7 ;
  wire \N_PZ_1154_MC.Q ;
  wire \N_PZ_1154_MC.D ;
  wire \N_PZ_1154_MC.D1 ;
  wire \N_PZ_1154_MC.D2 ;
  wire \N_PZ_1154_MC.D2_PT_0 ;
  wire \N_PZ_1154_MC.D2_PT_1 ;
  wire \N_PZ_1019_MC.Q ;
  wire \N_PZ_1019_MC.D ;
  wire \N_PZ_1019_MC.D1 ;
  wire \N_PZ_1019_MC.D2 ;
  wire NET2512;
  wire \U1/U4/LatchEdge1r ;
  wire \outDATA<7>\$WA3.UIM ;
  wire \N_PZ_1019_MC.D2_PT_0 ;
  wire \N_PZ_1019_MC.D2_PT_1 ;
  wire \NET2512_MC.Q ;
  wire \NET2512_MC.D ;
  wire NET2512_MC_tsimcreated_xor_;
  wire \NET2512_MC.REG_tsimcreated_inv_Mclk_II/FCLK ;
  wire \NET2512_MC.D1 ;
  wire \NET2512_MC.D2 ;
  wire \NET2512_MC.D2_PT_0 ;
  wire \NET2512_MC.D2_PT_1 ;
  wire \U1/U4/LatchEdge1r_MC.Q ;
  wire \U1/U4/LatchEdge1r_MC.D ;
  wire \U1/U4/LatchEdge1r_MC.REG_tsimcreated_inv_Mclk_II/FCLK ;
  wire \U1/U4/LatchEdge1r_MC.D1 ;
  wire \U1/U4/LatchEdge1r_MC.D2 ;
  wire \U1/U4/LatchEdge1r_MC.D2_PT_0 ;
  wire \U1/U4/LatchEdge1r_MC.D2_PT_1 ;
  wire \outDATA<7>\$WA3.UIM_MC.Q ;
  wire \outDATA<7>\$WA3.UIM_MC.D ;
  wire \outDATA<7>\$WA3.UIM_MC.D1 ;
  wire \outDATA<7>\$WA3.UIM_MC.D2 ;
  wire \DCOR1THRESLOWr_MC.Q ;
  wire \DCOR1THRESLOWr_MC.D ;
  wire \DCOR1THRESLOWr_MC.D1 ;
  wire \DCOR1THRESLOWr_MC.D2 ;
  wire \U1/U4/Latch1r<8>_MC.Q ;
  wire \U1/U4/Latch1r<8>_MC.D ;
  wire \U1/U4/Latch1r<8>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ;
  wire \U1/U4/Latch1r<8>_MC.D1 ;
  wire \U1/U4/Latch1r<8>_MC.D2 ;
  wire \U1/U4/Latch1r<8>_MC.D2_PT_0 ;
  wire \U1/U4/Latch1r<8>_MC.D2_PT_1 ;
  wire \U1/Channel1<8>_MC.Q ;
  wire \U1/Channel1<8>_MC.D ;
  wire \U1/Channel1<8>_MC_tsimcreated_xor_ ;
  wire \U1/Channel1<8>_MC.D1 ;
  wire \U1/Channel1<8>_MC.D2 ;
  wire \U1/Channel1<8>_MC.D2_PT_0 ;
  wire N_PZ_975;
  wire \U1/Channel1<8>_MC.D2_PT_1 ;
  wire \U1/Channel1<8>_MC.D2_PT_2 ;
  wire \U1/Channel1<8>_MC.D2_PT_3 ;
  wire \U1/Channel1<8>_MC.D2_PT_4 ;
  wire \U1/Channel1<8>_MC.D2_PT_5 ;
  wire \U1/Channel1<8>_MC.D2_PT_6 ;
  wire \U1/Channel1<8>_MC.D2_PT_7 ;
  wire \U1/Channel1<5>_MC.Q ;
  wire \U1/Channel1<5>_MC.D ;
  wire \U1/Channel1<5>_MC_tsimcreated_xor_ ;
  wire \U1/Channel1<5>_MC.D1 ;
  wire \U1/Channel1<5>_MC.D2 ;
  wire \U1/Channel1<5>_MC.D2_PT_0 ;
  wire \U1/Channel1<5>_MC.D2_PT_1 ;
  wire \U1/Channel1<5>_MC.D2_PT_2 ;
  wire \U1/U5/location_Maddsub__n0000__n0067<0>_MC.Q ;
  wire \U1/U5/location_Maddsub__n0000__n0067<0>_MC.D ;
  wire \U1/U5/location_Maddsub__n0000__n0067<0>_MC.D1 ;
  wire \U1/U5/location_Maddsub__n0000__n0067<0>_MC.D2 ;
  wire N_PZ_998;
  wire \U1/U5/location_Maddsub__n0000__n0067<0>_MC.D2_PT_0 ;
  wire \U1/U5/location_Maddsub__n0000__n0067<0>_MC.D2_PT_1 ;
  wire \N_PZ_998_MC.Q ;
  wire \N_PZ_998_MC.D ;
  wire \N_PZ_998_MC.D1 ;
  wire \N_PZ_998_MC.D2 ;
  wire \U1/NET3720 ;
  wire \N_PZ_998_MC.D2_PT_0 ;
  wire \N_PZ_998_MC.D2_PT_1 ;
  wire \U1/NET3720_MC.Q ;
  wire \U1/NET3720_MC.D ;
  wire \U1/NET3720_MC.REG_tsimcreated_inv_Mclk_II/FCLK ;
  wire \U1/NET3720_MC.D1 ;
  wire \U1/NET3720_MC.D2 ;
  wire \U1/NET3720_MC.D2_PT_0 ;
  wire \U1/NET3720_MC.D2_PT_1 ;
  wire \U1/Channel1<1>_MC.Q ;
  wire \U1/Channel1<1>_MC.D ;
  wire \U1/Channel1<1>_MC_tsimcreated_xor_ ;
  wire \U1/Channel1<1>_MC.D1 ;
  wire \U1/Channel1<1>_MC.D2 ;
  wire \U1/Channel1<1>_MC.D2_PT_0 ;
  wire \U1/Channel1<1>_MC.D2_PT_1 ;
  wire \U1/Channel1<1>_MC.D2_PT_2 ;
  wire \N_PZ_975_MC.Q ;
  wire \N_PZ_975_MC.D ;
  wire \N_PZ_975_MC.D1 ;
  wire \N_PZ_975_MC.D2 ;
  wire \N_PZ_975_MC.D2_PT_0 ;
  wire \N_PZ_975_MC.D2_PT_1 ;
  wire \U1/Channel1<2>_MC.Q ;
  wire \U1/Channel1<2>_MC.D ;
  wire \U1/Channel1<2>_MC_tsimcreated_xor_ ;
  wire \U1/Channel1<2>_MC.D1 ;
  wire \U1/Channel1<2>_MC.D2 ;
  wire \U1/Channel1<2>_MC.D2_PT_0 ;
  wire \U1/Channel1<2>_MC.D2_PT_1 ;
  wire \U1/Channel1<2>_MC.D2_PT_2 ;
  wire \U1/Channel1<3>_MC.Q ;
  wire \U1/Channel1<3>_MC.D ;
  wire \U1/Channel1<3>_MC_tsimcreated_xor_ ;
  wire \U1/Channel1<3>_MC.D1 ;
  wire \U1/Channel1<3>_MC.D2 ;
  wire \U1/Channel1<3>_MC.D2_PT_0 ;
  wire \U1/Channel1<3>_MC.D2_PT_1 ;
  wire \U1/Channel1<3>_MC.D2_PT_2 ;
  wire \U1/Channel1<4>_MC.Q ;
  wire \U1/Channel1<4>_MC.D ;
  wire \U1/Channel1<4>_MC_tsimcreated_xor_ ;
  wire \U1/Channel1<4>_MC.D1 ;
  wire \U1/Channel1<4>_MC.D2 ;
  wire \U1/Channel1<4>_MC.D2_PT_0 ;
  wire \U1/Channel1<4>_MC.D2_PT_1 ;
  wire \U1/Channel1<4>_MC.D2_PT_2 ;
  wire \U1/Channel1<4>_MC.D2_PT_3 ;
  wire \U1/Channel1<4>_MC.D2_PT_4 ;
  wire \U1/Channel1<4>_MC.D2_PT_5 ;
  wire \U1/Channel1<4>_MC.D2_PT_6 ;
  wire \U1/Channel1<4>_MC.D2_PT_7 ;
  wire \U1/Channel1<6>_MC.Q ;
  wire \U1/Channel1<6>_MC.D ;
  wire \U1/Channel1<6>_MC_tsimcreated_xor_ ;
  wire \U1/Channel1<6>_MC.D1 ;
  wire \U1/Channel1<6>_MC.D2 ;
  wire \U1/Channel1<6>_MC.D2_PT_0 ;
  wire \U1/Channel1<6>_MC.D2_PT_1 ;
  wire \U1/Channel1<6>_MC.D2_PT_2 ;
  wire \U1/Channel1<7>_MC.Q ;
  wire \U1/Channel1<7>_MC.D ;
  wire \U1/Channel1<7>_MC_tsimcreated_xor_ ;
  wire \U1/Channel1<7>_MC.D1 ;
  wire \U1/Channel1<7>_MC.D2 ;
  wire \U1/Channel1<7>_MC.D2_PT_0 ;
  wire \U1/Channel1<7>_MC.D2_PT_1 ;
  wire \U1/Channel1<7>_MC.D2_PT_2 ;
  wire \U1/U5/location_Maddsub__n0000__n0075<0>_MC.Q ;
  wire \U1/U5/location_Maddsub__n0000__n0075<0>_MC.D ;
  wire \U1/U5/location_Maddsub__n0000__n0075<0>_MC.D1 ;
  wire \U1/U5/location_Maddsub__n0000__n0075<0>_MC.D2 ;
  wire \U1/U5/location_Maddsub__n0000__n0075<0>_MC.D2_PT_0 ;
  wire \U1/U5/location_Maddsub__n0000__n0075<0>_MC.D2_PT_1 ;
  wire \DCORCONFIGr_MC.Q ;
  wire \DCORCONFIGr_MC.D ;
  wire \DCORCONFIGr_MC.D1 ;
  wire \DCORCONFIGr_MC.D2 ;
  wire \outDATA<0>\$WA3.UIM_MC.Q ;
  wire \outDATA<0>\$WA3.UIM_MC.D ;
  wire \outDATA<0>\$WA3.UIM_MC.D1 ;
  wire \outDATA<0>\$WA3.UIM_MC.D2 ;
  wire \DCORENCPWRr_MC.Q ;
  wire \DCORENCPWRr_MC.D ;
  wire \DCORENCPWRr_MC.D1 ;
  wire \DCORENCPWRr_MC.D2 ;
  wire \outDATA<0>\$WA5.UIM_MC.Q ;
  wire \outDATA<0>\$WA5.UIM_MC.D ;
  wire \outDATA<0>\$WA5.UIM_MC.D1 ;
  wire \outDATA<0>\$WA5.UIM_MC.D2 ;
  wire NET2528;
  wire \outDATA<0>\$WA5.UIM_MC.D2_PT_0 ;
  wire \outDATA<0>\$WA5.UIM_MC.D2_PT_1 ;
  wire \NET2528_MC.Q ;
  wire \NET2528_MC.D ;
  wire \NET2528_MC.REG_tsimcreated_inv_Mclk_II/FCLK ;
  wire \NET2528_MC.D1 ;
  wire \NET2528_MC.D2 ;
  wire \NET2528_MC.D2_PT_0 ;
  wire \NET2528_MC.D2_PT_1 ;
  wire \U4/orFLGs_MC.Q ;
  wire \U4/orFLGs ;
  wire \U4/orFLGs_MC.D ;
  wire \U4/orFLGs_MC.D1 ;
  wire \U4/orFLGs_MC.D2 ;
  wire \DCORIFGr_MC.Q ;
  wire \DCORIFGr_MC.D ;
  wire \DCORIFGr_MC.D1 ;
  wire \DCORIFGr_MC.D2 ;
  wire \outDATA<0>\$WA6.UIM_MC.Q ;
  wire \outDATA<0>\$WA6.UIM_MC.D ;
  wire \outDATA<0>\$WA6.UIM_MC.D1 ;
  wire \outDATA<0>\$WA6.UIM_MC.D2 ;
  wire \outDATA<0>\$WA4.UIM_MC.Q ;
  wire \outDATA<0>\$WA4.UIM_MC.D ;
  wire \outDATA<0>\$WA4.UIM_MC.D1 ;
  wire \outDATA<0>\$WA4.UIM_MC.D2 ;
  wire DCORLIMITSr;
  wire \outDATA<0>\$WA4.UIM_MC.D2_PT_0 ;
  wire \U5/RLS0fr ;
  wire \outDATA<0>\$WA4.UIM_MC.D2_PT_1 ;
  wire \DCORLIMITSr_MC.Q ;
  wire \DCORLIMITSr_MC.D ;
  wire \DCORLIMITSr_MC.D1 ;
  wire \DCORLIMITSr_MC.D2 ;
  wire \U5/RLS0fr_MC.Q ;
  wire \U5/RLS0fr_MC.D ;
  wire \U5/RLS0fr_MC.REG_tsimcreated_inv_Mclk_II/FCLK ;
  wire \U5/RLS0fr_MC.D1 ;
  wire \U5/RLS0fr_MC.D2 ;
  wire DCORLINTr;
  wire \U5/RLS0fr_MC.D2_PT_0 ;
  wire \U5/RLS0r ;
  wire \U5/RLS0fr_MC.D2_PT_1 ;
  wire \DCORLINTr_MC.Q ;
  wire \DCORLINTr_MC.D ;
  wire \DCORLINTr_MC.D1 ;
  wire \DCORLINTr_MC.D2 ;
  wire \U5/RLS0r_MC.Q ;
  wire \U5/RLS0r_MC.D ;
  wire \U5/RLS0r_MC.REG_tsimcreated_inv_Mclk_II/FCLK ;
  wire \U5/RLS0r_MC.D1 ;
  wire \U5/RLS0r_MC.D2 ;
  wire \N_PZ_1016_MC.Q ;
  wire \N_PZ_1016_MC.D ;
  wire \N_PZ_1016_MC.D1 ;
  wire \N_PZ_1016_MC.D2 ;
  wire \outDATA<0>\$WA1.UIM_MC.Q ;
  wire \outDATA<0>\$WA1.UIM_MC.D ;
  wire \outDATA<0>\$WA1.UIM_MC.D1 ;
  wire \outDATA<0>\$WA1.UIM_MC.D2 ;
  wire DCOR0CNTLOWr;
  wire \outDATA<0>\$WA1.UIM_MC.D2_PT_0 ;
  wire DCOR1CNTLOWr;
  wire \outDATA<0>\$WA1.UIM_MC.D2_PT_1 ;
  wire DCOR0CNTHIGHr;
  wire \outDATA<0>\$WA1.UIM_MC.D2_PT_2 ;
  wire \outDATA<0>\$WA1.UIM_MC.D2_PT_3 ;
  wire \U1/U3/holdingreg0<0>_MC.Q ;
  wire \U1/U3/holdingreg0<0>_MC.D ;
  wire \U1/U3/holdingreg0<0>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ;
  wire \U1/U3/holdingreg0<0>_MC.D1 ;
  wire \U1/U3/holdingreg0<0>_MC.D2 ;
  wire \U1/U3/holdingreg0<0>_MC.D2_PT_0 ;
  wire \U1/U3/holdingreg0<0>_MC.D2_PT_1 ;
  wire \DCOR0CNTLOWr_MC.Q ;
  wire \DCOR0CNTLOWr_MC.D ;
  wire \DCOR0CNTLOWr_MC.D1 ;
  wire \DCOR0CNTLOWr_MC.D2 ;
  wire \U1/U3/holdingreg1<0>_MC.Q ;
  wire \U1/U3/holdingreg1<0>_MC.D ;
  wire \U1/U3/holdingreg1<0>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ;
  wire \U1/U3/holdingreg1<0>_MC.D1 ;
  wire \U1/U3/holdingreg1<0>_MC.D2 ;
  wire \U1/U3/holdingreg1<0>_MC.D2_PT_0 ;
  wire \U1/U3/holdingreg1<0>_MC.D2_PT_1 ;
  wire \DCOR1CNTLOWr_MC.Q ;
  wire \DCOR1CNTLOWr_MC.D ;
  wire \DCOR1CNTLOWr_MC.D1 ;
  wire \DCOR1CNTLOWr_MC.D2 ;
  wire \U1/U3/holdingreg0<8>_MC.Q ;
  wire \U1/U3/holdingreg0<8>_MC.D ;
  wire \U1/U3/holdingreg0<8>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ;
  wire \U1/U3/holdingreg0<8>_MC.D1 ;
  wire \U1/U3/holdingreg0<8>_MC.D2 ;
  wire \U1/U3/holdingreg0<8>_MC.D2_PT_0 ;
  wire \U1/U3/holdingreg0<8>_MC.D2_PT_1 ;
  wire \DCOR0CNTHIGHr_MC.Q ;
  wire \DCOR0CNTHIGHr_MC.D ;
  wire \DCOR0CNTHIGHr_MC.D1 ;
  wire \DCOR0CNTHIGHr_MC.D2 ;
  wire \U1/U3/holdingreg1<8>_MC.Q ;
  wire \U1/U3/holdingreg1<8>_MC.D ;
  wire \U1/U3/holdingreg1<8>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ;
  wire \U1/U3/holdingreg1<8>_MC.D1 ;
  wire \U1/U3/holdingreg1<8>_MC.D2 ;
  wire \U1/U3/holdingreg1<8>_MC.D2_PT_0 ;
  wire \U1/U3/holdingreg1<8>_MC.D2_PT_1 ;
  wire \N_PZ_1017_MC.Q ;
  wire \N_PZ_1017_MC.D ;
  wire \N_PZ_1017_MC.D1 ;
  wire \N_PZ_1017_MC.D2 ;
  wire DCOR1CNTHIGHr;
  wire \DCOR1CNTHIGHr_MC.Q ;
  wire \DCOR1CNTHIGHr_MC.D ;
  wire \DCOR1CNTHIGHr_MC.D1 ;
  wire \DCOR1CNTHIGHr_MC.D2 ;
  wire \N_PZ_1053_MC.Q ;
  wire \N_PZ_1053_MC.D ;
  wire \N_PZ_1053_MC.D1 ;
  wire \N_PZ_1053_MC.D2 ;
  wire DCOR1THRESHIGHr;
  wire \DCOR1THRESHIGHr_MC.Q ;
  wire \DCOR1THRESHIGHr_MC.D ;
  wire \DCOR1THRESHIGHr_MC.D1 ;
  wire \DCOR1THRESHIGHr_MC.D2 ;
  wire \U2_Enable_AD_MC.Q ;
  wire U2_Enable_AD;
  wire \U2_Enable_AD_MC.D ;
  wire \U2_Enable_AD_MC.D1 ;
  wire \U2_Enable_AD_MC.D2 ;
  wire \AD<1>_MC.Q_tsimrenamed_net_ ;
  wire \AD<1>_MC.BUFOE.OUT ;
  wire \AD<1>_MC.D ;
  wire \AD<1>_MC.D1 ;
  wire \AD<1>_MC.D2 ;
  wire \outDATA<1>\$WA0.UIM ;
  wire \AD<1>_MC.D2_PT_0 ;
  wire \outDATA<1>\$WA2.UIM ;
  wire \AD<1>_MC.D2_PT_1 ;
  wire \outDATA<1>\$WA3.UIM ;
  wire \AD<1>_MC.D2_PT_2 ;
  wire \outDATA<1>\$WA5.UIM ;
  wire \AD<1>_MC.D2_PT_3 ;
  wire \AD<1>_MC.D2_PT_4 ;
  wire \outDATA<1>\$WA4.UIM ;
  wire \AD<1>_MC.D2_PT_5 ;
  wire \outDATA<1>\$WA1.UIM ;
  wire \AD<1>_MC.D2_PT_6 ;
  wire \AD<1>_MC.D2_PT_7 ;
  wire \outDATA<1>\$WA0.UIM_MC.Q ;
  wire \outDATA<1>\$WA0.UIM_MC.D ;
  wire \outDATA<1>\$WA0.UIM_MC.D1 ;
  wire \outDATA<1>\$WA0.UIM_MC.D2 ;
  wire \outDATA<1>\$WA2.UIM_MC.Q ;
  wire \outDATA<1>\$WA2.UIM_MC.D ;
  wire \outDATA<1>\$WA2.UIM_MC.D1 ;
  wire \outDATA<1>\$WA2.UIM_MC.D2 ;
  wire \outDATA<1>\$WA2.UIM_MC.D2_PT_0 ;
  wire \outDATA<1>\$WA2.UIM_MC.D2_PT_1 ;
  wire \outDATA<1>\$WA2.UIM_MC.D2_PT_2 ;
  wire \outDATA<1>\$WA2.UIM_MC.D2_PT_3 ;
  wire \U1/U4/Latch0r<1>_MC.Q ;
  wire \U1/U4/Latch0r<1>_MC.D ;
  wire \U1/U4/Latch0r<1>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ;
  wire \U1/U4/Latch0r<1>_MC.D1 ;
  wire \U1/U4/Latch0r<1>_MC.D2 ;
  wire \U1/U4/Latch0r<1>_MC.D2_PT_0 ;
  wire \U1/U4/Latch0r<1>_MC.D2_PT_1 ;
  wire \U1/U4/Latch0r<9>_MC.Q ;
  wire \U1/U4/Latch0r<9>_MC.D ;
  wire \U1/U4/Latch0r<9>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ;
  wire \U1/U4/Latch0r<9>_MC.D1 ;
  wire \U1/U4/Latch0r<9>_MC.D2 ;
  wire \U1/U4/Latch0r<9>_MC.D2_PT_0 ;
  wire \U1/U4/Latch0r<9>_MC.D2_PT_1 ;
  wire \U1/Channel0<9>_MC.Q ;
  wire \U1/Channel0<9>_MC.D ;
  wire \U1/Channel0<9>_MC_tsimcreated_xor_ ;
  wire \U1/Channel0<9>_MC.D1 ;
  wire \U1/Channel0<9>_MC.D2 ;
  wire \U1/Channel0<9>_MC.D2_PT_0 ;
  wire \U1/Channel0<9>_MC.D2_PT_1 ;
  wire \U1/Channel0<9>_MC.D2_PT_2 ;
  wire \U1/U4/Latch1r<1>_MC.Q ;
  wire \U1/U4/Latch1r<1>_MC.D ;
  wire \U1/U4/Latch1r<1>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ;
  wire \U1/U4/Latch1r<1>_MC.D1 ;
  wire \U1/U4/Latch1r<1>_MC.D2 ;
  wire \U1/U4/Latch1r<1>_MC.D2_PT_0 ;
  wire \U1/U4/Latch1r<1>_MC.D2_PT_1 ;
  wire \U1/U4/Latch1r<9>_MC.Q ;
  wire \U1/U4/Latch1r<9>_MC.D ;
  wire \U1/U4/Latch1r<9>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ;
  wire \U1/U4/Latch1r<9>_MC.D1 ;
  wire \U1/U4/Latch1r<9>_MC.D2 ;
  wire \U1/U4/Latch1r<9>_MC.D2_PT_0 ;
  wire \U1/U4/Latch1r<9>_MC.D2_PT_1 ;
  wire \U1/Channel1<9>_MC.Q ;
  wire \U1/Channel1<9>_MC.D ;
  wire \U1/Channel1<9>_MC_tsimcreated_xor_ ;
  wire \U1/Channel1<9>_MC.D1 ;
  wire \U1/Channel1<9>_MC.D2 ;
  wire \U1/Channel1<9>_MC.D2_PT_0 ;
  wire \U1/Channel1<9>_MC.D2_PT_1 ;
  wire \U1/Channel1<9>_MC.D2_PT_2 ;
  wire \outDATA<1>\$WA3.UIM_MC.Q ;
  wire \outDATA<1>\$WA3.UIM_MC.D ;
  wire \outDATA<1>\$WA3.UIM_MC.D1 ;
  wire \outDATA<1>\$WA3.UIM_MC.D2 ;
  wire \outDATA<1>\$WA5.UIM_MC.Q ;
  wire \outDATA<1>\$WA5.UIM_MC.D ;
  wire \outDATA<1>\$WA5.UIM_MC.D1 ;
  wire \outDATA<1>\$WA5.UIM_MC.D2 ;
  wire \outDATA<1>\$WA5.UIM_MC.D2_PT_0 ;
  wire \outDATA<1>\$WA5.UIM_MC.D2_PT_1 ;
  wire \outDATA<1>\$WA5.UIM_MC.D2_PT_2 ;
  wire \outDATA<1>\$WA4.UIM_MC.Q ;
  wire \outDATA<1>\$WA4.UIM_MC.D ;
  wire \outDATA<1>\$WA4.UIM_MC.D1 ;
  wire \outDATA<1>\$WA4.UIM_MC.D2 ;
  wire \outDATA<1>\$WA4.UIM_MC.D2_PT_0 ;
  wire \U5/FLS0fr ;
  wire \outDATA<1>\$WA4.UIM_MC.D2_PT_1 ;
  wire \U5/FLS0fr_MC.Q ;
  wire \U5/FLS0fr_MC.D ;
  wire \U5/FLS0fr_MC.REG_tsimcreated_inv_Mclk_II/FCLK ;
  wire \U5/FLS0fr_MC.D1 ;
  wire \U5/FLS0fr_MC.D2 ;
  wire \U5/FLS0fr_MC.D2_PT_0 ;
  wire \U5/FLS0r ;
  wire \U5/FLS0fr_MC.D2_PT_1 ;
  wire \U5/FLS0r_MC.Q ;
  wire \U5/FLS0r_MC.D ;
  wire \U5/FLS0r_MC.REG_tsimcreated_inv_Mclk_II/FCLK ;
  wire \U5/FLS0r_MC.D1 ;
  wire \U5/FLS0r_MC.D2 ;
  wire \outDATA<1>\$WA1.UIM_MC.Q ;
  wire \outDATA<1>\$WA1.UIM_MC.D ;
  wire \outDATA<1>\$WA1.UIM_MC.D1 ;
  wire \outDATA<1>\$WA1.UIM_MC.D2 ;
  wire \outDATA<1>\$WA1.UIM_MC.D2_PT_0 ;
  wire \outDATA<1>\$WA1.UIM_MC.D2_PT_1 ;
  wire \outDATA<1>\$WA1.UIM_MC.D2_PT_2 ;
  wire \outDATA<1>\$WA1.UIM_MC.D2_PT_3 ;
  wire \U1/U3/holdingreg0<1>_MC.Q ;
  wire \U1/U3/holdingreg0<1>_MC.D ;
  wire \U1/U3/holdingreg0<1>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ;
  wire \U1/U3/holdingreg0<1>_MC.D1 ;
  wire \U1/U3/holdingreg0<1>_MC.D2 ;
  wire \U1/U3/holdingreg0<1>_MC.D2_PT_0 ;
  wire \U1/U3/holdingreg0<1>_MC.D2_PT_1 ;
  wire \U1/U3/holdingreg1<1>_MC.Q ;
  wire \U1/U3/holdingreg1<1>_MC.D ;
  wire \U1/U3/holdingreg1<1>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ;
  wire \U1/U3/holdingreg1<1>_MC.D1 ;
  wire \U1/U3/holdingreg1<1>_MC.D2 ;
  wire \U1/U3/holdingreg1<1>_MC.D2_PT_0 ;
  wire \U1/U3/holdingreg1<1>_MC.D2_PT_1 ;
  wire \U1/U3/holdingreg0<9>_MC.Q ;
  wire \U1/U3/holdingreg0<9>_MC.D ;
  wire \U1/U3/holdingreg0<9>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ;
  wire \U1/U3/holdingreg0<9>_MC.D1 ;
  wire \U1/U3/holdingreg0<9>_MC.D2 ;
  wire \U1/U3/holdingreg0<9>_MC.D2_PT_0 ;
  wire \U1/U3/holdingreg0<9>_MC.D2_PT_1 ;
  wire \U1/U3/holdingreg1<9>_MC.Q ;
  wire \U1/U3/holdingreg1<9>_MC.D ;
  wire \U1/U3/holdingreg1<9>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ;
  wire \U1/U3/holdingreg1<9>_MC.D1 ;
  wire \U1/U3/holdingreg1<9>_MC.D2 ;
  wire \U1/U3/holdingreg1<9>_MC.D2_PT_0 ;
  wire \U1/U3/holdingreg1<9>_MC.D2_PT_1 ;
  wire \AD<4>_MC.Q_tsimrenamed_net_ ;
  wire \AD<4>_MC.BUFOE.OUT ;
  wire \AD<4>_MC.D ;
  wire \AD<4>_MC.D1 ;
  wire \AD<4>_MC.D2 ;
  wire \outDATA<4>\$WA0.UIM ;
  wire \AD<4>_MC.D2_PT_0 ;
  wire \outDATA<4>\$WA2.UIM ;
  wire \AD<4>_MC.D2_PT_1 ;
  wire \outDATA<4>\$WA3.UIM ;
  wire \AD<4>_MC.D2_PT_2 ;
  wire \outDATA<4>\$WA5.UIM ;
  wire \AD<4>_MC.D2_PT_3 ;
  wire \outDATA<4>\$WA6.UIM ;
  wire \AD<4>_MC.D2_PT_4 ;
  wire \outDATA<4>\$WA4.UIM ;
  wire \AD<4>_MC.D2_PT_5 ;
  wire \outDATA<4>\$WA1.UIM ;
  wire \AD<4>_MC.D2_PT_6 ;
  wire \AD<4>_MC.D2_PT_7 ;
  wire \outDATA<4>\$WA0.UIM_MC.Q ;
  wire \outDATA<4>\$WA0.UIM_MC.D ;
  wire \outDATA<4>\$WA0.UIM_MC.D1 ;
  wire \outDATA<4>\$WA0.UIM_MC.D2 ;
  wire \outDATA<4>\$WA2.UIM_MC.Q ;
  wire \outDATA<4>\$WA2.UIM_MC.D ;
  wire \outDATA<4>\$WA2.UIM_MC.D1 ;
  wire \outDATA<4>\$WA2.UIM_MC.D2 ;
  wire \outDATA<4>\$WA2.UIM_MC.D2_PT_0 ;
  wire \outDATA<4>\$WA2.UIM_MC.D2_PT_1 ;
  wire \outDATA<4>\$WA2.UIM_MC.D2_PT_2 ;
  wire \outDATA<4>\$WA2.UIM_MC.D2_PT_3 ;
  wire \U1/U4/Latch0r<4>_MC.Q ;
  wire \U1/U4/Latch0r<4>_MC.D ;
  wire \U1/U4/Latch0r<4>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ;
  wire \U1/U4/Latch0r<4>_MC.D1 ;
  wire \U1/U4/Latch0r<4>_MC.D2 ;
  wire \U1/U4/Latch0r<4>_MC.D2_PT_0 ;
  wire \U1/U4/Latch0r<4>_MC.D2_PT_1 ;
  wire \U1/U4/Latch0r<12>_MC.Q ;
  wire \U1/U4/Latch0r<12>_MC.D ;
  wire \U1/U4/Latch0r<12>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ;
  wire \U1/U4/Latch0r<12>_MC.D1 ;
  wire \U1/U4/Latch0r<12>_MC.D2 ;
  wire \U1/U4/Latch0r<12>_MC.D2_PT_0 ;
  wire \U1/U4/Latch0r<12>_MC.D2_PT_1 ;
  wire \U1/Channel0<12>_MC.Q ;
  wire \U1/Channel0<12>_MC.D ;
  wire \U1/Channel0<12>_MC_tsimcreated_xor_ ;
  wire \U1/Channel0<12>_MC.D1 ;
  wire \U1/Channel0<12>_MC.D2 ;
  wire \U1/Channel0<12>_MC.D2_PT_0 ;
  wire \U1/Channel0<12>_MC.D2_PT_1 ;
  wire \U1/Channel0<12>_MC.D2_PT_2 ;
  wire \U1/Channel0<10>_MC.Q ;
  wire \U1/Channel0<10>_MC.D ;
  wire \U1/Channel0<10>_MC_tsimcreated_xor_ ;
  wire \U1/Channel0<10>_MC.D1 ;
  wire \U1/Channel0<10>_MC.D2 ;
  wire \U1/Channel0<10>_MC.D2_PT_0 ;
  wire \U1/Channel0<10>_MC.D2_PT_1 ;
  wire \U1/Channel0<10>_MC.D2_PT_2 ;
  wire \U1/Channel0<11>_MC.Q ;
  wire \U1/Channel0<11>_MC.D ;
  wire \U1/Channel0<11>_MC_tsimcreated_xor_ ;
  wire \U1/Channel0<11>_MC.D1 ;
  wire \U1/Channel0<11>_MC.D2 ;
  wire \U1/Channel0<11>_MC.D2_PT_0 ;
  wire \U1/Channel0<11>_MC.D2_PT_1 ;
  wire \U1/Channel0<11>_MC.D2_PT_2 ;
  wire \U1/U4/Latch1r<4>_MC.Q ;
  wire \U1/U4/Latch1r<4>_MC.D ;
  wire \U1/U4/Latch1r<4>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ;
  wire \U1/U4/Latch1r<4>_MC.D1 ;
  wire \U1/U4/Latch1r<4>_MC.D2 ;
  wire \U1/U4/Latch1r<4>_MC.D2_PT_0 ;
  wire \U1/U4/Latch1r<4>_MC.D2_PT_1 ;
  wire \U1/U4/Latch1r<12>_MC.Q ;
  wire \U1/U4/Latch1r<12>_MC.D ;
  wire \U1/U4/Latch1r<12>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ;
  wire \U1/U4/Latch1r<12>_MC.D1 ;
  wire \U1/U4/Latch1r<12>_MC.D2 ;
  wire \U1/U4/Latch1r<12>_MC.D2_PT_0 ;
  wire \U1/U4/Latch1r<12>_MC.D2_PT_1 ;
  wire \U1/Channel1<12>_MC.Q ;
  wire \U1/Channel1<12>_MC.D ;
  wire \U1/Channel1<12>_MC_tsimcreated_xor_ ;
  wire \U1/Channel1<12>_MC.D1 ;
  wire \U1/Channel1<12>_MC.D2 ;
  wire \U1/Channel1<12>_MC.D2_PT_0 ;
  wire \U1/Channel1<12>_MC.D2_PT_1 ;
  wire \U1/Channel1<12>_MC.D2_PT_2 ;
  wire \U1/Channel1<10>_MC.Q ;
  wire \U1/Channel1<10>_MC.D ;
  wire \U1/Channel1<10>_MC_tsimcreated_xor_ ;
  wire \U1/Channel1<10>_MC.D1 ;
  wire \U1/Channel1<10>_MC.D2 ;
  wire \U1/Channel1<10>_MC.D2_PT_0 ;
  wire \U1/Channel1<10>_MC.D2_PT_1 ;
  wire \U1/Channel1<10>_MC.D2_PT_2 ;
  wire \U1/Channel1<11>_MC.Q ;
  wire \U1/Channel1<11>_MC.D ;
  wire \U1/Channel1<11>_MC_tsimcreated_xor_ ;
  wire \U1/Channel1<11>_MC.D1 ;
  wire \U1/Channel1<11>_MC.D2 ;
  wire \U1/Channel1<11>_MC.D2_PT_0 ;
  wire \U1/Channel1<11>_MC.D2_PT_1 ;
  wire \U1/Channel1<11>_MC.D2_PT_2 ;
  wire \outDATA<4>\$WA3.UIM_MC.Q ;
  wire \outDATA<4>\$WA3.UIM_MC.D ;
  wire \outDATA<4>\$WA3.UIM_MC.D1 ;
  wire \outDATA<4>\$WA3.UIM_MC.D2 ;
  wire \outDATA<4>\$WA5.UIM_MC.Q ;
  wire \outDATA<4>\$WA5.UIM_MC.D ;
  wire \outDATA<4>\$WA5.UIM_MC.D1 ;
  wire \outDATA<4>\$WA5.UIM_MC.D2 ;
  wire \outDATA<4>\$WA5.UIM_MC.D2_PT_0 ;
  wire \outDATA<4>\$WA5.UIM_MC.D2_PT_1 ;
  wire \outDATA<4>\$WA6.UIM_MC.Q ;
  wire \outDATA<4>\$WA6.UIM_MC.D ;
  wire \outDATA<4>\$WA6.UIM_MC.D1 ;
  wire \outDATA<4>\$WA6.UIM_MC.D2 ;
  wire NET2575;
  wire \NET2575_MC.Q ;
  wire \NET2575_MC.D ;
  wire \NET2575_MC.REG_tsimcreated_inv_Mclk_II/FCLK ;
  wire \NET2575_MC.D1 ;
  wire \NET2575_MC.D2 ;
  wire \NET2575_MC.D2_PT_0 ;
  wire \NET2575_MC.D2_PT_1 ;
  wire \NET2575_MC.D2_PT_2 ;
  wire \U5/FLS1fr ;
  wire \U5/RLS1fr ;
  wire \NET2575_MC.D2_PT_3 ;
  wire \U5/FLS1fr_MC.Q ;
  wire \U5/FLS1fr_MC.D ;
  wire \U5/FLS1fr_MC.REG_tsimcreated_inv_Mclk_II/FCLK ;
  wire \U5/FLS1fr_MC.D1 ;
  wire \U5/FLS1fr_MC.D2 ;
  wire \U5/FLS1fr_MC.D2_PT_0 ;
  wire \U5/FLS1r ;
  wire \U5/FLS1fr_MC.D2_PT_1 ;
  wire \U5/FLS1r_MC.Q ;
  wire \U5/FLS1r_MC.D ;
  wire \U5/FLS1r_MC.REG_tsimcreated_inv_Mclk_II/FCLK ;
  wire \U5/FLS1r_MC.D1 ;
  wire \U5/FLS1r_MC.D2 ;
  wire \U5/RLS1fr_MC.Q ;
  wire \U5/RLS1fr_MC.D ;
  wire \U5/RLS1fr_MC.REG_tsimcreated_inv_Mclk_II/FCLK ;
  wire \U5/RLS1fr_MC.D1 ;
  wire \U5/RLS1fr_MC.D2 ;
  wire \U5/RLS1fr_MC.D2_PT_0 ;
  wire \U5/RLS1r ;
  wire \U5/RLS1fr_MC.D2_PT_1 ;
  wire \U5/RLS1r_MC.Q ;
  wire \U5/RLS1r_MC.D ;
  wire \U5/RLS1r_MC.REG_tsimcreated_inv_Mclk_II/FCLK ;
  wire \U5/RLS1r_MC.D1 ;
  wire \U5/RLS1r_MC.D2 ;
  wire \outDATA<4>\$WA4.UIM_MC.Q ;
  wire \outDATA<4>\$WA4.UIM_MC.D ;
  wire \outDATA<4>\$WA4.UIM_MC.D1 ;
  wire \outDATA<4>\$WA4.UIM_MC.D2 ;
  wire \outDATA<4>\$WA4.UIM_MC.D2_PT_0 ;
  wire \outDATA<4>\$WA4.UIM_MC.D2_PT_1 ;
  wire \outDATA<4>\$WA1.UIM_MC.Q ;
  wire \outDATA<4>\$WA1.UIM_MC.D ;
  wire \outDATA<4>\$WA1.UIM_MC.D1 ;
  wire \outDATA<4>\$WA1.UIM_MC.D2 ;
  wire \outDATA<4>\$WA1.UIM_MC.D2_PT_0 ;
  wire \outDATA<4>\$WA1.UIM_MC.D2_PT_1 ;
  wire \outDATA<4>\$WA1.UIM_MC.D2_PT_2 ;
  wire \outDATA<4>\$WA1.UIM_MC.D2_PT_3 ;
  wire \U1/U3/holdingreg0<4>_MC.Q ;
  wire \U1/U3/holdingreg0<4>_MC.D ;
  wire \U1/U3/holdingreg0<4>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ;
  wire \U1/U3/holdingreg0<4>_MC.D1 ;
  wire \U1/U3/holdingreg0<4>_MC.D2 ;
  wire \U1/U3/holdingreg0<4>_MC.D2_PT_0 ;
  wire \U1/U3/holdingreg0<4>_MC.D2_PT_1 ;
  wire \U1/U3/holdingreg1<4>_MC.Q ;
  wire \U1/U3/holdingreg1<4>_MC.D ;
  wire \U1/U3/holdingreg1<4>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ;
  wire \U1/U3/holdingreg1<4>_MC.D1 ;
  wire \U1/U3/holdingreg1<4>_MC.D2 ;
  wire \U1/U3/holdingreg1<4>_MC.D2_PT_0 ;
  wire \U1/U3/holdingreg1<4>_MC.D2_PT_1 ;
  wire \U1/U3/holdingreg0<12>_MC.Q ;
  wire \U1/U3/holdingreg0<12>_MC.D ;
  wire \U1/U3/holdingreg0<12>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ;
  wire \U1/U3/holdingreg0<12>_MC.D1 ;
  wire \U1/U3/holdingreg0<12>_MC.D2 ;
  wire \U1/U3/holdingreg0<12>_MC.D2_PT_0 ;
  wire \U1/U3/holdingreg0<12>_MC.D2_PT_1 ;
  wire \U1/U3/holdingreg1<12>_MC.Q ;
  wire \U1/U3/holdingreg1<12>_MC.D ;
  wire \U1/U3/holdingreg1<12>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ;
  wire \U1/U3/holdingreg1<12>_MC.D1 ;
  wire \U1/U3/holdingreg1<12>_MC.D2 ;
  wire \U1/U3/holdingreg1<12>_MC.D2_PT_0 ;
  wire \U1/U3/holdingreg1<12>_MC.D2_PT_1 ;
  wire \AD<5>_MC.Q_tsimrenamed_net_ ;
  wire \AD<5>_MC.BUFOE.OUT ;
  wire \AD<5>_MC.D ;
  wire \AD<5>_MC.D1 ;
  wire \AD<5>_MC.D2 ;
  wire \outDATA<5>\$WA0.UIM ;
  wire \AD<5>_MC.D2_PT_0 ;
  wire \outDATA<5>\$WA3.UIM ;
  wire \AD<5>_MC.D2_PT_1 ;
  wire \outDATA<5>\$WA5.UIM ;
  wire \AD<5>_MC.D2_PT_2 ;
  wire \outDATA<5>\$WA4.UIM ;
  wire \AD<5>_MC.D2_PT_3 ;
  wire \outDATA<5>\$WA1.UIM ;
  wire \AD<5>_MC.D2_PT_4 ;
  wire \outDATA<5>\$WA2.UIM ;
  wire \AD<5>_MC.D2_PT_5 ;
  wire \outDATA<5>\$WA0.UIM_MC.Q ;
  wire \outDATA<5>\$WA0.UIM_MC.D ;
  wire \outDATA<5>\$WA0.UIM_MC.D1 ;
  wire \outDATA<5>\$WA0.UIM_MC.D2 ;
  wire \outDATA<5>\$WA3.UIM_MC.Q ;
  wire \outDATA<5>\$WA3.UIM_MC.D ;
  wire \outDATA<5>\$WA3.UIM_MC.D1 ;
  wire \outDATA<5>\$WA3.UIM_MC.D2 ;
  wire \outDATA<5>\$WA5.UIM_MC.Q ;
  wire \outDATA<5>\$WA5.UIM_MC.D ;
  wire \outDATA<5>\$WA5.UIM_MC.D1 ;
  wire \outDATA<5>\$WA5.UIM_MC.D2 ;
  wire \outDATA<5>\$WA5.UIM_MC.D2_PT_0 ;
  wire \outDATA<5>\$WA5.UIM_MC.D2_PT_1 ;
  wire \outDATA<5>\$WA4.UIM_MC.Q ;
  wire \outDATA<5>\$WA4.UIM_MC.D ;
  wire \outDATA<5>\$WA4.UIM_MC.D1 ;
  wire \outDATA<5>\$WA4.UIM_MC.D2 ;
  wire \outDATA<5>\$WA4.UIM_MC.D2_PT_0 ;
  wire \outDATA<5>\$WA4.UIM_MC.D2_PT_1 ;
  wire \outDATA<5>\$WA1.UIM_MC.Q ;
  wire \outDATA<5>\$WA1.UIM_MC.D ;
  wire \outDATA<5>\$WA1.UIM_MC.D1 ;
  wire \outDATA<5>\$WA1.UIM_MC.D2 ;
  wire \outDATA<5>\$WA1.UIM_MC.D2_PT_0 ;
  wire \outDATA<5>\$WA1.UIM_MC.D2_PT_1 ;
  wire \outDATA<5>\$WA1.UIM_MC.D2_PT_2 ;
  wire \outDATA<5>\$WA1.UIM_MC.D2_PT_3 ;
  wire \U1/U3/holdingreg0<5>_MC.Q ;
  wire \U1/U3/holdingreg0<5>_MC.D ;
  wire \U1/U3/holdingreg0<5>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ;
  wire \U1/U3/holdingreg0<5>_MC.D1 ;
  wire \U1/U3/holdingreg0<5>_MC.D2 ;
  wire \U1/U3/holdingreg0<5>_MC.D2_PT_0 ;
  wire \U1/U3/holdingreg0<5>_MC.D2_PT_1 ;
  wire \U1/U3/holdingreg1<5>_MC.Q ;
  wire \U1/U3/holdingreg1<5>_MC.D ;
  wire \U1/U3/holdingreg1<5>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ;
  wire \U1/U3/holdingreg1<5>_MC.D1 ;
  wire \U1/U3/holdingreg1<5>_MC.D2 ;
  wire \U1/U3/holdingreg1<5>_MC.D2_PT_0 ;
  wire \U1/U3/holdingreg1<5>_MC.D2_PT_1 ;
  wire \U1/U3/holdingreg0<13>_MC.Q ;
  wire \U1/U3/holdingreg0<13>_MC.D ;
  wire \U1/U3/holdingreg0<13>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ;
  wire \U1/U3/holdingreg0<13>_MC.D1 ;
  wire \U1/U3/holdingreg0<13>_MC.D2 ;
  wire \U1/U3/holdingreg0<13>_MC.D2_PT_0 ;
  wire \U1/U3/holdingreg0<13>_MC.D2_PT_1 ;
  wire \U1/Channel0<13>_MC.Q ;
  wire \U1/Channel0<13>_MC.D ;
  wire \U1/Channel0<13>_MC_tsimcreated_xor_ ;
  wire \U1/Channel0<13>_MC.D1 ;
  wire \U1/Channel0<13>_MC.D2 ;
  wire \U1/Channel0<13>_MC.D2_PT_0 ;
  wire \U1/Channel0<13>_MC.D2_PT_1 ;
  wire \U1/Channel0<13>_MC.D2_PT_2 ;
  wire \U1/U3/holdingreg1<13>_MC.Q ;
  wire \U1/U3/holdingreg1<13>_MC.D ;
  wire \U1/U3/holdingreg1<13>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ;
  wire \U1/U3/holdingreg1<13>_MC.D1 ;
  wire \U1/U3/holdingreg1<13>_MC.D2 ;
  wire \U1/U3/holdingreg1<13>_MC.D2_PT_0 ;
  wire \U1/U3/holdingreg1<13>_MC.D2_PT_1 ;
  wire \U1/Channel1<13>_MC.Q ;
  wire \U1/Channel1<13>_MC.D ;
  wire \U1/Channel1<13>_MC_tsimcreated_xor_ ;
  wire \U1/Channel1<13>_MC.D1 ;
  wire \U1/Channel1<13>_MC.D2 ;
  wire \U1/Channel1<13>_MC.D2_PT_0 ;
  wire \U1/Channel1<13>_MC.D2_PT_1 ;
  wire \U1/Channel1<13>_MC.D2_PT_2 ;
  wire \outDATA<5>\$WA2.UIM_MC.Q ;
  wire \outDATA<5>\$WA2.UIM_MC.D ;
  wire \outDATA<5>\$WA2.UIM_MC.D1 ;
  wire \outDATA<5>\$WA2.UIM_MC.D2 ;
  wire \outDATA<5>\$WA2.UIM_MC.D2_PT_0 ;
  wire \outDATA<5>\$WA2.UIM_MC.D2_PT_1 ;
  wire \outDATA<5>\$WA2.UIM_MC.D2_PT_2 ;
  wire \outDATA<5>\$WA2.UIM_MC.D2_PT_3 ;
  wire \outDATA<5>\$WA2.UIM_MC.D2_PT_4 ;
  wire \U1/U4/Latch0r<5>_MC.Q ;
  wire \U1/U4/Latch0r<5>_MC.D ;
  wire \U1/U4/Latch0r<5>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ;
  wire \U1/U4/Latch0r<5>_MC.D1 ;
  wire \U1/U4/Latch0r<5>_MC.D2 ;
  wire \U1/U4/Latch0r<5>_MC.D2_PT_0 ;
  wire \U1/U4/Latch0r<5>_MC.D2_PT_1 ;
  wire \U1/U4/Latch0r<13>_MC.Q ;
  wire \U1/U4/Latch0r<13>_MC.D ;
  wire \U1/U4/Latch0r<13>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ;
  wire \U1/U4/Latch0r<13>_MC.D1 ;
  wire \U1/U4/Latch0r<13>_MC.D2 ;
  wire \U1/U4/Latch0r<13>_MC.D2_PT_0 ;
  wire \U1/U4/Latch0r<13>_MC.D2_PT_1 ;
  wire \U1/U4/Latch1r<5>_MC.Q ;
  wire \U1/U4/Latch1r<5>_MC.D ;
  wire \U1/U4/Latch1r<5>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ;
  wire \U1/U4/Latch1r<5>_MC.D1 ;
  wire \U1/U4/Latch1r<5>_MC.D2 ;
  wire \U1/U4/Latch1r<5>_MC.D2_PT_0 ;
  wire \U1/U4/Latch1r<5>_MC.D2_PT_1 ;
  wire \U1/U4/Latch1r<13>_MC.Q ;
  wire \U1/U4/Latch1r<13>_MC.D ;
  wire \U1/U4/Latch1r<13>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ;
  wire \U1/U4/Latch1r<13>_MC.D1 ;
  wire \U1/U4/Latch1r<13>_MC.D2 ;
  wire \U1/U4/Latch1r<13>_MC.D2_PT_0 ;
  wire \U1/U4/Latch1r<13>_MC.D2_PT_1 ;
  wire \Enc033ctrl_MC.Q_tsimrenamed_net_ ;
  wire \Enc033ctrl_MC.D ;
  wire \Enc033ctrl_MC.D1 ;
  wire \Enc033ctrl_MC.D2 ;
  wire \U4/ctrlr<2>_MC.D ;
  wire \U4/ctrlr<2>_MC.BUFOE.OUT ;
  wire \U4/ctrlr<2>_MC.D1 ;
  wire \U4/ctrlr<2>_MC.D2 ;
  wire \outDATA<2>\$WA0.UIM ;
  wire \U4/ctrlr<2>_MC.D2_PT_0 ;
  wire \outDATA<2>\$WA3.UIM ;
  wire \U4/ctrlr<2>_MC.D2_PT_1 ;
  wire \outDATA<2>\$WA5.UIM ;
  wire \U4/ctrlr<2>_MC.D2_PT_2 ;
  wire \outDATA<2>\$WA4.UIM ;
  wire \U4/ctrlr<2>_MC.D2_PT_3 ;
  wire \outDATA<2>\$WA1.UIM ;
  wire \U4/ctrlr<2>_MC.D2_PT_4 ;
  wire \outDATA<2>\$WA2.UIM ;
  wire \U4/ctrlr<2>_MC.D2_PT_5 ;
  wire \DCORENCPWRw_MC.Q ;
  wire DCORENCPWRw;
  wire \DCORENCPWRw_MC.D ;
  wire \DCORENCPWRw_MC.D1 ;
  wire \DCORENCPWRw_MC.D2 ;
  wire \U4/ctrlr<3>_MC.D ;
  wire \U4/ctrlr<3>_MC.BUFOE.OUT ;
  wire \U4/ctrlr<3>_MC.D1 ;
  wire \U4/ctrlr<3>_MC.D2 ;
  wire \outDATA<3>\$WA0.UIM ;
  wire \U4/ctrlr<3>_MC.D2_PT_0 ;
  wire \outDATA<3>\$WA3.UIM ;
  wire \U4/ctrlr<3>_MC.D2_PT_1 ;
  wire \outDATA<3>\$WA5.UIM ;
  wire \U4/ctrlr<3>_MC.D2_PT_2 ;
  wire \outDATA<3>\$WA4.UIM ;
  wire \U4/ctrlr<3>_MC.D2_PT_3 ;
  wire \outDATA<3>\$WA1.UIM ;
  wire \U4/ctrlr<3>_MC.D2_PT_4 ;
  wire \outDATA<3>\$WA2.UIM ;
  wire \U4/ctrlr<3>_MC.D2_PT_5 ;
  wire \Enc05ctrl_MC.Q_tsimrenamed_net_ ;
  wire \Enc05ctrl_MC.D ;
  wire \Enc05ctrl_MC.D1 ;
  wire \Enc05ctrl_MC.D2 ;
  wire \Enc133ctrl_MC.Q_tsimrenamed_net_ ;
  wire \Enc133ctrl_MC.D ;
  wire \Enc133ctrl_MC.D1 ;
  wire \Enc133ctrl_MC.D2 ;
  wire \U4/ctrlr<6>_MC.D ;
  wire \U4/ctrlr<6>_MC.BUFOE.OUT ;
  wire \U4/ctrlr<6>_MC.D1 ;
  wire \U4/ctrlr<6>_MC.D2 ;
  wire \outDATA<6>\$WA0.UIM ;
  wire \U4/ctrlr<6>_MC.D2_PT_0 ;
  wire \U4/ctrlr<6>_MC.D2_PT_1 ;
  wire \outDATA<6>\$WA5.UIM ;
  wire \U4/ctrlr<6>_MC.D2_PT_2 ;
  wire \outDATA<6>\$WA4.UIM ;
  wire \U4/ctrlr<6>_MC.D2_PT_3 ;
  wire \outDATA<6>\$WA1.UIM ;
  wire \U4/ctrlr<6>_MC.D2_PT_4 ;
  wire \outDATA<6>\$WA2.UIM ;
  wire \U4/ctrlr<6>_MC.D2_PT_5 ;
  wire \U4/ctrlr<7>_MC.D ;
  wire \U4/ctrlr<7>_MC.BUFOE.OUT ;
  wire \U4/ctrlr<7>_MC.D1 ;
  wire \U4/ctrlr<7>_MC.D2 ;
  wire \outDATA<7>\$WA0.UIM ;
  wire \U4/ctrlr<7>_MC.D2_PT_0 ;
  wire \outDATA<7>\$WA2.UIM ;
  wire \U4/ctrlr<7>_MC.D2_PT_1 ;
  wire \U4/ctrlr<7>_MC.D2_PT_2 ;
  wire \outDATA<7>\$WA5.UIM ;
  wire \U4/ctrlr<7>_MC.D2_PT_3 ;
  wire \U4/ctrlr<7>_MC.D2_PT_4 ;
  wire \outDATA<7>\$WA4.UIM ;
  wire \U4/ctrlr<7>_MC.D2_PT_5 ;
  wire \outDATA<7>\$WA1.UIM ;
  wire \U4/ctrlr<7>_MC.D2_PT_6 ;
  wire \U4/ctrlr<7>_MC.D2_PT_7 ;
  wire \Enc15ctrl_MC.Q_tsimrenamed_net_ ;
  wire \Enc15ctrl_MC.D ;
  wire \Enc15ctrl_MC.D1 ;
  wire \Enc15ctrl_MC.D2 ;
  wire \GPIO8_MC.Q_tsimrenamed_net_ ;
  wire \GPIO8_MC.D ;
  wire \GPIO8_MC.D1 ;
  wire \GPIO8_MC.D2 ;
  wire \GPIO9_MC.Q_tsimrenamed_net_ ;
  wire \GPIO9_MC.D ;
  wire \GPIO9_MC.D1 ;
  wire \GPIO9_MC.D2 ;
  wire \GP_Motor0_1_MC.Q_tsimrenamed_net_ ;
  wire \GP_Motor0_1_MC.UIM ;
  wire \FOOBAR3__ctinst/7 ;
  wire GP_Motor0_1_MC_tsimcreated_prld_;
  wire \GP_Motor0_1_MC.D ;
  wire \GP_Motor0_1_MC.REG_tsimcreated_inv_Mclk_II/FCLK ;
  wire \GP_Motor0_1_MC.D1 ;
  wire \GP_Motor0_1_MC.D2 ;
  wire DCOROUTw;
  wire \GP_Motor0_1_MC.D2_PT_0 ;
  wire \GP_Motor0_1_MC.D2_PT_1 ;
  wire \DCOROUTw_MC.Q ;
  wire \DCOROUTw_MC.D ;
  wire \DCOROUTw_MC.D1 ;
  wire \DCOROUTw_MC.D2 ;
  wire \GP_Motor1_1_MC.Q_tsimrenamed_net_ ;
  wire \GP_Motor1_1_MC.UIM ;
  wire GP_Motor1_1_MC_tsimcreated_prld_;
  wire \GP_Motor1_1_MC.D ;
  wire \GP_Motor1_1_MC.REG_tsimcreated_inv_Mclk_II/FCLK ;
  wire \GP_Motor1_1_MC.D1 ;
  wire \GP_Motor1_1_MC.D2 ;
  wire \GP_Motor1_1_MC.D2_PT_0 ;
  wire \GP_Motor1_1_MC.D2_PT_1 ;
  wire \HSO_MC.Q_tsimrenamed_net_ ;
  wire \HSO_MC.D ;
  wire \HSO_MC.D1 ;
  wire \HSO_MC.D2 ;
  wire \Home033ctrl_MC.Q_tsimrenamed_net_ ;
  wire \FOOBAR2__ctinst/7 ;
  wire Home033ctrl_MC_tsimcreated_prld_;
  wire \Home033ctrl_MC.D ;
  wire \Home033ctrl_MC.REG_tsimcreated_inv_Mclk_II/FCLK ;
  wire \Home033ctrl_MC.CE ;
  wire \Home033ctrl_MC.D1 ;
  wire \Home033ctrl_MC.D2 ;
  wire \Home05ctrl_MC.Q_tsimrenamed_net_ ;
  wire Home05ctrl_MC_tsimcreated_prld_;
  wire \Home05ctrl_MC.D ;
  wire \Home05ctrl_MC.REG_tsimcreated_inv_Mclk_II/FCLK ;
  wire \FOOBAR14__ctinst/4 ;
  wire \Home05ctrl_MC.D1 ;
  wire \Home05ctrl_MC.D2 ;
  wire \Home133ctrl_MC.Q_tsimrenamed_net_ ;
  wire Home133ctrl_MC_tsimcreated_prld_;
  wire \Home133ctrl_MC.D ;
  wire \Home133ctrl_MC.REG_tsimcreated_inv_Mclk_II/FCLK ;
  wire \FOOBAR23__ctinst/4 ;
  wire \Home133ctrl_MC.D1 ;
  wire \Home133ctrl_MC.D2 ;
  wire \Home15ctrl_MC.Q_tsimrenamed_net_ ;
  wire Home15ctrl_MC_tsimcreated_prld_;
  wire \Home15ctrl_MC.D ;
  wire \Home15ctrl_MC.REG_tsimcreated_inv_Mclk_II/FCLK ;
  wire \Home15ctrl_MC.CE ;
  wire \Home15ctrl_MC.D1 ;
  wire \Home15ctrl_MC.D2 ;
  wire \INT_MC.Q_tsimrenamed_net_ ;
  wire \INT_MC.D ;
  wire \INT_MC.D1 ;
  wire \INT_MC.D2 ;
  wire \INT_MC.D2_PT_0 ;
  wire \INT_MC.D2_PT_1 ;
  wire \INT_MC.D2_PT_2 ;
  wire \INT_MC.D2_PT_3 ;
  wire \INT_MC.D2_PT_4 ;
  wire \INT_MC.D2_PT_5 ;
  wire \INT_MC.D2_PT_6 ;
  wire \INT_MC.D2_PT_7 ;
  wire \U3/DCORIE<0>_MC.Q ;
  wire \U3/DCORIE<0>_MC.D ;
  wire \U3/DCORIE<0>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ;
  wire \U3/DCORIE<0>_MC.D1 ;
  wire \U3/DCORIE<0>_MC.D2 ;
  wire DCORIEw;
  wire \U3/DCORIE<0>_MC.D2_PT_0 ;
  wire \U3/DCORIE<0>_MC.D2_PT_1 ;
  wire \DCORIEw_MC.Q ;
  wire \DCORIEw_MC.D ;
  wire \DCORIEw_MC.D1 ;
  wire \DCORIEw_MC.D2 ;
  wire \U3/DCORIE<1>_MC.Q ;
  wire \U3/DCORIE<1>_MC.D ;
  wire \U3/DCORIE<1>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ;
  wire \U3/DCORIE<1>_MC.D1 ;
  wire \U3/DCORIE<1>_MC.D2 ;
  wire \U3/DCORIE<1>_MC.D2_PT_0 ;
  wire \U3/DCORIE<1>_MC.D2_PT_1 ;
  wire \U3/DCORIE<2>_MC.Q ;
  wire \U3/DCORIE<2>_MC.D ;
  wire \U3/DCORIE<2>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ;
  wire \U3/DCORIE<2>_MC.D1 ;
  wire \U3/DCORIE<2>_MC.D2 ;
  wire \U3/DCORIE<2>_MC.D2_PT_0 ;
  wire \U3/DCORIE<2>_MC.D2_PT_1 ;
  wire \U3/DCORIE<3>_MC.Q ;
  wire \U3/DCORIE<3>_MC.D ;
  wire \U3/DCORIE<3>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ;
  wire \U3/DCORIE<3>_MC.D1 ;
  wire \U3/DCORIE<3>_MC.D2 ;
  wire \U3/DCORIE<3>_MC.D2_PT_0 ;
  wire \U3/DCORIE<3>_MC.D2_PT_1 ;
  wire \U3/DCORIE<4>_MC.Q ;
  wire \U3/DCORIE<4>_MC.D ;
  wire \U3/DCORIE<4>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ;
  wire \U3/DCORIE<4>_MC.D1 ;
  wire \U3/DCORIE<4>_MC.D2 ;
  wire \U3/DCORIE<4>_MC.D2_PT_0 ;
  wire \U3/DCORIE<4>_MC.D2_PT_1 ;
  wire \U3/DCORIE<5>_MC.Q ;
  wire \U3/DCORIE<5>_MC.D ;
  wire \U3/DCORIE<5>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ;
  wire \U3/DCORIE<5>_MC.D1 ;
  wire \U3/DCORIE<5>_MC.D2 ;
  wire \U3/DCORIE<5>_MC.D2_PT_0 ;
  wire \U3/DCORIE<5>_MC.D2_PT_1 ;
  wire \U3/DCORIE<6>_MC.Q ;
  wire \U3/DCORIE<6>_MC.D ;
  wire \U3/DCORIE<6>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ;
  wire \U3/DCORIE<6>_MC.D1 ;
  wire \U3/DCORIE<6>_MC.D2 ;
  wire \U3/DCORIE<6>_MC.D2_PT_0 ;
  wire \U3/DCORIE<6>_MC.D2_PT_1 ;
  wire \U3/DCORIE<7>_MC.Q ;
  wire \U3/DCORIE<7>_MC.D ;
  wire \U3/DCORIE<7>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ;
  wire \U3/DCORIE<7>_MC.D1 ;
  wire \U3/DCORIE<7>_MC.D2 ;
  wire \U3/DCORIE<7>_MC.D2_PT_0 ;
  wire \U3/DCORIE<7>_MC.D2_PT_1 ;
  wire \LED1_MC.Q_tsimrenamed_net_ ;
  wire \LED1_MC.D ;
  wire \LED1_MC.D1 ;
  wire \LED1_MC.D2 ;
  wire \U9/MISCr<0>_MC.Q ;
  wire \U9/MISCr<0>_MC_tsimcreated_prld_ ;
  wire \U9/MISCr<0>_MC.D ;
  wire \U9/MISCr<0>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ;
  wire \U9/MISCr<0>_MC.D1 ;
  wire \U9/MISCr<0>_MC.D2 ;
  wire \U9/MISCr<0>_MC.D2_PT_0 ;
  wire \U9/MISCr<0>_MC.D2_PT_1 ;
  wire \LED2_MC.Q_tsimrenamed_net_ ;
  wire \LED2_MC.D ;
  wire \LED2_MC.D1 ;
  wire \LED2_MC.D2 ;
  wire \U9/MISCr<1>_MC.Q ;
  wire \U9/MISCr<1>_MC_tsimcreated_prld_ ;
  wire \U9/MISCr<1>_MC.D ;
  wire \U9/MISCr<1>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ;
  wire \U9/MISCr<1>_MC.D1 ;
  wire \U9/MISCr<1>_MC.D2 ;
  wire \U9/MISCr<1>_MC.D2_PT_0 ;
  wire \U9/MISCr<1>_MC.D2_PT_1 ;
  wire \LED3_MC.Q_tsimrenamed_net_ ;
  wire \LED3_MC.D ;
  wire \LED3_MC.D1 ;
  wire \LED3_MC.D2 ;
  wire \U9/MISCr<2>_MC.Q ;
  wire \U9/MISCr<2>_MC_tsimcreated_prld_ ;
  wire \U9/MISCr<2>_MC.D ;
  wire \U9/MISCr<2>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ;
  wire \U9/MISCr<2>_MC.D1 ;
  wire \U9/MISCr<2>_MC.D2 ;
  wire \U9/MISCr<2>_MC.D2_PT_0 ;
  wire \U9/MISCr<2>_MC.D2_PT_1 ;
  wire \LED4_MC.Q_tsimrenamed_net_ ;
  wire \LED4_MC.D ;
  wire \LED4_MC.D1 ;
  wire \LED4_MC.D2 ;
  wire \U9/MISCr<3>_MC.Q ;
  wire \U9/MISCr<3>_MC_tsimcreated_prld_ ;
  wire \U9/MISCr<3>_MC.D ;
  wire \U9/MISCr<3>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ;
  wire \U9/MISCr<3>_MC.D1 ;
  wire \U9/MISCr<3>_MC.D2 ;
  wire \U9/MISCr<3>_MC.D2_PT_0 ;
  wire \U9/MISCr<3>_MC.D2_PT_1 ;
  wire \LED5_MC.Q_tsimrenamed_net_ ;
  wire \LED5_MC.D ;
  wire \LED5_MC.D1 ;
  wire \LED5_MC.D2 ;
  wire \U9/MISCr<4>_MC.Q ;
  wire \U9/MISCr<4>_MC_tsimcreated_prld_ ;
  wire \U9/MISCr<4>_MC.D ;
  wire \U9/MISCr<4>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ;
  wire \U9/MISCr<4>_MC.D1 ;
  wire \U9/MISCr<4>_MC.D2 ;
  wire \U9/MISCr<4>_MC.D2_PT_0 ;
  wire \U9/MISCr<4>_MC.D2_PT_1 ;
  wire \MHSI_MC.Q_tsimrenamed_net_ ;
  wire \MHSI_MC.D ;
  wire \MHSI_MC.D1 ;
  wire \MHSI_MC.D2 ;
  wire \MTRpwr_MC.Q_tsimrenamed_net_ ;
  wire \MTRpwr_MC.UIM ;
  wire MTRpwr_MC_tsimcreated_prld_;
  wire \MTRpwr_MC.D ;
  wire \MTRpwr_MC.REG_tsimcreated_inv_Mclk_II/FCLK ;
  wire \MTRpwr_MC.D1 ;
  wire \MTRpwr_MC.D2 ;
  wire \MTRpwr_MC.D2_PT_0 ;
  wire \MTRpwr_MC.D2_PT_1 ;
  wire \MTRpwrn_MC.Q_tsimrenamed_net_ ;
  wire \MTRpwrn_MC.UIM ;
  wire \FOOBAR7__ctinst/0 ;
  wire MTRpwrn_MC_tsimcreated_prld_;
  wire \MTRpwrn_MC.D ;
  wire \MTRpwrn_MC.REG_tsimcreated_inv_Mclk_II/FCLK ;
  wire \MTRpwrn_MC.D1 ;
  wire \MTRpwrn_MC.D2 ;
  wire \MTRpwrn_MC.D2_PT_0 ;
  wire \MTRpwrn_MC.D2_PT_1 ;
  wire \MTXI_MC.Q_tsimrenamed_net_ ;
  wire \MTXI_MC.D ;
  wire \MTXI_MC.D1 ;
  wire \MTXI_MC.D2 ;
  wire \PAH0_MC.Q_tsimrenamed_net_ ;
  wire \PAH0_MC.D ;
  wire \PAH0_MC.D1 ;
  wire \PAH0_MC.D2 ;
  wire \PAH1_MC.Q_tsimrenamed_net_ ;
  wire \PAH1_MC.D ;
  wire \PAH1_MC.D1 ;
  wire \PAH1_MC.D2 ;
  wire \PAL0_MC.Q_tsimrenamed_net_ ;
  wire \PAL0_MC.D ;
  wire \PAL0_MC.D1 ;
  wire \PAL0_MC.D2 ;
  wire NET3248;
  wire \PAL0_MC.D2_PT_0 ;
  wire \PAL0_MC.D2_PT_1 ;
  wire \NET3248_MC.Q ;
  wire \NET3248_MC.D ;
  wire NET3248_MC_tsimcreated_xor_;
  wire \NET3248_MC.REG_tsimcreated_inv_Mclk_II/FCLK ;
  wire \NET3248_MC.D1 ;
  wire \NET3248_MC.D2 ;
  wire \NET3248_MC.D2_PT_0 ;
  wire \NET3248_MC.D2_PT_1 ;
  wire \NET3248_MC.D2_PT_2 ;
  wire \NET3248_MC.D2_PT_3 ;
  wire \NET3248_MC.D2_PT_4 ;
  wire \NET3248_MC.D2_PT_5 ;
  wire \PAL1_MC.Q_tsimrenamed_net_ ;
  wire \PAL1_MC.D ;
  wire \PAL1_MC.D1 ;
  wire \PAL1_MC.D2 ;
  wire NET3253;
  wire \PAL1_MC.D2_PT_0 ;
  wire \PAL1_MC.D2_PT_1 ;
  wire \NET3253_MC.Q ;
  wire \NET3253_MC.D ;
  wire NET3253_MC_tsimcreated_xor_;
  wire \NET3253_MC.REG_tsimcreated_inv_Mclk_II/FCLK ;
  wire \NET3253_MC.D1 ;
  wire \NET3253_MC.D2 ;
  wire \NET3253_MC.D2_PT_0 ;
  wire \NET3253_MC.D2_PT_1 ;
  wire \NET3253_MC.D2_PT_2 ;
  wire \NET3253_MC.D2_PT_3 ;
  wire \NET3253_MC.D2_PT_4 ;
  wire \NET3253_MC.D2_PT_5 ;
  wire \PBH0_MC.Q_tsimrenamed_net_ ;
  wire \PBH0_MC.D ;
  wire \PBH0_MC.D1 ;
  wire \PBH0_MC.D2 ;
  wire \PBH1_MC.Q_tsimrenamed_net_ ;
  wire \PBH1_MC.D ;
  wire \PBH1_MC.D1 ;
  wire \PBH1_MC.D2 ;
  wire \PBL0_MC.Q_tsimrenamed_net_ ;
  wire \PBL0_MC.D ;
  wire \PBL0_MC.D1 ;
  wire \PBL0_MC.D2 ;
  wire \PBL0_MC.D2_PT_0 ;
  wire \PBL0_MC.D2_PT_1 ;
  wire \PBL1_MC.Q_tsimrenamed_net_ ;
  wire \PBL1_MC.D ;
  wire \PBL1_MC.D1 ;
  wire \PBL1_MC.D2 ;
  wire \PBL1_MC.D2_PT_0 ;
  wire \PBL1_MC.D2_PT_1 ;
  wire \PresEn_MC.Q_tsimrenamed_net_ ;
  wire PresEn_MC_tsimcreated_prld_;
  wire \PresEn_MC.D ;
  wire \PresEn_MC.REG_tsimcreated_inv_Mclk_II/FCLK ;
  wire \FOOBAR19__ctinst/4 ;
  wire \PresEn_MC.D1 ;
  wire \PresEn_MC.D2 ;
  wire \DCORSENSORw_MC.Q ;
  wire DCORSENSORw;
  wire \DCORSENSORw_MC.D ;
  wire \DCORSENSORw_MC.D1 ;
  wire \DCORSENSORw_MC.D2 ;
  wire \PresSlct_MC.Q_tsimrenamed_net_ ;
  wire \FOOBAR19__ctinst/0 ;
  wire PresSlct_MC_tsimcreated_prld_;
  wire \PresSlct_MC.D ;
  wire \PresSlct_MC.REG_tsimcreated_inv_Mclk_II/FCLK ;
  wire \PresSlct_MC.D1 ;
  wire \PresSlct_MC.D2 ;
  wire \SCLout_MC.Q_tsimrenamed_net_ ;
  wire \SCLout_MC.D ;
  wire \SCLout_MC.D1 ;
  wire \SCLout_MC.D2 ;
  wire \TP10_MC.Q_tsimrenamed_net_ ;
  wire \TP10_MC.D ;
  wire \TP10_MC.D1 ;
  wire \TP10_MC.D2 ;
  wire \TP11_MC.Q_tsimrenamed_net_ ;
  wire \TP11_MC.D ;
  wire \TP11_MC.D1 ;
  wire \TP11_MC.D2 ;
  wire \TmpEn_MC.Q_tsimrenamed_net_ ;
  wire TmpEn_MC_tsimcreated_prld_;
  wire \TmpEn_MC.D ;
  wire \TmpEn_MC.REG_tsimcreated_inv_Mclk_II/FCLK ;
  wire \TmpEn_MC.D1 ;
  wire \TmpEn_MC.D2 ;
  wire \TmpSlct_MC.Q_tsimrenamed_net_ ;
  wire TmpSlct_MC_tsimcreated_prld_;
  wire \TmpSlct_MC.D ;
  wire \TmpSlct_MC.REG_tsimcreated_inv_Mclk_II/FCLK ;
  wire \TmpSlct_MC.D1 ;
  wire \TmpSlct_MC.D2 ;
  wire \outDATA<2>\$WA0.UIM_MC.Q ;
  wire \outDATA<2>\$WA0.UIM_MC.D ;
  wire \outDATA<2>\$WA0.UIM_MC.D1 ;
  wire \outDATA<2>\$WA0.UIM_MC.D2 ;
  wire \outDATA<2>\$WA3.UIM_MC.Q ;
  wire \outDATA<2>\$WA3.UIM_MC.D ;
  wire \outDATA<2>\$WA3.UIM_MC.D1 ;
  wire \outDATA<2>\$WA3.UIM_MC.D2 ;
  wire \outDATA<2>\$WA5.UIM_MC.Q ;
  wire \outDATA<2>\$WA5.UIM_MC.D ;
  wire \outDATA<2>\$WA5.UIM_MC.D1 ;
  wire \outDATA<2>\$WA5.UIM_MC.D2 ;
  wire \outDATA<2>\$WA5.UIM_MC.D2_PT_0 ;
  wire \outDATA<2>\$WA5.UIM_MC.D2_PT_1 ;
  wire \outDATA<2>\$WA4.UIM_MC.Q ;
  wire \outDATA<2>\$WA4.UIM_MC.D ;
  wire \outDATA<2>\$WA4.UIM_MC.D1 ;
  wire \outDATA<2>\$WA4.UIM_MC.D2 ;
  wire \outDATA<2>\$WA1.UIM_MC.Q ;
  wire \outDATA<2>\$WA1.UIM_MC.D ;
  wire \outDATA<2>\$WA1.UIM_MC.D1 ;
  wire \outDATA<2>\$WA1.UIM_MC.D2 ;
  wire \outDATA<2>\$WA1.UIM_MC.D2_PT_0 ;
  wire \outDATA<2>\$WA1.UIM_MC.D2_PT_1 ;
  wire \outDATA<2>\$WA1.UIM_MC.D2_PT_2 ;
  wire \outDATA<2>\$WA1.UIM_MC.D2_PT_3 ;
  wire \U1/U3/holdingreg0<2>_MC.Q ;
  wire \U1/U3/holdingreg0<2>_MC.D ;
  wire \U1/U3/holdingreg0<2>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ;
  wire \U1/U3/holdingreg0<2>_MC.D1 ;
  wire \U1/U3/holdingreg0<2>_MC.D2 ;
  wire \U1/U3/holdingreg0<2>_MC.D2_PT_0 ;
  wire \U1/U3/holdingreg0<2>_MC.D2_PT_1 ;
  wire \U1/U3/holdingreg1<2>_MC.Q ;
  wire \U1/U3/holdingreg1<2>_MC.D ;
  wire \U1/U3/holdingreg1<2>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ;
  wire \U1/U3/holdingreg1<2>_MC.D1 ;
  wire \U1/U3/holdingreg1<2>_MC.D2 ;
  wire \U1/U3/holdingreg1<2>_MC.D2_PT_0 ;
  wire \U1/U3/holdingreg1<2>_MC.D2_PT_1 ;
  wire \U1/U3/holdingreg0<10>_MC.Q ;
  wire \U1/U3/holdingreg0<10>_MC.D ;
  wire \U1/U3/holdingreg0<10>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ;
  wire \U1/U3/holdingreg0<10>_MC.D1 ;
  wire \U1/U3/holdingreg0<10>_MC.D2 ;
  wire \U1/U3/holdingreg0<10>_MC.D2_PT_0 ;
  wire \U1/U3/holdingreg0<10>_MC.D2_PT_1 ;
  wire \U1/U3/holdingreg1<10>_MC.Q ;
  wire \U1/U3/holdingreg1<10>_MC.D ;
  wire \U1/U3/holdingreg1<10>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ;
  wire \U1/U3/holdingreg1<10>_MC.D1 ;
  wire \U1/U3/holdingreg1<10>_MC.D2 ;
  wire \U1/U3/holdingreg1<10>_MC.D2_PT_0 ;
  wire \U1/U3/holdingreg1<10>_MC.D2_PT_1 ;
  wire \outDATA<2>\$WA2.UIM_MC.Q ;
  wire \outDATA<2>\$WA2.UIM_MC.D ;
  wire \outDATA<2>\$WA2.UIM_MC.D1 ;
  wire \outDATA<2>\$WA2.UIM_MC.D2 ;
  wire \outDATA<2>\$WA2.UIM_MC.D2_PT_0 ;
  wire \outDATA<2>\$WA2.UIM_MC.D2_PT_1 ;
  wire \outDATA<2>\$WA2.UIM_MC.D2_PT_2 ;
  wire \outDATA<2>\$WA2.UIM_MC.D2_PT_3 ;
  wire \outDATA<2>\$WA2.UIM_MC.D2_PT_4 ;
  wire \U1/U4/Latch0r<2>_MC.Q ;
  wire \U1/U4/Latch0r<2>_MC.D ;
  wire \U1/U4/Latch0r<2>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ;
  wire \U1/U4/Latch0r<2>_MC.D1 ;
  wire \U1/U4/Latch0r<2>_MC.D2 ;
  wire \U1/U4/Latch0r<2>_MC.D2_PT_0 ;
  wire \U1/U4/Latch0r<2>_MC.D2_PT_1 ;
  wire \U1/U4/Latch0r<10>_MC.Q ;
  wire \U1/U4/Latch0r<10>_MC.D ;
  wire \U1/U4/Latch0r<10>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ;
  wire \U1/U4/Latch0r<10>_MC.D1 ;
  wire \U1/U4/Latch0r<10>_MC.D2 ;
  wire \U1/U4/Latch0r<10>_MC.D2_PT_0 ;
  wire \U1/U4/Latch0r<10>_MC.D2_PT_1 ;
  wire \U1/U4/Latch1r<2>_MC.Q ;
  wire \U1/U4/Latch1r<2>_MC.D ;
  wire \U1/U4/Latch1r<2>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ;
  wire \U1/U4/Latch1r<2>_MC.D1 ;
  wire \U1/U4/Latch1r<2>_MC.D2 ;
  wire \U1/U4/Latch1r<2>_MC.D2_PT_0 ;
  wire \U1/U4/Latch1r<2>_MC.D2_PT_1 ;
  wire \U1/U4/Latch1r<10>_MC.Q ;
  wire \U1/U4/Latch1r<10>_MC.D ;
  wire \U1/U4/Latch1r<10>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ;
  wire \U1/U4/Latch1r<10>_MC.D1 ;
  wire \U1/U4/Latch1r<10>_MC.D2 ;
  wire \U1/U4/Latch1r<10>_MC.D2_PT_0 ;
  wire \U1/U4/Latch1r<10>_MC.D2_PT_1 ;
  wire \outDATA<3>\$WA0.UIM_MC.Q ;
  wire \outDATA<3>\$WA0.UIM_MC.D ;
  wire \outDATA<3>\$WA0.UIM_MC.D1 ;
  wire \outDATA<3>\$WA0.UIM_MC.D2 ;
  wire \outDATA<3>\$WA3.UIM_MC.Q ;
  wire \outDATA<3>\$WA3.UIM_MC.D ;
  wire \outDATA<3>\$WA3.UIM_MC.D1 ;
  wire \outDATA<3>\$WA3.UIM_MC.D2 ;
  wire \outDATA<3>\$WA5.UIM_MC.Q ;
  wire \outDATA<3>\$WA5.UIM_MC.D ;
  wire \outDATA<3>\$WA5.UIM_MC.D1 ;
  wire \outDATA<3>\$WA5.UIM_MC.D2 ;
  wire \outDATA<3>\$WA5.UIM_MC.D2_PT_0 ;
  wire \outDATA<3>\$WA5.UIM_MC.D2_PT_1 ;
  wire \outDATA<3>\$WA4.UIM_MC.Q ;
  wire \outDATA<3>\$WA4.UIM_MC.D ;
  wire \outDATA<3>\$WA4.UIM_MC.D1 ;
  wire \outDATA<3>\$WA4.UIM_MC.D2 ;
  wire \outDATA<3>\$WA1.UIM_MC.Q ;
  wire \outDATA<3>\$WA1.UIM_MC.D ;
  wire \outDATA<3>\$WA1.UIM_MC.D1 ;
  wire \outDATA<3>\$WA1.UIM_MC.D2 ;
  wire \outDATA<3>\$WA1.UIM_MC.D2_PT_0 ;
  wire \outDATA<3>\$WA1.UIM_MC.D2_PT_1 ;
  wire \outDATA<3>\$WA1.UIM_MC.D2_PT_2 ;
  wire \outDATA<3>\$WA1.UIM_MC.D2_PT_3 ;
  wire \U1/U3/holdingreg0<3>_MC.Q ;
  wire \U1/U3/holdingreg0<3>_MC.D ;
  wire \U1/U3/holdingreg0<3>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ;
  wire \U1/U3/holdingreg0<3>_MC.D1 ;
  wire \U1/U3/holdingreg0<3>_MC.D2 ;
  wire \U1/U3/holdingreg0<3>_MC.D2_PT_0 ;
  wire \U1/U3/holdingreg0<3>_MC.D2_PT_1 ;
  wire \U1/U3/holdingreg1<3>_MC.Q ;
  wire \U1/U3/holdingreg1<3>_MC.D ;
  wire \U1/U3/holdingreg1<3>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ;
  wire \U1/U3/holdingreg1<3>_MC.D1 ;
  wire \U1/U3/holdingreg1<3>_MC.D2 ;
  wire \U1/U3/holdingreg1<3>_MC.D2_PT_0 ;
  wire \U1/U3/holdingreg1<3>_MC.D2_PT_1 ;
  wire \U1/U3/holdingreg0<11>_MC.Q ;
  wire \U1/U3/holdingreg0<11>_MC.D ;
  wire \U1/U3/holdingreg0<11>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ;
  wire \U1/U3/holdingreg0<11>_MC.D1 ;
  wire \U1/U3/holdingreg0<11>_MC.D2 ;
  wire \U1/U3/holdingreg0<11>_MC.D2_PT_0 ;
  wire \U1/U3/holdingreg0<11>_MC.D2_PT_1 ;
  wire \U1/U3/holdingreg1<11>_MC.Q ;
  wire \U1/U3/holdingreg1<11>_MC.D ;
  wire \U1/U3/holdingreg1<11>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ;
  wire \U1/U3/holdingreg1<11>_MC.D1 ;
  wire \U1/U3/holdingreg1<11>_MC.D2 ;
  wire \U1/U3/holdingreg1<11>_MC.D2_PT_0 ;
  wire \U1/U3/holdingreg1<11>_MC.D2_PT_1 ;
  wire \outDATA<3>\$WA2.UIM_MC.Q ;
  wire \outDATA<3>\$WA2.UIM_MC.D ;
  wire \outDATA<3>\$WA2.UIM_MC.D1 ;
  wire \outDATA<3>\$WA2.UIM_MC.D2 ;
  wire \outDATA<3>\$WA2.UIM_MC.D2_PT_0 ;
  wire \outDATA<3>\$WA2.UIM_MC.D2_PT_1 ;
  wire \outDATA<3>\$WA2.UIM_MC.D2_PT_2 ;
  wire \outDATA<3>\$WA2.UIM_MC.D2_PT_3 ;
  wire \outDATA<3>\$WA2.UIM_MC.D2_PT_4 ;
  wire \U1/U4/Latch0r<3>_MC.Q ;
  wire \U1/U4/Latch0r<3>_MC.D ;
  wire \U1/U4/Latch0r<3>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ;
  wire \U1/U4/Latch0r<3>_MC.D1 ;
  wire \U1/U4/Latch0r<3>_MC.D2 ;
  wire \U1/U4/Latch0r<3>_MC.D2_PT_0 ;
  wire \U1/U4/Latch0r<3>_MC.D2_PT_1 ;
  wire \U1/U4/Latch0r<11>_MC.Q ;
  wire \U1/U4/Latch0r<11>_MC.D ;
  wire \U1/U4/Latch0r<11>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ;
  wire \U1/U4/Latch0r<11>_MC.D1 ;
  wire \U1/U4/Latch0r<11>_MC.D2 ;
  wire \U1/U4/Latch0r<11>_MC.D2_PT_0 ;
  wire \U1/U4/Latch0r<11>_MC.D2_PT_1 ;
  wire \U1/U4/Latch1r<3>_MC.Q ;
  wire \U1/U4/Latch1r<3>_MC.D ;
  wire \U1/U4/Latch1r<3>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ;
  wire \U1/U4/Latch1r<3>_MC.D1 ;
  wire \U1/U4/Latch1r<3>_MC.D2 ;
  wire \U1/U4/Latch1r<3>_MC.D2_PT_0 ;
  wire \U1/U4/Latch1r<3>_MC.D2_PT_1 ;
  wire \U1/U4/Latch1r<11>_MC.Q ;
  wire \U1/U4/Latch1r<11>_MC.D ;
  wire \U1/U4/Latch1r<11>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ;
  wire \U1/U4/Latch1r<11>_MC.D1 ;
  wire \U1/U4/Latch1r<11>_MC.D2 ;
  wire \U1/U4/Latch1r<11>_MC.D2_PT_0 ;
  wire \U1/U4/Latch1r<11>_MC.D2_PT_1 ;
  wire \outDATA<6>\$WA0.UIM_MC.Q ;
  wire \outDATA<6>\$WA0.UIM_MC.D ;
  wire \outDATA<6>\$WA0.UIM_MC.D1 ;
  wire \outDATA<6>\$WA0.UIM_MC.D2 ;
  wire \outDATA<6>\$WA5.UIM_MC.Q ;
  wire \outDATA<6>\$WA5.UIM_MC.D ;
  wire \outDATA<6>\$WA5.UIM_MC.D1 ;
  wire \outDATA<6>\$WA5.UIM_MC.D2 ;
  wire \outDATA<6>\$WA5.UIM_MC.D2_PT_0 ;
  wire \outDATA<6>\$WA5.UIM_MC.D2_PT_1 ;
  wire \outDATA<6>\$WA4.UIM_MC.Q ;
  wire \outDATA<6>\$WA4.UIM_MC.D ;
  wire \outDATA<6>\$WA4.UIM_MC.D1 ;
  wire \outDATA<6>\$WA4.UIM_MC.D2 ;
  wire \outDATA<6>\$WA1.UIM_MC.Q ;
  wire \outDATA<6>\$WA1.UIM_MC.D ;
  wire \outDATA<6>\$WA1.UIM_MC.D1 ;
  wire \outDATA<6>\$WA1.UIM_MC.D2 ;
  wire \outDATA<6>\$WA1.UIM_MC.D2_PT_0 ;
  wire \outDATA<6>\$WA1.UIM_MC.D2_PT_1 ;
  wire \outDATA<6>\$WA1.UIM_MC.D2_PT_2 ;
  wire \outDATA<6>\$WA1.UIM_MC.D2_PT_3 ;
  wire \U1/U3/holdingreg0<6>_MC.Q ;
  wire \U1/U3/holdingreg0<6>_MC.D ;
  wire \U1/U3/holdingreg0<6>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ;
  wire \U1/U3/holdingreg0<6>_MC.D1 ;
  wire \U1/U3/holdingreg0<6>_MC.D2 ;
  wire \U1/U3/holdingreg0<6>_MC.D2_PT_0 ;
  wire \U1/U3/holdingreg0<6>_MC.D2_PT_1 ;
  wire \U1/U3/holdingreg1<6>_MC.Q ;
  wire \U1/U3/holdingreg1<6>_MC.D ;
  wire \U1/U3/holdingreg1<6>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ;
  wire \U1/U3/holdingreg1<6>_MC.D1 ;
  wire \U1/U3/holdingreg1<6>_MC.D2 ;
  wire \U1/U3/holdingreg1<6>_MC.D2_PT_0 ;
  wire \U1/U3/holdingreg1<6>_MC.D2_PT_1 ;
  wire \U1/U3/holdingreg0<14>_MC.Q ;
  wire \U1/U3/holdingreg0<14>_MC.D ;
  wire \U1/U3/holdingreg0<14>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ;
  wire \U1/U3/holdingreg0<14>_MC.D1 ;
  wire \U1/U3/holdingreg0<14>_MC.D2 ;
  wire \U1/U3/holdingreg0<14>_MC.D2_PT_0 ;
  wire \U1/U3/holdingreg0<14>_MC.D2_PT_1 ;
  wire \U1/Channel0<14>_MC.Q ;
  wire \U1/Channel0<14>_MC.D ;
  wire \U1/Channel0<14>_MC_tsimcreated_xor_ ;
  wire \U1/Channel0<14>_MC.D1 ;
  wire \U1/Channel0<14>_MC.D2 ;
  wire \U1/Channel0<14>_MC.D2_PT_0 ;
  wire \U1/Channel0<14>_MC.D2_PT_1 ;
  wire \U1/Channel0<14>_MC.D2_PT_2 ;
  wire \U1/U3/holdingreg1<14>_MC.Q ;
  wire \U1/U3/holdingreg1<14>_MC.D ;
  wire \U1/U3/holdingreg1<14>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ;
  wire \U1/U3/holdingreg1<14>_MC.D1 ;
  wire \U1/U3/holdingreg1<14>_MC.D2 ;
  wire \U1/U3/holdingreg1<14>_MC.D2_PT_0 ;
  wire \U1/U3/holdingreg1<14>_MC.D2_PT_1 ;
  wire \U1/Channel1<14>_MC.Q ;
  wire \U1/Channel1<14>_MC.D ;
  wire \U1/Channel1<14>_MC_tsimcreated_xor_ ;
  wire \U1/Channel1<14>_MC.D1 ;
  wire \U1/Channel1<14>_MC.D2 ;
  wire \U1/Channel1<14>_MC.D2_PT_0 ;
  wire \U1/Channel1<14>_MC.D2_PT_1 ;
  wire \U1/Channel1<14>_MC.D2_PT_2 ;
  wire \outDATA<6>\$WA2.UIM_MC.Q ;
  wire \outDATA<6>\$WA2.UIM_MC.D ;
  wire \outDATA<6>\$WA2.UIM_MC.D1 ;
  wire \outDATA<6>\$WA2.UIM_MC.D2 ;
  wire \outDATA<6>\$WA2.UIM_MC.D2_PT_0 ;
  wire \outDATA<6>\$WA2.UIM_MC.D2_PT_1 ;
  wire \outDATA<6>\$WA2.UIM_MC.D2_PT_2 ;
  wire \outDATA<6>\$WA2.UIM_MC.D2_PT_3 ;
  wire \outDATA<6>\$WA2.UIM_MC.D2_PT_4 ;
  wire \U1/U4/Latch0r<6>_MC.Q ;
  wire \U1/U4/Latch0r<6>_MC.D ;
  wire \U1/U4/Latch0r<6>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ;
  wire \U1/U4/Latch0r<6>_MC.D1 ;
  wire \U1/U4/Latch0r<6>_MC.D2 ;
  wire \U1/U4/Latch0r<6>_MC.D2_PT_0 ;
  wire \U1/U4/Latch0r<6>_MC.D2_PT_1 ;
  wire \U1/U4/Latch0r<14>_MC.Q ;
  wire \U1/U4/Latch0r<14>_MC.D ;
  wire \U1/U4/Latch0r<14>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ;
  wire \U1/U4/Latch0r<14>_MC.D1 ;
  wire \U1/U4/Latch0r<14>_MC.D2 ;
  wire \U1/U4/Latch0r<14>_MC.D2_PT_0 ;
  wire \U1/U4/Latch0r<14>_MC.D2_PT_1 ;
  wire \U1/U4/Latch1r<6>_MC.Q ;
  wire \U1/U4/Latch1r<6>_MC.D ;
  wire \U1/U4/Latch1r<6>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ;
  wire \U1/U4/Latch1r<6>_MC.D1 ;
  wire \U1/U4/Latch1r<6>_MC.D2 ;
  wire \U1/U4/Latch1r<6>_MC.D2_PT_0 ;
  wire \U1/U4/Latch1r<6>_MC.D2_PT_1 ;
  wire \U1/U4/Latch1r<14>_MC.Q ;
  wire \U1/U4/Latch1r<14>_MC.D ;
  wire \U1/U4/Latch1r<14>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ;
  wire \U1/U4/Latch1r<14>_MC.D1 ;
  wire \U1/U4/Latch1r<14>_MC.D2 ;
  wire \U1/U4/Latch1r<14>_MC.D2_PT_0 ;
  wire \U1/U4/Latch1r<14>_MC.D2_PT_1 ;
  wire \outDATA<7>\$WA0.UIM_MC.Q ;
  wire \outDATA<7>\$WA0.UIM_MC.D ;
  wire \outDATA<7>\$WA0.UIM_MC.D1 ;
  wire \outDATA<7>\$WA0.UIM_MC.D2 ;
  wire \outDATA<7>\$WA2.UIM_MC.Q ;
  wire \outDATA<7>\$WA2.UIM_MC.D ;
  wire \outDATA<7>\$WA2.UIM_MC.D1 ;
  wire \outDATA<7>\$WA2.UIM_MC.D2 ;
  wire \outDATA<7>\$WA2.UIM_MC.D2_PT_0 ;
  wire \outDATA<7>\$WA2.UIM_MC.D2_PT_1 ;
  wire \outDATA<7>\$WA2.UIM_MC.D2_PT_2 ;
  wire \outDATA<7>\$WA2.UIM_MC.D2_PT_3 ;
  wire \U1/U4/Latch0r<7>_MC.Q ;
  wire \U1/U4/Latch0r<7>_MC.D ;
  wire \U1/U4/Latch0r<7>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ;
  wire \U1/U4/Latch0r<7>_MC.D1 ;
  wire \U1/U4/Latch0r<7>_MC.D2 ;
  wire \U1/U4/Latch0r<7>_MC.D2_PT_0 ;
  wire \U1/U4/Latch0r<7>_MC.D2_PT_1 ;
  wire \U1/U4/Latch0r<15>_MC.Q ;
  wire \U1/U4/Latch0r<15>_MC.D ;
  wire \U1/U4/Latch0r<15>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ;
  wire \U1/U4/Latch0r<15>_MC.D1 ;
  wire \U1/U4/Latch0r<15>_MC.D2 ;
  wire \U1/U4/Latch0r<15>_MC.D2_PT_0 ;
  wire \U1/U4/Latch0r<15>_MC.D2_PT_1 ;
  wire \U1/Channel0<15>_MC.Q ;
  wire \U1/Channel0<15>_MC.D ;
  wire \U1/Channel0<15>_MC_tsimcreated_xor_ ;
  wire \U1/Channel0<15>_MC.D1 ;
  wire \U1/Channel0<15>_MC.D2 ;
  wire \U1/Channel0<15>_MC.D2_PT_0 ;
  wire \U1/Channel0<15>_MC.D2_PT_1 ;
  wire \U1/Channel0<15>_MC.D2_PT_2 ;
  wire \U1/U4/Latch1r<7>_MC.Q ;
  wire \U1/U4/Latch1r<7>_MC.D ;
  wire \U1/U4/Latch1r<7>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ;
  wire \U1/U4/Latch1r<7>_MC.D1 ;
  wire \U1/U4/Latch1r<7>_MC.D2 ;
  wire \U1/U4/Latch1r<7>_MC.D2_PT_0 ;
  wire \U1/U4/Latch1r<7>_MC.D2_PT_1 ;
  wire \U1/U4/Latch1r<15>_MC.Q ;
  wire \U1/U4/Latch1r<15>_MC.D ;
  wire \U1/U4/Latch1r<15>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ;
  wire \U1/U4/Latch1r<15>_MC.D1 ;
  wire \U1/U4/Latch1r<15>_MC.D2 ;
  wire \U1/U4/Latch1r<15>_MC.D2_PT_0 ;
  wire \U1/U4/Latch1r<15>_MC.D2_PT_1 ;
  wire \U1/Channel1<15>_MC.Q ;
  wire \U1/Channel1<15>_MC.D ;
  wire \U1/Channel1<15>_MC_tsimcreated_xor_ ;
  wire \U1/Channel1<15>_MC.D1 ;
  wire \U1/Channel1<15>_MC.D2 ;
  wire \U1/Channel1<15>_MC.D2_PT_0 ;
  wire \U1/Channel1<15>_MC.D2_PT_1 ;
  wire \U1/Channel1<15>_MC.D2_PT_2 ;
  wire \outDATA<7>\$WA5.UIM_MC.Q ;
  wire \outDATA<7>\$WA5.UIM_MC.D ;
  wire \outDATA<7>\$WA5.UIM_MC.D1 ;
  wire \outDATA<7>\$WA5.UIM_MC.D2 ;
  wire \outDATA<7>\$WA5.UIM_MC.D2_PT_0 ;
  wire \outDATA<7>\$WA5.UIM_MC.D2_PT_1 ;
  wire \outDATA<7>\$WA4.UIM_MC.Q ;
  wire \outDATA<7>\$WA4.UIM_MC.D ;
  wire \outDATA<7>\$WA4.UIM_MC.D1 ;
  wire \outDATA<7>\$WA4.UIM_MC.D2 ;
  wire \outDATA<7>\$WA1.UIM_MC.Q ;
  wire \outDATA<7>\$WA1.UIM_MC.D ;
  wire \outDATA<7>\$WA1.UIM_MC.D1 ;
  wire \outDATA<7>\$WA1.UIM_MC.D2 ;
  wire \outDATA<7>\$WA1.UIM_MC.D2_PT_0 ;
  wire \outDATA<7>\$WA1.UIM_MC.D2_PT_1 ;
  wire \outDATA<7>\$WA1.UIM_MC.D2_PT_2 ;
  wire \outDATA<7>\$WA1.UIM_MC.D2_PT_3 ;
  wire \U1/U3/holdingreg0<7>_MC.Q ;
  wire \U1/U3/holdingreg0<7>_MC.D ;
  wire \U1/U3/holdingreg0<7>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ;
  wire \U1/U3/holdingreg0<7>_MC.D1 ;
  wire \U1/U3/holdingreg0<7>_MC.D2 ;
  wire \U1/U3/holdingreg0<7>_MC.D2_PT_0 ;
  wire \U1/U3/holdingreg0<7>_MC.D2_PT_1 ;
  wire \U1/U3/holdingreg1<7>_MC.Q ;
  wire \U1/U3/holdingreg1<7>_MC.D ;
  wire \U1/U3/holdingreg1<7>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ;
  wire \U1/U3/holdingreg1<7>_MC.D1 ;
  wire \U1/U3/holdingreg1<7>_MC.D2 ;
  wire \U1/U3/holdingreg1<7>_MC.D2_PT_0 ;
  wire \U1/U3/holdingreg1<7>_MC.D2_PT_1 ;
  wire \U1/U3/holdingreg0<15>_MC.Q ;
  wire \U1/U3/holdingreg0<15>_MC.D ;
  wire \U1/U3/holdingreg0<15>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ;
  wire \U1/U3/holdingreg0<15>_MC.D1 ;
  wire \U1/U3/holdingreg0<15>_MC.D2 ;
  wire \U1/U3/holdingreg0<15>_MC.D2_PT_0 ;
  wire \U1/U3/holdingreg0<15>_MC.D2_PT_1 ;
  wire \U1/U3/holdingreg1<15>_MC.Q ;
  wire \U1/U3/holdingreg1<15>_MC.D ;
  wire \U1/U3/holdingreg1<15>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ;
  wire \U1/U3/holdingreg1<15>_MC.D1 ;
  wire \U1/U3/holdingreg1<15>_MC.D2 ;
  wire \U1/U3/holdingreg1<15>_MC.D2_PT_0 ;
  wire \U1/U3/holdingreg1<15>_MC.D2_PT_1 ;
  wire \NlwInverterSignal_AD<0>_MC.D/IN0 ;
  wire \NlwInverterSignal_AD<0>_MC.D2_PT_0/IN1 ;
  wire \NlwInverterSignal_AD<0>_MC.D2_PT_1/IN1 ;
  wire \NlwInverterSignal_AD<0>_MC.D2_PT_2/IN1 ;
  wire \NlwInverterSignal_AD<0>_MC.D2_PT_3/IN1 ;
  wire \NlwInverterSignal_AD<0>_MC.D2_PT_4/IN1 ;
  wire \NlwInverterSignal_AD<0>_MC.D2_PT_5/IN0 ;
  wire \NlwInverterSignal_AD<0>_MC.D2_PT_5/IN1 ;
  wire \NlwInverterSignal_AD<0>_MC.D2_PT_6/IN0 ;
  wire \NlwInverterSignal_AD<0>_MC.D2_PT_6/IN1 ;
  wire \NlwInverterSignal_AD<0>_MC.D2_PT_7/IN0 ;
  wire \NlwInverterSignal_AD<0>_MC.D2_PT_7/IN1 ;
  wire \NlwInverterSignal_AD<0>_MC.D2_PT_7/IN2 ;
  wire \NlwInverterSignal_DCORI2CCNTr_MC.D1/IN1 ;
  wire \NlwInverterSignal_DCORI2CCNTr_MC.D1/IN2 ;
  wire \NlwInverterSignal_DCORI2CCNTr_MC.D1/IN3 ;
  wire \NlwInverterSignal_DCORI2CCNTr_MC.D1/IN4 ;
  wire \NlwInverterSignal_DCORI2CCNTr_MC.D1/IN5 ;
  wire \NlwInverterSignal_DCORI2CCNTr_MC.D1/IN6 ;
  wire \NlwInverterSignal_DCORI2CCNTr_MC.D1/IN7 ;
  wire \NlwInverterSignal_DCORI2CCNTr_MC.D1/IN8 ;
  wire \NlwInverterSignal_DCORI2CCNTr_MC.D1/IN9 ;
  wire \NlwInverterSignal_U2_ADDR_reg<0>_MC.D2_PT_0/IN1 ;
  wire \NlwInverterSignal_U2_ADDR_reg<0>_MC.D2_PT_1/IN3 ;
  wire \NlwInverterSignal_U2_ADDR_reg<0>_MC.D2_PT_1/IN4 ;
  wire \NlwInverterSignal_U2_ADDR_reg<0>_MC.D2_PT_2/IN2 ;
  wire \NlwInverterSignal_U2_ADDR_reg<0>_MC.D2_PT_2/IN5 ;
  wire \NlwInverterSignal_U2_ADDR_reg<0>_MC.D2_PT_3/IN2 ;
  wire \NlwInverterSignal_U2_ADDR_reg<0>_MC.D2_PT_3/IN3 ;
  wire \NlwInverterSignal_U2_ADDR_reg<0>_MC.D2_PT_3/IN4 ;
  wire \NlwInverterSignal_U2_ADDR_reg<0>_MC.D2_PT_3/IN5 ;
  wire \NlwInverterSignal_U2_ADDR_reg<0>_MC.D2_PT_3/IN7 ;
  wire \NlwInverterSignal_U2_ADDR_reg<4>_MC.D2_PT_0/IN1 ;
  wire \NlwInverterSignal_U2_ADDR_reg<4>_MC.D2_PT_1/IN3 ;
  wire \NlwInverterSignal_U2_ADDR_reg<4>_MC.D2_PT_1/IN5 ;
  wire \NlwInverterSignal_U2_ADDR_reg<4>_MC.D2_PT_2/IN2 ;
  wire \NlwInverterSignal_U2_ADDR_reg<4>_MC.D2_PT_2/IN4 ;
  wire \NlwInverterSignal_U2_ADDR_reg<5>_MC.D2_PT_0/IN1 ;
  wire \NlwInverterSignal_U2_ADDR_reg<5>_MC.D2_PT_1/IN3 ;
  wire \NlwInverterSignal_U2_ADDR_reg<5>_MC.D2_PT_1/IN5 ;
  wire \NlwInverterSignal_U2_ADDR_reg<5>_MC.D2_PT_2/IN2 ;
  wire \NlwInverterSignal_U2_ADDR_reg<5>_MC.D2_PT_2/IN4 ;
  wire \NlwInverterSignal_U2_ADDR_reg<6>_MC.D2_PT_0/IN1 ;
  wire \NlwInverterSignal_U2_ADDR_reg<6>_MC.D2_PT_1/IN3 ;
  wire \NlwInverterSignal_U2_ADDR_reg<6>_MC.D2_PT_1/IN5 ;
  wire \NlwInverterSignal_U2_ADDR_reg<6>_MC.D2_PT_2/IN2 ;
  wire \NlwInverterSignal_U2_ADDR_reg<6>_MC.D2_PT_2/IN4 ;
  wire \NlwInverterSignal_U2_ADDR_reg<7>_MC.D2_PT_0/IN1 ;
  wire \NlwInverterSignal_U2_ADDR_reg<7>_MC.D2_PT_1/IN3 ;
  wire \NlwInverterSignal_U2_ADDR_reg<7>_MC.D2_PT_1/IN5 ;
  wire \NlwInverterSignal_U2_ADDR_reg<7>_MC.D2_PT_2/IN2 ;
  wire \NlwInverterSignal_U2_ADDR_reg<7>_MC.D2_PT_2/IN4 ;
  wire \NlwInverterSignal_U2_AutoInc_MC.D/IN0 ;
  wire \NlwInverterSignal_N_PZ_992_MC.D2_PT_1/IN1 ;
  wire \NlwInverterSignal_U2_ADDR_reg<3>_MC.D2_PT_0/IN1 ;
  wire \NlwInverterSignal_U2_ADDR_reg<3>_MC.D2_PT_1/IN3 ;
  wire \NlwInverterSignal_U2_ADDR_reg<3>_MC.D2_PT_1/IN5 ;
  wire \NlwInverterSignal_U2_ADDR_reg<3>_MC.D2_PT_2/IN2 ;
  wire \NlwInverterSignal_U2_ADDR_reg<3>_MC.D2_PT_2/IN4 ;
  wire \NlwInverterSignal_U2_ADDR_reg<3>_MC.D2_PT_3/IN3 ;
  wire \NlwInverterSignal_U2_ADDR_reg<3>_MC.D2_PT_3/IN4 ;
  wire \NlwInverterSignal_U2_ADDR_reg<3>_MC.D2_PT_3/IN5 ;
  wire \NlwInverterSignal_U2_ADDR_reg<3>_MC.D2_PT_3/IN6 ;
  wire \NlwInverterSignal_U2_ADDR_reg<3>_MC.D2_PT_3/IN10 ;
  wire \NlwInverterSignal_U2_ADDR_reg<1>_MC.D2_PT_0/IN1 ;
  wire \NlwInverterSignal_U2_ADDR_reg<1>_MC.D2_PT_1/IN3 ;
  wire \NlwInverterSignal_U2_ADDR_reg<1>_MC.D2_PT_1/IN5 ;
  wire \NlwInverterSignal_U2_ADDR_reg<1>_MC.D2_PT_2/IN2 ;
  wire \NlwInverterSignal_U2_ADDR_reg<1>_MC.D2_PT_2/IN4 ;
  wire \NlwInverterSignal_U2_ADDR_reg<1>_MC.D2_PT_3/IN3 ;
  wire \NlwInverterSignal_U2_ADDR_reg<1>_MC.D2_PT_3/IN4 ;
  wire \NlwInverterSignal_U2_ADDR_reg<1>_MC.D2_PT_3/IN5 ;
  wire \NlwInverterSignal_U2_ADDR_reg<1>_MC.D2_PT_3/IN6 ;
  wire \NlwInverterSignal_U2_ADDR_reg<1>_MC.D2_PT_3/IN8 ;
  wire \NlwInverterSignal_U2_ADDR_reg<2>_MC.D2_PT_0/IN1 ;
  wire \NlwInverterSignal_U2_ADDR_reg<2>_MC.D2_PT_1/IN3 ;
  wire \NlwInverterSignal_U2_ADDR_reg<2>_MC.D2_PT_1/IN5 ;
  wire \NlwInverterSignal_U2_ADDR_reg<2>_MC.D2_PT_2/IN2 ;
  wire \NlwInverterSignal_U2_ADDR_reg<2>_MC.D2_PT_2/IN4 ;
  wire \NlwInverterSignal_U2_ADDR_reg<2>_MC.D2_PT_3/IN3 ;
  wire \NlwInverterSignal_U2_ADDR_reg<2>_MC.D2_PT_3/IN4 ;
  wire \NlwInverterSignal_U2_ADDR_reg<2>_MC.D2_PT_3/IN5 ;
  wire \NlwInverterSignal_U2_ADDR_reg<2>_MC.D2_PT_3/IN6 ;
  wire \NlwInverterSignal_U2_ADDR_reg<2>_MC.D2_PT_3/IN9 ;
  wire \NlwInverterSignal_U11_U3_counterr<0>_MC.D2_PT_1/IN1 ;
  wire \NlwInverterSignal_U11_U3_counterr<0>_MC.D2_PT_2/IN1 ;
  wire \NlwInverterSignal_U11_U3_counterr<0>_MC.D2_PT_2/IN2 ;
  wire \NlwInverterSignal_U11_U3_counterr<0>_MC.D2_PT_2/IN3 ;
  wire \NlwInverterSignal_U11_U3_counterr<0>_MC.D2_PT_3/IN0 ;
  wire \NlwInverterSignal_U11_U3_counterr<0>_MC.D2_PT_3/IN1 ;
  wire \NlwInverterSignal_U11_U3_counterr<0>_MC.D2_PT_3/IN3 ;
  wire \NlwInverterSignal_U11_U3_counterr<0>_MC.D2_PT_4/IN0 ;
  wire \NlwInverterSignal_U11_U3_counterr<0>_MC.D2_PT_4/IN1 ;
  wire \NlwInverterSignal_U11_U3_counterr<0>_MC.D2_PT_5/IN0 ;
  wire \NlwInverterSignal_U11_U3_counterr<0>_MC.D2_PT_5/IN1 ;
  wire \NlwInverterSignal_U11_U3_counterr<0>_MC.D2_PT_5/IN2 ;
  wire \NlwInverterSignal_U11_U3_counterr<0>_MC.D2_PT_5/IN4 ;
  wire \NlwInverterSignal_U11_Incdetect_MC.D1/IN0 ;
  wire \NlwInverterSignal_U11_SCLdetect_MC.D1/IN0 ;
  wire \NlwInverterSignal_TP12_MC.D1/IN0 ;
  wire \NlwInverterSignal_TP12_MC.D1/IN1 ;
  wire \NlwInverterSignal_TP12_MC.D1/IN2 ;
  wire \NlwInverterSignal_TP12_MC.D1/IN3 ;
  wire \NlwInverterSignal_TP12_MC.D1/IN4 ;
  wire \NlwInverterSignal_TP12_MC.D1/IN5 ;
  wire \NlwInverterSignal_U11_U3_counterr<3>_MC.D/IN0 ;
  wire \NlwInverterSignal_U11_U3_counterr<3>_MC.D2_PT_1/IN1 ;
  wire \NlwInverterSignal_U11_U3_counterr<3>_MC.D2_PT_1/IN2 ;
  wire \NlwInverterSignal_U11_U3_counterr<3>_MC.D2_PT_2/IN0 ;
  wire \NlwInverterSignal_U11_U3_counterr<3>_MC.D2_PT_2/IN1 ;
  wire \NlwInverterSignal_U11_U3_counterr<3>_MC.D2_PT_3/IN0 ;
  wire \NlwInverterSignal_U11_U3_counterr<3>_MC.D2_PT_3/IN1 ;
  wire \NlwInverterSignal_U11_U3_counterr<3>_MC.D2_PT_3/IN2 ;
  wire \NlwInverterSignal_U11_U3_counterr<3>_MC.D2_PT_4/IN0 ;
  wire \NlwInverterSignal_U11_U3_counterr<3>_MC.D2_PT_4/IN2 ;
  wire \NlwInverterSignal_U11_U3_counterr<3>_MC.D2_PT_5/IN0 ;
  wire \NlwInverterSignal_U11_U3_counterr<3>_MC.D2_PT_5/IN2 ;
  wire \NlwInverterSignal_U11_U3_counterr<3>_MC.D2_PT_6/IN1 ;
  wire \NlwInverterSignal_U11_U3_counterr<3>_MC.D2_PT_6/IN4 ;
  wire \NlwInverterSignal_N_PZ_1128_MC.D2_PT_1/IN0 ;
  wire \NlwInverterSignal_N_PZ_1128_MC.D2_PT_2/IN0 ;
  wire \NlwInverterSignal_U11_ResetDetect_MC.D1/IN0 ;
  wire \NlwInverterSignal_U11_U3_counterr<1>_MC.D2_PT_0/IN1 ;
  wire \NlwInverterSignal_U11_U3_counterr<1>_MC.D2_PT_1/IN2 ;
  wire \NlwInverterSignal_U11_U3_counterr<1>_MC.D2_PT_1/IN3 ;
  wire \NlwInverterSignal_U11_U3_counterr<1>_MC.D2_PT_2/IN0 ;
  wire \NlwInverterSignal_U11_U3_counterr<1>_MC.D2_PT_2/IN1 ;
  wire \NlwInverterSignal_U11_U3_counterr<1>_MC.D2_PT_2/IN3 ;
  wire \NlwInverterSignal_U11_U3_counterr<2>_MC.D2_PT_1/IN2 ;
  wire \NlwInverterSignal_U11_U3_counterr<2>_MC.D2_PT_1/IN4 ;
  wire \NlwInverterSignal_U11_U3_counterr<2>_MC.D2_PT_2/IN0 ;
  wire \NlwInverterSignal_U11_U3_counterr<2>_MC.D2_PT_2/IN1 ;
  wire \NlwInverterSignal_U11_U3_counterr<2>_MC.D2_PT_2/IN3 ;
  wire \NlwInverterSignal_U11_U3_counterr<2>_MC.D2_PT_2/IN4 ;
  wire \NlwInverterSignal_U11_U3_counterr<4>_MC.D2_PT_1/IN2 ;
  wire \NlwInverterSignal_U11_U3_counterr<4>_MC.D2_PT_2/IN2 ;
  wire \NlwInverterSignal_U11_U3_counterr<4>_MC.D2_PT_2/IN5 ;
  wire \NlwInverterSignal_U11_U3_counterr<4>_MC.D2_PT_3/IN0 ;
  wire \NlwInverterSignal_U11_U3_counterr<4>_MC.D2_PT_3/IN1 ;
  wire \NlwInverterSignal_U11_U3_counterr<4>_MC.D2_PT_3/IN3 ;
  wire \NlwInverterSignal_U11_U3_counterr<4>_MC.D2_PT_3/IN4 ;
  wire \NlwInverterSignal_U11_U3_counterr<4>_MC.D2_PT_3/IN5 ;
  wire \NlwInverterSignal_U11_U3_counterr<4>_MC.D2_PT_3/IN6 ;
  wire \NlwInverterSignal_U11_U3_counterr<5>_MC.D2_PT_1/IN3 ;
  wire \NlwInverterSignal_U11_U3_counterr<5>_MC.D2_PT_2/IN2 ;
  wire \NlwInverterSignal_U11_U3_counterr<5>_MC.D2_PT_2/IN6 ;
  wire \NlwInverterSignal_U11_U3_counterr<5>_MC.D2_PT_3/IN0 ;
  wire \NlwInverterSignal_U11_U3_counterr<5>_MC.D2_PT_3/IN1 ;
  wire \NlwInverterSignal_U11_U3_counterr<5>_MC.D2_PT_3/IN3 ;
  wire \NlwInverterSignal_U11_U3_counterr<5>_MC.D2_PT_3/IN4 ;
  wire \NlwInverterSignal_U11_U3_counterr<5>_MC.D2_PT_3/IN5 ;
  wire \NlwInverterSignal_U11_U3_counterr<5>_MC.D2_PT_3/IN6 ;
  wire \NlwInverterSignal_U11_U3_counterr<5>_MC.D2_PT_3/IN7 ;
  wire \NlwInverterSignal_DCOR0THRESLOWr_MC.D1/IN1 ;
  wire \NlwInverterSignal_DCOR0THRESLOWr_MC.D1/IN2 ;
  wire \NlwInverterSignal_DCOR0THRESLOWr_MC.D1/IN3 ;
  wire \NlwInverterSignal_DCOR0THRESLOWr_MC.D1/IN4 ;
  wire \NlwInverterSignal_DCOR0THRESLOWr_MC.D1/IN5 ;
  wire \NlwInverterSignal_DCOR0THRESLOWr_MC.D1/IN6 ;
  wire \NlwInverterSignal_DCOR0THRESLOWr_MC.D1/IN8 ;
  wire \NlwInverterSignal_DCOR0THRESLOWr_MC.D1/IN9 ;
  wire \NlwInverterSignal_outDATA<0>\$WA2.UIM_MC.D2_PT_1/IN0 ;
  wire \NlwInverterSignal_outDATA<0>\$WA2.UIM_MC.D2_PT_2/IN0 ;
  wire \NlwInverterSignal_outDATA<0>\$WA2.UIM_MC.D2_PT_2/IN1 ;
  wire \NlwInverterSignal_outDATA<0>\$WA2.UIM_MC.D2_PT_3/IN0 ;
  wire \NlwInverterSignal_outDATA<0>\$WA2.UIM_MC.D2_PT_3/IN1 ;
  wire \NlwInverterSignal_outDATA<0>\$WA2.UIM_MC.D2_PT_3/IN2 ;
  wire \NlwInverterSignal_U1/U4/Latch0r<0>_MC.D2_PT_0/IN2 ;
  wire \NlwInverterSignal_U1/Channel0<0>_MC.D2_PT_0/IN1 ;
  wire \NlwInverterSignal_U1/Channel0<0>_MC.D2_PT_1/IN1 ;
  wire \NlwInverterSignal_U1/Channel0<0>_MC.D2_PT_1/IN4 ;
  wire \NlwInverterSignal_U1/Channel0<0>_MC.D2_PT_1/IN5 ;
  wire \NlwInverterSignal_U1/Channel0<0>_MC.D2_PT_2/IN1 ;
  wire \NlwInverterSignal_U1/Channel0<0>_MC.D2_PT_2/IN2 ;
  wire \NlwInverterSignal_U1/Channel0<0>_MC.D2_PT_2/IN4 ;
  wire \NlwInverterSignal_U1/Zero0_MC.D2_PT_0/IN0 ;
  wire \NlwInverterSignal_U1/Zero0_MC.D2_PT_3/IN1 ;
  wire \NlwInverterSignal_U1/Zero0_MC.D2_PT_3/IN2 ;
  wire \NlwInverterSignal_U1/Zero0_MC.D2_PT_3/IN3 ;
  wire \NlwInverterSignal_U1/Zero0_MC.D2_PT_3/IN7 ;
  wire \NlwInverterSignal_U1/Zero0_MC.D2_PT_4/IN1 ;
  wire \NlwInverterSignal_U1/Zero0_MC.D2_PT_4/IN2 ;
  wire \NlwInverterSignal_U1/Zero0_MC.D2_PT_4/IN3 ;
  wire \NlwInverterSignal_U1/Zero0_MC.D2_PT_4/IN4 ;
  wire \NlwInverterSignal_U1/Zero0_MC.D2_PT_4/IN6 ;
  wire \NlwInverterSignal_DCORIFGw_MC.D1/IN0 ;
  wire \NlwInverterSignal_DCORIFGw_MC.D1/IN3 ;
  wire \NlwInverterSignal_DCORIFGw_MC.D1/IN4 ;
  wire \NlwInverterSignal_DCORIFGw_MC.D1/IN5 ;
  wire \NlwInverterSignal_DCORIFGw_MC.D1/IN6 ;
  wire \NlwInverterSignal_DCORIFGw_MC.D1/IN7 ;
  wire \NlwInverterSignal_DCORIFGw_MC.D1/IN8 ;
  wire \NlwInverterSignal_DCORIFGw_MC.D1/IN9 ;
  wire \NlwInverterSignal_DCORENCCTLw_MC.D1/IN0 ;
  wire \NlwInverterSignal_DCORENCCTLw_MC.D1/IN3 ;
  wire \NlwInverterSignal_DCORENCCTLw_MC.D1/IN4 ;
  wire \NlwInverterSignal_DCORENCCTLw_MC.D1/IN5 ;
  wire \NlwInverterSignal_DCORENCCTLw_MC.D1/IN6 ;
  wire \NlwInverterSignal_DCORENCCTLw_MC.D1/IN7 ;
  wire \NlwInverterSignal_DCORENCCTLw_MC.D1/IN9 ;
  wire \NlwInverterSignal_NET2482_MC.D2_PT_0/IN0 ;
  wire \NlwInverterSignal_NET2482_MC.D2_PT_1/IN2 ;
  wire \NlwInverterSignal_NET2482_MC.D2_PT_2/IN1 ;
  wire \NlwInverterSignal_NET2482_MC.D2_PT_2/IN2 ;
  wire \NlwInverterSignal_NET2482_MC.D2_PT_2/IN3 ;
  wire \NlwInverterSignal_NET2482_MC.D2_PT_2/IN7 ;
  wire \NlwInverterSignal_NET2482_MC.D2_PT_3/IN1 ;
  wire \NlwInverterSignal_NET2482_MC.D2_PT_3/IN2 ;
  wire \NlwInverterSignal_NET2482_MC.D2_PT_3/IN3 ;
  wire \NlwInverterSignal_NET2482_MC.D2_PT_3/IN4 ;
  wire \NlwInverterSignal_NET2482_MC.D2_PT_3/IN6 ;
  wire \NlwInverterSignal_U1/U4/RF0r_MC.D2_PT_1/IN1 ;
  wire \NlwInverterSignal_U1/U4/E0r_MC.D2_PT_1/IN1 ;
  wire \NlwInverterSignal_U1/U1/CurrState_Sreg0_FFD1_MC.D2_PT_0/IN3 ;
  wire \NlwInverterSignal_U1/U1/CurrState_Sreg0_FFD1_MC.D2_PT_1/IN2 ;
  wire \NlwInverterSignal_U1/U1/CurrState_Sreg0_FFD1_MC.D2_PT_1/IN3 ;
  wire \NlwInverterSignal_U1/U1/CurrState_Sreg0_FFD1_MC.D2_PT_2/IN1 ;
  wire \NlwInverterSignal_U1/U1/CurrState_Sreg0_FFD1_MC.D2_PT_2/IN2 ;
  wire \NlwInverterSignal_U1/U1/CurrState_Sreg0_FFD1_MC.D2_PT_2/IN3 ;
  wire \NlwInverterSignal_U1/U1/CurrState_Sreg0_FFD1_MC.D2_PT_2/IN4 ;
  wire \NlwInverterSignal_U1/U1/CurrState_Sreg0_FFD3_MC.D2_PT_0/IN1 ;
  wire \NlwInverterSignal_U1/U1/CurrState_Sreg0_FFD3_MC.D2_PT_0/IN3 ;
  wire \NlwInverterSignal_U1/U1/CurrState_Sreg0_FFD3_MC.D2_PT_0/IN4 ;
  wire \NlwInverterSignal_U1/U1/CurrState_Sreg0_FFD3_MC.D2_PT_1/IN3 ;
  wire \NlwInverterSignal_U1/U1/CurrState_Sreg0_FFD3_MC.D2_PT_1/IN4 ;
  wire \NlwInverterSignal_U1/U1/CurrState_Sreg0_FFD3_MC.D2_PT_2/IN3 ;
  wire \NlwInverterSignal_U1/U1/CurrState_Sreg0_FFD3_MC.D2_PT_2/IN5 ;
  wire \NlwInverterSignal_U1/U1/CurrState_Sreg0_FFD3_MC.D2_PT_3/IN1 ;
  wire \NlwInverterSignal_U1/U1/CurrState_Sreg0_FFD3_MC.D2_PT_3/IN3 ;
  wire \NlwInverterSignal_U1/U1/CurrState_Sreg0_FFD2_MC.D2_PT_0/IN4 ;
  wire \NlwInverterSignal_U1/U1/CurrState_Sreg0_FFD2_MC.D2_PT_1/IN2 ;
  wire \NlwInverterSignal_U1/U1/CurrState_Sreg0_FFD2_MC.D2_PT_1/IN4 ;
  wire \NlwInverterSignal_U1/U1/CurrState_Sreg0_FFD2_MC.D2_PT_1/IN5 ;
  wire \NlwInverterSignal_U1/U1/CurrState_Sreg0_FFD2_MC.D2_PT_2/IN2 ;
  wire \NlwInverterSignal_U1/U1/CurrState_Sreg0_FFD2_MC.D2_PT_2/IN3 ;
  wire \NlwInverterSignal_U1/U1/CurrState_Sreg0_FFD2_MC.D2_PT_3/IN3 ;
  wire \NlwInverterSignal_U1/U1/CurrState_Sreg0_FFD2_MC.D2_PT_3/IN5 ;
  wire \NlwInverterSignal_U1/U1/CurrState_Sreg0_FFD2_MC.D2_PT_4/IN1 ;
  wire \NlwInverterSignal_U1/U1/CurrState_Sreg0_FFD2_MC.D2_PT_4/IN4 ;
  wire \NlwInverterSignal_U1/U1/CurrState_Sreg0_FFD2_MC.D2_PT_4/IN5 ;
  wire \NlwInverterSignal_U1/U1/CurrState_Sreg0_FFD2_MC.D2_PT_5/IN1 ;
  wire \NlwInverterSignal_U1/U1/CurrState_Sreg0_FFD2_MC.D2_PT_5/IN3 ;
  wire \NlwInverterSignal_U1/U1/CurrState_Sreg0_FFD2_MC.D2_PT_6/IN1 ;
  wire \NlwInverterSignal_U1/U1/CurrState_Sreg0_FFD2_MC.D2_PT_6/IN2 ;
  wire \NlwInverterSignal_U1/U1/CurrState_Sreg0_FFD2_MC.D2_PT_6/IN4 ;
  wire \NlwInverterSignal_U1/U1/CurrState_Sreg0_FFD2_MC.D2_PT_7/IN1 ;
  wire \NlwInverterSignal_U1/U1/CurrState_Sreg0_FFD2_MC.D2_PT_7/IN2 ;
  wire \NlwInverterSignal_U1/U1/CurrState_Sreg0_FFD2_MC.D2_PT_7/IN3 ;
  wire \NlwInverterSignal_U1/U1/CurrState_Sreg0_FFD2_MC.D2_PT_7/IN5 ;
  wire \NlwInverterSignal_U1/U1/CurrState_Sreg0_FFD4_MC.D1/IN1 ;
  wire \NlwInverterSignal_U1/U1/CurrState_Sreg0_FFD4_MC.D1/IN3 ;
  wire \NlwInverterSignal_U1/U1/CurrState_Sreg0_FFD4_MC.D1/IN4 ;
  wire \NlwInverterSignal_U1/U1/CurrState_Sreg0_FFD4_MC.D1/IN5 ;
  wire \NlwInverterSignal_U1/U1/CurrState_Sreg0_FFD4_MC.D1/IN6 ;
  wire \NlwInverterSignal_N_PZ_982_MC.D1/IN1 ;
  wire \NlwInverterSignal_N_PZ_1018_MC.D2_PT_0/IN0 ;
  wire \NlwInverterSignal_N_PZ_1018_MC.D2_PT_0/IN1 ;
  wire \NlwInverterSignal_N_PZ_1018_MC.D2_PT_0/IN2 ;
  wire \NlwInverterSignal_N_PZ_1018_MC.D2_PT_0/IN4 ;
  wire \NlwInverterSignal_N_PZ_1018_MC.D2_PT_1/IN0 ;
  wire \NlwInverterSignal_N_PZ_1018_MC.D2_PT_1/IN1 ;
  wire \NlwInverterSignal_N_PZ_1018_MC.D2_PT_1/IN2 ;
  wire \NlwInverterSignal_N_PZ_1018_MC.D2_PT_1/IN3 ;
  wire \NlwInverterSignal_N_PZ_1018_MC.D2_PT_1/IN5 ;
  wire \NlwInverterSignal_NET2501_MC.D2_PT_1/IN3 ;
  wire \NlwInverterSignal_U1/U4/LatchEdge0r_MC.D2_PT_1/IN1 ;
  wire \NlwInverterSignal_U1/U4/Latch0r<8>_MC.D2_PT_0/IN2 ;
  wire \NlwInverterSignal_U1/Channel0<8>_MC.D1/IN1 ;
  wire \NlwInverterSignal_U1/Channel0<8>_MC.D2_PT_0/IN0 ;
  wire \NlwInverterSignal_U1/Channel0<8>_MC.D2_PT_1/IN0 ;
  wire \NlwInverterSignal_U1/Channel0<8>_MC.D2_PT_1/IN2 ;
  wire \NlwInverterSignal_U1/Channel0<8>_MC.D2_PT_2/IN0 ;
  wire \NlwInverterSignal_U1/Channel0<8>_MC.D2_PT_3/IN0 ;
  wire \NlwInverterSignal_U1/Channel0<8>_MC.D2_PT_3/IN4 ;
  wire \NlwInverterSignal_U1/Channel0<8>_MC.D2_PT_4/IN1 ;
  wire \NlwInverterSignal_U1/Channel0<8>_MC.D2_PT_4/IN2 ;
  wire \NlwInverterSignal_U1/Channel0<8>_MC.D2_PT_4/IN4 ;
  wire \NlwInverterSignal_U1/Channel0<8>_MC.D2_PT_4/IN6 ;
  wire \NlwInverterSignal_U1/Channel0<8>_MC.D2_PT_4/IN7 ;
  wire \NlwInverterSignal_U1/Channel0<8>_MC.D2_PT_5/IN1 ;
  wire \NlwInverterSignal_U1/Channel0<8>_MC.D2_PT_5/IN3 ;
  wire \NlwInverterSignal_U1/Channel0<8>_MC.D2_PT_5/IN6 ;
  wire \NlwInverterSignal_U1/Channel0<8>_MC.D2_PT_5/IN8 ;
  wire \NlwInverterSignal_U1/U2/location_Maddsub__n0000__n0075<0>_MC.D2_PT_0/IN2 ;
  wire \NlwInverterSignal_U1/U2/location_Maddsub__n0000__n0075<0>_MC.D2_PT_1/IN0 ;
  wire \NlwInverterSignal_U1/U2/location_Maddsub__n0000__n0075<0>_MC.D2_PT_1/IN1 ;
  wire \NlwInverterSignal_U1/U2/location_Maddsub__n0000__n0075<0>_MC.D2_PT_1/IN3 ;
  wire \NlwInverterSignal_U1/U2/location_Maddsub__n0000__n0075<0>_MC.D2_PT_1/IN4 ;
  wire \NlwInverterSignal_U1/U2/location_Maddsub__n0000__n0075<0>_MC.D2_PT_1/IN5 ;
  wire \NlwInverterSignal_N_PZ_997_MC.D2_PT_0/IN0 ;
  wire \NlwInverterSignal_N_PZ_997_MC.D2_PT_0/IN2 ;
  wire \NlwInverterSignal_N_PZ_997_MC.D2_PT_1/IN0 ;
  wire \NlwInverterSignal_N_PZ_997_MC.D2_PT_1/IN2 ;
  wire \NlwInverterSignal_U1/NET3721_MC.D2_PT_1/IN1 ;
  wire \NlwInverterSignal_U1/Channel0<5>_MC.D2_PT_0/IN0 ;
  wire \NlwInverterSignal_U1/Channel0<5>_MC.D2_PT_1/IN1 ;
  wire \NlwInverterSignal_U1/U2/location_Maddsub__n0000__n0067<0>_MC.D2_PT_1/IN0 ;
  wire \NlwInverterSignal_U1/U2/location_Maddsub__n0000__n0067<0>_MC.D2_PT_1/IN1 ;
  wire \NlwInverterSignal_U1/U2/location_Maddsub__n0000__n0067<0>_MC.D2_PT_1/IN2 ;
  wire \NlwInverterSignal_U1/U2/location_Maddsub__n0000__n0067<0>_MC.D2_PT_1/IN3 ;
  wire \NlwInverterSignal_U1/U2/location_Maddsub__n0000__n0067<0>_MC.D2_PT_1/IN4 ;
  wire \NlwInverterSignal_U1/U2/location_Maddsub__n0000__n0067<0>_MC.D2_PT_1/IN5 ;
  wire \NlwInverterSignal_U1/Channel0<1>_MC.D2_PT_1/IN0 ;
  wire \NlwInverterSignal_U1/Channel0<1>_MC.D2_PT_2/IN0 ;
  wire \NlwInverterSignal_N_PZ_1021_MC.D2_PT_0/IN1 ;
  wire \NlwInverterSignal_N_PZ_1021_MC.D2_PT_0/IN4 ;
  wire \NlwInverterSignal_N_PZ_1021_MC.D2_PT_0/IN5 ;
  wire \NlwInverterSignal_N_PZ_1021_MC.D2_PT_0/IN6 ;
  wire \NlwInverterSignal_N_PZ_1021_MC.D2_PT_1/IN1 ;
  wire \NlwInverterSignal_N_PZ_1021_MC.D2_PT_1/IN2 ;
  wire \NlwInverterSignal_N_PZ_1021_MC.D2_PT_1/IN4 ;
  wire \NlwInverterSignal_N_PZ_1024_MC.D2_PT_0/IN1 ;
  wire \NlwInverterSignal_N_PZ_1024_MC.D2_PT_0/IN4 ;
  wire \NlwInverterSignal_N_PZ_1024_MC.D2_PT_0/IN5 ;
  wire \NlwInverterSignal_N_PZ_1024_MC.D2_PT_1/IN1 ;
  wire \NlwInverterSignal_N_PZ_1024_MC.D2_PT_1/IN2 ;
  wire \NlwInverterSignal_N_PZ_1024_MC.D2_PT_1/IN4 ;
  wire \NlwInverterSignal_N_PZ_1024_MC.D2_PT_1/IN6 ;
  wire \NlwInverterSignal_U1/Channel0<2>_MC.D2_PT_0/IN0 ;
  wire \NlwInverterSignal_U1/Channel0<2>_MC.D2_PT_2/IN0 ;
  wire \NlwInverterSignal_U1/Channel0<2>_MC.D2_PT_2/IN2 ;
  wire \NlwInverterSignal_U1/Channel0<3>_MC.D2_PT_0/IN0 ;
  wire \NlwInverterSignal_U1/Channel0<3>_MC.D2_PT_2/IN0 ;
  wire \NlwInverterSignal_U1/Channel0<3>_MC.D2_PT_2/IN2 ;
  wire \NlwInverterSignal_U1/Channel0<3>_MC.D2_PT_2/IN3 ;
  wire \NlwInverterSignal_U1/Channel0<4>_MC.D1/IN1 ;
  wire \NlwInverterSignal_U1/Channel0<4>_MC.D2_PT_0/IN0 ;
  wire \NlwInverterSignal_U1/Channel0<4>_MC.D2_PT_0/IN1 ;
  wire \NlwInverterSignal_U1/Channel0<4>_MC.D2_PT_1/IN0 ;
  wire \NlwInverterSignal_U1/Channel0<4>_MC.D2_PT_2/IN2 ;
  wire \NlwInverterSignal_U1/Channel0<4>_MC.D2_PT_3/IN6 ;
  wire \NlwInverterSignal_U1/Channel0<4>_MC.D2_PT_4/IN0 ;
  wire \NlwInverterSignal_U1/Channel0<4>_MC.D2_PT_4/IN1 ;
  wire \NlwInverterSignal_U1/Channel0<4>_MC.D2_PT_4/IN3 ;
  wire \NlwInverterSignal_U1/Channel0<4>_MC.D2_PT_4/IN4 ;
  wire \NlwInverterSignal_U1/Channel0<4>_MC.D2_PT_4/IN5 ;
  wire \NlwInverterSignal_U1/Channel0<4>_MC.D2_PT_4/IN6 ;
  wire \NlwInverterSignal_U1/Channel0<4>_MC.D2_PT_5/IN2 ;
  wire \NlwInverterSignal_U1/Channel0<4>_MC.D2_PT_5/IN4 ;
  wire \NlwInverterSignal_U1/Channel0<4>_MC.D2_PT_5/IN7 ;
  wire \NlwInverterSignal_U1/Channel0<6>_MC.D2_PT_0/IN0 ;
  wire \NlwInverterSignal_U1/Channel0<6>_MC.D2_PT_1/IN2 ;
  wire \NlwInverterSignal_U1/Channel0<6>_MC.D2_PT_2/IN1 ;
  wire \NlwInverterSignal_U1/Channel0<7>_MC.D2_PT_0/IN0 ;
  wire \NlwInverterSignal_U1/Channel0<7>_MC.D2_PT_1/IN2 ;
  wire \NlwInverterSignal_U1/Channel0<7>_MC.D2_PT_2/IN1 ;
  wire \NlwInverterSignal_U1/Channel0<7>_MC.D2_PT_2/IN3 ;
  wire \NlwInverterSignal_DCOR0THRESHIGHr_MC.D1/IN1 ;
  wire \NlwInverterSignal_DCOR0THRESHIGHr_MC.D1/IN3 ;
  wire \NlwInverterSignal_DCOR0THRESHIGHr_MC.D1/IN4 ;
  wire \NlwInverterSignal_DCOR0THRESHIGHr_MC.D1/IN5 ;
  wire \NlwInverterSignal_DCOR0THRESHIGHr_MC.D1/IN6 ;
  wire \NlwInverterSignal_DCOR0THRESHIGHr_MC.D1/IN8 ;
  wire \NlwInverterSignal_DCOR0THRESHIGHr_MC.D1/IN9 ;
  wire \NlwInverterSignal_U1/U4/Latch1r<0>_MC.D2_PT_0/IN2 ;
  wire \NlwInverterSignal_U1/Channel1<0>_MC.D2_PT_0/IN1 ;
  wire \NlwInverterSignal_U1/Channel1<0>_MC.D2_PT_1/IN1 ;
  wire \NlwInverterSignal_U1/Channel1<0>_MC.D2_PT_1/IN3 ;
  wire \NlwInverterSignal_N_PZ_983_MC.D1/IN1 ;
  wire \NlwInverterSignal_U1/Zero1_MC.D2_PT_0/IN0 ;
  wire \NlwInverterSignal_U1/Zero1_MC.D2_PT_3/IN1 ;
  wire \NlwInverterSignal_U1/Zero1_MC.D2_PT_3/IN2 ;
  wire \NlwInverterSignal_U1/Zero1_MC.D2_PT_3/IN3 ;
  wire \NlwInverterSignal_U1/Zero1_MC.D2_PT_3/IN7 ;
  wire \NlwInverterSignal_U1/Zero1_MC.D2_PT_4/IN1 ;
  wire \NlwInverterSignal_U1/Zero1_MC.D2_PT_4/IN2 ;
  wire \NlwInverterSignal_U1/Zero1_MC.D2_PT_4/IN3 ;
  wire \NlwInverterSignal_U1/Zero1_MC.D2_PT_4/IN4 ;
  wire \NlwInverterSignal_U1/Zero1_MC.D2_PT_4/IN6 ;
  wire \NlwInverterSignal_NET2493_MC.D2_PT_0/IN0 ;
  wire \NlwInverterSignal_NET2493_MC.D2_PT_1/IN2 ;
  wire \NlwInverterSignal_NET2493_MC.D2_PT_2/IN1 ;
  wire \NlwInverterSignal_NET2493_MC.D2_PT_2/IN2 ;
  wire \NlwInverterSignal_NET2493_MC.D2_PT_2/IN3 ;
  wire \NlwInverterSignal_NET2493_MC.D2_PT_2/IN7 ;
  wire \NlwInverterSignal_NET2493_MC.D2_PT_3/IN1 ;
  wire \NlwInverterSignal_NET2493_MC.D2_PT_3/IN2 ;
  wire \NlwInverterSignal_NET2493_MC.D2_PT_3/IN3 ;
  wire \NlwInverterSignal_NET2493_MC.D2_PT_3/IN4 ;
  wire \NlwInverterSignal_NET2493_MC.D2_PT_3/IN6 ;
  wire \NlwInverterSignal_U1/U4/RF1r_MC.D2_PT_1/IN1 ;
  wire \NlwInverterSignal_U1/U4/E1r_MC.D2_PT_1/IN1 ;
  wire \NlwInverterSignal_U1/U6/CurrState_Sreg0_FFD3_MC.D2_PT_0/IN3 ;
  wire \NlwInverterSignal_U1/U6/CurrState_Sreg0_FFD3_MC.D2_PT_0/IN4 ;
  wire \NlwInverterSignal_U1/U6/CurrState_Sreg0_FFD3_MC.D2_PT_1/IN2 ;
  wire \NlwInverterSignal_U1/U6/CurrState_Sreg0_FFD3_MC.D2_PT_1/IN3 ;
  wire \NlwInverterSignal_U1/U6/CurrState_Sreg0_FFD3_MC.D2_PT_1/IN4 ;
  wire \NlwInverterSignal_U1/U6/CurrState_Sreg0_FFD3_MC.D2_PT_2/IN3 ;
  wire \NlwInverterSignal_U1/U6/CurrState_Sreg0_FFD3_MC.D2_PT_2/IN5 ;
  wire \NlwInverterSignal_U1/U6/CurrState_Sreg0_FFD3_MC.D2_PT_3/IN3 ;
  wire \NlwInverterSignal_U1/U6/CurrState_Sreg0_FFD3_MC.D2_PT_3/IN4 ;
  wire \NlwInverterSignal_U1/U6/CurrState_Sreg0_FFD1_MC.D2_PT_0/IN2 ;
  wire \NlwInverterSignal_U1/U6/CurrState_Sreg0_FFD1_MC.D2_PT_1/IN1 ;
  wire \NlwInverterSignal_U1/U6/CurrState_Sreg0_FFD1_MC.D2_PT_1/IN3 ;
  wire \NlwInverterSignal_U1/U6/CurrState_Sreg0_FFD1_MC.D2_PT_2/IN1 ;
  wire \NlwInverterSignal_U1/U6/CurrState_Sreg0_FFD1_MC.D2_PT_2/IN2 ;
  wire \NlwInverterSignal_U1/U6/CurrState_Sreg0_FFD1_MC.D2_PT_2/IN3 ;
  wire \NlwInverterSignal_U1/U6/CurrState_Sreg0_FFD1_MC.D2_PT_2/IN4 ;
  wire \NlwInverterSignal_U1/U6/CurrState_Sreg0_FFD4_MC.D1/IN2 ;
  wire \NlwInverterSignal_U1/U6/CurrState_Sreg0_FFD4_MC.D1/IN3 ;
  wire \NlwInverterSignal_U1/U6/CurrState_Sreg0_FFD4_MC.D1/IN4 ;
  wire \NlwInverterSignal_U1/U6/CurrState_Sreg0_FFD4_MC.D1/IN5 ;
  wire \NlwInverterSignal_U1/U6/CurrState_Sreg0_FFD4_MC.D1/IN6 ;
  wire \NlwInverterSignal_U1/U6/CurrState_Sreg0_FFD2_MC.D2_PT_0/IN3 ;
  wire \NlwInverterSignal_U1/U6/CurrState_Sreg0_FFD2_MC.D2_PT_1/IN3 ;
  wire \NlwInverterSignal_U1/U6/CurrState_Sreg0_FFD2_MC.D2_PT_1/IN4 ;
  wire \NlwInverterSignal_U1/U6/CurrState_Sreg0_FFD2_MC.D2_PT_1/IN5 ;
  wire \NlwInverterSignal_U1/U6/CurrState_Sreg0_FFD2_MC.D2_PT_2/IN3 ;
  wire \NlwInverterSignal_U1/U6/CurrState_Sreg0_FFD2_MC.D2_PT_2/IN4 ;
  wire \NlwInverterSignal_U1/U6/CurrState_Sreg0_FFD2_MC.D2_PT_3/IN1 ;
  wire \NlwInverterSignal_U1/U6/CurrState_Sreg0_FFD2_MC.D2_PT_3/IN3 ;
  wire \NlwInverterSignal_U1/U6/CurrState_Sreg0_FFD2_MC.D2_PT_3/IN5 ;
  wire \NlwInverterSignal_U1/U6/CurrState_Sreg0_FFD2_MC.D2_PT_4/IN1 ;
  wire \NlwInverterSignal_U1/U6/CurrState_Sreg0_FFD2_MC.D2_PT_4/IN3 ;
  wire \NlwInverterSignal_U1/U6/CurrState_Sreg0_FFD2_MC.D2_PT_4/IN4 ;
  wire \NlwInverterSignal_U1/U6/CurrState_Sreg0_FFD2_MC.D2_PT_5/IN1 ;
  wire \NlwInverterSignal_U1/U6/CurrState_Sreg0_FFD2_MC.D2_PT_5/IN3 ;
  wire \NlwInverterSignal_U1/U6/CurrState_Sreg0_FFD2_MC.D2_PT_6/IN1 ;
  wire \NlwInverterSignal_U1/U6/CurrState_Sreg0_FFD2_MC.D2_PT_6/IN3 ;
  wire \NlwInverterSignal_U1/U6/CurrState_Sreg0_FFD2_MC.D2_PT_6/IN4 ;
  wire \NlwInverterSignal_U1/U6/CurrState_Sreg0_FFD2_MC.D2_PT_6/IN5 ;
  wire \NlwInverterSignal_U1/U6/CurrState_Sreg0_FFD2_MC.D2_PT_7/IN3 ;
  wire \NlwInverterSignal_U1/U6/CurrState_Sreg0_FFD2_MC.D2_PT_7/IN5 ;
  wire \NlwInverterSignal_N_PZ_1154_MC.D2_PT_0/IN1 ;
  wire \NlwInverterSignal_N_PZ_1154_MC.D2_PT_1/IN0 ;
  wire \NlwInverterSignal_N_PZ_1019_MC.D2_PT_0/IN0 ;
  wire \NlwInverterSignal_N_PZ_1019_MC.D2_PT_0/IN1 ;
  wire \NlwInverterSignal_N_PZ_1019_MC.D2_PT_0/IN2 ;
  wire \NlwInverterSignal_N_PZ_1019_MC.D2_PT_0/IN4 ;
  wire \NlwInverterSignal_N_PZ_1019_MC.D2_PT_1/IN0 ;
  wire \NlwInverterSignal_N_PZ_1019_MC.D2_PT_1/IN1 ;
  wire \NlwInverterSignal_N_PZ_1019_MC.D2_PT_1/IN2 ;
  wire \NlwInverterSignal_N_PZ_1019_MC.D2_PT_1/IN3 ;
  wire \NlwInverterSignal_N_PZ_1019_MC.D2_PT_1/IN5 ;
  wire \NlwInverterSignal_NET2512_MC.D2_PT_1/IN3 ;
  wire \NlwInverterSignal_U1/U4/LatchEdge1r_MC.D2_PT_1/IN1 ;
  wire \NlwInverterSignal_DCOR1THRESLOWr_MC.D1/IN1 ;
  wire \NlwInverterSignal_DCOR1THRESLOWr_MC.D1/IN2 ;
  wire \NlwInverterSignal_DCOR1THRESLOWr_MC.D1/IN3 ;
  wire \NlwInverterSignal_DCOR1THRESLOWr_MC.D1/IN4 ;
  wire \NlwInverterSignal_DCOR1THRESLOWr_MC.D1/IN5 ;
  wire \NlwInverterSignal_DCOR1THRESLOWr_MC.D1/IN6 ;
  wire \NlwInverterSignal_DCOR1THRESLOWr_MC.D1/IN9 ;
  wire \NlwInverterSignal_U1/U4/Latch1r<8>_MC.D2_PT_0/IN2 ;
  wire \NlwInverterSignal_U1/Channel1<8>_MC.D2_PT_0/IN0 ;
  wire \NlwInverterSignal_U1/Channel1<8>_MC.D2_PT_1/IN1 ;
  wire \NlwInverterSignal_U1/Channel1<8>_MC.D2_PT_1/IN3 ;
  wire \NlwInverterSignal_U1/Channel1<8>_MC.D2_PT_1/IN5 ;
  wire \NlwInverterSignal_U1/Channel1<8>_MC.D2_PT_2/IN1 ;
  wire \NlwInverterSignal_U1/Channel1<8>_MC.D2_PT_2/IN4 ;
  wire \NlwInverterSignal_U1/Channel1<8>_MC.D2_PT_3/IN1 ;
  wire \NlwInverterSignal_U1/Channel1<8>_MC.D2_PT_3/IN4 ;
  wire \NlwInverterSignal_U1/Channel1<8>_MC.D2_PT_3/IN5 ;
  wire \NlwInverterSignal_U1/Channel1<8>_MC.D2_PT_4/IN1 ;
  wire \NlwInverterSignal_U1/Channel1<8>_MC.D2_PT_4/IN4 ;
  wire \NlwInverterSignal_U1/Channel1<8>_MC.D2_PT_5/IN1 ;
  wire \NlwInverterSignal_U1/Channel1<8>_MC.D2_PT_5/IN3 ;
  wire \NlwInverterSignal_U1/Channel1<8>_MC.D2_PT_5/IN5 ;
  wire \NlwInverterSignal_U1/Channel1<8>_MC.D2_PT_5/IN6 ;
  wire \NlwInverterSignal_U1/Channel1<8>_MC.D2_PT_6/IN1 ;
  wire \NlwInverterSignal_U1/Channel1<8>_MC.D2_PT_6/IN4 ;
  wire \NlwInverterSignal_U1/Channel1<8>_MC.D2_PT_6/IN5 ;
  wire \NlwInverterSignal_U1/Channel1<8>_MC.D2_PT_6/IN7 ;
  wire \NlwInverterSignal_U1/Channel1<8>_MC.D2_PT_6/IN8 ;
  wire \NlwInverterSignal_U1/Channel1<8>_MC.D2_PT_7/IN1 ;
  wire \NlwInverterSignal_U1/Channel1<8>_MC.D2_PT_7/IN3 ;
  wire \NlwInverterSignal_U1/Channel1<8>_MC.D2_PT_7/IN5 ;
  wire \NlwInverterSignal_U1/Channel1<8>_MC.D2_PT_7/IN8 ;
  wire \NlwInverterSignal_U1/Channel1<5>_MC.D2_PT_0/IN0 ;
  wire \NlwInverterSignal_U1/Channel1<5>_MC.D2_PT_1/IN1 ;
  wire \NlwInverterSignal_U1/Channel1<5>_MC.D2_PT_1/IN3 ;
  wire \NlwInverterSignal_U1/Channel1<5>_MC.D2_PT_1/IN5 ;
  wire \NlwInverterSignal_U1/Channel1<5>_MC.D2_PT_2/IN1 ;
  wire \NlwInverterSignal_U1/Channel1<5>_MC.D2_PT_2/IN3 ;
  wire \NlwInverterSignal_U1/Channel1<5>_MC.D2_PT_2/IN5 ;
  wire \NlwInverterSignal_U1/U5/location_Maddsub__n0000__n0067<0>_MC.D2_PT_1/IN0 ;
  wire \NlwInverterSignal_U1/U5/location_Maddsub__n0000__n0067<0>_MC.D2_PT_1/IN1 ;
  wire \NlwInverterSignal_U1/U5/location_Maddsub__n0000__n0067<0>_MC.D2_PT_1/IN2 ;
  wire \NlwInverterSignal_U1/U5/location_Maddsub__n0000__n0067<0>_MC.D2_PT_1/IN3 ;
  wire \NlwInverterSignal_U1/U5/location_Maddsub__n0000__n0067<0>_MC.D2_PT_1/IN4 ;
  wire \NlwInverterSignal_U1/U5/location_Maddsub__n0000__n0067<0>_MC.D2_PT_1/IN5 ;
  wire \NlwInverterSignal_N_PZ_998_MC.D2_PT_0/IN1 ;
  wire \NlwInverterSignal_N_PZ_998_MC.D2_PT_0/IN2 ;
  wire \NlwInverterSignal_N_PZ_998_MC.D2_PT_1/IN1 ;
  wire \NlwInverterSignal_N_PZ_998_MC.D2_PT_1/IN2 ;
  wire \NlwInverterSignal_U1/NET3720_MC.D2_PT_1/IN1 ;
  wire \NlwInverterSignal_U1/Channel1<1>_MC.D2_PT_0/IN0 ;
  wire \NlwInverterSignal_U1/Channel1<1>_MC.D2_PT_1/IN2 ;
  wire \NlwInverterSignal_U1/Channel1<1>_MC.D2_PT_1/IN4 ;
  wire \NlwInverterSignal_U1/Channel1<1>_MC.D2_PT_2/IN1 ;
  wire \NlwInverterSignal_U1/Channel1<1>_MC.D2_PT_2/IN2 ;
  wire \NlwInverterSignal_U1/Channel1<1>_MC.D2_PT_2/IN4 ;
  wire \NlwInverterSignal_U1/Channel1<1>_MC.D2_PT_2/IN6 ;
  wire \NlwInverterSignal_N_PZ_975_MC.D2_PT_0/IN1 ;
  wire \NlwInverterSignal_N_PZ_975_MC.D2_PT_0/IN2 ;
  wire \NlwInverterSignal_N_PZ_975_MC.D2_PT_1/IN0 ;
  wire \NlwInverterSignal_U1/Channel1<2>_MC.D2_PT_0/IN0 ;
  wire \NlwInverterSignal_U1/Channel1<2>_MC.D2_PT_1/IN2 ;
  wire \NlwInverterSignal_U1/Channel1<2>_MC.D2_PT_1/IN4 ;
  wire \NlwInverterSignal_U1/Channel1<2>_MC.D2_PT_2/IN1 ;
  wire \NlwInverterSignal_U1/Channel1<2>_MC.D2_PT_2/IN2 ;
  wire \NlwInverterSignal_U1/Channel1<2>_MC.D2_PT_2/IN4 ;
  wire \NlwInverterSignal_U1/Channel1<2>_MC.D2_PT_2/IN6 ;
  wire \NlwInverterSignal_U1/Channel1<2>_MC.D2_PT_2/IN7 ;
  wire \NlwInverterSignal_U1/Channel1<3>_MC.D2_PT_0/IN0 ;
  wire \NlwInverterSignal_U1/Channel1<3>_MC.D2_PT_1/IN2 ;
  wire \NlwInverterSignal_U1/Channel1<3>_MC.D2_PT_1/IN4 ;
  wire \NlwInverterSignal_U1/Channel1<3>_MC.D2_PT_2/IN1 ;
  wire \NlwInverterSignal_U1/Channel1<3>_MC.D2_PT_2/IN2 ;
  wire \NlwInverterSignal_U1/Channel1<3>_MC.D2_PT_2/IN4 ;
  wire \NlwInverterSignal_U1/Channel1<3>_MC.D2_PT_2/IN6 ;
  wire \NlwInverterSignal_U1/Channel1<3>_MC.D2_PT_2/IN7 ;
  wire \NlwInverterSignal_U1/Channel1<3>_MC.D2_PT_2/IN8 ;
  wire \NlwInverterSignal_U1/Channel1<4>_MC.D2_PT_0/IN0 ;
  wire \NlwInverterSignal_U1/Channel1<4>_MC.D2_PT_1/IN0 ;
  wire \NlwInverterSignal_U1/Channel1<4>_MC.D2_PT_1/IN2 ;
  wire \NlwInverterSignal_U1/Channel1<4>_MC.D2_PT_1/IN4 ;
  wire \NlwInverterSignal_U1/Channel1<4>_MC.D2_PT_2/IN1 ;
  wire \NlwInverterSignal_U1/Channel1<4>_MC.D2_PT_2/IN3 ;
  wire \NlwInverterSignal_U1/Channel1<4>_MC.D2_PT_2/IN4 ;
  wire \NlwInverterSignal_U1/Channel1<4>_MC.D2_PT_3/IN1 ;
  wire \NlwInverterSignal_U1/Channel1<4>_MC.D2_PT_3/IN3 ;
  wire \NlwInverterSignal_U1/Channel1<4>_MC.D2_PT_3/IN4 ;
  wire \NlwInverterSignal_U1/Channel1<4>_MC.D2_PT_4/IN1 ;
  wire \NlwInverterSignal_U1/Channel1<4>_MC.D2_PT_4/IN3 ;
  wire \NlwInverterSignal_U1/Channel1<4>_MC.D2_PT_5/IN1 ;
  wire \NlwInverterSignal_U1/Channel1<4>_MC.D2_PT_5/IN3 ;
  wire \NlwInverterSignal_U1/Channel1<4>_MC.D2_PT_5/IN5 ;
  wire \NlwInverterSignal_U1/Channel1<4>_MC.D2_PT_5/IN7 ;
  wire \NlwInverterSignal_U1/Channel1<4>_MC.D2_PT_6/IN0 ;
  wire \NlwInverterSignal_U1/Channel1<4>_MC.D2_PT_6/IN2 ;
  wire \NlwInverterSignal_U1/Channel1<4>_MC.D2_PT_6/IN4 ;
  wire \NlwInverterSignal_U1/Channel1<4>_MC.D2_PT_6/IN5 ;
  wire \NlwInverterSignal_U1/Channel1<4>_MC.D2_PT_6/IN6 ;
  wire \NlwInverterSignal_U1/Channel1<4>_MC.D2_PT_6/IN7 ;
  wire \NlwInverterSignal_U1/Channel1<4>_MC.D2_PT_7/IN2 ;
  wire \NlwInverterSignal_U1/Channel1<4>_MC.D2_PT_7/IN4 ;
  wire \NlwInverterSignal_U1/Channel1<4>_MC.D2_PT_7/IN10 ;
  wire \NlwInverterSignal_U1/Channel1<6>_MC.D2_PT_0/IN0 ;
  wire \NlwInverterSignal_U1/Channel1<6>_MC.D2_PT_1/IN1 ;
  wire \NlwInverterSignal_U1/Channel1<6>_MC.D2_PT_1/IN3 ;
  wire \NlwInverterSignal_U1/Channel1<6>_MC.D2_PT_1/IN6 ;
  wire \NlwInverterSignal_U1/Channel1<6>_MC.D2_PT_2/IN1 ;
  wire \NlwInverterSignal_U1/Channel1<6>_MC.D2_PT_2/IN3 ;
  wire \NlwInverterSignal_U1/Channel1<6>_MC.D2_PT_2/IN5 ;
  wire \NlwInverterSignal_U1/Channel1<6>_MC.D2_PT_2/IN6 ;
  wire \NlwInverterSignal_U1/Channel1<7>_MC.D2_PT_0/IN0 ;
  wire \NlwInverterSignal_U1/Channel1<7>_MC.D2_PT_1/IN1 ;
  wire \NlwInverterSignal_U1/Channel1<7>_MC.D2_PT_1/IN3 ;
  wire \NlwInverterSignal_U1/Channel1<7>_MC.D2_PT_1/IN6 ;
  wire \NlwInverterSignal_U1/Channel1<7>_MC.D2_PT_2/IN1 ;
  wire \NlwInverterSignal_U1/Channel1<7>_MC.D2_PT_2/IN3 ;
  wire \NlwInverterSignal_U1/Channel1<7>_MC.D2_PT_2/IN5 ;
  wire \NlwInverterSignal_U1/Channel1<7>_MC.D2_PT_2/IN6 ;
  wire \NlwInverterSignal_U1/Channel1<7>_MC.D2_PT_2/IN8 ;
  wire \NlwInverterSignal_U1/U5/location_Maddsub__n0000__n0075<0>_MC.D2_PT_0/IN2 ;
  wire \NlwInverterSignal_U1/U5/location_Maddsub__n0000__n0075<0>_MC.D2_PT_1/IN0 ;
  wire \NlwInverterSignal_U1/U5/location_Maddsub__n0000__n0075<0>_MC.D2_PT_1/IN1 ;
  wire \NlwInverterSignal_U1/U5/location_Maddsub__n0000__n0075<0>_MC.D2_PT_1/IN3 ;
  wire \NlwInverterSignal_U1/U5/location_Maddsub__n0000__n0075<0>_MC.D2_PT_1/IN4 ;
  wire \NlwInverterSignal_U1/U5/location_Maddsub__n0000__n0075<0>_MC.D2_PT_1/IN5 ;
  wire \NlwInverterSignal_DCORCONFIGr_MC.D1/IN1 ;
  wire \NlwInverterSignal_DCORCONFIGr_MC.D1/IN3 ;
  wire \NlwInverterSignal_DCORCONFIGr_MC.D1/IN4 ;
  wire \NlwInverterSignal_DCORCONFIGr_MC.D1/IN5 ;
  wire \NlwInverterSignal_DCORCONFIGr_MC.D1/IN6 ;
  wire \NlwInverterSignal_DCORENCPWRr_MC.D1/IN1 ;
  wire \NlwInverterSignal_DCORENCPWRr_MC.D1/IN2 ;
  wire \NlwInverterSignal_DCORENCPWRr_MC.D1/IN3 ;
  wire \NlwInverterSignal_DCORENCPWRr_MC.D1/IN4 ;
  wire \NlwInverterSignal_DCORENCPWRr_MC.D1/IN5 ;
  wire \NlwInverterSignal_DCORENCPWRr_MC.D1/IN6 ;
  wire \NlwInverterSignal_outDATA<0>\$WA5.UIM_MC.D2_PT_0/IN1 ;
  wire \NlwInverterSignal_NET2528_MC.D1/IN1 ;
  wire \NlwInverterSignal_NET2528_MC.D2_PT_0/IN1 ;
  wire \NlwInverterSignal_NET2528_MC.D2_PT_1/IN1 ;
  wire \NlwInverterSignal_NET2528_MC.D2_PT_1/IN3 ;
  wire \NlwInverterSignal_DCORIFGr_MC.D1/IN1 ;
  wire \NlwInverterSignal_DCORIFGr_MC.D1/IN3 ;
  wire \NlwInverterSignal_DCORIFGr_MC.D1/IN4 ;
  wire \NlwInverterSignal_DCORIFGr_MC.D1/IN5 ;
  wire \NlwInverterSignal_DCORIFGr_MC.D1/IN6 ;
  wire \NlwInverterSignal_DCORIFGr_MC.D1/IN7 ;
  wire \NlwInverterSignal_DCORIFGr_MC.D1/IN8 ;
  wire \NlwInverterSignal_DCORIFGr_MC.D1/IN9 ;
  wire \NlwInverterSignal_outDATA<0>\$WA4.UIM_MC.D2_PT_0/IN0 ;
  wire \NlwInverterSignal_outDATA<0>\$WA4.UIM_MC.D2_PT_1/IN0 ;
  wire \NlwInverterSignal_DCORLIMITSr_MC.D1/IN1 ;
  wire \NlwInverterSignal_DCORLIMITSr_MC.D1/IN3 ;
  wire \NlwInverterSignal_DCORLIMITSr_MC.D1/IN4 ;
  wire \NlwInverterSignal_DCORLIMITSr_MC.D1/IN5 ;
  wire \NlwInverterSignal_DCORLIMITSr_MC.D1/IN6 ;
  wire \NlwInverterSignal_DCORLIMITSr_MC.D1/IN7 ;
  wire \NlwInverterSignal_DCORLIMITSr_MC.D1/IN9 ;
  wire \NlwInverterSignal_U5/RLS0fr_MC.D2_PT_0/IN2 ;
  wire \NlwInverterSignal_U5/RLS0fr_MC.D2_PT_1/IN1 ;
  wire \NlwInverterSignal_U5/RLS0fr_MC.D2_PT_1/IN2 ;
  wire \NlwInverterSignal_U5/RLS0fr_MC.D2_PT_1/IN3 ;
  wire \NlwInverterSignal_DCORLINTr_MC.D1/IN1 ;
  wire \NlwInverterSignal_DCORLINTr_MC.D1/IN2 ;
  wire \NlwInverterSignal_DCORLINTr_MC.D1/IN3 ;
  wire \NlwInverterSignal_DCORLINTr_MC.D1/IN4 ;
  wire \NlwInverterSignal_DCORLINTr_MC.D1/IN5 ;
  wire \NlwInverterSignal_DCORLINTr_MC.D1/IN6 ;
  wire \NlwInverterSignal_DCORLINTr_MC.D1/IN7 ;
  wire \NlwInverterSignal_DCORLINTr_MC.D1/IN9 ;
  wire \NlwInverterSignal_N_PZ_1016_MC.D1/IN0 ;
  wire \NlwInverterSignal_N_PZ_1016_MC.D1/IN1 ;
  wire \NlwInverterSignal_outDATA<0>\$WA1.UIM_MC.D2_PT_1/IN0 ;
  wire \NlwInverterSignal_outDATA<0>\$WA1.UIM_MC.D2_PT_2/IN0 ;
  wire \NlwInverterSignal_outDATA<0>\$WA1.UIM_MC.D2_PT_2/IN1 ;
  wire \NlwInverterSignal_outDATA<0>\$WA1.UIM_MC.D2_PT_3/IN0 ;
  wire \NlwInverterSignal_outDATA<0>\$WA1.UIM_MC.D2_PT_3/IN1 ;
  wire \NlwInverterSignal_outDATA<0>\$WA1.UIM_MC.D2_PT_3/IN2 ;
  wire \NlwInverterSignal_U1/U3/holdingreg0<0>_MC.D2_PT_1/IN1 ;
  wire \NlwInverterSignal_DCOR0CNTLOWr_MC.D1/IN1 ;
  wire \NlwInverterSignal_DCOR0CNTLOWr_MC.D1/IN2 ;
  wire \NlwInverterSignal_DCOR0CNTLOWr_MC.D1/IN3 ;
  wire \NlwInverterSignal_DCOR0CNTLOWr_MC.D1/IN4 ;
  wire \NlwInverterSignal_DCOR0CNTLOWr_MC.D1/IN5 ;
  wire \NlwInverterSignal_DCOR0CNTLOWr_MC.D1/IN6 ;
  wire \NlwInverterSignal_DCOR0CNTLOWr_MC.D1/IN7 ;
  wire \NlwInverterSignal_DCOR0CNTLOWr_MC.D1/IN8 ;
  wire \NlwInverterSignal_U1/U3/holdingreg1<0>_MC.D2_PT_1/IN1 ;
  wire \NlwInverterSignal_DCOR1CNTLOWr_MC.D1/IN1 ;
  wire \NlwInverterSignal_DCOR1CNTLOWr_MC.D1/IN2 ;
  wire \NlwInverterSignal_DCOR1CNTLOWr_MC.D1/IN3 ;
  wire \NlwInverterSignal_DCOR1CNTLOWr_MC.D1/IN4 ;
  wire \NlwInverterSignal_DCOR1CNTLOWr_MC.D1/IN5 ;
  wire \NlwInverterSignal_DCOR1CNTLOWr_MC.D1/IN6 ;
  wire \NlwInverterSignal_DCOR1CNTLOWr_MC.D1/IN7 ;
  wire \NlwInverterSignal_U1/U3/holdingreg0<8>_MC.D2_PT_1/IN1 ;
  wire \NlwInverterSignal_DCOR0CNTHIGHr_MC.D1/IN1 ;
  wire \NlwInverterSignal_DCOR0CNTHIGHr_MC.D1/IN3 ;
  wire \NlwInverterSignal_DCOR0CNTHIGHr_MC.D1/IN4 ;
  wire \NlwInverterSignal_DCOR0CNTHIGHr_MC.D1/IN5 ;
  wire \NlwInverterSignal_DCOR0CNTHIGHr_MC.D1/IN6 ;
  wire \NlwInverterSignal_DCOR0CNTHIGHr_MC.D1/IN7 ;
  wire \NlwInverterSignal_DCOR0CNTHIGHr_MC.D1/IN8 ;
  wire \NlwInverterSignal_U1/U3/holdingreg1<8>_MC.D2_PT_1/IN1 ;
  wire \NlwInverterSignal_N_PZ_1017_MC.D1/IN0 ;
  wire \NlwInverterSignal_N_PZ_1017_MC.D1/IN1 ;
  wire \NlwInverterSignal_N_PZ_1017_MC.D1/IN2 ;
  wire \NlwInverterSignal_N_PZ_1017_MC.D1/IN3 ;
  wire \NlwInverterSignal_DCOR1CNTHIGHr_MC.D1/IN1 ;
  wire \NlwInverterSignal_DCOR1CNTHIGHr_MC.D1/IN3 ;
  wire \NlwInverterSignal_DCOR1CNTHIGHr_MC.D1/IN4 ;
  wire \NlwInverterSignal_DCOR1CNTHIGHr_MC.D1/IN5 ;
  wire \NlwInverterSignal_DCOR1CNTHIGHr_MC.D1/IN6 ;
  wire \NlwInverterSignal_DCOR1CNTHIGHr_MC.D1/IN7 ;
  wire \NlwInverterSignal_N_PZ_1053_MC.D1/IN0 ;
  wire \NlwInverterSignal_N_PZ_1053_MC.D1/IN1 ;
  wire \NlwInverterSignal_N_PZ_1053_MC.D1/IN2 ;
  wire \NlwInverterSignal_N_PZ_1053_MC.D1/IN3 ;
  wire \NlwInverterSignal_N_PZ_1053_MC.D1/IN4 ;
  wire \NlwInverterSignal_DCOR1THRESHIGHr_MC.D1/IN1 ;
  wire \NlwInverterSignal_DCOR1THRESHIGHr_MC.D1/IN3 ;
  wire \NlwInverterSignal_DCOR1THRESHIGHr_MC.D1/IN4 ;
  wire \NlwInverterSignal_DCOR1THRESHIGHr_MC.D1/IN5 ;
  wire \NlwInverterSignal_DCOR1THRESHIGHr_MC.D1/IN6 ;
  wire \NlwInverterSignal_DCOR1THRESHIGHr_MC.D1/IN9 ;
  wire \NlwInverterSignal_U2_Enable_AD_MC.D1/IN1 ;
  wire \NlwInverterSignal_U2_Enable_AD_MC.D1/IN2 ;
  wire \NlwInverterSignal_U2_Enable_AD_MC.D1/IN3 ;
  wire \NlwInverterSignal_U2_Enable_AD_MC.D1/IN4 ;
  wire \NlwInverterSignal_U2_Enable_AD_MC.D1/IN5 ;
  wire \NlwInverterSignal_AD<1>_MC.D/IN0 ;
  wire \NlwInverterSignal_AD<1>_MC.D2_PT_0/IN1 ;
  wire \NlwInverterSignal_AD<1>_MC.D2_PT_1/IN1 ;
  wire \NlwInverterSignal_AD<1>_MC.D2_PT_2/IN1 ;
  wire \NlwInverterSignal_AD<1>_MC.D2_PT_3/IN1 ;
  wire \NlwInverterSignal_AD<1>_MC.D2_PT_4/IN1 ;
  wire \NlwInverterSignal_AD<1>_MC.D2_PT_5/IN0 ;
  wire \NlwInverterSignal_AD<1>_MC.D2_PT_5/IN1 ;
  wire \NlwInverterSignal_AD<1>_MC.D2_PT_6/IN0 ;
  wire \NlwInverterSignal_AD<1>_MC.D2_PT_6/IN1 ;
  wire \NlwInverterSignal_AD<1>_MC.D2_PT_7/IN0 ;
  wire \NlwInverterSignal_AD<1>_MC.D2_PT_7/IN1 ;
  wire \NlwInverterSignal_AD<1>_MC.D2_PT_7/IN2 ;
  wire \NlwInverterSignal_outDATA<1>\$WA2.UIM_MC.D2_PT_1/IN0 ;
  wire \NlwInverterSignal_outDATA<1>\$WA2.UIM_MC.D2_PT_2/IN0 ;
  wire \NlwInverterSignal_outDATA<1>\$WA2.UIM_MC.D2_PT_2/IN1 ;
  wire \NlwInverterSignal_outDATA<1>\$WA2.UIM_MC.D2_PT_3/IN0 ;
  wire \NlwInverterSignal_outDATA<1>\$WA2.UIM_MC.D2_PT_3/IN1 ;
  wire \NlwInverterSignal_outDATA<1>\$WA2.UIM_MC.D2_PT_3/IN2 ;
  wire \NlwInverterSignal_U1/U4/Latch0r<1>_MC.D2_PT_1/IN1 ;
  wire \NlwInverterSignal_U1/U4/Latch0r<9>_MC.D2_PT_1/IN1 ;
  wire \NlwInverterSignal_U1/Channel0<9>_MC.D2_PT_0/IN0 ;
  wire \NlwInverterSignal_U1/Channel0<9>_MC.D2_PT_2/IN0 ;
  wire \NlwInverterSignal_U1/U4/Latch1r<1>_MC.D2_PT_1/IN1 ;
  wire \NlwInverterSignal_U1/U4/Latch1r<9>_MC.D2_PT_1/IN1 ;
  wire \NlwInverterSignal_U1/Channel1<9>_MC.D2_PT_0/IN0 ;
  wire \NlwInverterSignal_U1/Channel1<9>_MC.D2_PT_1/IN1 ;
  wire \NlwInverterSignal_U1/Channel1<9>_MC.D2_PT_1/IN3 ;
  wire \NlwInverterSignal_U1/Channel1<9>_MC.D2_PT_1/IN5 ;
  wire \NlwInverterSignal_U1/Channel1<9>_MC.D2_PT_2/IN1 ;
  wire \NlwInverterSignal_U1/Channel1<9>_MC.D2_PT_2/IN3 ;
  wire \NlwInverterSignal_U1/Channel1<9>_MC.D2_PT_2/IN5 ;
  wire \NlwInverterSignal_outDATA<1>\$WA5.UIM_MC.D2_PT_0/IN0 ;
  wire \NlwInverterSignal_outDATA<1>\$WA5.UIM_MC.D2_PT_2/IN1 ;
  wire \NlwInverterSignal_outDATA<1>\$WA4.UIM_MC.D2_PT_0/IN1 ;
  wire \NlwInverterSignal_outDATA<1>\$WA4.UIM_MC.D2_PT_1/IN0 ;
  wire \NlwInverterSignal_U5/FLS0fr_MC.D2_PT_0/IN1 ;
  wire \NlwInverterSignal_U5/FLS0fr_MC.D2_PT_1/IN1 ;
  wire \NlwInverterSignal_U5/FLS0fr_MC.D2_PT_1/IN3 ;
  wire \NlwInverterSignal_outDATA<1>\$WA1.UIM_MC.D2_PT_1/IN0 ;
  wire \NlwInverterSignal_outDATA<1>\$WA1.UIM_MC.D2_PT_2/IN0 ;
  wire \NlwInverterSignal_outDATA<1>\$WA1.UIM_MC.D2_PT_2/IN1 ;
  wire \NlwInverterSignal_outDATA<1>\$WA1.UIM_MC.D2_PT_3/IN0 ;
  wire \NlwInverterSignal_outDATA<1>\$WA1.UIM_MC.D2_PT_3/IN1 ;
  wire \NlwInverterSignal_outDATA<1>\$WA1.UIM_MC.D2_PT_3/IN2 ;
  wire \NlwInverterSignal_U1/U3/holdingreg0<1>_MC.D2_PT_1/IN1 ;
  wire \NlwInverterSignal_U1/U3/holdingreg1<1>_MC.D2_PT_1/IN1 ;
  wire \NlwInverterSignal_U1/U3/holdingreg0<9>_MC.D2_PT_1/IN1 ;
  wire \NlwInverterSignal_U1/U3/holdingreg1<9>_MC.D2_PT_1/IN1 ;
  wire \NlwInverterSignal_AD<4>_MC.D/IN0 ;
  wire \NlwInverterSignal_AD<4>_MC.D2_PT_0/IN1 ;
  wire \NlwInverterSignal_AD<4>_MC.D2_PT_1/IN1 ;
  wire \NlwInverterSignal_AD<4>_MC.D2_PT_2/IN1 ;
  wire \NlwInverterSignal_AD<4>_MC.D2_PT_3/IN1 ;
  wire \NlwInverterSignal_AD<4>_MC.D2_PT_4/IN1 ;
  wire \NlwInverterSignal_AD<4>_MC.D2_PT_5/IN0 ;
  wire \NlwInverterSignal_AD<4>_MC.D2_PT_5/IN1 ;
  wire \NlwInverterSignal_AD<4>_MC.D2_PT_6/IN0 ;
  wire \NlwInverterSignal_AD<4>_MC.D2_PT_6/IN1 ;
  wire \NlwInverterSignal_AD<4>_MC.D2_PT_7/IN0 ;
  wire \NlwInverterSignal_AD<4>_MC.D2_PT_7/IN1 ;
  wire \NlwInverterSignal_AD<4>_MC.D2_PT_7/IN2 ;
  wire \NlwInverterSignal_outDATA<4>\$WA2.UIM_MC.D2_PT_1/IN0 ;
  wire \NlwInverterSignal_outDATA<4>\$WA2.UIM_MC.D2_PT_2/IN0 ;
  wire \NlwInverterSignal_outDATA<4>\$WA2.UIM_MC.D2_PT_2/IN1 ;
  wire \NlwInverterSignal_outDATA<4>\$WA2.UIM_MC.D2_PT_3/IN0 ;
  wire \NlwInverterSignal_outDATA<4>\$WA2.UIM_MC.D2_PT_3/IN1 ;
  wire \NlwInverterSignal_outDATA<4>\$WA2.UIM_MC.D2_PT_3/IN2 ;
  wire \NlwInverterSignal_U1/U4/Latch0r<4>_MC.D2_PT_1/IN1 ;
  wire \NlwInverterSignal_U1/U4/Latch0r<12>_MC.D2_PT_1/IN1 ;
  wire \NlwInverterSignal_U1/Channel0<12>_MC.D2_PT_0/IN0 ;
  wire \NlwInverterSignal_U1/Channel0<12>_MC.D2_PT_1/IN2 ;
  wire \NlwInverterSignal_U1/Channel0<12>_MC.D2_PT_1/IN3 ;
  wire \NlwInverterSignal_U1/Channel0<12>_MC.D2_PT_1/IN4 ;
  wire \NlwInverterSignal_U1/Channel0<12>_MC.D2_PT_2/IN0 ;
  wire \NlwInverterSignal_U1/Channel0<10>_MC.D2_PT_0/IN0 ;
  wire \NlwInverterSignal_U1/Channel0<10>_MC.D2_PT_1/IN2 ;
  wire \NlwInverterSignal_U1/Channel0<10>_MC.D2_PT_2/IN0 ;
  wire \NlwInverterSignal_U1/Channel0<11>_MC.D2_PT_0/IN0 ;
  wire \NlwInverterSignal_U1/Channel0<11>_MC.D2_PT_1/IN2 ;
  wire \NlwInverterSignal_U1/Channel0<11>_MC.D2_PT_1/IN3 ;
  wire \NlwInverterSignal_U1/Channel0<11>_MC.D2_PT_2/IN0 ;
  wire \NlwInverterSignal_U1/U4/Latch1r<4>_MC.D2_PT_1/IN1 ;
  wire \NlwInverterSignal_U1/U4/Latch1r<12>_MC.D2_PT_1/IN1 ;
  wire \NlwInverterSignal_U1/Channel1<12>_MC.D2_PT_0/IN0 ;
  wire \NlwInverterSignal_U1/Channel1<12>_MC.D2_PT_1/IN1 ;
  wire \NlwInverterSignal_U1/Channel1<12>_MC.D2_PT_1/IN3 ;
  wire \NlwInverterSignal_U1/Channel1<12>_MC.D2_PT_1/IN5 ;
  wire \NlwInverterSignal_U1/Channel1<12>_MC.D2_PT_2/IN1 ;
  wire \NlwInverterSignal_U1/Channel1<12>_MC.D2_PT_2/IN3 ;
  wire \NlwInverterSignal_U1/Channel1<12>_MC.D2_PT_2/IN5 ;
  wire \NlwInverterSignal_U1/Channel1<12>_MC.D2_PT_2/IN7 ;
  wire \NlwInverterSignal_U1/Channel1<12>_MC.D2_PT_2/IN8 ;
  wire \NlwInverterSignal_U1/Channel1<12>_MC.D2_PT_2/IN9 ;
  wire \NlwInverterSignal_U1/Channel1<10>_MC.D2_PT_0/IN0 ;
  wire \NlwInverterSignal_U1/Channel1<10>_MC.D2_PT_1/IN1 ;
  wire \NlwInverterSignal_U1/Channel1<10>_MC.D2_PT_1/IN3 ;
  wire \NlwInverterSignal_U1/Channel1<10>_MC.D2_PT_1/IN5 ;
  wire \NlwInverterSignal_U1/Channel1<10>_MC.D2_PT_2/IN1 ;
  wire \NlwInverterSignal_U1/Channel1<10>_MC.D2_PT_2/IN3 ;
  wire \NlwInverterSignal_U1/Channel1<10>_MC.D2_PT_2/IN5 ;
  wire \NlwInverterSignal_U1/Channel1<10>_MC.D2_PT_2/IN7 ;
  wire \NlwInverterSignal_U1/Channel1<11>_MC.D2_PT_0/IN0 ;
  wire \NlwInverterSignal_U1/Channel1<11>_MC.D2_PT_1/IN1 ;
  wire \NlwInverterSignal_U1/Channel1<11>_MC.D2_PT_1/IN3 ;
  wire \NlwInverterSignal_U1/Channel1<11>_MC.D2_PT_1/IN5 ;
  wire \NlwInverterSignal_U1/Channel1<11>_MC.D2_PT_2/IN1 ;
  wire \NlwInverterSignal_U1/Channel1<11>_MC.D2_PT_2/IN3 ;
  wire \NlwInverterSignal_U1/Channel1<11>_MC.D2_PT_2/IN5 ;
  wire \NlwInverterSignal_U1/Channel1<11>_MC.D2_PT_2/IN7 ;
  wire \NlwInverterSignal_U1/Channel1<11>_MC.D2_PT_2/IN8 ;
  wire \NlwInverterSignal_outDATA<4>\$WA5.UIM_MC.D2_PT_1/IN0 ;
  wire \NlwInverterSignal_NET2575_MC.D/IN0 ;
  wire \NlwInverterSignal_NET2575_MC.D2_PT_0/IN0 ;
  wire \NlwInverterSignal_NET2575_MC.D2_PT_0/IN1 ;
  wire \NlwInverterSignal_NET2575_MC.D2_PT_2/IN1 ;
  wire \NlwInverterSignal_NET2575_MC.D2_PT_3/IN0 ;
  wire \NlwInverterSignal_NET2575_MC.D2_PT_3/IN1 ;
  wire \NlwInverterSignal_NET2575_MC.D2_PT_3/IN2 ;
  wire \NlwInverterSignal_NET2575_MC.D2_PT_3/IN3 ;
  wire \NlwInverterSignal_NET2575_MC.D2_PT_3/IN4 ;
  wire \NlwInverterSignal_U5/FLS1fr_MC.D2_PT_0/IN1 ;
  wire \NlwInverterSignal_U5/FLS1fr_MC.D2_PT_1/IN1 ;
  wire \NlwInverterSignal_U5/FLS1fr_MC.D2_PT_1/IN3 ;
  wire \NlwInverterSignal_U5/RLS1fr_MC.D2_PT_0/IN1 ;
  wire \NlwInverterSignal_U5/RLS1fr_MC.D2_PT_1/IN1 ;
  wire \NlwInverterSignal_U5/RLS1fr_MC.D2_PT_1/IN2 ;
  wire \NlwInverterSignal_U5/RLS1fr_MC.D2_PT_1/IN3 ;
  wire \NlwInverterSignal_outDATA<4>\$WA4.UIM_MC.D2_PT_0/IN1 ;
  wire \NlwInverterSignal_outDATA<4>\$WA4.UIM_MC.D2_PT_1/IN0 ;
  wire \NlwInverterSignal_outDATA<4>\$WA1.UIM_MC.D2_PT_1/IN0 ;
  wire \NlwInverterSignal_outDATA<4>\$WA1.UIM_MC.D2_PT_2/IN0 ;
  wire \NlwInverterSignal_outDATA<4>\$WA1.UIM_MC.D2_PT_2/IN1 ;
  wire \NlwInverterSignal_outDATA<4>\$WA1.UIM_MC.D2_PT_3/IN0 ;
  wire \NlwInverterSignal_outDATA<4>\$WA1.UIM_MC.D2_PT_3/IN1 ;
  wire \NlwInverterSignal_outDATA<4>\$WA1.UIM_MC.D2_PT_3/IN2 ;
  wire \NlwInverterSignal_U1/U3/holdingreg0<4>_MC.D2_PT_1/IN1 ;
  wire \NlwInverterSignal_U1/U3/holdingreg1<4>_MC.D2_PT_1/IN1 ;
  wire \NlwInverterSignal_U1/U3/holdingreg0<12>_MC.D2_PT_1/IN1 ;
  wire \NlwInverterSignal_U1/U3/holdingreg1<12>_MC.D2_PT_1/IN1 ;
  wire \NlwInverterSignal_AD<5>_MC.D/IN0 ;
  wire \NlwInverterSignal_AD<5>_MC.D2_PT_0/IN1 ;
  wire \NlwInverterSignal_AD<5>_MC.D2_PT_1/IN1 ;
  wire \NlwInverterSignal_AD<5>_MC.D2_PT_2/IN1 ;
  wire \NlwInverterSignal_AD<5>_MC.D2_PT_3/IN0 ;
  wire \NlwInverterSignal_AD<5>_MC.D2_PT_3/IN1 ;
  wire \NlwInverterSignal_AD<5>_MC.D2_PT_4/IN0 ;
  wire \NlwInverterSignal_AD<5>_MC.D2_PT_4/IN1 ;
  wire \NlwInverterSignal_AD<5>_MC.D2_PT_5/IN0 ;
  wire \NlwInverterSignal_AD<5>_MC.D2_PT_5/IN1 ;
  wire \NlwInverterSignal_outDATA<5>\$WA5.UIM_MC.D2_PT_1/IN0 ;
  wire \NlwInverterSignal_outDATA<5>\$WA4.UIM_MC.D2_PT_0/IN1 ;
  wire \NlwInverterSignal_outDATA<5>\$WA4.UIM_MC.D2_PT_1/IN0 ;
  wire \NlwInverterSignal_outDATA<5>\$WA1.UIM_MC.D2_PT_1/IN0 ;
  wire \NlwInverterSignal_outDATA<5>\$WA1.UIM_MC.D2_PT_2/IN0 ;
  wire \NlwInverterSignal_outDATA<5>\$WA1.UIM_MC.D2_PT_2/IN1 ;
  wire \NlwInverterSignal_outDATA<5>\$WA1.UIM_MC.D2_PT_3/IN0 ;
  wire \NlwInverterSignal_outDATA<5>\$WA1.UIM_MC.D2_PT_3/IN1 ;
  wire \NlwInverterSignal_outDATA<5>\$WA1.UIM_MC.D2_PT_3/IN2 ;
  wire \NlwInverterSignal_U1/U3/holdingreg0<5>_MC.D2_PT_1/IN1 ;
  wire \NlwInverterSignal_U1/U3/holdingreg1<5>_MC.D2_PT_1/IN1 ;
  wire \NlwInverterSignal_U1/U3/holdingreg0<13>_MC.D2_PT_1/IN1 ;
  wire \NlwInverterSignal_U1/Channel0<13>_MC.D2_PT_0/IN0 ;
  wire \NlwInverterSignal_U1/Channel0<13>_MC.D2_PT_1/IN2 ;
  wire \NlwInverterSignal_U1/Channel0<13>_MC.D2_PT_1/IN3 ;
  wire \NlwInverterSignal_U1/Channel0<13>_MC.D2_PT_1/IN4 ;
  wire \NlwInverterSignal_U1/Channel0<13>_MC.D2_PT_1/IN5 ;
  wire \NlwInverterSignal_U1/Channel0<13>_MC.D2_PT_2/IN0 ;
  wire \NlwInverterSignal_U1/U3/holdingreg1<13>_MC.D2_PT_1/IN1 ;
  wire \NlwInverterSignal_U1/Channel1<13>_MC.D2_PT_0/IN0 ;
  wire \NlwInverterSignal_U1/Channel1<13>_MC.D2_PT_1/IN1 ;
  wire \NlwInverterSignal_U1/Channel1<13>_MC.D2_PT_1/IN3 ;
  wire \NlwInverterSignal_U1/Channel1<13>_MC.D2_PT_1/IN5 ;
  wire \NlwInverterSignal_U1/Channel1<13>_MC.D2_PT_2/IN1 ;
  wire \NlwInverterSignal_U1/Channel1<13>_MC.D2_PT_2/IN3 ;
  wire \NlwInverterSignal_U1/Channel1<13>_MC.D2_PT_2/IN5 ;
  wire \NlwInverterSignal_U1/Channel1<13>_MC.D2_PT_2/IN7 ;
  wire \NlwInverterSignal_U1/Channel1<13>_MC.D2_PT_2/IN8 ;
  wire \NlwInverterSignal_U1/Channel1<13>_MC.D2_PT_2/IN9 ;
  wire \NlwInverterSignal_U1/Channel1<13>_MC.D2_PT_2/IN10 ;
  wire \NlwInverterSignal_outDATA<5>\$WA2.UIM_MC.D2_PT_1/IN0 ;
  wire \NlwInverterSignal_outDATA<5>\$WA2.UIM_MC.D2_PT_2/IN0 ;
  wire \NlwInverterSignal_outDATA<5>\$WA2.UIM_MC.D2_PT_2/IN1 ;
  wire \NlwInverterSignal_outDATA<5>\$WA2.UIM_MC.D2_PT_3/IN0 ;
  wire \NlwInverterSignal_outDATA<5>\$WA2.UIM_MC.D2_PT_3/IN1 ;
  wire \NlwInverterSignal_outDATA<5>\$WA2.UIM_MC.D2_PT_3/IN2 ;
  wire \NlwInverterSignal_outDATA<5>\$WA2.UIM_MC.D2_PT_4/IN0 ;
  wire \NlwInverterSignal_outDATA<5>\$WA2.UIM_MC.D2_PT_4/IN1 ;
  wire \NlwInverterSignal_outDATA<5>\$WA2.UIM_MC.D2_PT_4/IN2 ;
  wire \NlwInverterSignal_outDATA<5>\$WA2.UIM_MC.D2_PT_4/IN3 ;
  wire \NlwInverterSignal_U1/U4/Latch0r<5>_MC.D2_PT_1/IN1 ;
  wire \NlwInverterSignal_U1/U4/Latch0r<13>_MC.D2_PT_1/IN1 ;
  wire \NlwInverterSignal_U1/U4/Latch1r<5>_MC.D2_PT_1/IN1 ;
  wire \NlwInverterSignal_U1/U4/Latch1r<13>_MC.D2_PT_1/IN1 ;
  wire \NlwInverterSignal_Enc033ctrl_MC.D/IN0 ;
  wire \NlwInverterSignal_Enc033ctrl_MC.D1/IN1 ;
  wire \NlwInverterSignal_U4/ctrlr<2>_MC.D/IN0 ;
  wire \NlwInverterSignal_U4/ctrlr<2>_MC.D2_PT_0/IN1 ;
  wire \NlwInverterSignal_U4/ctrlr<2>_MC.D2_PT_1/IN1 ;
  wire \NlwInverterSignal_U4/ctrlr<2>_MC.D2_PT_2/IN1 ;
  wire \NlwInverterSignal_U4/ctrlr<2>_MC.D2_PT_3/IN0 ;
  wire \NlwInverterSignal_U4/ctrlr<2>_MC.D2_PT_3/IN1 ;
  wire \NlwInverterSignal_U4/ctrlr<2>_MC.D2_PT_4/IN0 ;
  wire \NlwInverterSignal_U4/ctrlr<2>_MC.D2_PT_4/IN1 ;
  wire \NlwInverterSignal_U4/ctrlr<2>_MC.D2_PT_5/IN0 ;
  wire \NlwInverterSignal_U4/ctrlr<2>_MC.D2_PT_5/IN1 ;
  wire \NlwInverterSignal_DCORENCPWRw_MC.D1/IN0 ;
  wire \NlwInverterSignal_DCORENCPWRw_MC.D1/IN2 ;
  wire \NlwInverterSignal_DCORENCPWRw_MC.D1/IN3 ;
  wire \NlwInverterSignal_DCORENCPWRw_MC.D1/IN4 ;
  wire \NlwInverterSignal_DCORENCPWRw_MC.D1/IN5 ;
  wire \NlwInverterSignal_DCORENCPWRw_MC.D1/IN6 ;
  wire \NlwInverterSignal_U4/ctrlr<3>_MC.D/IN0 ;
  wire \NlwInverterSignal_U4/ctrlr<3>_MC.D2_PT_0/IN1 ;
  wire \NlwInverterSignal_U4/ctrlr<3>_MC.D2_PT_1/IN1 ;
  wire \NlwInverterSignal_U4/ctrlr<3>_MC.D2_PT_2/IN1 ;
  wire \NlwInverterSignal_U4/ctrlr<3>_MC.D2_PT_3/IN0 ;
  wire \NlwInverterSignal_U4/ctrlr<3>_MC.D2_PT_3/IN1 ;
  wire \NlwInverterSignal_U4/ctrlr<3>_MC.D2_PT_4/IN0 ;
  wire \NlwInverterSignal_U4/ctrlr<3>_MC.D2_PT_4/IN1 ;
  wire \NlwInverterSignal_U4/ctrlr<3>_MC.D2_PT_5/IN0 ;
  wire \NlwInverterSignal_U4/ctrlr<3>_MC.D2_PT_5/IN1 ;
  wire \NlwInverterSignal_Enc05ctrl_MC.D/IN0 ;
  wire \NlwInverterSignal_Enc05ctrl_MC.D1/IN0 ;
  wire \NlwInverterSignal_Enc133ctrl_MC.D/IN0 ;
  wire \NlwInverterSignal_U4/ctrlr<6>_MC.D/IN0 ;
  wire \NlwInverterSignal_U4/ctrlr<6>_MC.D2_PT_0/IN1 ;
  wire \NlwInverterSignal_U4/ctrlr<6>_MC.D2_PT_1/IN1 ;
  wire \NlwInverterSignal_U4/ctrlr<6>_MC.D2_PT_2/IN1 ;
  wire \NlwInverterSignal_U4/ctrlr<6>_MC.D2_PT_3/IN0 ;
  wire \NlwInverterSignal_U4/ctrlr<6>_MC.D2_PT_3/IN1 ;
  wire \NlwInverterSignal_U4/ctrlr<6>_MC.D2_PT_4/IN0 ;
  wire \NlwInverterSignal_U4/ctrlr<6>_MC.D2_PT_4/IN1 ;
  wire \NlwInverterSignal_U4/ctrlr<6>_MC.D2_PT_5/IN0 ;
  wire \NlwInverterSignal_U4/ctrlr<6>_MC.D2_PT_5/IN1 ;
  wire \NlwInverterSignal_U4/ctrlr<7>_MC.D/IN0 ;
  wire \NlwInverterSignal_U4/ctrlr<7>_MC.D2_PT_0/IN1 ;
  wire \NlwInverterSignal_U4/ctrlr<7>_MC.D2_PT_1/IN1 ;
  wire \NlwInverterSignal_U4/ctrlr<7>_MC.D2_PT_2/IN1 ;
  wire \NlwInverterSignal_U4/ctrlr<7>_MC.D2_PT_3/IN1 ;
  wire \NlwInverterSignal_U4/ctrlr<7>_MC.D2_PT_4/IN1 ;
  wire \NlwInverterSignal_U4/ctrlr<7>_MC.D2_PT_5/IN0 ;
  wire \NlwInverterSignal_U4/ctrlr<7>_MC.D2_PT_5/IN1 ;
  wire \NlwInverterSignal_U4/ctrlr<7>_MC.D2_PT_6/IN0 ;
  wire \NlwInverterSignal_U4/ctrlr<7>_MC.D2_PT_6/IN1 ;
  wire \NlwInverterSignal_U4/ctrlr<7>_MC.D2_PT_7/IN0 ;
  wire \NlwInverterSignal_U4/ctrlr<7>_MC.D2_PT_7/IN1 ;
  wire \NlwInverterSignal_U4/ctrlr<7>_MC.D2_PT_7/IN2 ;
  wire \NlwInverterSignal_Enc15ctrl_MC.D/IN0 ;
  wire \NlwInverterSignal_Enc15ctrl_MC.D1/IN0 ;
  wire \NlwInverterSignal_GP_Motor0_1_MC.D2_PT_1/IN1 ;
  wire \NlwInverterSignal_DCOROUTw_MC.D1/IN0 ;
  wire \NlwInverterSignal_DCOROUTw_MC.D1/IN3 ;
  wire \NlwInverterSignal_DCOROUTw_MC.D1/IN4 ;
  wire \NlwInverterSignal_DCOROUTw_MC.D1/IN5 ;
  wire \NlwInverterSignal_DCOROUTw_MC.D1/IN6 ;
  wire \NlwInverterSignal_GP_Motor1_1_MC.D2_PT_1/IN1 ;
  wire \NlwInverterSignal_Home033ctrl_MC.D/IN0 ;
  wire \NlwInverterSignal_Home05ctrl_MC.D/IN0 ;
  wire \NlwInverterSignal_Home133ctrl_MC.D/IN0 ;
  wire \NlwInverterSignal_Home15ctrl_MC.D/IN0 ;
  wire \NlwInverterSignal_INT_MC.D2_PT_6/IN0 ;
  wire \NlwInverterSignal_U3/DCORIE<0>_MC.D2_PT_1/IN2 ;
  wire \NlwInverterSignal_DCORIEw_MC.D1/IN0 ;
  wire \NlwInverterSignal_DCORIEw_MC.D1/IN2 ;
  wire \NlwInverterSignal_DCORIEw_MC.D1/IN3 ;
  wire \NlwInverterSignal_DCORIEw_MC.D1/IN4 ;
  wire \NlwInverterSignal_DCORIEw_MC.D1/IN5 ;
  wire \NlwInverterSignal_DCORIEw_MC.D1/IN6 ;
  wire \NlwInverterSignal_DCORIEw_MC.D1/IN7 ;
  wire \NlwInverterSignal_DCORIEw_MC.D1/IN8 ;
  wire \NlwInverterSignal_DCORIEw_MC.D1/IN9 ;
  wire \NlwInverterSignal_U3/DCORIE<1>_MC.D2_PT_1/IN2 ;
  wire \NlwInverterSignal_U3/DCORIE<2>_MC.D2_PT_1/IN2 ;
  wire \NlwInverterSignal_U3/DCORIE<3>_MC.D2_PT_1/IN2 ;
  wire \NlwInverterSignal_U3/DCORIE<4>_MC.D2_PT_1/IN2 ;
  wire \NlwInverterSignal_U3/DCORIE<5>_MC.D2_PT_1/IN2 ;
  wire \NlwInverterSignal_U3/DCORIE<6>_MC.D2_PT_1/IN2 ;
  wire \NlwInverterSignal_U3/DCORIE<7>_MC.D2_PT_1/IN2 ;
  wire \NlwInverterSignal_LED1_MC.D/IN0 ;
  wire \NlwInverterSignal_LED1_MC.D1/IN1 ;
  wire \NlwInverterSignal_U9/MISCr<0>_MC.D2_PT_1/IN1 ;
  wire \NlwInverterSignal_LED2_MC.D/IN0 ;
  wire \NlwInverterSignal_LED2_MC.D1/IN1 ;
  wire \NlwInverterSignal_U9/MISCr<1>_MC.D2_PT_1/IN1 ;
  wire \NlwInverterSignal_LED3_MC.D/IN0 ;
  wire \NlwInverterSignal_LED3_MC.D1/IN1 ;
  wire \NlwInverterSignal_U9/MISCr<2>_MC.D2_PT_1/IN1 ;
  wire \NlwInverterSignal_LED4_MC.D/IN0 ;
  wire \NlwInverterSignal_LED4_MC.D1/IN1 ;
  wire \NlwInverterSignal_U9/MISCr<3>_MC.D2_PT_1/IN1 ;
  wire \NlwInverterSignal_LED5_MC.D/IN0 ;
  wire \NlwInverterSignal_LED5_MC.D1/IN1 ;
  wire \NlwInverterSignal_U9/MISCr<4>_MC.D2_PT_1/IN1 ;
  wire \NlwInverterSignal_MTRpwr_MC.D2_PT_1/IN1 ;
  wire \NlwInverterSignal_MTRpwrn_MC.D/IN0 ;
  wire \NlwInverterSignal_MTRpwrn_MC.D2_PT_1/IN1 ;
  wire \NlwInverterSignal_MTRpwrn_MC.D2_PT_1/IN2 ;
  wire \NlwInverterSignal_PAL0_MC.D2_PT_0/IN1 ;
  wire \NlwInverterSignal_PAL0_MC.D2_PT_0/IN3 ;
  wire \NlwInverterSignal_PAL0_MC.D2_PT_0/IN4 ;
  wire \NlwInverterSignal_PAL0_MC.D2_PT_1/IN0 ;
  wire \NlwInverterSignal_PAL0_MC.D2_PT_1/IN1 ;
  wire \NlwInverterSignal_PAL0_MC.D2_PT_1/IN4 ;
  wire \NlwInverterSignal_NET3248_MC.D2_PT_0/IN1 ;
  wire \NlwInverterSignal_NET3248_MC.D2_PT_0/IN2 ;
  wire \NlwInverterSignal_NET3248_MC.D2_PT_0/IN3 ;
  wire \NlwInverterSignal_NET3248_MC.D2_PT_0/IN5 ;
  wire \NlwInverterSignal_NET3248_MC.D2_PT_1/IN1 ;
  wire \NlwInverterSignal_NET3248_MC.D2_PT_1/IN3 ;
  wire \NlwInverterSignal_NET3248_MC.D2_PT_1/IN5 ;
  wire \NlwInverterSignal_NET3248_MC.D2_PT_2/IN2 ;
  wire \NlwInverterSignal_NET3248_MC.D2_PT_2/IN3 ;
  wire \NlwInverterSignal_NET3248_MC.D2_PT_2/IN4 ;
  wire \NlwInverterSignal_NET3248_MC.D2_PT_2/IN5 ;
  wire \NlwInverterSignal_NET3248_MC.D2_PT_3/IN1 ;
  wire \NlwInverterSignal_NET3248_MC.D2_PT_3/IN2 ;
  wire \NlwInverterSignal_NET3248_MC.D2_PT_3/IN5 ;
  wire \NlwInverterSignal_NET3248_MC.D2_PT_4/IN1 ;
  wire \NlwInverterSignal_NET3248_MC.D2_PT_4/IN2 ;
  wire \NlwInverterSignal_NET3248_MC.D2_PT_4/IN4 ;
  wire \NlwInverterSignal_NET3248_MC.D2_PT_4/IN5 ;
  wire \NlwInverterSignal_NET3248_MC.D2_PT_5/IN1 ;
  wire \NlwInverterSignal_NET3248_MC.D2_PT_5/IN2 ;
  wire \NlwInverterSignal_NET3248_MC.D2_PT_5/IN3 ;
  wire \NlwInverterSignal_NET3248_MC.D2_PT_5/IN4 ;
  wire \NlwInverterSignal_NET3248_MC.D2_PT_5/IN5 ;
  wire \NlwInverterSignal_PAL1_MC.D2_PT_0/IN1 ;
  wire \NlwInverterSignal_PAL1_MC.D2_PT_0/IN3 ;
  wire \NlwInverterSignal_PAL1_MC.D2_PT_0/IN4 ;
  wire \NlwInverterSignal_PAL1_MC.D2_PT_1/IN0 ;
  wire \NlwInverterSignal_PAL1_MC.D2_PT_1/IN1 ;
  wire \NlwInverterSignal_PAL1_MC.D2_PT_1/IN4 ;
  wire \NlwInverterSignal_NET3253_MC.D2_PT_0/IN1 ;
  wire \NlwInverterSignal_NET3253_MC.D2_PT_0/IN3 ;
  wire \NlwInverterSignal_NET3253_MC.D2_PT_0/IN5 ;
  wire \NlwInverterSignal_NET3253_MC.D2_PT_1/IN1 ;
  wire \NlwInverterSignal_NET3253_MC.D2_PT_1/IN2 ;
  wire \NlwInverterSignal_NET3253_MC.D2_PT_1/IN3 ;
  wire \NlwInverterSignal_NET3253_MC.D2_PT_1/IN5 ;
  wire \NlwInverterSignal_NET3253_MC.D2_PT_2/IN1 ;
  wire \NlwInverterSignal_NET3253_MC.D2_PT_2/IN2 ;
  wire \NlwInverterSignal_NET3253_MC.D2_PT_2/IN3 ;
  wire \NlwInverterSignal_NET3253_MC.D2_PT_3/IN1 ;
  wire \NlwInverterSignal_NET3253_MC.D2_PT_3/IN2 ;
  wire \NlwInverterSignal_NET3253_MC.D2_PT_3/IN3 ;
  wire \NlwInverterSignal_NET3253_MC.D2_PT_3/IN5 ;
  wire \NlwInverterSignal_NET3253_MC.D2_PT_4/IN1 ;
  wire \NlwInverterSignal_NET3253_MC.D2_PT_4/IN2 ;
  wire \NlwInverterSignal_NET3253_MC.D2_PT_4/IN3 ;
  wire \NlwInverterSignal_NET3253_MC.D2_PT_4/IN4 ;
  wire \NlwInverterSignal_NET3253_MC.D2_PT_5/IN1 ;
  wire \NlwInverterSignal_NET3253_MC.D2_PT_5/IN2 ;
  wire \NlwInverterSignal_NET3253_MC.D2_PT_5/IN3 ;
  wire \NlwInverterSignal_NET3253_MC.D2_PT_5/IN4 ;
  wire \NlwInverterSignal_NET3253_MC.D2_PT_5/IN5 ;
  wire \NlwInverterSignal_PBL0_MC.D2_PT_0/IN1 ;
  wire \NlwInverterSignal_PBL0_MC.D2_PT_0/IN4 ;
  wire \NlwInverterSignal_PBL0_MC.D2_PT_1/IN0 ;
  wire \NlwInverterSignal_PBL0_MC.D2_PT_1/IN1 ;
  wire \NlwInverterSignal_PBL0_MC.D2_PT_1/IN3 ;
  wire \NlwInverterSignal_PBL0_MC.D2_PT_1/IN4 ;
  wire \NlwInverterSignal_PBL1_MC.D2_PT_0/IN1 ;
  wire \NlwInverterSignal_PBL1_MC.D2_PT_0/IN4 ;
  wire \NlwInverterSignal_PBL1_MC.D2_PT_1/IN0 ;
  wire \NlwInverterSignal_PBL1_MC.D2_PT_1/IN1 ;
  wire \NlwInverterSignal_PBL1_MC.D2_PT_1/IN3 ;
  wire \NlwInverterSignal_PBL1_MC.D2_PT_1/IN4 ;
  wire \NlwInverterSignal_PresEn_MC.D/IN0 ;
  wire \NlwInverterSignal_DCORSENSORw_MC.D1/IN0 ;
  wire \NlwInverterSignal_DCORSENSORw_MC.D1/IN2 ;
  wire \NlwInverterSignal_DCORSENSORw_MC.D1/IN3 ;
  wire \NlwInverterSignal_DCORSENSORw_MC.D1/IN4 ;
  wire \NlwInverterSignal_DCORSENSORw_MC.D1/IN5 ;
  wire \NlwInverterSignal_DCORSENSORw_MC.D1/IN6 ;
  wire \NlwInverterSignal_DCORSENSORw_MC.D1/IN8 ;
  wire \NlwInverterSignal_TP11_MC.D/IN0 ;
  wire \NlwInverterSignal_TmpEn_MC.D/IN0 ;
  wire \NlwInverterSignal_outDATA<2>\$WA5.UIM_MC.D2_PT_1/IN0 ;
  wire \NlwInverterSignal_outDATA<2>\$WA1.UIM_MC.D2_PT_1/IN0 ;
  wire \NlwInverterSignal_outDATA<2>\$WA1.UIM_MC.D2_PT_2/IN0 ;
  wire \NlwInverterSignal_outDATA<2>\$WA1.UIM_MC.D2_PT_2/IN1 ;
  wire \NlwInverterSignal_outDATA<2>\$WA1.UIM_MC.D2_PT_3/IN0 ;
  wire \NlwInverterSignal_outDATA<2>\$WA1.UIM_MC.D2_PT_3/IN1 ;
  wire \NlwInverterSignal_outDATA<2>\$WA1.UIM_MC.D2_PT_3/IN2 ;
  wire \NlwInverterSignal_U1/U3/holdingreg0<2>_MC.D2_PT_1/IN1 ;
  wire \NlwInverterSignal_U1/U3/holdingreg1<2>_MC.D2_PT_1/IN1 ;
  wire \NlwInverterSignal_U1/U3/holdingreg0<10>_MC.D2_PT_1/IN1 ;
  wire \NlwInverterSignal_U1/U3/holdingreg1<10>_MC.D2_PT_1/IN1 ;
  wire \NlwInverterSignal_outDATA<2>\$WA2.UIM_MC.D2_PT_1/IN0 ;
  wire \NlwInverterSignal_outDATA<2>\$WA2.UIM_MC.D2_PT_2/IN0 ;
  wire \NlwInverterSignal_outDATA<2>\$WA2.UIM_MC.D2_PT_2/IN1 ;
  wire \NlwInverterSignal_outDATA<2>\$WA2.UIM_MC.D2_PT_3/IN0 ;
  wire \NlwInverterSignal_outDATA<2>\$WA2.UIM_MC.D2_PT_3/IN1 ;
  wire \NlwInverterSignal_outDATA<2>\$WA2.UIM_MC.D2_PT_3/IN2 ;
  wire \NlwInverterSignal_outDATA<2>\$WA2.UIM_MC.D2_PT_4/IN0 ;
  wire \NlwInverterSignal_outDATA<2>\$WA2.UIM_MC.D2_PT_4/IN1 ;
  wire \NlwInverterSignal_outDATA<2>\$WA2.UIM_MC.D2_PT_4/IN2 ;
  wire \NlwInverterSignal_outDATA<2>\$WA2.UIM_MC.D2_PT_4/IN3 ;
  wire \NlwInverterSignal_U1/U4/Latch0r<2>_MC.D2_PT_1/IN1 ;
  wire \NlwInverterSignal_U1/U4/Latch0r<10>_MC.D2_PT_1/IN1 ;
  wire \NlwInverterSignal_U1/U4/Latch1r<2>_MC.D2_PT_1/IN1 ;
  wire \NlwInverterSignal_U1/U4/Latch1r<10>_MC.D2_PT_1/IN1 ;
  wire \NlwInverterSignal_outDATA<3>\$WA5.UIM_MC.D2_PT_1/IN0 ;
  wire \NlwInverterSignal_outDATA<3>\$WA1.UIM_MC.D2_PT_1/IN0 ;
  wire \NlwInverterSignal_outDATA<3>\$WA1.UIM_MC.D2_PT_2/IN0 ;
  wire \NlwInverterSignal_outDATA<3>\$WA1.UIM_MC.D2_PT_2/IN1 ;
  wire \NlwInverterSignal_outDATA<3>\$WA1.UIM_MC.D2_PT_3/IN0 ;
  wire \NlwInverterSignal_outDATA<3>\$WA1.UIM_MC.D2_PT_3/IN1 ;
  wire \NlwInverterSignal_outDATA<3>\$WA1.UIM_MC.D2_PT_3/IN2 ;
  wire \NlwInverterSignal_U1/U3/holdingreg0<3>_MC.D2_PT_1/IN1 ;
  wire \NlwInverterSignal_U1/U3/holdingreg1<3>_MC.D2_PT_1/IN1 ;
  wire \NlwInverterSignal_U1/U3/holdingreg0<11>_MC.D2_PT_1/IN1 ;
  wire \NlwInverterSignal_U1/U3/holdingreg1<11>_MC.D2_PT_1/IN1 ;
  wire \NlwInverterSignal_outDATA<3>\$WA2.UIM_MC.D2_PT_1/IN0 ;
  wire \NlwInverterSignal_outDATA<3>\$WA2.UIM_MC.D2_PT_2/IN0 ;
  wire \NlwInverterSignal_outDATA<3>\$WA2.UIM_MC.D2_PT_2/IN1 ;
  wire \NlwInverterSignal_outDATA<3>\$WA2.UIM_MC.D2_PT_3/IN0 ;
  wire \NlwInverterSignal_outDATA<3>\$WA2.UIM_MC.D2_PT_3/IN1 ;
  wire \NlwInverterSignal_outDATA<3>\$WA2.UIM_MC.D2_PT_3/IN2 ;
  wire \NlwInverterSignal_outDATA<3>\$WA2.UIM_MC.D2_PT_4/IN0 ;
  wire \NlwInverterSignal_outDATA<3>\$WA2.UIM_MC.D2_PT_4/IN1 ;
  wire \NlwInverterSignal_outDATA<3>\$WA2.UIM_MC.D2_PT_4/IN2 ;
  wire \NlwInverterSignal_outDATA<3>\$WA2.UIM_MC.D2_PT_4/IN3 ;
  wire \NlwInverterSignal_U1/U4/Latch0r<3>_MC.D2_PT_1/IN1 ;
  wire \NlwInverterSignal_U1/U4/Latch0r<11>_MC.D2_PT_1/IN1 ;
  wire \NlwInverterSignal_U1/U4/Latch1r<3>_MC.D2_PT_1/IN1 ;
  wire \NlwInverterSignal_U1/U4/Latch1r<11>_MC.D2_PT_1/IN1 ;
  wire \NlwInverterSignal_outDATA<6>\$WA5.UIM_MC.D2_PT_1/IN0 ;
  wire \NlwInverterSignal_outDATA<6>\$WA1.UIM_MC.D2_PT_1/IN0 ;
  wire \NlwInverterSignal_outDATA<6>\$WA1.UIM_MC.D2_PT_2/IN0 ;
  wire \NlwInverterSignal_outDATA<6>\$WA1.UIM_MC.D2_PT_2/IN1 ;
  wire \NlwInverterSignal_outDATA<6>\$WA1.UIM_MC.D2_PT_3/IN0 ;
  wire \NlwInverterSignal_outDATA<6>\$WA1.UIM_MC.D2_PT_3/IN1 ;
  wire \NlwInverterSignal_outDATA<6>\$WA1.UIM_MC.D2_PT_3/IN2 ;
  wire \NlwInverterSignal_U1/U3/holdingreg0<6>_MC.D2_PT_1/IN1 ;
  wire \NlwInverterSignal_U1/U3/holdingreg1<6>_MC.D2_PT_1/IN1 ;
  wire \NlwInverterSignal_U1/U3/holdingreg0<14>_MC.D2_PT_1/IN1 ;
  wire \NlwInverterSignal_U1/Channel0<14>_MC.D2_PT_0/IN0 ;
  wire \NlwInverterSignal_U1/Channel0<14>_MC.D2_PT_1/IN2 ;
  wire \NlwInverterSignal_U1/Channel0<14>_MC.D2_PT_1/IN3 ;
  wire \NlwInverterSignal_U1/Channel0<14>_MC.D2_PT_1/IN4 ;
  wire \NlwInverterSignal_U1/Channel0<14>_MC.D2_PT_1/IN5 ;
  wire \NlwInverterSignal_U1/Channel0<14>_MC.D2_PT_1/IN6 ;
  wire \NlwInverterSignal_U1/Channel0<14>_MC.D2_PT_2/IN0 ;
  wire \NlwInverterSignal_U1/U3/holdingreg1<14>_MC.D2_PT_1/IN1 ;
  wire \NlwInverterSignal_U1/Channel1<14>_MC.D2_PT_0/IN0 ;
  wire \NlwInverterSignal_U1/Channel1<14>_MC.D2_PT_1/IN1 ;
  wire \NlwInverterSignal_U1/Channel1<14>_MC.D2_PT_1/IN3 ;
  wire \NlwInverterSignal_U1/Channel1<14>_MC.D2_PT_1/IN5 ;
  wire \NlwInverterSignal_U1/Channel1<14>_MC.D2_PT_2/IN1 ;
  wire \NlwInverterSignal_U1/Channel1<14>_MC.D2_PT_2/IN3 ;
  wire \NlwInverterSignal_U1/Channel1<14>_MC.D2_PT_2/IN5 ;
  wire \NlwInverterSignal_U1/Channel1<14>_MC.D2_PT_2/IN7 ;
  wire \NlwInverterSignal_U1/Channel1<14>_MC.D2_PT_2/IN8 ;
  wire \NlwInverterSignal_U1/Channel1<14>_MC.D2_PT_2/IN9 ;
  wire \NlwInverterSignal_U1/Channel1<14>_MC.D2_PT_2/IN10 ;
  wire \NlwInverterSignal_U1/Channel1<14>_MC.D2_PT_2/IN11 ;
  wire \NlwInverterSignal_outDATA<6>\$WA2.UIM_MC.D2_PT_1/IN0 ;
  wire \NlwInverterSignal_outDATA<6>\$WA2.UIM_MC.D2_PT_2/IN0 ;
  wire \NlwInverterSignal_outDATA<6>\$WA2.UIM_MC.D2_PT_2/IN1 ;
  wire \NlwInverterSignal_outDATA<6>\$WA2.UIM_MC.D2_PT_3/IN0 ;
  wire \NlwInverterSignal_outDATA<6>\$WA2.UIM_MC.D2_PT_3/IN1 ;
  wire \NlwInverterSignal_outDATA<6>\$WA2.UIM_MC.D2_PT_3/IN2 ;
  wire \NlwInverterSignal_outDATA<6>\$WA2.UIM_MC.D2_PT_4/IN0 ;
  wire \NlwInverterSignal_outDATA<6>\$WA2.UIM_MC.D2_PT_4/IN1 ;
  wire \NlwInverterSignal_outDATA<6>\$WA2.UIM_MC.D2_PT_4/IN2 ;
  wire \NlwInverterSignal_outDATA<6>\$WA2.UIM_MC.D2_PT_4/IN3 ;
  wire \NlwInverterSignal_U1/U4/Latch0r<6>_MC.D2_PT_1/IN1 ;
  wire \NlwInverterSignal_U1/U4/Latch0r<14>_MC.D2_PT_1/IN1 ;
  wire \NlwInverterSignal_U1/U4/Latch1r<6>_MC.D2_PT_1/IN1 ;
  wire \NlwInverterSignal_U1/U4/Latch1r<14>_MC.D2_PT_1/IN1 ;
  wire \NlwInverterSignal_outDATA<7>\$WA2.UIM_MC.D2_PT_1/IN0 ;
  wire \NlwInverterSignal_outDATA<7>\$WA2.UIM_MC.D2_PT_2/IN0 ;
  wire \NlwInverterSignal_outDATA<7>\$WA2.UIM_MC.D2_PT_2/IN1 ;
  wire \NlwInverterSignal_outDATA<7>\$WA2.UIM_MC.D2_PT_3/IN0 ;
  wire \NlwInverterSignal_outDATA<7>\$WA2.UIM_MC.D2_PT_3/IN1 ;
  wire \NlwInverterSignal_outDATA<7>\$WA2.UIM_MC.D2_PT_3/IN2 ;
  wire \NlwInverterSignal_U1/U4/Latch0r<7>_MC.D2_PT_1/IN1 ;
  wire \NlwInverterSignal_U1/U4/Latch0r<15>_MC.D2_PT_1/IN1 ;
  wire \NlwInverterSignal_U1/Channel0<15>_MC.D2_PT_0/IN0 ;
  wire \NlwInverterSignal_U1/Channel0<15>_MC.D2_PT_1/IN2 ;
  wire \NlwInverterSignal_U1/Channel0<15>_MC.D2_PT_1/IN3 ;
  wire \NlwInverterSignal_U1/Channel0<15>_MC.D2_PT_1/IN4 ;
  wire \NlwInverterSignal_U1/Channel0<15>_MC.D2_PT_1/IN5 ;
  wire \NlwInverterSignal_U1/Channel0<15>_MC.D2_PT_1/IN6 ;
  wire \NlwInverterSignal_U1/Channel0<15>_MC.D2_PT_1/IN7 ;
  wire \NlwInverterSignal_U1/Channel0<15>_MC.D2_PT_2/IN0 ;
  wire \NlwInverterSignal_U1/U4/Latch1r<7>_MC.D2_PT_1/IN1 ;
  wire \NlwInverterSignal_U1/U4/Latch1r<15>_MC.D2_PT_1/IN1 ;
  wire \NlwInverterSignal_U1/Channel1<15>_MC.D2_PT_0/IN0 ;
  wire \NlwInverterSignal_U1/Channel1<15>_MC.D2_PT_1/IN1 ;
  wire \NlwInverterSignal_U1/Channel1<15>_MC.D2_PT_1/IN3 ;
  wire \NlwInverterSignal_U1/Channel1<15>_MC.D2_PT_1/IN5 ;
  wire \NlwInverterSignal_U1/Channel1<15>_MC.D2_PT_2/IN1 ;
  wire \NlwInverterSignal_U1/Channel1<15>_MC.D2_PT_2/IN3 ;
  wire \NlwInverterSignal_U1/Channel1<15>_MC.D2_PT_2/IN5 ;
  wire \NlwInverterSignal_U1/Channel1<15>_MC.D2_PT_2/IN7 ;
  wire \NlwInverterSignal_U1/Channel1<15>_MC.D2_PT_2/IN8 ;
  wire \NlwInverterSignal_U1/Channel1<15>_MC.D2_PT_2/IN9 ;
  wire \NlwInverterSignal_U1/Channel1<15>_MC.D2_PT_2/IN10 ;
  wire \NlwInverterSignal_U1/Channel1<15>_MC.D2_PT_2/IN11 ;
  wire \NlwInverterSignal_U1/Channel1<15>_MC.D2_PT_2/IN12 ;
  wire \NlwInverterSignal_outDATA<7>\$WA5.UIM_MC.D2_PT_1/IN0 ;
  wire \NlwInverterSignal_outDATA<7>\$WA1.UIM_MC.D2_PT_1/IN0 ;
  wire \NlwInverterSignal_outDATA<7>\$WA1.UIM_MC.D2_PT_2/IN0 ;
  wire \NlwInverterSignal_outDATA<7>\$WA1.UIM_MC.D2_PT_2/IN1 ;
  wire \NlwInverterSignal_outDATA<7>\$WA1.UIM_MC.D2_PT_3/IN0 ;
  wire \NlwInverterSignal_outDATA<7>\$WA1.UIM_MC.D2_PT_3/IN1 ;
  wire \NlwInverterSignal_outDATA<7>\$WA1.UIM_MC.D2_PT_3/IN2 ;
  wire \NlwInverterSignal_U1/U3/holdingreg0<7>_MC.D2_PT_1/IN1 ;
  wire \NlwInverterSignal_U1/U3/holdingreg1<7>_MC.D2_PT_1/IN1 ;
  wire \NlwInverterSignal_U1/U3/holdingreg0<15>_MC.D2_PT_1/IN1 ;
  wire \NlwInverterSignal_U1/U3/holdingreg1<15>_MC.D2_PT_1/IN1 ;
  wire \NlwInverterSignal_FOOBAR2__ctinst/7/OUT ;
  wire \NlwInverterSignal_FOOBAR6__ctinst/4/IN1 ;
  wire \NlwInverterSignal_FOOBAR9__ctinst/0/OUT ;
  wire \NlwInverterSignal_FOOBAR10__ctinst/0/OUT ;
  wire \NlwInverterSignal_FOOBAR12__ctinst/0/OUT ;
  wire \NlwInverterSignal_FOOBAR19__ctinst/0/OUT ;
  wire \NlwInverterSignal_FOOBAR21__ctinst/4/IN0 ;
  wire \NlwInverterSignal_FOOBAR21__ctinst/4/IN1 ;
  wire \NlwInverterSignal_FOOBAR24__ctinst/4/IN0 ;
  wire \NlwInverterSignal_FOOBAR24__ctinst/4/IN1 ;
  wire [7 : 0] \U4/Flgreg ;
  wire [7 : 0] U2_ADDR_reg;
  wire [5 : 0] U11_U3_counterr;
  wire [15 : 0] \U1/U4/Latch0r ;
  wire [15 : 0] \U1/U4/Latch1r ;
  wire [15 : 0] \U1/Channel0 ;
  wire [0 : 0] \U1/U2/location_Maddsub__n0000__n0075 ;
  wire [0 : 0] \U1/U2/location_Maddsub__n0000__n0067 ;
  wire [15 : 0] \U1/Channel1 ;
  wire [0 : 0] \U1/U5/location_Maddsub__n0000__n0075 ;
  wire [0 : 0] \U1/U5/location_Maddsub__n0000__n0067 ;
  wire [15 : 0] \U1/U3/holdingreg0 ;
  wire [15 : 0] \U1/U3/holdingreg1 ;
  wire [7 : 0] \U3/DCORIE ;
  wire [4 : 0] \U9/MISCr ;
  assign
    NlwRenamedSig_IO_WR = WR,
    NlwRenamedSig_IO_RD = RD,
    NlwRenamedSig_IO_AS = AS,
    NlwRenamedSig_IO_Home033FLG = Home033FLG,
    NlwRenamedSig_IO_Home15FLG = Home15FLG,
    NlwRenamedSig_IO_Home133FLG = Home133FLG,
    NlwRenamedSig_IO_Home05FLG = Home05FLG,
    NlwRenamedSig_IO_Enc15FLG = Enc15FLG,
    NlwRenamedSig_IO_Enc133FLG = Enc133FLG,
    NlwRenamedSig_IO_Enc05FLG = Enc05FLG,
    NlwRenamedSig_IO_Enc033FLG = Enc033FLG;
  initial $sdf_annotate("c:/projects/genosensor/2g/cplds/core/u21/implement/time_sim.sdf");
  X_IPAD \WR.PAD  (
    .PAD(NlwRenamedSig_IO_WR)
  );
  X_PU WR_tsimcreated__pullup_ (
    .O(NlwRenamedSig_IO_WR)
  );
  X_BUF \WR_II/UIM_0  (
    .I(NlwRenamedSig_IO_WR),
    .O(\WR_II/UIM )
  );
  X_IPAD \RD.PAD  (
    .PAD(NlwRenamedSig_IO_RD)
  );
  X_PU RD_tsimcreated__pullup_ (
    .O(NlwRenamedSig_IO_RD)
  );
  X_BUF \RD_II/UIM_1  (
    .I(NlwRenamedSig_IO_RD),
    .O(\RD_II/UIM )
  );
  X_IPAD \MSPReset.PAD  (
    .PAD(MSPReset)
  );
  X_BUF \MSPReset_II/UIM_2  (
    .I(MSPReset),
    .O(\MSPReset_II/UIM )
  );
  X_BUF \AD<0>_II/UIM_3  (
    .I(AD[0]),
    .O(\AD<0>_II/UIM )
  );
  X_IPAD \AS.PAD  (
    .PAD(NlwRenamedSig_IO_AS)
  );
  X_PU AS_tsimcreated__pullup_ (
    .O(NlwRenamedSig_IO_AS)
  );
  X_BUF \AS_II/UIM_4  (
    .I(NlwRenamedSig_IO_AS),
    .O(\AS_II/UIM )
  );
  X_BUF \AS_II/IREG_5  (
    .I(U2_ASedge),
    .O(\AS_II/IREG )
  );
  X_FF \U2_ASedge_MC.REG  (
    .I(NlwRenamedSig_IO_AS),
    .CE(Vcc),
    .CLK(\U2_ASedge_MC.REG_tsimcreated_inv_Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(U2_ASedge)
  );
  X_INV \U2_ASedge_MC.REG_tsimcreated_inv_Mclk_II/FCLK_6  (
    .I(\Mclk_II/FCLK ),
    .O(\U2_ASedge_MC.REG_tsimcreated_inv_Mclk_II/FCLK )
  );
  X_ZERO Gnd_7 (
    .O(Gnd)
  );
  X_ONE Vcc_8 (
    .O(Vcc)
  );
  X_IPAD \Mclk.PAD  (
    .PAD(Mclk)
  );
  X_BUF \Mclk_II/FCLK_9  (
    .I(Mclk),
    .O(\Mclk_II/FCLK )
  );
  X_BUF \AD<4>_II/UIM_10  (
    .I(AD[4]),
    .O(\AD<4>_II/UIM )
  );
  X_BUF \AD<5>_II/UIM_11  (
    .I(AD[5]),
    .O(\AD<5>_II/UIM )
  );
  X_BUF \AD<6>_II/UIM_12  (
    .I(AD[6]),
    .O(\AD<6>_II/UIM )
  );
  X_BUF \AD<6>_II/IREG_13  (
    .I(\U4/ctrlr[6] ),
    .O(\AD<6>_II/IREG )
  );
  X_OR2 \U4/ctrlr<6>_MC_tsimcreated_prld__14  (
    .I0(\FOOBAR10__ctinst/0 ),
    .I1(PRLD),
    .O(\U4/ctrlr<6>_MC_tsimcreated_prld_ )
  );
  X_FF \U4/ctrlr<6>_MC.REG  (
    .I(AD[6]),
    .CE(\FOOBAR10__ctinst/4 ),
    .CLK(\U4/ctrlr<6>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(\U4/ctrlr<6>_MC_tsimcreated_prld_ ),
    .O(\U4/ctrlr[6] )
  );
  X_INV \U4/ctrlr<6>_MC.REG_tsimcreated_inv_Mclk_II/FCLK_15  (
    .I(\Mclk_II/FCLK ),
    .O(\U4/ctrlr<6>_MC.REG_tsimcreated_inv_Mclk_II/FCLK )
  );
  X_BUF \AD<7>_II/UIM_16  (
    .I(AD[7]),
    .O(\AD<7>_II/UIM )
  );
  X_BUF \AD<7>_II/IREG_17  (
    .I(\U4/ctrlr[7] ),
    .O(\AD<7>_II/IREG )
  );
  X_OR2 \U4/ctrlr<7>_MC_tsimcreated_prld__18  (
    .I0(\FOOBAR9__ctinst/0 ),
    .I1(PRLD),
    .O(\U4/ctrlr<7>_MC_tsimcreated_prld_ )
  );
  X_FF \U4/ctrlr<7>_MC.REG  (
    .I(AD[7]),
    .CE(\FOOBAR9__ctinst/4 ),
    .CLK(\U4/ctrlr<7>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(\U4/ctrlr<7>_MC_tsimcreated_prld_ ),
    .O(\U4/ctrlr[7] )
  );
  X_INV \U4/ctrlr<7>_MC.REG_tsimcreated_inv_Mclk_II/FCLK_19  (
    .I(\Mclk_II/FCLK ),
    .O(\U4/ctrlr<7>_MC.REG_tsimcreated_inv_Mclk_II/FCLK )
  );
  X_BUF \AD<3>_II/UIM_20  (
    .I(AD[3]),
    .O(\AD<3>_II/UIM )
  );
  X_BUF \AD<3>_II/IREG_21  (
    .I(\U4/ctrlr[3] ),
    .O(\AD<3>_II/IREG )
  );
  X_OR2 \U4/ctrlr<3>_MC_tsimcreated_prld__22  (
    .I0(\FOOBAR12__ctinst/0 ),
    .I1(PRLD),
    .O(\U4/ctrlr<3>_MC_tsimcreated_prld_ )
  );
  X_FF \U4/ctrlr<3>_MC.REG  (
    .I(AD[3]),
    .CE(\FOOBAR12__ctinst/4 ),
    .CLK(\U4/ctrlr<3>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(\U4/ctrlr<3>_MC_tsimcreated_prld_ ),
    .O(\U4/ctrlr[3] )
  );
  X_INV \U4/ctrlr<3>_MC.REG_tsimcreated_inv_Mclk_II/FCLK_23  (
    .I(\Mclk_II/FCLK ),
    .O(\U4/ctrlr<3>_MC.REG_tsimcreated_inv_Mclk_II/FCLK )
  );
  X_BUF \AD<1>_II/UIM_24  (
    .I(AD[1]),
    .O(\AD<1>_II/UIM )
  );
  X_BUF \AD<2>_II/UIM_25  (
    .I(AD[2]),
    .O(\AD<2>_II/UIM )
  );
  X_BUF \AD<2>_II/IREG_26  (
    .I(\U4/ctrlr[2] ),
    .O(\AD<2>_II/IREG )
  );
  X_OR2 \U4/ctrlr<2>_MC_tsimcreated_prld__27  (
    .I0(\FOOBAR12__ctinst/0 ),
    .I1(PRLD),
    .O(\U4/ctrlr<2>_MC_tsimcreated_prld_ )
  );
  X_FF \U4/ctrlr<2>_MC.REG  (
    .I(AD[2]),
    .CE(\FOOBAR12__ctinst/4 ),
    .CLK(\U4/ctrlr<2>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(\U4/ctrlr<2>_MC_tsimcreated_prld_ ),
    .O(\U4/ctrlr[2] )
  );
  X_INV \U4/ctrlr<2>_MC.REG_tsimcreated_inv_Mclk_II/FCLK_28  (
    .I(\Mclk_II/FCLK ),
    .O(\U4/ctrlr<2>_MC.REG_tsimcreated_inv_Mclk_II/FCLK )
  );
  X_IPAD \SCLreset.PAD  (
    .PAD(SCLreset)
  );
  X_BUF \SCLreset_II/UIM_29  (
    .I(SCLreset),
    .O(\SCLreset_II/UIM )
  );
  X_BUF \SCLreset_II/IREG_30  (
    .I(\U11_U4/Line_last ),
    .O(\SCLreset_II/IREG )
  );
  X_FF \U11_U4/Line_last_MC.REG  (
    .I(SCLreset),
    .CE(Vcc),
    .CLK(\U11_U4/Line_last_MC.REG_tsimcreated_inv_Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\U11_U4/Line_last )
  );
  X_INV \U11_U4/Line_last_MC.REG_tsimcreated_inv_Mclk_II/FCLK_31  (
    .I(\Mclk_II/FCLK ),
    .O(\U11_U4/Line_last_MC.REG_tsimcreated_inv_Mclk_II/FCLK )
  );
  X_IPAD \SCLinc.PAD  (
    .PAD(SCLinc)
  );
  X_BUF \SCLinc_II/UIM_32  (
    .I(SCLinc),
    .O(\SCLinc_II/UIM )
  );
  X_BUF \SCLinc_II/IREG_33  (
    .I(\U11_U1/Line_last ),
    .O(\SCLinc_II/IREG )
  );
  X_FF \U11_U1/Line_last_MC.REG  (
    .I(SCLinc),
    .CE(Vcc),
    .CLK(\U11_U1/Line_last_MC.REG_tsimcreated_inv_Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\U11_U1/Line_last )
  );
  X_INV \U11_U1/Line_last_MC.REG_tsimcreated_inv_Mclk_II/FCLK_34  (
    .I(\Mclk_II/FCLK ),
    .O(\U11_U1/Line_last_MC.REG_tsimcreated_inv_Mclk_II/FCLK )
  );
  X_BUF \SCL_II/UIM_35  (
    .I(SCL),
    .O(\SCL_II/UIM )
  );
  X_BUF \SCL_II/IREG_36  (
    .I(\U11_U2/Line_last ),
    .O(\SCL_II/IREG )
  );
  X_FF \U11_U2/Line_last_MC.REG  (
    .I(SCL),
    .CE(Vcc),
    .CLK(\U11_U2/Line_last_MC.REG_tsimcreated_inv_Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\U11_U2/Line_last )
  );
  X_INV \U11_U2/Line_last_MC.REG_tsimcreated_inv_Mclk_II/FCLK_37  (
    .I(\Mclk_II/FCLK ),
    .O(\U11_U2/Line_last_MC.REG_tsimcreated_inv_Mclk_II/FCLK )
  );
  X_IPAD \PhaseA_Encoder0.PAD  (
    .PAD(PhaseA_Encoder0)
  );
  X_BUF \PhaseA_Encoder0_II/UIM_38  (
    .I(PhaseA_Encoder0),
    .O(\PhaseA_Encoder0_II/UIM )
  );
  X_IPAD \PhaseB_Encoder0.PAD  (
    .PAD(PhaseB_Encoder0)
  );
  X_BUF \PhaseB_Encoder0_II/UIM_39  (
    .I(PhaseB_Encoder0),
    .O(\PhaseB_Encoder0_II/UIM )
  );
  X_IPAD \GP_Motor0_0.PAD  (
    .PAD(GP_Motor0_0)
  );
  X_BUF \GP_Motor0_0_II/UIM_40  (
    .I(GP_Motor0_0),
    .O(\GP_Motor0_0_II/UIM )
  );
  X_BUF \GP_Motor0_0_II/IREG_41  (
    .I(\U1/U4/InEdge0r ),
    .O(\GP_Motor0_0_II/IREG )
  );
  X_FF \U1/U4/InEdge0r_MC.REG  (
    .I(GP_Motor0_0),
    .CE(Vcc),
    .CLK(\U1/U4/InEdge0r_MC.REG_tsimcreated_inv_Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\U1/U4/InEdge0r )
  );
  X_INV \U1/U4/InEdge0r_MC.REG_tsimcreated_inv_Mclk_II/FCLK_42  (
    .I(\Mclk_II/FCLK ),
    .O(\U1/U4/InEdge0r_MC.REG_tsimcreated_inv_Mclk_II/FCLK )
  );
  X_IPAD \PhaseB_Encoder1.PAD  (
    .PAD(PhaseB_Encoder1)
  );
  X_BUF \PhaseB_Encoder1_II/UIM_43  (
    .I(PhaseB_Encoder1),
    .O(\PhaseB_Encoder1_II/UIM )
  );
  X_IPAD \PhaseA_Encoder1.PAD  (
    .PAD(PhaseA_Encoder1)
  );
  X_BUF \PhaseA_Encoder1_II/UIM_44  (
    .I(PhaseA_Encoder1),
    .O(\PhaseA_Encoder1_II/UIM )
  );
  X_IPAD \GP_Motor1_0.PAD  (
    .PAD(GP_Motor1_0)
  );
  X_BUF \GP_Motor1_0_II/UIM_45  (
    .I(GP_Motor1_0),
    .O(\GP_Motor1_0_II/UIM )
  );
  X_BUF \GP_Motor1_0_II/IREG_46  (
    .I(\U1/U4/InEdge1r ),
    .O(\GP_Motor1_0_II/IREG )
  );
  X_FF \U1/U4/InEdge1r_MC.REG  (
    .I(GP_Motor1_0),
    .CE(Vcc),
    .CLK(\U1/U4/InEdge1r_MC.REG_tsimcreated_inv_Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\U1/U4/InEdge1r )
  );
  X_INV \U1/U4/InEdge1r_MC.REG_tsimcreated_inv_Mclk_II/FCLK_47  (
    .I(\Mclk_II/FCLK ),
    .O(\U1/U4/InEdge1r_MC.REG_tsimcreated_inv_Mclk_II/FCLK )
  );
  X_IPAD \I2CS<0>.PAD  (
    .PAD(I2CS[0])
  );
  X_BUF \I2CS<0>_II/UIM_48  (
    .I(I2CS[0]),
    .O(\I2CS<0>_II/UIM )
  );
  X_IPAD \Home033FLG.PAD  (
    .PAD(NlwRenamedSig_IO_Home033FLG)
  );
  X_PU Home033FLG_tsimcreated__pullup_ (
    .O(NlwRenamedSig_IO_Home033FLG)
  );
  X_BUF \Home033FLG_II/UIM_49  (
    .I(NlwRenamedSig_IO_Home033FLG),
    .O(\Home033FLG_II/UIM )
  );
  X_BUF \Home033FLG_II/IREG_50  (
    .I(\U4/Flgreg [0]),
    .O(\Home033FLG_II/IREG )
  );
  X_FF \U4/Flgreg<0>_MC.REG  (
    .I(NlwRenamedSig_IO_Home033FLG),
    .CE(\FOOBAR21__ctinst/4 ),
    .CLK(\U4/Flgreg<0>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\U4/Flgreg [0])
  );
  X_INV \U4/Flgreg<0>_MC.REG_tsimcreated_inv_Mclk_II/FCLK_51  (
    .I(\Mclk_II/FCLK ),
    .O(\U4/Flgreg<0>_MC.REG_tsimcreated_inv_Mclk_II/FCLK )
  );
  X_IPAD \Home15FLG.PAD  (
    .PAD(NlwRenamedSig_IO_Home15FLG)
  );
  X_PU Home15FLG_tsimcreated__pullup_ (
    .O(NlwRenamedSig_IO_Home15FLG)
  );
  X_BUF \Home15FLG_II/UIM_52  (
    .I(NlwRenamedSig_IO_Home15FLG),
    .O(\Home15FLG_II/UIM )
  );
  X_BUF \Home15FLG_II/IREG_53  (
    .I(\U4/Flgreg [5]),
    .O(\Home15FLG_II/IREG )
  );
  X_FF \U4/Flgreg<5>_MC.REG  (
    .I(NlwRenamedSig_IO_Home15FLG),
    .CE(\FOOBAR21__ctinst/4 ),
    .CLK(\U4/Flgreg<5>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\U4/Flgreg [5])
  );
  X_INV \U4/Flgreg<5>_MC.REG_tsimcreated_inv_Mclk_II/FCLK_54  (
    .I(\Mclk_II/FCLK ),
    .O(\U4/Flgreg<5>_MC.REG_tsimcreated_inv_Mclk_II/FCLK )
  );
  X_IPAD \Home133FLG.PAD  (
    .PAD(NlwRenamedSig_IO_Home133FLG)
  );
  X_PU Home133FLG_tsimcreated__pullup_ (
    .O(NlwRenamedSig_IO_Home133FLG)
  );
  X_BUF \Home133FLG_II/UIM_55  (
    .I(NlwRenamedSig_IO_Home133FLG),
    .O(\Home133FLG_II/UIM )
  );
  X_BUF \Home133FLG_II/IREG_56  (
    .I(\U4/Flgreg [4]),
    .O(\Home133FLG_II/IREG )
  );
  X_FF \U4/Flgreg<4>_MC.REG  (
    .I(NlwRenamedSig_IO_Home133FLG),
    .CE(\FOOBAR21__ctinst/4 ),
    .CLK(\U4/Flgreg<4>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\U4/Flgreg [4])
  );
  X_INV \U4/Flgreg<4>_MC.REG_tsimcreated_inv_Mclk_II/FCLK_57  (
    .I(\Mclk_II/FCLK ),
    .O(\U4/Flgreg<4>_MC.REG_tsimcreated_inv_Mclk_II/FCLK )
  );
  X_IPAD \Home05FLG.PAD  (
    .PAD(NlwRenamedSig_IO_Home05FLG)
  );
  X_PU Home05FLG_tsimcreated__pullup_ (
    .O(NlwRenamedSig_IO_Home05FLG)
  );
  X_BUF \Home05FLG_II/UIM_58  (
    .I(NlwRenamedSig_IO_Home05FLG),
    .O(\Home05FLG_II/UIM )
  );
  X_BUF \Home05FLG_II/IREG_59  (
    .I(\U4/Flgreg [1]),
    .O(\Home05FLG_II/IREG )
  );
  X_FF \U4/Flgreg<1>_MC.REG  (
    .I(NlwRenamedSig_IO_Home05FLG),
    .CE(\FOOBAR21__ctinst/4 ),
    .CLK(\U4/Flgreg<1>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\U4/Flgreg [1])
  );
  X_INV \U4/Flgreg<1>_MC.REG_tsimcreated_inv_Mclk_II/FCLK_60  (
    .I(\Mclk_II/FCLK ),
    .O(\U4/Flgreg<1>_MC.REG_tsimcreated_inv_Mclk_II/FCLK )
  );
  X_IPAD \Enc15FLG.PAD  (
    .PAD(NlwRenamedSig_IO_Enc15FLG)
  );
  X_PU Enc15FLG_tsimcreated__pullup_ (
    .O(NlwRenamedSig_IO_Enc15FLG)
  );
  X_BUF \Enc15FLG_II/UIM_61  (
    .I(NlwRenamedSig_IO_Enc15FLG),
    .O(\Enc15FLG_II/UIM )
  );
  X_BUF \Enc15FLG_II/IREG_62  (
    .I(\U4/Flgreg [7]),
    .O(\Enc15FLG_II/IREG )
  );
  X_FF \U4/Flgreg<7>_MC.REG  (
    .I(NlwRenamedSig_IO_Enc15FLG),
    .CE(\FOOBAR24__ctinst/4 ),
    .CLK(\U4/Flgreg<7>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\U4/Flgreg [7])
  );
  X_INV \U4/Flgreg<7>_MC.REG_tsimcreated_inv_Mclk_II/FCLK_63  (
    .I(\Mclk_II/FCLK ),
    .O(\U4/Flgreg<7>_MC.REG_tsimcreated_inv_Mclk_II/FCLK )
  );
  X_IPAD \Enc133FLG.PAD  (
    .PAD(NlwRenamedSig_IO_Enc133FLG)
  );
  X_PU Enc133FLG_tsimcreated__pullup_ (
    .O(NlwRenamedSig_IO_Enc133FLG)
  );
  X_BUF \Enc133FLG_II/UIM_64  (
    .I(NlwRenamedSig_IO_Enc133FLG),
    .O(\Enc133FLG_II/UIM )
  );
  X_BUF \Enc133FLG_II/IREG_65  (
    .I(\U4/Flgreg [6]),
    .O(\Enc133FLG_II/IREG )
  );
  X_FF \U4/Flgreg<6>_MC.REG  (
    .I(NlwRenamedSig_IO_Enc133FLG),
    .CE(\FOOBAR24__ctinst/4 ),
    .CLK(\U4/Flgreg<6>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\U4/Flgreg [6])
  );
  X_INV \U4/Flgreg<6>_MC.REG_tsimcreated_inv_Mclk_II/FCLK_66  (
    .I(\Mclk_II/FCLK ),
    .O(\U4/Flgreg<6>_MC.REG_tsimcreated_inv_Mclk_II/FCLK )
  );
  X_IPAD \Enc05FLG.PAD  (
    .PAD(NlwRenamedSig_IO_Enc05FLG)
  );
  X_PU Enc05FLG_tsimcreated__pullup_ (
    .O(NlwRenamedSig_IO_Enc05FLG)
  );
  X_BUF \Enc05FLG_II/UIM_67  (
    .I(NlwRenamedSig_IO_Enc05FLG),
    .O(\Enc05FLG_II/UIM )
  );
  X_BUF \Enc05FLG_II/IREG_68  (
    .I(\U4/Flgreg [3]),
    .O(\Enc05FLG_II/IREG )
  );
  X_FF \U4/Flgreg<3>_MC.REG  (
    .I(NlwRenamedSig_IO_Enc05FLG),
    .CE(\FOOBAR24__ctinst/4 ),
    .CLK(\U4/Flgreg<3>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\U4/Flgreg [3])
  );
  X_INV \U4/Flgreg<3>_MC.REG_tsimcreated_inv_Mclk_II/FCLK_69  (
    .I(\Mclk_II/FCLK ),
    .O(\U4/Flgreg<3>_MC.REG_tsimcreated_inv_Mclk_II/FCLK )
  );
  X_IPAD \Enc033FLG.PAD  (
    .PAD(NlwRenamedSig_IO_Enc033FLG)
  );
  X_PU Enc033FLG_tsimcreated__pullup_ (
    .O(NlwRenamedSig_IO_Enc033FLG)
  );
  X_BUF \Enc033FLG_II/UIM_70  (
    .I(NlwRenamedSig_IO_Enc033FLG),
    .O(\Enc033FLG_II/UIM )
  );
  X_BUF \Enc033FLG_II/IREG_71  (
    .I(\U4/Flgreg [2]),
    .O(\Enc033FLG_II/IREG )
  );
  X_FF \U4/Flgreg<2>_MC.REG  (
    .I(NlwRenamedSig_IO_Enc033FLG),
    .CE(\FOOBAR24__ctinst/4 ),
    .CLK(\U4/Flgreg<2>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\U4/Flgreg [2])
  );
  X_INV \U4/Flgreg<2>_MC.REG_tsimcreated_inv_Mclk_II/FCLK_72  (
    .I(\Mclk_II/FCLK ),
    .O(\U4/Flgreg<2>_MC.REG_tsimcreated_inv_Mclk_II/FCLK )
  );
  X_IPAD \INTbus.PAD  (
    .PAD(INTbus)
  );
  X_BUF \INTbus_II/UIM_73  (
    .I(INTbus),
    .O(\INTbus_II/UIM )
  );
  X_IPAD \RLS0.PAD  (
    .PAD(RLS0)
  );
  X_BUF \RLS0_II/UIM_74  (
    .I(RLS0),
    .O(\RLS0_II/UIM )
  );
  X_IPAD \DIR0.PAD  (
    .PAD(DIR0)
  );
  X_BUF \DIR0_II/UIM_75  (
    .I(DIR0),
    .O(\DIR0_II/UIM )
  );
  X_IPAD \I2CS<1>.PAD  (
    .PAD(I2CS[1])
  );
  X_BUF \I2CS<1>_II/UIM_76  (
    .I(I2CS[1]),
    .O(\I2CS<1>_II/UIM )
  );
  X_IPAD \FLS0.PAD  (
    .PAD(FLS0)
  );
  X_BUF \FLS0_II/UIM_77  (
    .I(FLS0),
    .O(\FLS0_II/UIM )
  );
  X_IPAD \I2CS<4>.PAD  (
    .PAD(I2CS[4])
  );
  X_BUF \I2CS<4>_II/UIM_78  (
    .I(I2CS[4]),
    .O(\I2CS<4>_II/UIM )
  );
  X_IPAD \DIR1.PAD  (
    .PAD(DIR1)
  );
  X_BUF \DIR1_II/UIM_79  (
    .I(DIR1),
    .O(\DIR1_II/UIM )
  );
  X_IPAD \FLS1.PAD  (
    .PAD(FLS1)
  );
  X_BUF \FLS1_II/UIM_80  (
    .I(FLS1),
    .O(\FLS1_II/UIM )
  );
  X_IPAD \RLS1.PAD  (
    .PAD(RLS1)
  );
  X_BUF \RLS1_II/UIM_81  (
    .I(RLS1),
    .O(\RLS1_II/UIM )
  );
  X_IPAD \I2CS<5>.PAD  (
    .PAD(I2CS[5])
  );
  X_BUF \I2CS<5>_II/UIM_82  (
    .I(I2CS[5]),
    .O(\I2CS<5>_II/UIM )
  );
  X_IPAD \Brake0.PAD  (
    .PAD(Brake0)
  );
  X_BUF \Brake0_II/UIM_83  (
    .I(Brake0),
    .O(\Brake0_II/UIM )
  );
  X_IPAD \Brake1.PAD  (
    .PAD(Brake1)
  );
  X_BUF \Brake1_II/UIM_84  (
    .I(Brake1),
    .O(\Brake1_II/UIM )
  );
  X_IPAD \PWM5.PAD  (
    .PAD(PWM5)
  );
  X_BUF \PWM5_II/UIM_85  (
    .I(PWM5),
    .O(\PWM5_II/UIM )
  );
  X_IPAD \PWM3.PAD  (
    .PAD(PWM3)
  );
  X_BUF \PWM3_II/UIM_86  (
    .I(PWM3),
    .O(\PWM3_II/UIM )
  );
  X_IPAD \MReset.PAD  (
    .PAD(MReset)
  );
  X_BUF \MReset_II/UIM_87  (
    .I(MReset),
    .O(\MReset_II/UIM )
  );
  X_IPAD \HSI.PAD  (
    .PAD(HSI)
  );
  X_BUF \HSI_II/UIM_88  (
    .I(HSI),
    .O(\HSI_II/UIM )
  );
  X_IPAD \MHSO.PAD  (
    .PAD(MHSO)
  );
  X_BUF \MHSO_II/UIM_89  (
    .I(MHSO),
    .O(\MHSO_II/UIM )
  );
  X_IPAD \I2CS<2>.PAD  (
    .PAD(I2CS[2])
  );
  X_BUF \I2CS<2>_II/UIM_90  (
    .I(I2CS[2]),
    .O(\I2CS<2>_II/UIM )
  );
  X_IPAD \I2CS<3>.PAD  (
    .PAD(I2CS[3])
  );
  X_BUF \I2CS<3>_II/UIM_91  (
    .I(I2CS[3]),
    .O(\I2CS<3>_II/UIM )
  );
  X_IPAD \LightSense.PAD  (
    .PAD(LightSense)
  );
  X_BUF \LightSense_II/UIM_92  (
    .I(LightSense),
    .O(\LightSense_II/UIM )
  );
  X_IPAD \TXI.PAD  (
    .PAD(TXI)
  );
  X_BUF \TXI_II/UIM_93  (
    .I(TXI),
    .O(\TXI_II/UIM )
  );
  X_IPAD \PWM1.PAD  (
    .PAD(PWM1)
  );
  X_BUF \PWM1_II/UIM_94  (
    .I(PWM1),
    .O(\PWM1_II/UIM )
  );
  X_IPAD \PWM2.PAD  (
    .PAD(PWM2)
  );
  X_BUF \PWM2_II/UIM_95  (
    .I(PWM2),
    .O(\PWM2_II/UIM )
  );
  X_IPAD \Home0.PAD  (
    .PAD(Home0)
  );
  X_BUF \Home0_II/UIM_96  (
    .I(Home0),
    .O(\Home0_II/UIM )
  );
  X_BUF \Home0_II/IREG_97  (
    .I(\U1/U4/HE0stater ),
    .O(\Home0_II/IREG )
  );
  X_FF \U1/U4/HE0stater_MC.REG  (
    .I(Home0),
    .CE(Vcc),
    .CLK(\U1/U4/HE0stater_MC.REG_tsimcreated_inv_Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\U1/U4/HE0stater )
  );
  X_INV \U1/U4/HE0stater_MC.REG_tsimcreated_inv_Mclk_II/FCLK_98  (
    .I(\Mclk_II/FCLK ),
    .O(\U1/U4/HE0stater_MC.REG_tsimcreated_inv_Mclk_II/FCLK )
  );
  X_IPAD \Home1.PAD  (
    .PAD(Home1)
  );
  X_BUF \Home1_II/UIM_99  (
    .I(Home1),
    .O(\Home1_II/UIM )
  );
  X_BUF \Home1_II/IREG_100  (
    .I(\U1/U4/HE1stater ),
    .O(\Home1_II/IREG )
  );
  X_FF \U1/U4/HE1stater_MC.REG  (
    .I(Home1),
    .CE(Vcc),
    .CLK(\U1/U4/HE1stater_MC.REG_tsimcreated_inv_Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\U1/U4/HE1stater )
  );
  X_INV \U1/U4/HE1stater_MC.REG_tsimcreated_inv_Mclk_II/FCLK_101  (
    .I(\Mclk_II/FCLK ),
    .O(\U1/U4/HE1stater_MC.REG_tsimcreated_inv_Mclk_II/FCLK )
  );
  X_BPAD \AD<0>.PAD  (
    .PAD(AD[0])
  );
  X_TRI \AD<0>  (
    .I(\AD<0>_MC.Q ),
    .CTL(\AD<0>_MC.OE ),
    .O(AD[0])
  );
  X_BPAD \AD<1>.PAD  (
    .PAD(AD[1])
  );
  X_TRI \AD<1>  (
    .I(\AD<1>_MC.Q ),
    .CTL(\AD<1>_MC.OE ),
    .O(AD[1])
  );
  X_BPAD \AD<4>.PAD  (
    .PAD(AD[4])
  );
  X_TRI \AD<4>  (
    .I(\AD<4>_MC.Q ),
    .CTL(\AD<4>_MC.OE ),
    .O(AD[4])
  );
  X_BPAD \AD<5>.PAD  (
    .PAD(AD[5])
  );
  X_TRI \AD<5>  (
    .I(\AD<5>_MC.Q ),
    .CTL(\AD<5>_MC.OE ),
    .O(AD[5])
  );
  X_OPAD \Enc033ctrl.PAD  (
    .PAD(Enc033ctrl)
  );
  X_BUF Enc033ctrl_102 (
    .I(\Enc033ctrl_MC.Q ),
    .O(Enc033ctrl)
  );
  X_OPAD \Enc05ctrl.PAD  (
    .PAD(Enc05ctrl)
  );
  X_BUF Enc05ctrl_103 (
    .I(\Enc05ctrl_MC.Q ),
    .O(Enc05ctrl)
  );
  X_OPAD \Enc133ctrl.PAD  (
    .PAD(Enc133ctrl)
  );
  X_BUF Enc133ctrl_104 (
    .I(\Enc133ctrl_MC.Q ),
    .O(Enc133ctrl)
  );
  X_OPAD \Enc15ctrl.PAD  (
    .PAD(Enc15ctrl)
  );
  X_BUF Enc15ctrl_105 (
    .I(\Enc15ctrl_MC.Q ),
    .O(Enc15ctrl)
  );
  X_OPAD \GPIO8.PAD  (
    .PAD(GPIO8)
  );
  X_BUF GPIO8_106 (
    .I(\GPIO8_MC.Q ),
    .O(GPIO8)
  );
  X_OPAD \GPIO9.PAD  (
    .PAD(GPIO9)
  );
  X_BUF GPIO9_107 (
    .I(\GPIO9_MC.Q ),
    .O(GPIO9)
  );
  X_OPAD \GP_Motor0_1.PAD  (
    .PAD(GP_Motor0_1)
  );
  X_BUF GP_Motor0_1_108 (
    .I(\GP_Motor0_1_MC.Q ),
    .O(GP_Motor0_1)
  );
  X_OPAD \GP_Motor1_1.PAD  (
    .PAD(GP_Motor1_1)
  );
  X_BUF GP_Motor1_1_109 (
    .I(\GP_Motor1_1_MC.Q ),
    .O(GP_Motor1_1)
  );
  X_OPAD \HSO.PAD  (
    .PAD(HSO)
  );
  X_BUF HSO_110 (
    .I(\HSO_MC.Q ),
    .O(HSO)
  );
  X_OPAD \Home033ctrl.PAD  (
    .PAD(Home033ctrl)
  );
  X_BUF Home033ctrl_111 (
    .I(\Home033ctrl_MC.Q ),
    .O(Home033ctrl)
  );
  X_OPAD \Home05ctrl.PAD  (
    .PAD(Home05ctrl)
  );
  X_BUF Home05ctrl_112 (
    .I(\Home05ctrl_MC.Q ),
    .O(Home05ctrl)
  );
  X_OPAD \Home133ctrl.PAD  (
    .PAD(Home133ctrl)
  );
  X_BUF Home133ctrl_113 (
    .I(\Home133ctrl_MC.Q ),
    .O(Home133ctrl)
  );
  X_OPAD \Home15ctrl.PAD  (
    .PAD(Home15ctrl)
  );
  X_BUF Home15ctrl_114 (
    .I(\Home15ctrl_MC.Q ),
    .O(Home15ctrl)
  );
  X_OPAD \INT.PAD  (
    .PAD(INT)
  );
  X_BUF INT_115 (
    .I(\INT_MC.Q ),
    .O(INT)
  );
  X_OPAD \LED1.PAD  (
    .PAD(LED1)
  );
  X_BUF LED1_116 (
    .I(\LED1_MC.Q ),
    .O(LED1)
  );
  X_OPAD \LED2.PAD  (
    .PAD(LED2)
  );
  X_BUF LED2_117 (
    .I(\LED2_MC.Q ),
    .O(LED2)
  );
  X_OPAD \LED3.PAD  (
    .PAD(LED3)
  );
  X_BUF LED3_118 (
    .I(\LED3_MC.Q ),
    .O(LED3)
  );
  X_OPAD \LED4.PAD  (
    .PAD(LED4)
  );
  X_BUF LED4_119 (
    .I(\LED4_MC.Q ),
    .O(LED4)
  );
  X_OPAD \LED5.PAD  (
    .PAD(LED5)
  );
  X_BUF LED5_120 (
    .I(\LED5_MC.Q ),
    .O(LED5)
  );
  X_OPAD \MHSI.PAD  (
    .PAD(MHSI)
  );
  X_BUF MHSI_121 (
    .I(\MHSI_MC.Q ),
    .O(MHSI)
  );
  X_OPAD \MTRpwr.PAD  (
    .PAD(MTRpwr)
  );
  X_BUF MTRpwr_122 (
    .I(\MTRpwr_MC.Q ),
    .O(MTRpwr)
  );
  X_OPAD \MTRpwrn.PAD  (
    .PAD(MTRpwrn)
  );
  X_BUF MTRpwrn_123 (
    .I(\MTRpwrn_MC.Q ),
    .O(MTRpwrn)
  );
  X_OPAD \MTXI.PAD  (
    .PAD(MTXI)
  );
  X_BUF MTXI_124 (
    .I(\MTXI_MC.Q ),
    .O(MTXI)
  );
  X_OPAD \PAH0.PAD  (
    .PAD(PAH0)
  );
  X_BUF PAH0_125 (
    .I(\PAH0_MC.Q ),
    .O(PAH0)
  );
  X_OPAD \PAH1.PAD  (
    .PAD(PAH1)
  );
  X_BUF PAH1_126 (
    .I(\PAH1_MC.Q ),
    .O(PAH1)
  );
  X_OPAD \PAL0.PAD  (
    .PAD(PAL0)
  );
  X_BUF PAL0_127 (
    .I(\PAL0_MC.Q ),
    .O(PAL0)
  );
  X_OPAD \PAL1.PAD  (
    .PAD(PAL1)
  );
  X_BUF PAL1_128 (
    .I(\PAL1_MC.Q ),
    .O(PAL1)
  );
  X_OPAD \PBH0.PAD  (
    .PAD(PBH0)
  );
  X_BUF PBH0_129 (
    .I(\PBH0_MC.Q ),
    .O(PBH0)
  );
  X_OPAD \PBH1.PAD  (
    .PAD(PBH1)
  );
  X_BUF PBH1_130 (
    .I(\PBH1_MC.Q ),
    .O(PBH1)
  );
  X_OPAD \PBL0.PAD  (
    .PAD(PBL0)
  );
  X_BUF PBL0_131 (
    .I(\PBL0_MC.Q ),
    .O(PBL0)
  );
  X_OPAD \PBL1.PAD  (
    .PAD(PBL1)
  );
  X_BUF PBL1_132 (
    .I(\PBL1_MC.Q ),
    .O(PBL1)
  );
  X_OPAD \PresEn.PAD  (
    .PAD(PresEn)
  );
  X_BUF PresEn_133 (
    .I(\PresEn_MC.Q ),
    .O(PresEn)
  );
  X_OPAD \PresSlct.PAD  (
    .PAD(PresSlct)
  );
  X_BUF PresSlct_134 (
    .I(\PresSlct_MC.Q ),
    .O(PresSlct)
  );
  X_OPAD \SCLout.PAD  (
    .PAD(SCLout)
  );
  X_BUF SCLout_135 (
    .I(\SCLout_MC.Q ),
    .O(SCLout)
  );
  X_OPAD \TP10.PAD  (
    .PAD(TP10)
  );
  X_BUF TP10_136 (
    .I(\TP10_MC.Q ),
    .O(TP10)
  );
  X_OPAD \TP11.PAD  (
    .PAD(TP11)
  );
  X_BUF TP11_137 (
    .I(\TP11_MC.Q ),
    .O(TP11)
  );
  X_OPAD \TP12.PAD  (
    .PAD(TP12)
  );
  X_BUF TP12_138 (
    .I(\TP12_MC.Q ),
    .O(TP12)
  );
  X_OPAD \TmpEn.PAD  (
    .PAD(TmpEn)
  );
  X_BUF TmpEn_139 (
    .I(\TmpEn_MC.Q ),
    .O(TmpEn)
  );
  X_OPAD \TmpSlct.PAD  (
    .PAD(TmpSlct)
  );
  X_BUF TmpSlct_140 (
    .I(\TmpSlct_MC.Q ),
    .O(TmpSlct)
  );
  X_BPAD \SCL.PAD  (
    .PAD(SCL)
  );
  X_TRI SCL_141 (
    .I(\U11_U2/Line_last_MC.Q ),
    .CTL(\U11_U2/Line_last_MC.OE ),
    .O(SCL)
  );
  X_BPAD \AD<2>.PAD  (
    .PAD(AD[2])
  );
  X_TRI \AD<2>  (
    .I(\U4/ctrlr<2>_MC.Q ),
    .CTL(\U4/ctrlr<2>_MC.OE ),
    .O(AD[2])
  );
  X_BPAD \AD<3>.PAD  (
    .PAD(AD[3])
  );
  X_TRI \AD<3>  (
    .I(\U4/ctrlr<3>_MC.Q ),
    .CTL(\U4/ctrlr<3>_MC.OE ),
    .O(AD[3])
  );
  X_BPAD \AD<6>.PAD  (
    .PAD(AD[6])
  );
  X_TRI \AD<6>  (
    .I(\U4/ctrlr<6>_MC.Q ),
    .CTL(\U4/ctrlr<6>_MC.OE ),
    .O(AD[6])
  );
  X_BPAD \AD<7>.PAD  (
    .PAD(AD[7])
  );
  X_TRI \AD<7>  (
    .I(\U4/ctrlr<7>_MC.Q ),
    .CTL(\U4/ctrlr<7>_MC.OE ),
    .O(AD[7])
  );
  X_BUF \AD<0>_MC.Q_142  (
    .I(\AD<0>_MC.Q_tsimrenamed_net_ ),
    .O(\AD<0>_MC.Q )
  );
  X_BUF \AD<0>_MC.OE_143  (
    .I(\AD<0>_MC.BUFOE.OUT ),
    .O(\AD<0>_MC.OE )
  );
  X_BUF \AD<0>_MC.BUFOE.OUT_144  (
    .I(\FOOBAR1__ctinst/7 ),
    .O(\AD<0>_MC.BUFOE.OUT )
  );
  X_BUF \AD<0>_MC.Q_tsimrenamed_net__145  (
    .I(\AD<0>_MC.D ),
    .O(\AD<0>_MC.Q_tsimrenamed_net_ )
  );
  X_XOR2 \AD<0>_MC.D_146  (
    .I0(\NlwInverterSignal_AD<0>_MC.D/IN0 ),
    .I1(\AD<0>_MC.D2 ),
    .O(\AD<0>_MC.D )
  );
  X_ZERO \AD<0>_MC.D1_147  (
    .O(\AD<0>_MC.D1 )
  );
  X_AND2 \AD<0>_MC.D2_PT_0_148  (
    .I0(DCORI2CCNTr),
    .I1(\NlwInverterSignal_AD<0>_MC.D2_PT_0/IN1 ),
    .O(\AD<0>_MC.D2_PT_0 )
  );
  X_AND2 \AD<0>_MC.D2_PT_1_149  (
    .I0(DCOR0THRESLOWr),
    .I1(\NlwInverterSignal_AD<0>_MC.D2_PT_1/IN1 ),
    .O(\AD<0>_MC.D2_PT_1 )
  );
  X_AND2 \AD<0>_MC.D2_PT_2_150  (
    .I0(DCORCONFIGr),
    .I1(\NlwInverterSignal_AD<0>_MC.D2_PT_2/IN1 ),
    .O(\AD<0>_MC.D2_PT_2 )
  );
  X_AND2 \AD<0>_MC.D2_PT_3_151  (
    .I0(DCORENCPWRr),
    .I1(\NlwInverterSignal_AD<0>_MC.D2_PT_3/IN1 ),
    .O(\AD<0>_MC.D2_PT_3 )
  );
  X_AND2 \AD<0>_MC.D2_PT_4_152  (
    .I0(DCORIFGr),
    .I1(\NlwInverterSignal_AD<0>_MC.D2_PT_4/IN1 ),
    .O(\AD<0>_MC.D2_PT_4 )
  );
  X_AND2 \AD<0>_MC.D2_PT_5_153  (
    .I0(\NlwInverterSignal_AD<0>_MC.D2_PT_5/IN0 ),
    .I1(\NlwInverterSignal_AD<0>_MC.D2_PT_5/IN1 ),
    .O(\AD<0>_MC.D2_PT_5 )
  );
  X_AND2 \AD<0>_MC.D2_PT_6_154  (
    .I0(\NlwInverterSignal_AD<0>_MC.D2_PT_6/IN0 ),
    .I1(\NlwInverterSignal_AD<0>_MC.D2_PT_6/IN1 ),
    .O(\AD<0>_MC.D2_PT_6 )
  );
  X_AND3 \AD<0>_MC.D2_PT_7_155  (
    .I0(\NlwInverterSignal_AD<0>_MC.D2_PT_7/IN0 ),
    .I1(\NlwInverterSignal_AD<0>_MC.D2_PT_7/IN1 ),
    .I2(\NlwInverterSignal_AD<0>_MC.D2_PT_7/IN2 ),
    .O(\AD<0>_MC.D2_PT_7 )
  );
  X_OR8 \AD<0>_MC.D2_156  (
    .I0(\AD<0>_MC.D2_PT_0 ),
    .I1(\AD<0>_MC.D2_PT_1 ),
    .I2(\AD<0>_MC.D2_PT_2 ),
    .I3(\AD<0>_MC.D2_PT_3 ),
    .I4(\AD<0>_MC.D2_PT_4 ),
    .I5(\AD<0>_MC.D2_PT_5 ),
    .I6(\AD<0>_MC.D2_PT_6 ),
    .I7(\AD<0>_MC.D2_PT_7 ),
    .O(\AD<0>_MC.D2 )
  );
  X_BUF DCORI2CCNTr_157 (
    .I(\DCORI2CCNTr_MC.Q ),
    .O(DCORI2CCNTr)
  );
  X_BUF \DCORI2CCNTr_MC.Q_158  (
    .I(\DCORI2CCNTr_MC.D ),
    .O(\DCORI2CCNTr_MC.Q )
  );
  X_XOR2 \DCORI2CCNTr_MC.D_159  (
    .I0(\DCORI2CCNTr_MC.D1 ),
    .I1(\DCORI2CCNTr_MC.D2 ),
    .O(\DCORI2CCNTr_MC.D )
  );
  X_AND16 \DCORI2CCNTr_MC.D1_160  (
    .I0(\WR_II/UIM ),
    .I1(\NlwInverterSignal_DCORI2CCNTr_MC.D1/IN1 ),
    .I2(\NlwInverterSignal_DCORI2CCNTr_MC.D1/IN2 ),
    .I3(\NlwInverterSignal_DCORI2CCNTr_MC.D1/IN3 ),
    .I4(\NlwInverterSignal_DCORI2CCNTr_MC.D1/IN4 ),
    .I5(\NlwInverterSignal_DCORI2CCNTr_MC.D1/IN5 ),
    .I6(\NlwInverterSignal_DCORI2CCNTr_MC.D1/IN6 ),
    .I7(\NlwInverterSignal_DCORI2CCNTr_MC.D1/IN7 ),
    .I8(\NlwInverterSignal_DCORI2CCNTr_MC.D1/IN8 ),
    .I9(\NlwInverterSignal_DCORI2CCNTr_MC.D1/IN9 ),
    .I10(Vcc),
    .I11(Vcc),
    .I12(Vcc),
    .I13(Vcc),
    .I14(Vcc),
    .I15(Vcc),
    .O(\DCORI2CCNTr_MC.D1 )
  );
  X_ZERO \DCORI2CCNTr_MC.D2_161  (
    .O(\DCORI2CCNTr_MC.D2 )
  );
  X_BUF \U2_ADDR_reg<0>  (
    .I(\U2_ADDR_reg<0>_MC.Q ),
    .O(U2_ADDR_reg[0])
  );
  X_XOR2 \U2_ADDR_reg<0>_MC_tsimcreated_xor__162  (
    .I0(\U2_ADDR_reg<0>_MC.D ),
    .I1(\U2_ADDR_reg<0>_MC.Q ),
    .O(\U2_ADDR_reg<0>_MC_tsimcreated_xor_ )
  );
  X_FF \U2_ADDR_reg<0>_MC.REG  (
    .I(\U2_ADDR_reg<0>_MC_tsimcreated_xor_ ),
    .CE(Vcc),
    .CLK(\U2_ADDR_reg<0>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\U2_ADDR_reg<0>_MC.Q )
  );
  X_INV \U2_ADDR_reg<0>_MC.REG_tsimcreated_inv_Mclk_II/FCLK_163  (
    .I(\Mclk_II/FCLK ),
    .O(\U2_ADDR_reg<0>_MC.REG_tsimcreated_inv_Mclk_II/FCLK )
  );
  X_XOR2 \U2_ADDR_reg<0>_MC.D_164  (
    .I0(\U2_ADDR_reg<0>_MC.D1 ),
    .I1(\U2_ADDR_reg<0>_MC.D2 ),
    .O(\U2_ADDR_reg<0>_MC.D )
  );
  X_ZERO \U2_ADDR_reg<0>_MC.D1_165  (
    .O(\U2_ADDR_reg<0>_MC.D1 )
  );
  X_AND2 \U2_ADDR_reg<0>_MC.D2_PT_0_166  (
    .I0(U2_ADDR_reg[0]),
    .I1(\NlwInverterSignal_U2_ADDR_reg<0>_MC.D2_PT_0/IN1 ),
    .O(\U2_ADDR_reg<0>_MC.D2_PT_0 )
  );
  X_AND6 \U2_ADDR_reg<0>_MC.D2_PT_1_167  (
    .I0(\WR_II/UIM ),
    .I1(\RD_II/UIM ),
    .I2(U2_ADDR_reg[0]),
    .I3(\NlwInverterSignal_U2_ADDR_reg<0>_MC.D2_PT_1/IN3 ),
    .I4(\NlwInverterSignal_U2_ADDR_reg<0>_MC.D2_PT_1/IN4 ),
    .I5(U2_ASedge),
    .O(\U2_ADDR_reg<0>_MC.D2_PT_1 )
  );
  X_AND7 \U2_ADDR_reg<0>_MC.D2_PT_2_168  (
    .I0(\WR_II/UIM ),
    .I1(\RD_II/UIM ),
    .I2(\NlwInverterSignal_U2_ADDR_reg<0>_MC.D2_PT_2/IN2 ),
    .I3(\MSPReset_II/UIM ),
    .I4(\AD<0>_II/UIM ),
    .I5(\NlwInverterSignal_U2_ADDR_reg<0>_MC.D2_PT_2/IN5 ),
    .I6(U2_ASedge),
    .O(\U2_ADDR_reg<0>_MC.D2_PT_2 )
  );
  X_AND16 \U2_ADDR_reg<0>_MC.D2_PT_3_169  (
    .I0(\WR_II/UIM ),
    .I1(\RD_II/UIM ),
    .I2(\NlwInverterSignal_U2_ADDR_reg<0>_MC.D2_PT_3/IN2 ),
    .I3(\NlwInverterSignal_U2_ADDR_reg<0>_MC.D2_PT_3/IN3 ),
    .I4(\NlwInverterSignal_U2_ADDR_reg<0>_MC.D2_PT_3/IN4 ),
    .I5(\NlwInverterSignal_U2_ADDR_reg<0>_MC.D2_PT_3/IN5 ),
    .I6(U2_AutoInc),
    .I7(\NlwInverterSignal_U2_ADDR_reg<0>_MC.D2_PT_3/IN7 ),
    .I8(N_PZ_992),
    .I9(Vcc),
    .I10(Vcc),
    .I11(Vcc),
    .I12(Vcc),
    .I13(Vcc),
    .I14(Vcc),
    .I15(Vcc),
    .O(\U2_ADDR_reg<0>_MC.D2_PT_3 )
  );
  X_OR4 \U2_ADDR_reg<0>_MC.D2_170  (
    .I0(\U2_ADDR_reg<0>_MC.D2_PT_0 ),
    .I1(\U2_ADDR_reg<0>_MC.D2_PT_1 ),
    .I2(\U2_ADDR_reg<0>_MC.D2_PT_2 ),
    .I3(\U2_ADDR_reg<0>_MC.D2_PT_3 ),
    .O(\U2_ADDR_reg<0>_MC.D2 )
  );
  X_BUF \U2_ADDR_reg<4>  (
    .I(\U2_ADDR_reg<4>_MC.Q ),
    .O(U2_ADDR_reg[4])
  );
  X_XOR2 \U2_ADDR_reg<4>_MC_tsimcreated_xor__171  (
    .I0(\U2_ADDR_reg<4>_MC.D ),
    .I1(\U2_ADDR_reg<4>_MC.Q ),
    .O(\U2_ADDR_reg<4>_MC_tsimcreated_xor_ )
  );
  X_FF \U2_ADDR_reg<4>_MC.REG  (
    .I(\U2_ADDR_reg<4>_MC_tsimcreated_xor_ ),
    .CE(Vcc),
    .CLK(\U2_ADDR_reg<4>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\U2_ADDR_reg<4>_MC.Q )
  );
  X_INV \U2_ADDR_reg<4>_MC.REG_tsimcreated_inv_Mclk_II/FCLK_172  (
    .I(\Mclk_II/FCLK ),
    .O(\U2_ADDR_reg<4>_MC.REG_tsimcreated_inv_Mclk_II/FCLK )
  );
  X_XOR2 \U2_ADDR_reg<4>_MC.D_173  (
    .I0(\U2_ADDR_reg<4>_MC.D1 ),
    .I1(\U2_ADDR_reg<4>_MC.D2 ),
    .O(\U2_ADDR_reg<4>_MC.D )
  );
  X_ZERO \U2_ADDR_reg<4>_MC.D1_174  (
    .O(\U2_ADDR_reg<4>_MC.D1 )
  );
  X_AND2 \U2_ADDR_reg<4>_MC.D2_PT_0_175  (
    .I0(U2_ADDR_reg[4]),
    .I1(\NlwInverterSignal_U2_ADDR_reg<4>_MC.D2_PT_0/IN1 ),
    .O(\U2_ADDR_reg<4>_MC.D2_PT_0 )
  );
  X_AND6 \U2_ADDR_reg<4>_MC.D2_PT_1_176  (
    .I0(\WR_II/UIM ),
    .I1(\RD_II/UIM ),
    .I2(U2_ADDR_reg[4]),
    .I3(\NlwInverterSignal_U2_ADDR_reg<4>_MC.D2_PT_1/IN3 ),
    .I4(U2_ASedge),
    .I5(\NlwInverterSignal_U2_ADDR_reg<4>_MC.D2_PT_1/IN5 ),
    .O(\U2_ADDR_reg<4>_MC.D2_PT_1 )
  );
  X_AND7 \U2_ADDR_reg<4>_MC.D2_PT_2_177  (
    .I0(\WR_II/UIM ),
    .I1(\RD_II/UIM ),
    .I2(\NlwInverterSignal_U2_ADDR_reg<4>_MC.D2_PT_2/IN2 ),
    .I3(\MSPReset_II/UIM ),
    .I4(\NlwInverterSignal_U2_ADDR_reg<4>_MC.D2_PT_2/IN4 ),
    .I5(U2_ASedge),
    .I6(\AD<4>_II/UIM ),
    .O(\U2_ADDR_reg<4>_MC.D2_PT_2 )
  );
  X_OR3 \U2_ADDR_reg<4>_MC.D2_178  (
    .I0(\U2_ADDR_reg<4>_MC.D2_PT_0 ),
    .I1(\U2_ADDR_reg<4>_MC.D2_PT_1 ),
    .I2(\U2_ADDR_reg<4>_MC.D2_PT_2 ),
    .O(\U2_ADDR_reg<4>_MC.D2 )
  );
  X_BUF \U2_ADDR_reg<5>  (
    .I(\U2_ADDR_reg<5>_MC.Q ),
    .O(U2_ADDR_reg[5])
  );
  X_XOR2 \U2_ADDR_reg<5>_MC_tsimcreated_xor__179  (
    .I0(\U2_ADDR_reg<5>_MC.D ),
    .I1(\U2_ADDR_reg<5>_MC.Q ),
    .O(\U2_ADDR_reg<5>_MC_tsimcreated_xor_ )
  );
  X_FF \U2_ADDR_reg<5>_MC.REG  (
    .I(\U2_ADDR_reg<5>_MC_tsimcreated_xor_ ),
    .CE(Vcc),
    .CLK(\U2_ADDR_reg<5>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\U2_ADDR_reg<5>_MC.Q )
  );
  X_INV \U2_ADDR_reg<5>_MC.REG_tsimcreated_inv_Mclk_II/FCLK_180  (
    .I(\Mclk_II/FCLK ),
    .O(\U2_ADDR_reg<5>_MC.REG_tsimcreated_inv_Mclk_II/FCLK )
  );
  X_XOR2 \U2_ADDR_reg<5>_MC.D_181  (
    .I0(\U2_ADDR_reg<5>_MC.D1 ),
    .I1(\U2_ADDR_reg<5>_MC.D2 ),
    .O(\U2_ADDR_reg<5>_MC.D )
  );
  X_ZERO \U2_ADDR_reg<5>_MC.D1_182  (
    .O(\U2_ADDR_reg<5>_MC.D1 )
  );
  X_AND2 \U2_ADDR_reg<5>_MC.D2_PT_0_183  (
    .I0(U2_ADDR_reg[5]),
    .I1(\NlwInverterSignal_U2_ADDR_reg<5>_MC.D2_PT_0/IN1 ),
    .O(\U2_ADDR_reg<5>_MC.D2_PT_0 )
  );
  X_AND6 \U2_ADDR_reg<5>_MC.D2_PT_1_184  (
    .I0(\WR_II/UIM ),
    .I1(\RD_II/UIM ),
    .I2(U2_ADDR_reg[5]),
    .I3(\NlwInverterSignal_U2_ADDR_reg<5>_MC.D2_PT_1/IN3 ),
    .I4(U2_ASedge),
    .I5(\NlwInverterSignal_U2_ADDR_reg<5>_MC.D2_PT_1/IN5 ),
    .O(\U2_ADDR_reg<5>_MC.D2_PT_1 )
  );
  X_AND7 \U2_ADDR_reg<5>_MC.D2_PT_2_185  (
    .I0(\WR_II/UIM ),
    .I1(\RD_II/UIM ),
    .I2(\NlwInverterSignal_U2_ADDR_reg<5>_MC.D2_PT_2/IN2 ),
    .I3(\MSPReset_II/UIM ),
    .I4(\NlwInverterSignal_U2_ADDR_reg<5>_MC.D2_PT_2/IN4 ),
    .I5(U2_ASedge),
    .I6(\AD<5>_II/UIM ),
    .O(\U2_ADDR_reg<5>_MC.D2_PT_2 )
  );
  X_OR3 \U2_ADDR_reg<5>_MC.D2_186  (
    .I0(\U2_ADDR_reg<5>_MC.D2_PT_0 ),
    .I1(\U2_ADDR_reg<5>_MC.D2_PT_1 ),
    .I2(\U2_ADDR_reg<5>_MC.D2_PT_2 ),
    .O(\U2_ADDR_reg<5>_MC.D2 )
  );
  X_BUF \U2_ADDR_reg<6>  (
    .I(\U2_ADDR_reg<6>_MC.Q ),
    .O(U2_ADDR_reg[6])
  );
  X_XOR2 \U2_ADDR_reg<6>_MC_tsimcreated_xor__187  (
    .I0(\U2_ADDR_reg<6>_MC.D ),
    .I1(\U2_ADDR_reg<6>_MC.Q ),
    .O(\U2_ADDR_reg<6>_MC_tsimcreated_xor_ )
  );
  X_FF \U2_ADDR_reg<6>_MC.REG  (
    .I(\U2_ADDR_reg<6>_MC_tsimcreated_xor_ ),
    .CE(Vcc),
    .CLK(\U2_ADDR_reg<6>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\U2_ADDR_reg<6>_MC.Q )
  );
  X_INV \U2_ADDR_reg<6>_MC.REG_tsimcreated_inv_Mclk_II/FCLK_188  (
    .I(\Mclk_II/FCLK ),
    .O(\U2_ADDR_reg<6>_MC.REG_tsimcreated_inv_Mclk_II/FCLK )
  );
  X_XOR2 \U2_ADDR_reg<6>_MC.D_189  (
    .I0(\U2_ADDR_reg<6>_MC.D1 ),
    .I1(\U2_ADDR_reg<6>_MC.D2 ),
    .O(\U2_ADDR_reg<6>_MC.D )
  );
  X_ZERO \U2_ADDR_reg<6>_MC.D1_190  (
    .O(\U2_ADDR_reg<6>_MC.D1 )
  );
  X_AND2 \U2_ADDR_reg<6>_MC.D2_PT_0_191  (
    .I0(U2_ADDR_reg[6]),
    .I1(\NlwInverterSignal_U2_ADDR_reg<6>_MC.D2_PT_0/IN1 ),
    .O(\U2_ADDR_reg<6>_MC.D2_PT_0 )
  );
  X_AND6 \U2_ADDR_reg<6>_MC.D2_PT_1_192  (
    .I0(\WR_II/UIM ),
    .I1(\RD_II/UIM ),
    .I2(U2_ADDR_reg[6]),
    .I3(\NlwInverterSignal_U2_ADDR_reg<6>_MC.D2_PT_1/IN3 ),
    .I4(U2_ASedge),
    .I5(\NlwInverterSignal_U2_ADDR_reg<6>_MC.D2_PT_1/IN5 ),
    .O(\U2_ADDR_reg<6>_MC.D2_PT_1 )
  );
  X_AND7 \U2_ADDR_reg<6>_MC.D2_PT_2_193  (
    .I0(\WR_II/UIM ),
    .I1(\RD_II/UIM ),
    .I2(\NlwInverterSignal_U2_ADDR_reg<6>_MC.D2_PT_2/IN2 ),
    .I3(\MSPReset_II/UIM ),
    .I4(\NlwInverterSignal_U2_ADDR_reg<6>_MC.D2_PT_2/IN4 ),
    .I5(U2_ASedge),
    .I6(\AD<6>_II/UIM ),
    .O(\U2_ADDR_reg<6>_MC.D2_PT_2 )
  );
  X_OR3 \U2_ADDR_reg<6>_MC.D2_194  (
    .I0(\U2_ADDR_reg<6>_MC.D2_PT_0 ),
    .I1(\U2_ADDR_reg<6>_MC.D2_PT_1 ),
    .I2(\U2_ADDR_reg<6>_MC.D2_PT_2 ),
    .O(\U2_ADDR_reg<6>_MC.D2 )
  );
  X_BUF \U2_ADDR_reg<7>  (
    .I(\U2_ADDR_reg<7>_MC.Q ),
    .O(U2_ADDR_reg[7])
  );
  X_XOR2 \U2_ADDR_reg<7>_MC_tsimcreated_xor__195  (
    .I0(\U2_ADDR_reg<7>_MC.D ),
    .I1(\U2_ADDR_reg<7>_MC.Q ),
    .O(\U2_ADDR_reg<7>_MC_tsimcreated_xor_ )
  );
  X_FF \U2_ADDR_reg<7>_MC.REG  (
    .I(\U2_ADDR_reg<7>_MC_tsimcreated_xor_ ),
    .CE(Vcc),
    .CLK(\U2_ADDR_reg<7>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\U2_ADDR_reg<7>_MC.Q )
  );
  X_INV \U2_ADDR_reg<7>_MC.REG_tsimcreated_inv_Mclk_II/FCLK_196  (
    .I(\Mclk_II/FCLK ),
    .O(\U2_ADDR_reg<7>_MC.REG_tsimcreated_inv_Mclk_II/FCLK )
  );
  X_XOR2 \U2_ADDR_reg<7>_MC.D_197  (
    .I0(\U2_ADDR_reg<7>_MC.D1 ),
    .I1(\U2_ADDR_reg<7>_MC.D2 ),
    .O(\U2_ADDR_reg<7>_MC.D )
  );
  X_ZERO \U2_ADDR_reg<7>_MC.D1_198  (
    .O(\U2_ADDR_reg<7>_MC.D1 )
  );
  X_AND2 \U2_ADDR_reg<7>_MC.D2_PT_0_199  (
    .I0(U2_ADDR_reg[7]),
    .I1(\NlwInverterSignal_U2_ADDR_reg<7>_MC.D2_PT_0/IN1 ),
    .O(\U2_ADDR_reg<7>_MC.D2_PT_0 )
  );
  X_AND6 \U2_ADDR_reg<7>_MC.D2_PT_1_200  (
    .I0(\WR_II/UIM ),
    .I1(\RD_II/UIM ),
    .I2(U2_ADDR_reg[7]),
    .I3(\NlwInverterSignal_U2_ADDR_reg<7>_MC.D2_PT_1/IN3 ),
    .I4(U2_ASedge),
    .I5(\NlwInverterSignal_U2_ADDR_reg<7>_MC.D2_PT_1/IN5 ),
    .O(\U2_ADDR_reg<7>_MC.D2_PT_1 )
  );
  X_AND7 \U2_ADDR_reg<7>_MC.D2_PT_2_201  (
    .I0(\WR_II/UIM ),
    .I1(\RD_II/UIM ),
    .I2(\NlwInverterSignal_U2_ADDR_reg<7>_MC.D2_PT_2/IN2 ),
    .I3(\MSPReset_II/UIM ),
    .I4(\NlwInverterSignal_U2_ADDR_reg<7>_MC.D2_PT_2/IN4 ),
    .I5(U2_ASedge),
    .I6(\AD<7>_II/UIM ),
    .O(\U2_ADDR_reg<7>_MC.D2_PT_2 )
  );
  X_OR3 \U2_ADDR_reg<7>_MC.D2_202  (
    .I0(\U2_ADDR_reg<7>_MC.D2_PT_0 ),
    .I1(\U2_ADDR_reg<7>_MC.D2_PT_1 ),
    .I2(\U2_ADDR_reg<7>_MC.D2_PT_2 ),
    .O(\U2_ADDR_reg<7>_MC.D2 )
  );
  X_BUF U2_AutoInc_203 (
    .I(\U2_AutoInc_MC.Q ),
    .O(U2_AutoInc)
  );
  X_FF \U2_AutoInc_MC.REG  (
    .I(\U2_AutoInc_MC.D ),
    .CE(\FOOBAR6__ctinst/4 ),
    .CLK(\U2_AutoInc_MC.REG_tsimcreated_inv_Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\U2_AutoInc_MC.Q )
  );
  X_INV \U2_AutoInc_MC.REG_tsimcreated_inv_Mclk_II/FCLK_204  (
    .I(\Mclk_II/FCLK ),
    .O(\U2_AutoInc_MC.REG_tsimcreated_inv_Mclk_II/FCLK )
  );
  X_XOR2 \U2_AutoInc_MC.D_205  (
    .I0(\NlwInverterSignal_U2_AutoInc_MC.D/IN0 ),
    .I1(\U2_AutoInc_MC.D2 ),
    .O(\U2_AutoInc_MC.D )
  );
  X_AND2 \U2_AutoInc_MC.D1_206  (
    .I0(\AS_II/UIM ),
    .I1(\AS_II/UIM ),
    .O(\U2_AutoInc_MC.D1 )
  );
  X_ZERO \U2_AutoInc_MC.D2_207  (
    .O(\U2_AutoInc_MC.D2 )
  );
  X_BUF U2_WRRDedge_208 (
    .I(\U2_WRRDedge_MC.Q ),
    .O(U2_WRRDedge)
  );
  X_FF \U2_WRRDedge_MC.REG  (
    .I(\U2_WRRDedge_MC.D ),
    .CE(Vcc),
    .CLK(\U2_WRRDedge_MC.REG_tsimcreated_inv_Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\U2_WRRDedge_MC.Q )
  );
  X_INV \U2_WRRDedge_MC.REG_tsimcreated_inv_Mclk_II/FCLK_209  (
    .I(\Mclk_II/FCLK ),
    .O(\U2_WRRDedge_MC.REG_tsimcreated_inv_Mclk_II/FCLK )
  );
  X_XOR2 \U2_WRRDedge_MC.D_210  (
    .I0(\U2_WRRDedge_MC.D1 ),
    .I1(\U2_WRRDedge_MC.D2 ),
    .O(\U2_WRRDedge_MC.D )
  );
  X_AND2 \U2_WRRDedge_MC.D1_211  (
    .I0(\WR_II/UIM ),
    .I1(\RD_II/UIM ),
    .O(\U2_WRRDedge_MC.D1 )
  );
  X_ZERO \U2_WRRDedge_MC.D2_212  (
    .O(\U2_WRRDedge_MC.D2 )
  );
  X_BUF N_PZ_1007_213 (
    .I(\N_PZ_1007_MC.Q ),
    .O(N_PZ_1007)
  );
  X_BUF \N_PZ_1007_MC.Q_214  (
    .I(\N_PZ_1007_MC.D ),
    .O(\N_PZ_1007_MC.Q )
  );
  X_XOR2 \N_PZ_1007_MC.D_215  (
    .I0(\N_PZ_1007_MC.D1 ),
    .I1(\N_PZ_1007_MC.D2 ),
    .O(\N_PZ_1007_MC.D )
  );
  X_AND2 \N_PZ_1007_MC.D1_216  (
    .I0(\WR_II/UIM ),
    .I1(\RD_II/UIM ),
    .O(\N_PZ_1007_MC.D1 )
  );
  X_ZERO \N_PZ_1007_MC.D2_217  (
    .O(\N_PZ_1007_MC.D2 )
  );
  X_BUF N_PZ_992_218 (
    .I(\N_PZ_992_MC.Q ),
    .O(N_PZ_992)
  );
  X_BUF \N_PZ_992_MC.Q_219  (
    .I(\N_PZ_992_MC.D ),
    .O(\N_PZ_992_MC.Q )
  );
  X_XOR2 \N_PZ_992_MC.D_220  (
    .I0(\N_PZ_992_MC.D1 ),
    .I1(\N_PZ_992_MC.D2 ),
    .O(\N_PZ_992_MC.D )
  );
  X_ZERO \N_PZ_992_MC.D1_221  (
    .O(\N_PZ_992_MC.D1 )
  );
  X_AND2 \N_PZ_992_MC.D2_PT_0_222  (
    .I0(\MSPReset_II/UIM ),
    .I1(\AS_II/UIM ),
    .O(\N_PZ_992_MC.D2_PT_0 )
  );
  X_AND2 \N_PZ_992_MC.D2_PT_1_223  (
    .I0(\MSPReset_II/UIM ),
    .I1(\NlwInverterSignal_N_PZ_992_MC.D2_PT_1/IN1 ),
    .O(\N_PZ_992_MC.D2_PT_1 )
  );
  X_OR2 \N_PZ_992_MC.D2_224  (
    .I0(\N_PZ_992_MC.D2_PT_0 ),
    .I1(\N_PZ_992_MC.D2_PT_1 ),
    .O(\N_PZ_992_MC.D2 )
  );
  X_BUF \U2_ADDR_reg<3>  (
    .I(\U2_ADDR_reg<3>_MC.Q ),
    .O(U2_ADDR_reg[3])
  );
  X_XOR2 \U2_ADDR_reg<3>_MC_tsimcreated_xor__225  (
    .I0(\U2_ADDR_reg<3>_MC.D ),
    .I1(\U2_ADDR_reg<3>_MC.Q ),
    .O(\U2_ADDR_reg<3>_MC_tsimcreated_xor_ )
  );
  X_FF \U2_ADDR_reg<3>_MC.REG  (
    .I(\U2_ADDR_reg<3>_MC_tsimcreated_xor_ ),
    .CE(Vcc),
    .CLK(\U2_ADDR_reg<3>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\U2_ADDR_reg<3>_MC.Q )
  );
  X_INV \U2_ADDR_reg<3>_MC.REG_tsimcreated_inv_Mclk_II/FCLK_226  (
    .I(\Mclk_II/FCLK ),
    .O(\U2_ADDR_reg<3>_MC.REG_tsimcreated_inv_Mclk_II/FCLK )
  );
  X_XOR2 \U2_ADDR_reg<3>_MC.D_227  (
    .I0(\U2_ADDR_reg<3>_MC.D1 ),
    .I1(\U2_ADDR_reg<3>_MC.D2 ),
    .O(\U2_ADDR_reg<3>_MC.D )
  );
  X_ZERO \U2_ADDR_reg<3>_MC.D1_228  (
    .O(\U2_ADDR_reg<3>_MC.D1 )
  );
  X_AND2 \U2_ADDR_reg<3>_MC.D2_PT_0_229  (
    .I0(U2_ADDR_reg[3]),
    .I1(\NlwInverterSignal_U2_ADDR_reg<3>_MC.D2_PT_0/IN1 ),
    .O(\U2_ADDR_reg<3>_MC.D2_PT_0 )
  );
  X_AND6 \U2_ADDR_reg<3>_MC.D2_PT_1_230  (
    .I0(\WR_II/UIM ),
    .I1(\RD_II/UIM ),
    .I2(U2_ADDR_reg[3]),
    .I3(\NlwInverterSignal_U2_ADDR_reg<3>_MC.D2_PT_1/IN3 ),
    .I4(U2_ASedge),
    .I5(\NlwInverterSignal_U2_ADDR_reg<3>_MC.D2_PT_1/IN5 ),
    .O(\U2_ADDR_reg<3>_MC.D2_PT_1 )
  );
  X_AND7 \U2_ADDR_reg<3>_MC.D2_PT_2_231  (
    .I0(\WR_II/UIM ),
    .I1(\RD_II/UIM ),
    .I2(\NlwInverterSignal_U2_ADDR_reg<3>_MC.D2_PT_2/IN2 ),
    .I3(\MSPReset_II/UIM ),
    .I4(\NlwInverterSignal_U2_ADDR_reg<3>_MC.D2_PT_2/IN4 ),
    .I5(U2_ASedge),
    .I6(\AD<3>_II/UIM ),
    .O(\U2_ADDR_reg<3>_MC.D2_PT_2 )
  );
  X_AND16 \U2_ADDR_reg<3>_MC.D2_PT_3_232  (
    .I0(\WR_II/UIM ),
    .I1(\RD_II/UIM ),
    .I2(U2_ADDR_reg[0]),
    .I3(\NlwInverterSignal_U2_ADDR_reg<3>_MC.D2_PT_3/IN3 ),
    .I4(\NlwInverterSignal_U2_ADDR_reg<3>_MC.D2_PT_3/IN4 ),
    .I5(\NlwInverterSignal_U2_ADDR_reg<3>_MC.D2_PT_3/IN5 ),
    .I6(\NlwInverterSignal_U2_ADDR_reg<3>_MC.D2_PT_3/IN6 ),
    .I7(U2_ADDR_reg[1]),
    .I8(U2_ADDR_reg[2]),
    .I9(U2_AutoInc),
    .I10(\NlwInverterSignal_U2_ADDR_reg<3>_MC.D2_PT_3/IN10 ),
    .I11(N_PZ_992),
    .I12(Vcc),
    .I13(Vcc),
    .I14(Vcc),
    .I15(Vcc),
    .O(\U2_ADDR_reg<3>_MC.D2_PT_3 )
  );
  X_OR4 \U2_ADDR_reg<3>_MC.D2_233  (
    .I0(\U2_ADDR_reg<3>_MC.D2_PT_0 ),
    .I1(\U2_ADDR_reg<3>_MC.D2_PT_1 ),
    .I2(\U2_ADDR_reg<3>_MC.D2_PT_2 ),
    .I3(\U2_ADDR_reg<3>_MC.D2_PT_3 ),
    .O(\U2_ADDR_reg<3>_MC.D2 )
  );
  X_BUF \U2_ADDR_reg<1>  (
    .I(\U2_ADDR_reg<1>_MC.Q ),
    .O(U2_ADDR_reg[1])
  );
  X_XOR2 \U2_ADDR_reg<1>_MC_tsimcreated_xor__234  (
    .I0(\U2_ADDR_reg<1>_MC.D ),
    .I1(\U2_ADDR_reg<1>_MC.Q ),
    .O(\U2_ADDR_reg<1>_MC_tsimcreated_xor_ )
  );
  X_FF \U2_ADDR_reg<1>_MC.REG  (
    .I(\U2_ADDR_reg<1>_MC_tsimcreated_xor_ ),
    .CE(Vcc),
    .CLK(\U2_ADDR_reg<1>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\U2_ADDR_reg<1>_MC.Q )
  );
  X_INV \U2_ADDR_reg<1>_MC.REG_tsimcreated_inv_Mclk_II/FCLK_235  (
    .I(\Mclk_II/FCLK ),
    .O(\U2_ADDR_reg<1>_MC.REG_tsimcreated_inv_Mclk_II/FCLK )
  );
  X_XOR2 \U2_ADDR_reg<1>_MC.D_236  (
    .I0(\U2_ADDR_reg<1>_MC.D1 ),
    .I1(\U2_ADDR_reg<1>_MC.D2 ),
    .O(\U2_ADDR_reg<1>_MC.D )
  );
  X_ZERO \U2_ADDR_reg<1>_MC.D1_237  (
    .O(\U2_ADDR_reg<1>_MC.D1 )
  );
  X_AND2 \U2_ADDR_reg<1>_MC.D2_PT_0_238  (
    .I0(U2_ADDR_reg[1]),
    .I1(\NlwInverterSignal_U2_ADDR_reg<1>_MC.D2_PT_0/IN1 ),
    .O(\U2_ADDR_reg<1>_MC.D2_PT_0 )
  );
  X_AND6 \U2_ADDR_reg<1>_MC.D2_PT_1_239  (
    .I0(\WR_II/UIM ),
    .I1(\RD_II/UIM ),
    .I2(U2_ADDR_reg[1]),
    .I3(\NlwInverterSignal_U2_ADDR_reg<1>_MC.D2_PT_1/IN3 ),
    .I4(U2_ASedge),
    .I5(\NlwInverterSignal_U2_ADDR_reg<1>_MC.D2_PT_1/IN5 ),
    .O(\U2_ADDR_reg<1>_MC.D2_PT_1 )
  );
  X_AND7 \U2_ADDR_reg<1>_MC.D2_PT_2_240  (
    .I0(\WR_II/UIM ),
    .I1(\RD_II/UIM ),
    .I2(\NlwInverterSignal_U2_ADDR_reg<1>_MC.D2_PT_2/IN2 ),
    .I3(\MSPReset_II/UIM ),
    .I4(\NlwInverterSignal_U2_ADDR_reg<1>_MC.D2_PT_2/IN4 ),
    .I5(U2_ASedge),
    .I6(\AD<1>_II/UIM ),
    .O(\U2_ADDR_reg<1>_MC.D2_PT_2 )
  );
  X_AND16 \U2_ADDR_reg<1>_MC.D2_PT_3_241  (
    .I0(\WR_II/UIM ),
    .I1(\RD_II/UIM ),
    .I2(U2_ADDR_reg[0]),
    .I3(\NlwInverterSignal_U2_ADDR_reg<1>_MC.D2_PT_3/IN3 ),
    .I4(\NlwInverterSignal_U2_ADDR_reg<1>_MC.D2_PT_3/IN4 ),
    .I5(\NlwInverterSignal_U2_ADDR_reg<1>_MC.D2_PT_3/IN5 ),
    .I6(\NlwInverterSignal_U2_ADDR_reg<1>_MC.D2_PT_3/IN6 ),
    .I7(U2_AutoInc),
    .I8(\NlwInverterSignal_U2_ADDR_reg<1>_MC.D2_PT_3/IN8 ),
    .I9(N_PZ_992),
    .I10(Vcc),
    .I11(Vcc),
    .I12(Vcc),
    .I13(Vcc),
    .I14(Vcc),
    .I15(Vcc),
    .O(\U2_ADDR_reg<1>_MC.D2_PT_3 )
  );
  X_OR4 \U2_ADDR_reg<1>_MC.D2_242  (
    .I0(\U2_ADDR_reg<1>_MC.D2_PT_0 ),
    .I1(\U2_ADDR_reg<1>_MC.D2_PT_1 ),
    .I2(\U2_ADDR_reg<1>_MC.D2_PT_2 ),
    .I3(\U2_ADDR_reg<1>_MC.D2_PT_3 ),
    .O(\U2_ADDR_reg<1>_MC.D2 )
  );
  X_BUF \U2_ADDR_reg<2>  (
    .I(\U2_ADDR_reg<2>_MC.Q ),
    .O(U2_ADDR_reg[2])
  );
  X_XOR2 \U2_ADDR_reg<2>_MC_tsimcreated_xor__243  (
    .I0(\U2_ADDR_reg<2>_MC.D ),
    .I1(\U2_ADDR_reg<2>_MC.Q ),
    .O(\U2_ADDR_reg<2>_MC_tsimcreated_xor_ )
  );
  X_FF \U2_ADDR_reg<2>_MC.REG  (
    .I(\U2_ADDR_reg<2>_MC_tsimcreated_xor_ ),
    .CE(Vcc),
    .CLK(\U2_ADDR_reg<2>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\U2_ADDR_reg<2>_MC.Q )
  );
  X_INV \U2_ADDR_reg<2>_MC.REG_tsimcreated_inv_Mclk_II/FCLK_244  (
    .I(\Mclk_II/FCLK ),
    .O(\U2_ADDR_reg<2>_MC.REG_tsimcreated_inv_Mclk_II/FCLK )
  );
  X_XOR2 \U2_ADDR_reg<2>_MC.D_245  (
    .I0(\U2_ADDR_reg<2>_MC.D1 ),
    .I1(\U2_ADDR_reg<2>_MC.D2 ),
    .O(\U2_ADDR_reg<2>_MC.D )
  );
  X_ZERO \U2_ADDR_reg<2>_MC.D1_246  (
    .O(\U2_ADDR_reg<2>_MC.D1 )
  );
  X_AND2 \U2_ADDR_reg<2>_MC.D2_PT_0_247  (
    .I0(U2_ADDR_reg[2]),
    .I1(\NlwInverterSignal_U2_ADDR_reg<2>_MC.D2_PT_0/IN1 ),
    .O(\U2_ADDR_reg<2>_MC.D2_PT_0 )
  );
  X_AND6 \U2_ADDR_reg<2>_MC.D2_PT_1_248  (
    .I0(\WR_II/UIM ),
    .I1(\RD_II/UIM ),
    .I2(U2_ADDR_reg[2]),
    .I3(\NlwInverterSignal_U2_ADDR_reg<2>_MC.D2_PT_1/IN3 ),
    .I4(U2_ASedge),
    .I5(\NlwInverterSignal_U2_ADDR_reg<2>_MC.D2_PT_1/IN5 ),
    .O(\U2_ADDR_reg<2>_MC.D2_PT_1 )
  );
  X_AND7 \U2_ADDR_reg<2>_MC.D2_PT_2_249  (
    .I0(\WR_II/UIM ),
    .I1(\RD_II/UIM ),
    .I2(\NlwInverterSignal_U2_ADDR_reg<2>_MC.D2_PT_2/IN2 ),
    .I3(\MSPReset_II/UIM ),
    .I4(\NlwInverterSignal_U2_ADDR_reg<2>_MC.D2_PT_2/IN4 ),
    .I5(U2_ASedge),
    .I6(\AD<2>_II/UIM ),
    .O(\U2_ADDR_reg<2>_MC.D2_PT_2 )
  );
  X_AND16 \U2_ADDR_reg<2>_MC.D2_PT_3_250  (
    .I0(\WR_II/UIM ),
    .I1(\RD_II/UIM ),
    .I2(U2_ADDR_reg[0]),
    .I3(\NlwInverterSignal_U2_ADDR_reg<2>_MC.D2_PT_3/IN3 ),
    .I4(\NlwInverterSignal_U2_ADDR_reg<2>_MC.D2_PT_3/IN4 ),
    .I5(\NlwInverterSignal_U2_ADDR_reg<2>_MC.D2_PT_3/IN5 ),
    .I6(\NlwInverterSignal_U2_ADDR_reg<2>_MC.D2_PT_3/IN6 ),
    .I7(U2_ADDR_reg[1]),
    .I8(U2_AutoInc),
    .I9(\NlwInverterSignal_U2_ADDR_reg<2>_MC.D2_PT_3/IN9 ),
    .I10(N_PZ_992),
    .I11(Vcc),
    .I12(Vcc),
    .I13(Vcc),
    .I14(Vcc),
    .I15(Vcc),
    .O(\U2_ADDR_reg<2>_MC.D2_PT_3 )
  );
  X_OR4 \U2_ADDR_reg<2>_MC.D2_251  (
    .I0(\U2_ADDR_reg<2>_MC.D2_PT_0 ),
    .I1(\U2_ADDR_reg<2>_MC.D2_PT_1 ),
    .I2(\U2_ADDR_reg<2>_MC.D2_PT_2 ),
    .I3(\U2_ADDR_reg<2>_MC.D2_PT_3 ),
    .O(\U2_ADDR_reg<2>_MC.D2 )
  );
  X_BUF \outDATA<0>\$WA0.UIM_252  (
    .I(\outDATA<0>\$WA0.UIM_MC.Q ),
    .O(\outDATA<0>\$WA0.UIM )
  );
  X_BUF \outDATA<0>\$WA0.UIM_MC.Q_253  (
    .I(\outDATA<0>\$WA0.UIM_MC.D ),
    .O(\outDATA<0>\$WA0.UIM_MC.Q )
  );
  X_XOR2 \outDATA<0>\$WA0.UIM_MC.D_254  (
    .I0(\outDATA<0>\$WA0.UIM_MC.D1 ),
    .I1(\outDATA<0>\$WA0.UIM_MC.D2 ),
    .O(\outDATA<0>\$WA0.UIM_MC.D )
  );
  X_AND2 \outDATA<0>\$WA0.UIM_MC.D1_255  (
    .I0(U11_U3_counterr[0]),
    .I1(U11_U3_counterr[0]),
    .O(\outDATA<0>\$WA0.UIM_MC.D1 )
  );
  X_ZERO \outDATA<0>\$WA0.UIM_MC.D2_256  (
    .O(\outDATA<0>\$WA0.UIM_MC.D2 )
  );
  X_BUF \U11_U3_counterr<0>  (
    .I(\U11_U3_counterr<0>_MC.Q ),
    .O(U11_U3_counterr[0])
  );
  X_FF \U11_U3_counterr<0>_MC.REG  (
    .I(\U11_U3_counterr<0>_MC.D ),
    .CE(Vcc),
    .CLK(\U11_U3_counterr<0>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\U11_U3_counterr<0>_MC.Q )
  );
  X_INV \U11_U3_counterr<0>_MC.REG_tsimcreated_inv_Mclk_II/FCLK_257  (
    .I(\Mclk_II/FCLK ),
    .O(\U11_U3_counterr<0>_MC.REG_tsimcreated_inv_Mclk_II/FCLK )
  );
  X_XOR2 \U11_U3_counterr<0>_MC.D_258  (
    .I0(\U11_U3_counterr<0>_MC.D1 ),
    .I1(\U11_U3_counterr<0>_MC.D2 ),
    .O(\U11_U3_counterr<0>_MC.D )
  );
  X_ZERO \U11_U3_counterr<0>_MC.D1_259  (
    .O(\U11_U3_counterr<0>_MC.D1 )
  );
  X_AND2 \U11_U3_counterr<0>_MC.D2_PT_0_260  (
    .I0(\SCLreset_II/UIM ),
    .I1(\SCLinc_II/UIM ),
    .O(\U11_U3_counterr<0>_MC.D2_PT_0 )
  );
  X_AND4 \U11_U3_counterr<0>_MC.D2_PT_1_261  (
    .I0(U11_U3_counterr[0]),
    .I1(\NlwInverterSignal_U11_U3_counterr<0>_MC.D2_PT_1/IN1 ),
    .I2(U11_Incdetect),
    .I3(U11_SCLdetect),
    .O(\U11_U3_counterr<0>_MC.D2_PT_1 )
  );
  X_AND4 \U11_U3_counterr<0>_MC.D2_PT_2_262  (
    .I0(U11_U3_counterr[0]),
    .I1(\NlwInverterSignal_U11_U3_counterr<0>_MC.D2_PT_2/IN1 ),
    .I2(\NlwInverterSignal_U11_U3_counterr<0>_MC.D2_PT_2/IN2 ),
    .I3(\NlwInverterSignal_U11_U3_counterr<0>_MC.D2_PT_2/IN3 ),
    .O(\U11_U3_counterr<0>_MC.D2_PT_2 )
  );
  X_AND4 \U11_U3_counterr<0>_MC.D2_PT_3_263  (
    .I0(\NlwInverterSignal_U11_U3_counterr<0>_MC.D2_PT_3/IN0 ),
    .I1(\NlwInverterSignal_U11_U3_counterr<0>_MC.D2_PT_3/IN1 ),
    .I2(U11_Incdetect),
    .I3(\NlwInverterSignal_U11_U3_counterr<0>_MC.D2_PT_3/IN3 ),
    .O(\U11_U3_counterr<0>_MC.D2_PT_3 )
  );
  X_AND4 \U11_U3_counterr<0>_MC.D2_PT_4_264  (
    .I0(\NlwInverterSignal_U11_U3_counterr<0>_MC.D2_PT_4/IN0 ),
    .I1(\NlwInverterSignal_U11_U3_counterr<0>_MC.D2_PT_4/IN1 ),
    .I2(U11_Incdetect),
    .I3(U11_ResetDetect),
    .O(\U11_U3_counterr<0>_MC.D2_PT_4 )
  );
  X_AND5 \U11_U3_counterr<0>_MC.D2_PT_5_265  (
    .I0(\NlwInverterSignal_U11_U3_counterr<0>_MC.D2_PT_5/IN0 ),
    .I1(\NlwInverterSignal_U11_U3_counterr<0>_MC.D2_PT_5/IN1 ),
    .I2(\NlwInverterSignal_U11_U3_counterr<0>_MC.D2_PT_5/IN2 ),
    .I3(U11_SCLdetect),
    .I4(\NlwInverterSignal_U11_U3_counterr<0>_MC.D2_PT_5/IN4 ),
    .O(\U11_U3_counterr<0>_MC.D2_PT_5 )
  );
  X_OR6 \U11_U3_counterr<0>_MC.D2_266  (
    .I0(\U11_U3_counterr<0>_MC.D2_PT_0 ),
    .I1(\U11_U3_counterr<0>_MC.D2_PT_1 ),
    .I2(\U11_U3_counterr<0>_MC.D2_PT_2 ),
    .I3(\U11_U3_counterr<0>_MC.D2_PT_3 ),
    .I4(\U11_U3_counterr<0>_MC.D2_PT_4 ),
    .I5(\U11_U3_counterr<0>_MC.D2_PT_5 ),
    .O(\U11_U3_counterr<0>_MC.D2 )
  );
  X_BUF U11_Incdetect_267 (
    .I(\U11_Incdetect_MC.Q ),
    .O(U11_Incdetect)
  );
  X_FF \U11_Incdetect_MC.REG  (
    .I(\U11_Incdetect_MC.D ),
    .CE(Vcc),
    .CLK(\U11_Incdetect_MC.REG_tsimcreated_inv_Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\U11_Incdetect_MC.Q )
  );
  X_INV \U11_Incdetect_MC.REG_tsimcreated_inv_Mclk_II/FCLK_268  (
    .I(\Mclk_II/FCLK ),
    .O(\U11_Incdetect_MC.REG_tsimcreated_inv_Mclk_II/FCLK )
  );
  X_XOR2 \U11_Incdetect_MC.D_269  (
    .I0(\U11_Incdetect_MC.D1 ),
    .I1(\U11_Incdetect_MC.D2 ),
    .O(\U11_Incdetect_MC.D )
  );
  X_AND2 \U11_Incdetect_MC.D1_270  (
    .I0(\NlwInverterSignal_U11_Incdetect_MC.D1/IN0 ),
    .I1(\U11_U1/Line_last ),
    .O(\U11_Incdetect_MC.D1 )
  );
  X_ZERO \U11_Incdetect_MC.D2_271  (
    .O(\U11_Incdetect_MC.D2 )
  );
  X_BUF U11_SCLdetect_272 (
    .I(\U11_SCLdetect_MC.Q ),
    .O(U11_SCLdetect)
  );
  X_FF \U11_SCLdetect_MC.REG  (
    .I(\U11_SCLdetect_MC.D ),
    .CE(Vcc),
    .CLK(\U11_SCLdetect_MC.REG_tsimcreated_inv_Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\U11_SCLdetect_MC.Q )
  );
  X_INV \U11_SCLdetect_MC.REG_tsimcreated_inv_Mclk_II/FCLK_273  (
    .I(\Mclk_II/FCLK ),
    .O(\U11_SCLdetect_MC.REG_tsimcreated_inv_Mclk_II/FCLK )
  );
  X_XOR2 \U11_SCLdetect_MC.D_274  (
    .I0(\U11_SCLdetect_MC.D1 ),
    .I1(\U11_SCLdetect_MC.D2 ),
    .O(\U11_SCLdetect_MC.D )
  );
  X_AND2 \U11_SCLdetect_MC.D1_275  (
    .I0(\NlwInverterSignal_U11_SCLdetect_MC.D1/IN0 ),
    .I1(\U11_U2/Line_last ),
    .O(\U11_SCLdetect_MC.D1 )
  );
  X_ZERO \U11_SCLdetect_MC.D2_276  (
    .O(\U11_SCLdetect_MC.D2 )
  );
  X_BUF \U11_U2/Line_last_MC.Q_277  (
    .I(\U11_U2/Line_last_MC.D ),
    .O(\U11_U2/Line_last_MC.Q )
  );
  X_BUF \U11_U2/Line_last_MC.OE_278  (
    .I(\U11_U2/Line_last_MC.BUFOE.OUT ),
    .O(\U11_U2/Line_last_MC.OE )
  );
  X_BUF \U11_U2/Line_last_MC.BUFOE.OUT_279  (
    .I(\FOOBAR4__ctinst/0 ),
    .O(\U11_U2/Line_last_MC.BUFOE.OUT )
  );
  X_XOR2 \U11_U2/Line_last_MC.D_280  (
    .I0(\U11_U2/Line_last_MC.D1 ),
    .I1(\U11_U2/Line_last_MC.D2 ),
    .O(\U11_U2/Line_last_MC.D )
  );
  X_ZERO \U11_U2/Line_last_MC.D1_281  (
    .O(\U11_U2/Line_last_MC.D1 )
  );
  X_ZERO \U11_U2/Line_last_MC.D2_282  (
    .O(\U11_U2/Line_last_MC.D2 )
  );
  X_BUF \TP12_MC.Q_283  (
    .I(\TP12_MC.Q_tsimrenamed_net_ ),
    .O(\TP12_MC.Q )
  );
  X_BUF \TP12_MC.UIM_284  (
    .I(\TP12_MC.Q_tsimrenamed_net_ ),
    .O(\TP12_MC.UIM )
  );
  X_BUF \TP12_MC.Q_tsimrenamed_net__285  (
    .I(\TP12_MC.D ),
    .O(\TP12_MC.Q_tsimrenamed_net_ )
  );
  X_XOR2 \TP12_MC.D_286  (
    .I0(\TP12_MC.D1 ),
    .I1(\TP12_MC.D2 ),
    .O(\TP12_MC.D )
  );
  X_AND6 \TP12_MC.D1_287  (
    .I0(\NlwInverterSignal_TP12_MC.D1/IN0 ),
    .I1(\NlwInverterSignal_TP12_MC.D1/IN1 ),
    .I2(\NlwInverterSignal_TP12_MC.D1/IN2 ),
    .I3(\NlwInverterSignal_TP12_MC.D1/IN3 ),
    .I4(\NlwInverterSignal_TP12_MC.D1/IN4 ),
    .I5(\NlwInverterSignal_TP12_MC.D1/IN5 ),
    .O(\TP12_MC.D1 )
  );
  X_ZERO \TP12_MC.D2_288  (
    .O(\TP12_MC.D2 )
  );
  X_BUF \U11_U3_counterr<3>  (
    .I(\U11_U3_counterr<3>_MC.Q ),
    .O(U11_U3_counterr[3])
  );
  X_XOR2 \U11_U3_counterr<3>_MC_tsimcreated_xor__289  (
    .I0(\U11_U3_counterr<3>_MC.D ),
    .I1(\U11_U3_counterr<3>_MC.Q ),
    .O(\U11_U3_counterr<3>_MC_tsimcreated_xor_ )
  );
  X_FF \U11_U3_counterr<3>_MC.REG  (
    .I(\U11_U3_counterr<3>_MC_tsimcreated_xor_ ),
    .CE(Vcc),
    .CLK(\U11_U3_counterr<3>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\U11_U3_counterr<3>_MC.Q )
  );
  X_INV \U11_U3_counterr<3>_MC.REG_tsimcreated_inv_Mclk_II/FCLK_290  (
    .I(\Mclk_II/FCLK ),
    .O(\U11_U3_counterr<3>_MC.REG_tsimcreated_inv_Mclk_II/FCLK )
  );
  X_XOR2 \U11_U3_counterr<3>_MC.D_291  (
    .I0(\NlwInverterSignal_U11_U3_counterr<3>_MC.D/IN0 ),
    .I1(\U11_U3_counterr<3>_MC.D2 ),
    .O(\U11_U3_counterr<3>_MC.D )
  );
  X_ZERO \U11_U3_counterr<3>_MC.D1_292  (
    .O(\U11_U3_counterr<3>_MC.D1 )
  );
  X_AND2 \U11_U3_counterr<3>_MC.D2_PT_0_293  (
    .I0(\SCLreset_II/UIM ),
    .I1(U11_U3_counterr[3]),
    .O(\U11_U3_counterr<3>_MC.D2_PT_0 )
  );
  X_AND3 \U11_U3_counterr<3>_MC.D2_PT_1_294  (
    .I0(U11_U3_counterr[0]),
    .I1(\NlwInverterSignal_U11_U3_counterr<3>_MC.D2_PT_1/IN1 ),
    .I2(\NlwInverterSignal_U11_U3_counterr<3>_MC.D2_PT_1/IN2 ),
    .O(\U11_U3_counterr<3>_MC.D2_PT_1 )
  );
  X_AND3 \U11_U3_counterr<3>_MC.D2_PT_2_295  (
    .I0(\NlwInverterSignal_U11_U3_counterr<3>_MC.D2_PT_2/IN0 ),
    .I1(\NlwInverterSignal_U11_U3_counterr<3>_MC.D2_PT_2/IN1 ),
    .I2(N_PZ_1128),
    .O(\U11_U3_counterr<3>_MC.D2_PT_2 )
  );
  X_AND3 \U11_U3_counterr<3>_MC.D2_PT_3_296  (
    .I0(\NlwInverterSignal_U11_U3_counterr<3>_MC.D2_PT_3/IN0 ),
    .I1(\NlwInverterSignal_U11_U3_counterr<3>_MC.D2_PT_3/IN1 ),
    .I2(\NlwInverterSignal_U11_U3_counterr<3>_MC.D2_PT_3/IN2 ),
    .O(\U11_U3_counterr<3>_MC.D2_PT_3 )
  );
  X_AND3 \U11_U3_counterr<3>_MC.D2_PT_4_297  (
    .I0(\NlwInverterSignal_U11_U3_counterr<3>_MC.D2_PT_4/IN0 ),
    .I1(U11_U3_counterr[1]),
    .I2(\NlwInverterSignal_U11_U3_counterr<3>_MC.D2_PT_4/IN2 ),
    .O(\U11_U3_counterr<3>_MC.D2_PT_4 )
  );
  X_AND3 \U11_U3_counterr<3>_MC.D2_PT_5_298  (
    .I0(\NlwInverterSignal_U11_U3_counterr<3>_MC.D2_PT_5/IN0 ),
    .I1(U11_U3_counterr[2]),
    .I2(\NlwInverterSignal_U11_U3_counterr<3>_MC.D2_PT_5/IN2 ),
    .O(\U11_U3_counterr<3>_MC.D2_PT_5 )
  );
  X_AND5 \U11_U3_counterr<3>_MC.D2_PT_6_299  (
    .I0(U11_U3_counterr[0]),
    .I1(\NlwInverterSignal_U11_U3_counterr<3>_MC.D2_PT_6/IN1 ),
    .I2(U11_U3_counterr[1]),
    .I3(U11_U3_counterr[2]),
    .I4(\NlwInverterSignal_U11_U3_counterr<3>_MC.D2_PT_6/IN4 ),
    .O(\U11_U3_counterr<3>_MC.D2_PT_6 )
  );
  X_OR7 \U11_U3_counterr<3>_MC.D2_300  (
    .I0(\U11_U3_counterr<3>_MC.D2_PT_0 ),
    .I1(\U11_U3_counterr<3>_MC.D2_PT_1 ),
    .I2(\U11_U3_counterr<3>_MC.D2_PT_2 ),
    .I3(\U11_U3_counterr<3>_MC.D2_PT_3 ),
    .I4(\U11_U3_counterr<3>_MC.D2_PT_4 ),
    .I5(\U11_U3_counterr<3>_MC.D2_PT_5 ),
    .I6(\U11_U3_counterr<3>_MC.D2_PT_6 ),
    .O(\U11_U3_counterr<3>_MC.D2 )
  );
  X_BUF N_PZ_1128_301 (
    .I(\N_PZ_1128_MC.Q ),
    .O(N_PZ_1128)
  );
  X_BUF \N_PZ_1128_MC.Q_302  (
    .I(\N_PZ_1128_MC.D ),
    .O(\N_PZ_1128_MC.Q )
  );
  X_XOR2 \N_PZ_1128_MC.D_303  (
    .I0(\N_PZ_1128_MC.D1 ),
    .I1(\N_PZ_1128_MC.D2 ),
    .O(\N_PZ_1128_MC.D )
  );
  X_ZERO \N_PZ_1128_MC.D1_304  (
    .O(\N_PZ_1128_MC.D1 )
  );
  X_AND2 \N_PZ_1128_MC.D2_PT_0_305  (
    .I0(\SCLreset_II/UIM ),
    .I1(\SCLreset_II/UIM ),
    .O(\N_PZ_1128_MC.D2_PT_0 )
  );
  X_AND3 \N_PZ_1128_MC.D2_PT_1_306  (
    .I0(\NlwInverterSignal_N_PZ_1128_MC.D2_PT_1/IN0 ),
    .I1(U11_Incdetect),
    .I2(U11_ResetDetect),
    .O(\N_PZ_1128_MC.D2_PT_1 )
  );
  X_AND3 \N_PZ_1128_MC.D2_PT_2_307  (
    .I0(\NlwInverterSignal_N_PZ_1128_MC.D2_PT_2/IN0 ),
    .I1(U11_SCLdetect),
    .I2(\outDATA<7>\$WA6.UIM ),
    .O(\N_PZ_1128_MC.D2_PT_2 )
  );
  X_OR3 \N_PZ_1128_MC.D2_308  (
    .I0(\N_PZ_1128_MC.D2_PT_0 ),
    .I1(\N_PZ_1128_MC.D2_PT_1 ),
    .I2(\N_PZ_1128_MC.D2_PT_2 ),
    .O(\N_PZ_1128_MC.D2 )
  );
  X_BUF U11_ResetDetect_309 (
    .I(\U11_ResetDetect_MC.Q ),
    .O(U11_ResetDetect)
  );
  X_FF \U11_ResetDetect_MC.REG  (
    .I(\U11_ResetDetect_MC.D ),
    .CE(Vcc),
    .CLK(\U11_ResetDetect_MC.REG_tsimcreated_inv_Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\U11_ResetDetect_MC.Q )
  );
  X_INV \U11_ResetDetect_MC.REG_tsimcreated_inv_Mclk_II/FCLK_310  (
    .I(\Mclk_II/FCLK ),
    .O(\U11_ResetDetect_MC.REG_tsimcreated_inv_Mclk_II/FCLK )
  );
  X_XOR2 \U11_ResetDetect_MC.D_311  (
    .I0(\U11_ResetDetect_MC.D1 ),
    .I1(\U11_ResetDetect_MC.D2 ),
    .O(\U11_ResetDetect_MC.D )
  );
  X_AND2 \U11_ResetDetect_MC.D1_312  (
    .I0(\NlwInverterSignal_U11_ResetDetect_MC.D1/IN0 ),
    .I1(\U11_U4/Line_last ),
    .O(\U11_ResetDetect_MC.D1 )
  );
  X_ZERO \U11_ResetDetect_MC.D2_313  (
    .O(\U11_ResetDetect_MC.D2 )
  );
  X_BUF \outDATA<7>\$WA6.UIM_314  (
    .I(\outDATA<7>\$WA6.UIM_MC.Q ),
    .O(\outDATA<7>\$WA6.UIM )
  );
  X_BUF \outDATA<7>\$WA6.UIM_MC.Q_315  (
    .I(\outDATA<7>\$WA6.UIM_MC.D ),
    .O(\outDATA<7>\$WA6.UIM_MC.Q )
  );
  X_XOR2 \outDATA<7>\$WA6.UIM_MC.D_316  (
    .I0(\outDATA<7>\$WA6.UIM_MC.D1 ),
    .I1(\outDATA<7>\$WA6.UIM_MC.D2 ),
    .O(\outDATA<7>\$WA6.UIM_MC.D )
  );
  X_AND2 \outDATA<7>\$WA6.UIM_MC.D1_317  (
    .I0(\TP12_MC.UIM ),
    .I1(\TP12_MC.UIM ),
    .O(\outDATA<7>\$WA6.UIM_MC.D1 )
  );
  X_ZERO \outDATA<7>\$WA6.UIM_MC.D2_318  (
    .O(\outDATA<7>\$WA6.UIM_MC.D2 )
  );
  X_BUF \U11_U3_counterr<1>  (
    .I(\U11_U3_counterr<1>_MC.Q ),
    .O(U11_U3_counterr[1])
  );
  X_XOR2 \U11_U3_counterr<1>_MC_tsimcreated_xor__319  (
    .I0(\U11_U3_counterr<1>_MC.D ),
    .I1(\U11_U3_counterr<1>_MC.Q ),
    .O(\U11_U3_counterr<1>_MC_tsimcreated_xor_ )
  );
  X_FF \U11_U3_counterr<1>_MC.REG  (
    .I(\U11_U3_counterr<1>_MC_tsimcreated_xor_ ),
    .CE(Vcc),
    .CLK(\U11_U3_counterr<1>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\U11_U3_counterr<1>_MC.Q )
  );
  X_INV \U11_U3_counterr<1>_MC.REG_tsimcreated_inv_Mclk_II/FCLK_320  (
    .I(\Mclk_II/FCLK ),
    .O(\U11_U3_counterr<1>_MC.REG_tsimcreated_inv_Mclk_II/FCLK )
  );
  X_XOR2 \U11_U3_counterr<1>_MC.D_321  (
    .I0(\U11_U3_counterr<1>_MC.D1 ),
    .I1(\U11_U3_counterr<1>_MC.D2 ),
    .O(\U11_U3_counterr<1>_MC.D )
  );
  X_AND2 \U11_U3_counterr<1>_MC.D1_322  (
    .I0(U11_U3_counterr[1]),
    .I1(N_PZ_1128),
    .O(\U11_U3_counterr<1>_MC.D1 )
  );
  X_AND3 \U11_U3_counterr<1>_MC.D2_PT_0_323  (
    .I0(\SCLreset_II/UIM ),
    .I1(\NlwInverterSignal_U11_U3_counterr<1>_MC.D2_PT_0/IN1 ),
    .I2(N_PZ_1128),
    .O(\U11_U3_counterr<1>_MC.D2_PT_0 )
  );
  X_AND4 \U11_U3_counterr<1>_MC.D2_PT_1_324  (
    .I0(U11_U3_counterr[0]),
    .I1(U11_Incdetect),
    .I2(\NlwInverterSignal_U11_U3_counterr<1>_MC.D2_PT_1/IN2 ),
    .I3(\NlwInverterSignal_U11_U3_counterr<1>_MC.D2_PT_1/IN3 ),
    .O(\U11_U3_counterr<1>_MC.D2_PT_1 )
  );
  X_AND4 \U11_U3_counterr<1>_MC.D2_PT_2_325  (
    .I0(\NlwInverterSignal_U11_U3_counterr<1>_MC.D2_PT_2/IN0 ),
    .I1(\NlwInverterSignal_U11_U3_counterr<1>_MC.D2_PT_2/IN1 ),
    .I2(U11_SCLdetect),
    .I3(\NlwInverterSignal_U11_U3_counterr<1>_MC.D2_PT_2/IN3 ),
    .O(\U11_U3_counterr<1>_MC.D2_PT_2 )
  );
  X_OR3 \U11_U3_counterr<1>_MC.D2_326  (
    .I0(\U11_U3_counterr<1>_MC.D2_PT_0 ),
    .I1(\U11_U3_counterr<1>_MC.D2_PT_1 ),
    .I2(\U11_U3_counterr<1>_MC.D2_PT_2 ),
    .O(\U11_U3_counterr<1>_MC.D2 )
  );
  X_BUF \U11_U3_counterr<2>  (
    .I(\U11_U3_counterr<2>_MC.Q ),
    .O(U11_U3_counterr[2])
  );
  X_XOR2 \U11_U3_counterr<2>_MC_tsimcreated_xor__327  (
    .I0(\U11_U3_counterr<2>_MC.D ),
    .I1(\U11_U3_counterr<2>_MC.Q ),
    .O(\U11_U3_counterr<2>_MC_tsimcreated_xor_ )
  );
  X_FF \U11_U3_counterr<2>_MC.REG  (
    .I(\U11_U3_counterr<2>_MC_tsimcreated_xor_ ),
    .CE(Vcc),
    .CLK(\U11_U3_counterr<2>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\U11_U3_counterr<2>_MC.Q )
  );
  X_INV \U11_U3_counterr<2>_MC.REG_tsimcreated_inv_Mclk_II/FCLK_328  (
    .I(\Mclk_II/FCLK ),
    .O(\U11_U3_counterr<2>_MC.REG_tsimcreated_inv_Mclk_II/FCLK )
  );
  X_XOR2 \U11_U3_counterr<2>_MC.D_329  (
    .I0(\U11_U3_counterr<2>_MC.D1 ),
    .I1(\U11_U3_counterr<2>_MC.D2 ),
    .O(\U11_U3_counterr<2>_MC.D )
  );
  X_ZERO \U11_U3_counterr<2>_MC.D1_330  (
    .O(\U11_U3_counterr<2>_MC.D1 )
  );
  X_AND2 \U11_U3_counterr<2>_MC.D2_PT_0_331  (
    .I0(U11_U3_counterr[2]),
    .I1(N_PZ_1128),
    .O(\U11_U3_counterr<2>_MC.D2_PT_0 )
  );
  X_AND5 \U11_U3_counterr<2>_MC.D2_PT_1_332  (
    .I0(U11_U3_counterr[0]),
    .I1(U11_Incdetect),
    .I2(\NlwInverterSignal_U11_U3_counterr<2>_MC.D2_PT_1/IN2 ),
    .I3(U11_U3_counterr[1]),
    .I4(\NlwInverterSignal_U11_U3_counterr<2>_MC.D2_PT_1/IN4 ),
    .O(\U11_U3_counterr<2>_MC.D2_PT_1 )
  );
  X_AND5 \U11_U3_counterr<2>_MC.D2_PT_2_333  (
    .I0(\NlwInverterSignal_U11_U3_counterr<2>_MC.D2_PT_2/IN0 ),
    .I1(\NlwInverterSignal_U11_U3_counterr<2>_MC.D2_PT_2/IN1 ),
    .I2(U11_SCLdetect),
    .I3(\NlwInverterSignal_U11_U3_counterr<2>_MC.D2_PT_2/IN3 ),
    .I4(\NlwInverterSignal_U11_U3_counterr<2>_MC.D2_PT_2/IN4 ),
    .O(\U11_U3_counterr<2>_MC.D2_PT_2 )
  );
  X_OR3 \U11_U3_counterr<2>_MC.D2_334  (
    .I0(\U11_U3_counterr<2>_MC.D2_PT_0 ),
    .I1(\U11_U3_counterr<2>_MC.D2_PT_1 ),
    .I2(\U11_U3_counterr<2>_MC.D2_PT_2 ),
    .O(\U11_U3_counterr<2>_MC.D2 )
  );
  X_BUF \U11_U3_counterr<4>  (
    .I(\U11_U3_counterr<4>_MC.Q ),
    .O(U11_U3_counterr[4])
  );
  X_XOR2 \U11_U3_counterr<4>_MC_tsimcreated_xor__335  (
    .I0(\U11_U3_counterr<4>_MC.D ),
    .I1(\U11_U3_counterr<4>_MC.Q ),
    .O(\U11_U3_counterr<4>_MC_tsimcreated_xor_ )
  );
  X_FF \U11_U3_counterr<4>_MC.REG  (
    .I(\U11_U3_counterr<4>_MC_tsimcreated_xor_ ),
    .CE(Vcc),
    .CLK(\U11_U3_counterr<4>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\U11_U3_counterr<4>_MC.Q )
  );
  X_INV \U11_U3_counterr<4>_MC.REG_tsimcreated_inv_Mclk_II/FCLK_336  (
    .I(\Mclk_II/FCLK ),
    .O(\U11_U3_counterr<4>_MC.REG_tsimcreated_inv_Mclk_II/FCLK )
  );
  X_XOR2 \U11_U3_counterr<4>_MC.D_337  (
    .I0(\U11_U3_counterr<4>_MC.D1 ),
    .I1(\U11_U3_counterr<4>_MC.D2 ),
    .O(\U11_U3_counterr<4>_MC.D )
  );
  X_ZERO \U11_U3_counterr<4>_MC.D1_338  (
    .O(\U11_U3_counterr<4>_MC.D1 )
  );
  X_AND2 \U11_U3_counterr<4>_MC.D2_PT_0_339  (
    .I0(U11_U3_counterr[4]),
    .I1(N_PZ_1128),
    .O(\U11_U3_counterr<4>_MC.D2_PT_0 )
  );
  X_AND3 \U11_U3_counterr<4>_MC.D2_PT_1_340  (
    .I0(U11_Incdetect),
    .I1(U11_U3_counterr[3]),
    .I2(\NlwInverterSignal_U11_U3_counterr<4>_MC.D2_PT_1/IN2 ),
    .O(\U11_U3_counterr<4>_MC.D2_PT_1 )
  );
  X_AND6 \U11_U3_counterr<4>_MC.D2_PT_2_341  (
    .I0(U11_U3_counterr[0]),
    .I1(U11_Incdetect),
    .I2(\NlwInverterSignal_U11_U3_counterr<4>_MC.D2_PT_2/IN2 ),
    .I3(U11_U3_counterr[1]),
    .I4(U11_U3_counterr[2]),
    .I5(\NlwInverterSignal_U11_U3_counterr<4>_MC.D2_PT_2/IN5 ),
    .O(\U11_U3_counterr<4>_MC.D2_PT_2 )
  );
  X_AND7 \U11_U3_counterr<4>_MC.D2_PT_3_342  (
    .I0(\NlwInverterSignal_U11_U3_counterr<4>_MC.D2_PT_3/IN0 ),
    .I1(\NlwInverterSignal_U11_U3_counterr<4>_MC.D2_PT_3/IN1 ),
    .I2(U11_SCLdetect),
    .I3(\NlwInverterSignal_U11_U3_counterr<4>_MC.D2_PT_3/IN3 ),
    .I4(\NlwInverterSignal_U11_U3_counterr<4>_MC.D2_PT_3/IN4 ),
    .I5(\NlwInverterSignal_U11_U3_counterr<4>_MC.D2_PT_3/IN5 ),
    .I6(\NlwInverterSignal_U11_U3_counterr<4>_MC.D2_PT_3/IN6 ),
    .O(\U11_U3_counterr<4>_MC.D2_PT_3 )
  );
  X_OR4 \U11_U3_counterr<4>_MC.D2_343  (
    .I0(\U11_U3_counterr<4>_MC.D2_PT_0 ),
    .I1(\U11_U3_counterr<4>_MC.D2_PT_1 ),
    .I2(\U11_U3_counterr<4>_MC.D2_PT_2 ),
    .I3(\U11_U3_counterr<4>_MC.D2_PT_3 ),
    .O(\U11_U3_counterr<4>_MC.D2 )
  );
  X_BUF \U11_U3_counterr<5>  (
    .I(\U11_U3_counterr<5>_MC.Q ),
    .O(U11_U3_counterr[5])
  );
  X_XOR2 \U11_U3_counterr<5>_MC_tsimcreated_xor__344  (
    .I0(\U11_U3_counterr<5>_MC.D ),
    .I1(\U11_U3_counterr<5>_MC.Q ),
    .O(\U11_U3_counterr<5>_MC_tsimcreated_xor_ )
  );
  X_FF \U11_U3_counterr<5>_MC.REG  (
    .I(\U11_U3_counterr<5>_MC_tsimcreated_xor_ ),
    .CE(Vcc),
    .CLK(\U11_U3_counterr<5>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\U11_U3_counterr<5>_MC.Q )
  );
  X_INV \U11_U3_counterr<5>_MC.REG_tsimcreated_inv_Mclk_II/FCLK_345  (
    .I(\Mclk_II/FCLK ),
    .O(\U11_U3_counterr<5>_MC.REG_tsimcreated_inv_Mclk_II/FCLK )
  );
  X_XOR2 \U11_U3_counterr<5>_MC.D_346  (
    .I0(\U11_U3_counterr<5>_MC.D1 ),
    .I1(\U11_U3_counterr<5>_MC.D2 ),
    .O(\U11_U3_counterr<5>_MC.D )
  );
  X_ZERO \U11_U3_counterr<5>_MC.D1_347  (
    .O(\U11_U3_counterr<5>_MC.D1 )
  );
  X_AND2 \U11_U3_counterr<5>_MC.D2_PT_0_348  (
    .I0(U11_U3_counterr[5]),
    .I1(N_PZ_1128),
    .O(\U11_U3_counterr<5>_MC.D2_PT_0 )
  );
  X_AND4 \U11_U3_counterr<5>_MC.D2_PT_1_349  (
    .I0(U11_Incdetect),
    .I1(U11_U3_counterr[3]),
    .I2(U11_U3_counterr[4]),
    .I3(\NlwInverterSignal_U11_U3_counterr<5>_MC.D2_PT_1/IN3 ),
    .O(\U11_U3_counterr<5>_MC.D2_PT_1 )
  );
  X_AND7 \U11_U3_counterr<5>_MC.D2_PT_2_350  (
    .I0(U11_U3_counterr[0]),
    .I1(U11_Incdetect),
    .I2(\NlwInverterSignal_U11_U3_counterr<5>_MC.D2_PT_2/IN2 ),
    .I3(U11_U3_counterr[1]),
    .I4(U11_U3_counterr[2]),
    .I5(U11_U3_counterr[4]),
    .I6(\NlwInverterSignal_U11_U3_counterr<5>_MC.D2_PT_2/IN6 ),
    .O(\U11_U3_counterr<5>_MC.D2_PT_2 )
  );
  X_AND8 \U11_U3_counterr<5>_MC.D2_PT_3_351  (
    .I0(\NlwInverterSignal_U11_U3_counterr<5>_MC.D2_PT_3/IN0 ),
    .I1(\NlwInverterSignal_U11_U3_counterr<5>_MC.D2_PT_3/IN1 ),
    .I2(U11_SCLdetect),
    .I3(\NlwInverterSignal_U11_U3_counterr<5>_MC.D2_PT_3/IN3 ),
    .I4(\NlwInverterSignal_U11_U3_counterr<5>_MC.D2_PT_3/IN4 ),
    .I5(\NlwInverterSignal_U11_U3_counterr<5>_MC.D2_PT_3/IN5 ),
    .I6(\NlwInverterSignal_U11_U3_counterr<5>_MC.D2_PT_3/IN6 ),
    .I7(\NlwInverterSignal_U11_U3_counterr<5>_MC.D2_PT_3/IN7 ),
    .O(\U11_U3_counterr<5>_MC.D2_PT_3 )
  );
  X_OR4 \U11_U3_counterr<5>_MC.D2_352  (
    .I0(\U11_U3_counterr<5>_MC.D2_PT_0 ),
    .I1(\U11_U3_counterr<5>_MC.D2_PT_1 ),
    .I2(\U11_U3_counterr<5>_MC.D2_PT_2 ),
    .I3(\U11_U3_counterr<5>_MC.D2_PT_3 ),
    .O(\U11_U3_counterr<5>_MC.D2 )
  );
  X_BUF DCOR0THRESLOWr_353 (
    .I(\DCOR0THRESLOWr_MC.Q ),
    .O(DCOR0THRESLOWr)
  );
  X_BUF \DCOR0THRESLOWr_MC.Q_354  (
    .I(\DCOR0THRESLOWr_MC.D ),
    .O(\DCOR0THRESLOWr_MC.Q )
  );
  X_XOR2 \DCOR0THRESLOWr_MC.D_355  (
    .I0(\DCOR0THRESLOWr_MC.D1 ),
    .I1(\DCOR0THRESLOWr_MC.D2 ),
    .O(\DCOR0THRESLOWr_MC.D )
  );
  X_AND16 \DCOR0THRESLOWr_MC.D1_356  (
    .I0(\WR_II/UIM ),
    .I1(\NlwInverterSignal_DCOR0THRESLOWr_MC.D1/IN1 ),
    .I2(\NlwInverterSignal_DCOR0THRESLOWr_MC.D1/IN2 ),
    .I3(\NlwInverterSignal_DCOR0THRESLOWr_MC.D1/IN3 ),
    .I4(\NlwInverterSignal_DCOR0THRESLOWr_MC.D1/IN4 ),
    .I5(\NlwInverterSignal_DCOR0THRESLOWr_MC.D1/IN5 ),
    .I6(\NlwInverterSignal_DCOR0THRESLOWr_MC.D1/IN6 ),
    .I7(U2_ADDR_reg[3]),
    .I8(\NlwInverterSignal_DCOR0THRESLOWr_MC.D1/IN8 ),
    .I9(\NlwInverterSignal_DCOR0THRESLOWr_MC.D1/IN9 ),
    .I10(Vcc),
    .I11(Vcc),
    .I12(Vcc),
    .I13(Vcc),
    .I14(Vcc),
    .I15(Vcc),
    .O(\DCOR0THRESLOWr_MC.D1 )
  );
  X_ZERO \DCOR0THRESLOWr_MC.D2_357  (
    .O(\DCOR0THRESLOWr_MC.D2 )
  );
  X_BUF \outDATA<0>\$WA2.UIM_358  (
    .I(\outDATA<0>\$WA2.UIM_MC.Q ),
    .O(\outDATA<0>\$WA2.UIM )
  );
  X_BUF \outDATA<0>\$WA2.UIM_MC.Q_359  (
    .I(\outDATA<0>\$WA2.UIM_MC.D ),
    .O(\outDATA<0>\$WA2.UIM_MC.Q )
  );
  X_XOR2 \outDATA<0>\$WA2.UIM_MC.D_360  (
    .I0(\outDATA<0>\$WA2.UIM_MC.D1 ),
    .I1(\outDATA<0>\$WA2.UIM_MC.D2 ),
    .O(\outDATA<0>\$WA2.UIM_MC.D )
  );
  X_ZERO \outDATA<0>\$WA2.UIM_MC.D1_361  (
    .O(\outDATA<0>\$WA2.UIM_MC.D1 )
  );
  X_AND2 \outDATA<0>\$WA2.UIM_MC.D2_PT_0_362  (
    .I0(DCOR0THRESLOWr),
    .I1(\U1/U4/Latch0r [0]),
    .O(\outDATA<0>\$WA2.UIM_MC.D2_PT_0 )
  );
  X_AND3 \outDATA<0>\$WA2.UIM_MC.D2_PT_1_363  (
    .I0(\NlwInverterSignal_outDATA<0>\$WA2.UIM_MC.D2_PT_1/IN0 ),
    .I1(\U1/U4/Latch0r [8]),
    .I2(DCOR0THRESHIGHr),
    .O(\outDATA<0>\$WA2.UIM_MC.D2_PT_1 )
  );
  X_AND4 \outDATA<0>\$WA2.UIM_MC.D2_PT_2_364  (
    .I0(\NlwInverterSignal_outDATA<0>\$WA2.UIM_MC.D2_PT_2/IN0 ),
    .I1(\NlwInverterSignal_outDATA<0>\$WA2.UIM_MC.D2_PT_2/IN1 ),
    .I2(\U1/U4/Latch1r [0]),
    .I3(DCOR1THRESLOWr),
    .O(\outDATA<0>\$WA2.UIM_MC.D2_PT_2 )
  );
  X_AND4 \outDATA<0>\$WA2.UIM_MC.D2_PT_3_365  (
    .I0(\NlwInverterSignal_outDATA<0>\$WA2.UIM_MC.D2_PT_3/IN0 ),
    .I1(\NlwInverterSignal_outDATA<0>\$WA2.UIM_MC.D2_PT_3/IN1 ),
    .I2(\NlwInverterSignal_outDATA<0>\$WA2.UIM_MC.D2_PT_3/IN2 ),
    .I3(\U1/U4/Latch1r [8]),
    .O(\outDATA<0>\$WA2.UIM_MC.D2_PT_3 )
  );
  X_OR4 \outDATA<0>\$WA2.UIM_MC.D2_366  (
    .I0(\outDATA<0>\$WA2.UIM_MC.D2_PT_0 ),
    .I1(\outDATA<0>\$WA2.UIM_MC.D2_PT_1 ),
    .I2(\outDATA<0>\$WA2.UIM_MC.D2_PT_2 ),
    .I3(\outDATA<0>\$WA2.UIM_MC.D2_PT_3 ),
    .O(\outDATA<0>\$WA2.UIM_MC.D2 )
  );
  X_BUF \U1/U4/Latch0r<0>  (
    .I(\U1/U4/Latch0r<0>_MC.Q ),
    .O(\U1/U4/Latch0r [0])
  );
  X_FF \U1/U4/Latch0r<0>_MC.REG  (
    .I(\U1/U4/Latch0r<0>_MC.D ),
    .CE(Vcc),
    .CLK(\U1/U4/Latch0r<0>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\U1/U4/Latch0r<0>_MC.Q )
  );
  X_INV \U1/U4/Latch0r<0>_MC.REG_tsimcreated_inv_Mclk_II/FCLK_367  (
    .I(\Mclk_II/FCLK ),
    .O(\U1/U4/Latch0r<0>_MC.REG_tsimcreated_inv_Mclk_II/FCLK )
  );
  X_XOR2 \U1/U4/Latch0r<0>_MC.D_368  (
    .I0(\U1/U4/Latch0r<0>_MC.D1 ),
    .I1(\U1/U4/Latch0r<0>_MC.D2 ),
    .O(\U1/U4/Latch0r<0>_MC.D )
  );
  X_ZERO \U1/U4/Latch0r<0>_MC.D1_369  (
    .O(\U1/U4/Latch0r<0>_MC.D1 )
  );
  X_AND3 \U1/U4/Latch0r<0>_MC.D2_PT_0_370  (
    .I0(\MSPReset_II/UIM ),
    .I1(\U1/U4/Latch0r [0]),
    .I2(\NlwInverterSignal_U1/U4/Latch0r<0>_MC.D2_PT_0/IN2 ),
    .O(\U1/U4/Latch0r<0>_MC.D2_PT_0 )
  );
  X_AND3 \U1/U4/Latch0r<0>_MC.D2_PT_1_371  (
    .I0(\MSPReset_II/UIM ),
    .I1(N_PZ_1018),
    .I2(\U1/Channel0 [0]),
    .O(\U1/U4/Latch0r<0>_MC.D2_PT_1 )
  );
  X_OR2 \U1/U4/Latch0r<0>_MC.D2_372  (
    .I0(\U1/U4/Latch0r<0>_MC.D2_PT_0 ),
    .I1(\U1/U4/Latch0r<0>_MC.D2_PT_1 ),
    .O(\U1/U4/Latch0r<0>_MC.D2 )
  );
  X_BUF \U1/Channel0<0>  (
    .I(\U1/Channel0<0>_MC.Q ),
    .O(\U1/Channel0 [0])
  );
  X_XOR2 \U1/Channel0<0>_MC_tsimcreated_xor__373  (
    .I0(\U1/Channel0<0>_MC.D ),
    .I1(\U1/Channel0<0>_MC.Q ),
    .O(\U1/Channel0<0>_MC_tsimcreated_xor_ )
  );
  X_FF \U1/Channel0<0>_MC.REG  (
    .I(\U1/Channel0<0>_MC_tsimcreated_xor_ ),
    .CE(Vcc),
    .CLK(\Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\U1/Channel0<0>_MC.Q )
  );
  X_XOR2 \U1/Channel0<0>_MC.D_374  (
    .I0(\U1/Channel0<0>_MC.D1 ),
    .I1(\U1/Channel0<0>_MC.D2 ),
    .O(\U1/Channel0<0>_MC.D )
  );
  X_ZERO \U1/Channel0<0>_MC.D1_375  (
    .O(\U1/Channel0<0>_MC.D1 )
  );
  X_AND2 \U1/Channel0<0>_MC.D2_PT_0_376  (
    .I0(\U1/Channel0 [0]),
    .I1(\NlwInverterSignal_U1/Channel0<0>_MC.D2_PT_0/IN1 ),
    .O(\U1/Channel0<0>_MC.D2_PT_0 )
  );
  X_AND6 \U1/Channel0<0>_MC.D2_PT_1_377  (
    .I0(\MSPReset_II/UIM ),
    .I1(\NlwInverterSignal_U1/Channel0<0>_MC.D2_PT_1/IN1 ),
    .I2(\U1/U1/CurrState_Sreg0_FFD1 ),
    .I3(\U1/U1/CurrState_Sreg0_FFD3 ),
    .I4(\NlwInverterSignal_U1/Channel0<0>_MC.D2_PT_1/IN4 ),
    .I5(\NlwInverterSignal_U1/Channel0<0>_MC.D2_PT_1/IN5 ),
    .O(\U1/Channel0<0>_MC.D2_PT_1 )
  );
  X_AND6 \U1/Channel0<0>_MC.D2_PT_2_378  (
    .I0(\MSPReset_II/UIM ),
    .I1(\NlwInverterSignal_U1/Channel0<0>_MC.D2_PT_2/IN1 ),
    .I2(\NlwInverterSignal_U1/Channel0<0>_MC.D2_PT_2/IN2 ),
    .I3(\U1/U1/CurrState_Sreg0_FFD3 ),
    .I4(\NlwInverterSignal_U1/Channel0<0>_MC.D2_PT_2/IN4 ),
    .I5(\U1/U1/CurrState_Sreg0_FFD4 ),
    .O(\U1/Channel0<0>_MC.D2_PT_2 )
  );
  X_OR3 \U1/Channel0<0>_MC.D2_379  (
    .I0(\U1/Channel0<0>_MC.D2_PT_0 ),
    .I1(\U1/Channel0<0>_MC.D2_PT_1 ),
    .I2(\U1/Channel0<0>_MC.D2_PT_2 ),
    .O(\U1/Channel0<0>_MC.D2 )
  );
  X_BUF \U1/Zero0_380  (
    .I(\U1/Zero0_MC.Q ),
    .O(\U1/Zero0 )
  );
  X_FF \U1/Zero0_MC.REG  (
    .I(\U1/Zero0_MC.D ),
    .CE(Vcc),
    .CLK(\U1/Zero0_MC.REG_tsimcreated_inv_Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\U1/Zero0_MC.Q )
  );
  X_INV \U1/Zero0_MC.REG_tsimcreated_inv_Mclk_II/FCLK_381  (
    .I(\Mclk_II/FCLK ),
    .O(\U1/Zero0_MC.REG_tsimcreated_inv_Mclk_II/FCLK )
  );
  X_XOR2 \U1/Zero0_MC.D_382  (
    .I0(\U1/Zero0_MC.D1 ),
    .I1(\U1/Zero0_MC.D2 ),
    .O(\U1/Zero0_MC.D )
  );
  X_ZERO \U1/Zero0_MC.D1_383  (
    .O(\U1/Zero0_MC.D1 )
  );
  X_AND2 \U1/Zero0_MC.D2_PT_0_384  (
    .I0(\NlwInverterSignal_U1/Zero0_MC.D2_PT_0/IN0 ),
    .I1(\U1/Zero0 ),
    .O(\U1/Zero0_MC.D2_PT_0 )
  );
  X_AND2 \U1/Zero0_MC.D2_PT_1_385  (
    .I0(\U1/Zero0 ),
    .I1(DCORIFGw),
    .O(\U1/Zero0_MC.D2_PT_1 )
  );
  X_AND2 \U1/Zero0_MC.D2_PT_2_386  (
    .I0(\U1/Zero0 ),
    .I1(DCORENCCTLw),
    .O(\U1/Zero0_MC.D2_PT_2 )
  );
  X_AND8 \U1/Zero0_MC.D2_PT_3_387  (
    .I0(\MSPReset_II/UIM ),
    .I1(\NlwInverterSignal_U1/Zero0_MC.D2_PT_3/IN1 ),
    .I2(\NlwInverterSignal_U1/Zero0_MC.D2_PT_3/IN2 ),
    .I3(\NlwInverterSignal_U1/Zero0_MC.D2_PT_3/IN3 ),
    .I4(\U1/U4/RF0r ),
    .I5(\U1/U4/E0r ),
    .I6(\U1/U4/HE0stater ),
    .I7(\NlwInverterSignal_U1/Zero0_MC.D2_PT_3/IN7 ),
    .O(\U1/Zero0_MC.D2_PT_3 )
  );
  X_AND8 \U1/Zero0_MC.D2_PT_4_388  (
    .I0(\MSPReset_II/UIM ),
    .I1(\NlwInverterSignal_U1/Zero0_MC.D2_PT_4/IN1 ),
    .I2(\NlwInverterSignal_U1/Zero0_MC.D2_PT_4/IN2 ),
    .I3(\NlwInverterSignal_U1/Zero0_MC.D2_PT_4/IN3 ),
    .I4(\NlwInverterSignal_U1/Zero0_MC.D2_PT_4/IN4 ),
    .I5(\U1/U4/E0r ),
    .I6(\NlwInverterSignal_U1/Zero0_MC.D2_PT_4/IN6 ),
    .I7(\U1/U4/HE0statelastr ),
    .O(\U1/Zero0_MC.D2_PT_4 )
  );
  X_OR5 \U1/Zero0_MC.D2_389  (
    .I0(\U1/Zero0_MC.D2_PT_0 ),
    .I1(\U1/Zero0_MC.D2_PT_1 ),
    .I2(\U1/Zero0_MC.D2_PT_2 ),
    .I3(\U1/Zero0_MC.D2_PT_3 ),
    .I4(\U1/Zero0_MC.D2_PT_4 ),
    .O(\U1/Zero0_MC.D2 )
  );
  X_BUF DCORIFGw_390 (
    .I(\DCORIFGw_MC.Q ),
    .O(DCORIFGw)
  );
  X_BUF \DCORIFGw_MC.Q_391  (
    .I(\DCORIFGw_MC.D ),
    .O(\DCORIFGw_MC.Q )
  );
  X_XOR2 \DCORIFGw_MC.D_392  (
    .I0(\DCORIFGw_MC.D1 ),
    .I1(\DCORIFGw_MC.D2 ),
    .O(\DCORIFGw_MC.D )
  );
  X_AND16 \DCORIFGw_MC.D1_393  (
    .I0(\NlwInverterSignal_DCORIFGw_MC.D1/IN0 ),
    .I1(\RD_II/UIM ),
    .I2(U2_ADDR_reg[0]),
    .I3(\NlwInverterSignal_DCORIFGw_MC.D1/IN3 ),
    .I4(\NlwInverterSignal_DCORIFGw_MC.D1/IN4 ),
    .I5(\NlwInverterSignal_DCORIFGw_MC.D1/IN5 ),
    .I6(\NlwInverterSignal_DCORIFGw_MC.D1/IN6 ),
    .I7(\NlwInverterSignal_DCORIFGw_MC.D1/IN7 ),
    .I8(\NlwInverterSignal_DCORIFGw_MC.D1/IN8 ),
    .I9(\NlwInverterSignal_DCORIFGw_MC.D1/IN9 ),
    .I10(Vcc),
    .I11(Vcc),
    .I12(Vcc),
    .I13(Vcc),
    .I14(Vcc),
    .I15(Vcc),
    .O(\DCORIFGw_MC.D1 )
  );
  X_ZERO \DCORIFGw_MC.D2_394  (
    .O(\DCORIFGw_MC.D2 )
  );
  X_BUF DCORENCCTLw_395 (
    .I(\DCORENCCTLw_MC.Q ),
    .O(DCORENCCTLw)
  );
  X_BUF \DCORENCCTLw_MC.Q_396  (
    .I(\DCORENCCTLw_MC.D ),
    .O(\DCORENCCTLw_MC.Q )
  );
  X_XOR2 \DCORENCCTLw_MC.D_397  (
    .I0(\DCORENCCTLw_MC.D1 ),
    .I1(\DCORENCCTLw_MC.D2 ),
    .O(\DCORENCCTLw_MC.D )
  );
  X_AND16 \DCORENCCTLw_MC.D1_398  (
    .I0(\NlwInverterSignal_DCORENCCTLw_MC.D1/IN0 ),
    .I1(\RD_II/UIM ),
    .I2(U2_ADDR_reg[0]),
    .I3(\NlwInverterSignal_DCORENCCTLw_MC.D1/IN3 ),
    .I4(\NlwInverterSignal_DCORENCCTLw_MC.D1/IN4 ),
    .I5(\NlwInverterSignal_DCORENCCTLw_MC.D1/IN5 ),
    .I6(\NlwInverterSignal_DCORENCCTLw_MC.D1/IN6 ),
    .I7(\NlwInverterSignal_DCORENCCTLw_MC.D1/IN7 ),
    .I8(U2_ADDR_reg[1]),
    .I9(\NlwInverterSignal_DCORENCCTLw_MC.D1/IN9 ),
    .I10(Vcc),
    .I11(Vcc),
    .I12(Vcc),
    .I13(Vcc),
    .I14(Vcc),
    .I15(Vcc),
    .O(\DCORENCCTLw_MC.D1 )
  );
  X_ZERO \DCORENCCTLw_MC.D2_399  (
    .O(\DCORENCCTLw_MC.D2 )
  );
  X_BUF NET2482_400 (
    .I(\NET2482_MC.Q ),
    .O(NET2482)
  );
  X_XOR2 NET2482_MC_tsimcreated_xor__401 (
    .I0(\NET2482_MC.D ),
    .I1(\NET2482_MC.Q ),
    .O(NET2482_MC_tsimcreated_xor_)
  );
  X_FF \NET2482_MC.REG  (
    .I(NET2482_MC_tsimcreated_xor_),
    .CE(Vcc),
    .CLK(\NET2482_MC.REG_tsimcreated_inv_Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\NET2482_MC.Q )
  );
  X_INV \NET2482_MC.REG_tsimcreated_inv_Mclk_II/FCLK_402  (
    .I(\Mclk_II/FCLK ),
    .O(\NET2482_MC.REG_tsimcreated_inv_Mclk_II/FCLK )
  );
  X_XOR2 \NET2482_MC.D_403  (
    .I0(\NET2482_MC.D1 ),
    .I1(\NET2482_MC.D2 ),
    .O(\NET2482_MC.D )
  );
  X_ZERO \NET2482_MC.D1_404  (
    .O(\NET2482_MC.D1 )
  );
  X_AND2 \NET2482_MC.D2_PT_0_405  (
    .I0(\NlwInverterSignal_NET2482_MC.D2_PT_0/IN0 ),
    .I1(NET2482),
    .O(\NET2482_MC.D2_PT_0 )
  );
  X_AND4 \NET2482_MC.D2_PT_1_406  (
    .I0(\AD<2>_II/UIM ),
    .I1(DCORIFGw),
    .I2(\NlwInverterSignal_NET2482_MC.D2_PT_1/IN2 ),
    .I3(NET2482),
    .O(\NET2482_MC.D2_PT_1 )
  );
  X_AND8 \NET2482_MC.D2_PT_2_407  (
    .I0(\MSPReset_II/UIM ),
    .I1(\NlwInverterSignal_NET2482_MC.D2_PT_2/IN1 ),
    .I2(\NlwInverterSignal_NET2482_MC.D2_PT_2/IN2 ),
    .I3(\NlwInverterSignal_NET2482_MC.D2_PT_2/IN3 ),
    .I4(\U1/U4/RF0r ),
    .I5(\U1/U4/E0r ),
    .I6(\U1/U4/HE0stater ),
    .I7(\NlwInverterSignal_NET2482_MC.D2_PT_2/IN7 ),
    .O(\NET2482_MC.D2_PT_2 )
  );
  X_AND8 \NET2482_MC.D2_PT_3_408  (
    .I0(\MSPReset_II/UIM ),
    .I1(\NlwInverterSignal_NET2482_MC.D2_PT_3/IN1 ),
    .I2(\NlwInverterSignal_NET2482_MC.D2_PT_3/IN2 ),
    .I3(\NlwInverterSignal_NET2482_MC.D2_PT_3/IN3 ),
    .I4(\NlwInverterSignal_NET2482_MC.D2_PT_3/IN4 ),
    .I5(\U1/U4/E0r ),
    .I6(\NlwInverterSignal_NET2482_MC.D2_PT_3/IN6 ),
    .I7(\U1/U4/HE0statelastr ),
    .O(\NET2482_MC.D2_PT_3 )
  );
  X_OR4 \NET2482_MC.D2_409  (
    .I0(\NET2482_MC.D2_PT_0 ),
    .I1(\NET2482_MC.D2_PT_1 ),
    .I2(\NET2482_MC.D2_PT_2 ),
    .I3(\NET2482_MC.D2_PT_3 ),
    .O(\NET2482_MC.D2 )
  );
  X_BUF \U1/U4/RF0r_410  (
    .I(\U1/U4/RF0r_MC.Q ),
    .O(\U1/U4/RF0r )
  );
  X_FF \U1/U4/RF0r_MC.REG  (
    .I(\U1/U4/RF0r_MC.D ),
    .CE(Vcc),
    .CLK(\U1/U4/RF0r_MC.REG_tsimcreated_inv_Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\U1/U4/RF0r_MC.Q )
  );
  X_INV \U1/U4/RF0r_MC.REG_tsimcreated_inv_Mclk_II/FCLK_411  (
    .I(\Mclk_II/FCLK ),
    .O(\U1/U4/RF0r_MC.REG_tsimcreated_inv_Mclk_II/FCLK )
  );
  X_XOR2 \U1/U4/RF0r_MC.D_412  (
    .I0(\U1/U4/RF0r_MC.D1 ),
    .I1(\U1/U4/RF0r_MC.D2 ),
    .O(\U1/U4/RF0r_MC.D )
  );
  X_ZERO \U1/U4/RF0r_MC.D1_413  (
    .O(\U1/U4/RF0r_MC.D1 )
  );
  X_AND3 \U1/U4/RF0r_MC.D2_PT_0_414  (
    .I0(\MSPReset_II/UIM ),
    .I1(\AD<0>_II/UIM ),
    .I2(DCORENCCTLw),
    .O(\U1/U4/RF0r_MC.D2_PT_0 )
  );
  X_AND3 \U1/U4/RF0r_MC.D2_PT_1_415  (
    .I0(\MSPReset_II/UIM ),
    .I1(\NlwInverterSignal_U1/U4/RF0r_MC.D2_PT_1/IN1 ),
    .I2(\U1/U4/RF0r ),
    .O(\U1/U4/RF0r_MC.D2_PT_1 )
  );
  X_OR2 \U1/U4/RF0r_MC.D2_416  (
    .I0(\U1/U4/RF0r_MC.D2_PT_0 ),
    .I1(\U1/U4/RF0r_MC.D2_PT_1 ),
    .O(\U1/U4/RF0r_MC.D2 )
  );
  X_BUF \U1/U4/E0r_417  (
    .I(\U1/U4/E0r_MC.Q ),
    .O(\U1/U4/E0r )
  );
  X_FF \U1/U4/E0r_MC.REG  (
    .I(\U1/U4/E0r_MC.D ),
    .CE(Vcc),
    .CLK(\U1/U4/E0r_MC.REG_tsimcreated_inv_Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\U1/U4/E0r_MC.Q )
  );
  X_INV \U1/U4/E0r_MC.REG_tsimcreated_inv_Mclk_II/FCLK_418  (
    .I(\Mclk_II/FCLK ),
    .O(\U1/U4/E0r_MC.REG_tsimcreated_inv_Mclk_II/FCLK )
  );
  X_XOR2 \U1/U4/E0r_MC.D_419  (
    .I0(\U1/U4/E0r_MC.D1 ),
    .I1(\U1/U4/E0r_MC.D2 ),
    .O(\U1/U4/E0r_MC.D )
  );
  X_ZERO \U1/U4/E0r_MC.D1_420  (
    .O(\U1/U4/E0r_MC.D1 )
  );
  X_AND3 \U1/U4/E0r_MC.D2_PT_0_421  (
    .I0(\MSPReset_II/UIM ),
    .I1(\AD<1>_II/UIM ),
    .I2(DCORENCCTLw),
    .O(\U1/U4/E0r_MC.D2_PT_0 )
  );
  X_AND3 \U1/U4/E0r_MC.D2_PT_1_422  (
    .I0(\MSPReset_II/UIM ),
    .I1(\NlwInverterSignal_U1/U4/E0r_MC.D2_PT_1/IN1 ),
    .I2(\U1/U4/E0r ),
    .O(\U1/U4/E0r_MC.D2_PT_1 )
  );
  X_OR2 \U1/U4/E0r_MC.D2_423  (
    .I0(\U1/U4/E0r_MC.D2_PT_0 ),
    .I1(\U1/U4/E0r_MC.D2_PT_1 ),
    .O(\U1/U4/E0r_MC.D2 )
  );
  X_BUF \U1/U4/HE0statelastr_424  (
    .I(\U1/U4/HE0statelastr_MC.Q ),
    .O(\U1/U4/HE0statelastr )
  );
  X_FF \U1/U4/HE0statelastr_MC.REG  (
    .I(\U1/U4/HE0statelastr_MC.D ),
    .CE(Vcc),
    .CLK(\U1/U4/HE0statelastr_MC.REG_tsimcreated_inv_Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\U1/U4/HE0statelastr_MC.Q )
  );
  X_INV \U1/U4/HE0statelastr_MC.REG_tsimcreated_inv_Mclk_II/FCLK_425  (
    .I(\Mclk_II/FCLK ),
    .O(\U1/U4/HE0statelastr_MC.REG_tsimcreated_inv_Mclk_II/FCLK )
  );
  X_XOR2 \U1/U4/HE0statelastr_MC.D_426  (
    .I0(\U1/U4/HE0statelastr_MC.D1 ),
    .I1(\U1/U4/HE0statelastr_MC.D2 ),
    .O(\U1/U4/HE0statelastr_MC.D )
  );
  X_AND2 \U1/U4/HE0statelastr_MC.D1_427  (
    .I0(\U1/U4/HE0stater ),
    .I1(\U1/U4/HE0stater ),
    .O(\U1/U4/HE0statelastr_MC.D1 )
  );
  X_ZERO \U1/U4/HE0statelastr_MC.D2_428  (
    .O(\U1/U4/HE0statelastr_MC.D2 )
  );
  X_BUF \U1/U1/CurrState_Sreg0_FFD1_429  (
    .I(\U1/U1/CurrState_Sreg0_FFD1_MC.Q ),
    .O(\U1/U1/CurrState_Sreg0_FFD1 )
  );
  X_FF \U1/U1/CurrState_Sreg0_FFD1_MC.REG  (
    .I(\U1/U1/CurrState_Sreg0_FFD1_MC.D ),
    .CE(Vcc),
    .CLK(\Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\U1/U1/CurrState_Sreg0_FFD1_MC.Q )
  );
  X_XOR2 \U1/U1/CurrState_Sreg0_FFD1_MC.D_430  (
    .I0(\U1/U1/CurrState_Sreg0_FFD1_MC.D1 ),
    .I1(\U1/U1/CurrState_Sreg0_FFD1_MC.D2 ),
    .O(\U1/U1/CurrState_Sreg0_FFD1_MC.D )
  );
  X_ZERO \U1/U1/CurrState_Sreg0_FFD1_MC.D1_431  (
    .O(\U1/U1/CurrState_Sreg0_FFD1_MC.D1 )
  );
  X_AND4 \U1/U1/CurrState_Sreg0_FFD1_MC.D2_PT_0_432  (
    .I0(\MSPReset_II/UIM ),
    .I1(\U1/U1/CurrState_Sreg0_FFD1 ),
    .I2(\U1/U1/CurrState_Sreg0_FFD2 ),
    .I3(\NlwInverterSignal_U1/U1/CurrState_Sreg0_FFD1_MC.D2_PT_0/IN3 ),
    .O(\U1/U1/CurrState_Sreg0_FFD1_MC.D2_PT_0 )
  );
  X_AND5 \U1/U1/CurrState_Sreg0_FFD1_MC.D2_PT_1_433  (
    .I0(\MSPReset_II/UIM ),
    .I1(\U1/U1/CurrState_Sreg0_FFD1 ),
    .I2(\NlwInverterSignal_U1/U1/CurrState_Sreg0_FFD1_MC.D2_PT_1/IN2 ),
    .I3(\NlwInverterSignal_U1/U1/CurrState_Sreg0_FFD1_MC.D2_PT_1/IN3 ),
    .I4(\PhaseA_Encoder0_II/UIM ),
    .O(\U1/U1/CurrState_Sreg0_FFD1_MC.D2_PT_1 )
  );
  X_AND6 \U1/U1/CurrState_Sreg0_FFD1_MC.D2_PT_2_434  (
    .I0(\MSPReset_II/UIM ),
    .I1(\NlwInverterSignal_U1/U1/CurrState_Sreg0_FFD1_MC.D2_PT_2/IN1 ),
    .I2(\NlwInverterSignal_U1/U1/CurrState_Sreg0_FFD1_MC.D2_PT_2/IN2 ),
    .I3(\NlwInverterSignal_U1/U1/CurrState_Sreg0_FFD1_MC.D2_PT_2/IN3 ),
    .I4(\NlwInverterSignal_U1/U1/CurrState_Sreg0_FFD1_MC.D2_PT_2/IN4 ),
    .I5(\PhaseB_Encoder0_II/UIM ),
    .O(\U1/U1/CurrState_Sreg0_FFD1_MC.D2_PT_2 )
  );
  X_OR3 \U1/U1/CurrState_Sreg0_FFD1_MC.D2_435  (
    .I0(\U1/U1/CurrState_Sreg0_FFD1_MC.D2_PT_0 ),
    .I1(\U1/U1/CurrState_Sreg0_FFD1_MC.D2_PT_1 ),
    .I2(\U1/U1/CurrState_Sreg0_FFD1_MC.D2_PT_2 ),
    .O(\U1/U1/CurrState_Sreg0_FFD1_MC.D2 )
  );
  X_BUF \U1/U1/CurrState_Sreg0_FFD3_436  (
    .I(\U1/U1/CurrState_Sreg0_FFD3_MC.Q ),
    .O(\U1/U1/CurrState_Sreg0_FFD3 )
  );
  X_FF \U1/U1/CurrState_Sreg0_FFD3_MC.REG  (
    .I(\U1/U1/CurrState_Sreg0_FFD3_MC.D ),
    .CE(Vcc),
    .CLK(\Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\U1/U1/CurrState_Sreg0_FFD3_MC.Q )
  );
  X_XOR2 \U1/U1/CurrState_Sreg0_FFD3_MC.D_437  (
    .I0(\U1/U1/CurrState_Sreg0_FFD3_MC.D1 ),
    .I1(\U1/U1/CurrState_Sreg0_FFD3_MC.D2 ),
    .O(\U1/U1/CurrState_Sreg0_FFD3_MC.D )
  );
  X_ZERO \U1/U1/CurrState_Sreg0_FFD3_MC.D1_438  (
    .O(\U1/U1/CurrState_Sreg0_FFD3_MC.D1 )
  );
  X_AND5 \U1/U1/CurrState_Sreg0_FFD3_MC.D2_PT_0_439  (
    .I0(\MSPReset_II/UIM ),
    .I1(\NlwInverterSignal_U1/U1/CurrState_Sreg0_FFD3_MC.D2_PT_0/IN1 ),
    .I2(\U1/U1/CurrState_Sreg0_FFD3 ),
    .I3(\NlwInverterSignal_U1/U1/CurrState_Sreg0_FFD3_MC.D2_PT_0/IN3 ),
    .I4(\NlwInverterSignal_U1/U1/CurrState_Sreg0_FFD3_MC.D2_PT_0/IN4 ),
    .O(\U1/U1/CurrState_Sreg0_FFD3_MC.D2_PT_0 )
  );
  X_AND5 \U1/U1/CurrState_Sreg0_FFD3_MC.D2_PT_1_440  (
    .I0(\MSPReset_II/UIM ),
    .I1(\U1/U1/CurrState_Sreg0_FFD3 ),
    .I2(\U1/U1/CurrState_Sreg0_FFD2 ),
    .I3(\NlwInverterSignal_U1/U1/CurrState_Sreg0_FFD3_MC.D2_PT_1/IN3 ),
    .I4(\NlwInverterSignal_U1/U1/CurrState_Sreg0_FFD3_MC.D2_PT_1/IN4 ),
    .O(\U1/U1/CurrState_Sreg0_FFD3_MC.D2_PT_1 )
  );
  X_AND6 \U1/U1/CurrState_Sreg0_FFD3_MC.D2_PT_2_441  (
    .I0(\MSPReset_II/UIM ),
    .I1(\U1/U1/CurrState_Sreg0_FFD1 ),
    .I2(\U1/U1/CurrState_Sreg0_FFD2 ),
    .I3(\NlwInverterSignal_U1/U1/CurrState_Sreg0_FFD3_MC.D2_PT_2/IN3 ),
    .I4(\PhaseA_Encoder0_II/UIM ),
    .I5(\NlwInverterSignal_U1/U1/CurrState_Sreg0_FFD3_MC.D2_PT_2/IN5 ),
    .O(\U1/U1/CurrState_Sreg0_FFD3_MC.D2_PT_2 )
  );
  X_AND6 \U1/U1/CurrState_Sreg0_FFD3_MC.D2_PT_3_442  (
    .I0(\MSPReset_II/UIM ),
    .I1(\NlwInverterSignal_U1/U1/CurrState_Sreg0_FFD3_MC.D2_PT_3/IN1 ),
    .I2(\U1/U1/CurrState_Sreg0_FFD2 ),
    .I3(\NlwInverterSignal_U1/U1/CurrState_Sreg0_FFD3_MC.D2_PT_3/IN3 ),
    .I4(\PhaseA_Encoder0_II/UIM ),
    .I5(\PhaseB_Encoder0_II/UIM ),
    .O(\U1/U1/CurrState_Sreg0_FFD3_MC.D2_PT_3 )
  );
  X_OR4 \U1/U1/CurrState_Sreg0_FFD3_MC.D2_443  (
    .I0(\U1/U1/CurrState_Sreg0_FFD3_MC.D2_PT_0 ),
    .I1(\U1/U1/CurrState_Sreg0_FFD3_MC.D2_PT_1 ),
    .I2(\U1/U1/CurrState_Sreg0_FFD3_MC.D2_PT_2 ),
    .I3(\U1/U1/CurrState_Sreg0_FFD3_MC.D2_PT_3 ),
    .O(\U1/U1/CurrState_Sreg0_FFD3_MC.D2 )
  );
  X_BUF \U1/U1/CurrState_Sreg0_FFD2_444  (
    .I(\U1/U1/CurrState_Sreg0_FFD2_MC.Q ),
    .O(\U1/U1/CurrState_Sreg0_FFD2 )
  );
  X_FF \U1/U1/CurrState_Sreg0_FFD2_MC.REG  (
    .I(\U1/U1/CurrState_Sreg0_FFD2_MC.D ),
    .CE(Vcc),
    .CLK(\Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\U1/U1/CurrState_Sreg0_FFD2_MC.Q )
  );
  X_XOR2 \U1/U1/CurrState_Sreg0_FFD2_MC.D_445  (
    .I0(\U1/U1/CurrState_Sreg0_FFD2_MC.D1 ),
    .I1(\U1/U1/CurrState_Sreg0_FFD2_MC.D2 ),
    .O(\U1/U1/CurrState_Sreg0_FFD2_MC.D )
  );
  X_ZERO \U1/U1/CurrState_Sreg0_FFD2_MC.D1_446  (
    .O(\U1/U1/CurrState_Sreg0_FFD2_MC.D1 )
  );
  X_AND6 \U1/U1/CurrState_Sreg0_FFD2_MC.D2_PT_0_447  (
    .I0(\MSPReset_II/UIM ),
    .I1(\U1/U1/CurrState_Sreg0_FFD1 ),
    .I2(\U1/U1/CurrState_Sreg0_FFD3 ),
    .I3(\U1/U1/CurrState_Sreg0_FFD2 ),
    .I4(\NlwInverterSignal_U1/U1/CurrState_Sreg0_FFD2_MC.D2_PT_0/IN4 ),
    .I5(\PhaseB_Encoder0_II/UIM ),
    .O(\U1/U1/CurrState_Sreg0_FFD2_MC.D2_PT_0 )
  );
  X_AND6 \U1/U1/CurrState_Sreg0_FFD2_MC.D2_PT_1_448  (
    .I0(\MSPReset_II/UIM ),
    .I1(\U1/U1/CurrState_Sreg0_FFD1 ),
    .I2(\NlwInverterSignal_U1/U1/CurrState_Sreg0_FFD2_MC.D2_PT_1/IN2 ),
    .I3(\U1/U1/CurrState_Sreg0_FFD2 ),
    .I4(\NlwInverterSignal_U1/U1/CurrState_Sreg0_FFD2_MC.D2_PT_1/IN4 ),
    .I5(\NlwInverterSignal_U1/U1/CurrState_Sreg0_FFD2_MC.D2_PT_1/IN5 ),
    .O(\U1/U1/CurrState_Sreg0_FFD2_MC.D2_PT_1 )
  );
  X_AND6 \U1/U1/CurrState_Sreg0_FFD2_MC.D2_PT_2_449  (
    .I0(\MSPReset_II/UIM ),
    .I1(\U1/U1/CurrState_Sreg0_FFD1 ),
    .I2(\NlwInverterSignal_U1/U1/CurrState_Sreg0_FFD2_MC.D2_PT_2/IN2 ),
    .I3(\NlwInverterSignal_U1/U1/CurrState_Sreg0_FFD2_MC.D2_PT_2/IN3 ),
    .I4(\PhaseA_Encoder0_II/UIM ),
    .I5(\PhaseB_Encoder0_II/UIM ),
    .O(\U1/U1/CurrState_Sreg0_FFD2_MC.D2_PT_2 )
  );
  X_AND6 \U1/U1/CurrState_Sreg0_FFD2_MC.D2_PT_3_450  (
    .I0(\MSPReset_II/UIM ),
    .I1(\U1/U1/CurrState_Sreg0_FFD1 ),
    .I2(\U1/U1/CurrState_Sreg0_FFD2 ),
    .I3(\NlwInverterSignal_U1/U1/CurrState_Sreg0_FFD2_MC.D2_PT_3/IN3 ),
    .I4(\PhaseA_Encoder0_II/UIM ),
    .I5(\NlwInverterSignal_U1/U1/CurrState_Sreg0_FFD2_MC.D2_PT_3/IN5 ),
    .O(\U1/U1/CurrState_Sreg0_FFD2_MC.D2_PT_3 )
  );
  X_AND6 \U1/U1/CurrState_Sreg0_FFD2_MC.D2_PT_4_451  (
    .I0(\MSPReset_II/UIM ),
    .I1(\NlwInverterSignal_U1/U1/CurrState_Sreg0_FFD2_MC.D2_PT_4/IN1 ),
    .I2(\U1/U1/CurrState_Sreg0_FFD3 ),
    .I3(\U1/U1/CurrState_Sreg0_FFD2 ),
    .I4(\NlwInverterSignal_U1/U1/CurrState_Sreg0_FFD2_MC.D2_PT_4/IN4 ),
    .I5(\NlwInverterSignal_U1/U1/CurrState_Sreg0_FFD2_MC.D2_PT_4/IN5 ),
    .O(\U1/U1/CurrState_Sreg0_FFD2_MC.D2_PT_4 )
  );
  X_AND6 \U1/U1/CurrState_Sreg0_FFD2_MC.D2_PT_5_452  (
    .I0(\MSPReset_II/UIM ),
    .I1(\NlwInverterSignal_U1/U1/CurrState_Sreg0_FFD2_MC.D2_PT_5/IN1 ),
    .I2(\U1/U1/CurrState_Sreg0_FFD3 ),
    .I3(\NlwInverterSignal_U1/U1/CurrState_Sreg0_FFD2_MC.D2_PT_5/IN3 ),
    .I4(\PhaseA_Encoder0_II/UIM ),
    .I5(\PhaseB_Encoder0_II/UIM ),
    .O(\U1/U1/CurrState_Sreg0_FFD2_MC.D2_PT_5 )
  );
  X_AND6 \U1/U1/CurrState_Sreg0_FFD2_MC.D2_PT_6_453  (
    .I0(\MSPReset_II/UIM ),
    .I1(\NlwInverterSignal_U1/U1/CurrState_Sreg0_FFD2_MC.D2_PT_6/IN1 ),
    .I2(\NlwInverterSignal_U1/U1/CurrState_Sreg0_FFD2_MC.D2_PT_6/IN2 ),
    .I3(\U1/U1/CurrState_Sreg0_FFD2 ),
    .I4(\NlwInverterSignal_U1/U1/CurrState_Sreg0_FFD2_MC.D2_PT_6/IN4 ),
    .I5(\PhaseB_Encoder0_II/UIM ),
    .O(\U1/U1/CurrState_Sreg0_FFD2_MC.D2_PT_6 )
  );
  X_AND6 \U1/U1/CurrState_Sreg0_FFD2_MC.D2_PT_7_454  (
    .I0(\MSPReset_II/UIM ),
    .I1(\NlwInverterSignal_U1/U1/CurrState_Sreg0_FFD2_MC.D2_PT_7/IN1 ),
    .I2(\NlwInverterSignal_U1/U1/CurrState_Sreg0_FFD2_MC.D2_PT_7/IN2 ),
    .I3(\NlwInverterSignal_U1/U1/CurrState_Sreg0_FFD2_MC.D2_PT_7/IN3 ),
    .I4(\PhaseA_Encoder0_II/UIM ),
    .I5(\NlwInverterSignal_U1/U1/CurrState_Sreg0_FFD2_MC.D2_PT_7/IN5 ),
    .O(\U1/U1/CurrState_Sreg0_FFD2_MC.D2_PT_7 )
  );
  X_OR8 \U1/U1/CurrState_Sreg0_FFD2_MC.D2_455  (
    .I0(\U1/U1/CurrState_Sreg0_FFD2_MC.D2_PT_0 ),
    .I1(\U1/U1/CurrState_Sreg0_FFD2_MC.D2_PT_1 ),
    .I2(\U1/U1/CurrState_Sreg0_FFD2_MC.D2_PT_2 ),
    .I3(\U1/U1/CurrState_Sreg0_FFD2_MC.D2_PT_3 ),
    .I4(\U1/U1/CurrState_Sreg0_FFD2_MC.D2_PT_4 ),
    .I5(\U1/U1/CurrState_Sreg0_FFD2_MC.D2_PT_5 ),
    .I6(\U1/U1/CurrState_Sreg0_FFD2_MC.D2_PT_6 ),
    .I7(\U1/U1/CurrState_Sreg0_FFD2_MC.D2_PT_7 ),
    .O(\U1/U1/CurrState_Sreg0_FFD2_MC.D2 )
  );
  X_BUF \U1/U1/CurrState_Sreg0_FFD4_456  (
    .I(\U1/U1/CurrState_Sreg0_FFD4_MC.Q ),
    .O(\U1/U1/CurrState_Sreg0_FFD4 )
  );
  X_FF \U1/U1/CurrState_Sreg0_FFD4_MC.REG  (
    .I(\U1/U1/CurrState_Sreg0_FFD4_MC.D ),
    .CE(Vcc),
    .CLK(\Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\U1/U1/CurrState_Sreg0_FFD4_MC.Q )
  );
  X_XOR2 \U1/U1/CurrState_Sreg0_FFD4_MC.D_457  (
    .I0(\U1/U1/CurrState_Sreg0_FFD4_MC.D1 ),
    .I1(\U1/U1/CurrState_Sreg0_FFD4_MC.D2 ),
    .O(\U1/U1/CurrState_Sreg0_FFD4_MC.D )
  );
  X_AND7 \U1/U1/CurrState_Sreg0_FFD4_MC.D1_458  (
    .I0(\MSPReset_II/UIM ),
    .I1(\NlwInverterSignal_U1/U1/CurrState_Sreg0_FFD4_MC.D1/IN1 ),
    .I2(\U1/U1/CurrState_Sreg0_FFD3 ),
    .I3(\NlwInverterSignal_U1/U1/CurrState_Sreg0_FFD4_MC.D1/IN3 ),
    .I4(\NlwInverterSignal_U1/U1/CurrState_Sreg0_FFD4_MC.D1/IN4 ),
    .I5(\NlwInverterSignal_U1/U1/CurrState_Sreg0_FFD4_MC.D1/IN5 ),
    .I6(\NlwInverterSignal_U1/U1/CurrState_Sreg0_FFD4_MC.D1/IN6 ),
    .O(\U1/U1/CurrState_Sreg0_FFD4_MC.D1 )
  );
  X_ZERO \U1/U1/CurrState_Sreg0_FFD4_MC.D2_459  (
    .O(\U1/U1/CurrState_Sreg0_FFD4_MC.D2 )
  );
  X_BUF N_PZ_982_460 (
    .I(\N_PZ_982_MC.Q ),
    .O(N_PZ_982)
  );
  X_BUF \N_PZ_982_MC.Q_461  (
    .I(\N_PZ_982_MC.D ),
    .O(\N_PZ_982_MC.Q )
  );
  X_XOR2 \N_PZ_982_MC.D_462  (
    .I0(\N_PZ_982_MC.D1 ),
    .I1(\N_PZ_982_MC.D2 ),
    .O(\N_PZ_982_MC.D )
  );
  X_AND2 \N_PZ_982_MC.D1_463  (
    .I0(\MSPReset_II/UIM ),
    .I1(\NlwInverterSignal_N_PZ_982_MC.D1/IN1 ),
    .O(\N_PZ_982_MC.D1 )
  );
  X_ZERO \N_PZ_982_MC.D2_464  (
    .O(\N_PZ_982_MC.D2 )
  );
  X_BUF N_PZ_1018_465 (
    .I(\N_PZ_1018_MC.Q ),
    .O(N_PZ_1018)
  );
  X_BUF \N_PZ_1018_MC.Q_466  (
    .I(\N_PZ_1018_MC.D ),
    .O(\N_PZ_1018_MC.Q )
  );
  X_XOR2 \N_PZ_1018_MC.D_467  (
    .I0(\N_PZ_1018_MC.D1 ),
    .I1(\N_PZ_1018_MC.D2 ),
    .O(\N_PZ_1018_MC.D )
  );
  X_ZERO \N_PZ_1018_MC.D1_468  (
    .O(\N_PZ_1018_MC.D1 )
  );
  X_AND6 \N_PZ_1018_MC.D2_PT_0_469  (
    .I0(\NlwInverterSignal_N_PZ_1018_MC.D2_PT_0/IN0 ),
    .I1(\NlwInverterSignal_N_PZ_1018_MC.D2_PT_0/IN1 ),
    .I2(\NlwInverterSignal_N_PZ_1018_MC.D2_PT_0/IN2 ),
    .I3(\U1/U4/LatchEdge0r ),
    .I4(\NlwInverterSignal_N_PZ_1018_MC.D2_PT_0/IN4 ),
    .I5(\outDATA<6>\$WA3.UIM ),
    .O(\N_PZ_1018_MC.D2_PT_0 )
  );
  X_AND6 \N_PZ_1018_MC.D2_PT_1_470  (
    .I0(\NlwInverterSignal_N_PZ_1018_MC.D2_PT_1/IN0 ),
    .I1(\NlwInverterSignal_N_PZ_1018_MC.D2_PT_1/IN1 ),
    .I2(\NlwInverterSignal_N_PZ_1018_MC.D2_PT_1/IN2 ),
    .I3(\NlwInverterSignal_N_PZ_1018_MC.D2_PT_1/IN3 ),
    .I4(\U1/U4/InEdge0r ),
    .I5(\NlwInverterSignal_N_PZ_1018_MC.D2_PT_1/IN5 ),
    .O(\N_PZ_1018_MC.D2_PT_1 )
  );
  X_OR2 \N_PZ_1018_MC.D2_471  (
    .I0(\N_PZ_1018_MC.D2_PT_0 ),
    .I1(\N_PZ_1018_MC.D2_PT_1 ),
    .O(\N_PZ_1018_MC.D2 )
  );
  X_BUF NET2501_472 (
    .I(\NET2501_MC.Q ),
    .O(NET2501)
  );
  X_XOR2 NET2501_MC_tsimcreated_xor__473 (
    .I0(\NET2501_MC.D ),
    .I1(\NET2501_MC.Q ),
    .O(NET2501_MC_tsimcreated_xor_)
  );
  X_FF \NET2501_MC.REG  (
    .I(NET2501_MC_tsimcreated_xor_),
    .CE(Vcc),
    .CLK(\NET2501_MC.REG_tsimcreated_inv_Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\NET2501_MC.Q )
  );
  X_INV \NET2501_MC.REG_tsimcreated_inv_Mclk_II/FCLK_474  (
    .I(\Mclk_II/FCLK ),
    .O(\NET2501_MC.REG_tsimcreated_inv_Mclk_II/FCLK )
  );
  X_XOR2 \NET2501_MC.D_475  (
    .I0(\NET2501_MC.D1 ),
    .I1(\NET2501_MC.D2 ),
    .O(\NET2501_MC.D )
  );
  X_ZERO \NET2501_MC.D1_476  (
    .O(\NET2501_MC.D1 )
  );
  X_AND2 \NET2501_MC.D2_PT_0_477  (
    .I0(\MSPReset_II/UIM ),
    .I1(N_PZ_1018),
    .O(\NET2501_MC.D2_PT_0 )
  );
  X_AND5 \NET2501_MC.D2_PT_1_478  (
    .I0(\MSPReset_II/UIM ),
    .I1(\AD<5>_II/UIM ),
    .I2(DCORIFGw),
    .I3(\NlwInverterSignal_NET2501_MC.D2_PT_1/IN3 ),
    .I4(NET2501),
    .O(\NET2501_MC.D2_PT_1 )
  );
  X_OR2 \NET2501_MC.D2_479  (
    .I0(\NET2501_MC.D2_PT_0 ),
    .I1(\NET2501_MC.D2_PT_1 ),
    .O(\NET2501_MC.D2 )
  );
  X_BUF \U1/U4/LatchEdge0r_480  (
    .I(\U1/U4/LatchEdge0r_MC.Q ),
    .O(\U1/U4/LatchEdge0r )
  );
  X_FF \U1/U4/LatchEdge0r_MC.REG  (
    .I(\U1/U4/LatchEdge0r_MC.D ),
    .CE(Vcc),
    .CLK(\U1/U4/LatchEdge0r_MC.REG_tsimcreated_inv_Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\U1/U4/LatchEdge0r_MC.Q )
  );
  X_INV \U1/U4/LatchEdge0r_MC.REG_tsimcreated_inv_Mclk_II/FCLK_481  (
    .I(\Mclk_II/FCLK ),
    .O(\U1/U4/LatchEdge0r_MC.REG_tsimcreated_inv_Mclk_II/FCLK )
  );
  X_XOR2 \U1/U4/LatchEdge0r_MC.D_482  (
    .I0(\U1/U4/LatchEdge0r_MC.D1 ),
    .I1(\U1/U4/LatchEdge0r_MC.D2 ),
    .O(\U1/U4/LatchEdge0r_MC.D )
  );
  X_ZERO \U1/U4/LatchEdge0r_MC.D1_483  (
    .O(\U1/U4/LatchEdge0r_MC.D1 )
  );
  X_AND3 \U1/U4/LatchEdge0r_MC.D2_PT_0_484  (
    .I0(\MSPReset_II/UIM ),
    .I1(\AD<2>_II/UIM ),
    .I2(DCORENCCTLw),
    .O(\U1/U4/LatchEdge0r_MC.D2_PT_0 )
  );
  X_AND3 \U1/U4/LatchEdge0r_MC.D2_PT_1_485  (
    .I0(\MSPReset_II/UIM ),
    .I1(\NlwInverterSignal_U1/U4/LatchEdge0r_MC.D2_PT_1/IN1 ),
    .I2(\U1/U4/LatchEdge0r ),
    .O(\U1/U4/LatchEdge0r_MC.D2_PT_1 )
  );
  X_OR2 \U1/U4/LatchEdge0r_MC.D2_486  (
    .I0(\U1/U4/LatchEdge0r_MC.D2_PT_0 ),
    .I1(\U1/U4/LatchEdge0r_MC.D2_PT_1 ),
    .O(\U1/U4/LatchEdge0r_MC.D2 )
  );
  X_BUF \outDATA<6>\$WA3.UIM_487  (
    .I(\outDATA<6>\$WA3.UIM_MC.Q ),
    .O(\outDATA<6>\$WA3.UIM )
  );
  X_BUF \outDATA<6>\$WA3.UIM_MC.Q_488  (
    .I(\outDATA<6>\$WA3.UIM_MC.D ),
    .O(\outDATA<6>\$WA3.UIM_MC.Q )
  );
  X_XOR2 \outDATA<6>\$WA3.UIM_MC.D_489  (
    .I0(\outDATA<6>\$WA3.UIM_MC.D1 ),
    .I1(\outDATA<6>\$WA3.UIM_MC.D2 ),
    .O(\outDATA<6>\$WA3.UIM_MC.D )
  );
  X_AND2 \outDATA<6>\$WA3.UIM_MC.D1_490  (
    .I0(\GP_Motor0_0_II/UIM ),
    .I1(\GP_Motor0_0_II/UIM ),
    .O(\outDATA<6>\$WA3.UIM_MC.D1 )
  );
  X_ZERO \outDATA<6>\$WA3.UIM_MC.D2_491  (
    .O(\outDATA<6>\$WA3.UIM_MC.D2 )
  );
  X_BUF \U1/U4/Latch0r<8>  (
    .I(\U1/U4/Latch0r<8>_MC.Q ),
    .O(\U1/U4/Latch0r [8])
  );
  X_FF \U1/U4/Latch0r<8>_MC.REG  (
    .I(\U1/U4/Latch0r<8>_MC.D ),
    .CE(Vcc),
    .CLK(\U1/U4/Latch0r<8>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\U1/U4/Latch0r<8>_MC.Q )
  );
  X_INV \U1/U4/Latch0r<8>_MC.REG_tsimcreated_inv_Mclk_II/FCLK_492  (
    .I(\Mclk_II/FCLK ),
    .O(\U1/U4/Latch0r<8>_MC.REG_tsimcreated_inv_Mclk_II/FCLK )
  );
  X_XOR2 \U1/U4/Latch0r<8>_MC.D_493  (
    .I0(\U1/U4/Latch0r<8>_MC.D1 ),
    .I1(\U1/U4/Latch0r<8>_MC.D2 ),
    .O(\U1/U4/Latch0r<8>_MC.D )
  );
  X_ZERO \U1/U4/Latch0r<8>_MC.D1_494  (
    .O(\U1/U4/Latch0r<8>_MC.D1 )
  );
  X_AND3 \U1/U4/Latch0r<8>_MC.D2_PT_0_495  (
    .I0(\MSPReset_II/UIM ),
    .I1(\U1/U4/Latch0r [8]),
    .I2(\NlwInverterSignal_U1/U4/Latch0r<8>_MC.D2_PT_0/IN2 ),
    .O(\U1/U4/Latch0r<8>_MC.D2_PT_0 )
  );
  X_AND3 \U1/U4/Latch0r<8>_MC.D2_PT_1_496  (
    .I0(\MSPReset_II/UIM ),
    .I1(N_PZ_1018),
    .I2(\U1/Channel0 [8]),
    .O(\U1/U4/Latch0r<8>_MC.D2_PT_1 )
  );
  X_OR2 \U1/U4/Latch0r<8>_MC.D2_497  (
    .I0(\U1/U4/Latch0r<8>_MC.D2_PT_0 ),
    .I1(\U1/U4/Latch0r<8>_MC.D2_PT_1 ),
    .O(\U1/U4/Latch0r<8>_MC.D2 )
  );
  X_BUF \U1/Channel0<8>  (
    .I(\U1/Channel0<8>_MC.Q ),
    .O(\U1/Channel0 [8])
  );
  X_XOR2 \U1/Channel0<8>_MC_tsimcreated_xor__498  (
    .I0(\U1/Channel0<8>_MC.D ),
    .I1(\U1/Channel0<8>_MC.Q ),
    .O(\U1/Channel0<8>_MC_tsimcreated_xor_ )
  );
  X_FF \U1/Channel0<8>_MC.REG  (
    .I(\U1/Channel0<8>_MC_tsimcreated_xor_ ),
    .CE(Vcc),
    .CLK(\Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\U1/Channel0<8>_MC.Q )
  );
  X_XOR2 \U1/Channel0<8>_MC.D_499  (
    .I0(\U1/Channel0<8>_MC.D1 ),
    .I1(\U1/Channel0<8>_MC.D2 ),
    .O(\U1/Channel0<8>_MC.D )
  );
  X_AND3 \U1/Channel0<8>_MC.D1_500  (
    .I0(\U1/Channel0 [8]),
    .I1(\NlwInverterSignal_U1/Channel0<8>_MC.D1/IN1 ),
    .I2(N_PZ_1024),
    .O(\U1/Channel0<8>_MC.D1 )
  );
  X_AND3 \U1/Channel0<8>_MC.D2_PT_0_501  (
    .I0(\NlwInverterSignal_U1/Channel0<8>_MC.D2_PT_0/IN0 ),
    .I1(\U1/Channel0 [8]),
    .I2(\U1/U2/location_Maddsub__n0000__n0075 [0]),
    .O(\U1/Channel0<8>_MC.D2_PT_0 )
  );
  X_AND3 \U1/Channel0<8>_MC.D2_PT_1_502  (
    .I0(\NlwInverterSignal_U1/Channel0<8>_MC.D2_PT_1/IN0 ),
    .I1(\U1/Channel0 [8]),
    .I2(\NlwInverterSignal_U1/Channel0<8>_MC.D2_PT_1/IN2 ),
    .O(\U1/Channel0<8>_MC.D2_PT_1 )
  );
  X_AND3 \U1/Channel0<8>_MC.D2_PT_2_503  (
    .I0(\NlwInverterSignal_U1/Channel0<8>_MC.D2_PT_2/IN0 ),
    .I1(\U1/U2/location_Maddsub__n0000__n0075 [0]),
    .I2(N_PZ_1021),
    .O(\U1/Channel0<8>_MC.D2_PT_2 )
  );
  X_AND7 \U1/Channel0<8>_MC.D2_PT_3_504  (
    .I0(\NlwInverterSignal_U1/Channel0<8>_MC.D2_PT_3/IN0 ),
    .I1(\U1/U2/location_Maddsub__n0000__n0075 [0]),
    .I2(N_PZ_1024),
    .I3(\U1/Channel0 [5]),
    .I4(\NlwInverterSignal_U1/Channel0<8>_MC.D2_PT_3/IN4 ),
    .I5(\U1/Channel0 [6]),
    .I6(\U1/Channel0 [7]),
    .O(\U1/Channel0<8>_MC.D2_PT_3 )
  );
  X_AND8 \U1/Channel0<8>_MC.D2_PT_4_505  (
    .I0(\U1/Channel0 [8]),
    .I1(\NlwInverterSignal_U1/Channel0<8>_MC.D2_PT_4/IN1 ),
    .I2(\NlwInverterSignal_U1/Channel0<8>_MC.D2_PT_4/IN2 ),
    .I3(N_PZ_1021),
    .I4(\NlwInverterSignal_U1/Channel0<8>_MC.D2_PT_4/IN4 ),
    .I5(\U1/U2/location_Maddsub__n0000__n0067 [0]),
    .I6(\NlwInverterSignal_U1/Channel0<8>_MC.D2_PT_4/IN6 ),
    .I7(\NlwInverterSignal_U1/Channel0<8>_MC.D2_PT_4/IN7 ),
    .O(\U1/Channel0<8>_MC.D2_PT_4 )
  );
  X_AND16 \U1/Channel0<8>_MC.D2_PT_5_506  (
    .I0(\MSPReset_II/UIM ),
    .I1(\NlwInverterSignal_U1/Channel0<8>_MC.D2_PT_5/IN1 ),
    .I2(\U1/Channel0 [8]),
    .I3(\NlwInverterSignal_U1/Channel0<8>_MC.D2_PT_5/IN3 ),
    .I4(N_PZ_1024),
    .I5(\U1/Channel0 [5]),
    .I6(\NlwInverterSignal_U1/Channel0<8>_MC.D2_PT_5/IN6 ),
    .I7(\U1/Channel0 [6]),
    .I8(\NlwInverterSignal_U1/Channel0<8>_MC.D2_PT_5/IN8 ),
    .I9(Vcc),
    .I10(Vcc),
    .I11(Vcc),
    .I12(Vcc),
    .I13(Vcc),
    .I14(Vcc),
    .I15(Vcc),
    .O(\U1/Channel0<8>_MC.D2_PT_5 )
  );
  X_OR6 \U1/Channel0<8>_MC.D2_507  (
    .I0(\U1/Channel0<8>_MC.D2_PT_0 ),
    .I1(\U1/Channel0<8>_MC.D2_PT_1 ),
    .I2(\U1/Channel0<8>_MC.D2_PT_2 ),
    .I3(\U1/Channel0<8>_MC.D2_PT_3 ),
    .I4(\U1/Channel0<8>_MC.D2_PT_4 ),
    .I5(\U1/Channel0<8>_MC.D2_PT_5 ),
    .O(\U1/Channel0<8>_MC.D2 )
  );
  X_BUF \U1/U2/location_Maddsub__n0000__n0075<0>  (
    .I(\U1/U2/location_Maddsub__n0000__n0075<0>_MC.Q ),
    .O(\U1/U2/location_Maddsub__n0000__n0075 [0])
  );
  X_BUF \U1/U2/location_Maddsub__n0000__n0075<0>_MC.Q_508  (
    .I(\U1/U2/location_Maddsub__n0000__n0075<0>_MC.D ),
    .O(\U1/U2/location_Maddsub__n0000__n0075<0>_MC.Q )
  );
  X_XOR2 \U1/U2/location_Maddsub__n0000__n0075<0>_MC.D_509  (
    .I0(\U1/U2/location_Maddsub__n0000__n0075<0>_MC.D1 ),
    .I1(\U1/U2/location_Maddsub__n0000__n0075<0>_MC.D2 ),
    .O(\U1/U2/location_Maddsub__n0000__n0075<0>_MC.D )
  );
  X_AND2 \U1/U2/location_Maddsub__n0000__n0075<0>_MC.D1_510  (
    .I0(N_PZ_997),
    .I1(N_PZ_997),
    .O(\U1/U2/location_Maddsub__n0000__n0075<0>_MC.D1 )
  );
  X_AND6 \U1/U2/location_Maddsub__n0000__n0075<0>_MC.D2_PT_0_511  (
    .I0(\U1/Channel0 [8]),
    .I1(\U1/Channel0 [5]),
    .I2(\NlwInverterSignal_U1/U2/location_Maddsub__n0000__n0075<0>_MC.D2_PT_0/IN2 ),
    .I3(\U1/Channel0 [6]),
    .I4(\U1/Channel0 [7]),
    .I5(N_PZ_997),
    .O(\U1/U2/location_Maddsub__n0000__n0075<0>_MC.D2_PT_0 )
  );
  X_AND6 \U1/U2/location_Maddsub__n0000__n0075<0>_MC.D2_PT_1_512  (
    .I0(\NlwInverterSignal_U1/U2/location_Maddsub__n0000__n0075<0>_MC.D2_PT_1/IN0 ),
    .I1(\NlwInverterSignal_U1/U2/location_Maddsub__n0000__n0075<0>_MC.D2_PT_1/IN1 ),
    .I2(\U1/U2/location_Maddsub__n0000__n0067 [0]),
    .I3(\NlwInverterSignal_U1/U2/location_Maddsub__n0000__n0075<0>_MC.D2_PT_1/IN3 ),
    .I4(\NlwInverterSignal_U1/U2/location_Maddsub__n0000__n0075<0>_MC.D2_PT_1/IN4 ),
    .I5(\NlwInverterSignal_U1/U2/location_Maddsub__n0000__n0075<0>_MC.D2_PT_1/IN5 ),
    .O(\U1/U2/location_Maddsub__n0000__n0075<0>_MC.D2_PT_1 )
  );
  X_OR2 \U1/U2/location_Maddsub__n0000__n0075<0>_MC.D2_513  (
    .I0(\U1/U2/location_Maddsub__n0000__n0075<0>_MC.D2_PT_0 ),
    .I1(\U1/U2/location_Maddsub__n0000__n0075<0>_MC.D2_PT_1 ),
    .O(\U1/U2/location_Maddsub__n0000__n0075<0>_MC.D2 )
  );
  X_BUF N_PZ_997_514 (
    .I(\N_PZ_997_MC.Q ),
    .O(N_PZ_997)
  );
  X_BUF \N_PZ_997_MC.Q_515  (
    .I(\N_PZ_997_MC.D ),
    .O(\N_PZ_997_MC.Q )
  );
  X_XOR2 \N_PZ_997_MC.D_516  (
    .I0(\N_PZ_997_MC.D1 ),
    .I1(\N_PZ_997_MC.D2 ),
    .O(\N_PZ_997_MC.D )
  );
  X_AND2 \N_PZ_997_MC.D1_517  (
    .I0(\U1/NET3721 ),
    .I1(\U1/NET3721 ),
    .O(\N_PZ_997_MC.D1 )
  );
  X_AND3 \N_PZ_997_MC.D2_PT_0_518  (
    .I0(\NlwInverterSignal_N_PZ_997_MC.D2_PT_0/IN0 ),
    .I1(\U1/U1/CurrState_Sreg0_FFD3 ),
    .I2(\NlwInverterSignal_N_PZ_997_MC.D2_PT_0/IN2 ),
    .O(\N_PZ_997_MC.D2_PT_0 )
  );
  X_AND3 \N_PZ_997_MC.D2_PT_1_519  (
    .I0(\NlwInverterSignal_N_PZ_997_MC.D2_PT_1/IN0 ),
    .I1(\U1/U1/CurrState_Sreg0_FFD2 ),
    .I2(\NlwInverterSignal_N_PZ_997_MC.D2_PT_1/IN2 ),
    .O(\N_PZ_997_MC.D2_PT_1 )
  );
  X_OR2 \N_PZ_997_MC.D2_520  (
    .I0(\N_PZ_997_MC.D2_PT_0 ),
    .I1(\N_PZ_997_MC.D2_PT_1 ),
    .O(\N_PZ_997_MC.D2 )
  );
  X_BUF \U1/NET3721_521  (
    .I(\U1/NET3721_MC.Q ),
    .O(\U1/NET3721 )
  );
  X_FF \U1/NET3721_MC.REG  (
    .I(\U1/NET3721_MC.D ),
    .CE(Vcc),
    .CLK(\U1/NET3721_MC.REG_tsimcreated_inv_Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\U1/NET3721_MC.Q )
  );
  X_INV \U1/NET3721_MC.REG_tsimcreated_inv_Mclk_II/FCLK_522  (
    .I(\Mclk_II/FCLK ),
    .O(\U1/NET3721_MC.REG_tsimcreated_inv_Mclk_II/FCLK )
  );
  X_XOR2 \U1/NET3721_MC.D_523  (
    .I0(\U1/NET3721_MC.D1 ),
    .I1(\U1/NET3721_MC.D2 ),
    .O(\U1/NET3721_MC.D )
  );
  X_ZERO \U1/NET3721_MC.D1_524  (
    .O(\U1/NET3721_MC.D1 )
  );
  X_AND3 \U1/NET3721_MC.D2_PT_0_525  (
    .I0(\MSPReset_II/UIM ),
    .I1(\AD<3>_II/UIM ),
    .I2(DCORENCCTLw),
    .O(\U1/NET3721_MC.D2_PT_0 )
  );
  X_AND3 \U1/NET3721_MC.D2_PT_1_526  (
    .I0(\MSPReset_II/UIM ),
    .I1(\NlwInverterSignal_U1/NET3721_MC.D2_PT_1/IN1 ),
    .I2(\U1/NET3721 ),
    .O(\U1/NET3721_MC.D2_PT_1 )
  );
  X_OR2 \U1/NET3721_MC.D2_527  (
    .I0(\U1/NET3721_MC.D2_PT_0 ),
    .I1(\U1/NET3721_MC.D2_PT_1 ),
    .O(\U1/NET3721_MC.D2 )
  );
  X_BUF \U1/Channel0<5>  (
    .I(\U1/Channel0<5>_MC.Q ),
    .O(\U1/Channel0 [5])
  );
  X_XOR2 \U1/Channel0<5>_MC_tsimcreated_xor__528  (
    .I0(\U1/Channel0<5>_MC.D ),
    .I1(\U1/Channel0<5>_MC.Q ),
    .O(\U1/Channel0<5>_MC_tsimcreated_xor_ )
  );
  X_FF \U1/Channel0<5>_MC.REG  (
    .I(\U1/Channel0<5>_MC_tsimcreated_xor_ ),
    .CE(Vcc),
    .CLK(\Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\U1/Channel0<5>_MC.Q )
  );
  X_XOR2 \U1/Channel0<5>_MC.D_529  (
    .I0(\U1/Channel0<5>_MC.D1 ),
    .I1(\U1/Channel0<5>_MC.D2 ),
    .O(\U1/Channel0<5>_MC.D )
  );
  X_ZERO \U1/Channel0<5>_MC.D1_530  (
    .O(\U1/Channel0<5>_MC.D1 )
  );
  X_AND2 \U1/Channel0<5>_MC.D2_PT_0_531  (
    .I0(\NlwInverterSignal_U1/Channel0<5>_MC.D2_PT_0/IN0 ),
    .I1(\U1/Channel0 [5]),
    .O(\U1/Channel0<5>_MC.D2_PT_0 )
  );
  X_AND2 \U1/Channel0<5>_MC.D2_PT_1_532  (
    .I0(N_PZ_1024),
    .I1(\NlwInverterSignal_U1/Channel0<5>_MC.D2_PT_1/IN1 ),
    .O(\U1/Channel0<5>_MC.D2_PT_1 )
  );
  X_AND2 \U1/Channel0<5>_MC.D2_PT_2_533  (
    .I0(N_PZ_1021),
    .I1(\U1/U2/location_Maddsub__n0000__n0067 [0]),
    .O(\U1/Channel0<5>_MC.D2_PT_2 )
  );
  X_OR3 \U1/Channel0<5>_MC.D2_534  (
    .I0(\U1/Channel0<5>_MC.D2_PT_0 ),
    .I1(\U1/Channel0<5>_MC.D2_PT_1 ),
    .I2(\U1/Channel0<5>_MC.D2_PT_2 ),
    .O(\U1/Channel0<5>_MC.D2 )
  );
  X_BUF \U1/U2/location_Maddsub__n0000__n0067<0>  (
    .I(\U1/U2/location_Maddsub__n0000__n0067<0>_MC.Q ),
    .O(\U1/U2/location_Maddsub__n0000__n0067 [0])
  );
  X_BUF \U1/U2/location_Maddsub__n0000__n0067<0>_MC.Q_535  (
    .I(\U1/U2/location_Maddsub__n0000__n0067<0>_MC.D ),
    .O(\U1/U2/location_Maddsub__n0000__n0067<0>_MC.Q )
  );
  X_XOR2 \U1/U2/location_Maddsub__n0000__n0067<0>_MC.D_536  (
    .I0(\U1/U2/location_Maddsub__n0000__n0067<0>_MC.D1 ),
    .I1(\U1/U2/location_Maddsub__n0000__n0067<0>_MC.D2 ),
    .O(\U1/U2/location_Maddsub__n0000__n0067<0>_MC.D )
  );
  X_AND2 \U1/U2/location_Maddsub__n0000__n0067<0>_MC.D1_537  (
    .I0(N_PZ_997),
    .I1(N_PZ_997),
    .O(\U1/U2/location_Maddsub__n0000__n0067<0>_MC.D1 )
  );
  X_AND6 \U1/U2/location_Maddsub__n0000__n0067<0>_MC.D2_PT_0_538  (
    .I0(\U1/Channel0 [0]),
    .I1(N_PZ_997),
    .I2(\U1/Channel0 [1]),
    .I3(\U1/Channel0 [2]),
    .I4(\U1/Channel0 [3]),
    .I5(\U1/Channel0 [4]),
    .O(\U1/U2/location_Maddsub__n0000__n0067<0>_MC.D2_PT_0 )
  );
  X_AND6 \U1/U2/location_Maddsub__n0000__n0067<0>_MC.D2_PT_1_539  (
    .I0(\NlwInverterSignal_U1/U2/location_Maddsub__n0000__n0067<0>_MC.D2_PT_1/IN0 ),
    .I1(\NlwInverterSignal_U1/U2/location_Maddsub__n0000__n0067<0>_MC.D2_PT_1/IN1 ),
    .I2(\NlwInverterSignal_U1/U2/location_Maddsub__n0000__n0067<0>_MC.D2_PT_1/IN2 ),
    .I3(\NlwInverterSignal_U1/U2/location_Maddsub__n0000__n0067<0>_MC.D2_PT_1/IN3 ),
    .I4(\NlwInverterSignal_U1/U2/location_Maddsub__n0000__n0067<0>_MC.D2_PT_1/IN4 ),
    .I5(\NlwInverterSignal_U1/U2/location_Maddsub__n0000__n0067<0>_MC.D2_PT_1/IN5 ),
    .O(\U1/U2/location_Maddsub__n0000__n0067<0>_MC.D2_PT_1 )
  );
  X_OR2 \U1/U2/location_Maddsub__n0000__n0067<0>_MC.D2_540  (
    .I0(\U1/U2/location_Maddsub__n0000__n0067<0>_MC.D2_PT_0 ),
    .I1(\U1/U2/location_Maddsub__n0000__n0067<0>_MC.D2_PT_1 ),
    .O(\U1/U2/location_Maddsub__n0000__n0067<0>_MC.D2 )
  );
  X_BUF \U1/Channel0<1>  (
    .I(\U1/Channel0<1>_MC.Q ),
    .O(\U1/Channel0 [1])
  );
  X_XOR2 \U1/Channel0<1>_MC_tsimcreated_xor__541  (
    .I0(\U1/Channel0<1>_MC.D ),
    .I1(\U1/Channel0<1>_MC.Q ),
    .O(\U1/Channel0<1>_MC_tsimcreated_xor_ )
  );
  X_FF \U1/Channel0<1>_MC.REG  (
    .I(\U1/Channel0<1>_MC_tsimcreated_xor_ ),
    .CE(Vcc),
    .CLK(\Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\U1/Channel0<1>_MC.Q )
  );
  X_XOR2 \U1/Channel0<1>_MC.D_542  (
    .I0(\U1/Channel0<1>_MC.D1 ),
    .I1(\U1/Channel0<1>_MC.D2 ),
    .O(\U1/Channel0<1>_MC.D )
  );
  X_ZERO \U1/Channel0<1>_MC.D1_543  (
    .O(\U1/Channel0<1>_MC.D1 )
  );
  X_AND2 \U1/Channel0<1>_MC.D2_PT_0_544  (
    .I0(\U1/Channel0 [0]),
    .I1(N_PZ_1024),
    .O(\U1/Channel0<1>_MC.D2_PT_0 )
  );
  X_AND2 \U1/Channel0<1>_MC.D2_PT_1_545  (
    .I0(\NlwInverterSignal_U1/Channel0<1>_MC.D2_PT_1/IN0 ),
    .I1(N_PZ_1021),
    .O(\U1/Channel0<1>_MC.D2_PT_1 )
  );
  X_AND2 \U1/Channel0<1>_MC.D2_PT_2_546  (
    .I0(\NlwInverterSignal_U1/Channel0<1>_MC.D2_PT_2/IN0 ),
    .I1(\U1/Channel0 [1]),
    .O(\U1/Channel0<1>_MC.D2_PT_2 )
  );
  X_OR3 \U1/Channel0<1>_MC.D2_547  (
    .I0(\U1/Channel0<1>_MC.D2_PT_0 ),
    .I1(\U1/Channel0<1>_MC.D2_PT_1 ),
    .I2(\U1/Channel0<1>_MC.D2_PT_2 ),
    .O(\U1/Channel0<1>_MC.D2 )
  );
  X_BUF N_PZ_1021_548 (
    .I(\N_PZ_1021_MC.Q ),
    .O(N_PZ_1021)
  );
  X_BUF \N_PZ_1021_MC.Q_549  (
    .I(\N_PZ_1021_MC.D ),
    .O(\N_PZ_1021_MC.Q )
  );
  X_XOR2 \N_PZ_1021_MC.D_550  (
    .I0(\N_PZ_1021_MC.D1 ),
    .I1(\N_PZ_1021_MC.D2 ),
    .O(\N_PZ_1021_MC.D )
  );
  X_ZERO \N_PZ_1021_MC.D1_551  (
    .O(\N_PZ_1021_MC.D1 )
  );
  X_AND7 \N_PZ_1021_MC.D2_PT_0_552  (
    .I0(\MSPReset_II/UIM ),
    .I1(\NlwInverterSignal_N_PZ_1021_MC.D2_PT_0/IN1 ),
    .I2(\U1/U1/CurrState_Sreg0_FFD1 ),
    .I3(\U1/U1/CurrState_Sreg0_FFD3 ),
    .I4(\NlwInverterSignal_N_PZ_1021_MC.D2_PT_0/IN4 ),
    .I5(\NlwInverterSignal_N_PZ_1021_MC.D2_PT_0/IN5 ),
    .I6(\NlwInverterSignal_N_PZ_1021_MC.D2_PT_0/IN6 ),
    .O(\N_PZ_1021_MC.D2_PT_0 )
  );
  X_AND7 \N_PZ_1021_MC.D2_PT_1_553  (
    .I0(\MSPReset_II/UIM ),
    .I1(\NlwInverterSignal_N_PZ_1021_MC.D2_PT_1/IN1 ),
    .I2(\NlwInverterSignal_N_PZ_1021_MC.D2_PT_1/IN2 ),
    .I3(\U1/U1/CurrState_Sreg0_FFD3 ),
    .I4(\NlwInverterSignal_N_PZ_1021_MC.D2_PT_1/IN4 ),
    .I5(\U1/U1/CurrState_Sreg0_FFD4 ),
    .I6(\U1/NET3721 ),
    .O(\N_PZ_1021_MC.D2_PT_1 )
  );
  X_OR2 \N_PZ_1021_MC.D2_554  (
    .I0(\N_PZ_1021_MC.D2_PT_0 ),
    .I1(\N_PZ_1021_MC.D2_PT_1 ),
    .O(\N_PZ_1021_MC.D2 )
  );
  X_BUF N_PZ_1024_555 (
    .I(\N_PZ_1024_MC.Q ),
    .O(N_PZ_1024)
  );
  X_BUF \N_PZ_1024_MC.Q_556  (
    .I(\N_PZ_1024_MC.D ),
    .O(\N_PZ_1024_MC.Q )
  );
  X_XOR2 \N_PZ_1024_MC.D_557  (
    .I0(\N_PZ_1024_MC.D1 ),
    .I1(\N_PZ_1024_MC.D2 ),
    .O(\N_PZ_1024_MC.D )
  );
  X_ZERO \N_PZ_1024_MC.D1_558  (
    .O(\N_PZ_1024_MC.D1 )
  );
  X_AND7 \N_PZ_1024_MC.D2_PT_0_559  (
    .I0(\MSPReset_II/UIM ),
    .I1(\NlwInverterSignal_N_PZ_1024_MC.D2_PT_0/IN1 ),
    .I2(\U1/U1/CurrState_Sreg0_FFD1 ),
    .I3(\U1/U1/CurrState_Sreg0_FFD3 ),
    .I4(\NlwInverterSignal_N_PZ_1024_MC.D2_PT_0/IN4 ),
    .I5(\NlwInverterSignal_N_PZ_1024_MC.D2_PT_0/IN5 ),
    .I6(\U1/NET3721 ),
    .O(\N_PZ_1024_MC.D2_PT_0 )
  );
  X_AND7 \N_PZ_1024_MC.D2_PT_1_560  (
    .I0(\MSPReset_II/UIM ),
    .I1(\NlwInverterSignal_N_PZ_1024_MC.D2_PT_1/IN1 ),
    .I2(\NlwInverterSignal_N_PZ_1024_MC.D2_PT_1/IN2 ),
    .I3(\U1/U1/CurrState_Sreg0_FFD3 ),
    .I4(\NlwInverterSignal_N_PZ_1024_MC.D2_PT_1/IN4 ),
    .I5(\U1/U1/CurrState_Sreg0_FFD4 ),
    .I6(\NlwInverterSignal_N_PZ_1024_MC.D2_PT_1/IN6 ),
    .O(\N_PZ_1024_MC.D2_PT_1 )
  );
  X_OR2 \N_PZ_1024_MC.D2_561  (
    .I0(\N_PZ_1024_MC.D2_PT_0 ),
    .I1(\N_PZ_1024_MC.D2_PT_1 ),
    .O(\N_PZ_1024_MC.D2 )
  );
  X_BUF \U1/Channel0<2>  (
    .I(\U1/Channel0<2>_MC.Q ),
    .O(\U1/Channel0 [2])
  );
  X_XOR2 \U1/Channel0<2>_MC_tsimcreated_xor__562  (
    .I0(\U1/Channel0<2>_MC.D ),
    .I1(\U1/Channel0<2>_MC.Q ),
    .O(\U1/Channel0<2>_MC_tsimcreated_xor_ )
  );
  X_FF \U1/Channel0<2>_MC.REG  (
    .I(\U1/Channel0<2>_MC_tsimcreated_xor_ ),
    .CE(Vcc),
    .CLK(\Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\U1/Channel0<2>_MC.Q )
  );
  X_XOR2 \U1/Channel0<2>_MC.D_563  (
    .I0(\U1/Channel0<2>_MC.D1 ),
    .I1(\U1/Channel0<2>_MC.D2 ),
    .O(\U1/Channel0<2>_MC.D )
  );
  X_ZERO \U1/Channel0<2>_MC.D1_564  (
    .O(\U1/Channel0<2>_MC.D1 )
  );
  X_AND2 \U1/Channel0<2>_MC.D2_PT_0_565  (
    .I0(\NlwInverterSignal_U1/Channel0<2>_MC.D2_PT_0/IN0 ),
    .I1(\U1/Channel0 [2]),
    .O(\U1/Channel0<2>_MC.D2_PT_0 )
  );
  X_AND3 \U1/Channel0<2>_MC.D2_PT_1_566  (
    .I0(\U1/Channel0 [0]),
    .I1(N_PZ_1024),
    .I2(\U1/Channel0 [1]),
    .O(\U1/Channel0<2>_MC.D2_PT_1 )
  );
  X_AND3 \U1/Channel0<2>_MC.D2_PT_2_567  (
    .I0(\NlwInverterSignal_U1/Channel0<2>_MC.D2_PT_2/IN0 ),
    .I1(N_PZ_1021),
    .I2(\NlwInverterSignal_U1/Channel0<2>_MC.D2_PT_2/IN2 ),
    .O(\U1/Channel0<2>_MC.D2_PT_2 )
  );
  X_OR3 \U1/Channel0<2>_MC.D2_568  (
    .I0(\U1/Channel0<2>_MC.D2_PT_0 ),
    .I1(\U1/Channel0<2>_MC.D2_PT_1 ),
    .I2(\U1/Channel0<2>_MC.D2_PT_2 ),
    .O(\U1/Channel0<2>_MC.D2 )
  );
  X_BUF \U1/Channel0<3>  (
    .I(\U1/Channel0<3>_MC.Q ),
    .O(\U1/Channel0 [3])
  );
  X_XOR2 \U1/Channel0<3>_MC_tsimcreated_xor__569  (
    .I0(\U1/Channel0<3>_MC.D ),
    .I1(\U1/Channel0<3>_MC.Q ),
    .O(\U1/Channel0<3>_MC_tsimcreated_xor_ )
  );
  X_FF \U1/Channel0<3>_MC.REG  (
    .I(\U1/Channel0<3>_MC_tsimcreated_xor_ ),
    .CE(Vcc),
    .CLK(\Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\U1/Channel0<3>_MC.Q )
  );
  X_XOR2 \U1/Channel0<3>_MC.D_570  (
    .I0(\U1/Channel0<3>_MC.D1 ),
    .I1(\U1/Channel0<3>_MC.D2 ),
    .O(\U1/Channel0<3>_MC.D )
  );
  X_ZERO \U1/Channel0<3>_MC.D1_571  (
    .O(\U1/Channel0<3>_MC.D1 )
  );
  X_AND2 \U1/Channel0<3>_MC.D2_PT_0_572  (
    .I0(\NlwInverterSignal_U1/Channel0<3>_MC.D2_PT_0/IN0 ),
    .I1(\U1/Channel0 [3]),
    .O(\U1/Channel0<3>_MC.D2_PT_0 )
  );
  X_AND4 \U1/Channel0<3>_MC.D2_PT_1_573  (
    .I0(\U1/Channel0 [0]),
    .I1(N_PZ_1024),
    .I2(\U1/Channel0 [1]),
    .I3(\U1/Channel0 [2]),
    .O(\U1/Channel0<3>_MC.D2_PT_1 )
  );
  X_AND4 \U1/Channel0<3>_MC.D2_PT_2_574  (
    .I0(\NlwInverterSignal_U1/Channel0<3>_MC.D2_PT_2/IN0 ),
    .I1(N_PZ_1021),
    .I2(\NlwInverterSignal_U1/Channel0<3>_MC.D2_PT_2/IN2 ),
    .I3(\NlwInverterSignal_U1/Channel0<3>_MC.D2_PT_2/IN3 ),
    .O(\U1/Channel0<3>_MC.D2_PT_2 )
  );
  X_OR3 \U1/Channel0<3>_MC.D2_575  (
    .I0(\U1/Channel0<3>_MC.D2_PT_0 ),
    .I1(\U1/Channel0<3>_MC.D2_PT_1 ),
    .I2(\U1/Channel0<3>_MC.D2_PT_2 ),
    .O(\U1/Channel0<3>_MC.D2 )
  );
  X_BUF \U1/Channel0<4>  (
    .I(\U1/Channel0<4>_MC.Q ),
    .O(\U1/Channel0 [4])
  );
  X_XOR2 \U1/Channel0<4>_MC_tsimcreated_xor__576  (
    .I0(\U1/Channel0<4>_MC.D ),
    .I1(\U1/Channel0<4>_MC.Q ),
    .O(\U1/Channel0<4>_MC_tsimcreated_xor_ )
  );
  X_FF \U1/Channel0<4>_MC.REG  (
    .I(\U1/Channel0<4>_MC_tsimcreated_xor_ ),
    .CE(Vcc),
    .CLK(\Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\U1/Channel0<4>_MC.Q )
  );
  X_XOR2 \U1/Channel0<4>_MC.D_577  (
    .I0(\U1/Channel0<4>_MC.D1 ),
    .I1(\U1/Channel0<4>_MC.D2 ),
    .O(\U1/Channel0<4>_MC.D )
  );
  X_AND3 \U1/Channel0<4>_MC.D1_578  (
    .I0(N_PZ_1024),
    .I1(\NlwInverterSignal_U1/Channel0<4>_MC.D1/IN1 ),
    .I2(\U1/Channel0 [4]),
    .O(\U1/Channel0<4>_MC.D1 )
  );
  X_AND3 \U1/Channel0<4>_MC.D2_PT_0_579  (
    .I0(\NlwInverterSignal_U1/Channel0<4>_MC.D2_PT_0/IN0 ),
    .I1(\NlwInverterSignal_U1/Channel0<4>_MC.D2_PT_0/IN1 ),
    .I2(\U1/Channel0 [4]),
    .O(\U1/Channel0<4>_MC.D2_PT_0 )
  );
  X_AND3 \U1/Channel0<4>_MC.D2_PT_1_580  (
    .I0(\NlwInverterSignal_U1/Channel0<4>_MC.D2_PT_1/IN0 ),
    .I1(\U1/U2/location_Maddsub__n0000__n0067 [0]),
    .I2(\U1/Channel0 [4]),
    .O(\U1/Channel0<4>_MC.D2_PT_1 )
  );
  X_AND3 \U1/Channel0<4>_MC.D2_PT_2_581  (
    .I0(N_PZ_1021),
    .I1(\U1/U2/location_Maddsub__n0000__n0067 [0]),
    .I2(\NlwInverterSignal_U1/Channel0<4>_MC.D2_PT_2/IN2 ),
    .O(\U1/Channel0<4>_MC.D2_PT_2 )
  );
  X_AND7 \U1/Channel0<4>_MC.D2_PT_3_582  (
    .I0(\U1/Channel0 [0]),
    .I1(N_PZ_1024),
    .I2(\U1/U2/location_Maddsub__n0000__n0067 [0]),
    .I3(\U1/Channel0 [1]),
    .I4(\U1/Channel0 [2]),
    .I5(\U1/Channel0 [3]),
    .I6(\NlwInverterSignal_U1/Channel0<4>_MC.D2_PT_3/IN6 ),
    .O(\U1/Channel0<4>_MC.D2_PT_3 )
  );
  X_AND8 \U1/Channel0<4>_MC.D2_PT_4_583  (
    .I0(\NlwInverterSignal_U1/Channel0<4>_MC.D2_PT_4/IN0 ),
    .I1(\NlwInverterSignal_U1/Channel0<4>_MC.D2_PT_4/IN1 ),
    .I2(N_PZ_1021),
    .I3(\NlwInverterSignal_U1/Channel0<4>_MC.D2_PT_4/IN3 ),
    .I4(\NlwInverterSignal_U1/Channel0<4>_MC.D2_PT_4/IN4 ),
    .I5(\NlwInverterSignal_U1/Channel0<4>_MC.D2_PT_4/IN5 ),
    .I6(\NlwInverterSignal_U1/Channel0<4>_MC.D2_PT_4/IN6 ),
    .I7(\U1/Channel0 [4]),
    .O(\U1/Channel0<4>_MC.D2_PT_4 )
  );
  X_AND16 \U1/Channel0<4>_MC.D2_PT_5_584  (
    .I0(\MSPReset_II/UIM ),
    .I1(\U1/Channel0 [0]),
    .I2(\NlwInverterSignal_U1/Channel0<4>_MC.D2_PT_5/IN2 ),
    .I3(N_PZ_1024),
    .I4(\NlwInverterSignal_U1/Channel0<4>_MC.D2_PT_5/IN4 ),
    .I5(\U1/Channel0 [1]),
    .I6(\U1/Channel0 [2]),
    .I7(\NlwInverterSignal_U1/Channel0<4>_MC.D2_PT_5/IN7 ),
    .I8(\U1/Channel0 [4]),
    .I9(Vcc),
    .I10(Vcc),
    .I11(Vcc),
    .I12(Vcc),
    .I13(Vcc),
    .I14(Vcc),
    .I15(Vcc),
    .O(\U1/Channel0<4>_MC.D2_PT_5 )
  );
  X_OR6 \U1/Channel0<4>_MC.D2_585  (
    .I0(\U1/Channel0<4>_MC.D2_PT_0 ),
    .I1(\U1/Channel0<4>_MC.D2_PT_1 ),
    .I2(\U1/Channel0<4>_MC.D2_PT_2 ),
    .I3(\U1/Channel0<4>_MC.D2_PT_3 ),
    .I4(\U1/Channel0<4>_MC.D2_PT_4 ),
    .I5(\U1/Channel0<4>_MC.D2_PT_5 ),
    .O(\U1/Channel0<4>_MC.D2 )
  );
  X_BUF \U1/Channel0<6>  (
    .I(\U1/Channel0<6>_MC.Q ),
    .O(\U1/Channel0 [6])
  );
  X_XOR2 \U1/Channel0<6>_MC_tsimcreated_xor__586  (
    .I0(\U1/Channel0<6>_MC.D ),
    .I1(\U1/Channel0<6>_MC.Q ),
    .O(\U1/Channel0<6>_MC_tsimcreated_xor_ )
  );
  X_FF \U1/Channel0<6>_MC.REG  (
    .I(\U1/Channel0<6>_MC_tsimcreated_xor_ ),
    .CE(Vcc),
    .CLK(\Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\U1/Channel0<6>_MC.Q )
  );
  X_XOR2 \U1/Channel0<6>_MC.D_587  (
    .I0(\U1/Channel0<6>_MC.D1 ),
    .I1(\U1/Channel0<6>_MC.D2 ),
    .O(\U1/Channel0<6>_MC.D )
  );
  X_ZERO \U1/Channel0<6>_MC.D1_588  (
    .O(\U1/Channel0<6>_MC.D1 )
  );
  X_AND2 \U1/Channel0<6>_MC.D2_PT_0_589  (
    .I0(\NlwInverterSignal_U1/Channel0<6>_MC.D2_PT_0/IN0 ),
    .I1(\U1/Channel0 [6]),
    .O(\U1/Channel0<6>_MC.D2_PT_0 )
  );
  X_AND3 \U1/Channel0<6>_MC.D2_PT_1_590  (
    .I0(N_PZ_1024),
    .I1(\U1/Channel0 [5]),
    .I2(\NlwInverterSignal_U1/Channel0<6>_MC.D2_PT_1/IN2 ),
    .O(\U1/Channel0<6>_MC.D2_PT_1 )
  );
  X_AND3 \U1/Channel0<6>_MC.D2_PT_2_591  (
    .I0(N_PZ_1021),
    .I1(\NlwInverterSignal_U1/Channel0<6>_MC.D2_PT_2/IN1 ),
    .I2(\U1/U2/location_Maddsub__n0000__n0067 [0]),
    .O(\U1/Channel0<6>_MC.D2_PT_2 )
  );
  X_OR3 \U1/Channel0<6>_MC.D2_592  (
    .I0(\U1/Channel0<6>_MC.D2_PT_0 ),
    .I1(\U1/Channel0<6>_MC.D2_PT_1 ),
    .I2(\U1/Channel0<6>_MC.D2_PT_2 ),
    .O(\U1/Channel0<6>_MC.D2 )
  );
  X_BUF \U1/Channel0<7>  (
    .I(\U1/Channel0<7>_MC.Q ),
    .O(\U1/Channel0 [7])
  );
  X_XOR2 \U1/Channel0<7>_MC_tsimcreated_xor__593  (
    .I0(\U1/Channel0<7>_MC.D ),
    .I1(\U1/Channel0<7>_MC.Q ),
    .O(\U1/Channel0<7>_MC_tsimcreated_xor_ )
  );
  X_FF \U1/Channel0<7>_MC.REG  (
    .I(\U1/Channel0<7>_MC_tsimcreated_xor_ ),
    .CE(Vcc),
    .CLK(\Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\U1/Channel0<7>_MC.Q )
  );
  X_XOR2 \U1/Channel0<7>_MC.D_594  (
    .I0(\U1/Channel0<7>_MC.D1 ),
    .I1(\U1/Channel0<7>_MC.D2 ),
    .O(\U1/Channel0<7>_MC.D )
  );
  X_ZERO \U1/Channel0<7>_MC.D1_595  (
    .O(\U1/Channel0<7>_MC.D1 )
  );
  X_AND2 \U1/Channel0<7>_MC.D2_PT_0_596  (
    .I0(\NlwInverterSignal_U1/Channel0<7>_MC.D2_PT_0/IN0 ),
    .I1(\U1/Channel0 [7]),
    .O(\U1/Channel0<7>_MC.D2_PT_0 )
  );
  X_AND4 \U1/Channel0<7>_MC.D2_PT_1_597  (
    .I0(N_PZ_1024),
    .I1(\U1/Channel0 [5]),
    .I2(\NlwInverterSignal_U1/Channel0<7>_MC.D2_PT_1/IN2 ),
    .I3(\U1/Channel0 [6]),
    .O(\U1/Channel0<7>_MC.D2_PT_1 )
  );
  X_AND4 \U1/Channel0<7>_MC.D2_PT_2_598  (
    .I0(N_PZ_1021),
    .I1(\NlwInverterSignal_U1/Channel0<7>_MC.D2_PT_2/IN1 ),
    .I2(\U1/U2/location_Maddsub__n0000__n0067 [0]),
    .I3(\NlwInverterSignal_U1/Channel0<7>_MC.D2_PT_2/IN3 ),
    .O(\U1/Channel0<7>_MC.D2_PT_2 )
  );
  X_OR3 \U1/Channel0<7>_MC.D2_599  (
    .I0(\U1/Channel0<7>_MC.D2_PT_0 ),
    .I1(\U1/Channel0<7>_MC.D2_PT_1 ),
    .I2(\U1/Channel0<7>_MC.D2_PT_2 ),
    .O(\U1/Channel0<7>_MC.D2 )
  );
  X_BUF DCOR0THRESHIGHr_600 (
    .I(\DCOR0THRESHIGHr_MC.Q ),
    .O(DCOR0THRESHIGHr)
  );
  X_BUF \DCOR0THRESHIGHr_MC.Q_601  (
    .I(\DCOR0THRESHIGHr_MC.D ),
    .O(\DCOR0THRESHIGHr_MC.Q )
  );
  X_XOR2 \DCOR0THRESHIGHr_MC.D_602  (
    .I0(\DCOR0THRESHIGHr_MC.D1 ),
    .I1(\DCOR0THRESHIGHr_MC.D2 ),
    .O(\DCOR0THRESHIGHr_MC.D )
  );
  X_AND16 \DCOR0THRESHIGHr_MC.D1_603  (
    .I0(\WR_II/UIM ),
    .I1(\NlwInverterSignal_DCOR0THRESHIGHr_MC.D1/IN1 ),
    .I2(U2_ADDR_reg[0]),
    .I3(\NlwInverterSignal_DCOR0THRESHIGHr_MC.D1/IN3 ),
    .I4(\NlwInverterSignal_DCOR0THRESHIGHr_MC.D1/IN4 ),
    .I5(\NlwInverterSignal_DCOR0THRESHIGHr_MC.D1/IN5 ),
    .I6(\NlwInverterSignal_DCOR0THRESHIGHr_MC.D1/IN6 ),
    .I7(U2_ADDR_reg[3]),
    .I8(\NlwInverterSignal_DCOR0THRESHIGHr_MC.D1/IN8 ),
    .I9(\NlwInverterSignal_DCOR0THRESHIGHr_MC.D1/IN9 ),
    .I10(Vcc),
    .I11(Vcc),
    .I12(Vcc),
    .I13(Vcc),
    .I14(Vcc),
    .I15(Vcc),
    .O(\DCOR0THRESHIGHr_MC.D1 )
  );
  X_ZERO \DCOR0THRESHIGHr_MC.D2_604  (
    .O(\DCOR0THRESHIGHr_MC.D2 )
  );
  X_BUF \U1/U4/Latch1r<0>  (
    .I(\U1/U4/Latch1r<0>_MC.Q ),
    .O(\U1/U4/Latch1r [0])
  );
  X_FF \U1/U4/Latch1r<0>_MC.REG  (
    .I(\U1/U4/Latch1r<0>_MC.D ),
    .CE(Vcc),
    .CLK(\U1/U4/Latch1r<0>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\U1/U4/Latch1r<0>_MC.Q )
  );
  X_INV \U1/U4/Latch1r<0>_MC.REG_tsimcreated_inv_Mclk_II/FCLK_605  (
    .I(\Mclk_II/FCLK ),
    .O(\U1/U4/Latch1r<0>_MC.REG_tsimcreated_inv_Mclk_II/FCLK )
  );
  X_XOR2 \U1/U4/Latch1r<0>_MC.D_606  (
    .I0(\U1/U4/Latch1r<0>_MC.D1 ),
    .I1(\U1/U4/Latch1r<0>_MC.D2 ),
    .O(\U1/U4/Latch1r<0>_MC.D )
  );
  X_ZERO \U1/U4/Latch1r<0>_MC.D1_607  (
    .O(\U1/U4/Latch1r<0>_MC.D1 )
  );
  X_AND3 \U1/U4/Latch1r<0>_MC.D2_PT_0_608  (
    .I0(\MSPReset_II/UIM ),
    .I1(\U1/U4/Latch1r [0]),
    .I2(\NlwInverterSignal_U1/U4/Latch1r<0>_MC.D2_PT_0/IN2 ),
    .O(\U1/U4/Latch1r<0>_MC.D2_PT_0 )
  );
  X_AND3 \U1/U4/Latch1r<0>_MC.D2_PT_1_609  (
    .I0(\MSPReset_II/UIM ),
    .I1(N_PZ_1019),
    .I2(\U1/Channel1 [0]),
    .O(\U1/U4/Latch1r<0>_MC.D2_PT_1 )
  );
  X_OR2 \U1/U4/Latch1r<0>_MC.D2_610  (
    .I0(\U1/U4/Latch1r<0>_MC.D2_PT_0 ),
    .I1(\U1/U4/Latch1r<0>_MC.D2_PT_1 ),
    .O(\U1/U4/Latch1r<0>_MC.D2 )
  );
  X_BUF \U1/Channel1<0>  (
    .I(\U1/Channel1<0>_MC.Q ),
    .O(\U1/Channel1 [0])
  );
  X_XOR2 \U1/Channel1<0>_MC_tsimcreated_xor__611  (
    .I0(\U1/Channel1<0>_MC.D ),
    .I1(\U1/Channel1<0>_MC.Q ),
    .O(\U1/Channel1<0>_MC_tsimcreated_xor_ )
  );
  X_FF \U1/Channel1<0>_MC.REG  (
    .I(\U1/Channel1<0>_MC_tsimcreated_xor_ ),
    .CE(Vcc),
    .CLK(\Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\U1/Channel1<0>_MC.Q )
  );
  X_XOR2 \U1/Channel1<0>_MC.D_612  (
    .I0(\U1/Channel1<0>_MC.D1 ),
    .I1(\U1/Channel1<0>_MC.D2 ),
    .O(\U1/Channel1<0>_MC.D )
  );
  X_ZERO \U1/Channel1<0>_MC.D1_613  (
    .O(\U1/Channel1<0>_MC.D1 )
  );
  X_AND2 \U1/Channel1<0>_MC.D2_PT_0_614  (
    .I0(\U1/Channel1 [0]),
    .I1(\NlwInverterSignal_U1/Channel1<0>_MC.D2_PT_0/IN1 ),
    .O(\U1/Channel1<0>_MC.D2_PT_0 )
  );
  X_AND5 \U1/Channel1<0>_MC.D2_PT_1_615  (
    .I0(\MSPReset_II/UIM ),
    .I1(\NlwInverterSignal_U1/Channel1<0>_MC.D2_PT_1/IN1 ),
    .I2(\U1/U6/CurrState_Sreg0_FFD3 ),
    .I3(\NlwInverterSignal_U1/Channel1<0>_MC.D2_PT_1/IN3 ),
    .I4(N_PZ_1154),
    .O(\U1/Channel1<0>_MC.D2_PT_1 )
  );
  X_OR2 \U1/Channel1<0>_MC.D2_616  (
    .I0(\U1/Channel1<0>_MC.D2_PT_0 ),
    .I1(\U1/Channel1<0>_MC.D2_PT_1 ),
    .O(\U1/Channel1<0>_MC.D2 )
  );
  X_BUF N_PZ_983_617 (
    .I(\N_PZ_983_MC.Q ),
    .O(N_PZ_983)
  );
  X_BUF \N_PZ_983_MC.Q_618  (
    .I(\N_PZ_983_MC.D ),
    .O(\N_PZ_983_MC.Q )
  );
  X_XOR2 \N_PZ_983_MC.D_619  (
    .I0(\N_PZ_983_MC.D1 ),
    .I1(\N_PZ_983_MC.D2 ),
    .O(\N_PZ_983_MC.D )
  );
  X_AND2 \N_PZ_983_MC.D1_620  (
    .I0(\MSPReset_II/UIM ),
    .I1(\NlwInverterSignal_N_PZ_983_MC.D1/IN1 ),
    .O(\N_PZ_983_MC.D1 )
  );
  X_ZERO \N_PZ_983_MC.D2_621  (
    .O(\N_PZ_983_MC.D2 )
  );
  X_BUF \U1/Zero1_622  (
    .I(\U1/Zero1_MC.Q ),
    .O(\U1/Zero1 )
  );
  X_FF \U1/Zero1_MC.REG  (
    .I(\U1/Zero1_MC.D ),
    .CE(Vcc),
    .CLK(\U1/Zero1_MC.REG_tsimcreated_inv_Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\U1/Zero1_MC.Q )
  );
  X_INV \U1/Zero1_MC.REG_tsimcreated_inv_Mclk_II/FCLK_623  (
    .I(\Mclk_II/FCLK ),
    .O(\U1/Zero1_MC.REG_tsimcreated_inv_Mclk_II/FCLK )
  );
  X_XOR2 \U1/Zero1_MC.D_624  (
    .I0(\U1/Zero1_MC.D1 ),
    .I1(\U1/Zero1_MC.D2 ),
    .O(\U1/Zero1_MC.D )
  );
  X_ZERO \U1/Zero1_MC.D1_625  (
    .O(\U1/Zero1_MC.D1 )
  );
  X_AND2 \U1/Zero1_MC.D2_PT_0_626  (
    .I0(\NlwInverterSignal_U1/Zero1_MC.D2_PT_0/IN0 ),
    .I1(\U1/Zero1 ),
    .O(\U1/Zero1_MC.D2_PT_0 )
  );
  X_AND2 \U1/Zero1_MC.D2_PT_1_627  (
    .I0(DCORIFGw),
    .I1(\U1/Zero1 ),
    .O(\U1/Zero1_MC.D2_PT_1 )
  );
  X_AND2 \U1/Zero1_MC.D2_PT_2_628  (
    .I0(DCORENCCTLw),
    .I1(\U1/Zero1 ),
    .O(\U1/Zero1_MC.D2_PT_2 )
  );
  X_AND8 \U1/Zero1_MC.D2_PT_3_629  (
    .I0(\MSPReset_II/UIM ),
    .I1(\NlwInverterSignal_U1/Zero1_MC.D2_PT_3/IN1 ),
    .I2(\NlwInverterSignal_U1/Zero1_MC.D2_PT_3/IN2 ),
    .I3(\NlwInverterSignal_U1/Zero1_MC.D2_PT_3/IN3 ),
    .I4(\U1/U4/RF1r ),
    .I5(\U1/U4/E1r ),
    .I6(\U1/U4/HE1stater ),
    .I7(\NlwInverterSignal_U1/Zero1_MC.D2_PT_3/IN7 ),
    .O(\U1/Zero1_MC.D2_PT_3 )
  );
  X_AND8 \U1/Zero1_MC.D2_PT_4_630  (
    .I0(\MSPReset_II/UIM ),
    .I1(\NlwInverterSignal_U1/Zero1_MC.D2_PT_4/IN1 ),
    .I2(\NlwInverterSignal_U1/Zero1_MC.D2_PT_4/IN2 ),
    .I3(\NlwInverterSignal_U1/Zero1_MC.D2_PT_4/IN3 ),
    .I4(\NlwInverterSignal_U1/Zero1_MC.D2_PT_4/IN4 ),
    .I5(\U1/U4/E1r ),
    .I6(\NlwInverterSignal_U1/Zero1_MC.D2_PT_4/IN6 ),
    .I7(\U1/U4/HE1statelastr ),
    .O(\U1/Zero1_MC.D2_PT_4 )
  );
  X_OR5 \U1/Zero1_MC.D2_631  (
    .I0(\U1/Zero1_MC.D2_PT_0 ),
    .I1(\U1/Zero1_MC.D2_PT_1 ),
    .I2(\U1/Zero1_MC.D2_PT_2 ),
    .I3(\U1/Zero1_MC.D2_PT_3 ),
    .I4(\U1/Zero1_MC.D2_PT_4 ),
    .O(\U1/Zero1_MC.D2 )
  );
  X_BUF NET2493_632 (
    .I(\NET2493_MC.Q ),
    .O(NET2493)
  );
  X_XOR2 NET2493_MC_tsimcreated_xor__633 (
    .I0(\NET2493_MC.D ),
    .I1(\NET2493_MC.Q ),
    .O(NET2493_MC_tsimcreated_xor_)
  );
  X_FF \NET2493_MC.REG  (
    .I(NET2493_MC_tsimcreated_xor_),
    .CE(Vcc),
    .CLK(\NET2493_MC.REG_tsimcreated_inv_Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\NET2493_MC.Q )
  );
  X_INV \NET2493_MC.REG_tsimcreated_inv_Mclk_II/FCLK_634  (
    .I(\Mclk_II/FCLK ),
    .O(\NET2493_MC.REG_tsimcreated_inv_Mclk_II/FCLK )
  );
  X_XOR2 \NET2493_MC.D_635  (
    .I0(\NET2493_MC.D1 ),
    .I1(\NET2493_MC.D2 ),
    .O(\NET2493_MC.D )
  );
  X_ZERO \NET2493_MC.D1_636  (
    .O(\NET2493_MC.D1 )
  );
  X_AND2 \NET2493_MC.D2_PT_0_637  (
    .I0(\NlwInverterSignal_NET2493_MC.D2_PT_0/IN0 ),
    .I1(NET2493),
    .O(\NET2493_MC.D2_PT_0 )
  );
  X_AND4 \NET2493_MC.D2_PT_1_638  (
    .I0(\AD<3>_II/UIM ),
    .I1(DCORIFGw),
    .I2(\NlwInverterSignal_NET2493_MC.D2_PT_1/IN2 ),
    .I3(NET2493),
    .O(\NET2493_MC.D2_PT_1 )
  );
  X_AND8 \NET2493_MC.D2_PT_2_639  (
    .I0(\MSPReset_II/UIM ),
    .I1(\NlwInverterSignal_NET2493_MC.D2_PT_2/IN1 ),
    .I2(\NlwInverterSignal_NET2493_MC.D2_PT_2/IN2 ),
    .I3(\NlwInverterSignal_NET2493_MC.D2_PT_2/IN3 ),
    .I4(\U1/U4/RF1r ),
    .I5(\U1/U4/E1r ),
    .I6(\U1/U4/HE1stater ),
    .I7(\NlwInverterSignal_NET2493_MC.D2_PT_2/IN7 ),
    .O(\NET2493_MC.D2_PT_2 )
  );
  X_AND8 \NET2493_MC.D2_PT_3_640  (
    .I0(\MSPReset_II/UIM ),
    .I1(\NlwInverterSignal_NET2493_MC.D2_PT_3/IN1 ),
    .I2(\NlwInverterSignal_NET2493_MC.D2_PT_3/IN2 ),
    .I3(\NlwInverterSignal_NET2493_MC.D2_PT_3/IN3 ),
    .I4(\NlwInverterSignal_NET2493_MC.D2_PT_3/IN4 ),
    .I5(\U1/U4/E1r ),
    .I6(\NlwInverterSignal_NET2493_MC.D2_PT_3/IN6 ),
    .I7(\U1/U4/HE1statelastr ),
    .O(\NET2493_MC.D2_PT_3 )
  );
  X_OR4 \NET2493_MC.D2_641  (
    .I0(\NET2493_MC.D2_PT_0 ),
    .I1(\NET2493_MC.D2_PT_1 ),
    .I2(\NET2493_MC.D2_PT_2 ),
    .I3(\NET2493_MC.D2_PT_3 ),
    .O(\NET2493_MC.D2 )
  );
  X_BUF \U1/U4/RF1r_642  (
    .I(\U1/U4/RF1r_MC.Q ),
    .O(\U1/U4/RF1r )
  );
  X_FF \U1/U4/RF1r_MC.REG  (
    .I(\U1/U4/RF1r_MC.D ),
    .CE(Vcc),
    .CLK(\U1/U4/RF1r_MC.REG_tsimcreated_inv_Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\U1/U4/RF1r_MC.Q )
  );
  X_INV \U1/U4/RF1r_MC.REG_tsimcreated_inv_Mclk_II/FCLK_643  (
    .I(\Mclk_II/FCLK ),
    .O(\U1/U4/RF1r_MC.REG_tsimcreated_inv_Mclk_II/FCLK )
  );
  X_XOR2 \U1/U4/RF1r_MC.D_644  (
    .I0(\U1/U4/RF1r_MC.D1 ),
    .I1(\U1/U4/RF1r_MC.D2 ),
    .O(\U1/U4/RF1r_MC.D )
  );
  X_ZERO \U1/U4/RF1r_MC.D1_645  (
    .O(\U1/U4/RF1r_MC.D1 )
  );
  X_AND3 \U1/U4/RF1r_MC.D2_PT_0_646  (
    .I0(\MSPReset_II/UIM ),
    .I1(\AD<4>_II/UIM ),
    .I2(DCORENCCTLw),
    .O(\U1/U4/RF1r_MC.D2_PT_0 )
  );
  X_AND3 \U1/U4/RF1r_MC.D2_PT_1_647  (
    .I0(\MSPReset_II/UIM ),
    .I1(\NlwInverterSignal_U1/U4/RF1r_MC.D2_PT_1/IN1 ),
    .I2(\U1/U4/RF1r ),
    .O(\U1/U4/RF1r_MC.D2_PT_1 )
  );
  X_OR2 \U1/U4/RF1r_MC.D2_648  (
    .I0(\U1/U4/RF1r_MC.D2_PT_0 ),
    .I1(\U1/U4/RF1r_MC.D2_PT_1 ),
    .O(\U1/U4/RF1r_MC.D2 )
  );
  X_BUF \U1/U4/E1r_649  (
    .I(\U1/U4/E1r_MC.Q ),
    .O(\U1/U4/E1r )
  );
  X_FF \U1/U4/E1r_MC.REG  (
    .I(\U1/U4/E1r_MC.D ),
    .CE(Vcc),
    .CLK(\U1/U4/E1r_MC.REG_tsimcreated_inv_Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\U1/U4/E1r_MC.Q )
  );
  X_INV \U1/U4/E1r_MC.REG_tsimcreated_inv_Mclk_II/FCLK_650  (
    .I(\Mclk_II/FCLK ),
    .O(\U1/U4/E1r_MC.REG_tsimcreated_inv_Mclk_II/FCLK )
  );
  X_XOR2 \U1/U4/E1r_MC.D_651  (
    .I0(\U1/U4/E1r_MC.D1 ),
    .I1(\U1/U4/E1r_MC.D2 ),
    .O(\U1/U4/E1r_MC.D )
  );
  X_ZERO \U1/U4/E1r_MC.D1_652  (
    .O(\U1/U4/E1r_MC.D1 )
  );
  X_AND3 \U1/U4/E1r_MC.D2_PT_0_653  (
    .I0(\MSPReset_II/UIM ),
    .I1(\AD<5>_II/UIM ),
    .I2(DCORENCCTLw),
    .O(\U1/U4/E1r_MC.D2_PT_0 )
  );
  X_AND3 \U1/U4/E1r_MC.D2_PT_1_654  (
    .I0(\MSPReset_II/UIM ),
    .I1(\NlwInverterSignal_U1/U4/E1r_MC.D2_PT_1/IN1 ),
    .I2(\U1/U4/E1r ),
    .O(\U1/U4/E1r_MC.D2_PT_1 )
  );
  X_OR2 \U1/U4/E1r_MC.D2_655  (
    .I0(\U1/U4/E1r_MC.D2_PT_0 ),
    .I1(\U1/U4/E1r_MC.D2_PT_1 ),
    .O(\U1/U4/E1r_MC.D2 )
  );
  X_BUF \U1/U4/HE1statelastr_656  (
    .I(\U1/U4/HE1statelastr_MC.Q ),
    .O(\U1/U4/HE1statelastr )
  );
  X_FF \U1/U4/HE1statelastr_MC.REG  (
    .I(\U1/U4/HE1statelastr_MC.D ),
    .CE(Vcc),
    .CLK(\U1/U4/HE1statelastr_MC.REG_tsimcreated_inv_Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\U1/U4/HE1statelastr_MC.Q )
  );
  X_INV \U1/U4/HE1statelastr_MC.REG_tsimcreated_inv_Mclk_II/FCLK_657  (
    .I(\Mclk_II/FCLK ),
    .O(\U1/U4/HE1statelastr_MC.REG_tsimcreated_inv_Mclk_II/FCLK )
  );
  X_XOR2 \U1/U4/HE1statelastr_MC.D_658  (
    .I0(\U1/U4/HE1statelastr_MC.D1 ),
    .I1(\U1/U4/HE1statelastr_MC.D2 ),
    .O(\U1/U4/HE1statelastr_MC.D )
  );
  X_AND2 \U1/U4/HE1statelastr_MC.D1_659  (
    .I0(\U1/U4/HE1stater ),
    .I1(\U1/U4/HE1stater ),
    .O(\U1/U4/HE1statelastr_MC.D1 )
  );
  X_ZERO \U1/U4/HE1statelastr_MC.D2_660  (
    .O(\U1/U4/HE1statelastr_MC.D2 )
  );
  X_BUF \U1/U6/CurrState_Sreg0_FFD3_661  (
    .I(\U1/U6/CurrState_Sreg0_FFD3_MC.Q ),
    .O(\U1/U6/CurrState_Sreg0_FFD3 )
  );
  X_FF \U1/U6/CurrState_Sreg0_FFD3_MC.REG  (
    .I(\U1/U6/CurrState_Sreg0_FFD3_MC.D ),
    .CE(Vcc),
    .CLK(\Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\U1/U6/CurrState_Sreg0_FFD3_MC.Q )
  );
  X_XOR2 \U1/U6/CurrState_Sreg0_FFD3_MC.D_662  (
    .I0(\U1/U6/CurrState_Sreg0_FFD3_MC.D1 ),
    .I1(\U1/U6/CurrState_Sreg0_FFD3_MC.D2 ),
    .O(\U1/U6/CurrState_Sreg0_FFD3_MC.D )
  );
  X_ZERO \U1/U6/CurrState_Sreg0_FFD3_MC.D1_663  (
    .O(\U1/U6/CurrState_Sreg0_FFD3_MC.D1 )
  );
  X_AND5 \U1/U6/CurrState_Sreg0_FFD3_MC.D2_PT_0_664  (
    .I0(\MSPReset_II/UIM ),
    .I1(\U1/U6/CurrState_Sreg0_FFD3 ),
    .I2(\U1/U6/CurrState_Sreg0_FFD2 ),
    .I3(\NlwInverterSignal_U1/U6/CurrState_Sreg0_FFD3_MC.D2_PT_0/IN3 ),
    .I4(\NlwInverterSignal_U1/U6/CurrState_Sreg0_FFD3_MC.D2_PT_0/IN4 ),
    .O(\U1/U6/CurrState_Sreg0_FFD3_MC.D2_PT_0 )
  );
  X_AND5 \U1/U6/CurrState_Sreg0_FFD3_MC.D2_PT_1_665  (
    .I0(\MSPReset_II/UIM ),
    .I1(\U1/U6/CurrState_Sreg0_FFD3 ),
    .I2(\NlwInverterSignal_U1/U6/CurrState_Sreg0_FFD3_MC.D2_PT_1/IN2 ),
    .I3(\NlwInverterSignal_U1/U6/CurrState_Sreg0_FFD3_MC.D2_PT_1/IN3 ),
    .I4(\NlwInverterSignal_U1/U6/CurrState_Sreg0_FFD3_MC.D2_PT_1/IN4 ),
    .O(\U1/U6/CurrState_Sreg0_FFD3_MC.D2_PT_1 )
  );
  X_AND6 \U1/U6/CurrState_Sreg0_FFD3_MC.D2_PT_2_666  (
    .I0(\MSPReset_II/UIM ),
    .I1(\U1/U6/CurrState_Sreg0_FFD2 ),
    .I2(\PhaseA_Encoder1_II/UIM ),
    .I3(\NlwInverterSignal_U1/U6/CurrState_Sreg0_FFD3_MC.D2_PT_2/IN3 ),
    .I4(\U1/U6/CurrState_Sreg0_FFD1 ),
    .I5(\NlwInverterSignal_U1/U6/CurrState_Sreg0_FFD3_MC.D2_PT_2/IN5 ),
    .O(\U1/U6/CurrState_Sreg0_FFD3_MC.D2_PT_2 )
  );
  X_AND6 \U1/U6/CurrState_Sreg0_FFD3_MC.D2_PT_3_667  (
    .I0(\MSPReset_II/UIM ),
    .I1(\U1/U6/CurrState_Sreg0_FFD2 ),
    .I2(\PhaseA_Encoder1_II/UIM ),
    .I3(\NlwInverterSignal_U1/U6/CurrState_Sreg0_FFD3_MC.D2_PT_3/IN3 ),
    .I4(\NlwInverterSignal_U1/U6/CurrState_Sreg0_FFD3_MC.D2_PT_3/IN4 ),
    .I5(\PhaseB_Encoder1_II/UIM ),
    .O(\U1/U6/CurrState_Sreg0_FFD3_MC.D2_PT_3 )
  );
  X_OR4 \U1/U6/CurrState_Sreg0_FFD3_MC.D2_668  (
    .I0(\U1/U6/CurrState_Sreg0_FFD3_MC.D2_PT_0 ),
    .I1(\U1/U6/CurrState_Sreg0_FFD3_MC.D2_PT_1 ),
    .I2(\U1/U6/CurrState_Sreg0_FFD3_MC.D2_PT_2 ),
    .I3(\U1/U6/CurrState_Sreg0_FFD3_MC.D2_PT_3 ),
    .O(\U1/U6/CurrState_Sreg0_FFD3_MC.D2 )
  );
  X_BUF \U1/U6/CurrState_Sreg0_FFD1_669  (
    .I(\U1/U6/CurrState_Sreg0_FFD1_MC.Q ),
    .O(\U1/U6/CurrState_Sreg0_FFD1 )
  );
  X_FF \U1/U6/CurrState_Sreg0_FFD1_MC.REG  (
    .I(\U1/U6/CurrState_Sreg0_FFD1_MC.D ),
    .CE(Vcc),
    .CLK(\Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\U1/U6/CurrState_Sreg0_FFD1_MC.Q )
  );
  X_XOR2 \U1/U6/CurrState_Sreg0_FFD1_MC.D_670  (
    .I0(\U1/U6/CurrState_Sreg0_FFD1_MC.D1 ),
    .I1(\U1/U6/CurrState_Sreg0_FFD1_MC.D2 ),
    .O(\U1/U6/CurrState_Sreg0_FFD1_MC.D )
  );
  X_ZERO \U1/U6/CurrState_Sreg0_FFD1_MC.D1_671  (
    .O(\U1/U6/CurrState_Sreg0_FFD1_MC.D1 )
  );
  X_AND4 \U1/U6/CurrState_Sreg0_FFD1_MC.D2_PT_0_672  (
    .I0(\MSPReset_II/UIM ),
    .I1(\U1/U6/CurrState_Sreg0_FFD2 ),
    .I2(\NlwInverterSignal_U1/U6/CurrState_Sreg0_FFD1_MC.D2_PT_0/IN2 ),
    .I3(\U1/U6/CurrState_Sreg0_FFD1 ),
    .O(\U1/U6/CurrState_Sreg0_FFD1_MC.D2_PT_0 )
  );
  X_AND5 \U1/U6/CurrState_Sreg0_FFD1_MC.D2_PT_1_673  (
    .I0(\MSPReset_II/UIM ),
    .I1(\NlwInverterSignal_U1/U6/CurrState_Sreg0_FFD1_MC.D2_PT_1/IN1 ),
    .I2(\PhaseA_Encoder1_II/UIM ),
    .I3(\NlwInverterSignal_U1/U6/CurrState_Sreg0_FFD1_MC.D2_PT_1/IN3 ),
    .I4(\U1/U6/CurrState_Sreg0_FFD1 ),
    .O(\U1/U6/CurrState_Sreg0_FFD1_MC.D2_PT_1 )
  );
  X_AND6 \U1/U6/CurrState_Sreg0_FFD1_MC.D2_PT_2_674  (
    .I0(\MSPReset_II/UIM ),
    .I1(\NlwInverterSignal_U1/U6/CurrState_Sreg0_FFD1_MC.D2_PT_2/IN1 ),
    .I2(\NlwInverterSignal_U1/U6/CurrState_Sreg0_FFD1_MC.D2_PT_2/IN2 ),
    .I3(\NlwInverterSignal_U1/U6/CurrState_Sreg0_FFD1_MC.D2_PT_2/IN3 ),
    .I4(\NlwInverterSignal_U1/U6/CurrState_Sreg0_FFD1_MC.D2_PT_2/IN4 ),
    .I5(\PhaseB_Encoder1_II/UIM ),
    .O(\U1/U6/CurrState_Sreg0_FFD1_MC.D2_PT_2 )
  );
  X_OR3 \U1/U6/CurrState_Sreg0_FFD1_MC.D2_675  (
    .I0(\U1/U6/CurrState_Sreg0_FFD1_MC.D2_PT_0 ),
    .I1(\U1/U6/CurrState_Sreg0_FFD1_MC.D2_PT_1 ),
    .I2(\U1/U6/CurrState_Sreg0_FFD1_MC.D2_PT_2 ),
    .O(\U1/U6/CurrState_Sreg0_FFD1_MC.D2 )
  );
  X_BUF \U1/U6/CurrState_Sreg0_FFD4_676  (
    .I(\U1/U6/CurrState_Sreg0_FFD4_MC.Q ),
    .O(\U1/U6/CurrState_Sreg0_FFD4 )
  );
  X_FF \U1/U6/CurrState_Sreg0_FFD4_MC.REG  (
    .I(\U1/U6/CurrState_Sreg0_FFD4_MC.D ),
    .CE(Vcc),
    .CLK(\Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\U1/U6/CurrState_Sreg0_FFD4_MC.Q )
  );
  X_XOR2 \U1/U6/CurrState_Sreg0_FFD4_MC.D_677  (
    .I0(\U1/U6/CurrState_Sreg0_FFD4_MC.D1 ),
    .I1(\U1/U6/CurrState_Sreg0_FFD4_MC.D2 ),
    .O(\U1/U6/CurrState_Sreg0_FFD4_MC.D )
  );
  X_AND7 \U1/U6/CurrState_Sreg0_FFD4_MC.D1_678  (
    .I0(\MSPReset_II/UIM ),
    .I1(\U1/U6/CurrState_Sreg0_FFD3 ),
    .I2(\NlwInverterSignal_U1/U6/CurrState_Sreg0_FFD4_MC.D1/IN2 ),
    .I3(\NlwInverterSignal_U1/U6/CurrState_Sreg0_FFD4_MC.D1/IN3 ),
    .I4(\NlwInverterSignal_U1/U6/CurrState_Sreg0_FFD4_MC.D1/IN4 ),
    .I5(\NlwInverterSignal_U1/U6/CurrState_Sreg0_FFD4_MC.D1/IN5 ),
    .I6(\NlwInverterSignal_U1/U6/CurrState_Sreg0_FFD4_MC.D1/IN6 ),
    .O(\U1/U6/CurrState_Sreg0_FFD4_MC.D1 )
  );
  X_ZERO \U1/U6/CurrState_Sreg0_FFD4_MC.D2_679  (
    .O(\U1/U6/CurrState_Sreg0_FFD4_MC.D2 )
  );
  X_BUF \U1/U6/CurrState_Sreg0_FFD2_680  (
    .I(\U1/U6/CurrState_Sreg0_FFD2_MC.Q ),
    .O(\U1/U6/CurrState_Sreg0_FFD2 )
  );
  X_FF \U1/U6/CurrState_Sreg0_FFD2_MC.REG  (
    .I(\U1/U6/CurrState_Sreg0_FFD2_MC.D ),
    .CE(Vcc),
    .CLK(\Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\U1/U6/CurrState_Sreg0_FFD2_MC.Q )
  );
  X_XOR2 \U1/U6/CurrState_Sreg0_FFD2_MC.D_681  (
    .I0(\U1/U6/CurrState_Sreg0_FFD2_MC.D1 ),
    .I1(\U1/U6/CurrState_Sreg0_FFD2_MC.D2 ),
    .O(\U1/U6/CurrState_Sreg0_FFD2_MC.D )
  );
  X_ZERO \U1/U6/CurrState_Sreg0_FFD2_MC.D1_682  (
    .O(\U1/U6/CurrState_Sreg0_FFD2_MC.D1 )
  );
  X_AND6 \U1/U6/CurrState_Sreg0_FFD2_MC.D2_PT_0_683  (
    .I0(\MSPReset_II/UIM ),
    .I1(\U1/U6/CurrState_Sreg0_FFD3 ),
    .I2(\U1/U6/CurrState_Sreg0_FFD2 ),
    .I3(\NlwInverterSignal_U1/U6/CurrState_Sreg0_FFD2_MC.D2_PT_0/IN3 ),
    .I4(\U1/U6/CurrState_Sreg0_FFD1 ),
    .I5(\PhaseB_Encoder1_II/UIM ),
    .O(\U1/U6/CurrState_Sreg0_FFD2_MC.D2_PT_0 )
  );
  X_AND6 \U1/U6/CurrState_Sreg0_FFD2_MC.D2_PT_1_684  (
    .I0(\MSPReset_II/UIM ),
    .I1(\U1/U6/CurrState_Sreg0_FFD3 ),
    .I2(\U1/U6/CurrState_Sreg0_FFD2 ),
    .I3(\NlwInverterSignal_U1/U6/CurrState_Sreg0_FFD2_MC.D2_PT_1/IN3 ),
    .I4(\NlwInverterSignal_U1/U6/CurrState_Sreg0_FFD2_MC.D2_PT_1/IN4 ),
    .I5(\NlwInverterSignal_U1/U6/CurrState_Sreg0_FFD2_MC.D2_PT_1/IN5 ),
    .O(\U1/U6/CurrState_Sreg0_FFD2_MC.D2_PT_1 )
  );
  X_AND6 \U1/U6/CurrState_Sreg0_FFD2_MC.D2_PT_2_685  (
    .I0(\MSPReset_II/UIM ),
    .I1(\U1/U6/CurrState_Sreg0_FFD3 ),
    .I2(\PhaseA_Encoder1_II/UIM ),
    .I3(\NlwInverterSignal_U1/U6/CurrState_Sreg0_FFD2_MC.D2_PT_2/IN3 ),
    .I4(\NlwInverterSignal_U1/U6/CurrState_Sreg0_FFD2_MC.D2_PT_2/IN4 ),
    .I5(\PhaseB_Encoder1_II/UIM ),
    .O(\U1/U6/CurrState_Sreg0_FFD2_MC.D2_PT_2 )
  );
  X_AND6 \U1/U6/CurrState_Sreg0_FFD2_MC.D2_PT_3_686  (
    .I0(\MSPReset_II/UIM ),
    .I1(\NlwInverterSignal_U1/U6/CurrState_Sreg0_FFD2_MC.D2_PT_3/IN1 ),
    .I2(\U1/U6/CurrState_Sreg0_FFD2 ),
    .I3(\NlwInverterSignal_U1/U6/CurrState_Sreg0_FFD2_MC.D2_PT_3/IN3 ),
    .I4(\U1/U6/CurrState_Sreg0_FFD1 ),
    .I5(\NlwInverterSignal_U1/U6/CurrState_Sreg0_FFD2_MC.D2_PT_3/IN5 ),
    .O(\U1/U6/CurrState_Sreg0_FFD2_MC.D2_PT_3 )
  );
  X_AND6 \U1/U6/CurrState_Sreg0_FFD2_MC.D2_PT_4_687  (
    .I0(\MSPReset_II/UIM ),
    .I1(\NlwInverterSignal_U1/U6/CurrState_Sreg0_FFD2_MC.D2_PT_4/IN1 ),
    .I2(\U1/U6/CurrState_Sreg0_FFD2 ),
    .I3(\NlwInverterSignal_U1/U6/CurrState_Sreg0_FFD2_MC.D2_PT_4/IN3 ),
    .I4(\NlwInverterSignal_U1/U6/CurrState_Sreg0_FFD2_MC.D2_PT_4/IN4 ),
    .I5(\PhaseB_Encoder1_II/UIM ),
    .O(\U1/U6/CurrState_Sreg0_FFD2_MC.D2_PT_4 )
  );
  X_AND6 \U1/U6/CurrState_Sreg0_FFD2_MC.D2_PT_5_688  (
    .I0(\MSPReset_II/UIM ),
    .I1(\NlwInverterSignal_U1/U6/CurrState_Sreg0_FFD2_MC.D2_PT_5/IN1 ),
    .I2(\PhaseA_Encoder1_II/UIM ),
    .I3(\NlwInverterSignal_U1/U6/CurrState_Sreg0_FFD2_MC.D2_PT_5/IN3 ),
    .I4(\U1/U6/CurrState_Sreg0_FFD1 ),
    .I5(\PhaseB_Encoder1_II/UIM ),
    .O(\U1/U6/CurrState_Sreg0_FFD2_MC.D2_PT_5 )
  );
  X_AND6 \U1/U6/CurrState_Sreg0_FFD2_MC.D2_PT_6_689  (
    .I0(\MSPReset_II/UIM ),
    .I1(\NlwInverterSignal_U1/U6/CurrState_Sreg0_FFD2_MC.D2_PT_6/IN1 ),
    .I2(\PhaseA_Encoder1_II/UIM ),
    .I3(\NlwInverterSignal_U1/U6/CurrState_Sreg0_FFD2_MC.D2_PT_6/IN3 ),
    .I4(\NlwInverterSignal_U1/U6/CurrState_Sreg0_FFD2_MC.D2_PT_6/IN4 ),
    .I5(\NlwInverterSignal_U1/U6/CurrState_Sreg0_FFD2_MC.D2_PT_6/IN5 ),
    .O(\U1/U6/CurrState_Sreg0_FFD2_MC.D2_PT_6 )
  );
  X_AND6 \U1/U6/CurrState_Sreg0_FFD2_MC.D2_PT_7_690  (
    .I0(\MSPReset_II/UIM ),
    .I1(\U1/U6/CurrState_Sreg0_FFD2 ),
    .I2(\PhaseA_Encoder1_II/UIM ),
    .I3(\NlwInverterSignal_U1/U6/CurrState_Sreg0_FFD2_MC.D2_PT_7/IN3 ),
    .I4(\U1/U6/CurrState_Sreg0_FFD1 ),
    .I5(\NlwInverterSignal_U1/U6/CurrState_Sreg0_FFD2_MC.D2_PT_7/IN5 ),
    .O(\U1/U6/CurrState_Sreg0_FFD2_MC.D2_PT_7 )
  );
  X_OR8 \U1/U6/CurrState_Sreg0_FFD2_MC.D2_691  (
    .I0(\U1/U6/CurrState_Sreg0_FFD2_MC.D2_PT_0 ),
    .I1(\U1/U6/CurrState_Sreg0_FFD2_MC.D2_PT_1 ),
    .I2(\U1/U6/CurrState_Sreg0_FFD2_MC.D2_PT_2 ),
    .I3(\U1/U6/CurrState_Sreg0_FFD2_MC.D2_PT_3 ),
    .I4(\U1/U6/CurrState_Sreg0_FFD2_MC.D2_PT_4 ),
    .I5(\U1/U6/CurrState_Sreg0_FFD2_MC.D2_PT_5 ),
    .I6(\U1/U6/CurrState_Sreg0_FFD2_MC.D2_PT_6 ),
    .I7(\U1/U6/CurrState_Sreg0_FFD2_MC.D2_PT_7 ),
    .O(\U1/U6/CurrState_Sreg0_FFD2_MC.D2 )
  );
  X_BUF N_PZ_1154_692 (
    .I(\N_PZ_1154_MC.Q ),
    .O(N_PZ_1154)
  );
  X_BUF \N_PZ_1154_MC.Q_693  (
    .I(\N_PZ_1154_MC.D ),
    .O(\N_PZ_1154_MC.Q )
  );
  X_XOR2 \N_PZ_1154_MC.D_694  (
    .I0(\N_PZ_1154_MC.D1 ),
    .I1(\N_PZ_1154_MC.D2 ),
    .O(\N_PZ_1154_MC.D )
  );
  X_ZERO \N_PZ_1154_MC.D1_695  (
    .O(\N_PZ_1154_MC.D1 )
  );
  X_AND2 \N_PZ_1154_MC.D2_PT_0_696  (
    .I0(\U1/U6/CurrState_Sreg0_FFD4 ),
    .I1(\NlwInverterSignal_N_PZ_1154_MC.D2_PT_0/IN1 ),
    .O(\N_PZ_1154_MC.D2_PT_0 )
  );
  X_AND2 \N_PZ_1154_MC.D2_PT_1_697  (
    .I0(\NlwInverterSignal_N_PZ_1154_MC.D2_PT_1/IN0 ),
    .I1(\U1/U6/CurrState_Sreg0_FFD1 ),
    .O(\N_PZ_1154_MC.D2_PT_1 )
  );
  X_OR2 \N_PZ_1154_MC.D2_698  (
    .I0(\N_PZ_1154_MC.D2_PT_0 ),
    .I1(\N_PZ_1154_MC.D2_PT_1 ),
    .O(\N_PZ_1154_MC.D2 )
  );
  X_BUF N_PZ_1019_699 (
    .I(\N_PZ_1019_MC.Q ),
    .O(N_PZ_1019)
  );
  X_BUF \N_PZ_1019_MC.Q_700  (
    .I(\N_PZ_1019_MC.D ),
    .O(\N_PZ_1019_MC.Q )
  );
  X_XOR2 \N_PZ_1019_MC.D_701  (
    .I0(\N_PZ_1019_MC.D1 ),
    .I1(\N_PZ_1019_MC.D2 ),
    .O(\N_PZ_1019_MC.D )
  );
  X_ZERO \N_PZ_1019_MC.D1_702  (
    .O(\N_PZ_1019_MC.D1 )
  );
  X_AND6 \N_PZ_1019_MC.D2_PT_0_703  (
    .I0(\NlwInverterSignal_N_PZ_1019_MC.D2_PT_0/IN0 ),
    .I1(\NlwInverterSignal_N_PZ_1019_MC.D2_PT_0/IN1 ),
    .I2(\NlwInverterSignal_N_PZ_1019_MC.D2_PT_0/IN2 ),
    .I3(\U1/U4/LatchEdge1r ),
    .I4(\NlwInverterSignal_N_PZ_1019_MC.D2_PT_0/IN4 ),
    .I5(\outDATA<7>\$WA3.UIM ),
    .O(\N_PZ_1019_MC.D2_PT_0 )
  );
  X_AND6 \N_PZ_1019_MC.D2_PT_1_704  (
    .I0(\NlwInverterSignal_N_PZ_1019_MC.D2_PT_1/IN0 ),
    .I1(\NlwInverterSignal_N_PZ_1019_MC.D2_PT_1/IN1 ),
    .I2(\NlwInverterSignal_N_PZ_1019_MC.D2_PT_1/IN2 ),
    .I3(\NlwInverterSignal_N_PZ_1019_MC.D2_PT_1/IN3 ),
    .I4(\U1/U4/InEdge1r ),
    .I5(\NlwInverterSignal_N_PZ_1019_MC.D2_PT_1/IN5 ),
    .O(\N_PZ_1019_MC.D2_PT_1 )
  );
  X_OR2 \N_PZ_1019_MC.D2_705  (
    .I0(\N_PZ_1019_MC.D2_PT_0 ),
    .I1(\N_PZ_1019_MC.D2_PT_1 ),
    .O(\N_PZ_1019_MC.D2 )
  );
  X_BUF NET2512_706 (
    .I(\NET2512_MC.Q ),
    .O(NET2512)
  );
  X_XOR2 NET2512_MC_tsimcreated_xor__707 (
    .I0(\NET2512_MC.D ),
    .I1(\NET2512_MC.Q ),
    .O(NET2512_MC_tsimcreated_xor_)
  );
  X_FF \NET2512_MC.REG  (
    .I(NET2512_MC_tsimcreated_xor_),
    .CE(Vcc),
    .CLK(\NET2512_MC.REG_tsimcreated_inv_Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\NET2512_MC.Q )
  );
  X_INV \NET2512_MC.REG_tsimcreated_inv_Mclk_II/FCLK_708  (
    .I(\Mclk_II/FCLK ),
    .O(\NET2512_MC.REG_tsimcreated_inv_Mclk_II/FCLK )
  );
  X_XOR2 \NET2512_MC.D_709  (
    .I0(\NET2512_MC.D1 ),
    .I1(\NET2512_MC.D2 ),
    .O(\NET2512_MC.D )
  );
  X_ZERO \NET2512_MC.D1_710  (
    .O(\NET2512_MC.D1 )
  );
  X_AND2 \NET2512_MC.D2_PT_0_711  (
    .I0(\MSPReset_II/UIM ),
    .I1(N_PZ_1019),
    .O(\NET2512_MC.D2_PT_0 )
  );
  X_AND5 \NET2512_MC.D2_PT_1_712  (
    .I0(\MSPReset_II/UIM ),
    .I1(\AD<6>_II/UIM ),
    .I2(DCORIFGw),
    .I3(\NlwInverterSignal_NET2512_MC.D2_PT_1/IN3 ),
    .I4(NET2512),
    .O(\NET2512_MC.D2_PT_1 )
  );
  X_OR2 \NET2512_MC.D2_713  (
    .I0(\NET2512_MC.D2_PT_0 ),
    .I1(\NET2512_MC.D2_PT_1 ),
    .O(\NET2512_MC.D2 )
  );
  X_BUF \U1/U4/LatchEdge1r_714  (
    .I(\U1/U4/LatchEdge1r_MC.Q ),
    .O(\U1/U4/LatchEdge1r )
  );
  X_FF \U1/U4/LatchEdge1r_MC.REG  (
    .I(\U1/U4/LatchEdge1r_MC.D ),
    .CE(Vcc),
    .CLK(\U1/U4/LatchEdge1r_MC.REG_tsimcreated_inv_Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\U1/U4/LatchEdge1r_MC.Q )
  );
  X_INV \U1/U4/LatchEdge1r_MC.REG_tsimcreated_inv_Mclk_II/FCLK_715  (
    .I(\Mclk_II/FCLK ),
    .O(\U1/U4/LatchEdge1r_MC.REG_tsimcreated_inv_Mclk_II/FCLK )
  );
  X_XOR2 \U1/U4/LatchEdge1r_MC.D_716  (
    .I0(\U1/U4/LatchEdge1r_MC.D1 ),
    .I1(\U1/U4/LatchEdge1r_MC.D2 ),
    .O(\U1/U4/LatchEdge1r_MC.D )
  );
  X_ZERO \U1/U4/LatchEdge1r_MC.D1_717  (
    .O(\U1/U4/LatchEdge1r_MC.D1 )
  );
  X_AND3 \U1/U4/LatchEdge1r_MC.D2_PT_0_718  (
    .I0(\MSPReset_II/UIM ),
    .I1(\AD<6>_II/UIM ),
    .I2(DCORENCCTLw),
    .O(\U1/U4/LatchEdge1r_MC.D2_PT_0 )
  );
  X_AND3 \U1/U4/LatchEdge1r_MC.D2_PT_1_719  (
    .I0(\MSPReset_II/UIM ),
    .I1(\NlwInverterSignal_U1/U4/LatchEdge1r_MC.D2_PT_1/IN1 ),
    .I2(\U1/U4/LatchEdge1r ),
    .O(\U1/U4/LatchEdge1r_MC.D2_PT_1 )
  );
  X_OR2 \U1/U4/LatchEdge1r_MC.D2_720  (
    .I0(\U1/U4/LatchEdge1r_MC.D2_PT_0 ),
    .I1(\U1/U4/LatchEdge1r_MC.D2_PT_1 ),
    .O(\U1/U4/LatchEdge1r_MC.D2 )
  );
  X_BUF \outDATA<7>\$WA3.UIM_721  (
    .I(\outDATA<7>\$WA3.UIM_MC.Q ),
    .O(\outDATA<7>\$WA3.UIM )
  );
  X_BUF \outDATA<7>\$WA3.UIM_MC.Q_722  (
    .I(\outDATA<7>\$WA3.UIM_MC.D ),
    .O(\outDATA<7>\$WA3.UIM_MC.Q )
  );
  X_XOR2 \outDATA<7>\$WA3.UIM_MC.D_723  (
    .I0(\outDATA<7>\$WA3.UIM_MC.D1 ),
    .I1(\outDATA<7>\$WA3.UIM_MC.D2 ),
    .O(\outDATA<7>\$WA3.UIM_MC.D )
  );
  X_AND2 \outDATA<7>\$WA3.UIM_MC.D1_724  (
    .I0(\GP_Motor1_0_II/UIM ),
    .I1(\GP_Motor1_0_II/UIM ),
    .O(\outDATA<7>\$WA3.UIM_MC.D1 )
  );
  X_ZERO \outDATA<7>\$WA3.UIM_MC.D2_725  (
    .O(\outDATA<7>\$WA3.UIM_MC.D2 )
  );
  X_BUF DCOR1THRESLOWr_726 (
    .I(\DCOR1THRESLOWr_MC.Q ),
    .O(DCOR1THRESLOWr)
  );
  X_BUF \DCOR1THRESLOWr_MC.Q_727  (
    .I(\DCOR1THRESLOWr_MC.D ),
    .O(\DCOR1THRESLOWr_MC.Q )
  );
  X_XOR2 \DCOR1THRESLOWr_MC.D_728  (
    .I0(\DCOR1THRESLOWr_MC.D1 ),
    .I1(\DCOR1THRESLOWr_MC.D2 ),
    .O(\DCOR1THRESLOWr_MC.D )
  );
  X_AND16 \DCOR1THRESLOWr_MC.D1_729  (
    .I0(\WR_II/UIM ),
    .I1(\NlwInverterSignal_DCOR1THRESLOWr_MC.D1/IN1 ),
    .I2(\NlwInverterSignal_DCOR1THRESLOWr_MC.D1/IN2 ),
    .I3(\NlwInverterSignal_DCOR1THRESLOWr_MC.D1/IN3 ),
    .I4(\NlwInverterSignal_DCOR1THRESLOWr_MC.D1/IN4 ),
    .I5(\NlwInverterSignal_DCOR1THRESLOWr_MC.D1/IN5 ),
    .I6(\NlwInverterSignal_DCOR1THRESLOWr_MC.D1/IN6 ),
    .I7(U2_ADDR_reg[3]),
    .I8(U2_ADDR_reg[1]),
    .I9(\NlwInverterSignal_DCOR1THRESLOWr_MC.D1/IN9 ),
    .I10(Vcc),
    .I11(Vcc),
    .I12(Vcc),
    .I13(Vcc),
    .I14(Vcc),
    .I15(Vcc),
    .O(\DCOR1THRESLOWr_MC.D1 )
  );
  X_ZERO \DCOR1THRESLOWr_MC.D2_730  (
    .O(\DCOR1THRESLOWr_MC.D2 )
  );
  X_BUF \U1/U4/Latch1r<8>  (
    .I(\U1/U4/Latch1r<8>_MC.Q ),
    .O(\U1/U4/Latch1r [8])
  );
  X_FF \U1/U4/Latch1r<8>_MC.REG  (
    .I(\U1/U4/Latch1r<8>_MC.D ),
    .CE(Vcc),
    .CLK(\U1/U4/Latch1r<8>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\U1/U4/Latch1r<8>_MC.Q )
  );
  X_INV \U1/U4/Latch1r<8>_MC.REG_tsimcreated_inv_Mclk_II/FCLK_731  (
    .I(\Mclk_II/FCLK ),
    .O(\U1/U4/Latch1r<8>_MC.REG_tsimcreated_inv_Mclk_II/FCLK )
  );
  X_XOR2 \U1/U4/Latch1r<8>_MC.D_732  (
    .I0(\U1/U4/Latch1r<8>_MC.D1 ),
    .I1(\U1/U4/Latch1r<8>_MC.D2 ),
    .O(\U1/U4/Latch1r<8>_MC.D )
  );
  X_ZERO \U1/U4/Latch1r<8>_MC.D1_733  (
    .O(\U1/U4/Latch1r<8>_MC.D1 )
  );
  X_AND3 \U1/U4/Latch1r<8>_MC.D2_PT_0_734  (
    .I0(\MSPReset_II/UIM ),
    .I1(\U1/U4/Latch1r [8]),
    .I2(\NlwInverterSignal_U1/U4/Latch1r<8>_MC.D2_PT_0/IN2 ),
    .O(\U1/U4/Latch1r<8>_MC.D2_PT_0 )
  );
  X_AND3 \U1/U4/Latch1r<8>_MC.D2_PT_1_735  (
    .I0(\MSPReset_II/UIM ),
    .I1(N_PZ_1019),
    .I2(\U1/Channel1 [8]),
    .O(\U1/U4/Latch1r<8>_MC.D2_PT_1 )
  );
  X_OR2 \U1/U4/Latch1r<8>_MC.D2_736  (
    .I0(\U1/U4/Latch1r<8>_MC.D2_PT_0 ),
    .I1(\U1/U4/Latch1r<8>_MC.D2_PT_1 ),
    .O(\U1/U4/Latch1r<8>_MC.D2 )
  );
  X_BUF \U1/Channel1<8>  (
    .I(\U1/Channel1<8>_MC.Q ),
    .O(\U1/Channel1 [8])
  );
  X_XOR2 \U1/Channel1<8>_MC_tsimcreated_xor__737  (
    .I0(\U1/Channel1<8>_MC.D ),
    .I1(\U1/Channel1<8>_MC.Q ),
    .O(\U1/Channel1<8>_MC_tsimcreated_xor_ )
  );
  X_FF \U1/Channel1<8>_MC.REG  (
    .I(\U1/Channel1<8>_MC_tsimcreated_xor_ ),
    .CE(Vcc),
    .CLK(\Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\U1/Channel1<8>_MC.Q )
  );
  X_XOR2 \U1/Channel1<8>_MC.D_738  (
    .I0(\U1/Channel1<8>_MC.D1 ),
    .I1(\U1/Channel1<8>_MC.D2 ),
    .O(\U1/Channel1<8>_MC.D )
  );
  X_ZERO \U1/Channel1<8>_MC.D1_739  (
    .O(\U1/Channel1<8>_MC.D1 )
  );
  X_AND2 \U1/Channel1<8>_MC.D2_PT_0_740  (
    .I0(\NlwInverterSignal_U1/Channel1<8>_MC.D2_PT_0/IN0 ),
    .I1(\U1/Channel1 [8]),
    .O(\U1/Channel1<8>_MC.D2_PT_0 )
  );
  X_AND6 \U1/Channel1<8>_MC.D2_PT_1_741  (
    .I0(\U1/U6/CurrState_Sreg0_FFD3 ),
    .I1(\NlwInverterSignal_U1/Channel1<8>_MC.D2_PT_1/IN1 ),
    .I2(\U1/Channel1 [8]),
    .I3(\NlwInverterSignal_U1/Channel1<8>_MC.D2_PT_1/IN3 ),
    .I4(N_PZ_975),
    .I5(\NlwInverterSignal_U1/Channel1<8>_MC.D2_PT_1/IN5 ),
    .O(\U1/Channel1<8>_MC.D2_PT_1 )
  );
  X_AND6 \U1/Channel1<8>_MC.D2_PT_2_742  (
    .I0(\U1/U6/CurrState_Sreg0_FFD3 ),
    .I1(\NlwInverterSignal_U1/Channel1<8>_MC.D2_PT_2/IN1 ),
    .I2(\U1/Channel1 [8]),
    .I3(N_PZ_975),
    .I4(\NlwInverterSignal_U1/Channel1<8>_MC.D2_PT_2/IN4 ),
    .I5(\U1/U5/location_Maddsub__n0000__n0067 [0]),
    .O(\U1/Channel1<8>_MC.D2_PT_2 )
  );
  X_AND6 \U1/Channel1<8>_MC.D2_PT_3_743  (
    .I0(\U1/U6/CurrState_Sreg0_FFD3 ),
    .I1(\NlwInverterSignal_U1/Channel1<8>_MC.D2_PT_3/IN1 ),
    .I2(\U1/Channel1 [8]),
    .I3(N_PZ_975),
    .I4(\NlwInverterSignal_U1/Channel1<8>_MC.D2_PT_3/IN4 ),
    .I5(\NlwInverterSignal_U1/Channel1<8>_MC.D2_PT_3/IN5 ),
    .O(\U1/Channel1<8>_MC.D2_PT_3 )
  );
  X_AND6 \U1/Channel1<8>_MC.D2_PT_4_744  (
    .I0(\U1/U6/CurrState_Sreg0_FFD3 ),
    .I1(\NlwInverterSignal_U1/Channel1<8>_MC.D2_PT_4/IN1 ),
    .I2(\U1/Channel1 [8]),
    .I3(N_PZ_975),
    .I4(\NlwInverterSignal_U1/Channel1<8>_MC.D2_PT_4/IN4 ),
    .I5(\U1/Channel1 [7]),
    .O(\U1/Channel1<8>_MC.D2_PT_4 )
  );
  X_AND8 \U1/Channel1<8>_MC.D2_PT_5_745  (
    .I0(\MSPReset_II/UIM ),
    .I1(\NlwInverterSignal_U1/Channel1<8>_MC.D2_PT_5/IN1 ),
    .I2(\U1/U6/CurrState_Sreg0_FFD3 ),
    .I3(\NlwInverterSignal_U1/Channel1<8>_MC.D2_PT_5/IN3 ),
    .I4(N_PZ_1154),
    .I5(\NlwInverterSignal_U1/Channel1<8>_MC.D2_PT_5/IN5 ),
    .I6(\NlwInverterSignal_U1/Channel1<8>_MC.D2_PT_5/IN6 ),
    .I7(\U1/U5/location_Maddsub__n0000__n0075 [0]),
    .O(\U1/Channel1<8>_MC.D2_PT_5 )
  );
  X_AND16 \U1/Channel1<8>_MC.D2_PT_6_746  (
    .I0(\U1/U6/CurrState_Sreg0_FFD3 ),
    .I1(\NlwInverterSignal_U1/Channel1<8>_MC.D2_PT_6/IN1 ),
    .I2(N_PZ_1154),
    .I3(\U1/Channel1 [8]),
    .I4(\NlwInverterSignal_U1/Channel1<8>_MC.D2_PT_6/IN4 ),
    .I5(\NlwInverterSignal_U1/Channel1<8>_MC.D2_PT_6/IN5 ),
    .I6(\U1/U5/location_Maddsub__n0000__n0067 [0]),
    .I7(\NlwInverterSignal_U1/Channel1<8>_MC.D2_PT_6/IN7 ),
    .I8(\NlwInverterSignal_U1/Channel1<8>_MC.D2_PT_6/IN8 ),
    .I9(Vcc),
    .I10(Vcc),
    .I11(Vcc),
    .I12(Vcc),
    .I13(Vcc),
    .I14(Vcc),
    .I15(Vcc),
    .O(\U1/Channel1<8>_MC.D2_PT_6 )
  );
  X_AND16 \U1/Channel1<8>_MC.D2_PT_7_747  (
    .I0(\MSPReset_II/UIM ),
    .I1(\NlwInverterSignal_U1/Channel1<8>_MC.D2_PT_7/IN1 ),
    .I2(\U1/U6/CurrState_Sreg0_FFD3 ),
    .I3(\NlwInverterSignal_U1/Channel1<8>_MC.D2_PT_7/IN3 ),
    .I4(N_PZ_1154),
    .I5(\NlwInverterSignal_U1/Channel1<8>_MC.D2_PT_7/IN5 ),
    .I6(\U1/Channel1 [5]),
    .I7(\U1/U5/location_Maddsub__n0000__n0075 [0]),
    .I8(\NlwInverterSignal_U1/Channel1<8>_MC.D2_PT_7/IN8 ),
    .I9(\U1/Channel1 [6]),
    .I10(\U1/Channel1 [7]),
    .I11(Vcc),
    .I12(Vcc),
    .I13(Vcc),
    .I14(Vcc),
    .I15(Vcc),
    .O(\U1/Channel1<8>_MC.D2_PT_7 )
  );
  X_OR8 \U1/Channel1<8>_MC.D2_748  (
    .I0(\U1/Channel1<8>_MC.D2_PT_0 ),
    .I1(\U1/Channel1<8>_MC.D2_PT_1 ),
    .I2(\U1/Channel1<8>_MC.D2_PT_2 ),
    .I3(\U1/Channel1<8>_MC.D2_PT_3 ),
    .I4(\U1/Channel1<8>_MC.D2_PT_4 ),
    .I5(\U1/Channel1<8>_MC.D2_PT_5 ),
    .I6(\U1/Channel1<8>_MC.D2_PT_6 ),
    .I7(\U1/Channel1<8>_MC.D2_PT_7 ),
    .O(\U1/Channel1<8>_MC.D2 )
  );
  X_BUF \U1/Channel1<5>  (
    .I(\U1/Channel1<5>_MC.Q ),
    .O(\U1/Channel1 [5])
  );
  X_XOR2 \U1/Channel1<5>_MC_tsimcreated_xor__749  (
    .I0(\U1/Channel1<5>_MC.D ),
    .I1(\U1/Channel1<5>_MC.Q ),
    .O(\U1/Channel1<5>_MC_tsimcreated_xor_ )
  );
  X_FF \U1/Channel1<5>_MC.REG  (
    .I(\U1/Channel1<5>_MC_tsimcreated_xor_ ),
    .CE(Vcc),
    .CLK(\Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\U1/Channel1<5>_MC.Q )
  );
  X_XOR2 \U1/Channel1<5>_MC.D_750  (
    .I0(\U1/Channel1<5>_MC.D1 ),
    .I1(\U1/Channel1<5>_MC.D2 ),
    .O(\U1/Channel1<5>_MC.D )
  );
  X_ZERO \U1/Channel1<5>_MC.D1_751  (
    .O(\U1/Channel1<5>_MC.D1 )
  );
  X_AND2 \U1/Channel1<5>_MC.D2_PT_0_752  (
    .I0(\NlwInverterSignal_U1/Channel1<5>_MC.D2_PT_0/IN0 ),
    .I1(\U1/Channel1 [5]),
    .O(\U1/Channel1<5>_MC.D2_PT_0 )
  );
  X_AND6 \U1/Channel1<5>_MC.D2_PT_1_753  (
    .I0(\MSPReset_II/UIM ),
    .I1(\NlwInverterSignal_U1/Channel1<5>_MC.D2_PT_1/IN1 ),
    .I2(\U1/U6/CurrState_Sreg0_FFD3 ),
    .I3(\NlwInverterSignal_U1/Channel1<5>_MC.D2_PT_1/IN3 ),
    .I4(N_PZ_975),
    .I5(\NlwInverterSignal_U1/Channel1<5>_MC.D2_PT_1/IN5 ),
    .O(\U1/Channel1<5>_MC.D2_PT_1 )
  );
  X_AND7 \U1/Channel1<5>_MC.D2_PT_2_754  (
    .I0(\MSPReset_II/UIM ),
    .I1(\NlwInverterSignal_U1/Channel1<5>_MC.D2_PT_2/IN1 ),
    .I2(\U1/U6/CurrState_Sreg0_FFD3 ),
    .I3(\NlwInverterSignal_U1/Channel1<5>_MC.D2_PT_2/IN3 ),
    .I4(N_PZ_1154),
    .I5(\NlwInverterSignal_U1/Channel1<5>_MC.D2_PT_2/IN5 ),
    .I6(\U1/U5/location_Maddsub__n0000__n0067 [0]),
    .O(\U1/Channel1<5>_MC.D2_PT_2 )
  );
  X_OR3 \U1/Channel1<5>_MC.D2_755  (
    .I0(\U1/Channel1<5>_MC.D2_PT_0 ),
    .I1(\U1/Channel1<5>_MC.D2_PT_1 ),
    .I2(\U1/Channel1<5>_MC.D2_PT_2 ),
    .O(\U1/Channel1<5>_MC.D2 )
  );
  X_BUF \U1/U5/location_Maddsub__n0000__n0067<0>  (
    .I(\U1/U5/location_Maddsub__n0000__n0067<0>_MC.Q ),
    .O(\U1/U5/location_Maddsub__n0000__n0067 [0])
  );
  X_BUF \U1/U5/location_Maddsub__n0000__n0067<0>_MC.Q_756  (
    .I(\U1/U5/location_Maddsub__n0000__n0067<0>_MC.D ),
    .O(\U1/U5/location_Maddsub__n0000__n0067<0>_MC.Q )
  );
  X_XOR2 \U1/U5/location_Maddsub__n0000__n0067<0>_MC.D_757  (
    .I0(\U1/U5/location_Maddsub__n0000__n0067<0>_MC.D1 ),
    .I1(\U1/U5/location_Maddsub__n0000__n0067<0>_MC.D2 ),
    .O(\U1/U5/location_Maddsub__n0000__n0067<0>_MC.D )
  );
  X_AND2 \U1/U5/location_Maddsub__n0000__n0067<0>_MC.D1_758  (
    .I0(N_PZ_998),
    .I1(N_PZ_998),
    .O(\U1/U5/location_Maddsub__n0000__n0067<0>_MC.D1 )
  );
  X_AND6 \U1/U5/location_Maddsub__n0000__n0067<0>_MC.D2_PT_0_759  (
    .I0(\U1/Channel1 [0]),
    .I1(N_PZ_998),
    .I2(\U1/Channel1 [1]),
    .I3(\U1/Channel1 [2]),
    .I4(\U1/Channel1 [3]),
    .I5(\U1/Channel1 [4]),
    .O(\U1/U5/location_Maddsub__n0000__n0067<0>_MC.D2_PT_0 )
  );
  X_AND6 \U1/U5/location_Maddsub__n0000__n0067<0>_MC.D2_PT_1_760  (
    .I0(\NlwInverterSignal_U1/U5/location_Maddsub__n0000__n0067<0>_MC.D2_PT_1/IN0 ),
    .I1(\NlwInverterSignal_U1/U5/location_Maddsub__n0000__n0067<0>_MC.D2_PT_1/IN1 ),
    .I2(\NlwInverterSignal_U1/U5/location_Maddsub__n0000__n0067<0>_MC.D2_PT_1/IN2 ),
    .I3(\NlwInverterSignal_U1/U5/location_Maddsub__n0000__n0067<0>_MC.D2_PT_1/IN3 ),
    .I4(\NlwInverterSignal_U1/U5/location_Maddsub__n0000__n0067<0>_MC.D2_PT_1/IN4 ),
    .I5(\NlwInverterSignal_U1/U5/location_Maddsub__n0000__n0067<0>_MC.D2_PT_1/IN5 ),
    .O(\U1/U5/location_Maddsub__n0000__n0067<0>_MC.D2_PT_1 )
  );
  X_OR2 \U1/U5/location_Maddsub__n0000__n0067<0>_MC.D2_761  (
    .I0(\U1/U5/location_Maddsub__n0000__n0067<0>_MC.D2_PT_0 ),
    .I1(\U1/U5/location_Maddsub__n0000__n0067<0>_MC.D2_PT_1 ),
    .O(\U1/U5/location_Maddsub__n0000__n0067<0>_MC.D2 )
  );
  X_BUF N_PZ_998_762 (
    .I(\N_PZ_998_MC.Q ),
    .O(N_PZ_998)
  );
  X_BUF \N_PZ_998_MC.Q_763  (
    .I(\N_PZ_998_MC.D ),
    .O(\N_PZ_998_MC.Q )
  );
  X_XOR2 \N_PZ_998_MC.D_764  (
    .I0(\N_PZ_998_MC.D1 ),
    .I1(\N_PZ_998_MC.D2 ),
    .O(\N_PZ_998_MC.D )
  );
  X_AND2 \N_PZ_998_MC.D1_765  (
    .I0(\U1/NET3720 ),
    .I1(\U1/NET3720 ),
    .O(\N_PZ_998_MC.D1 )
  );
  X_AND3 \N_PZ_998_MC.D2_PT_0_766  (
    .I0(\U1/U6/CurrState_Sreg0_FFD3 ),
    .I1(\NlwInverterSignal_N_PZ_998_MC.D2_PT_0/IN1 ),
    .I2(\NlwInverterSignal_N_PZ_998_MC.D2_PT_0/IN2 ),
    .O(\N_PZ_998_MC.D2_PT_0 )
  );
  X_AND3 \N_PZ_998_MC.D2_PT_1_767  (
    .I0(\U1/U6/CurrState_Sreg0_FFD2 ),
    .I1(\NlwInverterSignal_N_PZ_998_MC.D2_PT_1/IN1 ),
    .I2(\NlwInverterSignal_N_PZ_998_MC.D2_PT_1/IN2 ),
    .O(\N_PZ_998_MC.D2_PT_1 )
  );
  X_OR2 \N_PZ_998_MC.D2_768  (
    .I0(\N_PZ_998_MC.D2_PT_0 ),
    .I1(\N_PZ_998_MC.D2_PT_1 ),
    .O(\N_PZ_998_MC.D2 )
  );
  X_BUF \U1/NET3720_769  (
    .I(\U1/NET3720_MC.Q ),
    .O(\U1/NET3720 )
  );
  X_FF \U1/NET3720_MC.REG  (
    .I(\U1/NET3720_MC.D ),
    .CE(Vcc),
    .CLK(\U1/NET3720_MC.REG_tsimcreated_inv_Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\U1/NET3720_MC.Q )
  );
  X_INV \U1/NET3720_MC.REG_tsimcreated_inv_Mclk_II/FCLK_770  (
    .I(\Mclk_II/FCLK ),
    .O(\U1/NET3720_MC.REG_tsimcreated_inv_Mclk_II/FCLK )
  );
  X_XOR2 \U1/NET3720_MC.D_771  (
    .I0(\U1/NET3720_MC.D1 ),
    .I1(\U1/NET3720_MC.D2 ),
    .O(\U1/NET3720_MC.D )
  );
  X_ZERO \U1/NET3720_MC.D1_772  (
    .O(\U1/NET3720_MC.D1 )
  );
  X_AND3 \U1/NET3720_MC.D2_PT_0_773  (
    .I0(\MSPReset_II/UIM ),
    .I1(\AD<7>_II/UIM ),
    .I2(DCORENCCTLw),
    .O(\U1/NET3720_MC.D2_PT_0 )
  );
  X_AND3 \U1/NET3720_MC.D2_PT_1_774  (
    .I0(\MSPReset_II/UIM ),
    .I1(\NlwInverterSignal_U1/NET3720_MC.D2_PT_1/IN1 ),
    .I2(\U1/NET3720 ),
    .O(\U1/NET3720_MC.D2_PT_1 )
  );
  X_OR2 \U1/NET3720_MC.D2_775  (
    .I0(\U1/NET3720_MC.D2_PT_0 ),
    .I1(\U1/NET3720_MC.D2_PT_1 ),
    .O(\U1/NET3720_MC.D2 )
  );
  X_BUF \U1/Channel1<1>  (
    .I(\U1/Channel1<1>_MC.Q ),
    .O(\U1/Channel1 [1])
  );
  X_XOR2 \U1/Channel1<1>_MC_tsimcreated_xor__776  (
    .I0(\U1/Channel1<1>_MC.D ),
    .I1(\U1/Channel1<1>_MC.Q ),
    .O(\U1/Channel1<1>_MC_tsimcreated_xor_ )
  );
  X_FF \U1/Channel1<1>_MC.REG  (
    .I(\U1/Channel1<1>_MC_tsimcreated_xor_ ),
    .CE(Vcc),
    .CLK(\Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\U1/Channel1<1>_MC.Q )
  );
  X_XOR2 \U1/Channel1<1>_MC.D_777  (
    .I0(\U1/Channel1<1>_MC.D1 ),
    .I1(\U1/Channel1<1>_MC.D2 ),
    .O(\U1/Channel1<1>_MC.D )
  );
  X_ZERO \U1/Channel1<1>_MC.D1_778  (
    .O(\U1/Channel1<1>_MC.D1 )
  );
  X_AND2 \U1/Channel1<1>_MC.D2_PT_0_779  (
    .I0(\NlwInverterSignal_U1/Channel1<1>_MC.D2_PT_0/IN0 ),
    .I1(\U1/Channel1 [1]),
    .O(\U1/Channel1<1>_MC.D2_PT_0 )
  );
  X_AND6 \U1/Channel1<1>_MC.D2_PT_1_780  (
    .I0(\MSPReset_II/UIM ),
    .I1(\U1/Channel1 [0]),
    .I2(\NlwInverterSignal_U1/Channel1<1>_MC.D2_PT_1/IN2 ),
    .I3(\U1/U6/CurrState_Sreg0_FFD3 ),
    .I4(\NlwInverterSignal_U1/Channel1<1>_MC.D2_PT_1/IN4 ),
    .I5(N_PZ_975),
    .O(\U1/Channel1<1>_MC.D2_PT_1 )
  );
  X_AND7 \U1/Channel1<1>_MC.D2_PT_2_781  (
    .I0(\MSPReset_II/UIM ),
    .I1(\NlwInverterSignal_U1/Channel1<1>_MC.D2_PT_2/IN1 ),
    .I2(\NlwInverterSignal_U1/Channel1<1>_MC.D2_PT_2/IN2 ),
    .I3(\U1/U6/CurrState_Sreg0_FFD3 ),
    .I4(\NlwInverterSignal_U1/Channel1<1>_MC.D2_PT_2/IN4 ),
    .I5(N_PZ_1154),
    .I6(\NlwInverterSignal_U1/Channel1<1>_MC.D2_PT_2/IN6 ),
    .O(\U1/Channel1<1>_MC.D2_PT_2 )
  );
  X_OR3 \U1/Channel1<1>_MC.D2_782  (
    .I0(\U1/Channel1<1>_MC.D2_PT_0 ),
    .I1(\U1/Channel1<1>_MC.D2_PT_1 ),
    .I2(\U1/Channel1<1>_MC.D2_PT_2 ),
    .O(\U1/Channel1<1>_MC.D2 )
  );
  X_BUF N_PZ_975_783 (
    .I(\N_PZ_975_MC.Q ),
    .O(N_PZ_975)
  );
  X_BUF \N_PZ_975_MC.Q_784  (
    .I(\N_PZ_975_MC.D ),
    .O(\N_PZ_975_MC.Q )
  );
  X_XOR2 \N_PZ_975_MC.D_785  (
    .I0(\N_PZ_975_MC.D1 ),
    .I1(\N_PZ_975_MC.D2 ),
    .O(\N_PZ_975_MC.D )
  );
  X_ZERO \N_PZ_975_MC.D1_786  (
    .O(\N_PZ_975_MC.D1 )
  );
  X_AND3 \N_PZ_975_MC.D2_PT_0_787  (
    .I0(\U1/U6/CurrState_Sreg0_FFD4 ),
    .I1(\NlwInverterSignal_N_PZ_975_MC.D2_PT_0/IN1 ),
    .I2(\NlwInverterSignal_N_PZ_975_MC.D2_PT_0/IN2 ),
    .O(\N_PZ_975_MC.D2_PT_0 )
  );
  X_AND3 \N_PZ_975_MC.D2_PT_1_788  (
    .I0(\NlwInverterSignal_N_PZ_975_MC.D2_PT_1/IN0 ),
    .I1(\U1/U6/CurrState_Sreg0_FFD1 ),
    .I2(\U1/NET3720 ),
    .O(\N_PZ_975_MC.D2_PT_1 )
  );
  X_OR2 \N_PZ_975_MC.D2_789  (
    .I0(\N_PZ_975_MC.D2_PT_0 ),
    .I1(\N_PZ_975_MC.D2_PT_1 ),
    .O(\N_PZ_975_MC.D2 )
  );
  X_BUF \U1/Channel1<2>  (
    .I(\U1/Channel1<2>_MC.Q ),
    .O(\U1/Channel1 [2])
  );
  X_XOR2 \U1/Channel1<2>_MC_tsimcreated_xor__790  (
    .I0(\U1/Channel1<2>_MC.D ),
    .I1(\U1/Channel1<2>_MC.Q ),
    .O(\U1/Channel1<2>_MC_tsimcreated_xor_ )
  );
  X_FF \U1/Channel1<2>_MC.REG  (
    .I(\U1/Channel1<2>_MC_tsimcreated_xor_ ),
    .CE(Vcc),
    .CLK(\Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\U1/Channel1<2>_MC.Q )
  );
  X_XOR2 \U1/Channel1<2>_MC.D_791  (
    .I0(\U1/Channel1<2>_MC.D1 ),
    .I1(\U1/Channel1<2>_MC.D2 ),
    .O(\U1/Channel1<2>_MC.D )
  );
  X_ZERO \U1/Channel1<2>_MC.D1_792  (
    .O(\U1/Channel1<2>_MC.D1 )
  );
  X_AND2 \U1/Channel1<2>_MC.D2_PT_0_793  (
    .I0(\NlwInverterSignal_U1/Channel1<2>_MC.D2_PT_0/IN0 ),
    .I1(\U1/Channel1 [2]),
    .O(\U1/Channel1<2>_MC.D2_PT_0 )
  );
  X_AND7 \U1/Channel1<2>_MC.D2_PT_1_794  (
    .I0(\MSPReset_II/UIM ),
    .I1(\U1/Channel1 [0]),
    .I2(\NlwInverterSignal_U1/Channel1<2>_MC.D2_PT_1/IN2 ),
    .I3(\U1/U6/CurrState_Sreg0_FFD3 ),
    .I4(\NlwInverterSignal_U1/Channel1<2>_MC.D2_PT_1/IN4 ),
    .I5(N_PZ_975),
    .I6(\U1/Channel1 [1]),
    .O(\U1/Channel1<2>_MC.D2_PT_1 )
  );
  X_AND8 \U1/Channel1<2>_MC.D2_PT_2_795  (
    .I0(\MSPReset_II/UIM ),
    .I1(\NlwInverterSignal_U1/Channel1<2>_MC.D2_PT_2/IN1 ),
    .I2(\NlwInverterSignal_U1/Channel1<2>_MC.D2_PT_2/IN2 ),
    .I3(\U1/U6/CurrState_Sreg0_FFD3 ),
    .I4(\NlwInverterSignal_U1/Channel1<2>_MC.D2_PT_2/IN4 ),
    .I5(N_PZ_1154),
    .I6(\NlwInverterSignal_U1/Channel1<2>_MC.D2_PT_2/IN6 ),
    .I7(\NlwInverterSignal_U1/Channel1<2>_MC.D2_PT_2/IN7 ),
    .O(\U1/Channel1<2>_MC.D2_PT_2 )
  );
  X_OR3 \U1/Channel1<2>_MC.D2_796  (
    .I0(\U1/Channel1<2>_MC.D2_PT_0 ),
    .I1(\U1/Channel1<2>_MC.D2_PT_1 ),
    .I2(\U1/Channel1<2>_MC.D2_PT_2 ),
    .O(\U1/Channel1<2>_MC.D2 )
  );
  X_BUF \U1/Channel1<3>  (
    .I(\U1/Channel1<3>_MC.Q ),
    .O(\U1/Channel1 [3])
  );
  X_XOR2 \U1/Channel1<3>_MC_tsimcreated_xor__797  (
    .I0(\U1/Channel1<3>_MC.D ),
    .I1(\U1/Channel1<3>_MC.Q ),
    .O(\U1/Channel1<3>_MC_tsimcreated_xor_ )
  );
  X_FF \U1/Channel1<3>_MC.REG  (
    .I(\U1/Channel1<3>_MC_tsimcreated_xor_ ),
    .CE(Vcc),
    .CLK(\Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\U1/Channel1<3>_MC.Q )
  );
  X_XOR2 \U1/Channel1<3>_MC.D_798  (
    .I0(\U1/Channel1<3>_MC.D1 ),
    .I1(\U1/Channel1<3>_MC.D2 ),
    .O(\U1/Channel1<3>_MC.D )
  );
  X_ZERO \U1/Channel1<3>_MC.D1_799  (
    .O(\U1/Channel1<3>_MC.D1 )
  );
  X_AND2 \U1/Channel1<3>_MC.D2_PT_0_800  (
    .I0(\NlwInverterSignal_U1/Channel1<3>_MC.D2_PT_0/IN0 ),
    .I1(\U1/Channel1 [3]),
    .O(\U1/Channel1<3>_MC.D2_PT_0 )
  );
  X_AND8 \U1/Channel1<3>_MC.D2_PT_1_801  (
    .I0(\MSPReset_II/UIM ),
    .I1(\U1/Channel1 [0]),
    .I2(\NlwInverterSignal_U1/Channel1<3>_MC.D2_PT_1/IN2 ),
    .I3(\U1/U6/CurrState_Sreg0_FFD3 ),
    .I4(\NlwInverterSignal_U1/Channel1<3>_MC.D2_PT_1/IN4 ),
    .I5(N_PZ_975),
    .I6(\U1/Channel1 [1]),
    .I7(\U1/Channel1 [2]),
    .O(\U1/Channel1<3>_MC.D2_PT_1 )
  );
  X_AND16 \U1/Channel1<3>_MC.D2_PT_2_802  (
    .I0(\MSPReset_II/UIM ),
    .I1(\NlwInverterSignal_U1/Channel1<3>_MC.D2_PT_2/IN1 ),
    .I2(\NlwInverterSignal_U1/Channel1<3>_MC.D2_PT_2/IN2 ),
    .I3(\U1/U6/CurrState_Sreg0_FFD3 ),
    .I4(\NlwInverterSignal_U1/Channel1<3>_MC.D2_PT_2/IN4 ),
    .I5(N_PZ_1154),
    .I6(\NlwInverterSignal_U1/Channel1<3>_MC.D2_PT_2/IN6 ),
    .I7(\NlwInverterSignal_U1/Channel1<3>_MC.D2_PT_2/IN7 ),
    .I8(\NlwInverterSignal_U1/Channel1<3>_MC.D2_PT_2/IN8 ),
    .I9(Vcc),
    .I10(Vcc),
    .I11(Vcc),
    .I12(Vcc),
    .I13(Vcc),
    .I14(Vcc),
    .I15(Vcc),
    .O(\U1/Channel1<3>_MC.D2_PT_2 )
  );
  X_OR3 \U1/Channel1<3>_MC.D2_803  (
    .I0(\U1/Channel1<3>_MC.D2_PT_0 ),
    .I1(\U1/Channel1<3>_MC.D2_PT_1 ),
    .I2(\U1/Channel1<3>_MC.D2_PT_2 ),
    .O(\U1/Channel1<3>_MC.D2 )
  );
  X_BUF \U1/Channel1<4>  (
    .I(\U1/Channel1<4>_MC.Q ),
    .O(\U1/Channel1 [4])
  );
  X_XOR2 \U1/Channel1<4>_MC_tsimcreated_xor__804  (
    .I0(\U1/Channel1<4>_MC.D ),
    .I1(\U1/Channel1<4>_MC.Q ),
    .O(\U1/Channel1<4>_MC_tsimcreated_xor_ )
  );
  X_FF \U1/Channel1<4>_MC.REG  (
    .I(\U1/Channel1<4>_MC_tsimcreated_xor_ ),
    .CE(Vcc),
    .CLK(\Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\U1/Channel1<4>_MC.Q )
  );
  X_XOR2 \U1/Channel1<4>_MC.D_805  (
    .I0(\U1/Channel1<4>_MC.D1 ),
    .I1(\U1/Channel1<4>_MC.D2 ),
    .O(\U1/Channel1<4>_MC.D )
  );
  X_ZERO \U1/Channel1<4>_MC.D1_806  (
    .O(\U1/Channel1<4>_MC.D1 )
  );
  X_AND2 \U1/Channel1<4>_MC.D2_PT_0_807  (
    .I0(\NlwInverterSignal_U1/Channel1<4>_MC.D2_PT_0/IN0 ),
    .I1(\U1/Channel1 [4]),
    .O(\U1/Channel1<4>_MC.D2_PT_0 )
  );
  X_AND6 \U1/Channel1<4>_MC.D2_PT_1_808  (
    .I0(\NlwInverterSignal_U1/Channel1<4>_MC.D2_PT_1/IN0 ),
    .I1(\U1/U6/CurrState_Sreg0_FFD3 ),
    .I2(\NlwInverterSignal_U1/Channel1<4>_MC.D2_PT_1/IN2 ),
    .I3(N_PZ_975),
    .I4(\NlwInverterSignal_U1/Channel1<4>_MC.D2_PT_1/IN4 ),
    .I5(\U1/Channel1 [4]),
    .O(\U1/Channel1<4>_MC.D2_PT_1 )
  );
  X_AND6 \U1/Channel1<4>_MC.D2_PT_2_809  (
    .I0(\U1/U6/CurrState_Sreg0_FFD3 ),
    .I1(\NlwInverterSignal_U1/Channel1<4>_MC.D2_PT_2/IN1 ),
    .I2(N_PZ_975),
    .I3(\NlwInverterSignal_U1/Channel1<4>_MC.D2_PT_2/IN3 ),
    .I4(\NlwInverterSignal_U1/Channel1<4>_MC.D2_PT_2/IN4 ),
    .I5(\U1/Channel1 [4]),
    .O(\U1/Channel1<4>_MC.D2_PT_2 )
  );
  X_AND6 \U1/Channel1<4>_MC.D2_PT_3_810  (
    .I0(\U1/U6/CurrState_Sreg0_FFD3 ),
    .I1(\NlwInverterSignal_U1/Channel1<4>_MC.D2_PT_3/IN1 ),
    .I2(N_PZ_975),
    .I3(\NlwInverterSignal_U1/Channel1<4>_MC.D2_PT_3/IN3 ),
    .I4(\NlwInverterSignal_U1/Channel1<4>_MC.D2_PT_3/IN4 ),
    .I5(\U1/Channel1 [4]),
    .O(\U1/Channel1<4>_MC.D2_PT_3 )
  );
  X_AND6 \U1/Channel1<4>_MC.D2_PT_4_811  (
    .I0(\U1/U6/CurrState_Sreg0_FFD3 ),
    .I1(\NlwInverterSignal_U1/Channel1<4>_MC.D2_PT_4/IN1 ),
    .I2(N_PZ_975),
    .I3(\NlwInverterSignal_U1/Channel1<4>_MC.D2_PT_4/IN3 ),
    .I4(\U1/Channel1 [3]),
    .I5(\U1/Channel1 [4]),
    .O(\U1/Channel1<4>_MC.D2_PT_4 )
  );
  X_AND8 \U1/Channel1<4>_MC.D2_PT_5_812  (
    .I0(\MSPReset_II/UIM ),
    .I1(\NlwInverterSignal_U1/Channel1<4>_MC.D2_PT_5/IN1 ),
    .I2(\U1/U6/CurrState_Sreg0_FFD3 ),
    .I3(\NlwInverterSignal_U1/Channel1<4>_MC.D2_PT_5/IN3 ),
    .I4(N_PZ_1154),
    .I5(\NlwInverterSignal_U1/Channel1<4>_MC.D2_PT_5/IN5 ),
    .I6(\U1/U5/location_Maddsub__n0000__n0067 [0]),
    .I7(\NlwInverterSignal_U1/Channel1<4>_MC.D2_PT_5/IN7 ),
    .O(\U1/Channel1<4>_MC.D2_PT_5 )
  );
  X_AND16 \U1/Channel1<4>_MC.D2_PT_6_813  (
    .I0(\NlwInverterSignal_U1/Channel1<4>_MC.D2_PT_6/IN0 ),
    .I1(\U1/U6/CurrState_Sreg0_FFD3 ),
    .I2(\NlwInverterSignal_U1/Channel1<4>_MC.D2_PT_6/IN2 ),
    .I3(N_PZ_1154),
    .I4(\NlwInverterSignal_U1/Channel1<4>_MC.D2_PT_6/IN4 ),
    .I5(\NlwInverterSignal_U1/Channel1<4>_MC.D2_PT_6/IN5 ),
    .I6(\NlwInverterSignal_U1/Channel1<4>_MC.D2_PT_6/IN6 ),
    .I7(\NlwInverterSignal_U1/Channel1<4>_MC.D2_PT_6/IN7 ),
    .I8(\U1/Channel1 [4]),
    .I9(Vcc),
    .I10(Vcc),
    .I11(Vcc),
    .I12(Vcc),
    .I13(Vcc),
    .I14(Vcc),
    .I15(Vcc),
    .O(\U1/Channel1<4>_MC.D2_PT_6 )
  );
  X_AND16 \U1/Channel1<4>_MC.D2_PT_7_814  (
    .I0(\MSPReset_II/UIM ),
    .I1(\U1/Channel1 [0]),
    .I2(\NlwInverterSignal_U1/Channel1<4>_MC.D2_PT_7/IN2 ),
    .I3(\U1/U6/CurrState_Sreg0_FFD3 ),
    .I4(\NlwInverterSignal_U1/Channel1<4>_MC.D2_PT_7/IN4 ),
    .I5(N_PZ_1154),
    .I6(\U1/U5/location_Maddsub__n0000__n0067 [0]),
    .I7(\U1/Channel1 [1]),
    .I8(\U1/Channel1 [2]),
    .I9(\U1/Channel1 [3]),
    .I10(\NlwInverterSignal_U1/Channel1<4>_MC.D2_PT_7/IN10 ),
    .I11(Vcc),
    .I12(Vcc),
    .I13(Vcc),
    .I14(Vcc),
    .I15(Vcc),
    .O(\U1/Channel1<4>_MC.D2_PT_7 )
  );
  X_OR8 \U1/Channel1<4>_MC.D2_815  (
    .I0(\U1/Channel1<4>_MC.D2_PT_0 ),
    .I1(\U1/Channel1<4>_MC.D2_PT_1 ),
    .I2(\U1/Channel1<4>_MC.D2_PT_2 ),
    .I3(\U1/Channel1<4>_MC.D2_PT_3 ),
    .I4(\U1/Channel1<4>_MC.D2_PT_4 ),
    .I5(\U1/Channel1<4>_MC.D2_PT_5 ),
    .I6(\U1/Channel1<4>_MC.D2_PT_6 ),
    .I7(\U1/Channel1<4>_MC.D2_PT_7 ),
    .O(\U1/Channel1<4>_MC.D2 )
  );
  X_BUF \U1/Channel1<6>  (
    .I(\U1/Channel1<6>_MC.Q ),
    .O(\U1/Channel1 [6])
  );
  X_XOR2 \U1/Channel1<6>_MC_tsimcreated_xor__816  (
    .I0(\U1/Channel1<6>_MC.D ),
    .I1(\U1/Channel1<6>_MC.Q ),
    .O(\U1/Channel1<6>_MC_tsimcreated_xor_ )
  );
  X_FF \U1/Channel1<6>_MC.REG  (
    .I(\U1/Channel1<6>_MC_tsimcreated_xor_ ),
    .CE(Vcc),
    .CLK(\Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\U1/Channel1<6>_MC.Q )
  );
  X_XOR2 \U1/Channel1<6>_MC.D_817  (
    .I0(\U1/Channel1<6>_MC.D1 ),
    .I1(\U1/Channel1<6>_MC.D2 ),
    .O(\U1/Channel1<6>_MC.D )
  );
  X_ZERO \U1/Channel1<6>_MC.D1_818  (
    .O(\U1/Channel1<6>_MC.D1 )
  );
  X_AND2 \U1/Channel1<6>_MC.D2_PT_0_819  (
    .I0(\NlwInverterSignal_U1/Channel1<6>_MC.D2_PT_0/IN0 ),
    .I1(\U1/Channel1 [6]),
    .O(\U1/Channel1<6>_MC.D2_PT_0 )
  );
  X_AND7 \U1/Channel1<6>_MC.D2_PT_1_820  (
    .I0(\MSPReset_II/UIM ),
    .I1(\NlwInverterSignal_U1/Channel1<6>_MC.D2_PT_1/IN1 ),
    .I2(\U1/U6/CurrState_Sreg0_FFD3 ),
    .I3(\NlwInverterSignal_U1/Channel1<6>_MC.D2_PT_1/IN3 ),
    .I4(\U1/Channel1 [5]),
    .I5(N_PZ_975),
    .I6(\NlwInverterSignal_U1/Channel1<6>_MC.D2_PT_1/IN6 ),
    .O(\U1/Channel1<6>_MC.D2_PT_1 )
  );
  X_AND8 \U1/Channel1<6>_MC.D2_PT_2_821  (
    .I0(\MSPReset_II/UIM ),
    .I1(\NlwInverterSignal_U1/Channel1<6>_MC.D2_PT_2/IN1 ),
    .I2(\U1/U6/CurrState_Sreg0_FFD3 ),
    .I3(\NlwInverterSignal_U1/Channel1<6>_MC.D2_PT_2/IN3 ),
    .I4(N_PZ_1154),
    .I5(\NlwInverterSignal_U1/Channel1<6>_MC.D2_PT_2/IN5 ),
    .I6(\NlwInverterSignal_U1/Channel1<6>_MC.D2_PT_2/IN6 ),
    .I7(\U1/U5/location_Maddsub__n0000__n0067 [0]),
    .O(\U1/Channel1<6>_MC.D2_PT_2 )
  );
  X_OR3 \U1/Channel1<6>_MC.D2_822  (
    .I0(\U1/Channel1<6>_MC.D2_PT_0 ),
    .I1(\U1/Channel1<6>_MC.D2_PT_1 ),
    .I2(\U1/Channel1<6>_MC.D2_PT_2 ),
    .O(\U1/Channel1<6>_MC.D2 )
  );
  X_BUF \U1/Channel1<7>  (
    .I(\U1/Channel1<7>_MC.Q ),
    .O(\U1/Channel1 [7])
  );
  X_XOR2 \U1/Channel1<7>_MC_tsimcreated_xor__823  (
    .I0(\U1/Channel1<7>_MC.D ),
    .I1(\U1/Channel1<7>_MC.Q ),
    .O(\U1/Channel1<7>_MC_tsimcreated_xor_ )
  );
  X_FF \U1/Channel1<7>_MC.REG  (
    .I(\U1/Channel1<7>_MC_tsimcreated_xor_ ),
    .CE(Vcc),
    .CLK(\Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\U1/Channel1<7>_MC.Q )
  );
  X_XOR2 \U1/Channel1<7>_MC.D_824  (
    .I0(\U1/Channel1<7>_MC.D1 ),
    .I1(\U1/Channel1<7>_MC.D2 ),
    .O(\U1/Channel1<7>_MC.D )
  );
  X_ZERO \U1/Channel1<7>_MC.D1_825  (
    .O(\U1/Channel1<7>_MC.D1 )
  );
  X_AND2 \U1/Channel1<7>_MC.D2_PT_0_826  (
    .I0(\NlwInverterSignal_U1/Channel1<7>_MC.D2_PT_0/IN0 ),
    .I1(\U1/Channel1 [7]),
    .O(\U1/Channel1<7>_MC.D2_PT_0 )
  );
  X_AND8 \U1/Channel1<7>_MC.D2_PT_1_827  (
    .I0(\MSPReset_II/UIM ),
    .I1(\NlwInverterSignal_U1/Channel1<7>_MC.D2_PT_1/IN1 ),
    .I2(\U1/U6/CurrState_Sreg0_FFD3 ),
    .I3(\NlwInverterSignal_U1/Channel1<7>_MC.D2_PT_1/IN3 ),
    .I4(\U1/Channel1 [5]),
    .I5(N_PZ_975),
    .I6(\NlwInverterSignal_U1/Channel1<7>_MC.D2_PT_1/IN6 ),
    .I7(\U1/Channel1 [6]),
    .O(\U1/Channel1<7>_MC.D2_PT_1 )
  );
  X_AND16 \U1/Channel1<7>_MC.D2_PT_2_828  (
    .I0(\MSPReset_II/UIM ),
    .I1(\NlwInverterSignal_U1/Channel1<7>_MC.D2_PT_2/IN1 ),
    .I2(\U1/U6/CurrState_Sreg0_FFD3 ),
    .I3(\NlwInverterSignal_U1/Channel1<7>_MC.D2_PT_2/IN3 ),
    .I4(N_PZ_1154),
    .I5(\NlwInverterSignal_U1/Channel1<7>_MC.D2_PT_2/IN5 ),
    .I6(\NlwInverterSignal_U1/Channel1<7>_MC.D2_PT_2/IN6 ),
    .I7(\U1/U5/location_Maddsub__n0000__n0067 [0]),
    .I8(\NlwInverterSignal_U1/Channel1<7>_MC.D2_PT_2/IN8 ),
    .I9(Vcc),
    .I10(Vcc),
    .I11(Vcc),
    .I12(Vcc),
    .I13(Vcc),
    .I14(Vcc),
    .I15(Vcc),
    .O(\U1/Channel1<7>_MC.D2_PT_2 )
  );
  X_OR3 \U1/Channel1<7>_MC.D2_829  (
    .I0(\U1/Channel1<7>_MC.D2_PT_0 ),
    .I1(\U1/Channel1<7>_MC.D2_PT_1 ),
    .I2(\U1/Channel1<7>_MC.D2_PT_2 ),
    .O(\U1/Channel1<7>_MC.D2 )
  );
  X_BUF \U1/U5/location_Maddsub__n0000__n0075<0>  (
    .I(\U1/U5/location_Maddsub__n0000__n0075<0>_MC.Q ),
    .O(\U1/U5/location_Maddsub__n0000__n0075 [0])
  );
  X_BUF \U1/U5/location_Maddsub__n0000__n0075<0>_MC.Q_830  (
    .I(\U1/U5/location_Maddsub__n0000__n0075<0>_MC.D ),
    .O(\U1/U5/location_Maddsub__n0000__n0075<0>_MC.Q )
  );
  X_XOR2 \U1/U5/location_Maddsub__n0000__n0075<0>_MC.D_831  (
    .I0(\U1/U5/location_Maddsub__n0000__n0075<0>_MC.D1 ),
    .I1(\U1/U5/location_Maddsub__n0000__n0075<0>_MC.D2 ),
    .O(\U1/U5/location_Maddsub__n0000__n0075<0>_MC.D )
  );
  X_AND2 \U1/U5/location_Maddsub__n0000__n0075<0>_MC.D1_832  (
    .I0(N_PZ_998),
    .I1(N_PZ_998),
    .O(\U1/U5/location_Maddsub__n0000__n0075<0>_MC.D1 )
  );
  X_AND6 \U1/U5/location_Maddsub__n0000__n0075<0>_MC.D2_PT_0_833  (
    .I0(\U1/Channel1 [8]),
    .I1(\U1/Channel1 [5]),
    .I2(\NlwInverterSignal_U1/U5/location_Maddsub__n0000__n0075<0>_MC.D2_PT_0/IN2 ),
    .I3(\U1/Channel1 [6]),
    .I4(\U1/Channel1 [7]),
    .I5(N_PZ_998),
    .O(\U1/U5/location_Maddsub__n0000__n0075<0>_MC.D2_PT_0 )
  );
  X_AND6 \U1/U5/location_Maddsub__n0000__n0075<0>_MC.D2_PT_1_834  (
    .I0(\NlwInverterSignal_U1/U5/location_Maddsub__n0000__n0075<0>_MC.D2_PT_1/IN0 ),
    .I1(\NlwInverterSignal_U1/U5/location_Maddsub__n0000__n0075<0>_MC.D2_PT_1/IN1 ),
    .I2(\U1/U5/location_Maddsub__n0000__n0067 [0]),
    .I3(\NlwInverterSignal_U1/U5/location_Maddsub__n0000__n0075<0>_MC.D2_PT_1/IN3 ),
    .I4(\NlwInverterSignal_U1/U5/location_Maddsub__n0000__n0075<0>_MC.D2_PT_1/IN4 ),
    .I5(\NlwInverterSignal_U1/U5/location_Maddsub__n0000__n0075<0>_MC.D2_PT_1/IN5 ),
    .O(\U1/U5/location_Maddsub__n0000__n0075<0>_MC.D2_PT_1 )
  );
  X_OR2 \U1/U5/location_Maddsub__n0000__n0075<0>_MC.D2_835  (
    .I0(\U1/U5/location_Maddsub__n0000__n0075<0>_MC.D2_PT_0 ),
    .I1(\U1/U5/location_Maddsub__n0000__n0075<0>_MC.D2_PT_1 ),
    .O(\U1/U5/location_Maddsub__n0000__n0075<0>_MC.D2 )
  );
  X_BUF DCORCONFIGr_836 (
    .I(\DCORCONFIGr_MC.Q ),
    .O(DCORCONFIGr)
  );
  X_BUF \DCORCONFIGr_MC.Q_837  (
    .I(\DCORCONFIGr_MC.D ),
    .O(\DCORCONFIGr_MC.Q )
  );
  X_XOR2 \DCORCONFIGr_MC.D_838  (
    .I0(\DCORCONFIGr_MC.D1 ),
    .I1(\DCORCONFIGr_MC.D2 ),
    .O(\DCORCONFIGr_MC.D )
  );
  X_AND16 \DCORCONFIGr_MC.D1_839  (
    .I0(\WR_II/UIM ),
    .I1(\NlwInverterSignal_DCORCONFIGr_MC.D1/IN1 ),
    .I2(U2_ADDR_reg[0]),
    .I3(\NlwInverterSignal_DCORCONFIGr_MC.D1/IN3 ),
    .I4(\NlwInverterSignal_DCORCONFIGr_MC.D1/IN4 ),
    .I5(\NlwInverterSignal_DCORCONFIGr_MC.D1/IN5 ),
    .I6(\NlwInverterSignal_DCORCONFIGr_MC.D1/IN6 ),
    .I7(U2_ADDR_reg[3]),
    .I8(U2_ADDR_reg[1]),
    .I9(U2_ADDR_reg[2]),
    .I10(Vcc),
    .I11(Vcc),
    .I12(Vcc),
    .I13(Vcc),
    .I14(Vcc),
    .I15(Vcc),
    .O(\DCORCONFIGr_MC.D1 )
  );
  X_ZERO \DCORCONFIGr_MC.D2_840  (
    .O(\DCORCONFIGr_MC.D2 )
  );
  X_BUF \outDATA<0>\$WA3.UIM_841  (
    .I(\outDATA<0>\$WA3.UIM_MC.Q ),
    .O(\outDATA<0>\$WA3.UIM )
  );
  X_BUF \outDATA<0>\$WA3.UIM_MC.Q_842  (
    .I(\outDATA<0>\$WA3.UIM_MC.D ),
    .O(\outDATA<0>\$WA3.UIM_MC.Q )
  );
  X_XOR2 \outDATA<0>\$WA3.UIM_MC.D_843  (
    .I0(\outDATA<0>\$WA3.UIM_MC.D1 ),
    .I1(\outDATA<0>\$WA3.UIM_MC.D2 ),
    .O(\outDATA<0>\$WA3.UIM_MC.D )
  );
  X_AND2 \outDATA<0>\$WA3.UIM_MC.D1_844  (
    .I0(\I2CS<0>_II/UIM ),
    .I1(\I2CS<0>_II/UIM ),
    .O(\outDATA<0>\$WA3.UIM_MC.D1 )
  );
  X_ZERO \outDATA<0>\$WA3.UIM_MC.D2_845  (
    .O(\outDATA<0>\$WA3.UIM_MC.D2 )
  );
  X_BUF DCORENCPWRr_846 (
    .I(\DCORENCPWRr_MC.Q ),
    .O(DCORENCPWRr)
  );
  X_BUF \DCORENCPWRr_MC.Q_847  (
    .I(\DCORENCPWRr_MC.D ),
    .O(\DCORENCPWRr_MC.Q )
  );
  X_XOR2 \DCORENCPWRr_MC.D_848  (
    .I0(\DCORENCPWRr_MC.D1 ),
    .I1(\DCORENCPWRr_MC.D2 ),
    .O(\DCORENCPWRr_MC.D )
  );
  X_AND16 \DCORENCPWRr_MC.D1_849  (
    .I0(\WR_II/UIM ),
    .I1(\NlwInverterSignal_DCORENCPWRr_MC.D1/IN1 ),
    .I2(\NlwInverterSignal_DCORENCPWRr_MC.D1/IN2 ),
    .I3(\NlwInverterSignal_DCORENCPWRr_MC.D1/IN3 ),
    .I4(\NlwInverterSignal_DCORENCPWRr_MC.D1/IN4 ),
    .I5(\NlwInverterSignal_DCORENCPWRr_MC.D1/IN5 ),
    .I6(\NlwInverterSignal_DCORENCPWRr_MC.D1/IN6 ),
    .I7(U2_ADDR_reg[3]),
    .I8(U2_ADDR_reg[1]),
    .I9(U2_ADDR_reg[2]),
    .I10(Vcc),
    .I11(Vcc),
    .I12(Vcc),
    .I13(Vcc),
    .I14(Vcc),
    .I15(Vcc),
    .O(\DCORENCPWRr_MC.D1 )
  );
  X_ZERO \DCORENCPWRr_MC.D2_850  (
    .O(\DCORENCPWRr_MC.D2 )
  );
  X_BUF \outDATA<0>\$WA5.UIM_851  (
    .I(\outDATA<0>\$WA5.UIM_MC.Q ),
    .O(\outDATA<0>\$WA5.UIM )
  );
  X_BUF \outDATA<0>\$WA5.UIM_MC.Q_852  (
    .I(\outDATA<0>\$WA5.UIM_MC.D ),
    .O(\outDATA<0>\$WA5.UIM_MC.Q )
  );
  X_XOR2 \outDATA<0>\$WA5.UIM_MC.D_853  (
    .I0(\outDATA<0>\$WA5.UIM_MC.D1 ),
    .I1(\outDATA<0>\$WA5.UIM_MC.D2 ),
    .O(\outDATA<0>\$WA5.UIM_MC.D )
  );
  X_ZERO \outDATA<0>\$WA5.UIM_MC.D1_854  (
    .O(\outDATA<0>\$WA5.UIM_MC.D1 )
  );
  X_AND2 \outDATA<0>\$WA5.UIM_MC.D2_PT_0_855  (
    .I0(\Home033FLG_II/UIM ),
    .I1(\NlwInverterSignal_outDATA<0>\$WA5.UIM_MC.D2_PT_0/IN1 ),
    .O(\outDATA<0>\$WA5.UIM_MC.D2_PT_0 )
  );
  X_AND2 \outDATA<0>\$WA5.UIM_MC.D2_PT_1_856  (
    .I0(NET2528),
    .I1(\U4/Flgreg [0]),
    .O(\outDATA<0>\$WA5.UIM_MC.D2_PT_1 )
  );
  X_OR2 \outDATA<0>\$WA5.UIM_MC.D2_857  (
    .I0(\outDATA<0>\$WA5.UIM_MC.D2_PT_0 ),
    .I1(\outDATA<0>\$WA5.UIM_MC.D2_PT_1 ),
    .O(\outDATA<0>\$WA5.UIM_MC.D2 )
  );
  X_BUF NET2528_858 (
    .I(\NET2528_MC.Q ),
    .O(NET2528)
  );
  X_FF \NET2528_MC.REG  (
    .I(\NET2528_MC.D ),
    .CE(Vcc),
    .CLK(\NET2528_MC.REG_tsimcreated_inv_Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\NET2528_MC.Q )
  );
  X_INV \NET2528_MC.REG_tsimcreated_inv_Mclk_II/FCLK_859  (
    .I(\Mclk_II/FCLK ),
    .O(\NET2528_MC.REG_tsimcreated_inv_Mclk_II/FCLK )
  );
  X_XOR2 \NET2528_MC.D_860  (
    .I0(\NET2528_MC.D1 ),
    .I1(\NET2528_MC.D2 ),
    .O(\NET2528_MC.D )
  );
  X_AND2 \NET2528_MC.D1_861  (
    .I0(\MSPReset_II/UIM ),
    .I1(\NlwInverterSignal_NET2528_MC.D1/IN1 ),
    .O(\NET2528_MC.D1 )
  );
  X_AND4 \NET2528_MC.D2_PT_0_862  (
    .I0(\MSPReset_II/UIM ),
    .I1(\NlwInverterSignal_NET2528_MC.D2_PT_0/IN1 ),
    .I2(DCORIFGw),
    .I3(NET2528),
    .O(\NET2528_MC.D2_PT_0 )
  );
  X_AND16 \NET2528_MC.D2_PT_1_863  (
    .I0(\MSPReset_II/UIM ),
    .I1(\NlwInverterSignal_NET2528_MC.D2_PT_1/IN1 ),
    .I2(\Home033FLG_II/UIM ),
    .I3(\NlwInverterSignal_NET2528_MC.D2_PT_1/IN3 ),
    .I4(\Home15FLG_II/UIM ),
    .I5(\Home133FLG_II/UIM ),
    .I6(\Home05FLG_II/UIM ),
    .I7(\Enc15FLG_II/UIM ),
    .I8(\Enc133FLG_II/UIM ),
    .I9(\Enc05FLG_II/UIM ),
    .I10(\Enc033FLG_II/UIM ),
    .I11(Vcc),
    .I12(Vcc),
    .I13(Vcc),
    .I14(Vcc),
    .I15(Vcc),
    .O(\NET2528_MC.D2_PT_1 )
  );
  X_OR2 \NET2528_MC.D2_864  (
    .I0(\NET2528_MC.D2_PT_0 ),
    .I1(\NET2528_MC.D2_PT_1 ),
    .O(\NET2528_MC.D2 )
  );
  X_BUF \U4/orFLGs_865  (
    .I(\U4/orFLGs_MC.Q ),
    .O(\U4/orFLGs )
  );
  X_BUF \U4/orFLGs_MC.Q_866  (
    .I(\U4/orFLGs_MC.D ),
    .O(\U4/orFLGs_MC.Q )
  );
  X_XOR2 \U4/orFLGs_MC.D_867  (
    .I0(\U4/orFLGs_MC.D1 ),
    .I1(\U4/orFLGs_MC.D2 ),
    .O(\U4/orFLGs_MC.D )
  );
  X_AND8 \U4/orFLGs_MC.D1_868  (
    .I0(\Home033FLG_II/UIM ),
    .I1(\Home15FLG_II/UIM ),
    .I2(\Home133FLG_II/UIM ),
    .I3(\Home05FLG_II/UIM ),
    .I4(\Enc15FLG_II/UIM ),
    .I5(\Enc133FLG_II/UIM ),
    .I6(\Enc05FLG_II/UIM ),
    .I7(\Enc033FLG_II/UIM ),
    .O(\U4/orFLGs_MC.D1 )
  );
  X_ZERO \U4/orFLGs_MC.D2_869  (
    .O(\U4/orFLGs_MC.D2 )
  );
  X_BUF DCORIFGr_870 (
    .I(\DCORIFGr_MC.Q ),
    .O(DCORIFGr)
  );
  X_BUF \DCORIFGr_MC.Q_871  (
    .I(\DCORIFGr_MC.D ),
    .O(\DCORIFGr_MC.Q )
  );
  X_XOR2 \DCORIFGr_MC.D_872  (
    .I0(\DCORIFGr_MC.D1 ),
    .I1(\DCORIFGr_MC.D2 ),
    .O(\DCORIFGr_MC.D )
  );
  X_AND16 \DCORIFGr_MC.D1_873  (
    .I0(\WR_II/UIM ),
    .I1(\NlwInverterSignal_DCORIFGr_MC.D1/IN1 ),
    .I2(U2_ADDR_reg[0]),
    .I3(\NlwInverterSignal_DCORIFGr_MC.D1/IN3 ),
    .I4(\NlwInverterSignal_DCORIFGr_MC.D1/IN4 ),
    .I5(\NlwInverterSignal_DCORIFGr_MC.D1/IN5 ),
    .I6(\NlwInverterSignal_DCORIFGr_MC.D1/IN6 ),
    .I7(\NlwInverterSignal_DCORIFGr_MC.D1/IN7 ),
    .I8(\NlwInverterSignal_DCORIFGr_MC.D1/IN8 ),
    .I9(\NlwInverterSignal_DCORIFGr_MC.D1/IN9 ),
    .I10(Vcc),
    .I11(Vcc),
    .I12(Vcc),
    .I13(Vcc),
    .I14(Vcc),
    .I15(Vcc),
    .O(\DCORIFGr_MC.D1 )
  );
  X_ZERO \DCORIFGr_MC.D2_874  (
    .O(\DCORIFGr_MC.D2 )
  );
  X_BUF \outDATA<0>\$WA6.UIM_875  (
    .I(\outDATA<0>\$WA6.UIM_MC.Q ),
    .O(\outDATA<0>\$WA6.UIM )
  );
  X_BUF \outDATA<0>\$WA6.UIM_MC.Q_876  (
    .I(\outDATA<0>\$WA6.UIM_MC.D ),
    .O(\outDATA<0>\$WA6.UIM_MC.Q )
  );
  X_XOR2 \outDATA<0>\$WA6.UIM_MC.D_877  (
    .I0(\outDATA<0>\$WA6.UIM_MC.D1 ),
    .I1(\outDATA<0>\$WA6.UIM_MC.D2 ),
    .O(\outDATA<0>\$WA6.UIM_MC.D )
  );
  X_AND2 \outDATA<0>\$WA6.UIM_MC.D1_878  (
    .I0(\INTbus_II/UIM ),
    .I1(\INTbus_II/UIM ),
    .O(\outDATA<0>\$WA6.UIM_MC.D1 )
  );
  X_ZERO \outDATA<0>\$WA6.UIM_MC.D2_879  (
    .O(\outDATA<0>\$WA6.UIM_MC.D2 )
  );
  X_BUF \outDATA<0>\$WA4.UIM_880  (
    .I(\outDATA<0>\$WA4.UIM_MC.Q ),
    .O(\outDATA<0>\$WA4.UIM )
  );
  X_BUF \outDATA<0>\$WA4.UIM_MC.Q_881  (
    .I(\outDATA<0>\$WA4.UIM_MC.D ),
    .O(\outDATA<0>\$WA4.UIM_MC.Q )
  );
  X_XOR2 \outDATA<0>\$WA4.UIM_MC.D_882  (
    .I0(\outDATA<0>\$WA4.UIM_MC.D1 ),
    .I1(\outDATA<0>\$WA4.UIM_MC.D2 ),
    .O(\outDATA<0>\$WA4.UIM_MC.D )
  );
  X_ZERO \outDATA<0>\$WA4.UIM_MC.D1_883  (
    .O(\outDATA<0>\$WA4.UIM_MC.D1 )
  );
  X_AND2 \outDATA<0>\$WA4.UIM_MC.D2_PT_0_884  (
    .I0(\NlwInverterSignal_outDATA<0>\$WA4.UIM_MC.D2_PT_0/IN0 ),
    .I1(DCORLIMITSr),
    .O(\outDATA<0>\$WA4.UIM_MC.D2_PT_0 )
  );
  X_AND2 \outDATA<0>\$WA4.UIM_MC.D2_PT_1_885  (
    .I0(\NlwInverterSignal_outDATA<0>\$WA4.UIM_MC.D2_PT_1/IN0 ),
    .I1(\U5/RLS0fr ),
    .O(\outDATA<0>\$WA4.UIM_MC.D2_PT_1 )
  );
  X_OR2 \outDATA<0>\$WA4.UIM_MC.D2_886  (
    .I0(\outDATA<0>\$WA4.UIM_MC.D2_PT_0 ),
    .I1(\outDATA<0>\$WA4.UIM_MC.D2_PT_1 ),
    .O(\outDATA<0>\$WA4.UIM_MC.D2 )
  );
  X_BUF DCORLIMITSr_887 (
    .I(\DCORLIMITSr_MC.Q ),
    .O(DCORLIMITSr)
  );
  X_BUF \DCORLIMITSr_MC.Q_888  (
    .I(\DCORLIMITSr_MC.D ),
    .O(\DCORLIMITSr_MC.Q )
  );
  X_XOR2 \DCORLIMITSr_MC.D_889  (
    .I0(\DCORLIMITSr_MC.D1 ),
    .I1(\DCORLIMITSr_MC.D2 ),
    .O(\DCORLIMITSr_MC.D )
  );
  X_AND16 \DCORLIMITSr_MC.D1_890  (
    .I0(\WR_II/UIM ),
    .I1(\NlwInverterSignal_DCORLIMITSr_MC.D1/IN1 ),
    .I2(U2_ADDR_reg[0]),
    .I3(\NlwInverterSignal_DCORLIMITSr_MC.D1/IN3 ),
    .I4(\NlwInverterSignal_DCORLIMITSr_MC.D1/IN4 ),
    .I5(\NlwInverterSignal_DCORLIMITSr_MC.D1/IN5 ),
    .I6(\NlwInverterSignal_DCORLIMITSr_MC.D1/IN6 ),
    .I7(\NlwInverterSignal_DCORLIMITSr_MC.D1/IN7 ),
    .I8(U2_ADDR_reg[1]),
    .I9(\NlwInverterSignal_DCORLIMITSr_MC.D1/IN9 ),
    .I10(Vcc),
    .I11(Vcc),
    .I12(Vcc),
    .I13(Vcc),
    .I14(Vcc),
    .I15(Vcc),
    .O(\DCORLIMITSr_MC.D1 )
  );
  X_ZERO \DCORLIMITSr_MC.D2_891  (
    .O(\DCORLIMITSr_MC.D2 )
  );
  X_BUF \U5/RLS0fr_892  (
    .I(\U5/RLS0fr_MC.Q ),
    .O(\U5/RLS0fr )
  );
  X_FF \U5/RLS0fr_MC.REG  (
    .I(\U5/RLS0fr_MC.D ),
    .CE(Vcc),
    .CLK(\U5/RLS0fr_MC.REG_tsimcreated_inv_Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\U5/RLS0fr_MC.Q )
  );
  X_INV \U5/RLS0fr_MC.REG_tsimcreated_inv_Mclk_II/FCLK_893  (
    .I(\Mclk_II/FCLK ),
    .O(\U5/RLS0fr_MC.REG_tsimcreated_inv_Mclk_II/FCLK )
  );
  X_XOR2 \U5/RLS0fr_MC.D_894  (
    .I0(\U5/RLS0fr_MC.D1 ),
    .I1(\U5/RLS0fr_MC.D2 ),
    .O(\U5/RLS0fr_MC.D )
  );
  X_ZERO \U5/RLS0fr_MC.D1_895  (
    .O(\U5/RLS0fr_MC.D1 )
  );
  X_AND3 \U5/RLS0fr_MC.D2_PT_0_896  (
    .I0(\MSPReset_II/UIM ),
    .I1(\U5/RLS0fr ),
    .I2(\NlwInverterSignal_U5/RLS0fr_MC.D2_PT_0/IN2 ),
    .O(\U5/RLS0fr_MC.D2_PT_0 )
  );
  X_AND5 \U5/RLS0fr_MC.D2_PT_1_897  (
    .I0(\MSPReset_II/UIM ),
    .I1(\NlwInverterSignal_U5/RLS0fr_MC.D2_PT_1/IN1 ),
    .I2(\NlwInverterSignal_U5/RLS0fr_MC.D2_PT_1/IN2 ),
    .I3(\NlwInverterSignal_U5/RLS0fr_MC.D2_PT_1/IN3 ),
    .I4(\U5/RLS0r ),
    .O(\U5/RLS0fr_MC.D2_PT_1 )
  );
  X_OR2 \U5/RLS0fr_MC.D2_898  (
    .I0(\U5/RLS0fr_MC.D2_PT_0 ),
    .I1(\U5/RLS0fr_MC.D2_PT_1 ),
    .O(\U5/RLS0fr_MC.D2 )
  );
  X_BUF DCORLINTr_899 (
    .I(\DCORLINTr_MC.Q ),
    .O(DCORLINTr)
  );
  X_BUF \DCORLINTr_MC.Q_900  (
    .I(\DCORLINTr_MC.D ),
    .O(\DCORLINTr_MC.Q )
  );
  X_XOR2 \DCORLINTr_MC.D_901  (
    .I0(\DCORLINTr_MC.D1 ),
    .I1(\DCORLINTr_MC.D2 ),
    .O(\DCORLINTr_MC.D )
  );
  X_AND16 \DCORLINTr_MC.D1_902  (
    .I0(\WR_II/UIM ),
    .I1(\NlwInverterSignal_DCORLINTr_MC.D1/IN1 ),
    .I2(\NlwInverterSignal_DCORLINTr_MC.D1/IN2 ),
    .I3(\NlwInverterSignal_DCORLINTr_MC.D1/IN3 ),
    .I4(\NlwInverterSignal_DCORLINTr_MC.D1/IN4 ),
    .I5(\NlwInverterSignal_DCORLINTr_MC.D1/IN5 ),
    .I6(\NlwInverterSignal_DCORLINTr_MC.D1/IN6 ),
    .I7(\NlwInverterSignal_DCORLINTr_MC.D1/IN7 ),
    .I8(U2_ADDR_reg[1]),
    .I9(\NlwInverterSignal_DCORLINTr_MC.D1/IN9 ),
    .I10(Vcc),
    .I11(Vcc),
    .I12(Vcc),
    .I13(Vcc),
    .I14(Vcc),
    .I15(Vcc),
    .O(\DCORLINTr_MC.D1 )
  );
  X_ZERO \DCORLINTr_MC.D2_903  (
    .O(\DCORLINTr_MC.D2 )
  );
  X_BUF \U5/RLS0r_904  (
    .I(\U5/RLS0r_MC.Q ),
    .O(\U5/RLS0r )
  );
  X_FF \U5/RLS0r_MC.REG  (
    .I(\U5/RLS0r_MC.D ),
    .CE(Vcc),
    .CLK(\U5/RLS0r_MC.REG_tsimcreated_inv_Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\U5/RLS0r_MC.Q )
  );
  X_INV \U5/RLS0r_MC.REG_tsimcreated_inv_Mclk_II/FCLK_905  (
    .I(\Mclk_II/FCLK ),
    .O(\U5/RLS0r_MC.REG_tsimcreated_inv_Mclk_II/FCLK )
  );
  X_XOR2 \U5/RLS0r_MC.D_906  (
    .I0(\U5/RLS0r_MC.D1 ),
    .I1(\U5/RLS0r_MC.D2 ),
    .O(\U5/RLS0r_MC.D )
  );
  X_AND2 \U5/RLS0r_MC.D1_907  (
    .I0(\MSPReset_II/UIM ),
    .I1(\RLS0_II/UIM ),
    .O(\U5/RLS0r_MC.D1 )
  );
  X_ZERO \U5/RLS0r_MC.D2_908  (
    .O(\U5/RLS0r_MC.D2 )
  );
  X_BUF N_PZ_1016_909 (
    .I(\N_PZ_1016_MC.Q ),
    .O(N_PZ_1016)
  );
  X_BUF \N_PZ_1016_MC.Q_910  (
    .I(\N_PZ_1016_MC.D ),
    .O(\N_PZ_1016_MC.Q )
  );
  X_XOR2 \N_PZ_1016_MC.D_911  (
    .I0(\N_PZ_1016_MC.D1 ),
    .I1(\N_PZ_1016_MC.D2 ),
    .O(\N_PZ_1016_MC.D )
  );
  X_AND2 \N_PZ_1016_MC.D1_912  (
    .I0(\NlwInverterSignal_N_PZ_1016_MC.D1/IN0 ),
    .I1(\NlwInverterSignal_N_PZ_1016_MC.D1/IN1 ),
    .O(\N_PZ_1016_MC.D1 )
  );
  X_ZERO \N_PZ_1016_MC.D2_913  (
    .O(\N_PZ_1016_MC.D2 )
  );
  X_BUF \outDATA<0>\$WA1.UIM_914  (
    .I(\outDATA<0>\$WA1.UIM_MC.Q ),
    .O(\outDATA<0>\$WA1.UIM )
  );
  X_BUF \outDATA<0>\$WA1.UIM_MC.Q_915  (
    .I(\outDATA<0>\$WA1.UIM_MC.D ),
    .O(\outDATA<0>\$WA1.UIM_MC.Q )
  );
  X_XOR2 \outDATA<0>\$WA1.UIM_MC.D_916  (
    .I0(\outDATA<0>\$WA1.UIM_MC.D1 ),
    .I1(\outDATA<0>\$WA1.UIM_MC.D2 ),
    .O(\outDATA<0>\$WA1.UIM_MC.D )
  );
  X_ZERO \outDATA<0>\$WA1.UIM_MC.D1_917  (
    .O(\outDATA<0>\$WA1.UIM_MC.D1 )
  );
  X_AND2 \outDATA<0>\$WA1.UIM_MC.D2_PT_0_918  (
    .I0(\U1/U3/holdingreg0 [0]),
    .I1(DCOR0CNTLOWr),
    .O(\outDATA<0>\$WA1.UIM_MC.D2_PT_0 )
  );
  X_AND3 \outDATA<0>\$WA1.UIM_MC.D2_PT_1_919  (
    .I0(\NlwInverterSignal_outDATA<0>\$WA1.UIM_MC.D2_PT_1/IN0 ),
    .I1(\U1/U3/holdingreg1 [0]),
    .I2(DCOR1CNTLOWr),
    .O(\outDATA<0>\$WA1.UIM_MC.D2_PT_1 )
  );
  X_AND4 \outDATA<0>\$WA1.UIM_MC.D2_PT_2_920  (
    .I0(\NlwInverterSignal_outDATA<0>\$WA1.UIM_MC.D2_PT_2/IN0 ),
    .I1(\NlwInverterSignal_outDATA<0>\$WA1.UIM_MC.D2_PT_2/IN1 ),
    .I2(\U1/U3/holdingreg0 [8]),
    .I3(DCOR0CNTHIGHr),
    .O(\outDATA<0>\$WA1.UIM_MC.D2_PT_2 )
  );
  X_AND4 \outDATA<0>\$WA1.UIM_MC.D2_PT_3_921  (
    .I0(\NlwInverterSignal_outDATA<0>\$WA1.UIM_MC.D2_PT_3/IN0 ),
    .I1(\NlwInverterSignal_outDATA<0>\$WA1.UIM_MC.D2_PT_3/IN1 ),
    .I2(\NlwInverterSignal_outDATA<0>\$WA1.UIM_MC.D2_PT_3/IN2 ),
    .I3(\U1/U3/holdingreg1 [8]),
    .O(\outDATA<0>\$WA1.UIM_MC.D2_PT_3 )
  );
  X_OR4 \outDATA<0>\$WA1.UIM_MC.D2_922  (
    .I0(\outDATA<0>\$WA1.UIM_MC.D2_PT_0 ),
    .I1(\outDATA<0>\$WA1.UIM_MC.D2_PT_1 ),
    .I2(\outDATA<0>\$WA1.UIM_MC.D2_PT_2 ),
    .I3(\outDATA<0>\$WA1.UIM_MC.D2_PT_3 ),
    .O(\outDATA<0>\$WA1.UIM_MC.D2 )
  );
  X_BUF \U1/U3/holdingreg0<0>  (
    .I(\U1/U3/holdingreg0<0>_MC.Q ),
    .O(\U1/U3/holdingreg0 [0])
  );
  X_FF \U1/U3/holdingreg0<0>_MC.REG  (
    .I(\U1/U3/holdingreg0<0>_MC.D ),
    .CE(Vcc),
    .CLK(\U1/U3/holdingreg0<0>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\U1/U3/holdingreg0<0>_MC.Q )
  );
  X_INV \U1/U3/holdingreg0<0>_MC.REG_tsimcreated_inv_Mclk_II/FCLK_923  (
    .I(\Mclk_II/FCLK ),
    .O(\U1/U3/holdingreg0<0>_MC.REG_tsimcreated_inv_Mclk_II/FCLK )
  );
  X_XOR2 \U1/U3/holdingreg0<0>_MC.D_924  (
    .I0(\U1/U3/holdingreg0<0>_MC.D1 ),
    .I1(\U1/U3/holdingreg0<0>_MC.D2 ),
    .O(\U1/U3/holdingreg0<0>_MC.D )
  );
  X_ZERO \U1/U3/holdingreg0<0>_MC.D1_925  (
    .O(\U1/U3/holdingreg0<0>_MC.D1 )
  );
  X_AND2 \U1/U3/holdingreg0<0>_MC.D2_PT_0_926  (
    .I0(N_PZ_992),
    .I1(\U1/U3/holdingreg0 [0]),
    .O(\U1/U3/holdingreg0<0>_MC.D2_PT_0 )
  );
  X_AND4 \U1/U3/holdingreg0<0>_MC.D2_PT_1_927  (
    .I0(\MSPReset_II/UIM ),
    .I1(\NlwInverterSignal_U1/U3/holdingreg0<0>_MC.D2_PT_1/IN1 ),
    .I2(U2_ASedge),
    .I3(\U1/Channel0 [0]),
    .O(\U1/U3/holdingreg0<0>_MC.D2_PT_1 )
  );
  X_OR2 \U1/U3/holdingreg0<0>_MC.D2_928  (
    .I0(\U1/U3/holdingreg0<0>_MC.D2_PT_0 ),
    .I1(\U1/U3/holdingreg0<0>_MC.D2_PT_1 ),
    .O(\U1/U3/holdingreg0<0>_MC.D2 )
  );
  X_BUF DCOR0CNTLOWr_929 (
    .I(\DCOR0CNTLOWr_MC.Q ),
    .O(DCOR0CNTLOWr)
  );
  X_BUF \DCOR0CNTLOWr_MC.Q_930  (
    .I(\DCOR0CNTLOWr_MC.D ),
    .O(\DCOR0CNTLOWr_MC.Q )
  );
  X_XOR2 \DCOR0CNTLOWr_MC.D_931  (
    .I0(\DCOR0CNTLOWr_MC.D1 ),
    .I1(\DCOR0CNTLOWr_MC.D2 ),
    .O(\DCOR0CNTLOWr_MC.D )
  );
  X_AND16 \DCOR0CNTLOWr_MC.D1_932  (
    .I0(\WR_II/UIM ),
    .I1(\NlwInverterSignal_DCOR0CNTLOWr_MC.D1/IN1 ),
    .I2(\NlwInverterSignal_DCOR0CNTLOWr_MC.D1/IN2 ),
    .I3(\NlwInverterSignal_DCOR0CNTLOWr_MC.D1/IN3 ),
    .I4(\NlwInverterSignal_DCOR0CNTLOWr_MC.D1/IN4 ),
    .I5(\NlwInverterSignal_DCOR0CNTLOWr_MC.D1/IN5 ),
    .I6(\NlwInverterSignal_DCOR0CNTLOWr_MC.D1/IN6 ),
    .I7(\NlwInverterSignal_DCOR0CNTLOWr_MC.D1/IN7 ),
    .I8(\NlwInverterSignal_DCOR0CNTLOWr_MC.D1/IN8 ),
    .I9(U2_ADDR_reg[2]),
    .I10(Vcc),
    .I11(Vcc),
    .I12(Vcc),
    .I13(Vcc),
    .I14(Vcc),
    .I15(Vcc),
    .O(\DCOR0CNTLOWr_MC.D1 )
  );
  X_ZERO \DCOR0CNTLOWr_MC.D2_933  (
    .O(\DCOR0CNTLOWr_MC.D2 )
  );
  X_BUF \U1/U3/holdingreg1<0>  (
    .I(\U1/U3/holdingreg1<0>_MC.Q ),
    .O(\U1/U3/holdingreg1 [0])
  );
  X_FF \U1/U3/holdingreg1<0>_MC.REG  (
    .I(\U1/U3/holdingreg1<0>_MC.D ),
    .CE(Vcc),
    .CLK(\U1/U3/holdingreg1<0>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\U1/U3/holdingreg1<0>_MC.Q )
  );
  X_INV \U1/U3/holdingreg1<0>_MC.REG_tsimcreated_inv_Mclk_II/FCLK_934  (
    .I(\Mclk_II/FCLK ),
    .O(\U1/U3/holdingreg1<0>_MC.REG_tsimcreated_inv_Mclk_II/FCLK )
  );
  X_XOR2 \U1/U3/holdingreg1<0>_MC.D_935  (
    .I0(\U1/U3/holdingreg1<0>_MC.D1 ),
    .I1(\U1/U3/holdingreg1<0>_MC.D2 ),
    .O(\U1/U3/holdingreg1<0>_MC.D )
  );
  X_ZERO \U1/U3/holdingreg1<0>_MC.D1_936  (
    .O(\U1/U3/holdingreg1<0>_MC.D1 )
  );
  X_AND2 \U1/U3/holdingreg1<0>_MC.D2_PT_0_937  (
    .I0(N_PZ_992),
    .I1(\U1/U3/holdingreg1 [0]),
    .O(\U1/U3/holdingreg1<0>_MC.D2_PT_0 )
  );
  X_AND4 \U1/U3/holdingreg1<0>_MC.D2_PT_1_938  (
    .I0(\MSPReset_II/UIM ),
    .I1(\NlwInverterSignal_U1/U3/holdingreg1<0>_MC.D2_PT_1/IN1 ),
    .I2(U2_ASedge),
    .I3(\U1/Channel1 [0]),
    .O(\U1/U3/holdingreg1<0>_MC.D2_PT_1 )
  );
  X_OR2 \U1/U3/holdingreg1<0>_MC.D2_939  (
    .I0(\U1/U3/holdingreg1<0>_MC.D2_PT_0 ),
    .I1(\U1/U3/holdingreg1<0>_MC.D2_PT_1 ),
    .O(\U1/U3/holdingreg1<0>_MC.D2 )
  );
  X_BUF DCOR1CNTLOWr_940 (
    .I(\DCOR1CNTLOWr_MC.Q ),
    .O(DCOR1CNTLOWr)
  );
  X_BUF \DCOR1CNTLOWr_MC.Q_941  (
    .I(\DCOR1CNTLOWr_MC.D ),
    .O(\DCOR1CNTLOWr_MC.Q )
  );
  X_XOR2 \DCOR1CNTLOWr_MC.D_942  (
    .I0(\DCOR1CNTLOWr_MC.D1 ),
    .I1(\DCOR1CNTLOWr_MC.D2 ),
    .O(\DCOR1CNTLOWr_MC.D )
  );
  X_AND16 \DCOR1CNTLOWr_MC.D1_943  (
    .I0(\WR_II/UIM ),
    .I1(\NlwInverterSignal_DCOR1CNTLOWr_MC.D1/IN1 ),
    .I2(\NlwInverterSignal_DCOR1CNTLOWr_MC.D1/IN2 ),
    .I3(\NlwInverterSignal_DCOR1CNTLOWr_MC.D1/IN3 ),
    .I4(\NlwInverterSignal_DCOR1CNTLOWr_MC.D1/IN4 ),
    .I5(\NlwInverterSignal_DCOR1CNTLOWr_MC.D1/IN5 ),
    .I6(\NlwInverterSignal_DCOR1CNTLOWr_MC.D1/IN6 ),
    .I7(\NlwInverterSignal_DCOR1CNTLOWr_MC.D1/IN7 ),
    .I8(U2_ADDR_reg[1]),
    .I9(U2_ADDR_reg[2]),
    .I10(Vcc),
    .I11(Vcc),
    .I12(Vcc),
    .I13(Vcc),
    .I14(Vcc),
    .I15(Vcc),
    .O(\DCOR1CNTLOWr_MC.D1 )
  );
  X_ZERO \DCOR1CNTLOWr_MC.D2_944  (
    .O(\DCOR1CNTLOWr_MC.D2 )
  );
  X_BUF \U1/U3/holdingreg0<8>  (
    .I(\U1/U3/holdingreg0<8>_MC.Q ),
    .O(\U1/U3/holdingreg0 [8])
  );
  X_FF \U1/U3/holdingreg0<8>_MC.REG  (
    .I(\U1/U3/holdingreg0<8>_MC.D ),
    .CE(Vcc),
    .CLK(\U1/U3/holdingreg0<8>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\U1/U3/holdingreg0<8>_MC.Q )
  );
  X_INV \U1/U3/holdingreg0<8>_MC.REG_tsimcreated_inv_Mclk_II/FCLK_945  (
    .I(\Mclk_II/FCLK ),
    .O(\U1/U3/holdingreg0<8>_MC.REG_tsimcreated_inv_Mclk_II/FCLK )
  );
  X_XOR2 \U1/U3/holdingreg0<8>_MC.D_946  (
    .I0(\U1/U3/holdingreg0<8>_MC.D1 ),
    .I1(\U1/U3/holdingreg0<8>_MC.D2 ),
    .O(\U1/U3/holdingreg0<8>_MC.D )
  );
  X_ZERO \U1/U3/holdingreg0<8>_MC.D1_947  (
    .O(\U1/U3/holdingreg0<8>_MC.D1 )
  );
  X_AND2 \U1/U3/holdingreg0<8>_MC.D2_PT_0_948  (
    .I0(N_PZ_992),
    .I1(\U1/U3/holdingreg0 [8]),
    .O(\U1/U3/holdingreg0<8>_MC.D2_PT_0 )
  );
  X_AND4 \U1/U3/holdingreg0<8>_MC.D2_PT_1_949  (
    .I0(\MSPReset_II/UIM ),
    .I1(\NlwInverterSignal_U1/U3/holdingreg0<8>_MC.D2_PT_1/IN1 ),
    .I2(U2_ASedge),
    .I3(\U1/Channel0 [8]),
    .O(\U1/U3/holdingreg0<8>_MC.D2_PT_1 )
  );
  X_OR2 \U1/U3/holdingreg0<8>_MC.D2_950  (
    .I0(\U1/U3/holdingreg0<8>_MC.D2_PT_0 ),
    .I1(\U1/U3/holdingreg0<8>_MC.D2_PT_1 ),
    .O(\U1/U3/holdingreg0<8>_MC.D2 )
  );
  X_BUF DCOR0CNTHIGHr_951 (
    .I(\DCOR0CNTHIGHr_MC.Q ),
    .O(DCOR0CNTHIGHr)
  );
  X_BUF \DCOR0CNTHIGHr_MC.Q_952  (
    .I(\DCOR0CNTHIGHr_MC.D ),
    .O(\DCOR0CNTHIGHr_MC.Q )
  );
  X_XOR2 \DCOR0CNTHIGHr_MC.D_953  (
    .I0(\DCOR0CNTHIGHr_MC.D1 ),
    .I1(\DCOR0CNTHIGHr_MC.D2 ),
    .O(\DCOR0CNTHIGHr_MC.D )
  );
  X_AND16 \DCOR0CNTHIGHr_MC.D1_954  (
    .I0(\WR_II/UIM ),
    .I1(\NlwInverterSignal_DCOR0CNTHIGHr_MC.D1/IN1 ),
    .I2(U2_ADDR_reg[0]),
    .I3(\NlwInverterSignal_DCOR0CNTHIGHr_MC.D1/IN3 ),
    .I4(\NlwInverterSignal_DCOR0CNTHIGHr_MC.D1/IN4 ),
    .I5(\NlwInverterSignal_DCOR0CNTHIGHr_MC.D1/IN5 ),
    .I6(\NlwInverterSignal_DCOR0CNTHIGHr_MC.D1/IN6 ),
    .I7(\NlwInverterSignal_DCOR0CNTHIGHr_MC.D1/IN7 ),
    .I8(\NlwInverterSignal_DCOR0CNTHIGHr_MC.D1/IN8 ),
    .I9(U2_ADDR_reg[2]),
    .I10(Vcc),
    .I11(Vcc),
    .I12(Vcc),
    .I13(Vcc),
    .I14(Vcc),
    .I15(Vcc),
    .O(\DCOR0CNTHIGHr_MC.D1 )
  );
  X_ZERO \DCOR0CNTHIGHr_MC.D2_955  (
    .O(\DCOR0CNTHIGHr_MC.D2 )
  );
  X_BUF \U1/U3/holdingreg1<8>  (
    .I(\U1/U3/holdingreg1<8>_MC.Q ),
    .O(\U1/U3/holdingreg1 [8])
  );
  X_FF \U1/U3/holdingreg1<8>_MC.REG  (
    .I(\U1/U3/holdingreg1<8>_MC.D ),
    .CE(Vcc),
    .CLK(\U1/U3/holdingreg1<8>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\U1/U3/holdingreg1<8>_MC.Q )
  );
  X_INV \U1/U3/holdingreg1<8>_MC.REG_tsimcreated_inv_Mclk_II/FCLK_956  (
    .I(\Mclk_II/FCLK ),
    .O(\U1/U3/holdingreg1<8>_MC.REG_tsimcreated_inv_Mclk_II/FCLK )
  );
  X_XOR2 \U1/U3/holdingreg1<8>_MC.D_957  (
    .I0(\U1/U3/holdingreg1<8>_MC.D1 ),
    .I1(\U1/U3/holdingreg1<8>_MC.D2 ),
    .O(\U1/U3/holdingreg1<8>_MC.D )
  );
  X_ZERO \U1/U3/holdingreg1<8>_MC.D1_958  (
    .O(\U1/U3/holdingreg1<8>_MC.D1 )
  );
  X_AND2 \U1/U3/holdingreg1<8>_MC.D2_PT_0_959  (
    .I0(N_PZ_992),
    .I1(\U1/U3/holdingreg1 [8]),
    .O(\U1/U3/holdingreg1<8>_MC.D2_PT_0 )
  );
  X_AND4 \U1/U3/holdingreg1<8>_MC.D2_PT_1_960  (
    .I0(\MSPReset_II/UIM ),
    .I1(\NlwInverterSignal_U1/U3/holdingreg1<8>_MC.D2_PT_1/IN1 ),
    .I2(U2_ASedge),
    .I3(\U1/Channel1 [8]),
    .O(\U1/U3/holdingreg1<8>_MC.D2_PT_1 )
  );
  X_OR2 \U1/U3/holdingreg1<8>_MC.D2_961  (
    .I0(\U1/U3/holdingreg1<8>_MC.D2_PT_0 ),
    .I1(\U1/U3/holdingreg1<8>_MC.D2_PT_1 ),
    .O(\U1/U3/holdingreg1<8>_MC.D2 )
  );
  X_BUF N_PZ_1017_962 (
    .I(\N_PZ_1017_MC.Q ),
    .O(N_PZ_1017)
  );
  X_BUF \N_PZ_1017_MC.Q_963  (
    .I(\N_PZ_1017_MC.D ),
    .O(\N_PZ_1017_MC.Q )
  );
  X_XOR2 \N_PZ_1017_MC.D_964  (
    .I0(\N_PZ_1017_MC.D1 ),
    .I1(\N_PZ_1017_MC.D2 ),
    .O(\N_PZ_1017_MC.D )
  );
  X_AND4 \N_PZ_1017_MC.D1_965  (
    .I0(\NlwInverterSignal_N_PZ_1017_MC.D1/IN0 ),
    .I1(\NlwInverterSignal_N_PZ_1017_MC.D1/IN1 ),
    .I2(\NlwInverterSignal_N_PZ_1017_MC.D1/IN2 ),
    .I3(\NlwInverterSignal_N_PZ_1017_MC.D1/IN3 ),
    .O(\N_PZ_1017_MC.D1 )
  );
  X_ZERO \N_PZ_1017_MC.D2_966  (
    .O(\N_PZ_1017_MC.D2 )
  );
  X_BUF DCOR1CNTHIGHr_967 (
    .I(\DCOR1CNTHIGHr_MC.Q ),
    .O(DCOR1CNTHIGHr)
  );
  X_BUF \DCOR1CNTHIGHr_MC.Q_968  (
    .I(\DCOR1CNTHIGHr_MC.D ),
    .O(\DCOR1CNTHIGHr_MC.Q )
  );
  X_XOR2 \DCOR1CNTHIGHr_MC.D_969  (
    .I0(\DCOR1CNTHIGHr_MC.D1 ),
    .I1(\DCOR1CNTHIGHr_MC.D2 ),
    .O(\DCOR1CNTHIGHr_MC.D )
  );
  X_AND16 \DCOR1CNTHIGHr_MC.D1_970  (
    .I0(\WR_II/UIM ),
    .I1(\NlwInverterSignal_DCOR1CNTHIGHr_MC.D1/IN1 ),
    .I2(U2_ADDR_reg[0]),
    .I3(\NlwInverterSignal_DCOR1CNTHIGHr_MC.D1/IN3 ),
    .I4(\NlwInverterSignal_DCOR1CNTHIGHr_MC.D1/IN4 ),
    .I5(\NlwInverterSignal_DCOR1CNTHIGHr_MC.D1/IN5 ),
    .I6(\NlwInverterSignal_DCOR1CNTHIGHr_MC.D1/IN6 ),
    .I7(\NlwInverterSignal_DCOR1CNTHIGHr_MC.D1/IN7 ),
    .I8(U2_ADDR_reg[1]),
    .I9(U2_ADDR_reg[2]),
    .I10(Vcc),
    .I11(Vcc),
    .I12(Vcc),
    .I13(Vcc),
    .I14(Vcc),
    .I15(Vcc),
    .O(\DCOR1CNTHIGHr_MC.D1 )
  );
  X_ZERO \DCOR1CNTHIGHr_MC.D2_971  (
    .O(\DCOR1CNTHIGHr_MC.D2 )
  );
  X_BUF N_PZ_1053_972 (
    .I(\N_PZ_1053_MC.Q ),
    .O(N_PZ_1053)
  );
  X_BUF \N_PZ_1053_MC.Q_973  (
    .I(\N_PZ_1053_MC.D ),
    .O(\N_PZ_1053_MC.Q )
  );
  X_XOR2 \N_PZ_1053_MC.D_974  (
    .I0(\N_PZ_1053_MC.D1 ),
    .I1(\N_PZ_1053_MC.D2 ),
    .O(\N_PZ_1053_MC.D )
  );
  X_AND5 \N_PZ_1053_MC.D1_975  (
    .I0(\NlwInverterSignal_N_PZ_1053_MC.D1/IN0 ),
    .I1(\NlwInverterSignal_N_PZ_1053_MC.D1/IN1 ),
    .I2(\NlwInverterSignal_N_PZ_1053_MC.D1/IN2 ),
    .I3(\NlwInverterSignal_N_PZ_1053_MC.D1/IN3 ),
    .I4(\NlwInverterSignal_N_PZ_1053_MC.D1/IN4 ),
    .O(\N_PZ_1053_MC.D1 )
  );
  X_ZERO \N_PZ_1053_MC.D2_976  (
    .O(\N_PZ_1053_MC.D2 )
  );
  X_BUF DCOR1THRESHIGHr_977 (
    .I(\DCOR1THRESHIGHr_MC.Q ),
    .O(DCOR1THRESHIGHr)
  );
  X_BUF \DCOR1THRESHIGHr_MC.Q_978  (
    .I(\DCOR1THRESHIGHr_MC.D ),
    .O(\DCOR1THRESHIGHr_MC.Q )
  );
  X_XOR2 \DCOR1THRESHIGHr_MC.D_979  (
    .I0(\DCOR1THRESHIGHr_MC.D1 ),
    .I1(\DCOR1THRESHIGHr_MC.D2 ),
    .O(\DCOR1THRESHIGHr_MC.D )
  );
  X_AND16 \DCOR1THRESHIGHr_MC.D1_980  (
    .I0(\WR_II/UIM ),
    .I1(\NlwInverterSignal_DCOR1THRESHIGHr_MC.D1/IN1 ),
    .I2(U2_ADDR_reg[0]),
    .I3(\NlwInverterSignal_DCOR1THRESHIGHr_MC.D1/IN3 ),
    .I4(\NlwInverterSignal_DCOR1THRESHIGHr_MC.D1/IN4 ),
    .I5(\NlwInverterSignal_DCOR1THRESHIGHr_MC.D1/IN5 ),
    .I6(\NlwInverterSignal_DCOR1THRESHIGHr_MC.D1/IN6 ),
    .I7(U2_ADDR_reg[3]),
    .I8(U2_ADDR_reg[1]),
    .I9(\NlwInverterSignal_DCOR1THRESHIGHr_MC.D1/IN9 ),
    .I10(Vcc),
    .I11(Vcc),
    .I12(Vcc),
    .I13(Vcc),
    .I14(Vcc),
    .I15(Vcc),
    .O(\DCOR1THRESHIGHr_MC.D1 )
  );
  X_ZERO \DCOR1THRESHIGHr_MC.D2_981  (
    .O(\DCOR1THRESHIGHr_MC.D2 )
  );
  X_BUF U2_Enable_AD_982 (
    .I(\U2_Enable_AD_MC.Q ),
    .O(U2_Enable_AD)
  );
  X_BUF \U2_Enable_AD_MC.Q_983  (
    .I(\U2_Enable_AD_MC.D ),
    .O(\U2_Enable_AD_MC.Q )
  );
  X_XOR2 \U2_Enable_AD_MC.D_984  (
    .I0(\U2_Enable_AD_MC.D1 ),
    .I1(\U2_Enable_AD_MC.D2 ),
    .O(\U2_Enable_AD_MC.D )
  );
  X_AND6 \U2_Enable_AD_MC.D1_985  (
    .I0(\WR_II/UIM ),
    .I1(\NlwInverterSignal_U2_Enable_AD_MC.D1/IN1 ),
    .I2(\NlwInverterSignal_U2_Enable_AD_MC.D1/IN2 ),
    .I3(\NlwInverterSignal_U2_Enable_AD_MC.D1/IN3 ),
    .I4(\NlwInverterSignal_U2_Enable_AD_MC.D1/IN4 ),
    .I5(\NlwInverterSignal_U2_Enable_AD_MC.D1/IN5 ),
    .O(\U2_Enable_AD_MC.D1 )
  );
  X_ZERO \U2_Enable_AD_MC.D2_986  (
    .O(\U2_Enable_AD_MC.D2 )
  );
  X_BUF \AD<1>_MC.Q_987  (
    .I(\AD<1>_MC.Q_tsimrenamed_net_ ),
    .O(\AD<1>_MC.Q )
  );
  X_BUF \AD<1>_MC.OE_988  (
    .I(\AD<1>_MC.BUFOE.OUT ),
    .O(\AD<1>_MC.OE )
  );
  X_BUF \AD<1>_MC.BUFOE.OUT_989  (
    .I(\FOOBAR1__ctinst/7 ),
    .O(\AD<1>_MC.BUFOE.OUT )
  );
  X_BUF \AD<1>_MC.Q_tsimrenamed_net__990  (
    .I(\AD<1>_MC.D ),
    .O(\AD<1>_MC.Q_tsimrenamed_net_ )
  );
  X_XOR2 \AD<1>_MC.D_991  (
    .I0(\NlwInverterSignal_AD<1>_MC.D/IN0 ),
    .I1(\AD<1>_MC.D2 ),
    .O(\AD<1>_MC.D )
  );
  X_ZERO \AD<1>_MC.D1_992  (
    .O(\AD<1>_MC.D1 )
  );
  X_AND2 \AD<1>_MC.D2_PT_0_993  (
    .I0(DCORI2CCNTr),
    .I1(\NlwInverterSignal_AD<1>_MC.D2_PT_0/IN1 ),
    .O(\AD<1>_MC.D2_PT_0 )
  );
  X_AND2 \AD<1>_MC.D2_PT_1_994  (
    .I0(DCOR0THRESLOWr),
    .I1(\NlwInverterSignal_AD<1>_MC.D2_PT_1/IN1 ),
    .O(\AD<1>_MC.D2_PT_1 )
  );
  X_AND2 \AD<1>_MC.D2_PT_2_995  (
    .I0(DCORCONFIGr),
    .I1(\NlwInverterSignal_AD<1>_MC.D2_PT_2/IN1 ),
    .O(\AD<1>_MC.D2_PT_2 )
  );
  X_AND2 \AD<1>_MC.D2_PT_3_996  (
    .I0(DCORENCPWRr),
    .I1(\NlwInverterSignal_AD<1>_MC.D2_PT_3/IN1 ),
    .O(\AD<1>_MC.D2_PT_3 )
  );
  X_AND2 \AD<1>_MC.D2_PT_4_997  (
    .I0(DCORIFGr),
    .I1(\NlwInverterSignal_AD<1>_MC.D2_PT_4/IN1 ),
    .O(\AD<1>_MC.D2_PT_4 )
  );
  X_AND2 \AD<1>_MC.D2_PT_5_998  (
    .I0(\NlwInverterSignal_AD<1>_MC.D2_PT_5/IN0 ),
    .I1(\NlwInverterSignal_AD<1>_MC.D2_PT_5/IN1 ),
    .O(\AD<1>_MC.D2_PT_5 )
  );
  X_AND2 \AD<1>_MC.D2_PT_6_999  (
    .I0(\NlwInverterSignal_AD<1>_MC.D2_PT_6/IN0 ),
    .I1(\NlwInverterSignal_AD<1>_MC.D2_PT_6/IN1 ),
    .O(\AD<1>_MC.D2_PT_6 )
  );
  X_AND3 \AD<1>_MC.D2_PT_7_1000  (
    .I0(\NlwInverterSignal_AD<1>_MC.D2_PT_7/IN0 ),
    .I1(\NlwInverterSignal_AD<1>_MC.D2_PT_7/IN1 ),
    .I2(\NlwInverterSignal_AD<1>_MC.D2_PT_7/IN2 ),
    .O(\AD<1>_MC.D2_PT_7 )
  );
  X_OR8 \AD<1>_MC.D2_1001  (
    .I0(\AD<1>_MC.D2_PT_0 ),
    .I1(\AD<1>_MC.D2_PT_1 ),
    .I2(\AD<1>_MC.D2_PT_2 ),
    .I3(\AD<1>_MC.D2_PT_3 ),
    .I4(\AD<1>_MC.D2_PT_4 ),
    .I5(\AD<1>_MC.D2_PT_5 ),
    .I6(\AD<1>_MC.D2_PT_6 ),
    .I7(\AD<1>_MC.D2_PT_7 ),
    .O(\AD<1>_MC.D2 )
  );
  X_BUF \outDATA<1>\$WA0.UIM_1002  (
    .I(\outDATA<1>\$WA0.UIM_MC.Q ),
    .O(\outDATA<1>\$WA0.UIM )
  );
  X_BUF \outDATA<1>\$WA0.UIM_MC.Q_1003  (
    .I(\outDATA<1>\$WA0.UIM_MC.D ),
    .O(\outDATA<1>\$WA0.UIM_MC.Q )
  );
  X_XOR2 \outDATA<1>\$WA0.UIM_MC.D_1004  (
    .I0(\outDATA<1>\$WA0.UIM_MC.D1 ),
    .I1(\outDATA<1>\$WA0.UIM_MC.D2 ),
    .O(\outDATA<1>\$WA0.UIM_MC.D )
  );
  X_AND2 \outDATA<1>\$WA0.UIM_MC.D1_1005  (
    .I0(U11_U3_counterr[1]),
    .I1(U11_U3_counterr[1]),
    .O(\outDATA<1>\$WA0.UIM_MC.D1 )
  );
  X_ZERO \outDATA<1>\$WA0.UIM_MC.D2_1006  (
    .O(\outDATA<1>\$WA0.UIM_MC.D2 )
  );
  X_BUF \outDATA<1>\$WA2.UIM_1007  (
    .I(\outDATA<1>\$WA2.UIM_MC.Q ),
    .O(\outDATA<1>\$WA2.UIM )
  );
  X_BUF \outDATA<1>\$WA2.UIM_MC.Q_1008  (
    .I(\outDATA<1>\$WA2.UIM_MC.D ),
    .O(\outDATA<1>\$WA2.UIM_MC.Q )
  );
  X_XOR2 \outDATA<1>\$WA2.UIM_MC.D_1009  (
    .I0(\outDATA<1>\$WA2.UIM_MC.D1 ),
    .I1(\outDATA<1>\$WA2.UIM_MC.D2 ),
    .O(\outDATA<1>\$WA2.UIM_MC.D )
  );
  X_ZERO \outDATA<1>\$WA2.UIM_MC.D1_1010  (
    .O(\outDATA<1>\$WA2.UIM_MC.D1 )
  );
  X_AND2 \outDATA<1>\$WA2.UIM_MC.D2_PT_0_1011  (
    .I0(DCOR0THRESLOWr),
    .I1(\U1/U4/Latch0r [1]),
    .O(\outDATA<1>\$WA2.UIM_MC.D2_PT_0 )
  );
  X_AND3 \outDATA<1>\$WA2.UIM_MC.D2_PT_1_1012  (
    .I0(\NlwInverterSignal_outDATA<1>\$WA2.UIM_MC.D2_PT_1/IN0 ),
    .I1(DCOR0THRESHIGHr),
    .I2(\U1/U4/Latch0r [9]),
    .O(\outDATA<1>\$WA2.UIM_MC.D2_PT_1 )
  );
  X_AND4 \outDATA<1>\$WA2.UIM_MC.D2_PT_2_1013  (
    .I0(\NlwInverterSignal_outDATA<1>\$WA2.UIM_MC.D2_PT_2/IN0 ),
    .I1(\NlwInverterSignal_outDATA<1>\$WA2.UIM_MC.D2_PT_2/IN1 ),
    .I2(DCOR1THRESLOWr),
    .I3(\U1/U4/Latch1r [1]),
    .O(\outDATA<1>\$WA2.UIM_MC.D2_PT_2 )
  );
  X_AND4 \outDATA<1>\$WA2.UIM_MC.D2_PT_3_1014  (
    .I0(\NlwInverterSignal_outDATA<1>\$WA2.UIM_MC.D2_PT_3/IN0 ),
    .I1(\NlwInverterSignal_outDATA<1>\$WA2.UIM_MC.D2_PT_3/IN1 ),
    .I2(\NlwInverterSignal_outDATA<1>\$WA2.UIM_MC.D2_PT_3/IN2 ),
    .I3(\U1/U4/Latch1r [9]),
    .O(\outDATA<1>\$WA2.UIM_MC.D2_PT_3 )
  );
  X_OR4 \outDATA<1>\$WA2.UIM_MC.D2_1015  (
    .I0(\outDATA<1>\$WA2.UIM_MC.D2_PT_0 ),
    .I1(\outDATA<1>\$WA2.UIM_MC.D2_PT_1 ),
    .I2(\outDATA<1>\$WA2.UIM_MC.D2_PT_2 ),
    .I3(\outDATA<1>\$WA2.UIM_MC.D2_PT_3 ),
    .O(\outDATA<1>\$WA2.UIM_MC.D2 )
  );
  X_BUF \U1/U4/Latch0r<1>  (
    .I(\U1/U4/Latch0r<1>_MC.Q ),
    .O(\U1/U4/Latch0r [1])
  );
  X_FF \U1/U4/Latch0r<1>_MC.REG  (
    .I(\U1/U4/Latch0r<1>_MC.D ),
    .CE(Vcc),
    .CLK(\U1/U4/Latch0r<1>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\U1/U4/Latch0r<1>_MC.Q )
  );
  X_INV \U1/U4/Latch0r<1>_MC.REG_tsimcreated_inv_Mclk_II/FCLK_1016  (
    .I(\Mclk_II/FCLK ),
    .O(\U1/U4/Latch0r<1>_MC.REG_tsimcreated_inv_Mclk_II/FCLK )
  );
  X_XOR2 \U1/U4/Latch0r<1>_MC.D_1017  (
    .I0(\U1/U4/Latch0r<1>_MC.D1 ),
    .I1(\U1/U4/Latch0r<1>_MC.D2 ),
    .O(\U1/U4/Latch0r<1>_MC.D )
  );
  X_ZERO \U1/U4/Latch0r<1>_MC.D1_1018  (
    .O(\U1/U4/Latch0r<1>_MC.D1 )
  );
  X_AND3 \U1/U4/Latch0r<1>_MC.D2_PT_0_1019  (
    .I0(\MSPReset_II/UIM ),
    .I1(N_PZ_1018),
    .I2(\U1/Channel0 [1]),
    .O(\U1/U4/Latch0r<1>_MC.D2_PT_0 )
  );
  X_AND3 \U1/U4/Latch0r<1>_MC.D2_PT_1_1020  (
    .I0(\MSPReset_II/UIM ),
    .I1(\NlwInverterSignal_U1/U4/Latch0r<1>_MC.D2_PT_1/IN1 ),
    .I2(\U1/U4/Latch0r [1]),
    .O(\U1/U4/Latch0r<1>_MC.D2_PT_1 )
  );
  X_OR2 \U1/U4/Latch0r<1>_MC.D2_1021  (
    .I0(\U1/U4/Latch0r<1>_MC.D2_PT_0 ),
    .I1(\U1/U4/Latch0r<1>_MC.D2_PT_1 ),
    .O(\U1/U4/Latch0r<1>_MC.D2 )
  );
  X_BUF \U1/U4/Latch0r<9>  (
    .I(\U1/U4/Latch0r<9>_MC.Q ),
    .O(\U1/U4/Latch0r [9])
  );
  X_FF \U1/U4/Latch0r<9>_MC.REG  (
    .I(\U1/U4/Latch0r<9>_MC.D ),
    .CE(Vcc),
    .CLK(\U1/U4/Latch0r<9>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\U1/U4/Latch0r<9>_MC.Q )
  );
  X_INV \U1/U4/Latch0r<9>_MC.REG_tsimcreated_inv_Mclk_II/FCLK_1022  (
    .I(\Mclk_II/FCLK ),
    .O(\U1/U4/Latch0r<9>_MC.REG_tsimcreated_inv_Mclk_II/FCLK )
  );
  X_XOR2 \U1/U4/Latch0r<9>_MC.D_1023  (
    .I0(\U1/U4/Latch0r<9>_MC.D1 ),
    .I1(\U1/U4/Latch0r<9>_MC.D2 ),
    .O(\U1/U4/Latch0r<9>_MC.D )
  );
  X_ZERO \U1/U4/Latch0r<9>_MC.D1_1024  (
    .O(\U1/U4/Latch0r<9>_MC.D1 )
  );
  X_AND3 \U1/U4/Latch0r<9>_MC.D2_PT_0_1025  (
    .I0(\MSPReset_II/UIM ),
    .I1(N_PZ_1018),
    .I2(\U1/Channel0 [9]),
    .O(\U1/U4/Latch0r<9>_MC.D2_PT_0 )
  );
  X_AND3 \U1/U4/Latch0r<9>_MC.D2_PT_1_1026  (
    .I0(\MSPReset_II/UIM ),
    .I1(\NlwInverterSignal_U1/U4/Latch0r<9>_MC.D2_PT_1/IN1 ),
    .I2(\U1/U4/Latch0r [9]),
    .O(\U1/U4/Latch0r<9>_MC.D2_PT_1 )
  );
  X_OR2 \U1/U4/Latch0r<9>_MC.D2_1027  (
    .I0(\U1/U4/Latch0r<9>_MC.D2_PT_0 ),
    .I1(\U1/U4/Latch0r<9>_MC.D2_PT_1 ),
    .O(\U1/U4/Latch0r<9>_MC.D2 )
  );
  X_BUF \U1/Channel0<9>  (
    .I(\U1/Channel0<9>_MC.Q ),
    .O(\U1/Channel0 [9])
  );
  X_XOR2 \U1/Channel0<9>_MC_tsimcreated_xor__1028  (
    .I0(\U1/Channel0<9>_MC.D ),
    .I1(\U1/Channel0<9>_MC.Q ),
    .O(\U1/Channel0<9>_MC_tsimcreated_xor_ )
  );
  X_FF \U1/Channel0<9>_MC.REG  (
    .I(\U1/Channel0<9>_MC_tsimcreated_xor_ ),
    .CE(Vcc),
    .CLK(\Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\U1/Channel0<9>_MC.Q )
  );
  X_XOR2 \U1/Channel0<9>_MC.D_1029  (
    .I0(\U1/Channel0<9>_MC.D1 ),
    .I1(\U1/Channel0<9>_MC.D2 ),
    .O(\U1/Channel0<9>_MC.D )
  );
  X_ZERO \U1/Channel0<9>_MC.D1_1030  (
    .O(\U1/Channel0<9>_MC.D1 )
  );
  X_AND2 \U1/Channel0<9>_MC.D2_PT_0_1031  (
    .I0(\NlwInverterSignal_U1/Channel0<9>_MC.D2_PT_0/IN0 ),
    .I1(\U1/Channel0 [9]),
    .O(\U1/Channel0<9>_MC.D2_PT_0 )
  );
  X_AND2 \U1/Channel0<9>_MC.D2_PT_1_1032  (
    .I0(\U1/U2/location_Maddsub__n0000__n0075 [0]),
    .I1(N_PZ_1021),
    .O(\U1/Channel0<9>_MC.D2_PT_1 )
  );
  X_AND2 \U1/Channel0<9>_MC.D2_PT_2_1033  (
    .I0(\NlwInverterSignal_U1/Channel0<9>_MC.D2_PT_2/IN0 ),
    .I1(N_PZ_1024),
    .O(\U1/Channel0<9>_MC.D2_PT_2 )
  );
  X_OR3 \U1/Channel0<9>_MC.D2_1034  (
    .I0(\U1/Channel0<9>_MC.D2_PT_0 ),
    .I1(\U1/Channel0<9>_MC.D2_PT_1 ),
    .I2(\U1/Channel0<9>_MC.D2_PT_2 ),
    .O(\U1/Channel0<9>_MC.D2 )
  );
  X_BUF \U1/U4/Latch1r<1>  (
    .I(\U1/U4/Latch1r<1>_MC.Q ),
    .O(\U1/U4/Latch1r [1])
  );
  X_FF \U1/U4/Latch1r<1>_MC.REG  (
    .I(\U1/U4/Latch1r<1>_MC.D ),
    .CE(Vcc),
    .CLK(\U1/U4/Latch1r<1>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\U1/U4/Latch1r<1>_MC.Q )
  );
  X_INV \U1/U4/Latch1r<1>_MC.REG_tsimcreated_inv_Mclk_II/FCLK_1035  (
    .I(\Mclk_II/FCLK ),
    .O(\U1/U4/Latch1r<1>_MC.REG_tsimcreated_inv_Mclk_II/FCLK )
  );
  X_XOR2 \U1/U4/Latch1r<1>_MC.D_1036  (
    .I0(\U1/U4/Latch1r<1>_MC.D1 ),
    .I1(\U1/U4/Latch1r<1>_MC.D2 ),
    .O(\U1/U4/Latch1r<1>_MC.D )
  );
  X_ZERO \U1/U4/Latch1r<1>_MC.D1_1037  (
    .O(\U1/U4/Latch1r<1>_MC.D1 )
  );
  X_AND3 \U1/U4/Latch1r<1>_MC.D2_PT_0_1038  (
    .I0(\MSPReset_II/UIM ),
    .I1(N_PZ_1019),
    .I2(\U1/Channel1 [1]),
    .O(\U1/U4/Latch1r<1>_MC.D2_PT_0 )
  );
  X_AND3 \U1/U4/Latch1r<1>_MC.D2_PT_1_1039  (
    .I0(\MSPReset_II/UIM ),
    .I1(\NlwInverterSignal_U1/U4/Latch1r<1>_MC.D2_PT_1/IN1 ),
    .I2(\U1/U4/Latch1r [1]),
    .O(\U1/U4/Latch1r<1>_MC.D2_PT_1 )
  );
  X_OR2 \U1/U4/Latch1r<1>_MC.D2_1040  (
    .I0(\U1/U4/Latch1r<1>_MC.D2_PT_0 ),
    .I1(\U1/U4/Latch1r<1>_MC.D2_PT_1 ),
    .O(\U1/U4/Latch1r<1>_MC.D2 )
  );
  X_BUF \U1/U4/Latch1r<9>  (
    .I(\U1/U4/Latch1r<9>_MC.Q ),
    .O(\U1/U4/Latch1r [9])
  );
  X_FF \U1/U4/Latch1r<9>_MC.REG  (
    .I(\U1/U4/Latch1r<9>_MC.D ),
    .CE(Vcc),
    .CLK(\U1/U4/Latch1r<9>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\U1/U4/Latch1r<9>_MC.Q )
  );
  X_INV \U1/U4/Latch1r<9>_MC.REG_tsimcreated_inv_Mclk_II/FCLK_1041  (
    .I(\Mclk_II/FCLK ),
    .O(\U1/U4/Latch1r<9>_MC.REG_tsimcreated_inv_Mclk_II/FCLK )
  );
  X_XOR2 \U1/U4/Latch1r<9>_MC.D_1042  (
    .I0(\U1/U4/Latch1r<9>_MC.D1 ),
    .I1(\U1/U4/Latch1r<9>_MC.D2 ),
    .O(\U1/U4/Latch1r<9>_MC.D )
  );
  X_ZERO \U1/U4/Latch1r<9>_MC.D1_1043  (
    .O(\U1/U4/Latch1r<9>_MC.D1 )
  );
  X_AND3 \U1/U4/Latch1r<9>_MC.D2_PT_0_1044  (
    .I0(\MSPReset_II/UIM ),
    .I1(N_PZ_1019),
    .I2(\U1/Channel1 [9]),
    .O(\U1/U4/Latch1r<9>_MC.D2_PT_0 )
  );
  X_AND3 \U1/U4/Latch1r<9>_MC.D2_PT_1_1045  (
    .I0(\MSPReset_II/UIM ),
    .I1(\NlwInverterSignal_U1/U4/Latch1r<9>_MC.D2_PT_1/IN1 ),
    .I2(\U1/U4/Latch1r [9]),
    .O(\U1/U4/Latch1r<9>_MC.D2_PT_1 )
  );
  X_OR2 \U1/U4/Latch1r<9>_MC.D2_1046  (
    .I0(\U1/U4/Latch1r<9>_MC.D2_PT_0 ),
    .I1(\U1/U4/Latch1r<9>_MC.D2_PT_1 ),
    .O(\U1/U4/Latch1r<9>_MC.D2 )
  );
  X_BUF \U1/Channel1<9>  (
    .I(\U1/Channel1<9>_MC.Q ),
    .O(\U1/Channel1 [9])
  );
  X_XOR2 \U1/Channel1<9>_MC_tsimcreated_xor__1047  (
    .I0(\U1/Channel1<9>_MC.D ),
    .I1(\U1/Channel1<9>_MC.Q ),
    .O(\U1/Channel1<9>_MC_tsimcreated_xor_ )
  );
  X_FF \U1/Channel1<9>_MC.REG  (
    .I(\U1/Channel1<9>_MC_tsimcreated_xor_ ),
    .CE(Vcc),
    .CLK(\Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\U1/Channel1<9>_MC.Q )
  );
  X_XOR2 \U1/Channel1<9>_MC.D_1048  (
    .I0(\U1/Channel1<9>_MC.D1 ),
    .I1(\U1/Channel1<9>_MC.D2 ),
    .O(\U1/Channel1<9>_MC.D )
  );
  X_ZERO \U1/Channel1<9>_MC.D1_1049  (
    .O(\U1/Channel1<9>_MC.D1 )
  );
  X_AND2 \U1/Channel1<9>_MC.D2_PT_0_1050  (
    .I0(\NlwInverterSignal_U1/Channel1<9>_MC.D2_PT_0/IN0 ),
    .I1(\U1/Channel1 [9]),
    .O(\U1/Channel1<9>_MC.D2_PT_0 )
  );
  X_AND6 \U1/Channel1<9>_MC.D2_PT_1_1051  (
    .I0(\MSPReset_II/UIM ),
    .I1(\NlwInverterSignal_U1/Channel1<9>_MC.D2_PT_1/IN1 ),
    .I2(\U1/U6/CurrState_Sreg0_FFD3 ),
    .I3(\NlwInverterSignal_U1/Channel1<9>_MC.D2_PT_1/IN3 ),
    .I4(N_PZ_975),
    .I5(\NlwInverterSignal_U1/Channel1<9>_MC.D2_PT_1/IN5 ),
    .O(\U1/Channel1<9>_MC.D2_PT_1 )
  );
  X_AND7 \U1/Channel1<9>_MC.D2_PT_2_1052  (
    .I0(\MSPReset_II/UIM ),
    .I1(\NlwInverterSignal_U1/Channel1<9>_MC.D2_PT_2/IN1 ),
    .I2(\U1/U6/CurrState_Sreg0_FFD3 ),
    .I3(\NlwInverterSignal_U1/Channel1<9>_MC.D2_PT_2/IN3 ),
    .I4(N_PZ_1154),
    .I5(\NlwInverterSignal_U1/Channel1<9>_MC.D2_PT_2/IN5 ),
    .I6(\U1/U5/location_Maddsub__n0000__n0075 [0]),
    .O(\U1/Channel1<9>_MC.D2_PT_2 )
  );
  X_OR3 \U1/Channel1<9>_MC.D2_1053  (
    .I0(\U1/Channel1<9>_MC.D2_PT_0 ),
    .I1(\U1/Channel1<9>_MC.D2_PT_1 ),
    .I2(\U1/Channel1<9>_MC.D2_PT_2 ),
    .O(\U1/Channel1<9>_MC.D2 )
  );
  X_BUF \outDATA<1>\$WA3.UIM_1054  (
    .I(\outDATA<1>\$WA3.UIM_MC.Q ),
    .O(\outDATA<1>\$WA3.UIM )
  );
  X_BUF \outDATA<1>\$WA3.UIM_MC.Q_1055  (
    .I(\outDATA<1>\$WA3.UIM_MC.D ),
    .O(\outDATA<1>\$WA3.UIM_MC.Q )
  );
  X_XOR2 \outDATA<1>\$WA3.UIM_MC.D_1056  (
    .I0(\outDATA<1>\$WA3.UIM_MC.D1 ),
    .I1(\outDATA<1>\$WA3.UIM_MC.D2 ),
    .O(\outDATA<1>\$WA3.UIM_MC.D )
  );
  X_AND2 \outDATA<1>\$WA3.UIM_MC.D1_1057  (
    .I0(\I2CS<1>_II/UIM ),
    .I1(\I2CS<1>_II/UIM ),
    .O(\outDATA<1>\$WA3.UIM_MC.D1 )
  );
  X_ZERO \outDATA<1>\$WA3.UIM_MC.D2_1058  (
    .O(\outDATA<1>\$WA3.UIM_MC.D2 )
  );
  X_BUF \outDATA<1>\$WA5.UIM_1059  (
    .I(\outDATA<1>\$WA5.UIM_MC.Q ),
    .O(\outDATA<1>\$WA5.UIM )
  );
  X_BUF \outDATA<1>\$WA5.UIM_MC.Q_1060  (
    .I(\outDATA<1>\$WA5.UIM_MC.D ),
    .O(\outDATA<1>\$WA5.UIM_MC.Q )
  );
  X_XOR2 \outDATA<1>\$WA5.UIM_MC.D_1061  (
    .I0(\outDATA<1>\$WA5.UIM_MC.D1 ),
    .I1(\outDATA<1>\$WA5.UIM_MC.D2 ),
    .O(\outDATA<1>\$WA5.UIM_MC.D )
  );
  X_ZERO \outDATA<1>\$WA5.UIM_MC.D1_1062  (
    .O(\outDATA<1>\$WA5.UIM_MC.D1 )
  );
  X_AND2 \outDATA<1>\$WA5.UIM_MC.D2_PT_0_1063  (
    .I0(\NlwInverterSignal_outDATA<1>\$WA5.UIM_MC.D2_PT_0/IN0 ),
    .I1(NET2528),
    .O(\outDATA<1>\$WA5.UIM_MC.D2_PT_0 )
  );
  X_AND2 \outDATA<1>\$WA5.UIM_MC.D2_PT_1_1064  (
    .I0(NET2528),
    .I1(\U4/Flgreg [1]),
    .O(\outDATA<1>\$WA5.UIM_MC.D2_PT_1 )
  );
  X_AND3 \outDATA<1>\$WA5.UIM_MC.D2_PT_2_1065  (
    .I0(DCORENCPWRr),
    .I1(\NlwInverterSignal_outDATA<1>\$WA5.UIM_MC.D2_PT_2/IN1 ),
    .I2(\Home05FLG_II/UIM ),
    .O(\outDATA<1>\$WA5.UIM_MC.D2_PT_2 )
  );
  X_OR3 \outDATA<1>\$WA5.UIM_MC.D2_1066  (
    .I0(\outDATA<1>\$WA5.UIM_MC.D2_PT_0 ),
    .I1(\outDATA<1>\$WA5.UIM_MC.D2_PT_1 ),
    .I2(\outDATA<1>\$WA5.UIM_MC.D2_PT_2 ),
    .O(\outDATA<1>\$WA5.UIM_MC.D2 )
  );
  X_BUF \outDATA<1>\$WA4.UIM_1067  (
    .I(\outDATA<1>\$WA4.UIM_MC.Q ),
    .O(\outDATA<1>\$WA4.UIM )
  );
  X_BUF \outDATA<1>\$WA4.UIM_MC.Q_1068  (
    .I(\outDATA<1>\$WA4.UIM_MC.D ),
    .O(\outDATA<1>\$WA4.UIM_MC.Q )
  );
  X_XOR2 \outDATA<1>\$WA4.UIM_MC.D_1069  (
    .I0(\outDATA<1>\$WA4.UIM_MC.D1 ),
    .I1(\outDATA<1>\$WA4.UIM_MC.D2 ),
    .O(\outDATA<1>\$WA4.UIM_MC.D )
  );
  X_ZERO \outDATA<1>\$WA4.UIM_MC.D1_1070  (
    .O(\outDATA<1>\$WA4.UIM_MC.D1 )
  );
  X_AND2 \outDATA<1>\$WA4.UIM_MC.D2_PT_0_1071  (
    .I0(DCORLIMITSr),
    .I1(\NlwInverterSignal_outDATA<1>\$WA4.UIM_MC.D2_PT_0/IN1 ),
    .O(\outDATA<1>\$WA4.UIM_MC.D2_PT_0 )
  );
  X_AND2 \outDATA<1>\$WA4.UIM_MC.D2_PT_1_1072  (
    .I0(\NlwInverterSignal_outDATA<1>\$WA4.UIM_MC.D2_PT_1/IN0 ),
    .I1(\U5/FLS0fr ),
    .O(\outDATA<1>\$WA4.UIM_MC.D2_PT_1 )
  );
  X_OR2 \outDATA<1>\$WA4.UIM_MC.D2_1073  (
    .I0(\outDATA<1>\$WA4.UIM_MC.D2_PT_0 ),
    .I1(\outDATA<1>\$WA4.UIM_MC.D2_PT_1 ),
    .O(\outDATA<1>\$WA4.UIM_MC.D2 )
  );
  X_BUF \U5/FLS0fr_1074  (
    .I(\U5/FLS0fr_MC.Q ),
    .O(\U5/FLS0fr )
  );
  X_FF \U5/FLS0fr_MC.REG  (
    .I(\U5/FLS0fr_MC.D ),
    .CE(Vcc),
    .CLK(\U5/FLS0fr_MC.REG_tsimcreated_inv_Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\U5/FLS0fr_MC.Q )
  );
  X_INV \U5/FLS0fr_MC.REG_tsimcreated_inv_Mclk_II/FCLK_1075  (
    .I(\Mclk_II/FCLK ),
    .O(\U5/FLS0fr_MC.REG_tsimcreated_inv_Mclk_II/FCLK )
  );
  X_XOR2 \U5/FLS0fr_MC.D_1076  (
    .I0(\U5/FLS0fr_MC.D1 ),
    .I1(\U5/FLS0fr_MC.D2 ),
    .O(\U5/FLS0fr_MC.D )
  );
  X_ZERO \U5/FLS0fr_MC.D1_1077  (
    .O(\U5/FLS0fr_MC.D1 )
  );
  X_AND3 \U5/FLS0fr_MC.D2_PT_0_1078  (
    .I0(\MSPReset_II/UIM ),
    .I1(\NlwInverterSignal_U5/FLS0fr_MC.D2_PT_0/IN1 ),
    .I2(\U5/FLS0fr ),
    .O(\U5/FLS0fr_MC.D2_PT_0 )
  );
  X_AND5 \U5/FLS0fr_MC.D2_PT_1_1079  (
    .I0(\MSPReset_II/UIM ),
    .I1(\NlwInverterSignal_U5/FLS0fr_MC.D2_PT_1/IN1 ),
    .I2(\DIR0_II/UIM ),
    .I3(\NlwInverterSignal_U5/FLS0fr_MC.D2_PT_1/IN3 ),
    .I4(\U5/FLS0r ),
    .O(\U5/FLS0fr_MC.D2_PT_1 )
  );
  X_OR2 \U5/FLS0fr_MC.D2_1080  (
    .I0(\U5/FLS0fr_MC.D2_PT_0 ),
    .I1(\U5/FLS0fr_MC.D2_PT_1 ),
    .O(\U5/FLS0fr_MC.D2 )
  );
  X_BUF \U5/FLS0r_1081  (
    .I(\U5/FLS0r_MC.Q ),
    .O(\U5/FLS0r )
  );
  X_FF \U5/FLS0r_MC.REG  (
    .I(\U5/FLS0r_MC.D ),
    .CE(Vcc),
    .CLK(\U5/FLS0r_MC.REG_tsimcreated_inv_Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\U5/FLS0r_MC.Q )
  );
  X_INV \U5/FLS0r_MC.REG_tsimcreated_inv_Mclk_II/FCLK_1082  (
    .I(\Mclk_II/FCLK ),
    .O(\U5/FLS0r_MC.REG_tsimcreated_inv_Mclk_II/FCLK )
  );
  X_XOR2 \U5/FLS0r_MC.D_1083  (
    .I0(\U5/FLS0r_MC.D1 ),
    .I1(\U5/FLS0r_MC.D2 ),
    .O(\U5/FLS0r_MC.D )
  );
  X_AND2 \U5/FLS0r_MC.D1_1084  (
    .I0(\MSPReset_II/UIM ),
    .I1(\FLS0_II/UIM ),
    .O(\U5/FLS0r_MC.D1 )
  );
  X_ZERO \U5/FLS0r_MC.D2_1085  (
    .O(\U5/FLS0r_MC.D2 )
  );
  X_BUF \outDATA<1>\$WA1.UIM_1086  (
    .I(\outDATA<1>\$WA1.UIM_MC.Q ),
    .O(\outDATA<1>\$WA1.UIM )
  );
  X_BUF \outDATA<1>\$WA1.UIM_MC.Q_1087  (
    .I(\outDATA<1>\$WA1.UIM_MC.D ),
    .O(\outDATA<1>\$WA1.UIM_MC.Q )
  );
  X_XOR2 \outDATA<1>\$WA1.UIM_MC.D_1088  (
    .I0(\outDATA<1>\$WA1.UIM_MC.D1 ),
    .I1(\outDATA<1>\$WA1.UIM_MC.D2 ),
    .O(\outDATA<1>\$WA1.UIM_MC.D )
  );
  X_ZERO \outDATA<1>\$WA1.UIM_MC.D1_1089  (
    .O(\outDATA<1>\$WA1.UIM_MC.D1 )
  );
  X_AND2 \outDATA<1>\$WA1.UIM_MC.D2_PT_0_1090  (
    .I0(DCOR0CNTLOWr),
    .I1(\U1/U3/holdingreg0 [1]),
    .O(\outDATA<1>\$WA1.UIM_MC.D2_PT_0 )
  );
  X_AND3 \outDATA<1>\$WA1.UIM_MC.D2_PT_1_1091  (
    .I0(\NlwInverterSignal_outDATA<1>\$WA1.UIM_MC.D2_PT_1/IN0 ),
    .I1(DCOR1CNTLOWr),
    .I2(\U1/U3/holdingreg1 [1]),
    .O(\outDATA<1>\$WA1.UIM_MC.D2_PT_1 )
  );
  X_AND4 \outDATA<1>\$WA1.UIM_MC.D2_PT_2_1092  (
    .I0(\NlwInverterSignal_outDATA<1>\$WA1.UIM_MC.D2_PT_2/IN0 ),
    .I1(\NlwInverterSignal_outDATA<1>\$WA1.UIM_MC.D2_PT_2/IN1 ),
    .I2(DCOR0CNTHIGHr),
    .I3(\U1/U3/holdingreg0 [9]),
    .O(\outDATA<1>\$WA1.UIM_MC.D2_PT_2 )
  );
  X_AND4 \outDATA<1>\$WA1.UIM_MC.D2_PT_3_1093  (
    .I0(\NlwInverterSignal_outDATA<1>\$WA1.UIM_MC.D2_PT_3/IN0 ),
    .I1(\NlwInverterSignal_outDATA<1>\$WA1.UIM_MC.D2_PT_3/IN1 ),
    .I2(\NlwInverterSignal_outDATA<1>\$WA1.UIM_MC.D2_PT_3/IN2 ),
    .I3(\U1/U3/holdingreg1 [9]),
    .O(\outDATA<1>\$WA1.UIM_MC.D2_PT_3 )
  );
  X_OR4 \outDATA<1>\$WA1.UIM_MC.D2_1094  (
    .I0(\outDATA<1>\$WA1.UIM_MC.D2_PT_0 ),
    .I1(\outDATA<1>\$WA1.UIM_MC.D2_PT_1 ),
    .I2(\outDATA<1>\$WA1.UIM_MC.D2_PT_2 ),
    .I3(\outDATA<1>\$WA1.UIM_MC.D2_PT_3 ),
    .O(\outDATA<1>\$WA1.UIM_MC.D2 )
  );
  X_BUF \U1/U3/holdingreg0<1>  (
    .I(\U1/U3/holdingreg0<1>_MC.Q ),
    .O(\U1/U3/holdingreg0 [1])
  );
  X_FF \U1/U3/holdingreg0<1>_MC.REG  (
    .I(\U1/U3/holdingreg0<1>_MC.D ),
    .CE(Vcc),
    .CLK(\U1/U3/holdingreg0<1>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\U1/U3/holdingreg0<1>_MC.Q )
  );
  X_INV \U1/U3/holdingreg0<1>_MC.REG_tsimcreated_inv_Mclk_II/FCLK_1095  (
    .I(\Mclk_II/FCLK ),
    .O(\U1/U3/holdingreg0<1>_MC.REG_tsimcreated_inv_Mclk_II/FCLK )
  );
  X_XOR2 \U1/U3/holdingreg0<1>_MC.D_1096  (
    .I0(\U1/U3/holdingreg0<1>_MC.D1 ),
    .I1(\U1/U3/holdingreg0<1>_MC.D2 ),
    .O(\U1/U3/holdingreg0<1>_MC.D )
  );
  X_ZERO \U1/U3/holdingreg0<1>_MC.D1_1097  (
    .O(\U1/U3/holdingreg0<1>_MC.D1 )
  );
  X_AND2 \U1/U3/holdingreg0<1>_MC.D2_PT_0_1098  (
    .I0(N_PZ_992),
    .I1(\U1/U3/holdingreg0 [1]),
    .O(\U1/U3/holdingreg0<1>_MC.D2_PT_0 )
  );
  X_AND4 \U1/U3/holdingreg0<1>_MC.D2_PT_1_1099  (
    .I0(\MSPReset_II/UIM ),
    .I1(\NlwInverterSignal_U1/U3/holdingreg0<1>_MC.D2_PT_1/IN1 ),
    .I2(U2_ASedge),
    .I3(\U1/Channel0 [1]),
    .O(\U1/U3/holdingreg0<1>_MC.D2_PT_1 )
  );
  X_OR2 \U1/U3/holdingreg0<1>_MC.D2_1100  (
    .I0(\U1/U3/holdingreg0<1>_MC.D2_PT_0 ),
    .I1(\U1/U3/holdingreg0<1>_MC.D2_PT_1 ),
    .O(\U1/U3/holdingreg0<1>_MC.D2 )
  );
  X_BUF \U1/U3/holdingreg1<1>  (
    .I(\U1/U3/holdingreg1<1>_MC.Q ),
    .O(\U1/U3/holdingreg1 [1])
  );
  X_FF \U1/U3/holdingreg1<1>_MC.REG  (
    .I(\U1/U3/holdingreg1<1>_MC.D ),
    .CE(Vcc),
    .CLK(\U1/U3/holdingreg1<1>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\U1/U3/holdingreg1<1>_MC.Q )
  );
  X_INV \U1/U3/holdingreg1<1>_MC.REG_tsimcreated_inv_Mclk_II/FCLK_1101  (
    .I(\Mclk_II/FCLK ),
    .O(\U1/U3/holdingreg1<1>_MC.REG_tsimcreated_inv_Mclk_II/FCLK )
  );
  X_XOR2 \U1/U3/holdingreg1<1>_MC.D_1102  (
    .I0(\U1/U3/holdingreg1<1>_MC.D1 ),
    .I1(\U1/U3/holdingreg1<1>_MC.D2 ),
    .O(\U1/U3/holdingreg1<1>_MC.D )
  );
  X_ZERO \U1/U3/holdingreg1<1>_MC.D1_1103  (
    .O(\U1/U3/holdingreg1<1>_MC.D1 )
  );
  X_AND2 \U1/U3/holdingreg1<1>_MC.D2_PT_0_1104  (
    .I0(N_PZ_992),
    .I1(\U1/U3/holdingreg1 [1]),
    .O(\U1/U3/holdingreg1<1>_MC.D2_PT_0 )
  );
  X_AND4 \U1/U3/holdingreg1<1>_MC.D2_PT_1_1105  (
    .I0(\MSPReset_II/UIM ),
    .I1(\NlwInverterSignal_U1/U3/holdingreg1<1>_MC.D2_PT_1/IN1 ),
    .I2(U2_ASedge),
    .I3(\U1/Channel1 [1]),
    .O(\U1/U3/holdingreg1<1>_MC.D2_PT_1 )
  );
  X_OR2 \U1/U3/holdingreg1<1>_MC.D2_1106  (
    .I0(\U1/U3/holdingreg1<1>_MC.D2_PT_0 ),
    .I1(\U1/U3/holdingreg1<1>_MC.D2_PT_1 ),
    .O(\U1/U3/holdingreg1<1>_MC.D2 )
  );
  X_BUF \U1/U3/holdingreg0<9>  (
    .I(\U1/U3/holdingreg0<9>_MC.Q ),
    .O(\U1/U3/holdingreg0 [9])
  );
  X_FF \U1/U3/holdingreg0<9>_MC.REG  (
    .I(\U1/U3/holdingreg0<9>_MC.D ),
    .CE(Vcc),
    .CLK(\U1/U3/holdingreg0<9>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\U1/U3/holdingreg0<9>_MC.Q )
  );
  X_INV \U1/U3/holdingreg0<9>_MC.REG_tsimcreated_inv_Mclk_II/FCLK_1107  (
    .I(\Mclk_II/FCLK ),
    .O(\U1/U3/holdingreg0<9>_MC.REG_tsimcreated_inv_Mclk_II/FCLK )
  );
  X_XOR2 \U1/U3/holdingreg0<9>_MC.D_1108  (
    .I0(\U1/U3/holdingreg0<9>_MC.D1 ),
    .I1(\U1/U3/holdingreg0<9>_MC.D2 ),
    .O(\U1/U3/holdingreg0<9>_MC.D )
  );
  X_ZERO \U1/U3/holdingreg0<9>_MC.D1_1109  (
    .O(\U1/U3/holdingreg0<9>_MC.D1 )
  );
  X_AND2 \U1/U3/holdingreg0<9>_MC.D2_PT_0_1110  (
    .I0(N_PZ_992),
    .I1(\U1/U3/holdingreg0 [9]),
    .O(\U1/U3/holdingreg0<9>_MC.D2_PT_0 )
  );
  X_AND4 \U1/U3/holdingreg0<9>_MC.D2_PT_1_1111  (
    .I0(\MSPReset_II/UIM ),
    .I1(\NlwInverterSignal_U1/U3/holdingreg0<9>_MC.D2_PT_1/IN1 ),
    .I2(U2_ASedge),
    .I3(\U1/Channel0 [9]),
    .O(\U1/U3/holdingreg0<9>_MC.D2_PT_1 )
  );
  X_OR2 \U1/U3/holdingreg0<9>_MC.D2_1112  (
    .I0(\U1/U3/holdingreg0<9>_MC.D2_PT_0 ),
    .I1(\U1/U3/holdingreg0<9>_MC.D2_PT_1 ),
    .O(\U1/U3/holdingreg0<9>_MC.D2 )
  );
  X_BUF \U1/U3/holdingreg1<9>  (
    .I(\U1/U3/holdingreg1<9>_MC.Q ),
    .O(\U1/U3/holdingreg1 [9])
  );
  X_FF \U1/U3/holdingreg1<9>_MC.REG  (
    .I(\U1/U3/holdingreg1<9>_MC.D ),
    .CE(Vcc),
    .CLK(\U1/U3/holdingreg1<9>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\U1/U3/holdingreg1<9>_MC.Q )
  );
  X_INV \U1/U3/holdingreg1<9>_MC.REG_tsimcreated_inv_Mclk_II/FCLK_1113  (
    .I(\Mclk_II/FCLK ),
    .O(\U1/U3/holdingreg1<9>_MC.REG_tsimcreated_inv_Mclk_II/FCLK )
  );
  X_XOR2 \U1/U3/holdingreg1<9>_MC.D_1114  (
    .I0(\U1/U3/holdingreg1<9>_MC.D1 ),
    .I1(\U1/U3/holdingreg1<9>_MC.D2 ),
    .O(\U1/U3/holdingreg1<9>_MC.D )
  );
  X_ZERO \U1/U3/holdingreg1<9>_MC.D1_1115  (
    .O(\U1/U3/holdingreg1<9>_MC.D1 )
  );
  X_AND2 \U1/U3/holdingreg1<9>_MC.D2_PT_0_1116  (
    .I0(N_PZ_992),
    .I1(\U1/U3/holdingreg1 [9]),
    .O(\U1/U3/holdingreg1<9>_MC.D2_PT_0 )
  );
  X_AND4 \U1/U3/holdingreg1<9>_MC.D2_PT_1_1117  (
    .I0(\MSPReset_II/UIM ),
    .I1(\NlwInverterSignal_U1/U3/holdingreg1<9>_MC.D2_PT_1/IN1 ),
    .I2(U2_ASedge),
    .I3(\U1/Channel1 [9]),
    .O(\U1/U3/holdingreg1<9>_MC.D2_PT_1 )
  );
  X_OR2 \U1/U3/holdingreg1<9>_MC.D2_1118  (
    .I0(\U1/U3/holdingreg1<9>_MC.D2_PT_0 ),
    .I1(\U1/U3/holdingreg1<9>_MC.D2_PT_1 ),
    .O(\U1/U3/holdingreg1<9>_MC.D2 )
  );
  X_BUF \AD<4>_MC.Q_1119  (
    .I(\AD<4>_MC.Q_tsimrenamed_net_ ),
    .O(\AD<4>_MC.Q )
  );
  X_BUF \AD<4>_MC.OE_1120  (
    .I(\AD<4>_MC.BUFOE.OUT ),
    .O(\AD<4>_MC.OE )
  );
  X_BUF \AD<4>_MC.BUFOE.OUT_1121  (
    .I(\FOOBAR1__ctinst/7 ),
    .O(\AD<4>_MC.BUFOE.OUT )
  );
  X_BUF \AD<4>_MC.Q_tsimrenamed_net__1122  (
    .I(\AD<4>_MC.D ),
    .O(\AD<4>_MC.Q_tsimrenamed_net_ )
  );
  X_XOR2 \AD<4>_MC.D_1123  (
    .I0(\NlwInverterSignal_AD<4>_MC.D/IN0 ),
    .I1(\AD<4>_MC.D2 ),
    .O(\AD<4>_MC.D )
  );
  X_ZERO \AD<4>_MC.D1_1124  (
    .O(\AD<4>_MC.D1 )
  );
  X_AND2 \AD<4>_MC.D2_PT_0_1125  (
    .I0(DCORI2CCNTr),
    .I1(\NlwInverterSignal_AD<4>_MC.D2_PT_0/IN1 ),
    .O(\AD<4>_MC.D2_PT_0 )
  );
  X_AND2 \AD<4>_MC.D2_PT_1_1126  (
    .I0(DCOR0THRESLOWr),
    .I1(\NlwInverterSignal_AD<4>_MC.D2_PT_1/IN1 ),
    .O(\AD<4>_MC.D2_PT_1 )
  );
  X_AND2 \AD<4>_MC.D2_PT_2_1127  (
    .I0(DCORCONFIGr),
    .I1(\NlwInverterSignal_AD<4>_MC.D2_PT_2/IN1 ),
    .O(\AD<4>_MC.D2_PT_2 )
  );
  X_AND2 \AD<4>_MC.D2_PT_3_1128  (
    .I0(DCORENCPWRr),
    .I1(\NlwInverterSignal_AD<4>_MC.D2_PT_3/IN1 ),
    .O(\AD<4>_MC.D2_PT_3 )
  );
  X_AND2 \AD<4>_MC.D2_PT_4_1129  (
    .I0(DCORIFGr),
    .I1(\NlwInverterSignal_AD<4>_MC.D2_PT_4/IN1 ),
    .O(\AD<4>_MC.D2_PT_4 )
  );
  X_AND2 \AD<4>_MC.D2_PT_5_1130  (
    .I0(\NlwInverterSignal_AD<4>_MC.D2_PT_5/IN0 ),
    .I1(\NlwInverterSignal_AD<4>_MC.D2_PT_5/IN1 ),
    .O(\AD<4>_MC.D2_PT_5 )
  );
  X_AND2 \AD<4>_MC.D2_PT_6_1131  (
    .I0(\NlwInverterSignal_AD<4>_MC.D2_PT_6/IN0 ),
    .I1(\NlwInverterSignal_AD<4>_MC.D2_PT_6/IN1 ),
    .O(\AD<4>_MC.D2_PT_6 )
  );
  X_AND3 \AD<4>_MC.D2_PT_7_1132  (
    .I0(\NlwInverterSignal_AD<4>_MC.D2_PT_7/IN0 ),
    .I1(\NlwInverterSignal_AD<4>_MC.D2_PT_7/IN1 ),
    .I2(\NlwInverterSignal_AD<4>_MC.D2_PT_7/IN2 ),
    .O(\AD<4>_MC.D2_PT_7 )
  );
  X_OR8 \AD<4>_MC.D2_1133  (
    .I0(\AD<4>_MC.D2_PT_0 ),
    .I1(\AD<4>_MC.D2_PT_1 ),
    .I2(\AD<4>_MC.D2_PT_2 ),
    .I3(\AD<4>_MC.D2_PT_3 ),
    .I4(\AD<4>_MC.D2_PT_4 ),
    .I5(\AD<4>_MC.D2_PT_5 ),
    .I6(\AD<4>_MC.D2_PT_6 ),
    .I7(\AD<4>_MC.D2_PT_7 ),
    .O(\AD<4>_MC.D2 )
  );
  X_BUF \outDATA<4>\$WA0.UIM_1134  (
    .I(\outDATA<4>\$WA0.UIM_MC.Q ),
    .O(\outDATA<4>\$WA0.UIM )
  );
  X_BUF \outDATA<4>\$WA0.UIM_MC.Q_1135  (
    .I(\outDATA<4>\$WA0.UIM_MC.D ),
    .O(\outDATA<4>\$WA0.UIM_MC.Q )
  );
  X_XOR2 \outDATA<4>\$WA0.UIM_MC.D_1136  (
    .I0(\outDATA<4>\$WA0.UIM_MC.D1 ),
    .I1(\outDATA<4>\$WA0.UIM_MC.D2 ),
    .O(\outDATA<4>\$WA0.UIM_MC.D )
  );
  X_AND2 \outDATA<4>\$WA0.UIM_MC.D1_1137  (
    .I0(U11_U3_counterr[4]),
    .I1(U11_U3_counterr[4]),
    .O(\outDATA<4>\$WA0.UIM_MC.D1 )
  );
  X_ZERO \outDATA<4>\$WA0.UIM_MC.D2_1138  (
    .O(\outDATA<4>\$WA0.UIM_MC.D2 )
  );
  X_BUF \outDATA<4>\$WA2.UIM_1139  (
    .I(\outDATA<4>\$WA2.UIM_MC.Q ),
    .O(\outDATA<4>\$WA2.UIM )
  );
  X_BUF \outDATA<4>\$WA2.UIM_MC.Q_1140  (
    .I(\outDATA<4>\$WA2.UIM_MC.D ),
    .O(\outDATA<4>\$WA2.UIM_MC.Q )
  );
  X_XOR2 \outDATA<4>\$WA2.UIM_MC.D_1141  (
    .I0(\outDATA<4>\$WA2.UIM_MC.D1 ),
    .I1(\outDATA<4>\$WA2.UIM_MC.D2 ),
    .O(\outDATA<4>\$WA2.UIM_MC.D )
  );
  X_ZERO \outDATA<4>\$WA2.UIM_MC.D1_1142  (
    .O(\outDATA<4>\$WA2.UIM_MC.D1 )
  );
  X_AND2 \outDATA<4>\$WA2.UIM_MC.D2_PT_0_1143  (
    .I0(DCOR0THRESLOWr),
    .I1(\U1/U4/Latch0r [4]),
    .O(\outDATA<4>\$WA2.UIM_MC.D2_PT_0 )
  );
  X_AND3 \outDATA<4>\$WA2.UIM_MC.D2_PT_1_1144  (
    .I0(\NlwInverterSignal_outDATA<4>\$WA2.UIM_MC.D2_PT_1/IN0 ),
    .I1(DCOR0THRESHIGHr),
    .I2(\U1/U4/Latch0r [12]),
    .O(\outDATA<4>\$WA2.UIM_MC.D2_PT_1 )
  );
  X_AND4 \outDATA<4>\$WA2.UIM_MC.D2_PT_2_1145  (
    .I0(\NlwInverterSignal_outDATA<4>\$WA2.UIM_MC.D2_PT_2/IN0 ),
    .I1(\NlwInverterSignal_outDATA<4>\$WA2.UIM_MC.D2_PT_2/IN1 ),
    .I2(DCOR1THRESLOWr),
    .I3(\U1/U4/Latch1r [4]),
    .O(\outDATA<4>\$WA2.UIM_MC.D2_PT_2 )
  );
  X_AND4 \outDATA<4>\$WA2.UIM_MC.D2_PT_3_1146  (
    .I0(\NlwInverterSignal_outDATA<4>\$WA2.UIM_MC.D2_PT_3/IN0 ),
    .I1(\NlwInverterSignal_outDATA<4>\$WA2.UIM_MC.D2_PT_3/IN1 ),
    .I2(\NlwInverterSignal_outDATA<4>\$WA2.UIM_MC.D2_PT_3/IN2 ),
    .I3(\U1/U4/Latch1r [12]),
    .O(\outDATA<4>\$WA2.UIM_MC.D2_PT_3 )
  );
  X_OR4 \outDATA<4>\$WA2.UIM_MC.D2_1147  (
    .I0(\outDATA<4>\$WA2.UIM_MC.D2_PT_0 ),
    .I1(\outDATA<4>\$WA2.UIM_MC.D2_PT_1 ),
    .I2(\outDATA<4>\$WA2.UIM_MC.D2_PT_2 ),
    .I3(\outDATA<4>\$WA2.UIM_MC.D2_PT_3 ),
    .O(\outDATA<4>\$WA2.UIM_MC.D2 )
  );
  X_BUF \U1/U4/Latch0r<4>  (
    .I(\U1/U4/Latch0r<4>_MC.Q ),
    .O(\U1/U4/Latch0r [4])
  );
  X_FF \U1/U4/Latch0r<4>_MC.REG  (
    .I(\U1/U4/Latch0r<4>_MC.D ),
    .CE(Vcc),
    .CLK(\U1/U4/Latch0r<4>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\U1/U4/Latch0r<4>_MC.Q )
  );
  X_INV \U1/U4/Latch0r<4>_MC.REG_tsimcreated_inv_Mclk_II/FCLK_1148  (
    .I(\Mclk_II/FCLK ),
    .O(\U1/U4/Latch0r<4>_MC.REG_tsimcreated_inv_Mclk_II/FCLK )
  );
  X_XOR2 \U1/U4/Latch0r<4>_MC.D_1149  (
    .I0(\U1/U4/Latch0r<4>_MC.D1 ),
    .I1(\U1/U4/Latch0r<4>_MC.D2 ),
    .O(\U1/U4/Latch0r<4>_MC.D )
  );
  X_ZERO \U1/U4/Latch0r<4>_MC.D1_1150  (
    .O(\U1/U4/Latch0r<4>_MC.D1 )
  );
  X_AND3 \U1/U4/Latch0r<4>_MC.D2_PT_0_1151  (
    .I0(\MSPReset_II/UIM ),
    .I1(N_PZ_1018),
    .I2(\U1/Channel0 [4]),
    .O(\U1/U4/Latch0r<4>_MC.D2_PT_0 )
  );
  X_AND3 \U1/U4/Latch0r<4>_MC.D2_PT_1_1152  (
    .I0(\MSPReset_II/UIM ),
    .I1(\NlwInverterSignal_U1/U4/Latch0r<4>_MC.D2_PT_1/IN1 ),
    .I2(\U1/U4/Latch0r [4]),
    .O(\U1/U4/Latch0r<4>_MC.D2_PT_1 )
  );
  X_OR2 \U1/U4/Latch0r<4>_MC.D2_1153  (
    .I0(\U1/U4/Latch0r<4>_MC.D2_PT_0 ),
    .I1(\U1/U4/Latch0r<4>_MC.D2_PT_1 ),
    .O(\U1/U4/Latch0r<4>_MC.D2 )
  );
  X_BUF \U1/U4/Latch0r<12>  (
    .I(\U1/U4/Latch0r<12>_MC.Q ),
    .O(\U1/U4/Latch0r [12])
  );
  X_FF \U1/U4/Latch0r<12>_MC.REG  (
    .I(\U1/U4/Latch0r<12>_MC.D ),
    .CE(Vcc),
    .CLK(\U1/U4/Latch0r<12>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\U1/U4/Latch0r<12>_MC.Q )
  );
  X_INV \U1/U4/Latch0r<12>_MC.REG_tsimcreated_inv_Mclk_II/FCLK_1154  (
    .I(\Mclk_II/FCLK ),
    .O(\U1/U4/Latch0r<12>_MC.REG_tsimcreated_inv_Mclk_II/FCLK )
  );
  X_XOR2 \U1/U4/Latch0r<12>_MC.D_1155  (
    .I0(\U1/U4/Latch0r<12>_MC.D1 ),
    .I1(\U1/U4/Latch0r<12>_MC.D2 ),
    .O(\U1/U4/Latch0r<12>_MC.D )
  );
  X_ZERO \U1/U4/Latch0r<12>_MC.D1_1156  (
    .O(\U1/U4/Latch0r<12>_MC.D1 )
  );
  X_AND3 \U1/U4/Latch0r<12>_MC.D2_PT_0_1157  (
    .I0(\MSPReset_II/UIM ),
    .I1(N_PZ_1018),
    .I2(\U1/Channel0 [12]),
    .O(\U1/U4/Latch0r<12>_MC.D2_PT_0 )
  );
  X_AND3 \U1/U4/Latch0r<12>_MC.D2_PT_1_1158  (
    .I0(\MSPReset_II/UIM ),
    .I1(\NlwInverterSignal_U1/U4/Latch0r<12>_MC.D2_PT_1/IN1 ),
    .I2(\U1/U4/Latch0r [12]),
    .O(\U1/U4/Latch0r<12>_MC.D2_PT_1 )
  );
  X_OR2 \U1/U4/Latch0r<12>_MC.D2_1159  (
    .I0(\U1/U4/Latch0r<12>_MC.D2_PT_0 ),
    .I1(\U1/U4/Latch0r<12>_MC.D2_PT_1 ),
    .O(\U1/U4/Latch0r<12>_MC.D2 )
  );
  X_BUF \U1/Channel0<12>  (
    .I(\U1/Channel0<12>_MC.Q ),
    .O(\U1/Channel0 [12])
  );
  X_XOR2 \U1/Channel0<12>_MC_tsimcreated_xor__1160  (
    .I0(\U1/Channel0<12>_MC.D ),
    .I1(\U1/Channel0<12>_MC.Q ),
    .O(\U1/Channel0<12>_MC_tsimcreated_xor_ )
  );
  X_FF \U1/Channel0<12>_MC.REG  (
    .I(\U1/Channel0<12>_MC_tsimcreated_xor_ ),
    .CE(Vcc),
    .CLK(\Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\U1/Channel0<12>_MC.Q )
  );
  X_XOR2 \U1/Channel0<12>_MC.D_1161  (
    .I0(\U1/Channel0<12>_MC.D1 ),
    .I1(\U1/Channel0<12>_MC.D2 ),
    .O(\U1/Channel0<12>_MC.D )
  );
  X_ZERO \U1/Channel0<12>_MC.D1_1162  (
    .O(\U1/Channel0<12>_MC.D1 )
  );
  X_AND2 \U1/Channel0<12>_MC.D2_PT_0_1163  (
    .I0(\NlwInverterSignal_U1/Channel0<12>_MC.D2_PT_0/IN0 ),
    .I1(\U1/Channel0 [12]),
    .O(\U1/Channel0<12>_MC.D2_PT_0 )
  );
  X_AND5 \U1/Channel0<12>_MC.D2_PT_1_1164  (
    .I0(\U1/U2/location_Maddsub__n0000__n0075 [0]),
    .I1(N_PZ_1021),
    .I2(\NlwInverterSignal_U1/Channel0<12>_MC.D2_PT_1/IN2 ),
    .I3(\NlwInverterSignal_U1/Channel0<12>_MC.D2_PT_1/IN3 ),
    .I4(\NlwInverterSignal_U1/Channel0<12>_MC.D2_PT_1/IN4 ),
    .O(\U1/Channel0<12>_MC.D2_PT_1 )
  );
  X_AND5 \U1/Channel0<12>_MC.D2_PT_2_1165  (
    .I0(\NlwInverterSignal_U1/Channel0<12>_MC.D2_PT_2/IN0 ),
    .I1(N_PZ_1024),
    .I2(\U1/Channel0 [9]),
    .I3(\U1/Channel0 [10]),
    .I4(\U1/Channel0 [11]),
    .O(\U1/Channel0<12>_MC.D2_PT_2 )
  );
  X_OR3 \U1/Channel0<12>_MC.D2_1166  (
    .I0(\U1/Channel0<12>_MC.D2_PT_0 ),
    .I1(\U1/Channel0<12>_MC.D2_PT_1 ),
    .I2(\U1/Channel0<12>_MC.D2_PT_2 ),
    .O(\U1/Channel0<12>_MC.D2 )
  );
  X_BUF \U1/Channel0<10>  (
    .I(\U1/Channel0<10>_MC.Q ),
    .O(\U1/Channel0 [10])
  );
  X_XOR2 \U1/Channel0<10>_MC_tsimcreated_xor__1167  (
    .I0(\U1/Channel0<10>_MC.D ),
    .I1(\U1/Channel0<10>_MC.Q ),
    .O(\U1/Channel0<10>_MC_tsimcreated_xor_ )
  );
  X_FF \U1/Channel0<10>_MC.REG  (
    .I(\U1/Channel0<10>_MC_tsimcreated_xor_ ),
    .CE(Vcc),
    .CLK(\Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\U1/Channel0<10>_MC.Q )
  );
  X_XOR2 \U1/Channel0<10>_MC.D_1168  (
    .I0(\U1/Channel0<10>_MC.D1 ),
    .I1(\U1/Channel0<10>_MC.D2 ),
    .O(\U1/Channel0<10>_MC.D )
  );
  X_ZERO \U1/Channel0<10>_MC.D1_1169  (
    .O(\U1/Channel0<10>_MC.D1 )
  );
  X_AND2 \U1/Channel0<10>_MC.D2_PT_0_1170  (
    .I0(\NlwInverterSignal_U1/Channel0<10>_MC.D2_PT_0/IN0 ),
    .I1(\U1/Channel0 [10]),
    .O(\U1/Channel0<10>_MC.D2_PT_0 )
  );
  X_AND3 \U1/Channel0<10>_MC.D2_PT_1_1171  (
    .I0(\U1/U2/location_Maddsub__n0000__n0075 [0]),
    .I1(N_PZ_1021),
    .I2(\NlwInverterSignal_U1/Channel0<10>_MC.D2_PT_1/IN2 ),
    .O(\U1/Channel0<10>_MC.D2_PT_1 )
  );
  X_AND3 \U1/Channel0<10>_MC.D2_PT_2_1172  (
    .I0(\NlwInverterSignal_U1/Channel0<10>_MC.D2_PT_2/IN0 ),
    .I1(N_PZ_1024),
    .I2(\U1/Channel0 [9]),
    .O(\U1/Channel0<10>_MC.D2_PT_2 )
  );
  X_OR3 \U1/Channel0<10>_MC.D2_1173  (
    .I0(\U1/Channel0<10>_MC.D2_PT_0 ),
    .I1(\U1/Channel0<10>_MC.D2_PT_1 ),
    .I2(\U1/Channel0<10>_MC.D2_PT_2 ),
    .O(\U1/Channel0<10>_MC.D2 )
  );
  X_BUF \U1/Channel0<11>  (
    .I(\U1/Channel0<11>_MC.Q ),
    .O(\U1/Channel0 [11])
  );
  X_XOR2 \U1/Channel0<11>_MC_tsimcreated_xor__1174  (
    .I0(\U1/Channel0<11>_MC.D ),
    .I1(\U1/Channel0<11>_MC.Q ),
    .O(\U1/Channel0<11>_MC_tsimcreated_xor_ )
  );
  X_FF \U1/Channel0<11>_MC.REG  (
    .I(\U1/Channel0<11>_MC_tsimcreated_xor_ ),
    .CE(Vcc),
    .CLK(\Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\U1/Channel0<11>_MC.Q )
  );
  X_XOR2 \U1/Channel0<11>_MC.D_1175  (
    .I0(\U1/Channel0<11>_MC.D1 ),
    .I1(\U1/Channel0<11>_MC.D2 ),
    .O(\U1/Channel0<11>_MC.D )
  );
  X_ZERO \U1/Channel0<11>_MC.D1_1176  (
    .O(\U1/Channel0<11>_MC.D1 )
  );
  X_AND2 \U1/Channel0<11>_MC.D2_PT_0_1177  (
    .I0(\NlwInverterSignal_U1/Channel0<11>_MC.D2_PT_0/IN0 ),
    .I1(\U1/Channel0 [11]),
    .O(\U1/Channel0<11>_MC.D2_PT_0 )
  );
  X_AND4 \U1/Channel0<11>_MC.D2_PT_1_1178  (
    .I0(\U1/U2/location_Maddsub__n0000__n0075 [0]),
    .I1(N_PZ_1021),
    .I2(\NlwInverterSignal_U1/Channel0<11>_MC.D2_PT_1/IN2 ),
    .I3(\NlwInverterSignal_U1/Channel0<11>_MC.D2_PT_1/IN3 ),
    .O(\U1/Channel0<11>_MC.D2_PT_1 )
  );
  X_AND4 \U1/Channel0<11>_MC.D2_PT_2_1179  (
    .I0(\NlwInverterSignal_U1/Channel0<11>_MC.D2_PT_2/IN0 ),
    .I1(N_PZ_1024),
    .I2(\U1/Channel0 [9]),
    .I3(\U1/Channel0 [10]),
    .O(\U1/Channel0<11>_MC.D2_PT_2 )
  );
  X_OR3 \U1/Channel0<11>_MC.D2_1180  (
    .I0(\U1/Channel0<11>_MC.D2_PT_0 ),
    .I1(\U1/Channel0<11>_MC.D2_PT_1 ),
    .I2(\U1/Channel0<11>_MC.D2_PT_2 ),
    .O(\U1/Channel0<11>_MC.D2 )
  );
  X_BUF \U1/U4/Latch1r<4>  (
    .I(\U1/U4/Latch1r<4>_MC.Q ),
    .O(\U1/U4/Latch1r [4])
  );
  X_FF \U1/U4/Latch1r<4>_MC.REG  (
    .I(\U1/U4/Latch1r<4>_MC.D ),
    .CE(Vcc),
    .CLK(\U1/U4/Latch1r<4>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\U1/U4/Latch1r<4>_MC.Q )
  );
  X_INV \U1/U4/Latch1r<4>_MC.REG_tsimcreated_inv_Mclk_II/FCLK_1181  (
    .I(\Mclk_II/FCLK ),
    .O(\U1/U4/Latch1r<4>_MC.REG_tsimcreated_inv_Mclk_II/FCLK )
  );
  X_XOR2 \U1/U4/Latch1r<4>_MC.D_1182  (
    .I0(\U1/U4/Latch1r<4>_MC.D1 ),
    .I1(\U1/U4/Latch1r<4>_MC.D2 ),
    .O(\U1/U4/Latch1r<4>_MC.D )
  );
  X_ZERO \U1/U4/Latch1r<4>_MC.D1_1183  (
    .O(\U1/U4/Latch1r<4>_MC.D1 )
  );
  X_AND3 \U1/U4/Latch1r<4>_MC.D2_PT_0_1184  (
    .I0(\MSPReset_II/UIM ),
    .I1(N_PZ_1019),
    .I2(\U1/Channel1 [4]),
    .O(\U1/U4/Latch1r<4>_MC.D2_PT_0 )
  );
  X_AND3 \U1/U4/Latch1r<4>_MC.D2_PT_1_1185  (
    .I0(\MSPReset_II/UIM ),
    .I1(\NlwInverterSignal_U1/U4/Latch1r<4>_MC.D2_PT_1/IN1 ),
    .I2(\U1/U4/Latch1r [4]),
    .O(\U1/U4/Latch1r<4>_MC.D2_PT_1 )
  );
  X_OR2 \U1/U4/Latch1r<4>_MC.D2_1186  (
    .I0(\U1/U4/Latch1r<4>_MC.D2_PT_0 ),
    .I1(\U1/U4/Latch1r<4>_MC.D2_PT_1 ),
    .O(\U1/U4/Latch1r<4>_MC.D2 )
  );
  X_BUF \U1/U4/Latch1r<12>  (
    .I(\U1/U4/Latch1r<12>_MC.Q ),
    .O(\U1/U4/Latch1r [12])
  );
  X_FF \U1/U4/Latch1r<12>_MC.REG  (
    .I(\U1/U4/Latch1r<12>_MC.D ),
    .CE(Vcc),
    .CLK(\U1/U4/Latch1r<12>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\U1/U4/Latch1r<12>_MC.Q )
  );
  X_INV \U1/U4/Latch1r<12>_MC.REG_tsimcreated_inv_Mclk_II/FCLK_1187  (
    .I(\Mclk_II/FCLK ),
    .O(\U1/U4/Latch1r<12>_MC.REG_tsimcreated_inv_Mclk_II/FCLK )
  );
  X_XOR2 \U1/U4/Latch1r<12>_MC.D_1188  (
    .I0(\U1/U4/Latch1r<12>_MC.D1 ),
    .I1(\U1/U4/Latch1r<12>_MC.D2 ),
    .O(\U1/U4/Latch1r<12>_MC.D )
  );
  X_ZERO \U1/U4/Latch1r<12>_MC.D1_1189  (
    .O(\U1/U4/Latch1r<12>_MC.D1 )
  );
  X_AND3 \U1/U4/Latch1r<12>_MC.D2_PT_0_1190  (
    .I0(\MSPReset_II/UIM ),
    .I1(N_PZ_1019),
    .I2(\U1/Channel1 [12]),
    .O(\U1/U4/Latch1r<12>_MC.D2_PT_0 )
  );
  X_AND3 \U1/U4/Latch1r<12>_MC.D2_PT_1_1191  (
    .I0(\MSPReset_II/UIM ),
    .I1(\NlwInverterSignal_U1/U4/Latch1r<12>_MC.D2_PT_1/IN1 ),
    .I2(\U1/U4/Latch1r [12]),
    .O(\U1/U4/Latch1r<12>_MC.D2_PT_1 )
  );
  X_OR2 \U1/U4/Latch1r<12>_MC.D2_1192  (
    .I0(\U1/U4/Latch1r<12>_MC.D2_PT_0 ),
    .I1(\U1/U4/Latch1r<12>_MC.D2_PT_1 ),
    .O(\U1/U4/Latch1r<12>_MC.D2 )
  );
  X_BUF \U1/Channel1<12>  (
    .I(\U1/Channel1<12>_MC.Q ),
    .O(\U1/Channel1 [12])
  );
  X_XOR2 \U1/Channel1<12>_MC_tsimcreated_xor__1193  (
    .I0(\U1/Channel1<12>_MC.D ),
    .I1(\U1/Channel1<12>_MC.Q ),
    .O(\U1/Channel1<12>_MC_tsimcreated_xor_ )
  );
  X_FF \U1/Channel1<12>_MC.REG  (
    .I(\U1/Channel1<12>_MC_tsimcreated_xor_ ),
    .CE(Vcc),
    .CLK(\Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\U1/Channel1<12>_MC.Q )
  );
  X_XOR2 \U1/Channel1<12>_MC.D_1194  (
    .I0(\U1/Channel1<12>_MC.D1 ),
    .I1(\U1/Channel1<12>_MC.D2 ),
    .O(\U1/Channel1<12>_MC.D )
  );
  X_ZERO \U1/Channel1<12>_MC.D1_1195  (
    .O(\U1/Channel1<12>_MC.D1 )
  );
  X_AND2 \U1/Channel1<12>_MC.D2_PT_0_1196  (
    .I0(\NlwInverterSignal_U1/Channel1<12>_MC.D2_PT_0/IN0 ),
    .I1(\U1/Channel1 [12]),
    .O(\U1/Channel1<12>_MC.D2_PT_0 )
  );
  X_AND16 \U1/Channel1<12>_MC.D2_PT_1_1197  (
    .I0(\MSPReset_II/UIM ),
    .I1(\NlwInverterSignal_U1/Channel1<12>_MC.D2_PT_1/IN1 ),
    .I2(\U1/U6/CurrState_Sreg0_FFD3 ),
    .I3(\NlwInverterSignal_U1/Channel1<12>_MC.D2_PT_1/IN3 ),
    .I4(N_PZ_975),
    .I5(\NlwInverterSignal_U1/Channel1<12>_MC.D2_PT_1/IN5 ),
    .I6(\U1/Channel1 [9]),
    .I7(\U1/Channel1 [10]),
    .I8(\U1/Channel1 [11]),
    .I9(Vcc),
    .I10(Vcc),
    .I11(Vcc),
    .I12(Vcc),
    .I13(Vcc),
    .I14(Vcc),
    .I15(Vcc),
    .O(\U1/Channel1<12>_MC.D2_PT_1 )
  );
  X_AND16 \U1/Channel1<12>_MC.D2_PT_2_1198  (
    .I0(\MSPReset_II/UIM ),
    .I1(\NlwInverterSignal_U1/Channel1<12>_MC.D2_PT_2/IN1 ),
    .I2(\U1/U6/CurrState_Sreg0_FFD3 ),
    .I3(\NlwInverterSignal_U1/Channel1<12>_MC.D2_PT_2/IN3 ),
    .I4(N_PZ_1154),
    .I5(\NlwInverterSignal_U1/Channel1<12>_MC.D2_PT_2/IN5 ),
    .I6(\U1/U5/location_Maddsub__n0000__n0075 [0]),
    .I7(\NlwInverterSignal_U1/Channel1<12>_MC.D2_PT_2/IN7 ),
    .I8(\NlwInverterSignal_U1/Channel1<12>_MC.D2_PT_2/IN8 ),
    .I9(\NlwInverterSignal_U1/Channel1<12>_MC.D2_PT_2/IN9 ),
    .I10(Vcc),
    .I11(Vcc),
    .I12(Vcc),
    .I13(Vcc),
    .I14(Vcc),
    .I15(Vcc),
    .O(\U1/Channel1<12>_MC.D2_PT_2 )
  );
  X_OR3 \U1/Channel1<12>_MC.D2_1199  (
    .I0(\U1/Channel1<12>_MC.D2_PT_0 ),
    .I1(\U1/Channel1<12>_MC.D2_PT_1 ),
    .I2(\U1/Channel1<12>_MC.D2_PT_2 ),
    .O(\U1/Channel1<12>_MC.D2 )
  );
  X_BUF \U1/Channel1<10>  (
    .I(\U1/Channel1<10>_MC.Q ),
    .O(\U1/Channel1 [10])
  );
  X_XOR2 \U1/Channel1<10>_MC_tsimcreated_xor__1200  (
    .I0(\U1/Channel1<10>_MC.D ),
    .I1(\U1/Channel1<10>_MC.Q ),
    .O(\U1/Channel1<10>_MC_tsimcreated_xor_ )
  );
  X_FF \U1/Channel1<10>_MC.REG  (
    .I(\U1/Channel1<10>_MC_tsimcreated_xor_ ),
    .CE(Vcc),
    .CLK(\Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\U1/Channel1<10>_MC.Q )
  );
  X_XOR2 \U1/Channel1<10>_MC.D_1201  (
    .I0(\U1/Channel1<10>_MC.D1 ),
    .I1(\U1/Channel1<10>_MC.D2 ),
    .O(\U1/Channel1<10>_MC.D )
  );
  X_ZERO \U1/Channel1<10>_MC.D1_1202  (
    .O(\U1/Channel1<10>_MC.D1 )
  );
  X_AND2 \U1/Channel1<10>_MC.D2_PT_0_1203  (
    .I0(\NlwInverterSignal_U1/Channel1<10>_MC.D2_PT_0/IN0 ),
    .I1(\U1/Channel1 [10]),
    .O(\U1/Channel1<10>_MC.D2_PT_0 )
  );
  X_AND7 \U1/Channel1<10>_MC.D2_PT_1_1204  (
    .I0(\MSPReset_II/UIM ),
    .I1(\NlwInverterSignal_U1/Channel1<10>_MC.D2_PT_1/IN1 ),
    .I2(\U1/U6/CurrState_Sreg0_FFD3 ),
    .I3(\NlwInverterSignal_U1/Channel1<10>_MC.D2_PT_1/IN3 ),
    .I4(N_PZ_975),
    .I5(\NlwInverterSignal_U1/Channel1<10>_MC.D2_PT_1/IN5 ),
    .I6(\U1/Channel1 [9]),
    .O(\U1/Channel1<10>_MC.D2_PT_1 )
  );
  X_AND8 \U1/Channel1<10>_MC.D2_PT_2_1205  (
    .I0(\MSPReset_II/UIM ),
    .I1(\NlwInverterSignal_U1/Channel1<10>_MC.D2_PT_2/IN1 ),
    .I2(\U1/U6/CurrState_Sreg0_FFD3 ),
    .I3(\NlwInverterSignal_U1/Channel1<10>_MC.D2_PT_2/IN3 ),
    .I4(N_PZ_1154),
    .I5(\NlwInverterSignal_U1/Channel1<10>_MC.D2_PT_2/IN5 ),
    .I6(\U1/U5/location_Maddsub__n0000__n0075 [0]),
    .I7(\NlwInverterSignal_U1/Channel1<10>_MC.D2_PT_2/IN7 ),
    .O(\U1/Channel1<10>_MC.D2_PT_2 )
  );
  X_OR3 \U1/Channel1<10>_MC.D2_1206  (
    .I0(\U1/Channel1<10>_MC.D2_PT_0 ),
    .I1(\U1/Channel1<10>_MC.D2_PT_1 ),
    .I2(\U1/Channel1<10>_MC.D2_PT_2 ),
    .O(\U1/Channel1<10>_MC.D2 )
  );
  X_BUF \U1/Channel1<11>  (
    .I(\U1/Channel1<11>_MC.Q ),
    .O(\U1/Channel1 [11])
  );
  X_XOR2 \U1/Channel1<11>_MC_tsimcreated_xor__1207  (
    .I0(\U1/Channel1<11>_MC.D ),
    .I1(\U1/Channel1<11>_MC.Q ),
    .O(\U1/Channel1<11>_MC_tsimcreated_xor_ )
  );
  X_FF \U1/Channel1<11>_MC.REG  (
    .I(\U1/Channel1<11>_MC_tsimcreated_xor_ ),
    .CE(Vcc),
    .CLK(\Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\U1/Channel1<11>_MC.Q )
  );
  X_XOR2 \U1/Channel1<11>_MC.D_1208  (
    .I0(\U1/Channel1<11>_MC.D1 ),
    .I1(\U1/Channel1<11>_MC.D2 ),
    .O(\U1/Channel1<11>_MC.D )
  );
  X_ZERO \U1/Channel1<11>_MC.D1_1209  (
    .O(\U1/Channel1<11>_MC.D1 )
  );
  X_AND2 \U1/Channel1<11>_MC.D2_PT_0_1210  (
    .I0(\NlwInverterSignal_U1/Channel1<11>_MC.D2_PT_0/IN0 ),
    .I1(\U1/Channel1 [11]),
    .O(\U1/Channel1<11>_MC.D2_PT_0 )
  );
  X_AND8 \U1/Channel1<11>_MC.D2_PT_1_1211  (
    .I0(\MSPReset_II/UIM ),
    .I1(\NlwInverterSignal_U1/Channel1<11>_MC.D2_PT_1/IN1 ),
    .I2(\U1/U6/CurrState_Sreg0_FFD3 ),
    .I3(\NlwInverterSignal_U1/Channel1<11>_MC.D2_PT_1/IN3 ),
    .I4(N_PZ_975),
    .I5(\NlwInverterSignal_U1/Channel1<11>_MC.D2_PT_1/IN5 ),
    .I6(\U1/Channel1 [9]),
    .I7(\U1/Channel1 [10]),
    .O(\U1/Channel1<11>_MC.D2_PT_1 )
  );
  X_AND16 \U1/Channel1<11>_MC.D2_PT_2_1212  (
    .I0(\MSPReset_II/UIM ),
    .I1(\NlwInverterSignal_U1/Channel1<11>_MC.D2_PT_2/IN1 ),
    .I2(\U1/U6/CurrState_Sreg0_FFD3 ),
    .I3(\NlwInverterSignal_U1/Channel1<11>_MC.D2_PT_2/IN3 ),
    .I4(N_PZ_1154),
    .I5(\NlwInverterSignal_U1/Channel1<11>_MC.D2_PT_2/IN5 ),
    .I6(\U1/U5/location_Maddsub__n0000__n0075 [0]),
    .I7(\NlwInverterSignal_U1/Channel1<11>_MC.D2_PT_2/IN7 ),
    .I8(\NlwInverterSignal_U1/Channel1<11>_MC.D2_PT_2/IN8 ),
    .I9(Vcc),
    .I10(Vcc),
    .I11(Vcc),
    .I12(Vcc),
    .I13(Vcc),
    .I14(Vcc),
    .I15(Vcc),
    .O(\U1/Channel1<11>_MC.D2_PT_2 )
  );
  X_OR3 \U1/Channel1<11>_MC.D2_1213  (
    .I0(\U1/Channel1<11>_MC.D2_PT_0 ),
    .I1(\U1/Channel1<11>_MC.D2_PT_1 ),
    .I2(\U1/Channel1<11>_MC.D2_PT_2 ),
    .O(\U1/Channel1<11>_MC.D2 )
  );
  X_BUF \outDATA<4>\$WA3.UIM_1214  (
    .I(\outDATA<4>\$WA3.UIM_MC.Q ),
    .O(\outDATA<4>\$WA3.UIM )
  );
  X_BUF \outDATA<4>\$WA3.UIM_MC.Q_1215  (
    .I(\outDATA<4>\$WA3.UIM_MC.D ),
    .O(\outDATA<4>\$WA3.UIM_MC.Q )
  );
  X_XOR2 \outDATA<4>\$WA3.UIM_MC.D_1216  (
    .I0(\outDATA<4>\$WA3.UIM_MC.D1 ),
    .I1(\outDATA<4>\$WA3.UIM_MC.D2 ),
    .O(\outDATA<4>\$WA3.UIM_MC.D )
  );
  X_AND2 \outDATA<4>\$WA3.UIM_MC.D1_1217  (
    .I0(\I2CS<4>_II/UIM ),
    .I1(\I2CS<4>_II/UIM ),
    .O(\outDATA<4>\$WA3.UIM_MC.D1 )
  );
  X_ZERO \outDATA<4>\$WA3.UIM_MC.D2_1218  (
    .O(\outDATA<4>\$WA3.UIM_MC.D2 )
  );
  X_BUF \outDATA<4>\$WA5.UIM_1219  (
    .I(\outDATA<4>\$WA5.UIM_MC.Q ),
    .O(\outDATA<4>\$WA5.UIM )
  );
  X_BUF \outDATA<4>\$WA5.UIM_MC.Q_1220  (
    .I(\outDATA<4>\$WA5.UIM_MC.D ),
    .O(\outDATA<4>\$WA5.UIM_MC.Q )
  );
  X_XOR2 \outDATA<4>\$WA5.UIM_MC.D_1221  (
    .I0(\outDATA<4>\$WA5.UIM_MC.D1 ),
    .I1(\outDATA<4>\$WA5.UIM_MC.D2 ),
    .O(\outDATA<4>\$WA5.UIM_MC.D )
  );
  X_ZERO \outDATA<4>\$WA5.UIM_MC.D1_1222  (
    .O(\outDATA<4>\$WA5.UIM_MC.D1 )
  );
  X_AND2 \outDATA<4>\$WA5.UIM_MC.D2_PT_0_1223  (
    .I0(NET2528),
    .I1(\U4/Flgreg [4]),
    .O(\outDATA<4>\$WA5.UIM_MC.D2_PT_0 )
  );
  X_AND2 \outDATA<4>\$WA5.UIM_MC.D2_PT_1_1224  (
    .I0(\NlwInverterSignal_outDATA<4>\$WA5.UIM_MC.D2_PT_1/IN0 ),
    .I1(\Home133FLG_II/UIM ),
    .O(\outDATA<4>\$WA5.UIM_MC.D2_PT_1 )
  );
  X_OR2 \outDATA<4>\$WA5.UIM_MC.D2_1225  (
    .I0(\outDATA<4>\$WA5.UIM_MC.D2_PT_0 ),
    .I1(\outDATA<4>\$WA5.UIM_MC.D2_PT_1 ),
    .O(\outDATA<4>\$WA5.UIM_MC.D2 )
  );
  X_BUF \outDATA<4>\$WA6.UIM_1226  (
    .I(\outDATA<4>\$WA6.UIM_MC.Q ),
    .O(\outDATA<4>\$WA6.UIM )
  );
  X_BUF \outDATA<4>\$WA6.UIM_MC.Q_1227  (
    .I(\outDATA<4>\$WA6.UIM_MC.D ),
    .O(\outDATA<4>\$WA6.UIM_MC.Q )
  );
  X_XOR2 \outDATA<4>\$WA6.UIM_MC.D_1228  (
    .I0(\outDATA<4>\$WA6.UIM_MC.D1 ),
    .I1(\outDATA<4>\$WA6.UIM_MC.D2 ),
    .O(\outDATA<4>\$WA6.UIM_MC.D )
  );
  X_AND2 \outDATA<4>\$WA6.UIM_MC.D1_1229  (
    .I0(NET2575),
    .I1(NET2575),
    .O(\outDATA<4>\$WA6.UIM_MC.D1 )
  );
  X_ZERO \outDATA<4>\$WA6.UIM_MC.D2_1230  (
    .O(\outDATA<4>\$WA6.UIM_MC.D2 )
  );
  X_BUF NET2575_1231 (
    .I(\NET2575_MC.Q ),
    .O(NET2575)
  );
  X_FF \NET2575_MC.REG  (
    .I(\NET2575_MC.D ),
    .CE(Vcc),
    .CLK(\NET2575_MC.REG_tsimcreated_inv_Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\NET2575_MC.Q )
  );
  X_INV \NET2575_MC.REG_tsimcreated_inv_Mclk_II/FCLK_1232  (
    .I(\Mclk_II/FCLK ),
    .O(\NET2575_MC.REG_tsimcreated_inv_Mclk_II/FCLK )
  );
  X_XOR2 \NET2575_MC.D_1233  (
    .I0(\NlwInverterSignal_NET2575_MC.D/IN0 ),
    .I1(\NET2575_MC.D2 ),
    .O(\NET2575_MC.D )
  );
  X_ZERO \NET2575_MC.D1_1234  (
    .O(\NET2575_MC.D1 )
  );
  X_AND2 \NET2575_MC.D2_PT_0_1235  (
    .I0(\NlwInverterSignal_NET2575_MC.D2_PT_0/IN0 ),
    .I1(\NlwInverterSignal_NET2575_MC.D2_PT_0/IN1 ),
    .O(\NET2575_MC.D2_PT_0 )
  );
  X_AND2 \NET2575_MC.D2_PT_1_1236  (
    .I0(\AD<4>_II/UIM ),
    .I1(DCORIFGw),
    .O(\NET2575_MC.D2_PT_1 )
  );
  X_AND2 \NET2575_MC.D2_PT_2_1237  (
    .I0(DCORIFGw),
    .I1(\NlwInverterSignal_NET2575_MC.D2_PT_2/IN1 ),
    .O(\NET2575_MC.D2_PT_2 )
  );
  X_AND5 \NET2575_MC.D2_PT_3_1238  (
    .I0(\NlwInverterSignal_NET2575_MC.D2_PT_3/IN0 ),
    .I1(\NlwInverterSignal_NET2575_MC.D2_PT_3/IN1 ),
    .I2(\NlwInverterSignal_NET2575_MC.D2_PT_3/IN2 ),
    .I3(\NlwInverterSignal_NET2575_MC.D2_PT_3/IN3 ),
    .I4(\NlwInverterSignal_NET2575_MC.D2_PT_3/IN4 ),
    .O(\NET2575_MC.D2_PT_3 )
  );
  X_OR4 \NET2575_MC.D2_1239  (
    .I0(\NET2575_MC.D2_PT_0 ),
    .I1(\NET2575_MC.D2_PT_1 ),
    .I2(\NET2575_MC.D2_PT_2 ),
    .I3(\NET2575_MC.D2_PT_3 ),
    .O(\NET2575_MC.D2 )
  );
  X_BUF \U5/FLS1fr_1240  (
    .I(\U5/FLS1fr_MC.Q ),
    .O(\U5/FLS1fr )
  );
  X_FF \U5/FLS1fr_MC.REG  (
    .I(\U5/FLS1fr_MC.D ),
    .CE(Vcc),
    .CLK(\U5/FLS1fr_MC.REG_tsimcreated_inv_Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\U5/FLS1fr_MC.Q )
  );
  X_INV \U5/FLS1fr_MC.REG_tsimcreated_inv_Mclk_II/FCLK_1241  (
    .I(\Mclk_II/FCLK ),
    .O(\U5/FLS1fr_MC.REG_tsimcreated_inv_Mclk_II/FCLK )
  );
  X_XOR2 \U5/FLS1fr_MC.D_1242  (
    .I0(\U5/FLS1fr_MC.D1 ),
    .I1(\U5/FLS1fr_MC.D2 ),
    .O(\U5/FLS1fr_MC.D )
  );
  X_ZERO \U5/FLS1fr_MC.D1_1243  (
    .O(\U5/FLS1fr_MC.D1 )
  );
  X_AND3 \U5/FLS1fr_MC.D2_PT_0_1244  (
    .I0(\MSPReset_II/UIM ),
    .I1(\NlwInverterSignal_U5/FLS1fr_MC.D2_PT_0/IN1 ),
    .I2(\U5/FLS1fr ),
    .O(\U5/FLS1fr_MC.D2_PT_0 )
  );
  X_AND5 \U5/FLS1fr_MC.D2_PT_1_1245  (
    .I0(\MSPReset_II/UIM ),
    .I1(\NlwInverterSignal_U5/FLS1fr_MC.D2_PT_1/IN1 ),
    .I2(\DIR1_II/UIM ),
    .I3(\NlwInverterSignal_U5/FLS1fr_MC.D2_PT_1/IN3 ),
    .I4(\U5/FLS1r ),
    .O(\U5/FLS1fr_MC.D2_PT_1 )
  );
  X_OR2 \U5/FLS1fr_MC.D2_1246  (
    .I0(\U5/FLS1fr_MC.D2_PT_0 ),
    .I1(\U5/FLS1fr_MC.D2_PT_1 ),
    .O(\U5/FLS1fr_MC.D2 )
  );
  X_BUF \U5/FLS1r_1247  (
    .I(\U5/FLS1r_MC.Q ),
    .O(\U5/FLS1r )
  );
  X_FF \U5/FLS1r_MC.REG  (
    .I(\U5/FLS1r_MC.D ),
    .CE(Vcc),
    .CLK(\U5/FLS1r_MC.REG_tsimcreated_inv_Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\U5/FLS1r_MC.Q )
  );
  X_INV \U5/FLS1r_MC.REG_tsimcreated_inv_Mclk_II/FCLK_1248  (
    .I(\Mclk_II/FCLK ),
    .O(\U5/FLS1r_MC.REG_tsimcreated_inv_Mclk_II/FCLK )
  );
  X_XOR2 \U5/FLS1r_MC.D_1249  (
    .I0(\U5/FLS1r_MC.D1 ),
    .I1(\U5/FLS1r_MC.D2 ),
    .O(\U5/FLS1r_MC.D )
  );
  X_AND2 \U5/FLS1r_MC.D1_1250  (
    .I0(\MSPReset_II/UIM ),
    .I1(\FLS1_II/UIM ),
    .O(\U5/FLS1r_MC.D1 )
  );
  X_ZERO \U5/FLS1r_MC.D2_1251  (
    .O(\U5/FLS1r_MC.D2 )
  );
  X_BUF \U5/RLS1fr_1252  (
    .I(\U5/RLS1fr_MC.Q ),
    .O(\U5/RLS1fr )
  );
  X_FF \U5/RLS1fr_MC.REG  (
    .I(\U5/RLS1fr_MC.D ),
    .CE(Vcc),
    .CLK(\U5/RLS1fr_MC.REG_tsimcreated_inv_Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\U5/RLS1fr_MC.Q )
  );
  X_INV \U5/RLS1fr_MC.REG_tsimcreated_inv_Mclk_II/FCLK_1253  (
    .I(\Mclk_II/FCLK ),
    .O(\U5/RLS1fr_MC.REG_tsimcreated_inv_Mclk_II/FCLK )
  );
  X_XOR2 \U5/RLS1fr_MC.D_1254  (
    .I0(\U5/RLS1fr_MC.D1 ),
    .I1(\U5/RLS1fr_MC.D2 ),
    .O(\U5/RLS1fr_MC.D )
  );
  X_ZERO \U5/RLS1fr_MC.D1_1255  (
    .O(\U5/RLS1fr_MC.D1 )
  );
  X_AND3 \U5/RLS1fr_MC.D2_PT_0_1256  (
    .I0(\MSPReset_II/UIM ),
    .I1(\NlwInverterSignal_U5/RLS1fr_MC.D2_PT_0/IN1 ),
    .I2(\U5/RLS1fr ),
    .O(\U5/RLS1fr_MC.D2_PT_0 )
  );
  X_AND5 \U5/RLS1fr_MC.D2_PT_1_1257  (
    .I0(\MSPReset_II/UIM ),
    .I1(\NlwInverterSignal_U5/RLS1fr_MC.D2_PT_1/IN1 ),
    .I2(\NlwInverterSignal_U5/RLS1fr_MC.D2_PT_1/IN2 ),
    .I3(\NlwInverterSignal_U5/RLS1fr_MC.D2_PT_1/IN3 ),
    .I4(\U5/RLS1r ),
    .O(\U5/RLS1fr_MC.D2_PT_1 )
  );
  X_OR2 \U5/RLS1fr_MC.D2_1258  (
    .I0(\U5/RLS1fr_MC.D2_PT_0 ),
    .I1(\U5/RLS1fr_MC.D2_PT_1 ),
    .O(\U5/RLS1fr_MC.D2 )
  );
  X_BUF \U5/RLS1r_1259  (
    .I(\U5/RLS1r_MC.Q ),
    .O(\U5/RLS1r )
  );
  X_FF \U5/RLS1r_MC.REG  (
    .I(\U5/RLS1r_MC.D ),
    .CE(Vcc),
    .CLK(\U5/RLS1r_MC.REG_tsimcreated_inv_Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\U5/RLS1r_MC.Q )
  );
  X_INV \U5/RLS1r_MC.REG_tsimcreated_inv_Mclk_II/FCLK_1260  (
    .I(\Mclk_II/FCLK ),
    .O(\U5/RLS1r_MC.REG_tsimcreated_inv_Mclk_II/FCLK )
  );
  X_XOR2 \U5/RLS1r_MC.D_1261  (
    .I0(\U5/RLS1r_MC.D1 ),
    .I1(\U5/RLS1r_MC.D2 ),
    .O(\U5/RLS1r_MC.D )
  );
  X_AND2 \U5/RLS1r_MC.D1_1262  (
    .I0(\MSPReset_II/UIM ),
    .I1(\RLS1_II/UIM ),
    .O(\U5/RLS1r_MC.D1 )
  );
  X_ZERO \U5/RLS1r_MC.D2_1263  (
    .O(\U5/RLS1r_MC.D2 )
  );
  X_BUF \outDATA<4>\$WA4.UIM_1264  (
    .I(\outDATA<4>\$WA4.UIM_MC.Q ),
    .O(\outDATA<4>\$WA4.UIM )
  );
  X_BUF \outDATA<4>\$WA4.UIM_MC.Q_1265  (
    .I(\outDATA<4>\$WA4.UIM_MC.D ),
    .O(\outDATA<4>\$WA4.UIM_MC.Q )
  );
  X_XOR2 \outDATA<4>\$WA4.UIM_MC.D_1266  (
    .I0(\outDATA<4>\$WA4.UIM_MC.D1 ),
    .I1(\outDATA<4>\$WA4.UIM_MC.D2 ),
    .O(\outDATA<4>\$WA4.UIM_MC.D )
  );
  X_ZERO \outDATA<4>\$WA4.UIM_MC.D1_1267  (
    .O(\outDATA<4>\$WA4.UIM_MC.D1 )
  );
  X_AND2 \outDATA<4>\$WA4.UIM_MC.D2_PT_0_1268  (
    .I0(DCORLIMITSr),
    .I1(\NlwInverterSignal_outDATA<4>\$WA4.UIM_MC.D2_PT_0/IN1 ),
    .O(\outDATA<4>\$WA4.UIM_MC.D2_PT_0 )
  );
  X_AND2 \outDATA<4>\$WA4.UIM_MC.D2_PT_1_1269  (
    .I0(\NlwInverterSignal_outDATA<4>\$WA4.UIM_MC.D2_PT_1/IN0 ),
    .I1(\U5/RLS1fr ),
    .O(\outDATA<4>\$WA4.UIM_MC.D2_PT_1 )
  );
  X_OR2 \outDATA<4>\$WA4.UIM_MC.D2_1270  (
    .I0(\outDATA<4>\$WA4.UIM_MC.D2_PT_0 ),
    .I1(\outDATA<4>\$WA4.UIM_MC.D2_PT_1 ),
    .O(\outDATA<4>\$WA4.UIM_MC.D2 )
  );
  X_BUF \outDATA<4>\$WA1.UIM_1271  (
    .I(\outDATA<4>\$WA1.UIM_MC.Q ),
    .O(\outDATA<4>\$WA1.UIM )
  );
  X_BUF \outDATA<4>\$WA1.UIM_MC.Q_1272  (
    .I(\outDATA<4>\$WA1.UIM_MC.D ),
    .O(\outDATA<4>\$WA1.UIM_MC.Q )
  );
  X_XOR2 \outDATA<4>\$WA1.UIM_MC.D_1273  (
    .I0(\outDATA<4>\$WA1.UIM_MC.D1 ),
    .I1(\outDATA<4>\$WA1.UIM_MC.D2 ),
    .O(\outDATA<4>\$WA1.UIM_MC.D )
  );
  X_ZERO \outDATA<4>\$WA1.UIM_MC.D1_1274  (
    .O(\outDATA<4>\$WA1.UIM_MC.D1 )
  );
  X_AND2 \outDATA<4>\$WA1.UIM_MC.D2_PT_0_1275  (
    .I0(DCOR0CNTLOWr),
    .I1(\U1/U3/holdingreg0 [4]),
    .O(\outDATA<4>\$WA1.UIM_MC.D2_PT_0 )
  );
  X_AND3 \outDATA<4>\$WA1.UIM_MC.D2_PT_1_1276  (
    .I0(\NlwInverterSignal_outDATA<4>\$WA1.UIM_MC.D2_PT_1/IN0 ),
    .I1(DCOR1CNTLOWr),
    .I2(\U1/U3/holdingreg1 [4]),
    .O(\outDATA<4>\$WA1.UIM_MC.D2_PT_1 )
  );
  X_AND4 \outDATA<4>\$WA1.UIM_MC.D2_PT_2_1277  (
    .I0(\NlwInverterSignal_outDATA<4>\$WA1.UIM_MC.D2_PT_2/IN0 ),
    .I1(\NlwInverterSignal_outDATA<4>\$WA1.UIM_MC.D2_PT_2/IN1 ),
    .I2(DCOR0CNTHIGHr),
    .I3(\U1/U3/holdingreg0 [12]),
    .O(\outDATA<4>\$WA1.UIM_MC.D2_PT_2 )
  );
  X_AND4 \outDATA<4>\$WA1.UIM_MC.D2_PT_3_1278  (
    .I0(\NlwInverterSignal_outDATA<4>\$WA1.UIM_MC.D2_PT_3/IN0 ),
    .I1(\NlwInverterSignal_outDATA<4>\$WA1.UIM_MC.D2_PT_3/IN1 ),
    .I2(\NlwInverterSignal_outDATA<4>\$WA1.UIM_MC.D2_PT_3/IN2 ),
    .I3(\U1/U3/holdingreg1 [12]),
    .O(\outDATA<4>\$WA1.UIM_MC.D2_PT_3 )
  );
  X_OR4 \outDATA<4>\$WA1.UIM_MC.D2_1279  (
    .I0(\outDATA<4>\$WA1.UIM_MC.D2_PT_0 ),
    .I1(\outDATA<4>\$WA1.UIM_MC.D2_PT_1 ),
    .I2(\outDATA<4>\$WA1.UIM_MC.D2_PT_2 ),
    .I3(\outDATA<4>\$WA1.UIM_MC.D2_PT_3 ),
    .O(\outDATA<4>\$WA1.UIM_MC.D2 )
  );
  X_BUF \U1/U3/holdingreg0<4>  (
    .I(\U1/U3/holdingreg0<4>_MC.Q ),
    .O(\U1/U3/holdingreg0 [4])
  );
  X_FF \U1/U3/holdingreg0<4>_MC.REG  (
    .I(\U1/U3/holdingreg0<4>_MC.D ),
    .CE(Vcc),
    .CLK(\U1/U3/holdingreg0<4>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\U1/U3/holdingreg0<4>_MC.Q )
  );
  X_INV \U1/U3/holdingreg0<4>_MC.REG_tsimcreated_inv_Mclk_II/FCLK_1280  (
    .I(\Mclk_II/FCLK ),
    .O(\U1/U3/holdingreg0<4>_MC.REG_tsimcreated_inv_Mclk_II/FCLK )
  );
  X_XOR2 \U1/U3/holdingreg0<4>_MC.D_1281  (
    .I0(\U1/U3/holdingreg0<4>_MC.D1 ),
    .I1(\U1/U3/holdingreg0<4>_MC.D2 ),
    .O(\U1/U3/holdingreg0<4>_MC.D )
  );
  X_ZERO \U1/U3/holdingreg0<4>_MC.D1_1282  (
    .O(\U1/U3/holdingreg0<4>_MC.D1 )
  );
  X_AND2 \U1/U3/holdingreg0<4>_MC.D2_PT_0_1283  (
    .I0(N_PZ_992),
    .I1(\U1/U3/holdingreg0 [4]),
    .O(\U1/U3/holdingreg0<4>_MC.D2_PT_0 )
  );
  X_AND4 \U1/U3/holdingreg0<4>_MC.D2_PT_1_1284  (
    .I0(\MSPReset_II/UIM ),
    .I1(\NlwInverterSignal_U1/U3/holdingreg0<4>_MC.D2_PT_1/IN1 ),
    .I2(U2_ASedge),
    .I3(\U1/Channel0 [4]),
    .O(\U1/U3/holdingreg0<4>_MC.D2_PT_1 )
  );
  X_OR2 \U1/U3/holdingreg0<4>_MC.D2_1285  (
    .I0(\U1/U3/holdingreg0<4>_MC.D2_PT_0 ),
    .I1(\U1/U3/holdingreg0<4>_MC.D2_PT_1 ),
    .O(\U1/U3/holdingreg0<4>_MC.D2 )
  );
  X_BUF \U1/U3/holdingreg1<4>  (
    .I(\U1/U3/holdingreg1<4>_MC.Q ),
    .O(\U1/U3/holdingreg1 [4])
  );
  X_FF \U1/U3/holdingreg1<4>_MC.REG  (
    .I(\U1/U3/holdingreg1<4>_MC.D ),
    .CE(Vcc),
    .CLK(\U1/U3/holdingreg1<4>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\U1/U3/holdingreg1<4>_MC.Q )
  );
  X_INV \U1/U3/holdingreg1<4>_MC.REG_tsimcreated_inv_Mclk_II/FCLK_1286  (
    .I(\Mclk_II/FCLK ),
    .O(\U1/U3/holdingreg1<4>_MC.REG_tsimcreated_inv_Mclk_II/FCLK )
  );
  X_XOR2 \U1/U3/holdingreg1<4>_MC.D_1287  (
    .I0(\U1/U3/holdingreg1<4>_MC.D1 ),
    .I1(\U1/U3/holdingreg1<4>_MC.D2 ),
    .O(\U1/U3/holdingreg1<4>_MC.D )
  );
  X_ZERO \U1/U3/holdingreg1<4>_MC.D1_1288  (
    .O(\U1/U3/holdingreg1<4>_MC.D1 )
  );
  X_AND2 \U1/U3/holdingreg1<4>_MC.D2_PT_0_1289  (
    .I0(N_PZ_992),
    .I1(\U1/U3/holdingreg1 [4]),
    .O(\U1/U3/holdingreg1<4>_MC.D2_PT_0 )
  );
  X_AND4 \U1/U3/holdingreg1<4>_MC.D2_PT_1_1290  (
    .I0(\MSPReset_II/UIM ),
    .I1(\NlwInverterSignal_U1/U3/holdingreg1<4>_MC.D2_PT_1/IN1 ),
    .I2(U2_ASedge),
    .I3(\U1/Channel1 [4]),
    .O(\U1/U3/holdingreg1<4>_MC.D2_PT_1 )
  );
  X_OR2 \U1/U3/holdingreg1<4>_MC.D2_1291  (
    .I0(\U1/U3/holdingreg1<4>_MC.D2_PT_0 ),
    .I1(\U1/U3/holdingreg1<4>_MC.D2_PT_1 ),
    .O(\U1/U3/holdingreg1<4>_MC.D2 )
  );
  X_BUF \U1/U3/holdingreg0<12>  (
    .I(\U1/U3/holdingreg0<12>_MC.Q ),
    .O(\U1/U3/holdingreg0 [12])
  );
  X_FF \U1/U3/holdingreg0<12>_MC.REG  (
    .I(\U1/U3/holdingreg0<12>_MC.D ),
    .CE(Vcc),
    .CLK(\U1/U3/holdingreg0<12>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\U1/U3/holdingreg0<12>_MC.Q )
  );
  X_INV \U1/U3/holdingreg0<12>_MC.REG_tsimcreated_inv_Mclk_II/FCLK_1292  (
    .I(\Mclk_II/FCLK ),
    .O(\U1/U3/holdingreg0<12>_MC.REG_tsimcreated_inv_Mclk_II/FCLK )
  );
  X_XOR2 \U1/U3/holdingreg0<12>_MC.D_1293  (
    .I0(\U1/U3/holdingreg0<12>_MC.D1 ),
    .I1(\U1/U3/holdingreg0<12>_MC.D2 ),
    .O(\U1/U3/holdingreg0<12>_MC.D )
  );
  X_ZERO \U1/U3/holdingreg0<12>_MC.D1_1294  (
    .O(\U1/U3/holdingreg0<12>_MC.D1 )
  );
  X_AND2 \U1/U3/holdingreg0<12>_MC.D2_PT_0_1295  (
    .I0(N_PZ_992),
    .I1(\U1/U3/holdingreg0 [12]),
    .O(\U1/U3/holdingreg0<12>_MC.D2_PT_0 )
  );
  X_AND4 \U1/U3/holdingreg0<12>_MC.D2_PT_1_1296  (
    .I0(\MSPReset_II/UIM ),
    .I1(\NlwInverterSignal_U1/U3/holdingreg0<12>_MC.D2_PT_1/IN1 ),
    .I2(U2_ASedge),
    .I3(\U1/Channel0 [12]),
    .O(\U1/U3/holdingreg0<12>_MC.D2_PT_1 )
  );
  X_OR2 \U1/U3/holdingreg0<12>_MC.D2_1297  (
    .I0(\U1/U3/holdingreg0<12>_MC.D2_PT_0 ),
    .I1(\U1/U3/holdingreg0<12>_MC.D2_PT_1 ),
    .O(\U1/U3/holdingreg0<12>_MC.D2 )
  );
  X_BUF \U1/U3/holdingreg1<12>  (
    .I(\U1/U3/holdingreg1<12>_MC.Q ),
    .O(\U1/U3/holdingreg1 [12])
  );
  X_FF \U1/U3/holdingreg1<12>_MC.REG  (
    .I(\U1/U3/holdingreg1<12>_MC.D ),
    .CE(Vcc),
    .CLK(\U1/U3/holdingreg1<12>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\U1/U3/holdingreg1<12>_MC.Q )
  );
  X_INV \U1/U3/holdingreg1<12>_MC.REG_tsimcreated_inv_Mclk_II/FCLK_1298  (
    .I(\Mclk_II/FCLK ),
    .O(\U1/U3/holdingreg1<12>_MC.REG_tsimcreated_inv_Mclk_II/FCLK )
  );
  X_XOR2 \U1/U3/holdingreg1<12>_MC.D_1299  (
    .I0(\U1/U3/holdingreg1<12>_MC.D1 ),
    .I1(\U1/U3/holdingreg1<12>_MC.D2 ),
    .O(\U1/U3/holdingreg1<12>_MC.D )
  );
  X_ZERO \U1/U3/holdingreg1<12>_MC.D1_1300  (
    .O(\U1/U3/holdingreg1<12>_MC.D1 )
  );
  X_AND2 \U1/U3/holdingreg1<12>_MC.D2_PT_0_1301  (
    .I0(N_PZ_992),
    .I1(\U1/U3/holdingreg1 [12]),
    .O(\U1/U3/holdingreg1<12>_MC.D2_PT_0 )
  );
  X_AND4 \U1/U3/holdingreg1<12>_MC.D2_PT_1_1302  (
    .I0(\MSPReset_II/UIM ),
    .I1(\NlwInverterSignal_U1/U3/holdingreg1<12>_MC.D2_PT_1/IN1 ),
    .I2(U2_ASedge),
    .I3(\U1/Channel1 [12]),
    .O(\U1/U3/holdingreg1<12>_MC.D2_PT_1 )
  );
  X_OR2 \U1/U3/holdingreg1<12>_MC.D2_1303  (
    .I0(\U1/U3/holdingreg1<12>_MC.D2_PT_0 ),
    .I1(\U1/U3/holdingreg1<12>_MC.D2_PT_1 ),
    .O(\U1/U3/holdingreg1<12>_MC.D2 )
  );
  X_BUF \AD<5>_MC.Q_1304  (
    .I(\AD<5>_MC.Q_tsimrenamed_net_ ),
    .O(\AD<5>_MC.Q )
  );
  X_BUF \AD<5>_MC.OE_1305  (
    .I(\AD<5>_MC.BUFOE.OUT ),
    .O(\AD<5>_MC.OE )
  );
  X_BUF \AD<5>_MC.BUFOE.OUT_1306  (
    .I(\FOOBAR1__ctinst/7 ),
    .O(\AD<5>_MC.BUFOE.OUT )
  );
  X_BUF \AD<5>_MC.Q_tsimrenamed_net__1307  (
    .I(\AD<5>_MC.D ),
    .O(\AD<5>_MC.Q_tsimrenamed_net_ )
  );
  X_XOR2 \AD<5>_MC.D_1308  (
    .I0(\NlwInverterSignal_AD<5>_MC.D/IN0 ),
    .I1(\AD<5>_MC.D2 ),
    .O(\AD<5>_MC.D )
  );
  X_ZERO \AD<5>_MC.D1_1309  (
    .O(\AD<5>_MC.D1 )
  );
  X_AND2 \AD<5>_MC.D2_PT_0_1310  (
    .I0(DCORI2CCNTr),
    .I1(\NlwInverterSignal_AD<5>_MC.D2_PT_0/IN1 ),
    .O(\AD<5>_MC.D2_PT_0 )
  );
  X_AND2 \AD<5>_MC.D2_PT_1_1311  (
    .I0(DCORCONFIGr),
    .I1(\NlwInverterSignal_AD<5>_MC.D2_PT_1/IN1 ),
    .O(\AD<5>_MC.D2_PT_1 )
  );
  X_AND2 \AD<5>_MC.D2_PT_2_1312  (
    .I0(DCORENCPWRr),
    .I1(\NlwInverterSignal_AD<5>_MC.D2_PT_2/IN1 ),
    .O(\AD<5>_MC.D2_PT_2 )
  );
  X_AND2 \AD<5>_MC.D2_PT_3_1313  (
    .I0(\NlwInverterSignal_AD<5>_MC.D2_PT_3/IN0 ),
    .I1(\NlwInverterSignal_AD<5>_MC.D2_PT_3/IN1 ),
    .O(\AD<5>_MC.D2_PT_3 )
  );
  X_AND2 \AD<5>_MC.D2_PT_4_1314  (
    .I0(\NlwInverterSignal_AD<5>_MC.D2_PT_4/IN0 ),
    .I1(\NlwInverterSignal_AD<5>_MC.D2_PT_4/IN1 ),
    .O(\AD<5>_MC.D2_PT_4 )
  );
  X_AND2 \AD<5>_MC.D2_PT_5_1315  (
    .I0(\NlwInverterSignal_AD<5>_MC.D2_PT_5/IN0 ),
    .I1(\NlwInverterSignal_AD<5>_MC.D2_PT_5/IN1 ),
    .O(\AD<5>_MC.D2_PT_5 )
  );
  X_OR6 \AD<5>_MC.D2_1316  (
    .I0(\AD<5>_MC.D2_PT_0 ),
    .I1(\AD<5>_MC.D2_PT_1 ),
    .I2(\AD<5>_MC.D2_PT_2 ),
    .I3(\AD<5>_MC.D2_PT_3 ),
    .I4(\AD<5>_MC.D2_PT_4 ),
    .I5(\AD<5>_MC.D2_PT_5 ),
    .O(\AD<5>_MC.D2 )
  );
  X_BUF \outDATA<5>\$WA0.UIM_1317  (
    .I(\outDATA<5>\$WA0.UIM_MC.Q ),
    .O(\outDATA<5>\$WA0.UIM )
  );
  X_BUF \outDATA<5>\$WA0.UIM_MC.Q_1318  (
    .I(\outDATA<5>\$WA0.UIM_MC.D ),
    .O(\outDATA<5>\$WA0.UIM_MC.Q )
  );
  X_XOR2 \outDATA<5>\$WA0.UIM_MC.D_1319  (
    .I0(\outDATA<5>\$WA0.UIM_MC.D1 ),
    .I1(\outDATA<5>\$WA0.UIM_MC.D2 ),
    .O(\outDATA<5>\$WA0.UIM_MC.D )
  );
  X_AND2 \outDATA<5>\$WA0.UIM_MC.D1_1320  (
    .I0(U11_U3_counterr[5]),
    .I1(U11_U3_counterr[5]),
    .O(\outDATA<5>\$WA0.UIM_MC.D1 )
  );
  X_ZERO \outDATA<5>\$WA0.UIM_MC.D2_1321  (
    .O(\outDATA<5>\$WA0.UIM_MC.D2 )
  );
  X_BUF \outDATA<5>\$WA3.UIM_1322  (
    .I(\outDATA<5>\$WA3.UIM_MC.Q ),
    .O(\outDATA<5>\$WA3.UIM )
  );
  X_BUF \outDATA<5>\$WA3.UIM_MC.Q_1323  (
    .I(\outDATA<5>\$WA3.UIM_MC.D ),
    .O(\outDATA<5>\$WA3.UIM_MC.Q )
  );
  X_XOR2 \outDATA<5>\$WA3.UIM_MC.D_1324  (
    .I0(\outDATA<5>\$WA3.UIM_MC.D1 ),
    .I1(\outDATA<5>\$WA3.UIM_MC.D2 ),
    .O(\outDATA<5>\$WA3.UIM_MC.D )
  );
  X_AND2 \outDATA<5>\$WA3.UIM_MC.D1_1325  (
    .I0(\I2CS<5>_II/UIM ),
    .I1(\I2CS<5>_II/UIM ),
    .O(\outDATA<5>\$WA3.UIM_MC.D1 )
  );
  X_ZERO \outDATA<5>\$WA3.UIM_MC.D2_1326  (
    .O(\outDATA<5>\$WA3.UIM_MC.D2 )
  );
  X_BUF \outDATA<5>\$WA5.UIM_1327  (
    .I(\outDATA<5>\$WA5.UIM_MC.Q ),
    .O(\outDATA<5>\$WA5.UIM )
  );
  X_BUF \outDATA<5>\$WA5.UIM_MC.Q_1328  (
    .I(\outDATA<5>\$WA5.UIM_MC.D ),
    .O(\outDATA<5>\$WA5.UIM_MC.Q )
  );
  X_XOR2 \outDATA<5>\$WA5.UIM_MC.D_1329  (
    .I0(\outDATA<5>\$WA5.UIM_MC.D1 ),
    .I1(\outDATA<5>\$WA5.UIM_MC.D2 ),
    .O(\outDATA<5>\$WA5.UIM_MC.D )
  );
  X_ZERO \outDATA<5>\$WA5.UIM_MC.D1_1330  (
    .O(\outDATA<5>\$WA5.UIM_MC.D1 )
  );
  X_AND2 \outDATA<5>\$WA5.UIM_MC.D2_PT_0_1331  (
    .I0(NET2528),
    .I1(\U4/Flgreg [5]),
    .O(\outDATA<5>\$WA5.UIM_MC.D2_PT_0 )
  );
  X_AND2 \outDATA<5>\$WA5.UIM_MC.D2_PT_1_1332  (
    .I0(\NlwInverterSignal_outDATA<5>\$WA5.UIM_MC.D2_PT_1/IN0 ),
    .I1(\Home15FLG_II/UIM ),
    .O(\outDATA<5>\$WA5.UIM_MC.D2_PT_1 )
  );
  X_OR2 \outDATA<5>\$WA5.UIM_MC.D2_1333  (
    .I0(\outDATA<5>\$WA5.UIM_MC.D2_PT_0 ),
    .I1(\outDATA<5>\$WA5.UIM_MC.D2_PT_1 ),
    .O(\outDATA<5>\$WA5.UIM_MC.D2 )
  );
  X_BUF \outDATA<5>\$WA4.UIM_1334  (
    .I(\outDATA<5>\$WA4.UIM_MC.Q ),
    .O(\outDATA<5>\$WA4.UIM )
  );
  X_BUF \outDATA<5>\$WA4.UIM_MC.Q_1335  (
    .I(\outDATA<5>\$WA4.UIM_MC.D ),
    .O(\outDATA<5>\$WA4.UIM_MC.Q )
  );
  X_XOR2 \outDATA<5>\$WA4.UIM_MC.D_1336  (
    .I0(\outDATA<5>\$WA4.UIM_MC.D1 ),
    .I1(\outDATA<5>\$WA4.UIM_MC.D2 ),
    .O(\outDATA<5>\$WA4.UIM_MC.D )
  );
  X_ZERO \outDATA<5>\$WA4.UIM_MC.D1_1337  (
    .O(\outDATA<5>\$WA4.UIM_MC.D1 )
  );
  X_AND2 \outDATA<5>\$WA4.UIM_MC.D2_PT_0_1338  (
    .I0(DCORLIMITSr),
    .I1(\NlwInverterSignal_outDATA<5>\$WA4.UIM_MC.D2_PT_0/IN1 ),
    .O(\outDATA<5>\$WA4.UIM_MC.D2_PT_0 )
  );
  X_AND2 \outDATA<5>\$WA4.UIM_MC.D2_PT_1_1339  (
    .I0(\NlwInverterSignal_outDATA<5>\$WA4.UIM_MC.D2_PT_1/IN0 ),
    .I1(\U5/FLS1fr ),
    .O(\outDATA<5>\$WA4.UIM_MC.D2_PT_1 )
  );
  X_OR2 \outDATA<5>\$WA4.UIM_MC.D2_1340  (
    .I0(\outDATA<5>\$WA4.UIM_MC.D2_PT_0 ),
    .I1(\outDATA<5>\$WA4.UIM_MC.D2_PT_1 ),
    .O(\outDATA<5>\$WA4.UIM_MC.D2 )
  );
  X_BUF \outDATA<5>\$WA1.UIM_1341  (
    .I(\outDATA<5>\$WA1.UIM_MC.Q ),
    .O(\outDATA<5>\$WA1.UIM )
  );
  X_BUF \outDATA<5>\$WA1.UIM_MC.Q_1342  (
    .I(\outDATA<5>\$WA1.UIM_MC.D ),
    .O(\outDATA<5>\$WA1.UIM_MC.Q )
  );
  X_XOR2 \outDATA<5>\$WA1.UIM_MC.D_1343  (
    .I0(\outDATA<5>\$WA1.UIM_MC.D1 ),
    .I1(\outDATA<5>\$WA1.UIM_MC.D2 ),
    .O(\outDATA<5>\$WA1.UIM_MC.D )
  );
  X_ZERO \outDATA<5>\$WA1.UIM_MC.D1_1344  (
    .O(\outDATA<5>\$WA1.UIM_MC.D1 )
  );
  X_AND2 \outDATA<5>\$WA1.UIM_MC.D2_PT_0_1345  (
    .I0(DCOR0CNTLOWr),
    .I1(\U1/U3/holdingreg0 [5]),
    .O(\outDATA<5>\$WA1.UIM_MC.D2_PT_0 )
  );
  X_AND3 \outDATA<5>\$WA1.UIM_MC.D2_PT_1_1346  (
    .I0(\NlwInverterSignal_outDATA<5>\$WA1.UIM_MC.D2_PT_1/IN0 ),
    .I1(DCOR1CNTLOWr),
    .I2(\U1/U3/holdingreg1 [5]),
    .O(\outDATA<5>\$WA1.UIM_MC.D2_PT_1 )
  );
  X_AND4 \outDATA<5>\$WA1.UIM_MC.D2_PT_2_1347  (
    .I0(\NlwInverterSignal_outDATA<5>\$WA1.UIM_MC.D2_PT_2/IN0 ),
    .I1(\NlwInverterSignal_outDATA<5>\$WA1.UIM_MC.D2_PT_2/IN1 ),
    .I2(DCOR0CNTHIGHr),
    .I3(\U1/U3/holdingreg0 [13]),
    .O(\outDATA<5>\$WA1.UIM_MC.D2_PT_2 )
  );
  X_AND4 \outDATA<5>\$WA1.UIM_MC.D2_PT_3_1348  (
    .I0(\NlwInverterSignal_outDATA<5>\$WA1.UIM_MC.D2_PT_3/IN0 ),
    .I1(\NlwInverterSignal_outDATA<5>\$WA1.UIM_MC.D2_PT_3/IN1 ),
    .I2(\NlwInverterSignal_outDATA<5>\$WA1.UIM_MC.D2_PT_3/IN2 ),
    .I3(\U1/U3/holdingreg1 [13]),
    .O(\outDATA<5>\$WA1.UIM_MC.D2_PT_3 )
  );
  X_OR4 \outDATA<5>\$WA1.UIM_MC.D2_1349  (
    .I0(\outDATA<5>\$WA1.UIM_MC.D2_PT_0 ),
    .I1(\outDATA<5>\$WA1.UIM_MC.D2_PT_1 ),
    .I2(\outDATA<5>\$WA1.UIM_MC.D2_PT_2 ),
    .I3(\outDATA<5>\$WA1.UIM_MC.D2_PT_3 ),
    .O(\outDATA<5>\$WA1.UIM_MC.D2 )
  );
  X_BUF \U1/U3/holdingreg0<5>  (
    .I(\U1/U3/holdingreg0<5>_MC.Q ),
    .O(\U1/U3/holdingreg0 [5])
  );
  X_FF \U1/U3/holdingreg0<5>_MC.REG  (
    .I(\U1/U3/holdingreg0<5>_MC.D ),
    .CE(Vcc),
    .CLK(\U1/U3/holdingreg0<5>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\U1/U3/holdingreg0<5>_MC.Q )
  );
  X_INV \U1/U3/holdingreg0<5>_MC.REG_tsimcreated_inv_Mclk_II/FCLK_1350  (
    .I(\Mclk_II/FCLK ),
    .O(\U1/U3/holdingreg0<5>_MC.REG_tsimcreated_inv_Mclk_II/FCLK )
  );
  X_XOR2 \U1/U3/holdingreg0<5>_MC.D_1351  (
    .I0(\U1/U3/holdingreg0<5>_MC.D1 ),
    .I1(\U1/U3/holdingreg0<5>_MC.D2 ),
    .O(\U1/U3/holdingreg0<5>_MC.D )
  );
  X_ZERO \U1/U3/holdingreg0<5>_MC.D1_1352  (
    .O(\U1/U3/holdingreg0<5>_MC.D1 )
  );
  X_AND2 \U1/U3/holdingreg0<5>_MC.D2_PT_0_1353  (
    .I0(N_PZ_992),
    .I1(\U1/U3/holdingreg0 [5]),
    .O(\U1/U3/holdingreg0<5>_MC.D2_PT_0 )
  );
  X_AND4 \U1/U3/holdingreg0<5>_MC.D2_PT_1_1354  (
    .I0(\MSPReset_II/UIM ),
    .I1(\NlwInverterSignal_U1/U3/holdingreg0<5>_MC.D2_PT_1/IN1 ),
    .I2(U2_ASedge),
    .I3(\U1/Channel0 [5]),
    .O(\U1/U3/holdingreg0<5>_MC.D2_PT_1 )
  );
  X_OR2 \U1/U3/holdingreg0<5>_MC.D2_1355  (
    .I0(\U1/U3/holdingreg0<5>_MC.D2_PT_0 ),
    .I1(\U1/U3/holdingreg0<5>_MC.D2_PT_1 ),
    .O(\U1/U3/holdingreg0<5>_MC.D2 )
  );
  X_BUF \U1/U3/holdingreg1<5>  (
    .I(\U1/U3/holdingreg1<5>_MC.Q ),
    .O(\U1/U3/holdingreg1 [5])
  );
  X_FF \U1/U3/holdingreg1<5>_MC.REG  (
    .I(\U1/U3/holdingreg1<5>_MC.D ),
    .CE(Vcc),
    .CLK(\U1/U3/holdingreg1<5>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\U1/U3/holdingreg1<5>_MC.Q )
  );
  X_INV \U1/U3/holdingreg1<5>_MC.REG_tsimcreated_inv_Mclk_II/FCLK_1356  (
    .I(\Mclk_II/FCLK ),
    .O(\U1/U3/holdingreg1<5>_MC.REG_tsimcreated_inv_Mclk_II/FCLK )
  );
  X_XOR2 \U1/U3/holdingreg1<5>_MC.D_1357  (
    .I0(\U1/U3/holdingreg1<5>_MC.D1 ),
    .I1(\U1/U3/holdingreg1<5>_MC.D2 ),
    .O(\U1/U3/holdingreg1<5>_MC.D )
  );
  X_ZERO \U1/U3/holdingreg1<5>_MC.D1_1358  (
    .O(\U1/U3/holdingreg1<5>_MC.D1 )
  );
  X_AND2 \U1/U3/holdingreg1<5>_MC.D2_PT_0_1359  (
    .I0(N_PZ_992),
    .I1(\U1/U3/holdingreg1 [5]),
    .O(\U1/U3/holdingreg1<5>_MC.D2_PT_0 )
  );
  X_AND4 \U1/U3/holdingreg1<5>_MC.D2_PT_1_1360  (
    .I0(\MSPReset_II/UIM ),
    .I1(\NlwInverterSignal_U1/U3/holdingreg1<5>_MC.D2_PT_1/IN1 ),
    .I2(U2_ASedge),
    .I3(\U1/Channel1 [5]),
    .O(\U1/U3/holdingreg1<5>_MC.D2_PT_1 )
  );
  X_OR2 \U1/U3/holdingreg1<5>_MC.D2_1361  (
    .I0(\U1/U3/holdingreg1<5>_MC.D2_PT_0 ),
    .I1(\U1/U3/holdingreg1<5>_MC.D2_PT_1 ),
    .O(\U1/U3/holdingreg1<5>_MC.D2 )
  );
  X_BUF \U1/U3/holdingreg0<13>  (
    .I(\U1/U3/holdingreg0<13>_MC.Q ),
    .O(\U1/U3/holdingreg0 [13])
  );
  X_FF \U1/U3/holdingreg0<13>_MC.REG  (
    .I(\U1/U3/holdingreg0<13>_MC.D ),
    .CE(Vcc),
    .CLK(\U1/U3/holdingreg0<13>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\U1/U3/holdingreg0<13>_MC.Q )
  );
  X_INV \U1/U3/holdingreg0<13>_MC.REG_tsimcreated_inv_Mclk_II/FCLK_1362  (
    .I(\Mclk_II/FCLK ),
    .O(\U1/U3/holdingreg0<13>_MC.REG_tsimcreated_inv_Mclk_II/FCLK )
  );
  X_XOR2 \U1/U3/holdingreg0<13>_MC.D_1363  (
    .I0(\U1/U3/holdingreg0<13>_MC.D1 ),
    .I1(\U1/U3/holdingreg0<13>_MC.D2 ),
    .O(\U1/U3/holdingreg0<13>_MC.D )
  );
  X_ZERO \U1/U3/holdingreg0<13>_MC.D1_1364  (
    .O(\U1/U3/holdingreg0<13>_MC.D1 )
  );
  X_AND2 \U1/U3/holdingreg0<13>_MC.D2_PT_0_1365  (
    .I0(N_PZ_992),
    .I1(\U1/U3/holdingreg0 [13]),
    .O(\U1/U3/holdingreg0<13>_MC.D2_PT_0 )
  );
  X_AND4 \U1/U3/holdingreg0<13>_MC.D2_PT_1_1366  (
    .I0(\MSPReset_II/UIM ),
    .I1(\NlwInverterSignal_U1/U3/holdingreg0<13>_MC.D2_PT_1/IN1 ),
    .I2(U2_ASedge),
    .I3(\U1/Channel0 [13]),
    .O(\U1/U3/holdingreg0<13>_MC.D2_PT_1 )
  );
  X_OR2 \U1/U3/holdingreg0<13>_MC.D2_1367  (
    .I0(\U1/U3/holdingreg0<13>_MC.D2_PT_0 ),
    .I1(\U1/U3/holdingreg0<13>_MC.D2_PT_1 ),
    .O(\U1/U3/holdingreg0<13>_MC.D2 )
  );
  X_BUF \U1/Channel0<13>  (
    .I(\U1/Channel0<13>_MC.Q ),
    .O(\U1/Channel0 [13])
  );
  X_XOR2 \U1/Channel0<13>_MC_tsimcreated_xor__1368  (
    .I0(\U1/Channel0<13>_MC.D ),
    .I1(\U1/Channel0<13>_MC.Q ),
    .O(\U1/Channel0<13>_MC_tsimcreated_xor_ )
  );
  X_FF \U1/Channel0<13>_MC.REG  (
    .I(\U1/Channel0<13>_MC_tsimcreated_xor_ ),
    .CE(Vcc),
    .CLK(\Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\U1/Channel0<13>_MC.Q )
  );
  X_XOR2 \U1/Channel0<13>_MC.D_1369  (
    .I0(\U1/Channel0<13>_MC.D1 ),
    .I1(\U1/Channel0<13>_MC.D2 ),
    .O(\U1/Channel0<13>_MC.D )
  );
  X_ZERO \U1/Channel0<13>_MC.D1_1370  (
    .O(\U1/Channel0<13>_MC.D1 )
  );
  X_AND2 \U1/Channel0<13>_MC.D2_PT_0_1371  (
    .I0(\NlwInverterSignal_U1/Channel0<13>_MC.D2_PT_0/IN0 ),
    .I1(\U1/Channel0 [13]),
    .O(\U1/Channel0<13>_MC.D2_PT_0 )
  );
  X_AND6 \U1/Channel0<13>_MC.D2_PT_1_1372  (
    .I0(\U1/U2/location_Maddsub__n0000__n0075 [0]),
    .I1(N_PZ_1021),
    .I2(\NlwInverterSignal_U1/Channel0<13>_MC.D2_PT_1/IN2 ),
    .I3(\NlwInverterSignal_U1/Channel0<13>_MC.D2_PT_1/IN3 ),
    .I4(\NlwInverterSignal_U1/Channel0<13>_MC.D2_PT_1/IN4 ),
    .I5(\NlwInverterSignal_U1/Channel0<13>_MC.D2_PT_1/IN5 ),
    .O(\U1/Channel0<13>_MC.D2_PT_1 )
  );
  X_AND6 \U1/Channel0<13>_MC.D2_PT_2_1373  (
    .I0(\NlwInverterSignal_U1/Channel0<13>_MC.D2_PT_2/IN0 ),
    .I1(N_PZ_1024),
    .I2(\U1/Channel0 [9]),
    .I3(\U1/Channel0 [12]),
    .I4(\U1/Channel0 [10]),
    .I5(\U1/Channel0 [11]),
    .O(\U1/Channel0<13>_MC.D2_PT_2 )
  );
  X_OR3 \U1/Channel0<13>_MC.D2_1374  (
    .I0(\U1/Channel0<13>_MC.D2_PT_0 ),
    .I1(\U1/Channel0<13>_MC.D2_PT_1 ),
    .I2(\U1/Channel0<13>_MC.D2_PT_2 ),
    .O(\U1/Channel0<13>_MC.D2 )
  );
  X_BUF \U1/U3/holdingreg1<13>  (
    .I(\U1/U3/holdingreg1<13>_MC.Q ),
    .O(\U1/U3/holdingreg1 [13])
  );
  X_FF \U1/U3/holdingreg1<13>_MC.REG  (
    .I(\U1/U3/holdingreg1<13>_MC.D ),
    .CE(Vcc),
    .CLK(\U1/U3/holdingreg1<13>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\U1/U3/holdingreg1<13>_MC.Q )
  );
  X_INV \U1/U3/holdingreg1<13>_MC.REG_tsimcreated_inv_Mclk_II/FCLK_1375  (
    .I(\Mclk_II/FCLK ),
    .O(\U1/U3/holdingreg1<13>_MC.REG_tsimcreated_inv_Mclk_II/FCLK )
  );
  X_XOR2 \U1/U3/holdingreg1<13>_MC.D_1376  (
    .I0(\U1/U3/holdingreg1<13>_MC.D1 ),
    .I1(\U1/U3/holdingreg1<13>_MC.D2 ),
    .O(\U1/U3/holdingreg1<13>_MC.D )
  );
  X_ZERO \U1/U3/holdingreg1<13>_MC.D1_1377  (
    .O(\U1/U3/holdingreg1<13>_MC.D1 )
  );
  X_AND2 \U1/U3/holdingreg1<13>_MC.D2_PT_0_1378  (
    .I0(N_PZ_992),
    .I1(\U1/U3/holdingreg1 [13]),
    .O(\U1/U3/holdingreg1<13>_MC.D2_PT_0 )
  );
  X_AND4 \U1/U3/holdingreg1<13>_MC.D2_PT_1_1379  (
    .I0(\MSPReset_II/UIM ),
    .I1(\NlwInverterSignal_U1/U3/holdingreg1<13>_MC.D2_PT_1/IN1 ),
    .I2(U2_ASedge),
    .I3(\U1/Channel1 [13]),
    .O(\U1/U3/holdingreg1<13>_MC.D2_PT_1 )
  );
  X_OR2 \U1/U3/holdingreg1<13>_MC.D2_1380  (
    .I0(\U1/U3/holdingreg1<13>_MC.D2_PT_0 ),
    .I1(\U1/U3/holdingreg1<13>_MC.D2_PT_1 ),
    .O(\U1/U3/holdingreg1<13>_MC.D2 )
  );
  X_BUF \U1/Channel1<13>  (
    .I(\U1/Channel1<13>_MC.Q ),
    .O(\U1/Channel1 [13])
  );
  X_XOR2 \U1/Channel1<13>_MC_tsimcreated_xor__1381  (
    .I0(\U1/Channel1<13>_MC.D ),
    .I1(\U1/Channel1<13>_MC.Q ),
    .O(\U1/Channel1<13>_MC_tsimcreated_xor_ )
  );
  X_FF \U1/Channel1<13>_MC.REG  (
    .I(\U1/Channel1<13>_MC_tsimcreated_xor_ ),
    .CE(Vcc),
    .CLK(\Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\U1/Channel1<13>_MC.Q )
  );
  X_XOR2 \U1/Channel1<13>_MC.D_1382  (
    .I0(\U1/Channel1<13>_MC.D1 ),
    .I1(\U1/Channel1<13>_MC.D2 ),
    .O(\U1/Channel1<13>_MC.D )
  );
  X_ZERO \U1/Channel1<13>_MC.D1_1383  (
    .O(\U1/Channel1<13>_MC.D1 )
  );
  X_AND2 \U1/Channel1<13>_MC.D2_PT_0_1384  (
    .I0(\NlwInverterSignal_U1/Channel1<13>_MC.D2_PT_0/IN0 ),
    .I1(\U1/Channel1 [13]),
    .O(\U1/Channel1<13>_MC.D2_PT_0 )
  );
  X_AND16 \U1/Channel1<13>_MC.D2_PT_1_1385  (
    .I0(\MSPReset_II/UIM ),
    .I1(\NlwInverterSignal_U1/Channel1<13>_MC.D2_PT_1/IN1 ),
    .I2(\U1/U6/CurrState_Sreg0_FFD3 ),
    .I3(\NlwInverterSignal_U1/Channel1<13>_MC.D2_PT_1/IN3 ),
    .I4(N_PZ_975),
    .I5(\NlwInverterSignal_U1/Channel1<13>_MC.D2_PT_1/IN5 ),
    .I6(\U1/Channel1 [9]),
    .I7(\U1/Channel1 [12]),
    .I8(\U1/Channel1 [10]),
    .I9(\U1/Channel1 [11]),
    .I10(Vcc),
    .I11(Vcc),
    .I12(Vcc),
    .I13(Vcc),
    .I14(Vcc),
    .I15(Vcc),
    .O(\U1/Channel1<13>_MC.D2_PT_1 )
  );
  X_AND16 \U1/Channel1<13>_MC.D2_PT_2_1386  (
    .I0(\MSPReset_II/UIM ),
    .I1(\NlwInverterSignal_U1/Channel1<13>_MC.D2_PT_2/IN1 ),
    .I2(\U1/U6/CurrState_Sreg0_FFD3 ),
    .I3(\NlwInverterSignal_U1/Channel1<13>_MC.D2_PT_2/IN3 ),
    .I4(N_PZ_1154),
    .I5(\NlwInverterSignal_U1/Channel1<13>_MC.D2_PT_2/IN5 ),
    .I6(\U1/U5/location_Maddsub__n0000__n0075 [0]),
    .I7(\NlwInverterSignal_U1/Channel1<13>_MC.D2_PT_2/IN7 ),
    .I8(\NlwInverterSignal_U1/Channel1<13>_MC.D2_PT_2/IN8 ),
    .I9(\NlwInverterSignal_U1/Channel1<13>_MC.D2_PT_2/IN9 ),
    .I10(\NlwInverterSignal_U1/Channel1<13>_MC.D2_PT_2/IN10 ),
    .I11(Vcc),
    .I12(Vcc),
    .I13(Vcc),
    .I14(Vcc),
    .I15(Vcc),
    .O(\U1/Channel1<13>_MC.D2_PT_2 )
  );
  X_OR3 \U1/Channel1<13>_MC.D2_1387  (
    .I0(\U1/Channel1<13>_MC.D2_PT_0 ),
    .I1(\U1/Channel1<13>_MC.D2_PT_1 ),
    .I2(\U1/Channel1<13>_MC.D2_PT_2 ),
    .O(\U1/Channel1<13>_MC.D2 )
  );
  X_BUF \outDATA<5>\$WA2.UIM_1388  (
    .I(\outDATA<5>\$WA2.UIM_MC.Q ),
    .O(\outDATA<5>\$WA2.UIM )
  );
  X_BUF \outDATA<5>\$WA2.UIM_MC.Q_1389  (
    .I(\outDATA<5>\$WA2.UIM_MC.D ),
    .O(\outDATA<5>\$WA2.UIM_MC.Q )
  );
  X_XOR2 \outDATA<5>\$WA2.UIM_MC.D_1390  (
    .I0(\outDATA<5>\$WA2.UIM_MC.D1 ),
    .I1(\outDATA<5>\$WA2.UIM_MC.D2 ),
    .O(\outDATA<5>\$WA2.UIM_MC.D )
  );
  X_ZERO \outDATA<5>\$WA2.UIM_MC.D1_1391  (
    .O(\outDATA<5>\$WA2.UIM_MC.D1 )
  );
  X_AND2 \outDATA<5>\$WA2.UIM_MC.D2_PT_0_1392  (
    .I0(DCOR0THRESLOWr),
    .I1(\U1/U4/Latch0r [5]),
    .O(\outDATA<5>\$WA2.UIM_MC.D2_PT_0 )
  );
  X_AND3 \outDATA<5>\$WA2.UIM_MC.D2_PT_1_1393  (
    .I0(\NlwInverterSignal_outDATA<5>\$WA2.UIM_MC.D2_PT_1/IN0 ),
    .I1(DCORIFGr),
    .I2(NET2501),
    .O(\outDATA<5>\$WA2.UIM_MC.D2_PT_1 )
  );
  X_AND4 \outDATA<5>\$WA2.UIM_MC.D2_PT_2_1394  (
    .I0(\NlwInverterSignal_outDATA<5>\$WA2.UIM_MC.D2_PT_2/IN0 ),
    .I1(\NlwInverterSignal_outDATA<5>\$WA2.UIM_MC.D2_PT_2/IN1 ),
    .I2(DCOR0THRESHIGHr),
    .I3(\U1/U4/Latch0r [13]),
    .O(\outDATA<5>\$WA2.UIM_MC.D2_PT_2 )
  );
  X_AND5 \outDATA<5>\$WA2.UIM_MC.D2_PT_3_1395  (
    .I0(\NlwInverterSignal_outDATA<5>\$WA2.UIM_MC.D2_PT_3/IN0 ),
    .I1(\NlwInverterSignal_outDATA<5>\$WA2.UIM_MC.D2_PT_3/IN1 ),
    .I2(\NlwInverterSignal_outDATA<5>\$WA2.UIM_MC.D2_PT_3/IN2 ),
    .I3(DCOR1THRESLOWr),
    .I4(\U1/U4/Latch1r [5]),
    .O(\outDATA<5>\$WA2.UIM_MC.D2_PT_3 )
  );
  X_AND5 \outDATA<5>\$WA2.UIM_MC.D2_PT_4_1396  (
    .I0(\NlwInverterSignal_outDATA<5>\$WA2.UIM_MC.D2_PT_4/IN0 ),
    .I1(\NlwInverterSignal_outDATA<5>\$WA2.UIM_MC.D2_PT_4/IN1 ),
    .I2(\NlwInverterSignal_outDATA<5>\$WA2.UIM_MC.D2_PT_4/IN2 ),
    .I3(\NlwInverterSignal_outDATA<5>\$WA2.UIM_MC.D2_PT_4/IN3 ),
    .I4(\U1/U4/Latch1r [13]),
    .O(\outDATA<5>\$WA2.UIM_MC.D2_PT_4 )
  );
  X_OR5 \outDATA<5>\$WA2.UIM_MC.D2_1397  (
    .I0(\outDATA<5>\$WA2.UIM_MC.D2_PT_0 ),
    .I1(\outDATA<5>\$WA2.UIM_MC.D2_PT_1 ),
    .I2(\outDATA<5>\$WA2.UIM_MC.D2_PT_2 ),
    .I3(\outDATA<5>\$WA2.UIM_MC.D2_PT_3 ),
    .I4(\outDATA<5>\$WA2.UIM_MC.D2_PT_4 ),
    .O(\outDATA<5>\$WA2.UIM_MC.D2 )
  );
  X_BUF \U1/U4/Latch0r<5>  (
    .I(\U1/U4/Latch0r<5>_MC.Q ),
    .O(\U1/U4/Latch0r [5])
  );
  X_FF \U1/U4/Latch0r<5>_MC.REG  (
    .I(\U1/U4/Latch0r<5>_MC.D ),
    .CE(Vcc),
    .CLK(\U1/U4/Latch0r<5>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\U1/U4/Latch0r<5>_MC.Q )
  );
  X_INV \U1/U4/Latch0r<5>_MC.REG_tsimcreated_inv_Mclk_II/FCLK_1398  (
    .I(\Mclk_II/FCLK ),
    .O(\U1/U4/Latch0r<5>_MC.REG_tsimcreated_inv_Mclk_II/FCLK )
  );
  X_XOR2 \U1/U4/Latch0r<5>_MC.D_1399  (
    .I0(\U1/U4/Latch0r<5>_MC.D1 ),
    .I1(\U1/U4/Latch0r<5>_MC.D2 ),
    .O(\U1/U4/Latch0r<5>_MC.D )
  );
  X_ZERO \U1/U4/Latch0r<5>_MC.D1_1400  (
    .O(\U1/U4/Latch0r<5>_MC.D1 )
  );
  X_AND3 \U1/U4/Latch0r<5>_MC.D2_PT_0_1401  (
    .I0(\MSPReset_II/UIM ),
    .I1(N_PZ_1018),
    .I2(\U1/Channel0 [5]),
    .O(\U1/U4/Latch0r<5>_MC.D2_PT_0 )
  );
  X_AND3 \U1/U4/Latch0r<5>_MC.D2_PT_1_1402  (
    .I0(\MSPReset_II/UIM ),
    .I1(\NlwInverterSignal_U1/U4/Latch0r<5>_MC.D2_PT_1/IN1 ),
    .I2(\U1/U4/Latch0r [5]),
    .O(\U1/U4/Latch0r<5>_MC.D2_PT_1 )
  );
  X_OR2 \U1/U4/Latch0r<5>_MC.D2_1403  (
    .I0(\U1/U4/Latch0r<5>_MC.D2_PT_0 ),
    .I1(\U1/U4/Latch0r<5>_MC.D2_PT_1 ),
    .O(\U1/U4/Latch0r<5>_MC.D2 )
  );
  X_BUF \U1/U4/Latch0r<13>  (
    .I(\U1/U4/Latch0r<13>_MC.Q ),
    .O(\U1/U4/Latch0r [13])
  );
  X_FF \U1/U4/Latch0r<13>_MC.REG  (
    .I(\U1/U4/Latch0r<13>_MC.D ),
    .CE(Vcc),
    .CLK(\U1/U4/Latch0r<13>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\U1/U4/Latch0r<13>_MC.Q )
  );
  X_INV \U1/U4/Latch0r<13>_MC.REG_tsimcreated_inv_Mclk_II/FCLK_1404  (
    .I(\Mclk_II/FCLK ),
    .O(\U1/U4/Latch0r<13>_MC.REG_tsimcreated_inv_Mclk_II/FCLK )
  );
  X_XOR2 \U1/U4/Latch0r<13>_MC.D_1405  (
    .I0(\U1/U4/Latch0r<13>_MC.D1 ),
    .I1(\U1/U4/Latch0r<13>_MC.D2 ),
    .O(\U1/U4/Latch0r<13>_MC.D )
  );
  X_ZERO \U1/U4/Latch0r<13>_MC.D1_1406  (
    .O(\U1/U4/Latch0r<13>_MC.D1 )
  );
  X_AND3 \U1/U4/Latch0r<13>_MC.D2_PT_0_1407  (
    .I0(\MSPReset_II/UIM ),
    .I1(N_PZ_1018),
    .I2(\U1/Channel0 [13]),
    .O(\U1/U4/Latch0r<13>_MC.D2_PT_0 )
  );
  X_AND3 \U1/U4/Latch0r<13>_MC.D2_PT_1_1408  (
    .I0(\MSPReset_II/UIM ),
    .I1(\NlwInverterSignal_U1/U4/Latch0r<13>_MC.D2_PT_1/IN1 ),
    .I2(\U1/U4/Latch0r [13]),
    .O(\U1/U4/Latch0r<13>_MC.D2_PT_1 )
  );
  X_OR2 \U1/U4/Latch0r<13>_MC.D2_1409  (
    .I0(\U1/U4/Latch0r<13>_MC.D2_PT_0 ),
    .I1(\U1/U4/Latch0r<13>_MC.D2_PT_1 ),
    .O(\U1/U4/Latch0r<13>_MC.D2 )
  );
  X_BUF \U1/U4/Latch1r<5>  (
    .I(\U1/U4/Latch1r<5>_MC.Q ),
    .O(\U1/U4/Latch1r [5])
  );
  X_FF \U1/U4/Latch1r<5>_MC.REG  (
    .I(\U1/U4/Latch1r<5>_MC.D ),
    .CE(Vcc),
    .CLK(\U1/U4/Latch1r<5>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\U1/U4/Latch1r<5>_MC.Q )
  );
  X_INV \U1/U4/Latch1r<5>_MC.REG_tsimcreated_inv_Mclk_II/FCLK_1410  (
    .I(\Mclk_II/FCLK ),
    .O(\U1/U4/Latch1r<5>_MC.REG_tsimcreated_inv_Mclk_II/FCLK )
  );
  X_XOR2 \U1/U4/Latch1r<5>_MC.D_1411  (
    .I0(\U1/U4/Latch1r<5>_MC.D1 ),
    .I1(\U1/U4/Latch1r<5>_MC.D2 ),
    .O(\U1/U4/Latch1r<5>_MC.D )
  );
  X_ZERO \U1/U4/Latch1r<5>_MC.D1_1412  (
    .O(\U1/U4/Latch1r<5>_MC.D1 )
  );
  X_AND3 \U1/U4/Latch1r<5>_MC.D2_PT_0_1413  (
    .I0(\MSPReset_II/UIM ),
    .I1(N_PZ_1019),
    .I2(\U1/Channel1 [5]),
    .O(\U1/U4/Latch1r<5>_MC.D2_PT_0 )
  );
  X_AND3 \U1/U4/Latch1r<5>_MC.D2_PT_1_1414  (
    .I0(\MSPReset_II/UIM ),
    .I1(\NlwInverterSignal_U1/U4/Latch1r<5>_MC.D2_PT_1/IN1 ),
    .I2(\U1/U4/Latch1r [5]),
    .O(\U1/U4/Latch1r<5>_MC.D2_PT_1 )
  );
  X_OR2 \U1/U4/Latch1r<5>_MC.D2_1415  (
    .I0(\U1/U4/Latch1r<5>_MC.D2_PT_0 ),
    .I1(\U1/U4/Latch1r<5>_MC.D2_PT_1 ),
    .O(\U1/U4/Latch1r<5>_MC.D2 )
  );
  X_BUF \U1/U4/Latch1r<13>  (
    .I(\U1/U4/Latch1r<13>_MC.Q ),
    .O(\U1/U4/Latch1r [13])
  );
  X_FF \U1/U4/Latch1r<13>_MC.REG  (
    .I(\U1/U4/Latch1r<13>_MC.D ),
    .CE(Vcc),
    .CLK(\U1/U4/Latch1r<13>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\U1/U4/Latch1r<13>_MC.Q )
  );
  X_INV \U1/U4/Latch1r<13>_MC.REG_tsimcreated_inv_Mclk_II/FCLK_1416  (
    .I(\Mclk_II/FCLK ),
    .O(\U1/U4/Latch1r<13>_MC.REG_tsimcreated_inv_Mclk_II/FCLK )
  );
  X_XOR2 \U1/U4/Latch1r<13>_MC.D_1417  (
    .I0(\U1/U4/Latch1r<13>_MC.D1 ),
    .I1(\U1/U4/Latch1r<13>_MC.D2 ),
    .O(\U1/U4/Latch1r<13>_MC.D )
  );
  X_ZERO \U1/U4/Latch1r<13>_MC.D1_1418  (
    .O(\U1/U4/Latch1r<13>_MC.D1 )
  );
  X_AND3 \U1/U4/Latch1r<13>_MC.D2_PT_0_1419  (
    .I0(\MSPReset_II/UIM ),
    .I1(N_PZ_1019),
    .I2(\U1/Channel1 [13]),
    .O(\U1/U4/Latch1r<13>_MC.D2_PT_0 )
  );
  X_AND3 \U1/U4/Latch1r<13>_MC.D2_PT_1_1420  (
    .I0(\MSPReset_II/UIM ),
    .I1(\NlwInverterSignal_U1/U4/Latch1r<13>_MC.D2_PT_1/IN1 ),
    .I2(\U1/U4/Latch1r [13]),
    .O(\U1/U4/Latch1r<13>_MC.D2_PT_1 )
  );
  X_OR2 \U1/U4/Latch1r<13>_MC.D2_1421  (
    .I0(\U1/U4/Latch1r<13>_MC.D2_PT_0 ),
    .I1(\U1/U4/Latch1r<13>_MC.D2_PT_1 ),
    .O(\U1/U4/Latch1r<13>_MC.D2 )
  );
  X_BUF \Enc033ctrl_MC.Q_1422  (
    .I(\Enc033ctrl_MC.Q_tsimrenamed_net_ ),
    .O(\Enc033ctrl_MC.Q )
  );
  X_BUF \Enc033ctrl_MC.Q_tsimrenamed_net__1423  (
    .I(\Enc033ctrl_MC.D ),
    .O(\Enc033ctrl_MC.Q_tsimrenamed_net_ )
  );
  X_XOR2 \Enc033ctrl_MC.D_1424  (
    .I0(\NlwInverterSignal_Enc033ctrl_MC.D/IN0 ),
    .I1(\Enc033ctrl_MC.D2 ),
    .O(\Enc033ctrl_MC.D )
  );
  X_AND2 \Enc033ctrl_MC.D1_1425  (
    .I0(\U4/ctrlr[2] ),
    .I1(\NlwInverterSignal_Enc033ctrl_MC.D1/IN1 ),
    .O(\Enc033ctrl_MC.D1 )
  );
  X_ZERO \Enc033ctrl_MC.D2_1426  (
    .O(\Enc033ctrl_MC.D2 )
  );
  X_BUF \U4/ctrlr<2>_MC.Q_1427  (
    .I(\U4/ctrlr<2>_MC.D ),
    .O(\U4/ctrlr<2>_MC.Q )
  );
  X_BUF \U4/ctrlr<2>_MC.OE_1428  (
    .I(\U4/ctrlr<2>_MC.BUFOE.OUT ),
    .O(\U4/ctrlr<2>_MC.OE )
  );
  X_BUF \U4/ctrlr<2>_MC.BUFOE.OUT_1429  (
    .I(\FOOBAR1__ctinst/7 ),
    .O(\U4/ctrlr<2>_MC.BUFOE.OUT )
  );
  X_XOR2 \U4/ctrlr<2>_MC.D_1430  (
    .I0(\NlwInverterSignal_U4/ctrlr<2>_MC.D/IN0 ),
    .I1(\U4/ctrlr<2>_MC.D2 ),
    .O(\U4/ctrlr<2>_MC.D )
  );
  X_ZERO \U4/ctrlr<2>_MC.D1_1431  (
    .O(\U4/ctrlr<2>_MC.D1 )
  );
  X_AND2 \U4/ctrlr<2>_MC.D2_PT_0_1432  (
    .I0(DCORI2CCNTr),
    .I1(\NlwInverterSignal_U4/ctrlr<2>_MC.D2_PT_0/IN1 ),
    .O(\U4/ctrlr<2>_MC.D2_PT_0 )
  );
  X_AND2 \U4/ctrlr<2>_MC.D2_PT_1_1433  (
    .I0(DCORCONFIGr),
    .I1(\NlwInverterSignal_U4/ctrlr<2>_MC.D2_PT_1/IN1 ),
    .O(\U4/ctrlr<2>_MC.D2_PT_1 )
  );
  X_AND2 \U4/ctrlr<2>_MC.D2_PT_2_1434  (
    .I0(DCORENCPWRr),
    .I1(\NlwInverterSignal_U4/ctrlr<2>_MC.D2_PT_2/IN1 ),
    .O(\U4/ctrlr<2>_MC.D2_PT_2 )
  );
  X_AND2 \U4/ctrlr<2>_MC.D2_PT_3_1435  (
    .I0(\NlwInverterSignal_U4/ctrlr<2>_MC.D2_PT_3/IN0 ),
    .I1(\NlwInverterSignal_U4/ctrlr<2>_MC.D2_PT_3/IN1 ),
    .O(\U4/ctrlr<2>_MC.D2_PT_3 )
  );
  X_AND2 \U4/ctrlr<2>_MC.D2_PT_4_1436  (
    .I0(\NlwInverterSignal_U4/ctrlr<2>_MC.D2_PT_4/IN0 ),
    .I1(\NlwInverterSignal_U4/ctrlr<2>_MC.D2_PT_4/IN1 ),
    .O(\U4/ctrlr<2>_MC.D2_PT_4 )
  );
  X_AND2 \U4/ctrlr<2>_MC.D2_PT_5_1437  (
    .I0(\NlwInverterSignal_U4/ctrlr<2>_MC.D2_PT_5/IN0 ),
    .I1(\NlwInverterSignal_U4/ctrlr<2>_MC.D2_PT_5/IN1 ),
    .O(\U4/ctrlr<2>_MC.D2_PT_5 )
  );
  X_OR6 \U4/ctrlr<2>_MC.D2_1438  (
    .I0(\U4/ctrlr<2>_MC.D2_PT_0 ),
    .I1(\U4/ctrlr<2>_MC.D2_PT_1 ),
    .I2(\U4/ctrlr<2>_MC.D2_PT_2 ),
    .I3(\U4/ctrlr<2>_MC.D2_PT_3 ),
    .I4(\U4/ctrlr<2>_MC.D2_PT_4 ),
    .I5(\U4/ctrlr<2>_MC.D2_PT_5 ),
    .O(\U4/ctrlr<2>_MC.D2 )
  );
  X_BUF DCORENCPWRw_1439 (
    .I(\DCORENCPWRw_MC.Q ),
    .O(DCORENCPWRw)
  );
  X_BUF \DCORENCPWRw_MC.Q_1440  (
    .I(\DCORENCPWRw_MC.D ),
    .O(\DCORENCPWRw_MC.Q )
  );
  X_XOR2 \DCORENCPWRw_MC.D_1441  (
    .I0(\DCORENCPWRw_MC.D1 ),
    .I1(\DCORENCPWRw_MC.D2 ),
    .O(\DCORENCPWRw_MC.D )
  );
  X_AND16 \DCORENCPWRw_MC.D1_1442  (
    .I0(\NlwInverterSignal_DCORENCPWRw_MC.D1/IN0 ),
    .I1(\RD_II/UIM ),
    .I2(\NlwInverterSignal_DCORENCPWRw_MC.D1/IN2 ),
    .I3(\NlwInverterSignal_DCORENCPWRw_MC.D1/IN3 ),
    .I4(\NlwInverterSignal_DCORENCPWRw_MC.D1/IN4 ),
    .I5(\NlwInverterSignal_DCORENCPWRw_MC.D1/IN5 ),
    .I6(\NlwInverterSignal_DCORENCPWRw_MC.D1/IN6 ),
    .I7(U2_ADDR_reg[3]),
    .I8(U2_ADDR_reg[1]),
    .I9(U2_ADDR_reg[2]),
    .I10(Vcc),
    .I11(Vcc),
    .I12(Vcc),
    .I13(Vcc),
    .I14(Vcc),
    .I15(Vcc),
    .O(\DCORENCPWRw_MC.D1 )
  );
  X_ZERO \DCORENCPWRw_MC.D2_1443  (
    .O(\DCORENCPWRw_MC.D2 )
  );
  X_BUF \U4/ctrlr<3>_MC.Q_1444  (
    .I(\U4/ctrlr<3>_MC.D ),
    .O(\U4/ctrlr<3>_MC.Q )
  );
  X_BUF \U4/ctrlr<3>_MC.OE_1445  (
    .I(\U4/ctrlr<3>_MC.BUFOE.OUT ),
    .O(\U4/ctrlr<3>_MC.OE )
  );
  X_BUF \U4/ctrlr<3>_MC.BUFOE.OUT_1446  (
    .I(\FOOBAR1__ctinst/7 ),
    .O(\U4/ctrlr<3>_MC.BUFOE.OUT )
  );
  X_XOR2 \U4/ctrlr<3>_MC.D_1447  (
    .I0(\NlwInverterSignal_U4/ctrlr<3>_MC.D/IN0 ),
    .I1(\U4/ctrlr<3>_MC.D2 ),
    .O(\U4/ctrlr<3>_MC.D )
  );
  X_ZERO \U4/ctrlr<3>_MC.D1_1448  (
    .O(\U4/ctrlr<3>_MC.D1 )
  );
  X_AND2 \U4/ctrlr<3>_MC.D2_PT_0_1449  (
    .I0(DCORI2CCNTr),
    .I1(\NlwInverterSignal_U4/ctrlr<3>_MC.D2_PT_0/IN1 ),
    .O(\U4/ctrlr<3>_MC.D2_PT_0 )
  );
  X_AND2 \U4/ctrlr<3>_MC.D2_PT_1_1450  (
    .I0(DCORCONFIGr),
    .I1(\NlwInverterSignal_U4/ctrlr<3>_MC.D2_PT_1/IN1 ),
    .O(\U4/ctrlr<3>_MC.D2_PT_1 )
  );
  X_AND2 \U4/ctrlr<3>_MC.D2_PT_2_1451  (
    .I0(DCORENCPWRr),
    .I1(\NlwInverterSignal_U4/ctrlr<3>_MC.D2_PT_2/IN1 ),
    .O(\U4/ctrlr<3>_MC.D2_PT_2 )
  );
  X_AND2 \U4/ctrlr<3>_MC.D2_PT_3_1452  (
    .I0(\NlwInverterSignal_U4/ctrlr<3>_MC.D2_PT_3/IN0 ),
    .I1(\NlwInverterSignal_U4/ctrlr<3>_MC.D2_PT_3/IN1 ),
    .O(\U4/ctrlr<3>_MC.D2_PT_3 )
  );
  X_AND2 \U4/ctrlr<3>_MC.D2_PT_4_1453  (
    .I0(\NlwInverterSignal_U4/ctrlr<3>_MC.D2_PT_4/IN0 ),
    .I1(\NlwInverterSignal_U4/ctrlr<3>_MC.D2_PT_4/IN1 ),
    .O(\U4/ctrlr<3>_MC.D2_PT_4 )
  );
  X_AND2 \U4/ctrlr<3>_MC.D2_PT_5_1454  (
    .I0(\NlwInverterSignal_U4/ctrlr<3>_MC.D2_PT_5/IN0 ),
    .I1(\NlwInverterSignal_U4/ctrlr<3>_MC.D2_PT_5/IN1 ),
    .O(\U4/ctrlr<3>_MC.D2_PT_5 )
  );
  X_OR6 \U4/ctrlr<3>_MC.D2_1455  (
    .I0(\U4/ctrlr<3>_MC.D2_PT_0 ),
    .I1(\U4/ctrlr<3>_MC.D2_PT_1 ),
    .I2(\U4/ctrlr<3>_MC.D2_PT_2 ),
    .I3(\U4/ctrlr<3>_MC.D2_PT_3 ),
    .I4(\U4/ctrlr<3>_MC.D2_PT_4 ),
    .I5(\U4/ctrlr<3>_MC.D2_PT_5 ),
    .O(\U4/ctrlr<3>_MC.D2 )
  );
  X_BUF \Enc05ctrl_MC.Q_1456  (
    .I(\Enc05ctrl_MC.Q_tsimrenamed_net_ ),
    .O(\Enc05ctrl_MC.Q )
  );
  X_BUF \Enc05ctrl_MC.Q_tsimrenamed_net__1457  (
    .I(\Enc05ctrl_MC.D ),
    .O(\Enc05ctrl_MC.Q_tsimrenamed_net_ )
  );
  X_XOR2 \Enc05ctrl_MC.D_1458  (
    .I0(\NlwInverterSignal_Enc05ctrl_MC.D/IN0 ),
    .I1(\Enc05ctrl_MC.D2 ),
    .O(\Enc05ctrl_MC.D )
  );
  X_AND2 \Enc05ctrl_MC.D1_1459  (
    .I0(\NlwInverterSignal_Enc05ctrl_MC.D1/IN0 ),
    .I1(\U4/ctrlr[3] ),
    .O(\Enc05ctrl_MC.D1 )
  );
  X_ZERO \Enc05ctrl_MC.D2_1460  (
    .O(\Enc05ctrl_MC.D2 )
  );
  X_BUF \Enc133ctrl_MC.Q_1461  (
    .I(\Enc133ctrl_MC.Q_tsimrenamed_net_ ),
    .O(\Enc133ctrl_MC.Q )
  );
  X_BUF \Enc133ctrl_MC.Q_tsimrenamed_net__1462  (
    .I(\Enc133ctrl_MC.D ),
    .O(\Enc133ctrl_MC.Q_tsimrenamed_net_ )
  );
  X_XOR2 \Enc133ctrl_MC.D_1463  (
    .I0(\NlwInverterSignal_Enc133ctrl_MC.D/IN0 ),
    .I1(\Enc133ctrl_MC.D2 ),
    .O(\Enc133ctrl_MC.D )
  );
  X_AND2 \Enc133ctrl_MC.D1_1464  (
    .I0(\U4/ctrlr[6] ),
    .I1(\U4/ctrlr[7] ),
    .O(\Enc133ctrl_MC.D1 )
  );
  X_ZERO \Enc133ctrl_MC.D2_1465  (
    .O(\Enc133ctrl_MC.D2 )
  );
  X_BUF \U4/ctrlr<6>_MC.Q_1466  (
    .I(\U4/ctrlr<6>_MC.D ),
    .O(\U4/ctrlr<6>_MC.Q )
  );
  X_BUF \U4/ctrlr<6>_MC.OE_1467  (
    .I(\U4/ctrlr<6>_MC.BUFOE.OUT ),
    .O(\U4/ctrlr<6>_MC.OE )
  );
  X_BUF \U4/ctrlr<6>_MC.BUFOE.OUT_1468  (
    .I(\FOOBAR1__ctinst/7 ),
    .O(\U4/ctrlr<6>_MC.BUFOE.OUT )
  );
  X_XOR2 \U4/ctrlr<6>_MC.D_1469  (
    .I0(\NlwInverterSignal_U4/ctrlr<6>_MC.D/IN0 ),
    .I1(\U4/ctrlr<6>_MC.D2 ),
    .O(\U4/ctrlr<6>_MC.D )
  );
  X_ZERO \U4/ctrlr<6>_MC.D1_1470  (
    .O(\U4/ctrlr<6>_MC.D1 )
  );
  X_AND2 \U4/ctrlr<6>_MC.D2_PT_0_1471  (
    .I0(DCORI2CCNTr),
    .I1(\NlwInverterSignal_U4/ctrlr<6>_MC.D2_PT_0/IN1 ),
    .O(\U4/ctrlr<6>_MC.D2_PT_0 )
  );
  X_AND2 \U4/ctrlr<6>_MC.D2_PT_1_1472  (
    .I0(DCORCONFIGr),
    .I1(\NlwInverterSignal_U4/ctrlr<6>_MC.D2_PT_1/IN1 ),
    .O(\U4/ctrlr<6>_MC.D2_PT_1 )
  );
  X_AND2 \U4/ctrlr<6>_MC.D2_PT_2_1473  (
    .I0(DCORENCPWRr),
    .I1(\NlwInverterSignal_U4/ctrlr<6>_MC.D2_PT_2/IN1 ),
    .O(\U4/ctrlr<6>_MC.D2_PT_2 )
  );
  X_AND2 \U4/ctrlr<6>_MC.D2_PT_3_1474  (
    .I0(\NlwInverterSignal_U4/ctrlr<6>_MC.D2_PT_3/IN0 ),
    .I1(\NlwInverterSignal_U4/ctrlr<6>_MC.D2_PT_3/IN1 ),
    .O(\U4/ctrlr<6>_MC.D2_PT_3 )
  );
  X_AND2 \U4/ctrlr<6>_MC.D2_PT_4_1475  (
    .I0(\NlwInverterSignal_U4/ctrlr<6>_MC.D2_PT_4/IN0 ),
    .I1(\NlwInverterSignal_U4/ctrlr<6>_MC.D2_PT_4/IN1 ),
    .O(\U4/ctrlr<6>_MC.D2_PT_4 )
  );
  X_AND2 \U4/ctrlr<6>_MC.D2_PT_5_1476  (
    .I0(\NlwInverterSignal_U4/ctrlr<6>_MC.D2_PT_5/IN0 ),
    .I1(\NlwInverterSignal_U4/ctrlr<6>_MC.D2_PT_5/IN1 ),
    .O(\U4/ctrlr<6>_MC.D2_PT_5 )
  );
  X_OR6 \U4/ctrlr<6>_MC.D2_1477  (
    .I0(\U4/ctrlr<6>_MC.D2_PT_0 ),
    .I1(\U4/ctrlr<6>_MC.D2_PT_1 ),
    .I2(\U4/ctrlr<6>_MC.D2_PT_2 ),
    .I3(\U4/ctrlr<6>_MC.D2_PT_3 ),
    .I4(\U4/ctrlr<6>_MC.D2_PT_4 ),
    .I5(\U4/ctrlr<6>_MC.D2_PT_5 ),
    .O(\U4/ctrlr<6>_MC.D2 )
  );
  X_BUF \U4/ctrlr<7>_MC.Q_1478  (
    .I(\U4/ctrlr<7>_MC.D ),
    .O(\U4/ctrlr<7>_MC.Q )
  );
  X_BUF \U4/ctrlr<7>_MC.OE_1479  (
    .I(\U4/ctrlr<7>_MC.BUFOE.OUT ),
    .O(\U4/ctrlr<7>_MC.OE )
  );
  X_BUF \U4/ctrlr<7>_MC.BUFOE.OUT_1480  (
    .I(\FOOBAR1__ctinst/7 ),
    .O(\U4/ctrlr<7>_MC.BUFOE.OUT )
  );
  X_XOR2 \U4/ctrlr<7>_MC.D_1481  (
    .I0(\NlwInverterSignal_U4/ctrlr<7>_MC.D/IN0 ),
    .I1(\U4/ctrlr<7>_MC.D2 ),
    .O(\U4/ctrlr<7>_MC.D )
  );
  X_ZERO \U4/ctrlr<7>_MC.D1_1482  (
    .O(\U4/ctrlr<7>_MC.D1 )
  );
  X_AND2 \U4/ctrlr<7>_MC.D2_PT_0_1483  (
    .I0(DCORI2CCNTr),
    .I1(\NlwInverterSignal_U4/ctrlr<7>_MC.D2_PT_0/IN1 ),
    .O(\U4/ctrlr<7>_MC.D2_PT_0 )
  );
  X_AND2 \U4/ctrlr<7>_MC.D2_PT_1_1484  (
    .I0(DCOR0THRESLOWr),
    .I1(\NlwInverterSignal_U4/ctrlr<7>_MC.D2_PT_1/IN1 ),
    .O(\U4/ctrlr<7>_MC.D2_PT_1 )
  );
  X_AND2 \U4/ctrlr<7>_MC.D2_PT_2_1485  (
    .I0(DCORCONFIGr),
    .I1(\NlwInverterSignal_U4/ctrlr<7>_MC.D2_PT_2/IN1 ),
    .O(\U4/ctrlr<7>_MC.D2_PT_2 )
  );
  X_AND2 \U4/ctrlr<7>_MC.D2_PT_3_1486  (
    .I0(DCORENCPWRr),
    .I1(\NlwInverterSignal_U4/ctrlr<7>_MC.D2_PT_3/IN1 ),
    .O(\U4/ctrlr<7>_MC.D2_PT_3 )
  );
  X_AND2 \U4/ctrlr<7>_MC.D2_PT_4_1487  (
    .I0(DCORIFGr),
    .I1(\NlwInverterSignal_U4/ctrlr<7>_MC.D2_PT_4/IN1 ),
    .O(\U4/ctrlr<7>_MC.D2_PT_4 )
  );
  X_AND2 \U4/ctrlr<7>_MC.D2_PT_5_1488  (
    .I0(\NlwInverterSignal_U4/ctrlr<7>_MC.D2_PT_5/IN0 ),
    .I1(\NlwInverterSignal_U4/ctrlr<7>_MC.D2_PT_5/IN1 ),
    .O(\U4/ctrlr<7>_MC.D2_PT_5 )
  );
  X_AND2 \U4/ctrlr<7>_MC.D2_PT_6_1489  (
    .I0(\NlwInverterSignal_U4/ctrlr<7>_MC.D2_PT_6/IN0 ),
    .I1(\NlwInverterSignal_U4/ctrlr<7>_MC.D2_PT_6/IN1 ),
    .O(\U4/ctrlr<7>_MC.D2_PT_6 )
  );
  X_AND3 \U4/ctrlr<7>_MC.D2_PT_7_1490  (
    .I0(\NlwInverterSignal_U4/ctrlr<7>_MC.D2_PT_7/IN0 ),
    .I1(\NlwInverterSignal_U4/ctrlr<7>_MC.D2_PT_7/IN1 ),
    .I2(\NlwInverterSignal_U4/ctrlr<7>_MC.D2_PT_7/IN2 ),
    .O(\U4/ctrlr<7>_MC.D2_PT_7 )
  );
  X_OR8 \U4/ctrlr<7>_MC.D2_1491  (
    .I0(\U4/ctrlr<7>_MC.D2_PT_0 ),
    .I1(\U4/ctrlr<7>_MC.D2_PT_1 ),
    .I2(\U4/ctrlr<7>_MC.D2_PT_2 ),
    .I3(\U4/ctrlr<7>_MC.D2_PT_3 ),
    .I4(\U4/ctrlr<7>_MC.D2_PT_4 ),
    .I5(\U4/ctrlr<7>_MC.D2_PT_5 ),
    .I6(\U4/ctrlr<7>_MC.D2_PT_6 ),
    .I7(\U4/ctrlr<7>_MC.D2_PT_7 ),
    .O(\U4/ctrlr<7>_MC.D2 )
  );
  X_BUF \Enc15ctrl_MC.Q_1492  (
    .I(\Enc15ctrl_MC.Q_tsimrenamed_net_ ),
    .O(\Enc15ctrl_MC.Q )
  );
  X_BUF \Enc15ctrl_MC.Q_tsimrenamed_net__1493  (
    .I(\Enc15ctrl_MC.D ),
    .O(\Enc15ctrl_MC.Q_tsimrenamed_net_ )
  );
  X_XOR2 \Enc15ctrl_MC.D_1494  (
    .I0(\NlwInverterSignal_Enc15ctrl_MC.D/IN0 ),
    .I1(\Enc15ctrl_MC.D2 ),
    .O(\Enc15ctrl_MC.D )
  );
  X_AND2 \Enc15ctrl_MC.D1_1495  (
    .I0(\NlwInverterSignal_Enc15ctrl_MC.D1/IN0 ),
    .I1(\U4/ctrlr[7] ),
    .O(\Enc15ctrl_MC.D1 )
  );
  X_ZERO \Enc15ctrl_MC.D2_1496  (
    .O(\Enc15ctrl_MC.D2 )
  );
  X_BUF \GPIO8_MC.Q_1497  (
    .I(\GPIO8_MC.Q_tsimrenamed_net_ ),
    .O(\GPIO8_MC.Q )
  );
  X_BUF \GPIO8_MC.Q_tsimrenamed_net__1498  (
    .I(\GPIO8_MC.D ),
    .O(\GPIO8_MC.Q_tsimrenamed_net_ )
  );
  X_XOR2 \GPIO8_MC.D_1499  (
    .I0(\GPIO8_MC.D1 ),
    .I1(\GPIO8_MC.D2 ),
    .O(\GPIO8_MC.D )
  );
  X_AND2 \GPIO8_MC.D1_1500  (
    .I0(\PWM5_II/UIM ),
    .I1(\PWM5_II/UIM ),
    .O(\GPIO8_MC.D1 )
  );
  X_ZERO \GPIO8_MC.D2_1501  (
    .O(\GPIO8_MC.D2 )
  );
  X_BUF \GPIO9_MC.Q_1502  (
    .I(\GPIO9_MC.Q_tsimrenamed_net_ ),
    .O(\GPIO9_MC.Q )
  );
  X_BUF \GPIO9_MC.Q_tsimrenamed_net__1503  (
    .I(\GPIO9_MC.D ),
    .O(\GPIO9_MC.Q_tsimrenamed_net_ )
  );
  X_XOR2 \GPIO9_MC.D_1504  (
    .I0(\GPIO9_MC.D1 ),
    .I1(\GPIO9_MC.D2 ),
    .O(\GPIO9_MC.D )
  );
  X_AND2 \GPIO9_MC.D1_1505  (
    .I0(\PWM3_II/UIM ),
    .I1(\PWM3_II/UIM ),
    .O(\GPIO9_MC.D1 )
  );
  X_ZERO \GPIO9_MC.D2_1506  (
    .O(\GPIO9_MC.D2 )
  );
  X_BUF \GP_Motor0_1_MC.Q_1507  (
    .I(\GP_Motor0_1_MC.Q_tsimrenamed_net_ ),
    .O(\GP_Motor0_1_MC.Q )
  );
  X_BUF \GP_Motor0_1_MC.UIM_1508  (
    .I(\GP_Motor0_1_MC.Q_tsimrenamed_net_ ),
    .O(\GP_Motor0_1_MC.UIM )
  );
  X_OR2 GP_Motor0_1_MC_tsimcreated_prld__1509 (
    .I0(\FOOBAR3__ctinst/7 ),
    .I1(PRLD),
    .O(GP_Motor0_1_MC_tsimcreated_prld_)
  );
  X_FF \GP_Motor0_1_MC.REG  (
    .I(\GP_Motor0_1_MC.D ),
    .CE(Vcc),
    .CLK(\GP_Motor0_1_MC.REG_tsimcreated_inv_Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(GP_Motor0_1_MC_tsimcreated_prld_),
    .O(\GP_Motor0_1_MC.Q_tsimrenamed_net_ )
  );
  X_INV \GP_Motor0_1_MC.REG_tsimcreated_inv_Mclk_II/FCLK_1510  (
    .I(\Mclk_II/FCLK ),
    .O(\GP_Motor0_1_MC.REG_tsimcreated_inv_Mclk_II/FCLK )
  );
  X_XOR2 \GP_Motor0_1_MC.D_1511  (
    .I0(\GP_Motor0_1_MC.D1 ),
    .I1(\GP_Motor0_1_MC.D2 ),
    .O(\GP_Motor0_1_MC.D )
  );
  X_ZERO \GP_Motor0_1_MC.D1_1512  (
    .O(\GP_Motor0_1_MC.D1 )
  );
  X_AND3 \GP_Motor0_1_MC.D2_PT_0_1513  (
    .I0(\MSPReset_II/UIM ),
    .I1(\AD<6>_II/UIM ),
    .I2(DCOROUTw),
    .O(\GP_Motor0_1_MC.D2_PT_0 )
  );
  X_AND3 \GP_Motor0_1_MC.D2_PT_1_1514  (
    .I0(\MSPReset_II/UIM ),
    .I1(\NlwInverterSignal_GP_Motor0_1_MC.D2_PT_1/IN1 ),
    .I2(\GP_Motor0_1_MC.UIM ),
    .O(\GP_Motor0_1_MC.D2_PT_1 )
  );
  X_OR2 \GP_Motor0_1_MC.D2_1515  (
    .I0(\GP_Motor0_1_MC.D2_PT_0 ),
    .I1(\GP_Motor0_1_MC.D2_PT_1 ),
    .O(\GP_Motor0_1_MC.D2 )
  );
  X_BUF DCOROUTw_1516 (
    .I(\DCOROUTw_MC.Q ),
    .O(DCOROUTw)
  );
  X_BUF \DCOROUTw_MC.Q_1517  (
    .I(\DCOROUTw_MC.D ),
    .O(\DCOROUTw_MC.Q )
  );
  X_XOR2 \DCOROUTw_MC.D_1518  (
    .I0(\DCOROUTw_MC.D1 ),
    .I1(\DCOROUTw_MC.D2 ),
    .O(\DCOROUTw_MC.D )
  );
  X_AND16 \DCOROUTw_MC.D1_1519  (
    .I0(\NlwInverterSignal_DCOROUTw_MC.D1/IN0 ),
    .I1(\RD_II/UIM ),
    .I2(U2_ADDR_reg[0]),
    .I3(\NlwInverterSignal_DCOROUTw_MC.D1/IN3 ),
    .I4(\NlwInverterSignal_DCOROUTw_MC.D1/IN4 ),
    .I5(\NlwInverterSignal_DCOROUTw_MC.D1/IN5 ),
    .I6(\NlwInverterSignal_DCOROUTw_MC.D1/IN6 ),
    .I7(U2_ADDR_reg[3]),
    .I8(U2_ADDR_reg[1]),
    .I9(U2_ADDR_reg[2]),
    .I10(Vcc),
    .I11(Vcc),
    .I12(Vcc),
    .I13(Vcc),
    .I14(Vcc),
    .I15(Vcc),
    .O(\DCOROUTw_MC.D1 )
  );
  X_ZERO \DCOROUTw_MC.D2_1520  (
    .O(\DCOROUTw_MC.D2 )
  );
  X_BUF \GP_Motor1_1_MC.Q_1521  (
    .I(\GP_Motor1_1_MC.Q_tsimrenamed_net_ ),
    .O(\GP_Motor1_1_MC.Q )
  );
  X_BUF \GP_Motor1_1_MC.UIM_1522  (
    .I(\GP_Motor1_1_MC.Q_tsimrenamed_net_ ),
    .O(\GP_Motor1_1_MC.UIM )
  );
  X_OR2 GP_Motor1_1_MC_tsimcreated_prld__1523 (
    .I0(\FOOBAR3__ctinst/7 ),
    .I1(PRLD),
    .O(GP_Motor1_1_MC_tsimcreated_prld_)
  );
  X_FF \GP_Motor1_1_MC.REG  (
    .I(\GP_Motor1_1_MC.D ),
    .CE(Vcc),
    .CLK(\GP_Motor1_1_MC.REG_tsimcreated_inv_Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(GP_Motor1_1_MC_tsimcreated_prld_),
    .O(\GP_Motor1_1_MC.Q_tsimrenamed_net_ )
  );
  X_INV \GP_Motor1_1_MC.REG_tsimcreated_inv_Mclk_II/FCLK_1524  (
    .I(\Mclk_II/FCLK ),
    .O(\GP_Motor1_1_MC.REG_tsimcreated_inv_Mclk_II/FCLK )
  );
  X_XOR2 \GP_Motor1_1_MC.D_1525  (
    .I0(\GP_Motor1_1_MC.D1 ),
    .I1(\GP_Motor1_1_MC.D2 ),
    .O(\GP_Motor1_1_MC.D )
  );
  X_ZERO \GP_Motor1_1_MC.D1_1526  (
    .O(\GP_Motor1_1_MC.D1 )
  );
  X_AND3 \GP_Motor1_1_MC.D2_PT_0_1527  (
    .I0(\MSPReset_II/UIM ),
    .I1(\AD<7>_II/UIM ),
    .I2(DCOROUTw),
    .O(\GP_Motor1_1_MC.D2_PT_0 )
  );
  X_AND3 \GP_Motor1_1_MC.D2_PT_1_1528  (
    .I0(\MSPReset_II/UIM ),
    .I1(\NlwInverterSignal_GP_Motor1_1_MC.D2_PT_1/IN1 ),
    .I2(\GP_Motor1_1_MC.UIM ),
    .O(\GP_Motor1_1_MC.D2_PT_1 )
  );
  X_OR2 \GP_Motor1_1_MC.D2_1529  (
    .I0(\GP_Motor1_1_MC.D2_PT_0 ),
    .I1(\GP_Motor1_1_MC.D2_PT_1 ),
    .O(\GP_Motor1_1_MC.D2 )
  );
  X_BUF \HSO_MC.Q_1530  (
    .I(\HSO_MC.Q_tsimrenamed_net_ ),
    .O(\HSO_MC.Q )
  );
  X_BUF \HSO_MC.Q_tsimrenamed_net__1531  (
    .I(\HSO_MC.D ),
    .O(\HSO_MC.Q_tsimrenamed_net_ )
  );
  X_XOR2 \HSO_MC.D_1532  (
    .I0(\HSO_MC.D1 ),
    .I1(\HSO_MC.D2 ),
    .O(\HSO_MC.D )
  );
  X_AND2 \HSO_MC.D1_1533  (
    .I0(\MHSO_II/UIM ),
    .I1(\MHSO_II/UIM ),
    .O(\HSO_MC.D1 )
  );
  X_ZERO \HSO_MC.D2_1534  (
    .O(\HSO_MC.D2 )
  );
  X_BUF \Home033ctrl_MC.Q_1535  (
    .I(\Home033ctrl_MC.Q_tsimrenamed_net_ ),
    .O(\Home033ctrl_MC.Q )
  );
  X_OR2 Home033ctrl_MC_tsimcreated_prld__1536 (
    .I0(\FOOBAR2__ctinst/7 ),
    .I1(PRLD),
    .O(Home033ctrl_MC_tsimcreated_prld_)
  );
  X_FF \Home033ctrl_MC.REG  (
    .I(\Home033ctrl_MC.D ),
    .CE(\Home033ctrl_MC.CE ),
    .CLK(\Home033ctrl_MC.REG_tsimcreated_inv_Mclk_II/FCLK ),
    .SET(Home033ctrl_MC_tsimcreated_prld_),
    .RST(Gnd),
    .O(\Home033ctrl_MC.Q_tsimrenamed_net_ )
  );
  X_INV \Home033ctrl_MC.REG_tsimcreated_inv_Mclk_II/FCLK_1537  (
    .I(\Mclk_II/FCLK ),
    .O(\Home033ctrl_MC.REG_tsimcreated_inv_Mclk_II/FCLK )
  );
  X_XOR2 \Home033ctrl_MC.D_1538  (
    .I0(\NlwInverterSignal_Home033ctrl_MC.D/IN0 ),
    .I1(\Home033ctrl_MC.D2 ),
    .O(\Home033ctrl_MC.D )
  );
  X_AND2 \Home033ctrl_MC.D1_1539  (
    .I0(\AD<0>_II/UIM ),
    .I1(\AD<0>_II/UIM ),
    .O(\Home033ctrl_MC.D1 )
  );
  X_ZERO \Home033ctrl_MC.D2_1540  (
    .O(\Home033ctrl_MC.D2 )
  );
  X_AND2 \Home033ctrl_MC.CE_1541  (
    .I0(DCORENCPWRw),
    .I1(DCORENCPWRw),
    .O(\Home033ctrl_MC.CE )
  );
  X_BUF \Home05ctrl_MC.Q_1542  (
    .I(\Home05ctrl_MC.Q_tsimrenamed_net_ ),
    .O(\Home05ctrl_MC.Q )
  );
  X_OR2 Home05ctrl_MC_tsimcreated_prld__1543 (
    .I0(\FOOBAR2__ctinst/7 ),
    .I1(PRLD),
    .O(Home05ctrl_MC_tsimcreated_prld_)
  );
  X_FF \Home05ctrl_MC.REG  (
    .I(\Home05ctrl_MC.D ),
    .CE(\FOOBAR14__ctinst/4 ),
    .CLK(\Home05ctrl_MC.REG_tsimcreated_inv_Mclk_II/FCLK ),
    .SET(Home05ctrl_MC_tsimcreated_prld_),
    .RST(Gnd),
    .O(\Home05ctrl_MC.Q_tsimrenamed_net_ )
  );
  X_INV \Home05ctrl_MC.REG_tsimcreated_inv_Mclk_II/FCLK_1544  (
    .I(\Mclk_II/FCLK ),
    .O(\Home05ctrl_MC.REG_tsimcreated_inv_Mclk_II/FCLK )
  );
  X_XOR2 \Home05ctrl_MC.D_1545  (
    .I0(\NlwInverterSignal_Home05ctrl_MC.D/IN0 ),
    .I1(\Home05ctrl_MC.D2 ),
    .O(\Home05ctrl_MC.D )
  );
  X_AND2 \Home05ctrl_MC.D1_1546  (
    .I0(\AD<1>_II/UIM ),
    .I1(\AD<1>_II/UIM ),
    .O(\Home05ctrl_MC.D1 )
  );
  X_ZERO \Home05ctrl_MC.D2_1547  (
    .O(\Home05ctrl_MC.D2 )
  );
  X_BUF \Home133ctrl_MC.Q_1548  (
    .I(\Home133ctrl_MC.Q_tsimrenamed_net_ ),
    .O(\Home133ctrl_MC.Q )
  );
  X_OR2 Home133ctrl_MC_tsimcreated_prld__1549 (
    .I0(\FOOBAR2__ctinst/7 ),
    .I1(PRLD),
    .O(Home133ctrl_MC_tsimcreated_prld_)
  );
  X_FF \Home133ctrl_MC.REG  (
    .I(\Home133ctrl_MC.D ),
    .CE(\FOOBAR23__ctinst/4 ),
    .CLK(\Home133ctrl_MC.REG_tsimcreated_inv_Mclk_II/FCLK ),
    .SET(Home133ctrl_MC_tsimcreated_prld_),
    .RST(Gnd),
    .O(\Home133ctrl_MC.Q_tsimrenamed_net_ )
  );
  X_INV \Home133ctrl_MC.REG_tsimcreated_inv_Mclk_II/FCLK_1550  (
    .I(\Mclk_II/FCLK ),
    .O(\Home133ctrl_MC.REG_tsimcreated_inv_Mclk_II/FCLK )
  );
  X_XOR2 \Home133ctrl_MC.D_1551  (
    .I0(\NlwInverterSignal_Home133ctrl_MC.D/IN0 ),
    .I1(\Home133ctrl_MC.D2 ),
    .O(\Home133ctrl_MC.D )
  );
  X_AND2 \Home133ctrl_MC.D1_1552  (
    .I0(\AD<4>_II/UIM ),
    .I1(\AD<4>_II/UIM ),
    .O(\Home133ctrl_MC.D1 )
  );
  X_ZERO \Home133ctrl_MC.D2_1553  (
    .O(\Home133ctrl_MC.D2 )
  );
  X_BUF \Home15ctrl_MC.Q_1554  (
    .I(\Home15ctrl_MC.Q_tsimrenamed_net_ ),
    .O(\Home15ctrl_MC.Q )
  );
  X_OR2 Home15ctrl_MC_tsimcreated_prld__1555 (
    .I0(\FOOBAR2__ctinst/7 ),
    .I1(PRLD),
    .O(Home15ctrl_MC_tsimcreated_prld_)
  );
  X_FF \Home15ctrl_MC.REG  (
    .I(\Home15ctrl_MC.D ),
    .CE(\Home15ctrl_MC.CE ),
    .CLK(\Home15ctrl_MC.REG_tsimcreated_inv_Mclk_II/FCLK ),
    .SET(Home15ctrl_MC_tsimcreated_prld_),
    .RST(Gnd),
    .O(\Home15ctrl_MC.Q_tsimrenamed_net_ )
  );
  X_INV \Home15ctrl_MC.REG_tsimcreated_inv_Mclk_II/FCLK_1556  (
    .I(\Mclk_II/FCLK ),
    .O(\Home15ctrl_MC.REG_tsimcreated_inv_Mclk_II/FCLK )
  );
  X_XOR2 \Home15ctrl_MC.D_1557  (
    .I0(\NlwInverterSignal_Home15ctrl_MC.D/IN0 ),
    .I1(\Home15ctrl_MC.D2 ),
    .O(\Home15ctrl_MC.D )
  );
  X_AND2 \Home15ctrl_MC.D1_1558  (
    .I0(\AD<5>_II/UIM ),
    .I1(\AD<5>_II/UIM ),
    .O(\Home15ctrl_MC.D1 )
  );
  X_ZERO \Home15ctrl_MC.D2_1559  (
    .O(\Home15ctrl_MC.D2 )
  );
  X_AND2 \Home15ctrl_MC.CE_1560  (
    .I0(DCORENCPWRw),
    .I1(DCORENCPWRw),
    .O(\Home15ctrl_MC.CE )
  );
  X_BUF \INT_MC.Q_1561  (
    .I(\INT_MC.Q_tsimrenamed_net_ ),
    .O(\INT_MC.Q )
  );
  X_BUF \INT_MC.Q_tsimrenamed_net__1562  (
    .I(\INT_MC.D ),
    .O(\INT_MC.Q_tsimrenamed_net_ )
  );
  X_XOR2 \INT_MC.D_1563  (
    .I0(\INT_MC.D1 ),
    .I1(\INT_MC.D2 ),
    .O(\INT_MC.D )
  );
  X_ZERO \INT_MC.D1_1564  (
    .O(\INT_MC.D1 )
  );
  X_AND2 \INT_MC.D2_PT_0_1565  (
    .I0(\TP12_MC.UIM ),
    .I1(\U3/DCORIE [7]),
    .O(\INT_MC.D2_PT_0 )
  );
  X_AND2 \INT_MC.D2_PT_1_1566  (
    .I0(NET2482),
    .I1(\U3/DCORIE [2]),
    .O(\INT_MC.D2_PT_1 )
  );
  X_AND2 \INT_MC.D2_PT_2_1567  (
    .I0(NET2501),
    .I1(\U3/DCORIE [5]),
    .O(\INT_MC.D2_PT_2 )
  );
  X_AND2 \INT_MC.D2_PT_3_1568  (
    .I0(NET2493),
    .I1(\U3/DCORIE [3]),
    .O(\INT_MC.D2_PT_3 )
  );
  X_AND2 \INT_MC.D2_PT_4_1569  (
    .I0(NET2512),
    .I1(\U3/DCORIE [6]),
    .O(\INT_MC.D2_PT_4 )
  );
  X_AND2 \INT_MC.D2_PT_5_1570  (
    .I0(NET2528),
    .I1(\U3/DCORIE [1]),
    .O(\INT_MC.D2_PT_5 )
  );
  X_AND2 \INT_MC.D2_PT_6_1571  (
    .I0(\NlwInverterSignal_INT_MC.D2_PT_6/IN0 ),
    .I1(\U3/DCORIE [0]),
    .O(\INT_MC.D2_PT_6 )
  );
  X_AND2 \INT_MC.D2_PT_7_1572  (
    .I0(NET2575),
    .I1(\U3/DCORIE [4]),
    .O(\INT_MC.D2_PT_7 )
  );
  X_OR8 \INT_MC.D2_1573  (
    .I0(\INT_MC.D2_PT_0 ),
    .I1(\INT_MC.D2_PT_1 ),
    .I2(\INT_MC.D2_PT_2 ),
    .I3(\INT_MC.D2_PT_3 ),
    .I4(\INT_MC.D2_PT_4 ),
    .I5(\INT_MC.D2_PT_5 ),
    .I6(\INT_MC.D2_PT_6 ),
    .I7(\INT_MC.D2_PT_7 ),
    .O(\INT_MC.D2 )
  );
  X_BUF \U3/DCORIE<0>  (
    .I(\U3/DCORIE<0>_MC.Q ),
    .O(\U3/DCORIE [0])
  );
  X_FF \U3/DCORIE<0>_MC.REG  (
    .I(\U3/DCORIE<0>_MC.D ),
    .CE(Vcc),
    .CLK(\U3/DCORIE<0>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\U3/DCORIE<0>_MC.Q )
  );
  X_INV \U3/DCORIE<0>_MC.REG_tsimcreated_inv_Mclk_II/FCLK_1574  (
    .I(\Mclk_II/FCLK ),
    .O(\U3/DCORIE<0>_MC.REG_tsimcreated_inv_Mclk_II/FCLK )
  );
  X_XOR2 \U3/DCORIE<0>_MC.D_1575  (
    .I0(\U3/DCORIE<0>_MC.D1 ),
    .I1(\U3/DCORIE<0>_MC.D2 ),
    .O(\U3/DCORIE<0>_MC.D )
  );
  X_ZERO \U3/DCORIE<0>_MC.D1_1576  (
    .O(\U3/DCORIE<0>_MC.D1 )
  );
  X_AND3 \U3/DCORIE<0>_MC.D2_PT_0_1577  (
    .I0(\MSPReset_II/UIM ),
    .I1(\AD<0>_II/UIM ),
    .I2(DCORIEw),
    .O(\U3/DCORIE<0>_MC.D2_PT_0 )
  );
  X_AND3 \U3/DCORIE<0>_MC.D2_PT_1_1578  (
    .I0(\MSPReset_II/UIM ),
    .I1(\U3/DCORIE [0]),
    .I2(\NlwInverterSignal_U3/DCORIE<0>_MC.D2_PT_1/IN2 ),
    .O(\U3/DCORIE<0>_MC.D2_PT_1 )
  );
  X_OR2 \U3/DCORIE<0>_MC.D2_1579  (
    .I0(\U3/DCORIE<0>_MC.D2_PT_0 ),
    .I1(\U3/DCORIE<0>_MC.D2_PT_1 ),
    .O(\U3/DCORIE<0>_MC.D2 )
  );
  X_BUF DCORIEw_1580 (
    .I(\DCORIEw_MC.Q ),
    .O(DCORIEw)
  );
  X_BUF \DCORIEw_MC.Q_1581  (
    .I(\DCORIEw_MC.D ),
    .O(\DCORIEw_MC.Q )
  );
  X_XOR2 \DCORIEw_MC.D_1582  (
    .I0(\DCORIEw_MC.D1 ),
    .I1(\DCORIEw_MC.D2 ),
    .O(\DCORIEw_MC.D )
  );
  X_AND16 \DCORIEw_MC.D1_1583  (
    .I0(\NlwInverterSignal_DCORIEw_MC.D1/IN0 ),
    .I1(\RD_II/UIM ),
    .I2(\NlwInverterSignal_DCORIEw_MC.D1/IN2 ),
    .I3(\NlwInverterSignal_DCORIEw_MC.D1/IN3 ),
    .I4(\NlwInverterSignal_DCORIEw_MC.D1/IN4 ),
    .I5(\NlwInverterSignal_DCORIEw_MC.D1/IN5 ),
    .I6(\NlwInverterSignal_DCORIEw_MC.D1/IN6 ),
    .I7(\NlwInverterSignal_DCORIEw_MC.D1/IN7 ),
    .I8(\NlwInverterSignal_DCORIEw_MC.D1/IN8 ),
    .I9(\NlwInverterSignal_DCORIEw_MC.D1/IN9 ),
    .I10(Vcc),
    .I11(Vcc),
    .I12(Vcc),
    .I13(Vcc),
    .I14(Vcc),
    .I15(Vcc),
    .O(\DCORIEw_MC.D1 )
  );
  X_ZERO \DCORIEw_MC.D2_1584  (
    .O(\DCORIEw_MC.D2 )
  );
  X_BUF \U3/DCORIE<1>  (
    .I(\U3/DCORIE<1>_MC.Q ),
    .O(\U3/DCORIE [1])
  );
  X_FF \U3/DCORIE<1>_MC.REG  (
    .I(\U3/DCORIE<1>_MC.D ),
    .CE(Vcc),
    .CLK(\U3/DCORIE<1>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\U3/DCORIE<1>_MC.Q )
  );
  X_INV \U3/DCORIE<1>_MC.REG_tsimcreated_inv_Mclk_II/FCLK_1585  (
    .I(\Mclk_II/FCLK ),
    .O(\U3/DCORIE<1>_MC.REG_tsimcreated_inv_Mclk_II/FCLK )
  );
  X_XOR2 \U3/DCORIE<1>_MC.D_1586  (
    .I0(\U3/DCORIE<1>_MC.D1 ),
    .I1(\U3/DCORIE<1>_MC.D2 ),
    .O(\U3/DCORIE<1>_MC.D )
  );
  X_ZERO \U3/DCORIE<1>_MC.D1_1587  (
    .O(\U3/DCORIE<1>_MC.D1 )
  );
  X_AND3 \U3/DCORIE<1>_MC.D2_PT_0_1588  (
    .I0(\MSPReset_II/UIM ),
    .I1(\AD<1>_II/UIM ),
    .I2(DCORIEw),
    .O(\U3/DCORIE<1>_MC.D2_PT_0 )
  );
  X_AND3 \U3/DCORIE<1>_MC.D2_PT_1_1589  (
    .I0(\MSPReset_II/UIM ),
    .I1(\U3/DCORIE [1]),
    .I2(\NlwInverterSignal_U3/DCORIE<1>_MC.D2_PT_1/IN2 ),
    .O(\U3/DCORIE<1>_MC.D2_PT_1 )
  );
  X_OR2 \U3/DCORIE<1>_MC.D2_1590  (
    .I0(\U3/DCORIE<1>_MC.D2_PT_0 ),
    .I1(\U3/DCORIE<1>_MC.D2_PT_1 ),
    .O(\U3/DCORIE<1>_MC.D2 )
  );
  X_BUF \U3/DCORIE<2>  (
    .I(\U3/DCORIE<2>_MC.Q ),
    .O(\U3/DCORIE [2])
  );
  X_FF \U3/DCORIE<2>_MC.REG  (
    .I(\U3/DCORIE<2>_MC.D ),
    .CE(Vcc),
    .CLK(\U3/DCORIE<2>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\U3/DCORIE<2>_MC.Q )
  );
  X_INV \U3/DCORIE<2>_MC.REG_tsimcreated_inv_Mclk_II/FCLK_1591  (
    .I(\Mclk_II/FCLK ),
    .O(\U3/DCORIE<2>_MC.REG_tsimcreated_inv_Mclk_II/FCLK )
  );
  X_XOR2 \U3/DCORIE<2>_MC.D_1592  (
    .I0(\U3/DCORIE<2>_MC.D1 ),
    .I1(\U3/DCORIE<2>_MC.D2 ),
    .O(\U3/DCORIE<2>_MC.D )
  );
  X_ZERO \U3/DCORIE<2>_MC.D1_1593  (
    .O(\U3/DCORIE<2>_MC.D1 )
  );
  X_AND3 \U3/DCORIE<2>_MC.D2_PT_0_1594  (
    .I0(\MSPReset_II/UIM ),
    .I1(\AD<2>_II/UIM ),
    .I2(DCORIEw),
    .O(\U3/DCORIE<2>_MC.D2_PT_0 )
  );
  X_AND3 \U3/DCORIE<2>_MC.D2_PT_1_1595  (
    .I0(\MSPReset_II/UIM ),
    .I1(\U3/DCORIE [2]),
    .I2(\NlwInverterSignal_U3/DCORIE<2>_MC.D2_PT_1/IN2 ),
    .O(\U3/DCORIE<2>_MC.D2_PT_1 )
  );
  X_OR2 \U3/DCORIE<2>_MC.D2_1596  (
    .I0(\U3/DCORIE<2>_MC.D2_PT_0 ),
    .I1(\U3/DCORIE<2>_MC.D2_PT_1 ),
    .O(\U3/DCORIE<2>_MC.D2 )
  );
  X_BUF \U3/DCORIE<3>  (
    .I(\U3/DCORIE<3>_MC.Q ),
    .O(\U3/DCORIE [3])
  );
  X_FF \U3/DCORIE<3>_MC.REG  (
    .I(\U3/DCORIE<3>_MC.D ),
    .CE(Vcc),
    .CLK(\U3/DCORIE<3>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\U3/DCORIE<3>_MC.Q )
  );
  X_INV \U3/DCORIE<3>_MC.REG_tsimcreated_inv_Mclk_II/FCLK_1597  (
    .I(\Mclk_II/FCLK ),
    .O(\U3/DCORIE<3>_MC.REG_tsimcreated_inv_Mclk_II/FCLK )
  );
  X_XOR2 \U3/DCORIE<3>_MC.D_1598  (
    .I0(\U3/DCORIE<3>_MC.D1 ),
    .I1(\U3/DCORIE<3>_MC.D2 ),
    .O(\U3/DCORIE<3>_MC.D )
  );
  X_ZERO \U3/DCORIE<3>_MC.D1_1599  (
    .O(\U3/DCORIE<3>_MC.D1 )
  );
  X_AND3 \U3/DCORIE<3>_MC.D2_PT_0_1600  (
    .I0(\MSPReset_II/UIM ),
    .I1(\AD<3>_II/UIM ),
    .I2(DCORIEw),
    .O(\U3/DCORIE<3>_MC.D2_PT_0 )
  );
  X_AND3 \U3/DCORIE<3>_MC.D2_PT_1_1601  (
    .I0(\MSPReset_II/UIM ),
    .I1(\U3/DCORIE [3]),
    .I2(\NlwInverterSignal_U3/DCORIE<3>_MC.D2_PT_1/IN2 ),
    .O(\U3/DCORIE<3>_MC.D2_PT_1 )
  );
  X_OR2 \U3/DCORIE<3>_MC.D2_1602  (
    .I0(\U3/DCORIE<3>_MC.D2_PT_0 ),
    .I1(\U3/DCORIE<3>_MC.D2_PT_1 ),
    .O(\U3/DCORIE<3>_MC.D2 )
  );
  X_BUF \U3/DCORIE<4>  (
    .I(\U3/DCORIE<4>_MC.Q ),
    .O(\U3/DCORIE [4])
  );
  X_FF \U3/DCORIE<4>_MC.REG  (
    .I(\U3/DCORIE<4>_MC.D ),
    .CE(Vcc),
    .CLK(\U3/DCORIE<4>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\U3/DCORIE<4>_MC.Q )
  );
  X_INV \U3/DCORIE<4>_MC.REG_tsimcreated_inv_Mclk_II/FCLK_1603  (
    .I(\Mclk_II/FCLK ),
    .O(\U3/DCORIE<4>_MC.REG_tsimcreated_inv_Mclk_II/FCLK )
  );
  X_XOR2 \U3/DCORIE<4>_MC.D_1604  (
    .I0(\U3/DCORIE<4>_MC.D1 ),
    .I1(\U3/DCORIE<4>_MC.D2 ),
    .O(\U3/DCORIE<4>_MC.D )
  );
  X_ZERO \U3/DCORIE<4>_MC.D1_1605  (
    .O(\U3/DCORIE<4>_MC.D1 )
  );
  X_AND3 \U3/DCORIE<4>_MC.D2_PT_0_1606  (
    .I0(\MSPReset_II/UIM ),
    .I1(\AD<4>_II/UIM ),
    .I2(DCORIEw),
    .O(\U3/DCORIE<4>_MC.D2_PT_0 )
  );
  X_AND3 \U3/DCORIE<4>_MC.D2_PT_1_1607  (
    .I0(\MSPReset_II/UIM ),
    .I1(\U3/DCORIE [4]),
    .I2(\NlwInverterSignal_U3/DCORIE<4>_MC.D2_PT_1/IN2 ),
    .O(\U3/DCORIE<4>_MC.D2_PT_1 )
  );
  X_OR2 \U3/DCORIE<4>_MC.D2_1608  (
    .I0(\U3/DCORIE<4>_MC.D2_PT_0 ),
    .I1(\U3/DCORIE<4>_MC.D2_PT_1 ),
    .O(\U3/DCORIE<4>_MC.D2 )
  );
  X_BUF \U3/DCORIE<5>  (
    .I(\U3/DCORIE<5>_MC.Q ),
    .O(\U3/DCORIE [5])
  );
  X_FF \U3/DCORIE<5>_MC.REG  (
    .I(\U3/DCORIE<5>_MC.D ),
    .CE(Vcc),
    .CLK(\U3/DCORIE<5>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\U3/DCORIE<5>_MC.Q )
  );
  X_INV \U3/DCORIE<5>_MC.REG_tsimcreated_inv_Mclk_II/FCLK_1609  (
    .I(\Mclk_II/FCLK ),
    .O(\U3/DCORIE<5>_MC.REG_tsimcreated_inv_Mclk_II/FCLK )
  );
  X_XOR2 \U3/DCORIE<5>_MC.D_1610  (
    .I0(\U3/DCORIE<5>_MC.D1 ),
    .I1(\U3/DCORIE<5>_MC.D2 ),
    .O(\U3/DCORIE<5>_MC.D )
  );
  X_ZERO \U3/DCORIE<5>_MC.D1_1611  (
    .O(\U3/DCORIE<5>_MC.D1 )
  );
  X_AND3 \U3/DCORIE<5>_MC.D2_PT_0_1612  (
    .I0(\MSPReset_II/UIM ),
    .I1(\AD<5>_II/UIM ),
    .I2(DCORIEw),
    .O(\U3/DCORIE<5>_MC.D2_PT_0 )
  );
  X_AND3 \U3/DCORIE<5>_MC.D2_PT_1_1613  (
    .I0(\MSPReset_II/UIM ),
    .I1(\U3/DCORIE [5]),
    .I2(\NlwInverterSignal_U3/DCORIE<5>_MC.D2_PT_1/IN2 ),
    .O(\U3/DCORIE<5>_MC.D2_PT_1 )
  );
  X_OR2 \U3/DCORIE<5>_MC.D2_1614  (
    .I0(\U3/DCORIE<5>_MC.D2_PT_0 ),
    .I1(\U3/DCORIE<5>_MC.D2_PT_1 ),
    .O(\U3/DCORIE<5>_MC.D2 )
  );
  X_BUF \U3/DCORIE<6>  (
    .I(\U3/DCORIE<6>_MC.Q ),
    .O(\U3/DCORIE [6])
  );
  X_FF \U3/DCORIE<6>_MC.REG  (
    .I(\U3/DCORIE<6>_MC.D ),
    .CE(Vcc),
    .CLK(\U3/DCORIE<6>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\U3/DCORIE<6>_MC.Q )
  );
  X_INV \U3/DCORIE<6>_MC.REG_tsimcreated_inv_Mclk_II/FCLK_1615  (
    .I(\Mclk_II/FCLK ),
    .O(\U3/DCORIE<6>_MC.REG_tsimcreated_inv_Mclk_II/FCLK )
  );
  X_XOR2 \U3/DCORIE<6>_MC.D_1616  (
    .I0(\U3/DCORIE<6>_MC.D1 ),
    .I1(\U3/DCORIE<6>_MC.D2 ),
    .O(\U3/DCORIE<6>_MC.D )
  );
  X_ZERO \U3/DCORIE<6>_MC.D1_1617  (
    .O(\U3/DCORIE<6>_MC.D1 )
  );
  X_AND3 \U3/DCORIE<6>_MC.D2_PT_0_1618  (
    .I0(\MSPReset_II/UIM ),
    .I1(\AD<6>_II/UIM ),
    .I2(DCORIEw),
    .O(\U3/DCORIE<6>_MC.D2_PT_0 )
  );
  X_AND3 \U3/DCORIE<6>_MC.D2_PT_1_1619  (
    .I0(\MSPReset_II/UIM ),
    .I1(\U3/DCORIE [6]),
    .I2(\NlwInverterSignal_U3/DCORIE<6>_MC.D2_PT_1/IN2 ),
    .O(\U3/DCORIE<6>_MC.D2_PT_1 )
  );
  X_OR2 \U3/DCORIE<6>_MC.D2_1620  (
    .I0(\U3/DCORIE<6>_MC.D2_PT_0 ),
    .I1(\U3/DCORIE<6>_MC.D2_PT_1 ),
    .O(\U3/DCORIE<6>_MC.D2 )
  );
  X_BUF \U3/DCORIE<7>  (
    .I(\U3/DCORIE<7>_MC.Q ),
    .O(\U3/DCORIE [7])
  );
  X_FF \U3/DCORIE<7>_MC.REG  (
    .I(\U3/DCORIE<7>_MC.D ),
    .CE(Vcc),
    .CLK(\U3/DCORIE<7>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\U3/DCORIE<7>_MC.Q )
  );
  X_INV \U3/DCORIE<7>_MC.REG_tsimcreated_inv_Mclk_II/FCLK_1621  (
    .I(\Mclk_II/FCLK ),
    .O(\U3/DCORIE<7>_MC.REG_tsimcreated_inv_Mclk_II/FCLK )
  );
  X_XOR2 \U3/DCORIE<7>_MC.D_1622  (
    .I0(\U3/DCORIE<7>_MC.D1 ),
    .I1(\U3/DCORIE<7>_MC.D2 ),
    .O(\U3/DCORIE<7>_MC.D )
  );
  X_ZERO \U3/DCORIE<7>_MC.D1_1623  (
    .O(\U3/DCORIE<7>_MC.D1 )
  );
  X_AND3 \U3/DCORIE<7>_MC.D2_PT_0_1624  (
    .I0(\MSPReset_II/UIM ),
    .I1(\AD<7>_II/UIM ),
    .I2(DCORIEw),
    .O(\U3/DCORIE<7>_MC.D2_PT_0 )
  );
  X_AND3 \U3/DCORIE<7>_MC.D2_PT_1_1625  (
    .I0(\MSPReset_II/UIM ),
    .I1(\U3/DCORIE [7]),
    .I2(\NlwInverterSignal_U3/DCORIE<7>_MC.D2_PT_1/IN2 ),
    .O(\U3/DCORIE<7>_MC.D2_PT_1 )
  );
  X_OR2 \U3/DCORIE<7>_MC.D2_1626  (
    .I0(\U3/DCORIE<7>_MC.D2_PT_0 ),
    .I1(\U3/DCORIE<7>_MC.D2_PT_1 ),
    .O(\U3/DCORIE<7>_MC.D2 )
  );
  X_BUF \LED1_MC.Q_1627  (
    .I(\LED1_MC.Q_tsimrenamed_net_ ),
    .O(\LED1_MC.Q )
  );
  X_BUF \LED1_MC.Q_tsimrenamed_net__1628  (
    .I(\LED1_MC.D ),
    .O(\LED1_MC.Q_tsimrenamed_net_ )
  );
  X_XOR2 \LED1_MC.D_1629  (
    .I0(\NlwInverterSignal_LED1_MC.D/IN0 ),
    .I1(\LED1_MC.D2 ),
    .O(\LED1_MC.D )
  );
  X_AND2 \LED1_MC.D1_1630  (
    .I0(\LightSense_II/UIM ),
    .I1(\NlwInverterSignal_LED1_MC.D1/IN1 ),
    .O(\LED1_MC.D1 )
  );
  X_ZERO \LED1_MC.D2_1631  (
    .O(\LED1_MC.D2 )
  );
  X_BUF \U9/MISCr<0>  (
    .I(\U9/MISCr<0>_MC.Q ),
    .O(\U9/MISCr [0])
  );
  X_OR2 \U9/MISCr<0>_MC_tsimcreated_prld__1632  (
    .I0(\FOOBAR3__ctinst/7 ),
    .I1(PRLD),
    .O(\U9/MISCr<0>_MC_tsimcreated_prld_ )
  );
  X_FF \U9/MISCr<0>_MC.REG  (
    .I(\U9/MISCr<0>_MC.D ),
    .CE(Vcc),
    .CLK(\U9/MISCr<0>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(\U9/MISCr<0>_MC_tsimcreated_prld_ ),
    .O(\U9/MISCr<0>_MC.Q )
  );
  X_INV \U9/MISCr<0>_MC.REG_tsimcreated_inv_Mclk_II/FCLK_1633  (
    .I(\Mclk_II/FCLK ),
    .O(\U9/MISCr<0>_MC.REG_tsimcreated_inv_Mclk_II/FCLK )
  );
  X_XOR2 \U9/MISCr<0>_MC.D_1634  (
    .I0(\U9/MISCr<0>_MC.D1 ),
    .I1(\U9/MISCr<0>_MC.D2 ),
    .O(\U9/MISCr<0>_MC.D )
  );
  X_ZERO \U9/MISCr<0>_MC.D1_1635  (
    .O(\U9/MISCr<0>_MC.D1 )
  );
  X_AND3 \U9/MISCr<0>_MC.D2_PT_0_1636  (
    .I0(\MSPReset_II/UIM ),
    .I1(\AD<0>_II/UIM ),
    .I2(DCOROUTw),
    .O(\U9/MISCr<0>_MC.D2_PT_0 )
  );
  X_AND3 \U9/MISCr<0>_MC.D2_PT_1_1637  (
    .I0(\MSPReset_II/UIM ),
    .I1(\NlwInverterSignal_U9/MISCr<0>_MC.D2_PT_1/IN1 ),
    .I2(\U9/MISCr [0]),
    .O(\U9/MISCr<0>_MC.D2_PT_1 )
  );
  X_OR2 \U9/MISCr<0>_MC.D2_1638  (
    .I0(\U9/MISCr<0>_MC.D2_PT_0 ),
    .I1(\U9/MISCr<0>_MC.D2_PT_1 ),
    .O(\U9/MISCr<0>_MC.D2 )
  );
  X_BUF \LED2_MC.Q_1639  (
    .I(\LED2_MC.Q_tsimrenamed_net_ ),
    .O(\LED2_MC.Q )
  );
  X_BUF \LED2_MC.Q_tsimrenamed_net__1640  (
    .I(\LED2_MC.D ),
    .O(\LED2_MC.Q_tsimrenamed_net_ )
  );
  X_XOR2 \LED2_MC.D_1641  (
    .I0(\NlwInverterSignal_LED2_MC.D/IN0 ),
    .I1(\LED2_MC.D2 ),
    .O(\LED2_MC.D )
  );
  X_AND2 \LED2_MC.D1_1642  (
    .I0(\LightSense_II/UIM ),
    .I1(\NlwInverterSignal_LED2_MC.D1/IN1 ),
    .O(\LED2_MC.D1 )
  );
  X_ZERO \LED2_MC.D2_1643  (
    .O(\LED2_MC.D2 )
  );
  X_BUF \U9/MISCr<1>  (
    .I(\U9/MISCr<1>_MC.Q ),
    .O(\U9/MISCr [1])
  );
  X_OR2 \U9/MISCr<1>_MC_tsimcreated_prld__1644  (
    .I0(\FOOBAR3__ctinst/7 ),
    .I1(PRLD),
    .O(\U9/MISCr<1>_MC_tsimcreated_prld_ )
  );
  X_FF \U9/MISCr<1>_MC.REG  (
    .I(\U9/MISCr<1>_MC.D ),
    .CE(Vcc),
    .CLK(\U9/MISCr<1>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(\U9/MISCr<1>_MC_tsimcreated_prld_ ),
    .O(\U9/MISCr<1>_MC.Q )
  );
  X_INV \U9/MISCr<1>_MC.REG_tsimcreated_inv_Mclk_II/FCLK_1645  (
    .I(\Mclk_II/FCLK ),
    .O(\U9/MISCr<1>_MC.REG_tsimcreated_inv_Mclk_II/FCLK )
  );
  X_XOR2 \U9/MISCr<1>_MC.D_1646  (
    .I0(\U9/MISCr<1>_MC.D1 ),
    .I1(\U9/MISCr<1>_MC.D2 ),
    .O(\U9/MISCr<1>_MC.D )
  );
  X_ZERO \U9/MISCr<1>_MC.D1_1647  (
    .O(\U9/MISCr<1>_MC.D1 )
  );
  X_AND3 \U9/MISCr<1>_MC.D2_PT_0_1648  (
    .I0(\MSPReset_II/UIM ),
    .I1(\AD<1>_II/UIM ),
    .I2(DCOROUTw),
    .O(\U9/MISCr<1>_MC.D2_PT_0 )
  );
  X_AND3 \U9/MISCr<1>_MC.D2_PT_1_1649  (
    .I0(\MSPReset_II/UIM ),
    .I1(\NlwInverterSignal_U9/MISCr<1>_MC.D2_PT_1/IN1 ),
    .I2(\U9/MISCr [1]),
    .O(\U9/MISCr<1>_MC.D2_PT_1 )
  );
  X_OR2 \U9/MISCr<1>_MC.D2_1650  (
    .I0(\U9/MISCr<1>_MC.D2_PT_0 ),
    .I1(\U9/MISCr<1>_MC.D2_PT_1 ),
    .O(\U9/MISCr<1>_MC.D2 )
  );
  X_BUF \LED3_MC.Q_1651  (
    .I(\LED3_MC.Q_tsimrenamed_net_ ),
    .O(\LED3_MC.Q )
  );
  X_BUF \LED3_MC.Q_tsimrenamed_net__1652  (
    .I(\LED3_MC.D ),
    .O(\LED3_MC.Q_tsimrenamed_net_ )
  );
  X_XOR2 \LED3_MC.D_1653  (
    .I0(\NlwInverterSignal_LED3_MC.D/IN0 ),
    .I1(\LED3_MC.D2 ),
    .O(\LED3_MC.D )
  );
  X_AND2 \LED3_MC.D1_1654  (
    .I0(\LightSense_II/UIM ),
    .I1(\NlwInverterSignal_LED3_MC.D1/IN1 ),
    .O(\LED3_MC.D1 )
  );
  X_ZERO \LED3_MC.D2_1655  (
    .O(\LED3_MC.D2 )
  );
  X_BUF \U9/MISCr<2>  (
    .I(\U9/MISCr<2>_MC.Q ),
    .O(\U9/MISCr [2])
  );
  X_OR2 \U9/MISCr<2>_MC_tsimcreated_prld__1656  (
    .I0(\FOOBAR3__ctinst/7 ),
    .I1(PRLD),
    .O(\U9/MISCr<2>_MC_tsimcreated_prld_ )
  );
  X_FF \U9/MISCr<2>_MC.REG  (
    .I(\U9/MISCr<2>_MC.D ),
    .CE(Vcc),
    .CLK(\U9/MISCr<2>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(\U9/MISCr<2>_MC_tsimcreated_prld_ ),
    .O(\U9/MISCr<2>_MC.Q )
  );
  X_INV \U9/MISCr<2>_MC.REG_tsimcreated_inv_Mclk_II/FCLK_1657  (
    .I(\Mclk_II/FCLK ),
    .O(\U9/MISCr<2>_MC.REG_tsimcreated_inv_Mclk_II/FCLK )
  );
  X_XOR2 \U9/MISCr<2>_MC.D_1658  (
    .I0(\U9/MISCr<2>_MC.D1 ),
    .I1(\U9/MISCr<2>_MC.D2 ),
    .O(\U9/MISCr<2>_MC.D )
  );
  X_ZERO \U9/MISCr<2>_MC.D1_1659  (
    .O(\U9/MISCr<2>_MC.D1 )
  );
  X_AND3 \U9/MISCr<2>_MC.D2_PT_0_1660  (
    .I0(\MSPReset_II/UIM ),
    .I1(\AD<2>_II/UIM ),
    .I2(DCOROUTw),
    .O(\U9/MISCr<2>_MC.D2_PT_0 )
  );
  X_AND3 \U9/MISCr<2>_MC.D2_PT_1_1661  (
    .I0(\MSPReset_II/UIM ),
    .I1(\NlwInverterSignal_U9/MISCr<2>_MC.D2_PT_1/IN1 ),
    .I2(\U9/MISCr [2]),
    .O(\U9/MISCr<2>_MC.D2_PT_1 )
  );
  X_OR2 \U9/MISCr<2>_MC.D2_1662  (
    .I0(\U9/MISCr<2>_MC.D2_PT_0 ),
    .I1(\U9/MISCr<2>_MC.D2_PT_1 ),
    .O(\U9/MISCr<2>_MC.D2 )
  );
  X_BUF \LED4_MC.Q_1663  (
    .I(\LED4_MC.Q_tsimrenamed_net_ ),
    .O(\LED4_MC.Q )
  );
  X_BUF \LED4_MC.Q_tsimrenamed_net__1664  (
    .I(\LED4_MC.D ),
    .O(\LED4_MC.Q_tsimrenamed_net_ )
  );
  X_XOR2 \LED4_MC.D_1665  (
    .I0(\NlwInverterSignal_LED4_MC.D/IN0 ),
    .I1(\LED4_MC.D2 ),
    .O(\LED4_MC.D )
  );
  X_AND2 \LED4_MC.D1_1666  (
    .I0(\LightSense_II/UIM ),
    .I1(\NlwInverterSignal_LED4_MC.D1/IN1 ),
    .O(\LED4_MC.D1 )
  );
  X_ZERO \LED4_MC.D2_1667  (
    .O(\LED4_MC.D2 )
  );
  X_BUF \U9/MISCr<3>  (
    .I(\U9/MISCr<3>_MC.Q ),
    .O(\U9/MISCr [3])
  );
  X_OR2 \U9/MISCr<3>_MC_tsimcreated_prld__1668  (
    .I0(\FOOBAR3__ctinst/7 ),
    .I1(PRLD),
    .O(\U9/MISCr<3>_MC_tsimcreated_prld_ )
  );
  X_FF \U9/MISCr<3>_MC.REG  (
    .I(\U9/MISCr<3>_MC.D ),
    .CE(Vcc),
    .CLK(\U9/MISCr<3>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(\U9/MISCr<3>_MC_tsimcreated_prld_ ),
    .O(\U9/MISCr<3>_MC.Q )
  );
  X_INV \U9/MISCr<3>_MC.REG_tsimcreated_inv_Mclk_II/FCLK_1669  (
    .I(\Mclk_II/FCLK ),
    .O(\U9/MISCr<3>_MC.REG_tsimcreated_inv_Mclk_II/FCLK )
  );
  X_XOR2 \U9/MISCr<3>_MC.D_1670  (
    .I0(\U9/MISCr<3>_MC.D1 ),
    .I1(\U9/MISCr<3>_MC.D2 ),
    .O(\U9/MISCr<3>_MC.D )
  );
  X_ZERO \U9/MISCr<3>_MC.D1_1671  (
    .O(\U9/MISCr<3>_MC.D1 )
  );
  X_AND3 \U9/MISCr<3>_MC.D2_PT_0_1672  (
    .I0(\MSPReset_II/UIM ),
    .I1(\AD<3>_II/UIM ),
    .I2(DCOROUTw),
    .O(\U9/MISCr<3>_MC.D2_PT_0 )
  );
  X_AND3 \U9/MISCr<3>_MC.D2_PT_1_1673  (
    .I0(\MSPReset_II/UIM ),
    .I1(\NlwInverterSignal_U9/MISCr<3>_MC.D2_PT_1/IN1 ),
    .I2(\U9/MISCr [3]),
    .O(\U9/MISCr<3>_MC.D2_PT_1 )
  );
  X_OR2 \U9/MISCr<3>_MC.D2_1674  (
    .I0(\U9/MISCr<3>_MC.D2_PT_0 ),
    .I1(\U9/MISCr<3>_MC.D2_PT_1 ),
    .O(\U9/MISCr<3>_MC.D2 )
  );
  X_BUF \LED5_MC.Q_1675  (
    .I(\LED5_MC.Q_tsimrenamed_net_ ),
    .O(\LED5_MC.Q )
  );
  X_BUF \LED5_MC.Q_tsimrenamed_net__1676  (
    .I(\LED5_MC.D ),
    .O(\LED5_MC.Q_tsimrenamed_net_ )
  );
  X_XOR2 \LED5_MC.D_1677  (
    .I0(\NlwInverterSignal_LED5_MC.D/IN0 ),
    .I1(\LED5_MC.D2 ),
    .O(\LED5_MC.D )
  );
  X_AND2 \LED5_MC.D1_1678  (
    .I0(\LightSense_II/UIM ),
    .I1(\NlwInverterSignal_LED5_MC.D1/IN1 ),
    .O(\LED5_MC.D1 )
  );
  X_ZERO \LED5_MC.D2_1679  (
    .O(\LED5_MC.D2 )
  );
  X_BUF \U9/MISCr<4>  (
    .I(\U9/MISCr<4>_MC.Q ),
    .O(\U9/MISCr [4])
  );
  X_OR2 \U9/MISCr<4>_MC_tsimcreated_prld__1680  (
    .I0(\FOOBAR3__ctinst/7 ),
    .I1(PRLD),
    .O(\U9/MISCr<4>_MC_tsimcreated_prld_ )
  );
  X_FF \U9/MISCr<4>_MC.REG  (
    .I(\U9/MISCr<4>_MC.D ),
    .CE(Vcc),
    .CLK(\U9/MISCr<4>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(\U9/MISCr<4>_MC_tsimcreated_prld_ ),
    .O(\U9/MISCr<4>_MC.Q )
  );
  X_INV \U9/MISCr<4>_MC.REG_tsimcreated_inv_Mclk_II/FCLK_1681  (
    .I(\Mclk_II/FCLK ),
    .O(\U9/MISCr<4>_MC.REG_tsimcreated_inv_Mclk_II/FCLK )
  );
  X_XOR2 \U9/MISCr<4>_MC.D_1682  (
    .I0(\U9/MISCr<4>_MC.D1 ),
    .I1(\U9/MISCr<4>_MC.D2 ),
    .O(\U9/MISCr<4>_MC.D )
  );
  X_ZERO \U9/MISCr<4>_MC.D1_1683  (
    .O(\U9/MISCr<4>_MC.D1 )
  );
  X_AND3 \U9/MISCr<4>_MC.D2_PT_0_1684  (
    .I0(\MSPReset_II/UIM ),
    .I1(\AD<4>_II/UIM ),
    .I2(DCOROUTw),
    .O(\U9/MISCr<4>_MC.D2_PT_0 )
  );
  X_AND3 \U9/MISCr<4>_MC.D2_PT_1_1685  (
    .I0(\MSPReset_II/UIM ),
    .I1(\NlwInverterSignal_U9/MISCr<4>_MC.D2_PT_1/IN1 ),
    .I2(\U9/MISCr [4]),
    .O(\U9/MISCr<4>_MC.D2_PT_1 )
  );
  X_OR2 \U9/MISCr<4>_MC.D2_1686  (
    .I0(\U9/MISCr<4>_MC.D2_PT_0 ),
    .I1(\U9/MISCr<4>_MC.D2_PT_1 ),
    .O(\U9/MISCr<4>_MC.D2 )
  );
  X_BUF \MHSI_MC.Q_1687  (
    .I(\MHSI_MC.Q_tsimrenamed_net_ ),
    .O(\MHSI_MC.Q )
  );
  X_BUF \MHSI_MC.Q_tsimrenamed_net__1688  (
    .I(\MHSI_MC.D ),
    .O(\MHSI_MC.Q_tsimrenamed_net_ )
  );
  X_XOR2 \MHSI_MC.D_1689  (
    .I0(\MHSI_MC.D1 ),
    .I1(\MHSI_MC.D2 ),
    .O(\MHSI_MC.D )
  );
  X_AND2 \MHSI_MC.D1_1690  (
    .I0(\HSI_II/UIM ),
    .I1(\HSI_II/UIM ),
    .O(\MHSI_MC.D1 )
  );
  X_ZERO \MHSI_MC.D2_1691  (
    .O(\MHSI_MC.D2 )
  );
  X_BUF \MTRpwr_MC.Q_1692  (
    .I(\MTRpwr_MC.Q_tsimrenamed_net_ ),
    .O(\MTRpwr_MC.Q )
  );
  X_BUF \MTRpwr_MC.UIM_1693  (
    .I(\MTRpwr_MC.Q_tsimrenamed_net_ ),
    .O(\MTRpwr_MC.UIM )
  );
  X_OR2 MTRpwr_MC_tsimcreated_prld__1694 (
    .I0(\FOOBAR3__ctinst/7 ),
    .I1(PRLD),
    .O(MTRpwr_MC_tsimcreated_prld_)
  );
  X_FF \MTRpwr_MC.REG  (
    .I(\MTRpwr_MC.D ),
    .CE(Vcc),
    .CLK(\MTRpwr_MC.REG_tsimcreated_inv_Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(MTRpwr_MC_tsimcreated_prld_),
    .O(\MTRpwr_MC.Q_tsimrenamed_net_ )
  );
  X_INV \MTRpwr_MC.REG_tsimcreated_inv_Mclk_II/FCLK_1695  (
    .I(\Mclk_II/FCLK ),
    .O(\MTRpwr_MC.REG_tsimcreated_inv_Mclk_II/FCLK )
  );
  X_XOR2 \MTRpwr_MC.D_1696  (
    .I0(\MTRpwr_MC.D1 ),
    .I1(\MTRpwr_MC.D2 ),
    .O(\MTRpwr_MC.D )
  );
  X_ZERO \MTRpwr_MC.D1_1697  (
    .O(\MTRpwr_MC.D1 )
  );
  X_AND3 \MTRpwr_MC.D2_PT_0_1698  (
    .I0(\MSPReset_II/UIM ),
    .I1(\AD<5>_II/UIM ),
    .I2(DCOROUTw),
    .O(\MTRpwr_MC.D2_PT_0 )
  );
  X_AND3 \MTRpwr_MC.D2_PT_1_1699  (
    .I0(\MSPReset_II/UIM ),
    .I1(\NlwInverterSignal_MTRpwr_MC.D2_PT_1/IN1 ),
    .I2(\MTRpwr_MC.UIM ),
    .O(\MTRpwr_MC.D2_PT_1 )
  );
  X_OR2 \MTRpwr_MC.D2_1700  (
    .I0(\MTRpwr_MC.D2_PT_0 ),
    .I1(\MTRpwr_MC.D2_PT_1 ),
    .O(\MTRpwr_MC.D2 )
  );
  X_BUF \MTRpwrn_MC.Q_1701  (
    .I(\MTRpwrn_MC.Q_tsimrenamed_net_ ),
    .O(\MTRpwrn_MC.Q )
  );
  X_BUF \MTRpwrn_MC.UIM_1702  (
    .I(\MTRpwrn_MC.Q_tsimrenamed_net_ ),
    .O(\MTRpwrn_MC.UIM )
  );
  X_OR2 MTRpwrn_MC_tsimcreated_prld__1703 (
    .I0(\FOOBAR7__ctinst/0 ),
    .I1(PRLD),
    .O(MTRpwrn_MC_tsimcreated_prld_)
  );
  X_FF \MTRpwrn_MC.REG  (
    .I(\MTRpwrn_MC.D ),
    .CE(Vcc),
    .CLK(\MTRpwrn_MC.REG_tsimcreated_inv_Mclk_II/FCLK ),
    .SET(MTRpwrn_MC_tsimcreated_prld_),
    .RST(Gnd),
    .O(\MTRpwrn_MC.Q_tsimrenamed_net_ )
  );
  X_INV \MTRpwrn_MC.REG_tsimcreated_inv_Mclk_II/FCLK_1704  (
    .I(\Mclk_II/FCLK ),
    .O(\MTRpwrn_MC.REG_tsimcreated_inv_Mclk_II/FCLK )
  );
  X_XOR2 \MTRpwrn_MC.D_1705  (
    .I0(\NlwInverterSignal_MTRpwrn_MC.D/IN0 ),
    .I1(\MTRpwrn_MC.D2 ),
    .O(\MTRpwrn_MC.D )
  );
  X_ZERO \MTRpwrn_MC.D1_1706  (
    .O(\MTRpwrn_MC.D1 )
  );
  X_AND3 \MTRpwrn_MC.D2_PT_0_1707  (
    .I0(\MSPReset_II/UIM ),
    .I1(\AD<5>_II/UIM ),
    .I2(DCOROUTw),
    .O(\MTRpwrn_MC.D2_PT_0 )
  );
  X_AND3 \MTRpwrn_MC.D2_PT_1_1708  (
    .I0(\MSPReset_II/UIM ),
    .I1(\NlwInverterSignal_MTRpwrn_MC.D2_PT_1/IN1 ),
    .I2(\NlwInverterSignal_MTRpwrn_MC.D2_PT_1/IN2 ),
    .O(\MTRpwrn_MC.D2_PT_1 )
  );
  X_OR2 \MTRpwrn_MC.D2_1709  (
    .I0(\MTRpwrn_MC.D2_PT_0 ),
    .I1(\MTRpwrn_MC.D2_PT_1 ),
    .O(\MTRpwrn_MC.D2 )
  );
  X_BUF \MTXI_MC.Q_1710  (
    .I(\MTXI_MC.Q_tsimrenamed_net_ ),
    .O(\MTXI_MC.Q )
  );
  X_BUF \MTXI_MC.Q_tsimrenamed_net__1711  (
    .I(\MTXI_MC.D ),
    .O(\MTXI_MC.Q_tsimrenamed_net_ )
  );
  X_XOR2 \MTXI_MC.D_1712  (
    .I0(\MTXI_MC.D1 ),
    .I1(\MTXI_MC.D2 ),
    .O(\MTXI_MC.D )
  );
  X_AND2 \MTXI_MC.D1_1713  (
    .I0(\TXI_II/UIM ),
    .I1(\TXI_II/UIM ),
    .O(\MTXI_MC.D1 )
  );
  X_ZERO \MTXI_MC.D2_1714  (
    .O(\MTXI_MC.D2 )
  );
  X_BUF \PAH0_MC.Q_1715  (
    .I(\PAH0_MC.Q_tsimrenamed_net_ ),
    .O(\PAH0_MC.Q )
  );
  X_BUF \PAH0_MC.Q_tsimrenamed_net__1716  (
    .I(\PAH0_MC.D ),
    .O(\PAH0_MC.Q_tsimrenamed_net_ )
  );
  X_XOR2 \PAH0_MC.D_1717  (
    .I0(\PAH0_MC.D1 ),
    .I1(\PAH0_MC.D2 ),
    .O(\PAH0_MC.D )
  );
  X_ZERO \PAH0_MC.D1_1718  (
    .O(\PAH0_MC.D1 )
  );
  X_ZERO \PAH0_MC.D2_1719  (
    .O(\PAH0_MC.D2 )
  );
  X_BUF \PAH1_MC.Q_1720  (
    .I(\PAH1_MC.Q_tsimrenamed_net_ ),
    .O(\PAH1_MC.Q )
  );
  X_BUF \PAH1_MC.Q_tsimrenamed_net__1721  (
    .I(\PAH1_MC.D ),
    .O(\PAH1_MC.Q_tsimrenamed_net_ )
  );
  X_XOR2 \PAH1_MC.D_1722  (
    .I0(\PAH1_MC.D1 ),
    .I1(\PAH1_MC.D2 ),
    .O(\PAH1_MC.D )
  );
  X_ZERO \PAH1_MC.D1_1723  (
    .O(\PAH1_MC.D1 )
  );
  X_ZERO \PAH1_MC.D2_1724  (
    .O(\PAH1_MC.D2 )
  );
  X_BUF \PAL0_MC.Q_1725  (
    .I(\PAL0_MC.Q_tsimrenamed_net_ ),
    .O(\PAL0_MC.Q )
  );
  X_BUF \PAL0_MC.Q_tsimrenamed_net__1726  (
    .I(\PAL0_MC.D ),
    .O(\PAL0_MC.Q_tsimrenamed_net_ )
  );
  X_XOR2 \PAL0_MC.D_1727  (
    .I0(\PAL0_MC.D1 ),
    .I1(\PAL0_MC.D2 ),
    .O(\PAL0_MC.D )
  );
  X_ZERO \PAL0_MC.D1_1728  (
    .O(\PAL0_MC.D1 )
  );
  X_AND5 \PAL0_MC.D2_PT_0_1729  (
    .I0(\DIR0_II/UIM ),
    .I1(\NlwInverterSignal_PAL0_MC.D2_PT_0/IN1 ),
    .I2(\MTRpwr_MC.UIM ),
    .I3(\NlwInverterSignal_PAL0_MC.D2_PT_0/IN3 ),
    .I4(\NlwInverterSignal_PAL0_MC.D2_PT_0/IN4 ),
    .O(\PAL0_MC.D2_PT_0 )
  );
  X_AND5 \PAL0_MC.D2_PT_1_1730  (
    .I0(\NlwInverterSignal_PAL0_MC.D2_PT_1/IN0 ),
    .I1(\NlwInverterSignal_PAL0_MC.D2_PT_1/IN1 ),
    .I2(\MTRpwr_MC.UIM ),
    .I3(\PWM1_II/UIM ),
    .I4(\NlwInverterSignal_PAL0_MC.D2_PT_1/IN4 ),
    .O(\PAL0_MC.D2_PT_1 )
  );
  X_OR2 \PAL0_MC.D2_1731  (
    .I0(\PAL0_MC.D2_PT_0 ),
    .I1(\PAL0_MC.D2_PT_1 ),
    .O(\PAL0_MC.D2 )
  );
  X_BUF NET3248_1732 (
    .I(\NET3248_MC.Q ),
    .O(NET3248)
  );
  X_XOR2 NET3248_MC_tsimcreated_xor__1733 (
    .I0(\NET3248_MC.D ),
    .I1(\NET3248_MC.Q ),
    .O(NET3248_MC_tsimcreated_xor_)
  );
  X_FF \NET3248_MC.REG  (
    .I(NET3248_MC_tsimcreated_xor_),
    .CE(Vcc),
    .CLK(\NET3248_MC.REG_tsimcreated_inv_Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\NET3248_MC.Q )
  );
  X_INV \NET3248_MC.REG_tsimcreated_inv_Mclk_II/FCLK_1734  (
    .I(\Mclk_II/FCLK ),
    .O(\NET3248_MC.REG_tsimcreated_inv_Mclk_II/FCLK )
  );
  X_XOR2 \NET3248_MC.D_1735  (
    .I0(\NET3248_MC.D1 ),
    .I1(\NET3248_MC.D2 ),
    .O(\NET3248_MC.D )
  );
  X_ZERO \NET3248_MC.D1_1736  (
    .O(\NET3248_MC.D1 )
  );
  X_AND6 \NET3248_MC.D2_PT_0_1737  (
    .I0(\MSPReset_II/UIM ),
    .I1(\NlwInverterSignal_NET3248_MC.D2_PT_0/IN1 ),
    .I2(\NlwInverterSignal_NET3248_MC.D2_PT_0/IN2 ),
    .I3(\NlwInverterSignal_NET3248_MC.D2_PT_0/IN3 ),
    .I4(\U5/RLS0r ),
    .I5(\NlwInverterSignal_NET3248_MC.D2_PT_0/IN5 ),
    .O(\NET3248_MC.D2_PT_0 )
  );
  X_AND6 \NET3248_MC.D2_PT_1_1738  (
    .I0(\MSPReset_II/UIM ),
    .I1(\NlwInverterSignal_NET3248_MC.D2_PT_1/IN1 ),
    .I2(\DIR0_II/UIM ),
    .I3(\NlwInverterSignal_NET3248_MC.D2_PT_1/IN3 ),
    .I4(\U5/FLS0r ),
    .I5(\NlwInverterSignal_NET3248_MC.D2_PT_1/IN5 ),
    .O(\NET3248_MC.D2_PT_1 )
  );
  X_AND8 \NET3248_MC.D2_PT_2_1739  (
    .I0(\MSPReset_II/UIM ),
    .I1(\RLS0_II/UIM ),
    .I2(\NlwInverterSignal_NET3248_MC.D2_PT_2/IN2 ),
    .I3(\NlwInverterSignal_NET3248_MC.D2_PT_2/IN3 ),
    .I4(\NlwInverterSignal_NET3248_MC.D2_PT_2/IN4 ),
    .I5(\NlwInverterSignal_NET3248_MC.D2_PT_2/IN5 ),
    .I6(\Brake0_II/UIM ),
    .I7(NET3248),
    .O(\NET3248_MC.D2_PT_2 )
  );
  X_AND8 \NET3248_MC.D2_PT_3_1740  (
    .I0(\MSPReset_II/UIM ),
    .I1(\NlwInverterSignal_NET3248_MC.D2_PT_3/IN1 ),
    .I2(\NlwInverterSignal_NET3248_MC.D2_PT_3/IN2 ),
    .I3(\DIR0_II/UIM ),
    .I4(\FLS0_II/UIM ),
    .I5(\NlwInverterSignal_NET3248_MC.D2_PT_3/IN5 ),
    .I6(\Brake0_II/UIM ),
    .I7(NET3248),
    .O(\NET3248_MC.D2_PT_3 )
  );
  X_AND8 \NET3248_MC.D2_PT_4_1741  (
    .I0(\MSPReset_II/UIM ),
    .I1(\NlwInverterSignal_NET3248_MC.D2_PT_4/IN1 ),
    .I2(\NlwInverterSignal_NET3248_MC.D2_PT_4/IN2 ),
    .I3(\DIR0_II/UIM ),
    .I4(\NlwInverterSignal_NET3248_MC.D2_PT_4/IN4 ),
    .I5(\NlwInverterSignal_NET3248_MC.D2_PT_4/IN5 ),
    .I6(\Brake0_II/UIM ),
    .I7(NET3248),
    .O(\NET3248_MC.D2_PT_4 )
  );
  X_AND8 \NET3248_MC.D2_PT_5_1742  (
    .I0(\MSPReset_II/UIM ),
    .I1(\NlwInverterSignal_NET3248_MC.D2_PT_5/IN1 ),
    .I2(\NlwInverterSignal_NET3248_MC.D2_PT_5/IN2 ),
    .I3(\NlwInverterSignal_NET3248_MC.D2_PT_5/IN3 ),
    .I4(\NlwInverterSignal_NET3248_MC.D2_PT_5/IN4 ),
    .I5(\NlwInverterSignal_NET3248_MC.D2_PT_5/IN5 ),
    .I6(\Brake0_II/UIM ),
    .I7(NET3248),
    .O(\NET3248_MC.D2_PT_5 )
  );
  X_OR6 \NET3248_MC.D2_1743  (
    .I0(\NET3248_MC.D2_PT_0 ),
    .I1(\NET3248_MC.D2_PT_1 ),
    .I2(\NET3248_MC.D2_PT_2 ),
    .I3(\NET3248_MC.D2_PT_3 ),
    .I4(\NET3248_MC.D2_PT_4 ),
    .I5(\NET3248_MC.D2_PT_5 ),
    .O(\NET3248_MC.D2 )
  );
  X_BUF \PAL1_MC.Q_1744  (
    .I(\PAL1_MC.Q_tsimrenamed_net_ ),
    .O(\PAL1_MC.Q )
  );
  X_BUF \PAL1_MC.Q_tsimrenamed_net__1745  (
    .I(\PAL1_MC.D ),
    .O(\PAL1_MC.Q_tsimrenamed_net_ )
  );
  X_XOR2 \PAL1_MC.D_1746  (
    .I0(\PAL1_MC.D1 ),
    .I1(\PAL1_MC.D2 ),
    .O(\PAL1_MC.D )
  );
  X_ZERO \PAL1_MC.D1_1747  (
    .O(\PAL1_MC.D1 )
  );
  X_AND5 \PAL1_MC.D2_PT_0_1748  (
    .I0(\DIR1_II/UIM ),
    .I1(\NlwInverterSignal_PAL1_MC.D2_PT_0/IN1 ),
    .I2(\MTRpwr_MC.UIM ),
    .I3(\NlwInverterSignal_PAL1_MC.D2_PT_0/IN3 ),
    .I4(\NlwInverterSignal_PAL1_MC.D2_PT_0/IN4 ),
    .O(\PAL1_MC.D2_PT_0 )
  );
  X_AND5 \PAL1_MC.D2_PT_1_1749  (
    .I0(\NlwInverterSignal_PAL1_MC.D2_PT_1/IN0 ),
    .I1(\NlwInverterSignal_PAL1_MC.D2_PT_1/IN1 ),
    .I2(\MTRpwr_MC.UIM ),
    .I3(\PWM2_II/UIM ),
    .I4(\NlwInverterSignal_PAL1_MC.D2_PT_1/IN4 ),
    .O(\PAL1_MC.D2_PT_1 )
  );
  X_OR2 \PAL1_MC.D2_1750  (
    .I0(\PAL1_MC.D2_PT_0 ),
    .I1(\PAL1_MC.D2_PT_1 ),
    .O(\PAL1_MC.D2 )
  );
  X_BUF NET3253_1751 (
    .I(\NET3253_MC.Q ),
    .O(NET3253)
  );
  X_XOR2 NET3253_MC_tsimcreated_xor__1752 (
    .I0(\NET3253_MC.D ),
    .I1(\NET3253_MC.Q ),
    .O(NET3253_MC_tsimcreated_xor_)
  );
  X_FF \NET3253_MC.REG  (
    .I(NET3253_MC_tsimcreated_xor_),
    .CE(Vcc),
    .CLK(\NET3253_MC.REG_tsimcreated_inv_Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\NET3253_MC.Q )
  );
  X_INV \NET3253_MC.REG_tsimcreated_inv_Mclk_II/FCLK_1753  (
    .I(\Mclk_II/FCLK ),
    .O(\NET3253_MC.REG_tsimcreated_inv_Mclk_II/FCLK )
  );
  X_XOR2 \NET3253_MC.D_1754  (
    .I0(\NET3253_MC.D1 ),
    .I1(\NET3253_MC.D2 ),
    .O(\NET3253_MC.D )
  );
  X_ZERO \NET3253_MC.D1_1755  (
    .O(\NET3253_MC.D1 )
  );
  X_AND6 \NET3253_MC.D2_PT_0_1756  (
    .I0(\MSPReset_II/UIM ),
    .I1(\NlwInverterSignal_NET3253_MC.D2_PT_0/IN1 ),
    .I2(\DIR1_II/UIM ),
    .I3(\NlwInverterSignal_NET3253_MC.D2_PT_0/IN3 ),
    .I4(\U5/FLS1r ),
    .I5(\NlwInverterSignal_NET3253_MC.D2_PT_0/IN5 ),
    .O(\NET3253_MC.D2_PT_0 )
  );
  X_AND6 \NET3253_MC.D2_PT_1_1757  (
    .I0(\MSPReset_II/UIM ),
    .I1(\NlwInverterSignal_NET3253_MC.D2_PT_1/IN1 ),
    .I2(\NlwInverterSignal_NET3253_MC.D2_PT_1/IN2 ),
    .I3(\NlwInverterSignal_NET3253_MC.D2_PT_1/IN3 ),
    .I4(\U5/RLS1r ),
    .I5(\NlwInverterSignal_NET3253_MC.D2_PT_1/IN5 ),
    .O(\NET3253_MC.D2_PT_1 )
  );
  X_AND8 \NET3253_MC.D2_PT_2_1758  (
    .I0(\MSPReset_II/UIM ),
    .I1(\NlwInverterSignal_NET3253_MC.D2_PT_2/IN1 ),
    .I2(\NlwInverterSignal_NET3253_MC.D2_PT_2/IN2 ),
    .I3(\NlwInverterSignal_NET3253_MC.D2_PT_2/IN3 ),
    .I4(\DIR1_II/UIM ),
    .I5(\FLS1_II/UIM ),
    .I6(\Brake1_II/UIM ),
    .I7(NET3253),
    .O(\NET3253_MC.D2_PT_2 )
  );
  X_AND8 \NET3253_MC.D2_PT_3_1759  (
    .I0(\MSPReset_II/UIM ),
    .I1(\NlwInverterSignal_NET3253_MC.D2_PT_3/IN1 ),
    .I2(\NlwInverterSignal_NET3253_MC.D2_PT_3/IN2 ),
    .I3(\NlwInverterSignal_NET3253_MC.D2_PT_3/IN3 ),
    .I4(\DIR1_II/UIM ),
    .I5(\NlwInverterSignal_NET3253_MC.D2_PT_3/IN5 ),
    .I6(\Brake1_II/UIM ),
    .I7(NET3253),
    .O(\NET3253_MC.D2_PT_3 )
  );
  X_AND8 \NET3253_MC.D2_PT_4_1760  (
    .I0(\MSPReset_II/UIM ),
    .I1(\NlwInverterSignal_NET3253_MC.D2_PT_4/IN1 ),
    .I2(\NlwInverterSignal_NET3253_MC.D2_PT_4/IN2 ),
    .I3(\NlwInverterSignal_NET3253_MC.D2_PT_4/IN3 ),
    .I4(\NlwInverterSignal_NET3253_MC.D2_PT_4/IN4 ),
    .I5(\RLS1_II/UIM ),
    .I6(\Brake1_II/UIM ),
    .I7(NET3253),
    .O(\NET3253_MC.D2_PT_4 )
  );
  X_AND8 \NET3253_MC.D2_PT_5_1761  (
    .I0(\MSPReset_II/UIM ),
    .I1(\NlwInverterSignal_NET3253_MC.D2_PT_5/IN1 ),
    .I2(\NlwInverterSignal_NET3253_MC.D2_PT_5/IN2 ),
    .I3(\NlwInverterSignal_NET3253_MC.D2_PT_5/IN3 ),
    .I4(\NlwInverterSignal_NET3253_MC.D2_PT_5/IN4 ),
    .I5(\NlwInverterSignal_NET3253_MC.D2_PT_5/IN5 ),
    .I6(\Brake1_II/UIM ),
    .I7(NET3253),
    .O(\NET3253_MC.D2_PT_5 )
  );
  X_OR6 \NET3253_MC.D2_1762  (
    .I0(\NET3253_MC.D2_PT_0 ),
    .I1(\NET3253_MC.D2_PT_1 ),
    .I2(\NET3253_MC.D2_PT_2 ),
    .I3(\NET3253_MC.D2_PT_3 ),
    .I4(\NET3253_MC.D2_PT_4 ),
    .I5(\NET3253_MC.D2_PT_5 ),
    .O(\NET3253_MC.D2 )
  );
  X_BUF \PBH0_MC.Q_1763  (
    .I(\PBH0_MC.Q_tsimrenamed_net_ ),
    .O(\PBH0_MC.Q )
  );
  X_BUF \PBH0_MC.Q_tsimrenamed_net__1764  (
    .I(\PBH0_MC.D ),
    .O(\PBH0_MC.Q_tsimrenamed_net_ )
  );
  X_XOR2 \PBH0_MC.D_1765  (
    .I0(\PBH0_MC.D1 ),
    .I1(\PBH0_MC.D2 ),
    .O(\PBH0_MC.D )
  );
  X_ZERO \PBH0_MC.D1_1766  (
    .O(\PBH0_MC.D1 )
  );
  X_ZERO \PBH0_MC.D2_1767  (
    .O(\PBH0_MC.D2 )
  );
  X_BUF \PBH1_MC.Q_1768  (
    .I(\PBH1_MC.Q_tsimrenamed_net_ ),
    .O(\PBH1_MC.Q )
  );
  X_BUF \PBH1_MC.Q_tsimrenamed_net__1769  (
    .I(\PBH1_MC.D ),
    .O(\PBH1_MC.Q_tsimrenamed_net_ )
  );
  X_XOR2 \PBH1_MC.D_1770  (
    .I0(\PBH1_MC.D1 ),
    .I1(\PBH1_MC.D2 ),
    .O(\PBH1_MC.D )
  );
  X_ZERO \PBH1_MC.D1_1771  (
    .O(\PBH1_MC.D1 )
  );
  X_ZERO \PBH1_MC.D2_1772  (
    .O(\PBH1_MC.D2 )
  );
  X_BUF \PBL0_MC.Q_1773  (
    .I(\PBL0_MC.Q_tsimrenamed_net_ ),
    .O(\PBL0_MC.Q )
  );
  X_BUF \PBL0_MC.Q_tsimrenamed_net__1774  (
    .I(\PBL0_MC.D ),
    .O(\PBL0_MC.Q_tsimrenamed_net_ )
  );
  X_XOR2 \PBL0_MC.D_1775  (
    .I0(\PBL0_MC.D1 ),
    .I1(\PBL0_MC.D2 ),
    .O(\PBL0_MC.D )
  );
  X_ZERO \PBL0_MC.D1_1776  (
    .O(\PBL0_MC.D1 )
  );
  X_AND5 \PBL0_MC.D2_PT_0_1777  (
    .I0(\DIR0_II/UIM ),
    .I1(\NlwInverterSignal_PBL0_MC.D2_PT_0/IN1 ),
    .I2(\MTRpwr_MC.UIM ),
    .I3(\PWM1_II/UIM ),
    .I4(\NlwInverterSignal_PBL0_MC.D2_PT_0/IN4 ),
    .O(\PBL0_MC.D2_PT_0 )
  );
  X_AND5 \PBL0_MC.D2_PT_1_1778  (
    .I0(\NlwInverterSignal_PBL0_MC.D2_PT_1/IN0 ),
    .I1(\NlwInverterSignal_PBL0_MC.D2_PT_1/IN1 ),
    .I2(\MTRpwr_MC.UIM ),
    .I3(\NlwInverterSignal_PBL0_MC.D2_PT_1/IN3 ),
    .I4(\NlwInverterSignal_PBL0_MC.D2_PT_1/IN4 ),
    .O(\PBL0_MC.D2_PT_1 )
  );
  X_OR2 \PBL0_MC.D2_1779  (
    .I0(\PBL0_MC.D2_PT_0 ),
    .I1(\PBL0_MC.D2_PT_1 ),
    .O(\PBL0_MC.D2 )
  );
  X_BUF \PBL1_MC.Q_1780  (
    .I(\PBL1_MC.Q_tsimrenamed_net_ ),
    .O(\PBL1_MC.Q )
  );
  X_BUF \PBL1_MC.Q_tsimrenamed_net__1781  (
    .I(\PBL1_MC.D ),
    .O(\PBL1_MC.Q_tsimrenamed_net_ )
  );
  X_XOR2 \PBL1_MC.D_1782  (
    .I0(\PBL1_MC.D1 ),
    .I1(\PBL1_MC.D2 ),
    .O(\PBL1_MC.D )
  );
  X_ZERO \PBL1_MC.D1_1783  (
    .O(\PBL1_MC.D1 )
  );
  X_AND5 \PBL1_MC.D2_PT_0_1784  (
    .I0(\DIR1_II/UIM ),
    .I1(\NlwInverterSignal_PBL1_MC.D2_PT_0/IN1 ),
    .I2(\MTRpwr_MC.UIM ),
    .I3(\PWM2_II/UIM ),
    .I4(\NlwInverterSignal_PBL1_MC.D2_PT_0/IN4 ),
    .O(\PBL1_MC.D2_PT_0 )
  );
  X_AND5 \PBL1_MC.D2_PT_1_1785  (
    .I0(\NlwInverterSignal_PBL1_MC.D2_PT_1/IN0 ),
    .I1(\NlwInverterSignal_PBL1_MC.D2_PT_1/IN1 ),
    .I2(\MTRpwr_MC.UIM ),
    .I3(\NlwInverterSignal_PBL1_MC.D2_PT_1/IN3 ),
    .I4(\NlwInverterSignal_PBL1_MC.D2_PT_1/IN4 ),
    .O(\PBL1_MC.D2_PT_1 )
  );
  X_OR2 \PBL1_MC.D2_1786  (
    .I0(\PBL1_MC.D2_PT_0 ),
    .I1(\PBL1_MC.D2_PT_1 ),
    .O(\PBL1_MC.D2 )
  );
  X_BUF \PresEn_MC.Q_1787  (
    .I(\PresEn_MC.Q_tsimrenamed_net_ ),
    .O(\PresEn_MC.Q )
  );
  X_OR2 PresEn_MC_tsimcreated_prld__1788 (
    .I0(\FOOBAR2__ctinst/7 ),
    .I1(PRLD),
    .O(PresEn_MC_tsimcreated_prld_)
  );
  X_FF \PresEn_MC.REG  (
    .I(\PresEn_MC.D ),
    .CE(\FOOBAR19__ctinst/4 ),
    .CLK(\PresEn_MC.REG_tsimcreated_inv_Mclk_II/FCLK ),
    .SET(PresEn_MC_tsimcreated_prld_),
    .RST(Gnd),
    .O(\PresEn_MC.Q_tsimrenamed_net_ )
  );
  X_INV \PresEn_MC.REG_tsimcreated_inv_Mclk_II/FCLK_1789  (
    .I(\Mclk_II/FCLK ),
    .O(\PresEn_MC.REG_tsimcreated_inv_Mclk_II/FCLK )
  );
  X_XOR2 \PresEn_MC.D_1790  (
    .I0(\NlwInverterSignal_PresEn_MC.D/IN0 ),
    .I1(\PresEn_MC.D2 ),
    .O(\PresEn_MC.D )
  );
  X_AND2 \PresEn_MC.D1_1791  (
    .I0(\AD<0>_II/UIM ),
    .I1(\AD<0>_II/UIM ),
    .O(\PresEn_MC.D1 )
  );
  X_ZERO \PresEn_MC.D2_1792  (
    .O(\PresEn_MC.D2 )
  );
  X_BUF DCORSENSORw_1793 (
    .I(\DCORSENSORw_MC.Q ),
    .O(DCORSENSORw)
  );
  X_BUF \DCORSENSORw_MC.Q_1794  (
    .I(\DCORSENSORw_MC.D ),
    .O(\DCORSENSORw_MC.Q )
  );
  X_XOR2 \DCORSENSORw_MC.D_1795  (
    .I0(\DCORSENSORw_MC.D1 ),
    .I1(\DCORSENSORw_MC.D2 ),
    .O(\DCORSENSORw_MC.D )
  );
  X_AND16 \DCORSENSORw_MC.D1_1796  (
    .I0(\NlwInverterSignal_DCORSENSORw_MC.D1/IN0 ),
    .I1(\RD_II/UIM ),
    .I2(\NlwInverterSignal_DCORSENSORw_MC.D1/IN2 ),
    .I3(\NlwInverterSignal_DCORSENSORw_MC.D1/IN3 ),
    .I4(\NlwInverterSignal_DCORSENSORw_MC.D1/IN4 ),
    .I5(\NlwInverterSignal_DCORSENSORw_MC.D1/IN5 ),
    .I6(\NlwInverterSignal_DCORSENSORw_MC.D1/IN6 ),
    .I7(U2_ADDR_reg[3]),
    .I8(\NlwInverterSignal_DCORSENSORw_MC.D1/IN8 ),
    .I9(U2_ADDR_reg[2]),
    .I10(Vcc),
    .I11(Vcc),
    .I12(Vcc),
    .I13(Vcc),
    .I14(Vcc),
    .I15(Vcc),
    .O(\DCORSENSORw_MC.D1 )
  );
  X_ZERO \DCORSENSORw_MC.D2_1797  (
    .O(\DCORSENSORw_MC.D2 )
  );
  X_BUF \PresSlct_MC.Q_1798  (
    .I(\PresSlct_MC.Q_tsimrenamed_net_ ),
    .O(\PresSlct_MC.Q )
  );
  X_OR2 PresSlct_MC_tsimcreated_prld__1799 (
    .I0(\FOOBAR19__ctinst/0 ),
    .I1(PRLD),
    .O(PresSlct_MC_tsimcreated_prld_)
  );
  X_FF \PresSlct_MC.REG  (
    .I(\PresSlct_MC.D ),
    .CE(\FOOBAR19__ctinst/4 ),
    .CLK(\PresSlct_MC.REG_tsimcreated_inv_Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PresSlct_MC_tsimcreated_prld_),
    .O(\PresSlct_MC.Q_tsimrenamed_net_ )
  );
  X_INV \PresSlct_MC.REG_tsimcreated_inv_Mclk_II/FCLK_1800  (
    .I(\Mclk_II/FCLK ),
    .O(\PresSlct_MC.REG_tsimcreated_inv_Mclk_II/FCLK )
  );
  X_XOR2 \PresSlct_MC.D_1801  (
    .I0(\PresSlct_MC.D1 ),
    .I1(\PresSlct_MC.D2 ),
    .O(\PresSlct_MC.D )
  );
  X_AND2 \PresSlct_MC.D1_1802  (
    .I0(\AD<1>_II/UIM ),
    .I1(\AD<1>_II/UIM ),
    .O(\PresSlct_MC.D1 )
  );
  X_ZERO \PresSlct_MC.D2_1803  (
    .O(\PresSlct_MC.D2 )
  );
  X_BUF \SCLout_MC.Q_1804  (
    .I(\SCLout_MC.Q_tsimrenamed_net_ ),
    .O(\SCLout_MC.Q )
  );
  X_BUF \SCLout_MC.Q_tsimrenamed_net__1805  (
    .I(\SCLout_MC.D ),
    .O(\SCLout_MC.Q_tsimrenamed_net_ )
  );
  X_XOR2 \SCLout_MC.D_1806  (
    .I0(\SCLout_MC.D1 ),
    .I1(\SCLout_MC.D2 ),
    .O(\SCLout_MC.D )
  );
  X_AND2 \SCLout_MC.D1_1807  (
    .I0(\SCL_II/UIM ),
    .I1(\SCL_II/UIM ),
    .O(\SCLout_MC.D1 )
  );
  X_ZERO \SCLout_MC.D2_1808  (
    .O(\SCLout_MC.D2 )
  );
  X_BUF \TP10_MC.Q_1809  (
    .I(\TP10_MC.Q_tsimrenamed_net_ ),
    .O(\TP10_MC.Q )
  );
  X_BUF \TP10_MC.Q_tsimrenamed_net__1810  (
    .I(\TP10_MC.D ),
    .O(\TP10_MC.Q_tsimrenamed_net_ )
  );
  X_XOR2 \TP10_MC.D_1811  (
    .I0(\TP10_MC.D1 ),
    .I1(\TP10_MC.D2 ),
    .O(\TP10_MC.D )
  );
  X_AND2 \TP10_MC.D1_1812  (
    .I0(\SCLreset_II/UIM ),
    .I1(\SCLreset_II/UIM ),
    .O(\TP10_MC.D1 )
  );
  X_ZERO \TP10_MC.D2_1813  (
    .O(\TP10_MC.D2 )
  );
  X_BUF \TP11_MC.Q_1814  (
    .I(\TP11_MC.Q_tsimrenamed_net_ ),
    .O(\TP11_MC.Q )
  );
  X_BUF \TP11_MC.Q_tsimrenamed_net__1815  (
    .I(\TP11_MC.D ),
    .O(\TP11_MC.Q_tsimrenamed_net_ )
  );
  X_XOR2 \TP11_MC.D_1816  (
    .I0(\NlwInverterSignal_TP11_MC.D/IN0 ),
    .I1(\TP11_MC.D2 ),
    .O(\TP11_MC.D )
  );
  X_AND2 \TP11_MC.D1_1817  (
    .I0(\MSPReset_II/UIM ),
    .I1(\MSPReset_II/UIM ),
    .O(\TP11_MC.D1 )
  );
  X_ZERO \TP11_MC.D2_1818  (
    .O(\TP11_MC.D2 )
  );
  X_BUF \TmpEn_MC.Q_1819  (
    .I(\TmpEn_MC.Q_tsimrenamed_net_ ),
    .O(\TmpEn_MC.Q )
  );
  X_OR2 TmpEn_MC_tsimcreated_prld__1820 (
    .I0(\FOOBAR2__ctinst/7 ),
    .I1(PRLD),
    .O(TmpEn_MC_tsimcreated_prld_)
  );
  X_FF \TmpEn_MC.REG  (
    .I(\TmpEn_MC.D ),
    .CE(\FOOBAR19__ctinst/4 ),
    .CLK(\TmpEn_MC.REG_tsimcreated_inv_Mclk_II/FCLK ),
    .SET(TmpEn_MC_tsimcreated_prld_),
    .RST(Gnd),
    .O(\TmpEn_MC.Q_tsimrenamed_net_ )
  );
  X_INV \TmpEn_MC.REG_tsimcreated_inv_Mclk_II/FCLK_1821  (
    .I(\Mclk_II/FCLK ),
    .O(\TmpEn_MC.REG_tsimcreated_inv_Mclk_II/FCLK )
  );
  X_XOR2 \TmpEn_MC.D_1822  (
    .I0(\NlwInverterSignal_TmpEn_MC.D/IN0 ),
    .I1(\TmpEn_MC.D2 ),
    .O(\TmpEn_MC.D )
  );
  X_AND2 \TmpEn_MC.D1_1823  (
    .I0(\AD<2>_II/UIM ),
    .I1(\AD<2>_II/UIM ),
    .O(\TmpEn_MC.D1 )
  );
  X_ZERO \TmpEn_MC.D2_1824  (
    .O(\TmpEn_MC.D2 )
  );
  X_BUF \TmpSlct_MC.Q_1825  (
    .I(\TmpSlct_MC.Q_tsimrenamed_net_ ),
    .O(\TmpSlct_MC.Q )
  );
  X_OR2 TmpSlct_MC_tsimcreated_prld__1826 (
    .I0(\FOOBAR19__ctinst/0 ),
    .I1(PRLD),
    .O(TmpSlct_MC_tsimcreated_prld_)
  );
  X_FF \TmpSlct_MC.REG  (
    .I(\TmpSlct_MC.D ),
    .CE(\FOOBAR19__ctinst/4 ),
    .CLK(\TmpSlct_MC.REG_tsimcreated_inv_Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(TmpSlct_MC_tsimcreated_prld_),
    .O(\TmpSlct_MC.Q_tsimrenamed_net_ )
  );
  X_INV \TmpSlct_MC.REG_tsimcreated_inv_Mclk_II/FCLK_1827  (
    .I(\Mclk_II/FCLK ),
    .O(\TmpSlct_MC.REG_tsimcreated_inv_Mclk_II/FCLK )
  );
  X_XOR2 \TmpSlct_MC.D_1828  (
    .I0(\TmpSlct_MC.D1 ),
    .I1(\TmpSlct_MC.D2 ),
    .O(\TmpSlct_MC.D )
  );
  X_AND2 \TmpSlct_MC.D1_1829  (
    .I0(\AD<3>_II/UIM ),
    .I1(\AD<3>_II/UIM ),
    .O(\TmpSlct_MC.D1 )
  );
  X_ZERO \TmpSlct_MC.D2_1830  (
    .O(\TmpSlct_MC.D2 )
  );
  X_BUF \outDATA<2>\$WA0.UIM_1831  (
    .I(\outDATA<2>\$WA0.UIM_MC.Q ),
    .O(\outDATA<2>\$WA0.UIM )
  );
  X_BUF \outDATA<2>\$WA0.UIM_MC.Q_1832  (
    .I(\outDATA<2>\$WA0.UIM_MC.D ),
    .O(\outDATA<2>\$WA0.UIM_MC.Q )
  );
  X_XOR2 \outDATA<2>\$WA0.UIM_MC.D_1833  (
    .I0(\outDATA<2>\$WA0.UIM_MC.D1 ),
    .I1(\outDATA<2>\$WA0.UIM_MC.D2 ),
    .O(\outDATA<2>\$WA0.UIM_MC.D )
  );
  X_AND2 \outDATA<2>\$WA0.UIM_MC.D1_1834  (
    .I0(U11_U3_counterr[2]),
    .I1(U11_U3_counterr[2]),
    .O(\outDATA<2>\$WA0.UIM_MC.D1 )
  );
  X_ZERO \outDATA<2>\$WA0.UIM_MC.D2_1835  (
    .O(\outDATA<2>\$WA0.UIM_MC.D2 )
  );
  X_BUF \outDATA<2>\$WA3.UIM_1836  (
    .I(\outDATA<2>\$WA3.UIM_MC.Q ),
    .O(\outDATA<2>\$WA3.UIM )
  );
  X_BUF \outDATA<2>\$WA3.UIM_MC.Q_1837  (
    .I(\outDATA<2>\$WA3.UIM_MC.D ),
    .O(\outDATA<2>\$WA3.UIM_MC.Q )
  );
  X_XOR2 \outDATA<2>\$WA3.UIM_MC.D_1838  (
    .I0(\outDATA<2>\$WA3.UIM_MC.D1 ),
    .I1(\outDATA<2>\$WA3.UIM_MC.D2 ),
    .O(\outDATA<2>\$WA3.UIM_MC.D )
  );
  X_AND2 \outDATA<2>\$WA3.UIM_MC.D1_1839  (
    .I0(\I2CS<2>_II/UIM ),
    .I1(\I2CS<2>_II/UIM ),
    .O(\outDATA<2>\$WA3.UIM_MC.D1 )
  );
  X_ZERO \outDATA<2>\$WA3.UIM_MC.D2_1840  (
    .O(\outDATA<2>\$WA3.UIM_MC.D2 )
  );
  X_BUF \outDATA<2>\$WA5.UIM_1841  (
    .I(\outDATA<2>\$WA5.UIM_MC.Q ),
    .O(\outDATA<2>\$WA5.UIM )
  );
  X_BUF \outDATA<2>\$WA5.UIM_MC.Q_1842  (
    .I(\outDATA<2>\$WA5.UIM_MC.D ),
    .O(\outDATA<2>\$WA5.UIM_MC.Q )
  );
  X_XOR2 \outDATA<2>\$WA5.UIM_MC.D_1843  (
    .I0(\outDATA<2>\$WA5.UIM_MC.D1 ),
    .I1(\outDATA<2>\$WA5.UIM_MC.D2 ),
    .O(\outDATA<2>\$WA5.UIM_MC.D )
  );
  X_ZERO \outDATA<2>\$WA5.UIM_MC.D1_1844  (
    .O(\outDATA<2>\$WA5.UIM_MC.D1 )
  );
  X_AND2 \outDATA<2>\$WA5.UIM_MC.D2_PT_0_1845  (
    .I0(NET2528),
    .I1(\U4/Flgreg [2]),
    .O(\outDATA<2>\$WA5.UIM_MC.D2_PT_0 )
  );
  X_AND2 \outDATA<2>\$WA5.UIM_MC.D2_PT_1_1846  (
    .I0(\NlwInverterSignal_outDATA<2>\$WA5.UIM_MC.D2_PT_1/IN0 ),
    .I1(\Enc033FLG_II/UIM ),
    .O(\outDATA<2>\$WA5.UIM_MC.D2_PT_1 )
  );
  X_OR2 \outDATA<2>\$WA5.UIM_MC.D2_1847  (
    .I0(\outDATA<2>\$WA5.UIM_MC.D2_PT_0 ),
    .I1(\outDATA<2>\$WA5.UIM_MC.D2_PT_1 ),
    .O(\outDATA<2>\$WA5.UIM_MC.D2 )
  );
  X_BUF \outDATA<2>\$WA4.UIM_1848  (
    .I(\outDATA<2>\$WA4.UIM_MC.Q ),
    .O(\outDATA<2>\$WA4.UIM )
  );
  X_BUF \outDATA<2>\$WA4.UIM_MC.Q_1849  (
    .I(\outDATA<2>\$WA4.UIM_MC.D ),
    .O(\outDATA<2>\$WA4.UIM_MC.Q )
  );
  X_XOR2 \outDATA<2>\$WA4.UIM_MC.D_1850  (
    .I0(\outDATA<2>\$WA4.UIM_MC.D1 ),
    .I1(\outDATA<2>\$WA4.UIM_MC.D2 ),
    .O(\outDATA<2>\$WA4.UIM_MC.D )
  );
  X_AND2 \outDATA<2>\$WA4.UIM_MC.D1_1851  (
    .I0(DCORLIMITSr),
    .I1(\Home0_II/UIM ),
    .O(\outDATA<2>\$WA4.UIM_MC.D1 )
  );
  X_ZERO \outDATA<2>\$WA4.UIM_MC.D2_1852  (
    .O(\outDATA<2>\$WA4.UIM_MC.D2 )
  );
  X_BUF \outDATA<2>\$WA1.UIM_1853  (
    .I(\outDATA<2>\$WA1.UIM_MC.Q ),
    .O(\outDATA<2>\$WA1.UIM )
  );
  X_BUF \outDATA<2>\$WA1.UIM_MC.Q_1854  (
    .I(\outDATA<2>\$WA1.UIM_MC.D ),
    .O(\outDATA<2>\$WA1.UIM_MC.Q )
  );
  X_XOR2 \outDATA<2>\$WA1.UIM_MC.D_1855  (
    .I0(\outDATA<2>\$WA1.UIM_MC.D1 ),
    .I1(\outDATA<2>\$WA1.UIM_MC.D2 ),
    .O(\outDATA<2>\$WA1.UIM_MC.D )
  );
  X_ZERO \outDATA<2>\$WA1.UIM_MC.D1_1856  (
    .O(\outDATA<2>\$WA1.UIM_MC.D1 )
  );
  X_AND2 \outDATA<2>\$WA1.UIM_MC.D2_PT_0_1857  (
    .I0(DCOR0CNTLOWr),
    .I1(\U1/U3/holdingreg0 [2]),
    .O(\outDATA<2>\$WA1.UIM_MC.D2_PT_0 )
  );
  X_AND3 \outDATA<2>\$WA1.UIM_MC.D2_PT_1_1858  (
    .I0(\NlwInverterSignal_outDATA<2>\$WA1.UIM_MC.D2_PT_1/IN0 ),
    .I1(DCOR1CNTLOWr),
    .I2(\U1/U3/holdingreg1 [2]),
    .O(\outDATA<2>\$WA1.UIM_MC.D2_PT_1 )
  );
  X_AND4 \outDATA<2>\$WA1.UIM_MC.D2_PT_2_1859  (
    .I0(\NlwInverterSignal_outDATA<2>\$WA1.UIM_MC.D2_PT_2/IN0 ),
    .I1(\NlwInverterSignal_outDATA<2>\$WA1.UIM_MC.D2_PT_2/IN1 ),
    .I2(DCOR0CNTHIGHr),
    .I3(\U1/U3/holdingreg0 [10]),
    .O(\outDATA<2>\$WA1.UIM_MC.D2_PT_2 )
  );
  X_AND4 \outDATA<2>\$WA1.UIM_MC.D2_PT_3_1860  (
    .I0(\NlwInverterSignal_outDATA<2>\$WA1.UIM_MC.D2_PT_3/IN0 ),
    .I1(\NlwInverterSignal_outDATA<2>\$WA1.UIM_MC.D2_PT_3/IN1 ),
    .I2(\NlwInverterSignal_outDATA<2>\$WA1.UIM_MC.D2_PT_3/IN2 ),
    .I3(\U1/U3/holdingreg1 [10]),
    .O(\outDATA<2>\$WA1.UIM_MC.D2_PT_3 )
  );
  X_OR4 \outDATA<2>\$WA1.UIM_MC.D2_1861  (
    .I0(\outDATA<2>\$WA1.UIM_MC.D2_PT_0 ),
    .I1(\outDATA<2>\$WA1.UIM_MC.D2_PT_1 ),
    .I2(\outDATA<2>\$WA1.UIM_MC.D2_PT_2 ),
    .I3(\outDATA<2>\$WA1.UIM_MC.D2_PT_3 ),
    .O(\outDATA<2>\$WA1.UIM_MC.D2 )
  );
  X_BUF \U1/U3/holdingreg0<2>  (
    .I(\U1/U3/holdingreg0<2>_MC.Q ),
    .O(\U1/U3/holdingreg0 [2])
  );
  X_FF \U1/U3/holdingreg0<2>_MC.REG  (
    .I(\U1/U3/holdingreg0<2>_MC.D ),
    .CE(Vcc),
    .CLK(\U1/U3/holdingreg0<2>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\U1/U3/holdingreg0<2>_MC.Q )
  );
  X_INV \U1/U3/holdingreg0<2>_MC.REG_tsimcreated_inv_Mclk_II/FCLK_1862  (
    .I(\Mclk_II/FCLK ),
    .O(\U1/U3/holdingreg0<2>_MC.REG_tsimcreated_inv_Mclk_II/FCLK )
  );
  X_XOR2 \U1/U3/holdingreg0<2>_MC.D_1863  (
    .I0(\U1/U3/holdingreg0<2>_MC.D1 ),
    .I1(\U1/U3/holdingreg0<2>_MC.D2 ),
    .O(\U1/U3/holdingreg0<2>_MC.D )
  );
  X_ZERO \U1/U3/holdingreg0<2>_MC.D1_1864  (
    .O(\U1/U3/holdingreg0<2>_MC.D1 )
  );
  X_AND2 \U1/U3/holdingreg0<2>_MC.D2_PT_0_1865  (
    .I0(N_PZ_992),
    .I1(\U1/U3/holdingreg0 [2]),
    .O(\U1/U3/holdingreg0<2>_MC.D2_PT_0 )
  );
  X_AND4 \U1/U3/holdingreg0<2>_MC.D2_PT_1_1866  (
    .I0(\MSPReset_II/UIM ),
    .I1(\NlwInverterSignal_U1/U3/holdingreg0<2>_MC.D2_PT_1/IN1 ),
    .I2(U2_ASedge),
    .I3(\U1/Channel0 [2]),
    .O(\U1/U3/holdingreg0<2>_MC.D2_PT_1 )
  );
  X_OR2 \U1/U3/holdingreg0<2>_MC.D2_1867  (
    .I0(\U1/U3/holdingreg0<2>_MC.D2_PT_0 ),
    .I1(\U1/U3/holdingreg0<2>_MC.D2_PT_1 ),
    .O(\U1/U3/holdingreg0<2>_MC.D2 )
  );
  X_BUF \U1/U3/holdingreg1<2>  (
    .I(\U1/U3/holdingreg1<2>_MC.Q ),
    .O(\U1/U3/holdingreg1 [2])
  );
  X_FF \U1/U3/holdingreg1<2>_MC.REG  (
    .I(\U1/U3/holdingreg1<2>_MC.D ),
    .CE(Vcc),
    .CLK(\U1/U3/holdingreg1<2>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\U1/U3/holdingreg1<2>_MC.Q )
  );
  X_INV \U1/U3/holdingreg1<2>_MC.REG_tsimcreated_inv_Mclk_II/FCLK_1868  (
    .I(\Mclk_II/FCLK ),
    .O(\U1/U3/holdingreg1<2>_MC.REG_tsimcreated_inv_Mclk_II/FCLK )
  );
  X_XOR2 \U1/U3/holdingreg1<2>_MC.D_1869  (
    .I0(\U1/U3/holdingreg1<2>_MC.D1 ),
    .I1(\U1/U3/holdingreg1<2>_MC.D2 ),
    .O(\U1/U3/holdingreg1<2>_MC.D )
  );
  X_ZERO \U1/U3/holdingreg1<2>_MC.D1_1870  (
    .O(\U1/U3/holdingreg1<2>_MC.D1 )
  );
  X_AND2 \U1/U3/holdingreg1<2>_MC.D2_PT_0_1871  (
    .I0(N_PZ_992),
    .I1(\U1/U3/holdingreg1 [2]),
    .O(\U1/U3/holdingreg1<2>_MC.D2_PT_0 )
  );
  X_AND4 \U1/U3/holdingreg1<2>_MC.D2_PT_1_1872  (
    .I0(\MSPReset_II/UIM ),
    .I1(\NlwInverterSignal_U1/U3/holdingreg1<2>_MC.D2_PT_1/IN1 ),
    .I2(U2_ASedge),
    .I3(\U1/Channel1 [2]),
    .O(\U1/U3/holdingreg1<2>_MC.D2_PT_1 )
  );
  X_OR2 \U1/U3/holdingreg1<2>_MC.D2_1873  (
    .I0(\U1/U3/holdingreg1<2>_MC.D2_PT_0 ),
    .I1(\U1/U3/holdingreg1<2>_MC.D2_PT_1 ),
    .O(\U1/U3/holdingreg1<2>_MC.D2 )
  );
  X_BUF \U1/U3/holdingreg0<10>  (
    .I(\U1/U3/holdingreg0<10>_MC.Q ),
    .O(\U1/U3/holdingreg0 [10])
  );
  X_FF \U1/U3/holdingreg0<10>_MC.REG  (
    .I(\U1/U3/holdingreg0<10>_MC.D ),
    .CE(Vcc),
    .CLK(\U1/U3/holdingreg0<10>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\U1/U3/holdingreg0<10>_MC.Q )
  );
  X_INV \U1/U3/holdingreg0<10>_MC.REG_tsimcreated_inv_Mclk_II/FCLK_1874  (
    .I(\Mclk_II/FCLK ),
    .O(\U1/U3/holdingreg0<10>_MC.REG_tsimcreated_inv_Mclk_II/FCLK )
  );
  X_XOR2 \U1/U3/holdingreg0<10>_MC.D_1875  (
    .I0(\U1/U3/holdingreg0<10>_MC.D1 ),
    .I1(\U1/U3/holdingreg0<10>_MC.D2 ),
    .O(\U1/U3/holdingreg0<10>_MC.D )
  );
  X_ZERO \U1/U3/holdingreg0<10>_MC.D1_1876  (
    .O(\U1/U3/holdingreg0<10>_MC.D1 )
  );
  X_AND2 \U1/U3/holdingreg0<10>_MC.D2_PT_0_1877  (
    .I0(N_PZ_992),
    .I1(\U1/U3/holdingreg0 [10]),
    .O(\U1/U3/holdingreg0<10>_MC.D2_PT_0 )
  );
  X_AND4 \U1/U3/holdingreg0<10>_MC.D2_PT_1_1878  (
    .I0(\MSPReset_II/UIM ),
    .I1(\NlwInverterSignal_U1/U3/holdingreg0<10>_MC.D2_PT_1/IN1 ),
    .I2(U2_ASedge),
    .I3(\U1/Channel0 [10]),
    .O(\U1/U3/holdingreg0<10>_MC.D2_PT_1 )
  );
  X_OR2 \U1/U3/holdingreg0<10>_MC.D2_1879  (
    .I0(\U1/U3/holdingreg0<10>_MC.D2_PT_0 ),
    .I1(\U1/U3/holdingreg0<10>_MC.D2_PT_1 ),
    .O(\U1/U3/holdingreg0<10>_MC.D2 )
  );
  X_BUF \U1/U3/holdingreg1<10>  (
    .I(\U1/U3/holdingreg1<10>_MC.Q ),
    .O(\U1/U3/holdingreg1 [10])
  );
  X_FF \U1/U3/holdingreg1<10>_MC.REG  (
    .I(\U1/U3/holdingreg1<10>_MC.D ),
    .CE(Vcc),
    .CLK(\U1/U3/holdingreg1<10>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\U1/U3/holdingreg1<10>_MC.Q )
  );
  X_INV \U1/U3/holdingreg1<10>_MC.REG_tsimcreated_inv_Mclk_II/FCLK_1880  (
    .I(\Mclk_II/FCLK ),
    .O(\U1/U3/holdingreg1<10>_MC.REG_tsimcreated_inv_Mclk_II/FCLK )
  );
  X_XOR2 \U1/U3/holdingreg1<10>_MC.D_1881  (
    .I0(\U1/U3/holdingreg1<10>_MC.D1 ),
    .I1(\U1/U3/holdingreg1<10>_MC.D2 ),
    .O(\U1/U3/holdingreg1<10>_MC.D )
  );
  X_ZERO \U1/U3/holdingreg1<10>_MC.D1_1882  (
    .O(\U1/U3/holdingreg1<10>_MC.D1 )
  );
  X_AND2 \U1/U3/holdingreg1<10>_MC.D2_PT_0_1883  (
    .I0(N_PZ_992),
    .I1(\U1/U3/holdingreg1 [10]),
    .O(\U1/U3/holdingreg1<10>_MC.D2_PT_0 )
  );
  X_AND4 \U1/U3/holdingreg1<10>_MC.D2_PT_1_1884  (
    .I0(\MSPReset_II/UIM ),
    .I1(\NlwInverterSignal_U1/U3/holdingreg1<10>_MC.D2_PT_1/IN1 ),
    .I2(U2_ASedge),
    .I3(\U1/Channel1 [10]),
    .O(\U1/U3/holdingreg1<10>_MC.D2_PT_1 )
  );
  X_OR2 \U1/U3/holdingreg1<10>_MC.D2_1885  (
    .I0(\U1/U3/holdingreg1<10>_MC.D2_PT_0 ),
    .I1(\U1/U3/holdingreg1<10>_MC.D2_PT_1 ),
    .O(\U1/U3/holdingreg1<10>_MC.D2 )
  );
  X_BUF \outDATA<2>\$WA2.UIM_1886  (
    .I(\outDATA<2>\$WA2.UIM_MC.Q ),
    .O(\outDATA<2>\$WA2.UIM )
  );
  X_BUF \outDATA<2>\$WA2.UIM_MC.Q_1887  (
    .I(\outDATA<2>\$WA2.UIM_MC.D ),
    .O(\outDATA<2>\$WA2.UIM_MC.Q )
  );
  X_XOR2 \outDATA<2>\$WA2.UIM_MC.D_1888  (
    .I0(\outDATA<2>\$WA2.UIM_MC.D1 ),
    .I1(\outDATA<2>\$WA2.UIM_MC.D2 ),
    .O(\outDATA<2>\$WA2.UIM_MC.D )
  );
  X_ZERO \outDATA<2>\$WA2.UIM_MC.D1_1889  (
    .O(\outDATA<2>\$WA2.UIM_MC.D1 )
  );
  X_AND2 \outDATA<2>\$WA2.UIM_MC.D2_PT_0_1890  (
    .I0(DCOR0THRESLOWr),
    .I1(\U1/U4/Latch0r [2]),
    .O(\outDATA<2>\$WA2.UIM_MC.D2_PT_0 )
  );
  X_AND3 \outDATA<2>\$WA2.UIM_MC.D2_PT_1_1891  (
    .I0(\NlwInverterSignal_outDATA<2>\$WA2.UIM_MC.D2_PT_1/IN0 ),
    .I1(DCORIFGr),
    .I2(NET2482),
    .O(\outDATA<2>\$WA2.UIM_MC.D2_PT_1 )
  );
  X_AND4 \outDATA<2>\$WA2.UIM_MC.D2_PT_2_1892  (
    .I0(\NlwInverterSignal_outDATA<2>\$WA2.UIM_MC.D2_PT_2/IN0 ),
    .I1(\NlwInverterSignal_outDATA<2>\$WA2.UIM_MC.D2_PT_2/IN1 ),
    .I2(DCOR0THRESHIGHr),
    .I3(\U1/U4/Latch0r [10]),
    .O(\outDATA<2>\$WA2.UIM_MC.D2_PT_2 )
  );
  X_AND5 \outDATA<2>\$WA2.UIM_MC.D2_PT_3_1893  (
    .I0(\NlwInverterSignal_outDATA<2>\$WA2.UIM_MC.D2_PT_3/IN0 ),
    .I1(\NlwInverterSignal_outDATA<2>\$WA2.UIM_MC.D2_PT_3/IN1 ),
    .I2(\NlwInverterSignal_outDATA<2>\$WA2.UIM_MC.D2_PT_3/IN2 ),
    .I3(DCOR1THRESLOWr),
    .I4(\U1/U4/Latch1r [2]),
    .O(\outDATA<2>\$WA2.UIM_MC.D2_PT_3 )
  );
  X_AND5 \outDATA<2>\$WA2.UIM_MC.D2_PT_4_1894  (
    .I0(\NlwInverterSignal_outDATA<2>\$WA2.UIM_MC.D2_PT_4/IN0 ),
    .I1(\NlwInverterSignal_outDATA<2>\$WA2.UIM_MC.D2_PT_4/IN1 ),
    .I2(\NlwInverterSignal_outDATA<2>\$WA2.UIM_MC.D2_PT_4/IN2 ),
    .I3(\NlwInverterSignal_outDATA<2>\$WA2.UIM_MC.D2_PT_4/IN3 ),
    .I4(\U1/U4/Latch1r [10]),
    .O(\outDATA<2>\$WA2.UIM_MC.D2_PT_4 )
  );
  X_OR5 \outDATA<2>\$WA2.UIM_MC.D2_1895  (
    .I0(\outDATA<2>\$WA2.UIM_MC.D2_PT_0 ),
    .I1(\outDATA<2>\$WA2.UIM_MC.D2_PT_1 ),
    .I2(\outDATA<2>\$WA2.UIM_MC.D2_PT_2 ),
    .I3(\outDATA<2>\$WA2.UIM_MC.D2_PT_3 ),
    .I4(\outDATA<2>\$WA2.UIM_MC.D2_PT_4 ),
    .O(\outDATA<2>\$WA2.UIM_MC.D2 )
  );
  X_BUF \U1/U4/Latch0r<2>  (
    .I(\U1/U4/Latch0r<2>_MC.Q ),
    .O(\U1/U4/Latch0r [2])
  );
  X_FF \U1/U4/Latch0r<2>_MC.REG  (
    .I(\U1/U4/Latch0r<2>_MC.D ),
    .CE(Vcc),
    .CLK(\U1/U4/Latch0r<2>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\U1/U4/Latch0r<2>_MC.Q )
  );
  X_INV \U1/U4/Latch0r<2>_MC.REG_tsimcreated_inv_Mclk_II/FCLK_1896  (
    .I(\Mclk_II/FCLK ),
    .O(\U1/U4/Latch0r<2>_MC.REG_tsimcreated_inv_Mclk_II/FCLK )
  );
  X_XOR2 \U1/U4/Latch0r<2>_MC.D_1897  (
    .I0(\U1/U4/Latch0r<2>_MC.D1 ),
    .I1(\U1/U4/Latch0r<2>_MC.D2 ),
    .O(\U1/U4/Latch0r<2>_MC.D )
  );
  X_ZERO \U1/U4/Latch0r<2>_MC.D1_1898  (
    .O(\U1/U4/Latch0r<2>_MC.D1 )
  );
  X_AND3 \U1/U4/Latch0r<2>_MC.D2_PT_0_1899  (
    .I0(\MSPReset_II/UIM ),
    .I1(N_PZ_1018),
    .I2(\U1/Channel0 [2]),
    .O(\U1/U4/Latch0r<2>_MC.D2_PT_0 )
  );
  X_AND3 \U1/U4/Latch0r<2>_MC.D2_PT_1_1900  (
    .I0(\MSPReset_II/UIM ),
    .I1(\NlwInverterSignal_U1/U4/Latch0r<2>_MC.D2_PT_1/IN1 ),
    .I2(\U1/U4/Latch0r [2]),
    .O(\U1/U4/Latch0r<2>_MC.D2_PT_1 )
  );
  X_OR2 \U1/U4/Latch0r<2>_MC.D2_1901  (
    .I0(\U1/U4/Latch0r<2>_MC.D2_PT_0 ),
    .I1(\U1/U4/Latch0r<2>_MC.D2_PT_1 ),
    .O(\U1/U4/Latch0r<2>_MC.D2 )
  );
  X_BUF \U1/U4/Latch0r<10>  (
    .I(\U1/U4/Latch0r<10>_MC.Q ),
    .O(\U1/U4/Latch0r [10])
  );
  X_FF \U1/U4/Latch0r<10>_MC.REG  (
    .I(\U1/U4/Latch0r<10>_MC.D ),
    .CE(Vcc),
    .CLK(\U1/U4/Latch0r<10>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\U1/U4/Latch0r<10>_MC.Q )
  );
  X_INV \U1/U4/Latch0r<10>_MC.REG_tsimcreated_inv_Mclk_II/FCLK_1902  (
    .I(\Mclk_II/FCLK ),
    .O(\U1/U4/Latch0r<10>_MC.REG_tsimcreated_inv_Mclk_II/FCLK )
  );
  X_XOR2 \U1/U4/Latch0r<10>_MC.D_1903  (
    .I0(\U1/U4/Latch0r<10>_MC.D1 ),
    .I1(\U1/U4/Latch0r<10>_MC.D2 ),
    .O(\U1/U4/Latch0r<10>_MC.D )
  );
  X_ZERO \U1/U4/Latch0r<10>_MC.D1_1904  (
    .O(\U1/U4/Latch0r<10>_MC.D1 )
  );
  X_AND3 \U1/U4/Latch0r<10>_MC.D2_PT_0_1905  (
    .I0(\MSPReset_II/UIM ),
    .I1(N_PZ_1018),
    .I2(\U1/Channel0 [10]),
    .O(\U1/U4/Latch0r<10>_MC.D2_PT_0 )
  );
  X_AND3 \U1/U4/Latch0r<10>_MC.D2_PT_1_1906  (
    .I0(\MSPReset_II/UIM ),
    .I1(\NlwInverterSignal_U1/U4/Latch0r<10>_MC.D2_PT_1/IN1 ),
    .I2(\U1/U4/Latch0r [10]),
    .O(\U1/U4/Latch0r<10>_MC.D2_PT_1 )
  );
  X_OR2 \U1/U4/Latch0r<10>_MC.D2_1907  (
    .I0(\U1/U4/Latch0r<10>_MC.D2_PT_0 ),
    .I1(\U1/U4/Latch0r<10>_MC.D2_PT_1 ),
    .O(\U1/U4/Latch0r<10>_MC.D2 )
  );
  X_BUF \U1/U4/Latch1r<2>  (
    .I(\U1/U4/Latch1r<2>_MC.Q ),
    .O(\U1/U4/Latch1r [2])
  );
  X_FF \U1/U4/Latch1r<2>_MC.REG  (
    .I(\U1/U4/Latch1r<2>_MC.D ),
    .CE(Vcc),
    .CLK(\U1/U4/Latch1r<2>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\U1/U4/Latch1r<2>_MC.Q )
  );
  X_INV \U1/U4/Latch1r<2>_MC.REG_tsimcreated_inv_Mclk_II/FCLK_1908  (
    .I(\Mclk_II/FCLK ),
    .O(\U1/U4/Latch1r<2>_MC.REG_tsimcreated_inv_Mclk_II/FCLK )
  );
  X_XOR2 \U1/U4/Latch1r<2>_MC.D_1909  (
    .I0(\U1/U4/Latch1r<2>_MC.D1 ),
    .I1(\U1/U4/Latch1r<2>_MC.D2 ),
    .O(\U1/U4/Latch1r<2>_MC.D )
  );
  X_ZERO \U1/U4/Latch1r<2>_MC.D1_1910  (
    .O(\U1/U4/Latch1r<2>_MC.D1 )
  );
  X_AND3 \U1/U4/Latch1r<2>_MC.D2_PT_0_1911  (
    .I0(\MSPReset_II/UIM ),
    .I1(N_PZ_1019),
    .I2(\U1/Channel1 [2]),
    .O(\U1/U4/Latch1r<2>_MC.D2_PT_0 )
  );
  X_AND3 \U1/U4/Latch1r<2>_MC.D2_PT_1_1912  (
    .I0(\MSPReset_II/UIM ),
    .I1(\NlwInverterSignal_U1/U4/Latch1r<2>_MC.D2_PT_1/IN1 ),
    .I2(\U1/U4/Latch1r [2]),
    .O(\U1/U4/Latch1r<2>_MC.D2_PT_1 )
  );
  X_OR2 \U1/U4/Latch1r<2>_MC.D2_1913  (
    .I0(\U1/U4/Latch1r<2>_MC.D2_PT_0 ),
    .I1(\U1/U4/Latch1r<2>_MC.D2_PT_1 ),
    .O(\U1/U4/Latch1r<2>_MC.D2 )
  );
  X_BUF \U1/U4/Latch1r<10>  (
    .I(\U1/U4/Latch1r<10>_MC.Q ),
    .O(\U1/U4/Latch1r [10])
  );
  X_FF \U1/U4/Latch1r<10>_MC.REG  (
    .I(\U1/U4/Latch1r<10>_MC.D ),
    .CE(Vcc),
    .CLK(\U1/U4/Latch1r<10>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\U1/U4/Latch1r<10>_MC.Q )
  );
  X_INV \U1/U4/Latch1r<10>_MC.REG_tsimcreated_inv_Mclk_II/FCLK_1914  (
    .I(\Mclk_II/FCLK ),
    .O(\U1/U4/Latch1r<10>_MC.REG_tsimcreated_inv_Mclk_II/FCLK )
  );
  X_XOR2 \U1/U4/Latch1r<10>_MC.D_1915  (
    .I0(\U1/U4/Latch1r<10>_MC.D1 ),
    .I1(\U1/U4/Latch1r<10>_MC.D2 ),
    .O(\U1/U4/Latch1r<10>_MC.D )
  );
  X_ZERO \U1/U4/Latch1r<10>_MC.D1_1916  (
    .O(\U1/U4/Latch1r<10>_MC.D1 )
  );
  X_AND3 \U1/U4/Latch1r<10>_MC.D2_PT_0_1917  (
    .I0(\MSPReset_II/UIM ),
    .I1(N_PZ_1019),
    .I2(\U1/Channel1 [10]),
    .O(\U1/U4/Latch1r<10>_MC.D2_PT_0 )
  );
  X_AND3 \U1/U4/Latch1r<10>_MC.D2_PT_1_1918  (
    .I0(\MSPReset_II/UIM ),
    .I1(\NlwInverterSignal_U1/U4/Latch1r<10>_MC.D2_PT_1/IN1 ),
    .I2(\U1/U4/Latch1r [10]),
    .O(\U1/U4/Latch1r<10>_MC.D2_PT_1 )
  );
  X_OR2 \U1/U4/Latch1r<10>_MC.D2_1919  (
    .I0(\U1/U4/Latch1r<10>_MC.D2_PT_0 ),
    .I1(\U1/U4/Latch1r<10>_MC.D2_PT_1 ),
    .O(\U1/U4/Latch1r<10>_MC.D2 )
  );
  X_BUF \outDATA<3>\$WA0.UIM_1920  (
    .I(\outDATA<3>\$WA0.UIM_MC.Q ),
    .O(\outDATA<3>\$WA0.UIM )
  );
  X_BUF \outDATA<3>\$WA0.UIM_MC.Q_1921  (
    .I(\outDATA<3>\$WA0.UIM_MC.D ),
    .O(\outDATA<3>\$WA0.UIM_MC.Q )
  );
  X_XOR2 \outDATA<3>\$WA0.UIM_MC.D_1922  (
    .I0(\outDATA<3>\$WA0.UIM_MC.D1 ),
    .I1(\outDATA<3>\$WA0.UIM_MC.D2 ),
    .O(\outDATA<3>\$WA0.UIM_MC.D )
  );
  X_AND2 \outDATA<3>\$WA0.UIM_MC.D1_1923  (
    .I0(U11_U3_counterr[3]),
    .I1(U11_U3_counterr[3]),
    .O(\outDATA<3>\$WA0.UIM_MC.D1 )
  );
  X_ZERO \outDATA<3>\$WA0.UIM_MC.D2_1924  (
    .O(\outDATA<3>\$WA0.UIM_MC.D2 )
  );
  X_BUF \outDATA<3>\$WA3.UIM_1925  (
    .I(\outDATA<3>\$WA3.UIM_MC.Q ),
    .O(\outDATA<3>\$WA3.UIM )
  );
  X_BUF \outDATA<3>\$WA3.UIM_MC.Q_1926  (
    .I(\outDATA<3>\$WA3.UIM_MC.D ),
    .O(\outDATA<3>\$WA3.UIM_MC.Q )
  );
  X_XOR2 \outDATA<3>\$WA3.UIM_MC.D_1927  (
    .I0(\outDATA<3>\$WA3.UIM_MC.D1 ),
    .I1(\outDATA<3>\$WA3.UIM_MC.D2 ),
    .O(\outDATA<3>\$WA3.UIM_MC.D )
  );
  X_AND2 \outDATA<3>\$WA3.UIM_MC.D1_1928  (
    .I0(\I2CS<3>_II/UIM ),
    .I1(\I2CS<3>_II/UIM ),
    .O(\outDATA<3>\$WA3.UIM_MC.D1 )
  );
  X_ZERO \outDATA<3>\$WA3.UIM_MC.D2_1929  (
    .O(\outDATA<3>\$WA3.UIM_MC.D2 )
  );
  X_BUF \outDATA<3>\$WA5.UIM_1930  (
    .I(\outDATA<3>\$WA5.UIM_MC.Q ),
    .O(\outDATA<3>\$WA5.UIM )
  );
  X_BUF \outDATA<3>\$WA5.UIM_MC.Q_1931  (
    .I(\outDATA<3>\$WA5.UIM_MC.D ),
    .O(\outDATA<3>\$WA5.UIM_MC.Q )
  );
  X_XOR2 \outDATA<3>\$WA5.UIM_MC.D_1932  (
    .I0(\outDATA<3>\$WA5.UIM_MC.D1 ),
    .I1(\outDATA<3>\$WA5.UIM_MC.D2 ),
    .O(\outDATA<3>\$WA5.UIM_MC.D )
  );
  X_ZERO \outDATA<3>\$WA5.UIM_MC.D1_1933  (
    .O(\outDATA<3>\$WA5.UIM_MC.D1 )
  );
  X_AND2 \outDATA<3>\$WA5.UIM_MC.D2_PT_0_1934  (
    .I0(NET2528),
    .I1(\U4/Flgreg [3]),
    .O(\outDATA<3>\$WA5.UIM_MC.D2_PT_0 )
  );
  X_AND2 \outDATA<3>\$WA5.UIM_MC.D2_PT_1_1935  (
    .I0(\NlwInverterSignal_outDATA<3>\$WA5.UIM_MC.D2_PT_1/IN0 ),
    .I1(\Enc05FLG_II/UIM ),
    .O(\outDATA<3>\$WA5.UIM_MC.D2_PT_1 )
  );
  X_OR2 \outDATA<3>\$WA5.UIM_MC.D2_1936  (
    .I0(\outDATA<3>\$WA5.UIM_MC.D2_PT_0 ),
    .I1(\outDATA<3>\$WA5.UIM_MC.D2_PT_1 ),
    .O(\outDATA<3>\$WA5.UIM_MC.D2 )
  );
  X_BUF \outDATA<3>\$WA4.UIM_1937  (
    .I(\outDATA<3>\$WA4.UIM_MC.Q ),
    .O(\outDATA<3>\$WA4.UIM )
  );
  X_BUF \outDATA<3>\$WA4.UIM_MC.Q_1938  (
    .I(\outDATA<3>\$WA4.UIM_MC.D ),
    .O(\outDATA<3>\$WA4.UIM_MC.Q )
  );
  X_XOR2 \outDATA<3>\$WA4.UIM_MC.D_1939  (
    .I0(\outDATA<3>\$WA4.UIM_MC.D1 ),
    .I1(\outDATA<3>\$WA4.UIM_MC.D2 ),
    .O(\outDATA<3>\$WA4.UIM_MC.D )
  );
  X_AND2 \outDATA<3>\$WA4.UIM_MC.D1_1940  (
    .I0(NET3248),
    .I1(NET3248),
    .O(\outDATA<3>\$WA4.UIM_MC.D1 )
  );
  X_ZERO \outDATA<3>\$WA4.UIM_MC.D2_1941  (
    .O(\outDATA<3>\$WA4.UIM_MC.D2 )
  );
  X_BUF \outDATA<3>\$WA1.UIM_1942  (
    .I(\outDATA<3>\$WA1.UIM_MC.Q ),
    .O(\outDATA<3>\$WA1.UIM )
  );
  X_BUF \outDATA<3>\$WA1.UIM_MC.Q_1943  (
    .I(\outDATA<3>\$WA1.UIM_MC.D ),
    .O(\outDATA<3>\$WA1.UIM_MC.Q )
  );
  X_XOR2 \outDATA<3>\$WA1.UIM_MC.D_1944  (
    .I0(\outDATA<3>\$WA1.UIM_MC.D1 ),
    .I1(\outDATA<3>\$WA1.UIM_MC.D2 ),
    .O(\outDATA<3>\$WA1.UIM_MC.D )
  );
  X_ZERO \outDATA<3>\$WA1.UIM_MC.D1_1945  (
    .O(\outDATA<3>\$WA1.UIM_MC.D1 )
  );
  X_AND2 \outDATA<3>\$WA1.UIM_MC.D2_PT_0_1946  (
    .I0(DCOR0CNTLOWr),
    .I1(\U1/U3/holdingreg0 [3]),
    .O(\outDATA<3>\$WA1.UIM_MC.D2_PT_0 )
  );
  X_AND3 \outDATA<3>\$WA1.UIM_MC.D2_PT_1_1947  (
    .I0(\NlwInverterSignal_outDATA<3>\$WA1.UIM_MC.D2_PT_1/IN0 ),
    .I1(DCOR1CNTLOWr),
    .I2(\U1/U3/holdingreg1 [3]),
    .O(\outDATA<3>\$WA1.UIM_MC.D2_PT_1 )
  );
  X_AND4 \outDATA<3>\$WA1.UIM_MC.D2_PT_2_1948  (
    .I0(\NlwInverterSignal_outDATA<3>\$WA1.UIM_MC.D2_PT_2/IN0 ),
    .I1(\NlwInverterSignal_outDATA<3>\$WA1.UIM_MC.D2_PT_2/IN1 ),
    .I2(DCOR0CNTHIGHr),
    .I3(\U1/U3/holdingreg0 [11]),
    .O(\outDATA<3>\$WA1.UIM_MC.D2_PT_2 )
  );
  X_AND4 \outDATA<3>\$WA1.UIM_MC.D2_PT_3_1949  (
    .I0(\NlwInverterSignal_outDATA<3>\$WA1.UIM_MC.D2_PT_3/IN0 ),
    .I1(\NlwInverterSignal_outDATA<3>\$WA1.UIM_MC.D2_PT_3/IN1 ),
    .I2(\NlwInverterSignal_outDATA<3>\$WA1.UIM_MC.D2_PT_3/IN2 ),
    .I3(\U1/U3/holdingreg1 [11]),
    .O(\outDATA<3>\$WA1.UIM_MC.D2_PT_3 )
  );
  X_OR4 \outDATA<3>\$WA1.UIM_MC.D2_1950  (
    .I0(\outDATA<3>\$WA1.UIM_MC.D2_PT_0 ),
    .I1(\outDATA<3>\$WA1.UIM_MC.D2_PT_1 ),
    .I2(\outDATA<3>\$WA1.UIM_MC.D2_PT_2 ),
    .I3(\outDATA<3>\$WA1.UIM_MC.D2_PT_3 ),
    .O(\outDATA<3>\$WA1.UIM_MC.D2 )
  );
  X_BUF \U1/U3/holdingreg0<3>  (
    .I(\U1/U3/holdingreg0<3>_MC.Q ),
    .O(\U1/U3/holdingreg0 [3])
  );
  X_FF \U1/U3/holdingreg0<3>_MC.REG  (
    .I(\U1/U3/holdingreg0<3>_MC.D ),
    .CE(Vcc),
    .CLK(\U1/U3/holdingreg0<3>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\U1/U3/holdingreg0<3>_MC.Q )
  );
  X_INV \U1/U3/holdingreg0<3>_MC.REG_tsimcreated_inv_Mclk_II/FCLK_1951  (
    .I(\Mclk_II/FCLK ),
    .O(\U1/U3/holdingreg0<3>_MC.REG_tsimcreated_inv_Mclk_II/FCLK )
  );
  X_XOR2 \U1/U3/holdingreg0<3>_MC.D_1952  (
    .I0(\U1/U3/holdingreg0<3>_MC.D1 ),
    .I1(\U1/U3/holdingreg0<3>_MC.D2 ),
    .O(\U1/U3/holdingreg0<3>_MC.D )
  );
  X_ZERO \U1/U3/holdingreg0<3>_MC.D1_1953  (
    .O(\U1/U3/holdingreg0<3>_MC.D1 )
  );
  X_AND2 \U1/U3/holdingreg0<3>_MC.D2_PT_0_1954  (
    .I0(N_PZ_992),
    .I1(\U1/U3/holdingreg0 [3]),
    .O(\U1/U3/holdingreg0<3>_MC.D2_PT_0 )
  );
  X_AND4 \U1/U3/holdingreg0<3>_MC.D2_PT_1_1955  (
    .I0(\MSPReset_II/UIM ),
    .I1(\NlwInverterSignal_U1/U3/holdingreg0<3>_MC.D2_PT_1/IN1 ),
    .I2(U2_ASedge),
    .I3(\U1/Channel0 [3]),
    .O(\U1/U3/holdingreg0<3>_MC.D2_PT_1 )
  );
  X_OR2 \U1/U3/holdingreg0<3>_MC.D2_1956  (
    .I0(\U1/U3/holdingreg0<3>_MC.D2_PT_0 ),
    .I1(\U1/U3/holdingreg0<3>_MC.D2_PT_1 ),
    .O(\U1/U3/holdingreg0<3>_MC.D2 )
  );
  X_BUF \U1/U3/holdingreg1<3>  (
    .I(\U1/U3/holdingreg1<3>_MC.Q ),
    .O(\U1/U3/holdingreg1 [3])
  );
  X_FF \U1/U3/holdingreg1<3>_MC.REG  (
    .I(\U1/U3/holdingreg1<3>_MC.D ),
    .CE(Vcc),
    .CLK(\U1/U3/holdingreg1<3>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\U1/U3/holdingreg1<3>_MC.Q )
  );
  X_INV \U1/U3/holdingreg1<3>_MC.REG_tsimcreated_inv_Mclk_II/FCLK_1957  (
    .I(\Mclk_II/FCLK ),
    .O(\U1/U3/holdingreg1<3>_MC.REG_tsimcreated_inv_Mclk_II/FCLK )
  );
  X_XOR2 \U1/U3/holdingreg1<3>_MC.D_1958  (
    .I0(\U1/U3/holdingreg1<3>_MC.D1 ),
    .I1(\U1/U3/holdingreg1<3>_MC.D2 ),
    .O(\U1/U3/holdingreg1<3>_MC.D )
  );
  X_ZERO \U1/U3/holdingreg1<3>_MC.D1_1959  (
    .O(\U1/U3/holdingreg1<3>_MC.D1 )
  );
  X_AND2 \U1/U3/holdingreg1<3>_MC.D2_PT_0_1960  (
    .I0(N_PZ_992),
    .I1(\U1/U3/holdingreg1 [3]),
    .O(\U1/U3/holdingreg1<3>_MC.D2_PT_0 )
  );
  X_AND4 \U1/U3/holdingreg1<3>_MC.D2_PT_1_1961  (
    .I0(\MSPReset_II/UIM ),
    .I1(\NlwInverterSignal_U1/U3/holdingreg1<3>_MC.D2_PT_1/IN1 ),
    .I2(U2_ASedge),
    .I3(\U1/Channel1 [3]),
    .O(\U1/U3/holdingreg1<3>_MC.D2_PT_1 )
  );
  X_OR2 \U1/U3/holdingreg1<3>_MC.D2_1962  (
    .I0(\U1/U3/holdingreg1<3>_MC.D2_PT_0 ),
    .I1(\U1/U3/holdingreg1<3>_MC.D2_PT_1 ),
    .O(\U1/U3/holdingreg1<3>_MC.D2 )
  );
  X_BUF \U1/U3/holdingreg0<11>  (
    .I(\U1/U3/holdingreg0<11>_MC.Q ),
    .O(\U1/U3/holdingreg0 [11])
  );
  X_FF \U1/U3/holdingreg0<11>_MC.REG  (
    .I(\U1/U3/holdingreg0<11>_MC.D ),
    .CE(Vcc),
    .CLK(\U1/U3/holdingreg0<11>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\U1/U3/holdingreg0<11>_MC.Q )
  );
  X_INV \U1/U3/holdingreg0<11>_MC.REG_tsimcreated_inv_Mclk_II/FCLK_1963  (
    .I(\Mclk_II/FCLK ),
    .O(\U1/U3/holdingreg0<11>_MC.REG_tsimcreated_inv_Mclk_II/FCLK )
  );
  X_XOR2 \U1/U3/holdingreg0<11>_MC.D_1964  (
    .I0(\U1/U3/holdingreg0<11>_MC.D1 ),
    .I1(\U1/U3/holdingreg0<11>_MC.D2 ),
    .O(\U1/U3/holdingreg0<11>_MC.D )
  );
  X_ZERO \U1/U3/holdingreg0<11>_MC.D1_1965  (
    .O(\U1/U3/holdingreg0<11>_MC.D1 )
  );
  X_AND2 \U1/U3/holdingreg0<11>_MC.D2_PT_0_1966  (
    .I0(N_PZ_992),
    .I1(\U1/U3/holdingreg0 [11]),
    .O(\U1/U3/holdingreg0<11>_MC.D2_PT_0 )
  );
  X_AND4 \U1/U3/holdingreg0<11>_MC.D2_PT_1_1967  (
    .I0(\MSPReset_II/UIM ),
    .I1(\NlwInverterSignal_U1/U3/holdingreg0<11>_MC.D2_PT_1/IN1 ),
    .I2(U2_ASedge),
    .I3(\U1/Channel0 [11]),
    .O(\U1/U3/holdingreg0<11>_MC.D2_PT_1 )
  );
  X_OR2 \U1/U3/holdingreg0<11>_MC.D2_1968  (
    .I0(\U1/U3/holdingreg0<11>_MC.D2_PT_0 ),
    .I1(\U1/U3/holdingreg0<11>_MC.D2_PT_1 ),
    .O(\U1/U3/holdingreg0<11>_MC.D2 )
  );
  X_BUF \U1/U3/holdingreg1<11>  (
    .I(\U1/U3/holdingreg1<11>_MC.Q ),
    .O(\U1/U3/holdingreg1 [11])
  );
  X_FF \U1/U3/holdingreg1<11>_MC.REG  (
    .I(\U1/U3/holdingreg1<11>_MC.D ),
    .CE(Vcc),
    .CLK(\U1/U3/holdingreg1<11>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\U1/U3/holdingreg1<11>_MC.Q )
  );
  X_INV \U1/U3/holdingreg1<11>_MC.REG_tsimcreated_inv_Mclk_II/FCLK_1969  (
    .I(\Mclk_II/FCLK ),
    .O(\U1/U3/holdingreg1<11>_MC.REG_tsimcreated_inv_Mclk_II/FCLK )
  );
  X_XOR2 \U1/U3/holdingreg1<11>_MC.D_1970  (
    .I0(\U1/U3/holdingreg1<11>_MC.D1 ),
    .I1(\U1/U3/holdingreg1<11>_MC.D2 ),
    .O(\U1/U3/holdingreg1<11>_MC.D )
  );
  X_ZERO \U1/U3/holdingreg1<11>_MC.D1_1971  (
    .O(\U1/U3/holdingreg1<11>_MC.D1 )
  );
  X_AND2 \U1/U3/holdingreg1<11>_MC.D2_PT_0_1972  (
    .I0(N_PZ_992),
    .I1(\U1/U3/holdingreg1 [11]),
    .O(\U1/U3/holdingreg1<11>_MC.D2_PT_0 )
  );
  X_AND4 \U1/U3/holdingreg1<11>_MC.D2_PT_1_1973  (
    .I0(\MSPReset_II/UIM ),
    .I1(\NlwInverterSignal_U1/U3/holdingreg1<11>_MC.D2_PT_1/IN1 ),
    .I2(U2_ASedge),
    .I3(\U1/Channel1 [11]),
    .O(\U1/U3/holdingreg1<11>_MC.D2_PT_1 )
  );
  X_OR2 \U1/U3/holdingreg1<11>_MC.D2_1974  (
    .I0(\U1/U3/holdingreg1<11>_MC.D2_PT_0 ),
    .I1(\U1/U3/holdingreg1<11>_MC.D2_PT_1 ),
    .O(\U1/U3/holdingreg1<11>_MC.D2 )
  );
  X_BUF \outDATA<3>\$WA2.UIM_1975  (
    .I(\outDATA<3>\$WA2.UIM_MC.Q ),
    .O(\outDATA<3>\$WA2.UIM )
  );
  X_BUF \outDATA<3>\$WA2.UIM_MC.Q_1976  (
    .I(\outDATA<3>\$WA2.UIM_MC.D ),
    .O(\outDATA<3>\$WA2.UIM_MC.Q )
  );
  X_XOR2 \outDATA<3>\$WA2.UIM_MC.D_1977  (
    .I0(\outDATA<3>\$WA2.UIM_MC.D1 ),
    .I1(\outDATA<3>\$WA2.UIM_MC.D2 ),
    .O(\outDATA<3>\$WA2.UIM_MC.D )
  );
  X_ZERO \outDATA<3>\$WA2.UIM_MC.D1_1978  (
    .O(\outDATA<3>\$WA2.UIM_MC.D1 )
  );
  X_AND2 \outDATA<3>\$WA2.UIM_MC.D2_PT_0_1979  (
    .I0(DCOR0THRESLOWr),
    .I1(\U1/U4/Latch0r [3]),
    .O(\outDATA<3>\$WA2.UIM_MC.D2_PT_0 )
  );
  X_AND3 \outDATA<3>\$WA2.UIM_MC.D2_PT_1_1980  (
    .I0(\NlwInverterSignal_outDATA<3>\$WA2.UIM_MC.D2_PT_1/IN0 ),
    .I1(DCORIFGr),
    .I2(NET2493),
    .O(\outDATA<3>\$WA2.UIM_MC.D2_PT_1 )
  );
  X_AND4 \outDATA<3>\$WA2.UIM_MC.D2_PT_2_1981  (
    .I0(\NlwInverterSignal_outDATA<3>\$WA2.UIM_MC.D2_PT_2/IN0 ),
    .I1(\NlwInverterSignal_outDATA<3>\$WA2.UIM_MC.D2_PT_2/IN1 ),
    .I2(DCOR0THRESHIGHr),
    .I3(\U1/U4/Latch0r [11]),
    .O(\outDATA<3>\$WA2.UIM_MC.D2_PT_2 )
  );
  X_AND5 \outDATA<3>\$WA2.UIM_MC.D2_PT_3_1982  (
    .I0(\NlwInverterSignal_outDATA<3>\$WA2.UIM_MC.D2_PT_3/IN0 ),
    .I1(\NlwInverterSignal_outDATA<3>\$WA2.UIM_MC.D2_PT_3/IN1 ),
    .I2(\NlwInverterSignal_outDATA<3>\$WA2.UIM_MC.D2_PT_3/IN2 ),
    .I3(DCOR1THRESLOWr),
    .I4(\U1/U4/Latch1r [3]),
    .O(\outDATA<3>\$WA2.UIM_MC.D2_PT_3 )
  );
  X_AND5 \outDATA<3>\$WA2.UIM_MC.D2_PT_4_1983  (
    .I0(\NlwInverterSignal_outDATA<3>\$WA2.UIM_MC.D2_PT_4/IN0 ),
    .I1(\NlwInverterSignal_outDATA<3>\$WA2.UIM_MC.D2_PT_4/IN1 ),
    .I2(\NlwInverterSignal_outDATA<3>\$WA2.UIM_MC.D2_PT_4/IN2 ),
    .I3(\NlwInverterSignal_outDATA<3>\$WA2.UIM_MC.D2_PT_4/IN3 ),
    .I4(\U1/U4/Latch1r [11]),
    .O(\outDATA<3>\$WA2.UIM_MC.D2_PT_4 )
  );
  X_OR5 \outDATA<3>\$WA2.UIM_MC.D2_1984  (
    .I0(\outDATA<3>\$WA2.UIM_MC.D2_PT_0 ),
    .I1(\outDATA<3>\$WA2.UIM_MC.D2_PT_1 ),
    .I2(\outDATA<3>\$WA2.UIM_MC.D2_PT_2 ),
    .I3(\outDATA<3>\$WA2.UIM_MC.D2_PT_3 ),
    .I4(\outDATA<3>\$WA2.UIM_MC.D2_PT_4 ),
    .O(\outDATA<3>\$WA2.UIM_MC.D2 )
  );
  X_BUF \U1/U4/Latch0r<3>  (
    .I(\U1/U4/Latch0r<3>_MC.Q ),
    .O(\U1/U4/Latch0r [3])
  );
  X_FF \U1/U4/Latch0r<3>_MC.REG  (
    .I(\U1/U4/Latch0r<3>_MC.D ),
    .CE(Vcc),
    .CLK(\U1/U4/Latch0r<3>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\U1/U4/Latch0r<3>_MC.Q )
  );
  X_INV \U1/U4/Latch0r<3>_MC.REG_tsimcreated_inv_Mclk_II/FCLK_1985  (
    .I(\Mclk_II/FCLK ),
    .O(\U1/U4/Latch0r<3>_MC.REG_tsimcreated_inv_Mclk_II/FCLK )
  );
  X_XOR2 \U1/U4/Latch0r<3>_MC.D_1986  (
    .I0(\U1/U4/Latch0r<3>_MC.D1 ),
    .I1(\U1/U4/Latch0r<3>_MC.D2 ),
    .O(\U1/U4/Latch0r<3>_MC.D )
  );
  X_ZERO \U1/U4/Latch0r<3>_MC.D1_1987  (
    .O(\U1/U4/Latch0r<3>_MC.D1 )
  );
  X_AND3 \U1/U4/Latch0r<3>_MC.D2_PT_0_1988  (
    .I0(\MSPReset_II/UIM ),
    .I1(N_PZ_1018),
    .I2(\U1/Channel0 [3]),
    .O(\U1/U4/Latch0r<3>_MC.D2_PT_0 )
  );
  X_AND3 \U1/U4/Latch0r<3>_MC.D2_PT_1_1989  (
    .I0(\MSPReset_II/UIM ),
    .I1(\NlwInverterSignal_U1/U4/Latch0r<3>_MC.D2_PT_1/IN1 ),
    .I2(\U1/U4/Latch0r [3]),
    .O(\U1/U4/Latch0r<3>_MC.D2_PT_1 )
  );
  X_OR2 \U1/U4/Latch0r<3>_MC.D2_1990  (
    .I0(\U1/U4/Latch0r<3>_MC.D2_PT_0 ),
    .I1(\U1/U4/Latch0r<3>_MC.D2_PT_1 ),
    .O(\U1/U4/Latch0r<3>_MC.D2 )
  );
  X_BUF \U1/U4/Latch0r<11>  (
    .I(\U1/U4/Latch0r<11>_MC.Q ),
    .O(\U1/U4/Latch0r [11])
  );
  X_FF \U1/U4/Latch0r<11>_MC.REG  (
    .I(\U1/U4/Latch0r<11>_MC.D ),
    .CE(Vcc),
    .CLK(\U1/U4/Latch0r<11>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\U1/U4/Latch0r<11>_MC.Q )
  );
  X_INV \U1/U4/Latch0r<11>_MC.REG_tsimcreated_inv_Mclk_II/FCLK_1991  (
    .I(\Mclk_II/FCLK ),
    .O(\U1/U4/Latch0r<11>_MC.REG_tsimcreated_inv_Mclk_II/FCLK )
  );
  X_XOR2 \U1/U4/Latch0r<11>_MC.D_1992  (
    .I0(\U1/U4/Latch0r<11>_MC.D1 ),
    .I1(\U1/U4/Latch0r<11>_MC.D2 ),
    .O(\U1/U4/Latch0r<11>_MC.D )
  );
  X_ZERO \U1/U4/Latch0r<11>_MC.D1_1993  (
    .O(\U1/U4/Latch0r<11>_MC.D1 )
  );
  X_AND3 \U1/U4/Latch0r<11>_MC.D2_PT_0_1994  (
    .I0(\MSPReset_II/UIM ),
    .I1(N_PZ_1018),
    .I2(\U1/Channel0 [11]),
    .O(\U1/U4/Latch0r<11>_MC.D2_PT_0 )
  );
  X_AND3 \U1/U4/Latch0r<11>_MC.D2_PT_1_1995  (
    .I0(\MSPReset_II/UIM ),
    .I1(\NlwInverterSignal_U1/U4/Latch0r<11>_MC.D2_PT_1/IN1 ),
    .I2(\U1/U4/Latch0r [11]),
    .O(\U1/U4/Latch0r<11>_MC.D2_PT_1 )
  );
  X_OR2 \U1/U4/Latch0r<11>_MC.D2_1996  (
    .I0(\U1/U4/Latch0r<11>_MC.D2_PT_0 ),
    .I1(\U1/U4/Latch0r<11>_MC.D2_PT_1 ),
    .O(\U1/U4/Latch0r<11>_MC.D2 )
  );
  X_BUF \U1/U4/Latch1r<3>  (
    .I(\U1/U4/Latch1r<3>_MC.Q ),
    .O(\U1/U4/Latch1r [3])
  );
  X_FF \U1/U4/Latch1r<3>_MC.REG  (
    .I(\U1/U4/Latch1r<3>_MC.D ),
    .CE(Vcc),
    .CLK(\U1/U4/Latch1r<3>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\U1/U4/Latch1r<3>_MC.Q )
  );
  X_INV \U1/U4/Latch1r<3>_MC.REG_tsimcreated_inv_Mclk_II/FCLK_1997  (
    .I(\Mclk_II/FCLK ),
    .O(\U1/U4/Latch1r<3>_MC.REG_tsimcreated_inv_Mclk_II/FCLK )
  );
  X_XOR2 \U1/U4/Latch1r<3>_MC.D_1998  (
    .I0(\U1/U4/Latch1r<3>_MC.D1 ),
    .I1(\U1/U4/Latch1r<3>_MC.D2 ),
    .O(\U1/U4/Latch1r<3>_MC.D )
  );
  X_ZERO \U1/U4/Latch1r<3>_MC.D1_1999  (
    .O(\U1/U4/Latch1r<3>_MC.D1 )
  );
  X_AND3 \U1/U4/Latch1r<3>_MC.D2_PT_0_2000  (
    .I0(\MSPReset_II/UIM ),
    .I1(N_PZ_1019),
    .I2(\U1/Channel1 [3]),
    .O(\U1/U4/Latch1r<3>_MC.D2_PT_0 )
  );
  X_AND3 \U1/U4/Latch1r<3>_MC.D2_PT_1_2001  (
    .I0(\MSPReset_II/UIM ),
    .I1(\NlwInverterSignal_U1/U4/Latch1r<3>_MC.D2_PT_1/IN1 ),
    .I2(\U1/U4/Latch1r [3]),
    .O(\U1/U4/Latch1r<3>_MC.D2_PT_1 )
  );
  X_OR2 \U1/U4/Latch1r<3>_MC.D2_2002  (
    .I0(\U1/U4/Latch1r<3>_MC.D2_PT_0 ),
    .I1(\U1/U4/Latch1r<3>_MC.D2_PT_1 ),
    .O(\U1/U4/Latch1r<3>_MC.D2 )
  );
  X_BUF \U1/U4/Latch1r<11>  (
    .I(\U1/U4/Latch1r<11>_MC.Q ),
    .O(\U1/U4/Latch1r [11])
  );
  X_FF \U1/U4/Latch1r<11>_MC.REG  (
    .I(\U1/U4/Latch1r<11>_MC.D ),
    .CE(Vcc),
    .CLK(\U1/U4/Latch1r<11>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\U1/U4/Latch1r<11>_MC.Q )
  );
  X_INV \U1/U4/Latch1r<11>_MC.REG_tsimcreated_inv_Mclk_II/FCLK_2003  (
    .I(\Mclk_II/FCLK ),
    .O(\U1/U4/Latch1r<11>_MC.REG_tsimcreated_inv_Mclk_II/FCLK )
  );
  X_XOR2 \U1/U4/Latch1r<11>_MC.D_2004  (
    .I0(\U1/U4/Latch1r<11>_MC.D1 ),
    .I1(\U1/U4/Latch1r<11>_MC.D2 ),
    .O(\U1/U4/Latch1r<11>_MC.D )
  );
  X_ZERO \U1/U4/Latch1r<11>_MC.D1_2005  (
    .O(\U1/U4/Latch1r<11>_MC.D1 )
  );
  X_AND3 \U1/U4/Latch1r<11>_MC.D2_PT_0_2006  (
    .I0(\MSPReset_II/UIM ),
    .I1(N_PZ_1019),
    .I2(\U1/Channel1 [11]),
    .O(\U1/U4/Latch1r<11>_MC.D2_PT_0 )
  );
  X_AND3 \U1/U4/Latch1r<11>_MC.D2_PT_1_2007  (
    .I0(\MSPReset_II/UIM ),
    .I1(\NlwInverterSignal_U1/U4/Latch1r<11>_MC.D2_PT_1/IN1 ),
    .I2(\U1/U4/Latch1r [11]),
    .O(\U1/U4/Latch1r<11>_MC.D2_PT_1 )
  );
  X_OR2 \U1/U4/Latch1r<11>_MC.D2_2008  (
    .I0(\U1/U4/Latch1r<11>_MC.D2_PT_0 ),
    .I1(\U1/U4/Latch1r<11>_MC.D2_PT_1 ),
    .O(\U1/U4/Latch1r<11>_MC.D2 )
  );
  X_BUF \outDATA<6>\$WA0.UIM_2009  (
    .I(\outDATA<6>\$WA0.UIM_MC.Q ),
    .O(\outDATA<6>\$WA0.UIM )
  );
  X_BUF \outDATA<6>\$WA0.UIM_MC.Q_2010  (
    .I(\outDATA<6>\$WA0.UIM_MC.D ),
    .O(\outDATA<6>\$WA0.UIM_MC.Q )
  );
  X_XOR2 \outDATA<6>\$WA0.UIM_MC.D_2011  (
    .I0(\outDATA<6>\$WA0.UIM_MC.D1 ),
    .I1(\outDATA<6>\$WA0.UIM_MC.D2 ),
    .O(\outDATA<6>\$WA0.UIM_MC.D )
  );
  X_ZERO \outDATA<6>\$WA0.UIM_MC.D1_2012  (
    .O(\outDATA<6>\$WA0.UIM_MC.D1 )
  );
  X_ZERO \outDATA<6>\$WA0.UIM_MC.D2_2013  (
    .O(\outDATA<6>\$WA0.UIM_MC.D2 )
  );
  X_BUF \outDATA<6>\$WA5.UIM_2014  (
    .I(\outDATA<6>\$WA5.UIM_MC.Q ),
    .O(\outDATA<6>\$WA5.UIM )
  );
  X_BUF \outDATA<6>\$WA5.UIM_MC.Q_2015  (
    .I(\outDATA<6>\$WA5.UIM_MC.D ),
    .O(\outDATA<6>\$WA5.UIM_MC.Q )
  );
  X_XOR2 \outDATA<6>\$WA5.UIM_MC.D_2016  (
    .I0(\outDATA<6>\$WA5.UIM_MC.D1 ),
    .I1(\outDATA<6>\$WA5.UIM_MC.D2 ),
    .O(\outDATA<6>\$WA5.UIM_MC.D )
  );
  X_ZERO \outDATA<6>\$WA5.UIM_MC.D1_2017  (
    .O(\outDATA<6>\$WA5.UIM_MC.D1 )
  );
  X_AND2 \outDATA<6>\$WA5.UIM_MC.D2_PT_0_2018  (
    .I0(NET2528),
    .I1(\U4/Flgreg [6]),
    .O(\outDATA<6>\$WA5.UIM_MC.D2_PT_0 )
  );
  X_AND2 \outDATA<6>\$WA5.UIM_MC.D2_PT_1_2019  (
    .I0(\NlwInverterSignal_outDATA<6>\$WA5.UIM_MC.D2_PT_1/IN0 ),
    .I1(\Enc133FLG_II/UIM ),
    .O(\outDATA<6>\$WA5.UIM_MC.D2_PT_1 )
  );
  X_OR2 \outDATA<6>\$WA5.UIM_MC.D2_2020  (
    .I0(\outDATA<6>\$WA5.UIM_MC.D2_PT_0 ),
    .I1(\outDATA<6>\$WA5.UIM_MC.D2_PT_1 ),
    .O(\outDATA<6>\$WA5.UIM_MC.D2 )
  );
  X_BUF \outDATA<6>\$WA4.UIM_2021  (
    .I(\outDATA<6>\$WA4.UIM_MC.Q ),
    .O(\outDATA<6>\$WA4.UIM )
  );
  X_BUF \outDATA<6>\$WA4.UIM_MC.Q_2022  (
    .I(\outDATA<6>\$WA4.UIM_MC.D ),
    .O(\outDATA<6>\$WA4.UIM_MC.Q )
  );
  X_XOR2 \outDATA<6>\$WA4.UIM_MC.D_2023  (
    .I0(\outDATA<6>\$WA4.UIM_MC.D1 ),
    .I1(\outDATA<6>\$WA4.UIM_MC.D2 ),
    .O(\outDATA<6>\$WA4.UIM_MC.D )
  );
  X_AND2 \outDATA<6>\$WA4.UIM_MC.D1_2024  (
    .I0(DCORLIMITSr),
    .I1(\Home1_II/UIM ),
    .O(\outDATA<6>\$WA4.UIM_MC.D1 )
  );
  X_ZERO \outDATA<6>\$WA4.UIM_MC.D2_2025  (
    .O(\outDATA<6>\$WA4.UIM_MC.D2 )
  );
  X_BUF \outDATA<6>\$WA1.UIM_2026  (
    .I(\outDATA<6>\$WA1.UIM_MC.Q ),
    .O(\outDATA<6>\$WA1.UIM )
  );
  X_BUF \outDATA<6>\$WA1.UIM_MC.Q_2027  (
    .I(\outDATA<6>\$WA1.UIM_MC.D ),
    .O(\outDATA<6>\$WA1.UIM_MC.Q )
  );
  X_XOR2 \outDATA<6>\$WA1.UIM_MC.D_2028  (
    .I0(\outDATA<6>\$WA1.UIM_MC.D1 ),
    .I1(\outDATA<6>\$WA1.UIM_MC.D2 ),
    .O(\outDATA<6>\$WA1.UIM_MC.D )
  );
  X_ZERO \outDATA<6>\$WA1.UIM_MC.D1_2029  (
    .O(\outDATA<6>\$WA1.UIM_MC.D1 )
  );
  X_AND2 \outDATA<6>\$WA1.UIM_MC.D2_PT_0_2030  (
    .I0(DCOR0CNTLOWr),
    .I1(\U1/U3/holdingreg0 [6]),
    .O(\outDATA<6>\$WA1.UIM_MC.D2_PT_0 )
  );
  X_AND3 \outDATA<6>\$WA1.UIM_MC.D2_PT_1_2031  (
    .I0(\NlwInverterSignal_outDATA<6>\$WA1.UIM_MC.D2_PT_1/IN0 ),
    .I1(DCOR1CNTLOWr),
    .I2(\U1/U3/holdingreg1 [6]),
    .O(\outDATA<6>\$WA1.UIM_MC.D2_PT_1 )
  );
  X_AND4 \outDATA<6>\$WA1.UIM_MC.D2_PT_2_2032  (
    .I0(\NlwInverterSignal_outDATA<6>\$WA1.UIM_MC.D2_PT_2/IN0 ),
    .I1(\NlwInverterSignal_outDATA<6>\$WA1.UIM_MC.D2_PT_2/IN1 ),
    .I2(DCOR0CNTHIGHr),
    .I3(\U1/U3/holdingreg0 [14]),
    .O(\outDATA<6>\$WA1.UIM_MC.D2_PT_2 )
  );
  X_AND4 \outDATA<6>\$WA1.UIM_MC.D2_PT_3_2033  (
    .I0(\NlwInverterSignal_outDATA<6>\$WA1.UIM_MC.D2_PT_3/IN0 ),
    .I1(\NlwInverterSignal_outDATA<6>\$WA1.UIM_MC.D2_PT_3/IN1 ),
    .I2(\NlwInverterSignal_outDATA<6>\$WA1.UIM_MC.D2_PT_3/IN2 ),
    .I3(\U1/U3/holdingreg1 [14]),
    .O(\outDATA<6>\$WA1.UIM_MC.D2_PT_3 )
  );
  X_OR4 \outDATA<6>\$WA1.UIM_MC.D2_2034  (
    .I0(\outDATA<6>\$WA1.UIM_MC.D2_PT_0 ),
    .I1(\outDATA<6>\$WA1.UIM_MC.D2_PT_1 ),
    .I2(\outDATA<6>\$WA1.UIM_MC.D2_PT_2 ),
    .I3(\outDATA<6>\$WA1.UIM_MC.D2_PT_3 ),
    .O(\outDATA<6>\$WA1.UIM_MC.D2 )
  );
  X_BUF \U1/U3/holdingreg0<6>  (
    .I(\U1/U3/holdingreg0<6>_MC.Q ),
    .O(\U1/U3/holdingreg0 [6])
  );
  X_FF \U1/U3/holdingreg0<6>_MC.REG  (
    .I(\U1/U3/holdingreg0<6>_MC.D ),
    .CE(Vcc),
    .CLK(\U1/U3/holdingreg0<6>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\U1/U3/holdingreg0<6>_MC.Q )
  );
  X_INV \U1/U3/holdingreg0<6>_MC.REG_tsimcreated_inv_Mclk_II/FCLK_2035  (
    .I(\Mclk_II/FCLK ),
    .O(\U1/U3/holdingreg0<6>_MC.REG_tsimcreated_inv_Mclk_II/FCLK )
  );
  X_XOR2 \U1/U3/holdingreg0<6>_MC.D_2036  (
    .I0(\U1/U3/holdingreg0<6>_MC.D1 ),
    .I1(\U1/U3/holdingreg0<6>_MC.D2 ),
    .O(\U1/U3/holdingreg0<6>_MC.D )
  );
  X_ZERO \U1/U3/holdingreg0<6>_MC.D1_2037  (
    .O(\U1/U3/holdingreg0<6>_MC.D1 )
  );
  X_AND2 \U1/U3/holdingreg0<6>_MC.D2_PT_0_2038  (
    .I0(N_PZ_992),
    .I1(\U1/U3/holdingreg0 [6]),
    .O(\U1/U3/holdingreg0<6>_MC.D2_PT_0 )
  );
  X_AND4 \U1/U3/holdingreg0<6>_MC.D2_PT_1_2039  (
    .I0(\MSPReset_II/UIM ),
    .I1(\NlwInverterSignal_U1/U3/holdingreg0<6>_MC.D2_PT_1/IN1 ),
    .I2(U2_ASedge),
    .I3(\U1/Channel0 [6]),
    .O(\U1/U3/holdingreg0<6>_MC.D2_PT_1 )
  );
  X_OR2 \U1/U3/holdingreg0<6>_MC.D2_2040  (
    .I0(\U1/U3/holdingreg0<6>_MC.D2_PT_0 ),
    .I1(\U1/U3/holdingreg0<6>_MC.D2_PT_1 ),
    .O(\U1/U3/holdingreg0<6>_MC.D2 )
  );
  X_BUF \U1/U3/holdingreg1<6>  (
    .I(\U1/U3/holdingreg1<6>_MC.Q ),
    .O(\U1/U3/holdingreg1 [6])
  );
  X_FF \U1/U3/holdingreg1<6>_MC.REG  (
    .I(\U1/U3/holdingreg1<6>_MC.D ),
    .CE(Vcc),
    .CLK(\U1/U3/holdingreg1<6>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\U1/U3/holdingreg1<6>_MC.Q )
  );
  X_INV \U1/U3/holdingreg1<6>_MC.REG_tsimcreated_inv_Mclk_II/FCLK_2041  (
    .I(\Mclk_II/FCLK ),
    .O(\U1/U3/holdingreg1<6>_MC.REG_tsimcreated_inv_Mclk_II/FCLK )
  );
  X_XOR2 \U1/U3/holdingreg1<6>_MC.D_2042  (
    .I0(\U1/U3/holdingreg1<6>_MC.D1 ),
    .I1(\U1/U3/holdingreg1<6>_MC.D2 ),
    .O(\U1/U3/holdingreg1<6>_MC.D )
  );
  X_ZERO \U1/U3/holdingreg1<6>_MC.D1_2043  (
    .O(\U1/U3/holdingreg1<6>_MC.D1 )
  );
  X_AND2 \U1/U3/holdingreg1<6>_MC.D2_PT_0_2044  (
    .I0(N_PZ_992),
    .I1(\U1/U3/holdingreg1 [6]),
    .O(\U1/U3/holdingreg1<6>_MC.D2_PT_0 )
  );
  X_AND4 \U1/U3/holdingreg1<6>_MC.D2_PT_1_2045  (
    .I0(\MSPReset_II/UIM ),
    .I1(\NlwInverterSignal_U1/U3/holdingreg1<6>_MC.D2_PT_1/IN1 ),
    .I2(U2_ASedge),
    .I3(\U1/Channel1 [6]),
    .O(\U1/U3/holdingreg1<6>_MC.D2_PT_1 )
  );
  X_OR2 \U1/U3/holdingreg1<6>_MC.D2_2046  (
    .I0(\U1/U3/holdingreg1<6>_MC.D2_PT_0 ),
    .I1(\U1/U3/holdingreg1<6>_MC.D2_PT_1 ),
    .O(\U1/U3/holdingreg1<6>_MC.D2 )
  );
  X_BUF \U1/U3/holdingreg0<14>  (
    .I(\U1/U3/holdingreg0<14>_MC.Q ),
    .O(\U1/U3/holdingreg0 [14])
  );
  X_FF \U1/U3/holdingreg0<14>_MC.REG  (
    .I(\U1/U3/holdingreg0<14>_MC.D ),
    .CE(Vcc),
    .CLK(\U1/U3/holdingreg0<14>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\U1/U3/holdingreg0<14>_MC.Q )
  );
  X_INV \U1/U3/holdingreg0<14>_MC.REG_tsimcreated_inv_Mclk_II/FCLK_2047  (
    .I(\Mclk_II/FCLK ),
    .O(\U1/U3/holdingreg0<14>_MC.REG_tsimcreated_inv_Mclk_II/FCLK )
  );
  X_XOR2 \U1/U3/holdingreg0<14>_MC.D_2048  (
    .I0(\U1/U3/holdingreg0<14>_MC.D1 ),
    .I1(\U1/U3/holdingreg0<14>_MC.D2 ),
    .O(\U1/U3/holdingreg0<14>_MC.D )
  );
  X_ZERO \U1/U3/holdingreg0<14>_MC.D1_2049  (
    .O(\U1/U3/holdingreg0<14>_MC.D1 )
  );
  X_AND2 \U1/U3/holdingreg0<14>_MC.D2_PT_0_2050  (
    .I0(N_PZ_992),
    .I1(\U1/U3/holdingreg0 [14]),
    .O(\U1/U3/holdingreg0<14>_MC.D2_PT_0 )
  );
  X_AND4 \U1/U3/holdingreg0<14>_MC.D2_PT_1_2051  (
    .I0(\MSPReset_II/UIM ),
    .I1(\NlwInverterSignal_U1/U3/holdingreg0<14>_MC.D2_PT_1/IN1 ),
    .I2(U2_ASedge),
    .I3(\U1/Channel0 [14]),
    .O(\U1/U3/holdingreg0<14>_MC.D2_PT_1 )
  );
  X_OR2 \U1/U3/holdingreg0<14>_MC.D2_2052  (
    .I0(\U1/U3/holdingreg0<14>_MC.D2_PT_0 ),
    .I1(\U1/U3/holdingreg0<14>_MC.D2_PT_1 ),
    .O(\U1/U3/holdingreg0<14>_MC.D2 )
  );
  X_BUF \U1/Channel0<14>  (
    .I(\U1/Channel0<14>_MC.Q ),
    .O(\U1/Channel0 [14])
  );
  X_XOR2 \U1/Channel0<14>_MC_tsimcreated_xor__2053  (
    .I0(\U1/Channel0<14>_MC.D ),
    .I1(\U1/Channel0<14>_MC.Q ),
    .O(\U1/Channel0<14>_MC_tsimcreated_xor_ )
  );
  X_FF \U1/Channel0<14>_MC.REG  (
    .I(\U1/Channel0<14>_MC_tsimcreated_xor_ ),
    .CE(Vcc),
    .CLK(\Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\U1/Channel0<14>_MC.Q )
  );
  X_XOR2 \U1/Channel0<14>_MC.D_2054  (
    .I0(\U1/Channel0<14>_MC.D1 ),
    .I1(\U1/Channel0<14>_MC.D2 ),
    .O(\U1/Channel0<14>_MC.D )
  );
  X_ZERO \U1/Channel0<14>_MC.D1_2055  (
    .O(\U1/Channel0<14>_MC.D1 )
  );
  X_AND2 \U1/Channel0<14>_MC.D2_PT_0_2056  (
    .I0(\NlwInverterSignal_U1/Channel0<14>_MC.D2_PT_0/IN0 ),
    .I1(\U1/Channel0 [14]),
    .O(\U1/Channel0<14>_MC.D2_PT_0 )
  );
  X_AND7 \U1/Channel0<14>_MC.D2_PT_1_2057  (
    .I0(\U1/U2/location_Maddsub__n0000__n0075 [0]),
    .I1(N_PZ_1021),
    .I2(\NlwInverterSignal_U1/Channel0<14>_MC.D2_PT_1/IN2 ),
    .I3(\NlwInverterSignal_U1/Channel0<14>_MC.D2_PT_1/IN3 ),
    .I4(\NlwInverterSignal_U1/Channel0<14>_MC.D2_PT_1/IN4 ),
    .I5(\NlwInverterSignal_U1/Channel0<14>_MC.D2_PT_1/IN5 ),
    .I6(\NlwInverterSignal_U1/Channel0<14>_MC.D2_PT_1/IN6 ),
    .O(\U1/Channel0<14>_MC.D2_PT_1 )
  );
  X_AND7 \U1/Channel0<14>_MC.D2_PT_2_2058  (
    .I0(\NlwInverterSignal_U1/Channel0<14>_MC.D2_PT_2/IN0 ),
    .I1(N_PZ_1024),
    .I2(\U1/Channel0 [9]),
    .I3(\U1/Channel0 [12]),
    .I4(\U1/Channel0 [10]),
    .I5(\U1/Channel0 [11]),
    .I6(\U1/Channel0 [13]),
    .O(\U1/Channel0<14>_MC.D2_PT_2 )
  );
  X_OR3 \U1/Channel0<14>_MC.D2_2059  (
    .I0(\U1/Channel0<14>_MC.D2_PT_0 ),
    .I1(\U1/Channel0<14>_MC.D2_PT_1 ),
    .I2(\U1/Channel0<14>_MC.D2_PT_2 ),
    .O(\U1/Channel0<14>_MC.D2 )
  );
  X_BUF \U1/U3/holdingreg1<14>  (
    .I(\U1/U3/holdingreg1<14>_MC.Q ),
    .O(\U1/U3/holdingreg1 [14])
  );
  X_FF \U1/U3/holdingreg1<14>_MC.REG  (
    .I(\U1/U3/holdingreg1<14>_MC.D ),
    .CE(Vcc),
    .CLK(\U1/U3/holdingreg1<14>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\U1/U3/holdingreg1<14>_MC.Q )
  );
  X_INV \U1/U3/holdingreg1<14>_MC.REG_tsimcreated_inv_Mclk_II/FCLK_2060  (
    .I(\Mclk_II/FCLK ),
    .O(\U1/U3/holdingreg1<14>_MC.REG_tsimcreated_inv_Mclk_II/FCLK )
  );
  X_XOR2 \U1/U3/holdingreg1<14>_MC.D_2061  (
    .I0(\U1/U3/holdingreg1<14>_MC.D1 ),
    .I1(\U1/U3/holdingreg1<14>_MC.D2 ),
    .O(\U1/U3/holdingreg1<14>_MC.D )
  );
  X_ZERO \U1/U3/holdingreg1<14>_MC.D1_2062  (
    .O(\U1/U3/holdingreg1<14>_MC.D1 )
  );
  X_AND2 \U1/U3/holdingreg1<14>_MC.D2_PT_0_2063  (
    .I0(N_PZ_992),
    .I1(\U1/U3/holdingreg1 [14]),
    .O(\U1/U3/holdingreg1<14>_MC.D2_PT_0 )
  );
  X_AND4 \U1/U3/holdingreg1<14>_MC.D2_PT_1_2064  (
    .I0(\MSPReset_II/UIM ),
    .I1(\NlwInverterSignal_U1/U3/holdingreg1<14>_MC.D2_PT_1/IN1 ),
    .I2(U2_ASedge),
    .I3(\U1/Channel1 [14]),
    .O(\U1/U3/holdingreg1<14>_MC.D2_PT_1 )
  );
  X_OR2 \U1/U3/holdingreg1<14>_MC.D2_2065  (
    .I0(\U1/U3/holdingreg1<14>_MC.D2_PT_0 ),
    .I1(\U1/U3/holdingreg1<14>_MC.D2_PT_1 ),
    .O(\U1/U3/holdingreg1<14>_MC.D2 )
  );
  X_BUF \U1/Channel1<14>  (
    .I(\U1/Channel1<14>_MC.Q ),
    .O(\U1/Channel1 [14])
  );
  X_XOR2 \U1/Channel1<14>_MC_tsimcreated_xor__2066  (
    .I0(\U1/Channel1<14>_MC.D ),
    .I1(\U1/Channel1<14>_MC.Q ),
    .O(\U1/Channel1<14>_MC_tsimcreated_xor_ )
  );
  X_FF \U1/Channel1<14>_MC.REG  (
    .I(\U1/Channel1<14>_MC_tsimcreated_xor_ ),
    .CE(Vcc),
    .CLK(\Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\U1/Channel1<14>_MC.Q )
  );
  X_XOR2 \U1/Channel1<14>_MC.D_2067  (
    .I0(\U1/Channel1<14>_MC.D1 ),
    .I1(\U1/Channel1<14>_MC.D2 ),
    .O(\U1/Channel1<14>_MC.D )
  );
  X_ZERO \U1/Channel1<14>_MC.D1_2068  (
    .O(\U1/Channel1<14>_MC.D1 )
  );
  X_AND2 \U1/Channel1<14>_MC.D2_PT_0_2069  (
    .I0(\NlwInverterSignal_U1/Channel1<14>_MC.D2_PT_0/IN0 ),
    .I1(\U1/Channel1 [14]),
    .O(\U1/Channel1<14>_MC.D2_PT_0 )
  );
  X_AND16 \U1/Channel1<14>_MC.D2_PT_1_2070  (
    .I0(\MSPReset_II/UIM ),
    .I1(\NlwInverterSignal_U1/Channel1<14>_MC.D2_PT_1/IN1 ),
    .I2(\U1/U6/CurrState_Sreg0_FFD3 ),
    .I3(\NlwInverterSignal_U1/Channel1<14>_MC.D2_PT_1/IN3 ),
    .I4(N_PZ_975),
    .I5(\NlwInverterSignal_U1/Channel1<14>_MC.D2_PT_1/IN5 ),
    .I6(\U1/Channel1 [9]),
    .I7(\U1/Channel1 [12]),
    .I8(\U1/Channel1 [10]),
    .I9(\U1/Channel1 [11]),
    .I10(\U1/Channel1 [13]),
    .I11(Vcc),
    .I12(Vcc),
    .I13(Vcc),
    .I14(Vcc),
    .I15(Vcc),
    .O(\U1/Channel1<14>_MC.D2_PT_1 )
  );
  X_AND16 \U1/Channel1<14>_MC.D2_PT_2_2071  (
    .I0(\MSPReset_II/UIM ),
    .I1(\NlwInverterSignal_U1/Channel1<14>_MC.D2_PT_2/IN1 ),
    .I2(\U1/U6/CurrState_Sreg0_FFD3 ),
    .I3(\NlwInverterSignal_U1/Channel1<14>_MC.D2_PT_2/IN3 ),
    .I4(N_PZ_1154),
    .I5(\NlwInverterSignal_U1/Channel1<14>_MC.D2_PT_2/IN5 ),
    .I6(\U1/U5/location_Maddsub__n0000__n0075 [0]),
    .I7(\NlwInverterSignal_U1/Channel1<14>_MC.D2_PT_2/IN7 ),
    .I8(\NlwInverterSignal_U1/Channel1<14>_MC.D2_PT_2/IN8 ),
    .I9(\NlwInverterSignal_U1/Channel1<14>_MC.D2_PT_2/IN9 ),
    .I10(\NlwInverterSignal_U1/Channel1<14>_MC.D2_PT_2/IN10 ),
    .I11(\NlwInverterSignal_U1/Channel1<14>_MC.D2_PT_2/IN11 ),
    .I12(Vcc),
    .I13(Vcc),
    .I14(Vcc),
    .I15(Vcc),
    .O(\U1/Channel1<14>_MC.D2_PT_2 )
  );
  X_OR3 \U1/Channel1<14>_MC.D2_2072  (
    .I0(\U1/Channel1<14>_MC.D2_PT_0 ),
    .I1(\U1/Channel1<14>_MC.D2_PT_1 ),
    .I2(\U1/Channel1<14>_MC.D2_PT_2 ),
    .O(\U1/Channel1<14>_MC.D2 )
  );
  X_BUF \outDATA<6>\$WA2.UIM_2073  (
    .I(\outDATA<6>\$WA2.UIM_MC.Q ),
    .O(\outDATA<6>\$WA2.UIM )
  );
  X_BUF \outDATA<6>\$WA2.UIM_MC.Q_2074  (
    .I(\outDATA<6>\$WA2.UIM_MC.D ),
    .O(\outDATA<6>\$WA2.UIM_MC.Q )
  );
  X_XOR2 \outDATA<6>\$WA2.UIM_MC.D_2075  (
    .I0(\outDATA<6>\$WA2.UIM_MC.D1 ),
    .I1(\outDATA<6>\$WA2.UIM_MC.D2 ),
    .O(\outDATA<6>\$WA2.UIM_MC.D )
  );
  X_ZERO \outDATA<6>\$WA2.UIM_MC.D1_2076  (
    .O(\outDATA<6>\$WA2.UIM_MC.D1 )
  );
  X_AND2 \outDATA<6>\$WA2.UIM_MC.D2_PT_0_2077  (
    .I0(DCOR0THRESLOWr),
    .I1(\U1/U4/Latch0r [6]),
    .O(\outDATA<6>\$WA2.UIM_MC.D2_PT_0 )
  );
  X_AND3 \outDATA<6>\$WA2.UIM_MC.D2_PT_1_2078  (
    .I0(\NlwInverterSignal_outDATA<6>\$WA2.UIM_MC.D2_PT_1/IN0 ),
    .I1(DCORIFGr),
    .I2(NET2512),
    .O(\outDATA<6>\$WA2.UIM_MC.D2_PT_1 )
  );
  X_AND4 \outDATA<6>\$WA2.UIM_MC.D2_PT_2_2079  (
    .I0(\NlwInverterSignal_outDATA<6>\$WA2.UIM_MC.D2_PT_2/IN0 ),
    .I1(\NlwInverterSignal_outDATA<6>\$WA2.UIM_MC.D2_PT_2/IN1 ),
    .I2(DCOR0THRESHIGHr),
    .I3(\U1/U4/Latch0r [14]),
    .O(\outDATA<6>\$WA2.UIM_MC.D2_PT_2 )
  );
  X_AND5 \outDATA<6>\$WA2.UIM_MC.D2_PT_3_2080  (
    .I0(\NlwInverterSignal_outDATA<6>\$WA2.UIM_MC.D2_PT_3/IN0 ),
    .I1(\NlwInverterSignal_outDATA<6>\$WA2.UIM_MC.D2_PT_3/IN1 ),
    .I2(\NlwInverterSignal_outDATA<6>\$WA2.UIM_MC.D2_PT_3/IN2 ),
    .I3(DCOR1THRESLOWr),
    .I4(\U1/U4/Latch1r [6]),
    .O(\outDATA<6>\$WA2.UIM_MC.D2_PT_3 )
  );
  X_AND5 \outDATA<6>\$WA2.UIM_MC.D2_PT_4_2081  (
    .I0(\NlwInverterSignal_outDATA<6>\$WA2.UIM_MC.D2_PT_4/IN0 ),
    .I1(\NlwInverterSignal_outDATA<6>\$WA2.UIM_MC.D2_PT_4/IN1 ),
    .I2(\NlwInverterSignal_outDATA<6>\$WA2.UIM_MC.D2_PT_4/IN2 ),
    .I3(\NlwInverterSignal_outDATA<6>\$WA2.UIM_MC.D2_PT_4/IN3 ),
    .I4(\U1/U4/Latch1r [14]),
    .O(\outDATA<6>\$WA2.UIM_MC.D2_PT_4 )
  );
  X_OR5 \outDATA<6>\$WA2.UIM_MC.D2_2082  (
    .I0(\outDATA<6>\$WA2.UIM_MC.D2_PT_0 ),
    .I1(\outDATA<6>\$WA2.UIM_MC.D2_PT_1 ),
    .I2(\outDATA<6>\$WA2.UIM_MC.D2_PT_2 ),
    .I3(\outDATA<6>\$WA2.UIM_MC.D2_PT_3 ),
    .I4(\outDATA<6>\$WA2.UIM_MC.D2_PT_4 ),
    .O(\outDATA<6>\$WA2.UIM_MC.D2 )
  );
  X_BUF \U1/U4/Latch0r<6>  (
    .I(\U1/U4/Latch0r<6>_MC.Q ),
    .O(\U1/U4/Latch0r [6])
  );
  X_FF \U1/U4/Latch0r<6>_MC.REG  (
    .I(\U1/U4/Latch0r<6>_MC.D ),
    .CE(Vcc),
    .CLK(\U1/U4/Latch0r<6>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\U1/U4/Latch0r<6>_MC.Q )
  );
  X_INV \U1/U4/Latch0r<6>_MC.REG_tsimcreated_inv_Mclk_II/FCLK_2083  (
    .I(\Mclk_II/FCLK ),
    .O(\U1/U4/Latch0r<6>_MC.REG_tsimcreated_inv_Mclk_II/FCLK )
  );
  X_XOR2 \U1/U4/Latch0r<6>_MC.D_2084  (
    .I0(\U1/U4/Latch0r<6>_MC.D1 ),
    .I1(\U1/U4/Latch0r<6>_MC.D2 ),
    .O(\U1/U4/Latch0r<6>_MC.D )
  );
  X_ZERO \U1/U4/Latch0r<6>_MC.D1_2085  (
    .O(\U1/U4/Latch0r<6>_MC.D1 )
  );
  X_AND3 \U1/U4/Latch0r<6>_MC.D2_PT_0_2086  (
    .I0(\MSPReset_II/UIM ),
    .I1(N_PZ_1018),
    .I2(\U1/Channel0 [6]),
    .O(\U1/U4/Latch0r<6>_MC.D2_PT_0 )
  );
  X_AND3 \U1/U4/Latch0r<6>_MC.D2_PT_1_2087  (
    .I0(\MSPReset_II/UIM ),
    .I1(\NlwInverterSignal_U1/U4/Latch0r<6>_MC.D2_PT_1/IN1 ),
    .I2(\U1/U4/Latch0r [6]),
    .O(\U1/U4/Latch0r<6>_MC.D2_PT_1 )
  );
  X_OR2 \U1/U4/Latch0r<6>_MC.D2_2088  (
    .I0(\U1/U4/Latch0r<6>_MC.D2_PT_0 ),
    .I1(\U1/U4/Latch0r<6>_MC.D2_PT_1 ),
    .O(\U1/U4/Latch0r<6>_MC.D2 )
  );
  X_BUF \U1/U4/Latch0r<14>  (
    .I(\U1/U4/Latch0r<14>_MC.Q ),
    .O(\U1/U4/Latch0r [14])
  );
  X_FF \U1/U4/Latch0r<14>_MC.REG  (
    .I(\U1/U4/Latch0r<14>_MC.D ),
    .CE(Vcc),
    .CLK(\U1/U4/Latch0r<14>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\U1/U4/Latch0r<14>_MC.Q )
  );
  X_INV \U1/U4/Latch0r<14>_MC.REG_tsimcreated_inv_Mclk_II/FCLK_2089  (
    .I(\Mclk_II/FCLK ),
    .O(\U1/U4/Latch0r<14>_MC.REG_tsimcreated_inv_Mclk_II/FCLK )
  );
  X_XOR2 \U1/U4/Latch0r<14>_MC.D_2090  (
    .I0(\U1/U4/Latch0r<14>_MC.D1 ),
    .I1(\U1/U4/Latch0r<14>_MC.D2 ),
    .O(\U1/U4/Latch0r<14>_MC.D )
  );
  X_ZERO \U1/U4/Latch0r<14>_MC.D1_2091  (
    .O(\U1/U4/Latch0r<14>_MC.D1 )
  );
  X_AND3 \U1/U4/Latch0r<14>_MC.D2_PT_0_2092  (
    .I0(\MSPReset_II/UIM ),
    .I1(N_PZ_1018),
    .I2(\U1/Channel0 [14]),
    .O(\U1/U4/Latch0r<14>_MC.D2_PT_0 )
  );
  X_AND3 \U1/U4/Latch0r<14>_MC.D2_PT_1_2093  (
    .I0(\MSPReset_II/UIM ),
    .I1(\NlwInverterSignal_U1/U4/Latch0r<14>_MC.D2_PT_1/IN1 ),
    .I2(\U1/U4/Latch0r [14]),
    .O(\U1/U4/Latch0r<14>_MC.D2_PT_1 )
  );
  X_OR2 \U1/U4/Latch0r<14>_MC.D2_2094  (
    .I0(\U1/U4/Latch0r<14>_MC.D2_PT_0 ),
    .I1(\U1/U4/Latch0r<14>_MC.D2_PT_1 ),
    .O(\U1/U4/Latch0r<14>_MC.D2 )
  );
  X_BUF \U1/U4/Latch1r<6>  (
    .I(\U1/U4/Latch1r<6>_MC.Q ),
    .O(\U1/U4/Latch1r [6])
  );
  X_FF \U1/U4/Latch1r<6>_MC.REG  (
    .I(\U1/U4/Latch1r<6>_MC.D ),
    .CE(Vcc),
    .CLK(\U1/U4/Latch1r<6>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\U1/U4/Latch1r<6>_MC.Q )
  );
  X_INV \U1/U4/Latch1r<6>_MC.REG_tsimcreated_inv_Mclk_II/FCLK_2095  (
    .I(\Mclk_II/FCLK ),
    .O(\U1/U4/Latch1r<6>_MC.REG_tsimcreated_inv_Mclk_II/FCLK )
  );
  X_XOR2 \U1/U4/Latch1r<6>_MC.D_2096  (
    .I0(\U1/U4/Latch1r<6>_MC.D1 ),
    .I1(\U1/U4/Latch1r<6>_MC.D2 ),
    .O(\U1/U4/Latch1r<6>_MC.D )
  );
  X_ZERO \U1/U4/Latch1r<6>_MC.D1_2097  (
    .O(\U1/U4/Latch1r<6>_MC.D1 )
  );
  X_AND3 \U1/U4/Latch1r<6>_MC.D2_PT_0_2098  (
    .I0(\MSPReset_II/UIM ),
    .I1(N_PZ_1019),
    .I2(\U1/Channel1 [6]),
    .O(\U1/U4/Latch1r<6>_MC.D2_PT_0 )
  );
  X_AND3 \U1/U4/Latch1r<6>_MC.D2_PT_1_2099  (
    .I0(\MSPReset_II/UIM ),
    .I1(\NlwInverterSignal_U1/U4/Latch1r<6>_MC.D2_PT_1/IN1 ),
    .I2(\U1/U4/Latch1r [6]),
    .O(\U1/U4/Latch1r<6>_MC.D2_PT_1 )
  );
  X_OR2 \U1/U4/Latch1r<6>_MC.D2_2100  (
    .I0(\U1/U4/Latch1r<6>_MC.D2_PT_0 ),
    .I1(\U1/U4/Latch1r<6>_MC.D2_PT_1 ),
    .O(\U1/U4/Latch1r<6>_MC.D2 )
  );
  X_BUF \U1/U4/Latch1r<14>  (
    .I(\U1/U4/Latch1r<14>_MC.Q ),
    .O(\U1/U4/Latch1r [14])
  );
  X_FF \U1/U4/Latch1r<14>_MC.REG  (
    .I(\U1/U4/Latch1r<14>_MC.D ),
    .CE(Vcc),
    .CLK(\U1/U4/Latch1r<14>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\U1/U4/Latch1r<14>_MC.Q )
  );
  X_INV \U1/U4/Latch1r<14>_MC.REG_tsimcreated_inv_Mclk_II/FCLK_2101  (
    .I(\Mclk_II/FCLK ),
    .O(\U1/U4/Latch1r<14>_MC.REG_tsimcreated_inv_Mclk_II/FCLK )
  );
  X_XOR2 \U1/U4/Latch1r<14>_MC.D_2102  (
    .I0(\U1/U4/Latch1r<14>_MC.D1 ),
    .I1(\U1/U4/Latch1r<14>_MC.D2 ),
    .O(\U1/U4/Latch1r<14>_MC.D )
  );
  X_ZERO \U1/U4/Latch1r<14>_MC.D1_2103  (
    .O(\U1/U4/Latch1r<14>_MC.D1 )
  );
  X_AND3 \U1/U4/Latch1r<14>_MC.D2_PT_0_2104  (
    .I0(\MSPReset_II/UIM ),
    .I1(N_PZ_1019),
    .I2(\U1/Channel1 [14]),
    .O(\U1/U4/Latch1r<14>_MC.D2_PT_0 )
  );
  X_AND3 \U1/U4/Latch1r<14>_MC.D2_PT_1_2105  (
    .I0(\MSPReset_II/UIM ),
    .I1(\NlwInverterSignal_U1/U4/Latch1r<14>_MC.D2_PT_1/IN1 ),
    .I2(\U1/U4/Latch1r [14]),
    .O(\U1/U4/Latch1r<14>_MC.D2_PT_1 )
  );
  X_OR2 \U1/U4/Latch1r<14>_MC.D2_2106  (
    .I0(\U1/U4/Latch1r<14>_MC.D2_PT_0 ),
    .I1(\U1/U4/Latch1r<14>_MC.D2_PT_1 ),
    .O(\U1/U4/Latch1r<14>_MC.D2 )
  );
  X_BUF \outDATA<7>\$WA0.UIM_2107  (
    .I(\outDATA<7>\$WA0.UIM_MC.Q ),
    .O(\outDATA<7>\$WA0.UIM )
  );
  X_BUF \outDATA<7>\$WA0.UIM_MC.Q_2108  (
    .I(\outDATA<7>\$WA0.UIM_MC.D ),
    .O(\outDATA<7>\$WA0.UIM_MC.Q )
  );
  X_XOR2 \outDATA<7>\$WA0.UIM_MC.D_2109  (
    .I0(\outDATA<7>\$WA0.UIM_MC.D1 ),
    .I1(\outDATA<7>\$WA0.UIM_MC.D2 ),
    .O(\outDATA<7>\$WA0.UIM_MC.D )
  );
  X_ZERO \outDATA<7>\$WA0.UIM_MC.D1_2110  (
    .O(\outDATA<7>\$WA0.UIM_MC.D1 )
  );
  X_ZERO \outDATA<7>\$WA0.UIM_MC.D2_2111  (
    .O(\outDATA<7>\$WA0.UIM_MC.D2 )
  );
  X_BUF \outDATA<7>\$WA2.UIM_2112  (
    .I(\outDATA<7>\$WA2.UIM_MC.Q ),
    .O(\outDATA<7>\$WA2.UIM )
  );
  X_BUF \outDATA<7>\$WA2.UIM_MC.Q_2113  (
    .I(\outDATA<7>\$WA2.UIM_MC.D ),
    .O(\outDATA<7>\$WA2.UIM_MC.Q )
  );
  X_XOR2 \outDATA<7>\$WA2.UIM_MC.D_2114  (
    .I0(\outDATA<7>\$WA2.UIM_MC.D1 ),
    .I1(\outDATA<7>\$WA2.UIM_MC.D2 ),
    .O(\outDATA<7>\$WA2.UIM_MC.D )
  );
  X_ZERO \outDATA<7>\$WA2.UIM_MC.D1_2115  (
    .O(\outDATA<7>\$WA2.UIM_MC.D1 )
  );
  X_AND2 \outDATA<7>\$WA2.UIM_MC.D2_PT_0_2116  (
    .I0(DCOR0THRESLOWr),
    .I1(\U1/U4/Latch0r [7]),
    .O(\outDATA<7>\$WA2.UIM_MC.D2_PT_0 )
  );
  X_AND3 \outDATA<7>\$WA2.UIM_MC.D2_PT_1_2117  (
    .I0(\NlwInverterSignal_outDATA<7>\$WA2.UIM_MC.D2_PT_1/IN0 ),
    .I1(DCOR0THRESHIGHr),
    .I2(\U1/U4/Latch0r [15]),
    .O(\outDATA<7>\$WA2.UIM_MC.D2_PT_1 )
  );
  X_AND4 \outDATA<7>\$WA2.UIM_MC.D2_PT_2_2118  (
    .I0(\NlwInverterSignal_outDATA<7>\$WA2.UIM_MC.D2_PT_2/IN0 ),
    .I1(\NlwInverterSignal_outDATA<7>\$WA2.UIM_MC.D2_PT_2/IN1 ),
    .I2(DCOR1THRESLOWr),
    .I3(\U1/U4/Latch1r [7]),
    .O(\outDATA<7>\$WA2.UIM_MC.D2_PT_2 )
  );
  X_AND4 \outDATA<7>\$WA2.UIM_MC.D2_PT_3_2119  (
    .I0(\NlwInverterSignal_outDATA<7>\$WA2.UIM_MC.D2_PT_3/IN0 ),
    .I1(\NlwInverterSignal_outDATA<7>\$WA2.UIM_MC.D2_PT_3/IN1 ),
    .I2(\NlwInverterSignal_outDATA<7>\$WA2.UIM_MC.D2_PT_3/IN2 ),
    .I3(\U1/U4/Latch1r [15]),
    .O(\outDATA<7>\$WA2.UIM_MC.D2_PT_3 )
  );
  X_OR4 \outDATA<7>\$WA2.UIM_MC.D2_2120  (
    .I0(\outDATA<7>\$WA2.UIM_MC.D2_PT_0 ),
    .I1(\outDATA<7>\$WA2.UIM_MC.D2_PT_1 ),
    .I2(\outDATA<7>\$WA2.UIM_MC.D2_PT_2 ),
    .I3(\outDATA<7>\$WA2.UIM_MC.D2_PT_3 ),
    .O(\outDATA<7>\$WA2.UIM_MC.D2 )
  );
  X_BUF \U1/U4/Latch0r<7>  (
    .I(\U1/U4/Latch0r<7>_MC.Q ),
    .O(\U1/U4/Latch0r [7])
  );
  X_FF \U1/U4/Latch0r<7>_MC.REG  (
    .I(\U1/U4/Latch0r<7>_MC.D ),
    .CE(Vcc),
    .CLK(\U1/U4/Latch0r<7>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\U1/U4/Latch0r<7>_MC.Q )
  );
  X_INV \U1/U4/Latch0r<7>_MC.REG_tsimcreated_inv_Mclk_II/FCLK_2121  (
    .I(\Mclk_II/FCLK ),
    .O(\U1/U4/Latch0r<7>_MC.REG_tsimcreated_inv_Mclk_II/FCLK )
  );
  X_XOR2 \U1/U4/Latch0r<7>_MC.D_2122  (
    .I0(\U1/U4/Latch0r<7>_MC.D1 ),
    .I1(\U1/U4/Latch0r<7>_MC.D2 ),
    .O(\U1/U4/Latch0r<7>_MC.D )
  );
  X_ZERO \U1/U4/Latch0r<7>_MC.D1_2123  (
    .O(\U1/U4/Latch0r<7>_MC.D1 )
  );
  X_AND3 \U1/U4/Latch0r<7>_MC.D2_PT_0_2124  (
    .I0(\MSPReset_II/UIM ),
    .I1(N_PZ_1018),
    .I2(\U1/Channel0 [7]),
    .O(\U1/U4/Latch0r<7>_MC.D2_PT_0 )
  );
  X_AND3 \U1/U4/Latch0r<7>_MC.D2_PT_1_2125  (
    .I0(\MSPReset_II/UIM ),
    .I1(\NlwInverterSignal_U1/U4/Latch0r<7>_MC.D2_PT_1/IN1 ),
    .I2(\U1/U4/Latch0r [7]),
    .O(\U1/U4/Latch0r<7>_MC.D2_PT_1 )
  );
  X_OR2 \U1/U4/Latch0r<7>_MC.D2_2126  (
    .I0(\U1/U4/Latch0r<7>_MC.D2_PT_0 ),
    .I1(\U1/U4/Latch0r<7>_MC.D2_PT_1 ),
    .O(\U1/U4/Latch0r<7>_MC.D2 )
  );
  X_BUF \U1/U4/Latch0r<15>  (
    .I(\U1/U4/Latch0r<15>_MC.Q ),
    .O(\U1/U4/Latch0r [15])
  );
  X_FF \U1/U4/Latch0r<15>_MC.REG  (
    .I(\U1/U4/Latch0r<15>_MC.D ),
    .CE(Vcc),
    .CLK(\U1/U4/Latch0r<15>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\U1/U4/Latch0r<15>_MC.Q )
  );
  X_INV \U1/U4/Latch0r<15>_MC.REG_tsimcreated_inv_Mclk_II/FCLK_2127  (
    .I(\Mclk_II/FCLK ),
    .O(\U1/U4/Latch0r<15>_MC.REG_tsimcreated_inv_Mclk_II/FCLK )
  );
  X_XOR2 \U1/U4/Latch0r<15>_MC.D_2128  (
    .I0(\U1/U4/Latch0r<15>_MC.D1 ),
    .I1(\U1/U4/Latch0r<15>_MC.D2 ),
    .O(\U1/U4/Latch0r<15>_MC.D )
  );
  X_ZERO \U1/U4/Latch0r<15>_MC.D1_2129  (
    .O(\U1/U4/Latch0r<15>_MC.D1 )
  );
  X_AND3 \U1/U4/Latch0r<15>_MC.D2_PT_0_2130  (
    .I0(\MSPReset_II/UIM ),
    .I1(N_PZ_1018),
    .I2(\U1/Channel0 [15]),
    .O(\U1/U4/Latch0r<15>_MC.D2_PT_0 )
  );
  X_AND3 \U1/U4/Latch0r<15>_MC.D2_PT_1_2131  (
    .I0(\MSPReset_II/UIM ),
    .I1(\NlwInverterSignal_U1/U4/Latch0r<15>_MC.D2_PT_1/IN1 ),
    .I2(\U1/U4/Latch0r [15]),
    .O(\U1/U4/Latch0r<15>_MC.D2_PT_1 )
  );
  X_OR2 \U1/U4/Latch0r<15>_MC.D2_2132  (
    .I0(\U1/U4/Latch0r<15>_MC.D2_PT_0 ),
    .I1(\U1/U4/Latch0r<15>_MC.D2_PT_1 ),
    .O(\U1/U4/Latch0r<15>_MC.D2 )
  );
  X_BUF \U1/Channel0<15>  (
    .I(\U1/Channel0<15>_MC.Q ),
    .O(\U1/Channel0 [15])
  );
  X_XOR2 \U1/Channel0<15>_MC_tsimcreated_xor__2133  (
    .I0(\U1/Channel0<15>_MC.D ),
    .I1(\U1/Channel0<15>_MC.Q ),
    .O(\U1/Channel0<15>_MC_tsimcreated_xor_ )
  );
  X_FF \U1/Channel0<15>_MC.REG  (
    .I(\U1/Channel0<15>_MC_tsimcreated_xor_ ),
    .CE(Vcc),
    .CLK(\Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\U1/Channel0<15>_MC.Q )
  );
  X_XOR2 \U1/Channel0<15>_MC.D_2134  (
    .I0(\U1/Channel0<15>_MC.D1 ),
    .I1(\U1/Channel0<15>_MC.D2 ),
    .O(\U1/Channel0<15>_MC.D )
  );
  X_ZERO \U1/Channel0<15>_MC.D1_2135  (
    .O(\U1/Channel0<15>_MC.D1 )
  );
  X_AND2 \U1/Channel0<15>_MC.D2_PT_0_2136  (
    .I0(\NlwInverterSignal_U1/Channel0<15>_MC.D2_PT_0/IN0 ),
    .I1(\U1/Channel0 [15]),
    .O(\U1/Channel0<15>_MC.D2_PT_0 )
  );
  X_AND8 \U1/Channel0<15>_MC.D2_PT_1_2137  (
    .I0(\U1/U2/location_Maddsub__n0000__n0075 [0]),
    .I1(N_PZ_1021),
    .I2(\NlwInverterSignal_U1/Channel0<15>_MC.D2_PT_1/IN2 ),
    .I3(\NlwInverterSignal_U1/Channel0<15>_MC.D2_PT_1/IN3 ),
    .I4(\NlwInverterSignal_U1/Channel0<15>_MC.D2_PT_1/IN4 ),
    .I5(\NlwInverterSignal_U1/Channel0<15>_MC.D2_PT_1/IN5 ),
    .I6(\NlwInverterSignal_U1/Channel0<15>_MC.D2_PT_1/IN6 ),
    .I7(\NlwInverterSignal_U1/Channel0<15>_MC.D2_PT_1/IN7 ),
    .O(\U1/Channel0<15>_MC.D2_PT_1 )
  );
  X_AND8 \U1/Channel0<15>_MC.D2_PT_2_2138  (
    .I0(\NlwInverterSignal_U1/Channel0<15>_MC.D2_PT_2/IN0 ),
    .I1(N_PZ_1024),
    .I2(\U1/Channel0 [9]),
    .I3(\U1/Channel0 [12]),
    .I4(\U1/Channel0 [10]),
    .I5(\U1/Channel0 [11]),
    .I6(\U1/Channel0 [13]),
    .I7(\U1/Channel0 [14]),
    .O(\U1/Channel0<15>_MC.D2_PT_2 )
  );
  X_OR3 \U1/Channel0<15>_MC.D2_2139  (
    .I0(\U1/Channel0<15>_MC.D2_PT_0 ),
    .I1(\U1/Channel0<15>_MC.D2_PT_1 ),
    .I2(\U1/Channel0<15>_MC.D2_PT_2 ),
    .O(\U1/Channel0<15>_MC.D2 )
  );
  X_BUF \U1/U4/Latch1r<7>  (
    .I(\U1/U4/Latch1r<7>_MC.Q ),
    .O(\U1/U4/Latch1r [7])
  );
  X_FF \U1/U4/Latch1r<7>_MC.REG  (
    .I(\U1/U4/Latch1r<7>_MC.D ),
    .CE(Vcc),
    .CLK(\U1/U4/Latch1r<7>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\U1/U4/Latch1r<7>_MC.Q )
  );
  X_INV \U1/U4/Latch1r<7>_MC.REG_tsimcreated_inv_Mclk_II/FCLK_2140  (
    .I(\Mclk_II/FCLK ),
    .O(\U1/U4/Latch1r<7>_MC.REG_tsimcreated_inv_Mclk_II/FCLK )
  );
  X_XOR2 \U1/U4/Latch1r<7>_MC.D_2141  (
    .I0(\U1/U4/Latch1r<7>_MC.D1 ),
    .I1(\U1/U4/Latch1r<7>_MC.D2 ),
    .O(\U1/U4/Latch1r<7>_MC.D )
  );
  X_ZERO \U1/U4/Latch1r<7>_MC.D1_2142  (
    .O(\U1/U4/Latch1r<7>_MC.D1 )
  );
  X_AND3 \U1/U4/Latch1r<7>_MC.D2_PT_0_2143  (
    .I0(\MSPReset_II/UIM ),
    .I1(N_PZ_1019),
    .I2(\U1/Channel1 [7]),
    .O(\U1/U4/Latch1r<7>_MC.D2_PT_0 )
  );
  X_AND3 \U1/U4/Latch1r<7>_MC.D2_PT_1_2144  (
    .I0(\MSPReset_II/UIM ),
    .I1(\NlwInverterSignal_U1/U4/Latch1r<7>_MC.D2_PT_1/IN1 ),
    .I2(\U1/U4/Latch1r [7]),
    .O(\U1/U4/Latch1r<7>_MC.D2_PT_1 )
  );
  X_OR2 \U1/U4/Latch1r<7>_MC.D2_2145  (
    .I0(\U1/U4/Latch1r<7>_MC.D2_PT_0 ),
    .I1(\U1/U4/Latch1r<7>_MC.D2_PT_1 ),
    .O(\U1/U4/Latch1r<7>_MC.D2 )
  );
  X_BUF \U1/U4/Latch1r<15>  (
    .I(\U1/U4/Latch1r<15>_MC.Q ),
    .O(\U1/U4/Latch1r [15])
  );
  X_FF \U1/U4/Latch1r<15>_MC.REG  (
    .I(\U1/U4/Latch1r<15>_MC.D ),
    .CE(Vcc),
    .CLK(\U1/U4/Latch1r<15>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\U1/U4/Latch1r<15>_MC.Q )
  );
  X_INV \U1/U4/Latch1r<15>_MC.REG_tsimcreated_inv_Mclk_II/FCLK_2146  (
    .I(\Mclk_II/FCLK ),
    .O(\U1/U4/Latch1r<15>_MC.REG_tsimcreated_inv_Mclk_II/FCLK )
  );
  X_XOR2 \U1/U4/Latch1r<15>_MC.D_2147  (
    .I0(\U1/U4/Latch1r<15>_MC.D1 ),
    .I1(\U1/U4/Latch1r<15>_MC.D2 ),
    .O(\U1/U4/Latch1r<15>_MC.D )
  );
  X_ZERO \U1/U4/Latch1r<15>_MC.D1_2148  (
    .O(\U1/U4/Latch1r<15>_MC.D1 )
  );
  X_AND3 \U1/U4/Latch1r<15>_MC.D2_PT_0_2149  (
    .I0(\MSPReset_II/UIM ),
    .I1(N_PZ_1019),
    .I2(\U1/Channel1 [15]),
    .O(\U1/U4/Latch1r<15>_MC.D2_PT_0 )
  );
  X_AND3 \U1/U4/Latch1r<15>_MC.D2_PT_1_2150  (
    .I0(\MSPReset_II/UIM ),
    .I1(\NlwInverterSignal_U1/U4/Latch1r<15>_MC.D2_PT_1/IN1 ),
    .I2(\U1/U4/Latch1r [15]),
    .O(\U1/U4/Latch1r<15>_MC.D2_PT_1 )
  );
  X_OR2 \U1/U4/Latch1r<15>_MC.D2_2151  (
    .I0(\U1/U4/Latch1r<15>_MC.D2_PT_0 ),
    .I1(\U1/U4/Latch1r<15>_MC.D2_PT_1 ),
    .O(\U1/U4/Latch1r<15>_MC.D2 )
  );
  X_BUF \U1/Channel1<15>  (
    .I(\U1/Channel1<15>_MC.Q ),
    .O(\U1/Channel1 [15])
  );
  X_XOR2 \U1/Channel1<15>_MC_tsimcreated_xor__2152  (
    .I0(\U1/Channel1<15>_MC.D ),
    .I1(\U1/Channel1<15>_MC.Q ),
    .O(\U1/Channel1<15>_MC_tsimcreated_xor_ )
  );
  X_FF \U1/Channel1<15>_MC.REG  (
    .I(\U1/Channel1<15>_MC_tsimcreated_xor_ ),
    .CE(Vcc),
    .CLK(\Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\U1/Channel1<15>_MC.Q )
  );
  X_XOR2 \U1/Channel1<15>_MC.D_2153  (
    .I0(\U1/Channel1<15>_MC.D1 ),
    .I1(\U1/Channel1<15>_MC.D2 ),
    .O(\U1/Channel1<15>_MC.D )
  );
  X_ZERO \U1/Channel1<15>_MC.D1_2154  (
    .O(\U1/Channel1<15>_MC.D1 )
  );
  X_AND2 \U1/Channel1<15>_MC.D2_PT_0_2155  (
    .I0(\NlwInverterSignal_U1/Channel1<15>_MC.D2_PT_0/IN0 ),
    .I1(\U1/Channel1 [15]),
    .O(\U1/Channel1<15>_MC.D2_PT_0 )
  );
  X_AND16 \U1/Channel1<15>_MC.D2_PT_1_2156  (
    .I0(\MSPReset_II/UIM ),
    .I1(\NlwInverterSignal_U1/Channel1<15>_MC.D2_PT_1/IN1 ),
    .I2(\U1/U6/CurrState_Sreg0_FFD3 ),
    .I3(\NlwInverterSignal_U1/Channel1<15>_MC.D2_PT_1/IN3 ),
    .I4(N_PZ_975),
    .I5(\NlwInverterSignal_U1/Channel1<15>_MC.D2_PT_1/IN5 ),
    .I6(\U1/Channel1 [9]),
    .I7(\U1/Channel1 [12]),
    .I8(\U1/Channel1 [10]),
    .I9(\U1/Channel1 [11]),
    .I10(\U1/Channel1 [13]),
    .I11(\U1/Channel1 [14]),
    .I12(Vcc),
    .I13(Vcc),
    .I14(Vcc),
    .I15(Vcc),
    .O(\U1/Channel1<15>_MC.D2_PT_1 )
  );
  X_AND16 \U1/Channel1<15>_MC.D2_PT_2_2157  (
    .I0(\MSPReset_II/UIM ),
    .I1(\NlwInverterSignal_U1/Channel1<15>_MC.D2_PT_2/IN1 ),
    .I2(\U1/U6/CurrState_Sreg0_FFD3 ),
    .I3(\NlwInverterSignal_U1/Channel1<15>_MC.D2_PT_2/IN3 ),
    .I4(N_PZ_1154),
    .I5(\NlwInverterSignal_U1/Channel1<15>_MC.D2_PT_2/IN5 ),
    .I6(\U1/U5/location_Maddsub__n0000__n0075 [0]),
    .I7(\NlwInverterSignal_U1/Channel1<15>_MC.D2_PT_2/IN7 ),
    .I8(\NlwInverterSignal_U1/Channel1<15>_MC.D2_PT_2/IN8 ),
    .I9(\NlwInverterSignal_U1/Channel1<15>_MC.D2_PT_2/IN9 ),
    .I10(\NlwInverterSignal_U1/Channel1<15>_MC.D2_PT_2/IN10 ),
    .I11(\NlwInverterSignal_U1/Channel1<15>_MC.D2_PT_2/IN11 ),
    .I12(\NlwInverterSignal_U1/Channel1<15>_MC.D2_PT_2/IN12 ),
    .I13(Vcc),
    .I14(Vcc),
    .I15(Vcc),
    .O(\U1/Channel1<15>_MC.D2_PT_2 )
  );
  X_OR3 \U1/Channel1<15>_MC.D2_2158  (
    .I0(\U1/Channel1<15>_MC.D2_PT_0 ),
    .I1(\U1/Channel1<15>_MC.D2_PT_1 ),
    .I2(\U1/Channel1<15>_MC.D2_PT_2 ),
    .O(\U1/Channel1<15>_MC.D2 )
  );
  X_BUF \outDATA<7>\$WA5.UIM_2159  (
    .I(\outDATA<7>\$WA5.UIM_MC.Q ),
    .O(\outDATA<7>\$WA5.UIM )
  );
  X_BUF \outDATA<7>\$WA5.UIM_MC.Q_2160  (
    .I(\outDATA<7>\$WA5.UIM_MC.D ),
    .O(\outDATA<7>\$WA5.UIM_MC.Q )
  );
  X_XOR2 \outDATA<7>\$WA5.UIM_MC.D_2161  (
    .I0(\outDATA<7>\$WA5.UIM_MC.D1 ),
    .I1(\outDATA<7>\$WA5.UIM_MC.D2 ),
    .O(\outDATA<7>\$WA5.UIM_MC.D )
  );
  X_ZERO \outDATA<7>\$WA5.UIM_MC.D1_2162  (
    .O(\outDATA<7>\$WA5.UIM_MC.D1 )
  );
  X_AND2 \outDATA<7>\$WA5.UIM_MC.D2_PT_0_2163  (
    .I0(NET2528),
    .I1(\U4/Flgreg [7]),
    .O(\outDATA<7>\$WA5.UIM_MC.D2_PT_0 )
  );
  X_AND2 \outDATA<7>\$WA5.UIM_MC.D2_PT_1_2164  (
    .I0(\NlwInverterSignal_outDATA<7>\$WA5.UIM_MC.D2_PT_1/IN0 ),
    .I1(\Enc15FLG_II/UIM ),
    .O(\outDATA<7>\$WA5.UIM_MC.D2_PT_1 )
  );
  X_OR2 \outDATA<7>\$WA5.UIM_MC.D2_2165  (
    .I0(\outDATA<7>\$WA5.UIM_MC.D2_PT_0 ),
    .I1(\outDATA<7>\$WA5.UIM_MC.D2_PT_1 ),
    .O(\outDATA<7>\$WA5.UIM_MC.D2 )
  );
  X_BUF \outDATA<7>\$WA4.UIM_2166  (
    .I(\outDATA<7>\$WA4.UIM_MC.Q ),
    .O(\outDATA<7>\$WA4.UIM )
  );
  X_BUF \outDATA<7>\$WA4.UIM_MC.Q_2167  (
    .I(\outDATA<7>\$WA4.UIM_MC.D ),
    .O(\outDATA<7>\$WA4.UIM_MC.Q )
  );
  X_XOR2 \outDATA<7>\$WA4.UIM_MC.D_2168  (
    .I0(\outDATA<7>\$WA4.UIM_MC.D1 ),
    .I1(\outDATA<7>\$WA4.UIM_MC.D2 ),
    .O(\outDATA<7>\$WA4.UIM_MC.D )
  );
  X_AND2 \outDATA<7>\$WA4.UIM_MC.D1_2169  (
    .I0(NET3253),
    .I1(NET3253),
    .O(\outDATA<7>\$WA4.UIM_MC.D1 )
  );
  X_ZERO \outDATA<7>\$WA4.UIM_MC.D2_2170  (
    .O(\outDATA<7>\$WA4.UIM_MC.D2 )
  );
  X_BUF \outDATA<7>\$WA1.UIM_2171  (
    .I(\outDATA<7>\$WA1.UIM_MC.Q ),
    .O(\outDATA<7>\$WA1.UIM )
  );
  X_BUF \outDATA<7>\$WA1.UIM_MC.Q_2172  (
    .I(\outDATA<7>\$WA1.UIM_MC.D ),
    .O(\outDATA<7>\$WA1.UIM_MC.Q )
  );
  X_XOR2 \outDATA<7>\$WA1.UIM_MC.D_2173  (
    .I0(\outDATA<7>\$WA1.UIM_MC.D1 ),
    .I1(\outDATA<7>\$WA1.UIM_MC.D2 ),
    .O(\outDATA<7>\$WA1.UIM_MC.D )
  );
  X_ZERO \outDATA<7>\$WA1.UIM_MC.D1_2174  (
    .O(\outDATA<7>\$WA1.UIM_MC.D1 )
  );
  X_AND2 \outDATA<7>\$WA1.UIM_MC.D2_PT_0_2175  (
    .I0(DCOR0CNTLOWr),
    .I1(\U1/U3/holdingreg0 [7]),
    .O(\outDATA<7>\$WA1.UIM_MC.D2_PT_0 )
  );
  X_AND3 \outDATA<7>\$WA1.UIM_MC.D2_PT_1_2176  (
    .I0(\NlwInverterSignal_outDATA<7>\$WA1.UIM_MC.D2_PT_1/IN0 ),
    .I1(DCOR1CNTLOWr),
    .I2(\U1/U3/holdingreg1 [7]),
    .O(\outDATA<7>\$WA1.UIM_MC.D2_PT_1 )
  );
  X_AND4 \outDATA<7>\$WA1.UIM_MC.D2_PT_2_2177  (
    .I0(\NlwInverterSignal_outDATA<7>\$WA1.UIM_MC.D2_PT_2/IN0 ),
    .I1(\NlwInverterSignal_outDATA<7>\$WA1.UIM_MC.D2_PT_2/IN1 ),
    .I2(DCOR0CNTHIGHr),
    .I3(\U1/U3/holdingreg0 [15]),
    .O(\outDATA<7>\$WA1.UIM_MC.D2_PT_2 )
  );
  X_AND4 \outDATA<7>\$WA1.UIM_MC.D2_PT_3_2178  (
    .I0(\NlwInverterSignal_outDATA<7>\$WA1.UIM_MC.D2_PT_3/IN0 ),
    .I1(\NlwInverterSignal_outDATA<7>\$WA1.UIM_MC.D2_PT_3/IN1 ),
    .I2(\NlwInverterSignal_outDATA<7>\$WA1.UIM_MC.D2_PT_3/IN2 ),
    .I3(\U1/U3/holdingreg1 [15]),
    .O(\outDATA<7>\$WA1.UIM_MC.D2_PT_3 )
  );
  X_OR4 \outDATA<7>\$WA1.UIM_MC.D2_2179  (
    .I0(\outDATA<7>\$WA1.UIM_MC.D2_PT_0 ),
    .I1(\outDATA<7>\$WA1.UIM_MC.D2_PT_1 ),
    .I2(\outDATA<7>\$WA1.UIM_MC.D2_PT_2 ),
    .I3(\outDATA<7>\$WA1.UIM_MC.D2_PT_3 ),
    .O(\outDATA<7>\$WA1.UIM_MC.D2 )
  );
  X_BUF \U1/U3/holdingreg0<7>  (
    .I(\U1/U3/holdingreg0<7>_MC.Q ),
    .O(\U1/U3/holdingreg0 [7])
  );
  X_FF \U1/U3/holdingreg0<7>_MC.REG  (
    .I(\U1/U3/holdingreg0<7>_MC.D ),
    .CE(Vcc),
    .CLK(\U1/U3/holdingreg0<7>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\U1/U3/holdingreg0<7>_MC.Q )
  );
  X_INV \U1/U3/holdingreg0<7>_MC.REG_tsimcreated_inv_Mclk_II/FCLK_2180  (
    .I(\Mclk_II/FCLK ),
    .O(\U1/U3/holdingreg0<7>_MC.REG_tsimcreated_inv_Mclk_II/FCLK )
  );
  X_XOR2 \U1/U3/holdingreg0<7>_MC.D_2181  (
    .I0(\U1/U3/holdingreg0<7>_MC.D1 ),
    .I1(\U1/U3/holdingreg0<7>_MC.D2 ),
    .O(\U1/U3/holdingreg0<7>_MC.D )
  );
  X_ZERO \U1/U3/holdingreg0<7>_MC.D1_2182  (
    .O(\U1/U3/holdingreg0<7>_MC.D1 )
  );
  X_AND2 \U1/U3/holdingreg0<7>_MC.D2_PT_0_2183  (
    .I0(N_PZ_992),
    .I1(\U1/U3/holdingreg0 [7]),
    .O(\U1/U3/holdingreg0<7>_MC.D2_PT_0 )
  );
  X_AND4 \U1/U3/holdingreg0<7>_MC.D2_PT_1_2184  (
    .I0(\MSPReset_II/UIM ),
    .I1(\NlwInverterSignal_U1/U3/holdingreg0<7>_MC.D2_PT_1/IN1 ),
    .I2(U2_ASedge),
    .I3(\U1/Channel0 [7]),
    .O(\U1/U3/holdingreg0<7>_MC.D2_PT_1 )
  );
  X_OR2 \U1/U3/holdingreg0<7>_MC.D2_2185  (
    .I0(\U1/U3/holdingreg0<7>_MC.D2_PT_0 ),
    .I1(\U1/U3/holdingreg0<7>_MC.D2_PT_1 ),
    .O(\U1/U3/holdingreg0<7>_MC.D2 )
  );
  X_BUF \U1/U3/holdingreg1<7>  (
    .I(\U1/U3/holdingreg1<7>_MC.Q ),
    .O(\U1/U3/holdingreg1 [7])
  );
  X_FF \U1/U3/holdingreg1<7>_MC.REG  (
    .I(\U1/U3/holdingreg1<7>_MC.D ),
    .CE(Vcc),
    .CLK(\U1/U3/holdingreg1<7>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\U1/U3/holdingreg1<7>_MC.Q )
  );
  X_INV \U1/U3/holdingreg1<7>_MC.REG_tsimcreated_inv_Mclk_II/FCLK_2186  (
    .I(\Mclk_II/FCLK ),
    .O(\U1/U3/holdingreg1<7>_MC.REG_tsimcreated_inv_Mclk_II/FCLK )
  );
  X_XOR2 \U1/U3/holdingreg1<7>_MC.D_2187  (
    .I0(\U1/U3/holdingreg1<7>_MC.D1 ),
    .I1(\U1/U3/holdingreg1<7>_MC.D2 ),
    .O(\U1/U3/holdingreg1<7>_MC.D )
  );
  X_ZERO \U1/U3/holdingreg1<7>_MC.D1_2188  (
    .O(\U1/U3/holdingreg1<7>_MC.D1 )
  );
  X_AND2 \U1/U3/holdingreg1<7>_MC.D2_PT_0_2189  (
    .I0(N_PZ_992),
    .I1(\U1/U3/holdingreg1 [7]),
    .O(\U1/U3/holdingreg1<7>_MC.D2_PT_0 )
  );
  X_AND4 \U1/U3/holdingreg1<7>_MC.D2_PT_1_2190  (
    .I0(\MSPReset_II/UIM ),
    .I1(\NlwInverterSignal_U1/U3/holdingreg1<7>_MC.D2_PT_1/IN1 ),
    .I2(U2_ASedge),
    .I3(\U1/Channel1 [7]),
    .O(\U1/U3/holdingreg1<7>_MC.D2_PT_1 )
  );
  X_OR2 \U1/U3/holdingreg1<7>_MC.D2_2191  (
    .I0(\U1/U3/holdingreg1<7>_MC.D2_PT_0 ),
    .I1(\U1/U3/holdingreg1<7>_MC.D2_PT_1 ),
    .O(\U1/U3/holdingreg1<7>_MC.D2 )
  );
  X_BUF \U1/U3/holdingreg0<15>  (
    .I(\U1/U3/holdingreg0<15>_MC.Q ),
    .O(\U1/U3/holdingreg0 [15])
  );
  X_FF \U1/U3/holdingreg0<15>_MC.REG  (
    .I(\U1/U3/holdingreg0<15>_MC.D ),
    .CE(Vcc),
    .CLK(\U1/U3/holdingreg0<15>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\U1/U3/holdingreg0<15>_MC.Q )
  );
  X_INV \U1/U3/holdingreg0<15>_MC.REG_tsimcreated_inv_Mclk_II/FCLK_2192  (
    .I(\Mclk_II/FCLK ),
    .O(\U1/U3/holdingreg0<15>_MC.REG_tsimcreated_inv_Mclk_II/FCLK )
  );
  X_XOR2 \U1/U3/holdingreg0<15>_MC.D_2193  (
    .I0(\U1/U3/holdingreg0<15>_MC.D1 ),
    .I1(\U1/U3/holdingreg0<15>_MC.D2 ),
    .O(\U1/U3/holdingreg0<15>_MC.D )
  );
  X_ZERO \U1/U3/holdingreg0<15>_MC.D1_2194  (
    .O(\U1/U3/holdingreg0<15>_MC.D1 )
  );
  X_AND2 \U1/U3/holdingreg0<15>_MC.D2_PT_0_2195  (
    .I0(N_PZ_992),
    .I1(\U1/U3/holdingreg0 [15]),
    .O(\U1/U3/holdingreg0<15>_MC.D2_PT_0 )
  );
  X_AND4 \U1/U3/holdingreg0<15>_MC.D2_PT_1_2196  (
    .I0(\MSPReset_II/UIM ),
    .I1(\NlwInverterSignal_U1/U3/holdingreg0<15>_MC.D2_PT_1/IN1 ),
    .I2(U2_ASedge),
    .I3(\U1/Channel0 [15]),
    .O(\U1/U3/holdingreg0<15>_MC.D2_PT_1 )
  );
  X_OR2 \U1/U3/holdingreg0<15>_MC.D2_2197  (
    .I0(\U1/U3/holdingreg0<15>_MC.D2_PT_0 ),
    .I1(\U1/U3/holdingreg0<15>_MC.D2_PT_1 ),
    .O(\U1/U3/holdingreg0<15>_MC.D2 )
  );
  X_BUF \U1/U3/holdingreg1<15>  (
    .I(\U1/U3/holdingreg1<15>_MC.Q ),
    .O(\U1/U3/holdingreg1 [15])
  );
  X_FF \U1/U3/holdingreg1<15>_MC.REG  (
    .I(\U1/U3/holdingreg1<15>_MC.D ),
    .CE(Vcc),
    .CLK(\U1/U3/holdingreg1<15>_MC.REG_tsimcreated_inv_Mclk_II/FCLK ),
    .SET(Gnd),
    .RST(PRLD),
    .O(\U1/U3/holdingreg1<15>_MC.Q )
  );
  X_INV \U1/U3/holdingreg1<15>_MC.REG_tsimcreated_inv_Mclk_II/FCLK_2198  (
    .I(\Mclk_II/FCLK ),
    .O(\U1/U3/holdingreg1<15>_MC.REG_tsimcreated_inv_Mclk_II/FCLK )
  );
  X_XOR2 \U1/U3/holdingreg1<15>_MC.D_2199  (
    .I0(\U1/U3/holdingreg1<15>_MC.D1 ),
    .I1(\U1/U3/holdingreg1<15>_MC.D2 ),
    .O(\U1/U3/holdingreg1<15>_MC.D )
  );
  X_ZERO \U1/U3/holdingreg1<15>_MC.D1_2200  (
    .O(\U1/U3/holdingreg1<15>_MC.D1 )
  );
  X_AND2 \U1/U3/holdingreg1<15>_MC.D2_PT_0_2201  (
    .I0(N_PZ_992),
    .I1(\U1/U3/holdingreg1 [15]),
    .O(\U1/U3/holdingreg1<15>_MC.D2_PT_0 )
  );
  X_AND4 \U1/U3/holdingreg1<15>_MC.D2_PT_1_2202  (
    .I0(\MSPReset_II/UIM ),
    .I1(\NlwInverterSignal_U1/U3/holdingreg1<15>_MC.D2_PT_1/IN1 ),
    .I2(U2_ASedge),
    .I3(\U1/Channel1 [15]),
    .O(\U1/U3/holdingreg1<15>_MC.D2_PT_1 )
  );
  X_OR2 \U1/U3/holdingreg1<15>_MC.D2_2203  (
    .I0(\U1/U3/holdingreg1<15>_MC.D2_PT_0 ),
    .I1(\U1/U3/holdingreg1<15>_MC.D2_PT_1 ),
    .O(\U1/U3/holdingreg1<15>_MC.D2 )
  );
  X_AND2 \FOOBAR1__ctinst/7_2204  (
    .I0(U2_Enable_AD),
    .I1(U2_Enable_AD),
    .O(\FOOBAR1__ctinst/7 )
  );
  X_AND2 \FOOBAR2__ctinst/7_2205  (
    .I0(\MSPReset_II/UIM ),
    .I1(\MSPReset_II/UIM ),
    .O(\NlwInverterSignal_FOOBAR2__ctinst/7/OUT )
  );
  X_AND2 \FOOBAR3__ctinst/7_2206  (
    .I0(\MReset_II/UIM ),
    .I1(\MReset_II/UIM ),
    .O(\FOOBAR3__ctinst/7 )
  );
  X_AND2 \FOOBAR4__ctinst/0_2207  (
    .I0(\TP12_MC.UIM ),
    .I1(\TP12_MC.UIM ),
    .O(\FOOBAR4__ctinst/0 )
  );
  X_AND2 \FOOBAR6__ctinst/4_2208  (
    .I0(U2_WRRDedge),
    .I1(\NlwInverterSignal_FOOBAR6__ctinst/4/IN1 ),
    .O(\FOOBAR6__ctinst/4 )
  );
  X_AND2 \FOOBAR7__ctinst/0_2209  (
    .I0(\MReset_II/UIM ),
    .I1(\MReset_II/UIM ),
    .O(\FOOBAR7__ctinst/0 )
  );
  X_AND2 \FOOBAR9__ctinst/0_2210  (
    .I0(\MSPReset_II/UIM ),
    .I1(\MSPReset_II/UIM ),
    .O(\NlwInverterSignal_FOOBAR9__ctinst/0/OUT )
  );
  X_AND2 \FOOBAR9__ctinst/4_2211  (
    .I0(DCORENCPWRw),
    .I1(DCORENCPWRw),
    .O(\FOOBAR9__ctinst/4 )
  );
  X_AND2 \FOOBAR10__ctinst/0_2212  (
    .I0(\MSPReset_II/UIM ),
    .I1(\MSPReset_II/UIM ),
    .O(\NlwInverterSignal_FOOBAR10__ctinst/0/OUT )
  );
  X_AND2 \FOOBAR10__ctinst/4_2213  (
    .I0(DCORENCPWRw),
    .I1(DCORENCPWRw),
    .O(\FOOBAR10__ctinst/4 )
  );
  X_AND2 \FOOBAR12__ctinst/0_2214  (
    .I0(\MSPReset_II/UIM ),
    .I1(\MSPReset_II/UIM ),
    .O(\NlwInverterSignal_FOOBAR12__ctinst/0/OUT )
  );
  X_AND2 \FOOBAR12__ctinst/4_2215  (
    .I0(DCORENCPWRw),
    .I1(DCORENCPWRw),
    .O(\FOOBAR12__ctinst/4 )
  );
  X_AND2 \FOOBAR14__ctinst/4_2216  (
    .I0(DCORENCPWRw),
    .I1(DCORENCPWRw),
    .O(\FOOBAR14__ctinst/4 )
  );
  X_AND2 \FOOBAR19__ctinst/0_2217  (
    .I0(\MSPReset_II/UIM ),
    .I1(\MSPReset_II/UIM ),
    .O(\NlwInverterSignal_FOOBAR19__ctinst/0/OUT )
  );
  X_AND2 \FOOBAR19__ctinst/4_2218  (
    .I0(DCORSENSORw),
    .I1(DCORSENSORw),
    .O(\FOOBAR19__ctinst/4 )
  );
  X_AND2 \FOOBAR21__ctinst/4_2219  (
    .I0(\NlwInverterSignal_FOOBAR21__ctinst/4/IN0 ),
    .I1(\NlwInverterSignal_FOOBAR21__ctinst/4/IN1 ),
    .O(\FOOBAR21__ctinst/4 )
  );
  X_AND2 \FOOBAR23__ctinst/4_2220  (
    .I0(DCORENCPWRw),
    .I1(DCORENCPWRw),
    .O(\FOOBAR23__ctinst/4 )
  );
  X_AND2 \FOOBAR24__ctinst/4_2221  (
    .I0(\NlwInverterSignal_FOOBAR24__ctinst/4/IN0 ),
    .I1(\NlwInverterSignal_FOOBAR24__ctinst/4/IN1 ),
    .O(\FOOBAR24__ctinst/4 )
  );
  X_INV \NlwInverterBlock_AD<0>_MC.D/IN0  (
    .I(\AD<0>_MC.D1 ),
    .O(\NlwInverterSignal_AD<0>_MC.D/IN0 )
  );
  X_INV \NlwInverterBlock_AD<0>_MC.D2_PT_0/IN1  (
    .I(\outDATA<0>\$WA0.UIM ),
    .O(\NlwInverterSignal_AD<0>_MC.D2_PT_0/IN1 )
  );
  X_INV \NlwInverterBlock_AD<0>_MC.D2_PT_1/IN1  (
    .I(\outDATA<0>\$WA2.UIM ),
    .O(\NlwInverterSignal_AD<0>_MC.D2_PT_1/IN1 )
  );
  X_INV \NlwInverterBlock_AD<0>_MC.D2_PT_2/IN1  (
    .I(\outDATA<0>\$WA3.UIM ),
    .O(\NlwInverterSignal_AD<0>_MC.D2_PT_2/IN1 )
  );
  X_INV \NlwInverterBlock_AD<0>_MC.D2_PT_3/IN1  (
    .I(\outDATA<0>\$WA5.UIM ),
    .O(\NlwInverterSignal_AD<0>_MC.D2_PT_3/IN1 )
  );
  X_INV \NlwInverterBlock_AD<0>_MC.D2_PT_4/IN1  (
    .I(\outDATA<0>\$WA6.UIM ),
    .O(\NlwInverterSignal_AD<0>_MC.D2_PT_4/IN1 )
  );
  X_INV \NlwInverterBlock_AD<0>_MC.D2_PT_5/IN0  (
    .I(\outDATA<0>\$WA4.UIM ),
    .O(\NlwInverterSignal_AD<0>_MC.D2_PT_5/IN0 )
  );
  X_INV \NlwInverterBlock_AD<0>_MC.D2_PT_5/IN1  (
    .I(N_PZ_1016),
    .O(\NlwInverterSignal_AD<0>_MC.D2_PT_5/IN1 )
  );
  X_INV \NlwInverterBlock_AD<0>_MC.D2_PT_6/IN0  (
    .I(\outDATA<0>\$WA1.UIM ),
    .O(\NlwInverterSignal_AD<0>_MC.D2_PT_6/IN0 )
  );
  X_INV \NlwInverterBlock_AD<0>_MC.D2_PT_6/IN1  (
    .I(N_PZ_1017),
    .O(\NlwInverterSignal_AD<0>_MC.D2_PT_6/IN1 )
  );
  X_INV \NlwInverterBlock_AD<0>_MC.D2_PT_7/IN0  (
    .I(\outDATA<0>\$WA2.UIM ),
    .O(\NlwInverterSignal_AD<0>_MC.D2_PT_7/IN0 )
  );
  X_INV \NlwInverterBlock_AD<0>_MC.D2_PT_7/IN1  (
    .I(DCORIFGr),
    .O(\NlwInverterSignal_AD<0>_MC.D2_PT_7/IN1 )
  );
  X_INV \NlwInverterBlock_AD<0>_MC.D2_PT_7/IN2  (
    .I(N_PZ_1053),
    .O(\NlwInverterSignal_AD<0>_MC.D2_PT_7/IN2 )
  );
  X_INV \NlwInverterBlock_DCORI2CCNTr_MC.D1/IN1  (
    .I(\RD_II/UIM ),
    .O(\NlwInverterSignal_DCORI2CCNTr_MC.D1/IN1 )
  );
  X_INV \NlwInverterBlock_DCORI2CCNTr_MC.D1/IN2  (
    .I(U2_ADDR_reg[0]),
    .O(\NlwInverterSignal_DCORI2CCNTr_MC.D1/IN2 )
  );
  X_INV \NlwInverterBlock_DCORI2CCNTr_MC.D1/IN3  (
    .I(U2_ADDR_reg[4]),
    .O(\NlwInverterSignal_DCORI2CCNTr_MC.D1/IN3 )
  );
  X_INV \NlwInverterBlock_DCORI2CCNTr_MC.D1/IN4  (
    .I(U2_ADDR_reg[5]),
    .O(\NlwInverterSignal_DCORI2CCNTr_MC.D1/IN4 )
  );
  X_INV \NlwInverterBlock_DCORI2CCNTr_MC.D1/IN5  (
    .I(U2_ADDR_reg[6]),
    .O(\NlwInverterSignal_DCORI2CCNTr_MC.D1/IN5 )
  );
  X_INV \NlwInverterBlock_DCORI2CCNTr_MC.D1/IN6  (
    .I(U2_ADDR_reg[7]),
    .O(\NlwInverterSignal_DCORI2CCNTr_MC.D1/IN6 )
  );
  X_INV \NlwInverterBlock_DCORI2CCNTr_MC.D1/IN7  (
    .I(U2_ADDR_reg[3]),
    .O(\NlwInverterSignal_DCORI2CCNTr_MC.D1/IN7 )
  );
  X_INV \NlwInverterBlock_DCORI2CCNTr_MC.D1/IN8  (
    .I(U2_ADDR_reg[1]),
    .O(\NlwInverterSignal_DCORI2CCNTr_MC.D1/IN8 )
  );
  X_INV \NlwInverterBlock_DCORI2CCNTr_MC.D1/IN9  (
    .I(U2_ADDR_reg[2]),
    .O(\NlwInverterSignal_DCORI2CCNTr_MC.D1/IN9 )
  );
  X_INV \NlwInverterBlock_U2_ADDR_reg<0>_MC.D2_PT_0/IN1  (
    .I(\MSPReset_II/UIM ),
    .O(\NlwInverterSignal_U2_ADDR_reg<0>_MC.D2_PT_0/IN1 )
  );
  X_INV \NlwInverterBlock_U2_ADDR_reg<0>_MC.D2_PT_1/IN3  (
    .I(\AD<0>_II/UIM ),
    .O(\NlwInverterSignal_U2_ADDR_reg<0>_MC.D2_PT_1/IN3 )
  );
  X_INV \NlwInverterBlock_U2_ADDR_reg<0>_MC.D2_PT_1/IN4  (
    .I(\AS_II/UIM ),
    .O(\NlwInverterSignal_U2_ADDR_reg<0>_MC.D2_PT_1/IN4 )
  );
  X_INV \NlwInverterBlock_U2_ADDR_reg<0>_MC.D2_PT_2/IN2  (
    .I(U2_ADDR_reg[0]),
    .O(\NlwInverterSignal_U2_ADDR_reg<0>_MC.D2_PT_2/IN2 )
  );
  X_INV \NlwInverterBlock_U2_ADDR_reg<0>_MC.D2_PT_2/IN5  (
    .I(\AS_II/UIM ),
    .O(\NlwInverterSignal_U2_ADDR_reg<0>_MC.D2_PT_2/IN5 )
  );
  X_INV \NlwInverterBlock_U2_ADDR_reg<0>_MC.D2_PT_3/IN2  (
    .I(U2_ADDR_reg[4]),
    .O(\NlwInverterSignal_U2_ADDR_reg<0>_MC.D2_PT_3/IN2 )
  );
  X_INV \NlwInverterBlock_U2_ADDR_reg<0>_MC.D2_PT_3/IN3  (
    .I(U2_ADDR_reg[5]),
    .O(\NlwInverterSignal_U2_ADDR_reg<0>_MC.D2_PT_3/IN3 )
  );
  X_INV \NlwInverterBlock_U2_ADDR_reg<0>_MC.D2_PT_3/IN4  (
    .I(U2_ADDR_reg[6]),
    .O(\NlwInverterSignal_U2_ADDR_reg<0>_MC.D2_PT_3/IN4 )
  );
  X_INV \NlwInverterBlock_U2_ADDR_reg<0>_MC.D2_PT_3/IN5  (
    .I(U2_ADDR_reg[7]),
    .O(\NlwInverterSignal_U2_ADDR_reg<0>_MC.D2_PT_3/IN5 )
  );
  X_INV \NlwInverterBlock_U2_ADDR_reg<0>_MC.D2_PT_3/IN7  (
    .I(U2_WRRDedge),
    .O(\NlwInverterSignal_U2_ADDR_reg<0>_MC.D2_PT_3/IN7 )
  );
  X_INV \NlwInverterBlock_U2_ADDR_reg<4>_MC.D2_PT_0/IN1  (
    .I(\MSPReset_II/UIM ),
    .O(\NlwInverterSignal_U2_ADDR_reg<4>_MC.D2_PT_0/IN1 )
  );
  X_INV \NlwInverterBlock_U2_ADDR_reg<4>_MC.D2_PT_1/IN3  (
    .I(\AS_II/UIM ),
    .O(\NlwInverterSignal_U2_ADDR_reg<4>_MC.D2_PT_1/IN3 )
  );
  X_INV \NlwInverterBlock_U2_ADDR_reg<4>_MC.D2_PT_1/IN5  (
    .I(\AD<4>_II/UIM ),
    .O(\NlwInverterSignal_U2_ADDR_reg<4>_MC.D2_PT_1/IN5 )
  );
  X_INV \NlwInverterBlock_U2_ADDR_reg<4>_MC.D2_PT_2/IN2  (
    .I(U2_ADDR_reg[4]),
    .O(\NlwInverterSignal_U2_ADDR_reg<4>_MC.D2_PT_2/IN2 )
  );
  X_INV \NlwInverterBlock_U2_ADDR_reg<4>_MC.D2_PT_2/IN4  (
    .I(\AS_II/UIM ),
    .O(\NlwInverterSignal_U2_ADDR_reg<4>_MC.D2_PT_2/IN4 )
  );
  X_INV \NlwInverterBlock_U2_ADDR_reg<5>_MC.D2_PT_0/IN1  (
    .I(\MSPReset_II/UIM ),
    .O(\NlwInverterSignal_U2_ADDR_reg<5>_MC.D2_PT_0/IN1 )
  );
  X_INV \NlwInverterBlock_U2_ADDR_reg<5>_MC.D2_PT_1/IN3  (
    .I(\AS_II/UIM ),
    .O(\NlwInverterSignal_U2_ADDR_reg<5>_MC.D2_PT_1/IN3 )
  );
  X_INV \NlwInverterBlock_U2_ADDR_reg<5>_MC.D2_PT_1/IN5  (
    .I(\AD<5>_II/UIM ),
    .O(\NlwInverterSignal_U2_ADDR_reg<5>_MC.D2_PT_1/IN5 )
  );
  X_INV \NlwInverterBlock_U2_ADDR_reg<5>_MC.D2_PT_2/IN2  (
    .I(U2_ADDR_reg[5]),
    .O(\NlwInverterSignal_U2_ADDR_reg<5>_MC.D2_PT_2/IN2 )
  );
  X_INV \NlwInverterBlock_U2_ADDR_reg<5>_MC.D2_PT_2/IN4  (
    .I(\AS_II/UIM ),
    .O(\NlwInverterSignal_U2_ADDR_reg<5>_MC.D2_PT_2/IN4 )
  );
  X_INV \NlwInverterBlock_U2_ADDR_reg<6>_MC.D2_PT_0/IN1  (
    .I(\MSPReset_II/UIM ),
    .O(\NlwInverterSignal_U2_ADDR_reg<6>_MC.D2_PT_0/IN1 )
  );
  X_INV \NlwInverterBlock_U2_ADDR_reg<6>_MC.D2_PT_1/IN3  (
    .I(\AS_II/UIM ),
    .O(\NlwInverterSignal_U2_ADDR_reg<6>_MC.D2_PT_1/IN3 )
  );
  X_INV \NlwInverterBlock_U2_ADDR_reg<6>_MC.D2_PT_1/IN5  (
    .I(\AD<6>_II/UIM ),
    .O(\NlwInverterSignal_U2_ADDR_reg<6>_MC.D2_PT_1/IN5 )
  );
  X_INV \NlwInverterBlock_U2_ADDR_reg<6>_MC.D2_PT_2/IN2  (
    .I(U2_ADDR_reg[6]),
    .O(\NlwInverterSignal_U2_ADDR_reg<6>_MC.D2_PT_2/IN2 )
  );
  X_INV \NlwInverterBlock_U2_ADDR_reg<6>_MC.D2_PT_2/IN4  (
    .I(\AS_II/UIM ),
    .O(\NlwInverterSignal_U2_ADDR_reg<6>_MC.D2_PT_2/IN4 )
  );
  X_INV \NlwInverterBlock_U2_ADDR_reg<7>_MC.D2_PT_0/IN1  (
    .I(\MSPReset_II/UIM ),
    .O(\NlwInverterSignal_U2_ADDR_reg<7>_MC.D2_PT_0/IN1 )
  );
  X_INV \NlwInverterBlock_U2_ADDR_reg<7>_MC.D2_PT_1/IN3  (
    .I(\AS_II/UIM ),
    .O(\NlwInverterSignal_U2_ADDR_reg<7>_MC.D2_PT_1/IN3 )
  );
  X_INV \NlwInverterBlock_U2_ADDR_reg<7>_MC.D2_PT_1/IN5  (
    .I(\AD<7>_II/UIM ),
    .O(\NlwInverterSignal_U2_ADDR_reg<7>_MC.D2_PT_1/IN5 )
  );
  X_INV \NlwInverterBlock_U2_ADDR_reg<7>_MC.D2_PT_2/IN2  (
    .I(U2_ADDR_reg[7]),
    .O(\NlwInverterSignal_U2_ADDR_reg<7>_MC.D2_PT_2/IN2 )
  );
  X_INV \NlwInverterBlock_U2_ADDR_reg<7>_MC.D2_PT_2/IN4  (
    .I(\AS_II/UIM ),
    .O(\NlwInverterSignal_U2_ADDR_reg<7>_MC.D2_PT_2/IN4 )
  );
  X_INV \NlwInverterBlock_U2_AutoInc_MC.D/IN0  (
    .I(\U2_AutoInc_MC.D1 ),
    .O(\NlwInverterSignal_U2_AutoInc_MC.D/IN0 )
  );
  X_INV \NlwInverterBlock_N_PZ_992_MC.D2_PT_1/IN1  (
    .I(U2_ASedge),
    .O(\NlwInverterSignal_N_PZ_992_MC.D2_PT_1/IN1 )
  );
  X_INV \NlwInverterBlock_U2_ADDR_reg<3>_MC.D2_PT_0/IN1  (
    .I(\MSPReset_II/UIM ),
    .O(\NlwInverterSignal_U2_ADDR_reg<3>_MC.D2_PT_0/IN1 )
  );
  X_INV \NlwInverterBlock_U2_ADDR_reg<3>_MC.D2_PT_1/IN3  (
    .I(\AS_II/UIM ),
    .O(\NlwInverterSignal_U2_ADDR_reg<3>_MC.D2_PT_1/IN3 )
  );
  X_INV \NlwInverterBlock_U2_ADDR_reg<3>_MC.D2_PT_1/IN5  (
    .I(\AD<3>_II/UIM ),
    .O(\NlwInverterSignal_U2_ADDR_reg<3>_MC.D2_PT_1/IN5 )
  );
  X_INV \NlwInverterBlock_U2_ADDR_reg<3>_MC.D2_PT_2/IN2  (
    .I(U2_ADDR_reg[3]),
    .O(\NlwInverterSignal_U2_ADDR_reg<3>_MC.D2_PT_2/IN2 )
  );
  X_INV \NlwInverterBlock_U2_ADDR_reg<3>_MC.D2_PT_2/IN4  (
    .I(\AS_II/UIM ),
    .O(\NlwInverterSignal_U2_ADDR_reg<3>_MC.D2_PT_2/IN4 )
  );
  X_INV \NlwInverterBlock_U2_ADDR_reg<3>_MC.D2_PT_3/IN3  (
    .I(U2_ADDR_reg[4]),
    .O(\NlwInverterSignal_U2_ADDR_reg<3>_MC.D2_PT_3/IN3 )
  );
  X_INV \NlwInverterBlock_U2_ADDR_reg<3>_MC.D2_PT_3/IN4  (
    .I(U2_ADDR_reg[5]),
    .O(\NlwInverterSignal_U2_ADDR_reg<3>_MC.D2_PT_3/IN4 )
  );
  X_INV \NlwInverterBlock_U2_ADDR_reg<3>_MC.D2_PT_3/IN5  (
    .I(U2_ADDR_reg[6]),
    .O(\NlwInverterSignal_U2_ADDR_reg<3>_MC.D2_PT_3/IN5 )
  );
  X_INV \NlwInverterBlock_U2_ADDR_reg<3>_MC.D2_PT_3/IN6  (
    .I(U2_ADDR_reg[7]),
    .O(\NlwInverterSignal_U2_ADDR_reg<3>_MC.D2_PT_3/IN6 )
  );
  X_INV \NlwInverterBlock_U2_ADDR_reg<3>_MC.D2_PT_3/IN10  (
    .I(U2_WRRDedge),
    .O(\NlwInverterSignal_U2_ADDR_reg<3>_MC.D2_PT_3/IN10 )
  );
  X_INV \NlwInverterBlock_U2_ADDR_reg<1>_MC.D2_PT_0/IN1  (
    .I(\MSPReset_II/UIM ),
    .O(\NlwInverterSignal_U2_ADDR_reg<1>_MC.D2_PT_0/IN1 )
  );
  X_INV \NlwInverterBlock_U2_ADDR_reg<1>_MC.D2_PT_1/IN3  (
    .I(\AS_II/UIM ),
    .O(\NlwInverterSignal_U2_ADDR_reg<1>_MC.D2_PT_1/IN3 )
  );
  X_INV \NlwInverterBlock_U2_ADDR_reg<1>_MC.D2_PT_1/IN5  (
    .I(\AD<1>_II/UIM ),
    .O(\NlwInverterSignal_U2_ADDR_reg<1>_MC.D2_PT_1/IN5 )
  );
  X_INV \NlwInverterBlock_U2_ADDR_reg<1>_MC.D2_PT_2/IN2  (
    .I(U2_ADDR_reg[1]),
    .O(\NlwInverterSignal_U2_ADDR_reg<1>_MC.D2_PT_2/IN2 )
  );
  X_INV \NlwInverterBlock_U2_ADDR_reg<1>_MC.D2_PT_2/IN4  (
    .I(\AS_II/UIM ),
    .O(\NlwInverterSignal_U2_ADDR_reg<1>_MC.D2_PT_2/IN4 )
  );
  X_INV \NlwInverterBlock_U2_ADDR_reg<1>_MC.D2_PT_3/IN3  (
    .I(U2_ADDR_reg[4]),
    .O(\NlwInverterSignal_U2_ADDR_reg<1>_MC.D2_PT_3/IN3 )
  );
  X_INV \NlwInverterBlock_U2_ADDR_reg<1>_MC.D2_PT_3/IN4  (
    .I(U2_ADDR_reg[5]),
    .O(\NlwInverterSignal_U2_ADDR_reg<1>_MC.D2_PT_3/IN4 )
  );
  X_INV \NlwInverterBlock_U2_ADDR_reg<1>_MC.D2_PT_3/IN5  (
    .I(U2_ADDR_reg[6]),
    .O(\NlwInverterSignal_U2_ADDR_reg<1>_MC.D2_PT_3/IN5 )
  );
  X_INV \NlwInverterBlock_U2_ADDR_reg<1>_MC.D2_PT_3/IN6  (
    .I(U2_ADDR_reg[7]),
    .O(\NlwInverterSignal_U2_ADDR_reg<1>_MC.D2_PT_3/IN6 )
  );
  X_INV \NlwInverterBlock_U2_ADDR_reg<1>_MC.D2_PT_3/IN8  (
    .I(U2_WRRDedge),
    .O(\NlwInverterSignal_U2_ADDR_reg<1>_MC.D2_PT_3/IN8 )
  );
  X_INV \NlwInverterBlock_U2_ADDR_reg<2>_MC.D2_PT_0/IN1  (
    .I(\MSPReset_II/UIM ),
    .O(\NlwInverterSignal_U2_ADDR_reg<2>_MC.D2_PT_0/IN1 )
  );
  X_INV \NlwInverterBlock_U2_ADDR_reg<2>_MC.D2_PT_1/IN3  (
    .I(\AS_II/UIM ),
    .O(\NlwInverterSignal_U2_ADDR_reg<2>_MC.D2_PT_1/IN3 )
  );
  X_INV \NlwInverterBlock_U2_ADDR_reg<2>_MC.D2_PT_1/IN5  (
    .I(\AD<2>_II/UIM ),
    .O(\NlwInverterSignal_U2_ADDR_reg<2>_MC.D2_PT_1/IN5 )
  );
  X_INV \NlwInverterBlock_U2_ADDR_reg<2>_MC.D2_PT_2/IN2  (
    .I(U2_ADDR_reg[2]),
    .O(\NlwInverterSignal_U2_ADDR_reg<2>_MC.D2_PT_2/IN2 )
  );
  X_INV \NlwInverterBlock_U2_ADDR_reg<2>_MC.D2_PT_2/IN4  (
    .I(\AS_II/UIM ),
    .O(\NlwInverterSignal_U2_ADDR_reg<2>_MC.D2_PT_2/IN4 )
  );
  X_INV \NlwInverterBlock_U2_ADDR_reg<2>_MC.D2_PT_3/IN3  (
    .I(U2_ADDR_reg[4]),
    .O(\NlwInverterSignal_U2_ADDR_reg<2>_MC.D2_PT_3/IN3 )
  );
  X_INV \NlwInverterBlock_U2_ADDR_reg<2>_MC.D2_PT_3/IN4  (
    .I(U2_ADDR_reg[5]),
    .O(\NlwInverterSignal_U2_ADDR_reg<2>_MC.D2_PT_3/IN4 )
  );
  X_INV \NlwInverterBlock_U2_ADDR_reg<2>_MC.D2_PT_3/IN5  (
    .I(U2_ADDR_reg[6]),
    .O(\NlwInverterSignal_U2_ADDR_reg<2>_MC.D2_PT_3/IN5 )
  );
  X_INV \NlwInverterBlock_U2_ADDR_reg<2>_MC.D2_PT_3/IN6  (
    .I(U2_ADDR_reg[7]),
    .O(\NlwInverterSignal_U2_ADDR_reg<2>_MC.D2_PT_3/IN6 )
  );
  X_INV \NlwInverterBlock_U2_ADDR_reg<2>_MC.D2_PT_3/IN9  (
    .I(U2_WRRDedge),
    .O(\NlwInverterSignal_U2_ADDR_reg<2>_MC.D2_PT_3/IN9 )
  );
  X_INV \NlwInverterBlock_U11_U3_counterr<0>_MC.D2_PT_1/IN1  (
    .I(\SCLreset_II/UIM ),
    .O(\NlwInverterSignal_U11_U3_counterr<0>_MC.D2_PT_1/IN1 )
  );
  X_INV \NlwInverterBlock_U11_U3_counterr<0>_MC.D2_PT_2/IN1  (
    .I(\SCLreset_II/UIM ),
    .O(\NlwInverterSignal_U11_U3_counterr<0>_MC.D2_PT_2/IN1 )
  );
  X_INV \NlwInverterBlock_U11_U3_counterr<0>_MC.D2_PT_2/IN2  (
    .I(U11_Incdetect),
    .O(\NlwInverterSignal_U11_U3_counterr<0>_MC.D2_PT_2/IN2 )
  );
  X_INV \NlwInverterBlock_U11_U3_counterr<0>_MC.D2_PT_2/IN3  (
    .I(U11_SCLdetect),
    .O(\NlwInverterSignal_U11_U3_counterr<0>_MC.D2_PT_2/IN3 )
  );
  X_INV \NlwInverterBlock_U11_U3_counterr<0>_MC.D2_PT_3/IN0  (
    .I(U11_U3_counterr[0]),
    .O(\NlwInverterSignal_U11_U3_counterr<0>_MC.D2_PT_3/IN0 )
  );
  X_INV \NlwInverterBlock_U11_U3_counterr<0>_MC.D2_PT_3/IN1  (
    .I(\SCLreset_II/UIM ),
    .O(\NlwInverterSignal_U11_U3_counterr<0>_MC.D2_PT_3/IN1 )
  );
  X_INV \NlwInverterBlock_U11_U3_counterr<0>_MC.D2_PT_3/IN3  (
    .I(U11_SCLdetect),
    .O(\NlwInverterSignal_U11_U3_counterr<0>_MC.D2_PT_3/IN3 )
  );
  X_INV \NlwInverterBlock_U11_U3_counterr<0>_MC.D2_PT_4/IN0  (
    .I(\SCLreset_II/UIM ),
    .O(\NlwInverterSignal_U11_U3_counterr<0>_MC.D2_PT_4/IN0 )
  );
  X_INV \NlwInverterBlock_U11_U3_counterr<0>_MC.D2_PT_4/IN1  (
    .I(\SCLinc_II/UIM ),
    .O(\NlwInverterSignal_U11_U3_counterr<0>_MC.D2_PT_4/IN1 )
  );
  X_INV \NlwInverterBlock_U11_U3_counterr<0>_MC.D2_PT_5/IN0  (
    .I(U11_U3_counterr[0]),
    .O(\NlwInverterSignal_U11_U3_counterr<0>_MC.D2_PT_5/IN0 )
  );
  X_INV \NlwInverterBlock_U11_U3_counterr<0>_MC.D2_PT_5/IN1  (
    .I(\SCLreset_II/UIM ),
    .O(\NlwInverterSignal_U11_U3_counterr<0>_MC.D2_PT_5/IN1 )
  );
  X_INV \NlwInverterBlock_U11_U3_counterr<0>_MC.D2_PT_5/IN2  (
    .I(U11_Incdetect),
    .O(\NlwInverterSignal_U11_U3_counterr<0>_MC.D2_PT_5/IN2 )
  );
  X_INV \NlwInverterBlock_U11_U3_counterr<0>_MC.D2_PT_5/IN4  (
    .I(\TP12_MC.UIM ),
    .O(\NlwInverterSignal_U11_U3_counterr<0>_MC.D2_PT_5/IN4 )
  );
  X_INV \NlwInverterBlock_U11_Incdetect_MC.D1/IN0  (
    .I(\SCLinc_II/UIM ),
    .O(\NlwInverterSignal_U11_Incdetect_MC.D1/IN0 )
  );
  X_INV \NlwInverterBlock_U11_SCLdetect_MC.D1/IN0  (
    .I(\SCL_II/UIM ),
    .O(\NlwInverterSignal_U11_SCLdetect_MC.D1/IN0 )
  );
  X_INV \NlwInverterBlock_TP12_MC.D1/IN0  (
    .I(U11_U3_counterr[0]),
    .O(\NlwInverterSignal_TP12_MC.D1/IN0 )
  );
  X_INV \NlwInverterBlock_TP12_MC.D1/IN1  (
    .I(U11_U3_counterr[3]),
    .O(\NlwInverterSignal_TP12_MC.D1/IN1 )
  );
  X_INV \NlwInverterBlock_TP12_MC.D1/IN2  (
    .I(U11_U3_counterr[1]),
    .O(\NlwInverterSignal_TP12_MC.D1/IN2 )
  );
  X_INV \NlwInverterBlock_TP12_MC.D1/IN3  (
    .I(U11_U3_counterr[2]),
    .O(\NlwInverterSignal_TP12_MC.D1/IN3 )
  );
  X_INV \NlwInverterBlock_TP12_MC.D1/IN4  (
    .I(U11_U3_counterr[4]),
    .O(\NlwInverterSignal_TP12_MC.D1/IN4 )
  );
  X_INV \NlwInverterBlock_TP12_MC.D1/IN5  (
    .I(U11_U3_counterr[5]),
    .O(\NlwInverterSignal_TP12_MC.D1/IN5 )
  );
  X_INV \NlwInverterBlock_U11_U3_counterr<3>_MC.D/IN0  (
    .I(\U11_U3_counterr<3>_MC.D1 ),
    .O(\NlwInverterSignal_U11_U3_counterr<3>_MC.D/IN0 )
  );
  X_INV \NlwInverterBlock_U11_U3_counterr<3>_MC.D2_PT_1/IN1  (
    .I(U11_Incdetect),
    .O(\NlwInverterSignal_U11_U3_counterr<3>_MC.D2_PT_1/IN1 )
  );
  X_INV \NlwInverterBlock_U11_U3_counterr<3>_MC.D2_PT_1/IN2  (
    .I(N_PZ_1128),
    .O(\NlwInverterSignal_U11_U3_counterr<3>_MC.D2_PT_1/IN2 )
  );
  X_INV \NlwInverterBlock_U11_U3_counterr<3>_MC.D2_PT_2/IN0  (
    .I(\SCLreset_II/UIM ),
    .O(\NlwInverterSignal_U11_U3_counterr<3>_MC.D2_PT_2/IN0 )
  );
  X_INV \NlwInverterBlock_U11_U3_counterr<3>_MC.D2_PT_2/IN1  (
    .I(U11_U3_counterr[3]),
    .O(\NlwInverterSignal_U11_U3_counterr<3>_MC.D2_PT_2/IN1 )
  );
  X_INV \NlwInverterBlock_U11_U3_counterr<3>_MC.D2_PT_3/IN0  (
    .I(U11_Incdetect),
    .O(\NlwInverterSignal_U11_U3_counterr<3>_MC.D2_PT_3/IN0 )
  );
  X_INV \NlwInverterBlock_U11_U3_counterr<3>_MC.D2_PT_3/IN1  (
    .I(U11_SCLdetect),
    .O(\NlwInverterSignal_U11_U3_counterr<3>_MC.D2_PT_3/IN1 )
  );
  X_INV \NlwInverterBlock_U11_U3_counterr<3>_MC.D2_PT_3/IN2  (
    .I(N_PZ_1128),
    .O(\NlwInverterSignal_U11_U3_counterr<3>_MC.D2_PT_3/IN2 )
  );
  X_INV \NlwInverterBlock_U11_U3_counterr<3>_MC.D2_PT_4/IN0  (
    .I(U11_Incdetect),
    .O(\NlwInverterSignal_U11_U3_counterr<3>_MC.D2_PT_4/IN0 )
  );
  X_INV \NlwInverterBlock_U11_U3_counterr<3>_MC.D2_PT_4/IN2  (
    .I(N_PZ_1128),
    .O(\NlwInverterSignal_U11_U3_counterr<3>_MC.D2_PT_4/IN2 )
  );
  X_INV \NlwInverterBlock_U11_U3_counterr<3>_MC.D2_PT_5/IN0  (
    .I(U11_Incdetect),
    .O(\NlwInverterSignal_U11_U3_counterr<3>_MC.D2_PT_5/IN0 )
  );
  X_INV \NlwInverterBlock_U11_U3_counterr<3>_MC.D2_PT_5/IN2  (
    .I(N_PZ_1128),
    .O(\NlwInverterSignal_U11_U3_counterr<3>_MC.D2_PT_5/IN2 )
  );
  X_INV \NlwInverterBlock_U11_U3_counterr<3>_MC.D2_PT_6/IN1  (
    .I(U11_SCLdetect),
    .O(\NlwInverterSignal_U11_U3_counterr<3>_MC.D2_PT_6/IN1 )
  );
  X_INV \NlwInverterBlock_U11_U3_counterr<3>_MC.D2_PT_6/IN4  (
    .I(N_PZ_1128),
    .O(\NlwInverterSignal_U11_U3_counterr<3>_MC.D2_PT_6/IN4 )
  );
  X_INV \NlwInverterBlock_N_PZ_1128_MC.D2_PT_1/IN0  (
    .I(\SCLinc_II/UIM ),
    .O(\NlwInverterSignal_N_PZ_1128_MC.D2_PT_1/IN0 )
  );
  X_INV \NlwInverterBlock_N_PZ_1128_MC.D2_PT_2/IN0  (
    .I(U11_Incdetect),
    .O(\NlwInverterSignal_N_PZ_1128_MC.D2_PT_2/IN0 )
  );
  X_INV \NlwInverterBlock_U11_ResetDetect_MC.D1/IN0  (
    .I(\SCLreset_II/UIM ),
    .O(\NlwInverterSignal_U11_ResetDetect_MC.D1/IN0 )
  );
  X_INV \NlwInverterBlock_U11_U3_counterr<1>_MC.D2_PT_0/IN1  (
    .I(\SCLinc_II/UIM ),
    .O(\NlwInverterSignal_U11_U3_counterr<1>_MC.D2_PT_0/IN1 )
  );
  X_INV \NlwInverterBlock_U11_U3_counterr<1>_MC.D2_PT_1/IN2  (
    .I(U11_SCLdetect),
    .O(\NlwInverterSignal_U11_U3_counterr<1>_MC.D2_PT_1/IN2 )
  );
  X_INV \NlwInverterBlock_U11_U3_counterr<1>_MC.D2_PT_1/IN3  (
    .I(N_PZ_1128),
    .O(\NlwInverterSignal_U11_U3_counterr<1>_MC.D2_PT_1/IN3 )
  );
  X_INV \NlwInverterBlock_U11_U3_counterr<1>_MC.D2_PT_2/IN0  (
    .I(U11_U3_counterr[0]),
    .O(\NlwInverterSignal_U11_U3_counterr<1>_MC.D2_PT_2/IN0 )
  );
  X_INV \NlwInverterBlock_U11_U3_counterr<1>_MC.D2_PT_2/IN1  (
    .I(U11_Incdetect),
    .O(\NlwInverterSignal_U11_U3_counterr<1>_MC.D2_PT_2/IN1 )
  );
  X_INV \NlwInverterBlock_U11_U3_counterr<1>_MC.D2_PT_2/IN3  (
    .I(N_PZ_1128),
    .O(\NlwInverterSignal_U11_U3_counterr<1>_MC.D2_PT_2/IN3 )
  );
  X_INV \NlwInverterBlock_U11_U3_counterr<2>_MC.D2_PT_1/IN2  (
    .I(U11_SCLdetect),
    .O(\NlwInverterSignal_U11_U3_counterr<2>_MC.D2_PT_1/IN2 )
  );
  X_INV \NlwInverterBlock_U11_U3_counterr<2>_MC.D2_PT_1/IN4  (
    .I(N_PZ_1128),
    .O(\NlwInverterSignal_U11_U3_counterr<2>_MC.D2_PT_1/IN4 )
  );
  X_INV \NlwInverterBlock_U11_U3_counterr<2>_MC.D2_PT_2/IN0  (
    .I(U11_U3_counterr[0]),
    .O(\NlwInverterSignal_U11_U3_counterr<2>_MC.D2_PT_2/IN0 )
  );
  X_INV \NlwInverterBlock_U11_U3_counterr<2>_MC.D2_PT_2/IN1  (
    .I(U11_Incdetect),
    .O(\NlwInverterSignal_U11_U3_counterr<2>_MC.D2_PT_2/IN1 )
  );
  X_INV \NlwInverterBlock_U11_U3_counterr<2>_MC.D2_PT_2/IN3  (
    .I(U11_U3_counterr[1]),
    .O(\NlwInverterSignal_U11_U3_counterr<2>_MC.D2_PT_2/IN3 )
  );
  X_INV \NlwInverterBlock_U11_U3_counterr<2>_MC.D2_PT_2/IN4  (
    .I(N_PZ_1128),
    .O(\NlwInverterSignal_U11_U3_counterr<2>_MC.D2_PT_2/IN4 )
  );
  X_INV \NlwInverterBlock_U11_U3_counterr<4>_MC.D2_PT_1/IN2  (
    .I(N_PZ_1128),
    .O(\NlwInverterSignal_U11_U3_counterr<4>_MC.D2_PT_1/IN2 )
  );
  X_INV \NlwInverterBlock_U11_U3_counterr<4>_MC.D2_PT_2/IN2  (
    .I(U11_SCLdetect),
    .O(\NlwInverterSignal_U11_U3_counterr<4>_MC.D2_PT_2/IN2 )
  );
  X_INV \NlwInverterBlock_U11_U3_counterr<4>_MC.D2_PT_2/IN5  (
    .I(N_PZ_1128),
    .O(\NlwInverterSignal_U11_U3_counterr<4>_MC.D2_PT_2/IN5 )
  );
  X_INV \NlwInverterBlock_U11_U3_counterr<4>_MC.D2_PT_3/IN0  (
    .I(U11_U3_counterr[0]),
    .O(\NlwInverterSignal_U11_U3_counterr<4>_MC.D2_PT_3/IN0 )
  );
  X_INV \NlwInverterBlock_U11_U3_counterr<4>_MC.D2_PT_3/IN1  (
    .I(U11_Incdetect),
    .O(\NlwInverterSignal_U11_U3_counterr<4>_MC.D2_PT_3/IN1 )
  );
  X_INV \NlwInverterBlock_U11_U3_counterr<4>_MC.D2_PT_3/IN3  (
    .I(U11_U3_counterr[3]),
    .O(\NlwInverterSignal_U11_U3_counterr<4>_MC.D2_PT_3/IN3 )
  );
  X_INV \NlwInverterBlock_U11_U3_counterr<4>_MC.D2_PT_3/IN4  (
    .I(U11_U3_counterr[1]),
    .O(\NlwInverterSignal_U11_U3_counterr<4>_MC.D2_PT_3/IN4 )
  );
  X_INV \NlwInverterBlock_U11_U3_counterr<4>_MC.D2_PT_3/IN5  (
    .I(U11_U3_counterr[2]),
    .O(\NlwInverterSignal_U11_U3_counterr<4>_MC.D2_PT_3/IN5 )
  );
  X_INV \NlwInverterBlock_U11_U3_counterr<4>_MC.D2_PT_3/IN6  (
    .I(N_PZ_1128),
    .O(\NlwInverterSignal_U11_U3_counterr<4>_MC.D2_PT_3/IN6 )
  );
  X_INV \NlwInverterBlock_U11_U3_counterr<5>_MC.D2_PT_1/IN3  (
    .I(N_PZ_1128),
    .O(\NlwInverterSignal_U11_U3_counterr<5>_MC.D2_PT_1/IN3 )
  );
  X_INV \NlwInverterBlock_U11_U3_counterr<5>_MC.D2_PT_2/IN2  (
    .I(U11_SCLdetect),
    .O(\NlwInverterSignal_U11_U3_counterr<5>_MC.D2_PT_2/IN2 )
  );
  X_INV \NlwInverterBlock_U11_U3_counterr<5>_MC.D2_PT_2/IN6  (
    .I(N_PZ_1128),
    .O(\NlwInverterSignal_U11_U3_counterr<5>_MC.D2_PT_2/IN6 )
  );
  X_INV \NlwInverterBlock_U11_U3_counterr<5>_MC.D2_PT_3/IN0  (
    .I(U11_U3_counterr[0]),
    .O(\NlwInverterSignal_U11_U3_counterr<5>_MC.D2_PT_3/IN0 )
  );
  X_INV \NlwInverterBlock_U11_U3_counterr<5>_MC.D2_PT_3/IN1  (
    .I(U11_Incdetect),
    .O(\NlwInverterSignal_U11_U3_counterr<5>_MC.D2_PT_3/IN1 )
  );
  X_INV \NlwInverterBlock_U11_U3_counterr<5>_MC.D2_PT_3/IN3  (
    .I(U11_U3_counterr[3]),
    .O(\NlwInverterSignal_U11_U3_counterr<5>_MC.D2_PT_3/IN3 )
  );
  X_INV \NlwInverterBlock_U11_U3_counterr<5>_MC.D2_PT_3/IN4  (
    .I(U11_U3_counterr[1]),
    .O(\NlwInverterSignal_U11_U3_counterr<5>_MC.D2_PT_3/IN4 )
  );
  X_INV \NlwInverterBlock_U11_U3_counterr<5>_MC.D2_PT_3/IN5  (
    .I(U11_U3_counterr[2]),
    .O(\NlwInverterSignal_U11_U3_counterr<5>_MC.D2_PT_3/IN5 )
  );
  X_INV \NlwInverterBlock_U11_U3_counterr<5>_MC.D2_PT_3/IN6  (
    .I(U11_U3_counterr[4]),
    .O(\NlwInverterSignal_U11_U3_counterr<5>_MC.D2_PT_3/IN6 )
  );
  X_INV \NlwInverterBlock_U11_U3_counterr<5>_MC.D2_PT_3/IN7  (
    .I(N_PZ_1128),
    .O(\NlwInverterSignal_U11_U3_counterr<5>_MC.D2_PT_3/IN7 )
  );
  X_INV \NlwInverterBlock_DCOR0THRESLOWr_MC.D1/IN1  (
    .I(\RD_II/UIM ),
    .O(\NlwInverterSignal_DCOR0THRESLOWr_MC.D1/IN1 )
  );
  X_INV \NlwInverterBlock_DCOR0THRESLOWr_MC.D1/IN2  (
    .I(U2_ADDR_reg[0]),
    .O(\NlwInverterSignal_DCOR0THRESLOWr_MC.D1/IN2 )
  );
  X_INV \NlwInverterBlock_DCOR0THRESLOWr_MC.D1/IN3  (
    .I(U2_ADDR_reg[4]),
    .O(\NlwInverterSignal_DCOR0THRESLOWr_MC.D1/IN3 )
  );
  X_INV \NlwInverterBlock_DCOR0THRESLOWr_MC.D1/IN4  (
    .I(U2_ADDR_reg[5]),
    .O(\NlwInverterSignal_DCOR0THRESLOWr_MC.D1/IN4 )
  );
  X_INV \NlwInverterBlock_DCOR0THRESLOWr_MC.D1/IN5  (
    .I(U2_ADDR_reg[6]),
    .O(\NlwInverterSignal_DCOR0THRESLOWr_MC.D1/IN5 )
  );
  X_INV \NlwInverterBlock_DCOR0THRESLOWr_MC.D1/IN6  (
    .I(U2_ADDR_reg[7]),
    .O(\NlwInverterSignal_DCOR0THRESLOWr_MC.D1/IN6 )
  );
  X_INV \NlwInverterBlock_DCOR0THRESLOWr_MC.D1/IN8  (
    .I(U2_ADDR_reg[1]),
    .O(\NlwInverterSignal_DCOR0THRESLOWr_MC.D1/IN8 )
  );
  X_INV \NlwInverterBlock_DCOR0THRESLOWr_MC.D1/IN9  (
    .I(U2_ADDR_reg[2]),
    .O(\NlwInverterSignal_DCOR0THRESLOWr_MC.D1/IN9 )
  );
  X_INV \NlwInverterBlock_outDATA<0>\$WA2.UIM_MC.D2_PT_1/IN0  (
    .I(DCOR0THRESLOWr),
    .O(\NlwInverterSignal_outDATA<0>\$WA2.UIM_MC.D2_PT_1/IN0 )
  );
  X_INV \NlwInverterBlock_outDATA<0>\$WA2.UIM_MC.D2_PT_2/IN0  (
    .I(DCOR0THRESLOWr),
    .O(\NlwInverterSignal_outDATA<0>\$WA2.UIM_MC.D2_PT_2/IN0 )
  );
  X_INV \NlwInverterBlock_outDATA<0>\$WA2.UIM_MC.D2_PT_2/IN1  (
    .I(DCOR0THRESHIGHr),
    .O(\NlwInverterSignal_outDATA<0>\$WA2.UIM_MC.D2_PT_2/IN1 )
  );
  X_INV \NlwInverterBlock_outDATA<0>\$WA2.UIM_MC.D2_PT_3/IN0  (
    .I(DCOR0THRESLOWr),
    .O(\NlwInverterSignal_outDATA<0>\$WA2.UIM_MC.D2_PT_3/IN0 )
  );
  X_INV \NlwInverterBlock_outDATA<0>\$WA2.UIM_MC.D2_PT_3/IN1  (
    .I(DCOR0THRESHIGHr),
    .O(\NlwInverterSignal_outDATA<0>\$WA2.UIM_MC.D2_PT_3/IN1 )
  );
  X_INV \NlwInverterBlock_outDATA<0>\$WA2.UIM_MC.D2_PT_3/IN2  (
    .I(DCOR1THRESLOWr),
    .O(\NlwInverterSignal_outDATA<0>\$WA2.UIM_MC.D2_PT_3/IN2 )
  );
  X_INV \NlwInverterBlock_U1/U4/Latch0r<0>_MC.D2_PT_0/IN2  (
    .I(N_PZ_1018),
    .O(\NlwInverterSignal_U1/U4/Latch0r<0>_MC.D2_PT_0/IN2 )
  );
  X_INV \NlwInverterBlock_U1/Channel0<0>_MC.D2_PT_0/IN1  (
    .I(N_PZ_982),
    .O(\NlwInverterSignal_U1/Channel0<0>_MC.D2_PT_0/IN1 )
  );
  X_INV \NlwInverterBlock_U1/Channel0<0>_MC.D2_PT_1/IN1  (
    .I(\U1/Zero0 ),
    .O(\NlwInverterSignal_U1/Channel0<0>_MC.D2_PT_1/IN1 )
  );
  X_INV \NlwInverterBlock_U1/Channel0<0>_MC.D2_PT_1/IN4  (
    .I(\U1/U1/CurrState_Sreg0_FFD2 ),
    .O(\NlwInverterSignal_U1/Channel0<0>_MC.D2_PT_1/IN4 )
  );
  X_INV \NlwInverterBlock_U1/Channel0<0>_MC.D2_PT_1/IN5  (
    .I(\U1/U1/CurrState_Sreg0_FFD4 ),
    .O(\NlwInverterSignal_U1/Channel0<0>_MC.D2_PT_1/IN5 )
  );
  X_INV \NlwInverterBlock_U1/Channel0<0>_MC.D2_PT_2/IN1  (
    .I(\U1/Zero0 ),
    .O(\NlwInverterSignal_U1/Channel0<0>_MC.D2_PT_2/IN1 )
  );
  X_INV \NlwInverterBlock_U1/Channel0<0>_MC.D2_PT_2/IN2  (
    .I(\U1/U1/CurrState_Sreg0_FFD1 ),
    .O(\NlwInverterSignal_U1/Channel0<0>_MC.D2_PT_2/IN2 )
  );
  X_INV \NlwInverterBlock_U1/Channel0<0>_MC.D2_PT_2/IN4  (
    .I(\U1/U1/CurrState_Sreg0_FFD2 ),
    .O(\NlwInverterSignal_U1/Channel0<0>_MC.D2_PT_2/IN4 )
  );
  X_INV \NlwInverterBlock_U1/Zero0_MC.D2_PT_0/IN0  (
    .I(\MSPReset_II/UIM ),
    .O(\NlwInverterSignal_U1/Zero0_MC.D2_PT_0/IN0 )
  );
  X_INV \NlwInverterBlock_U1/Zero0_MC.D2_PT_3/IN1  (
    .I(DCORIFGw),
    .O(\NlwInverterSignal_U1/Zero0_MC.D2_PT_3/IN1 )
  );
  X_INV \NlwInverterBlock_U1/Zero0_MC.D2_PT_3/IN2  (
    .I(DCORENCCTLw),
    .O(\NlwInverterSignal_U1/Zero0_MC.D2_PT_3/IN2 )
  );
  X_INV \NlwInverterBlock_U1/Zero0_MC.D2_PT_3/IN3  (
    .I(NET2482),
    .O(\NlwInverterSignal_U1/Zero0_MC.D2_PT_3/IN3 )
  );
  X_INV \NlwInverterBlock_U1/Zero0_MC.D2_PT_3/IN7  (
    .I(\U1/U4/HE0statelastr ),
    .O(\NlwInverterSignal_U1/Zero0_MC.D2_PT_3/IN7 )
  );
  X_INV \NlwInverterBlock_U1/Zero0_MC.D2_PT_4/IN1  (
    .I(DCORIFGw),
    .O(\NlwInverterSignal_U1/Zero0_MC.D2_PT_4/IN1 )
  );
  X_INV \NlwInverterBlock_U1/Zero0_MC.D2_PT_4/IN2  (
    .I(DCORENCCTLw),
    .O(\NlwInverterSignal_U1/Zero0_MC.D2_PT_4/IN2 )
  );
  X_INV \NlwInverterBlock_U1/Zero0_MC.D2_PT_4/IN3  (
    .I(NET2482),
    .O(\NlwInverterSignal_U1/Zero0_MC.D2_PT_4/IN3 )
  );
  X_INV \NlwInverterBlock_U1/Zero0_MC.D2_PT_4/IN4  (
    .I(\U1/U4/RF0r ),
    .O(\NlwInverterSignal_U1/Zero0_MC.D2_PT_4/IN4 )
  );
  X_INV \NlwInverterBlock_U1/Zero0_MC.D2_PT_4/IN6  (
    .I(\U1/U4/HE0stater ),
    .O(\NlwInverterSignal_U1/Zero0_MC.D2_PT_4/IN6 )
  );
  X_INV \NlwInverterBlock_DCORIFGw_MC.D1/IN0  (
    .I(\WR_II/UIM ),
    .O(\NlwInverterSignal_DCORIFGw_MC.D1/IN0 )
  );
  X_INV \NlwInverterBlock_DCORIFGw_MC.D1/IN3  (
    .I(U2_ADDR_reg[4]),
    .O(\NlwInverterSignal_DCORIFGw_MC.D1/IN3 )
  );
  X_INV \NlwInverterBlock_DCORIFGw_MC.D1/IN4  (
    .I(U2_ADDR_reg[5]),
    .O(\NlwInverterSignal_DCORIFGw_MC.D1/IN4 )
  );
  X_INV \NlwInverterBlock_DCORIFGw_MC.D1/IN5  (
    .I(U2_ADDR_reg[6]),
    .O(\NlwInverterSignal_DCORIFGw_MC.D1/IN5 )
  );
  X_INV \NlwInverterBlock_DCORIFGw_MC.D1/IN6  (
    .I(U2_ADDR_reg[7]),
    .O(\NlwInverterSignal_DCORIFGw_MC.D1/IN6 )
  );
  X_INV \NlwInverterBlock_DCORIFGw_MC.D1/IN7  (
    .I(U2_ADDR_reg[3]),
    .O(\NlwInverterSignal_DCORIFGw_MC.D1/IN7 )
  );
  X_INV \NlwInverterBlock_DCORIFGw_MC.D1/IN8  (
    .I(U2_ADDR_reg[1]),
    .O(\NlwInverterSignal_DCORIFGw_MC.D1/IN8 )
  );
  X_INV \NlwInverterBlock_DCORIFGw_MC.D1/IN9  (
    .I(U2_ADDR_reg[2]),
    .O(\NlwInverterSignal_DCORIFGw_MC.D1/IN9 )
  );
  X_INV \NlwInverterBlock_DCORENCCTLw_MC.D1/IN0  (
    .I(\WR_II/UIM ),
    .O(\NlwInverterSignal_DCORENCCTLw_MC.D1/IN0 )
  );
  X_INV \NlwInverterBlock_DCORENCCTLw_MC.D1/IN3  (
    .I(U2_ADDR_reg[4]),
    .O(\NlwInverterSignal_DCORENCCTLw_MC.D1/IN3 )
  );
  X_INV \NlwInverterBlock_DCORENCCTLw_MC.D1/IN4  (
    .I(U2_ADDR_reg[5]),
    .O(\NlwInverterSignal_DCORENCCTLw_MC.D1/IN4 )
  );
  X_INV \NlwInverterBlock_DCORENCCTLw_MC.D1/IN5  (
    .I(U2_ADDR_reg[6]),
    .O(\NlwInverterSignal_DCORENCCTLw_MC.D1/IN5 )
  );
  X_INV \NlwInverterBlock_DCORENCCTLw_MC.D1/IN6  (
    .I(U2_ADDR_reg[7]),
    .O(\NlwInverterSignal_DCORENCCTLw_MC.D1/IN6 )
  );
  X_INV \NlwInverterBlock_DCORENCCTLw_MC.D1/IN7  (
    .I(U2_ADDR_reg[3]),
    .O(\NlwInverterSignal_DCORENCCTLw_MC.D1/IN7 )
  );
  X_INV \NlwInverterBlock_DCORENCCTLw_MC.D1/IN9  (
    .I(U2_ADDR_reg[2]),
    .O(\NlwInverterSignal_DCORENCCTLw_MC.D1/IN9 )
  );
  X_INV \NlwInverterBlock_NET2482_MC.D2_PT_0/IN0  (
    .I(\MSPReset_II/UIM ),
    .O(\NlwInverterSignal_NET2482_MC.D2_PT_0/IN0 )
  );
  X_INV \NlwInverterBlock_NET2482_MC.D2_PT_1/IN2  (
    .I(DCORENCCTLw),
    .O(\NlwInverterSignal_NET2482_MC.D2_PT_1/IN2 )
  );
  X_INV \NlwInverterBlock_NET2482_MC.D2_PT_2/IN1  (
    .I(DCORIFGw),
    .O(\NlwInverterSignal_NET2482_MC.D2_PT_2/IN1 )
  );
  X_INV \NlwInverterBlock_NET2482_MC.D2_PT_2/IN2  (
    .I(DCORENCCTLw),
    .O(\NlwInverterSignal_NET2482_MC.D2_PT_2/IN2 )
  );
  X_INV \NlwInverterBlock_NET2482_MC.D2_PT_2/IN3  (
    .I(NET2482),
    .O(\NlwInverterSignal_NET2482_MC.D2_PT_2/IN3 )
  );
  X_INV \NlwInverterBlock_NET2482_MC.D2_PT_2/IN7  (
    .I(\U1/U4/HE0statelastr ),
    .O(\NlwInverterSignal_NET2482_MC.D2_PT_2/IN7 )
  );
  X_INV \NlwInverterBlock_NET2482_MC.D2_PT_3/IN1  (
    .I(DCORIFGw),
    .O(\NlwInverterSignal_NET2482_MC.D2_PT_3/IN1 )
  );
  X_INV \NlwInverterBlock_NET2482_MC.D2_PT_3/IN2  (
    .I(DCORENCCTLw),
    .O(\NlwInverterSignal_NET2482_MC.D2_PT_3/IN2 )
  );
  X_INV \NlwInverterBlock_NET2482_MC.D2_PT_3/IN3  (
    .I(NET2482),
    .O(\NlwInverterSignal_NET2482_MC.D2_PT_3/IN3 )
  );
  X_INV \NlwInverterBlock_NET2482_MC.D2_PT_3/IN4  (
    .I(\U1/U4/RF0r ),
    .O(\NlwInverterSignal_NET2482_MC.D2_PT_3/IN4 )
  );
  X_INV \NlwInverterBlock_NET2482_MC.D2_PT_3/IN6  (
    .I(\U1/U4/HE0stater ),
    .O(\NlwInverterSignal_NET2482_MC.D2_PT_3/IN6 )
  );
  X_INV \NlwInverterBlock_U1/U4/RF0r_MC.D2_PT_1/IN1  (
    .I(DCORENCCTLw),
    .O(\NlwInverterSignal_U1/U4/RF0r_MC.D2_PT_1/IN1 )
  );
  X_INV \NlwInverterBlock_U1/U4/E0r_MC.D2_PT_1/IN1  (
    .I(DCORENCCTLw),
    .O(\NlwInverterSignal_U1/U4/E0r_MC.D2_PT_1/IN1 )
  );
  X_INV \NlwInverterBlock_U1/U1/CurrState_Sreg0_FFD1_MC.D2_PT_0/IN3  (
    .I(\U1/U1/CurrState_Sreg0_FFD4 ),
    .O(\NlwInverterSignal_U1/U1/CurrState_Sreg0_FFD1_MC.D2_PT_0/IN3 )
  );
  X_INV \NlwInverterBlock_U1/U1/CurrState_Sreg0_FFD1_MC.D2_PT_1/IN2  (
    .I(\U1/U1/CurrState_Sreg0_FFD3 ),
    .O(\NlwInverterSignal_U1/U1/CurrState_Sreg0_FFD1_MC.D2_PT_1/IN2 )
  );
  X_INV \NlwInverterBlock_U1/U1/CurrState_Sreg0_FFD1_MC.D2_PT_1/IN3  (
    .I(\U1/U1/CurrState_Sreg0_FFD4 ),
    .O(\NlwInverterSignal_U1/U1/CurrState_Sreg0_FFD1_MC.D2_PT_1/IN3 )
  );
  X_INV \NlwInverterBlock_U1/U1/CurrState_Sreg0_FFD1_MC.D2_PT_2/IN1  (
    .I(\U1/U1/CurrState_Sreg0_FFD3 ),
    .O(\NlwInverterSignal_U1/U1/CurrState_Sreg0_FFD1_MC.D2_PT_2/IN1 )
  );
  X_INV \NlwInverterBlock_U1/U1/CurrState_Sreg0_FFD1_MC.D2_PT_2/IN2  (
    .I(\U1/U1/CurrState_Sreg0_FFD2 ),
    .O(\NlwInverterSignal_U1/U1/CurrState_Sreg0_FFD1_MC.D2_PT_2/IN2 )
  );
  X_INV \NlwInverterBlock_U1/U1/CurrState_Sreg0_FFD1_MC.D2_PT_2/IN3  (
    .I(\U1/U1/CurrState_Sreg0_FFD4 ),
    .O(\NlwInverterSignal_U1/U1/CurrState_Sreg0_FFD1_MC.D2_PT_2/IN3 )
  );
  X_INV \NlwInverterBlock_U1/U1/CurrState_Sreg0_FFD1_MC.D2_PT_2/IN4  (
    .I(\PhaseA_Encoder0_II/UIM ),
    .O(\NlwInverterSignal_U1/U1/CurrState_Sreg0_FFD1_MC.D2_PT_2/IN4 )
  );
  X_INV \NlwInverterBlock_U1/U1/CurrState_Sreg0_FFD3_MC.D2_PT_0/IN1  (
    .I(\U1/U1/CurrState_Sreg0_FFD1 ),
    .O(\NlwInverterSignal_U1/U1/CurrState_Sreg0_FFD3_MC.D2_PT_0/IN1 )
  );
  X_INV \NlwInverterBlock_U1/U1/CurrState_Sreg0_FFD3_MC.D2_PT_0/IN3  (
    .I(\U1/U1/CurrState_Sreg0_FFD2 ),
    .O(\NlwInverterSignal_U1/U1/CurrState_Sreg0_FFD3_MC.D2_PT_0/IN3 )
  );
  X_INV \NlwInverterBlock_U1/U1/CurrState_Sreg0_FFD3_MC.D2_PT_0/IN4  (
    .I(\U1/U1/CurrState_Sreg0_FFD4 ),
    .O(\NlwInverterSignal_U1/U1/CurrState_Sreg0_FFD3_MC.D2_PT_0/IN4 )
  );
  X_INV \NlwInverterBlock_U1/U1/CurrState_Sreg0_FFD3_MC.D2_PT_1/IN3  (
    .I(\U1/U1/CurrState_Sreg0_FFD4 ),
    .O(\NlwInverterSignal_U1/U1/CurrState_Sreg0_FFD3_MC.D2_PT_1/IN3 )
  );
  X_INV \NlwInverterBlock_U1/U1/CurrState_Sreg0_FFD3_MC.D2_PT_1/IN4  (
    .I(\PhaseA_Encoder0_II/UIM ),
    .O(\NlwInverterSignal_U1/U1/CurrState_Sreg0_FFD3_MC.D2_PT_1/IN4 )
  );
  X_INV \NlwInverterBlock_U1/U1/CurrState_Sreg0_FFD3_MC.D2_PT_2/IN3  (
    .I(\U1/U1/CurrState_Sreg0_FFD4 ),
    .O(\NlwInverterSignal_U1/U1/CurrState_Sreg0_FFD3_MC.D2_PT_2/IN3 )
  );
  X_INV \NlwInverterBlock_U1/U1/CurrState_Sreg0_FFD3_MC.D2_PT_2/IN5  (
    .I(\PhaseB_Encoder0_II/UIM ),
    .O(\NlwInverterSignal_U1/U1/CurrState_Sreg0_FFD3_MC.D2_PT_2/IN5 )
  );
  X_INV \NlwInverterBlock_U1/U1/CurrState_Sreg0_FFD3_MC.D2_PT_3/IN1  (
    .I(\U1/U1/CurrState_Sreg0_FFD1 ),
    .O(\NlwInverterSignal_U1/U1/CurrState_Sreg0_FFD3_MC.D2_PT_3/IN1 )
  );
  X_INV \NlwInverterBlock_U1/U1/CurrState_Sreg0_FFD3_MC.D2_PT_3/IN3  (
    .I(\U1/U1/CurrState_Sreg0_FFD4 ),
    .O(\NlwInverterSignal_U1/U1/CurrState_Sreg0_FFD3_MC.D2_PT_3/IN3 )
  );
  X_INV \NlwInverterBlock_U1/U1/CurrState_Sreg0_FFD2_MC.D2_PT_0/IN4  (
    .I(\U1/U1/CurrState_Sreg0_FFD4 ),
    .O(\NlwInverterSignal_U1/U1/CurrState_Sreg0_FFD2_MC.D2_PT_0/IN4 )
  );
  X_INV \NlwInverterBlock_U1/U1/CurrState_Sreg0_FFD2_MC.D2_PT_1/IN2  (
    .I(\U1/U1/CurrState_Sreg0_FFD3 ),
    .O(\NlwInverterSignal_U1/U1/CurrState_Sreg0_FFD2_MC.D2_PT_1/IN2 )
  );
  X_INV \NlwInverterBlock_U1/U1/CurrState_Sreg0_FFD2_MC.D2_PT_1/IN4  (
    .I(\U1/U1/CurrState_Sreg0_FFD4 ),
    .O(\NlwInverterSignal_U1/U1/CurrState_Sreg0_FFD2_MC.D2_PT_1/IN4 )
  );
  X_INV \NlwInverterBlock_U1/U1/CurrState_Sreg0_FFD2_MC.D2_PT_1/IN5  (
    .I(\PhaseB_Encoder0_II/UIM ),
    .O(\NlwInverterSignal_U1/U1/CurrState_Sreg0_FFD2_MC.D2_PT_1/IN5 )
  );
  X_INV \NlwInverterBlock_U1/U1/CurrState_Sreg0_FFD2_MC.D2_PT_2/IN2  (
    .I(\U1/U1/CurrState_Sreg0_FFD3 ),
    .O(\NlwInverterSignal_U1/U1/CurrState_Sreg0_FFD2_MC.D2_PT_2/IN2 )
  );
  X_INV \NlwInverterBlock_U1/U1/CurrState_Sreg0_FFD2_MC.D2_PT_2/IN3  (
    .I(\U1/U1/CurrState_Sreg0_FFD4 ),
    .O(\NlwInverterSignal_U1/U1/CurrState_Sreg0_FFD2_MC.D2_PT_2/IN3 )
  );
  X_INV \NlwInverterBlock_U1/U1/CurrState_Sreg0_FFD2_MC.D2_PT_3/IN3  (
    .I(\U1/U1/CurrState_Sreg0_FFD4 ),
    .O(\NlwInverterSignal_U1/U1/CurrState_Sreg0_FFD2_MC.D2_PT_3/IN3 )
  );
  X_INV \NlwInverterBlock_U1/U1/CurrState_Sreg0_FFD2_MC.D2_PT_3/IN5  (
    .I(\PhaseB_Encoder0_II/UIM ),
    .O(\NlwInverterSignal_U1/U1/CurrState_Sreg0_FFD2_MC.D2_PT_3/IN5 )
  );
  X_INV \NlwInverterBlock_U1/U1/CurrState_Sreg0_FFD2_MC.D2_PT_4/IN1  (
    .I(\U1/U1/CurrState_Sreg0_FFD1 ),
    .O(\NlwInverterSignal_U1/U1/CurrState_Sreg0_FFD2_MC.D2_PT_4/IN1 )
  );
  X_INV \NlwInverterBlock_U1/U1/CurrState_Sreg0_FFD2_MC.D2_PT_4/IN4  (
    .I(\U1/U1/CurrState_Sreg0_FFD4 ),
    .O(\NlwInverterSignal_U1/U1/CurrState_Sreg0_FFD2_MC.D2_PT_4/IN4 )
  );
  X_INV \NlwInverterBlock_U1/U1/CurrState_Sreg0_FFD2_MC.D2_PT_4/IN5  (
    .I(\PhaseB_Encoder0_II/UIM ),
    .O(\NlwInverterSignal_U1/U1/CurrState_Sreg0_FFD2_MC.D2_PT_4/IN5 )
  );
  X_INV \NlwInverterBlock_U1/U1/CurrState_Sreg0_FFD2_MC.D2_PT_5/IN1  (
    .I(\U1/U1/CurrState_Sreg0_FFD1 ),
    .O(\NlwInverterSignal_U1/U1/CurrState_Sreg0_FFD2_MC.D2_PT_5/IN1 )
  );
  X_INV \NlwInverterBlock_U1/U1/CurrState_Sreg0_FFD2_MC.D2_PT_5/IN3  (
    .I(\U1/U1/CurrState_Sreg0_FFD4 ),
    .O(\NlwInverterSignal_U1/U1/CurrState_Sreg0_FFD2_MC.D2_PT_5/IN3 )
  );
  X_INV \NlwInverterBlock_U1/U1/CurrState_Sreg0_FFD2_MC.D2_PT_6/IN1  (
    .I(\U1/U1/CurrState_Sreg0_FFD1 ),
    .O(\NlwInverterSignal_U1/U1/CurrState_Sreg0_FFD2_MC.D2_PT_6/IN1 )
  );
  X_INV \NlwInverterBlock_U1/U1/CurrState_Sreg0_FFD2_MC.D2_PT_6/IN2  (
    .I(\U1/U1/CurrState_Sreg0_FFD3 ),
    .O(\NlwInverterSignal_U1/U1/CurrState_Sreg0_FFD2_MC.D2_PT_6/IN2 )
  );
  X_INV \NlwInverterBlock_U1/U1/CurrState_Sreg0_FFD2_MC.D2_PT_6/IN4  (
    .I(\U1/U1/CurrState_Sreg0_FFD4 ),
    .O(\NlwInverterSignal_U1/U1/CurrState_Sreg0_FFD2_MC.D2_PT_6/IN4 )
  );
  X_INV \NlwInverterBlock_U1/U1/CurrState_Sreg0_FFD2_MC.D2_PT_7/IN1  (
    .I(\U1/U1/CurrState_Sreg0_FFD1 ),
    .O(\NlwInverterSignal_U1/U1/CurrState_Sreg0_FFD2_MC.D2_PT_7/IN1 )
  );
  X_INV \NlwInverterBlock_U1/U1/CurrState_Sreg0_FFD2_MC.D2_PT_7/IN2  (
    .I(\U1/U1/CurrState_Sreg0_FFD3 ),
    .O(\NlwInverterSignal_U1/U1/CurrState_Sreg0_FFD2_MC.D2_PT_7/IN2 )
  );
  X_INV \NlwInverterBlock_U1/U1/CurrState_Sreg0_FFD2_MC.D2_PT_7/IN3  (
    .I(\U1/U1/CurrState_Sreg0_FFD4 ),
    .O(\NlwInverterSignal_U1/U1/CurrState_Sreg0_FFD2_MC.D2_PT_7/IN3 )
  );
  X_INV \NlwInverterBlock_U1/U1/CurrState_Sreg0_FFD2_MC.D2_PT_7/IN5  (
    .I(\PhaseB_Encoder0_II/UIM ),
    .O(\NlwInverterSignal_U1/U1/CurrState_Sreg0_FFD2_MC.D2_PT_7/IN5 )
  );
  X_INV \NlwInverterBlock_U1/U1/CurrState_Sreg0_FFD4_MC.D1/IN1  (
    .I(\U1/U1/CurrState_Sreg0_FFD1 ),
    .O(\NlwInverterSignal_U1/U1/CurrState_Sreg0_FFD4_MC.D1/IN1 )
  );
  X_INV \NlwInverterBlock_U1/U1/CurrState_Sreg0_FFD4_MC.D1/IN3  (
    .I(\U1/U1/CurrState_Sreg0_FFD2 ),
    .O(\NlwInverterSignal_U1/U1/CurrState_Sreg0_FFD4_MC.D1/IN3 )
  );
  X_INV \NlwInverterBlock_U1/U1/CurrState_Sreg0_FFD4_MC.D1/IN4  (
    .I(\U1/U1/CurrState_Sreg0_FFD4 ),
    .O(\NlwInverterSignal_U1/U1/CurrState_Sreg0_FFD4_MC.D1/IN4 )
  );
  X_INV \NlwInverterBlock_U1/U1/CurrState_Sreg0_FFD4_MC.D1/IN5  (
    .I(\PhaseA_Encoder0_II/UIM ),
    .O(\NlwInverterSignal_U1/U1/CurrState_Sreg0_FFD4_MC.D1/IN5 )
  );
  X_INV \NlwInverterBlock_U1/U1/CurrState_Sreg0_FFD4_MC.D1/IN6  (
    .I(\PhaseB_Encoder0_II/UIM ),
    .O(\NlwInverterSignal_U1/U1/CurrState_Sreg0_FFD4_MC.D1/IN6 )
  );
  X_INV \NlwInverterBlock_N_PZ_982_MC.D1/IN1  (
    .I(\U1/Zero0 ),
    .O(\NlwInverterSignal_N_PZ_982_MC.D1/IN1 )
  );
  X_INV \NlwInverterBlock_N_PZ_1018_MC.D2_PT_0/IN0  (
    .I(DCORIFGw),
    .O(\NlwInverterSignal_N_PZ_1018_MC.D2_PT_0/IN0 )
  );
  X_INV \NlwInverterBlock_N_PZ_1018_MC.D2_PT_0/IN1  (
    .I(DCORENCCTLw),
    .O(\NlwInverterSignal_N_PZ_1018_MC.D2_PT_0/IN1 )
  );
  X_INV \NlwInverterBlock_N_PZ_1018_MC.D2_PT_0/IN2  (
    .I(NET2501),
    .O(\NlwInverterSignal_N_PZ_1018_MC.D2_PT_0/IN2 )
  );
  X_INV \NlwInverterBlock_N_PZ_1018_MC.D2_PT_0/IN4  (
    .I(\U1/U4/InEdge0r ),
    .O(\NlwInverterSignal_N_PZ_1018_MC.D2_PT_0/IN4 )
  );
  X_INV \NlwInverterBlock_N_PZ_1018_MC.D2_PT_1/IN0  (
    .I(DCORIFGw),
    .O(\NlwInverterSignal_N_PZ_1018_MC.D2_PT_1/IN0 )
  );
  X_INV \NlwInverterBlock_N_PZ_1018_MC.D2_PT_1/IN1  (
    .I(DCORENCCTLw),
    .O(\NlwInverterSignal_N_PZ_1018_MC.D2_PT_1/IN1 )
  );
  X_INV \NlwInverterBlock_N_PZ_1018_MC.D2_PT_1/IN2  (
    .I(NET2501),
    .O(\NlwInverterSignal_N_PZ_1018_MC.D2_PT_1/IN2 )
  );
  X_INV \NlwInverterBlock_N_PZ_1018_MC.D2_PT_1/IN3  (
    .I(\U1/U4/LatchEdge0r ),
    .O(\NlwInverterSignal_N_PZ_1018_MC.D2_PT_1/IN3 )
  );
  X_INV \NlwInverterBlock_N_PZ_1018_MC.D2_PT_1/IN5  (
    .I(\outDATA<6>\$WA3.UIM ),
    .O(\NlwInverterSignal_N_PZ_1018_MC.D2_PT_1/IN5 )
  );
  X_INV \NlwInverterBlock_NET2501_MC.D2_PT_1/IN3  (
    .I(DCORENCCTLw),
    .O(\NlwInverterSignal_NET2501_MC.D2_PT_1/IN3 )
  );
  X_INV \NlwInverterBlock_U1/U4/LatchEdge0r_MC.D2_PT_1/IN1  (
    .I(DCORENCCTLw),
    .O(\NlwInverterSignal_U1/U4/LatchEdge0r_MC.D2_PT_1/IN1 )
  );
  X_INV \NlwInverterBlock_U1/U4/Latch0r<8>_MC.D2_PT_0/IN2  (
    .I(N_PZ_1018),
    .O(\NlwInverterSignal_U1/U4/Latch0r<8>_MC.D2_PT_0/IN2 )
  );
  X_INV \NlwInverterBlock_U1/Channel0<8>_MC.D1/IN1  (
    .I(\U1/U2/location_Maddsub__n0000__n0075 [0]),
    .O(\NlwInverterSignal_U1/Channel0<8>_MC.D1/IN1 )
  );
  X_INV \NlwInverterBlock_U1/Channel0<8>_MC.D2_PT_0/IN0  (
    .I(N_PZ_982),
    .O(\NlwInverterSignal_U1/Channel0<8>_MC.D2_PT_0/IN0 )
  );
  X_INV \NlwInverterBlock_U1/Channel0<8>_MC.D2_PT_1/IN0  (
    .I(N_PZ_982),
    .O(\NlwInverterSignal_U1/Channel0<8>_MC.D2_PT_1/IN0 )
  );
  X_INV \NlwInverterBlock_U1/Channel0<8>_MC.D2_PT_1/IN2  (
    .I(N_PZ_1024),
    .O(\NlwInverterSignal_U1/Channel0<8>_MC.D2_PT_1/IN2 )
  );
  X_INV \NlwInverterBlock_U1/Channel0<8>_MC.D2_PT_2/IN0  (
    .I(\U1/Channel0 [8]),
    .O(\NlwInverterSignal_U1/Channel0<8>_MC.D2_PT_2/IN0 )
  );
  X_INV \NlwInverterBlock_U1/Channel0<8>_MC.D2_PT_3/IN0  (
    .I(\U1/Channel0 [8]),
    .O(\NlwInverterSignal_U1/Channel0<8>_MC.D2_PT_3/IN0 )
  );
  X_INV \NlwInverterBlock_U1/Channel0<8>_MC.D2_PT_3/IN4  (
    .I(\U1/U2/location_Maddsub__n0000__n0067 [0]),
    .O(\NlwInverterSignal_U1/Channel0<8>_MC.D2_PT_3/IN4 )
  );
  X_INV \NlwInverterBlock_U1/Channel0<8>_MC.D2_PT_4/IN1  (
    .I(\U1/U2/location_Maddsub__n0000__n0075 [0]),
    .O(\NlwInverterSignal_U1/Channel0<8>_MC.D2_PT_4/IN1 )
  );
  X_INV \NlwInverterBlock_U1/Channel0<8>_MC.D2_PT_4/IN2  (
    .I(N_PZ_1024),
    .O(\NlwInverterSignal_U1/Channel0<8>_MC.D2_PT_4/IN2 )
  );
  X_INV \NlwInverterBlock_U1/Channel0<8>_MC.D2_PT_4/IN4  (
    .I(\U1/Channel0 [5]),
    .O(\NlwInverterSignal_U1/Channel0<8>_MC.D2_PT_4/IN4 )
  );
  X_INV \NlwInverterBlock_U1/Channel0<8>_MC.D2_PT_4/IN6  (
    .I(\U1/Channel0 [6]),
    .O(\NlwInverterSignal_U1/Channel0<8>_MC.D2_PT_4/IN6 )
  );
  X_INV \NlwInverterBlock_U1/Channel0<8>_MC.D2_PT_4/IN7  (
    .I(\U1/Channel0 [7]),
    .O(\NlwInverterSignal_U1/Channel0<8>_MC.D2_PT_4/IN7 )
  );
  X_INV \NlwInverterBlock_U1/Channel0<8>_MC.D2_PT_5/IN1  (
    .I(\U1/Zero0 ),
    .O(\NlwInverterSignal_U1/Channel0<8>_MC.D2_PT_5/IN1 )
  );
  X_INV \NlwInverterBlock_U1/Channel0<8>_MC.D2_PT_5/IN3  (
    .I(\U1/U2/location_Maddsub__n0000__n0075 [0]),
    .O(\NlwInverterSignal_U1/Channel0<8>_MC.D2_PT_5/IN3 )
  );
  X_INV \NlwInverterBlock_U1/Channel0<8>_MC.D2_PT_5/IN6  (
    .I(\U1/U2/location_Maddsub__n0000__n0067 [0]),
    .O(\NlwInverterSignal_U1/Channel0<8>_MC.D2_PT_5/IN6 )
  );
  X_INV \NlwInverterBlock_U1/Channel0<8>_MC.D2_PT_5/IN8  (
    .I(\U1/Channel0 [7]),
    .O(\NlwInverterSignal_U1/Channel0<8>_MC.D2_PT_5/IN8 )
  );
  X_INV \NlwInverterBlock_U1/U2/location_Maddsub__n0000__n0075<0>_MC.D2_PT_0/IN2  (
    .I(\U1/U2/location_Maddsub__n0000__n0067 [0]),
    .O(\NlwInverterSignal_U1/U2/location_Maddsub__n0000__n0075<0>_MC.D2_PT_0/IN2 )
  );
  X_INV \NlwInverterBlock_U1/U2/location_Maddsub__n0000__n0075<0>_MC.D2_PT_1/IN0  (
    .I(\U1/Channel0 [8]),
    .O(\NlwInverterSignal_U1/U2/location_Maddsub__n0000__n0075<0>_MC.D2_PT_1/IN0 )
  );
  X_INV \NlwInverterBlock_U1/U2/location_Maddsub__n0000__n0075<0>_MC.D2_PT_1/IN1  (
    .I(\U1/Channel0 [5]),
    .O(\NlwInverterSignal_U1/U2/location_Maddsub__n0000__n0075<0>_MC.D2_PT_1/IN1 )
  );
  X_INV \NlwInverterBlock_U1/U2/location_Maddsub__n0000__n0075<0>_MC.D2_PT_1/IN3  (
    .I(\U1/Channel0 [6]),
    .O(\NlwInverterSignal_U1/U2/location_Maddsub__n0000__n0075<0>_MC.D2_PT_1/IN3 )
  );
  X_INV \NlwInverterBlock_U1/U2/location_Maddsub__n0000__n0075<0>_MC.D2_PT_1/IN4  (
    .I(\U1/Channel0 [7]),
    .O(\NlwInverterSignal_U1/U2/location_Maddsub__n0000__n0075<0>_MC.D2_PT_1/IN4 )
  );
  X_INV \NlwInverterBlock_U1/U2/location_Maddsub__n0000__n0075<0>_MC.D2_PT_1/IN5  (
    .I(N_PZ_997),
    .O(\NlwInverterSignal_U1/U2/location_Maddsub__n0000__n0075<0>_MC.D2_PT_1/IN5 )
  );
  X_INV \NlwInverterBlock_N_PZ_997_MC.D2_PT_0/IN0  (
    .I(\U1/U1/CurrState_Sreg0_FFD1 ),
    .O(\NlwInverterSignal_N_PZ_997_MC.D2_PT_0/IN0 )
  );
  X_INV \NlwInverterBlock_N_PZ_997_MC.D2_PT_0/IN2  (
    .I(\U1/U1/CurrState_Sreg0_FFD2 ),
    .O(\NlwInverterSignal_N_PZ_997_MC.D2_PT_0/IN2 )
  );
  X_INV \NlwInverterBlock_N_PZ_997_MC.D2_PT_1/IN0  (
    .I(\U1/U1/CurrState_Sreg0_FFD1 ),
    .O(\NlwInverterSignal_N_PZ_997_MC.D2_PT_1/IN0 )
  );
  X_INV \NlwInverterBlock_N_PZ_997_MC.D2_PT_1/IN2  (
    .I(\U1/U1/CurrState_Sreg0_FFD4 ),
    .O(\NlwInverterSignal_N_PZ_997_MC.D2_PT_1/IN2 )
  );
  X_INV \NlwInverterBlock_U1/NET3721_MC.D2_PT_1/IN1  (
    .I(DCORENCCTLw),
    .O(\NlwInverterSignal_U1/NET3721_MC.D2_PT_1/IN1 )
  );
  X_INV \NlwInverterBlock_U1/Channel0<5>_MC.D2_PT_0/IN0  (
    .I(N_PZ_982),
    .O(\NlwInverterSignal_U1/Channel0<5>_MC.D2_PT_0/IN0 )
  );
  X_INV \NlwInverterBlock_U1/Channel0<5>_MC.D2_PT_1/IN1  (
    .I(\U1/U2/location_Maddsub__n0000__n0067 [0]),
    .O(\NlwInverterSignal_U1/Channel0<5>_MC.D2_PT_1/IN1 )
  );
  X_INV \NlwInverterBlock_U1/U2/location_Maddsub__n0000__n0067<0>_MC.D2_PT_1/IN0  (
    .I(\U1/Channel0 [0]),
    .O(\NlwInverterSignal_U1/U2/location_Maddsub__n0000__n0067<0>_MC.D2_PT_1/IN0 )
  );
  X_INV \NlwInverterBlock_U1/U2/location_Maddsub__n0000__n0067<0>_MC.D2_PT_1/IN1  (
    .I(N_PZ_997),
    .O(\NlwInverterSignal_U1/U2/location_Maddsub__n0000__n0067<0>_MC.D2_PT_1/IN1 )
  );
  X_INV \NlwInverterBlock_U1/U2/location_Maddsub__n0000__n0067<0>_MC.D2_PT_1/IN2  (
    .I(\U1/Channel0 [1]),
    .O(\NlwInverterSignal_U1/U2/location_Maddsub__n0000__n0067<0>_MC.D2_PT_1/IN2 )
  );
  X_INV \NlwInverterBlock_U1/U2/location_Maddsub__n0000__n0067<0>_MC.D2_PT_1/IN3  (
    .I(\U1/Channel0 [2]),
    .O(\NlwInverterSignal_U1/U2/location_Maddsub__n0000__n0067<0>_MC.D2_PT_1/IN3 )
  );
  X_INV \NlwInverterBlock_U1/U2/location_Maddsub__n0000__n0067<0>_MC.D2_PT_1/IN4  (
    .I(\U1/Channel0 [3]),
    .O(\NlwInverterSignal_U1/U2/location_Maddsub__n0000__n0067<0>_MC.D2_PT_1/IN4 )
  );
  X_INV \NlwInverterBlock_U1/U2/location_Maddsub__n0000__n0067<0>_MC.D2_PT_1/IN5  (
    .I(\U1/Channel0 [4]),
    .O(\NlwInverterSignal_U1/U2/location_Maddsub__n0000__n0067<0>_MC.D2_PT_1/IN5 )
  );
  X_INV \NlwInverterBlock_U1/Channel0<1>_MC.D2_PT_1/IN0  (
    .I(\U1/Channel0 [0]),
    .O(\NlwInverterSignal_U1/Channel0<1>_MC.D2_PT_1/IN0 )
  );
  X_INV \NlwInverterBlock_U1/Channel0<1>_MC.D2_PT_2/IN0  (
    .I(N_PZ_982),
    .O(\NlwInverterSignal_U1/Channel0<1>_MC.D2_PT_2/IN0 )
  );
  X_INV \NlwInverterBlock_N_PZ_1021_MC.D2_PT_0/IN1  (
    .I(\U1/Zero0 ),
    .O(\NlwInverterSignal_N_PZ_1021_MC.D2_PT_0/IN1 )
  );
  X_INV \NlwInverterBlock_N_PZ_1021_MC.D2_PT_0/IN4  (
    .I(\U1/U1/CurrState_Sreg0_FFD2 ),
    .O(\NlwInverterSignal_N_PZ_1021_MC.D2_PT_0/IN4 )
  );
  X_INV \NlwInverterBlock_N_PZ_1021_MC.D2_PT_0/IN5  (
    .I(\U1/U1/CurrState_Sreg0_FFD4 ),
    .O(\NlwInverterSignal_N_PZ_1021_MC.D2_PT_0/IN5 )
  );
  X_INV \NlwInverterBlock_N_PZ_1021_MC.D2_PT_0/IN6  (
    .I(\U1/NET3721 ),
    .O(\NlwInverterSignal_N_PZ_1021_MC.D2_PT_0/IN6 )
  );
  X_INV \NlwInverterBlock_N_PZ_1021_MC.D2_PT_1/IN1  (
    .I(\U1/Zero0 ),
    .O(\NlwInverterSignal_N_PZ_1021_MC.D2_PT_1/IN1 )
  );
  X_INV \NlwInverterBlock_N_PZ_1021_MC.D2_PT_1/IN2  (
    .I(\U1/U1/CurrState_Sreg0_FFD1 ),
    .O(\NlwInverterSignal_N_PZ_1021_MC.D2_PT_1/IN2 )
  );
  X_INV \NlwInverterBlock_N_PZ_1021_MC.D2_PT_1/IN4  (
    .I(\U1/U1/CurrState_Sreg0_FFD2 ),
    .O(\NlwInverterSignal_N_PZ_1021_MC.D2_PT_1/IN4 )
  );
  X_INV \NlwInverterBlock_N_PZ_1024_MC.D2_PT_0/IN1  (
    .I(\U1/Zero0 ),
    .O(\NlwInverterSignal_N_PZ_1024_MC.D2_PT_0/IN1 )
  );
  X_INV \NlwInverterBlock_N_PZ_1024_MC.D2_PT_0/IN4  (
    .I(\U1/U1/CurrState_Sreg0_FFD2 ),
    .O(\NlwInverterSignal_N_PZ_1024_MC.D2_PT_0/IN4 )
  );
  X_INV \NlwInverterBlock_N_PZ_1024_MC.D2_PT_0/IN5  (
    .I(\U1/U1/CurrState_Sreg0_FFD4 ),
    .O(\NlwInverterSignal_N_PZ_1024_MC.D2_PT_0/IN5 )
  );
  X_INV \NlwInverterBlock_N_PZ_1024_MC.D2_PT_1/IN1  (
    .I(\U1/Zero0 ),
    .O(\NlwInverterSignal_N_PZ_1024_MC.D2_PT_1/IN1 )
  );
  X_INV \NlwInverterBlock_N_PZ_1024_MC.D2_PT_1/IN2  (
    .I(\U1/U1/CurrState_Sreg0_FFD1 ),
    .O(\NlwInverterSignal_N_PZ_1024_MC.D2_PT_1/IN2 )
  );
  X_INV \NlwInverterBlock_N_PZ_1024_MC.D2_PT_1/IN4  (
    .I(\U1/U1/CurrState_Sreg0_FFD2 ),
    .O(\NlwInverterSignal_N_PZ_1024_MC.D2_PT_1/IN4 )
  );
  X_INV \NlwInverterBlock_N_PZ_1024_MC.D2_PT_1/IN6  (
    .I(\U1/NET3721 ),
    .O(\NlwInverterSignal_N_PZ_1024_MC.D2_PT_1/IN6 )
  );
  X_INV \NlwInverterBlock_U1/Channel0<2>_MC.D2_PT_0/IN0  (
    .I(N_PZ_982),
    .O(\NlwInverterSignal_U1/Channel0<2>_MC.D2_PT_0/IN0 )
  );
  X_INV \NlwInverterBlock_U1/Channel0<2>_MC.D2_PT_2/IN0  (
    .I(\U1/Channel0 [0]),
    .O(\NlwInverterSignal_U1/Channel0<2>_MC.D2_PT_2/IN0 )
  );
  X_INV \NlwInverterBlock_U1/Channel0<2>_MC.D2_PT_2/IN2  (
    .I(\U1/Channel0 [1]),
    .O(\NlwInverterSignal_U1/Channel0<2>_MC.D2_PT_2/IN2 )
  );
  X_INV \NlwInverterBlock_U1/Channel0<3>_MC.D2_PT_0/IN0  (
    .I(N_PZ_982),
    .O(\NlwInverterSignal_U1/Channel0<3>_MC.D2_PT_0/IN0 )
  );
  X_INV \NlwInverterBlock_U1/Channel0<3>_MC.D2_PT_2/IN0  (
    .I(\U1/Channel0 [0]),
    .O(\NlwInverterSignal_U1/Channel0<3>_MC.D2_PT_2/IN0 )
  );
  X_INV \NlwInverterBlock_U1/Channel0<3>_MC.D2_PT_2/IN2  (
    .I(\U1/Channel0 [1]),
    .O(\NlwInverterSignal_U1/Channel0<3>_MC.D2_PT_2/IN2 )
  );
  X_INV \NlwInverterBlock_U1/Channel0<3>_MC.D2_PT_2/IN3  (
    .I(\U1/Channel0 [2]),
    .O(\NlwInverterSignal_U1/Channel0<3>_MC.D2_PT_2/IN3 )
  );
  X_INV \NlwInverterBlock_U1/Channel0<4>_MC.D1/IN1  (
    .I(\U1/U2/location_Maddsub__n0000__n0067 [0]),
    .O(\NlwInverterSignal_U1/Channel0<4>_MC.D1/IN1 )
  );
  X_INV \NlwInverterBlock_U1/Channel0<4>_MC.D2_PT_0/IN0  (
    .I(N_PZ_982),
    .O(\NlwInverterSignal_U1/Channel0<4>_MC.D2_PT_0/IN0 )
  );
  X_INV \NlwInverterBlock_U1/Channel0<4>_MC.D2_PT_0/IN1  (
    .I(N_PZ_1024),
    .O(\NlwInverterSignal_U1/Channel0<4>_MC.D2_PT_0/IN1 )
  );
  X_INV \NlwInverterBlock_U1/Channel0<4>_MC.D2_PT_1/IN0  (
    .I(N_PZ_982),
    .O(\NlwInverterSignal_U1/Channel0<4>_MC.D2_PT_1/IN0 )
  );
  X_INV \NlwInverterBlock_U1/Channel0<4>_MC.D2_PT_2/IN2  (
    .I(\U1/Channel0 [4]),
    .O(\NlwInverterSignal_U1/Channel0<4>_MC.D2_PT_2/IN2 )
  );
  X_INV \NlwInverterBlock_U1/Channel0<4>_MC.D2_PT_3/IN6  (
    .I(\U1/Channel0 [4]),
    .O(\NlwInverterSignal_U1/Channel0<4>_MC.D2_PT_3/IN6 )
  );
  X_INV \NlwInverterBlock_U1/Channel0<4>_MC.D2_PT_4/IN0  (
    .I(\U1/Channel0 [0]),
    .O(\NlwInverterSignal_U1/Channel0<4>_MC.D2_PT_4/IN0 )
  );
  X_INV \NlwInverterBlock_U1/Channel0<4>_MC.D2_PT_4/IN1  (
    .I(N_PZ_1024),
    .O(\NlwInverterSignal_U1/Channel0<4>_MC.D2_PT_4/IN1 )
  );
  X_INV \NlwInverterBlock_U1/Channel0<4>_MC.D2_PT_4/IN3  (
    .I(\U1/U2/location_Maddsub__n0000__n0067 [0]),
    .O(\NlwInverterSignal_U1/Channel0<4>_MC.D2_PT_4/IN3 )
  );
  X_INV \NlwInverterBlock_U1/Channel0<4>_MC.D2_PT_4/IN4  (
    .I(\U1/Channel0 [1]),
    .O(\NlwInverterSignal_U1/Channel0<4>_MC.D2_PT_4/IN4 )
  );
  X_INV \NlwInverterBlock_U1/Channel0<4>_MC.D2_PT_4/IN5  (
    .I(\U1/Channel0 [2]),
    .O(\NlwInverterSignal_U1/Channel0<4>_MC.D2_PT_4/IN5 )
  );
  X_INV \NlwInverterBlock_U1/Channel0<4>_MC.D2_PT_4/IN6  (
    .I(\U1/Channel0 [3]),
    .O(\NlwInverterSignal_U1/Channel0<4>_MC.D2_PT_4/IN6 )
  );
  X_INV \NlwInverterBlock_U1/Channel0<4>_MC.D2_PT_5/IN2  (
    .I(\U1/Zero0 ),
    .O(\NlwInverterSignal_U1/Channel0<4>_MC.D2_PT_5/IN2 )
  );
  X_INV \NlwInverterBlock_U1/Channel0<4>_MC.D2_PT_5/IN4  (
    .I(\U1/U2/location_Maddsub__n0000__n0067 [0]),
    .O(\NlwInverterSignal_U1/Channel0<4>_MC.D2_PT_5/IN4 )
  );
  X_INV \NlwInverterBlock_U1/Channel0<4>_MC.D2_PT_5/IN7  (
    .I(\U1/Channel0 [3]),
    .O(\NlwInverterSignal_U1/Channel0<4>_MC.D2_PT_5/IN7 )
  );
  X_INV \NlwInverterBlock_U1/Channel0<6>_MC.D2_PT_0/IN0  (
    .I(N_PZ_982),
    .O(\NlwInverterSignal_U1/Channel0<6>_MC.D2_PT_0/IN0 )
  );
  X_INV \NlwInverterBlock_U1/Channel0<6>_MC.D2_PT_1/IN2  (
    .I(\U1/U2/location_Maddsub__n0000__n0067 [0]),
    .O(\NlwInverterSignal_U1/Channel0<6>_MC.D2_PT_1/IN2 )
  );
  X_INV \NlwInverterBlock_U1/Channel0<6>_MC.D2_PT_2/IN1  (
    .I(\U1/Channel0 [5]),
    .O(\NlwInverterSignal_U1/Channel0<6>_MC.D2_PT_2/IN1 )
  );
  X_INV \NlwInverterBlock_U1/Channel0<7>_MC.D2_PT_0/IN0  (
    .I(N_PZ_982),
    .O(\NlwInverterSignal_U1/Channel0<7>_MC.D2_PT_0/IN0 )
  );
  X_INV \NlwInverterBlock_U1/Channel0<7>_MC.D2_PT_1/IN2  (
    .I(\U1/U2/location_Maddsub__n0000__n0067 [0]),
    .O(\NlwInverterSignal_U1/Channel0<7>_MC.D2_PT_1/IN2 )
  );
  X_INV \NlwInverterBlock_U1/Channel0<7>_MC.D2_PT_2/IN1  (
    .I(\U1/Channel0 [5]),
    .O(\NlwInverterSignal_U1/Channel0<7>_MC.D2_PT_2/IN1 )
  );
  X_INV \NlwInverterBlock_U1/Channel0<7>_MC.D2_PT_2/IN3  (
    .I(\U1/Channel0 [6]),
    .O(\NlwInverterSignal_U1/Channel0<7>_MC.D2_PT_2/IN3 )
  );
  X_INV \NlwInverterBlock_DCOR0THRESHIGHr_MC.D1/IN1  (
    .I(\RD_II/UIM ),
    .O(\NlwInverterSignal_DCOR0THRESHIGHr_MC.D1/IN1 )
  );
  X_INV \NlwInverterBlock_DCOR0THRESHIGHr_MC.D1/IN3  (
    .I(U2_ADDR_reg[4]),
    .O(\NlwInverterSignal_DCOR0THRESHIGHr_MC.D1/IN3 )
  );
  X_INV \NlwInverterBlock_DCOR0THRESHIGHr_MC.D1/IN4  (
    .I(U2_ADDR_reg[5]),
    .O(\NlwInverterSignal_DCOR0THRESHIGHr_MC.D1/IN4 )
  );
  X_INV \NlwInverterBlock_DCOR0THRESHIGHr_MC.D1/IN5  (
    .I(U2_ADDR_reg[6]),
    .O(\NlwInverterSignal_DCOR0THRESHIGHr_MC.D1/IN5 )
  );
  X_INV \NlwInverterBlock_DCOR0THRESHIGHr_MC.D1/IN6  (
    .I(U2_ADDR_reg[7]),
    .O(\NlwInverterSignal_DCOR0THRESHIGHr_MC.D1/IN6 )
  );
  X_INV \NlwInverterBlock_DCOR0THRESHIGHr_MC.D1/IN8  (
    .I(U2_ADDR_reg[1]),
    .O(\NlwInverterSignal_DCOR0THRESHIGHr_MC.D1/IN8 )
  );
  X_INV \NlwInverterBlock_DCOR0THRESHIGHr_MC.D1/IN9  (
    .I(U2_ADDR_reg[2]),
    .O(\NlwInverterSignal_DCOR0THRESHIGHr_MC.D1/IN9 )
  );
  X_INV \NlwInverterBlock_U1/U4/Latch1r<0>_MC.D2_PT_0/IN2  (
    .I(N_PZ_1019),
    .O(\NlwInverterSignal_U1/U4/Latch1r<0>_MC.D2_PT_0/IN2 )
  );
  X_INV \NlwInverterBlock_U1/Channel1<0>_MC.D2_PT_0/IN1  (
    .I(N_PZ_983),
    .O(\NlwInverterSignal_U1/Channel1<0>_MC.D2_PT_0/IN1 )
  );
  X_INV \NlwInverterBlock_U1/Channel1<0>_MC.D2_PT_1/IN1  (
    .I(\U1/Zero1 ),
    .O(\NlwInverterSignal_U1/Channel1<0>_MC.D2_PT_1/IN1 )
  );
  X_INV \NlwInverterBlock_U1/Channel1<0>_MC.D2_PT_1/IN3  (
    .I(\U1/U6/CurrState_Sreg0_FFD2 ),
    .O(\NlwInverterSignal_U1/Channel1<0>_MC.D2_PT_1/IN3 )
  );
  X_INV \NlwInverterBlock_N_PZ_983_MC.D1/IN1  (
    .I(\U1/Zero1 ),
    .O(\NlwInverterSignal_N_PZ_983_MC.D1/IN1 )
  );
  X_INV \NlwInverterBlock_U1/Zero1_MC.D2_PT_0/IN0  (
    .I(\MSPReset_II/UIM ),
    .O(\NlwInverterSignal_U1/Zero1_MC.D2_PT_0/IN0 )
  );
  X_INV \NlwInverterBlock_U1/Zero1_MC.D2_PT_3/IN1  (
    .I(DCORIFGw),
    .O(\NlwInverterSignal_U1/Zero1_MC.D2_PT_3/IN1 )
  );
  X_INV \NlwInverterBlock_U1/Zero1_MC.D2_PT_3/IN2  (
    .I(DCORENCCTLw),
    .O(\NlwInverterSignal_U1/Zero1_MC.D2_PT_3/IN2 )
  );
  X_INV \NlwInverterBlock_U1/Zero1_MC.D2_PT_3/IN3  (
    .I(NET2493),
    .O(\NlwInverterSignal_U1/Zero1_MC.D2_PT_3/IN3 )
  );
  X_INV \NlwInverterBlock_U1/Zero1_MC.D2_PT_3/IN7  (
    .I(\U1/U4/HE1statelastr ),
    .O(\NlwInverterSignal_U1/Zero1_MC.D2_PT_3/IN7 )
  );
  X_INV \NlwInverterBlock_U1/Zero1_MC.D2_PT_4/IN1  (
    .I(DCORIFGw),
    .O(\NlwInverterSignal_U1/Zero1_MC.D2_PT_4/IN1 )
  );
  X_INV \NlwInverterBlock_U1/Zero1_MC.D2_PT_4/IN2  (
    .I(DCORENCCTLw),
    .O(\NlwInverterSignal_U1/Zero1_MC.D2_PT_4/IN2 )
  );
  X_INV \NlwInverterBlock_U1/Zero1_MC.D2_PT_4/IN3  (
    .I(NET2493),
    .O(\NlwInverterSignal_U1/Zero1_MC.D2_PT_4/IN3 )
  );
  X_INV \NlwInverterBlock_U1/Zero1_MC.D2_PT_4/IN4  (
    .I(\U1/U4/RF1r ),
    .O(\NlwInverterSignal_U1/Zero1_MC.D2_PT_4/IN4 )
  );
  X_INV \NlwInverterBlock_U1/Zero1_MC.D2_PT_4/IN6  (
    .I(\U1/U4/HE1stater ),
    .O(\NlwInverterSignal_U1/Zero1_MC.D2_PT_4/IN6 )
  );
  X_INV \NlwInverterBlock_NET2493_MC.D2_PT_0/IN0  (
    .I(\MSPReset_II/UIM ),
    .O(\NlwInverterSignal_NET2493_MC.D2_PT_0/IN0 )
  );
  X_INV \NlwInverterBlock_NET2493_MC.D2_PT_1/IN2  (
    .I(DCORENCCTLw),
    .O(\NlwInverterSignal_NET2493_MC.D2_PT_1/IN2 )
  );
  X_INV \NlwInverterBlock_NET2493_MC.D2_PT_2/IN1  (
    .I(DCORIFGw),
    .O(\NlwInverterSignal_NET2493_MC.D2_PT_2/IN1 )
  );
  X_INV \NlwInverterBlock_NET2493_MC.D2_PT_2/IN2  (
    .I(DCORENCCTLw),
    .O(\NlwInverterSignal_NET2493_MC.D2_PT_2/IN2 )
  );
  X_INV \NlwInverterBlock_NET2493_MC.D2_PT_2/IN3  (
    .I(NET2493),
    .O(\NlwInverterSignal_NET2493_MC.D2_PT_2/IN3 )
  );
  X_INV \NlwInverterBlock_NET2493_MC.D2_PT_2/IN7  (
    .I(\U1/U4/HE1statelastr ),
    .O(\NlwInverterSignal_NET2493_MC.D2_PT_2/IN7 )
  );
  X_INV \NlwInverterBlock_NET2493_MC.D2_PT_3/IN1  (
    .I(DCORIFGw),
    .O(\NlwInverterSignal_NET2493_MC.D2_PT_3/IN1 )
  );
  X_INV \NlwInverterBlock_NET2493_MC.D2_PT_3/IN2  (
    .I(DCORENCCTLw),
    .O(\NlwInverterSignal_NET2493_MC.D2_PT_3/IN2 )
  );
  X_INV \NlwInverterBlock_NET2493_MC.D2_PT_3/IN3  (
    .I(NET2493),
    .O(\NlwInverterSignal_NET2493_MC.D2_PT_3/IN3 )
  );
  X_INV \NlwInverterBlock_NET2493_MC.D2_PT_3/IN4  (
    .I(\U1/U4/RF1r ),
    .O(\NlwInverterSignal_NET2493_MC.D2_PT_3/IN4 )
  );
  X_INV \NlwInverterBlock_NET2493_MC.D2_PT_3/IN6  (
    .I(\U1/U4/HE1stater ),
    .O(\NlwInverterSignal_NET2493_MC.D2_PT_3/IN6 )
  );
  X_INV \NlwInverterBlock_U1/U4/RF1r_MC.D2_PT_1/IN1  (
    .I(DCORENCCTLw),
    .O(\NlwInverterSignal_U1/U4/RF1r_MC.D2_PT_1/IN1 )
  );
  X_INV \NlwInverterBlock_U1/U4/E1r_MC.D2_PT_1/IN1  (
    .I(DCORENCCTLw),
    .O(\NlwInverterSignal_U1/U4/E1r_MC.D2_PT_1/IN1 )
  );
  X_INV \NlwInverterBlock_U1/U6/CurrState_Sreg0_FFD3_MC.D2_PT_0/IN3  (
    .I(\PhaseA_Encoder1_II/UIM ),
    .O(\NlwInverterSignal_U1/U6/CurrState_Sreg0_FFD3_MC.D2_PT_0/IN3 )
  );
  X_INV \NlwInverterBlock_U1/U6/CurrState_Sreg0_FFD3_MC.D2_PT_0/IN4  (
    .I(\U1/U6/CurrState_Sreg0_FFD4 ),
    .O(\NlwInverterSignal_U1/U6/CurrState_Sreg0_FFD3_MC.D2_PT_0/IN4 )
  );
  X_INV \NlwInverterBlock_U1/U6/CurrState_Sreg0_FFD3_MC.D2_PT_1/IN2  (
    .I(\U1/U6/CurrState_Sreg0_FFD2 ),
    .O(\NlwInverterSignal_U1/U6/CurrState_Sreg0_FFD3_MC.D2_PT_1/IN2 )
  );
  X_INV \NlwInverterBlock_U1/U6/CurrState_Sreg0_FFD3_MC.D2_PT_1/IN3  (
    .I(\U1/U6/CurrState_Sreg0_FFD4 ),
    .O(\NlwInverterSignal_U1/U6/CurrState_Sreg0_FFD3_MC.D2_PT_1/IN3 )
  );
  X_INV \NlwInverterBlock_U1/U6/CurrState_Sreg0_FFD3_MC.D2_PT_1/IN4  (
    .I(\U1/U6/CurrState_Sreg0_FFD1 ),
    .O(\NlwInverterSignal_U1/U6/CurrState_Sreg0_FFD3_MC.D2_PT_1/IN4 )
  );
  X_INV \NlwInverterBlock_U1/U6/CurrState_Sreg0_FFD3_MC.D2_PT_2/IN3  (
    .I(\U1/U6/CurrState_Sreg0_FFD4 ),
    .O(\NlwInverterSignal_U1/U6/CurrState_Sreg0_FFD3_MC.D2_PT_2/IN3 )
  );
  X_INV \NlwInverterBlock_U1/U6/CurrState_Sreg0_FFD3_MC.D2_PT_2/IN5  (
    .I(\PhaseB_Encoder1_II/UIM ),
    .O(\NlwInverterSignal_U1/U6/CurrState_Sreg0_FFD3_MC.D2_PT_2/IN5 )
  );
  X_INV \NlwInverterBlock_U1/U6/CurrState_Sreg0_FFD3_MC.D2_PT_3/IN3  (
    .I(\U1/U6/CurrState_Sreg0_FFD4 ),
    .O(\NlwInverterSignal_U1/U6/CurrState_Sreg0_FFD3_MC.D2_PT_3/IN3 )
  );
  X_INV \NlwInverterBlock_U1/U6/CurrState_Sreg0_FFD3_MC.D2_PT_3/IN4  (
    .I(\U1/U6/CurrState_Sreg0_FFD1 ),
    .O(\NlwInverterSignal_U1/U6/CurrState_Sreg0_FFD3_MC.D2_PT_3/IN4 )
  );
  X_INV \NlwInverterBlock_U1/U6/CurrState_Sreg0_FFD1_MC.D2_PT_0/IN2  (
    .I(\U1/U6/CurrState_Sreg0_FFD4 ),
    .O(\NlwInverterSignal_U1/U6/CurrState_Sreg0_FFD1_MC.D2_PT_0/IN2 )
  );
  X_INV \NlwInverterBlock_U1/U6/CurrState_Sreg0_FFD1_MC.D2_PT_1/IN1  (
    .I(\U1/U6/CurrState_Sreg0_FFD3 ),
    .O(\NlwInverterSignal_U1/U6/CurrState_Sreg0_FFD1_MC.D2_PT_1/IN1 )
  );
  X_INV \NlwInverterBlock_U1/U6/CurrState_Sreg0_FFD1_MC.D2_PT_1/IN3  (
    .I(\U1/U6/CurrState_Sreg0_FFD4 ),
    .O(\NlwInverterSignal_U1/U6/CurrState_Sreg0_FFD1_MC.D2_PT_1/IN3 )
  );
  X_INV \NlwInverterBlock_U1/U6/CurrState_Sreg0_FFD1_MC.D2_PT_2/IN1  (
    .I(\U1/U6/CurrState_Sreg0_FFD3 ),
    .O(\NlwInverterSignal_U1/U6/CurrState_Sreg0_FFD1_MC.D2_PT_2/IN1 )
  );
  X_INV \NlwInverterBlock_U1/U6/CurrState_Sreg0_FFD1_MC.D2_PT_2/IN2  (
    .I(\U1/U6/CurrState_Sreg0_FFD2 ),
    .O(\NlwInverterSignal_U1/U6/CurrState_Sreg0_FFD1_MC.D2_PT_2/IN2 )
  );
  X_INV \NlwInverterBlock_U1/U6/CurrState_Sreg0_FFD1_MC.D2_PT_2/IN3  (
    .I(\PhaseA_Encoder1_II/UIM ),
    .O(\NlwInverterSignal_U1/U6/CurrState_Sreg0_FFD1_MC.D2_PT_2/IN3 )
  );
  X_INV \NlwInverterBlock_U1/U6/CurrState_Sreg0_FFD1_MC.D2_PT_2/IN4  (
    .I(\U1/U6/CurrState_Sreg0_FFD4 ),
    .O(\NlwInverterSignal_U1/U6/CurrState_Sreg0_FFD1_MC.D2_PT_2/IN4 )
  );
  X_INV \NlwInverterBlock_U1/U6/CurrState_Sreg0_FFD4_MC.D1/IN2  (
    .I(\U1/U6/CurrState_Sreg0_FFD2 ),
    .O(\NlwInverterSignal_U1/U6/CurrState_Sreg0_FFD4_MC.D1/IN2 )
  );
  X_INV \NlwInverterBlock_U1/U6/CurrState_Sreg0_FFD4_MC.D1/IN3  (
    .I(\PhaseA_Encoder1_II/UIM ),
    .O(\NlwInverterSignal_U1/U6/CurrState_Sreg0_FFD4_MC.D1/IN3 )
  );
  X_INV \NlwInverterBlock_U1/U6/CurrState_Sreg0_FFD4_MC.D1/IN4  (
    .I(\U1/U6/CurrState_Sreg0_FFD4 ),
    .O(\NlwInverterSignal_U1/U6/CurrState_Sreg0_FFD4_MC.D1/IN4 )
  );
  X_INV \NlwInverterBlock_U1/U6/CurrState_Sreg0_FFD4_MC.D1/IN5  (
    .I(\U1/U6/CurrState_Sreg0_FFD1 ),
    .O(\NlwInverterSignal_U1/U6/CurrState_Sreg0_FFD4_MC.D1/IN5 )
  );
  X_INV \NlwInverterBlock_U1/U6/CurrState_Sreg0_FFD4_MC.D1/IN6  (
    .I(\PhaseB_Encoder1_II/UIM ),
    .O(\NlwInverterSignal_U1/U6/CurrState_Sreg0_FFD4_MC.D1/IN6 )
  );
  X_INV \NlwInverterBlock_U1/U6/CurrState_Sreg0_FFD2_MC.D2_PT_0/IN3  (
    .I(\U1/U6/CurrState_Sreg0_FFD4 ),
    .O(\NlwInverterSignal_U1/U6/CurrState_Sreg0_FFD2_MC.D2_PT_0/IN3 )
  );
  X_INV \NlwInverterBlock_U1/U6/CurrState_Sreg0_FFD2_MC.D2_PT_1/IN3  (
    .I(\U1/U6/CurrState_Sreg0_FFD4 ),
    .O(\NlwInverterSignal_U1/U6/CurrState_Sreg0_FFD2_MC.D2_PT_1/IN3 )
  );
  X_INV \NlwInverterBlock_U1/U6/CurrState_Sreg0_FFD2_MC.D2_PT_1/IN4  (
    .I(\U1/U6/CurrState_Sreg0_FFD1 ),
    .O(\NlwInverterSignal_U1/U6/CurrState_Sreg0_FFD2_MC.D2_PT_1/IN4 )
  );
  X_INV \NlwInverterBlock_U1/U6/CurrState_Sreg0_FFD2_MC.D2_PT_1/IN5  (
    .I(\PhaseB_Encoder1_II/UIM ),
    .O(\NlwInverterSignal_U1/U6/CurrState_Sreg0_FFD2_MC.D2_PT_1/IN5 )
  );
  X_INV \NlwInverterBlock_U1/U6/CurrState_Sreg0_FFD2_MC.D2_PT_2/IN3  (
    .I(\U1/U6/CurrState_Sreg0_FFD4 ),
    .O(\NlwInverterSignal_U1/U6/CurrState_Sreg0_FFD2_MC.D2_PT_2/IN3 )
  );
  X_INV \NlwInverterBlock_U1/U6/CurrState_Sreg0_FFD2_MC.D2_PT_2/IN4  (
    .I(\U1/U6/CurrState_Sreg0_FFD1 ),
    .O(\NlwInverterSignal_U1/U6/CurrState_Sreg0_FFD2_MC.D2_PT_2/IN4 )
  );
  X_INV \NlwInverterBlock_U1/U6/CurrState_Sreg0_FFD2_MC.D2_PT_3/IN1  (
    .I(\U1/U6/CurrState_Sreg0_FFD3 ),
    .O(\NlwInverterSignal_U1/U6/CurrState_Sreg0_FFD2_MC.D2_PT_3/IN1 )
  );
  X_INV \NlwInverterBlock_U1/U6/CurrState_Sreg0_FFD2_MC.D2_PT_3/IN3  (
    .I(\U1/U6/CurrState_Sreg0_FFD4 ),
    .O(\NlwInverterSignal_U1/U6/CurrState_Sreg0_FFD2_MC.D2_PT_3/IN3 )
  );
  X_INV \NlwInverterBlock_U1/U6/CurrState_Sreg0_FFD2_MC.D2_PT_3/IN5  (
    .I(\PhaseB_Encoder1_II/UIM ),
    .O(\NlwInverterSignal_U1/U6/CurrState_Sreg0_FFD2_MC.D2_PT_3/IN5 )
  );
  X_INV \NlwInverterBlock_U1/U6/CurrState_Sreg0_FFD2_MC.D2_PT_4/IN1  (
    .I(\U1/U6/CurrState_Sreg0_FFD3 ),
    .O(\NlwInverterSignal_U1/U6/CurrState_Sreg0_FFD2_MC.D2_PT_4/IN1 )
  );
  X_INV \NlwInverterBlock_U1/U6/CurrState_Sreg0_FFD2_MC.D2_PT_4/IN3  (
    .I(\U1/U6/CurrState_Sreg0_FFD4 ),
    .O(\NlwInverterSignal_U1/U6/CurrState_Sreg0_FFD2_MC.D2_PT_4/IN3 )
  );
  X_INV \NlwInverterBlock_U1/U6/CurrState_Sreg0_FFD2_MC.D2_PT_4/IN4  (
    .I(\U1/U6/CurrState_Sreg0_FFD1 ),
    .O(\NlwInverterSignal_U1/U6/CurrState_Sreg0_FFD2_MC.D2_PT_4/IN4 )
  );
  X_INV \NlwInverterBlock_U1/U6/CurrState_Sreg0_FFD2_MC.D2_PT_5/IN1  (
    .I(\U1/U6/CurrState_Sreg0_FFD3 ),
    .O(\NlwInverterSignal_U1/U6/CurrState_Sreg0_FFD2_MC.D2_PT_5/IN1 )
  );
  X_INV \NlwInverterBlock_U1/U6/CurrState_Sreg0_FFD2_MC.D2_PT_5/IN3  (
    .I(\U1/U6/CurrState_Sreg0_FFD4 ),
    .O(\NlwInverterSignal_U1/U6/CurrState_Sreg0_FFD2_MC.D2_PT_5/IN3 )
  );
  X_INV \NlwInverterBlock_U1/U6/CurrState_Sreg0_FFD2_MC.D2_PT_6/IN1  (
    .I(\U1/U6/CurrState_Sreg0_FFD3 ),
    .O(\NlwInverterSignal_U1/U6/CurrState_Sreg0_FFD2_MC.D2_PT_6/IN1 )
  );
  X_INV \NlwInverterBlock_U1/U6/CurrState_Sreg0_FFD2_MC.D2_PT_6/IN3  (
    .I(\U1/U6/CurrState_Sreg0_FFD4 ),
    .O(\NlwInverterSignal_U1/U6/CurrState_Sreg0_FFD2_MC.D2_PT_6/IN3 )
  );
  X_INV \NlwInverterBlock_U1/U6/CurrState_Sreg0_FFD2_MC.D2_PT_6/IN4  (
    .I(\U1/U6/CurrState_Sreg0_FFD1 ),
    .O(\NlwInverterSignal_U1/U6/CurrState_Sreg0_FFD2_MC.D2_PT_6/IN4 )
  );
  X_INV \NlwInverterBlock_U1/U6/CurrState_Sreg0_FFD2_MC.D2_PT_6/IN5  (
    .I(\PhaseB_Encoder1_II/UIM ),
    .O(\NlwInverterSignal_U1/U6/CurrState_Sreg0_FFD2_MC.D2_PT_6/IN5 )
  );
  X_INV \NlwInverterBlock_U1/U6/CurrState_Sreg0_FFD2_MC.D2_PT_7/IN3  (
    .I(\U1/U6/CurrState_Sreg0_FFD4 ),
    .O(\NlwInverterSignal_U1/U6/CurrState_Sreg0_FFD2_MC.D2_PT_7/IN3 )
  );
  X_INV \NlwInverterBlock_U1/U6/CurrState_Sreg0_FFD2_MC.D2_PT_7/IN5  (
    .I(\PhaseB_Encoder1_II/UIM ),
    .O(\NlwInverterSignal_U1/U6/CurrState_Sreg0_FFD2_MC.D2_PT_7/IN5 )
  );
  X_INV \NlwInverterBlock_N_PZ_1154_MC.D2_PT_0/IN1  (
    .I(\U1/U6/CurrState_Sreg0_FFD1 ),
    .O(\NlwInverterSignal_N_PZ_1154_MC.D2_PT_0/IN1 )
  );
  X_INV \NlwInverterBlock_N_PZ_1154_MC.D2_PT_1/IN0  (
    .I(\U1/U6/CurrState_Sreg0_FFD4 ),
    .O(\NlwInverterSignal_N_PZ_1154_MC.D2_PT_1/IN0 )
  );
  X_INV \NlwInverterBlock_N_PZ_1019_MC.D2_PT_0/IN0  (
    .I(DCORIFGw),
    .O(\NlwInverterSignal_N_PZ_1019_MC.D2_PT_0/IN0 )
  );
  X_INV \NlwInverterBlock_N_PZ_1019_MC.D2_PT_0/IN1  (
    .I(DCORENCCTLw),
    .O(\NlwInverterSignal_N_PZ_1019_MC.D2_PT_0/IN1 )
  );
  X_INV \NlwInverterBlock_N_PZ_1019_MC.D2_PT_0/IN2  (
    .I(NET2512),
    .O(\NlwInverterSignal_N_PZ_1019_MC.D2_PT_0/IN2 )
  );
  X_INV \NlwInverterBlock_N_PZ_1019_MC.D2_PT_0/IN4  (
    .I(\U1/U4/InEdge1r ),
    .O(\NlwInverterSignal_N_PZ_1019_MC.D2_PT_0/IN4 )
  );
  X_INV \NlwInverterBlock_N_PZ_1019_MC.D2_PT_1/IN0  (
    .I(DCORIFGw),
    .O(\NlwInverterSignal_N_PZ_1019_MC.D2_PT_1/IN0 )
  );
  X_INV \NlwInverterBlock_N_PZ_1019_MC.D2_PT_1/IN1  (
    .I(DCORENCCTLw),
    .O(\NlwInverterSignal_N_PZ_1019_MC.D2_PT_1/IN1 )
  );
  X_INV \NlwInverterBlock_N_PZ_1019_MC.D2_PT_1/IN2  (
    .I(NET2512),
    .O(\NlwInverterSignal_N_PZ_1019_MC.D2_PT_1/IN2 )
  );
  X_INV \NlwInverterBlock_N_PZ_1019_MC.D2_PT_1/IN3  (
    .I(\U1/U4/LatchEdge1r ),
    .O(\NlwInverterSignal_N_PZ_1019_MC.D2_PT_1/IN3 )
  );
  X_INV \NlwInverterBlock_N_PZ_1019_MC.D2_PT_1/IN5  (
    .I(\outDATA<7>\$WA3.UIM ),
    .O(\NlwInverterSignal_N_PZ_1019_MC.D2_PT_1/IN5 )
  );
  X_INV \NlwInverterBlock_NET2512_MC.D2_PT_1/IN3  (
    .I(DCORENCCTLw),
    .O(\NlwInverterSignal_NET2512_MC.D2_PT_1/IN3 )
  );
  X_INV \NlwInverterBlock_U1/U4/LatchEdge1r_MC.D2_PT_1/IN1  (
    .I(DCORENCCTLw),
    .O(\NlwInverterSignal_U1/U4/LatchEdge1r_MC.D2_PT_1/IN1 )
  );
  X_INV \NlwInverterBlock_DCOR1THRESLOWr_MC.D1/IN1  (
    .I(\RD_II/UIM ),
    .O(\NlwInverterSignal_DCOR1THRESLOWr_MC.D1/IN1 )
  );
  X_INV \NlwInverterBlock_DCOR1THRESLOWr_MC.D1/IN2  (
    .I(U2_ADDR_reg[0]),
    .O(\NlwInverterSignal_DCOR1THRESLOWr_MC.D1/IN2 )
  );
  X_INV \NlwInverterBlock_DCOR1THRESLOWr_MC.D1/IN3  (
    .I(U2_ADDR_reg[4]),
    .O(\NlwInverterSignal_DCOR1THRESLOWr_MC.D1/IN3 )
  );
  X_INV \NlwInverterBlock_DCOR1THRESLOWr_MC.D1/IN4  (
    .I(U2_ADDR_reg[5]),
    .O(\NlwInverterSignal_DCOR1THRESLOWr_MC.D1/IN4 )
  );
  X_INV \NlwInverterBlock_DCOR1THRESLOWr_MC.D1/IN5  (
    .I(U2_ADDR_reg[6]),
    .O(\NlwInverterSignal_DCOR1THRESLOWr_MC.D1/IN5 )
  );
  X_INV \NlwInverterBlock_DCOR1THRESLOWr_MC.D1/IN6  (
    .I(U2_ADDR_reg[7]),
    .O(\NlwInverterSignal_DCOR1THRESLOWr_MC.D1/IN6 )
  );
  X_INV \NlwInverterBlock_DCOR1THRESLOWr_MC.D1/IN9  (
    .I(U2_ADDR_reg[2]),
    .O(\NlwInverterSignal_DCOR1THRESLOWr_MC.D1/IN9 )
  );
  X_INV \NlwInverterBlock_U1/U4/Latch1r<8>_MC.D2_PT_0/IN2  (
    .I(N_PZ_1019),
    .O(\NlwInverterSignal_U1/U4/Latch1r<8>_MC.D2_PT_0/IN2 )
  );
  X_INV \NlwInverterBlock_U1/Channel1<8>_MC.D2_PT_0/IN0  (
    .I(N_PZ_983),
    .O(\NlwInverterSignal_U1/Channel1<8>_MC.D2_PT_0/IN0 )
  );
  X_INV \NlwInverterBlock_U1/Channel1<8>_MC.D2_PT_1/IN1  (
    .I(\U1/U6/CurrState_Sreg0_FFD2 ),
    .O(\NlwInverterSignal_U1/Channel1<8>_MC.D2_PT_1/IN1 )
  );
  X_INV \NlwInverterBlock_U1/Channel1<8>_MC.D2_PT_1/IN3  (
    .I(\U1/Channel1 [5]),
    .O(\NlwInverterSignal_U1/Channel1<8>_MC.D2_PT_1/IN3 )
  );
  X_INV \NlwInverterBlock_U1/Channel1<8>_MC.D2_PT_1/IN5  (
    .I(\U1/U5/location_Maddsub__n0000__n0075 [0]),
    .O(\NlwInverterSignal_U1/Channel1<8>_MC.D2_PT_1/IN5 )
  );
  X_INV \NlwInverterBlock_U1/Channel1<8>_MC.D2_PT_2/IN1  (
    .I(\U1/U6/CurrState_Sreg0_FFD2 ),
    .O(\NlwInverterSignal_U1/Channel1<8>_MC.D2_PT_2/IN1 )
  );
  X_INV \NlwInverterBlock_U1/Channel1<8>_MC.D2_PT_2/IN4  (
    .I(\U1/U5/location_Maddsub__n0000__n0075 [0]),
    .O(\NlwInverterSignal_U1/Channel1<8>_MC.D2_PT_2/IN4 )
  );
  X_INV \NlwInverterBlock_U1/Channel1<8>_MC.D2_PT_3/IN1  (
    .I(\U1/U6/CurrState_Sreg0_FFD2 ),
    .O(\NlwInverterSignal_U1/Channel1<8>_MC.D2_PT_3/IN1 )
  );
  X_INV \NlwInverterBlock_U1/Channel1<8>_MC.D2_PT_3/IN4  (
    .I(\U1/U5/location_Maddsub__n0000__n0075 [0]),
    .O(\NlwInverterSignal_U1/Channel1<8>_MC.D2_PT_3/IN4 )
  );
  X_INV \NlwInverterBlock_U1/Channel1<8>_MC.D2_PT_3/IN5  (
    .I(\U1/Channel1 [6]),
    .O(\NlwInverterSignal_U1/Channel1<8>_MC.D2_PT_3/IN5 )
  );
  X_INV \NlwInverterBlock_U1/Channel1<8>_MC.D2_PT_4/IN1  (
    .I(\U1/U6/CurrState_Sreg0_FFD2 ),
    .O(\NlwInverterSignal_U1/Channel1<8>_MC.D2_PT_4/IN1 )
  );
  X_INV \NlwInverterBlock_U1/Channel1<8>_MC.D2_PT_4/IN4  (
    .I(\U1/U5/location_Maddsub__n0000__n0075 [0]),
    .O(\NlwInverterSignal_U1/Channel1<8>_MC.D2_PT_4/IN4 )
  );
  X_INV \NlwInverterBlock_U1/Channel1<8>_MC.D2_PT_5/IN1  (
    .I(\U1/Zero1 ),
    .O(\NlwInverterSignal_U1/Channel1<8>_MC.D2_PT_5/IN1 )
  );
  X_INV \NlwInverterBlock_U1/Channel1<8>_MC.D2_PT_5/IN3  (
    .I(\U1/U6/CurrState_Sreg0_FFD2 ),
    .O(\NlwInverterSignal_U1/Channel1<8>_MC.D2_PT_5/IN3 )
  );
  X_INV \NlwInverterBlock_U1/Channel1<8>_MC.D2_PT_5/IN5  (
    .I(\U1/Channel1 [8]),
    .O(\NlwInverterSignal_U1/Channel1<8>_MC.D2_PT_5/IN5 )
  );
  X_INV \NlwInverterBlock_U1/Channel1<8>_MC.D2_PT_5/IN6  (
    .I(N_PZ_975),
    .O(\NlwInverterSignal_U1/Channel1<8>_MC.D2_PT_5/IN6 )
  );
  X_INV \NlwInverterBlock_U1/Channel1<8>_MC.D2_PT_6/IN1  (
    .I(\U1/U6/CurrState_Sreg0_FFD2 ),
    .O(\NlwInverterSignal_U1/Channel1<8>_MC.D2_PT_6/IN1 )
  );
  X_INV \NlwInverterBlock_U1/Channel1<8>_MC.D2_PT_6/IN4  (
    .I(\U1/Channel1 [5]),
    .O(\NlwInverterSignal_U1/Channel1<8>_MC.D2_PT_6/IN4 )
  );
  X_INV \NlwInverterBlock_U1/Channel1<8>_MC.D2_PT_6/IN5  (
    .I(\U1/U5/location_Maddsub__n0000__n0075 [0]),
    .O(\NlwInverterSignal_U1/Channel1<8>_MC.D2_PT_6/IN5 )
  );
  X_INV \NlwInverterBlock_U1/Channel1<8>_MC.D2_PT_6/IN7  (
    .I(\U1/Channel1 [6]),
    .O(\NlwInverterSignal_U1/Channel1<8>_MC.D2_PT_6/IN7 )
  );
  X_INV \NlwInverterBlock_U1/Channel1<8>_MC.D2_PT_6/IN8  (
    .I(\U1/Channel1 [7]),
    .O(\NlwInverterSignal_U1/Channel1<8>_MC.D2_PT_6/IN8 )
  );
  X_INV \NlwInverterBlock_U1/Channel1<8>_MC.D2_PT_7/IN1  (
    .I(\U1/Zero1 ),
    .O(\NlwInverterSignal_U1/Channel1<8>_MC.D2_PT_7/IN1 )
  );
  X_INV \NlwInverterBlock_U1/Channel1<8>_MC.D2_PT_7/IN3  (
    .I(\U1/U6/CurrState_Sreg0_FFD2 ),
    .O(\NlwInverterSignal_U1/Channel1<8>_MC.D2_PT_7/IN3 )
  );
  X_INV \NlwInverterBlock_U1/Channel1<8>_MC.D2_PT_7/IN5  (
    .I(\U1/Channel1 [8]),
    .O(\NlwInverterSignal_U1/Channel1<8>_MC.D2_PT_7/IN5 )
  );
  X_INV \NlwInverterBlock_U1/Channel1<8>_MC.D2_PT_7/IN8  (
    .I(\U1/U5/location_Maddsub__n0000__n0067 [0]),
    .O(\NlwInverterSignal_U1/Channel1<8>_MC.D2_PT_7/IN8 )
  );
  X_INV \NlwInverterBlock_U1/Channel1<5>_MC.D2_PT_0/IN0  (
    .I(N_PZ_983),
    .O(\NlwInverterSignal_U1/Channel1<5>_MC.D2_PT_0/IN0 )
  );
  X_INV \NlwInverterBlock_U1/Channel1<5>_MC.D2_PT_1/IN1  (
    .I(\U1/Zero1 ),
    .O(\NlwInverterSignal_U1/Channel1<5>_MC.D2_PT_1/IN1 )
  );
  X_INV \NlwInverterBlock_U1/Channel1<5>_MC.D2_PT_1/IN3  (
    .I(\U1/U6/CurrState_Sreg0_FFD2 ),
    .O(\NlwInverterSignal_U1/Channel1<5>_MC.D2_PT_1/IN3 )
  );
  X_INV \NlwInverterBlock_U1/Channel1<5>_MC.D2_PT_1/IN5  (
    .I(\U1/U5/location_Maddsub__n0000__n0067 [0]),
    .O(\NlwInverterSignal_U1/Channel1<5>_MC.D2_PT_1/IN5 )
  );
  X_INV \NlwInverterBlock_U1/Channel1<5>_MC.D2_PT_2/IN1  (
    .I(\U1/Zero1 ),
    .O(\NlwInverterSignal_U1/Channel1<5>_MC.D2_PT_2/IN1 )
  );
  X_INV \NlwInverterBlock_U1/Channel1<5>_MC.D2_PT_2/IN3  (
    .I(\U1/U6/CurrState_Sreg0_FFD2 ),
    .O(\NlwInverterSignal_U1/Channel1<5>_MC.D2_PT_2/IN3 )
  );
  X_INV \NlwInverterBlock_U1/Channel1<5>_MC.D2_PT_2/IN5  (
    .I(N_PZ_975),
    .O(\NlwInverterSignal_U1/Channel1<5>_MC.D2_PT_2/IN5 )
  );
  X_INV \NlwInverterBlock_U1/U5/location_Maddsub__n0000__n0067<0>_MC.D2_PT_1/IN0  (
    .I(\U1/Channel1 [0]),
    .O(\NlwInverterSignal_U1/U5/location_Maddsub__n0000__n0067<0>_MC.D2_PT_1/IN0 )
  );
  X_INV \NlwInverterBlock_U1/U5/location_Maddsub__n0000__n0067<0>_MC.D2_PT_1/IN1  (
    .I(N_PZ_998),
    .O(\NlwInverterSignal_U1/U5/location_Maddsub__n0000__n0067<0>_MC.D2_PT_1/IN1 )
  );
  X_INV \NlwInverterBlock_U1/U5/location_Maddsub__n0000__n0067<0>_MC.D2_PT_1/IN2  (
    .I(\U1/Channel1 [1]),
    .O(\NlwInverterSignal_U1/U5/location_Maddsub__n0000__n0067<0>_MC.D2_PT_1/IN2 )
  );
  X_INV \NlwInverterBlock_U1/U5/location_Maddsub__n0000__n0067<0>_MC.D2_PT_1/IN3  (
    .I(\U1/Channel1 [2]),
    .O(\NlwInverterSignal_U1/U5/location_Maddsub__n0000__n0067<0>_MC.D2_PT_1/IN3 )
  );
  X_INV \NlwInverterBlock_U1/U5/location_Maddsub__n0000__n0067<0>_MC.D2_PT_1/IN4  (
    .I(\U1/Channel1 [3]),
    .O(\NlwInverterSignal_U1/U5/location_Maddsub__n0000__n0067<0>_MC.D2_PT_1/IN4 )
  );
  X_INV \NlwInverterBlock_U1/U5/location_Maddsub__n0000__n0067<0>_MC.D2_PT_1/IN5  (
    .I(\U1/Channel1 [4]),
    .O(\NlwInverterSignal_U1/U5/location_Maddsub__n0000__n0067<0>_MC.D2_PT_1/IN5 )
  );
  X_INV \NlwInverterBlock_N_PZ_998_MC.D2_PT_0/IN1  (
    .I(\U1/U6/CurrState_Sreg0_FFD2 ),
    .O(\NlwInverterSignal_N_PZ_998_MC.D2_PT_0/IN1 )
  );
  X_INV \NlwInverterBlock_N_PZ_998_MC.D2_PT_0/IN2  (
    .I(\U1/U6/CurrState_Sreg0_FFD1 ),
    .O(\NlwInverterSignal_N_PZ_998_MC.D2_PT_0/IN2 )
  );
  X_INV \NlwInverterBlock_N_PZ_998_MC.D2_PT_1/IN1  (
    .I(\U1/U6/CurrState_Sreg0_FFD4 ),
    .O(\NlwInverterSignal_N_PZ_998_MC.D2_PT_1/IN1 )
  );
  X_INV \NlwInverterBlock_N_PZ_998_MC.D2_PT_1/IN2  (
    .I(\U1/U6/CurrState_Sreg0_FFD1 ),
    .O(\NlwInverterSignal_N_PZ_998_MC.D2_PT_1/IN2 )
  );
  X_INV \NlwInverterBlock_U1/NET3720_MC.D2_PT_1/IN1  (
    .I(DCORENCCTLw),
    .O(\NlwInverterSignal_U1/NET3720_MC.D2_PT_1/IN1 )
  );
  X_INV \NlwInverterBlock_U1/Channel1<1>_MC.D2_PT_0/IN0  (
    .I(N_PZ_983),
    .O(\NlwInverterSignal_U1/Channel1<1>_MC.D2_PT_0/IN0 )
  );
  X_INV \NlwInverterBlock_U1/Channel1<1>_MC.D2_PT_1/IN2  (
    .I(\U1/Zero1 ),
    .O(\NlwInverterSignal_U1/Channel1<1>_MC.D2_PT_1/IN2 )
  );
  X_INV \NlwInverterBlock_U1/Channel1<1>_MC.D2_PT_1/IN4  (
    .I(\U1/U6/CurrState_Sreg0_FFD2 ),
    .O(\NlwInverterSignal_U1/Channel1<1>_MC.D2_PT_1/IN4 )
  );
  X_INV \NlwInverterBlock_U1/Channel1<1>_MC.D2_PT_2/IN1  (
    .I(\U1/Channel1 [0]),
    .O(\NlwInverterSignal_U1/Channel1<1>_MC.D2_PT_2/IN1 )
  );
  X_INV \NlwInverterBlock_U1/Channel1<1>_MC.D2_PT_2/IN2  (
    .I(\U1/Zero1 ),
    .O(\NlwInverterSignal_U1/Channel1<1>_MC.D2_PT_2/IN2 )
  );
  X_INV \NlwInverterBlock_U1/Channel1<1>_MC.D2_PT_2/IN4  (
    .I(\U1/U6/CurrState_Sreg0_FFD2 ),
    .O(\NlwInverterSignal_U1/Channel1<1>_MC.D2_PT_2/IN4 )
  );
  X_INV \NlwInverterBlock_U1/Channel1<1>_MC.D2_PT_2/IN6  (
    .I(N_PZ_975),
    .O(\NlwInverterSignal_U1/Channel1<1>_MC.D2_PT_2/IN6 )
  );
  X_INV \NlwInverterBlock_N_PZ_975_MC.D2_PT_0/IN1  (
    .I(\U1/U6/CurrState_Sreg0_FFD1 ),
    .O(\NlwInverterSignal_N_PZ_975_MC.D2_PT_0/IN1 )
  );
  X_INV \NlwInverterBlock_N_PZ_975_MC.D2_PT_0/IN2  (
    .I(\U1/NET3720 ),
    .O(\NlwInverterSignal_N_PZ_975_MC.D2_PT_0/IN2 )
  );
  X_INV \NlwInverterBlock_N_PZ_975_MC.D2_PT_1/IN0  (
    .I(\U1/U6/CurrState_Sreg0_FFD4 ),
    .O(\NlwInverterSignal_N_PZ_975_MC.D2_PT_1/IN0 )
  );
  X_INV \NlwInverterBlock_U1/Channel1<2>_MC.D2_PT_0/IN0  (
    .I(N_PZ_983),
    .O(\NlwInverterSignal_U1/Channel1<2>_MC.D2_PT_0/IN0 )
  );
  X_INV \NlwInverterBlock_U1/Channel1<2>_MC.D2_PT_1/IN2  (
    .I(\U1/Zero1 ),
    .O(\NlwInverterSignal_U1/Channel1<2>_MC.D2_PT_1/IN2 )
  );
  X_INV \NlwInverterBlock_U1/Channel1<2>_MC.D2_PT_1/IN4  (
    .I(\U1/U6/CurrState_Sreg0_FFD2 ),
    .O(\NlwInverterSignal_U1/Channel1<2>_MC.D2_PT_1/IN4 )
  );
  X_INV \NlwInverterBlock_U1/Channel1<2>_MC.D2_PT_2/IN1  (
    .I(\U1/Channel1 [0]),
    .O(\NlwInverterSignal_U1/Channel1<2>_MC.D2_PT_2/IN1 )
  );
  X_INV \NlwInverterBlock_U1/Channel1<2>_MC.D2_PT_2/IN2  (
    .I(\U1/Zero1 ),
    .O(\NlwInverterSignal_U1/Channel1<2>_MC.D2_PT_2/IN2 )
  );
  X_INV \NlwInverterBlock_U1/Channel1<2>_MC.D2_PT_2/IN4  (
    .I(\U1/U6/CurrState_Sreg0_FFD2 ),
    .O(\NlwInverterSignal_U1/Channel1<2>_MC.D2_PT_2/IN4 )
  );
  X_INV \NlwInverterBlock_U1/Channel1<2>_MC.D2_PT_2/IN6  (
    .I(N_PZ_975),
    .O(\NlwInverterSignal_U1/Channel1<2>_MC.D2_PT_2/IN6 )
  );
  X_INV \NlwInverterBlock_U1/Channel1<2>_MC.D2_PT_2/IN7  (
    .I(\U1/Channel1 [1]),
    .O(\NlwInverterSignal_U1/Channel1<2>_MC.D2_PT_2/IN7 )
  );
  X_INV \NlwInverterBlock_U1/Channel1<3>_MC.D2_PT_0/IN0  (
    .I(N_PZ_983),
    .O(\NlwInverterSignal_U1/Channel1<3>_MC.D2_PT_0/IN0 )
  );
  X_INV \NlwInverterBlock_U1/Channel1<3>_MC.D2_PT_1/IN2  (
    .I(\U1/Zero1 ),
    .O(\NlwInverterSignal_U1/Channel1<3>_MC.D2_PT_1/IN2 )
  );
  X_INV \NlwInverterBlock_U1/Channel1<3>_MC.D2_PT_1/IN4  (
    .I(\U1/U6/CurrState_Sreg0_FFD2 ),
    .O(\NlwInverterSignal_U1/Channel1<3>_MC.D2_PT_1/IN4 )
  );
  X_INV \NlwInverterBlock_U1/Channel1<3>_MC.D2_PT_2/IN1  (
    .I(\U1/Channel1 [0]),
    .O(\NlwInverterSignal_U1/Channel1<3>_MC.D2_PT_2/IN1 )
  );
  X_INV \NlwInverterBlock_U1/Channel1<3>_MC.D2_PT_2/IN2  (
    .I(\U1/Zero1 ),
    .O(\NlwInverterSignal_U1/Channel1<3>_MC.D2_PT_2/IN2 )
  );
  X_INV \NlwInverterBlock_U1/Channel1<3>_MC.D2_PT_2/IN4  (
    .I(\U1/U6/CurrState_Sreg0_FFD2 ),
    .O(\NlwInverterSignal_U1/Channel1<3>_MC.D2_PT_2/IN4 )
  );
  X_INV \NlwInverterBlock_U1/Channel1<3>_MC.D2_PT_2/IN6  (
    .I(N_PZ_975),
    .O(\NlwInverterSignal_U1/Channel1<3>_MC.D2_PT_2/IN6 )
  );
  X_INV \NlwInverterBlock_U1/Channel1<3>_MC.D2_PT_2/IN7  (
    .I(\U1/Channel1 [1]),
    .O(\NlwInverterSignal_U1/Channel1<3>_MC.D2_PT_2/IN7 )
  );
  X_INV \NlwInverterBlock_U1/Channel1<3>_MC.D2_PT_2/IN8  (
    .I(\U1/Channel1 [2]),
    .O(\NlwInverterSignal_U1/Channel1<3>_MC.D2_PT_2/IN8 )
  );
  X_INV \NlwInverterBlock_U1/Channel1<4>_MC.D2_PT_0/IN0  (
    .I(N_PZ_983),
    .O(\NlwInverterSignal_U1/Channel1<4>_MC.D2_PT_0/IN0 )
  );
  X_INV \NlwInverterBlock_U1/Channel1<4>_MC.D2_PT_1/IN0  (
    .I(\U1/Channel1 [0]),
    .O(\NlwInverterSignal_U1/Channel1<4>_MC.D2_PT_1/IN0 )
  );
  X_INV \NlwInverterBlock_U1/Channel1<4>_MC.D2_PT_1/IN2  (
    .I(\U1/U6/CurrState_Sreg0_FFD2 ),
    .O(\NlwInverterSignal_U1/Channel1<4>_MC.D2_PT_1/IN2 )
  );
  X_INV \NlwInverterBlock_U1/Channel1<4>_MC.D2_PT_1/IN4  (
    .I(\U1/U5/location_Maddsub__n0000__n0067 [0]),
    .O(\NlwInverterSignal_U1/Channel1<4>_MC.D2_PT_1/IN4 )
  );
  X_INV \NlwInverterBlock_U1/Channel1<4>_MC.D2_PT_2/IN1  (
    .I(\U1/U6/CurrState_Sreg0_FFD2 ),
    .O(\NlwInverterSignal_U1/Channel1<4>_MC.D2_PT_2/IN1 )
  );
  X_INV \NlwInverterBlock_U1/Channel1<4>_MC.D2_PT_2/IN3  (
    .I(\U1/U5/location_Maddsub__n0000__n0067 [0]),
    .O(\NlwInverterSignal_U1/Channel1<4>_MC.D2_PT_2/IN3 )
  );
  X_INV \NlwInverterBlock_U1/Channel1<4>_MC.D2_PT_2/IN4  (
    .I(\U1/Channel1 [1]),
    .O(\NlwInverterSignal_U1/Channel1<4>_MC.D2_PT_2/IN4 )
  );
  X_INV \NlwInverterBlock_U1/Channel1<4>_MC.D2_PT_3/IN1  (
    .I(\U1/U6/CurrState_Sreg0_FFD2 ),
    .O(\NlwInverterSignal_U1/Channel1<4>_MC.D2_PT_3/IN1 )
  );
  X_INV \NlwInverterBlock_U1/Channel1<4>_MC.D2_PT_3/IN3  (
    .I(\U1/U5/location_Maddsub__n0000__n0067 [0]),
    .O(\NlwInverterSignal_U1/Channel1<4>_MC.D2_PT_3/IN3 )
  );
  X_INV \NlwInverterBlock_U1/Channel1<4>_MC.D2_PT_3/IN4  (
    .I(\U1/Channel1 [2]),
    .O(\NlwInverterSignal_U1/Channel1<4>_MC.D2_PT_3/IN4 )
  );
  X_INV \NlwInverterBlock_U1/Channel1<4>_MC.D2_PT_4/IN1  (
    .I(\U1/U6/CurrState_Sreg0_FFD2 ),
    .O(\NlwInverterSignal_U1/Channel1<4>_MC.D2_PT_4/IN1 )
  );
  X_INV \NlwInverterBlock_U1/Channel1<4>_MC.D2_PT_4/IN3  (
    .I(\U1/U5/location_Maddsub__n0000__n0067 [0]),
    .O(\NlwInverterSignal_U1/Channel1<4>_MC.D2_PT_4/IN3 )
  );
  X_INV \NlwInverterBlock_U1/Channel1<4>_MC.D2_PT_5/IN1  (
    .I(\U1/Zero1 ),
    .O(\NlwInverterSignal_U1/Channel1<4>_MC.D2_PT_5/IN1 )
  );
  X_INV \NlwInverterBlock_U1/Channel1<4>_MC.D2_PT_5/IN3  (
    .I(\U1/U6/CurrState_Sreg0_FFD2 ),
    .O(\NlwInverterSignal_U1/Channel1<4>_MC.D2_PT_5/IN3 )
  );
  X_INV \NlwInverterBlock_U1/Channel1<4>_MC.D2_PT_5/IN5  (
    .I(N_PZ_975),
    .O(\NlwInverterSignal_U1/Channel1<4>_MC.D2_PT_5/IN5 )
  );
  X_INV \NlwInverterBlock_U1/Channel1<4>_MC.D2_PT_5/IN7  (
    .I(\U1/Channel1 [4]),
    .O(\NlwInverterSignal_U1/Channel1<4>_MC.D2_PT_5/IN7 )
  );
  X_INV \NlwInverterBlock_U1/Channel1<4>_MC.D2_PT_6/IN0  (
    .I(\U1/Channel1 [0]),
    .O(\NlwInverterSignal_U1/Channel1<4>_MC.D2_PT_6/IN0 )
  );
  X_INV \NlwInverterBlock_U1/Channel1<4>_MC.D2_PT_6/IN2  (
    .I(\U1/U6/CurrState_Sreg0_FFD2 ),
    .O(\NlwInverterSignal_U1/Channel1<4>_MC.D2_PT_6/IN2 )
  );
  X_INV \NlwInverterBlock_U1/Channel1<4>_MC.D2_PT_6/IN4  (
    .I(\U1/U5/location_Maddsub__n0000__n0067 [0]),
    .O(\NlwInverterSignal_U1/Channel1<4>_MC.D2_PT_6/IN4 )
  );
  X_INV \NlwInverterBlock_U1/Channel1<4>_MC.D2_PT_6/IN5  (
    .I(\U1/Channel1 [1]),
    .O(\NlwInverterSignal_U1/Channel1<4>_MC.D2_PT_6/IN5 )
  );
  X_INV \NlwInverterBlock_U1/Channel1<4>_MC.D2_PT_6/IN6  (
    .I(\U1/Channel1 [2]),
    .O(\NlwInverterSignal_U1/Channel1<4>_MC.D2_PT_6/IN6 )
  );
  X_INV \NlwInverterBlock_U1/Channel1<4>_MC.D2_PT_6/IN7  (
    .I(\U1/Channel1 [3]),
    .O(\NlwInverterSignal_U1/Channel1<4>_MC.D2_PT_6/IN7 )
  );
  X_INV \NlwInverterBlock_U1/Channel1<4>_MC.D2_PT_7/IN2  (
    .I(\U1/Zero1 ),
    .O(\NlwInverterSignal_U1/Channel1<4>_MC.D2_PT_7/IN2 )
  );
  X_INV \NlwInverterBlock_U1/Channel1<4>_MC.D2_PT_7/IN4  (
    .I(\U1/U6/CurrState_Sreg0_FFD2 ),
    .O(\NlwInverterSignal_U1/Channel1<4>_MC.D2_PT_7/IN4 )
  );
  X_INV \NlwInverterBlock_U1/Channel1<4>_MC.D2_PT_7/IN10  (
    .I(\U1/Channel1 [4]),
    .O(\NlwInverterSignal_U1/Channel1<4>_MC.D2_PT_7/IN10 )
  );
  X_INV \NlwInverterBlock_U1/Channel1<6>_MC.D2_PT_0/IN0  (
    .I(N_PZ_983),
    .O(\NlwInverterSignal_U1/Channel1<6>_MC.D2_PT_0/IN0 )
  );
  X_INV \NlwInverterBlock_U1/Channel1<6>_MC.D2_PT_1/IN1  (
    .I(\U1/Zero1 ),
    .O(\NlwInverterSignal_U1/Channel1<6>_MC.D2_PT_1/IN1 )
  );
  X_INV \NlwInverterBlock_U1/Channel1<6>_MC.D2_PT_1/IN3  (
    .I(\U1/U6/CurrState_Sreg0_FFD2 ),
    .O(\NlwInverterSignal_U1/Channel1<6>_MC.D2_PT_1/IN3 )
  );
  X_INV \NlwInverterBlock_U1/Channel1<6>_MC.D2_PT_1/IN6  (
    .I(\U1/U5/location_Maddsub__n0000__n0067 [0]),
    .O(\NlwInverterSignal_U1/Channel1<6>_MC.D2_PT_1/IN6 )
  );
  X_INV \NlwInverterBlock_U1/Channel1<6>_MC.D2_PT_2/IN1  (
    .I(\U1/Zero1 ),
    .O(\NlwInverterSignal_U1/Channel1<6>_MC.D2_PT_2/IN1 )
  );
  X_INV \NlwInverterBlock_U1/Channel1<6>_MC.D2_PT_2/IN3  (
    .I(\U1/U6/CurrState_Sreg0_FFD2 ),
    .O(\NlwInverterSignal_U1/Channel1<6>_MC.D2_PT_2/IN3 )
  );
  X_INV \NlwInverterBlock_U1/Channel1<6>_MC.D2_PT_2/IN5  (
    .I(\U1/Channel1 [5]),
    .O(\NlwInverterSignal_U1/Channel1<6>_MC.D2_PT_2/IN5 )
  );
  X_INV \NlwInverterBlock_U1/Channel1<6>_MC.D2_PT_2/IN6  (
    .I(N_PZ_975),
    .O(\NlwInverterSignal_U1/Channel1<6>_MC.D2_PT_2/IN6 )
  );
  X_INV \NlwInverterBlock_U1/Channel1<7>_MC.D2_PT_0/IN0  (
    .I(N_PZ_983),
    .O(\NlwInverterSignal_U1/Channel1<7>_MC.D2_PT_0/IN0 )
  );
  X_INV \NlwInverterBlock_U1/Channel1<7>_MC.D2_PT_1/IN1  (
    .I(\U1/Zero1 ),
    .O(\NlwInverterSignal_U1/Channel1<7>_MC.D2_PT_1/IN1 )
  );
  X_INV \NlwInverterBlock_U1/Channel1<7>_MC.D2_PT_1/IN3  (
    .I(\U1/U6/CurrState_Sreg0_FFD2 ),
    .O(\NlwInverterSignal_U1/Channel1<7>_MC.D2_PT_1/IN3 )
  );
  X_INV \NlwInverterBlock_U1/Channel1<7>_MC.D2_PT_1/IN6  (
    .I(\U1/U5/location_Maddsub__n0000__n0067 [0]),
    .O(\NlwInverterSignal_U1/Channel1<7>_MC.D2_PT_1/IN6 )
  );
  X_INV \NlwInverterBlock_U1/Channel1<7>_MC.D2_PT_2/IN1  (
    .I(\U1/Zero1 ),
    .O(\NlwInverterSignal_U1/Channel1<7>_MC.D2_PT_2/IN1 )
  );
  X_INV \NlwInverterBlock_U1/Channel1<7>_MC.D2_PT_2/IN3  (
    .I(\U1/U6/CurrState_Sreg0_FFD2 ),
    .O(\NlwInverterSignal_U1/Channel1<7>_MC.D2_PT_2/IN3 )
  );
  X_INV \NlwInverterBlock_U1/Channel1<7>_MC.D2_PT_2/IN5  (
    .I(\U1/Channel1 [5]),
    .O(\NlwInverterSignal_U1/Channel1<7>_MC.D2_PT_2/IN5 )
  );
  X_INV \NlwInverterBlock_U1/Channel1<7>_MC.D2_PT_2/IN6  (
    .I(N_PZ_975),
    .O(\NlwInverterSignal_U1/Channel1<7>_MC.D2_PT_2/IN6 )
  );
  X_INV \NlwInverterBlock_U1/Channel1<7>_MC.D2_PT_2/IN8  (
    .I(\U1/Channel1 [6]),
    .O(\NlwInverterSignal_U1/Channel1<7>_MC.D2_PT_2/IN8 )
  );
  X_INV \NlwInverterBlock_U1/U5/location_Maddsub__n0000__n0075<0>_MC.D2_PT_0/IN2  (
    .I(\U1/U5/location_Maddsub__n0000__n0067 [0]),
    .O(\NlwInverterSignal_U1/U5/location_Maddsub__n0000__n0075<0>_MC.D2_PT_0/IN2 )
  );
  X_INV \NlwInverterBlock_U1/U5/location_Maddsub__n0000__n0075<0>_MC.D2_PT_1/IN0  (
    .I(\U1/Channel1 [8]),
    .O(\NlwInverterSignal_U1/U5/location_Maddsub__n0000__n0075<0>_MC.D2_PT_1/IN0 )
  );
  X_INV \NlwInverterBlock_U1/U5/location_Maddsub__n0000__n0075<0>_MC.D2_PT_1/IN1  (
    .I(\U1/Channel1 [5]),
    .O(\NlwInverterSignal_U1/U5/location_Maddsub__n0000__n0075<0>_MC.D2_PT_1/IN1 )
  );
  X_INV \NlwInverterBlock_U1/U5/location_Maddsub__n0000__n0075<0>_MC.D2_PT_1/IN3  (
    .I(\U1/Channel1 [6]),
    .O(\NlwInverterSignal_U1/U5/location_Maddsub__n0000__n0075<0>_MC.D2_PT_1/IN3 )
  );
  X_INV \NlwInverterBlock_U1/U5/location_Maddsub__n0000__n0075<0>_MC.D2_PT_1/IN4  (
    .I(\U1/Channel1 [7]),
    .O(\NlwInverterSignal_U1/U5/location_Maddsub__n0000__n0075<0>_MC.D2_PT_1/IN4 )
  );
  X_INV \NlwInverterBlock_U1/U5/location_Maddsub__n0000__n0075<0>_MC.D2_PT_1/IN5  (
    .I(N_PZ_998),
    .O(\NlwInverterSignal_U1/U5/location_Maddsub__n0000__n0075<0>_MC.D2_PT_1/IN5 )
  );
  X_INV \NlwInverterBlock_DCORCONFIGr_MC.D1/IN1  (
    .I(\RD_II/UIM ),
    .O(\NlwInverterSignal_DCORCONFIGr_MC.D1/IN1 )
  );
  X_INV \NlwInverterBlock_DCORCONFIGr_MC.D1/IN3  (
    .I(U2_ADDR_reg[4]),
    .O(\NlwInverterSignal_DCORCONFIGr_MC.D1/IN3 )
  );
  X_INV \NlwInverterBlock_DCORCONFIGr_MC.D1/IN4  (
    .I(U2_ADDR_reg[5]),
    .O(\NlwInverterSignal_DCORCONFIGr_MC.D1/IN4 )
  );
  X_INV \NlwInverterBlock_DCORCONFIGr_MC.D1/IN5  (
    .I(U2_ADDR_reg[6]),
    .O(\NlwInverterSignal_DCORCONFIGr_MC.D1/IN5 )
  );
  X_INV \NlwInverterBlock_DCORCONFIGr_MC.D1/IN6  (
    .I(U2_ADDR_reg[7]),
    .O(\NlwInverterSignal_DCORCONFIGr_MC.D1/IN6 )
  );
  X_INV \NlwInverterBlock_DCORENCPWRr_MC.D1/IN1  (
    .I(\RD_II/UIM ),
    .O(\NlwInverterSignal_DCORENCPWRr_MC.D1/IN1 )
  );
  X_INV \NlwInverterBlock_DCORENCPWRr_MC.D1/IN2  (
    .I(U2_ADDR_reg[0]),
    .O(\NlwInverterSignal_DCORENCPWRr_MC.D1/IN2 )
  );
  X_INV \NlwInverterBlock_DCORENCPWRr_MC.D1/IN3  (
    .I(U2_ADDR_reg[4]),
    .O(\NlwInverterSignal_DCORENCPWRr_MC.D1/IN3 )
  );
  X_INV \NlwInverterBlock_DCORENCPWRr_MC.D1/IN4  (
    .I(U2_ADDR_reg[5]),
    .O(\NlwInverterSignal_DCORENCPWRr_MC.D1/IN4 )
  );
  X_INV \NlwInverterBlock_DCORENCPWRr_MC.D1/IN5  (
    .I(U2_ADDR_reg[6]),
    .O(\NlwInverterSignal_DCORENCPWRr_MC.D1/IN5 )
  );
  X_INV \NlwInverterBlock_DCORENCPWRr_MC.D1/IN6  (
    .I(U2_ADDR_reg[7]),
    .O(\NlwInverterSignal_DCORENCPWRr_MC.D1/IN6 )
  );
  X_INV \NlwInverterBlock_outDATA<0>\$WA5.UIM_MC.D2_PT_0/IN1  (
    .I(NET2528),
    .O(\NlwInverterSignal_outDATA<0>\$WA5.UIM_MC.D2_PT_0/IN1 )
  );
  X_INV \NlwInverterBlock_NET2528_MC.D1/IN1  (
    .I(DCORIFGw),
    .O(\NlwInverterSignal_NET2528_MC.D1/IN1 )
  );
  X_INV \NlwInverterBlock_NET2528_MC.D2_PT_0/IN1  (
    .I(\AD<1>_II/UIM ),
    .O(\NlwInverterSignal_NET2528_MC.D2_PT_0/IN1 )
  );
  X_INV \NlwInverterBlock_NET2528_MC.D2_PT_1/IN1  (
    .I(DCORIFGw),
    .O(\NlwInverterSignal_NET2528_MC.D2_PT_1/IN1 )
  );
  X_INV \NlwInverterBlock_NET2528_MC.D2_PT_1/IN3  (
    .I(NET2528),
    .O(\NlwInverterSignal_NET2528_MC.D2_PT_1/IN3 )
  );
  X_INV \NlwInverterBlock_DCORIFGr_MC.D1/IN1  (
    .I(\RD_II/UIM ),
    .O(\NlwInverterSignal_DCORIFGr_MC.D1/IN1 )
  );
  X_INV \NlwInverterBlock_DCORIFGr_MC.D1/IN3  (
    .I(U2_ADDR_reg[4]),
    .O(\NlwInverterSignal_DCORIFGr_MC.D1/IN3 )
  );
  X_INV \NlwInverterBlock_DCORIFGr_MC.D1/IN4  (
    .I(U2_ADDR_reg[5]),
    .O(\NlwInverterSignal_DCORIFGr_MC.D1/IN4 )
  );
  X_INV \NlwInverterBlock_DCORIFGr_MC.D1/IN5  (
    .I(U2_ADDR_reg[6]),
    .O(\NlwInverterSignal_DCORIFGr_MC.D1/IN5 )
  );
  X_INV \NlwInverterBlock_DCORIFGr_MC.D1/IN6  (
    .I(U2_ADDR_reg[7]),
    .O(\NlwInverterSignal_DCORIFGr_MC.D1/IN6 )
  );
  X_INV \NlwInverterBlock_DCORIFGr_MC.D1/IN7  (
    .I(U2_ADDR_reg[3]),
    .O(\NlwInverterSignal_DCORIFGr_MC.D1/IN7 )
  );
  X_INV \NlwInverterBlock_DCORIFGr_MC.D1/IN8  (
    .I(U2_ADDR_reg[1]),
    .O(\NlwInverterSignal_DCORIFGr_MC.D1/IN8 )
  );
  X_INV \NlwInverterBlock_DCORIFGr_MC.D1/IN9  (
    .I(U2_ADDR_reg[2]),
    .O(\NlwInverterSignal_DCORIFGr_MC.D1/IN9 )
  );
  X_INV \NlwInverterBlock_outDATA<0>\$WA4.UIM_MC.D2_PT_0/IN0  (
    .I(\RLS0_II/UIM ),
    .O(\NlwInverterSignal_outDATA<0>\$WA4.UIM_MC.D2_PT_0/IN0 )
  );
  X_INV \NlwInverterBlock_outDATA<0>\$WA4.UIM_MC.D2_PT_1/IN0  (
    .I(DCORLIMITSr),
    .O(\NlwInverterSignal_outDATA<0>\$WA4.UIM_MC.D2_PT_1/IN0 )
  );
  X_INV \NlwInverterBlock_DCORLIMITSr_MC.D1/IN1  (
    .I(\RD_II/UIM ),
    .O(\NlwInverterSignal_DCORLIMITSr_MC.D1/IN1 )
  );
  X_INV \NlwInverterBlock_DCORLIMITSr_MC.D1/IN3  (
    .I(U2_ADDR_reg[4]),
    .O(\NlwInverterSignal_DCORLIMITSr_MC.D1/IN3 )
  );
  X_INV \NlwInverterBlock_DCORLIMITSr_MC.D1/IN4  (
    .I(U2_ADDR_reg[5]),
    .O(\NlwInverterSignal_DCORLIMITSr_MC.D1/IN4 )
  );
  X_INV \NlwInverterBlock_DCORLIMITSr_MC.D1/IN5  (
    .I(U2_ADDR_reg[6]),
    .O(\NlwInverterSignal_DCORLIMITSr_MC.D1/IN5 )
  );
  X_INV \NlwInverterBlock_DCORLIMITSr_MC.D1/IN6  (
    .I(U2_ADDR_reg[7]),
    .O(\NlwInverterSignal_DCORLIMITSr_MC.D1/IN6 )
  );
  X_INV \NlwInverterBlock_DCORLIMITSr_MC.D1/IN7  (
    .I(U2_ADDR_reg[3]),
    .O(\NlwInverterSignal_DCORLIMITSr_MC.D1/IN7 )
  );
  X_INV \NlwInverterBlock_DCORLIMITSr_MC.D1/IN9  (
    .I(U2_ADDR_reg[2]),
    .O(\NlwInverterSignal_DCORLIMITSr_MC.D1/IN9 )
  );
  X_INV \NlwInverterBlock_U5/RLS0fr_MC.D2_PT_0/IN2  (
    .I(DCORLINTr),
    .O(\NlwInverterSignal_U5/RLS0fr_MC.D2_PT_0/IN2 )
  );
  X_INV \NlwInverterBlock_U5/RLS0fr_MC.D2_PT_1/IN1  (
    .I(\RLS0_II/UIM ),
    .O(\NlwInverterSignal_U5/RLS0fr_MC.D2_PT_1/IN1 )
  );
  X_INV \NlwInverterBlock_U5/RLS0fr_MC.D2_PT_1/IN2  (
    .I(DCORLINTr),
    .O(\NlwInverterSignal_U5/RLS0fr_MC.D2_PT_1/IN2 )
  );
  X_INV \NlwInverterBlock_U5/RLS0fr_MC.D2_PT_1/IN3  (
    .I(\DIR0_II/UIM ),
    .O(\NlwInverterSignal_U5/RLS0fr_MC.D2_PT_1/IN3 )
  );
  X_INV \NlwInverterBlock_DCORLINTr_MC.D1/IN1  (
    .I(\RD_II/UIM ),
    .O(\NlwInverterSignal_DCORLINTr_MC.D1/IN1 )
  );
  X_INV \NlwInverterBlock_DCORLINTr_MC.D1/IN2  (
    .I(U2_ADDR_reg[0]),
    .O(\NlwInverterSignal_DCORLINTr_MC.D1/IN2 )
  );
  X_INV \NlwInverterBlock_DCORLINTr_MC.D1/IN3  (
    .I(U2_ADDR_reg[4]),
    .O(\NlwInverterSignal_DCORLINTr_MC.D1/IN3 )
  );
  X_INV \NlwInverterBlock_DCORLINTr_MC.D1/IN4  (
    .I(U2_ADDR_reg[5]),
    .O(\NlwInverterSignal_DCORLINTr_MC.D1/IN4 )
  );
  X_INV \NlwInverterBlock_DCORLINTr_MC.D1/IN5  (
    .I(U2_ADDR_reg[6]),
    .O(\NlwInverterSignal_DCORLINTr_MC.D1/IN5 )
  );
  X_INV \NlwInverterBlock_DCORLINTr_MC.D1/IN6  (
    .I(U2_ADDR_reg[7]),
    .O(\NlwInverterSignal_DCORLINTr_MC.D1/IN6 )
  );
  X_INV \NlwInverterBlock_DCORLINTr_MC.D1/IN7  (
    .I(U2_ADDR_reg[3]),
    .O(\NlwInverterSignal_DCORLINTr_MC.D1/IN7 )
  );
  X_INV \NlwInverterBlock_DCORLINTr_MC.D1/IN9  (
    .I(U2_ADDR_reg[2]),
    .O(\NlwInverterSignal_DCORLINTr_MC.D1/IN9 )
  );
  X_INV \NlwInverterBlock_N_PZ_1016_MC.D1/IN0  (
    .I(DCORLIMITSr),
    .O(\NlwInverterSignal_N_PZ_1016_MC.D1/IN0 )
  );
  X_INV \NlwInverterBlock_N_PZ_1016_MC.D1/IN1  (
    .I(DCORLINTr),
    .O(\NlwInverterSignal_N_PZ_1016_MC.D1/IN1 )
  );
  X_INV \NlwInverterBlock_outDATA<0>\$WA1.UIM_MC.D2_PT_1/IN0  (
    .I(DCOR0CNTLOWr),
    .O(\NlwInverterSignal_outDATA<0>\$WA1.UIM_MC.D2_PT_1/IN0 )
  );
  X_INV \NlwInverterBlock_outDATA<0>\$WA1.UIM_MC.D2_PT_2/IN0  (
    .I(DCOR0CNTLOWr),
    .O(\NlwInverterSignal_outDATA<0>\$WA1.UIM_MC.D2_PT_2/IN0 )
  );
  X_INV \NlwInverterBlock_outDATA<0>\$WA1.UIM_MC.D2_PT_2/IN1  (
    .I(DCOR1CNTLOWr),
    .O(\NlwInverterSignal_outDATA<0>\$WA1.UIM_MC.D2_PT_2/IN1 )
  );
  X_INV \NlwInverterBlock_outDATA<0>\$WA1.UIM_MC.D2_PT_3/IN0  (
    .I(DCOR0CNTLOWr),
    .O(\NlwInverterSignal_outDATA<0>\$WA1.UIM_MC.D2_PT_3/IN0 )
  );
  X_INV \NlwInverterBlock_outDATA<0>\$WA1.UIM_MC.D2_PT_3/IN1  (
    .I(DCOR1CNTLOWr),
    .O(\NlwInverterSignal_outDATA<0>\$WA1.UIM_MC.D2_PT_3/IN1 )
  );
  X_INV \NlwInverterBlock_outDATA<0>\$WA1.UIM_MC.D2_PT_3/IN2  (
    .I(DCOR0CNTHIGHr),
    .O(\NlwInverterSignal_outDATA<0>\$WA1.UIM_MC.D2_PT_3/IN2 )
  );
  X_INV \NlwInverterBlock_U1/U3/holdingreg0<0>_MC.D2_PT_1/IN1  (
    .I(\AS_II/UIM ),
    .O(\NlwInverterSignal_U1/U3/holdingreg0<0>_MC.D2_PT_1/IN1 )
  );
  X_INV \NlwInverterBlock_DCOR0CNTLOWr_MC.D1/IN1  (
    .I(\RD_II/UIM ),
    .O(\NlwInverterSignal_DCOR0CNTLOWr_MC.D1/IN1 )
  );
  X_INV \NlwInverterBlock_DCOR0CNTLOWr_MC.D1/IN2  (
    .I(U2_ADDR_reg[0]),
    .O(\NlwInverterSignal_DCOR0CNTLOWr_MC.D1/IN2 )
  );
  X_INV \NlwInverterBlock_DCOR0CNTLOWr_MC.D1/IN3  (
    .I(U2_ADDR_reg[4]),
    .O(\NlwInverterSignal_DCOR0CNTLOWr_MC.D1/IN3 )
  );
  X_INV \NlwInverterBlock_DCOR0CNTLOWr_MC.D1/IN4  (
    .I(U2_ADDR_reg[5]),
    .O(\NlwInverterSignal_DCOR0CNTLOWr_MC.D1/IN4 )
  );
  X_INV \NlwInverterBlock_DCOR0CNTLOWr_MC.D1/IN5  (
    .I(U2_ADDR_reg[6]),
    .O(\NlwInverterSignal_DCOR0CNTLOWr_MC.D1/IN5 )
  );
  X_INV \NlwInverterBlock_DCOR0CNTLOWr_MC.D1/IN6  (
    .I(U2_ADDR_reg[7]),
    .O(\NlwInverterSignal_DCOR0CNTLOWr_MC.D1/IN6 )
  );
  X_INV \NlwInverterBlock_DCOR0CNTLOWr_MC.D1/IN7  (
    .I(U2_ADDR_reg[3]),
    .O(\NlwInverterSignal_DCOR0CNTLOWr_MC.D1/IN7 )
  );
  X_INV \NlwInverterBlock_DCOR0CNTLOWr_MC.D1/IN8  (
    .I(U2_ADDR_reg[1]),
    .O(\NlwInverterSignal_DCOR0CNTLOWr_MC.D1/IN8 )
  );
  X_INV \NlwInverterBlock_U1/U3/holdingreg1<0>_MC.D2_PT_1/IN1  (
    .I(\AS_II/UIM ),
    .O(\NlwInverterSignal_U1/U3/holdingreg1<0>_MC.D2_PT_1/IN1 )
  );
  X_INV \NlwInverterBlock_DCOR1CNTLOWr_MC.D1/IN1  (
    .I(\RD_II/UIM ),
    .O(\NlwInverterSignal_DCOR1CNTLOWr_MC.D1/IN1 )
  );
  X_INV \NlwInverterBlock_DCOR1CNTLOWr_MC.D1/IN2  (
    .I(U2_ADDR_reg[0]),
    .O(\NlwInverterSignal_DCOR1CNTLOWr_MC.D1/IN2 )
  );
  X_INV \NlwInverterBlock_DCOR1CNTLOWr_MC.D1/IN3  (
    .I(U2_ADDR_reg[4]),
    .O(\NlwInverterSignal_DCOR1CNTLOWr_MC.D1/IN3 )
  );
  X_INV \NlwInverterBlock_DCOR1CNTLOWr_MC.D1/IN4  (
    .I(U2_ADDR_reg[5]),
    .O(\NlwInverterSignal_DCOR1CNTLOWr_MC.D1/IN4 )
  );
  X_INV \NlwInverterBlock_DCOR1CNTLOWr_MC.D1/IN5  (
    .I(U2_ADDR_reg[6]),
    .O(\NlwInverterSignal_DCOR1CNTLOWr_MC.D1/IN5 )
  );
  X_INV \NlwInverterBlock_DCOR1CNTLOWr_MC.D1/IN6  (
    .I(U2_ADDR_reg[7]),
    .O(\NlwInverterSignal_DCOR1CNTLOWr_MC.D1/IN6 )
  );
  X_INV \NlwInverterBlock_DCOR1CNTLOWr_MC.D1/IN7  (
    .I(U2_ADDR_reg[3]),
    .O(\NlwInverterSignal_DCOR1CNTLOWr_MC.D1/IN7 )
  );
  X_INV \NlwInverterBlock_U1/U3/holdingreg0<8>_MC.D2_PT_1/IN1  (
    .I(\AS_II/UIM ),
    .O(\NlwInverterSignal_U1/U3/holdingreg0<8>_MC.D2_PT_1/IN1 )
  );
  X_INV \NlwInverterBlock_DCOR0CNTHIGHr_MC.D1/IN1  (
    .I(\RD_II/UIM ),
    .O(\NlwInverterSignal_DCOR0CNTHIGHr_MC.D1/IN1 )
  );
  X_INV \NlwInverterBlock_DCOR0CNTHIGHr_MC.D1/IN3  (
    .I(U2_ADDR_reg[4]),
    .O(\NlwInverterSignal_DCOR0CNTHIGHr_MC.D1/IN3 )
  );
  X_INV \NlwInverterBlock_DCOR0CNTHIGHr_MC.D1/IN4  (
    .I(U2_ADDR_reg[5]),
    .O(\NlwInverterSignal_DCOR0CNTHIGHr_MC.D1/IN4 )
  );
  X_INV \NlwInverterBlock_DCOR0CNTHIGHr_MC.D1/IN5  (
    .I(U2_ADDR_reg[6]),
    .O(\NlwInverterSignal_DCOR0CNTHIGHr_MC.D1/IN5 )
  );
  X_INV \NlwInverterBlock_DCOR0CNTHIGHr_MC.D1/IN6  (
    .I(U2_ADDR_reg[7]),
    .O(\NlwInverterSignal_DCOR0CNTHIGHr_MC.D1/IN6 )
  );
  X_INV \NlwInverterBlock_DCOR0CNTHIGHr_MC.D1/IN7  (
    .I(U2_ADDR_reg[3]),
    .O(\NlwInverterSignal_DCOR0CNTHIGHr_MC.D1/IN7 )
  );
  X_INV \NlwInverterBlock_DCOR0CNTHIGHr_MC.D1/IN8  (
    .I(U2_ADDR_reg[1]),
    .O(\NlwInverterSignal_DCOR0CNTHIGHr_MC.D1/IN8 )
  );
  X_INV \NlwInverterBlock_U1/U3/holdingreg1<8>_MC.D2_PT_1/IN1  (
    .I(\AS_II/UIM ),
    .O(\NlwInverterSignal_U1/U3/holdingreg1<8>_MC.D2_PT_1/IN1 )
  );
  X_INV \NlwInverterBlock_N_PZ_1017_MC.D1/IN0  (
    .I(DCOR0CNTLOWr),
    .O(\NlwInverterSignal_N_PZ_1017_MC.D1/IN0 )
  );
  X_INV \NlwInverterBlock_N_PZ_1017_MC.D1/IN1  (
    .I(DCOR1CNTLOWr),
    .O(\NlwInverterSignal_N_PZ_1017_MC.D1/IN1 )
  );
  X_INV \NlwInverterBlock_N_PZ_1017_MC.D1/IN2  (
    .I(DCOR0CNTHIGHr),
    .O(\NlwInverterSignal_N_PZ_1017_MC.D1/IN2 )
  );
  X_INV \NlwInverterBlock_N_PZ_1017_MC.D1/IN3  (
    .I(DCOR1CNTHIGHr),
    .O(\NlwInverterSignal_N_PZ_1017_MC.D1/IN3 )
  );
  X_INV \NlwInverterBlock_DCOR1CNTHIGHr_MC.D1/IN1  (
    .I(\RD_II/UIM ),
    .O(\NlwInverterSignal_DCOR1CNTHIGHr_MC.D1/IN1 )
  );
  X_INV \NlwInverterBlock_DCOR1CNTHIGHr_MC.D1/IN3  (
    .I(U2_ADDR_reg[4]),
    .O(\NlwInverterSignal_DCOR1CNTHIGHr_MC.D1/IN3 )
  );
  X_INV \NlwInverterBlock_DCOR1CNTHIGHr_MC.D1/IN4  (
    .I(U2_ADDR_reg[5]),
    .O(\NlwInverterSignal_DCOR1CNTHIGHr_MC.D1/IN4 )
  );
  X_INV \NlwInverterBlock_DCOR1CNTHIGHr_MC.D1/IN5  (
    .I(U2_ADDR_reg[6]),
    .O(\NlwInverterSignal_DCOR1CNTHIGHr_MC.D1/IN5 )
  );
  X_INV \NlwInverterBlock_DCOR1CNTHIGHr_MC.D1/IN6  (
    .I(U2_ADDR_reg[7]),
    .O(\NlwInverterSignal_DCOR1CNTHIGHr_MC.D1/IN6 )
  );
  X_INV \NlwInverterBlock_DCOR1CNTHIGHr_MC.D1/IN7  (
    .I(U2_ADDR_reg[3]),
    .O(\NlwInverterSignal_DCOR1CNTHIGHr_MC.D1/IN7 )
  );
  X_INV \NlwInverterBlock_N_PZ_1053_MC.D1/IN0  (
    .I(DCOR0THRESLOWr),
    .O(\NlwInverterSignal_N_PZ_1053_MC.D1/IN0 )
  );
  X_INV \NlwInverterBlock_N_PZ_1053_MC.D1/IN1  (
    .I(DCORIFGr),
    .O(\NlwInverterSignal_N_PZ_1053_MC.D1/IN1 )
  );
  X_INV \NlwInverterBlock_N_PZ_1053_MC.D1/IN2  (
    .I(DCOR0THRESHIGHr),
    .O(\NlwInverterSignal_N_PZ_1053_MC.D1/IN2 )
  );
  X_INV \NlwInverterBlock_N_PZ_1053_MC.D1/IN3  (
    .I(DCOR1THRESLOWr),
    .O(\NlwInverterSignal_N_PZ_1053_MC.D1/IN3 )
  );
  X_INV \NlwInverterBlock_N_PZ_1053_MC.D1/IN4  (
    .I(DCOR1THRESHIGHr),
    .O(\NlwInverterSignal_N_PZ_1053_MC.D1/IN4 )
  );
  X_INV \NlwInverterBlock_DCOR1THRESHIGHr_MC.D1/IN1  (
    .I(\RD_II/UIM ),
    .O(\NlwInverterSignal_DCOR1THRESHIGHr_MC.D1/IN1 )
  );
  X_INV \NlwInverterBlock_DCOR1THRESHIGHr_MC.D1/IN3  (
    .I(U2_ADDR_reg[4]),
    .O(\NlwInverterSignal_DCOR1THRESHIGHr_MC.D1/IN3 )
  );
  X_INV \NlwInverterBlock_DCOR1THRESHIGHr_MC.D1/IN4  (
    .I(U2_ADDR_reg[5]),
    .O(\NlwInverterSignal_DCOR1THRESHIGHr_MC.D1/IN4 )
  );
  X_INV \NlwInverterBlock_DCOR1THRESHIGHr_MC.D1/IN5  (
    .I(U2_ADDR_reg[6]),
    .O(\NlwInverterSignal_DCOR1THRESHIGHr_MC.D1/IN5 )
  );
  X_INV \NlwInverterBlock_DCOR1THRESHIGHr_MC.D1/IN6  (
    .I(U2_ADDR_reg[7]),
    .O(\NlwInverterSignal_DCOR1THRESHIGHr_MC.D1/IN6 )
  );
  X_INV \NlwInverterBlock_DCOR1THRESHIGHr_MC.D1/IN9  (
    .I(U2_ADDR_reg[2]),
    .O(\NlwInverterSignal_DCOR1THRESHIGHr_MC.D1/IN9 )
  );
  X_INV \NlwInverterBlock_U2_Enable_AD_MC.D1/IN1  (
    .I(\RD_II/UIM ),
    .O(\NlwInverterSignal_U2_Enable_AD_MC.D1/IN1 )
  );
  X_INV \NlwInverterBlock_U2_Enable_AD_MC.D1/IN2  (
    .I(U2_ADDR_reg[4]),
    .O(\NlwInverterSignal_U2_Enable_AD_MC.D1/IN2 )
  );
  X_INV \NlwInverterBlock_U2_Enable_AD_MC.D1/IN3  (
    .I(U2_ADDR_reg[5]),
    .O(\NlwInverterSignal_U2_Enable_AD_MC.D1/IN3 )
  );
  X_INV \NlwInverterBlock_U2_Enable_AD_MC.D1/IN4  (
    .I(U2_ADDR_reg[6]),
    .O(\NlwInverterSignal_U2_Enable_AD_MC.D1/IN4 )
  );
  X_INV \NlwInverterBlock_U2_Enable_AD_MC.D1/IN5  (
    .I(U2_ADDR_reg[7]),
    .O(\NlwInverterSignal_U2_Enable_AD_MC.D1/IN5 )
  );
  X_INV \NlwInverterBlock_AD<1>_MC.D/IN0  (
    .I(\AD<1>_MC.D1 ),
    .O(\NlwInverterSignal_AD<1>_MC.D/IN0 )
  );
  X_INV \NlwInverterBlock_AD<1>_MC.D2_PT_0/IN1  (
    .I(\outDATA<1>\$WA0.UIM ),
    .O(\NlwInverterSignal_AD<1>_MC.D2_PT_0/IN1 )
  );
  X_INV \NlwInverterBlock_AD<1>_MC.D2_PT_1/IN1  (
    .I(\outDATA<1>\$WA2.UIM ),
    .O(\NlwInverterSignal_AD<1>_MC.D2_PT_1/IN1 )
  );
  X_INV \NlwInverterBlock_AD<1>_MC.D2_PT_2/IN1  (
    .I(\outDATA<1>\$WA3.UIM ),
    .O(\NlwInverterSignal_AD<1>_MC.D2_PT_2/IN1 )
  );
  X_INV \NlwInverterBlock_AD<1>_MC.D2_PT_3/IN1  (
    .I(\outDATA<1>\$WA5.UIM ),
    .O(\NlwInverterSignal_AD<1>_MC.D2_PT_3/IN1 )
  );
  X_INV \NlwInverterBlock_AD<1>_MC.D2_PT_4/IN1  (
    .I(\outDATA<1>\$WA5.UIM ),
    .O(\NlwInverterSignal_AD<1>_MC.D2_PT_4/IN1 )
  );
  X_INV \NlwInverterBlock_AD<1>_MC.D2_PT_5/IN0  (
    .I(N_PZ_1016),
    .O(\NlwInverterSignal_AD<1>_MC.D2_PT_5/IN0 )
  );
  X_INV \NlwInverterBlock_AD<1>_MC.D2_PT_5/IN1  (
    .I(\outDATA<1>\$WA4.UIM ),
    .O(\NlwInverterSignal_AD<1>_MC.D2_PT_5/IN1 )
  );
  X_INV \NlwInverterBlock_AD<1>_MC.D2_PT_6/IN0  (
    .I(N_PZ_1017),
    .O(\NlwInverterSignal_AD<1>_MC.D2_PT_6/IN0 )
  );
  X_INV \NlwInverterBlock_AD<1>_MC.D2_PT_6/IN1  (
    .I(\outDATA<1>\$WA1.UIM ),
    .O(\NlwInverterSignal_AD<1>_MC.D2_PT_6/IN1 )
  );
  X_INV \NlwInverterBlock_AD<1>_MC.D2_PT_7/IN0  (
    .I(DCORIFGr),
    .O(\NlwInverterSignal_AD<1>_MC.D2_PT_7/IN0 )
  );
  X_INV \NlwInverterBlock_AD<1>_MC.D2_PT_7/IN1  (
    .I(N_PZ_1053),
    .O(\NlwInverterSignal_AD<1>_MC.D2_PT_7/IN1 )
  );
  X_INV \NlwInverterBlock_AD<1>_MC.D2_PT_7/IN2  (
    .I(\outDATA<1>\$WA2.UIM ),
    .O(\NlwInverterSignal_AD<1>_MC.D2_PT_7/IN2 )
  );
  X_INV \NlwInverterBlock_outDATA<1>\$WA2.UIM_MC.D2_PT_1/IN0  (
    .I(DCOR0THRESLOWr),
    .O(\NlwInverterSignal_outDATA<1>\$WA2.UIM_MC.D2_PT_1/IN0 )
  );
  X_INV \NlwInverterBlock_outDATA<1>\$WA2.UIM_MC.D2_PT_2/IN0  (
    .I(DCOR0THRESLOWr),
    .O(\NlwInverterSignal_outDATA<1>\$WA2.UIM_MC.D2_PT_2/IN0 )
  );
  X_INV \NlwInverterBlock_outDATA<1>\$WA2.UIM_MC.D2_PT_2/IN1  (
    .I(DCOR0THRESHIGHr),
    .O(\NlwInverterSignal_outDATA<1>\$WA2.UIM_MC.D2_PT_2/IN1 )
  );
  X_INV \NlwInverterBlock_outDATA<1>\$WA2.UIM_MC.D2_PT_3/IN0  (
    .I(DCOR0THRESLOWr),
    .O(\NlwInverterSignal_outDATA<1>\$WA2.UIM_MC.D2_PT_3/IN0 )
  );
  X_INV \NlwInverterBlock_outDATA<1>\$WA2.UIM_MC.D2_PT_3/IN1  (
    .I(DCOR0THRESHIGHr),
    .O(\NlwInverterSignal_outDATA<1>\$WA2.UIM_MC.D2_PT_3/IN1 )
  );
  X_INV \NlwInverterBlock_outDATA<1>\$WA2.UIM_MC.D2_PT_3/IN2  (
    .I(DCOR1THRESLOWr),
    .O(\NlwInverterSignal_outDATA<1>\$WA2.UIM_MC.D2_PT_3/IN2 )
  );
  X_INV \NlwInverterBlock_U1/U4/Latch0r<1>_MC.D2_PT_1/IN1  (
    .I(N_PZ_1018),
    .O(\NlwInverterSignal_U1/U4/Latch0r<1>_MC.D2_PT_1/IN1 )
  );
  X_INV \NlwInverterBlock_U1/U4/Latch0r<9>_MC.D2_PT_1/IN1  (
    .I(N_PZ_1018),
    .O(\NlwInverterSignal_U1/U4/Latch0r<9>_MC.D2_PT_1/IN1 )
  );
  X_INV \NlwInverterBlock_U1/Channel0<9>_MC.D2_PT_0/IN0  (
    .I(N_PZ_982),
    .O(\NlwInverterSignal_U1/Channel0<9>_MC.D2_PT_0/IN0 )
  );
  X_INV \NlwInverterBlock_U1/Channel0<9>_MC.D2_PT_2/IN0  (
    .I(\U1/U2/location_Maddsub__n0000__n0075 [0]),
    .O(\NlwInverterSignal_U1/Channel0<9>_MC.D2_PT_2/IN0 )
  );
  X_INV \NlwInverterBlock_U1/U4/Latch1r<1>_MC.D2_PT_1/IN1  (
    .I(N_PZ_1019),
    .O(\NlwInverterSignal_U1/U4/Latch1r<1>_MC.D2_PT_1/IN1 )
  );
  X_INV \NlwInverterBlock_U1/U4/Latch1r<9>_MC.D2_PT_1/IN1  (
    .I(N_PZ_1019),
    .O(\NlwInverterSignal_U1/U4/Latch1r<9>_MC.D2_PT_1/IN1 )
  );
  X_INV \NlwInverterBlock_U1/Channel1<9>_MC.D2_PT_0/IN0  (
    .I(N_PZ_983),
    .O(\NlwInverterSignal_U1/Channel1<9>_MC.D2_PT_0/IN0 )
  );
  X_INV \NlwInverterBlock_U1/Channel1<9>_MC.D2_PT_1/IN1  (
    .I(\U1/Zero1 ),
    .O(\NlwInverterSignal_U1/Channel1<9>_MC.D2_PT_1/IN1 )
  );
  X_INV \NlwInverterBlock_U1/Channel1<9>_MC.D2_PT_1/IN3  (
    .I(\U1/U6/CurrState_Sreg0_FFD2 ),
    .O(\NlwInverterSignal_U1/Channel1<9>_MC.D2_PT_1/IN3 )
  );
  X_INV \NlwInverterBlock_U1/Channel1<9>_MC.D2_PT_1/IN5  (
    .I(\U1/U5/location_Maddsub__n0000__n0075 [0]),
    .O(\NlwInverterSignal_U1/Channel1<9>_MC.D2_PT_1/IN5 )
  );
  X_INV \NlwInverterBlock_U1/Channel1<9>_MC.D2_PT_2/IN1  (
    .I(\U1/Zero1 ),
    .O(\NlwInverterSignal_U1/Channel1<9>_MC.D2_PT_2/IN1 )
  );
  X_INV \NlwInverterBlock_U1/Channel1<9>_MC.D2_PT_2/IN3  (
    .I(\U1/U6/CurrState_Sreg0_FFD2 ),
    .O(\NlwInverterSignal_U1/Channel1<9>_MC.D2_PT_2/IN3 )
  );
  X_INV \NlwInverterBlock_U1/Channel1<9>_MC.D2_PT_2/IN5  (
    .I(N_PZ_975),
    .O(\NlwInverterSignal_U1/Channel1<9>_MC.D2_PT_2/IN5 )
  );
  X_INV \NlwInverterBlock_outDATA<1>\$WA5.UIM_MC.D2_PT_0/IN0  (
    .I(DCORENCPWRr),
    .O(\NlwInverterSignal_outDATA<1>\$WA5.UIM_MC.D2_PT_0/IN0 )
  );
  X_INV \NlwInverterBlock_outDATA<1>\$WA5.UIM_MC.D2_PT_2/IN1  (
    .I(NET2528),
    .O(\NlwInverterSignal_outDATA<1>\$WA5.UIM_MC.D2_PT_2/IN1 )
  );
  X_INV \NlwInverterBlock_outDATA<1>\$WA4.UIM_MC.D2_PT_0/IN1  (
    .I(\FLS0_II/UIM ),
    .O(\NlwInverterSignal_outDATA<1>\$WA4.UIM_MC.D2_PT_0/IN1 )
  );
  X_INV \NlwInverterBlock_outDATA<1>\$WA4.UIM_MC.D2_PT_1/IN0  (
    .I(DCORLIMITSr),
    .O(\NlwInverterSignal_outDATA<1>\$WA4.UIM_MC.D2_PT_1/IN0 )
  );
  X_INV \NlwInverterBlock_U5/FLS0fr_MC.D2_PT_0/IN1  (
    .I(DCORLINTr),
    .O(\NlwInverterSignal_U5/FLS0fr_MC.D2_PT_0/IN1 )
  );
  X_INV \NlwInverterBlock_U5/FLS0fr_MC.D2_PT_1/IN1  (
    .I(DCORLINTr),
    .O(\NlwInverterSignal_U5/FLS0fr_MC.D2_PT_1/IN1 )
  );
  X_INV \NlwInverterBlock_U5/FLS0fr_MC.D2_PT_1/IN3  (
    .I(\FLS0_II/UIM ),
    .O(\NlwInverterSignal_U5/FLS0fr_MC.D2_PT_1/IN3 )
  );
  X_INV \NlwInverterBlock_outDATA<1>\$WA1.UIM_MC.D2_PT_1/IN0  (
    .I(DCOR0CNTLOWr),
    .O(\NlwInverterSignal_outDATA<1>\$WA1.UIM_MC.D2_PT_1/IN0 )
  );
  X_INV \NlwInverterBlock_outDATA<1>\$WA1.UIM_MC.D2_PT_2/IN0  (
    .I(DCOR0CNTLOWr),
    .O(\NlwInverterSignal_outDATA<1>\$WA1.UIM_MC.D2_PT_2/IN0 )
  );
  X_INV \NlwInverterBlock_outDATA<1>\$WA1.UIM_MC.D2_PT_2/IN1  (
    .I(DCOR1CNTLOWr),
    .O(\NlwInverterSignal_outDATA<1>\$WA1.UIM_MC.D2_PT_2/IN1 )
  );
  X_INV \NlwInverterBlock_outDATA<1>\$WA1.UIM_MC.D2_PT_3/IN0  (
    .I(DCOR0CNTLOWr),
    .O(\NlwInverterSignal_outDATA<1>\$WA1.UIM_MC.D2_PT_3/IN0 )
  );
  X_INV \NlwInverterBlock_outDATA<1>\$WA1.UIM_MC.D2_PT_3/IN1  (
    .I(DCOR1CNTLOWr),
    .O(\NlwInverterSignal_outDATA<1>\$WA1.UIM_MC.D2_PT_3/IN1 )
  );
  X_INV \NlwInverterBlock_outDATA<1>\$WA1.UIM_MC.D2_PT_3/IN2  (
    .I(DCOR0CNTHIGHr),
    .O(\NlwInverterSignal_outDATA<1>\$WA1.UIM_MC.D2_PT_3/IN2 )
  );
  X_INV \NlwInverterBlock_U1/U3/holdingreg0<1>_MC.D2_PT_1/IN1  (
    .I(\AS_II/UIM ),
    .O(\NlwInverterSignal_U1/U3/holdingreg0<1>_MC.D2_PT_1/IN1 )
  );
  X_INV \NlwInverterBlock_U1/U3/holdingreg1<1>_MC.D2_PT_1/IN1  (
    .I(\AS_II/UIM ),
    .O(\NlwInverterSignal_U1/U3/holdingreg1<1>_MC.D2_PT_1/IN1 )
  );
  X_INV \NlwInverterBlock_U1/U3/holdingreg0<9>_MC.D2_PT_1/IN1  (
    .I(\AS_II/UIM ),
    .O(\NlwInverterSignal_U1/U3/holdingreg0<9>_MC.D2_PT_1/IN1 )
  );
  X_INV \NlwInverterBlock_U1/U3/holdingreg1<9>_MC.D2_PT_1/IN1  (
    .I(\AS_II/UIM ),
    .O(\NlwInverterSignal_U1/U3/holdingreg1<9>_MC.D2_PT_1/IN1 )
  );
  X_INV \NlwInverterBlock_AD<4>_MC.D/IN0  (
    .I(\AD<4>_MC.D1 ),
    .O(\NlwInverterSignal_AD<4>_MC.D/IN0 )
  );
  X_INV \NlwInverterBlock_AD<4>_MC.D2_PT_0/IN1  (
    .I(\outDATA<4>\$WA0.UIM ),
    .O(\NlwInverterSignal_AD<4>_MC.D2_PT_0/IN1 )
  );
  X_INV \NlwInverterBlock_AD<4>_MC.D2_PT_1/IN1  (
    .I(\outDATA<4>\$WA2.UIM ),
    .O(\NlwInverterSignal_AD<4>_MC.D2_PT_1/IN1 )
  );
  X_INV \NlwInverterBlock_AD<4>_MC.D2_PT_2/IN1  (
    .I(\outDATA<4>\$WA3.UIM ),
    .O(\NlwInverterSignal_AD<4>_MC.D2_PT_2/IN1 )
  );
  X_INV \NlwInverterBlock_AD<4>_MC.D2_PT_3/IN1  (
    .I(\outDATA<4>\$WA5.UIM ),
    .O(\NlwInverterSignal_AD<4>_MC.D2_PT_3/IN1 )
  );
  X_INV \NlwInverterBlock_AD<4>_MC.D2_PT_4/IN1  (
    .I(\outDATA<4>\$WA6.UIM ),
    .O(\NlwInverterSignal_AD<4>_MC.D2_PT_4/IN1 )
  );
  X_INV \NlwInverterBlock_AD<4>_MC.D2_PT_5/IN0  (
    .I(N_PZ_1016),
    .O(\NlwInverterSignal_AD<4>_MC.D2_PT_5/IN0 )
  );
  X_INV \NlwInverterBlock_AD<4>_MC.D2_PT_5/IN1  (
    .I(\outDATA<4>\$WA4.UIM ),
    .O(\NlwInverterSignal_AD<4>_MC.D2_PT_5/IN1 )
  );
  X_INV \NlwInverterBlock_AD<4>_MC.D2_PT_6/IN0  (
    .I(N_PZ_1017),
    .O(\NlwInverterSignal_AD<4>_MC.D2_PT_6/IN0 )
  );
  X_INV \NlwInverterBlock_AD<4>_MC.D2_PT_6/IN1  (
    .I(\outDATA<4>\$WA1.UIM ),
    .O(\NlwInverterSignal_AD<4>_MC.D2_PT_6/IN1 )
  );
  X_INV \NlwInverterBlock_AD<4>_MC.D2_PT_7/IN0  (
    .I(DCORIFGr),
    .O(\NlwInverterSignal_AD<4>_MC.D2_PT_7/IN0 )
  );
  X_INV \NlwInverterBlock_AD<4>_MC.D2_PT_7/IN1  (
    .I(N_PZ_1053),
    .O(\NlwInverterSignal_AD<4>_MC.D2_PT_7/IN1 )
  );
  X_INV \NlwInverterBlock_AD<4>_MC.D2_PT_7/IN2  (
    .I(\outDATA<4>\$WA2.UIM ),
    .O(\NlwInverterSignal_AD<4>_MC.D2_PT_7/IN2 )
  );
  X_INV \NlwInverterBlock_outDATA<4>\$WA2.UIM_MC.D2_PT_1/IN0  (
    .I(DCOR0THRESLOWr),
    .O(\NlwInverterSignal_outDATA<4>\$WA2.UIM_MC.D2_PT_1/IN0 )
  );
  X_INV \NlwInverterBlock_outDATA<4>\$WA2.UIM_MC.D2_PT_2/IN0  (
    .I(DCOR0THRESLOWr),
    .O(\NlwInverterSignal_outDATA<4>\$WA2.UIM_MC.D2_PT_2/IN0 )
  );
  X_INV \NlwInverterBlock_outDATA<4>\$WA2.UIM_MC.D2_PT_2/IN1  (
    .I(DCOR0THRESHIGHr),
    .O(\NlwInverterSignal_outDATA<4>\$WA2.UIM_MC.D2_PT_2/IN1 )
  );
  X_INV \NlwInverterBlock_outDATA<4>\$WA2.UIM_MC.D2_PT_3/IN0  (
    .I(DCOR0THRESLOWr),
    .O(\NlwInverterSignal_outDATA<4>\$WA2.UIM_MC.D2_PT_3/IN0 )
  );
  X_INV \NlwInverterBlock_outDATA<4>\$WA2.UIM_MC.D2_PT_3/IN1  (
    .I(DCOR0THRESHIGHr),
    .O(\NlwInverterSignal_outDATA<4>\$WA2.UIM_MC.D2_PT_3/IN1 )
  );
  X_INV \NlwInverterBlock_outDATA<4>\$WA2.UIM_MC.D2_PT_3/IN2  (
    .I(DCOR1THRESLOWr),
    .O(\NlwInverterSignal_outDATA<4>\$WA2.UIM_MC.D2_PT_3/IN2 )
  );
  X_INV \NlwInverterBlock_U1/U4/Latch0r<4>_MC.D2_PT_1/IN1  (
    .I(N_PZ_1018),
    .O(\NlwInverterSignal_U1/U4/Latch0r<4>_MC.D2_PT_1/IN1 )
  );
  X_INV \NlwInverterBlock_U1/U4/Latch0r<12>_MC.D2_PT_1/IN1  (
    .I(N_PZ_1018),
    .O(\NlwInverterSignal_U1/U4/Latch0r<12>_MC.D2_PT_1/IN1 )
  );
  X_INV \NlwInverterBlock_U1/Channel0<12>_MC.D2_PT_0/IN0  (
    .I(N_PZ_982),
    .O(\NlwInverterSignal_U1/Channel0<12>_MC.D2_PT_0/IN0 )
  );
  X_INV \NlwInverterBlock_U1/Channel0<12>_MC.D2_PT_1/IN2  (
    .I(\U1/Channel0 [9]),
    .O(\NlwInverterSignal_U1/Channel0<12>_MC.D2_PT_1/IN2 )
  );
  X_INV \NlwInverterBlock_U1/Channel0<12>_MC.D2_PT_1/IN3  (
    .I(\U1/Channel0 [10]),
    .O(\NlwInverterSignal_U1/Channel0<12>_MC.D2_PT_1/IN3 )
  );
  X_INV \NlwInverterBlock_U1/Channel0<12>_MC.D2_PT_1/IN4  (
    .I(\U1/Channel0 [11]),
    .O(\NlwInverterSignal_U1/Channel0<12>_MC.D2_PT_1/IN4 )
  );
  X_INV \NlwInverterBlock_U1/Channel0<12>_MC.D2_PT_2/IN0  (
    .I(\U1/U2/location_Maddsub__n0000__n0075 [0]),
    .O(\NlwInverterSignal_U1/Channel0<12>_MC.D2_PT_2/IN0 )
  );
  X_INV \NlwInverterBlock_U1/Channel0<10>_MC.D2_PT_0/IN0  (
    .I(N_PZ_982),
    .O(\NlwInverterSignal_U1/Channel0<10>_MC.D2_PT_0/IN0 )
  );
  X_INV \NlwInverterBlock_U1/Channel0<10>_MC.D2_PT_1/IN2  (
    .I(\U1/Channel0 [9]),
    .O(\NlwInverterSignal_U1/Channel0<10>_MC.D2_PT_1/IN2 )
  );
  X_INV \NlwInverterBlock_U1/Channel0<10>_MC.D2_PT_2/IN0  (
    .I(\U1/U2/location_Maddsub__n0000__n0075 [0]),
    .O(\NlwInverterSignal_U1/Channel0<10>_MC.D2_PT_2/IN0 )
  );
  X_INV \NlwInverterBlock_U1/Channel0<11>_MC.D2_PT_0/IN0  (
    .I(N_PZ_982),
    .O(\NlwInverterSignal_U1/Channel0<11>_MC.D2_PT_0/IN0 )
  );
  X_INV \NlwInverterBlock_U1/Channel0<11>_MC.D2_PT_1/IN2  (
    .I(\U1/Channel0 [9]),
    .O(\NlwInverterSignal_U1/Channel0<11>_MC.D2_PT_1/IN2 )
  );
  X_INV \NlwInverterBlock_U1/Channel0<11>_MC.D2_PT_1/IN3  (
    .I(\U1/Channel0 [10]),
    .O(\NlwInverterSignal_U1/Channel0<11>_MC.D2_PT_1/IN3 )
  );
  X_INV \NlwInverterBlock_U1/Channel0<11>_MC.D2_PT_2/IN0  (
    .I(\U1/U2/location_Maddsub__n0000__n0075 [0]),
    .O(\NlwInverterSignal_U1/Channel0<11>_MC.D2_PT_2/IN0 )
  );
  X_INV \NlwInverterBlock_U1/U4/Latch1r<4>_MC.D2_PT_1/IN1  (
    .I(N_PZ_1019),
    .O(\NlwInverterSignal_U1/U4/Latch1r<4>_MC.D2_PT_1/IN1 )
  );
  X_INV \NlwInverterBlock_U1/U4/Latch1r<12>_MC.D2_PT_1/IN1  (
    .I(N_PZ_1019),
    .O(\NlwInverterSignal_U1/U4/Latch1r<12>_MC.D2_PT_1/IN1 )
  );
  X_INV \NlwInverterBlock_U1/Channel1<12>_MC.D2_PT_0/IN0  (
    .I(N_PZ_983),
    .O(\NlwInverterSignal_U1/Channel1<12>_MC.D2_PT_0/IN0 )
  );
  X_INV \NlwInverterBlock_U1/Channel1<12>_MC.D2_PT_1/IN1  (
    .I(\U1/Zero1 ),
    .O(\NlwInverterSignal_U1/Channel1<12>_MC.D2_PT_1/IN1 )
  );
  X_INV \NlwInverterBlock_U1/Channel1<12>_MC.D2_PT_1/IN3  (
    .I(\U1/U6/CurrState_Sreg0_FFD2 ),
    .O(\NlwInverterSignal_U1/Channel1<12>_MC.D2_PT_1/IN3 )
  );
  X_INV \NlwInverterBlock_U1/Channel1<12>_MC.D2_PT_1/IN5  (
    .I(\U1/U5/location_Maddsub__n0000__n0075 [0]),
    .O(\NlwInverterSignal_U1/Channel1<12>_MC.D2_PT_1/IN5 )
  );
  X_INV \NlwInverterBlock_U1/Channel1<12>_MC.D2_PT_2/IN1  (
    .I(\U1/Zero1 ),
    .O(\NlwInverterSignal_U1/Channel1<12>_MC.D2_PT_2/IN1 )
  );
  X_INV \NlwInverterBlock_U1/Channel1<12>_MC.D2_PT_2/IN3  (
    .I(\U1/U6/CurrState_Sreg0_FFD2 ),
    .O(\NlwInverterSignal_U1/Channel1<12>_MC.D2_PT_2/IN3 )
  );
  X_INV \NlwInverterBlock_U1/Channel1<12>_MC.D2_PT_2/IN5  (
    .I(N_PZ_975),
    .O(\NlwInverterSignal_U1/Channel1<12>_MC.D2_PT_2/IN5 )
  );
  X_INV \NlwInverterBlock_U1/Channel1<12>_MC.D2_PT_2/IN7  (
    .I(\U1/Channel1 [9]),
    .O(\NlwInverterSignal_U1/Channel1<12>_MC.D2_PT_2/IN7 )
  );
  X_INV \NlwInverterBlock_U1/Channel1<12>_MC.D2_PT_2/IN8  (
    .I(\U1/Channel1 [10]),
    .O(\NlwInverterSignal_U1/Channel1<12>_MC.D2_PT_2/IN8 )
  );
  X_INV \NlwInverterBlock_U1/Channel1<12>_MC.D2_PT_2/IN9  (
    .I(\U1/Channel1 [11]),
    .O(\NlwInverterSignal_U1/Channel1<12>_MC.D2_PT_2/IN9 )
  );
  X_INV \NlwInverterBlock_U1/Channel1<10>_MC.D2_PT_0/IN0  (
    .I(N_PZ_983),
    .O(\NlwInverterSignal_U1/Channel1<10>_MC.D2_PT_0/IN0 )
  );
  X_INV \NlwInverterBlock_U1/Channel1<10>_MC.D2_PT_1/IN1  (
    .I(\U1/Zero1 ),
    .O(\NlwInverterSignal_U1/Channel1<10>_MC.D2_PT_1/IN1 )
  );
  X_INV \NlwInverterBlock_U1/Channel1<10>_MC.D2_PT_1/IN3  (
    .I(\U1/U6/CurrState_Sreg0_FFD2 ),
    .O(\NlwInverterSignal_U1/Channel1<10>_MC.D2_PT_1/IN3 )
  );
  X_INV \NlwInverterBlock_U1/Channel1<10>_MC.D2_PT_1/IN5  (
    .I(\U1/U5/location_Maddsub__n0000__n0075 [0]),
    .O(\NlwInverterSignal_U1/Channel1<10>_MC.D2_PT_1/IN5 )
  );
  X_INV \NlwInverterBlock_U1/Channel1<10>_MC.D2_PT_2/IN1  (
    .I(\U1/Zero1 ),
    .O(\NlwInverterSignal_U1/Channel1<10>_MC.D2_PT_2/IN1 )
  );
  X_INV \NlwInverterBlock_U1/Channel1<10>_MC.D2_PT_2/IN3  (
    .I(\U1/U6/CurrState_Sreg0_FFD2 ),
    .O(\NlwInverterSignal_U1/Channel1<10>_MC.D2_PT_2/IN3 )
  );
  X_INV \NlwInverterBlock_U1/Channel1<10>_MC.D2_PT_2/IN5  (
    .I(N_PZ_975),
    .O(\NlwInverterSignal_U1/Channel1<10>_MC.D2_PT_2/IN5 )
  );
  X_INV \NlwInverterBlock_U1/Channel1<10>_MC.D2_PT_2/IN7  (
    .I(\U1/Channel1 [9]),
    .O(\NlwInverterSignal_U1/Channel1<10>_MC.D2_PT_2/IN7 )
  );
  X_INV \NlwInverterBlock_U1/Channel1<11>_MC.D2_PT_0/IN0  (
    .I(N_PZ_983),
    .O(\NlwInverterSignal_U1/Channel1<11>_MC.D2_PT_0/IN0 )
  );
  X_INV \NlwInverterBlock_U1/Channel1<11>_MC.D2_PT_1/IN1  (
    .I(\U1/Zero1 ),
    .O(\NlwInverterSignal_U1/Channel1<11>_MC.D2_PT_1/IN1 )
  );
  X_INV \NlwInverterBlock_U1/Channel1<11>_MC.D2_PT_1/IN3  (
    .I(\U1/U6/CurrState_Sreg0_FFD2 ),
    .O(\NlwInverterSignal_U1/Channel1<11>_MC.D2_PT_1/IN3 )
  );
  X_INV \NlwInverterBlock_U1/Channel1<11>_MC.D2_PT_1/IN5  (
    .I(\U1/U5/location_Maddsub__n0000__n0075 [0]),
    .O(\NlwInverterSignal_U1/Channel1<11>_MC.D2_PT_1/IN5 )
  );
  X_INV \NlwInverterBlock_U1/Channel1<11>_MC.D2_PT_2/IN1  (
    .I(\U1/Zero1 ),
    .O(\NlwInverterSignal_U1/Channel1<11>_MC.D2_PT_2/IN1 )
  );
  X_INV \NlwInverterBlock_U1/Channel1<11>_MC.D2_PT_2/IN3  (
    .I(\U1/U6/CurrState_Sreg0_FFD2 ),
    .O(\NlwInverterSignal_U1/Channel1<11>_MC.D2_PT_2/IN3 )
  );
  X_INV \NlwInverterBlock_U1/Channel1<11>_MC.D2_PT_2/IN5  (
    .I(N_PZ_975),
    .O(\NlwInverterSignal_U1/Channel1<11>_MC.D2_PT_2/IN5 )
  );
  X_INV \NlwInverterBlock_U1/Channel1<11>_MC.D2_PT_2/IN7  (
    .I(\U1/Channel1 [9]),
    .O(\NlwInverterSignal_U1/Channel1<11>_MC.D2_PT_2/IN7 )
  );
  X_INV \NlwInverterBlock_U1/Channel1<11>_MC.D2_PT_2/IN8  (
    .I(\U1/Channel1 [10]),
    .O(\NlwInverterSignal_U1/Channel1<11>_MC.D2_PT_2/IN8 )
  );
  X_INV \NlwInverterBlock_outDATA<4>\$WA5.UIM_MC.D2_PT_1/IN0  (
    .I(NET2528),
    .O(\NlwInverterSignal_outDATA<4>\$WA5.UIM_MC.D2_PT_1/IN0 )
  );
  X_INV \NlwInverterBlock_NET2575_MC.D/IN0  (
    .I(\NET2575_MC.D1 ),
    .O(\NlwInverterSignal_NET2575_MC.D/IN0 )
  );
  X_INV \NlwInverterBlock_NET2575_MC.D2_PT_0/IN0  (
    .I(\MSPReset_II/UIM ),
    .O(\NlwInverterSignal_NET2575_MC.D2_PT_0/IN0 )
  );
  X_INV \NlwInverterBlock_NET2575_MC.D2_PT_0/IN1  (
    .I(\MSPReset_II/UIM ),
    .O(\NlwInverterSignal_NET2575_MC.D2_PT_0/IN1 )
  );
  X_INV \NlwInverterBlock_NET2575_MC.D2_PT_2/IN1  (
    .I(NET2575),
    .O(\NlwInverterSignal_NET2575_MC.D2_PT_2/IN1 )
  );
  X_INV \NlwInverterBlock_NET2575_MC.D2_PT_3/IN0  (
    .I(\U5/RLS0fr ),
    .O(\NlwInverterSignal_NET2575_MC.D2_PT_3/IN0 )
  );
  X_INV \NlwInverterBlock_NET2575_MC.D2_PT_3/IN1  (
    .I(\U5/FLS0fr ),
    .O(\NlwInverterSignal_NET2575_MC.D2_PT_3/IN1 )
  );
  X_INV \NlwInverterBlock_NET2575_MC.D2_PT_3/IN2  (
    .I(NET2575),
    .O(\NlwInverterSignal_NET2575_MC.D2_PT_3/IN2 )
  );
  X_INV \NlwInverterBlock_NET2575_MC.D2_PT_3/IN3  (
    .I(\U5/FLS1fr ),
    .O(\NlwInverterSignal_NET2575_MC.D2_PT_3/IN3 )
  );
  X_INV \NlwInverterBlock_NET2575_MC.D2_PT_3/IN4  (
    .I(\U5/RLS1fr ),
    .O(\NlwInverterSignal_NET2575_MC.D2_PT_3/IN4 )
  );
  X_INV \NlwInverterBlock_U5/FLS1fr_MC.D2_PT_0/IN1  (
    .I(DCORLINTr),
    .O(\NlwInverterSignal_U5/FLS1fr_MC.D2_PT_0/IN1 )
  );
  X_INV \NlwInverterBlock_U5/FLS1fr_MC.D2_PT_1/IN1  (
    .I(DCORLINTr),
    .O(\NlwInverterSignal_U5/FLS1fr_MC.D2_PT_1/IN1 )
  );
  X_INV \NlwInverterBlock_U5/FLS1fr_MC.D2_PT_1/IN3  (
    .I(\FLS1_II/UIM ),
    .O(\NlwInverterSignal_U5/FLS1fr_MC.D2_PT_1/IN3 )
  );
  X_INV \NlwInverterBlock_U5/RLS1fr_MC.D2_PT_0/IN1  (
    .I(DCORLINTr),
    .O(\NlwInverterSignal_U5/RLS1fr_MC.D2_PT_0/IN1 )
  );
  X_INV \NlwInverterBlock_U5/RLS1fr_MC.D2_PT_1/IN1  (
    .I(DCORLINTr),
    .O(\NlwInverterSignal_U5/RLS1fr_MC.D2_PT_1/IN1 )
  );
  X_INV \NlwInverterBlock_U5/RLS1fr_MC.D2_PT_1/IN2  (
    .I(\DIR1_II/UIM ),
    .O(\NlwInverterSignal_U5/RLS1fr_MC.D2_PT_1/IN2 )
  );
  X_INV \NlwInverterBlock_U5/RLS1fr_MC.D2_PT_1/IN3  (
    .I(\RLS1_II/UIM ),
    .O(\NlwInverterSignal_U5/RLS1fr_MC.D2_PT_1/IN3 )
  );
  X_INV \NlwInverterBlock_outDATA<4>\$WA4.UIM_MC.D2_PT_0/IN1  (
    .I(\RLS1_II/UIM ),
    .O(\NlwInverterSignal_outDATA<4>\$WA4.UIM_MC.D2_PT_0/IN1 )
  );
  X_INV \NlwInverterBlock_outDATA<4>\$WA4.UIM_MC.D2_PT_1/IN0  (
    .I(DCORLIMITSr),
    .O(\NlwInverterSignal_outDATA<4>\$WA4.UIM_MC.D2_PT_1/IN0 )
  );
  X_INV \NlwInverterBlock_outDATA<4>\$WA1.UIM_MC.D2_PT_1/IN0  (
    .I(DCOR0CNTLOWr),
    .O(\NlwInverterSignal_outDATA<4>\$WA1.UIM_MC.D2_PT_1/IN0 )
  );
  X_INV \NlwInverterBlock_outDATA<4>\$WA1.UIM_MC.D2_PT_2/IN0  (
    .I(DCOR0CNTLOWr),
    .O(\NlwInverterSignal_outDATA<4>\$WA1.UIM_MC.D2_PT_2/IN0 )
  );
  X_INV \NlwInverterBlock_outDATA<4>\$WA1.UIM_MC.D2_PT_2/IN1  (
    .I(DCOR1CNTLOWr),
    .O(\NlwInverterSignal_outDATA<4>\$WA1.UIM_MC.D2_PT_2/IN1 )
  );
  X_INV \NlwInverterBlock_outDATA<4>\$WA1.UIM_MC.D2_PT_3/IN0  (
    .I(DCOR0CNTLOWr),
    .O(\NlwInverterSignal_outDATA<4>\$WA1.UIM_MC.D2_PT_3/IN0 )
  );
  X_INV \NlwInverterBlock_outDATA<4>\$WA1.UIM_MC.D2_PT_3/IN1  (
    .I(DCOR1CNTLOWr),
    .O(\NlwInverterSignal_outDATA<4>\$WA1.UIM_MC.D2_PT_3/IN1 )
  );
  X_INV \NlwInverterBlock_outDATA<4>\$WA1.UIM_MC.D2_PT_3/IN2  (
    .I(DCOR0CNTHIGHr),
    .O(\NlwInverterSignal_outDATA<4>\$WA1.UIM_MC.D2_PT_3/IN2 )
  );
  X_INV \NlwInverterBlock_U1/U3/holdingreg0<4>_MC.D2_PT_1/IN1  (
    .I(\AS_II/UIM ),
    .O(\NlwInverterSignal_U1/U3/holdingreg0<4>_MC.D2_PT_1/IN1 )
  );
  X_INV \NlwInverterBlock_U1/U3/holdingreg1<4>_MC.D2_PT_1/IN1  (
    .I(\AS_II/UIM ),
    .O(\NlwInverterSignal_U1/U3/holdingreg1<4>_MC.D2_PT_1/IN1 )
  );
  X_INV \NlwInverterBlock_U1/U3/holdingreg0<12>_MC.D2_PT_1/IN1  (
    .I(\AS_II/UIM ),
    .O(\NlwInverterSignal_U1/U3/holdingreg0<12>_MC.D2_PT_1/IN1 )
  );
  X_INV \NlwInverterBlock_U1/U3/holdingreg1<12>_MC.D2_PT_1/IN1  (
    .I(\AS_II/UIM ),
    .O(\NlwInverterSignal_U1/U3/holdingreg1<12>_MC.D2_PT_1/IN1 )
  );
  X_INV \NlwInverterBlock_AD<5>_MC.D/IN0  (
    .I(\AD<5>_MC.D1 ),
    .O(\NlwInverterSignal_AD<5>_MC.D/IN0 )
  );
  X_INV \NlwInverterBlock_AD<5>_MC.D2_PT_0/IN1  (
    .I(\outDATA<5>\$WA0.UIM ),
    .O(\NlwInverterSignal_AD<5>_MC.D2_PT_0/IN1 )
  );
  X_INV \NlwInverterBlock_AD<5>_MC.D2_PT_1/IN1  (
    .I(\outDATA<5>\$WA3.UIM ),
    .O(\NlwInverterSignal_AD<5>_MC.D2_PT_1/IN1 )
  );
  X_INV \NlwInverterBlock_AD<5>_MC.D2_PT_2/IN1  (
    .I(\outDATA<5>\$WA5.UIM ),
    .O(\NlwInverterSignal_AD<5>_MC.D2_PT_2/IN1 )
  );
  X_INV \NlwInverterBlock_AD<5>_MC.D2_PT_3/IN0  (
    .I(N_PZ_1016),
    .O(\NlwInverterSignal_AD<5>_MC.D2_PT_3/IN0 )
  );
  X_INV \NlwInverterBlock_AD<5>_MC.D2_PT_3/IN1  (
    .I(\outDATA<5>\$WA4.UIM ),
    .O(\NlwInverterSignal_AD<5>_MC.D2_PT_3/IN1 )
  );
  X_INV \NlwInverterBlock_AD<5>_MC.D2_PT_4/IN0  (
    .I(N_PZ_1017),
    .O(\NlwInverterSignal_AD<5>_MC.D2_PT_4/IN0 )
  );
  X_INV \NlwInverterBlock_AD<5>_MC.D2_PT_4/IN1  (
    .I(\outDATA<5>\$WA1.UIM ),
    .O(\NlwInverterSignal_AD<5>_MC.D2_PT_4/IN1 )
  );
  X_INV \NlwInverterBlock_AD<5>_MC.D2_PT_5/IN0  (
    .I(N_PZ_1053),
    .O(\NlwInverterSignal_AD<5>_MC.D2_PT_5/IN0 )
  );
  X_INV \NlwInverterBlock_AD<5>_MC.D2_PT_5/IN1  (
    .I(\outDATA<5>\$WA2.UIM ),
    .O(\NlwInverterSignal_AD<5>_MC.D2_PT_5/IN1 )
  );
  X_INV \NlwInverterBlock_outDATA<5>\$WA5.UIM_MC.D2_PT_1/IN0  (
    .I(NET2528),
    .O(\NlwInverterSignal_outDATA<5>\$WA5.UIM_MC.D2_PT_1/IN0 )
  );
  X_INV \NlwInverterBlock_outDATA<5>\$WA4.UIM_MC.D2_PT_0/IN1  (
    .I(\FLS1_II/UIM ),
    .O(\NlwInverterSignal_outDATA<5>\$WA4.UIM_MC.D2_PT_0/IN1 )
  );
  X_INV \NlwInverterBlock_outDATA<5>\$WA4.UIM_MC.D2_PT_1/IN0  (
    .I(DCORLIMITSr),
    .O(\NlwInverterSignal_outDATA<5>\$WA4.UIM_MC.D2_PT_1/IN0 )
  );
  X_INV \NlwInverterBlock_outDATA<5>\$WA1.UIM_MC.D2_PT_1/IN0  (
    .I(DCOR0CNTLOWr),
    .O(\NlwInverterSignal_outDATA<5>\$WA1.UIM_MC.D2_PT_1/IN0 )
  );
  X_INV \NlwInverterBlock_outDATA<5>\$WA1.UIM_MC.D2_PT_2/IN0  (
    .I(DCOR0CNTLOWr),
    .O(\NlwInverterSignal_outDATA<5>\$WA1.UIM_MC.D2_PT_2/IN0 )
  );
  X_INV \NlwInverterBlock_outDATA<5>\$WA1.UIM_MC.D2_PT_2/IN1  (
    .I(DCOR1CNTLOWr),
    .O(\NlwInverterSignal_outDATA<5>\$WA1.UIM_MC.D2_PT_2/IN1 )
  );
  X_INV \NlwInverterBlock_outDATA<5>\$WA1.UIM_MC.D2_PT_3/IN0  (
    .I(DCOR0CNTLOWr),
    .O(\NlwInverterSignal_outDATA<5>\$WA1.UIM_MC.D2_PT_3/IN0 )
  );
  X_INV \NlwInverterBlock_outDATA<5>\$WA1.UIM_MC.D2_PT_3/IN1  (
    .I(DCOR1CNTLOWr),
    .O(\NlwInverterSignal_outDATA<5>\$WA1.UIM_MC.D2_PT_3/IN1 )
  );
  X_INV \NlwInverterBlock_outDATA<5>\$WA1.UIM_MC.D2_PT_3/IN2  (
    .I(DCOR0CNTHIGHr),
    .O(\NlwInverterSignal_outDATA<5>\$WA1.UIM_MC.D2_PT_3/IN2 )
  );
  X_INV \NlwInverterBlock_U1/U3/holdingreg0<5>_MC.D2_PT_1/IN1  (
    .I(\AS_II/UIM ),
    .O(\NlwInverterSignal_U1/U3/holdingreg0<5>_MC.D2_PT_1/IN1 )
  );
  X_INV \NlwInverterBlock_U1/U3/holdingreg1<5>_MC.D2_PT_1/IN1  (
    .I(\AS_II/UIM ),
    .O(\NlwInverterSignal_U1/U3/holdingreg1<5>_MC.D2_PT_1/IN1 )
  );
  X_INV \NlwInverterBlock_U1/U3/holdingreg0<13>_MC.D2_PT_1/IN1  (
    .I(\AS_II/UIM ),
    .O(\NlwInverterSignal_U1/U3/holdingreg0<13>_MC.D2_PT_1/IN1 )
  );
  X_INV \NlwInverterBlock_U1/Channel0<13>_MC.D2_PT_0/IN0  (
    .I(N_PZ_982),
    .O(\NlwInverterSignal_U1/Channel0<13>_MC.D2_PT_0/IN0 )
  );
  X_INV \NlwInverterBlock_U1/Channel0<13>_MC.D2_PT_1/IN2  (
    .I(\U1/Channel0 [9]),
    .O(\NlwInverterSignal_U1/Channel0<13>_MC.D2_PT_1/IN2 )
  );
  X_INV \NlwInverterBlock_U1/Channel0<13>_MC.D2_PT_1/IN3  (
    .I(\U1/Channel0 [12]),
    .O(\NlwInverterSignal_U1/Channel0<13>_MC.D2_PT_1/IN3 )
  );
  X_INV \NlwInverterBlock_U1/Channel0<13>_MC.D2_PT_1/IN4  (
    .I(\U1/Channel0 [10]),
    .O(\NlwInverterSignal_U1/Channel0<13>_MC.D2_PT_1/IN4 )
  );
  X_INV \NlwInverterBlock_U1/Channel0<13>_MC.D2_PT_1/IN5  (
    .I(\U1/Channel0 [11]),
    .O(\NlwInverterSignal_U1/Channel0<13>_MC.D2_PT_1/IN5 )
  );
  X_INV \NlwInverterBlock_U1/Channel0<13>_MC.D2_PT_2/IN0  (
    .I(\U1/U2/location_Maddsub__n0000__n0075 [0]),
    .O(\NlwInverterSignal_U1/Channel0<13>_MC.D2_PT_2/IN0 )
  );
  X_INV \NlwInverterBlock_U1/U3/holdingreg1<13>_MC.D2_PT_1/IN1  (
    .I(\AS_II/UIM ),
    .O(\NlwInverterSignal_U1/U3/holdingreg1<13>_MC.D2_PT_1/IN1 )
  );
  X_INV \NlwInverterBlock_U1/Channel1<13>_MC.D2_PT_0/IN0  (
    .I(N_PZ_983),
    .O(\NlwInverterSignal_U1/Channel1<13>_MC.D2_PT_0/IN0 )
  );
  X_INV \NlwInverterBlock_U1/Channel1<13>_MC.D2_PT_1/IN1  (
    .I(\U1/Zero1 ),
    .O(\NlwInverterSignal_U1/Channel1<13>_MC.D2_PT_1/IN1 )
  );
  X_INV \NlwInverterBlock_U1/Channel1<13>_MC.D2_PT_1/IN3  (
    .I(\U1/U6/CurrState_Sreg0_FFD2 ),
    .O(\NlwInverterSignal_U1/Channel1<13>_MC.D2_PT_1/IN3 )
  );
  X_INV \NlwInverterBlock_U1/Channel1<13>_MC.D2_PT_1/IN5  (
    .I(\U1/U5/location_Maddsub__n0000__n0075 [0]),
    .O(\NlwInverterSignal_U1/Channel1<13>_MC.D2_PT_1/IN5 )
  );
  X_INV \NlwInverterBlock_U1/Channel1<13>_MC.D2_PT_2/IN1  (
    .I(\U1/Zero1 ),
    .O(\NlwInverterSignal_U1/Channel1<13>_MC.D2_PT_2/IN1 )
  );
  X_INV \NlwInverterBlock_U1/Channel1<13>_MC.D2_PT_2/IN3  (
    .I(\U1/U6/CurrState_Sreg0_FFD2 ),
    .O(\NlwInverterSignal_U1/Channel1<13>_MC.D2_PT_2/IN3 )
  );
  X_INV \NlwInverterBlock_U1/Channel1<13>_MC.D2_PT_2/IN5  (
    .I(N_PZ_975),
    .O(\NlwInverterSignal_U1/Channel1<13>_MC.D2_PT_2/IN5 )
  );
  X_INV \NlwInverterBlock_U1/Channel1<13>_MC.D2_PT_2/IN7  (
    .I(\U1/Channel1 [9]),
    .O(\NlwInverterSignal_U1/Channel1<13>_MC.D2_PT_2/IN7 )
  );
  X_INV \NlwInverterBlock_U1/Channel1<13>_MC.D2_PT_2/IN8  (
    .I(\U1/Channel1 [12]),
    .O(\NlwInverterSignal_U1/Channel1<13>_MC.D2_PT_2/IN8 )
  );
  X_INV \NlwInverterBlock_U1/Channel1<13>_MC.D2_PT_2/IN9  (
    .I(\U1/Channel1 [10]),
    .O(\NlwInverterSignal_U1/Channel1<13>_MC.D2_PT_2/IN9 )
  );
  X_INV \NlwInverterBlock_U1/Channel1<13>_MC.D2_PT_2/IN10  (
    .I(\U1/Channel1 [11]),
    .O(\NlwInverterSignal_U1/Channel1<13>_MC.D2_PT_2/IN10 )
  );
  X_INV \NlwInverterBlock_outDATA<5>\$WA2.UIM_MC.D2_PT_1/IN0  (
    .I(DCOR0THRESLOWr),
    .O(\NlwInverterSignal_outDATA<5>\$WA2.UIM_MC.D2_PT_1/IN0 )
  );
  X_INV \NlwInverterBlock_outDATA<5>\$WA2.UIM_MC.D2_PT_2/IN0  (
    .I(DCOR0THRESLOWr),
    .O(\NlwInverterSignal_outDATA<5>\$WA2.UIM_MC.D2_PT_2/IN0 )
  );
  X_INV \NlwInverterBlock_outDATA<5>\$WA2.UIM_MC.D2_PT_2/IN1  (
    .I(DCORIFGr),
    .O(\NlwInverterSignal_outDATA<5>\$WA2.UIM_MC.D2_PT_2/IN1 )
  );
  X_INV \NlwInverterBlock_outDATA<5>\$WA2.UIM_MC.D2_PT_3/IN0  (
    .I(DCOR0THRESLOWr),
    .O(\NlwInverterSignal_outDATA<5>\$WA2.UIM_MC.D2_PT_3/IN0 )
  );
  X_INV \NlwInverterBlock_outDATA<5>\$WA2.UIM_MC.D2_PT_3/IN1  (
    .I(DCORIFGr),
    .O(\NlwInverterSignal_outDATA<5>\$WA2.UIM_MC.D2_PT_3/IN1 )
  );
  X_INV \NlwInverterBlock_outDATA<5>\$WA2.UIM_MC.D2_PT_3/IN2  (
    .I(DCOR0THRESHIGHr),
    .O(\NlwInverterSignal_outDATA<5>\$WA2.UIM_MC.D2_PT_3/IN2 )
  );
  X_INV \NlwInverterBlock_outDATA<5>\$WA2.UIM_MC.D2_PT_4/IN0  (
    .I(DCOR0THRESLOWr),
    .O(\NlwInverterSignal_outDATA<5>\$WA2.UIM_MC.D2_PT_4/IN0 )
  );
  X_INV \NlwInverterBlock_outDATA<5>\$WA2.UIM_MC.D2_PT_4/IN1  (
    .I(DCORIFGr),
    .O(\NlwInverterSignal_outDATA<5>\$WA2.UIM_MC.D2_PT_4/IN1 )
  );
  X_INV \NlwInverterBlock_outDATA<5>\$WA2.UIM_MC.D2_PT_4/IN2  (
    .I(DCOR0THRESHIGHr),
    .O(\NlwInverterSignal_outDATA<5>\$WA2.UIM_MC.D2_PT_4/IN2 )
  );
  X_INV \NlwInverterBlock_outDATA<5>\$WA2.UIM_MC.D2_PT_4/IN3  (
    .I(DCOR1THRESLOWr),
    .O(\NlwInverterSignal_outDATA<5>\$WA2.UIM_MC.D2_PT_4/IN3 )
  );
  X_INV \NlwInverterBlock_U1/U4/Latch0r<5>_MC.D2_PT_1/IN1  (
    .I(N_PZ_1018),
    .O(\NlwInverterSignal_U1/U4/Latch0r<5>_MC.D2_PT_1/IN1 )
  );
  X_INV \NlwInverterBlock_U1/U4/Latch0r<13>_MC.D2_PT_1/IN1  (
    .I(N_PZ_1018),
    .O(\NlwInverterSignal_U1/U4/Latch0r<13>_MC.D2_PT_1/IN1 )
  );
  X_INV \NlwInverterBlock_U1/U4/Latch1r<5>_MC.D2_PT_1/IN1  (
    .I(N_PZ_1019),
    .O(\NlwInverterSignal_U1/U4/Latch1r<5>_MC.D2_PT_1/IN1 )
  );
  X_INV \NlwInverterBlock_U1/U4/Latch1r<13>_MC.D2_PT_1/IN1  (
    .I(N_PZ_1019),
    .O(\NlwInverterSignal_U1/U4/Latch1r<13>_MC.D2_PT_1/IN1 )
  );
  X_INV \NlwInverterBlock_Enc033ctrl_MC.D/IN0  (
    .I(\Enc033ctrl_MC.D1 ),
    .O(\NlwInverterSignal_Enc033ctrl_MC.D/IN0 )
  );
  X_INV \NlwInverterBlock_Enc033ctrl_MC.D1/IN1  (
    .I(\U4/ctrlr[3] ),
    .O(\NlwInverterSignal_Enc033ctrl_MC.D1/IN1 )
  );
  X_INV \NlwInverterBlock_U4/ctrlr<2>_MC.D/IN0  (
    .I(\U4/ctrlr<2>_MC.D1 ),
    .O(\NlwInverterSignal_U4/ctrlr<2>_MC.D/IN0 )
  );
  X_INV \NlwInverterBlock_U4/ctrlr<2>_MC.D2_PT_0/IN1  (
    .I(\outDATA<2>\$WA0.UIM ),
    .O(\NlwInverterSignal_U4/ctrlr<2>_MC.D2_PT_0/IN1 )
  );
  X_INV \NlwInverterBlock_U4/ctrlr<2>_MC.D2_PT_1/IN1  (
    .I(\outDATA<2>\$WA3.UIM ),
    .O(\NlwInverterSignal_U4/ctrlr<2>_MC.D2_PT_1/IN1 )
  );
  X_INV \NlwInverterBlock_U4/ctrlr<2>_MC.D2_PT_2/IN1  (
    .I(\outDATA<2>\$WA5.UIM ),
    .O(\NlwInverterSignal_U4/ctrlr<2>_MC.D2_PT_2/IN1 )
  );
  X_INV \NlwInverterBlock_U4/ctrlr<2>_MC.D2_PT_3/IN0  (
    .I(N_PZ_1016),
    .O(\NlwInverterSignal_U4/ctrlr<2>_MC.D2_PT_3/IN0 )
  );
  X_INV \NlwInverterBlock_U4/ctrlr<2>_MC.D2_PT_3/IN1  (
    .I(\outDATA<2>\$WA4.UIM ),
    .O(\NlwInverterSignal_U4/ctrlr<2>_MC.D2_PT_3/IN1 )
  );
  X_INV \NlwInverterBlock_U4/ctrlr<2>_MC.D2_PT_4/IN0  (
    .I(N_PZ_1017),
    .O(\NlwInverterSignal_U4/ctrlr<2>_MC.D2_PT_4/IN0 )
  );
  X_INV \NlwInverterBlock_U4/ctrlr<2>_MC.D2_PT_4/IN1  (
    .I(\outDATA<2>\$WA1.UIM ),
    .O(\NlwInverterSignal_U4/ctrlr<2>_MC.D2_PT_4/IN1 )
  );
  X_INV \NlwInverterBlock_U4/ctrlr<2>_MC.D2_PT_5/IN0  (
    .I(N_PZ_1053),
    .O(\NlwInverterSignal_U4/ctrlr<2>_MC.D2_PT_5/IN0 )
  );
  X_INV \NlwInverterBlock_U4/ctrlr<2>_MC.D2_PT_5/IN1  (
    .I(\outDATA<2>\$WA2.UIM ),
    .O(\NlwInverterSignal_U4/ctrlr<2>_MC.D2_PT_5/IN1 )
  );
  X_INV \NlwInverterBlock_DCORENCPWRw_MC.D1/IN0  (
    .I(\WR_II/UIM ),
    .O(\NlwInverterSignal_DCORENCPWRw_MC.D1/IN0 )
  );
  X_INV \NlwInverterBlock_DCORENCPWRw_MC.D1/IN2  (
    .I(U2_ADDR_reg[0]),
    .O(\NlwInverterSignal_DCORENCPWRw_MC.D1/IN2 )
  );
  X_INV \NlwInverterBlock_DCORENCPWRw_MC.D1/IN3  (
    .I(U2_ADDR_reg[4]),
    .O(\NlwInverterSignal_DCORENCPWRw_MC.D1/IN3 )
  );
  X_INV \NlwInverterBlock_DCORENCPWRw_MC.D1/IN4  (
    .I(U2_ADDR_reg[5]),
    .O(\NlwInverterSignal_DCORENCPWRw_MC.D1/IN4 )
  );
  X_INV \NlwInverterBlock_DCORENCPWRw_MC.D1/IN5  (
    .I(U2_ADDR_reg[6]),
    .O(\NlwInverterSignal_DCORENCPWRw_MC.D1/IN5 )
  );
  X_INV \NlwInverterBlock_DCORENCPWRw_MC.D1/IN6  (
    .I(U2_ADDR_reg[7]),
    .O(\NlwInverterSignal_DCORENCPWRw_MC.D1/IN6 )
  );
  X_INV \NlwInverterBlock_U4/ctrlr<3>_MC.D/IN0  (
    .I(\U4/ctrlr<3>_MC.D1 ),
    .O(\NlwInverterSignal_U4/ctrlr<3>_MC.D/IN0 )
  );
  X_INV \NlwInverterBlock_U4/ctrlr<3>_MC.D2_PT_0/IN1  (
    .I(\outDATA<3>\$WA0.UIM ),
    .O(\NlwInverterSignal_U4/ctrlr<3>_MC.D2_PT_0/IN1 )
  );
  X_INV \NlwInverterBlock_U4/ctrlr<3>_MC.D2_PT_1/IN1  (
    .I(\outDATA<3>\$WA3.UIM ),
    .O(\NlwInverterSignal_U4/ctrlr<3>_MC.D2_PT_1/IN1 )
  );
  X_INV \NlwInverterBlock_U4/ctrlr<3>_MC.D2_PT_2/IN1  (
    .I(\outDATA<3>\$WA5.UIM ),
    .O(\NlwInverterSignal_U4/ctrlr<3>_MC.D2_PT_2/IN1 )
  );
  X_INV \NlwInverterBlock_U4/ctrlr<3>_MC.D2_PT_3/IN0  (
    .I(N_PZ_1016),
    .O(\NlwInverterSignal_U4/ctrlr<3>_MC.D2_PT_3/IN0 )
  );
  X_INV \NlwInverterBlock_U4/ctrlr<3>_MC.D2_PT_3/IN1  (
    .I(\outDATA<3>\$WA4.UIM ),
    .O(\NlwInverterSignal_U4/ctrlr<3>_MC.D2_PT_3/IN1 )
  );
  X_INV \NlwInverterBlock_U4/ctrlr<3>_MC.D2_PT_4/IN0  (
    .I(N_PZ_1017),
    .O(\NlwInverterSignal_U4/ctrlr<3>_MC.D2_PT_4/IN0 )
  );
  X_INV \NlwInverterBlock_U4/ctrlr<3>_MC.D2_PT_4/IN1  (
    .I(\outDATA<3>\$WA1.UIM ),
    .O(\NlwInverterSignal_U4/ctrlr<3>_MC.D2_PT_4/IN1 )
  );
  X_INV \NlwInverterBlock_U4/ctrlr<3>_MC.D2_PT_5/IN0  (
    .I(N_PZ_1053),
    .O(\NlwInverterSignal_U4/ctrlr<3>_MC.D2_PT_5/IN0 )
  );
  X_INV \NlwInverterBlock_U4/ctrlr<3>_MC.D2_PT_5/IN1  (
    .I(\outDATA<3>\$WA2.UIM ),
    .O(\NlwInverterSignal_U4/ctrlr<3>_MC.D2_PT_5/IN1 )
  );
  X_INV \NlwInverterBlock_Enc05ctrl_MC.D/IN0  (
    .I(\Enc05ctrl_MC.D1 ),
    .O(\NlwInverterSignal_Enc05ctrl_MC.D/IN0 )
  );
  X_INV \NlwInverterBlock_Enc05ctrl_MC.D1/IN0  (
    .I(\U4/ctrlr[2] ),
    .O(\NlwInverterSignal_Enc05ctrl_MC.D1/IN0 )
  );
  X_INV \NlwInverterBlock_Enc133ctrl_MC.D/IN0  (
    .I(\Enc133ctrl_MC.D1 ),
    .O(\NlwInverterSignal_Enc133ctrl_MC.D/IN0 )
  );
  X_INV \NlwInverterBlock_U4/ctrlr<6>_MC.D/IN0  (
    .I(\U4/ctrlr<6>_MC.D1 ),
    .O(\NlwInverterSignal_U4/ctrlr<6>_MC.D/IN0 )
  );
  X_INV \NlwInverterBlock_U4/ctrlr<6>_MC.D2_PT_0/IN1  (
    .I(\outDATA<6>\$WA0.UIM ),
    .O(\NlwInverterSignal_U4/ctrlr<6>_MC.D2_PT_0/IN1 )
  );
  X_INV \NlwInverterBlock_U4/ctrlr<6>_MC.D2_PT_1/IN1  (
    .I(\outDATA<6>\$WA3.UIM ),
    .O(\NlwInverterSignal_U4/ctrlr<6>_MC.D2_PT_1/IN1 )
  );
  X_INV \NlwInverterBlock_U4/ctrlr<6>_MC.D2_PT_2/IN1  (
    .I(\outDATA<6>\$WA5.UIM ),
    .O(\NlwInverterSignal_U4/ctrlr<6>_MC.D2_PT_2/IN1 )
  );
  X_INV \NlwInverterBlock_U4/ctrlr<6>_MC.D2_PT_3/IN0  (
    .I(N_PZ_1016),
    .O(\NlwInverterSignal_U4/ctrlr<6>_MC.D2_PT_3/IN0 )
  );
  X_INV \NlwInverterBlock_U4/ctrlr<6>_MC.D2_PT_3/IN1  (
    .I(\outDATA<6>\$WA4.UIM ),
    .O(\NlwInverterSignal_U4/ctrlr<6>_MC.D2_PT_3/IN1 )
  );
  X_INV \NlwInverterBlock_U4/ctrlr<6>_MC.D2_PT_4/IN0  (
    .I(N_PZ_1017),
    .O(\NlwInverterSignal_U4/ctrlr<6>_MC.D2_PT_4/IN0 )
  );
  X_INV \NlwInverterBlock_U4/ctrlr<6>_MC.D2_PT_4/IN1  (
    .I(\outDATA<6>\$WA1.UIM ),
    .O(\NlwInverterSignal_U4/ctrlr<6>_MC.D2_PT_4/IN1 )
  );
  X_INV \NlwInverterBlock_U4/ctrlr<6>_MC.D2_PT_5/IN0  (
    .I(N_PZ_1053),
    .O(\NlwInverterSignal_U4/ctrlr<6>_MC.D2_PT_5/IN0 )
  );
  X_INV \NlwInverterBlock_U4/ctrlr<6>_MC.D2_PT_5/IN1  (
    .I(\outDATA<6>\$WA2.UIM ),
    .O(\NlwInverterSignal_U4/ctrlr<6>_MC.D2_PT_5/IN1 )
  );
  X_INV \NlwInverterBlock_U4/ctrlr<7>_MC.D/IN0  (
    .I(\U4/ctrlr<7>_MC.D1 ),
    .O(\NlwInverterSignal_U4/ctrlr<7>_MC.D/IN0 )
  );
  X_INV \NlwInverterBlock_U4/ctrlr<7>_MC.D2_PT_0/IN1  (
    .I(\outDATA<7>\$WA0.UIM ),
    .O(\NlwInverterSignal_U4/ctrlr<7>_MC.D2_PT_0/IN1 )
  );
  X_INV \NlwInverterBlock_U4/ctrlr<7>_MC.D2_PT_1/IN1  (
    .I(\outDATA<7>\$WA2.UIM ),
    .O(\NlwInverterSignal_U4/ctrlr<7>_MC.D2_PT_1/IN1 )
  );
  X_INV \NlwInverterBlock_U4/ctrlr<7>_MC.D2_PT_2/IN1  (
    .I(\outDATA<7>\$WA3.UIM ),
    .O(\NlwInverterSignal_U4/ctrlr<7>_MC.D2_PT_2/IN1 )
  );
  X_INV \NlwInverterBlock_U4/ctrlr<7>_MC.D2_PT_3/IN1  (
    .I(\outDATA<7>\$WA5.UIM ),
    .O(\NlwInverterSignal_U4/ctrlr<7>_MC.D2_PT_3/IN1 )
  );
  X_INV \NlwInverterBlock_U4/ctrlr<7>_MC.D2_PT_4/IN1  (
    .I(\outDATA<7>\$WA6.UIM ),
    .O(\NlwInverterSignal_U4/ctrlr<7>_MC.D2_PT_4/IN1 )
  );
  X_INV \NlwInverterBlock_U4/ctrlr<7>_MC.D2_PT_5/IN0  (
    .I(N_PZ_1016),
    .O(\NlwInverterSignal_U4/ctrlr<7>_MC.D2_PT_5/IN0 )
  );
  X_INV \NlwInverterBlock_U4/ctrlr<7>_MC.D2_PT_5/IN1  (
    .I(\outDATA<7>\$WA4.UIM ),
    .O(\NlwInverterSignal_U4/ctrlr<7>_MC.D2_PT_5/IN1 )
  );
  X_INV \NlwInverterBlock_U4/ctrlr<7>_MC.D2_PT_6/IN0  (
    .I(N_PZ_1017),
    .O(\NlwInverterSignal_U4/ctrlr<7>_MC.D2_PT_6/IN0 )
  );
  X_INV \NlwInverterBlock_U4/ctrlr<7>_MC.D2_PT_6/IN1  (
    .I(\outDATA<7>\$WA1.UIM ),
    .O(\NlwInverterSignal_U4/ctrlr<7>_MC.D2_PT_6/IN1 )
  );
  X_INV \NlwInverterBlock_U4/ctrlr<7>_MC.D2_PT_7/IN0  (
    .I(DCORIFGr),
    .O(\NlwInverterSignal_U4/ctrlr<7>_MC.D2_PT_7/IN0 )
  );
  X_INV \NlwInverterBlock_U4/ctrlr<7>_MC.D2_PT_7/IN1  (
    .I(N_PZ_1053),
    .O(\NlwInverterSignal_U4/ctrlr<7>_MC.D2_PT_7/IN1 )
  );
  X_INV \NlwInverterBlock_U4/ctrlr<7>_MC.D2_PT_7/IN2  (
    .I(\outDATA<7>\$WA2.UIM ),
    .O(\NlwInverterSignal_U4/ctrlr<7>_MC.D2_PT_7/IN2 )
  );
  X_INV \NlwInverterBlock_Enc15ctrl_MC.D/IN0  (
    .I(\Enc15ctrl_MC.D1 ),
    .O(\NlwInverterSignal_Enc15ctrl_MC.D/IN0 )
  );
  X_INV \NlwInverterBlock_Enc15ctrl_MC.D1/IN0  (
    .I(\U4/ctrlr[6] ),
    .O(\NlwInverterSignal_Enc15ctrl_MC.D1/IN0 )
  );
  X_INV \NlwInverterBlock_GP_Motor0_1_MC.D2_PT_1/IN1  (
    .I(DCOROUTw),
    .O(\NlwInverterSignal_GP_Motor0_1_MC.D2_PT_1/IN1 )
  );
  X_INV \NlwInverterBlock_DCOROUTw_MC.D1/IN0  (
    .I(\WR_II/UIM ),
    .O(\NlwInverterSignal_DCOROUTw_MC.D1/IN0 )
  );
  X_INV \NlwInverterBlock_DCOROUTw_MC.D1/IN3  (
    .I(U2_ADDR_reg[4]),
    .O(\NlwInverterSignal_DCOROUTw_MC.D1/IN3 )
  );
  X_INV \NlwInverterBlock_DCOROUTw_MC.D1/IN4  (
    .I(U2_ADDR_reg[5]),
    .O(\NlwInverterSignal_DCOROUTw_MC.D1/IN4 )
  );
  X_INV \NlwInverterBlock_DCOROUTw_MC.D1/IN5  (
    .I(U2_ADDR_reg[6]),
    .O(\NlwInverterSignal_DCOROUTw_MC.D1/IN5 )
  );
  X_INV \NlwInverterBlock_DCOROUTw_MC.D1/IN6  (
    .I(U2_ADDR_reg[7]),
    .O(\NlwInverterSignal_DCOROUTw_MC.D1/IN6 )
  );
  X_INV \NlwInverterBlock_GP_Motor1_1_MC.D2_PT_1/IN1  (
    .I(DCOROUTw),
    .O(\NlwInverterSignal_GP_Motor1_1_MC.D2_PT_1/IN1 )
  );
  X_INV \NlwInverterBlock_Home033ctrl_MC.D/IN0  (
    .I(\Home033ctrl_MC.D1 ),
    .O(\NlwInverterSignal_Home033ctrl_MC.D/IN0 )
  );
  X_INV \NlwInverterBlock_Home05ctrl_MC.D/IN0  (
    .I(\Home05ctrl_MC.D1 ),
    .O(\NlwInverterSignal_Home05ctrl_MC.D/IN0 )
  );
  X_INV \NlwInverterBlock_Home133ctrl_MC.D/IN0  (
    .I(\Home133ctrl_MC.D1 ),
    .O(\NlwInverterSignal_Home133ctrl_MC.D/IN0 )
  );
  X_INV \NlwInverterBlock_Home15ctrl_MC.D/IN0  (
    .I(\Home15ctrl_MC.D1 ),
    .O(\NlwInverterSignal_Home15ctrl_MC.D/IN0 )
  );
  X_INV \NlwInverterBlock_INT_MC.D2_PT_6/IN0  (
    .I(\INTbus_II/UIM ),
    .O(\NlwInverterSignal_INT_MC.D2_PT_6/IN0 )
  );
  X_INV \NlwInverterBlock_U3/DCORIE<0>_MC.D2_PT_1/IN2  (
    .I(DCORIEw),
    .O(\NlwInverterSignal_U3/DCORIE<0>_MC.D2_PT_1/IN2 )
  );
  X_INV \NlwInverterBlock_DCORIEw_MC.D1/IN0  (
    .I(\WR_II/UIM ),
    .O(\NlwInverterSignal_DCORIEw_MC.D1/IN0 )
  );
  X_INV \NlwInverterBlock_DCORIEw_MC.D1/IN2  (
    .I(U2_ADDR_reg[0]),
    .O(\NlwInverterSignal_DCORIEw_MC.D1/IN2 )
  );
  X_INV \NlwInverterBlock_DCORIEw_MC.D1/IN3  (
    .I(U2_ADDR_reg[4]),
    .O(\NlwInverterSignal_DCORIEw_MC.D1/IN3 )
  );
  X_INV \NlwInverterBlock_DCORIEw_MC.D1/IN4  (
    .I(U2_ADDR_reg[5]),
    .O(\NlwInverterSignal_DCORIEw_MC.D1/IN4 )
  );
  X_INV \NlwInverterBlock_DCORIEw_MC.D1/IN5  (
    .I(U2_ADDR_reg[6]),
    .O(\NlwInverterSignal_DCORIEw_MC.D1/IN5 )
  );
  X_INV \NlwInverterBlock_DCORIEw_MC.D1/IN6  (
    .I(U2_ADDR_reg[7]),
    .O(\NlwInverterSignal_DCORIEw_MC.D1/IN6 )
  );
  X_INV \NlwInverterBlock_DCORIEw_MC.D1/IN7  (
    .I(U2_ADDR_reg[3]),
    .O(\NlwInverterSignal_DCORIEw_MC.D1/IN7 )
  );
  X_INV \NlwInverterBlock_DCORIEw_MC.D1/IN8  (
    .I(U2_ADDR_reg[1]),
    .O(\NlwInverterSignal_DCORIEw_MC.D1/IN8 )
  );
  X_INV \NlwInverterBlock_DCORIEw_MC.D1/IN9  (
    .I(U2_ADDR_reg[2]),
    .O(\NlwInverterSignal_DCORIEw_MC.D1/IN9 )
  );
  X_INV \NlwInverterBlock_U3/DCORIE<1>_MC.D2_PT_1/IN2  (
    .I(DCORIEw),
    .O(\NlwInverterSignal_U3/DCORIE<1>_MC.D2_PT_1/IN2 )
  );
  X_INV \NlwInverterBlock_U3/DCORIE<2>_MC.D2_PT_1/IN2  (
    .I(DCORIEw),
    .O(\NlwInverterSignal_U3/DCORIE<2>_MC.D2_PT_1/IN2 )
  );
  X_INV \NlwInverterBlock_U3/DCORIE<3>_MC.D2_PT_1/IN2  (
    .I(DCORIEw),
    .O(\NlwInverterSignal_U3/DCORIE<3>_MC.D2_PT_1/IN2 )
  );
  X_INV \NlwInverterBlock_U3/DCORIE<4>_MC.D2_PT_1/IN2  (
    .I(DCORIEw),
    .O(\NlwInverterSignal_U3/DCORIE<4>_MC.D2_PT_1/IN2 )
  );
  X_INV \NlwInverterBlock_U3/DCORIE<5>_MC.D2_PT_1/IN2  (
    .I(DCORIEw),
    .O(\NlwInverterSignal_U3/DCORIE<5>_MC.D2_PT_1/IN2 )
  );
  X_INV \NlwInverterBlock_U3/DCORIE<6>_MC.D2_PT_1/IN2  (
    .I(DCORIEw),
    .O(\NlwInverterSignal_U3/DCORIE<6>_MC.D2_PT_1/IN2 )
  );
  X_INV \NlwInverterBlock_U3/DCORIE<7>_MC.D2_PT_1/IN2  (
    .I(DCORIEw),
    .O(\NlwInverterSignal_U3/DCORIE<7>_MC.D2_PT_1/IN2 )
  );
  X_INV \NlwInverterBlock_LED1_MC.D/IN0  (
    .I(\LED1_MC.D1 ),
    .O(\NlwInverterSignal_LED1_MC.D/IN0 )
  );
  X_INV \NlwInverterBlock_LED1_MC.D1/IN1  (
    .I(\U9/MISCr [0]),
    .O(\NlwInverterSignal_LED1_MC.D1/IN1 )
  );
  X_INV \NlwInverterBlock_U9/MISCr<0>_MC.D2_PT_1/IN1  (
    .I(DCOROUTw),
    .O(\NlwInverterSignal_U9/MISCr<0>_MC.D2_PT_1/IN1 )
  );
  X_INV \NlwInverterBlock_LED2_MC.D/IN0  (
    .I(\LED2_MC.D1 ),
    .O(\NlwInverterSignal_LED2_MC.D/IN0 )
  );
  X_INV \NlwInverterBlock_LED2_MC.D1/IN1  (
    .I(\U9/MISCr [1]),
    .O(\NlwInverterSignal_LED2_MC.D1/IN1 )
  );
  X_INV \NlwInverterBlock_U9/MISCr<1>_MC.D2_PT_1/IN1  (
    .I(DCOROUTw),
    .O(\NlwInverterSignal_U9/MISCr<1>_MC.D2_PT_1/IN1 )
  );
  X_INV \NlwInverterBlock_LED3_MC.D/IN0  (
    .I(\LED3_MC.D1 ),
    .O(\NlwInverterSignal_LED3_MC.D/IN0 )
  );
  X_INV \NlwInverterBlock_LED3_MC.D1/IN1  (
    .I(\U9/MISCr [2]),
    .O(\NlwInverterSignal_LED3_MC.D1/IN1 )
  );
  X_INV \NlwInverterBlock_U9/MISCr<2>_MC.D2_PT_1/IN1  (
    .I(DCOROUTw),
    .O(\NlwInverterSignal_U9/MISCr<2>_MC.D2_PT_1/IN1 )
  );
  X_INV \NlwInverterBlock_LED4_MC.D/IN0  (
    .I(\LED4_MC.D1 ),
    .O(\NlwInverterSignal_LED4_MC.D/IN0 )
  );
  X_INV \NlwInverterBlock_LED4_MC.D1/IN1  (
    .I(\U9/MISCr [3]),
    .O(\NlwInverterSignal_LED4_MC.D1/IN1 )
  );
  X_INV \NlwInverterBlock_U9/MISCr<3>_MC.D2_PT_1/IN1  (
    .I(DCOROUTw),
    .O(\NlwInverterSignal_U9/MISCr<3>_MC.D2_PT_1/IN1 )
  );
  X_INV \NlwInverterBlock_LED5_MC.D/IN0  (
    .I(\LED5_MC.D1 ),
    .O(\NlwInverterSignal_LED5_MC.D/IN0 )
  );
  X_INV \NlwInverterBlock_LED5_MC.D1/IN1  (
    .I(\U9/MISCr [4]),
    .O(\NlwInverterSignal_LED5_MC.D1/IN1 )
  );
  X_INV \NlwInverterBlock_U9/MISCr<4>_MC.D2_PT_1/IN1  (
    .I(DCOROUTw),
    .O(\NlwInverterSignal_U9/MISCr<4>_MC.D2_PT_1/IN1 )
  );
  X_INV \NlwInverterBlock_MTRpwr_MC.D2_PT_1/IN1  (
    .I(DCOROUTw),
    .O(\NlwInverterSignal_MTRpwr_MC.D2_PT_1/IN1 )
  );
  X_INV \NlwInverterBlock_MTRpwrn_MC.D/IN0  (
    .I(\MTRpwrn_MC.D1 ),
    .O(\NlwInverterSignal_MTRpwrn_MC.D/IN0 )
  );
  X_INV \NlwInverterBlock_MTRpwrn_MC.D2_PT_1/IN1  (
    .I(DCOROUTw),
    .O(\NlwInverterSignal_MTRpwrn_MC.D2_PT_1/IN1 )
  );
  X_INV \NlwInverterBlock_MTRpwrn_MC.D2_PT_1/IN2  (
    .I(\MTRpwrn_MC.UIM ),
    .O(\NlwInverterSignal_MTRpwrn_MC.D2_PT_1/IN2 )
  );
  X_INV \NlwInverterBlock_PAL0_MC.D2_PT_0/IN1  (
    .I(\Brake0_II/UIM ),
    .O(\NlwInverterSignal_PAL0_MC.D2_PT_0/IN1 )
  );
  X_INV \NlwInverterBlock_PAL0_MC.D2_PT_0/IN3  (
    .I(\PWM1_II/UIM ),
    .O(\NlwInverterSignal_PAL0_MC.D2_PT_0/IN3 )
  );
  X_INV \NlwInverterBlock_PAL0_MC.D2_PT_0/IN4  (
    .I(NET3248),
    .O(\NlwInverterSignal_PAL0_MC.D2_PT_0/IN4 )
  );
  X_INV \NlwInverterBlock_PAL0_MC.D2_PT_1/IN0  (
    .I(\DIR0_II/UIM ),
    .O(\NlwInverterSignal_PAL0_MC.D2_PT_1/IN0 )
  );
  X_INV \NlwInverterBlock_PAL0_MC.D2_PT_1/IN1  (
    .I(\Brake0_II/UIM ),
    .O(\NlwInverterSignal_PAL0_MC.D2_PT_1/IN1 )
  );
  X_INV \NlwInverterBlock_PAL0_MC.D2_PT_1/IN4  (
    .I(NET3248),
    .O(\NlwInverterSignal_PAL0_MC.D2_PT_1/IN4 )
  );
  X_INV \NlwInverterBlock_NET3248_MC.D2_PT_0/IN1  (
    .I(\RLS0_II/UIM ),
    .O(\NlwInverterSignal_NET3248_MC.D2_PT_0/IN1 )
  );
  X_INV \NlwInverterBlock_NET3248_MC.D2_PT_0/IN2  (
    .I(DCORLINTr),
    .O(\NlwInverterSignal_NET3248_MC.D2_PT_0/IN2 )
  );
  X_INV \NlwInverterBlock_NET3248_MC.D2_PT_0/IN3  (
    .I(\DIR0_II/UIM ),
    .O(\NlwInverterSignal_NET3248_MC.D2_PT_0/IN3 )
  );
  X_INV \NlwInverterBlock_NET3248_MC.D2_PT_0/IN5  (
    .I(NET3248),
    .O(\NlwInverterSignal_NET3248_MC.D2_PT_0/IN5 )
  );
  X_INV \NlwInverterBlock_NET3248_MC.D2_PT_1/IN1  (
    .I(DCORLINTr),
    .O(\NlwInverterSignal_NET3248_MC.D2_PT_1/IN1 )
  );
  X_INV \NlwInverterBlock_NET3248_MC.D2_PT_1/IN3  (
    .I(\FLS0_II/UIM ),
    .O(\NlwInverterSignal_NET3248_MC.D2_PT_1/IN3 )
  );
  X_INV \NlwInverterBlock_NET3248_MC.D2_PT_1/IN5  (
    .I(NET3248),
    .O(\NlwInverterSignal_NET3248_MC.D2_PT_1/IN5 )
  );
  X_INV \NlwInverterBlock_NET3248_MC.D2_PT_2/IN2  (
    .I(\U5/RLS0fr ),
    .O(\NlwInverterSignal_NET3248_MC.D2_PT_2/IN2 )
  );
  X_INV \NlwInverterBlock_NET3248_MC.D2_PT_2/IN3  (
    .I(DCORLINTr),
    .O(\NlwInverterSignal_NET3248_MC.D2_PT_2/IN3 )
  );
  X_INV \NlwInverterBlock_NET3248_MC.D2_PT_2/IN4  (
    .I(\DIR0_II/UIM ),
    .O(\NlwInverterSignal_NET3248_MC.D2_PT_2/IN4 )
  );
  X_INV \NlwInverterBlock_NET3248_MC.D2_PT_2/IN5  (
    .I(\U5/FLS0fr ),
    .O(\NlwInverterSignal_NET3248_MC.D2_PT_2/IN5 )
  );
  X_INV \NlwInverterBlock_NET3248_MC.D2_PT_3/IN1  (
    .I(\U5/RLS0fr ),
    .O(\NlwInverterSignal_NET3248_MC.D2_PT_3/IN1 )
  );
  X_INV \NlwInverterBlock_NET3248_MC.D2_PT_3/IN2  (
    .I(DCORLINTr),
    .O(\NlwInverterSignal_NET3248_MC.D2_PT_3/IN2 )
  );
  X_INV \NlwInverterBlock_NET3248_MC.D2_PT_3/IN5  (
    .I(\U5/FLS0fr ),
    .O(\NlwInverterSignal_NET3248_MC.D2_PT_3/IN5 )
  );
  X_INV \NlwInverterBlock_NET3248_MC.D2_PT_4/IN1  (
    .I(\U5/RLS0fr ),
    .O(\NlwInverterSignal_NET3248_MC.D2_PT_4/IN1 )
  );
  X_INV \NlwInverterBlock_NET3248_MC.D2_PT_4/IN2  (
    .I(DCORLINTr),
    .O(\NlwInverterSignal_NET3248_MC.D2_PT_4/IN2 )
  );
  X_INV \NlwInverterBlock_NET3248_MC.D2_PT_4/IN4  (
    .I(\U5/FLS0fr ),
    .O(\NlwInverterSignal_NET3248_MC.D2_PT_4/IN4 )
  );
  X_INV \NlwInverterBlock_NET3248_MC.D2_PT_4/IN5  (
    .I(\U5/FLS0r ),
    .O(\NlwInverterSignal_NET3248_MC.D2_PT_4/IN5 )
  );
  X_INV \NlwInverterBlock_NET3248_MC.D2_PT_5/IN1  (
    .I(\U5/RLS0fr ),
    .O(\NlwInverterSignal_NET3248_MC.D2_PT_5/IN1 )
  );
  X_INV \NlwInverterBlock_NET3248_MC.D2_PT_5/IN2  (
    .I(DCORLINTr),
    .O(\NlwInverterSignal_NET3248_MC.D2_PT_5/IN2 )
  );
  X_INV \NlwInverterBlock_NET3248_MC.D2_PT_5/IN3  (
    .I(\DIR0_II/UIM ),
    .O(\NlwInverterSignal_NET3248_MC.D2_PT_5/IN3 )
  );
  X_INV \NlwInverterBlock_NET3248_MC.D2_PT_5/IN4  (
    .I(\U5/RLS0r ),
    .O(\NlwInverterSignal_NET3248_MC.D2_PT_5/IN4 )
  );
  X_INV \NlwInverterBlock_NET3248_MC.D2_PT_5/IN5  (
    .I(\U5/FLS0fr ),
    .O(\NlwInverterSignal_NET3248_MC.D2_PT_5/IN5 )
  );
  X_INV \NlwInverterBlock_PAL1_MC.D2_PT_0/IN1  (
    .I(\Brake1_II/UIM ),
    .O(\NlwInverterSignal_PAL1_MC.D2_PT_0/IN1 )
  );
  X_INV \NlwInverterBlock_PAL1_MC.D2_PT_0/IN3  (
    .I(\PWM2_II/UIM ),
    .O(\NlwInverterSignal_PAL1_MC.D2_PT_0/IN3 )
  );
  X_INV \NlwInverterBlock_PAL1_MC.D2_PT_0/IN4  (
    .I(NET3253),
    .O(\NlwInverterSignal_PAL1_MC.D2_PT_0/IN4 )
  );
  X_INV \NlwInverterBlock_PAL1_MC.D2_PT_1/IN0  (
    .I(\DIR1_II/UIM ),
    .O(\NlwInverterSignal_PAL1_MC.D2_PT_1/IN0 )
  );
  X_INV \NlwInverterBlock_PAL1_MC.D2_PT_1/IN1  (
    .I(\Brake1_II/UIM ),
    .O(\NlwInverterSignal_PAL1_MC.D2_PT_1/IN1 )
  );
  X_INV \NlwInverterBlock_PAL1_MC.D2_PT_1/IN4  (
    .I(NET3253),
    .O(\NlwInverterSignal_PAL1_MC.D2_PT_1/IN4 )
  );
  X_INV \NlwInverterBlock_NET3253_MC.D2_PT_0/IN1  (
    .I(DCORLINTr),
    .O(\NlwInverterSignal_NET3253_MC.D2_PT_0/IN1 )
  );
  X_INV \NlwInverterBlock_NET3253_MC.D2_PT_0/IN3  (
    .I(\FLS1_II/UIM ),
    .O(\NlwInverterSignal_NET3253_MC.D2_PT_0/IN3 )
  );
  X_INV \NlwInverterBlock_NET3253_MC.D2_PT_0/IN5  (
    .I(NET3253),
    .O(\NlwInverterSignal_NET3253_MC.D2_PT_0/IN5 )
  );
  X_INV \NlwInverterBlock_NET3253_MC.D2_PT_1/IN1  (
    .I(DCORLINTr),
    .O(\NlwInverterSignal_NET3253_MC.D2_PT_1/IN1 )
  );
  X_INV \NlwInverterBlock_NET3253_MC.D2_PT_1/IN2  (
    .I(\DIR1_II/UIM ),
    .O(\NlwInverterSignal_NET3253_MC.D2_PT_1/IN2 )
  );
  X_INV \NlwInverterBlock_NET3253_MC.D2_PT_1/IN3  (
    .I(\RLS1_II/UIM ),
    .O(\NlwInverterSignal_NET3253_MC.D2_PT_1/IN3 )
  );
  X_INV \NlwInverterBlock_NET3253_MC.D2_PT_1/IN5  (
    .I(NET3253),
    .O(\NlwInverterSignal_NET3253_MC.D2_PT_1/IN5 )
  );
  X_INV \NlwInverterBlock_NET3253_MC.D2_PT_2/IN1  (
    .I(DCORLINTr),
    .O(\NlwInverterSignal_NET3253_MC.D2_PT_2/IN1 )
  );
  X_INV \NlwInverterBlock_NET3253_MC.D2_PT_2/IN2  (
    .I(\U5/FLS1fr ),
    .O(\NlwInverterSignal_NET3253_MC.D2_PT_2/IN2 )
  );
  X_INV \NlwInverterBlock_NET3253_MC.D2_PT_2/IN3  (
    .I(\U5/RLS1fr ),
    .O(\NlwInverterSignal_NET3253_MC.D2_PT_2/IN3 )
  );
  X_INV \NlwInverterBlock_NET3253_MC.D2_PT_3/IN1  (
    .I(DCORLINTr),
    .O(\NlwInverterSignal_NET3253_MC.D2_PT_3/IN1 )
  );
  X_INV \NlwInverterBlock_NET3253_MC.D2_PT_3/IN2  (
    .I(\U5/FLS1fr ),
    .O(\NlwInverterSignal_NET3253_MC.D2_PT_3/IN2 )
  );
  X_INV \NlwInverterBlock_NET3253_MC.D2_PT_3/IN3  (
    .I(\U5/RLS1fr ),
    .O(\NlwInverterSignal_NET3253_MC.D2_PT_3/IN3 )
  );
  X_INV \NlwInverterBlock_NET3253_MC.D2_PT_3/IN5  (
    .I(\U5/FLS1r ),
    .O(\NlwInverterSignal_NET3253_MC.D2_PT_3/IN5 )
  );
  X_INV \NlwInverterBlock_NET3253_MC.D2_PT_4/IN1  (
    .I(DCORLINTr),
    .O(\NlwInverterSignal_NET3253_MC.D2_PT_4/IN1 )
  );
  X_INV \NlwInverterBlock_NET3253_MC.D2_PT_4/IN2  (
    .I(\U5/FLS1fr ),
    .O(\NlwInverterSignal_NET3253_MC.D2_PT_4/IN2 )
  );
  X_INV \NlwInverterBlock_NET3253_MC.D2_PT_4/IN3  (
    .I(\U5/RLS1fr ),
    .O(\NlwInverterSignal_NET3253_MC.D2_PT_4/IN3 )
  );
  X_INV \NlwInverterBlock_NET3253_MC.D2_PT_4/IN4  (
    .I(\DIR1_II/UIM ),
    .O(\NlwInverterSignal_NET3253_MC.D2_PT_4/IN4 )
  );
  X_INV \NlwInverterBlock_NET3253_MC.D2_PT_5/IN1  (
    .I(DCORLINTr),
    .O(\NlwInverterSignal_NET3253_MC.D2_PT_5/IN1 )
  );
  X_INV \NlwInverterBlock_NET3253_MC.D2_PT_5/IN2  (
    .I(\U5/FLS1fr ),
    .O(\NlwInverterSignal_NET3253_MC.D2_PT_5/IN2 )
  );
  X_INV \NlwInverterBlock_NET3253_MC.D2_PT_5/IN3  (
    .I(\U5/RLS1fr ),
    .O(\NlwInverterSignal_NET3253_MC.D2_PT_5/IN3 )
  );
  X_INV \NlwInverterBlock_NET3253_MC.D2_PT_5/IN4  (
    .I(\DIR1_II/UIM ),
    .O(\NlwInverterSignal_NET3253_MC.D2_PT_5/IN4 )
  );
  X_INV \NlwInverterBlock_NET3253_MC.D2_PT_5/IN5  (
    .I(\U5/RLS1r ),
    .O(\NlwInverterSignal_NET3253_MC.D2_PT_5/IN5 )
  );
  X_INV \NlwInverterBlock_PBL0_MC.D2_PT_0/IN1  (
    .I(\Brake0_II/UIM ),
    .O(\NlwInverterSignal_PBL0_MC.D2_PT_0/IN1 )
  );
  X_INV \NlwInverterBlock_PBL0_MC.D2_PT_0/IN4  (
    .I(NET3248),
    .O(\NlwInverterSignal_PBL0_MC.D2_PT_0/IN4 )
  );
  X_INV \NlwInverterBlock_PBL0_MC.D2_PT_1/IN0  (
    .I(\DIR0_II/UIM ),
    .O(\NlwInverterSignal_PBL0_MC.D2_PT_1/IN0 )
  );
  X_INV \NlwInverterBlock_PBL0_MC.D2_PT_1/IN1  (
    .I(\Brake0_II/UIM ),
    .O(\NlwInverterSignal_PBL0_MC.D2_PT_1/IN1 )
  );
  X_INV \NlwInverterBlock_PBL0_MC.D2_PT_1/IN3  (
    .I(\PWM1_II/UIM ),
    .O(\NlwInverterSignal_PBL0_MC.D2_PT_1/IN3 )
  );
  X_INV \NlwInverterBlock_PBL0_MC.D2_PT_1/IN4  (
    .I(NET3248),
    .O(\NlwInverterSignal_PBL0_MC.D2_PT_1/IN4 )
  );
  X_INV \NlwInverterBlock_PBL1_MC.D2_PT_0/IN1  (
    .I(\Brake1_II/UIM ),
    .O(\NlwInverterSignal_PBL1_MC.D2_PT_0/IN1 )
  );
  X_INV \NlwInverterBlock_PBL1_MC.D2_PT_0/IN4  (
    .I(NET3253),
    .O(\NlwInverterSignal_PBL1_MC.D2_PT_0/IN4 )
  );
  X_INV \NlwInverterBlock_PBL1_MC.D2_PT_1/IN0  (
    .I(\DIR1_II/UIM ),
    .O(\NlwInverterSignal_PBL1_MC.D2_PT_1/IN0 )
  );
  X_INV \NlwInverterBlock_PBL1_MC.D2_PT_1/IN1  (
    .I(\Brake1_II/UIM ),
    .O(\NlwInverterSignal_PBL1_MC.D2_PT_1/IN1 )
  );
  X_INV \NlwInverterBlock_PBL1_MC.D2_PT_1/IN3  (
    .I(\PWM2_II/UIM ),
    .O(\NlwInverterSignal_PBL1_MC.D2_PT_1/IN3 )
  );
  X_INV \NlwInverterBlock_PBL1_MC.D2_PT_1/IN4  (
    .I(NET3253),
    .O(\NlwInverterSignal_PBL1_MC.D2_PT_1/IN4 )
  );
  X_INV \NlwInverterBlock_PresEn_MC.D/IN0  (
    .I(\PresEn_MC.D1 ),
    .O(\NlwInverterSignal_PresEn_MC.D/IN0 )
  );
  X_INV \NlwInverterBlock_DCORSENSORw_MC.D1/IN0  (
    .I(\WR_II/UIM ),
    .O(\NlwInverterSignal_DCORSENSORw_MC.D1/IN0 )
  );
  X_INV \NlwInverterBlock_DCORSENSORw_MC.D1/IN2  (
    .I(U2_ADDR_reg[0]),
    .O(\NlwInverterSignal_DCORSENSORw_MC.D1/IN2 )
  );
  X_INV \NlwInverterBlock_DCORSENSORw_MC.D1/IN3  (
    .I(U2_ADDR_reg[4]),
    .O(\NlwInverterSignal_DCORSENSORw_MC.D1/IN3 )
  );
  X_INV \NlwInverterBlock_DCORSENSORw_MC.D1/IN4  (
    .I(U2_ADDR_reg[5]),
    .O(\NlwInverterSignal_DCORSENSORw_MC.D1/IN4 )
  );
  X_INV \NlwInverterBlock_DCORSENSORw_MC.D1/IN5  (
    .I(U2_ADDR_reg[6]),
    .O(\NlwInverterSignal_DCORSENSORw_MC.D1/IN5 )
  );
  X_INV \NlwInverterBlock_DCORSENSORw_MC.D1/IN6  (
    .I(U2_ADDR_reg[7]),
    .O(\NlwInverterSignal_DCORSENSORw_MC.D1/IN6 )
  );
  X_INV \NlwInverterBlock_DCORSENSORw_MC.D1/IN8  (
    .I(U2_ADDR_reg[1]),
    .O(\NlwInverterSignal_DCORSENSORw_MC.D1/IN8 )
  );
  X_INV \NlwInverterBlock_TP11_MC.D/IN0  (
    .I(\TP11_MC.D1 ),
    .O(\NlwInverterSignal_TP11_MC.D/IN0 )
  );
  X_INV \NlwInverterBlock_TmpEn_MC.D/IN0  (
    .I(\TmpEn_MC.D1 ),
    .O(\NlwInverterSignal_TmpEn_MC.D/IN0 )
  );
  X_INV \NlwInverterBlock_outDATA<2>\$WA5.UIM_MC.D2_PT_1/IN0  (
    .I(NET2528),
    .O(\NlwInverterSignal_outDATA<2>\$WA5.UIM_MC.D2_PT_1/IN0 )
  );
  X_INV \NlwInverterBlock_outDATA<2>\$WA1.UIM_MC.D2_PT_1/IN0  (
    .I(DCOR0CNTLOWr),
    .O(\NlwInverterSignal_outDATA<2>\$WA1.UIM_MC.D2_PT_1/IN0 )
  );
  X_INV \NlwInverterBlock_outDATA<2>\$WA1.UIM_MC.D2_PT_2/IN0  (
    .I(DCOR0CNTLOWr),
    .O(\NlwInverterSignal_outDATA<2>\$WA1.UIM_MC.D2_PT_2/IN0 )
  );
  X_INV \NlwInverterBlock_outDATA<2>\$WA1.UIM_MC.D2_PT_2/IN1  (
    .I(DCOR1CNTLOWr),
    .O(\NlwInverterSignal_outDATA<2>\$WA1.UIM_MC.D2_PT_2/IN1 )
  );
  X_INV \NlwInverterBlock_outDATA<2>\$WA1.UIM_MC.D2_PT_3/IN0  (
    .I(DCOR0CNTLOWr),
    .O(\NlwInverterSignal_outDATA<2>\$WA1.UIM_MC.D2_PT_3/IN0 )
  );
  X_INV \NlwInverterBlock_outDATA<2>\$WA1.UIM_MC.D2_PT_3/IN1  (
    .I(DCOR1CNTLOWr),
    .O(\NlwInverterSignal_outDATA<2>\$WA1.UIM_MC.D2_PT_3/IN1 )
  );
  X_INV \NlwInverterBlock_outDATA<2>\$WA1.UIM_MC.D2_PT_3/IN2  (
    .I(DCOR0CNTHIGHr),
    .O(\NlwInverterSignal_outDATA<2>\$WA1.UIM_MC.D2_PT_3/IN2 )
  );
  X_INV \NlwInverterBlock_U1/U3/holdingreg0<2>_MC.D2_PT_1/IN1  (
    .I(\AS_II/UIM ),
    .O(\NlwInverterSignal_U1/U3/holdingreg0<2>_MC.D2_PT_1/IN1 )
  );
  X_INV \NlwInverterBlock_U1/U3/holdingreg1<2>_MC.D2_PT_1/IN1  (
    .I(\AS_II/UIM ),
    .O(\NlwInverterSignal_U1/U3/holdingreg1<2>_MC.D2_PT_1/IN1 )
  );
  X_INV \NlwInverterBlock_U1/U3/holdingreg0<10>_MC.D2_PT_1/IN1  (
    .I(\AS_II/UIM ),
    .O(\NlwInverterSignal_U1/U3/holdingreg0<10>_MC.D2_PT_1/IN1 )
  );
  X_INV \NlwInverterBlock_U1/U3/holdingreg1<10>_MC.D2_PT_1/IN1  (
    .I(\AS_II/UIM ),
    .O(\NlwInverterSignal_U1/U3/holdingreg1<10>_MC.D2_PT_1/IN1 )
  );
  X_INV \NlwInverterBlock_outDATA<2>\$WA2.UIM_MC.D2_PT_1/IN0  (
    .I(DCOR0THRESLOWr),
    .O(\NlwInverterSignal_outDATA<2>\$WA2.UIM_MC.D2_PT_1/IN0 )
  );
  X_INV \NlwInverterBlock_outDATA<2>\$WA2.UIM_MC.D2_PT_2/IN0  (
    .I(DCOR0THRESLOWr),
    .O(\NlwInverterSignal_outDATA<2>\$WA2.UIM_MC.D2_PT_2/IN0 )
  );
  X_INV \NlwInverterBlock_outDATA<2>\$WA2.UIM_MC.D2_PT_2/IN1  (
    .I(DCORIFGr),
    .O(\NlwInverterSignal_outDATA<2>\$WA2.UIM_MC.D2_PT_2/IN1 )
  );
  X_INV \NlwInverterBlock_outDATA<2>\$WA2.UIM_MC.D2_PT_3/IN0  (
    .I(DCOR0THRESLOWr),
    .O(\NlwInverterSignal_outDATA<2>\$WA2.UIM_MC.D2_PT_3/IN0 )
  );
  X_INV \NlwInverterBlock_outDATA<2>\$WA2.UIM_MC.D2_PT_3/IN1  (
    .I(DCORIFGr),
    .O(\NlwInverterSignal_outDATA<2>\$WA2.UIM_MC.D2_PT_3/IN1 )
  );
  X_INV \NlwInverterBlock_outDATA<2>\$WA2.UIM_MC.D2_PT_3/IN2  (
    .I(DCOR0THRESHIGHr),
    .O(\NlwInverterSignal_outDATA<2>\$WA2.UIM_MC.D2_PT_3/IN2 )
  );
  X_INV \NlwInverterBlock_outDATA<2>\$WA2.UIM_MC.D2_PT_4/IN0  (
    .I(DCOR0THRESLOWr),
    .O(\NlwInverterSignal_outDATA<2>\$WA2.UIM_MC.D2_PT_4/IN0 )
  );
  X_INV \NlwInverterBlock_outDATA<2>\$WA2.UIM_MC.D2_PT_4/IN1  (
    .I(DCORIFGr),
    .O(\NlwInverterSignal_outDATA<2>\$WA2.UIM_MC.D2_PT_4/IN1 )
  );
  X_INV \NlwInverterBlock_outDATA<2>\$WA2.UIM_MC.D2_PT_4/IN2  (
    .I(DCOR0THRESHIGHr),
    .O(\NlwInverterSignal_outDATA<2>\$WA2.UIM_MC.D2_PT_4/IN2 )
  );
  X_INV \NlwInverterBlock_outDATA<2>\$WA2.UIM_MC.D2_PT_4/IN3  (
    .I(DCOR1THRESLOWr),
    .O(\NlwInverterSignal_outDATA<2>\$WA2.UIM_MC.D2_PT_4/IN3 )
  );
  X_INV \NlwInverterBlock_U1/U4/Latch0r<2>_MC.D2_PT_1/IN1  (
    .I(N_PZ_1018),
    .O(\NlwInverterSignal_U1/U4/Latch0r<2>_MC.D2_PT_1/IN1 )
  );
  X_INV \NlwInverterBlock_U1/U4/Latch0r<10>_MC.D2_PT_1/IN1  (
    .I(N_PZ_1018),
    .O(\NlwInverterSignal_U1/U4/Latch0r<10>_MC.D2_PT_1/IN1 )
  );
  X_INV \NlwInverterBlock_U1/U4/Latch1r<2>_MC.D2_PT_1/IN1  (
    .I(N_PZ_1019),
    .O(\NlwInverterSignal_U1/U4/Latch1r<2>_MC.D2_PT_1/IN1 )
  );
  X_INV \NlwInverterBlock_U1/U4/Latch1r<10>_MC.D2_PT_1/IN1  (
    .I(N_PZ_1019),
    .O(\NlwInverterSignal_U1/U4/Latch1r<10>_MC.D2_PT_1/IN1 )
  );
  X_INV \NlwInverterBlock_outDATA<3>\$WA5.UIM_MC.D2_PT_1/IN0  (
    .I(NET2528),
    .O(\NlwInverterSignal_outDATA<3>\$WA5.UIM_MC.D2_PT_1/IN0 )
  );
  X_INV \NlwInverterBlock_outDATA<3>\$WA1.UIM_MC.D2_PT_1/IN0  (
    .I(DCOR0CNTLOWr),
    .O(\NlwInverterSignal_outDATA<3>\$WA1.UIM_MC.D2_PT_1/IN0 )
  );
  X_INV \NlwInverterBlock_outDATA<3>\$WA1.UIM_MC.D2_PT_2/IN0  (
    .I(DCOR0CNTLOWr),
    .O(\NlwInverterSignal_outDATA<3>\$WA1.UIM_MC.D2_PT_2/IN0 )
  );
  X_INV \NlwInverterBlock_outDATA<3>\$WA1.UIM_MC.D2_PT_2/IN1  (
    .I(DCOR1CNTLOWr),
    .O(\NlwInverterSignal_outDATA<3>\$WA1.UIM_MC.D2_PT_2/IN1 )
  );
  X_INV \NlwInverterBlock_outDATA<3>\$WA1.UIM_MC.D2_PT_3/IN0  (
    .I(DCOR0CNTLOWr),
    .O(\NlwInverterSignal_outDATA<3>\$WA1.UIM_MC.D2_PT_3/IN0 )
  );
  X_INV \NlwInverterBlock_outDATA<3>\$WA1.UIM_MC.D2_PT_3/IN1  (
    .I(DCOR1CNTLOWr),
    .O(\NlwInverterSignal_outDATA<3>\$WA1.UIM_MC.D2_PT_3/IN1 )
  );
  X_INV \NlwInverterBlock_outDATA<3>\$WA1.UIM_MC.D2_PT_3/IN2  (
    .I(DCOR0CNTHIGHr),
    .O(\NlwInverterSignal_outDATA<3>\$WA1.UIM_MC.D2_PT_3/IN2 )
  );
  X_INV \NlwInverterBlock_U1/U3/holdingreg0<3>_MC.D2_PT_1/IN1  (
    .I(\AS_II/UIM ),
    .O(\NlwInverterSignal_U1/U3/holdingreg0<3>_MC.D2_PT_1/IN1 )
  );
  X_INV \NlwInverterBlock_U1/U3/holdingreg1<3>_MC.D2_PT_1/IN1  (
    .I(\AS_II/UIM ),
    .O(\NlwInverterSignal_U1/U3/holdingreg1<3>_MC.D2_PT_1/IN1 )
  );
  X_INV \NlwInverterBlock_U1/U3/holdingreg0<11>_MC.D2_PT_1/IN1  (
    .I(\AS_II/UIM ),
    .O(\NlwInverterSignal_U1/U3/holdingreg0<11>_MC.D2_PT_1/IN1 )
  );
  X_INV \NlwInverterBlock_U1/U3/holdingreg1<11>_MC.D2_PT_1/IN1  (
    .I(\AS_II/UIM ),
    .O(\NlwInverterSignal_U1/U3/holdingreg1<11>_MC.D2_PT_1/IN1 )
  );
  X_INV \NlwInverterBlock_outDATA<3>\$WA2.UIM_MC.D2_PT_1/IN0  (
    .I(DCOR0THRESLOWr),
    .O(\NlwInverterSignal_outDATA<3>\$WA2.UIM_MC.D2_PT_1/IN0 )
  );
  X_INV \NlwInverterBlock_outDATA<3>\$WA2.UIM_MC.D2_PT_2/IN0  (
    .I(DCOR0THRESLOWr),
    .O(\NlwInverterSignal_outDATA<3>\$WA2.UIM_MC.D2_PT_2/IN0 )
  );
  X_INV \NlwInverterBlock_outDATA<3>\$WA2.UIM_MC.D2_PT_2/IN1  (
    .I(DCORIFGr),
    .O(\NlwInverterSignal_outDATA<3>\$WA2.UIM_MC.D2_PT_2/IN1 )
  );
  X_INV \NlwInverterBlock_outDATA<3>\$WA2.UIM_MC.D2_PT_3/IN0  (
    .I(DCOR0THRESLOWr),
    .O(\NlwInverterSignal_outDATA<3>\$WA2.UIM_MC.D2_PT_3/IN0 )
  );
  X_INV \NlwInverterBlock_outDATA<3>\$WA2.UIM_MC.D2_PT_3/IN1  (
    .I(DCORIFGr),
    .O(\NlwInverterSignal_outDATA<3>\$WA2.UIM_MC.D2_PT_3/IN1 )
  );
  X_INV \NlwInverterBlock_outDATA<3>\$WA2.UIM_MC.D2_PT_3/IN2  (
    .I(DCOR0THRESHIGHr),
    .O(\NlwInverterSignal_outDATA<3>\$WA2.UIM_MC.D2_PT_3/IN2 )
  );
  X_INV \NlwInverterBlock_outDATA<3>\$WA2.UIM_MC.D2_PT_4/IN0  (
    .I(DCOR0THRESLOWr),
    .O(\NlwInverterSignal_outDATA<3>\$WA2.UIM_MC.D2_PT_4/IN0 )
  );
  X_INV \NlwInverterBlock_outDATA<3>\$WA2.UIM_MC.D2_PT_4/IN1  (
    .I(DCORIFGr),
    .O(\NlwInverterSignal_outDATA<3>\$WA2.UIM_MC.D2_PT_4/IN1 )
  );
  X_INV \NlwInverterBlock_outDATA<3>\$WA2.UIM_MC.D2_PT_4/IN2  (
    .I(DCOR0THRESHIGHr),
    .O(\NlwInverterSignal_outDATA<3>\$WA2.UIM_MC.D2_PT_4/IN2 )
  );
  X_INV \NlwInverterBlock_outDATA<3>\$WA2.UIM_MC.D2_PT_4/IN3  (
    .I(DCOR1THRESLOWr),
    .O(\NlwInverterSignal_outDATA<3>\$WA2.UIM_MC.D2_PT_4/IN3 )
  );
  X_INV \NlwInverterBlock_U1/U4/Latch0r<3>_MC.D2_PT_1/IN1  (
    .I(N_PZ_1018),
    .O(\NlwInverterSignal_U1/U4/Latch0r<3>_MC.D2_PT_1/IN1 )
  );
  X_INV \NlwInverterBlock_U1/U4/Latch0r<11>_MC.D2_PT_1/IN1  (
    .I(N_PZ_1018),
    .O(\NlwInverterSignal_U1/U4/Latch0r<11>_MC.D2_PT_1/IN1 )
  );
  X_INV \NlwInverterBlock_U1/U4/Latch1r<3>_MC.D2_PT_1/IN1  (
    .I(N_PZ_1019),
    .O(\NlwInverterSignal_U1/U4/Latch1r<3>_MC.D2_PT_1/IN1 )
  );
  X_INV \NlwInverterBlock_U1/U4/Latch1r<11>_MC.D2_PT_1/IN1  (
    .I(N_PZ_1019),
    .O(\NlwInverterSignal_U1/U4/Latch1r<11>_MC.D2_PT_1/IN1 )
  );
  X_INV \NlwInverterBlock_outDATA<6>\$WA5.UIM_MC.D2_PT_1/IN0  (
    .I(NET2528),
    .O(\NlwInverterSignal_outDATA<6>\$WA5.UIM_MC.D2_PT_1/IN0 )
  );
  X_INV \NlwInverterBlock_outDATA<6>\$WA1.UIM_MC.D2_PT_1/IN0  (
    .I(DCOR0CNTLOWr),
    .O(\NlwInverterSignal_outDATA<6>\$WA1.UIM_MC.D2_PT_1/IN0 )
  );
  X_INV \NlwInverterBlock_outDATA<6>\$WA1.UIM_MC.D2_PT_2/IN0  (
    .I(DCOR0CNTLOWr),
    .O(\NlwInverterSignal_outDATA<6>\$WA1.UIM_MC.D2_PT_2/IN0 )
  );
  X_INV \NlwInverterBlock_outDATA<6>\$WA1.UIM_MC.D2_PT_2/IN1  (
    .I(DCOR1CNTLOWr),
    .O(\NlwInverterSignal_outDATA<6>\$WA1.UIM_MC.D2_PT_2/IN1 )
  );
  X_INV \NlwInverterBlock_outDATA<6>\$WA1.UIM_MC.D2_PT_3/IN0  (
    .I(DCOR0CNTLOWr),
    .O(\NlwInverterSignal_outDATA<6>\$WA1.UIM_MC.D2_PT_3/IN0 )
  );
  X_INV \NlwInverterBlock_outDATA<6>\$WA1.UIM_MC.D2_PT_3/IN1  (
    .I(DCOR1CNTLOWr),
    .O(\NlwInverterSignal_outDATA<6>\$WA1.UIM_MC.D2_PT_3/IN1 )
  );
  X_INV \NlwInverterBlock_outDATA<6>\$WA1.UIM_MC.D2_PT_3/IN2  (
    .I(DCOR0CNTHIGHr),
    .O(\NlwInverterSignal_outDATA<6>\$WA1.UIM_MC.D2_PT_3/IN2 )
  );
  X_INV \NlwInverterBlock_U1/U3/holdingreg0<6>_MC.D2_PT_1/IN1  (
    .I(\AS_II/UIM ),
    .O(\NlwInverterSignal_U1/U3/holdingreg0<6>_MC.D2_PT_1/IN1 )
  );
  X_INV \NlwInverterBlock_U1/U3/holdingreg1<6>_MC.D2_PT_1/IN1  (
    .I(\AS_II/UIM ),
    .O(\NlwInverterSignal_U1/U3/holdingreg1<6>_MC.D2_PT_1/IN1 )
  );
  X_INV \NlwInverterBlock_U1/U3/holdingreg0<14>_MC.D2_PT_1/IN1  (
    .I(\AS_II/UIM ),
    .O(\NlwInverterSignal_U1/U3/holdingreg0<14>_MC.D2_PT_1/IN1 )
  );
  X_INV \NlwInverterBlock_U1/Channel0<14>_MC.D2_PT_0/IN0  (
    .I(N_PZ_982),
    .O(\NlwInverterSignal_U1/Channel0<14>_MC.D2_PT_0/IN0 )
  );
  X_INV \NlwInverterBlock_U1/Channel0<14>_MC.D2_PT_1/IN2  (
    .I(\U1/Channel0 [9]),
    .O(\NlwInverterSignal_U1/Channel0<14>_MC.D2_PT_1/IN2 )
  );
  X_INV \NlwInverterBlock_U1/Channel0<14>_MC.D2_PT_1/IN3  (
    .I(\U1/Channel0 [12]),
    .O(\NlwInverterSignal_U1/Channel0<14>_MC.D2_PT_1/IN3 )
  );
  X_INV \NlwInverterBlock_U1/Channel0<14>_MC.D2_PT_1/IN4  (
    .I(\U1/Channel0 [10]),
    .O(\NlwInverterSignal_U1/Channel0<14>_MC.D2_PT_1/IN4 )
  );
  X_INV \NlwInverterBlock_U1/Channel0<14>_MC.D2_PT_1/IN5  (
    .I(\U1/Channel0 [11]),
    .O(\NlwInverterSignal_U1/Channel0<14>_MC.D2_PT_1/IN5 )
  );
  X_INV \NlwInverterBlock_U1/Channel0<14>_MC.D2_PT_1/IN6  (
    .I(\U1/Channel0 [13]),
    .O(\NlwInverterSignal_U1/Channel0<14>_MC.D2_PT_1/IN6 )
  );
  X_INV \NlwInverterBlock_U1/Channel0<14>_MC.D2_PT_2/IN0  (
    .I(\U1/U2/location_Maddsub__n0000__n0075 [0]),
    .O(\NlwInverterSignal_U1/Channel0<14>_MC.D2_PT_2/IN0 )
  );
  X_INV \NlwInverterBlock_U1/U3/holdingreg1<14>_MC.D2_PT_1/IN1  (
    .I(\AS_II/UIM ),
    .O(\NlwInverterSignal_U1/U3/holdingreg1<14>_MC.D2_PT_1/IN1 )
  );
  X_INV \NlwInverterBlock_U1/Channel1<14>_MC.D2_PT_0/IN0  (
    .I(N_PZ_983),
    .O(\NlwInverterSignal_U1/Channel1<14>_MC.D2_PT_0/IN0 )
  );
  X_INV \NlwInverterBlock_U1/Channel1<14>_MC.D2_PT_1/IN1  (
    .I(\U1/Zero1 ),
    .O(\NlwInverterSignal_U1/Channel1<14>_MC.D2_PT_1/IN1 )
  );
  X_INV \NlwInverterBlock_U1/Channel1<14>_MC.D2_PT_1/IN3  (
    .I(\U1/U6/CurrState_Sreg0_FFD2 ),
    .O(\NlwInverterSignal_U1/Channel1<14>_MC.D2_PT_1/IN3 )
  );
  X_INV \NlwInverterBlock_U1/Channel1<14>_MC.D2_PT_1/IN5  (
    .I(\U1/U5/location_Maddsub__n0000__n0075 [0]),
    .O(\NlwInverterSignal_U1/Channel1<14>_MC.D2_PT_1/IN5 )
  );
  X_INV \NlwInverterBlock_U1/Channel1<14>_MC.D2_PT_2/IN1  (
    .I(\U1/Zero1 ),
    .O(\NlwInverterSignal_U1/Channel1<14>_MC.D2_PT_2/IN1 )
  );
  X_INV \NlwInverterBlock_U1/Channel1<14>_MC.D2_PT_2/IN3  (
    .I(\U1/U6/CurrState_Sreg0_FFD2 ),
    .O(\NlwInverterSignal_U1/Channel1<14>_MC.D2_PT_2/IN3 )
  );
  X_INV \NlwInverterBlock_U1/Channel1<14>_MC.D2_PT_2/IN5  (
    .I(N_PZ_975),
    .O(\NlwInverterSignal_U1/Channel1<14>_MC.D2_PT_2/IN5 )
  );
  X_INV \NlwInverterBlock_U1/Channel1<14>_MC.D2_PT_2/IN7  (
    .I(\U1/Channel1 [9]),
    .O(\NlwInverterSignal_U1/Channel1<14>_MC.D2_PT_2/IN7 )
  );
  X_INV \NlwInverterBlock_U1/Channel1<14>_MC.D2_PT_2/IN8  (
    .I(\U1/Channel1 [12]),
    .O(\NlwInverterSignal_U1/Channel1<14>_MC.D2_PT_2/IN8 )
  );
  X_INV \NlwInverterBlock_U1/Channel1<14>_MC.D2_PT_2/IN9  (
    .I(\U1/Channel1 [10]),
    .O(\NlwInverterSignal_U1/Channel1<14>_MC.D2_PT_2/IN9 )
  );
  X_INV \NlwInverterBlock_U1/Channel1<14>_MC.D2_PT_2/IN10  (
    .I(\U1/Channel1 [11]),
    .O(\NlwInverterSignal_U1/Channel1<14>_MC.D2_PT_2/IN10 )
  );
  X_INV \NlwInverterBlock_U1/Channel1<14>_MC.D2_PT_2/IN11  (
    .I(\U1/Channel1 [13]),
    .O(\NlwInverterSignal_U1/Channel1<14>_MC.D2_PT_2/IN11 )
  );
  X_INV \NlwInverterBlock_outDATA<6>\$WA2.UIM_MC.D2_PT_1/IN0  (
    .I(DCOR0THRESLOWr),
    .O(\NlwInverterSignal_outDATA<6>\$WA2.UIM_MC.D2_PT_1/IN0 )
  );
  X_INV \NlwInverterBlock_outDATA<6>\$WA2.UIM_MC.D2_PT_2/IN0  (
    .I(DCOR0THRESLOWr),
    .O(\NlwInverterSignal_outDATA<6>\$WA2.UIM_MC.D2_PT_2/IN0 )
  );
  X_INV \NlwInverterBlock_outDATA<6>\$WA2.UIM_MC.D2_PT_2/IN1  (
    .I(DCORIFGr),
    .O(\NlwInverterSignal_outDATA<6>\$WA2.UIM_MC.D2_PT_2/IN1 )
  );
  X_INV \NlwInverterBlock_outDATA<6>\$WA2.UIM_MC.D2_PT_3/IN0  (
    .I(DCOR0THRESLOWr),
    .O(\NlwInverterSignal_outDATA<6>\$WA2.UIM_MC.D2_PT_3/IN0 )
  );
  X_INV \NlwInverterBlock_outDATA<6>\$WA2.UIM_MC.D2_PT_3/IN1  (
    .I(DCORIFGr),
    .O(\NlwInverterSignal_outDATA<6>\$WA2.UIM_MC.D2_PT_3/IN1 )
  );
  X_INV \NlwInverterBlock_outDATA<6>\$WA2.UIM_MC.D2_PT_3/IN2  (
    .I(DCOR0THRESHIGHr),
    .O(\NlwInverterSignal_outDATA<6>\$WA2.UIM_MC.D2_PT_3/IN2 )
  );
  X_INV \NlwInverterBlock_outDATA<6>\$WA2.UIM_MC.D2_PT_4/IN0  (
    .I(DCOR0THRESLOWr),
    .O(\NlwInverterSignal_outDATA<6>\$WA2.UIM_MC.D2_PT_4/IN0 )
  );
  X_INV \NlwInverterBlock_outDATA<6>\$WA2.UIM_MC.D2_PT_4/IN1  (
    .I(DCORIFGr),
    .O(\NlwInverterSignal_outDATA<6>\$WA2.UIM_MC.D2_PT_4/IN1 )
  );
  X_INV \NlwInverterBlock_outDATA<6>\$WA2.UIM_MC.D2_PT_4/IN2  (
    .I(DCOR0THRESHIGHr),
    .O(\NlwInverterSignal_outDATA<6>\$WA2.UIM_MC.D2_PT_4/IN2 )
  );
  X_INV \NlwInverterBlock_outDATA<6>\$WA2.UIM_MC.D2_PT_4/IN3  (
    .I(DCOR1THRESLOWr),
    .O(\NlwInverterSignal_outDATA<6>\$WA2.UIM_MC.D2_PT_4/IN3 )
  );
  X_INV \NlwInverterBlock_U1/U4/Latch0r<6>_MC.D2_PT_1/IN1  (
    .I(N_PZ_1018),
    .O(\NlwInverterSignal_U1/U4/Latch0r<6>_MC.D2_PT_1/IN1 )
  );
  X_INV \NlwInverterBlock_U1/U4/Latch0r<14>_MC.D2_PT_1/IN1  (
    .I(N_PZ_1018),
    .O(\NlwInverterSignal_U1/U4/Latch0r<14>_MC.D2_PT_1/IN1 )
  );
  X_INV \NlwInverterBlock_U1/U4/Latch1r<6>_MC.D2_PT_1/IN1  (
    .I(N_PZ_1019),
    .O(\NlwInverterSignal_U1/U4/Latch1r<6>_MC.D2_PT_1/IN1 )
  );
  X_INV \NlwInverterBlock_U1/U4/Latch1r<14>_MC.D2_PT_1/IN1  (
    .I(N_PZ_1019),
    .O(\NlwInverterSignal_U1/U4/Latch1r<14>_MC.D2_PT_1/IN1 )
  );
  X_INV \NlwInverterBlock_outDATA<7>\$WA2.UIM_MC.D2_PT_1/IN0  (
    .I(DCOR0THRESLOWr),
    .O(\NlwInverterSignal_outDATA<7>\$WA2.UIM_MC.D2_PT_1/IN0 )
  );
  X_INV \NlwInverterBlock_outDATA<7>\$WA2.UIM_MC.D2_PT_2/IN0  (
    .I(DCOR0THRESLOWr),
    .O(\NlwInverterSignal_outDATA<7>\$WA2.UIM_MC.D2_PT_2/IN0 )
  );
  X_INV \NlwInverterBlock_outDATA<7>\$WA2.UIM_MC.D2_PT_2/IN1  (
    .I(DCOR0THRESHIGHr),
    .O(\NlwInverterSignal_outDATA<7>\$WA2.UIM_MC.D2_PT_2/IN1 )
  );
  X_INV \NlwInverterBlock_outDATA<7>\$WA2.UIM_MC.D2_PT_3/IN0  (
    .I(DCOR0THRESLOWr),
    .O(\NlwInverterSignal_outDATA<7>\$WA2.UIM_MC.D2_PT_3/IN0 )
  );
  X_INV \NlwInverterBlock_outDATA<7>\$WA2.UIM_MC.D2_PT_3/IN1  (
    .I(DCOR0THRESHIGHr),
    .O(\NlwInverterSignal_outDATA<7>\$WA2.UIM_MC.D2_PT_3/IN1 )
  );
  X_INV \NlwInverterBlock_outDATA<7>\$WA2.UIM_MC.D2_PT_3/IN2  (
    .I(DCOR1THRESLOWr),
    .O(\NlwInverterSignal_outDATA<7>\$WA2.UIM_MC.D2_PT_3/IN2 )
  );
  X_INV \NlwInverterBlock_U1/U4/Latch0r<7>_MC.D2_PT_1/IN1  (
    .I(N_PZ_1018),
    .O(\NlwInverterSignal_U1/U4/Latch0r<7>_MC.D2_PT_1/IN1 )
  );
  X_INV \NlwInverterBlock_U1/U4/Latch0r<15>_MC.D2_PT_1/IN1  (
    .I(N_PZ_1018),
    .O(\NlwInverterSignal_U1/U4/Latch0r<15>_MC.D2_PT_1/IN1 )
  );
  X_INV \NlwInverterBlock_U1/Channel0<15>_MC.D2_PT_0/IN0  (
    .I(N_PZ_982),
    .O(\NlwInverterSignal_U1/Channel0<15>_MC.D2_PT_0/IN0 )
  );
  X_INV \NlwInverterBlock_U1/Channel0<15>_MC.D2_PT_1/IN2  (
    .I(\U1/Channel0 [9]),
    .O(\NlwInverterSignal_U1/Channel0<15>_MC.D2_PT_1/IN2 )
  );
  X_INV \NlwInverterBlock_U1/Channel0<15>_MC.D2_PT_1/IN3  (
    .I(\U1/Channel0 [12]),
    .O(\NlwInverterSignal_U1/Channel0<15>_MC.D2_PT_1/IN3 )
  );
  X_INV \NlwInverterBlock_U1/Channel0<15>_MC.D2_PT_1/IN4  (
    .I(\U1/Channel0 [10]),
    .O(\NlwInverterSignal_U1/Channel0<15>_MC.D2_PT_1/IN4 )
  );
  X_INV \NlwInverterBlock_U1/Channel0<15>_MC.D2_PT_1/IN5  (
    .I(\U1/Channel0 [11]),
    .O(\NlwInverterSignal_U1/Channel0<15>_MC.D2_PT_1/IN5 )
  );
  X_INV \NlwInverterBlock_U1/Channel0<15>_MC.D2_PT_1/IN6  (
    .I(\U1/Channel0 [13]),
    .O(\NlwInverterSignal_U1/Channel0<15>_MC.D2_PT_1/IN6 )
  );
  X_INV \NlwInverterBlock_U1/Channel0<15>_MC.D2_PT_1/IN7  (
    .I(\U1/Channel0 [14]),
    .O(\NlwInverterSignal_U1/Channel0<15>_MC.D2_PT_1/IN7 )
  );
  X_INV \NlwInverterBlock_U1/Channel0<15>_MC.D2_PT_2/IN0  (
    .I(\U1/U2/location_Maddsub__n0000__n0075 [0]),
    .O(\NlwInverterSignal_U1/Channel0<15>_MC.D2_PT_2/IN0 )
  );
  X_INV \NlwInverterBlock_U1/U4/Latch1r<7>_MC.D2_PT_1/IN1  (
    .I(N_PZ_1019),
    .O(\NlwInverterSignal_U1/U4/Latch1r<7>_MC.D2_PT_1/IN1 )
  );
  X_INV \NlwInverterBlock_U1/U4/Latch1r<15>_MC.D2_PT_1/IN1  (
    .I(N_PZ_1019),
    .O(\NlwInverterSignal_U1/U4/Latch1r<15>_MC.D2_PT_1/IN1 )
  );
  X_INV \NlwInverterBlock_U1/Channel1<15>_MC.D2_PT_0/IN0  (
    .I(N_PZ_983),
    .O(\NlwInverterSignal_U1/Channel1<15>_MC.D2_PT_0/IN0 )
  );
  X_INV \NlwInverterBlock_U1/Channel1<15>_MC.D2_PT_1/IN1  (
    .I(\U1/Zero1 ),
    .O(\NlwInverterSignal_U1/Channel1<15>_MC.D2_PT_1/IN1 )
  );
  X_INV \NlwInverterBlock_U1/Channel1<15>_MC.D2_PT_1/IN3  (
    .I(\U1/U6/CurrState_Sreg0_FFD2 ),
    .O(\NlwInverterSignal_U1/Channel1<15>_MC.D2_PT_1/IN3 )
  );
  X_INV \NlwInverterBlock_U1/Channel1<15>_MC.D2_PT_1/IN5  (
    .I(\U1/U5/location_Maddsub__n0000__n0075 [0]),
    .O(\NlwInverterSignal_U1/Channel1<15>_MC.D2_PT_1/IN5 )
  );
  X_INV \NlwInverterBlock_U1/Channel1<15>_MC.D2_PT_2/IN1  (
    .I(\U1/Zero1 ),
    .O(\NlwInverterSignal_U1/Channel1<15>_MC.D2_PT_2/IN1 )
  );
  X_INV \NlwInverterBlock_U1/Channel1<15>_MC.D2_PT_2/IN3  (
    .I(\U1/U6/CurrState_Sreg0_FFD2 ),
    .O(\NlwInverterSignal_U1/Channel1<15>_MC.D2_PT_2/IN3 )
  );
  X_INV \NlwInverterBlock_U1/Channel1<15>_MC.D2_PT_2/IN5  (
    .I(N_PZ_975),
    .O(\NlwInverterSignal_U1/Channel1<15>_MC.D2_PT_2/IN5 )
  );
  X_INV \NlwInverterBlock_U1/Channel1<15>_MC.D2_PT_2/IN7  (
    .I(\U1/Channel1 [9]),
    .O(\NlwInverterSignal_U1/Channel1<15>_MC.D2_PT_2/IN7 )
  );
  X_INV \NlwInverterBlock_U1/Channel1<15>_MC.D2_PT_2/IN8  (
    .I(\U1/Channel1 [12]),
    .O(\NlwInverterSignal_U1/Channel1<15>_MC.D2_PT_2/IN8 )
  );
  X_INV \NlwInverterBlock_U1/Channel1<15>_MC.D2_PT_2/IN9  (
    .I(\U1/Channel1 [10]),
    .O(\NlwInverterSignal_U1/Channel1<15>_MC.D2_PT_2/IN9 )
  );
  X_INV \NlwInverterBlock_U1/Channel1<15>_MC.D2_PT_2/IN10  (
    .I(\U1/Channel1 [11]),
    .O(\NlwInverterSignal_U1/Channel1<15>_MC.D2_PT_2/IN10 )
  );
  X_INV \NlwInverterBlock_U1/Channel1<15>_MC.D2_PT_2/IN11  (
    .I(\U1/Channel1 [13]),
    .O(\NlwInverterSignal_U1/Channel1<15>_MC.D2_PT_2/IN11 )
  );
  X_INV \NlwInverterBlock_U1/Channel1<15>_MC.D2_PT_2/IN12  (
    .I(\U1/Channel1 [14]),
    .O(\NlwInverterSignal_U1/Channel1<15>_MC.D2_PT_2/IN12 )
  );
  X_INV \NlwInverterBlock_outDATA<7>\$WA5.UIM_MC.D2_PT_1/IN0  (
    .I(NET2528),
    .O(\NlwInverterSignal_outDATA<7>\$WA5.UIM_MC.D2_PT_1/IN0 )
  );
  X_INV \NlwInverterBlock_outDATA<7>\$WA1.UIM_MC.D2_PT_1/IN0  (
    .I(DCOR0CNTLOWr),
    .O(\NlwInverterSignal_outDATA<7>\$WA1.UIM_MC.D2_PT_1/IN0 )
  );
  X_INV \NlwInverterBlock_outDATA<7>\$WA1.UIM_MC.D2_PT_2/IN0  (
    .I(DCOR0CNTLOWr),
    .O(\NlwInverterSignal_outDATA<7>\$WA1.UIM_MC.D2_PT_2/IN0 )
  );
  X_INV \NlwInverterBlock_outDATA<7>\$WA1.UIM_MC.D2_PT_2/IN1  (
    .I(DCOR1CNTLOWr),
    .O(\NlwInverterSignal_outDATA<7>\$WA1.UIM_MC.D2_PT_2/IN1 )
  );
  X_INV \NlwInverterBlock_outDATA<7>\$WA1.UIM_MC.D2_PT_3/IN0  (
    .I(DCOR0CNTLOWr),
    .O(\NlwInverterSignal_outDATA<7>\$WA1.UIM_MC.D2_PT_3/IN0 )
  );
  X_INV \NlwInverterBlock_outDATA<7>\$WA1.UIM_MC.D2_PT_3/IN1  (
    .I(DCOR1CNTLOWr),
    .O(\NlwInverterSignal_outDATA<7>\$WA1.UIM_MC.D2_PT_3/IN1 )
  );
  X_INV \NlwInverterBlock_outDATA<7>\$WA1.UIM_MC.D2_PT_3/IN2  (
    .I(DCOR0CNTHIGHr),
    .O(\NlwInverterSignal_outDATA<7>\$WA1.UIM_MC.D2_PT_3/IN2 )
  );
  X_INV \NlwInverterBlock_U1/U3/holdingreg0<7>_MC.D2_PT_1/IN1  (
    .I(\AS_II/UIM ),
    .O(\NlwInverterSignal_U1/U3/holdingreg0<7>_MC.D2_PT_1/IN1 )
  );
  X_INV \NlwInverterBlock_U1/U3/holdingreg1<7>_MC.D2_PT_1/IN1  (
    .I(\AS_II/UIM ),
    .O(\NlwInverterSignal_U1/U3/holdingreg1<7>_MC.D2_PT_1/IN1 )
  );
  X_INV \NlwInverterBlock_U1/U3/holdingreg0<15>_MC.D2_PT_1/IN1  (
    .I(\AS_II/UIM ),
    .O(\NlwInverterSignal_U1/U3/holdingreg0<15>_MC.D2_PT_1/IN1 )
  );
  X_INV \NlwInverterBlock_U1/U3/holdingreg1<15>_MC.D2_PT_1/IN1  (
    .I(\AS_II/UIM ),
    .O(\NlwInverterSignal_U1/U3/holdingreg1<15>_MC.D2_PT_1/IN1 )
  );
  X_INV \NlwInverterBlock_FOOBAR2__ctinst/7/OUT  (
    .I(\NlwInverterSignal_FOOBAR2__ctinst/7/OUT ),
    .O(\FOOBAR2__ctinst/7 )
  );
  X_INV \NlwInverterBlock_FOOBAR6__ctinst/4/IN1  (
    .I(N_PZ_1007),
    .O(\NlwInverterSignal_FOOBAR6__ctinst/4/IN1 )
  );
  X_INV \NlwInverterBlock_FOOBAR9__ctinst/0/OUT  (
    .I(\NlwInverterSignal_FOOBAR9__ctinst/0/OUT ),
    .O(\FOOBAR9__ctinst/0 )
  );
  X_INV \NlwInverterBlock_FOOBAR10__ctinst/0/OUT  (
    .I(\NlwInverterSignal_FOOBAR10__ctinst/0/OUT ),
    .O(\FOOBAR10__ctinst/0 )
  );
  X_INV \NlwInverterBlock_FOOBAR12__ctinst/0/OUT  (
    .I(\NlwInverterSignal_FOOBAR12__ctinst/0/OUT ),
    .O(\FOOBAR12__ctinst/0 )
  );
  X_INV \NlwInverterBlock_FOOBAR19__ctinst/0/OUT  (
    .I(\NlwInverterSignal_FOOBAR19__ctinst/0/OUT ),
    .O(\FOOBAR19__ctinst/0 )
  );
  X_INV \NlwInverterBlock_FOOBAR21__ctinst/4/IN0  (
    .I(NET2528),
    .O(\NlwInverterSignal_FOOBAR21__ctinst/4/IN0 )
  );
  X_INV \NlwInverterBlock_FOOBAR21__ctinst/4/IN1  (
    .I(\U4/orFLGs ),
    .O(\NlwInverterSignal_FOOBAR21__ctinst/4/IN1 )
  );
  X_INV \NlwInverterBlock_FOOBAR24__ctinst/4/IN0  (
    .I(NET2528),
    .O(\NlwInverterSignal_FOOBAR24__ctinst/4/IN0 )
  );
  X_INV \NlwInverterBlock_FOOBAR24__ctinst/4/IN1  (
    .I(\U4/orFLGs ),
    .O(\NlwInverterSignal_FOOBAR24__ctinst/4/IN1 )
  );
endmodule

