//--------------------------------------------------------------------------------------------------
//
// Title       : Holdreg
// Design      : quaddecode
// Author      : mbari585
// Company     : MBARI
//
//-------------------------------------------------------------------------------------------------
//
// File        : c:\projects\genosensor\ESP 2003\quaddecode\quaddecode\src\Holdreg.v
// Generated   : Mon Oct 21 08:20:12 2002
// From        : interface description file
// By          : Itf2Vhdl ver. 1.20
//
//-------------------------------------------------------------------------------------------------
//
// Description : 
//
//-------------------------------------------------------------------------------------------------
`timescale 1ps / 1ps

//{{ Section below this comment is automatically maintained
//   and may be overwritten
//{module {Holdreg}}
module Holdreg ( DCOR1CNTHIGHr ,DCOR0CNTLOWr ,outDATA ,DCOR1CNTLOWr ,ch0in ,ch1in ,Reset ,ASleading ,Sclk ,DCOR0CNTHIGHr );

input DCOR1CNTHIGHr ;
wire DCOR1CNTHIGHr ;
input DCOR0CNTLOWr ;
wire DCOR0CNTLOWr ;
input DCOR1CNTLOWr ;
wire DCOR1CNTLOWr ;
input [15:0] ch0in ;
wire [15:0] ch0in ;
input [15:0] ch1in ;
wire [15:0] ch1in ;
input Reset ;
wire Reset ;
input ASleading ;
wire ASleading ;
input Sclk ;
wire Sclk ;
input DCOR0CNTHIGHr ;
wire DCOR0CNTHIGHr ;

output [7:0] outDATA ;
wire [7:0] outDATA ;

//}} End of automatically maintained section

// -- Enter your statements here -- //

//how this works 
//the six registers that make up the two encoder are placed in numerical order
// to take advantage of the Autoinc feature (see Interface module).  to get a clean read of the register
//a holding register is used.  This register will clock initial the requested channel on the 
//falling edge of the Sclk signal to allow for the counter to 
//stabalize before loading.
//to read channel 0 read from address DCOR0CNTLOW with auto inc.
//then pulse RD again for middle byte and then once more for High byte.
// to continue reading channel 1 also keeping strobing initial using the RD
//line.  To only read channel 1 read from address DCOR1CNTLOW.  then contnue
//on reading the next two bytes using auto inc.  The holding register is 
//loaded on the rising edge of the read of DCOR0CNTLOW and DCOR1CNTLOW.  
// this means that channel one has a small amount of time lag from where it
//is latched.

//this is used to find the edge of the reading line
reg RDedge;									  

reg [15:0] holdingreg0,holdingreg1;
wire [7:0] interDATA;

///define output muliplexer	  
//synthesis attribute KEEP of interDATA is TRUE;
//assign interDATA = ((DCOR0CNTLOWr | DCOR1CNTLOWr)) ? holdingreg[7:0] :
//			 	 ((DCOR0CNTMIDr | DCOR1CNTMIDr)) ? holdingreg[15:8] :
//			 	 (DCOR0CNTHIGHr | DCOR1CNTHIGHr) ? holdingreg[23:16] :
//			 	  8'bz;

assign interDATA =  (DCOR0CNTLOWr) ? holdingreg0[7:0] :
					(DCOR1CNTLOWr) ? holdingreg1[7:0] :
			 	 	(DCOR0CNTHIGHr) ? holdingreg0[15:8] :
					(DCOR1CNTHIGHr) ? holdingreg1[15:8] :
//			 	 	(DCOR0CNTHIGHr) ? holdingreg0[23:16] :
//					(DCOR1CNTHIGHr) ? holdingreg1[23:16] :
			 	  8'bz;

assign outDATA = interDATA;

always @ (negedge Sclk)	 //this should run on the neg edge since the counter runs on the positive
	begin
		RDedge <= (DCOR0CNTLOWr | DCOR1CNTLOWr);
		if (Reset)				// reset all the registers
			begin
				holdingreg0 <= 16'b0;
				holdingreg1 <= 16'b0;
				//rdyreg <= 1'b0;
			end				
		else
			begin
				//rdyreg <= (RDslct1 | RDslct2); 	//rdy reg is used to let the processor know that it has
				//latched the data and is ready for reading.
				//This is not really needed any more.			 
				//		if (RDslct1) holdingreg <= ch0in; 		//clock in the data from the requested/
				//		else if (RDslct2) holdingreg <= ch1in;	//register for reading
				//		else holdingreg <= holdingreg;

				//latch on the leading edge of AS, this way always ready	
				if (ASleading)
					begin
						holdingreg0 <= ch0in;
						holdingreg1 <= ch1in;
					end
			end	
	end
endmodule