//--------------------------------------------------------------------------------------------------
//
// Title       : Lswitch
// Design      : U4
// Author      : mbari###
// Company     : MBARI
//
//-------------------------------------------------------------------------------------------------
//
// File        : c:\Projects\genosensor\2g\CPLDs\Core\U4\src\Lswitch.v
// Generated   : Wed Dec 17 14:13:49 2003
// From        : interface description file
// By          : Itf2Vhdl ver. 1.20
//
//-------------------------------------------------------------------------------------------------
//
// Description : 
//
//-------------------------------------------------------------------------------------------------
`timescale 1ps / 1ps

//{{ Section below this comment is automatically maintained
//   and may be overwritten
//{module {Lswitch}}
module Lswitch ( RLS1 ,RLS2 ,Reset ,Mclk ,WR ,RDslct ,DIR1 ,DIR2 ,outDATA ,AS ,fBRK1 ,RD ,FLS1 ,Brake1 ,fBRK2 ,FLS2 ,Brake2 ,Home1 ,Home2 ,ADDR );

input RLS1 ;
wire RLS1 ;
input RLS2 ;
wire RLS2 ;
input Reset ;
wire Reset ;
input Mclk ;
wire Mclk ;
input WR ;
wire WR ;
input RDslct ;
wire RDslct ;
input DIR1 ;
wire DIR1 ;
input DIR2 ;
wire DIR2 ;
input AS ;
wire AS ;
input RD ;
wire RD ;
input FLS1 ;
wire FLS1 ;
input Brake1 ;
wire Brake1 ;
input FLS2 ;
wire FLS2 ;
input Brake2 ;
wire Brake2 ;
input Home1 ;
wire Home1 ;
input Home2 ;
wire Home2 ;
input [7:0] ADDR ;
wire [7:0] ADDR ;

output [7:0] outDATA ;
wire [7:0] outDATA ;
output fBRK1 ;
wire fBRK1 ;
output fBRK2 ;
wire fBRK2 ;

//}} End of automatically maintained section

// -- Enter your statements here -- //						 

reg fBRKr1;
reg fBRKr2;

assign outDATA = (RDslct) ? {1'bz, Home2, FLS2, RLS2, 1'bz, Home1, FLS1, RLS1} : 8'bz;
assign fBRK1 = fBRKr1;
assign fBRK2 = fBRKr2;

always @ (posedge Mclk)
	begin
		if (Reset) {fBRKr1, fBRKr2} <= 2'b0;
		else
			begin
				if ((DIR1 & !FLS1) | (!DIR1 & !RLS1)) fBRKr1 <= 1'b1;  //apply brake
				else 
					if (Brake1) fBRKr1 <= 1'b0;   //release if manual brake applied 
					else fBRKr1 <= fBRKr1;    ///leave as is.

				if ((DIR2 & !FLS2) | (!DIR2 & !RLS2)) fBRKr2 <= 1'b1;  //apply brake
				else 
					if (Brake2) fBRKr2 <= 1'b0;   //release if manual brake applied 
					else fBRKr2 <= fBRKr2;    ///leave as is.
			end
	end
endmodule
