//--------------------------------------------------------------------------------------------------
//
// Title       : Servos
// Design      : U21
// Author      : mbari###
// Company     : MBARI
//
//-------------------------------------------------------------------------------------------------
//
// File        : C:\Projects\genosensor\2g\CPLDs\Core\U21\restore\U21\compile\Servos.v
// Generated   : Fri Mar  5 13:42:09 2004
// From        : C:\Projects\genosensor\2g\CPLDs\Core\U21\restore\U21\src\Servos.bde
// By          : Bde2Verilog ver. 2.01
//
//-------------------------------------------------------------------------------------------------
//
// Description : 
//
//-------------------------------------------------------------------------------------------------

// synopsys translate_off
`ifdef _VCP
`else
`define library(a,b)
`endif
// synopsys translate_on


// ---------- Design Unit Header ---------- //
`timescale 1ns / 1ns

module Servos (DCOR0CNTHIGHr,DCOR0CNTLOWr,DCOR0CNTMIDr,DCOR0THRESLOWr,DCOR0THRESMIDr,DCOR1CNTHIGHr,DCOR1CNTLOWr,DCOR1CNTMIDr,DCOR1THRESLOWr,DCOR1THRESMIDr,
DCORENCCTLw,DCORIFGr,DCORIFGw,Home_Encoder0,Home_Encoder1,Mclk,MotorIn0,Motorin1,PhaseA_Encoder0,PhaseA_Encoder1,
PhaseB_Encoder0,PhaseB_Encoder1,Reset,inDATA,Hfound0,Hfound1,Tfound0,Tfound1,outDATA) ;

// ------------ Port declarations --------- //
input DCOR0CNTHIGHr;
wire DCOR0CNTHIGHr;
input DCOR0CNTLOWr;
wire DCOR0CNTLOWr;
input DCOR0CNTMIDr;
wire DCOR0CNTMIDr;
input DCOR0THRESLOWr;
wire DCOR0THRESLOWr;
input DCOR0THRESMIDr;
wire DCOR0THRESMIDr;
input DCOR1CNTHIGHr;
wire DCOR1CNTHIGHr;
input DCOR1CNTLOWr;
wire DCOR1CNTLOWr;
input DCOR1CNTMIDr;
wire DCOR1CNTMIDr;
input DCOR1THRESLOWr;
wire DCOR1THRESLOWr;
input DCOR1THRESMIDr;
wire DCOR1THRESMIDr;
input DCORENCCTLw;
wire DCORENCCTLw;
input DCORIFGr;
wire DCORIFGr;
input DCORIFGw;
wire DCORIFGw;
input Home_Encoder0;
wire Home_Encoder0;
input Home_Encoder1;
wire Home_Encoder1;
input Mclk;
wire Mclk;
input MotorIn0;
wire MotorIn0;
input Motorin1;
wire Motorin1;
input PhaseA_Encoder0;
wire PhaseA_Encoder0;
input PhaseA_Encoder1;
wire PhaseA_Encoder1;
input PhaseB_Encoder0;
wire PhaseB_Encoder0;
input PhaseB_Encoder1;
wire PhaseB_Encoder1;
input Reset;
wire Reset;
input [7:0] inDATA;
wire [7:0] inDATA;
output Hfound0;
wire Hfound0;
output Hfound1;
wire Hfound1;
output Tfound0;
wire Tfound0;
output Tfound1;
wire Tfound1;
output [7:0] outDATA;
wire [7:0] outDATA;

// ----------- Signal declarations -------- //
wire ce0;
wire ce1;
wire NET3720;
wire NET3721;
wire Sclk;
wire updown0;
wire updown1;
wire Zero0;
wire Zero1;
wire [23:0] Channel0;
wire [23:0] Channel1;

// -------- Component instantiations -------//

Decode U1
(
	.Reset(Reset),
	.Sclk(Sclk),
	.ce(ce0),
	.phaseA(PhaseA_Encoder0),
	.phaseB(PhaseB_Encoder0),
	.updown(updown0)
);



Counter U2
(
	.Reset(Reset),
	.Sclk(Sclk),
	.Zero(Zero0),
	.ce(ce0),
	.count(Channel0),
	.sense(NET3721),
	.updown(updown0)
);



Holdreg U3
(
	.DCOR0CNTHIGHr(DCOR0CNTHIGHr),
	.DCOR0CNTLOWr(DCOR0CNTLOWr),
	.DCOR0CNTMIDr(DCOR0CNTMIDr),
	.DCOR1CNTHIGHr(DCOR1CNTHIGHr),
	.DCOR1CNTLOWr(DCOR1CNTLOWr),
	.DCOR1CNTMIDr(DCOR1CNTMIDr),
	.Reset(Reset),
	.Sclk(Sclk),
	.ch0in(Channel0),
	.ch1in(Channel1),
	.outDATA(outDATA)
);



HomeConfig U4
(
	.Channel0(Channel0[15:0]),
	.Channel1(Channel1[15:0]),
	.DCOR0THRESLOWr(DCOR0THRESLOWr),
	.DCOR0THRESMIDr(DCOR0THRESMIDr),
	.DCOR1THRESLOWr(DCOR1THRESLOWr),
	.DCOR1THRESMIDr(DCOR1THRESMIDr),
	.DCORENCCTLw(DCORENCCTLw),
	.DCORIFGr(DCORIFGr),
	.DCORIFGw(DCORIFGw),
	.Hfound0(Hfound0),
	.Hfound1(Hfound1),
	.Home_Encoder0(Home_Encoder0),
	.Home_Encoder1(Home_Encoder1),
	.MotorIn0(MotorIn0),
	.MotorIn1(Motorin1),
	.Reset(Reset),
	.Sclk(Sclk),
	.Tfound0(Tfound0),
	.Tfound1(Tfound1),
	.Zero0(Zero0),
	.Zero1(Zero1),
	.inDATA(inDATA),
	.outDATA(outDATA),
	.sense0(NET3721),
	.sense1(NET3720)
);



Counter U5
(
	.Reset(Reset),
	.Sclk(Sclk),
	.Zero(Zero1),
	.ce(ce1),
	.count(Channel1),
	.sense(NET3720),
	.updown(updown1)
);



Decode U6
(
	.Reset(Reset),
	.Sclk(Sclk),
	.ce(ce1),
	.phaseA(PhaseA_Encoder1),
	.phaseB(PhaseB_Encoder1),
	.updown(updown1)
);



// ----------- Terminals assignment --------//
//	       ---- Input terminals ---         //
assign Sclk = Mclk;

endmodule 
