Notes on development of the PLD for the Dwarf Core
									
23-Jan-2004 SJensen
Assigned the outDATA bus to some buried FB_macrocells to help with AD pins.
Now have a problem with one of the AD pins.  Need to look into this today

Going to try assign Enable_AD as a FB to force all these signals out of the AD equations
try using FB13_2 because this block is all inputs anyways.																						 

Added "//synthesis attribute keep of Enable_AD is true;" in U4.bde this keeps Enable_AD but still does not fit.
Enable_AD does appear in the fiiting at the proper location.
This helps the enable output for the AD lines not the equation for the AD lines.
Need to reduce the compartor and save the outputs.
will generate some internal signals and keep them.

the biggest help was using keep on outDATA, and removing thier location from the UCF
Design fits now!
Could continue to do some trimming using more keeps as above

Trying to implement an address decoder in a seperate module that has all its select output KEEPed.
Does not seem top be keeping them?
maybe add KEEP in U4.bde

Without any simulation things seem to be working and fitting.  The select lines show up in the fitter output.
Going to archive at this point.

22-Jan-2004 SJensen
from xilinx prohibit does:
PROHIBIT is a basic placement constraint and a modular design constraint. It disallows the use of a site within PAR, FPGA Editor, and the CPLD fitter. 

OK, the problem was that I had pins defined in the block digram and then prohibited in the UCF.
Also since I had the outDATA defined as a pin, the fitter was tyting to find a pin for it



20-Jan-2004 SJensen
Notes started.

Need to determine why a few of the I2CS pins are being optimized out

Added in prohibit to portect assigned but currently unsued pins.  Now 
there is an error for to many pins.  Need to figure out if multiple 
assignments are happening.   Also need to look at what prohibit actually 
does, Xilinx web currently down.
