//--------------------------------------------------------------------------------------------------
//
// Title       : MSP
// Design      : U4
// Author      : mbari###
// Company     : MBARI
//
//-------------------------------------------------------------------------------------------------
//
// File        : c:\Projects\genosensor\2g\CPLDs\Core\U4\src\MSP.v
// Generated   : Wed Dec 17 11:50:44 2003
// From        : interface description file
// By          : Itf2Vhdl ver. 1.20
//
//-------------------------------------------------------------------------------------------------
//
// Description : 
//
//-------------------------------------------------------------------------------------------------
`timescale 1ps / 1ps

//{{ Section below this comment is automatically maintained
//   and may be overwritten
//{module {MSP}}
module MSP ( WR ,AS ,AD ,RD ,Mclk );

output WR ;
wire WR ;
output AS ;
wire AS ;
output RD ;
wire RD ;
output Mclk ;
wire Mclk ;

inout [7:0] AD ;
wire [7:0] AD ;

//}} End of automatically maintained section

// -- Enter your statements here -- //

reg ASr;
reg WRr;
reg RDr;
reg Mclkr;
reg [7:0] ADr;
reg busDrive;

integer J;

parameter Half_period = 500000; //this is 0.5us
parameter BITS = 12, WORDS = 87;
reg [1:BITS] Vmem [1:WORDS];


assign AS = ASr;
assign RD = RDr;
assign WR = WRr;
assign AD = (busDrive) ? ADr : 8'bz;
assign Mclk = Mclkr;

initial	  
	begin		   			  
		$readmemb("msp_vectors.txt",Vmem);
		
		for (J = 1; J<= WORDS; J = J+1)
			begin										 
				Mclkr = 0;
				{ASr, RDr, WRr, busDrive, ADr} = Vmem[J];
				#(Half_period);
				Mclkr = 1;
				#(Half_period);
			end
		#(Half_period);
		
		
	end
	
endmodule
