//--------------------------------------------------------------------------------------------------
//
// Title       : IntTest
// Design      : U21
// Author      : mbari###
// Company     : MBARI
//
//-------------------------------------------------------------------------------------------------
//
// File        : c:\Projects\genosensor\2g\CPLDs\Core\U21\src\IntTest.v
// Generated   : Fri Mar  5 13:13:54 2004
// From        : interface description file
// By          : Itf2Vhdl ver. 1.20
//
//-------------------------------------------------------------------------------------------------
//
// Description : 
//
//-------------------------------------------------------------------------------------------------
`timescale IntTest

//{{ Section below this comment is automatically maintained
//   and may be overwritten
//{module {IntTest}}
module IntTest ( inDATA ,Reset ,PWRint ,BusInt ,Thres0 ,Mclk ,Thres1 ,I2Cint ,LSwitchInt ,INT ,DCORIEw ,Homed0 ,Homed1 );

input [7:0] inDATA ;
wire [7:0] inDATA ;
input Reset ;
wire Reset ;
input PWRint ;
wire PWRint ;
input BusInt ;
wire BusInt ;
input Thres0 ;
wire Thres0 ;
input Mclk ;
wire Mclk ;
input Thres1 ;
wire Thres1 ;
input I2Cint ;
wire I2Cint ;
input LSwitchInt ;
wire LSwitchInt ;
input DCORIEw ;
wire DCORIEw ;
input Homed0 ;
wire Homed0 ;
input Homed1 ;
wire Homed1 ;

output INT ;
wire INT ;

//}} End of automatically maintained section

// -- Enter your statements here -- //

endmodule
