## Synthesis Log

Created on 08:27:10 01/12/05

Running XST Synthesis...
Please wait...
Release 6.1i - xst G.26
Copyright (c) 1995-2003 Xilinx, Inc. All rights reserved.
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TABLE OF CONTENTS
1) Synthesis Options Summary
2) HDL Compilation
3) HDL Analysis
4) HDL Synthesis
4.1) HDL Synthesis Report
5) Advanced HDL Synthesis
6) Low Level Synthesis
7) Final Report
=========================================================================
* Synthesis Options Summary *
=========================================================================
---- Source Parameters
Input File Name : U21.prj
Input Format : mixed
Verilog Include Directory : "C:\Projects\genosensor\2g\CPLDs\Core\Core_Ver1\Core\src"
Ignore Synthesis Constraint File : no
---- Target Parameters
Output File Name : U21
Output Format : NGC
Target Device : xcr3384xlTQ144-7
---- Source Options
Top Module Name : U21
Automatic FSM Extraction : yes
FSM Encoding Algorithm : Auto
Mux Extraction : yes
Resource Sharing : yes
---- Target Options
Add IO Buffers : yes
Equivalent register Removal : yes
MACRO Preserve : yes
XOR Preserve : yes
---- General Options
Optimization Goal : speed
Optimization Effort : 1
RTL Output : yes
Keep Hierarchy : yes
Hierarchy Separator : _
Bus Delimiter : <>
Case Specifier : maintain
---- Other Options
verilog2001 : yes
Clock Enable : yes
wysiwyg : no
=========================================================================
=========================================================================
* HDL Compilation *
=========================================================================
Compiling source file "C:\Projects\genosensor\2g\CPLDs\Core\Core_Ver1\Core\src/.\..\compile\U21.v"
Module <U21> compiled
Compiling source file "C:\Projects\genosensor\2g\CPLDs\Core\Core_Ver1\Core\src/.\..\src\U21AddDecode.v"
Compiling include file "C:\Projects\genosensor\2g\CPLDs\Core\Core_Ver1\Core\src/U21AddressMap.v"
Module <U21AddDecode> compiled
Compiling source file "C:\Projects\genosensor\2g\CPLDs\Core\Core_Ver1\Core\src/.\..\compile\Servos.v"
Module <Servos> compiled
Compiling source file "C:\Projects\genosensor\2g\CPLDs\Core\Core_Ver1\Core\src/.\..\src\MISCouts.v"
Module <MISCouts> compiled
Compiling source file "C:\Projects\genosensor\2g\CPLDs\Core\Core_Ver1\Core\src/.\..\src\PWRreg.v"
Module <PWRreg> compiled
Compiling source file "C:\Projects\genosensor\2g\CPLDs\Core\Core_Ver1\Core\src/.\..\src\Lswitch.v"
Module <Lswitch> compiled
Compiling source file "C:\Projects\genosensor\2g\CPLDs\Core\Core_Ver1\Core\src/.\..\compile\PWMcontrol.v"
Module <PWMcontrol> compiled
Compiling source file "C:\Projects\genosensor\2g\CPLDs\Core\Core_Ver1\Core\src/.\..\src\PWMtranslator.v"
Module <PWMtranslator> compiled
Compiling source file "C:\Projects\genosensor\2g\CPLDs\Core\Core_Ver1\Core\src/.\..\compile\I2Cfix.v"
Module <I2Cfix> compiled
Compiling source file "C:\Projects\genosensor\2g\CPLDs\Core\Core_Ver1\Core\src/.\..\src\I2CAddress.v"
Module <I2CAddress> compiled
Compiling source file "C:\Projects\genosensor\2g\CPLDs\Core\Core_Ver1\Core\src/.\..\compile\Qdecode.v"
Module <Decode> compiled
Compiling source file "C:\Projects\genosensor\2g\CPLDs\Core\Core_Ver1\Core\src/.\..\src\counter.v"
Module <Counter> compiled
Compiling source file "C:\Projects\genosensor\2g\CPLDs\Core\Core_Ver1\Core\src/.\..\src\holdreg.v"
Module <Holdreg> compiled
Compiling source file "C:\Projects\genosensor\2g\CPLDs\Core\Core_Ver1\Core\src/.\..\src\HomeConfig.v"
Module <HomeConfig> compiled
Compiling source file "C:\Projects\genosensor\2g\CPLDs\Core\Core_Ver1\Core\src/.\..\src\negdetect.v"
Module <NegDetect> compiled
Compiling source file "C:\Projects\genosensor\2g\CPLDs\Core\Core_Ver1\Core\src/.\..\src\BitCounter.v"
Module <BitCounter> compiled
Compiling source file "C:\Projects\genosensor\2g\CPLDs\Core\Core_Ver1\Core\src/.\..\src\Interface.v"
Module <Interface> compiled
Compiling source file "C:\Projects\genosensor\2g\CPLDs\Core\Core_Ver1\Core\src/.\..\src\Interrupt.v"
Module <Interrupt> compiled
Compiling source file "C:\Projects\genosensor\2g\CPLDs\Core\Core_Ver1\Core\src/.\..\src\Sensor.v"
Module <Sensor> compiled
No errors in compilation
Analysis of file <U21.prj> succeeded.
=========================================================================
* HDL Analysis *
=========================================================================
Analyzing top module <U21>.
Module <U21> is correct for synthesis.
Analyzing module <Servos>.
Module <Servos> is correct for synthesis.
Analyzing module <Decode>.
Module <Decode> is correct for synthesis.
Set property "fsm_extract = yes" for signal <CurrState_Sreg0>.
Set property "fsm_fftype = d" for signal <CurrState_Sreg0>.
Analyzing module <Counter>.
Module <Counter> is correct for synthesis.
Analyzing module <Holdreg>.
Module <Holdreg> is correct for synthesis.
Set user-defined property "KEEP = TRUE" for signal <interDATA>.
Analyzing module <HomeConfig>.
Module <HomeConfig> is correct for synthesis.
Analyzing module <I2Cfix>.
Module <I2Cfix> is correct for synthesis.
Analyzing module <NegDetect>.
Module <NegDetect> is correct for synthesis.
Analyzing module <BitCounter>.
Module <BitCounter> is correct for synthesis.
Analyzing module <U21AddDecode>.
Calling function <Select>.
Calling function <Select>.
Calling function <Select>.
Calling function <Select>.
Calling function <Select>.
Calling function <Select>.
Calling function <Select>.
Calling function <Select>.
Calling function <Select>.
Calling function <Select>.
Calling function <Select>.
Calling function <Select>.
Calling function <Select>.
Calling function <Select>.
Calling function <Select>.
Calling function <Select>.
Calling function <Select>.
Calling function <Select>.
Calling function <Select>.
Calling function <Select>.
Module <U21AddDecode> is correct for synthesis.
Set user-defined property "KEEP = TRUE" for signal <DCORSENSORw> in unit <U21AddDecode>.
Set user-defined property "KEEP = TRUE" for signal <DCORIEw> in unit <U21AddDecode>.
Set user-defined property "KEEP = TRUE" for signal <DCORIFGw> in unit <U21AddDecode>.
Set user-defined property "KEEP = TRUE" for signal <DCORIFGr> in unit <U21AddDecode>.
Set user-defined property "KEEP = TRUE" for signal <DCORLIMITSr> in unit <U21AddDecode>.
Set user-defined property "KEEP = TRUE" for signal <DCORLINTr> in unit <U21AddDecode>.
Set user-defined property "KEEP = TRUE" for signal <DCORENCCTLw> in unit <U21AddDecode>.
Set user-defined property "KEEP = TRUE" for signal <DCOR0CNTLOWr> in unit <U21AddDecode>.
Set user-defined property "KEEP = TRUE" for signal <DCOR0CNTHIGHr> in unit <U21AddDecode>.
Set user-defined property "KEEP = TRUE" for signal <DCOR1CNTLOWr> in unit <U21AddDecode>.
Set user-defined property "KEEP = TRUE" for signal <DCOR1CNTHIGHr> in unit <U21AddDecode>.
Set user-defined property "KEEP = TRUE" for signal <DCOR0THRESLOWr> in unit <U21AddDecode>.
Set user-defined property "KEEP = TRUE" for signal <DCOR0THRESHIGHr> in unit <U21AddDecode>.
Set user-defined property "KEEP = TRUE" for signal <DCOR1THRESLOWr> in unit <U21AddDecode>.
Set user-defined property "KEEP = TRUE" for signal <DCOR1THRESHIGHr> in unit <U21AddDecode>.
Set user-defined property "KEEP = TRUE" for signal <DCORENCPWRr> in unit <U21AddDecode>.
Set user-defined property "KEEP = TRUE" for signal <DCORENCPWRw> in unit <U21AddDecode>.
Set user-defined property "KEEP = TRUE" for signal <DCORCONFIGr> in unit <U21AddDecode>.
Set user-defined property "KEEP = TRUE" for signal <DCOROUTw> in unit <U21AddDecode>.
Set user-defined property "KEEP = TRUE" for signal <DCORI2CCNTr> in unit <U21AddDecode>.
Analyzing module <Interface>.
Module <Interface> is correct for synthesis.
Set user-defined property "KEEP = true" for signal <Enable_AD>.
Analyzing module <Interrupt>.
Module <Interrupt> is correct for synthesis.
Analyzing module <PWRreg>.
Module <PWRreg> is correct for synthesis.
Analyzing module <Lswitch>.
Module <Lswitch> is correct for synthesis.
Analyzing module <I2CAddress>.
Module <I2CAddress> is correct for synthesis.
Analyzing module <PWMcontrol>.
Module <PWMcontrol> is correct for synthesis.
Analyzing module <PWMtranslator>.
Module <PWMtranslator> is correct for synthesis.
Analyzing module <Sensor>.
Module <Sensor> is correct for synthesis.
Analyzing module <MISCouts>.
Module <MISCouts> is correct for synthesis.
Set user-defined property "KEEP = TRUE" for signal <DCORIEw>.
Set user-defined property "KEEP = TRUE" for signal <DCORIFGw>.
Set user-defined property "KEEP = TRUE" for signal <DCORIFGr>.
Set user-defined property "KEEP = TRUE" for signal <DCORLIMITSr>.
Set user-defined property "KEEP = TRUE" for signal <DCORENCCTLw>.
Set user-defined property "KEEP = TRUE" for signal <DCOR1CNTLOWr>.
Set user-defined property "KEEP = TRUE" for signal <DCOR1THRESLOWr>.
Set user-defined property "KEEP = TRUE" for signal <DCOR1THRESHIGHr>.
Set user-defined property "KEEP = TRUE" for signal <DCOR0CNTLOWr>.
Set user-defined property "KEEP = TRUE" for signal <DCOR0CNTHIGHr>.
Set user-defined property "KEEP = TRUE" for signal <DCOR1CNTHIGHr>.
Set user-defined property "KEEP = TRUE" for signal <DCOR0THRESLOWr>.
Set user-defined property "KEEP = TRUE" for signal <DCOR0THRESHIGHr>.
Set user-defined property "KEEP = TRUE" for signal <DCORENCPWRr>.
Set user-defined property "KEEP = TRUE" for signal <DCORENCPWRw>.
Set user-defined property "KEEP = TRUE" for signal <DCORCONFIGr>.
Set user-defined property "KEEP = TRUE" for signal <DCOROUTw>.
Set user-defined property "KEEP = TRUE" for signal <DCORI2CCNTr>.
Set user-defined property "KEEP = TRUE" for signal <DCORSENSORw>.
Set user-defined property "KEEP = TRUE" for signal <DCORLINTr>.
=========================================================================
* HDL Synthesis *
=========================================================================
Synthesizing Unit <PWMtranslator>.
Related source file is C:\Projects\genosensor\2g\CPLDs\Core\Core_Ver1\Core\src/.\..\src\PWMtranslator.v.
Unit <PWMtranslator> synthesized.
Synthesizing Unit <BitCounter>.
Related source file is C:\Projects\genosensor\2g\CPLDs\Core\Core_Ver1\Core\src/.\..\src\BitCounter.v.
WARNING:Xst:1778 - Inout <DriveSCL> is assigned but never used.
Found 8-bit tristate buffer for signal <outDATA>.
Found 1-bit tristate buffer for signal <DriveSCL>.
Found 3-bit adder for signal <$n0001> created at line 102.
Found 6-bit addsub for signal <$n0002> created at line 70.
Found 6-bit register for signal <counterr>.
Summary:
inferred 2 Adder/Subtracter(s).
inferred 9 Tristate(s).
Unit <BitCounter> synthesized.
Synthesizing Unit <NegDetect>.
Related source file is C:\Projects\genosensor\2g\CPLDs\Core\Core_Ver1\Core\src/.\..\src\negdetect.v.
Found 1-bit register for signal <Line_last>.
Found 1-bit register for signal <Ndetectr>.
Summary:
inferred 1 D-type flip-flop(s).
Unit <NegDetect> synthesized.
Synthesizing Unit <HomeConfig>.
Related source file is C:\Projects\genosensor\2g\CPLDs\Core\Core_Ver1\Core\src/.\..\src\HomeConfig.v.
Found 8-bit tristate buffer for signal <outDATA>.
Found 1-bit register for signal <E0r>.
Found 1-bit register for signal <E1r>.
Found 1-bit register for signal <HE0statelastr>.
Found 1-bit register for signal <HE0stater>.
Found 1-bit register for signal <HE1statelastr>.
Found 1-bit register for signal <HE1stater>.
Found 1-bit register for signal <Hfound0r>.
Found 1-bit register for signal <Hfound1r>.
Found 1-bit register for signal <InEdge0r>.
Found 1-bit register for signal <InEdge1r>.
Found 16-bit register for signal <Latch0r>.
Found 16-bit register for signal <Latch1r>.
Found 1-bit register for signal <LatchEdge0r>.
Found 1-bit register for signal <LatchEdge1r>.
Found 1-bit register for signal <RF0r>.
Found 1-bit register for signal <RF1r>.
Found 1-bit register for signal <sense0r>.
Found 1-bit register for signal <sense1r>.
Found 1-bit register for signal <Tfound0r>.
Found 1-bit register for signal <Tfound1r>.
Found 1-bit register for signal <Zero0r>.
Found 1-bit register for signal <Zero1r>.
Summary:
inferred 10 D-type flip-flop(s).
inferred 8 Tristate(s).
Unit <HomeConfig> synthesized.
Synthesizing Unit <Holdreg>.
Related source file is C:\Projects\genosensor\2g\CPLDs\Core\Core_Ver1\Core\src/.\..\src\holdreg.v.
WARNING:Xst:646 - Signal <RDedge> is assigned but never used.
Found 16-bit register for signal <holdingreg0>.
Found 16-bit register for signal <holdingreg1>.
Found 8-bit tristate buffer for signal <interDATA>.
Summary:
inferred 8 Tristate(s).
Unit <Holdreg> synthesized.
Synthesizing Unit <Counter>.
Related source file is C:\Projects\genosensor\2g\CPLDs\Core\Core_Ver1\Core\src/.\..\src\counter.v.
Found 16-bit up accumulator for signal <location>.
Summary:
inferred 1 Accumulator(s).
Unit <Counter> synthesized.
Synthesizing Unit <Decode>.
Related source file is C:\Projects\genosensor\2g\CPLDs\Core\Core_Ver1\Core\src/.\..\compile\Qdecode.v.
WARNING:Xst:1778 - Inout <ce> is assigned but never used.
WARNING:Xst:1778 - Inout <updown> is assigned but never used.
WARNING:Xst:1780 - Signal <ino_ce> is never used or assigned.
WARNING:Xst:1780 - Signal <ino_updown> is never used or assigned.
Found finite state machine <FSM_0> for signal <CurrState_Sreg0>.
-----------------------------------------------------------------------
| States | 9 |
| Transitions | 30 |
| Inputs | 2 |
| Outputs | 2 |
| Reset type | synchronous |
| Encoding | automatic |
| State register | d flip-flops |
-----------------------------------------------------------------------
Summary:
inferred 1 Finite State Machine(s).
Unit <Decode> synthesized.
Synthesizing Unit <MISCouts>.
Related source file is C:\Projects\genosensor\2g\CPLDs\Core\Core_Ver1\Core\src/.\..\src\MISCouts.v.
Found 8-bit register for signal <MISCr>.
Unit <MISCouts> synthesized.
Synthesizing Unit <Sensor>.
Related source file is C:\Projects\genosensor\2g\CPLDs\Core\Core_Ver1\Core\src/.\..\src\Sensor.v.
Found 4-bit register for signal <sensorr>.
Unit <Sensor> synthesized.
Synthesizing Unit <PWMcontrol>.
Related source file is C:\Projects\genosensor\2g\CPLDs\Core\Core_Ver1\Core\src/.\..\compile\PWMcontrol.v.
Unit <PWMcontrol> synthesized.
Synthesizing Unit <I2CAddress>.
Related source file is C:\Projects\genosensor\2g\CPLDs\Core\Core_Ver1\Core\src/.\..\src\I2CAddress.v.
Found 8-bit tristate buffer for signal <outDATA>.
Summary:
inferred 8 Tristate(s).
Unit <I2CAddress> synthesized.
Synthesizing Unit <Lswitch>.
Related source file is C:\Projects\genosensor\2g\CPLDs\Core\Core_Ver1\Core\src/.\..\src\Lswitch.v.
Found 8-bit tristate buffer for signal <outDATA>.
Found 1-bit register for signal <DCORIFG>.
Found 1-bit register for signal <fBRK0r>.
Found 1-bit register for signal <fBRK1r>.
Found 1-bit register for signal <FLS0fr>.
Found 1-bit register for signal <FLS0r>.
Found 1-bit register for signal <FLS1fr>.
Found 1-bit register for signal <FLS1r>.
Found 1-bit register for signal <RLS0fr>.
Found 1-bit register for signal <RLS0r>.
Found 1-bit register for signal <RLS1fr>.
Found 1-bit register for signal <RLS1r>.
Found 8 1-bit 2-to-1 multiplexers.
Summary:
inferred 2 D-type flip-flop(s).
inferred 8 Tristate(s).
Unit <Lswitch> synthesized.
Synthesizing Unit <PWRreg>.
Related source file is C:\Projects\genosensor\2g\CPLDs\Core\Core_Ver1\Core\src/.\..\src\PWRreg.v.
Found 8-bit tristate buffer for signal <outDATA>.
Found 8-bit register for signal <ctrlr>.
Found 1-bit register for signal <DCORIFG>.
Found 8-bit register for signal <Flgreg>.
Found 7 1-bit 2-to-1 multiplexers.
Summary:
inferred 8 Tristate(s).
Unit <PWRreg> synthesized.
Synthesizing Unit <Interrupt>.
Related source file is C:\Projects\genosensor\2g\CPLDs\Core\Core_Ver1\Core\src/.\..\src\Interrupt.v.
Found 8-bit tristate buffer for signal <outDATA>.
Found 8-bit register for signal <DCORIE>.
Summary:
inferred 8 Tristate(s).
Unit <Interrupt> synthesized.
Synthesizing Unit <Interface>.
Related source file is C:\Projects\genosensor\2g\CPLDs\Core\Core_Ver1\Core\src/.\..\src\Interface.v.
Found 8-bit tristate buffer for signal <AD>.
Found 8-bit comparator less for signal <$n0006> created at line 101.
Found 8-bit comparator lessequal for signal <$n0007> created at line 101.
Found 8-bit adder for signal <$n0011> created at line 101.
Found 8-bit comparator lessequal for signal <ADDR_in_Range>.
Found 8-bit register for signal <ADDR_reg>.
Found 1-bit register for signal <ASedge>.
Found 1-bit register for signal <AutoInc>.
Found 1-bit register for signal <WRRDedge>.
Summary:
inferred 3 D-type flip-flop(s).
inferred 1 Adder/Subtracter(s).
inferred 3 Comparator(s).
inferred 8 Tristate(s).
Unit <Interface> synthesized.
Synthesizing Unit <U21AddDecode>.
Related source file is C:\Projects\genosensor\2g\CPLDs\Core\Core_Ver1\Core\src/.\..\src\U21AddDecode.v.
WARNING:Xst:647 - Input <AS> is never used.
Unit <U21AddDecode> synthesized.
Synthesizing Unit <I2Cfix>.
Related source file is C:\Projects\genosensor\2g\CPLDs\Core\Core_Ver1\Core\src/.\..\compile\I2Cfix.v.
Unit <I2Cfix> synthesized.
Synthesizing Unit <Servos>.
Related source file is C:\Projects\genosensor\2g\CPLDs\Core\Core_Ver1\Core\src/.\..\compile\Servos.v.
Unit <Servos> synthesized.
Synthesizing Unit <U21>.
Related source file is C:\Projects\genosensor\2g\CPLDs\Core\Core_Ver1\Core\src/.\..\compile\U21.v.
Found 1-bit tristate buffer for signal <$n0000>.
Found 1-bit tristate buffer for signal <$n0001>.
Found 1-bit tristate buffer for signal <Dangling_Input_Signal>.
Summary:
inferred 3 Tristate(s).
Unit <U21> synthesized.
=========================================================================
HDL Synthesis Report
Macro Statistics
# FSMs : 2
# Registers : 52
6-bit register : 1
8-bit register : 5
4-bit register : 1
1-bit register : 41
16-bit register : 4
# Accumulators : 2
16-bit up accumulator : 2
# Multiplexers : 8
2-to-1 multiplexer : 8
# Tristates : 40
1-bit tristate buffer : 36
8-bit tristate buffer : 4
# Adders/Subtractors : 3
3-bit adder : 1
6-bit addsub : 1
8-bit adder : 1
# Comparators : 3
8-bit comparator lessequal : 2
8-bit comparator less : 1
=========================================================================
=========================================================================
* Advanced HDL Synthesis *
=========================================================================
INFO:Xst:1767 - HDL ADVISOR - Resource sharing has identified that some arithmetic operations in this design can share the same physical resources for reduced device utilization. For improved clock frequency you may try to disable resource sharing.
Selecting encoding for FSM_0 ...
Encoding for FSM_0 is Sequential flip-flop = D
=========================================================================
* Low Level Synthesis *
=========================================================================
WARNING:Xst:1348 - Unit Interface is merged (output interface has tristates)
WARNING:Xst:1348 - Unit BitCounter is merged (output interface has tristates)
WARNING:Xst:1348 - Unit I2Cfix is merged (output interface has tristates)
Optimizing unit <U21> ...
implementation constraint: KEEP : DCORENCPWRr
implementation constraint: KEEP : DCORI2CCNTr
implementation constraint: KEEP : DCOR0CNTLOWr
implementation constraint: KEEP : DCORENCPWRw
implementation constraint: KEEP : DCORENCCTLw
implementation constraint: KEEP : DCOR0THRESLOWr
implementation constraint: KEEP : DCOR0THRESHIGHr
implementation constraint: KEEP : DCOR1CNTHIGHr
implementation constraint: KEEP : DCORLINTr
implementation constraint: KEEP : DCOR0CNTHIGHr
implementation constraint: KEEP : DCOR1THRESHIGHr
implementation constraint: KEEP : DCORLIMITSr
implementation constraint: KEEP : DCORSENSORw
implementation constraint: KEEP : DCORCONFIGr
implementation constraint: KEEP : DCORIFGr
implementation constraint: KEEP : DCORIFGw
implementation constraint: KEEP : DCOROUTw
implementation constraint: KEEP : DCORIEw
implementation constraint: KEEP : DCOR1THRESLOWr
implementation constraint: KEEP : DCOR1CNTLOWr
implementation constraint: KEEP : U2_Enable_AD
Optimizing unit <U21AddDecode> ...
Optimizing unit <PWMtranslator> ...
Optimizing unit <I2CAddress> ...
Optimizing unit <PWMcontrol> ...
Optimizing unit <Decode> ...
Optimizing unit <NegDetect> ...
Optimizing unit <Interrupt> ...
Optimizing unit <PWRreg> ...
Optimizing unit <Lswitch> ...
Optimizing unit <Sensor> ...
Optimizing unit <MISCouts> ...
Optimizing unit <Holdreg> ...
implementation constraint: KEEP : interDATA<7>
implementation constraint: KEEP : interDATA<6>
implementation constraint: KEEP : interDATA<5>
implementation constraint: KEEP : interDATA<4>
implementation constraint: KEEP : interDATA<3>
implementation constraint: KEEP : interDATA<2>
implementation constraint: KEEP : interDATA<1>
implementation constraint: KEEP : interDATA<0>
Optimizing unit <HomeConfig> ...
Optimizing unit <Counter> ...
Optimizing unit <Servos> ...
WARNING:Xst:1710 - FF/Latch <Flgreg_6> (without init value) is constant in block <U4>.
WARNING:Xst:1710 - FF/Latch <Flgreg_2> (without init value) is constant in block <U4>.
=========================================================================
* Final Report *
=========================================================================
Final Results
RTL Top Level Output File Name : U21.ngr
Top Level Output File Name : U21
Output Format : NGC
Optimization Goal : speed
Keep Hierarchy : yes
Target Technology : xcr3384xlTQ144-7
Macro Preserve : yes
XOR Preserve : yes
Clock Enable : yes
wysiwyg : no
Design Statistics
# IOs : 85
Macro Statistics :
# Registers : 306
# 1-bit register : 306
# Tristates : 39
# 1-bit tristate buffer : 35
# 8-bit tristate buffer : 4
# Comparators : 3
# 8-bit comparator less : 1
# 8-bit comparator lessequal : 2
# Xors : 139
# 1-bit xor2 : 139
Cell Usage :
# BELS : 1696
# AND2 : 635
# AND3 : 53
# AND4 : 19
# AND5 : 4
# AND6 : 4
# AND8 : 1
# GND : 8
# INV : 711
# OR2 : 152
# OR3 : 8
# OR4 : 1
# VCC : 4
# XOR2 : 96
# FlipFlops/Latches : 193
# FD : 32
# FDCE : 161
# Tri-States : 56
# BUFE : 56
# IO Buffers : 85
# IBUF : 43
# IOBUFE : 9
# OBUF : 33
=========================================================================
CPU : 2.66 / 3.02 s | Elapsed : 3.00 / 3.00 s
-->
Total memory usage is 59912 kilobytes
Processing design ...
WARNING:NetListWriters:306 - Signal bus _n0011[6 : 0] on block Lswitch is not
reconstructed, because there are some missing bus signals.
WARNING:NetListWriters:306 - Signal bus Flgreg[7 : 0] on block PWRreg is not
reconstructed, because there are some missing bus signals.
WARNING:NetListWriters:306 - Signal bus sensorr[2 : 0] on block Sensor is not
reconstructed, because there are some missing bus signals.
Writing file U21.v completed.
Synthesis finished with warnings.