//--------------------------------------------------------------------------------------------------
//
// Title       : HomeConfig
// Design      : U4
// Author      : mbari###
// Company     : MBARI
//
//-------------------------------------------------------------------------------------------------
//
// File        : c:\Projects\genosensor\2g\CPLDs\Core\U4\src\HomeConfig.v
// Generated   : Thu Dec 18 09:50:41 2003
// From        : interface description file
// By          : Itf2Vhdl ver. 1.20
//
//-------------------------------------------------------------------------------------------------
//
// Description : 
//
//-------------------------------------------------------------------------------------------------
`timescale 1ps / 1ps

//{{ Section below this comment is automatically maintained
//   and may be overwritten
//{module {HomeConfig}}
module HomeConfig ( HF2 ,Zero1 ,inDATA ,Zero2 ,Reset ,AS ,RD ,WR ,Home_Encoder1 ,Home_Encoder2 ,ADDR ,RDslct ,Sclk ,HF1 ,WRslct );

input [7:0] inDATA ;
wire [7:0] inDATA ;
input Reset ;
wire Reset ;
input AS ;
wire AS ;
input RD ;
wire RD ;
input WR ;
wire WR ;
input Home_Encoder1 ;
wire Home_Encoder1 ;
input Home_Encoder2 ;
wire Home_Encoder2 ;
input [7:0] ADDR ;
wire [7:0] ADDR ;
input RDslct ;
wire RDslct ;
input Sclk ;
wire Sclk ;
input WRslct ;
wire WRslct ;

output HF2 ;
wire HF2 ;
output Zero1 ;
wire Zero1 ;
output Zero2 ;
wire Zero2 ;
output HF1 ;
wire HF1 ;

//}} End of automatically maintained section

// -- Enter your statements here -- //

reg RF2r;
reg E2r;
reg RF1r;
reg E1r;

reg HE1stater;
reg HE1statelastr;
reg HE2stater;
reg HE2statelastr;

reg Hfound1;
reg Hfound2;

reg Zero1r;
reg Zero2r;

assign Zero1 = Zero1r;
assign Zero2 = Zero2r;

//synthesis attribute keep of HFslct is true;
//wire HFslct;
//assign HFslct = (!AS & RD & !WR & (ADDR == 8'h04));

//assign outDATA = (!AS & RD & !WR & (ADDR == 8'h07)) ? {1'b0,Hfound2,E2r,RF2r,1'b0,Hfound1,E1r,RF1r} : 8'bz;
assign HF1 = (RDslct) ? Hfound1 : 1'bz;
assign HF2 = (RDslct) ? Hfound2 : 1'bz;

always @ (posedge Sclk)
	begin
		HE1stater <= Home_Encoder1;
		HE1statelastr <= HE1stater;
		
		HE2stater <= Home_Encoder2;
		HE2statelastr <= HE1stater;
		
		if (Reset) {Hfound2,E2r, RF2r, Hfound1, E1r, RF1r} <= 6'b0;
		else if (WRslct) {Hfound2, E2r, RF2r, Hfound1, E1r, RF1r} <= {inDATA[6:4], inDATA[2:0]};
		else 
			begin
				case ({E1r,RF1r,HE1stater,HE1statelastr})
					4'b1001,
					4'b1110:begin
								Zero1r <= 1'b1;
								Hfound1 <= 1'b1;
							end					
					default 
						begin
							Zero1r <= 1'b0;
							Hfound1 <= Hfound1;
						end
				endcase	
				case ({E2r,RF2r,HE2stater,HE2statelastr})
					4'b1001,
					4'b1101:begin
								Zero2r <= 1'b1;
								Hfound2 <= 1'b1;
							end					
					default 
						begin
							Zero2r <= 1'b0;
							Hfound2 <= Hfound2;
						end
				endcase	
			end
	end
endmodule
