//--------------------------------------------------------------------------------------------------
//
// Title       : ESP 2G Core CPLD U4
// Design      : U4
// Author      : mbari###
// Company     : MBARI
//
//-------------------------------------------------------------------------------------------------
//
// File        : C:\Projects\genosensor\2g\CPLDs\Core\U21\restore\U4\compile\U4.v
// Generated   : Fri Mar  5 13:59:31 2004
// From        : C:\Projects\genosensor\2g\CPLDs\Core\U21\restore\U4\src\U4.bde
// By          : Bde2Verilog ver. 2.01
//
//-------------------------------------------------------------------------------------------------
//
// Description : 
//
//-------------------------------------------------------------------------------------------------

// synopsys translate_off
`ifdef _VCP
`else
`define library(a,b)
`endif
// synopsys translate_on


// ---------- Design Unit Header ---------- //
`timescale 1ps / 1ps
//synthesis attribute keep of Enable_AD is true;
//synthesis attribute keep of outDATA is true;
//synthesis attribute KEEP of Rslctb is TRUE;
//synthesis attribute KEEP of Wslcta is TRUE;
//synthesis attribute KEEP of Rslct4 is TRUE;
//synthesis attribute KEEP of Rslct5 is TRUE;
//synthesis attribute KEEP of Wslct6 is TRUE;
//synthesis attribute KEEP of RslctA is TRUE;
//synthesis attribute KEEP of Wslct9 is TRUE;
//synthesis attribute KEEP of Wslctd is TRUE;
//synthesis attribute KEEP of Rslct0 is TRUE;
//synthesis attribute KEEP of Rslct1 is TRUE;
//synthesis attribute KEEP of Rslct2 is TRUE;
//synthesis attribute KEEP of Rslct3 is TRUE;
//synthesis attribute KEEP of Rslct7 is TRUE;
//synthesis attribute KEEP of Wslct7 is TRUE;

module U4 (AS,Aclk,Brake1,Brake2,DIR1,DIR2,Enc133FLG,Enc15FLG,Enc233FLG,Enc25FLG,
FLS1,FLS2,Home1,Home133FLG,Home15FLG,Home2,Home233FLG,Home25FLG,Mclk,PWM1,
PWM2,PhaseA_Encoder1,PhaseA_Encoder2,PhaseB_Encoder1,PhaseB_Encoder2,RD,RLS1,RLS2,Reset,SMclk,
WR,I2CS,Enc133ctrl,Enc15ctrl,Enc233ctrl,Enc25ctrl,Home133ctrl,Home15ctrl,Home233ctrl,Home25ctrl,
INT,LED1,LED2,LED3,LED4,LED5,MTRpwr,MTRpwrn,PAH1,PAH2,
PAL1,PAL2,PBH1,PBH2,PBL1,PBL2,AD) ;

// ------------ Port declarations --------- //
input AS;
wire AS;
input Aclk;
wire Aclk;
input Brake1;
wire Brake1;
input Brake2;
wire Brake2;
input DIR1;
wire DIR1;
input DIR2;
wire DIR2;
input Enc133FLG;
wire Enc133FLG;
input Enc15FLG;
wire Enc15FLG;
input Enc233FLG;
wire Enc233FLG;
input Enc25FLG;
wire Enc25FLG;
input FLS1;
wire FLS1;
input FLS2;
wire FLS2;
input Home1;
wire Home1;
input Home133FLG;
wire Home133FLG;
input Home15FLG;
wire Home15FLG;
input Home2;
wire Home2;
input Home233FLG;
wire Home233FLG;
input Home25FLG;
wire Home25FLG;
input Mclk;
wire Mclk;
input PWM1;
wire PWM1;
input PWM2;
wire PWM2;
input PhaseA_Encoder1;
wire PhaseA_Encoder1;
input PhaseA_Encoder2;
wire PhaseA_Encoder2;
input PhaseB_Encoder1;
wire PhaseB_Encoder1;
input PhaseB_Encoder2;
wire PhaseB_Encoder2;
input RD;
wire RD;
input RLS1;
wire RLS1;
input RLS2;
wire RLS2;
input Reset;
wire Reset;
input SMclk;
wire SMclk;
input WR;
wire WR;
input [5:0] I2CS;
wire [5:0] I2CS;
output Enc133ctrl;
wire Enc133ctrl;
output Enc15ctrl;
wire Enc15ctrl;
output Enc233ctrl;
wire Enc233ctrl;
output Enc25ctrl;
wire Enc25ctrl;
output Home133ctrl;
wire Home133ctrl;
output Home15ctrl;
wire Home15ctrl;
output Home233ctrl;
wire Home233ctrl;
output Home25ctrl;
wire Home25ctrl;
output INT;
wire INT;
output LED1;
wire LED1;
output LED2;
wire LED2;
output LED3;
wire LED3;
output LED4;
wire LED4;
output LED5;
wire LED5;
output MTRpwr;
wire MTRpwr;
output MTRpwrn;
wire MTRpwrn;
output PAH1;
wire PAH1;
output PAH2;
wire PAH2;
output PAL1;
wire PAL1;
output PAL2;
wire PAL2;
output PBH1;
wire PBH1;
output PBH2;
wire PBH2;
output PBL1;
wire PBL1;
output PBL2;
wire PBL2;
inout [7:0] AD;
wire [7:0] AD;

// ----------- Signal declarations -------- //
wire Enable_AD;
wire NET4512;
wire NET4523;
wire Rslct0;
wire Rslct1;
wire Rslct2;
wire Rslct3;
wire Rslct4;
wire Rslct5;
wire Rslct7;
wire Rslcta;
wire Rslctb;
wire Wslct6;
wire Wslct7;
wire Wslct9;
wire Wslcta;
wire Wslctd;
wire [7:0] ADDR;
wire [7:0] inDATA;
wire [7:0] outDATA;
wire [7:0] PWRflgs;

// -------- Component instantiations -------//

Servos U1
(
	.ADDR(ADDR),
	.AS(AS),
	.Home_Encoder1(Home1),
	.Home_Encoder2(Home2),
	.PhaseA_Encoder1(PhaseA_Encoder1),
	.PhaseA_Encoder2(PhaseA_Encoder2),
	.PhaseB_Encoder1(PhaseB_Encoder1),
	.PhaseB_Encoder2(PhaseB_Encoder2),
	.RD(RD),
	.RDslct1(Rslct0),
	.RDslct2(Rslct1),
	.RDslct3(Rslct2),
	.RDslct4(Rslct3),
	.RDslct5(Rslct7),
	.Reset(Reset),
	.Sclk(Mclk),
	.WR(WR),
	.WRslct(Wslct7),
	.inDATA(inDATA),
	.outDATA(outDATA)
);



AddDecode U10
(
	.ADDR(ADDR),
	.AS(AS),
	.RD(RD),
	.Rslct0(Rslct0),
	.Rslct1(Rslct1),
	.Rslct2(Rslct2),
	.Rslct3(Rslct3),
	.Rslct4(Rslct4),
	.Rslct5(Rslct5),
	.Rslct7(Rslct7),
	.Rslcta(Rslcta),
	.Rslctb(Rslctb),
	.WR(WR),
	.Wslct6(Wslct6),
	.Wslct7(Wslct7),
	.Wslct9(Wslct9),
	.Wslcta(Wslcta),
	.Wslctd(Wslctd)
);



Interface U2
(
	.AD(AD),
	.ADDR(ADDR),
	.AS(AS),
	.Enable_AD(Enable_AD),
	.Mclk(Mclk),
	.RD(RD),
	.Reset(Reset),
	.WR(WR),
	.inDATA(inDATA),
	.outDATA(outDATA)
);



I2CAddress U3
(
	.ADDR(ADDR),
	.AS(AS),
	.I2CS(I2CS),
	.RD(RD),
	.RDslct(Rslctb),
	.WR(WR),
	.outDATA(outDATA[5:0])
);



Lswitch U4
(
	.ADDR(ADDR),
	.AS(AS),
	.Brake1(Brake1),
	.Brake2(Brake2),
	.DIR1(DIR1),
	.DIR2(DIR2),
	.FLS1(FLS1),
	.FLS2(FLS2),
	.Home1(Home1),
	.Home2(Home2),
	.Mclk(Mclk),
	.RD(RD),
	.RDslct(Rslct4),
	.RLS1(RLS1),
	.RLS2(RLS2),
	.Reset(Reset),
	.WR(WR),
	.fBRK1(NET4512),
	.fBRK2(NET4523),
	.outDATA(outDATA)
);



PwrCtrl U5
(
	.ADDR(ADDR),
	.AS(AS),
	.Enc33FLG(PWRflgs[2]),
	.Enc33ctrl(Enc133ctrl),
	.Enc5FLG(PWRflgs[3]),
	.Enc5ctrl(Enc15ctrl),
	.Home33FLG(PWRflgs[0]),
	.Home33ctrl(Home133ctrl),
	.Home5FLG(PWRflgs[1]),
	.Home5ctrl(Home15ctrl),
	.Mclk(Mclk),
	.RD(RD),
	.RDslct(Rslct5),
	.Reset(Reset),
	.WR(WR),
	.WRslct(Wslct6),
	.inDATA(inDATA[3:0]),
	.outDATA(outDATA[3:0])
);



PWMcontrol U6
(
	.Brake1(Brake1),
	.Brake2(Brake2),
	.DIR1(DIR1),
	.DIR2(DIR2),
	.Mclk(Mclk),
	.PAH1(PAH1),
	.PAH2(PAH2),
	.PAL1(PAL1),
	.PAL2(PAL2),
	.PBH1(PBH1),
	.PBH2(PBH2),
	.PBL1(PBL1),
	.PBL2(PBL2),
	.PWM1(PWM1),
	.PWM2(PWM2),
	.Reset(Reset),
	.fBRK1(NET4512),
	.fBRK2(NET4523)
);



IntControl U7
(
	.ADDR(ADDR),
	.AS(AS),
	.INT(INT),
	.Mclk(Mclk),
	.PWRflgs(PWRflgs),
	.RD(RD),
	.RDslct(Rslcta),
	.Reset(Reset),
	.WR(WR),
	.WRslct1(Wslct9),
	.WRslct2(Wslctd),
	.fBRK1(NET4512),
	.fBRK2(NET4523),
	.inDATA(inDATA),
	.outDATA(outDATA)
);



PwrCtrl U8
(
	.ADDR(ADDR),
	.AS(AS),
	.Enc33FLG(PWRflgs[6]),
	.Enc33ctrl(Enc233ctrl),
	.Enc5FLG(PWRflgs[7]),
	.Enc5ctrl(Enc25ctrl),
	.Home33FLG(PWRflgs[4]),
	.Home33ctrl(Home233ctrl),
	.Home5FLG(PWRflgs[5]),
	.Home5ctrl(Home25ctrl),
	.Mclk(Mclk),
	.RD(RD),
	.RDslct(Rslct5),
	.Reset(Reset),
	.WR(WR),
	.WRslct(Wslct6),
	.inDATA(inDATA[7:4]),
	.outDATA(outDATA[7:4])
);



MISCouts U9
(
	.ADDR(ADDR),
	.AS(AS),
	.LED1(LED1),
	.LED2(LED2),
	.LED3(LED3),
	.LED4(LED4),
	.LED5(LED5),
	.MTRpwr(MTRpwr),
	.MTRpwrn(MTRpwrn),
	.Mclk(Mclk),
	.RD(RD),
	.Reset(Reset),
	.WR(WR),
	.WRslct(Wslcta),
	.inDATA(inDATA)
);



// ----------- Terminals assignment --------//
//	       ---- Input terminals ---         //
assign PWRflgs[0] = Home133FLG;
assign PWRflgs[1] = Home15FLG;
assign PWRflgs[2] = Enc133FLG;
assign PWRflgs[3] = Enc15FLG;
assign PWRflgs[4] = Home233FLG;
assign PWRflgs[5] = Home25FLG;
assign PWRflgs[6] = Enc233FLG;
assign PWRflgs[7] = Enc25FLG;

endmodule 
