## Synthesis Log

Created on 09:44:40 01/04/05

Running XST Synthesis...
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Release 6.1i - xst G.26
Copyright (c) 1995-2003 Xilinx, Inc. All rights reserved.
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TABLE OF CONTENTS
1) Synthesis Options Summary
2) HDL Compilation
3) HDL Analysis
4) HDL Synthesis
4.1) HDL Synthesis Report
5) Advanced HDL Synthesis
6) Low Level Synthesis
7) Final Report
=========================================================================
* Synthesis Options Summary *
=========================================================================
---- Source Parameters
Input File Name : SleepyPLD.prj
Input Format : mixed
Verilog Include Directory : "c:/Projects/genosensor/2g/CPLDs/Sleepy/SleepyPLD/src"
Ignore Synthesis Constraint File : no
---- Target Parameters
Output File Name : SleepyPLD
Output Format : NGC
Target Device : xcr3384xlTQ144-7
---- Source Options
Top Module Name : SleepyPLD
Automatic FSM Extraction : yes
FSM Encoding Algorithm : Auto
Mux Extraction : yes
Resource Sharing : yes
---- Target Options
Add IO Buffers : yes
Equivalent register Removal : yes
MACRO Preserve : yes
XOR Preserve : yes
---- General Options
Optimization Goal : speed
Optimization Effort : 1
RTL Output : yes
Keep Hierarchy : yes
Hierarchy Separator : _
Bus Delimiter : <>
Case Specifier : maintain
---- Other Options
verilog2001 : yes
Clock Enable : yes
wysiwyg : no
=========================================================================
=========================================================================
* HDL Compilation *
=========================================================================
Compiling source file "c:/Projects/genosensor/2g/CPLDs/Sleepy/SleepyPLD/src/.\..\compile\SleepyPLD.v"
Module <SleepyPLD> compiled
Compiling source file "c:/Projects/genosensor/2g/CPLDs/Sleepy/SleepyPLD/src/.\..\src\adddecode.v"
Module <AddDecode> compiled
Compiling source file "c:/Projects/genosensor/2g/CPLDs/Sleepy/SleepyPLD/src/.\..\src\interface.v"
Module <Interface> compiled
Compiling source file "c:/Projects/genosensor/2g/CPLDs/Sleepy/SleepyPLD/src/.\..\src\UARTaddr.v"
Module <UARTaddr> compiled
Compiling source file "c:/Projects/genosensor/2g/CPLDs/Sleepy/SleepyPLD/src/.\..\src\GalvRelay.v"
Module <GalvRelay> compiled
Compiling source file "c:/Projects/genosensor/2g/CPLDs/Sleepy/SleepyPLD/src/.\..\src\TransceiverControl.v"
Module <TransceiverControl> compiled
Compiling source file "c:/Projects/genosensor/2g/CPLDs/Sleepy/SleepyPLD/src/.\..\src\PwrControl.v"
Module <PwrControl> compiled
Compiling source file "c:/Projects/genosensor/2g/CPLDs/Sleepy/SleepyPLD/src/.\..\compile\I2Cfix.v"
Module <I2Cfix> compiled
Compiling source file "c:/Projects/genosensor/2g/CPLDs/Sleepy/SleepyPLD/src/.\..\src\negdetect.v"
Module <NegDetect> compiled
Compiling source file "c:/Projects/genosensor/2g/CPLDs/Sleepy/SleepyPLD/src/.\..\src\bitcounter.v"
Module <BitCounter> compiled
Compiling source file "c:/Projects/genosensor/2g/CPLDs/Sleepy/SleepyPLD/src/.\..\src\interrupt.v"
Module <Interrupt> compiled
Compiling source file "c:/Projects/genosensor/2g/CPLDs/Sleepy/SleepyPLD/src/.\..\src\UnusedPins.v"
Module <UnusedPins> compiled
No errors in compilation
Analysis of file <SleepyPLD.prj> succeeded.
=========================================================================
* HDL Analysis *
=========================================================================
Analyzing top module <SleepyPLD>.
Module <SleepyPLD> is correct for synthesis.
Analyzing module <AddDecode>.
Calling function <Select>.
Calling function <Select>.
Calling function <Select>.
Calling function <Select>.
Calling function <Select>.
Calling function <Select>.
Calling function <Select>.
Calling function <Select>.
Calling function <Select>.
Calling function <Select>.
Calling function <Select>.
Module <AddDecode> is correct for synthesis.
Set user-defined property "KEEP = TRUE" for signal <Wslct0> in unit <AddDecode>.
Set user-defined property "KEEP = TRUE" for signal <Wslct2> in unit <AddDecode>.
Set user-defined property "KEEP = TRUE" for signal <Wslct3> in unit <AddDecode>.
Set user-defined property "KEEP = TRUE" for signal <Wslct4> in unit <AddDecode>.
Set user-defined property "KEEP = TRUE" for signal <Wslct5> in unit <AddDecode>.
Set user-defined property "KEEP = TRUE" for signal <Wslct6> in unit <AddDecode>.
Set user-defined property "KEEP = TRUE" for signal <Wslct7> in unit <AddDecode>.
Set user-defined property "KEEP = TRUE" for signal <Wslct8> in unit <AddDecode>.
Set user-defined property "KEEP = TRUE" for signal <Rslct0> in unit <AddDecode>.
Set user-defined property "KEEP = TRUE" for signal <Rslct1> in unit <AddDecode>.
Set user-defined property "KEEP = TRUE" for signal <Rslct6> in unit <AddDecode>.
Analyzing module <Interface>.
Module <Interface> is correct for synthesis.
Set user-defined property "KEEP = true" for signal <Enable_AD>.
Analyzing module <UARTaddr>.
Module <UARTaddr> is correct for synthesis.
Analyzing module <GalvRelay>.
Module <GalvRelay> is correct for synthesis.
Analyzing module <TransceiverControl>.
Module <TransceiverControl> is correct for synthesis.
Analyzing module <PwrControl>.
Module <PwrControl> is correct for synthesis.
Analyzing module <I2Cfix>.
Module <I2Cfix> is correct for synthesis.
Analyzing module <NegDetect>.
Module <NegDetect> is correct for synthesis.
Analyzing module <BitCounter>.
Module <BitCounter> is correct for synthesis.
Analyzing module <Interrupt>.
Module <Interrupt> is correct for synthesis.
Analyzing module <UnusedPins>.
Module <UnusedPins> is correct for synthesis.
=========================================================================
* HDL Synthesis *
=========================================================================
Synthesizing Unit <BitCounter>.
Related source file is c:/Projects/genosensor/2g/CPLDs/Sleepy/SleepyPLD/src/.\..\src\bitcounter.v.
WARNING:Xst:1778 - Inout <DriveSCL> is assigned but never used.
Found 8-bit tristate buffer for signal <outDATA>.
Found 1-bit tristate buffer for signal <DriveSCL>.
Found 3-bit adder for signal <$n0001> created at line 102.
Found 6-bit addsub for signal <$n0002> created at line 70.
Found 6-bit register for signal <counterr>.
Summary:
inferred 2 Adder/Subtracter(s).
inferred 9 Tristate(s).
Unit <BitCounter> synthesized.
Synthesizing Unit <NegDetect>.
Related source file is c:/Projects/genosensor/2g/CPLDs/Sleepy/SleepyPLD/src/.\..\src\negdetect.v.
Found 1-bit register for signal <Line_last>.
Found 1-bit register for signal <Ndetectr>.
Summary:
inferred 1 D-type flip-flop(s).
Unit <NegDetect> synthesized.
Synthesizing Unit <UnusedPins>.
Related source file is c:/Projects/genosensor/2g/CPLDs/Sleepy/SleepyPLD/src/.\..\src\UnusedPins.v.
Found 1-bit tristate buffer for signal <ENDXFR>.
Found 1-bit tristate buffer for signal <IOCHCHK>.
Summary:
inferred 2 Tristate(s).
Unit <UnusedPins> synthesized.
Synthesizing Unit <Interrupt>.
Related source file is c:/Projects/genosensor/2g/CPLDs/Sleepy/SleepyPLD/src/.\..\src\interrupt.v.
WARNING:Xst:647 - Input <inDATA<6:2>> is never used.
Found 8-bit tristate buffer for signal <outDATA>.
Found 3-bit register for signal <SLPYIE>.
Summary:
inferred 8 Tristate(s).
Unit <Interrupt> synthesized.
Synthesizing Unit <I2Cfix>.
Related source file is c:/Projects/genosensor/2g/CPLDs/Sleepy/SleepyPLD/src/.\..\compile\I2Cfix.v.
Unit <I2Cfix> synthesized.
Synthesizing Unit <PwrControl>.
Related source file is c:/Projects/genosensor/2g/CPLDs/Sleepy/SleepyPLD/src/.\..\src\PwrControl.v.
Found 8-bit tristate buffer for signal <outDATA>.
Found 8-bit register for signal <Enable>.
Found 1-bit register for signal <SysEn>.
Summary:
inferred 8 Tristate(s).
Unit <PwrControl> synthesized.
Synthesizing Unit <TransceiverControl>.
Related source file is c:/Projects/genosensor/2g/CPLDs/Sleepy/SleepyPLD/src/.\..\src\TransceiverControl.v.
Found 8-bit register for signal <en>.
Found 8-bit register for signal <pd>.
Unit <TransceiverControl> synthesized.
Synthesizing Unit <GalvRelay>.
Related source file is c:/Projects/genosensor/2g/CPLDs/Sleepy/SleepyPLD/src/.\..\src\GalvRelay.v.
WARNING:Xst:647 - Input <inDATA<5:3>> is never used.
Found 5-bit register for signal <connect>.
Found 5-bit register for signal <loop>.
Unit <GalvRelay> synthesized.
Synthesizing Unit <UARTaddr>.
Related source file is c:/Projects/genosensor/2g/CPLDs/Sleepy/SleepyPLD/src/.\..\src\UARTaddr.v.
Found 1-bit tristate buffer for signal <IRQ>.
Found 8-bit tristate buffer for signal <outDATA>.
Found 8-bit tristate buffer for signal <UDATA>.
Found 8-bit tristate buffer for signal <SD>.
Found 4-bit adder for signal <$n0000> created at line 82.
Found 8-bit comparator equal for signal <$n0011> created at line 83.
Found 4-bit comparator greatequal for signal <$n0014> created at line 86.
Found 8-bit register for signal <PC104reg>.
Found 3 1-bit 2-to-1 multiplexers.
Summary:
inferred 1 Adder/Subtracter(s).
inferred 2 Comparator(s).
inferred 25 Tristate(s).
Unit <UARTaddr> synthesized.
Synthesizing Unit <Interface>.
Related source file is c:/Projects/genosensor/2g/CPLDs/Sleepy/SleepyPLD/src/.\..\src\interface.v.
Found 8-bit tristate buffer for signal <AD>.
Found 8-bit comparator less for signal <$n0006> created at line 101.
Found 8-bit comparator lessequal for signal <$n0007> created at line 101.
Found 8-bit adder for signal <$n0011> created at line 101.
Found 8-bit register for signal <ADDR_reg>.
Found 1-bit register for signal <ASedge>.
Found 1-bit register for signal <AutoInc>.
Found 1-bit register for signal <WRRDedge>.
Summary:
inferred 3 D-type flip-flop(s).
inferred 1 Adder/Subtracter(s).
inferred 2 Comparator(s).
inferred 8 Tristate(s).
Unit <Interface> synthesized.
Synthesizing Unit <AddDecode>.
Related source file is c:/Projects/genosensor/2g/CPLDs/Sleepy/SleepyPLD/src/.\..\src\adddecode.v.
WARNING:Xst:647 - Input <AS> is never used.
Unit <AddDecode> synthesized.
Synthesizing Unit <SleepyPLD>.
Related source file is c:/Projects/genosensor/2g/CPLDs/Sleepy/SleepyPLD/src/.\..\compile\SleepyPLD.v.
WARNING:Xst:647 - Input <PC104_RESET> is never used.
Unit <SleepyPLD> synthesized.
=========================================================================
HDL Synthesis Report
Macro Statistics
# Registers : 19
6-bit register : 1
1-bit register : 10
3-bit register : 1
8-bit register : 5
5-bit register : 2
# Multiplexers : 3
2-to-1 multiplexer : 3
# Tristates : 11
1-bit tristate buffer : 4
8-bit tristate buffer : 7
# Adders/Subtractors : 4
3-bit adder : 1
6-bit addsub : 1
4-bit adder : 1
8-bit adder : 1
# Comparators : 4
8-bit comparator equal : 1
4-bit comparator greatequal : 1
8-bit comparator less : 1
8-bit comparator lessequal : 1
=========================================================================
=========================================================================
* Advanced HDL Synthesis *
=========================================================================
INFO:Xst:1767 - HDL ADVISOR - Resource sharing has identified that some arithmetic operations in this design can share the same physical resources for reduced device utilization. For improved clock frequency you may try to disable resource sharing.
=========================================================================
* Low Level Synthesis *
=========================================================================
WARNING:Xst:1348 - Unit Interface is merged (output interface has tristates)
WARNING:Xst:1348 - Unit UARTaddr is merged (output interface has tristates)
WARNING:Xst:1348 - Unit BitCounter is merged (output interface has tristates)
WARNING:Xst:1348 - Unit I2Cfix is merged (output interface has tristates)
WARNING:Xst:1348 - Unit UnusedPins is merged (output interface has tristates)
Optimizing unit <SleepyPLD> ...
implementation constraint: KEEP : U2_Enable_AD
Optimizing unit <AddDecode> ...
Optimizing unit <NegDetect> ...
Optimizing unit <GalvRelay> ...
Optimizing unit <TransceiverControl> ...
Optimizing unit <PwrControl> ...
Optimizing unit <Interrupt> ...
=========================================================================
* Final Report *
=========================================================================
Final Results
RTL Top Level Output File Name : SleepyPLD.ngr
Top Level Output File Name : SleepyPLD
Output Format : NGC
Optimization Goal : speed
Keep Hierarchy : yes
Target Technology : xcr3384xlTQ144-7
Macro Preserve : yes
XOR Preserve : yes
Clock Enable : yes
wysiwyg : no
Design Statistics
# IOs : 111
Macro Statistics :
# Registers : 6
# 1-bit register : 6
# Tristates : 11
# 1-bit tristate buffer : 4
# 8-bit tristate buffer : 7
# Comparators : 3
# 4-bit comparator greatequal : 1
# 8-bit comparator less : 1
# 8-bit comparator lessequal : 1
# Xors : 44
# 1-bit xor2 : 44
Cell Usage :
# BELS : 573
# AND2 : 202
# AND3 : 35
# AND4 : 6
# AND6 : 1
# AND7 : 1
# AND8 : 2
# GND : 5
# INV : 234
# OR2 : 43
# OR3 : 6
# OR4 : 1
# VCC : 2
# XOR2 : 35
# FlipFlops/Latches : 69
# FD : 14
# FDCE : 55
# Tri-States : 32
# BUFE : 32
# IO Buffers : 110
# IBUF : 35
# IOBUFE : 25
# OBUF : 47
# OBUFE : 3
=========================================================================
CPU : 2.05 / 4.89 s | Elapsed : 2.00 / 4.00 s
-->
Total memory usage is 52744 kilobytes
Processing design ...
Writing file SleepyPLD.v completed.
Synthesis finished with warnings.