This file was created to keep notes on this design created: 17-Mar-04 SJensen 8-june10 SJensen Sleepy on Betty was reseting when an ESD event happened with the puck raising and the hand closing. Two changes were applied 1)100pF capacitor from C17, 18, 21 or, 24 ground to R75 signal side 2)100 ohm resistor across pins 4 and 5 of U5 Changes know as Recall 2 made version 1_0_1 11-Dec-09 SJensen DWSM 4km sleepy haqd trouble with the remote reset input causing spurious resets. A 100 pull-up resistor should be placed on the Master Reset line. 18-July-06 JRosal Fixed U36 pinout to match datasheet. Backannotated from Layout file. "SLEEPY_REV1_0_0_071806-1330.MAX" is the final layout. 10-May-06 SJensen In preparation for buil;ding copies I am creating version 1-0-0 for rebuild to fix the few errors on the board. 13-Oct-05 SJensen Made Version 0_1_1. To have consitence in the the power sourceing from the analytical, external sampler, and modem power ports J21 and J24 must be installed backwards. 31-Aug-05 SJensen Due to power glitch when dwarf power is turned on the Host would reset. The rate of transition has been slowed to about 2ms using an RC around the swithcing FET. C124 and R77, and C125 and R78 add at Q15. 10-Aug-05 SJensen 02-Aug-05 SJensen Rev 0.1.0 Cummulative board changes to make rev 0 functional: 1) U30, Camera 12V DC-DC converter is not installed. Place jumer wire across leads 2) C99 in not installed instead C122 is used, this part is to large for the pads 3) Lift pin 1 of U2. From U2 pin1, D7 is placed to via connecting Pad (Anode at Pin) 4) Blue wire from U2 pin 1 to U6 pin 33. 5) U5 pin 5 is lifted and a blue from the pin to sleepy 3.3 is connected. 6) D9 should be added in conjunction in a back to back arrangement with D1 7) U36 pin out was layed out incorrectly, need to contort part. 8) D50, photodiode needs to be installed backwards. 9) Added C123, 0.1uF from MSP_reset to ground. Used via on trace from Pin 58 of U6, to C19 15-Jul-05 SJensen need to document the change in power for U5. The chip should get it's power from Sleepy 3.3 07-APR-05 SJensen Added some blue wire changes to sleepy diode to couple MR reset to CPLD reset Cap on Mr reset to stabalize UART reset from Mr to CPLDreset 22-Nov-04 SJensen Need to be able to shut off the battery power to the dwarf subsystem. Added IPS5551 to provide this function. Removed ICHCHK from CPLD for a control pin. 27-Aug-04 SJensen Upon starting the PLd development I noticed that I do not have control points for the analytical modules connect and loop lines. I do not have the pins either on the PLD, thus I am removing them from the design. 3-August-04 JRosal R74 footprint changed to 0805 to fulfill 100ppm requirement. J23 footprint change from VS to VP version. U5 footprint changed to SOT23-5-DBV. 28-July-04 SJensen Adding RS232 transcievers to command port. 12-July-04 SJensen Finished change over to TQ2's. Reset reference designators. 7-July-04 JRosal Added footprints. Changed root file to create NET List. 2-July-04 SJensen Creating version 003. Going to change from TQ4 to TQ2 relays and fix a few part problems. 1-July-04 SJensen Cleaned up design and readied for Layout. New parts and deleted a few wrong footprints. 30-June-04 SJensen Made a number of wiring changes and added a couple of parts. Need to add bypass capacitors! 29-June-04 JRosal Entered footprints for all components. Made fuseclips into a single component. 18-June-04 SJensen Enetered all part numbers to begin layout 14-June-04 SJensen Removed from the system power supply seperate feedback of status. Add a gat such that when the status line is pulled low both 3.3 and 5 are shutdown. Because of this you will not get seperate status indication. Added three connectors for power ouput to system and I2C bus. 11-June-04 SJensen I am going to remove the temperature sensors on the control switches to remove and save output pins on the processor. Moving to rev 002 to make this change 17-Mar-04 SJensen Check out the modem interface and make sure it is right. Need pull down on PE Set up SCL and serial stuff to be pin compatibale with Rev1 Core as follows: P2.0 SCLreset P2.1 SCLinc P2.2 HandShake in P2.3 tied to Pin 3.7 RXin P2.5 Dosc resistor to +3.3 P2.7 interrupt P3.6 TX out P3.7 RX in P5.7 Handshake out Set up CPLD interface compatible with core P1 Address/Data 7-0 P3.0 AS P3.2 WR P3.4 RD Set up part programming plug compatible with Core Setup Serial interface to be compatible with Core Pin 1 = 3.3V 2 = TX out 3 = RX in 4 = Gnd 5 = Handshake in 6 = Handshake out