Notes on development of the PLD for the Dwarf Core
for searching use this phrase: Things to add
	 
5-Mar-04 SJensen
Setting up to simulate timing model.

Things to add - Cut down to 16 bit encoder counters

4-Mar-04 SJensen
Updated Interrupt to be the logical and of DCORIE and its input.
Added GP_MOTOR outputs to the MISCouts
Fixed up Encpwr, and included the flag latch

3-Mar-04 SJensen
Some things to think about.  AS, RD, and WR during MSP start up are floating.  If switched to active low and the pld inputs
configurerd for pullup then they would be somewhat defined during this time.

The AS, RD and WR lines have been switched to active high, and PULLUP added to UCF.

Homing the channel
  the bits which control this feature are:
		DCORENCCTL - Edge - this set the edge to sense, rising (1) or falling (0).
		DCORENCCTL - Home Enable - enables(1) the homing function
		DCORIFG - Homed - this bit indicates that the home edge has been sensed (1).
		DCOREIE - Homed - this bit enables (1) an interrupt on the setting of the homed flag.

The limit switches should be set up to show a latched version of them when the IFG is set
This also applies to the power flags.

home edge should always cause a latch
cut down to 16 bits

It seems to fit with 124 bit counters!

27-Feb-04 SJensen
This design has been migrated over frmo U4 to U21 since there is a major change happening in the structure of how
the CPLD interacts with the processor.  The reason for U21 is that is the acual part number on the board.  this was changed 
when the board was fabricated but not updated until now in the code.

   								
Brent put together after our dicussions yesterday Dwarfcore.h  This is included in this workspace so that there is a 
reference to what the cpld looks like.  It will be archived with this workspace
	 
I think all is moved over and renamed to work under the U21 project,Suthesised and Implemented.

26-Feb-04 SJensen
Discussion with brent come up with some good fixes.  I am going to archive this as it stand right now.
then make changes as discussed.  Shall change to version 2.
On to version 0 Reversion 1.

the reason is that version will match the board and revision will be used for the code revision on the board

first change is to define the state of the unsed pins in the I2Caddress register to 0.

Then combine the statues and reset register for interrupts.  Also make the write set the register directly
allows soft6ware interrupts.															   

Combine encoder/home register to common with flag



25-Feb-04 SJensen
added in the brent I2C fix.

need to add in the handshake from gpio to ud's

home routine brakes motor

9-Feb-04 SJensen

changed MISCouts and PWRctrl to be Async reset so that they will shut down when a reset is pressed.

Made a few other changes and don't remeber them all, Small to correct functionality.

Change to negative egde clock in the home found routine.

2-Feb-04 SJensen
Changed the clock source from Mclk to SMclk.  Did this by the UCF file and setting Mclk
pin number equal to the SMckl pin number.  Mclk goes on and off due to power savings and such.

2-Feb-04 SJensen

Added LightSense to design.  A low on the light sense input gates the LED's off. 						
		
28-Jan-04 SJensen

Continue testing of timing model.  Commenting vector file.  have changed address and need to update vector.  

Things to add - Need to be able to read home found directly not through interupt, actually you can in the servos block
                but I need to move this to the limit switch address - did it!

27-Jan-04 SJensen
Modified the srvos BDE to label the two counter buses Channel1 and 2.  Also labeld ce, updown and Zero2.
Going to recomile ad fit the design.  This should make the finding of these signal easier in the timing simulation.
												   
Fitter output shows that RF2r from home config has been removed.  need to look into this.  Shoudl also try to fix the 
warning error about enable_AD.  This is just to many instantses of it.
   
Cleaned up a lot of the warnings.  A few reamin but are OK.
Warnings associated with Qdecode ce and up_down are ok.  Because state machine forces an inout type
Warning from homeconfig inDATA 3 and 7 ok
Warning from MISCouts inDATA 6, 5 OK

Found a few design errors which have been fixed.
Enable_AD still exsist in fitter

Now ready to do some more timing simulation!

Things to add - Limit switch sense!

26-Jan-04 SJensen

To use the signals from the timing simulation, select in the browser and then look below for the appropriate signal and
 drag that in.

Right now it looks like the ADDR register is not working in the fitted version.  Went back to functional and it works.
What now!
																	  
Problem - the PRLD line need to be toggled start at 1 for 100ns then leave low.  I added a stimulator to the simulation.
Seems to be working now!

Need to define a name for the two encoder counter buses in the servo channels.  This is t help in debugging.  Aldec
assigns it a BUSxxx name which is hard to find.  This bus then becomes the encoder counter.


25-Jan-04 SJensen
With all the success as below.  It is time to try the timing model.  I'll try to get it and set up a seperate project 
to see if it compiles and then test it.  I'll also try to link in this project testbench to run it.	

Investigating how to get the timing model to simulate within the U4 project.  Using design flow and options to timing
simulation.  got all the files included, MSP, U4_TB, time_sim ...  but does not seem to get the test becnh in there.

Problem appears that, I'm not sure how to get the top-level set correctly for the time sim to use the TB?

Got it loaded, using the simulation options on the design flow page, added in U4_TB and MSP.   Then set the top level to 
U4_TB.  This caused an error in loading the glbl.  After a restart, the trick is to have to top level selection look like this:
"U4_TB glbl"  this causes two thing to get loaded.  Now on to see if this works!

Looks like it may work.  Need to figure out what the signals names mean and are?

Going to archive at this point.


									
23-Jan-2004 SJensen
Assigned the outDATA bus to some buried FB_macrocells to help with AD pins.
Now have a problem with one of the AD pins.  Need to look into this today

Going to try assign Enable_AD as a FB to force all these signals out of the AD equations
try using FB13_2 because this block is all inputs anyways.																						 

Added "//synthesis attribute keep of Enable_AD is true;" in U4.bde this keeps Enable_AD but still does not fit.
Enable_AD does appear in the fiiting at the proper location.
This helps the enable output for the AD lines not the equation for the AD lines.
Need to reduce the compartor and save the outputs.
will generate some internal signals and keep them.

the biggest help was using keep on outDATA, and removing thier location from the UCF
Design fits now!
Could continue to do some trimming using more keeps as above

Trying to implement an address decoder in a seperate module that has all its select outputs defined as KEEP TRUE.
Does not seem top be keeping them?
maybe add KEEP in U4.bde

Without any simulation things seem to be working and fitting.  The select lines show up in the fitter output.
Going to archive at this point.
								   
Also the I2C issue seems to be fixed, probable something that was not compiled and all my messing I compiled it.
Also removed the need to have the internal outDATA bus defined seperate from the AD lines.  Removing the address
and control lines fromt he equation was the big help.


22-Jan-2004 SJensen
from xilinx prohibit does:
PROHIBIT is a basic placement constraint and a modular design constraint. It disallows the use of a site within PAR, FPGA Editor, and the CPLD fitter. 

OK, the problem was that I had pins defined in the block digram and then prohibited in the UCF.
Also since I had the outDATA defined as a pin, the fitter was tyting to find a pin for it



20-Jan-2004 SJensen
Notes started.

Need to determine why a few of the I2CS pins are being optimized out

Added in prohibit to portect assigned but currently unsued pins.  Now 
there is an error for to many pins.  Need to figure out if multiple 
assignments are happening.   Also need to look at what prohibit actually 
does, Xilinx web currently down.
