## Synthesis Log

Created on 08:07:19 03/05/04

Running XST Synthesis...
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Release 6.1i - xst G.26
Copyright (c) 1995-2003 Xilinx, Inc. All rights reserved.
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TABLE OF CONTENTS
1) Synthesis Options Summary
2) HDL Compilation
3) HDL Analysis
4) HDL Synthesis
4.1) HDL Synthesis Report
5) Advanced HDL Synthesis
6) Low Level Synthesis
7) Final Report
=========================================================================
* Synthesis Options Summary *
=========================================================================
---- Source Parameters
Input File Name : U21.prj
Input Format : mixed
Verilog Include Directory : c:\Projects\genosensor\2g\CPLDs\Core\U21\src
Synthesis Constraint File : C:\Projects\genosensor\2g\CPLDs\Core\U21\src\U21.xcf
Ignore Synthesis Constraint File : YES
---- Target Parameters
Output File Name : U21
Output Format : NGC
Target Device : xcr3384xl-7TQ144
---- Source Options
Top Module Name : U21
Automatic FSM Extraction : YES
FSM Encoding Algorithm : Auto
Mux Extraction : YES
Resource Sharing : YES
---- Target Options
Add IO Buffers : YES
Equivalent register Removal : YES
MACRO Preserve : YES
XOR Preserve : YES
---- General Options
Optimization Goal : Area
Optimization Effort : 1
Keep Hierarchy : YES
RTL Output : Yes
Hierarchy Separator : _
Bus Delimiter : <>
Case Specifier : Maintain
---- Other Options
wysiwyg : NO
Clock Enable : YES
=========================================================================
=========================================================================
* HDL Compilation *
=========================================================================
Compiling source file "c:\Projects\genosensor\2g\CPLDs\Core\U21\src/.\..\compile\U21.v"
Module <U21> compiled
Compiling source file "c:\Projects\genosensor\2g\CPLDs\Core\U21\src/.\..\src\U21AddDecode.v"
Compiling include file "c:\Projects\genosensor\2g\CPLDs\Core\U21\src/U21AddressMap.v"
Module <U21AddDecode> compiled
Compiling source file "c:\Projects\genosensor\2g\CPLDs\Core\U21\src/.\..\src\Interrupt.v"
Module <Interrupt> compiled
Compiling source file "c:\Projects\genosensor\2g\CPLDs\Core\U21\src/.\..\compile\Servos.v"
Module <Servos> compiled
Compiling source file "c:\Projects\genosensor\2g\CPLDs\Core\U21\src/.\..\src\MISCouts.v"
Module <MISCouts> compiled
Compiling source file "c:\Projects\genosensor\2g\CPLDs\Core\U21\src/.\..\src\PWRreg.v"
Module <PWRreg> compiled
Compiling source file "c:\Projects\genosensor\2g\CPLDs\Core\U21\src/.\..\src\Lswitch.v"
Module <Lswitch> compiled
Compiling source file "c:\Projects\genosensor\2g\CPLDs\Core\U21\src/.\..\compile\PWMcontrol.v"
Module <PWMcontrol> compiled
Compiling source file "c:\Projects\genosensor\2g\CPLDs\Core\U21\src/.\..\src\PWMtranslator.v"
Module <PWMtranslator> compiled
Compiling source file "c:\Projects\genosensor\2g\CPLDs\Core\U21\src/.\..\compile\I2Cfix.v"
Module <I2Cfix> compiled
Compiling source file "c:\Projects\genosensor\2g\CPLDs\Core\U21\src/.\..\src\I2CAddress.v"
Module <I2CAddress> compiled
Compiling source file "c:\Projects\genosensor\2g\CPLDs\Core\U21\src/.\..\compile\Qdecode.v"
Module <Decode> compiled
Compiling source file "c:\Projects\genosensor\2g\CPLDs\Core\U21\src/.\..\src\counter.v"
Module <Counter> compiled
Compiling source file "c:\Projects\genosensor\2g\CPLDs\Core\U21\src/.\..\src\holdreg.v"
Module <Holdreg> compiled
Compiling source file "c:\Projects\genosensor\2g\CPLDs\Core\U21\src/.\..\src\Interface.v"
Module <Interface> compiled
Compiling source file "c:\Projects\genosensor\2g\CPLDs\Core\U21\src/.\..\src\PwrCtrl.v"
Module <PwrCtrl> compiled
Compiling source file "c:\Projects\genosensor\2g\CPLDs\Core\U21\src/.\..\src\HomeConfig.v"
Module <HomeConfig> compiled
Compiling source file "c:\Projects\genosensor\2g\CPLDs\Core\U21\src/.\..\src\MSP.v"
Module <MSP> compiled
Compiling source file "c:\Projects\genosensor\2g\CPLDs\Core\U21\src/.\..\src\negdetect.v"
Module <NegDetect> compiled
Compiling source file "c:\Projects\genosensor\2g\CPLDs\Core\U21\src/.\..\src\BitCounter.v"
Module <BitCounter> compiled
No errors in compilation
Analysis of file <U21.prj> succeeded.
=========================================================================
* HDL Analysis *
=========================================================================
Analyzing top module <U21>.
Module <U21> is correct for synthesis.
Analyzing module <Servos>.
Module <Servos> is correct for synthesis.
Analyzing module <Decode>.
Module <Decode> is correct for synthesis.
Set property "fsm_extract = yes" for signal <CurrState_Sreg0>.
Set property "fsm_fftype = d" for signal <CurrState_Sreg0>.
Analyzing module <Counter>.
Module <Counter> is correct for synthesis.
Analyzing module <Holdreg>.
Module <Holdreg> is correct for synthesis.
Set user-defined property "KEEP = TRUE" for signal <interDATA>.
Analyzing module <HomeConfig>.
Module <HomeConfig> is correct for synthesis.
Analyzing module <I2Cfix>.
Module <I2Cfix> is correct for synthesis.
Analyzing module <NegDetect>.
Module <NegDetect> is correct for synthesis.
Analyzing module <BitCounter>.
Module <BitCounter> is correct for synthesis.
Analyzing module <U21AddDecode>.
Calling function <Select>.
Calling function <Select>.
Calling function <Select>.
Calling function <Select>.
Calling function <Select>.
Calling function <Select>.
Calling function <Select>.
Calling function <Select>.
Calling function <Select>.
Calling function <Select>.
Calling function <Select>.
Calling function <Select>.
Calling function <Select>.
Calling function <Select>.
Calling function <Select>.
Calling function <Select>.
Calling function <Select>.
Calling function <Select>.
Calling function <Select>.
Calling function <Select>.
Module <U21AddDecode> is correct for synthesis.
Set user-defined property "KEEP = TRUE" for signal <DCORIEw> in unit <U21AddDecode>.
Set user-defined property "KEEP = TRUE" for signal <DCORIFGw> in unit <U21AddDecode>.
Set user-defined property "KEEP = TRUE" for signal <DCORIFGr> in unit <U21AddDecode>.
Set user-defined property "KEEP = TRUE" for signal <DCORLIMITSr> in unit <U21AddDecode>.
Set user-defined property "KEEP = TRUE" for signal <DCORENCCTLw> in unit <U21AddDecode>.
Set user-defined property "KEEP = TRUE" for signal <DCOR0CNTLOWr> in unit <U21AddDecode>.
Set user-defined property "KEEP = TRUE" for signal <DCOR0CNTMIDr> in unit <U21AddDecode>.
Set user-defined property "KEEP = TRUE" for signal <DCOR0CNTHIGHr> in unit <U21AddDecode>.
Set user-defined property "KEEP = TRUE" for signal <DCOR1CNTLOWr> in unit <U21AddDecode>.
Set user-defined property "KEEP = TRUE" for signal <DCOR1CNTMIDr> in unit <U21AddDecode>.
Set user-defined property "KEEP = TRUE" for signal <DCOR1CNTHIGHr> in unit <U21AddDecode>.
Set user-defined property "KEEP = TRUE" for signal <DCOR0THRESLOWr> in unit <U21AddDecode>.
Set user-defined property "KEEP = TRUE" for signal <DCOR0THRESMIDr> in unit <U21AddDecode>.
Set user-defined property "KEEP = TRUE" for signal <DCOR1THRESLOWr> in unit <U21AddDecode>.
Set user-defined property "KEEP = TRUE" for signal <DCOR1THRESMIDr> in unit <U21AddDecode>.
Set user-defined property "KEEP = TRUE" for signal <DCORENCPWRr> in unit <U21AddDecode>.
Set user-defined property "KEEP = TRUE" for signal <DCORENCPWRw> in unit <U21AddDecode>.
Set user-defined property "KEEP = TRUE" for signal <DCORCONFIGr> in unit <U21AddDecode>.
Set user-defined property "KEEP = TRUE" for signal <DCOROUTw> in unit <U21AddDecode>.
Set user-defined property "KEEP = TRUE" for signal <DCORI2CCNTr> in unit <U21AddDecode>.
Analyzing module <Interface>.
Module <Interface> is correct for synthesis.
Set user-defined property "KEEP = true" for signal <Enable_AD>.
Analyzing module <Interrupt>.
Module <Interrupt> is correct for synthesis.
Analyzing module <PWRreg>.
Module <PWRreg> is correct for synthesis.
Analyzing module <Lswitch>.
Module <Lswitch> is correct for synthesis.
Analyzing module <I2CAddress>.
Module <I2CAddress> is correct for synthesis.
Analyzing module <PWMcontrol>.
Module <PWMcontrol> is correct for synthesis.
Analyzing module <PWMtranslator>.
Module <PWMtranslator> is correct for synthesis.
Analyzing module <MISCouts>.
Module <MISCouts> is correct for synthesis.
WARNING:Xst:1364 - Synthesis constraint file 'C:\Projects\genosensor\2g\CPLDs\Core\U21\src\U21.xcf' ignored due to -iuc option set to yes
=========================================================================
* HDL Synthesis *
=========================================================================
Synthesizing Unit <PWMtranslator>.
Related source file is c:\Projects\genosensor\2g\CPLDs\Core\U21\src/.\..\src\PWMtranslator.v.
Unit <PWMtranslator> synthesized.
Synthesizing Unit <BitCounter>.
Related source file is c:\Projects\genosensor\2g\CPLDs\Core\U21\src/.\..\src\BitCounter.v.
WARNING:Xst:1778 - Inout <DriveSCL> is assigned but never used.
Found 8-bit tristate buffer for signal <outDATA>.
Found 1-bit tristate buffer for signal <DriveSCL>.
Found 3-bit adder for signal <$n0001> created at line 70.
Found 6-bit addsub for signal <$n0002> created at line 62.
Found 6-bit register for signal <counterr>.
Summary:
inferred 2 Adder/Subtracter(s).
inferred 9 Tristate(s).
Unit <BitCounter> synthesized.
Synthesizing Unit <NegDetect>.
Related source file is c:\Projects\genosensor\2g\CPLDs\Core\U21\src/.\..\src\negdetect.v.
Found 1-bit register for signal <Line_last>.
Found 1-bit register for signal <Ndetectr>.
Summary:
inferred 1 D-type flip-flop(s).
Unit <NegDetect> synthesized.
Synthesizing Unit <HomeConfig>.
Related source file is c:\Projects\genosensor\2g\CPLDs\Core\U21\src/.\..\src\HomeConfig.v.
WARNING:Xst:647 - Input <DCORIFGr> is never used.
Found 8-bit tristate buffer for signal <outDATA>.
Found 1-bit register for signal <E0r>.
Found 1-bit register for signal <E1r>.
Found 1-bit register for signal <HE0statelastr>.
Found 1-bit register for signal <HE0stater>.
Found 1-bit register for signal <HE1statelastr>.
Found 1-bit register for signal <HE1stater>.
Found 1-bit register for signal <Hfound0r>.
Found 1-bit register for signal <Hfound1r>.
Found 1-bit register for signal <InEdge0r>.
Found 1-bit register for signal <InEdge1r>.
Found 16-bit register for signal <Latch0r>.
Found 16-bit register for signal <Latch1r>.
Found 1-bit register for signal <LatchEdge0r>.
Found 1-bit register for signal <LatchEdge1r>.
Found 1-bit register for signal <RF0r>.
Found 1-bit register for signal <RF1r>.
Found 1-bit register for signal <sense0r>.
Found 1-bit register for signal <sense1r>.
Found 1-bit register for signal <Tfound0r>.
Found 1-bit register for signal <Tfound1r>.
Found 1-bit register for signal <Zero0r>.
Found 1-bit register for signal <Zero1r>.
Summary:
inferred 12 D-type flip-flop(s).
inferred 8 Tristate(s).
Unit <HomeConfig> synthesized.
Synthesizing Unit <Holdreg>.
Related source file is c:\Projects\genosensor\2g\CPLDs\Core\U21\src/.\..\src\holdreg.v.
Found 24-bit register for signal <holdingreg>.
Found 8-bit tristate buffer for signal <interDATA>.
Found 1-bit register for signal <RDedge>.
Found 24 1-bit 2-to-1 multiplexers.
Summary:
inferred 1 D-type flip-flop(s).
inferred 8 Tristate(s).
Unit <Holdreg> synthesized.
Synthesizing Unit <Counter>.
Related source file is c:\Projects\genosensor\2g\CPLDs\Core\U21\src/.\..\src\counter.v.
Found 24-bit updown counter for signal <location>.
Summary:
inferred 1 Counter(s).
Unit <Counter> synthesized.
Synthesizing Unit <Decode>.
Related source file is c:\Projects\genosensor\2g\CPLDs\Core\U21\src/.\..\compile\Qdecode.v.
WARNING:Xst:1778 - Inout <ce> is assigned but never used.
WARNING:Xst:1778 - Inout <updown> is assigned but never used.
WARNING:Xst:1780 - Signal <ino_ce> is never used or assigned.
WARNING:Xst:1780 - Signal <ino_updown> is never used or assigned.
Found finite state machine <FSM_0> for signal <CurrState_Sreg0>.
-----------------------------------------------------------------------
| States | 9 |
| Transitions | 30 |
| Inputs | 2 |
| Outputs | 2 |
| Reset type | synchronous |
| Encoding | automatic |
| State register | d flip-flops |
-----------------------------------------------------------------------
Summary:
inferred 1 Finite State Machine(s).
Unit <Decode> synthesized.
Synthesizing Unit <MISCouts>.
Related source file is c:\Projects\genosensor\2g\CPLDs\Core\U21\src/.\..\src\MISCouts.v.
Found 8-bit register for signal <MISCr>.
Unit <MISCouts> synthesized.
Synthesizing Unit <PWMcontrol>.
Related source file is c:\Projects\genosensor\2g\CPLDs\Core\U21\src/.\..\compile\PWMcontrol.v.
Unit <PWMcontrol> synthesized.
Synthesizing Unit <I2CAddress>.
Related source file is c:\Projects\genosensor\2g\CPLDs\Core\U21\src/.\..\src\I2CAddress.v.
Found 8-bit tristate buffer for signal <outDATA>.
Summary:
inferred 8 Tristate(s).
Unit <I2CAddress> synthesized.
Synthesizing Unit <Lswitch>.
Related source file is c:\Projects\genosensor\2g\CPLDs\Core\U21\src/.\..\src\Lswitch.v.
WARNING:Xst:647 - Input <DCORIFGr> is never used.
WARNING:Xst:647 - Input <inDATA<7:5>> is never used.
WARNING:Xst:647 - Input <inDATA<3:0>> is never used.
Found 8-bit tristate buffer for signal <outDATA>.
Found 1-bit register for signal <DCORIFG>.
Found 1-bit register for signal <fBRK0r>.
Found 1-bit register for signal <fBRK1r>.
Summary:
inferred 8 Tristate(s).
Unit <Lswitch> synthesized.
Synthesizing Unit <PWRreg>.
Related source file is c:\Projects\genosensor\2g\CPLDs\Core\U21\src/.\..\src\PWRreg.v.
Found 8-bit tristate buffer for signal <outDATA>.
Found 8-bit register for signal <ctrlr>.
Found 1-bit register for signal <DCORIFG>.
Found 8-bit register for signal <Flgreg>.
Found 7 1-bit 2-to-1 multiplexers.
Summary:
inferred 8 Tristate(s).
Unit <PWRreg> synthesized.
Synthesizing Unit <Interrupt>.
Related source file is c:\Projects\genosensor\2g\CPLDs\Core\U21\src/.\..\src\Interrupt.v.
Found 8-bit register for signal <DCORIE>.
Unit <Interrupt> synthesized.
Synthesizing Unit <Interface>.
Related source file is c:\Projects\genosensor\2g\CPLDs\Core\U21\src/.\..\src\Interface.v.
Found 8-bit tristate buffer for signal <AD>.
Found 8-bit comparator lessequal for signal <$n0006> created at line 95.
Found 8-bit comparator lessequal for signal <$n0007> created at line 95.
Found 8-bit adder for signal <$n0011> created at line 95.
Found 8-bit register for signal <ADDR_reg>.
Found 1-bit register for signal <ASedge>.
Found 1-bit register for signal <AutoInc>.
Found 1-bit register for signal <WRRDedge>.
Summary:
inferred 3 D-type flip-flop(s).
inferred 1 Adder/Subtracter(s).
inferred 2 Comparator(s).
inferred 8 Tristate(s).
Unit <Interface> synthesized.
Synthesizing Unit <U21AddDecode>.
Related source file is c:\Projects\genosensor\2g\CPLDs\Core\U21\src/.\..\src\U21AddDecode.v.
WARNING:Xst:647 - Input <AS> is never used.
Unit <U21AddDecode> synthesized.
Synthesizing Unit <I2Cfix>.
Related source file is c:\Projects\genosensor\2g\CPLDs\Core\U21\src/.\..\compile\I2Cfix.v.
Unit <I2Cfix> synthesized.
Synthesizing Unit <Servos>.
Related source file is c:\Projects\genosensor\2g\CPLDs\Core\U21\src/.\..\compile\Servos.v.
Unit <Servos> synthesized.
Synthesizing Unit <U21>.
Related source file is c:\Projects\genosensor\2g\CPLDs\Core\U21\src/.\..\compile\U21.v.
Unit <U21> synthesized.
=========================================================================
HDL Synthesis Report
Macro Statistics
# FSMs : 2
# Registers : 41
6-bit register : 1
1-bit register : 32
24-bit register : 1
8-bit register : 5
16-bit register : 2
# Counters : 2
24-bit updown counter : 2
# Multiplexers : 8
2-to-1 multiplexer : 8
# Tristates : 22
1-bit tristate buffer : 17
8-bit tristate buffer : 5
# Adders/Subtractors : 3
3-bit adder : 1
6-bit addsub : 1
8-bit adder : 1
# Comparators : 2
8-bit comparator lessequal : 2
=========================================================================
=========================================================================
* Advanced HDL Synthesis *
=========================================================================
Selecting encoding for FSM_0 ...
Encoding for FSM_0 is Sequential flip-flop = D
=========================================================================
* Low Level Synthesis *
=========================================================================
WARNING:Xst:1348 - Unit Interface is merged (output interface has tristates)
WARNING:Xst:1348 - Unit BitCounter is merged (output interface has tristates)
WARNING:Xst:1348 - Unit I2Cfix is merged (output interface has tristates)
Optimizing unit <U21> ...
implementation constraint: KEEP : U2_Enable_AD
Optimizing unit <U21AddDecode> ...
Optimizing unit <PWMtranslator> ...
Optimizing unit <Lswitch> ...
Optimizing unit <I2CAddress> ...
Optimizing unit <PWMcontrol> ...
Optimizing unit <Decode> ...
Optimizing unit <NegDetect> ...
Optimizing unit <Interrupt> ...
Optimizing unit <PWRreg> ...
Optimizing unit <MISCouts> ...
Optimizing unit <Holdreg> ...
implementation constraint: KEEP : interDATA<7>
implementation constraint: KEEP : interDATA<6>
implementation constraint: KEEP : interDATA<5>
implementation constraint: KEEP : interDATA<4>
implementation constraint: KEEP : interDATA<3>
implementation constraint: KEEP : interDATA<2>
implementation constraint: KEEP : interDATA<1>
implementation constraint: KEEP : interDATA<0>
Optimizing unit <HomeConfig> ...
Optimizing unit <Counter> ...
Optimizing unit <Servos> ...
=========================================================================
* Final Report *
=========================================================================
Final Results
RTL Top Level Output File Name : U21.ngr
Top Level Output File Name : U21
Output Format : NGC
Optimization Goal : Area
Keep Hierarchy : YES
Target Technology : xcr3384xl-7TQ144
Macro Preserve : YES
XOR Preserve : YES
Clock Enable : YES
wysiwyg : NO
Design Statistics
# IOs : 82
Macro Statistics :
# Registers : 218
# 1-bit register : 218
# Tristates : 22
# 1-bit tristate buffer : 17
# 8-bit tristate buffer : 5
# Comparators : 2
# 8-bit comparator lessequal : 2
# Xors : 142
# 1-bit xor2 : 142
Cell Usage :
# BELS : 1453
# AND2 : 576
# AND3 : 16
# AND4 : 8
# GND : 9
# INV : 457
# OR2 : 246
# OR3 : 17
# OR4 : 1
# VCC : 1
# XOR2 : 122
# FlipFlops/Latches : 190
# FD : 27
# FDCE : 163
# Tri-States : 48
# BUFE : 48
# IO Buffers : 82
# IBUF : 44
# IOBUFE : 9
# OBUF : 29
=========================================================================
CPU : 3.02 / 4.63 s | Elapsed : 3.00 / 5.00 s
-->
Total memory usage is 58840 kilobytes
Synthesis finished with warnings.