/**********************************  dwarfcore.h  *****************************
 * $Source: /home/cvs/ESP/gen2/software/msp430/include/dwarfcore.h,v $
 *  Copyright (C) 2003 MBARI
 *
 *  MBARI Proprietary Information. All rights reserved.
 * $Id: dwarfcore.h,v 1.1 2004/02/27 01:37:38 brent Exp $
 *
 * This header documents the hardware interface between the
 * MSP430F1xx microcontroller and the "Dwarf Core" board,
 * particularly the registers in the board's CPLD.
 *
 *****************************************************************************/

#ifndef dwarfcore_h

#include "msp430x16x.h" //register and I/O definitions

// Dwarf Core CPLD Registers

/*
  Interrupt Enable and Flag Registers
*/
#define DCORIE       0    //write only interrupt enable mask [active high]
#define DCORIFG      1    //read/write interrupt flag mask [active high]
//clear bits in DCORIFG clear the interrupt sources, one bits set them

#define DCORBUSIE    0x01   //interrupt from dwarf daughter card
#define DCOR0PWRIE   0x02   //Ch 0 encoder power fault
#define DCOR1PWRIE   0x04   //Ch 1 encoder power fault

//The following two interrupts are not latches and cannot be set or cleared.
//They are merely the logical combination of the appropriate pair of latched
//status bits in the DCORLIMITS register.  
#define DCORHOMEDIE  0x08   //either channel homed
#define DCORCRASHIE  0x10   //either channel hit limit switch

#define DCOR0THRESIE 0x20   //ch 0 latched threshold
#define DCOR1THRESIE 0x40   //ch 1 latched threshold
#define DCORI2CCLIE  0x80   //I2C clock being held due to zero count


/*
   Read only limit status registers
*/
#define DCORLIMITS  2
#define DCOR0RLS    0x01    //ch 0 reverse limit [latched] (active low)
#define DCOR0FLS    0x02    //ch 0 forward limit [latched] (active low)
#define DCOR0ATHOME 0x04    //ch 0 home switch [not latched] (active low)
#define DCOR0HOMED  0x08    //ch 0 home found [latched] (active high)
#define DCOR1RLS    0x10    //ch 1 reverse limit [latched] (active low)
#define DCOR1FLS    0x20    //ch 1 forward limit [latched] (active low)
#define DCOR1ATHOME 0x40    //ch 1 home switch [not latched] (active low)
#define DCOR1HOMED  0x80    //ch 1 home found [latched] (active high)
// DCORxHOMED is set after the channel's encoder count has been cleared.
// a channel's encoder count cannot be cleared while DCORxHOMED is set.


/*
  Write Only Encoder Control register
*/
#define DCORENCCTL  3
#define DCOR0HMEDGE 0x01   //ch0 set home flag on rising=1/falling=0 edge
#define DCOR0HMON   0x02   //ch0 enable home flag counter reset [active high]
#define DCOR0HMCLR  0x04   //ch0 clear latched homed flag [active low]
#define DCOR0TREDGE 0x08   //ch0 latch threshold on rising=1/falling=0 edge
#define DCOR1HMEDGE 0x10   //ch1 set home flag on rising=1/falling=0 edge
#define DCOR1HMON   0x20   //ch1 enable home flag counter reset [active high]
#define DCOR1HMCLR  0x40   //ch1 clear home flag [active low]
#define DCOR1TREDGE 0x08   //ch1 latch threshold on rising=1/falling=0 edge


/* 
  Read only current encoder count registers.  
*/
#define DCOR0CNTLOW  4
#define DCOR0CNTMID  5
#define DCOR0CNTHIGH 6
#define DCOR1CNTLOW  7
#define DCOR1CNTMID  8
#define DCOR1CNTHIGH 9

/*
  Read only threshold latched encoder count registers
   Note that THRESHIGH is not latched and must be derived from the current count
   Once a channel's threshold is latched, it cannot be latched again
   until the corresponding interrupt flag bit in DCORIFG is cleared 
*/
#define DCOR0THRESLOW  10
#define DCOR0THRESMID  11
#define DCOR1THRESLOW  12
#define DCOR1THRESMID  13



/*
  Read/Write Encoder Power Fault/Control register
    Power Fault inputs are active low
    Power Control outputs are active high
*/
#define DCORENCPWR  14
#define DCOR0HOME3  0x01    //ch0 3.3V Power fault/control
#define DCOR0HOME5  0x02    //ch0 5V Power fault/control
#define DCOR0ENC3   0x04    //ch0 3.3V Power fault/control
#define DCOR0ENC5   0x08    //ch0 5V Power fault/control
#define DCOR1HOME3  0x10    //ch1 3.3V Power fault/control
#define DCOR1HOME5  0x20    //ch1 5V Power fault/control
#define DCOR1ENC3   0x40    //ch1 3.3V Power fault/control
#define DCOR1ENC5   0x80    //ch1 5V Power fault/control
 


/*
  Read Only configuration switch register
*/
#define DCORCONFIG   15   //closed switches=1, unused bits=0


/*
  Write Only Miscellenous outputs
*/
#define DCOROUT      15
#define DCORLED1     0x01  //status LED output [active low]
#define DCORLED1     0x02  //status LED output [active low]
#define DCORLED1     0x04  //status LED output [active low]
#define DCORLED1     0x08  //status LED output [active low]
#define DCORLED1     0x10  //status LED output [active low]
#define DCOR0ENCDIR  0x20  //ch0 encoder "sense" or quadrature phase 
#define DCOR1ENCDIR  0x40  //ch1 encoder "sense" or quadrature phase 
#define DCORMOTORPWR 0x80  //motor power enable for both channels [active high]


/*
  Read Only I2C Clock counter register
*/
#define DCORI2CCL   3      //6-bit counter.  uppper bits are undefined.


// Direct (non-registered) I/O bits
// PWM control is on port 4 (TIMER B)
#define DCORPWMOUT  P4OUT
#define DCORPWMSEL  P4SEL
#define DCOR0PWM    0x01 
#define DCOR1PWM    0x02
#define DCOR2PWM    0x04
#define DCOR3PWM    0x08
#define DCOR4PWM    0x10
#define DCOR5PWM    0x20
#define DCOR6PWM    0x40
#define DCORPWMCLK  0x80    //external PWM clock input

// Motor PWM direction control
#define DCORMOTOROUT  P5OUT
#define DCOR0DIR    0x01    //forward=?, backward=?
#define DCOR0BRAKE  0x02    //active ??, overrides DIR
#define DCOR1DIR    0x04    //forward=?, backward=?
#define DCOR1BRAKE  0x08    //active ??, overrides DIR

// I2C Clock Counter
#define DCORI2COUT  P2OUT
#define DCORI2CHOLD 0x01    //hold I2C counter at 9  [active high]
#define DCORI2CINC  0x02    //increment count by 9 on falling edge

// RS232 handshakes for USART1
#define DCORCTSOUT  P5OUT
#define DCORCTS     0x80    //CTS output [active low]

#define DCORRTSIN   P2IN
#define DCORRTSDIR  P2DIR
#define DCORRTSIES  P2IES
#define DCORRTSIE   P2IE
#define DCORRTSIFG  P2IFG
#define DCORRTS     0x04    //RTS input [active low]
#define DCORRxD     0x08    //RxD in connected to port 3.7 [break is active low]

#endif
