//--------------------------------------------------------------------------------------------------
//
// Title       : U21AddDecode
// Design      : U21
// Author      : mbari###
// Company     : MBARI
//
//-------------------------------------------------------------------------------------------------
//
// File        : C:\Projects\genosensor\2g\CPLDs\Core\U21\src\U21AddDecode.v
// Generated   : Fri Feb 27 07:29:51 2004
// From        : interface description file
// By          : Itf2Vhdl ver. 1.20
//
//-------------------------------------------------------------------------------------------------
//
// Description : 
//
//-------------------------------------------------------------------------------------------------
`timescale 1ps / 1ps

`include "U21AddressMap.v"

//{{ Section below this comment is automatically maintained
//   and may be overwritten
//{module {U21AddDecode}}
module U21AddDecode ( DCOR0CNTLOWr ,DCOR0THRESLOWr ,DCOR1CNTLOWr ,DCOR1THRESLOWr ,DCORENCPWRr ,WR ,DCOR0CNTMIDr ,DCOR0THRESMIDr ,DCOR1CNTMIDr ,DCOR1THRESMIDr ,DCORLIMITSr ,DCORIEw ,DCORENCPWRw ,DCOR0CNTHIGHr ,DCORCONFIGr ,DCORIFGr ,DCOR1CNTHIGHr ,AS ,DCORIFGw ,RD ,DCOROUTw ,DCORENCCTLw ,ADDR ,DCORI2CCNTr );

input WR ;
wire WR ;
input [7:0] ADDR ;
wire [7:0] ADDR ;
input AS ;
wire AS ;
input RD ;
wire RD ;

output DCOR0CNTLOWr ;
wire DCOR0CNTLOWr ;
output DCOR0THRESLOWr ;
wire DCOR0THRESLOWr ;
output DCOR1CNTLOWr ;
wire DCOR1CNTLOWr ;
output DCOR1THRESLOWr ;
wire DCOR1THRESLOWr ;
output DCORENCPWRr ;
wire DCORENCPWRr ;
output DCOR0CNTMIDr ;
wire DCOR0CNTMIDr ;
output DCOR1CNTMIDr ;
wire DCOR1CNTMIDr ;
output DCOR0THRESMIDr ;
wire DCOR0THRESMIDr ;
output DCOR1THRESMIDr ;
wire DCOR1THRESMIDr ;
output DCORLIMITSr ;
wire DCORLIMITSr ;
output DCORIEw ;
wire DCORIEw ;
output DCORENCPWRw ;
wire DCORENCPWRw ;
output DCOR0CNTHIGHr ;
wire DCOR0CNTHIGHr ;
output DCORIFGr ;
wire DCORIFGr ;
output DCOR1CNTHIGHr ;
wire DCOR1CNTHIGHr ;
output DCORCONFIGr ;
wire DCORCONFIGr ;
output DCORIFGw ;
wire DCORIFGw ;
output DCOROUTw ;
wire DCOROUTw ;
output DCORENCCTLw ;
wire DCORENCCTLw ;
output DCORI2CCNTr ;
wire DCORI2CCNTr ;

//}} End of automatically maintained section

// -- Enter your statements here -- //			   

//how does this thing work...
//we will no longer consider the AS in the qualification of the select assign its state is used 
//by the interface unit to autoincrement

`define READ 1
`define WRITE 0

function Select;
input [7:0] Address;
input [7:0] Location;
input RD, WR;
input RorW;
 Select =  (RorW == `WRITE) ? (RD & !WR & (ADDR == Location)) :  (!RD & WR & (ADDR ==  Location)) ;
endfunction								   

//s-ynthesis attribute KEEP of DCORr is TRUE;
//assign  DCORr = Select(ADDR, `DCOR1, RD, WR, `READ);

//synthesis attribute KEEP of DCORIEw is TRUE;
assign  DCORIEw = Select(ADDR, `DCORIE, RD, WR, `WRITE);

//synthesis attribute KEEP of DCORIFGw is TRUE;
assign  DCORIFGw = Select(ADDR, `DCORIFG, RD, WR, `WRITE);

//synthesis attribute KEEP of DCORIFGr is TRUE;
assign  DCORIFGr = Select(ADDR, `DCORIFG, RD, WR, `READ);

//synthesis attribute KEEP of DCORLIMITSr is TRUE;
assign  DCORLIMITSr = Select(ADDR, `DCORLIMITS, RD, WR, `READ);

//synthesis attribute KEEP of DCORENCCTLw is TRUE;
assign  DCORENCCTLw = Select(ADDR, `DCORENCCTL, RD, WR, `WRITE);

//synthesis attribute KEEP of DCOR0CNTLOWr is TRUE;
assign  DCOR0CNTLOWr = Select(ADDR, `DCOR0CNTLOW, RD, WR, `READ);

//synthesis attribute KEEP of DCOR0CNTMIDr is TRUE;
assign  DCOR0CNTMIDr = Select(ADDR, `DCOR0CNTMID, RD, WR, `READ);

//synthesis attribute KEEP of DCOR0CNTHIGHr is TRUE;
assign  DCOR0CNTHIGHr = Select(ADDR, `DCOR0CNTHIGH, RD, WR, `READ);

//synthesis attribute KEEP of DCOR1CNTLOWr is TRUE;
assign  DCOR1CNTLOWr = Select(ADDR, `DCOR1CNTLOW, RD, WR, `READ);

//synthesis attribute KEEP of DCOR1CNTMIDr is TRUE;
assign  DCOR1CNTMIDr = Select(ADDR, `DCOR1CNTMID, RD, WR, `READ);

//synthesis attribute KEEP of DCOR1CNTHIGHr is TRUE;
assign  DCOR1CNTHIGHr = Select(ADDR, `DCOR1CNTHIGH, RD, WR, `READ);

//synthesis attribute KEEP of DCOR0THRESLOWr is TRUE;
assign  DCOR0THRESLOWr = Select(ADDR, `DCOR0THRESLOW, RD, WR, `READ);

//synthesis attribute KEEP of DCOR0THRESMIDr is TRUE;
assign  DCOR0THRESMIDr = Select(ADDR, `DCOR0THRESMID, RD, WR, `READ);

//synthesis attribute KEEP of DCOR1THRESLOWr is TRUE;
assign  DCOR1THRESLOWr = Select(ADDR, `DCOR1THRESLOW, RD, WR, `READ);

//synthesis attribute KEEP of DCOR1THRESMIDr is TRUE;
assign  DCOR1THRESMIDr = Select(ADDR, `DCOR1THRESMID, RD, WR, `READ);

//synthesis attribute KEEP of DCORENCPWRr is TRUE;
assign  DCORENCPWRr = Select(ADDR, `DCORENCPWR, RD, WR, `READ);

//synthesis attribute KEEP of DCORENCPWRw is TRUE;
assign  DCORENCPWRw = Select(ADDR, `DCORENCPWR, RD, WR, `WRITE);

//synthesis attribute KEEP of DCORCONFIGr is TRUE;
assign  DCORCONFIGr = Select(ADDR, `DCORCONFIG, RD, WR, `READ);

//synthesis attribute KEEP of DCOROUTw is TRUE;
assign  DCOROUTw = Select(ADDR, `DCOROUT, RD, WR, `WRITE);

//synthesis attribute KEEP of DCORI2CCNTr is TRUE;
assign  DCORI2CCNTr = Select(ADDR, `DCORI2CCNT, RD, WR, `READ);

endmodule
