//--------------------------------------------------------------------------------------------------
//
// Title       : HomeConfig
// Design      : U4
// Author      : mbari###
// Company     : MBARI
//
//-------------------------------------------------------------------------------------------------
//
// File        : c:\Projects\genosensor\2g\CPLDs\Core\U4\src\HomeConfig.v
// Generated   : Thu Dec 18 09:50:41 2003
// From        : interface description file
// By          : Itf2Vhdl ver. 1.20
//
//-------------------------------------------------------------------------------------------------
//
// Description : 
//
//-------------------------------------------------------------------------------------------------
`timescale 1ps / 1ps

//{{ Section below this comment is automatically maintained
//   and may be overwritten
//{module {HomeConfig}}
module HomeConfig ( Tfound0 ,Tfound1 ,DCOR0THRESLOWr ,DCOR1THRESLOWr ,Reset ,Channel0 ,Channel1 ,DCOR0THRESMIDr ,DCOR1THRESMIDr ,Sclk ,sense0 ,sense1 ,DCORIFGr ,Zero0 ,inDATA ,Zero1 ,outDATA ,Hfound0 ,Hfound1 ,DCORIFGw ,MotorIn0 ,Home_Encoder0 ,DCORENCCTLw ,MotorIn1 ,Home_Encoder1 );

input DCORIFGr ;
wire DCORIFGr ;
input [7:0] inDATA ;
wire [7:0] inDATA ;
input DCOR0THRESLOWr ;
wire DCOR0THRESLOWr ;
input DCOR1THRESLOWr ;
wire DCOR1THRESLOWr ;
input Reset ;
wire Reset ;
input DCORIFGw ;
wire DCORIFGw ;
input DCORENCCTLw ;
wire DCORENCCTLw ;
input Home_Encoder0 ;
wire Home_Encoder0 ;
input MotorIn0 ;
wire MotorIn0 ;
input [15:0] Channel0 ;
wire [15:0] Channel0 ;
input Home_Encoder1 ;
wire Home_Encoder1 ;
input MotorIn1 ;
wire MotorIn1 ;
input [15:0] Channel1 ;
wire [15:0] Channel1 ;
input DCOR0THRESMIDr ;
wire DCOR0THRESMIDr ;
input DCOR1THRESMIDr ;
wire DCOR1THRESMIDr ;
input Sclk ;
wire Sclk ;

output Tfound0 ;
wire Tfound0 ;
output Zero0 ;
wire Zero0 ;
output Tfound1 ;
wire Tfound1 ;
output Zero1 ;
wire Zero1 ;
output [7:0] outDATA ;
wire [7:0] outDATA ;
output Hfound0 ;
wire Hfound0 ;
output Hfound1 ;
wire Hfound1 ;
output sense0 ;
wire sense0 ;
output sense1 ;
wire sense1 ;

//}} End of automatically maintained section

// -- Enter your statements here -- //

//Rising Falling select
reg RF1r;			   
//Enable homing
reg E1r;	   
//Rising Falling select
reg RF0r;
//Enable homing
reg E0r;   	   
//Rising falling of latch
reg LatchEdge0r;
reg LatchEdge1r;		 
//Encoder direction
reg sense0r;
reg sense1r; 	   

//Used to detect edge
reg HE0stater;
reg HE0statelastr;
reg HE1stater;
reg HE1statelastr;

//the homed registers in the DCORIFGr/w
reg Hfound0r;
reg Hfound1r;
//used to tell counter to reset due to home
reg Zero0r;
reg Zero1r;

//the latch register in the DCORIFGr/w
reg Tfound0r;
reg Tfound1r;		   

//these are the latch registers to hold the encoder counter value
reg [15:0] Latch0r;
reg [15:0] Latch1r;	

//used to detect edges on the latch inputs
reg InEdge0r;
reg InEdge1r;  							  


//reg LatchIt0r;
//reg LatchIt1r;

assign Zero0 = Zero0r;
assign Zero1 = Zero1r;



assign sense0 = sense0r;
assign sense1 = sense1r;

assign Hfound1 = Hfound1r;
assign Hfound0 = Hfound0r;
assign Tfound0 = Tfound0r;
assign Tfound1 = Tfound1r;

//(DCORIFGr) ? {4'bz, Hfound2, Hfound1, 2'bz}:
assign outDATA = (DCOR0THRESLOWr) ? Latch0r[7:0] :
				 (DCOR0THRESMIDr) ? Latch0r[15:8] : 
				 (DCOR1THRESLOWr) ? Latch1r[7:0] :
				 (DCOR1THRESMIDr) ? Latch1r[15:8] : 
				 8'bz;

always @ (negedge Sclk)
	begin
		HE0stater <= Home_Encoder0;
		HE0statelastr <= HE0stater;
		
		HE1stater <= Home_Encoder1;
		HE1statelastr <= HE1stater;
		
		InEdge0r <= MotorIn0;
		InEdge1r <= MotorIn1;
		
		if (Reset) 
			begin
				{sense1r, LatchEdge1r, E1r, RF1r, sense0r, LatchEdge0r,E0r, RF0r} <= 8'b0;
				Latch0r <= 16'b0;
				Latch1r <= 16'b0;
			end	
		else if (DCORENCCTLw) {sense1r, LatchEdge1r, E1r, RF1r, sense0r, LatchEdge0r,E0r, RF0r} <= {inDATA[7:0]};	
		else if (DCORIFGw) {Tfound1r,Tfound0r,Hfound1r,Hfound0r} <= {inDATA[6],inDATA[5],inDATA[3],inDATA[2]};
		else 
			begin
				case ({RF0r,HE0stater,HE0statelastr,Hfound0})
					4'b0010,
					4'b1100:begin
								Zero0r <= E0r;
								Hfound0r <= 1'b1;
							end					
					default 
						begin
							Zero0r <= 1'b0;
							Hfound0r <= Hfound0r;
						end
				endcase	
				case ({E1r,RF1r,HE1stater,HE1statelastr,Hfound1})
					5'b10010,
					5'b11100:begin
								Zero1r <= E1r;
								Hfound1r <= 1'b1;
							end					
					default 
						begin
							Zero1r <= 1'b0;
							Hfound1r <= Hfound1r;
						end
				endcase	
				case ({Tfound0,InEdge0r,MotorIn0,LatchEdge0r})
					4'b0100,
					4'b0011:begin
								Tfound0r <= 1'b1;
								Latch0r <= Channel0;
							end					
					default 
						begin
							Tfound0r <= Tfound0r;
							Latch0r <= Latch0r;
						end
				endcase	 
				case ({Tfound1,InEdge1r,MotorIn1,LatchEdge1r})
					4'b0100,
					4'b0011:begin
								Tfound1r <= 1'b1;
								Latch1r <= Channel1;
							end					
					default 
						begin
							Tfound1r <= Tfound1r;	
							Latch1r <= Channel1;
						end
				endcase	

			end
	end
endmodule
