//--------------------------------------------------------------------------------------------------
//
// Title       : EncPwr
// Design      : U21
// Author      : mbari###
// Company     : MBARI
//
//-------------------------------------------------------------------------------------------------
//
// File        : C:\Projects\genosensor\2g\CPLDs\Core\U21\src\EncPwr.v
// Generated   : Fri Feb 27 13:35:17 2004
// From        : interface description file
// By          : Itf2Vhdl ver. 1.20
//
//-------------------------------------------------------------------------------------------------
//
// Description : 
//
//-------------------------------------------------------------------------------------------------
`timescale 1ps / 1ps

//{{ Section below this comment is automatically maintained
//   and may be overwritten
//{module {EncPwr}}
module EncPwr ( Enc133ctrl ,Enc233ctrl ,Reset ,Home15ctrl ,Home25ctrl ,Enc133FLG ,Mclk ,Enc233FLG ,Home15FLG ,DCORENCPWRr ,Home25FLG ,DCORENCPWRw ,Enc15ctrl ,inDATA ,outDATA ,Enc25ctrl ,enc15FLG ,Home133ctrl ,Enc25FLG ,Home233ctrl ,Home133FLG ,Home233FLG );

input Reset ;
wire Reset ;
input enc15FLG ;
wire enc15FLG ;
input Enc133FLG ;
wire Enc133FLG ;
input Enc25FLG ;
wire Enc25FLG ;
input Mclk ;
wire Mclk ;
input Enc233FLG ;
wire Enc233FLG ;
input Home15FLG ;
wire Home15FLG ;
input DCORENCPWRr ;
wire DCORENCPWRr ;
input Home25FLG ;
wire Home25FLG ;
input Home133FLG ;
wire Home133FLG ;
input Home233FLG ;
wire Home233FLG ;
input DCORENCPWRw ;
wire DCORENCPWRw ;

output Enc15ctrl ;
wire Enc15ctrl ;
output [7:0] inDATA ;
wire [7:0] inDATA ;
output Enc133ctrl ;
wire Enc133ctrl ;
output Enc25ctrl ;
wire Enc25ctrl ;
output [7:0] outDATA ;
wire [7:0] outDATA ;
output Enc233ctrl ;
wire Enc233ctrl ;
output Home15ctrl ;
wire Home15ctrl ;
output Home133ctrl ;
wire Home133ctrl ;
output Home25ctrl ;
wire Home25ctrl ;
output Home233ctrl ;
wire Home233ctrl ;

//}} End of automatically maintained section

// -- Enter your statements here -- //
reg [7:0] ctrlr;

assign outDATA =  ? {Enc5FLG, Enc33FLG, Home5FLG, Home33FLG} : 4'bz;
assign Enc15ctrl = !ctrlr[3] | (ctrlr[2] & ctrlr[3]);	   //this is reguired since the register power up low
assign Enc133ctrl = !ctrlr[2] | (ctrlr[2] & ctrlr[3]);     //this will cause the output to begin high and power off!
assign Home15ctrl = !ctrlr[1] | (ctrlr[1] & ctrlr[0]);    //this forces both off if both are tried to turn on
assign Home133ctrl = !ctrlr[0] | (ctrlr[1] & ctrlr[0]);   //not a good condition if both are on at the same time!

always @ (posedge Mclk or posedge Reset)//added to make reset async to shut off when reset high
	begin
		if (Reset) ctrlr <= 4'b0;
		else if (WRslct) ctrlr <= {inDATA[3], inDATA[2], inDATA[1], inDATA[0]};
	end
endmodule
