//--------------------------------------------------------------------------------------------------
//
// Title       : U4 TestBench
// Design      : U4
// Author      : mbari###
// Company     : MBARI
//
//-------------------------------------------------------------------------------------------------
//
// File        : c:\Projects\genosensor\2g\CPLDs\Core\U4\compile\U4_TB_tsim.v
// Generated   : Thu Feb 26 13:00:17 2004
// From        : c:\Projects\genosensor\2g\CPLDs\Core\U4\src\U4_TB_tsim.bde
// By          : Bde2Verilog ver. 2.01
//
//-------------------------------------------------------------------------------------------------
//
// Description : 
//
//-------------------------------------------------------------------------------------------------

// synopsys translate_off
`ifdef _VCP
`else
`define library(a,b)
`endif
// synopsys translate_on


// ---------- Design Unit Header ---------- //
`timescale 1ps / 1ps

module U4_TB_tsim (Brake1,Brake2,DIR1,DIR2,Enc133FLG,Enc15FLG,Enc233FLG,Enc25FLG,FLS1,FLS2,
Home1,Home133FLG,Home15FLG,Home2,Home233FLG,Home25FLG,PWM1,PWM2,PhaseA_Encoder1,PhaseA_Encoder2,
PhaseB_Encoder1,PhaseB_Encoder2,RLS1,RLS2,Reset,Enc133ctrl,Enc15ctrl,Enc233ctrl,Enc25ctrl,Home133ctrl,
Home15ctrl,Home233ctrl,Home25ctrl,INT,LED1,LED2,LED3,LED4,LED5,MTRpwr,
MTRpwrn,PAH1,PAH2,PAL1,PAL2,PBH1,PBH2,PBL1,PBL2) ;

// ------------ Port declarations --------- //
input Brake1;
wire Brake1;
input Brake2;
wire Brake2;
input DIR1;
wire DIR1;
input DIR2;
wire DIR2;
input Enc133FLG;
wire Enc133FLG;
input Enc15FLG;
wire Enc15FLG;
input Enc233FLG;
wire Enc233FLG;
input Enc25FLG;
wire Enc25FLG;
input FLS1;
wire FLS1;
input FLS2;
wire FLS2;
input Home1;
wire Home1;
input Home133FLG;
wire Home133FLG;
input Home15FLG;
wire Home15FLG;
input Home2;
wire Home2;
input Home233FLG;
wire Home233FLG;
input Home25FLG;
wire Home25FLG;
input PWM1;
wire PWM1;
input PWM2;
wire PWM2;
input PhaseA_Encoder1;
wire PhaseA_Encoder1;
input PhaseA_Encoder2;
wire PhaseA_Encoder2;
input PhaseB_Encoder1;
wire PhaseB_Encoder1;
input PhaseB_Encoder2;
wire PhaseB_Encoder2;
input RLS1;
wire RLS1;
input RLS2;
wire RLS2;
input Reset;
wire Reset;
output Enc133ctrl;
wire Enc133ctrl;
output Enc15ctrl;
wire Enc15ctrl;
output Enc233ctrl;
wire Enc233ctrl;
output Enc25ctrl;
wire Enc25ctrl;
output Home133ctrl;
wire Home133ctrl;
output Home15ctrl;
wire Home15ctrl;
output Home233ctrl;
wire Home233ctrl;
output Home25ctrl;
wire Home25ctrl;
output INT;
wire INT;
output LED1;
wire LED1;
output LED2;
wire LED2;
output LED3;
wire LED3;
output LED4;
wire LED4;
output LED5;
wire LED5;
output MTRpwr;
wire MTRpwr;
output MTRpwrn;
wire MTRpwrn;
output PAH1;
wire PAH1;
output PAH2;
wire PAH2;
output PAL1;
wire PAL1;
output PAL2;
wire PAL2;
output PBH1;
wire PBH1;
output PBH2;
wire PBH2;
output PBL1;
wire PBL1;
output PBL2;
wire PBL2;

// ----------------- Constants ------------ //
parameter DANGLING_INPUT_CONSTANT = 1'bZ;

// ----------- Signal declarations -------- //
wire AS;
wire Mclk;
wire RD;
wire WR;
wire [7:0] AD;

// ---- Declaration for Dangling inputs ----//
wire Dangling_Input_Signal = DANGLING_INPUT_CONSTANT;

// -------- Component instantiations -------//

U4 U1
(
	.AD(AD),
	.AS(AS),
	.Brake1(Brake1),
	.Brake2(Brake2),
	.DIR1(DIR1),
	.DIR2(DIR2),
	.Enc133FLG(Enc133FLG),
	.Enc133ctrl(Enc133ctrl),
	.Enc15FLG(Enc15FLG),
	.Enc15ctrl(Enc15ctrl),
	.Enc233FLG(Enc233FLG),
	.Enc233ctrl(Enc233ctrl),
	.Enc25FLG(Enc25FLG),
	.Enc25ctrl(Enc25ctrl),
	.FLS1(FLS1),
	.FLS2(FLS2),
	.Home1(Home1),
	.Home133FLG(Home133FLG),
	.Home133ctrl(Home133ctrl),
	.Home15FLG(Home15FLG),
	.Home15ctrl(Home15ctrl),
	.Home2(Home2),
	.Home233FLG(Home233FLG),
	.Home233ctrl(Home233ctrl),
	.Home25FLG(Home25FLG),
	.Home25ctrl(Home25ctrl),
	.I2CS({6{Dangling_Input_Signal}}),
	.INT(INT),
	.LED1(LED1),
	.LED2(LED2),
	.LED3(LED3),
	.LED4(LED4),
	.LED5(LED5),
	.MTRpwr(MTRpwr),
	.MTRpwrn(MTRpwrn),
	.Mclk(Mclk),
	.PAH1(PAH1),
	.PAH2(PAH2),
	.PAL1(PAL1),
	.PAL2(PAL2),
	.PBH1(PBH1),
	.PBH2(PBH2),
	.PBL1(PBL1),
	.PBL2(PBL2),
	.PWM1(PWM1),
	.PWM2(PWM2),
	.PhaseA_Encoder1(PhaseA_Encoder1),
	.PhaseA_Encoder2(PhaseA_Encoder2),
	.PhaseB_Encoder1(PhaseB_Encoder1),
	.PhaseB_Encoder2(PhaseB_Encoder2),
	.RD(RD),
	.RLS1(RLS1),
	.RLS2(RLS2),
	.Reset(Reset),
	.WR(WR)
);



MSP U2
(
	.AD(AD),
	.AS(AS),
	.Mclk(Mclk),
	.RD(RD),
	.WR(WR)
);



endmodule 
