//--------------------------------------------------------------------------------------------------
//
// Title       : I2Cfix
// Design      : U21
// Author      : mbari###
// Company     : MBARI
//
//-------------------------------------------------------------------------------------------------
//
// File        : c:\Projects\genosensor\2g\CPLDs\Core\U21\compile\i2cfix.v
// Generated   : Thu Mar  4 13:43:01 2004
// From        : c:\projects\genosensor\2g\cplds\core\u21\src\i2cfix.bde
// By          : Bde2Verilog ver. 2.01
//
//-------------------------------------------------------------------------------------------------
//
// Description : 
//
//-------------------------------------------------------------------------------------------------

// synopsys translate_off
`ifdef _VCP
`else
`define library(a,b)
`endif
// synopsys translate_on


// ---------- Design Unit Header ---------- //
`timescale 1ns / 1ns

module I2Cfix (DCORI2CCNTr,Inc,Mclk,SCLreset,SCLint,outDATA,SCL) ;

// ------------ Port declarations --------- //
input DCORI2CCNTr;
wire DCORI2CCNTr;
input Inc;
wire Inc;
input Mclk;
wire Mclk;
input SCLreset;
wire SCLreset;
output SCLint;
wire SCLint;
output [7:0] outDATA;
wire [7:0] outDATA;
inout SCL;
wire SCL;

// ----------- Signal declarations -------- //
wire Incdetect;
wire SCLdetect;

// -------- Component instantiations -------//

NegDetect U1
(
	.Line(Inc),
	.Mclk(Mclk),
	.Ndetect(Incdetect)
);



NegDetect U2
(
	.Line(SCL),
	.Mclk(Mclk),
	.Ndetect(SCLdetect)
);



BitCounter U3
(
	.DCORI2CCNTr(DCORI2CCNTr),
	.DriveSCL(SCL),
	.Mclk(Mclk),
	.NegInc(Incdetect),
	.NegSCL(SCLdetect),
	.SCLint(SCLint),
	.SCLreset(SCLreset),
	.outDATA(outDATA)
);



endmodule 
