## Implement Log

Created on 14:21:28 03/04/04

InputFile = c:/Projects/genosensor/2g/CPLDs/Core/U21/implement/xie0.ini
Executing C:\Xilinx\bin\nt\ngdbuild.exe -p R3384XLTQ144-7 -sd "c:\Projects\genosensor\2g\CPLDs\Core\U21\synthesis" -sd "c:\Projects\genosensor\2g\CPLDs\Core\U21\compile" -sd "c:\Projects\genosensor\2g\CPLDs\Core\U21\src" -sd "C:\Program Files\Aldec\Active-HDL 6.2\vlib\XC9500\compile" -uc "U21.ucf" "U21.ngc" "U21.ngd"
c:\Projects\genosensor\2g\CPLDs\Core\U21\implement\ver0\rev0>set XILINX=C:\Xilinx
c:\Projects\genosensor\2g\CPLDs\Core\U21\implement\ver0\rev0>set PATH=C:\Xilinx\bin\nt
Release 6.1i - ngdbuild G.26
Copyright (c) 1995-2003 Xilinx, Inc. All rights reserved.
Command Line: ngdbuild -p R3384XLTQ144-7 -sd
c:\Projects\genosensor\2g\CPLDs\Core\U21\synthesis -sd
c:\Projects\genosensor\2g\CPLDs\Core\U21\compile -sd
c:\Projects\genosensor\2g\CPLDs\Core\U21\src -sd "C:\Program
Files\Aldec\Active-HDL 6.2\vlib\XC9500\compile" -uc U21.ucf U21.ngc U21.ngd
Reading NGO file
"c:/Projects/genosensor/2g/CPLDs/Core/U21/implement/ver0/rev0/U21.ngc" ...
Reading component libraries for design expansion...
Annotating constraints to design from file "U21.ucf" ...
Attached a PULLUP primitive to pad net Home033FLG
Attached a PULLUP primitive to pad net AS
Attached a PULLUP primitive to pad net Home05FLG
Attached a PULLUP primitive to pad net Home133FLG
Attached a PULLUP primitive to pad net Enc033FLG
Attached a PULLUP primitive to pad net Home15FLG
Attached a PULLUP primitive to pad net RD
Attached a PULLUP primitive to pad net Enc05FLG
Attached a PULLUP primitive to pad net Enc133FLG
Attached a PULLUP primitive to pad net WR
Attached a PULLUP primitive to pad net Enc15FLG
Checking timing specifications ...
Checking expanded design ...
NGDBUILD Design Results Summary:
Number of errors: 0
Number of warnings: 0
Total memory usage is 37476 kilobytes
Writing NGD file "U21.ngd" ...
Writing NGDBUILD log file "U21.bld"...
NGDBUILD done.
Executing C:\Xilinx\bin\nt\cpldfit.exe -p XCR3384XL-7-TQ144 -blkfanin 36 -inreg on -optimize density -inputs 32 -slew slow -loc on -nofbnand -init low -pterms 40 "U21.ngd"
c:\Projects\genosensor\2g\CPLDs\Core\U21\implement\ver0\rev0>set XILINX=C:\Xilinx
c:\Projects\genosensor\2g\CPLDs\Core\U21\implement\ver0\rev0>set PATH=C:\Xilinx\bin\nt
Release 6.1i - CPLD Optimizer/Partitioner G.26
Copyright (c) 1995-2003 Xilinx, Inc. All rights reserved.
Cpld:987 - An internal tristate buffer 'outDATA<4>\$WA2' is detected.
The logic is being translated to a mux implementation.
Cpld:987 - An internal tristate buffer 'outDATA<0>\$WA2' is detected.
The logic is being translated to a mux implementation.
Cpld:987 - An internal tristate buffer 'outDATA<5>\$WA1' is detected.
The logic is being translated to a mux implementation.
Cpld:987 - An internal tristate buffer 'outDATA<4>\$WA1' is detected.
The logic is being translated to a mux implementation.
Cpld:987 - An internal tristate buffer 'outDATA<3>\$WA1' is detected.
The logic is being translated to a mux implementation.
Cpld:987 - An internal tristate buffer 'outDATA<2>\$WA1' is detected.
The logic is being translated to a mux implementation.
Cpld:987 - An internal tristate buffer 'outDATA<1>\$WA1' is detected.
The logic is being translated to a mux implementation.
Cpld:987 - An internal tristate buffer 'outDATA<0>\$WA1' is detected.
The logic is being translated to a mux implementation.
Cpld:987 - An internal tristate buffer 'outDATA<6>\$WA2' is detected.
The logic is being translated to a mux implementation.
Cpld:987 - An internal tristate buffer 'outDATA<2>\$WA2' is detected.
The logic is being translated to a mux implementation.
Cpld:987 - An internal tristate buffer 'outDATA<7>\$WA1' is detected.
The logic is being translated to a mux implementation.
Cpld:987 - An internal tristate buffer 'outDATA<6>\$WA1' is detected.
The logic is being translated to a mux implementation.
Cpld:987 - An internal tristate buffer 'outDATA<5>\$WA2' is detected.
The logic is being translated to a mux implementation.
Cpld:987 - An internal tristate buffer 'outDATA<1>\$WA2' is detected.
The logic is being translated to a mux implementation.
Cpld:987 - An internal tristate buffer 'outDATA<0>\$WA0' is detected.
The logic is being translated to a mux implementation.
Cpld:987 - An internal tristate buffer 'outDATA<1>\$WA0' is detected.
The logic is being translated to a mux implementation.
Cpld:987 - An internal tristate buffer 'outDATA<2>\$WA0' is detected.
The logic is being translated to a mux implementation.
Cpld:987 - An internal tristate buffer 'outDATA<3>\$WA0' is detected.
The logic is being translated to a mux implementation.
Cpld:987 - An internal tristate buffer 'outDATA<4>\$WA0' is detected.
The logic is being translated to a mux implementation.
Cpld:987 - An internal tristate buffer 'outDATA<5>\$WA0' is detected.
The logic is being translated to a mux implementation.
Cpld:987 - An internal tristate buffer 'outDATA<3>\$WA2' is detected.
The logic is being translated to a mux implementation.
Cpld:987 - An internal tristate buffer 'outDATA<7>\$WA2' is detected.
The logic is being translated to a mux implementation.
Cpld:987 - An internal tristate buffer 'outDATA<6>\$WA0' is detected.
The logic is being translated to a mux implementation.
Cpld:987 - An internal tristate buffer 'outDATA<7>\$WA0' is detected.
The logic is being translated to a mux implementation.
Cpld:987 - An internal tristate buffer 'outDATA<0>\$WA3' is detected.
The logic is being translated to a mux implementation.
Cpld:987 - An internal tristate buffer 'outDATA<2>\$WA3' is detected.
The logic is being translated to a mux implementation.
Cpld:987 - An internal tristate buffer 'outDATA<3>\$WA3' is detected.
The logic is being translated to a mux implementation.
Cpld:987 - An internal tristate buffer 'outDATA<4>\$WA3' is detected.
The logic is being translated to a mux implementation.
Cpld:987 - An internal tristate buffer 'outDATA<5>\$WA3' is detected.
The logic is being translated to a mux implementation.
Cpld:987 - An internal tristate buffer 'outDATA<6>\$WA3' is detected.
The logic is being translated to a mux implementation.
Cpld:987 - An internal tristate buffer 'outDATA<7>\$WA3' is detected.
The logic is being translated to a mux implementation.
Cpld:987 - An internal tristate buffer 'outDATA<1>\$WA3' is detected.
The logic is being translated to a mux implementation.
Cpld:987 - An internal tristate buffer 'outDATA<0>\$WA4' is detected.
The logic is being translated to a mux implementation.
Cpld:987 - An internal tristate buffer 'outDATA<1>\$WA4' is detected.
The logic is being translated to a mux implementation.
Cpld:987 - An internal tristate buffer 'outDATA<2>\$WA4' is detected.
The logic is being translated to a mux implementation.
Cpld:987 - An internal tristate buffer 'outDATA<3>\$WA4' is detected.
The logic is being translated to a mux implementation.
Cpld:987 - An internal tristate buffer 'outDATA<4>\$WA4' is detected.
The logic is being translated to a mux implementation.
Cpld:987 - An internal tristate buffer 'outDATA<5>\$WA4' is detected.
The logic is being translated to a mux implementation.
Cpld:987 - An internal tristate buffer 'outDATA<6>\$WA4' is detected.
The logic is being translated to a mux implementation.
Cpld:987 - An internal tristate buffer 'outDATA<7>\$WA4' is detected.
The logic is being translated to a mux implementation.
Cpld:987 - An internal tristate buffer 'outDATA<0>\$WA5' is detected.
The logic is being translated to a mux implementation.
Cpld:987 - An internal tristate buffer 'outDATA<1>\$WA5' is detected.
The logic is being translated to a mux implementation.
Cpld:987 - An internal tristate buffer 'outDATA<2>\$WA5' is detected.
The logic is being translated to a mux implementation.
Cpld:987 - An internal tristate buffer 'outDATA<3>\$WA5' is detected.
The logic is being translated to a mux implementation.
Cpld:987 - An internal tristate buffer 'outDATA<4>\$WA5' is detected.
The logic is being translated to a mux implementation.
Cpld:987 - An internal tristate buffer 'outDATA<5>\$WA5' is detected.
The logic is being translated to a mux implementation.
Cpld:987 - An internal tristate buffer 'outDATA<6>\$WA5' is detected.
The logic is being translated to a mux implementation.
Cpld:987 - An internal tristate buffer 'outDATA<7>\$WA5' is detected.
The logic is being translated to a mux implementation.
Considering device XCR3384XL-7-TQ144.
Re-checking device resources ...
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Synthesizing and Optimizing...
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Fitting...
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Cpld:1086 - Design contains 82 pins, exceeds device limit 81 (37 JTAG pins
reserved).
Cpld:1064 - Design rules checking error. Fitting process stopped.
...o
Cpld:868 - Cannot fit the design into any of the specified devices with
the selected implementation options.
Fit failed.
Implementation ver0->rev0 Failed.