I 000044 55 23536         1078524615307 U21
(_unit VERILOG 6.349C.6.256 (U21 0 32 (U21 0 32 ))
	(_version v32)
	(_time 1078524614993 2004.03.05 14:10:14)
	(_source (\./compile/u21.v\ VERILOG (\./compile/u21.v\ VERILOG)))
	(_use (std(standard))(vl(verilog_logic)))
	(_base (E 7))
	(_entity
		(_time 1078524614993)
		(_use )
	)
	(_timescale 1ns 1ns)
	(_parameters    dbg   accs  )
	(_attribute )
	(_object
		(_port (_internal AS ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Brake0 ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Brake1 ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal DIR0 ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal DIR1 ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Enc033FLG ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Enc05FLG ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Enc133FLG ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Enc15FLG ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal FLS0 ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal FLS1 ~wire 0 33 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal GP_Motor0_0 ~wire 0 33 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal GP_Motor1_0 ~wire 0 33 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal HSI ~wire 0 33 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal Home0 ~wire 0 33 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Home033FLG ~wire 0 33 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Home05FLG ~wire 0 33 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Home1 ~wire 0 33 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Home133FLG ~wire 0 33 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Home15FLG ~wire 0 33 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal INTbus ~wire 0 34 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal LightSense ~wire 0 34 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal MHSO ~wire 0 34 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal Mclk ~wire 0 34 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PWM1 ~wire 0 34 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PWM2 ~wire 0 34 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PhaseA_Encoder0 ~wire 0 34 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PhaseA_Encoder1 ~wire 0 34 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PhaseB_Encoder0 ~wire 0 34 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PhaseB_Encoder1 ~wire 0 34 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal RD ~wire 0 35 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal RLS0 ~wire 0 35 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal RLS1 ~wire 0 35 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Reset ~wire 0 35 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal SCLinc ~wire 0 35 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal SCLreset ~wire 0 35 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal TXI ~wire 0 35 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal WR ~wire 0 35 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_type (_internal ~[5:0]wire~ 0 35 (_array ~wire ((_downto (i 5) (i 0))))))
		(_port (_internal I2CS ~[5:0]wire~ 0 35 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Enc033ctrl ~wire 0 35 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Enc05ctrl ~wire 0 36 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Enc133ctrl ~wire 0 36 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Enc15ctrl ~wire 0 36 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal GP_Motor0_1 ~wire 0 36 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal GP_Motor1_1 ~wire 0 36 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal HSO ~wire 0 36 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal Home033ctrl ~wire 0 36 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Home05ctrl ~wire 0 36 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Home133ctrl ~wire 0 36 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Home15ctrl ~wire 0 36 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal INT ~wire 0 37 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal LED1 ~wire 0 37 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal LED2 ~wire 0 37 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal LED3 ~wire 0 37 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal LED4 ~wire 0 37 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal LED5 ~wire 0 37 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal MHSI ~wire 0 37 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal MTRpwr ~wire 0 37 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal MTRpwrn ~wire 0 37 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal MTXI ~wire 0 37 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal PAH0 ~wire 0 38 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PAH1 ~wire 0 38 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PAL0 ~wire 0 38 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PAL1 ~wire 0 38 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PBH0 ~wire 0 38 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PBH1 ~wire 0 38 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PBL0 ~wire 0 38 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PBL1 ~wire 0 38 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal SCL ~wire 0 38 (_architecture (_inout ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_type (_internal ~[7:0]wire~ 0 38 (_array ~wire ((_downto (i 7) (i 0))))))
		(_port (_internal AD ~[7:0]wire~ 0 38 (_architecture (_inout ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET1635 ~wire 0 183 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET1643 ~wire 0 184 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET1651 ~wire 0 185 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET1659 ~wire 0 186 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET1667 ~wire 0 187 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET1675 ~wire 0 188 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET1683 ~wire 0 189 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET1691 ~wire 0 190 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET1699 ~wire 0 191 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET1707 ~wire 0 192 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET1970 ~wire 0 193 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET1978 ~wire 0 194 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET1989 ~wire 0 195 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET2017 ~wire 0 196 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET2025 ~wire 0 197 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET2036 ~wire 0 198 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET2047 ~wire 0 199 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET2064 ~wire 0 200 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET2078 ~wire 0 201 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET2311 ~wire 0 202 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET2482 ~wire 0 203 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET2493 ~wire 0 204 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET2501 ~wire 0 205 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET2512 ~wire 0 206 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET2528 ~wire 0 207 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET2539 ~wire 0 208 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET2575 ~wire 0 209 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET3248 ~wire 0 210 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET3253 ~wire 0 211 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET615 ~wire 0 212 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal NET621 ~wire 0 213 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal NET629 ~wire 0 214 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal BUS1564 ~[7:0]wire~ 0 215 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal inDATA ~[7:0]wire~ 0 216 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal outDATA ~[7:0]wire~ 0 217 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_subprogram
			

		)
		(_type (_external ~wire (vl verilog_logic wire)))
		(_type (_external ~reg (vl verilog_logic reg)))
		(_type (_external ~event (vl verilog_logic event)))
		(_type (_external ~wand (vl verilog_logic wand)))
		(_type (_external ~wor (vl verilog_logic wor)))
		(_type (_external ~tri1 (vl verilog_logic tri1)))
		(_type (_external ~tri0 (vl verilog_logic tri0)))
		(_type (_external ~trireg (vl verilog_logic trireg)))
		(_type (_external ~supply0 (vl verilog_logic supply0)))
		(_type (_external ~supply1 (vl verilog_logic supply1)))
		(_type (_external ~real (vl verilog_logic real)))
		(_type (_external ~realtime (vl verilog_logic realtime)))
		(_type (_external ~tri (vl verilog_logic tri)))
		(_type (_external ~triand (vl verilog_logic triand)))
		(_type (_external ~trior (vl verilog_logic trior)))
		(_type (_external ~bit (vl verilog_logic bit)))
		(_type (_external ~extstd.standard.integer (std standard integer)))
		(_type (_external ~extstd.standard.bit (std standard bit)))
		(_process
			(#ASSIGN#447_0 (_architecture 0 0 447 (_process (_alias ((NET615)(MHSO)))(_simple)
				(_target(99))
				(_sensitivity(22))
			)))
			(#ASSIGN#448_1 (_architecture 1 0 448 (_process (_alias ((NET621)(HSI)))(_simple)
				(_target(100))
				(_sensitivity(13))
			)))
			(#ASSIGN#449_2 (_architecture 2 0 449 (_process (_alias ((NET629)(TXI)))(_simple)
				(_target(101))
				(_sensitivity(36))
			)))
			(#ASSIGN#452_3 (_architecture 3 0 452 (_process (_alias ((HSO)(NET615)))(_simple)
				(_target(45))
				(_sensitivity(99))
			)))
			(#ASSIGN#453_4 (_architecture 4 0 453 (_process (_alias ((MHSI)(NET621)))(_simple)
				(_target(56))
				(_sensitivity(100))
			)))
			(#ASSIGN#454_5 (_architecture 5 0 454 (_process (_alias ((MTXI)(NET629)))(_simple)
				(_target(59))
				(_sensitivity(101))
			)))
		)
	)
	
	
	(_defparam
	)
	(_scope
	)
	(_instantiation U1 0 221 (_entity .  Servos)
		(_port
			((DCOR0CNTHIGHr) (NET1667))
			((DCOR0CNTLOWr) (NET1651))
			((DCOR0CNTMIDr) (NET1659))
			((DCOR0THRESLOWr) (NET1635))
			((DCOR0THRESMIDr) (NET1643))
			((DCOR1CNTHIGHr) (NET1675))
			((DCOR1CNTLOWr) (NET1683))
			((DCOR1CNTMIDr) (NET1691))
			((DCOR1THRESLOWr) (NET1707))
			((DCOR1THRESMIDr) (NET1699))
			((DCORENCCTLw) (NET1970))
			((DCORIFGr) (NET1978))
			((DCORIFGw) (NET1989))
			((Hfound0) (NET2482))
			((Hfound1) (NET2493))
			((Home_Encoder0) (Home0))
			((Home_Encoder1) (Home1))
			((Mclk) (Mclk))
			((MotorIn0) (GP_Motor0_0))
			((Motorin1) (GP_Motor1_0))
			((PhaseA_Encoder0) (PhaseA_Encoder0))
			((PhaseA_Encoder1) (PhaseA_Encoder1))
			((PhaseB_Encoder0) (PhaseB_Encoder0))
			((PhaseB_Encoder1) (PhaseB_Encoder1))
			((Reset) (Reset))
			((Tfound0) (NET2501))
			((Tfound1) (NET2512))
			((inDATA) (inDATA))
			((outDATA) (outDATA))
		)
		(_strength)
	)
	(_instantiation U11 0 256 (_entity .  I2Cfix)
		(_port
			((DCORI2CCNTr) (NET2311))
			((Inc) (SCLinc))
			((Mclk) (Mclk))
			((SCL) (SCL))
			((SCLint) (NET2539))
			((SCLreset) (SCLreset))
			((outDATA) (outDATA))
		)
		(_strength)
	)
	(_instantiation U12 0 269 (_entity .  U21AddDecode)
		(_port
			((ADDR) (BUS1564))
			((AS) (AS))
			((DCOR0CNTHIGHr) (NET1667))
			((DCOR0CNTLOWr) (NET1651))
			((DCOR0CNTMIDr) (NET1659))
			((DCOR0THRESLOWr) (NET1635))
			((DCOR0THRESMIDr) (NET1643))
			((DCOR1CNTHIGHr) (NET1675))
			((DCOR1CNTLOWr) (NET1683))
			((DCOR1CNTMIDr) (NET1691))
			((DCOR1THRESLOWr) (NET1707))
			((DCOR1THRESMIDr) (NET1699))
			((DCORCONFIGr) (NET2064))
			((DCORENCCTLw) (NET1970))
			((DCORENCPWRr) (NET2036))
			((DCORENCPWRw) (NET2025))
			((DCORI2CCNTr) (NET2311))
			((DCORIEw) (NET2078))
			((DCORIFGr) (NET1978))
			((DCORIFGw) (NET1989))
			((DCORLIMITSr) (NET2047))
			((DCOROUTw) (NET2017))
			((RD) (RD))
			((WR) (WR))
		)
		(_strength)
	)
	(_instantiation U2 0 299 (_entity .  Interface)
		(_port
			((AD) (AD))
			((ADDR) (BUS1564))
			((AS) (AS))
			((Mclk) (Mclk))
			((RD) (RD))
			((Reset) (Reset))
			((WR) (WR))
			((inDATA) (inDATA))
			((outDATA) (outDATA))
		)
		(_strength)
	)
	(_instantiation U3 0 314 (_entity .  Interrupt)
		(_port
			((BusInt) (INTbus))
			((DCORIEw) (NET2078))
			((Homed0) (NET2482))
			((Homed1) (NET2493))
			((I2Cint) (NET2539))
			((INT) (INT))
			((LSwitchInt) (NET2575))
			((Mclk) (Mclk))
			((PWRint) (NET2528))
			((Reset) (Reset))
			((Thres0) (NET2501))
			((Thres1) (NET2512))
			((inDATA) (inDATA))
		)
		(_strength)
	)
	(_instantiation U4 0 333 (_entity .  PWRreg)
		(_port
			((DCORENCPWRr) (NET2036))
			((DCORENCPWRw) (NET2025))
			((DCORIFGr) (NET1978))
			((DCORIFGw) (NET1989))
			((Enc033ctl) (Home15ctrl))
			((Enc033flg) (Enc033FLG))
			((Enc05ctl) (Home133ctrl))
			((Enc05flg) (Enc05FLG))
			((Enc133ctl) (Home05ctrl))
			((Enc133flg) (Enc133FLG))
			((Enc15ctl) (Home033ctrl))
			((Enc15flg) (Enc15FLG))
			((Hme033ctl) (Enc15ctrl))
			((Hme033flg) (Home033FLG))
			((Hme05ctl) (Enc133ctrl))
			((Hme05flg) (Home05FLG))
			((Hme133ctl) (Enc05ctrl))
			((Hme133flg) (Home133FLG))
			((Hme15ctl) (Enc033ctrl))
			((Hme15flg) (Home15FLG))
			((Mclk) (Mclk))
			((PWRint) (NET2528))
			((Reset) (Reset))
			((inDATA) (inDATA))
			((outDATA) (outDATA))
		)
		(_strength)
	)
	(_instantiation U5 0 364 (_entity .  Lswitch)
		(_port
			((Brake0) (Brake0))
			((Brake1) (Brake1))
			((DCORIFGr) (NET1978))
			((DCORIFGw) (NET1989))
			((DCORLIMITSr) (NET2047))
			((DIR0) (DIR0))
			((DIR1) (DIR1))
			((FLS0) (FLS0))
			((FLS1) (FLS1))
			((Home0) (Home0))
			((Home1) (Home1))
			((LSwitchInt) (NET2575))
			((Mclk) (Mclk))
			((RLS0) (RLS0))
			((RLS1) (RLS1))
			((Reset) (Reset))
			((fBRK0) (NET3248))
			((fBRK1) (NET3253))
			((inDATA) (inDATA))
			((outDATA) (outDATA))
		)
		(_strength)
	)
	(_instantiation U6 0 390 (_entity .  I2CAddress)
		(_port
			((DCORCONFIGr) (NET2064))
			((I2CS) (I2CS))
			((MotorIn0) (GP_Motor0_0))
			((MotorIn1) (GP_Motor1_0))
			((outDATA) (outDATA))
		)
		(_strength)
	)
	(_instantiation U7 0 401 (_entity .  PWMcontrol)
		(_port
			((Brake1) (Brake0))
			((Brake2) (Brake1))
			((DIR1) (DIR0))
			((DIR2) (DIR1))
			((HBRK1) (NET3248))
			((HBRK2) (NET3253))
			((PAH1) (PAH0))
			((PAH2) (PBL1))
			((PAL1) (PAL0))
			((PAL2) (PBH1))
			((PBH1) (PBH0))
			((PBH2) (PAL1))
			((PBL1) (PBL0))
			((PBL2) (PAH1))
			((PWM1) (PWM1))
			((PWM2) (PWM2))
			((fBRK1) (NET3248))
			((fBRK2) (NET3253))
		)
		(_strength)
	)
	(_instantiation U9 0 425 (_entity .  MISCouts)
		(_port
			((DCOROUTw) (NET2017))
			((GP_Motor0_1) (GP_Motor0_1))
			((GP_Motor1_1) (GP_Motor1_1))
			((LED1) (LED1))
			((LED2) (LED2))
			((LED3) (LED3))
			((LED4) (LED4))
			((LED5) (LED5))
			((LightSense) (LightSense))
			((MTRpwr) (MTRpwr))
			((MTRpwrn) (MTRpwrn))
			((Mclk) (Mclk))
			((Reset) (Reset))
			((inDATA) (inDATA))
		)
		(_strength)
	)
	(_model . U21 7 -1)

)
V 000047 55 10141         1078524615321 Servos
(_unit VERILOG 6.349C.6.256 (Servos 0 32 (Servos 0 32 ))
	(_version v32)
	(_time 1078524614993 2004.03.05 14:10:14)
	(_source (\./compile/Servos.v\ VERILOG (\./compile/servos.v\ VERILOG)))
	(_use (std(standard))(vl(verilog_logic)))
	(_base (E 2))
	(_entity
		(_time 1078524614993)
		(_use )
	)
	(_timescale 1ns 1ns)
	(_parameters    dbg   accs  )
	(_attribute )
	(_object
		(_port (_internal DCOR0CNTHIGHr ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal DCOR0CNTLOWr ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal DCOR0CNTMIDr ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal DCOR0THRESLOWr ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal DCOR0THRESMIDr ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal DCOR1CNTHIGHr ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal DCOR1CNTLOWr ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal DCOR1CNTMIDr ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal DCOR1THRESLOWr ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal DCOR1THRESMIDr ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal DCORENCCTLw ~wire 0 33 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal DCORIFGr ~wire 0 33 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal DCORIFGw ~wire 0 33 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Home_Encoder0 ~wire 0 33 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Home_Encoder1 ~wire 0 33 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Mclk ~wire 0 33 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal MotorIn0 ~wire 0 33 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Motorin1 ~wire 0 33 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PhaseA_Encoder0 ~wire 0 33 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PhaseA_Encoder1 ~wire 0 33 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PhaseB_Encoder0 ~wire 0 34 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PhaseB_Encoder1 ~wire 0 34 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Reset ~wire 0 34 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_type (_internal ~[7:0]wire~ 0 34 (_array ~wire ((_downto (i 7) (i 0))))))
		(_port (_internal inDATA ~[7:0]wire~ 0 34 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Hfound0 ~wire 0 34 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Hfound1 ~wire 0 34 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Tfound0 ~wire 0 34 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Tfound1 ~wire 0 34 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal outDATA ~[7:0]wire~ 0 34 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal ce0 ~wire 0 97 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal ce1 ~wire 0 98 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET3720 ~wire 0 99 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET3721 ~wire 0 100 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal Sclk ~wire 0 101 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal updown0 ~wire 0 102 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal updown1 ~wire 0 103 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal Zero0 ~wire 0 104 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal Zero1 ~wire 0 105 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_type (_internal ~[23:0]wire~ 0 106 (_array ~wire ((_downto (i 23) (i 0))))))
		(_signal (_internal Channel0 ~[23:0]wire~ 0 106 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal Channel1 ~[23:0]wire~ 0 107 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_subprogram
			

		)
		(_type (_external ~wire (vl verilog_logic wire)))
		(_type (_external ~reg (vl verilog_logic reg)))
		(_type (_external ~event (vl verilog_logic event)))
		(_type (_external ~wand (vl verilog_logic wand)))
		(_type (_external ~wor (vl verilog_logic wor)))
		(_type (_external ~tri1 (vl verilog_logic tri1)))
		(_type (_external ~tri0 (vl verilog_logic tri0)))
		(_type (_external ~trireg (vl verilog_logic trireg)))
		(_type (_external ~supply0 (vl verilog_logic supply0)))
		(_type (_external ~supply1 (vl verilog_logic supply1)))
		(_type (_external ~real (vl verilog_logic real)))
		(_type (_external ~realtime (vl verilog_logic realtime)))
		(_type (_external ~tri (vl verilog_logic tri)))
		(_type (_external ~triand (vl verilog_logic triand)))
		(_type (_external ~trior (vl verilog_logic trior)))
		(_type (_external ~bit (vl verilog_logic bit)))
		(_type (_external ~extstd.standard.integer (std standard integer)))
		(_type (_external ~extstd.standard.bit (std standard bit)))
		(_process
			(#ASSIGN#211_0 (_architecture 0 0 211 (_process (_alias ((Sclk)(Mclk)))(_simple)
				(_target(33))
				(_sensitivity(15))
			)))
		)
	)
	
	
	(_defparam
	)
	(_scope
	)
	(_instantiation U1 0 111 (_entity .  Decode)
		(_port
			((Reset) (Reset))
			((Sclk) (Sclk))
			((ce) (ce0))
			((phaseA) (PhaseA_Encoder0))
			((phaseB) (PhaseB_Encoder0))
			((updown) (updown0))
		)
		(_strength)
	)
	(_instantiation U2 0 123 (_entity .  Counter)
		(_port
			((Reset) (Reset))
			((Sclk) (Sclk))
			((Zero) (Zero0))
			((ce) (ce0))
			((count) (Channel0))
			((sense) (NET3721))
			((updown) (updown0))
		)
		(_strength)
	)
	(_instantiation U3 0 136 (_entity .  Holdreg)
		(_port
			((DCOR0CNTHIGHr) (DCOR0CNTHIGHr))
			((DCOR0CNTLOWr) (DCOR0CNTLOWr))
			((DCOR0CNTMIDr) (DCOR0CNTMIDr))
			((DCOR1CNTHIGHr) (DCOR1CNTHIGHr))
			((DCOR1CNTLOWr) (DCOR1CNTLOWr))
			((DCOR1CNTMIDr) (DCOR1CNTMIDr))
			((Reset) (Reset))
			((Sclk) (Sclk))
			((ch0in) (Channel0))
			((ch1in) (Channel1))
			((outDATA) (outDATA))
		)
		(_strength)
	)
	(_instantiation U4 0 153 (_entity .  HomeConfig)
		(_port
			((Channel0) (Channel0(d_15_0)))
			((Channel1) (Channel1(d_15_0)))
			((DCOR0THRESLOWr) (DCOR0THRESLOWr))
			((DCOR0THRESMIDr) (DCOR0THRESMIDr))
			((DCOR1THRESLOWr) (DCOR1THRESLOWr))
			((DCOR1THRESMIDr) (DCOR1THRESMIDr))
			((DCORENCCTLw) (DCORENCCTLw))
			((DCORIFGr) (DCORIFGr))
			((DCORIFGw) (DCORIFGw))
			((Hfound0) (Hfound0))
			((Hfound1) (Hfound1))
			((Home_Encoder0) (Home_Encoder0))
			((Home_Encoder1) (Home_Encoder1))
			((MotorIn0) (MotorIn0))
			((MotorIn1) (Motorin1))
			((Reset) (Reset))
			((Sclk) (Sclk))
			((Tfound0) (Tfound0))
			((Tfound1) (Tfound1))
			((Zero0) (Zero0))
			((Zero1) (Zero1))
			((inDATA) (inDATA))
			((outDATA) (outDATA))
			((sense0) (NET3721))
			((sense1) (NET3720))
		)
		(_strength)
	)
	(_instantiation U5 0 184 (_entity .  Counter)
		(_port
			((Reset) (Reset))
			((Sclk) (Sclk))
			((Zero) (Zero1))
			((ce) (ce1))
			((count) (Channel1))
			((sense) (NET3720))
			((updown) (updown1))
		)
		(_strength)
	)
	(_instantiation U6 0 197 (_entity .  Decode)
		(_port
			((Reset) (Reset))
			((Sclk) (Sclk))
			((ce) (ce1))
			((phaseA) (PhaseA_Encoder1))
			((phaseB) (PhaseB_Encoder1))
			((updown) (updown1))
		)
		(_strength)
	)
	(_model . Servos 2 -1)

)
V 000047 55 3488          1078524615325 I2Cfix
(_unit VERILOG 6.349C.6.256 (I2Cfix 0 32 (I2Cfix 0 32 ))
	(_version v32)
	(_time 1078524614993 2004.03.05 14:10:14)
	(_source (\./compile/I2Cfix.v\ VERILOG (\./compile/i2cfix.v\ VERILOG)))
	(_use (std(standard))(vl(verilog_logic)))
	(_base (E 1))
	(_entity
		(_time 1078524614993)
		(_use )
	)
	(_timescale 1ns 1ns)
	(_parameters    dbg   accs  )
	(_attribute )
	(_object
		(_port (_internal DCORI2CCNTr ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Inc ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Mclk ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal SCLreset ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal SCLint ~wire 0 32 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_type (_internal ~[7:0]wire~ 0 32 (_array ~wire ((_downto (i 7) (i 0))))))
		(_port (_internal outDATA ~[7:0]wire~ 0 32 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal SCL ~wire 0 32 (_architecture (_inout ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal Incdetect ~wire 0 51 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal SCLdetect ~wire 0 52 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_subprogram
			

		)
		(_type (_external ~wire (vl verilog_logic wire)))
		(_type (_external ~reg (vl verilog_logic reg)))
		(_type (_external ~event (vl verilog_logic event)))
		(_type (_external ~wand (vl verilog_logic wand)))
		(_type (_external ~wor (vl verilog_logic wor)))
		(_type (_external ~tri1 (vl verilog_logic tri1)))
		(_type (_external ~tri0 (vl verilog_logic tri0)))
		(_type (_external ~trireg (vl verilog_logic trireg)))
		(_type (_external ~supply0 (vl verilog_logic supply0)))
		(_type (_external ~supply1 (vl verilog_logic supply1)))
		(_type (_external ~real (vl verilog_logic real)))
		(_type (_external ~realtime (vl verilog_logic realtime)))
		(_type (_external ~tri (vl verilog_logic tri)))
		(_type (_external ~triand (vl verilog_logic triand)))
		(_type (_external ~trior (vl verilog_logic trior)))
		(_type (_external ~bit (vl verilog_logic bit)))
		(_type (_external ~extstd.standard.integer (std standard integer)))
		(_type (_external ~extstd.standard.bit (std standard bit)))
	)
	
	
	(_defparam
	)
	(_scope
	)
	(_instantiation U1 0 56 (_entity .  NegDetect)
		(_port
			((Line) (Inc))
			((Mclk) (Mclk))
			((Ndetect) (Incdetect))
		)
		(_strength)
	)
	(_instantiation U2 0 65 (_entity .  NegDetect)
		(_port
			((Line) (SCL))
			((Mclk) (Mclk))
			((Ndetect) (SCLdetect))
		)
		(_strength)
	)
	(_instantiation U3 0 74 (_entity .  BitCounter)
		(_port
			((DCORI2CCNTr) (DCORI2CCNTr))
			((DriveSCL) (SCL))
			((Mclk) (Mclk))
			((NegInc) (Incdetect))
			((NegSCL) (SCLdetect))
			((SCLint) (SCLint))
			((SCLreset) (SCLreset))
			((outDATA) (outDATA))
		)
		(_strength)
	)
	(_model . I2Cfix 1 -1)

)
I 000053 55 9137          1078524615329 U21AddDecode
(_unit VERILOG 6.349C.6.256 (U21AddDecode 0 27 (U21AddDecode 0 27 ))
	(_version v32)
	(_time 1078524614993 2004.03.05 14:10:14)
	(_source (\./src/u21adddecode.v\ VERILOG (\./src/u21adddecode.v\ VERILOG)))
	(_use (std(standard))(vl(verilog_logic)))
	(_base (E 22))
	(_entity
		(_time 1078524614993)
		(_use )
	)
	(_timescale 1ps 1ps)
	(_parameters    dbg   accs  )
	(_attribute )
	(_object
		(_port (_internal DCOR0CNTLOWr ~wire 0 27 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal DCOR0THRESLOWr ~wire 0 27 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal DCOR1CNTLOWr ~wire 0 27 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal DCOR1THRESLOWr ~wire 0 27 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal DCORENCPWRr ~wire 0 27 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal WR ~wire 0 27 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal DCOR0CNTMIDr ~wire 0 27 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal DCOR0THRESMIDr ~wire 0 27 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal DCOR1CNTMIDr ~wire 0 27 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal DCOR1THRESMIDr ~wire 0 27 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal DCORLIMITSr ~wire 0 27 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal DCORIEw ~wire 0 27 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal DCORENCPWRw ~wire 0 27 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal DCOR0CNTHIGHr ~wire 0 27 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal DCORCONFIGr ~wire 0 27 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal DCORIFGr ~wire 0 27 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal DCOR1CNTHIGHr ~wire 0 27 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal AS ~wire 0 27 (_architecture (_in ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal DCORIFGw ~wire 0 27 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal RD ~wire 0 27 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal DCOROUTw ~wire 0 27 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal DCORENCCTLw ~wire 0 27 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_type (_internal ~[7:0]wire~ 0 27 (_array ~wire ((_downto (i 7) (i 0))))))
		(_port (_internal ADDR ~[7:0]wire~ 0 27 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal DCORI2CCNTr ~wire 0 27 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_type (_internal ~[7:0]reg~ 0 91 (_array ~reg ((_downto (i 7) (i 0))))))
		(_signal (_internal Select.Address ~[7:0]reg~ 0 91 (_subprogram Select (_in ))) (_reg ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal Select.Location ~[7:0]reg~ 0 92 (_subprogram Select (_in ))) (_reg ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal Select.RD ~reg 0 93 (_subprogram Select (_in ))) (_reg ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal Select.WR ~reg 0 93 (_subprogram Select (_in ))) (_reg ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal Select.RorW ~reg 0 94 (_subprogram Select (_in ))) (_reg ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal Select.Select ~reg 0 0 (_subprogram Select (_out ))) (_reg ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_subprogram
			
			(_internal Select 20 0 90 (_architecture (_function)(_target(29))
				(_read(28)(26)(27)(22)(25))
			))

		)
		(_type (_external ~wire (vl verilog_logic wire)))
		(_type (_external ~reg (vl verilog_logic reg)))
		(_type (_external ~event (vl verilog_logic event)))
		(_type (_external ~wand (vl verilog_logic wand)))
		(_type (_external ~wor (vl verilog_logic wor)))
		(_type (_external ~tri1 (vl verilog_logic tri1)))
		(_type (_external ~tri0 (vl verilog_logic tri0)))
		(_type (_external ~trireg (vl verilog_logic trireg)))
		(_type (_external ~supply0 (vl verilog_logic supply0)))
		(_type (_external ~supply1 (vl verilog_logic supply1)))
		(_type (_external ~real (vl verilog_logic real)))
		(_type (_external ~realtime (vl verilog_logic realtime)))
		(_type (_external ~tri (vl verilog_logic tri)))
		(_type (_external ~triand (vl verilog_logic triand)))
		(_type (_external ~trior (vl verilog_logic trior)))
		(_type (_external ~bit (vl verilog_logic bit)))
		(_type (_external ~extstd.standard.integer (std standard integer)))
		(_type (_external ~extstd.standard.bit (std standard bit)))
		(_process
			(#ASSIGN#102_0 (_architecture 0 0 102 (_process (_simple)
				(_target(11))
				(_sensitivity(22)(19)(5))
				(_call(0))
			)))
			(#ASSIGN#105_1 (_architecture 1 0 105 (_process (_simple)
				(_target(18))
				(_sensitivity(22)(19)(5))
				(_call(0))
			)))
			(#ASSIGN#108_2 (_architecture 2 0 108 (_process (_simple)
				(_target(15))
				(_sensitivity(22)(19)(5))
				(_call(0))
			)))
			(#ASSIGN#111_3 (_architecture 3 0 111 (_process (_simple)
				(_target(10))
				(_sensitivity(22)(19)(5))
				(_call(0))
			)))
			(#ASSIGN#114_4 (_architecture 4 0 114 (_process (_simple)
				(_target(21))
				(_sensitivity(22)(19)(5))
				(_call(0))
			)))
			(#ASSIGN#117_5 (_architecture 5 0 117 (_process (_simple)
				(_target(0))
				(_sensitivity(22)(19)(5))
				(_call(0))
			)))
			(#ASSIGN#120_6 (_architecture 6 0 120 (_process (_simple)
				(_target(6))
				(_sensitivity(22)(19)(5))
				(_call(0))
			)))
			(#ASSIGN#123_7 (_architecture 7 0 123 (_process (_simple)
				(_target(13))
				(_sensitivity(22)(19)(5))
				(_call(0))
			)))
			(#ASSIGN#126_8 (_architecture 8 0 126 (_process (_simple)
				(_target(2))
				(_sensitivity(22)(19)(5))
				(_call(0))
			)))
			(#ASSIGN#129_9 (_architecture 9 0 129 (_process (_simple)
				(_target(8))
				(_sensitivity(22)(19)(5))
				(_call(0))
			)))
			(#ASSIGN#132_10 (_architecture 10 0 132 (_process (_simple)
				(_target(16))
				(_sensitivity(22)(19)(5))
				(_call(0))
			)))
			(#ASSIGN#135_11 (_architecture 11 0 135 (_process (_simple)
				(_target(1))
				(_sensitivity(22)(19)(5))
				(_call(0))
			)))
			(#ASSIGN#138_12 (_architecture 12 0 138 (_process (_simple)
				(_target(7))
				(_sensitivity(22)(19)(5))
				(_call(0))
			)))
			(#ASSIGN#141_13 (_architecture 13 0 141 (_process (_simple)
				(_target(3))
				(_sensitivity(22)(19)(5))
				(_call(0))
			)))
			(#ASSIGN#144_14 (_architecture 14 0 144 (_process (_simple)
				(_target(9))
				(_sensitivity(22)(19)(5))
				(_call(0))
			)))
			(#ASSIGN#147_15 (_architecture 15 0 147 (_process (_simple)
				(_target(4))
				(_sensitivity(22)(19)(5))
				(_call(0))
			)))
			(#ASSIGN#150_16 (_architecture 16 0 150 (_process (_simple)
				(_target(12))
				(_sensitivity(22)(19)(5))
				(_call(0))
			)))
			(#ASSIGN#153_17 (_architecture 17 0 153 (_process (_simple)
				(_target(14))
				(_sensitivity(22)(19)(5))
				(_call(0))
			)))
			(#ASSIGN#156_18 (_architecture 18 0 156 (_process (_simple)
				(_target(20))
				(_sensitivity(22)(19)(5))
				(_call(0))
			)))
			(#ASSIGN#159_19 (_architecture 19 0 159 (_process (_simple)
				(_target(23))
				(_sensitivity(22)(19)(5))
				(_call(0))
			)))
			(#INTERNAL#0_21 (_internal 21 0 0 (_process (_virtual))))
		)
	)
	
	
	(_defparam
	)
	(_scope
		(_unit Select function 0 90
		)
	)
	(_model . U21AddDecode 22 -1)

)
I 000050 55 4270          1078524615333 Interface
(_unit VERILOG 6.349C.6.256 (Interface 0 25 (Interface 0 25 ))
	(_version v32)
	(_time 1078524614993 2004.03.05 14:10:14)
	(_source (\./src/interface.v\ VERILOG (\./src/interface.v\ VERILOG)))
	(_use (std(standard))(vl(verilog_logic)))
	(_base (E 6))
	(_entity
		(_time 1078524614993)
		(_use )
	)
	(_timescale 1ps 1ps)
	(_parameters    dbg   accs  )
	(_attribute nb_assign )
	(_object
		(_type (_internal ~[7:0]wire~ 0 25 (_array ~wire ((_downto (i 7) (i 0))))))
		(_port (_internal inDATA ~[7:0]wire~ 0 25 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal outDATA ~[7:0]wire~ 0 25 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal Reset ~wire 0 25 (_architecture (_in ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal AS ~wire 0 25 (_architecture (_in ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal AD ~[7:0]wire~ 0 25 (_architecture (_inout ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal RD ~wire 0 25 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal Mclk ~wire 0 25 (_architecture (_in ))) (_net  ) (_nonbaction) (_noforceassign))
		(_port (_internal WR ~wire 0 25 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal ADDR ~[7:0]wire~ 0 25 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_type (_internal ~[7:0]reg~ 0 56 (_array ~reg ((_downto (i 7) (i 0))))))
		(_signal (_internal ADDR_reg ~[7:0]reg~ 0 56 (_architecture (_uni ))) (_reg ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal AutoInc ~reg 0 64 (_architecture (_uni ))) (_reg ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal ASedge ~reg 0 66 (_architecture (_uni ))) (_reg ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal WRRDedge ~reg 0 68 (_architecture (_uni ))) (_reg ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal Enable_AD ~wire 0 72 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_subprogram
			

		)
		(_type (_external ~wire (vl verilog_logic wire)))
		(_type (_external ~reg (vl verilog_logic reg)))
		(_type (_external ~event (vl verilog_logic event)))
		(_type (_external ~wand (vl verilog_logic wand)))
		(_type (_external ~wor (vl verilog_logic wor)))
		(_type (_external ~tri1 (vl verilog_logic tri1)))
		(_type (_external ~tri0 (vl verilog_logic tri0)))
		(_type (_external ~trireg (vl verilog_logic trireg)))
		(_type (_external ~supply0 (vl verilog_logic supply0)))
		(_type (_external ~supply1 (vl verilog_logic supply1)))
		(_type (_external ~real (vl verilog_logic real)))
		(_type (_external ~realtime (vl verilog_logic realtime)))
		(_type (_external ~tri (vl verilog_logic tri)))
		(_type (_external ~triand (vl verilog_logic triand)))
		(_type (_external ~trior (vl verilog_logic trior)))
		(_type (_external ~bit (vl verilog_logic bit)))
		(_type (_external ~extstd.standard.integer (std standard integer)))
		(_type (_external ~extstd.standard.bit (std standard bit)))
		(_process
			(#ASSIGN#75_0 (_architecture 0 0 75 (_process (_alias ((ADDR)(ADDR_reg)))(_simple)
				(_target(8))
				(_sensitivity(9))
			)))
			(#ASSIGN#78_1 (_architecture 1 0 78 (_process (_alias ((Enable_AD)(WR)(RD)))(_simple)
				(_target(13))
				(_sensitivity(7)(5))
			)))
			(#ASSIGN#85_2 (_architecture 2 0 85 (_process (_alias ((inDATA)(AD)))(_simple)
				(_target(0))
				(_sensitivity(4))
			)))
			(#ASSIGN#86_3 (_architecture 3 0 86 (_process (_simple)
				(_target(4))
				(_sensitivity(13)(1))
			)))
			(#ALWAYS#88_4 (_architecture 4 0 88 (_process 
				(_target(11)(12)(9)(10))
				(_read(6)(3)(7)(5)(2)(11)(4)(12)(10)(9))
			)))
		)
	)
	
	
	(_defparam
	)
	(_model . Interface 6 -1)

)
I 000050 55 4040          1078524615337 Interrupt
(_unit VERILOG 6.349C.6.256 (Interrupt 0 25 (Interrupt 0 25 ))
	(_version v32)
	(_time 1078524614993 2004.03.05 14:10:14)
	(_source (\./src/interrupt.v\ VERILOG (\./src/interrupt.v\ VERILOG)))
	(_use (std(standard))(vl(verilog_logic)))
	(_base (E 3))
	(_entity
		(_time 1078524614993)
		(_use )
	)
	(_timescale 1ps 1ps)
	(_parameters    dbg   accs  )
	(_attribute nb_assign )
	(_object
		(_type (_internal ~[7:0]wire~ 0 25 (_array ~wire ((_downto (i 7) (i 0))))))
		(_port (_internal inDATA ~[7:0]wire~ 0 25 (_architecture (_in ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal Reset ~wire 0 25 (_architecture (_in ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal PWRint ~wire 0 25 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal BusInt ~wire 0 25 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal Thres0 ~wire 0 25 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal Mclk ~wire 0 25 (_architecture (_in ))) (_net  ) (_nonbaction) (_noforceassign))
		(_port (_internal Thres1 ~wire 0 25 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal I2Cint ~wire 0 25 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal LSwitchInt ~wire 0 25 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal INT ~wire 0 25 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal DCORIEw ~wire 0 25 (_architecture (_in ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal Homed0 ~wire 0 25 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal Homed1 ~wire 0 25 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_type (_internal ~[7:0]reg~ 0 59 (_array ~reg ((_downto (i 7) (i 0))))))
		(_signal (_internal DCORIE ~[7:0]reg~ 0 59 (_architecture (_uni ))) (_reg ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_subprogram
			

		)
		(_type (_external ~wire (vl verilog_logic wire)))
		(_type (_external ~reg (vl verilog_logic reg)))
		(_type (_external ~event (vl verilog_logic event)))
		(_type (_external ~wand (vl verilog_logic wand)))
		(_type (_external ~wor (vl verilog_logic wor)))
		(_type (_external ~tri1 (vl verilog_logic tri1)))
		(_type (_external ~tri0 (vl verilog_logic tri0)))
		(_type (_external ~trireg (vl verilog_logic trireg)))
		(_type (_external ~supply0 (vl verilog_logic supply0)))
		(_type (_external ~supply1 (vl verilog_logic supply1)))
		(_type (_external ~real (vl verilog_logic real)))
		(_type (_external ~realtime (vl verilog_logic realtime)))
		(_type (_external ~tri (vl verilog_logic tri)))
		(_type (_external ~triand (vl verilog_logic triand)))
		(_type (_external ~trior (vl verilog_logic trior)))
		(_type (_external ~bit (vl verilog_logic bit)))
		(_type (_external ~extstd.standard.integer (std standard integer)))
		(_type (_external ~extstd.standard.bit (std standard bit)))
		(_process
			(#ASSIGN#68_0 (_architecture 0 0 68 (_process (_alias ((INT)(DCORIE(7))(I2Cint)(DCORIE(6))(Thres1)(DCORIE(5))(Thres0)(DCORIE(4))(LSwitchInt)(DCORIE(3))(Homed1)(DCORIE(2))(Homed0)(DCORIE(1))(PWRint)(DCORIE(0))(BusInt)))(_simple)
				(_target(9))
				(_sensitivity(13(7))(7)(13(6))(6)(13(5))(4)(13(4))(8)(13(3))(12)(13(2))(11)(13(1))(2)(13(0))(3))
			)))
			(#ALWAYS#70_1 (_architecture 1 0 70 (_process 
				(_target(13))
				(_read(5)(1)(10)(0))
			)))
		)
	)
	
	
	(_defparam
	)
	(_model . Interrupt 3 -1)

)
I 000047 55 7698          1078524615341 PWRreg
(_unit VERILOG 6.349C.6.256 (PWRreg 0 25 (PWRreg 0 25 ))
	(_version v32)
	(_time 1078524614993 2004.03.05 14:10:14)
	(_source (\./src/PWRreg.v\ VERILOG (\./src/pwrreg.v\ VERILOG)))
	(_use (std(standard))(vl(verilog_logic)))
	(_base (E 14))
	(_entity
		(_time 1078524614993)
		(_use )
	)
	(_timescale 1ps 1ps)
	(_parameters    dbg   accs  )
	(_attribute nb_assign )
	(_object
		(_port (_internal Hme05ctl ~wire 0 25 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal Hme15ctl ~wire 0 25 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal Reset ~wire 0 25 (_architecture (_in ))) (_net  ) (_nonbaction) (_noforceassign))
		(_port (_internal PWRint ~wire 0 25 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal Enc033flg ~wire 0 25 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal Enc133flg ~wire 0 25 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal Mclk ~wire 0 25 (_architecture (_in ))) (_net  ) (_nonbaction) (_noforceassign))
		(_port (_internal Hme033flg ~wire 0 25 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal DCORENCPWRr ~wire 0 25 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal Hme133flg ~wire 0 25 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal DCORENCPWRw ~wire 0 25 (_architecture (_in ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal Enc033ctl ~wire 0 25 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal Enc133ctl ~wire 0 25 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal DCORIFGr ~wire 0 25 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_type (_internal ~[7:0]wire~ 0 25 (_array ~wire ((_downto (i 7) (i 0))))))
		(_port (_internal inDATA ~[7:0]wire~ 0 25 (_architecture (_in ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal outDATA ~[7:0]wire~ 0 25 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal Hme033ctl ~wire 0 25 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal Hme133ctl ~wire 0 25 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal Enc05flg ~wire 0 25 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal Enc15flg ~wire 0 25 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal DCORIFGw ~wire 0 25 (_architecture (_in ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal Hme05flg ~wire 0 25 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal Hme15flg ~wire 0 25 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal Enc05ctl ~wire 0 25 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal Enc15ctl ~wire 0 25 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_type (_internal ~[7:0]reg~ 0 82 (_array ~reg ((_downto (i 7) (i 0))))))
		(_signal (_internal ctrlr ~[7:0]reg~ 0 82 (_architecture (_uni ))) (_reg ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal Flgreg ~[7:0]reg~ 0 83 (_architecture (_uni ))) (_reg ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal DCORIFG ~reg 0 84 (_architecture (_uni ))) (_reg ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal orFLGs ~wire 0 85 (_architecture (_uni ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_subprogram
			

		)
		(_type (_external ~wire (vl verilog_logic wire)))
		(_type (_external ~reg (vl verilog_logic reg)))
		(_type (_external ~event (vl verilog_logic event)))
		(_type (_external ~wand (vl verilog_logic wand)))
		(_type (_external ~wor (vl verilog_logic wor)))
		(_type (_external ~tri1 (vl verilog_logic tri1)))
		(_type (_external ~tri0 (vl verilog_logic tri0)))
		(_type (_external ~trireg (vl verilog_logic trireg)))
		(_type (_external ~supply0 (vl verilog_logic supply0)))
		(_type (_external ~supply1 (vl verilog_logic supply1)))
		(_type (_external ~real (vl verilog_logic real)))
		(_type (_external ~realtime (vl verilog_logic realtime)))
		(_type (_external ~tri (vl verilog_logic tri)))
		(_type (_external ~triand (vl verilog_logic triand)))
		(_type (_external ~trior (vl verilog_logic trior)))
		(_type (_external ~bit (vl verilog_logic bit)))
		(_type (_external ~extstd.standard.integer (std standard integer)))
		(_type (_external ~extstd.standard.bit (std standard bit)))
		(_process
			(#ASSIGN#88_0 (_architecture 0 0 88 (_process (_simple)
				(_target(15))
				(_sensitivity(8)(27)(26)(19)(5)(22)(9)(18)(4)(21)(7)(13))
			)))
			(#ASSIGN#89_1 (_architecture 1 0 89 (_process (_alias ((PWRint)(DCORIFG)))(_simple)
				(_target(3))
				(_sensitivity(27))
			)))
			(#ASSIGN#90_2 (_architecture 2 0 90 (_process (_alias ((orFLGs)(Enc15flg)(Enc133flg)(Hme15flg)(Hme133flg)(Enc05flg)(Enc033flg)(Hme05flg)(Hme033flg)))(_simple)
				(_target(28))
				(_sensitivity(19)(5)(22)(9)(18)(4)(21)(7))
			)))
			(#ASSIGN#92_3 (_architecture 3 0 92 (_process (_alias ((Enc15ctl)(ctrlr(7))))(_simple)
				(_target(24))
				(_sensitivity(25(7)))
			)))
			(#ASSIGN#93_4 (_architecture 4 0 93 (_process (_alias ((Enc133ctl)(ctrlr(6))))(_simple)
				(_target(12))
				(_sensitivity(25(6)))
			)))
			(#ASSIGN#94_5 (_architecture 5 0 94 (_process (_alias ((Hme15ctl)(ctrlr(5))))(_simple)
				(_target(1))
				(_sensitivity(25(5)))
			)))
			(#ASSIGN#95_6 (_architecture 6 0 95 (_process (_alias ((Hme133ctl)(ctrlr(4))))(_simple)
				(_target(17))
				(_sensitivity(25(4)))
			)))
			(#ASSIGN#96_7 (_architecture 7 0 96 (_process (_alias ((Enc05ctl)(ctrlr(3))))(_simple)
				(_target(23))
				(_sensitivity(25(3)))
			)))
			(#ASSIGN#97_8 (_architecture 8 0 97 (_process (_alias ((Enc033ctl)(ctrlr(2))))(_simple)
				(_target(11))
				(_sensitivity(25(2)))
			)))
			(#ASSIGN#98_9 (_architecture 9 0 98 (_process (_alias ((Hme05ctl)(ctrlr(1))))(_simple)
				(_target(0))
				(_sensitivity(25(1)))
			)))
			(#ASSIGN#99_10 (_architecture 10 0 99 (_process (_alias ((Hme033ctl)(ctrlr(0))))(_simple)
				(_target(16))
				(_sensitivity(25(0)))
			)))
			(#ALWAYS#101_11 (_architecture 11 0 101 (_process 
				(_target(27)(26))
				(_read(6)(2)(20)(14(1))(28)(27)(19)(5)(22)(9)(18)(4)(21)(7))
			)))
			(#ALWAYS#112_12 (_architecture 12 0 112 (_process 
				(_target(25))
				(_read(6)(2)(10)(14))
			)))
		)
	)
	
	
	(_defparam
	)
	(_model . PWRreg 14 -1)

)
I 000048 55 6214          1078524615345 Lswitch
(_unit VERILOG 6.349C.6.256 (Lswitch 0 25 (Lswitch 0 25 ))
	(_version v32)
	(_time 1078524614993 2004.03.05 14:10:14)
	(_source (\./src/lswitch.v\ VERILOG (\./src/lswitch.v\ VERILOG)))
	(_use (std(standard))(vl(verilog_logic)))
	(_base (E 9))
	(_entity
		(_time 1078524614993)
		(_use )
	)
	(_timescale 1ps 1ps)
	(_parameters    dbg   accs  )
	(_attribute nb_assign )
	(_object
		(_port (_internal DCORIFGr ~wire 0 25 (_architecture (_in ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal DIR1 ~wire 0 25 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_type (_internal ~[7:0]wire~ 0 25 (_array ~wire ((_downto (i 7) (i 0))))))
		(_port (_internal inDATA ~[7:0]wire~ 0 25 (_architecture (_in ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal RLS0 ~wire 0 25 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal outDATA ~[7:0]wire~ 0 25 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal RLS1 ~wire 0 25 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal Reset ~wire 0 25 (_architecture (_in ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal fBRK0 ~wire 0 25 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal DCORIFGw ~wire 0 25 (_architecture (_in ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal Brake0 ~wire 0 25 (_architecture (_in ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal FLS0 ~wire 0 25 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal fBRK1 ~wire 0 25 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal Brake1 ~wire 0 25 (_architecture (_in ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal FLS1 ~wire 0 25 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal Mclk ~wire 0 25 (_architecture (_in ))) (_net  ) (_nonbaction) (_noforceassign))
		(_port (_internal LSwitchInt ~wire 0 25 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal Home0 ~wire 0 25 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal Home1 ~wire 0 25 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal DCORLIMITSr ~wire 0 25 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal DIR0 ~wire 0 25 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal DCORIFG ~reg 0 73 (_architecture (_uni ))) (_reg ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal fBRK0r ~reg 0 74 (_architecture (_uni ))) (_reg ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal fBRK1r ~reg 0 74 (_architecture (_uni ))) (_reg ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal trip0 ~wire 0 75 (_architecture (_uni ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal trip1 ~wire 0 75 (_architecture (_uni ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_subprogram
			

		)
		(_type (_external ~wire (vl verilog_logic wire)))
		(_type (_external ~reg (vl verilog_logic reg)))
		(_type (_external ~event (vl verilog_logic event)))
		(_type (_external ~wand (vl verilog_logic wand)))
		(_type (_external ~wor (vl verilog_logic wor)))
		(_type (_external ~tri1 (vl verilog_logic tri1)))
		(_type (_external ~tri0 (vl verilog_logic tri0)))
		(_type (_external ~trireg (vl verilog_logic trireg)))
		(_type (_external ~supply0 (vl verilog_logic supply0)))
		(_type (_external ~supply1 (vl verilog_logic supply1)))
		(_type (_external ~real (vl verilog_logic real)))
		(_type (_external ~realtime (vl verilog_logic realtime)))
		(_type (_external ~tri (vl verilog_logic tri)))
		(_type (_external ~triand (vl verilog_logic triand)))
		(_type (_external ~trior (vl verilog_logic trior)))
		(_type (_external ~bit (vl verilog_logic bit)))
		(_type (_external ~extstd.standard.integer (std standard integer)))
		(_type (_external ~extstd.standard.bit (std standard bit)))
		(_process
			(#ASSIGN#77_0 (_architecture 0 0 77 (_process (_simple)
				(_target(4))
				(_sensitivity(18)(22)(17)(13)(5)(21)(16)(10)(3))
			)))
			(#ASSIGN#79_1 (_architecture 1 0 79 (_process (_alias ((trip1)(DIR1)(FLS1)(DIR1)(RLS1)))(_simple)
				(_target(24))
				(_sensitivity(1)(13)(5))
			)))
			(#ASSIGN#80_2 (_architecture 2 0 80 (_process (_alias ((trip0)(DIR0)(FLS0)(DIR0)(RLS0)))(_simple)
				(_target(23))
				(_sensitivity(19)(10)(3))
			)))
			(#ASSIGN#82_3 (_architecture 3 0 82 (_process (_alias ((fBRK1)(fBRK1r)))(_simple)
				(_target(11))
				(_sensitivity(22))
			)))
			(#ASSIGN#83_4 (_architecture 4 0 83 (_process (_alias ((fBRK0)(fBRK0r)))(_simple)
				(_target(7))
				(_sensitivity(21))
			)))
			(#ASSIGN#85_5 (_architecture 5 0 85 (_process (_alias ((LSwitchInt)(DCORIFG)))(_simple)
				(_target(15))
				(_sensitivity(20))
			)))
			(#ALWAYS#87_6 (_architecture 6 0 87 (_process 
				(_target(20))
				(_read(14)(6)(24)(23)(8)(2(4))(20))
			)))
			(#ALWAYS#98_7 (_architecture 7 0 98 (_process 
				(_target(22)(21))
				(_read(14)(6)(24)(12)(22)(23)(9)(21))
			)))
		)
	)
	
	
	(_defparam
	)
	(_model . Lswitch 9 -1)

)
I 000051 55 3250          1078524615349 I2CAddress
(_unit VERILOG 6.349C.6.256 (I2CAddress 0 25 (I2CAddress 0 25 ))
	(_version v32)
	(_time 1078524614993 2004.03.05 14:10:14)
	(_source (\./src/i2caddress.v\ VERILOG (\./src/i2caddress.v\ VERILOG)))
	(_use (std(standard))(vl(verilog_logic)))
	(_base (E 9))
	(_entity
		(_time 1078524614993)
		(_use )
	)
	(_timescale 1ps 1ps)
	(_parameters    dbg   accs  )
	(_attribute )
	(_object
		(_port (_internal MotorIn0 ~wire 0 25 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal DCORCONFIGr ~wire 0 25 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal MotorIn1 ~wire 0 25 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_type (_internal ~[5:0]wire~ 0 25 (_array ~wire ((_downto (i 5) (i 0))))))
		(_port (_internal I2CS ~[5:0]wire~ 0 25 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_type (_internal ~[7:0]wire~ 0 25 (_array ~wire ((_downto (i 7) (i 0))))))
		(_port (_internal outDATA ~[7:0]wire~ 0 25 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_subprogram
			

		)
		(_type (_external ~wire (vl verilog_logic wire)))
		(_type (_external ~reg (vl verilog_logic reg)))
		(_type (_external ~event (vl verilog_logic event)))
		(_type (_external ~wand (vl verilog_logic wand)))
		(_type (_external ~wor (vl verilog_logic wor)))
		(_type (_external ~tri1 (vl verilog_logic tri1)))
		(_type (_external ~tri0 (vl verilog_logic tri0)))
		(_type (_external ~trireg (vl verilog_logic trireg)))
		(_type (_external ~supply0 (vl verilog_logic supply0)))
		(_type (_external ~supply1 (vl verilog_logic supply1)))
		(_type (_external ~real (vl verilog_logic real)))
		(_type (_external ~realtime (vl verilog_logic realtime)))
		(_type (_external ~tri (vl verilog_logic tri)))
		(_type (_external ~triand (vl verilog_logic triand)))
		(_type (_external ~trior (vl verilog_logic trior)))
		(_type (_external ~bit (vl verilog_logic bit)))
		(_type (_external ~extstd.standard.integer (std standard integer)))
		(_type (_external ~extstd.standard.bit (std standard bit)))
		(_process
			(#ASSIGN#43_0 (_architecture 0 0 43 (_process (_simple)
				(_target(4(0)))
				(_sensitivity(1)(3(0)))
			)))
			(#ASSIGN#44_1 (_architecture 1 0 44 (_process (_simple)
				(_target(4(1)))
				(_sensitivity(1)(3(1)))
			)))
			(#ASSIGN#45_2 (_architecture 2 0 45 (_process (_simple)
				(_target(4(2)))
				(_sensitivity(1)(3(2)))
			)))
			(#ASSIGN#46_3 (_architecture 3 0 46 (_process (_simple)
				(_target(4(3)))
				(_sensitivity(1)(3(3)))
			)))
			(#ASSIGN#47_4 (_architecture 4 0 47 (_process (_simple)
				(_target(4(4)))
				(_sensitivity(1)(3(4)))
			)))
			(#ASSIGN#48_5 (_architecture 5 0 48 (_process (_simple)
				(_target(4(5)))
				(_sensitivity(1)(3(5)))
			)))
			(#ASSIGN#49_6 (_architecture 6 0 49 (_process (_simple)
				(_target(4(6)))
				(_sensitivity(1)(0))
			)))
			(#ASSIGN#50_7 (_architecture 7 0 50 (_process (_simple)
				(_target(4(7)))
				(_sensitivity(1)(2))
			)))
		)
	)
	
	
	(_defparam
	)
	(_model . I2CAddress 9 -1)

)
V 000051 55 4704          1078524615353 PWMcontrol
(_unit VERILOG 6.349C.6.256 (PWMcontrol 0 32 (PWMcontrol 0 32 ))
	(_version v32)
	(_time 1078524614993 2004.03.05 14:10:14)
	(_source (\./compile/PWMcontrol.v\ VERILOG (\./compile/pwmcontrol.v\ VERILOG)))
	(_use (std(standard))(vl(verilog_logic)))
	(_base (E 1))
	(_entity
		(_time 1078524614993)
		(_use )
	)
	(_timescale 1ns 1ns)
	(_parameters    dbg   accs  )
	(_attribute )
	(_object
		(_port (_internal Brake1 ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Brake2 ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal DIR1 ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal DIR2 ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal HBRK1 ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal HBRK2 ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PWM1 ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PWM2 ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal fBRK1 ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal fBRK2 ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PAH1 ~wire 0 33 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PAH2 ~wire 0 33 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PAL1 ~wire 0 33 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PAL2 ~wire 0 33 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PBH1 ~wire 0 33 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PBH2 ~wire 0 33 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PBL1 ~wire 0 33 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PBL2 ~wire 0 33 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_subprogram
			

		)
		(_type (_external ~wire (vl verilog_logic wire)))
		(_type (_external ~reg (vl verilog_logic reg)))
		(_type (_external ~event (vl verilog_logic event)))
		(_type (_external ~wand (vl verilog_logic wand)))
		(_type (_external ~wor (vl verilog_logic wor)))
		(_type (_external ~tri1 (vl verilog_logic tri1)))
		(_type (_external ~tri0 (vl verilog_logic tri0)))
		(_type (_external ~trireg (vl verilog_logic trireg)))
		(_type (_external ~supply0 (vl verilog_logic supply0)))
		(_type (_external ~supply1 (vl verilog_logic supply1)))
		(_type (_external ~real (vl verilog_logic real)))
		(_type (_external ~realtime (vl verilog_logic realtime)))
		(_type (_external ~tri (vl verilog_logic tri)))
		(_type (_external ~triand (vl verilog_logic triand)))
		(_type (_external ~trior (vl verilog_logic trior)))
		(_type (_external ~bit (vl verilog_logic bit)))
		(_type (_external ~extstd.standard.integer (std standard integer)))
		(_type (_external ~extstd.standard.bit (std standard bit)))
	)
	
	
	(_defparam
	)
	(_scope
	)
	(_instantiation U1 0 75 (_entity .  PWMtranslator)
		(_port
			((Brake) (Brake1))
			((DIR) (DIR1))
			((HBRK) (HBRK1))
			((PAH) (PAH1))
			((PAL) (PAL1))
			((PBH) (PBH1))
			((PBL) (PBL1))
			((PWM) (PWM1))
			((fBRK) (fBRK1))
		)
		(_strength)
	)
	(_instantiation U2 0 90 (_entity .  PWMtranslator)
		(_port
			((Brake) (Brake2))
			((DIR) (DIR2))
			((HBRK) (HBRK2))
			((PAH) (PAH2))
			((PAL) (PAL2))
			((PBH) (PBH2))
			((PBL) (PBL2))
			((PWM) (PWM2))
			((fBRK) (fBRK2))
		)
		(_strength)
	)
	(_model . PWMcontrol 1 -1)

)
I 000049 55 5191          1078524615357 MISCouts
(_unit VERILOG 6.349C.6.256 (MISCouts 0 25 (MISCouts 0 25 ))
	(_version v32)
	(_time 1078524614993 2004.03.05 14:10:14)
	(_source (\./src/miscouts.v\ VERILOG (\./src/miscouts.v\ VERILOG)))
	(_use (std(standard))(vl(verilog_logic)))
	(_base (E 11))
	(_entity
		(_time 1078524614993)
		(_use )
	)
	(_timescale 1ps 1ps)
	(_parameters    dbg   accs  )
	(_attribute nb_assign )
	(_object
		(_type (_internal ~[7:0]wire~ 0 25 (_array ~wire ((_downto (i 7) (i 0))))))
		(_port (_internal inDATA ~[7:0]wire~ 0 25 (_architecture (_in ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal Reset ~wire 0 25 (_architecture (_in ))) (_net  ) (_nonbaction) (_noforceassign))
		(_port (_internal LED1 ~wire 0 25 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal LightSense ~wire 0 25 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal GP_Motor0_1 ~wire 0 25 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal LED2 ~wire 0 25 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal DCOROUTw ~wire 0 25 (_architecture (_in ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal Mclk ~wire 0 25 (_architecture (_in ))) (_net  ) (_nonbaction) (_noforceassign))
		(_port (_internal GP_Motor1_1 ~wire 0 25 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal LED3 ~wire 0 25 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal LED4 ~wire 0 25 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal MTRpwrn ~wire 0 25 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal LED5 ~wire 0 25 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal MTRpwr ~wire 0 25 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_type (_internal ~[7:0]reg~ 0 63 (_array ~reg ((_downto (i 7) (i 0))))))
		(_signal (_internal MISCr ~[7:0]reg~ 0 63 (_architecture (_uni ))) (_reg ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_subprogram
			

		)
		(_type (_external ~wire (vl verilog_logic wire)))
		(_type (_external ~reg (vl verilog_logic reg)))
		(_type (_external ~event (vl verilog_logic event)))
		(_type (_external ~wand (vl verilog_logic wand)))
		(_type (_external ~wor (vl verilog_logic wor)))
		(_type (_external ~tri1 (vl verilog_logic tri1)))
		(_type (_external ~tri0 (vl verilog_logic tri0)))
		(_type (_external ~trireg (vl verilog_logic trireg)))
		(_type (_external ~supply0 (vl verilog_logic supply0)))
		(_type (_external ~supply1 (vl verilog_logic supply1)))
		(_type (_external ~real (vl verilog_logic real)))
		(_type (_external ~realtime (vl verilog_logic realtime)))
		(_type (_external ~tri (vl verilog_logic tri)))
		(_type (_external ~triand (vl verilog_logic triand)))
		(_type (_external ~trior (vl verilog_logic trior)))
		(_type (_external ~bit (vl verilog_logic bit)))
		(_type (_external ~extstd.standard.integer (std standard integer)))
		(_type (_external ~extstd.standard.bit (std standard bit)))
		(_process
			(#ASSIGN#65_0 (_architecture 0 0 65 (_process (_alias ((LED1)(MISCr(0))(LightSense)))(_simple)
				(_target(2))
				(_sensitivity(14(0))(3))
			)))
			(#ASSIGN#66_1 (_architecture 1 0 66 (_process (_alias ((LED2)(MISCr(1))(LightSense)))(_simple)
				(_target(5))
				(_sensitivity(14(1))(3))
			)))
			(#ASSIGN#67_2 (_architecture 2 0 67 (_process (_alias ((LED3)(MISCr(2))(LightSense)))(_simple)
				(_target(9))
				(_sensitivity(14(2))(3))
			)))
			(#ASSIGN#68_3 (_architecture 3 0 68 (_process (_alias ((LED4)(MISCr(3))(LightSense)))(_simple)
				(_target(10))
				(_sensitivity(14(3))(3))
			)))
			(#ASSIGN#69_4 (_architecture 4 0 69 (_process (_alias ((LED5)(MISCr(4))(LightSense)))(_simple)
				(_target(12))
				(_sensitivity(14(4))(3))
			)))
			(#ASSIGN#70_5 (_architecture 5 0 70 (_process (_alias ((GP_Motor0_1)(MISCr(5))))(_simple)
				(_target(4))
				(_sensitivity(14(5)))
			)))
			(#ASSIGN#71_6 (_architecture 6 0 71 (_process (_alias ((GP_Motor1_1)(MISCr(6))))(_simple)
				(_target(8))
				(_sensitivity(14(6)))
			)))
			(#ASSIGN#72_7 (_architecture 7 0 72 (_process (_alias ((MTRpwr)(MISCr(7))))(_simple)
				(_target(13))
				(_sensitivity(14(7)))
			)))
			(#ASSIGN#73_8 (_architecture 8 0 73 (_process (_alias ((MTRpwrn)(MISCr(7))))(_simple)
				(_target(11))
				(_sensitivity(14(7)))
			)))
			(#ALWAYS#75_9 (_architecture 9 0 75 (_process 
				(_target(14))
				(_read(7)(1)(6)(0)(14))
			)))
		)
	)
	
	
	(_defparam
	)
	(_model . MISCouts 11 -1)

)
I 000047 55 3614          1078524615361 Decode
(_unit VERILOG 6.349C.6.256 (Decode 0 23 (Decode 0 23 ))
	(_version v32)
	(_time 1078524614993 2004.03.05 14:10:14)
	(_source (\./compile/Qdecode.v\ VERILOG (\./compile/qdecode.v\ VERILOG)))
	(_use (std(standard))(vl(verilog_logic)))
	(_base (E 5))
	(_entity
		(_time 1078524614993)
		(_use )
	)
	(_timescale 1ns 1ps)
	(_parameters    dbg   accs  )
	(_attribute nb_assign )
	(_object
		(_port (_internal Reset ~wire 0 23 (_architecture (_in ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal Sclk ~wire 0 23 (_architecture (_in ))) (_net  ) (_nonbaction) (_noforceassign))
		(_port (_internal ce ~wire 0 23 (_architecture (_inout ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal phaseA ~wire 0 23 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal phaseB ~wire 0 23 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal updown ~wire 0 23 (_architecture (_inout ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal ino_ce ~reg 0 34 (_architecture (_uni ))) (_reg ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal ino_updown ~reg 0 38 (_architecture (_uni ))) (_reg ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_type (_internal ~[3:0]reg~ 0 52 (_array ~reg ((_downto (i 3) (i 0))))))
		(_signal (_internal CurrState_Sreg0 ~[3:0]reg~ 0 52 (_architecture (_uni ))) (_reg ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal NextState_Sreg0 ~[3:0]reg~ 0 54 (_architecture (_uni ))) (_reg ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_subprogram
			

		)
		(_type (_external ~wire (vl verilog_logic wire)))
		(_type (_external ~reg (vl verilog_logic reg)))
		(_type (_external ~event (vl verilog_logic event)))
		(_type (_external ~wand (vl verilog_logic wand)))
		(_type (_external ~wor (vl verilog_logic wor)))
		(_type (_external ~tri1 (vl verilog_logic tri1)))
		(_type (_external ~tri0 (vl verilog_logic tri0)))
		(_type (_external ~trireg (vl verilog_logic trireg)))
		(_type (_external ~supply0 (vl verilog_logic supply0)))
		(_type (_external ~supply1 (vl verilog_logic supply1)))
		(_type (_external ~real (vl verilog_logic real)))
		(_type (_external ~realtime (vl verilog_logic realtime)))
		(_type (_external ~tri (vl verilog_logic tri)))
		(_type (_external ~triand (vl verilog_logic triand)))
		(_type (_external ~trior (vl verilog_logic trior)))
		(_type (_external ~bit (vl verilog_logic bit)))
		(_type (_external ~extstd.standard.integer (std standard integer)))
		(_type (_external ~extstd.standard.bit (std standard bit)))
		(_process
			(#ASSIGN#57_0 (_architecture 0 0 57 (_process (_alias ((updown)(CurrState_Sreg0(3))))(_simple)
				(_target(5))
				(_sensitivity(8(3)))
			)))
			(#ASSIGN#58_1 (_architecture 1 0 58 (_process (_alias ((ce)(CurrState_Sreg0(2))))(_simple)
				(_target(2))
				(_sensitivity(8(2)))
			)))
			(#ALWAYS#67_2 (_architecture 2 0 67 (_process 
				(_target(9))
				(_read)
				(_sensitivity(3)(4)(8))
			)))
			(#ALWAYS#150_3 (_architecture 3 0 150 (_process 
				(_target(8))
				(_read(1)(0)(9))
			)))
		)
	)
	
	
	(_defparam
	)
	(_scope
		(_unit Sreg0_NextState begin 0 68
		)
		(_unit Sreg0_CurrentState begin 0 151
		)
	)
	(_model . Decode 5 -1)

)
I 000048 55 2998          1078524615365 Counter
(_unit VERILOG 6.349C.6.256 (Counter 0 25 (Counter 0 25 ))
	(_version v32)
	(_time 1078524614993 2004.03.05 14:10:14)
	(_source (\./src/counter.v\ VERILOG (\./src/counter.v\ VERILOG)))
	(_use (std(standard))(vl(verilog_logic)))
	(_base (E 3))
	(_entity
		(_time 1078524614993)
		(_use )
	)
	(_timescale 1ps 1ps)
	(_parameters    dbg   accs  )
	(_attribute nb_assign )
	(_object
		(_port (_internal Zero ~wire 0 25 (_architecture (_in ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal ce ~wire 0 25 (_architecture (_in ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_type (_internal ~[23:0]wire~ 0 25 (_array ~wire ((_downto (i 23) (i 0))))))
		(_port (_internal count ~[23:0]wire~ 0 25 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal Reset ~wire 0 25 (_architecture (_in ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal updown ~wire 0 25 (_architecture (_in ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal Sclk ~wire 0 25 (_architecture (_in ))) (_net  ) (_nonbaction) (_noforceassign))
		(_port (_internal sense ~wire 0 25 (_architecture (_in ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_type (_internal ~[23:0]reg~ 0 48 (_array ~reg ((_downto (i 23) (i 0))))))
		(_signal (_internal location ~[23:0]reg~ 0 48 (_architecture (_uni ))) (_reg ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_subprogram
			

		)
		(_type (_external ~wire (vl verilog_logic wire)))
		(_type (_external ~reg (vl verilog_logic reg)))
		(_type (_external ~event (vl verilog_logic event)))
		(_type (_external ~wand (vl verilog_logic wand)))
		(_type (_external ~wor (vl verilog_logic wor)))
		(_type (_external ~tri1 (vl verilog_logic tri1)))
		(_type (_external ~tri0 (vl verilog_logic tri0)))
		(_type (_external ~trireg (vl verilog_logic trireg)))
		(_type (_external ~supply0 (vl verilog_logic supply0)))
		(_type (_external ~supply1 (vl verilog_logic supply1)))
		(_type (_external ~real (vl verilog_logic real)))
		(_type (_external ~realtime (vl verilog_logic realtime)))
		(_type (_external ~tri (vl verilog_logic tri)))
		(_type (_external ~triand (vl verilog_logic triand)))
		(_type (_external ~trior (vl verilog_logic trior)))
		(_type (_external ~bit (vl verilog_logic bit)))
		(_type (_external ~extstd.standard.integer (std standard integer)))
		(_type (_external ~extstd.standard.bit (std standard bit)))
		(_process
			(#ASSIGN#49_0 (_architecture 0 0 49 (_process (_alias ((count)(location)))(_simple)
				(_target(2))
				(_sensitivity(7))
			)))
			(#ALWAYS#51_1 (_architecture 1 0 51 (_process 
				(_target(7))
				(_read(5)(3)(0)(1)(4)(6)(7))
			)))
		)
	)
	
	
	(_defparam
	)
	(_model . Counter 3 -1)

)
I 000048 55 4141          1078524615369 Holdreg
(_unit VERILOG 6.349C.6.256 (Holdreg 0 25 (Holdreg 0 25 ))
	(_version v32)
	(_time 1078524614993 2004.03.05 14:10:14)
	(_source (\./src/holdreg.v\ VERILOG (\./src/holdreg.v\ VERILOG)))
	(_use (std(standard))(vl(verilog_logic)))
	(_base (E 4))
	(_entity
		(_time 1078524614993)
		(_use )
	)
	(_timescale 1ps 1ps)
	(_parameters    dbg   accs  )
	(_attribute nb_assign )
	(_object
		(_port (_internal DCOR0CNTLOWr ~wire 0 25 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal DCOR1CNTLOWr ~wire 0 25 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_type (_internal ~[7:0]wire~ 0 25 (_array ~wire ((_downto (i 7) (i 0))))))
		(_port (_internal outDATA ~[7:0]wire~ 0 25 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_type (_internal ~[23:0]wire~ 0 25 (_array ~wire ((_downto (i 23) (i 0))))))
		(_port (_internal ch0in ~[23:0]wire~ 0 25 (_architecture (_in ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal ch1in ~[23:0]wire~ 0 25 (_architecture (_in ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal Reset ~wire 0 25 (_architecture (_in ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal Sclk ~wire 0 25 (_architecture (_in ))) (_net  ) (_nonbaction) (_noforceassign))
		(_port (_internal DCOR0CNTMIDr ~wire 0 25 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal DCOR1CNTMIDr ~wire 0 25 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal DCOR0CNTHIGHr ~wire 0 25 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal DCOR1CNTHIGHr ~wire 0 25 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal RDedge ~reg 0 70 (_architecture (_uni ))) (_reg ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_type (_internal ~[23:0]reg~ 0 72 (_array ~reg ((_downto (i 23) (i 0))))))
		(_signal (_internal holdingreg ~[23:0]reg~ 0 72 (_architecture (_uni ))) (_reg ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal interDATA ~[7:0]wire~ 0 73 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_subprogram
			

		)
		(_type (_external ~wire (vl verilog_logic wire)))
		(_type (_external ~reg (vl verilog_logic reg)))
		(_type (_external ~event (vl verilog_logic event)))
		(_type (_external ~wand (vl verilog_logic wand)))
		(_type (_external ~wor (vl verilog_logic wor)))
		(_type (_external ~tri1 (vl verilog_logic tri1)))
		(_type (_external ~tri0 (vl verilog_logic tri0)))
		(_type (_external ~trireg (vl verilog_logic trireg)))
		(_type (_external ~supply0 (vl verilog_logic supply0)))
		(_type (_external ~supply1 (vl verilog_logic supply1)))
		(_type (_external ~real (vl verilog_logic real)))
		(_type (_external ~realtime (vl verilog_logic realtime)))
		(_type (_external ~tri (vl verilog_logic tri)))
		(_type (_external ~triand (vl verilog_logic triand)))
		(_type (_external ~trior (vl verilog_logic trior)))
		(_type (_external ~bit (vl verilog_logic bit)))
		(_type (_external ~extstd.standard.integer (std standard integer)))
		(_type (_external ~extstd.standard.bit (std standard bit)))
		(_process
			(#ASSIGN#80_0 (_architecture 0 0 80 (_process (_simple)
				(_target(13))
				(_sensitivity(0)(1)(12(d_7_0))(7)(8)(12(d_15_8))(9)(10)(12(d_23_16)))
			)))
			(#ASSIGN#82_1 (_architecture 1 0 82 (_process (_alias ((outDATA)(interDATA)))(_simple)
				(_target(2))
				(_sensitivity(13))
			)))
			(#ALWAYS#84_2 (_architecture 2 0 84 (_process 
				(_target(11)(12))
				(_read(6)(0)(1)(5)(11)(3)(4))
			)))
		)
	)
	
	
	(_defparam
	)
	(_model . Holdreg 4 -1)

)
I 000051 55 10303         1078524615373 HomeConfig
(_unit VERILOG 6.349C.6.256 (HomeConfig 0 25 (HomeConfig 0 25 ))
	(_version v32)
	(_time 1078524614993 2004.03.05 14:10:14)
	(_source (\./src/homeconfig.v\ VERILOG (\./src/homeconfig.v\ VERILOG)))
	(_use (std(standard))(vl(verilog_logic)))
	(_base (E 11))
	(_entity
		(_time 1078524614993)
		(_use )
	)
	(_timescale 1ps 1ps)
	(_parameters    dbg   accs  )
	(_attribute nb_assign )
	(_object
		(_port (_internal Tfound0 ~wire 0 25 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal Tfound1 ~wire 0 25 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal DCOR0THRESLOWr ~wire 0 25 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal DCOR1THRESLOWr ~wire 0 25 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal Reset ~wire 0 25 (_architecture (_in ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_type (_internal ~[15:0]wire~ 0 25 (_array ~wire ((_downto (i 15) (i 0))))))
		(_port (_internal Channel0 ~[15:0]wire~ 0 25 (_architecture (_in ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal Channel1 ~[15:0]wire~ 0 25 (_architecture (_in ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal DCOR0THRESMIDr ~wire 0 25 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal DCOR1THRESMIDr ~wire 0 25 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal Sclk ~wire 0 25 (_architecture (_in ))) (_net  ) (_nonbaction) (_noforceassign))
		(_port (_internal sense0 ~wire 0 25 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal sense1 ~wire 0 25 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal DCORIFGr ~wire 0 25 (_architecture (_in ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Zero0 ~wire 0 25 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_type (_internal ~[7:0]wire~ 0 25 (_array ~wire ((_downto (i 7) (i 0))))))
		(_port (_internal inDATA ~[7:0]wire~ 0 25 (_architecture (_in ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal Zero1 ~wire 0 25 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal outDATA ~[7:0]wire~ 0 25 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal Hfound0 ~wire 0 25 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal Hfound1 ~wire 0 25 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal DCORIFGw ~wire 0 25 (_architecture (_in ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal MotorIn0 ~wire 0 25 (_architecture (_in ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal Home_Encoder0 ~wire 0 25 (_architecture (_in ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal DCORENCCTLw ~wire 0 25 (_architecture (_in ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal MotorIn1 ~wire 0 25 (_architecture (_in ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal Home_Encoder1 ~wire 0 25 (_architecture (_in ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal RF1r ~reg 0 84 (_architecture (_uni ))) (_reg ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal E1r ~reg 0 86 (_architecture (_uni ))) (_reg ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal RF0r ~reg 0 88 (_architecture (_uni ))) (_reg ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal E0r ~reg 0 90 (_architecture (_uni ))) (_reg ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal LatchEdge0r ~reg 0 92 (_architecture (_uni ))) (_reg ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal LatchEdge1r ~reg 0 93 (_architecture (_uni ))) (_reg ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal sense0r ~reg 0 95 (_architecture (_uni ))) (_reg ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal sense1r ~reg 0 96 (_architecture (_uni ))) (_reg ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal HE0stater ~reg 0 99 (_architecture (_uni ))) (_reg ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal HE0statelastr ~reg 0 100 (_architecture (_uni ))) (_reg ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal HE1stater ~reg 0 101 (_architecture (_uni ))) (_reg ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal HE1statelastr ~reg 0 102 (_architecture (_uni ))) (_reg ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal Hfound0r ~reg 0 105 (_architecture (_uni ))) (_reg ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal Hfound1r ~reg 0 106 (_architecture (_uni ))) (_reg ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal Zero0r ~reg 0 108 (_architecture (_uni ))) (_reg ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal Zero1r ~reg 0 109 (_architecture (_uni ))) (_reg ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal Tfound0r ~reg 0 112 (_architecture (_uni ))) (_reg ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal Tfound1r ~reg 0 113 (_architecture (_uni ))) (_reg ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_type (_internal ~[15:0]reg~ 0 116 (_array ~reg ((_downto (i 15) (i 0))))))
		(_signal (_internal Latch0r ~[15:0]reg~ 0 116 (_architecture (_uni ))) (_reg ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal Latch1r ~[15:0]reg~ 0 117 (_architecture (_uni ))) (_reg ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal InEdge0r ~reg 0 120 (_architecture (_uni ))) (_reg ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal InEdge1r ~reg 0 121 (_architecture (_uni ))) (_reg ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_subprogram
			

		)
		(_type (_external ~wire (vl verilog_logic wire)))
		(_type (_external ~reg (vl verilog_logic reg)))
		(_type (_external ~event (vl verilog_logic event)))
		(_type (_external ~wand (vl verilog_logic wand)))
		(_type (_external ~wor (vl verilog_logic wor)))
		(_type (_external ~tri1 (vl verilog_logic tri1)))
		(_type (_external ~tri0 (vl verilog_logic tri0)))
		(_type (_external ~trireg (vl verilog_logic trireg)))
		(_type (_external ~supply0 (vl verilog_logic supply0)))
		(_type (_external ~supply1 (vl verilog_logic supply1)))
		(_type (_external ~real (vl verilog_logic real)))
		(_type (_external ~realtime (vl verilog_logic realtime)))
		(_type (_external ~tri (vl verilog_logic tri)))
		(_type (_external ~triand (vl verilog_logic triand)))
		(_type (_external ~trior (vl verilog_logic trior)))
		(_type (_external ~bit (vl verilog_logic bit)))
		(_type (_external ~extstd.standard.integer (std standard integer)))
		(_type (_external ~extstd.standard.bit (std standard bit)))
		(_process
			(#ASSIGN#127_0 (_architecture 0 0 127 (_process (_alias ((Zero0)(Zero0r)))(_simple)
				(_target(13))
				(_sensitivity(39))
			)))
			(#ASSIGN#128_1 (_architecture 1 0 128 (_process (_alias ((Zero1)(Zero1r)))(_simple)
				(_target(15))
				(_sensitivity(40))
			)))
			(#ASSIGN#132_2 (_architecture 2 0 132 (_process (_alias ((sense0)(sense0r)))(_simple)
				(_target(10))
				(_sensitivity(31))
			)))
			(#ASSIGN#133_3 (_architecture 3 0 133 (_process (_alias ((sense1)(sense1r)))(_simple)
				(_target(11))
				(_sensitivity(32))
			)))
			(#ASSIGN#135_4 (_architecture 4 0 135 (_process (_alias ((Hfound1)(Hfound1r)))(_simple)
				(_target(18))
				(_sensitivity(38))
			)))
			(#ASSIGN#136_5 (_architecture 5 0 136 (_process (_alias ((Hfound0)(Hfound0r)))(_simple)
				(_target(17))
				(_sensitivity(37))
			)))
			(#ASSIGN#137_6 (_architecture 6 0 137 (_process (_alias ((Tfound0)(Tfound0r)))(_simple)
				(_target(0))
				(_sensitivity(41))
			)))
			(#ASSIGN#138_7 (_architecture 7 0 138 (_process (_alias ((Tfound1)(Tfound1r)))(_simple)
				(_target(1))
				(_sensitivity(42))
			)))
			(#ASSIGN#145_8 (_architecture 8 0 145 (_process (_simple)
				(_target(16))
				(_sensitivity(2)(43(d_7_0))(7)(43(d_15_8))(3)(44(d_7_0))(8)(44(d_15_8)))
			)))
			(#ALWAYS#147_9 (_architecture 9 0 147 (_process 
				(_target(33)(34)(35)(36)(45)(46)(32)(30)(26)(25)(31)(29)(28)(27)(43)(44)(42)(41)(38)(37)(39)(40))
				(_read(9)(21)(33)(24)(35)(20)(23)(4)(22)(14)(19)(14(d_6_5))(14(d_3_2))(27)(34)(17)(28)(37)(26)(25)(36)(18)(38)(0)(45)(29)(5)(41)(43)(1)(46)(30)(6)(42))
			)))
		)
	)
	
	
	(_defparam
	)
	(_model . HomeConfig 11 -1)

)
I 000054 55 3632          1078524615377 PWMtranslator
(_unit VERILOG 6.349C.6.256 (PWMtranslator 0 27 (PWMtranslator 0 27 ))
	(_version v32)
	(_time 1078524614993 2004.03.05 14:10:14)
	(_source (\./src/PWMtranslator.v\ VERILOG (\./src/pwmtranslator.v\ VERILOG)))
	(_use (std(standard))(vl(verilog_logic)))
	(_base (E 6))
	(_entity
		(_time 1078524614993)
		(_use )
	)
	(_timescale 1ps 1ps)
	(_parameters    dbg   accs  )
	(_attribute )
	(_object
		(_port (_internal PWM ~wire 0 27 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal fBRK ~wire 0 27 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal Brake ~wire 0 27 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal HBRK ~wire 0 27 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal PAH ~wire 0 27 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal PBH ~wire 0 27 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal PAL ~wire 0 27 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal PBL ~wire 0 27 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal DIR ~wire 0 27 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal BRK ~wire 0 55 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_subprogram
			

		)
		(_type (_external ~wire (vl verilog_logic wire)))
		(_type (_external ~reg (vl verilog_logic reg)))
		(_type (_external ~event (vl verilog_logic event)))
		(_type (_external ~wand (vl verilog_logic wand)))
		(_type (_external ~wor (vl verilog_logic wor)))
		(_type (_external ~tri1 (vl verilog_logic tri1)))
		(_type (_external ~tri0 (vl verilog_logic tri0)))
		(_type (_external ~trireg (vl verilog_logic trireg)))
		(_type (_external ~supply0 (vl verilog_logic supply0)))
		(_type (_external ~supply1 (vl verilog_logic supply1)))
		(_type (_external ~real (vl verilog_logic real)))
		(_type (_external ~realtime (vl verilog_logic realtime)))
		(_type (_external ~tri (vl verilog_logic tri)))
		(_type (_external ~triand (vl verilog_logic triand)))
		(_type (_external ~trior (vl verilog_logic trior)))
		(_type (_external ~bit (vl verilog_logic bit)))
		(_type (_external ~extstd.standard.integer (std standard integer)))
		(_type (_external ~extstd.standard.bit (std standard bit)))
		(_process
			(#ASSIGN#57_0 (_architecture 0 0 57 (_process (_alias ((BRK)(fBRK)(Brake)(HBRK)))(_simple)
				(_target(9))
				(_sensitivity(1)(2)(3))
			)))
			(#ASSIGN#64_1 (_architecture 1 0 64 (_process (_alias ((PAH)(PWM)(DIR)(BRK)))(_simple)
				(_target(4))
				(_sensitivity(0)(8)(9))
			)))
			(#ASSIGN#65_2 (_architecture 2 0 65 (_process (_alias ((PAL)(PWM)(DIR)(BRK)(PWM)(DIR)(BRK)))(_simple)
				(_target(6))
				(_sensitivity(0)(8)(9))
			)))
			(#ASSIGN#66_3 (_architecture 3 0 66 (_process (_alias ((PBH)(PWM)(DIR)(BRK)))(_simple)
				(_target(5))
				(_sensitivity(0)(8)(9))
			)))
			(#ASSIGN#67_4 (_architecture 4 0 67 (_process (_alias ((PBL)(PWM)(DIR)(BRK)(PWM)(DIR)(BRK)))(_simple)
				(_target(7))
				(_sensitivity(0)(8)(9))
			)))
		)
	)
	
	
	(_defparam
	)
	(_model . PWMtranslator 6 -1)

)
I 000050 55 2394          1078524615381 NegDetect
(_unit VERILOG 6.349C.6.256 (NegDetect 0 25 (NegDetect 0 25 ))
	(_version v32)
	(_time 1078524614993 2004.03.05 14:10:14)
	(_source (\./src/negdetect.v\ VERILOG (\./src/negdetect.v\ VERILOG)))
	(_use (std(standard))(vl(verilog_logic)))
	(_base (E 3))
	(_entity
		(_time 1078524614993)
		(_use )
	)
	(_timescale 1ps 1ps)
	(_parameters    dbg   accs  )
	(_attribute nb_assign )
	(_object
		(_port (_internal Line ~wire 0 25 (_architecture (_in ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal Ndetect ~wire 0 25 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal Mclk ~wire 0 25 (_architecture (_in ))) (_net  ) (_nonbaction) (_noforceassign))
		(_signal (_internal Line_last ~reg 0 39 (_architecture (_uni ))) (_reg ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal Ndetectr ~reg 0 40 (_architecture (_uni ))) (_reg ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_subprogram
			

		)
		(_type (_external ~wire (vl verilog_logic wire)))
		(_type (_external ~reg (vl verilog_logic reg)))
		(_type (_external ~event (vl verilog_logic event)))
		(_type (_external ~wand (vl verilog_logic wand)))
		(_type (_external ~wor (vl verilog_logic wor)))
		(_type (_external ~tri1 (vl verilog_logic tri1)))
		(_type (_external ~tri0 (vl verilog_logic tri0)))
		(_type (_external ~trireg (vl verilog_logic trireg)))
		(_type (_external ~supply0 (vl verilog_logic supply0)))
		(_type (_external ~supply1 (vl verilog_logic supply1)))
		(_type (_external ~real (vl verilog_logic real)))
		(_type (_external ~realtime (vl verilog_logic realtime)))
		(_type (_external ~tri (vl verilog_logic tri)))
		(_type (_external ~triand (vl verilog_logic triand)))
		(_type (_external ~trior (vl verilog_logic trior)))
		(_type (_external ~bit (vl verilog_logic bit)))
		(_type (_external ~extstd.standard.integer (std standard integer)))
		(_type (_external ~extstd.standard.bit (std standard bit)))
		(_process
			(#ASSIGN#42_0 (_architecture 0 0 42 (_process (_alias ((Ndetect)(Ndetectr)))(_simple)
				(_target(1))
				(_sensitivity(4))
			)))
			(#ALWAYS#44_1 (_architecture 1 0 44 (_process 
				(_target(3)(4))
				(_read(2)(0)(3))
			)))
		)
	)
	
	
	(_defparam
	)
	(_model . NegDetect 3 -1)

)
I 000051 55 3348          1078524615385 BitCounter
(_unit VERILOG 6.349C.6.256 (BitCounter 0 25 (BitCounter 0 25 ))
	(_version v32)
	(_time 1078524614993 2004.03.05 14:10:14)
	(_source (\./src/bitcounter.v\ VERILOG (\./src/bitcounter.v\ VERILOG)))
	(_use (std(standard))(vl(verilog_logic)))
	(_base (E 5))
	(_entity
		(_time 1078524614993)
		(_use )
	)
	(_timescale 1ps 1ps)
	(_parameters    dbg   accs  )
	(_attribute nb_assign )
	(_object
		(_type (_internal ~[7:0]wire~ 0 25 (_array ~wire ((_downto (i 7) (i 0))))))
		(_port (_internal outDATA ~[7:0]wire~ 0 25 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal DriveSCL ~wire 0 25 (_architecture (_inout ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal NegSCL ~wire 0 25 (_architecture (_in ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal NegInc ~wire 0 25 (_architecture (_in ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal SCLint ~wire 0 25 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal DCORI2CCNTr ~wire 0 25 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal SCLreset ~wire 0 25 (_architecture (_in ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal Mclk ~wire 0 25 (_architecture (_in ))) (_net  ) (_nonbaction) (_noforceassign))
		(_type (_internal ~[5:0]reg~ 0 50 (_array ~reg ((_downto (i 5) (i 0))))))
		(_signal (_internal counterr ~[5:0]reg~ 0 50 (_architecture (_uni ))) (_reg ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_subprogram
			

		)
		(_type (_external ~wire (vl verilog_logic wire)))
		(_type (_external ~reg (vl verilog_logic reg)))
		(_type (_external ~event (vl verilog_logic event)))
		(_type (_external ~wand (vl verilog_logic wand)))
		(_type (_external ~wor (vl verilog_logic wor)))
		(_type (_external ~tri1 (vl verilog_logic tri1)))
		(_type (_external ~tri0 (vl verilog_logic tri0)))
		(_type (_external ~trireg (vl verilog_logic trireg)))
		(_type (_external ~supply0 (vl verilog_logic supply0)))
		(_type (_external ~supply1 (vl verilog_logic supply1)))
		(_type (_external ~real (vl verilog_logic real)))
		(_type (_external ~realtime (vl verilog_logic realtime)))
		(_type (_external ~tri (vl verilog_logic tri)))
		(_type (_external ~triand (vl verilog_logic triand)))
		(_type (_external ~trior (vl verilog_logic trior)))
		(_type (_external ~bit (vl verilog_logic bit)))
		(_type (_external ~extstd.standard.integer (std standard integer)))
		(_type (_external ~extstd.standard.bit (std standard bit)))
		(_process
			(#ASSIGN#52_0 (_architecture 0 0 52 (_process (_simple)
				(_target(4))
				(_sensitivity(8))
			)))
			(#ASSIGN#54_1 (_architecture 1 0 54 (_process (_simple)
				(_target(1))
				(_sensitivity(8))
			)))
			(#ASSIGN#56_2 (_architecture 2 0 56 (_process (_simple)
				(_target(0))
				(_sensitivity(5)(8))
			)))
			(#ALWAYS#58_3 (_architecture 3 0 58 (_process 
				(_target(8))
				(_read(7)(6)(3)(2)(8))
			)))
		)
	)
	
	
	(_defparam
	)
	(_model . BitCounter 5 -1)

)
I 000045 55 7027          1078524615389 GPIO
(_unit VERILOG 6.349C.6.256 (GPIO 0 25 (GPIO 0 25 ))
	(_version v32)
	(_time 1078524614993 2004.03.05 14:10:14)
	(_source (\./src/GPIO.v\ VERILOG (\./src/gpio.v\ VERILOG)))
	(_use (std(standard))(vl(verilog_logic)))
	(_base (E 20))
	(_entity
		(_time 1078524614993)
		(_use )
	)
	(_timescale 1ps 1ps)
	(_parameters    dbg   accs  )
	(_attribute nb_assign )
	(_object
		(_type (_internal ~vector~0 0 52 (_array ~bit ((_uto (i 0) (i 0))))))
		(_generic (_internal ddrlow ~vector~0 0 52 \8'h0c\ (_entity -1 (_constant \8'h0c\))))
		(_type (_internal ~vector~1 0 53 (_array ~bit ((_uto (i 0) (i 0))))))
		(_generic (_internal ddrhigh ~vector~1 0 53 \8'h0d\ (_entity -1 (_constant \8'h0d\))))
		(_type (_internal ~vector~2 0 54 (_array ~bit ((_uto (i 0) (i 0))))))
		(_generic (_internal gpiolow ~vector~2 0 54 \8'h0e\ (_entity -1 (_constant \8'h0e\))))
		(_type (_internal ~vector~3 0 55 (_array ~bit ((_uto (i 0) (i 0))))))
		(_generic (_internal gpiohigh ~vector~3 0 55 \8'h0f\ (_entity -1 (_constant \8'h0f\))))
		(_type (_internal ~[7:0]wire~ 0 25 (_array ~wire ((_downto (i 7) (i 0))))))
		(_port (_internal inDATA ~[7:0]wire~ 0 25 (_architecture (_in ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal outDATA ~[7:0]wire~ 0 25 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Reset ~wire 0 25 (_architecture (_in ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal AS ~wire 0 25 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal RD ~wire 0 25 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal Mclk ~wire 0 25 (_architecture (_in ))) (_net  ) (_nonbaction) (_noforceassign))
		(_port (_internal WR ~wire 0 25 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal ADDR ~[7:0]wire~ 0 25 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_type (_internal ~[12:0]wire~ 0 25 (_array ~wire ((_downto (i 12) (i 0))))))
		(_port (_internal GPIO ~[12:0]wire~ 0 25 (_architecture (_inout ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_type (_internal ~[12:0]reg~ 0 57 (_array ~reg ((_downto (i 12) (i 0))))))
		(_signal (_internal GPIOr ~[12:0]reg~ 0 57 (_architecture (_uni ))) (_reg ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal DDR ~[12:0]reg~ 0 58 (_architecture (_uni ))) (_reg ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal enable ~wire 0 60 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal slcddrlow ~wire 0 61 (_architecture (_uni ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal slcddrhigh ~wire 0 62 (_architecture (_uni ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal slcgpiolow ~wire 0 63 (_architecture (_uni ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal slcgpiohigh ~wire 0 64 (_architecture (_uni ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_subprogram
			

		)
		(_type (_external ~wire (vl verilog_logic wire)))
		(_type (_external ~reg (vl verilog_logic reg)))
		(_type (_external ~event (vl verilog_logic event)))
		(_type (_external ~wand (vl verilog_logic wand)))
		(_type (_external ~wor (vl verilog_logic wor)))
		(_type (_external ~tri1 (vl verilog_logic tri1)))
		(_type (_external ~tri0 (vl verilog_logic tri0)))
		(_type (_external ~trireg (vl verilog_logic trireg)))
		(_type (_external ~supply0 (vl verilog_logic supply0)))
		(_type (_external ~supply1 (vl verilog_logic supply1)))
		(_type (_external ~real (vl verilog_logic real)))
		(_type (_external ~realtime (vl verilog_logic realtime)))
		(_type (_external ~tri (vl verilog_logic tri)))
		(_type (_external ~triand (vl verilog_logic triand)))
		(_type (_external ~trior (vl verilog_logic trior)))
		(_type (_external ~bit (vl verilog_logic bit)))
		(_type (_external ~extstd.standard.integer (std standard integer)))
		(_type (_external ~extstd.standard.bit (std standard bit)))
		(_process
			(#ASSIGN#70_0 (_architecture 0 0 70 (_process (_simple)
				(_target(8(0)))
				(_sensitivity(10(0))(9(0)))
			)))
			(#ASSIGN#71_1 (_architecture 1 0 71 (_process (_simple)
				(_target(8(1)))
				(_sensitivity(10(1))(9(1)))
			)))
			(#ASSIGN#72_2 (_architecture 2 0 72 (_process (_simple)
				(_target(8(2)))
				(_sensitivity(10(2))(9(2)))
			)))
			(#ASSIGN#73_3 (_architecture 3 0 73 (_process (_simple)
				(_target(8(3)))
				(_sensitivity(10(3))(9(3)))
			)))
			(#ASSIGN#74_4 (_architecture 4 0 74 (_process (_simple)
				(_target(8(4)))
				(_sensitivity(10(4))(9(4)))
			)))
			(#ASSIGN#75_5 (_architecture 5 0 75 (_process (_simple)
				(_target(8(5)))
				(_sensitivity(10(5))(9(5)))
			)))
			(#ASSIGN#76_6 (_architecture 6 0 76 (_process (_simple)
				(_target(8(6)))
				(_sensitivity(10(6))(9(6)))
			)))
			(#ASSIGN#77_7 (_architecture 7 0 77 (_process (_simple)
				(_target(8(7)))
				(_sensitivity(10(7))(9(7)))
			)))
			(#ASSIGN#78_8 (_architecture 8 0 78 (_process (_simple)
				(_target(8(8)))
				(_sensitivity(10(8))(9(8)))
			)))
			(#ASSIGN#79_9 (_architecture 9 0 79 (_process (_simple)
				(_target(8(9)))
				(_sensitivity(10(9))(9(9)))
			)))
			(#ASSIGN#80_10 (_architecture 10 0 80 (_process (_simple)
				(_target(8(10)))
				(_sensitivity(10(10))(9(10)))
			)))
			(#ASSIGN#81_11 (_architecture 11 0 81 (_process (_simple)
				(_target(8(11)))
				(_sensitivity(10(11))(9(11)))
			)))
			(#ASSIGN#82_12 (_architecture 12 0 82 (_process (_simple)
				(_target(8(12)))
				(_sensitivity(10(12))(9(12)))
			)))
			(#ASSIGN#84_13 (_architecture 13 0 84 (_process (_alias ((enable)(AS)(RD)(WR)))(_simple)
				(_target(11))
				(_sensitivity(3)(4)(6))
			)))
			(#ASSIGN#85_14 (_architecture 14 0 85 (_process (_simple)
				(_target(12))
				(_sensitivity(7)(11))
			)))
			(#ASSIGN#86_15 (_architecture 15 0 86 (_process (_simple)
				(_target(13))
				(_sensitivity(7)(11))
			)))
			(#ASSIGN#87_16 (_architecture 16 0 87 (_process (_simple)
				(_target(14))
				(_sensitivity(7)(11))
			)))
			(#ASSIGN#88_17 (_architecture 17 0 88 (_process (_simple)
				(_target(15))
				(_sensitivity(7)(11))
			)))
			(#ALWAYS#96_18 (_architecture 18 0 96 (_process 
				(_target(9)(10)(10(d_7_0))(10(d_12_8))(9(d_7_0))(9(d_12_8)))
				(_read(5)(2)(6)(3)(7)(0)(0(d_4_0)))
			)))
			(#INTERNAL#0_19 (_internal 19 0 0 (_process (_virtual))))
		)
	)
	
	
	(_defparam
	)
	(_model . GPIO 20 -1)

)
I 000044 55 5014          1078524615393 MSP
(_unit VERILOG 6.349C.6.256 (MSP 0 25 (MSP 0 25 ))
	(_version v32)
	(_time 1078524614993 2004.03.05 14:10:14)
	(_source (\./src/msp.v\ VERILOG (\./src/msp.v\ VERILOG)))
	(_use (std(standard))(vl(verilog_logic)))
	(_base (E 7))
	(_entity
		(_time 1078524614993)
		(_use )
	)
	(_timescale 1ps 1ps)
	(_parameters    dbg   accs  )
	(_attribute )
	(_object
		(_type (_internal ~vector~0 0 52 (_array ~bit ((_uto (i 0) (i 0))))(_attribute signed)))
		(_generic (_internal Half_period ~vector~0 0 52 \500000\ (_entity -1 (_constant \500000\))))
		(_type (_internal ~vector~1 0 53 (_array ~bit ((_uto (i 0) (i 0))))(_attribute signed)))
		(_generic (_internal BITS ~vector~1 0 53 \12\ (_entity -1 (_constant \12\))))
		(_type (_internal ~vector~2 0 53 (_array ~bit ((_uto (i 0) (i 0))))(_attribute signed)))
		(_generic (_internal WORDS ~vector~2 0 53 \159\ (_entity -1 (_constant \159\))))
		(_port (_internal WR ~wire 0 25 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal AS ~wire 0 25 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_type (_internal ~[7:0]wire~ 0 25 (_array ~wire ((_downto (i 7) (i 0))))))
		(_port (_internal AD ~[7:0]wire~ 0 25 (_architecture (_inout ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal RD ~wire 0 25 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal Mclk ~wire 0 25 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal ASr ~reg 0 43 (_architecture (_uni ))) (_reg ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal WRr ~reg 0 44 (_architecture (_uni ))) (_reg ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal RDr ~reg 0 45 (_architecture (_uni ))) (_reg ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal Mclkr ~reg 0 46 (_architecture (_uni ))) (_reg ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_type (_internal ~[7:0]reg~ 0 47 (_array ~reg ((_downto (i 7) (i 0))))))
		(_signal (_internal ADr ~[7:0]reg~ 0 47 (_architecture (_uni ))) (_reg ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal busDrive ~reg 0 48 (_architecture (_uni ))) (_reg ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_type (_internal ~integer 0 50 (_array ~reg ((_downto (i 31) (i 0))))(_attribute signed)))
		(_signal (_internal J ~integer 0 50 (_architecture (_uni ))) (_reg integer) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_type (_internal ~[1:BITS]reg~[1:WORDS]~ 0 54 (_array ~reg ((_range  7)(_range  8)))))
		(_signal (_internal Vmem ~[1:BITS]reg~[1:WORDS]~ 0 54 (_architecture (_uni ))) (_reg memory) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_subprogram
			
			(_function \$readmemb\)

		)
		(_type (_external ~wire (vl verilog_logic wire)))
		(_type (_external ~reg (vl verilog_logic reg)))
		(_type (_external ~event (vl verilog_logic event)))
		(_type (_external ~wand (vl verilog_logic wand)))
		(_type (_external ~wor (vl verilog_logic wor)))
		(_type (_external ~tri1 (vl verilog_logic tri1)))
		(_type (_external ~tri0 (vl verilog_logic tri0)))
		(_type (_external ~trireg (vl verilog_logic trireg)))
		(_type (_external ~supply0 (vl verilog_logic supply0)))
		(_type (_external ~supply1 (vl verilog_logic supply1)))
		(_type (_external ~real (vl verilog_logic real)))
		(_type (_external ~realtime (vl verilog_logic realtime)))
		(_type (_external ~tri (vl verilog_logic tri)))
		(_type (_external ~triand (vl verilog_logic triand)))
		(_type (_external ~trior (vl verilog_logic trior)))
		(_type (_external ~bit (vl verilog_logic bit)))
		(_type (_external ~extstd.standard.integer (std standard integer)))
		(_type (_external ~extstd.standard.bit (std standard bit)))
		(_process
			(#ASSIGN#57_0 (_architecture 0 0 57 (_process (_alias ((AS)(ASr)))(_simple)
				(_target(1))
				(_sensitivity(5))
			)))
			(#ASSIGN#58_1 (_architecture 1 0 58 (_process (_alias ((RD)(RDr)))(_simple)
				(_target(3))
				(_sensitivity(7))
			)))
			(#ASSIGN#59_2 (_architecture 2 0 59 (_process (_alias ((WR)(WRr)))(_simple)
				(_target(0))
				(_sensitivity(6))
			)))
			(#ASSIGN#60_3 (_architecture 3 0 60 (_process (_simple)
				(_target(2))
				(_sensitivity(10)(9))
			)))
			(#ASSIGN#61_4 (_architecture 4 0 61 (_process (_alias ((Mclk)(Mclkr)))(_simple)
				(_target(4))
				(_sensitivity(8))
			)))
			(#INITIAL#63_5 (_architecture 5 0 63 (_process 
				(_target(11)(8)(5)(7)(6)(10)(9))
				(_read(12)(11))
			)))
			(#INTERNAL#0_6 (_internal 6 0 0 (_process (_virtual))))
		)
	)
	
	
	(_defparam
	)
	(_model . MSP 9 -1)

)
V 000046 55 7708          1078524615397 U4_TB
(_unit VERILOG 6.349C.6.256 (U4_TB 0 32 (U4_TB 0 32 ))
	(_version v32)
	(_time 1078524614993 2004.03.05 14:10:14)
	(_source (\./compile/U21_TB.v\ VERILOG (\./compile/u21_tb.v\ VERILOG)))
	(_use (std(standard))(vl(verilog_logic)))
	(_base (E 3))
	(_entity
		(_time 1078524614993)
		(_use )
	)
	(_timescale 1ns 1ns)
	(_parameters    dbg   accs  )
	(_attribute )
	(_object
		(_type (_internal ~vector~0 0 72 (_array ~bit ((_uto (i 0) (i 0))))))
		(_generic (_internal DANGLING_INPUT_CONSTANT ~vector~0 0 72 \1'bZ\ (_entity -1 (_constant \1'bZ\))))
		(_port (_internal Enc133FLG ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Enc15FLG ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal FLS1 ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal FLS2 ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Home1 ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Home133FLG ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Home15FLG ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Home2 ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PhaseA_Encoder1 ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PhaseB_Encoder1 ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal RLS1 ~wire 0 33 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal RLS2 ~wire 0 33 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Reset ~wire 0 33 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Enc133ctrl ~wire 0 33 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Enc15ctrl ~wire 0 33 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Home133ctrl ~wire 0 33 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Home15ctrl ~wire 0 33 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal AS ~wire 0 75 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal Mclk ~wire 0 76 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal RD ~wire 0 77 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal WR ~wire 0 78 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_type (_internal ~[7:0]wire~ 0 79 (_array ~wire ((_downto (i 7) (i 0))))))
		(_signal (_internal AD ~[7:0]wire~ 0 79 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal Dangling_Input_Signal ~wire 0 82 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_type (_internal ~[5:0]wire~ 0 110 (_array ~wire ((_downto (i 5) (i 0))))))
		(_signal (_internal \1 \ ~[5:0]wire~ -1 110 (_internal (_uni ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_subprogram
			

		)
		(_type (_external ~wire (vl verilog_logic wire)))
		(_type (_external ~reg (vl verilog_logic reg)))
		(_type (_external ~event (vl verilog_logic event)))
		(_type (_external ~wand (vl verilog_logic wand)))
		(_type (_external ~wor (vl verilog_logic wor)))
		(_type (_external ~tri1 (vl verilog_logic tri1)))
		(_type (_external ~tri0 (vl verilog_logic tri0)))
		(_type (_external ~trireg (vl verilog_logic trireg)))
		(_type (_external ~supply0 (vl verilog_logic supply0)))
		(_type (_external ~supply1 (vl verilog_logic supply1)))
		(_type (_external ~real (vl verilog_logic real)))
		(_type (_external ~realtime (vl verilog_logic realtime)))
		(_type (_external ~tri (vl verilog_logic tri)))
		(_type (_external ~triand (vl verilog_logic triand)))
		(_type (_external ~trior (vl verilog_logic trior)))
		(_type (_external ~bit (vl verilog_logic bit)))
		(_type (_external ~extstd.standard.integer (std standard integer)))
		(_type (_external ~extstd.standard.bit (std standard bit)))
		(_process
			(#INTERNAL#110_0 (_internal 0 0 110 (_process (_simple)
				(_target(23))
				(_sensitivity(22))
			)))
			(#ASSIGN#82_1 (_architecture 1 0 82 (_process (_simple)
				(_target(22))
			)))
			(#INTERNAL#0_2 (_internal 2 0 0 (_process (_virtual))))
		)
	)
	
	
	(_defparam
	)
	(_scope
	)
	(_instantiation U1 0 86 (_entity .  U4)
		(_port
			((AD) (AD))
			((AS) (AS))
			((Brake1) (Dangling_Input_Signal))
			((Brake2) (Dangling_Input_Signal))
			((DIR1) (Dangling_Input_Signal))
			((DIR2) (Dangling_Input_Signal))
			((Enc133FLG) (Enc133FLG))
			((Enc133ctrl) (Enc133ctrl))
			((Enc15FLG) (Enc15FLG))
			((Enc15ctrl) (Enc15ctrl))
			((Enc233FLG) (Dangling_Input_Signal))
			((Enc25FLG) (Dangling_Input_Signal))
			((FLS1) (FLS1))
			((FLS2) (FLS2))
			((Home1) (Home1))
			((Home133FLG) (Home133FLG))
			((Home133ctrl) (Home133ctrl))
			((Home15FLG) (Home15FLG))
			((Home15ctrl) (Home15ctrl))
			((Home2) (Home2))
			((Home233FLG) (Dangling_Input_Signal))
			((Home25FLG) (Dangling_Input_Signal))
			((I2CS) (\1 \))
			((Mclk) (Mclk))
			((PWM1) (Dangling_Input_Signal))
			((PWM2) (Dangling_Input_Signal))
			((PhaseA_Encoder1) (PhaseA_Encoder1))
			((PhaseA_Encoder2) (Dangling_Input_Signal))
			((PhaseB_Encoder1) (PhaseB_Encoder1))
			((PhaseB_Encoder2) (Dangling_Input_Signal))
			((RD) (RD))
			((RLS1) (RLS1))
			((RLS2) (RLS2))
			((Reset) (Reset))
			((WR) (WR))
			((HSI) (_open))
			((INTbus) (_open))
			((LightSense) (_open))
			((MHSO) (_open))
			((SCLinc) (_open))
			((SCLreset) (_open))
			((TXI) (_open))
			((Enc233ctrl) (_open))
			((Enc25ctrl) (_open))
			((HSO) (_open))
			((Home233ctrl) (_open))
			((Home25ctrl) (_open))
			((INT) (_open))
			((LED1) (_open))
			((LED2) (_open))
			((LED3) (_open))
			((LED4) (_open))
			((LED5) (_open))
			((MHSI) (_open))
			((MTRpwr) (_open))
			((MTRpwrn) (_open))
			((MTXI) (_open))
			((PAH1) (_open))
			((PAH2) (_open))
			((PAL1) (_open))
			((PAL2) (_open))
			((PBH1) (_open))
			((PBH2) (_open))
			((PBL1) (_open))
			((PBL2) (_open))
			((SCL) (_open))
		)
		(_strength strong0 strong1)
	)
	(_instantiation U2 0 127 (_entity .  MSP)
		(_port
			((AD) (AD))
			((AS) (AS))
			((Mclk) (Mclk))
			((RD) (RD))
			((WR) (WR))
		)
		(_strength)
	)
	(_model . U4_TB 3 -1)

)
V 000052 55 12761         1078524615401 U21_TB_tsim
(_unit VERILOG 6.349C.6.256 (U21_TB_tsim 0 32 (U21_TB_tsim 0 32 ))
	(_version v32)
	(_time 1078524614993 2004.03.05 14:10:14)
	(_source (\./compile/U21_TB_tsim.v\ VERILOG (\./compile/u21_tb_tsim.v\ VERILOG)))
	(_use (std(standard))(vl(verilog_logic)))
	(_base (E 3))
	(_entity
		(_time 1078524614993)
		(_use )
	)
	(_timescale 1ns 1ns)
	(_parameters    dbg   accs  )
	(_attribute )
	(_object
		(_type (_internal ~vector~0 0 139 (_array ~bit ((_uto (i 0) (i 0))))))
		(_generic (_internal DANGLING_INPUT_CONSTANT ~vector~0 0 139 \1'bZ\ (_entity -1 (_constant \1'bZ\))))
		(_port (_internal Brake1 ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Brake2 ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal DIR1 ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal DIR2 ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Enc133FLG ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Enc15FLG ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Enc233FLG ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Enc25FLG ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal FLS1 ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal FLS2 ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Home1 ~wire 0 33 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Home133FLG ~wire 0 33 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Home15FLG ~wire 0 33 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Home2 ~wire 0 33 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Home233FLG ~wire 0 33 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Home25FLG ~wire 0 33 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PWM1 ~wire 0 33 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PWM2 ~wire 0 33 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PhaseA_Encoder1 ~wire 0 33 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PhaseA_Encoder2 ~wire 0 33 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PhaseB_Encoder1 ~wire 0 34 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PhaseB_Encoder2 ~wire 0 34 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal RLS1 ~wire 0 34 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal RLS2 ~wire 0 34 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Reset ~wire 0 34 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Enc133ctrl ~wire 0 34 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Enc15ctrl ~wire 0 34 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Enc233ctrl ~wire 0 34 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Enc25ctrl ~wire 0 34 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Home133ctrl ~wire 0 34 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Home15ctrl ~wire 0 35 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Home233ctrl ~wire 0 35 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Home25ctrl ~wire 0 35 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal INT ~wire 0 35 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal LED1 ~wire 0 35 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal LED2 ~wire 0 35 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal LED3 ~wire 0 35 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal LED4 ~wire 0 35 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal LED5 ~wire 0 35 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal MTRpwr ~wire 0 35 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal MTRpwrn ~wire 0 36 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PAH1 ~wire 0 36 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PAH2 ~wire 0 36 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PAL1 ~wire 0 36 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PAL2 ~wire 0 36 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PBH1 ~wire 0 36 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PBH2 ~wire 0 36 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PBL1 ~wire 0 36 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PBL2 ~wire 0 36 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal AS ~wire 0 142 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal Mclk ~wire 0 143 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal RD ~wire 0 144 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal WR ~wire 0 145 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_type (_internal ~[7:0]wire~ 0 146 (_array ~wire ((_downto (i 7) (i 0))))))
		(_signal (_internal AD ~[7:0]wire~ 0 146 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal Dangling_Input_Signal ~wire 0 149 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_type (_internal ~[5:0]wire~ 0 184 (_array ~wire ((_downto (i 5) (i 0))))))
		(_signal (_internal \1 \ ~[5:0]wire~ -1 184 (_internal (_uni ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_subprogram
			

		)
		(_type (_external ~wire (vl verilog_logic wire)))
		(_type (_external ~reg (vl verilog_logic reg)))
		(_type (_external ~event (vl verilog_logic event)))
		(_type (_external ~wand (vl verilog_logic wand)))
		(_type (_external ~wor (vl verilog_logic wor)))
		(_type (_external ~tri1 (vl verilog_logic tri1)))
		(_type (_external ~tri0 (vl verilog_logic tri0)))
		(_type (_external ~trireg (vl verilog_logic trireg)))
		(_type (_external ~supply0 (vl verilog_logic supply0)))
		(_type (_external ~supply1 (vl verilog_logic supply1)))
		(_type (_external ~real (vl verilog_logic real)))
		(_type (_external ~realtime (vl verilog_logic realtime)))
		(_type (_external ~tri (vl verilog_logic tri)))
		(_type (_external ~triand (vl verilog_logic triand)))
		(_type (_external ~trior (vl verilog_logic trior)))
		(_type (_external ~bit (vl verilog_logic bit)))
		(_type (_external ~extstd.standard.integer (std standard integer)))
		(_type (_external ~extstd.standard.bit (std standard bit)))
		(_process
			(#INTERNAL#184_0 (_internal 0 0 184 (_process (_simple)
				(_target(55))
				(_sensitivity(54))
			)))
			(#ASSIGN#149_1 (_architecture 1 0 149 (_process (_simple)
				(_target(54))
			)))
			(#INTERNAL#0_2 (_internal 2 0 0 (_process (_virtual))))
		)
	)
	
	
	(_defparam
	)
	(_scope
	)
	(_instantiation U1 0 153 (_entity .  U21)
		(_port
			((AD) (AD))
			((AS) (AS))
			((Brake0) (Brake1))
			((Brake1) (Brake2))
			((DIR0) (DIR1))
			((DIR1) (DIR2))
			((Enc033FLG) (Enc133FLG))
			((Enc033ctrl) (Enc133ctrl))
			((Enc05FLG) (Enc15FLG))
			((Enc05ctrl) (Enc15ctrl))
			((Enc133FLG) (Enc233FLG))
			((Enc133ctrl) (Enc233ctrl))
			((Enc15FLG) (Enc25FLG))
			((Enc15ctrl) (Enc25ctrl))
			((FLS0) (FLS1))
			((FLS1) (FLS2))
			((GP_Motor0_0) (Dangling_Input_Signal))
			((GP_Motor1_0) (Dangling_Input_Signal))
			((HSI) (Dangling_Input_Signal))
			((Home0) (Home1))
			((Home033FLG) (Home133FLG))
			((Home033ctrl) (Home133ctrl))
			((Home05FLG) (Home15FLG))
			((Home05ctrl) (Home15ctrl))
			((Home1) (Home2))
			((Home133FLG) (Home233FLG))
			((Home133ctrl) (Home233ctrl))
			((Home15FLG) (Home25FLG))
			((Home15ctrl) (Home25ctrl))
			((I2CS) (\1 \))
			((INT) (INT))
			((INTbus) (Dangling_Input_Signal))
			((LED1) (LED1))
			((LED2) (LED2))
			((LED3) (LED3))
			((LED4) (LED4))
			((LED5) (LED5))
			((LightSense) (Dangling_Input_Signal))
			((MHSO) (Dangling_Input_Signal))
			((MTRpwr) (MTRpwr))
			((MTRpwrn) (MTRpwrn))
			((Mclk) (Mclk))
			((PAH0) (PAH1))
			((PAH1) (PAH2))
			((PAL0) (PAL1))
			((PAL1) (PAL2))
			((PBH0) (PBH1))
			((PBH1) (PBH2))
			((PBL0) (PBL1))
			((PBL1) (PBL2))
			((PWM1) (PWM1))
			((PWM2) (PWM2))
			((PhaseA_Encoder0) (PhaseA_Encoder1))
			((PhaseA_Encoder1) (PhaseA_Encoder2))
			((PhaseB_Encoder0) (PhaseB_Encoder1))
			((PhaseB_Encoder1) (PhaseB_Encoder2))
			((RD) (RD))
			((RLS0) (RLS1))
			((RLS1) (RLS2))
			((Reset) (Reset))
			((SCLinc) (Dangling_Input_Signal))
			((SCLreset) (Dangling_Input_Signal))
			((TXI) (Dangling_Input_Signal))
			((WR) (WR))
			((GP_Motor0_1) (_open))
			((GP_Motor1_1) (_open))
			((HSO) (_open))
			((MHSI) (_open))
			((MTXI) (_open))
			((SCL) (_open))
		)
		(_strength)
	)
	(_instantiation U2 0 223 (_entity .  MSP)
		(_port
			((AD) (AD))
			((AS) (AS))
			((Mclk) (Mclk))
			((RD) (RD))
			((WR) (WR))
		)
		(_strength)
	)
	(_model . U21_TB_tsim 3 -1)

)
I 000050 55 4040          1078524870540 Interrupt
(_unit VERILOG 6.349C.6.256 (Interrupt 0 25 (Interrupt 0 25 ))
	(_version v32)
	(_time 1078524870431 2004.03.05 14:14:30)
	(_source (\./src/interrupt.v\ VERILOG (\./src/interrupt.v\ VERILOG)))
	(_use (std(standard))(vl(verilog_logic)))
	(_base (E 3))
	(_entity
		(_time 1078524870431)
		(_use )
	)
	(_timescale 1ps 1ps)
	(_parameters    dbg   accs  )
	(_attribute nb_assign )
	(_object
		(_type (_internal ~[7:0]wire~ 0 25 (_array ~wire ((_downto (i 7) (i 0))))))
		(_port (_internal inDATA ~[7:0]wire~ 0 25 (_architecture (_in ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal Reset ~wire 0 25 (_architecture (_in ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal PWRint ~wire 0 25 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal BusInt ~wire 0 25 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal Thres0 ~wire 0 25 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal Mclk ~wire 0 25 (_architecture (_in ))) (_net  ) (_nonbaction) (_noforceassign))
		(_port (_internal Thres1 ~wire 0 25 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal I2Cint ~wire 0 25 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal LSwitchInt ~wire 0 25 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal INT ~wire 0 25 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal DCORIEw ~wire 0 25 (_architecture (_in ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal Homed0 ~wire 0 25 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal Homed1 ~wire 0 25 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_type (_internal ~[7:0]reg~ 0 59 (_array ~reg ((_downto (i 7) (i 0))))))
		(_signal (_internal DCORIE ~[7:0]reg~ 0 59 (_architecture (_uni ))) (_reg ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_subprogram
			

		)
		(_type (_external ~wire (vl verilog_logic wire)))
		(_type (_external ~reg (vl verilog_logic reg)))
		(_type (_external ~event (vl verilog_logic event)))
		(_type (_external ~wand (vl verilog_logic wand)))
		(_type (_external ~wor (vl verilog_logic wor)))
		(_type (_external ~tri1 (vl verilog_logic tri1)))
		(_type (_external ~tri0 (vl verilog_logic tri0)))
		(_type (_external ~trireg (vl verilog_logic trireg)))
		(_type (_external ~supply0 (vl verilog_logic supply0)))
		(_type (_external ~supply1 (vl verilog_logic supply1)))
		(_type (_external ~real (vl verilog_logic real)))
		(_type (_external ~realtime (vl verilog_logic realtime)))
		(_type (_external ~tri (vl verilog_logic tri)))
		(_type (_external ~triand (vl verilog_logic triand)))
		(_type (_external ~trior (vl verilog_logic trior)))
		(_type (_external ~bit (vl verilog_logic bit)))
		(_type (_external ~extstd.standard.integer (std standard integer)))
		(_type (_external ~extstd.standard.bit (std standard bit)))
		(_process
			(#ASSIGN#68_0 (_architecture 0 0 68 (_process (_alias ((INT)(DCORIE(7))(I2Cint)(DCORIE(6))(Thres1)(DCORIE(5))(Thres0)(DCORIE(4))(LSwitchInt)(DCORIE(3))(Homed1)(DCORIE(2))(Homed0)(DCORIE(1))(PWRint)(DCORIE(0))(BusInt)))(_simple)
				(_target(9))
				(_sensitivity(13(7))(7)(13(6))(6)(13(5))(4)(13(4))(8)(13(3))(12)(13(2))(11)(13(1))(2)(13(0))(3))
			)))
			(#ALWAYS#70_1 (_architecture 1 0 70 (_process 
				(_target(13))
				(_read(5)(1)(10)(0))
			)))
		)
	)
	
	
	(_defparam
	)
	(_model . Interrupt 3 -1)

)
I 000050 55 4270          1078524951572 Interface
(_unit VERILOG 6.349C.6.256 (Interface 0 25 (Interface 0 25 ))
	(_version v32)
	(_time 1078524951509 2004.03.05 14:15:51)
	(_source (\./src/interface.v\ VERILOG (\./src/interface.v\ VERILOG)))
	(_use (std(standard))(vl(verilog_logic)))
	(_base (E 6))
	(_entity
		(_time 1078524951509)
		(_use )
	)
	(_timescale 1ps 1ps)
	(_parameters    dbg   accs  )
	(_attribute nb_assign )
	(_object
		(_type (_internal ~[7:0]wire~ 0 25 (_array ~wire ((_downto (i 7) (i 0))))))
		(_port (_internal inDATA ~[7:0]wire~ 0 25 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal outDATA ~[7:0]wire~ 0 25 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal Reset ~wire 0 25 (_architecture (_in ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal AS ~wire 0 25 (_architecture (_in ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal AD ~[7:0]wire~ 0 25 (_architecture (_inout ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal RD ~wire 0 25 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal Mclk ~wire 0 25 (_architecture (_in ))) (_net  ) (_nonbaction) (_noforceassign))
		(_port (_internal WR ~wire 0 25 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal ADDR ~[7:0]wire~ 0 25 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_type (_internal ~[7:0]reg~ 0 56 (_array ~reg ((_downto (i 7) (i 0))))))
		(_signal (_internal ADDR_reg ~[7:0]reg~ 0 56 (_architecture (_uni ))) (_reg ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal AutoInc ~reg 0 64 (_architecture (_uni ))) (_reg ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal ASedge ~reg 0 66 (_architecture (_uni ))) (_reg ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal WRRDedge ~reg 0 68 (_architecture (_uni ))) (_reg ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal Enable_AD ~wire 0 72 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_subprogram
			

		)
		(_type (_external ~wire (vl verilog_logic wire)))
		(_type (_external ~reg (vl verilog_logic reg)))
		(_type (_external ~event (vl verilog_logic event)))
		(_type (_external ~wand (vl verilog_logic wand)))
		(_type (_external ~wor (vl verilog_logic wor)))
		(_type (_external ~tri1 (vl verilog_logic tri1)))
		(_type (_external ~tri0 (vl verilog_logic tri0)))
		(_type (_external ~trireg (vl verilog_logic trireg)))
		(_type (_external ~supply0 (vl verilog_logic supply0)))
		(_type (_external ~supply1 (vl verilog_logic supply1)))
		(_type (_external ~real (vl verilog_logic real)))
		(_type (_external ~realtime (vl verilog_logic realtime)))
		(_type (_external ~tri (vl verilog_logic tri)))
		(_type (_external ~triand (vl verilog_logic triand)))
		(_type (_external ~trior (vl verilog_logic trior)))
		(_type (_external ~bit (vl verilog_logic bit)))
		(_type (_external ~extstd.standard.integer (std standard integer)))
		(_type (_external ~extstd.standard.bit (std standard bit)))
		(_process
			(#ASSIGN#75_0 (_architecture 0 0 75 (_process (_alias ((ADDR)(ADDR_reg)))(_simple)
				(_target(8))
				(_sensitivity(9))
			)))
			(#ASSIGN#78_1 (_architecture 1 0 78 (_process (_alias ((Enable_AD)(WR)(RD)))(_simple)
				(_target(13))
				(_sensitivity(7)(5))
			)))
			(#ASSIGN#85_2 (_architecture 2 0 85 (_process (_alias ((inDATA)(AD)))(_simple)
				(_target(0))
				(_sensitivity(4))
			)))
			(#ASSIGN#86_3 (_architecture 3 0 86 (_process (_simple)
				(_target(4))
				(_sensitivity(13)(1))
			)))
			(#ALWAYS#88_4 (_architecture 4 0 88 (_process 
				(_target(11)(12)(9)(10))
				(_read(6)(3)(7)(5)(2)(11)(4)(12)(10)(9))
			)))
		)
	)
	
	
	(_defparam
	)
	(_model . Interface 6 -1)

)
I 000050 55 4040          1078524966541 Interrupt
(_unit VERILOG 6.349C.6.256 (Interrupt 0 25 (Interrupt 0 25 ))
	(_version v32)
	(_time 1078524966478 2004.03.05 14:16:06)
	(_source (\./src/interrupt.v\ VERILOG (\./src/interrupt.v\ VERILOG)))
	(_use (std(standard))(vl(verilog_logic)))
	(_base (E 3))
	(_entity
		(_time 1078524966478)
		(_use )
	)
	(_timescale 1ps 1ps)
	(_parameters    dbg   accs  )
	(_attribute nb_assign )
	(_object
		(_type (_internal ~[7:0]wire~ 0 25 (_array ~wire ((_downto (i 7) (i 0))))))
		(_port (_internal inDATA ~[7:0]wire~ 0 25 (_architecture (_in ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal Reset ~wire 0 25 (_architecture (_in ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal PWRint ~wire 0 25 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal BusInt ~wire 0 25 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal Thres0 ~wire 0 25 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal Mclk ~wire 0 25 (_architecture (_in ))) (_net  ) (_nonbaction) (_noforceassign))
		(_port (_internal Thres1 ~wire 0 25 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal I2Cint ~wire 0 25 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal LSwitchInt ~wire 0 25 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal INT ~wire 0 25 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal DCORIEw ~wire 0 25 (_architecture (_in ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal Homed0 ~wire 0 25 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal Homed1 ~wire 0 25 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_type (_internal ~[7:0]reg~ 0 59 (_array ~reg ((_downto (i 7) (i 0))))))
		(_signal (_internal DCORIE ~[7:0]reg~ 0 59 (_architecture (_uni ))) (_reg ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_subprogram
			

		)
		(_type (_external ~wire (vl verilog_logic wire)))
		(_type (_external ~reg (vl verilog_logic reg)))
		(_type (_external ~event (vl verilog_logic event)))
		(_type (_external ~wand (vl verilog_logic wand)))
		(_type (_external ~wor (vl verilog_logic wor)))
		(_type (_external ~tri1 (vl verilog_logic tri1)))
		(_type (_external ~tri0 (vl verilog_logic tri0)))
		(_type (_external ~trireg (vl verilog_logic trireg)))
		(_type (_external ~supply0 (vl verilog_logic supply0)))
		(_type (_external ~supply1 (vl verilog_logic supply1)))
		(_type (_external ~real (vl verilog_logic real)))
		(_type (_external ~realtime (vl verilog_logic realtime)))
		(_type (_external ~tri (vl verilog_logic tri)))
		(_type (_external ~triand (vl verilog_logic triand)))
		(_type (_external ~trior (vl verilog_logic trior)))
		(_type (_external ~bit (vl verilog_logic bit)))
		(_type (_external ~extstd.standard.integer (std standard integer)))
		(_type (_external ~extstd.standard.bit (std standard bit)))
		(_process
			(#ASSIGN#68_0 (_architecture 0 0 68 (_process (_alias ((INT)(DCORIE(7))(I2Cint)(DCORIE(6))(Thres1)(DCORIE(5))(Thres0)(DCORIE(4))(LSwitchInt)(DCORIE(3))(Homed1)(DCORIE(2))(Homed0)(DCORIE(1))(PWRint)(DCORIE(0))(BusInt)))(_simple)
				(_target(9))
				(_sensitivity(13(7))(7)(13(6))(6)(13(5))(4)(13(4))(8)(13(3))(12)(13(2))(11)(13(1))(2)(13(0))(3))
			)))
			(#ALWAYS#70_1 (_architecture 1 0 70 (_process 
				(_target(13))
				(_read(5)(1)(10)(0))
			)))
		)
	)
	
	
	(_defparam
	)
	(_model . Interrupt 3 -1)

)
V 000044 55 1745817       1078756852566 U21
(_unit VERILOG 6.349C.6.256 (U21 0 18 (U21 0 18 ))
	(_version v32)
	(_time 1078756852144 2004.03.08 06:40:52)
	(_source (\./implement/ver0/rev1/time_sim.v\ VERILOG (\./implement/ver0/rev1/time_sim.v\ VERILOG)))
	(_use (std(standard))(vl(verilog_logic)))
	(_base (E 47))
	(_entity
		(_time 1078756852144)
		(_use )
	)
	(_timescale 1ns 1ps)
	(_parameters    dbg   accs  )
	(_attribute )
	(_sdf_annotate
		(
			(_file (_string \V"c:/projects/genosensor/2g/cplds/core/u21/implement/ver0/rev1/time_sim.sdf"\))
			(_instantiation)
			(_file)
			(_file)
			(_delay)
			(_unit)
			(_range)
		)
	)
	(_object
		(_port (_internal WR ~wire 0 19 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal RD ~wire 0 19 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal Reset ~wire 0 19 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal AS ~wire 0 19 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal Mclk ~wire 0 19 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal SCLreset ~wire 0 19 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal SCLinc ~wire 0 19 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal FLS1 ~wire 0 19 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal Home15FLG ~wire 0 19 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal Home033FLG ~wire 0 19 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal Home05FLG ~wire 0 19 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal Enc033FLG ~wire 0 19 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal Enc05FLG ~wire 0 19 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal Home133FLG ~wire 0 19 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal Enc133FLG ~wire 0 19 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal Enc15FLG ~wire 0 19 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal PhaseA_Encoder0 ~wire 0 20 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal PhaseB_Encoder0 ~wire 0 20 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal PhaseA_Encoder1 ~wire 0 20 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal PhaseB_Encoder1 ~wire 0 20 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal GP_Motor0_0 ~wire 0 20 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal Home1 ~wire 0 20 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal GP_Motor1_0 ~wire 0 20 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal DIR1 ~wire 0 20 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal RLS1 ~wire 0 20 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal Brake1 ~wire 0 20 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal Brake0 ~wire 0 20 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal DIR0 ~wire 0 20 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal FLS0 ~wire 0 20 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal HSI ~wire 0 20 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal MHSO ~wire 0 21 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal INTbus ~wire 0 21 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal RLS0 ~wire 0 21 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal LightSense ~wire 0 21 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal TXI ~wire 0 21 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal PWM1 ~wire 0 21 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal PWM2 ~wire 0 21 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal Home0 ~wire 0 21 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal Enc033ctrl ~wire 0 21 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Enc05ctrl ~wire 0 21 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Enc133ctrl ~wire 0 21 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Enc15ctrl ~wire 0 21 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal GP_Motor0_1 ~wire 0 21 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal GP_Motor1_1 ~wire 0 21 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal HSO ~wire 0 21 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Home033ctrl ~wire 0 21 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Home05ctrl ~wire 0 22 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Home133ctrl ~wire 0 22 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Home15ctrl ~wire 0 22 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal INT ~wire 0 22 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal LED1 ~wire 0 22 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal LED2 ~wire 0 22 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal LED3 ~wire 0 22 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal LED4 ~wire 0 22 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal LED5 ~wire 0 22 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal MHSI ~wire 0 22 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal MTRpwr ~wire 0 22 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal MTRpwrn ~wire 0 22 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal MTXI ~wire 0 22 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PAH0 ~wire 0 22 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PAH1 ~wire 0 22 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PAL0 ~wire 0 22 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PAL1 ~wire 0 22 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PBH0 ~wire 0 22 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PBH1 ~wire 0 22 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PBL0 ~wire 0 22 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PBL1 ~wire 0 22 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal SCL ~wire 0 23 (_architecture (_inout ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_type (_internal ~[5:0]wire~ 0 23 (_array ~wire ((_downto (i 5) (i 0))))))
		(_port (_internal I2CS ~[5:0]wire~ 0 23 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_type (_internal ~[7:0]wire~ 0 24 (_array ~wire ((_downto (i 7) (i 0))))))
		(_port (_internal AD ~[7:0]wire~ 0 24 (_architecture (_inout ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NlwRenamedSig_IO_WR ~wire 0 95 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal \WR_II/UIM \ ~wire 0 96 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NlwRenamedSig_IO_RD ~wire 0 97 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal \RD_II/UIM \ ~wire 0 98 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NlwRenamedSig_IO_Reset ~wire 0 99 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal \Reset_II/UIM \ ~wire 0 100 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \AD<0>_II/UIM \ ~wire 0 101 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \AD<0>_II/IREG \ ~wire 0 102 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \FOOBAR1__ctinst/7 \ ~wire 0 103 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal PRLD ~wire 0 104 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal \U9/MISCr<0>_MC_tsimcreated_prld_ \ ~wire 0 105 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \Mclk_II/FCLK \ ~wire 0 106 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal Gnd ~wire 0 107 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \FOOBAR12__ctinst/4 \ ~wire 0 108 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NlwRenamedSig_IO_AS ~wire 0 109 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal \AS_II/UIM \ ~wire 0 110 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal U2_ASedge ~wire 0 111 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \AS_II/IREG \ ~wire 0 112 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal Vcc ~wire 0 113 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NlwRenamedSig_IO_Mclk ~wire 0 114 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal \AD<4>_II/UIM \ ~wire 0 115 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \AD<4>_II/IREG \ ~wire 0 116 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \U9/MISCr<4>_MC_tsimcreated_prld_ \ ~wire 0 117 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \FOOBAR10__ctinst/4 \ ~wire 0 118 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \AD<2>_II/UIM \ ~wire 0 119 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \AD<2>_II/IREG \ ~wire 0 120 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \U9/MISCr<2>_MC_tsimcreated_prld_ \ ~wire 0 121 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \AD<3>_II/UIM \ ~wire 0 122 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \AD<3>_II/IREG \ ~wire 0 123 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \U9/MISCr<3>_MC_tsimcreated_prld_ \ ~wire 0 124 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \AD<5>_II/UIM \ ~wire 0 125 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \AD<6>_II/UIM \ ~wire 0 126 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \AD<7>_II/UIM \ ~wire 0 127 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \AD<1>_II/UIM \ ~wire 0 128 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \AD<1>_II/IREG \ ~wire 0 129 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \U9/MISCr<1>_MC_tsimcreated_prld_ \ ~wire 0 130 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NlwRenamedSig_IO_SCLreset ~wire 0 131 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal \SCLreset_II/UIM \ ~wire 0 132 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NlwRenamedSig_IO_SCLinc ~wire 0 133 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal \SCLinc_II/UIM \ ~wire 0 134 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \U11_U1/Line_last \ ~wire 0 135 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \SCLinc_II/IREG \ ~wire 0 136 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \U11_U1/Line_last_MC.REG_tsimcreated_inv_Mclk_II/FCLK \ ~wire 0 137 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \SCL_II/UIM \ ~wire 0 138 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \U11_U2/Line_last \ ~wire 0 139 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \SCL_II/IREG \ ~wire 0 140 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \U11_U2/Line_last_MC.REG_tsimcreated_inv_Mclk_II/FCLK \ ~wire 0 141 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \I2CS<5>_II/UIM \ ~wire 0 142 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NlwRenamedSig_IO_FLS1 ~wire 0 143 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal \FLS1_II/UIM \ ~wire 0 144 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NlwRenamedSig_IO_Home15FLG ~wire 0 145 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal \Home15FLG_II/UIM \ ~wire 0 146 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \Home15FLG_II/IREG \ ~wire 0 147 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \FOOBAR21__ctinst/4 \ ~wire 0 148 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NlwRenamedSig_IO_Home033FLG ~wire 0 149 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal \Home033FLG_II/UIM \ ~wire 0 150 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \Home033FLG_II/IREG \ ~wire 0 151 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NlwRenamedSig_IO_Home05FLG ~wire 0 152 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal \Home05FLG_II/UIM \ ~wire 0 153 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \Home05FLG_II/IREG \ ~wire 0 154 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NlwRenamedSig_IO_Enc033FLG ~wire 0 155 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal \Enc033FLG_II/UIM \ ~wire 0 156 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \Enc033FLG_II/IREG \ ~wire 0 157 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \FOOBAR24__ctinst/4 \ ~wire 0 158 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NlwRenamedSig_IO_Enc05FLG ~wire 0 159 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal \Enc05FLG_II/UIM \ ~wire 0 160 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \Enc05FLG_II/IREG \ ~wire 0 161 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NlwRenamedSig_IO_Home133FLG ~wire 0 162 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal \Home133FLG_II/UIM \ ~wire 0 163 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \Home133FLG_II/IREG \ ~wire 0 164 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NlwRenamedSig_IO_Enc133FLG ~wire 0 165 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal \Enc133FLG_II/UIM \ ~wire 0 166 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \Enc133FLG_II/IREG \ ~wire 0 167 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NlwRenamedSig_IO_Enc15FLG ~wire 0 168 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal \Enc15FLG_II/UIM \ ~wire 0 169 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \Enc15FLG_II/IREG \ ~wire 0 170 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NlwRenamedSig_IO_PhaseA_Encoder0 ~wire 0 171 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal \PhaseA_Encoder0_II/UIM \ ~wire 0 172 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NlwRenamedSig_IO_PhaseB_Encoder0 ~wire 0 173 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal \PhaseB_Encoder0_II/UIM \ ~wire 0 174 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NlwRenamedSig_IO_PhaseA_Encoder1 ~wire 0 175 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal \PhaseA_Encoder1_II/UIM \ ~wire 0 176 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NlwRenamedSig_IO_PhaseB_Encoder1 ~wire 0 177 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal \PhaseB_Encoder1_II/UIM \ ~wire 0 178 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NlwRenamedSig_IO_GP_Motor0_0 ~wire 0 179 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal \GP_Motor0_0_II/UIM \ ~wire 0 180 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \U1/U4/InEdge0r \ ~wire 0 181 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \GP_Motor0_0_II/IREG \ ~wire 0 182 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \U1/U4/InEdge0r_MC.REG_tsimcreated_inv_Mclk_II/FCLK \ ~wire 0 183 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NlwRenamedSig_IO_Home1 ~wire 0 184 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal \Home1_II/UIM \ ~wire 0 185 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \U1/U4/HE1stater \ ~wire 0 186 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \Home1_II/IREG \ ~wire 0 187 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \U1/U4/HE1stater_MC.REG_tsimcreated_inv_Mclk_II/FCLK \ ~wire 0 188 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NlwRenamedSig_IO_GP_Motor1_0 ~wire 0 189 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal \GP_Motor1_0_II/UIM \ ~wire 0 190 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \U1/U4/InEdge1r \ ~wire 0 191 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \GP_Motor1_0_II/IREG \ ~wire 0 192 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \U1/U4/InEdge1r_MC.REG_tsimcreated_inv_Mclk_II/FCLK \ ~wire 0 193 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NlwRenamedSig_IO_DIR1 ~wire 0 194 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal \DIR1_II/UIM \ ~wire 0 195 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NlwRenamedSig_IO_RLS1 ~wire 0 196 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal \RLS1_II/UIM \ ~wire 0 197 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NlwRenamedSig_IO_Brake1 ~wire 0 198 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal \Brake1_II/UIM \ ~wire 0 199 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NlwRenamedSig_IO_Brake0 ~wire 0 200 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal \Brake0_II/UIM \ ~wire 0 201 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NlwRenamedSig_IO_DIR0 ~wire 0 202 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal \DIR0_II/UIM \ ~wire 0 203 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NlwRenamedSig_IO_FLS0 ~wire 0 204 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal \FLS0_II/UIM \ ~wire 0 205 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NlwRenamedSig_IO_HSI ~wire 0 206 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal \HSI_II/UIM \ ~wire 0 207 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NlwRenamedSig_IO_MHSO ~wire 0 208 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal \MHSO_II/UIM \ ~wire 0 209 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \I2CS<0>_II/UIM \ ~wire 0 210 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \I2CS<1>_II/UIM \ ~wire 0 211 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \I2CS<2>_II/UIM \ ~wire 0 212 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \I2CS<3>_II/UIM \ ~wire 0 213 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \I2CS<4>_II/UIM \ ~wire 0 214 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NlwRenamedSig_IO_INTbus ~wire 0 215 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal \INTbus_II/UIM \ ~wire 0 216 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NlwRenamedSig_IO_RLS0 ~wire 0 217 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal \RLS0_II/UIM \ ~wire 0 218 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NlwRenamedSig_IO_LightSense ~wire 0 219 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal \LightSense_II/UIM \ ~wire 0 220 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NlwRenamedSig_IO_TXI ~wire 0 221 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal \TXI_II/UIM \ ~wire 0 222 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NlwRenamedSig_IO_PWM1 ~wire 0 223 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal \PWM1_II/UIM \ ~wire 0 224 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NlwRenamedSig_IO_PWM2 ~wire 0 225 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal \PWM2_II/UIM \ ~wire 0 226 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NlwRenamedSig_IO_Home0 ~wire 0 227 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal \Home0_II/UIM \ ~wire 0 228 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \U1/U4/HE0stater \ ~wire 0 229 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \Home0_II/IREG \ ~wire 0 230 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \U1/U4/HE0stater_MC.REG_tsimcreated_inv_Mclk_II/FCLK \ ~wire 0 231 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \AD<5>_MC.Q \ ~wire 0 232 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \AD<5>_MC.OE \ ~wire 0 233 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \AD<6>_MC.Q \ ~wire 0 234 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \AD<6>_MC.OE \ ~wire 0 235 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \AD<7>_MC.Q \ ~wire 0 236 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \AD<7>_MC.OE \ ~wire 0 237 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \Enc033ctrl_MC.Q \ ~wire 0 238 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \Enc05ctrl_MC.Q \ ~wire 0 239 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \Enc133ctrl_MC.Q \ ~wire 0 240 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \Enc15ctrl_MC.Q \ ~wire 0 241 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \GP_Motor0_1_MC.Q \ ~wire 0 242 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \GP_Motor1_1_MC.Q \ ~wire 0 243 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \HSO_MC.Q \ ~wire 0 244 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \Home033ctrl_MC.Q \ ~wire 0 245 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \Home05ctrl_MC.Q \ ~wire 0 246 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \Home133ctrl_MC.Q \ ~wire 0 247 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \Home15ctrl_MC.Q \ ~wire 0 248 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \INT_MC.Q \ ~wire 0 249 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \LED1_MC.Q \ ~wire 0 250 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \LED2_MC.Q \ ~wire 0 251 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \LED3_MC.Q \ ~wire 0 252 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \LED4_MC.Q \ ~wire 0 253 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \LED5_MC.Q \ ~wire 0 254 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \MHSI_MC.Q \ ~wire 0 255 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \MTRpwr_MC.Q \ ~wire 0 256 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \MTRpwrn_MC.Q \ ~wire 0 257 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \MTXI_MC.Q \ ~wire 0 258 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \PAH0_MC.Q \ ~wire 0 259 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \PAH1_MC.Q \ ~wire 0 260 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \PAL0_MC.Q \ ~wire 0 261 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \PAL1_MC.Q \ ~wire 0 262 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \PBH0_MC.Q \ ~wire 0 263 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \PBH1_MC.Q \ ~wire 0 264 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \PBL0_MC.Q \ ~wire 0 265 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \PBL1_MC.Q \ ~wire 0 266 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \U11_U2/Line_last_MC.Q \ ~wire 0 267 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \U11_U2/Line_last_MC.OE \ ~wire 0 268 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \U9/MISCr<0>_MC.Q \ ~wire 0 269 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \U9/MISCr<0>_MC.OE \ ~wire 0 270 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \U9/MISCr<1>_MC.Q \ ~wire 0 271 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \U9/MISCr<1>_MC.OE \ ~wire 0 272 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \U9/MISCr<2>_MC.Q \ ~wire 0 273 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \U9/MISCr<2>_MC.OE \ ~wire 0 274 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \U9/MISCr<3>_MC.Q \ ~wire 0 275 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \U9/MISCr<3>_MC.OE \ ~wire 0 276 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \U9/MISCr<4>_MC.Q \ ~wire 0 277 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \U9/MISCr<4>_MC.OE \ ~wire 0 278 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \AD<5>_MC.Q_tsimrenamed_net_ \ ~wire 0 279 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \AD<5>_MC.BUFOE.OUT \ ~wire 0 280 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \FOOBAR3__ctinst/7 \ ~wire 0 281 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \AD<5>_MC.D \ ~wire 0 282 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \AD<5>_MC.D1 \ ~wire 0 283 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \AD<5>_MC.D2 \ ~wire 0 284 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \outDATA<5>\\$WA5.UIM \ ~wire 0 285 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal N_PZ_964 ~wire 0 286 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \AD<5>_MC.D2_PT_0 \ ~wire 0 287 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \outDATA<5>\\$WA4.UIM \ ~wire 0 288 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal N_PZ_1060 ~wire 0 289 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \AD<5>_MC.D2_PT_1 \ ~wire 0 290 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal N_PZ_931 ~wire 0 291 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \outDATA<5>\\$WA1.UIM \ ~wire 0 292 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \AD<5>_MC.D2_PT_2 \ ~wire 0 293 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \outDATA<5>\\$WA2.UIM \ ~wire 0 294 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \AD<5>_MC.D2_PT_3 \ ~wire 0 295 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \outDATA<5>\\$WA3.UIM \ ~wire 0 296 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \AD<5>_MC.D2_PT_4 \ ~wire 0 297 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \outDATA<5>\\$WA0.UIM \ ~wire 0 298 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \AD<5>_MC.D2_PT_5 \ ~wire 0 299 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \U2_ADDR_reg<1>_MC.Q \ ~wire 0 300 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \U2_ADDR_reg<1>_MC.D \ ~wire 0 301 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \U2_ADDR_reg<1>_MC.D1 \ ~wire 0 302 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \U2_ADDR_reg<1>_MC.D2 \ ~wire 0 303 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal N_PZ_947 ~wire 0 304 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal N_PZ_989 ~wire 0 305 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \U2_ADDR_reg<1>_MC.D2_PT_0 \ ~wire 0 306 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \U2_ADDR_reg<1>_MC.D2_PT_1 \ ~wire 0 307 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \U2_ADDR_reg<1>_MC.D2_PT_2 \ ~wire 0 308 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \U2_ADDR_reg<1>_MC.D2_PT_3 \ ~wire 0 309 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \U2_ADDR_reg<0>_MC.Q \ ~wire 0 310 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \U2_ADDR_reg<0>_MC.D \ ~wire 0 311 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal U2_ADDR_reg<0>_MC_tsimcreated_xor_ ~wire 0 312 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \U2_ADDR_reg<0>_MC.D1 \ ~wire 0 313 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \U2_ADDR_reg<0>_MC.D2 \ ~wire 0 314 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \U2_ADDR_reg<0>_MC.D2_PT_0 \ ~wire 0 315 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \U2_ADDR_reg<0>_MC.D2_PT_1 \ ~wire 0 316 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \U2_ADDR_reg<0>_MC.D2_PT_2 \ ~wire 0 317 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal U2_AutoInc ~wire 0 318 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal U2_WRRDedge ~wire 0 319 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \U2_ADDR_reg<0>_MC.D2_PT_3 \ ~wire 0 320 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \N_PZ_947_MC.Q \ ~wire 0 321 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \N_PZ_947_MC.D \ ~wire 0 322 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \N_PZ_947_MC.D1 \ ~wire 0 323 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \N_PZ_947_MC.D2 \ ~wire 0 324 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \U2_AutoInc_MC.Q \ ~wire 0 325 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \U2_AutoInc_MC.D \ ~wire 0 326 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \FOOBAR16__ctinst/4 \ ~wire 0 327 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \U2_AutoInc_MC.D1 \ ~wire 0 328 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \U2_AutoInc_MC.D2 \ ~wire 0 329 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \U2_WRRDedge_MC.Q \ ~wire 0 330 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \U2_WRRDedge_MC.D \ ~wire 0 331 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \U2_WRRDedge_MC.D1 \ ~wire 0 332 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \U2_WRRDedge_MC.D2 \ ~wire 0 333 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \U2__n0017_MC.Q \ ~wire 0 334 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal U2__n0017 ~wire 0 335 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \U2__n0017_MC.D \ ~wire 0 336 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \U2__n0017_MC.D1 \ ~wire 0 337 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \U2__n0017_MC.D2 \ ~wire 0 338 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \N_PZ_931_MC.Q \ ~wire 0 339 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \N_PZ_931_MC.D \ ~wire 0 340 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \N_PZ_931_MC.D1 \ ~wire 0 341 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \N_PZ_931_MC.D2 \ ~wire 0 342 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \U2_ADDR_reg<4>_MC.Q \ ~wire 0 343 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \U2_ADDR_reg<4>_MC.D \ ~wire 0 344 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal U2_ADDR_reg<4>_MC_tsimcreated_xor_ ~wire 0 345 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \U2_ADDR_reg<4>_MC.D1 \ ~wire 0 346 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \U2_ADDR_reg<4>_MC.D2 \ ~wire 0 347 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \U2_ADDR_reg<4>_MC.D2_PT_0 \ ~wire 0 348 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \U2_ADDR_reg<4>_MC.D2_PT_1 \ ~wire 0 349 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \U2_ADDR_reg<4>_MC.D2_PT_2 \ ~wire 0 350 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \U2_ADDR_reg<4>_MC.D2_PT_3 \ ~wire 0 351 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \U2_ADDR_reg<2>_MC.Q \ ~wire 0 352 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \U2_ADDR_reg<2>_MC.D \ ~wire 0 353 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
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		(_signal (_internal \U2_ADDR_reg<2>_MC.D1 \ ~wire 0 355 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \U2_ADDR_reg<2>_MC.D2 \ ~wire 0 356 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
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		(_signal (_internal \U2_ADDR_reg<2>_MC.D2_PT_4 \ ~wire 0 361 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \U2_ADDR_reg<3>_MC.Q \ ~wire 0 362 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \U2_ADDR_reg<3>_MC.D \ ~wire 0 363 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal U2_ADDR_reg<3>_MC_tsimcreated_xor_ ~wire 0 364 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \U2_ADDR_reg<3>_MC.D1 \ ~wire 0 365 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \U2_ADDR_reg<3>_MC.D2 \ ~wire 0 366 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
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		(_signal (_internal \U2_ADDR_reg<3>_MC.D2_PT_3 \ ~wire 0 370 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \U2_ADDR_reg<3>_MC.D2_PT_4 \ ~wire 0 371 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \U2_ADDR_reg<5>_MC.Q \ ~wire 0 372 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \U2_ADDR_reg<5>_MC.D \ ~wire 0 373 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \U2_ADDR_reg<5>_MC.D1 \ ~wire 0 374 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \U2_ADDR_reg<5>_MC.D2 \ ~wire 0 375 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \U2_ADDR_reg<5>_MC.D2_PT_0 \ ~wire 0 376 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \U2_ADDR_reg<5>_MC.D2_PT_1 \ ~wire 0 377 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \N_PZ_989_MC.Q \ ~wire 0 378 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
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		(_signal (_internal \N_PZ_989_MC.D1 \ ~wire 0 380 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \N_PZ_989_MC.D2 \ ~wire 0 381 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \N_PZ_989_MC.D2_PT_0 \ ~wire 0 382 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \N_PZ_989_MC.D2_PT_1 \ ~wire 0 383 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \U2_ADDR_reg<6>_MC.Q \ ~wire 0 384 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \U2_ADDR_reg<6>_MC.D \ ~wire 0 385 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \U2_ADDR_reg<6>_MC.D1 \ ~wire 0 386 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \U2_ADDR_reg<6>_MC.D2 \ ~wire 0 387 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \U2_ADDR_reg<6>_MC.D2_PT_0 \ ~wire 0 388 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \U2_ADDR_reg<6>_MC.D2_PT_1 \ ~wire 0 389 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \U2_ADDR_reg<7>_MC.Q \ ~wire 0 390 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \U2_ADDR_reg<7>_MC.D \ ~wire 0 391 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \U2_ADDR_reg<7>_MC.D1 \ ~wire 0 392 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \U2_ADDR_reg<7>_MC.D2 \ ~wire 0 393 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
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		(_signal (_internal U11_Incdetect ~wire 0 405 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
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		(_signal (_internal \U1/U3/RDedge_MC.Q \ ~wire 0 532 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \U1/U3/RDedge_MC.D \ ~wire 0 533 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \U1/U3/RDedge_MC.REG_tsimcreated_inv_Mclk_II/FCLK \ ~wire 0 534 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \U1/U3/RDedge_MC.D1 \ ~wire 0 535 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \U1/U3/RDedge_MC.D2 \ ~wire 0 536 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \N_PZ_966_MC.Q \ ~wire 0 537 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \N_PZ_966_MC.D \ ~wire 0 538 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \N_PZ_966_MC.D1 \ ~wire 0 539 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \N_PZ_966_MC.D2 \ ~wire 0 540 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal U2_Enable_AD ~wire 0 541 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \N_PZ_966_MC.D2_PT_0 \ ~wire 0 542 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \N_PZ_966_MC.D2_PT_1 \ ~wire 0 543 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \U2_Enable_AD_MC.Q \ ~wire 0 544 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \U2_Enable_AD_MC.D \ ~wire 0 545 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \U2_Enable_AD_MC.D1 \ ~wire 0 546 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \U2_Enable_AD_MC.D2 \ ~wire 0 547 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \U1/Channel0<5>_MC.Q \ ~wire 0 548 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \U1/Channel0<5>_MC.D \ ~wire 0 549 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \U1/Channel0<5>_MC_tsimcreated_xor_ \ ~wire 0 550 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \U1/Channel0<5>_MC.D1 \ ~wire 0 551 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \U1/Channel0<5>_MC.D2 \ ~wire 0 552 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal N_PZ_949 ~wire 0 553 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \U1/Channel0<5>_MC.D2_PT_0 \ ~wire 0 554 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal N_PZ_1018 ~wire 0 555 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal N_PZ_961 ~wire 0 556 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \U1/Channel0<5>_MC.D2_PT_1 \ ~wire 0 557 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \U1/Channel0<5>_MC.D2_PT_2 \ ~wire 0 558 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \N_PZ_949_MC.Q \ ~wire 0 559 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \N_PZ_949_MC.D \ ~wire 0 560 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \N_PZ_949_MC.D1 \ ~wire 0 561 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \N_PZ_949_MC.D2 \ ~wire 0 562 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \U1/Zero0 \ ~wire 0 563 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \U1/Zero0_MC.Q \ ~wire 0 564 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \U1/Zero0_MC.D \ ~wire 0 565 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \U1/Zero0_MC.REG_tsimcreated_inv_Mclk_II/FCLK \ ~wire 0 566 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \U1/Zero0_MC.D1 \ ~wire 0 567 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \U1/Zero0_MC.D2 \ ~wire 0 568 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \U1/Zero0_MC.D2_PT_0 \ ~wire 0 569 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET2482 ~wire 0 570 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \U1/U4/RF0r \ ~wire 0 571 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \U1/U4/HE0statelastr \ ~wire 0 572 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \U1/U4/E0r \ ~wire 0 573 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \U1/Zero0_MC.D2_PT_1 \ ~wire 0 574 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \U1/Zero0_MC.D2_PT_2 \ ~wire 0 575 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NET2482_MC.Q \ ~wire 0 576 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NET2482_MC.D \ ~wire 0 577 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET2482_MC_tsimcreated_xor_ ~wire 0 578 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NET2482_MC.REG_tsimcreated_inv_Mclk_II/FCLK \ ~wire 0 579 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NET2482_MC.D1 \ ~wire 0 580 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NET2482_MC.D2 \ ~wire 0 581 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NET2482_MC.D2_PT_0 \ ~wire 0 582 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NET2482_MC.D2_PT_1 \ ~wire 0 583 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NET2482_MC.D2_PT_2 \ ~wire 0 584 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NET2482_MC.D2_PT_3 \ ~wire 0 585 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \U1/U4/RF0r_MC.Q \ ~wire 0 586 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \U1/U4/RF0r_MC.D \ ~wire 0 587 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \U1/U4/RF0r_MC_tsimcreated_xor_ \ ~wire 0 588 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \U1/U4/RF0r_MC.REG_tsimcreated_inv_Mclk_II/FCLK \ ~wire 0 589 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \U1/U4/RF0r_MC.D1 \ ~wire 0 590 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \U1/U4/RF0r_MC.D2 \ ~wire 0 591 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \U1/U4/RF0r_MC.D2_PT_0 \ ~wire 0 592 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \U1/U4/RF0r_MC.D2_PT_1 \ ~wire 0 593 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \U1/U4/RF0r_MC.D2_PT_2 \ ~wire 0 594 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \U1/U4/HE0statelastr_MC.Q \ ~wire 0 595 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \U1/U4/HE0statelastr_MC.D \ ~wire 0 596 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \U1/U4/HE0statelastr_MC.REG_tsimcreated_inv_Mclk_II/FCLK \ ~wire 0 597 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \U1/U4/HE0statelastr_MC.D1 \ ~wire 0 598 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \U1/U4/HE0statelastr_MC.D2 \ ~wire 0 599 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \U1/U4/E0r_MC.Q \ ~wire 0 600 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \U1/U4/E0r_MC.D \ ~wire 0 601 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \U1/U4/E0r_MC_tsimcreated_xor_ \ ~wire 0 602 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \U1/U4/E0r_MC.REG_tsimcreated_inv_Mclk_II/FCLK \ ~wire 0 603 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \U1/U4/E0r_MC.D1 \ ~wire 0 604 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \U1/U4/E0r_MC.D2 \ ~wire 0 605 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \U1/U4/E0r_MC.D2_PT_0 \ ~wire 0 606 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \U1/U4/E0r_MC.D2_PT_1 \ ~wire 0 607 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \U1/U4/E0r_MC.D2_PT_2 \ ~wire 0 608 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \U1/Channel0<0>_MC.Q \ ~wire 0 609 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \U1/Channel0<0>_MC.D \ ~wire 0 610 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \U1/Channel0<0>_MC.D1 \ ~wire 0 611 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \U1/Channel0<0>_MC.D2 \ ~wire 0 612 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \U1/Channel0<0>_MC.D2_PT_0 \ ~wire 0 613 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \U1/Channel0<0>_MC.D2_PT_1 \ ~wire 0 614 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \N_PZ_1018_MC.Q \ ~wire 0 615 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \N_PZ_1018_MC.D \ ~wire 0 616 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \N_PZ_1018_MC.D1 \ ~wire 0 617 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \N_PZ_1018_MC.D2 \ ~wire 0 618 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \U1/U1/CurrState_Sreg0_FFD3 \ ~wire 0 619 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \U1/U1/CurrState_Sreg0_FFD2 \ ~wire 0 620 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \U1/U1/CurrState_Sreg0_FFD4 \ ~wire 0 621 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \U1/U1/CurrState_Sreg0_FFD1 \ ~wire 0 622 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \N_PZ_1018_MC.D2_PT_0 \ ~wire 0 623 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \N_PZ_1018_MC.D2_PT_1 \ ~wire 0 624 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \U1/U1/CurrState_Sreg0_FFD3_MC.Q \ ~wire 0 625 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \U1/U1/CurrState_Sreg0_FFD3_MC.D \ ~wire 0 626 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \U1/U1/CurrState_Sreg0_FFD3_MC.D1 \ ~wire 0 627 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \U1/U1/CurrState_Sreg0_FFD3_MC.D2 \ ~wire 0 628 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \U1/U1/CurrState_Sreg0_FFD3_MC.D2_PT_0 \ ~wire 0 629 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \U1/U1/CurrState_Sreg0_FFD3_MC.D2_PT_1 \ ~wire 0 630 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal N_PZ_1183 ~wire 0 631 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \U1/U1/CurrState_Sreg0_FFD3_MC.D2_PT_2 \ ~wire 0 632 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \U1/U1/CurrState_Sreg0_FFD2_MC.Q \ ~wire 0 633 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \U1/U1/CurrState_Sreg0_FFD2_MC.D \ ~wire 0 634 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \U1/U1/CurrState_Sreg0_FFD2_MC.D1 \ ~wire 0 635 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \U1/U1/CurrState_Sreg0_FFD2_MC.D2 \ ~wire 0 636 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \U1/U1/CurrState_Sreg0_FFD2_MC.D2_PT_0 \ ~wire 0 637 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \U1/U1/CurrState_Sreg0_FFD2_MC.D2_PT_1 \ ~wire 0 638 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \U1/U1/CurrState_Sreg0_FFD2_MC.D2_PT_2 \ ~wire 0 639 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \U1/U1/CurrState_Sreg0_FFD2_MC.D2_PT_3 \ ~wire 0 640 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \U1/U1/CurrState_Sreg0_FFD4_MC.Q \ ~wire 0 641 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \U1/U1/CurrState_Sreg0_FFD4_MC.D \ ~wire 0 642 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \U1/U1/CurrState_Sreg0_FFD4_MC.D1 \ ~wire 0 643 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \U1/U1/CurrState_Sreg0_FFD4_MC.D2 \ ~wire 0 644 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \U1/U1/CurrState_Sreg0_FFD1_MC.Q \ ~wire 0 645 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \U1/U1/CurrState_Sreg0_FFD1_MC.D \ ~wire 0 646 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \U1/U1/CurrState_Sreg0_FFD1_MC.D1 \ ~wire 0 647 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \U1/U1/CurrState_Sreg0_FFD1_MC.D2 \ ~wire 0 648 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \U1/U1/CurrState_Sreg0_FFD1_MC.D2_PT_0 \ ~wire 0 649 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \U1/U1/CurrState_Sreg0_FFD1_MC.D2_PT_1 \ ~wire 0 650 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \U1/U1/CurrState_Sreg0_FFD1_MC.D2_PT_2 \ ~wire 0 651 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \N_PZ_1183_MC.Q \ ~wire 0 652 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \N_PZ_1183_MC.D \ ~wire 0 653 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \N_PZ_1183_MC.D1 \ ~wire 0 654 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \N_PZ_1183_MC.D2 \ ~wire 0 655 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \N_PZ_1183_MC.D2_PT_0 \ ~wire 0 656 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \N_PZ_1183_MC.D2_PT_1 \ ~wire 0 657 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \U1/Channel0<1>_MC.Q \ ~wire 0 658 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \U1/Channel0<1>_MC.D \ ~wire 0 659 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \U1/Channel0<1>_MC_tsimcreated_xor_ \ ~wire 0 660 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \U1/Channel0<1>_MC.D1 \ ~wire 0 661 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \U1/Channel0<1>_MC.D2 \ ~wire 0 662 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \U1/Channel0<1>_MC.D2_PT_0 \ ~wire 0 663 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \U1/Channel0<1>_MC.D2_PT_1 \ ~wire 0 664 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \U1/Channel0<1>_MC.D2_PT_2 \ ~wire 0 665 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \N_PZ_961_MC.Q \ ~wire 0 666 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \N_PZ_961_MC.D \ ~wire 0 667 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \N_PZ_961_MC.D1 \ ~wire 0 668 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \N_PZ_961_MC.D2 \ ~wire 0 669 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \U1/NET3721 \ ~wire 0 670 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \N_PZ_961_MC.D2_PT_0 \ ~wire 0 671 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \N_PZ_961_MC.D2_PT_1 \ ~wire 0 672 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \U1/NET3721_MC.Q \ ~wire 0 673 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \U1/NET3721_MC.D \ ~wire 0 674 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \U1/NET3721_MC_tsimcreated_xor_ \ ~wire 0 675 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \U1/NET3721_MC.REG_tsimcreated_inv_Mclk_II/FCLK \ ~wire 0 676 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \U1/NET3721_MC.D1 \ ~wire 0 677 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \U1/NET3721_MC.D2 \ ~wire 0 678 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \U1/NET3721_MC.D2_PT_0 \ ~wire 0 679 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \U1/NET3721_MC.D2_PT_1 \ ~wire 0 680 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \U1/NET3721_MC.D2_PT_2 \ ~wire 0 681 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \U1/Channel0<2>_MC.Q \ ~wire 0 682 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \U1/Channel0<2>_MC.D \ ~wire 0 683 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \U1/Channel0<2>_MC_tsimcreated_xor_ \ ~wire 0 684 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \U1/Channel0<2>_MC.D1 \ ~wire 0 685 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \U1/Channel0<2>_MC.D2 \ ~wire 0 686 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \U1/Channel0<2>_MC.D2_PT_0 \ ~wire 0 687 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \U1/Channel0<2>_MC.D2_PT_1 \ ~wire 0 688 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \U1/Channel0<2>_MC.D2_PT_2 \ ~wire 0 689 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \U1/Channel0<3>_MC.Q \ ~wire 0 690 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \U1/Channel0<3>_MC.D \ ~wire 0 691 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \U1/Channel0<3>_MC_tsimcreated_xor_ \ ~wire 0 692 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \U1/Channel0<3>_MC.D1 \ ~wire 0 693 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \U1/Channel0<3>_MC.D2 \ ~wire 0 694 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \U1/Channel0<3>_MC.D2_PT_0 \ ~wire 0 695 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \U1/Channel0<3>_MC.D2_PT_1 \ ~wire 0 696 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \U1/Channel0<3>_MC.D2_PT_2 \ ~wire 0 697 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \U1/Channel0<4>_MC.Q \ ~wire 0 698 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \U1/Channel0<4>_MC.D \ ~wire 0 699 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \U1/Channel0<4>_MC_tsimcreated_xor_ \ ~wire 0 700 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \U1/Channel0<4>_MC.D1 \ ~wire 0 701 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \U1/Channel0<4>_MC.D2 \ ~wire 0 702 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \U1/Channel0<4>_MC.D2_PT_0 \ ~wire 0 703 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \U1/Channel0<4>_MC.D2_PT_1 \ ~wire 0 704 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \U1/Channel0<4>_MC.D2_PT_2 \ ~wire 0 705 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \U1/Channel1<5>_MC.Q \ ~wire 0 706 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \U1/Channel1<5>_MC.D \ ~wire 0 707 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \U1/Channel1<5>_MC_tsimcreated_xor_ \ ~wire 0 708 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \U1/Channel1<5>_MC.D1 \ ~wire 0 709 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \U1/Channel1<5>_MC.D2 \ ~wire 0 710 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal N_PZ_948 ~wire 0 711 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \U1/Channel1<5>_MC.D2_PT_0 \ ~wire 0 712 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal N_PZ_1082 ~wire 0 713 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
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		(_signal (_internal \N_PZ_948_MC.D2 \ ~wire 0 721 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \U1/Zero1 \ ~wire 0 722 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
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		(_signal (_internal \U1/Zero1_MC.REG_tsimcreated_inv_Mclk_II/FCLK \ ~wire 0 725 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \U1/Zero1_MC.D1 \ ~wire 0 726 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \U1/Zero1_MC.D2 \ ~wire 0 727 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \U1/Zero1_MC.D2_PT_0 \ ~wire 0 728 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET2493 ~wire 0 729 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
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		(_signal (_internal \U1/Zero1_MC.D2_PT_1 \ ~wire 0 733 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \U1/Zero1_MC.D2_PT_2 \ ~wire 0 734 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NET2493_MC.Q \ ~wire 0 735 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NET2493_MC.D \ ~wire 0 736 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET2493_MC_tsimcreated_xor_ ~wire 0 737 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NET2493_MC.REG_tsimcreated_inv_Mclk_II/FCLK \ ~wire 0 738 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NET2493_MC.D1 \ ~wire 0 739 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NET2493_MC.D2 \ ~wire 0 740 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NET2493_MC.D2_PT_0 \ ~wire 0 741 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NET2493_MC.D2_PT_1 \ ~wire 0 742 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NET2493_MC.D2_PT_2 \ ~wire 0 743 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NET2493_MC.D2_PT_3 \ ~wire 0 744 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \U1/U4/RF1r_MC.Q \ ~wire 0 745 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \U1/U4/RF1r_MC.D \ ~wire 0 746 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
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		(_signal (_internal \U1/U4/RF1r_MC.REG_tsimcreated_inv_Mclk_II/FCLK \ ~wire 0 748 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \U1/U4/RF1r_MC.D1 \ ~wire 0 749 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
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		(_signal (_internal \U1/U4/E1r_MC.REG_tsimcreated_inv_Mclk_II/FCLK \ ~wire 0 757 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \U1/U4/E1r_MC.D1 \ ~wire 0 758 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
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		(_signal (_internal \U1/U4/E1r_MC.D2_PT_0 \ ~wire 0 760 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
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		(_signal (_internal \U1/U4/HE1statelastr_MC.Q \ ~wire 0 763 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \U1/U4/HE1statelastr_MC.D \ ~wire 0 764 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \U1/U4/HE1statelastr_MC.REG_tsimcreated_inv_Mclk_II/FCLK \ ~wire 0 765 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \U1/U4/HE1statelastr_MC.D1 \ ~wire 0 766 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \U1/U4/HE1statelastr_MC.D2 \ ~wire 0 767 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \U1/Channel1<0>_MC.Q \ ~wire 0 768 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \U1/Channel1<0>_MC.D \ ~wire 0 769 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \U1/Channel1<0>_MC.D1 \ ~wire 0 770 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
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		(_signal (_internal \U1/Channel1<0>_MC.D2_PT_0 \ ~wire 0 772 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \U1/Channel1<0>_MC.D2_PT_1 \ ~wire 0 773 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
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		(_signal (_internal \N_PZ_1082_MC.D2 \ ~wire 0 777 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \U1/U6/CurrState_Sreg0_FFD3 \ ~wire 0 778 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \U1/U6/CurrState_Sreg0_FFD2 \ ~wire 0 779 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \U1/U6/CurrState_Sreg0_FFD4 \ ~wire 0 780 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \U1/U6/CurrState_Sreg0_FFD1 \ ~wire 0 781 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
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		(_signal (_internal \N_PZ_1082_MC.D2_PT_1 \ ~wire 0 783 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
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		(_signal (_internal \U1/U6/CurrState_Sreg0_FFD3_MC.D2_PT_1 \ ~wire 0 789 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal N_PZ_1184 ~wire 0 790 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \U1/U6/CurrState_Sreg0_FFD3_MC.D2_PT_2 \ ~wire 0 791 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
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		(_signal (_internal \U1/Channel0<17>_MC.D2_PT_2 \ ~wire 0 1042 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
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		(_signal (_internal \U1/Channel1<19>_MC.D \ ~wire 0 1216 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \U1/Channel1<19>_MC_tsimcreated_xor_ \ ~wire 0 1217 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \U1/Channel1<19>_MC.D1 \ ~wire 0 1218 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
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		(_signal (_internal \U1/U3/holdingreg<13>_MC.REG_tsimcreated_inv_Mclk_II/FCLK \ ~wire 0 1233 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \U1/U3/holdingreg<13>_MC.D1 \ ~wire 0 1234 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
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		(_signal (_internal NET2501 ~wire 0 1260 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
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		(_signal (_internal \U1/U4/LatchEdge0r \ ~wire 0 1262 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
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		(_signal (_internal NET2501_MC_tsimcreated_xor_ ~wire 0 1270 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NET2501_MC.REG_tsimcreated_inv_Mclk_II/FCLK \ ~wire 0 1271 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NET2501_MC.D1 \ ~wire 0 1272 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
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		(_signal (_internal \U1/U4/Latch0r<15>_MC.D \ ~wire 0 1541 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \U1/U4/Latch0r<15>_MC.REG_tsimcreated_inv_Mclk_II/FCLK \ ~wire 0 1542 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \U1/U4/Latch0r<15>_MC.D1 \ ~wire 0 1543 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \U1/U4/Latch0r<15>_MC.D2 \ ~wire 0 1544 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \U1/U4/Latch0r<15>_MC.D2_PT_0 \ ~wire 0 1545 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \U1/U4/Latch0r<15>_MC.D2_PT_1 \ ~wire 0 1546 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \U1/U4/Latch0r<7>_MC.Q \ ~wire 0 1547 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \U1/U4/Latch0r<7>_MC.D \ ~wire 0 1548 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \U1/U4/Latch0r<7>_MC.REG_tsimcreated_inv_Mclk_II/FCLK \ ~wire 0 1549 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \U1/U4/Latch0r<7>_MC.D1 \ ~wire 0 1550 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \U1/U4/Latch0r<7>_MC.D2 \ ~wire 0 1551 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \U1/U4/Latch0r<7>_MC.D2_PT_0 \ ~wire 0 1552 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \U1/U4/Latch0r<7>_MC.D2_PT_1 \ ~wire 0 1553 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \U1/U4/Latch1r<7>_MC.Q \ ~wire 0 1554 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \U1/U4/Latch1r<7>_MC.D \ ~wire 0 1555 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \U1/U4/Latch1r<7>_MC.REG_tsimcreated_inv_Mclk_II/FCLK \ ~wire 0 1556 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \U1/U4/Latch1r<7>_MC.D1 \ ~wire 0 1557 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \U1/U4/Latch1r<7>_MC.D2 \ ~wire 0 1558 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \U1/U4/Latch1r<7>_MC.D2_PT_0 \ ~wire 0 1559 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \U1/U4/Latch1r<7>_MC.D2_PT_1 \ ~wire 0 1560 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \U1/U4/Latch1r<15>_MC.Q \ ~wire 0 1561 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \U1/U4/Latch1r<15>_MC.D \ ~wire 0 1562 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \U1/U4/Latch1r<15>_MC.REG_tsimcreated_inv_Mclk_II/FCLK \ ~wire 0 1563 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \U1/U4/Latch1r<15>_MC.D1 \ ~wire 0 1564 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \U1/U4/Latch1r<15>_MC.D2 \ ~wire 0 1565 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \U1/U4/Latch1r<15>_MC.D2_PT_0 \ ~wire 0 1566 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \U1/U4/Latch1r<15>_MC.D2_PT_1 \ ~wire 0 1567 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \Enc033ctrl_MC.Q_tsimrenamed_net_ \ ~wire 0 1568 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal Enc033ctrl_MC_tsimcreated_prld_ ~wire 0 1569 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \Enc033ctrl_MC.D \ ~wire 0 1570 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \FOOBAR23__ctinst/4 \ ~wire 0 1571 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \Enc033ctrl_MC.D1 \ ~wire 0 1572 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \Enc033ctrl_MC.D2 \ ~wire 0 1573 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \Enc05ctrl_MC.Q_tsimrenamed_net_ \ ~wire 0 1574 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal Enc05ctrl_MC_tsimcreated_prld_ ~wire 0 1575 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \Enc05ctrl_MC.D \ ~wire 0 1576 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \Enc05ctrl_MC.CE \ ~wire 0 1577 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \Enc05ctrl_MC.D1 \ ~wire 0 1578 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \Enc05ctrl_MC.D2 \ ~wire 0 1579 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \Enc133ctrl_MC.Q_tsimrenamed_net_ \ ~wire 0 1580 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal Enc133ctrl_MC_tsimcreated_prld_ ~wire 0 1581 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \Enc133ctrl_MC.D \ ~wire 0 1582 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \Enc133ctrl_MC.CE \ ~wire 0 1583 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \Enc133ctrl_MC.D1 \ ~wire 0 1584 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \Enc133ctrl_MC.D2 \ ~wire 0 1585 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \Enc15ctrl_MC.Q_tsimrenamed_net_ \ ~wire 0 1586 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal Enc15ctrl_MC_tsimcreated_prld_ ~wire 0 1587 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \Enc15ctrl_MC.D \ ~wire 0 1588 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \Enc15ctrl_MC.CE \ ~wire 0 1589 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \Enc15ctrl_MC.D1 \ ~wire 0 1590 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \Enc15ctrl_MC.D2 \ ~wire 0 1591 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \GP_Motor0_1_MC.Q_tsimrenamed_net_ \ ~wire 0 1592 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal GP_Motor0_1_MC_tsimcreated_prld_ ~wire 0 1593 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \GP_Motor0_1_MC.D \ ~wire 0 1594 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \FOOBAR8__ctinst/4 \ ~wire 0 1595 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \GP_Motor0_1_MC.D1 \ ~wire 0 1596 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \GP_Motor0_1_MC.D2 \ ~wire 0 1597 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \GP_Motor1_1_MC.Q_tsimrenamed_net_ \ ~wire 0 1598 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal GP_Motor1_1_MC_tsimcreated_prld_ ~wire 0 1599 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \GP_Motor1_1_MC.D \ ~wire 0 1600 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \FOOBAR15__ctinst/4 \ ~wire 0 1601 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \GP_Motor1_1_MC.D1 \ ~wire 0 1602 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \GP_Motor1_1_MC.D2 \ ~wire 0 1603 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \HSO_MC.Q_tsimrenamed_net_ \ ~wire 0 1604 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \HSO_MC.D \ ~wire 0 1605 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \HSO_MC.D1 \ ~wire 0 1606 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \HSO_MC.D2 \ ~wire 0 1607 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \Home033ctrl_MC.Q_tsimrenamed_net_ \ ~wire 0 1608 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal Home033ctrl_MC_tsimcreated_prld_ ~wire 0 1609 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \Home033ctrl_MC.D \ ~wire 0 1610 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \Home033ctrl_MC.CE \ ~wire 0 1611 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \Home033ctrl_MC.D1 \ ~wire 0 1612 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \Home033ctrl_MC.D2 \ ~wire 0 1613 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \Home05ctrl_MC.Q_tsimrenamed_net_ \ ~wire 0 1614 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal Home05ctrl_MC_tsimcreated_prld_ ~wire 0 1615 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \Home05ctrl_MC.D \ ~wire 0 1616 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \FOOBAR14__ctinst/4 \ ~wire 0 1617 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \Home05ctrl_MC.D1 \ ~wire 0 1618 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \Home05ctrl_MC.D2 \ ~wire 0 1619 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \Home133ctrl_MC.Q_tsimrenamed_net_ \ ~wire 0 1620 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal Home133ctrl_MC_tsimcreated_prld_ ~wire 0 1621 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \Home133ctrl_MC.D \ ~wire 0 1622 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \Home133ctrl_MC.D1 \ ~wire 0 1623 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \Home133ctrl_MC.D2 \ ~wire 0 1624 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \Home15ctrl_MC.Q_tsimrenamed_net_ \ ~wire 0 1625 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal Home15ctrl_MC_tsimcreated_prld_ ~wire 0 1626 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \Home15ctrl_MC.D \ ~wire 0 1627 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \Home15ctrl_MC.CE \ ~wire 0 1628 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \Home15ctrl_MC.D1 \ ~wire 0 1629 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \Home15ctrl_MC.D2 \ ~wire 0 1630 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \INT_MC.Q_tsimrenamed_net_ \ ~wire 0 1631 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \INT_MC.D \ ~wire 0 1632 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \INT_MC.D1 \ ~wire 0 1633 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \INT_MC.D2 \ ~wire 0 1634 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \INT_MC.D2_PT_0 \ ~wire 0 1635 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \INT_MC.D2_PT_1 \ ~wire 0 1636 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \INT_MC.D2_PT_2 \ ~wire 0 1637 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \INT_MC.D2_PT_3 \ ~wire 0 1638 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \INT_MC.D2_PT_4 \ ~wire 0 1639 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET2575 ~wire 0 1640 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \INT_MC.D2_PT_5 \ ~wire 0 1641 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET2512 ~wire 0 1642 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \INT_MC.D2_PT_6 \ ~wire 0 1643 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \INT_MC.D2_PT_7 \ ~wire 0 1644 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \U3/DCORIE<0>_MC.Q \ ~wire 0 1645 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \U3/DCORIE<0>_MC.D \ ~wire 0 1646 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \U3/DCORIE<0>_MC_tsimcreated_xor_ \ ~wire 0 1647 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \U3/DCORIE<0>_MC.D1 \ ~wire 0 1648 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \U3/DCORIE<0>_MC.D2 \ ~wire 0 1649 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \U3/DCORIE<0>_MC.D2_PT_0 \ ~wire 0 1650 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \U3/DCORIE<0>_MC.D2_PT_1 \ ~wire 0 1651 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \U3/DCORIE<0>_MC.D2_PT_2 \ ~wire 0 1652 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \U3/DCORIE<1>_MC.Q \ ~wire 0 1653 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \U3/DCORIE<1>_MC.D \ ~wire 0 1654 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \U3/DCORIE<1>_MC_tsimcreated_xor_ \ ~wire 0 1655 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \U3/DCORIE<1>_MC.D1 \ ~wire 0 1656 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \U3/DCORIE<1>_MC.D2 \ ~wire 0 1657 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \U3/DCORIE<1>_MC.D2_PT_0 \ ~wire 0 1658 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \U3/DCORIE<1>_MC.D2_PT_1 \ ~wire 0 1659 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \U3/DCORIE<1>_MC.D2_PT_2 \ ~wire 0 1660 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \U3/DCORIE<2>_MC.Q \ ~wire 0 1661 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \U3/DCORIE<2>_MC.D \ ~wire 0 1662 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \U3/DCORIE<2>_MC_tsimcreated_xor_ \ ~wire 0 1663 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \U3/DCORIE<2>_MC.D1 \ ~wire 0 1664 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \U3/DCORIE<2>_MC.D2 \ ~wire 0 1665 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \U3/DCORIE<2>_MC.D2_PT_0 \ ~wire 0 1666 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \U3/DCORIE<2>_MC.D2_PT_1 \ ~wire 0 1667 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \U3/DCORIE<2>_MC.D2_PT_2 \ ~wire 0 1668 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \U3/DCORIE<3>_MC.Q \ ~wire 0 1669 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \U3/DCORIE<3>_MC.D \ ~wire 0 1670 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
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		(_signal (_internal \U3/DCORIE<3>_MC.D1 \ ~wire 0 1672 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \U3/DCORIE<3>_MC.D2 \ ~wire 0 1673 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \U3/DCORIE<3>_MC.D2_PT_0 \ ~wire 0 1674 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \U3/DCORIE<3>_MC.D2_PT_1 \ ~wire 0 1675 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \U3/DCORIE<3>_MC.D2_PT_2 \ ~wire 0 1676 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NET2575_MC.Q \ ~wire 0 1677 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
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		(_signal (_internal NET2575_MC_tsimcreated_xor_ ~wire 0 1679 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NET2575_MC.D1 \ ~wire 0 1680 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
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		(_signal (_internal \NET2575_MC.D2_PT_2 \ ~wire 0 1684 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
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		(_signal (_internal \NET2575_MC.D2_PT_4 \ ~wire 0 1686 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
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		(_signal (_internal \NET2575_MC.D2_PT_6 \ ~wire 0 1688 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
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		(_signal (_internal \NET2512_MC.REG_tsimcreated_inv_Mclk_II/FCLK \ ~wire 0 1708 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
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		(_signal (_internal \U1/U4/LatchEdge1r_MC.Q \ ~wire 0 1716 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \U1/U4/LatchEdge1r_MC.D \ ~wire 0 1717 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \U1/U4/LatchEdge1r_MC_tsimcreated_xor_ \ ~wire 0 1718 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \U1/U4/LatchEdge1r_MC.REG_tsimcreated_inv_Mclk_II/FCLK \ ~wire 0 1719 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \U1/U4/LatchEdge1r_MC.D1 \ ~wire 0 1720 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \U1/U4/LatchEdge1r_MC.D2 \ ~wire 0 1721 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \U1/U4/LatchEdge1r_MC.D2_PT_0 \ ~wire 0 1722 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \U1/U4/LatchEdge1r_MC.D2_PT_1 \ ~wire 0 1723 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
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		(_signal (_internal \U9/MISCr<1>_MC.D2_PT_4 \ ~wire 0 1778 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \outDATA<1>\\$WA2.UIM \ ~wire 0 1779 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \U9/MISCr<1>_MC.D2_PT_5 \ ~wire 0 1780 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
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		(_signal (_internal \PBH0_MC.D \ ~wire 0 1891 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
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		(_signal (_internal \PBH1_MC.Q_tsimrenamed_net_ \ ~wire 0 1894 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \PBH1_MC.D \ ~wire 0 1895 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \PBH1_MC.D1 \ ~wire 0 1896 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \PBH1_MC.D2 \ ~wire 0 1897 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \PBH1_MC.D2_PT_0 \ ~wire 0 1898 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \PBH1_MC.D2_PT_1 \ ~wire 0 1899 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \PBL0_MC.Q_tsimrenamed_net_ \ ~wire 0 1900 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \PBL0_MC.D \ ~wire 0 1901 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \PBL0_MC.D1 \ ~wire 0 1902 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \PBL0_MC.D2 \ ~wire 0 1903 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \PBL0_MC.D2_PT_0 \ ~wire 0 1904 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \PBL0_MC.D2_PT_1 \ ~wire 0 1905 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \PBL1_MC.Q_tsimrenamed_net_ \ ~wire 0 1906 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \PBL1_MC.D \ ~wire 0 1907 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \PBL1_MC.D1 \ ~wire 0 1908 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \PBL1_MC.D2 \ ~wire 0 1909 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \outDATA<0>\\$WA0.UIM_MC.Q \ ~wire 0 1910 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
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		(_signal (_internal \outDATA<0>\\$WA0.UIM_MC.D2 \ ~wire 0 1913 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \outDATA<0>\\$WA1.UIM_MC.Q \ ~wire 0 1914 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
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		(_signal (_internal \outDATA<0>\\$WA1.UIM_MC.D2 \ ~wire 0 1917 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \outDATA<0>\\$WA2.UIM_MC.Q \ ~wire 0 1918 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \outDATA<0>\\$WA2.UIM_MC.D \ ~wire 0 1919 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \outDATA<0>\\$WA2.UIM_MC.D1 \ ~wire 0 1920 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \outDATA<0>\\$WA2.UIM_MC.D2 \ ~wire 0 1921 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \outDATA<0>\\$WA3.UIM_MC.Q \ ~wire 0 1922 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \outDATA<0>\\$WA3.UIM_MC.D \ ~wire 0 1923 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \outDATA<0>\\$WA3.UIM_MC.D1 \ ~wire 0 1924 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \outDATA<0>\\$WA3.UIM_MC.D2 \ ~wire 0 1925 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \outDATA<0>\\$WA3.UIM_MC.D2_PT_0 \ ~wire 0 1926 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \outDATA<0>\\$WA3.UIM_MC.D2_PT_1 \ ~wire 0 1927 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \outDATA<0>\\$WA5.UIM_MC.Q \ ~wire 0 1928 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \outDATA<0>\\$WA5.UIM_MC.D \ ~wire 0 1929 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \outDATA<0>\\$WA5.UIM_MC.D1 \ ~wire 0 1930 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \outDATA<0>\\$WA5.UIM_MC.D2 \ ~wire 0 1931 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \outDATA<0>\\$WA5.UIM_MC.D2_PT_0 \ ~wire 0 1932 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \outDATA<0>\\$WA5.UIM_MC.D2_PT_1 \ ~wire 0 1933 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \outDATA<0>\\$WA5.UIM_MC.D2_PT_2 \ ~wire 0 1934 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \U1/U3/holdingreg<0>_MC.Q \ ~wire 0 1935 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \U1/U3/holdingreg<0>_MC.D \ ~wire 0 1936 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \U1/U3/holdingreg<0>_MC.REG_tsimcreated_inv_Mclk_II/FCLK \ ~wire 0 1937 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \U1/U3/holdingreg<0>_MC.D1 \ ~wire 0 1938 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \U1/U3/holdingreg<0>_MC.D2 \ ~wire 0 1939 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \U1/U3/holdingreg<0>_MC.D2_PT_0 \ ~wire 0 1940 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \U1/U3/holdingreg<0>_MC.D2_PT_1 \ ~wire 0 1941 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \U1/U3/holdingreg<0>_MC.D2_PT_2 \ ~wire 0 1942 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \U1/U3/holdingreg<16>_MC.Q \ ~wire 0 1943 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \U1/U3/holdingreg<16>_MC.D \ ~wire 0 1944 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \U1/U3/holdingreg<16>_MC.REG_tsimcreated_inv_Mclk_II/FCLK \ ~wire 0 1945 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \U1/U3/holdingreg<16>_MC.D1 \ ~wire 0 1946 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \U1/U3/holdingreg<16>_MC.D2 \ ~wire 0 1947 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \U1/U3/holdingreg<16>_MC.D2_PT_0 \ ~wire 0 1948 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \U1/U3/holdingreg<16>_MC.D2_PT_1 \ ~wire 0 1949 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \U1/U3/holdingreg<16>_MC.D2_PT_2 \ ~wire 0 1950 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \U1/U3/holdingreg<8>_MC.Q \ ~wire 0 1951 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \U1/U3/holdingreg<8>_MC.D \ ~wire 0 1952 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \U1/U3/holdingreg<8>_MC.REG_tsimcreated_inv_Mclk_II/FCLK \ ~wire 0 1953 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \U1/U3/holdingreg<8>_MC.D1 \ ~wire 0 1954 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \U1/U3/holdingreg<8>_MC.D2 \ ~wire 0 1955 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \U1/U3/holdingreg<8>_MC.D2_PT_0 \ ~wire 0 1956 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \U1/U3/holdingreg<8>_MC.D2_PT_1 \ ~wire 0 1957 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \U1/U3/holdingreg<8>_MC.D2_PT_2 \ ~wire 0 1958 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \outDATA<0>\\$WA4.UIM_MC.Q \ ~wire 0 1959 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \outDATA<0>\\$WA4.UIM_MC.D \ ~wire 0 1960 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \outDATA<0>\\$WA4.UIM_MC.D1 \ ~wire 0 1961 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \outDATA<0>\\$WA4.UIM_MC.D2 \ ~wire 0 1962 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \outDATA<0>\\$WA4.UIM_MC.D2_PT_0 \ ~wire 0 1963 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \outDATA<0>\\$WA4.UIM_MC.D2_PT_1 \ ~wire 0 1964 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \outDATA<0>\\$WA4.UIM_MC.D2_PT_2 \ ~wire 0 1965 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \outDATA<0>\\$WA4.UIM_MC.D2_PT_3 \ ~wire 0 1966 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
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		(_signal (_internal \U1/U4/Latch0r<0>_MC.D \ ~wire 0 1968 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \U1/U4/Latch0r<0>_MC.REG_tsimcreated_inv_Mclk_II/FCLK \ ~wire 0 1969 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \U1/U4/Latch0r<0>_MC.D1 \ ~wire 0 1970 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \U1/U4/Latch0r<0>_MC.D2 \ ~wire 0 1971 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \U1/U4/Latch0r<0>_MC.D2_PT_0 \ ~wire 0 1972 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \U1/U4/Latch0r<0>_MC.D2_PT_1 \ ~wire 0 1973 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \U1/U4/Latch0r<8>_MC.Q \ ~wire 0 1974 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \U1/U4/Latch0r<8>_MC.D \ ~wire 0 1975 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \U1/U4/Latch0r<8>_MC.REG_tsimcreated_inv_Mclk_II/FCLK \ ~wire 0 1976 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \U1/U4/Latch0r<8>_MC.D1 \ ~wire 0 1977 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \U1/U4/Latch0r<8>_MC.D2 \ ~wire 0 1978 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \U1/U4/Latch0r<8>_MC.D2_PT_0 \ ~wire 0 1979 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
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		(_signal (_internal \U1/U4/Latch1r<0>_MC.Q \ ~wire 0 1981 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \U1/U4/Latch1r<0>_MC.D \ ~wire 0 1982 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \U1/U4/Latch1r<0>_MC.REG_tsimcreated_inv_Mclk_II/FCLK \ ~wire 0 1983 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \U1/U4/Latch1r<0>_MC.D1 \ ~wire 0 1984 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \U1/U4/Latch1r<0>_MC.D2 \ ~wire 0 1985 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \U1/U4/Latch1r<0>_MC.D2_PT_0 \ ~wire 0 1986 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \U1/U4/Latch1r<0>_MC.D2_PT_1 \ ~wire 0 1987 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \U1/U4/Latch1r<8>_MC.Q \ ~wire 0 1988 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \U1/U4/Latch1r<8>_MC.D \ ~wire 0 1989 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \U1/U4/Latch1r<8>_MC.REG_tsimcreated_inv_Mclk_II/FCLK \ ~wire 0 1990 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \U1/U4/Latch1r<8>_MC.D1 \ ~wire 0 1991 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \U1/U4/Latch1r<8>_MC.D2 \ ~wire 0 1992 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \U1/U4/Latch1r<8>_MC.D2_PT_0 \ ~wire 0 1993 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \U1/U4/Latch1r<8>_MC.D2_PT_1 \ ~wire 0 1994 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \outDATA<1>\\$WA1.UIM_MC.Q \ ~wire 0 1995 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \outDATA<1>\\$WA1.UIM_MC.D \ ~wire 0 1996 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \outDATA<1>\\$WA1.UIM_MC.D1 \ ~wire 0 1997 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
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		(_signal (_internal \U1/U4/Latch0r<4>_MC.D2_PT_1 \ ~wire 0 2320 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
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		(_signal (_internal \U1/U4/Latch1r<4>_MC.REG_tsimcreated_inv_Mclk_II/FCLK \ ~wire 0 2323 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
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		(_signal (_internal \U1/U4/Latch1r<4>_MC.D2_PT_0 \ ~wire 0 2326 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \U1/U4/Latch1r<4>_MC.D2_PT_1 \ ~wire 0 2327 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \U1/U4/Latch1r<12>_MC.Q \ ~wire 0 2328 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \U1/U4/Latch1r<12>_MC.D \ ~wire 0 2329 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \U1/U4/Latch1r<12>_MC.REG_tsimcreated_inv_Mclk_II/FCLK \ ~wire 0 2330 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \U1/U4/Latch1r<12>_MC.D1 \ ~wire 0 2331 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \U1/U4/Latch1r<12>_MC.D2 \ ~wire 0 2332 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \U1/U4/Latch1r<12>_MC.D2_PT_0 \ ~wire 0 2333 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \U1/U4/Latch1r<12>_MC.D2_PT_1 \ ~wire 0 2334 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_AD<5>_MC.D/IN0 \ ~wire 0 2335 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_AD<5>_MC.D2_PT_0/IN0 \ ~wire 0 2336 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_AD<5>_MC.D2_PT_1/IN0 \ ~wire 0 2337 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_AD<5>_MC.D2_PT_2/IN1 \ ~wire 0 2338 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_AD<5>_MC.D2_PT_2/IN7 \ ~wire 0 2339 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_AD<5>_MC.D2_PT_3/IN1 \ ~wire 0 2340 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_AD<5>_MC.D2_PT_3/IN5 \ ~wire 0 2341 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_AD<5>_MC.D2_PT_3/IN6 \ ~wire 0 2342 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_AD<5>_MC.D2_PT_3/IN7 \ ~wire 0 2343 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_AD<5>_MC.D2_PT_4/IN1 \ ~wire 0 2344 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_AD<5>_MC.D2_PT_4/IN3 \ ~wire 0 2345 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_AD<5>_MC.D2_PT_4/IN7 \ ~wire 0 2346 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_AD<5>_MC.D2_PT_5/IN1 \ ~wire 0 2347 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_AD<5>_MC.D2_PT_5/IN2 \ ~wire 0 2348 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_AD<5>_MC.D2_PT_5/IN3 \ ~wire 0 2349 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_AD<5>_MC.D2_PT_5/IN5 \ ~wire 0 2350 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_AD<5>_MC.D2_PT_5/IN6 \ ~wire 0 2351 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_AD<5>_MC.D2_PT_5/IN7 \ ~wire 0 2352 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U2_ADDR_reg<1>_MC.D2_PT_0/IN1 \ ~wire 0 2353 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U2_ADDR_reg<1>_MC.D2_PT_0/IN2 \ ~wire 0 2354 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U2_ADDR_reg<1>_MC.D2_PT_1/IN1 \ ~wire 0 2355 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U2_ADDR_reg<1>_MC.D2_PT_2/IN1 \ ~wire 0 2356 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U2_ADDR_reg<1>_MC.D2_PT_2/IN4 \ ~wire 0 2357 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U2_ADDR_reg<1>_MC.D2_PT_3/IN0 \ ~wire 0 2358 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U2_ADDR_reg<1>_MC.D2_PT_3/IN4 \ ~wire 0 2359 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U2_ADDR_reg<0>_MC.D2_PT_1/IN2 \ ~wire 0 2360 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U2_ADDR_reg<0>_MC.D2_PT_2/IN0 \ ~wire 0 2361 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U2_ADDR_reg<0>_MC.D2_PT_2/IN2 \ ~wire 0 2362 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U2_ADDR_reg<0>_MC.D2_PT_3/IN3 \ ~wire 0 2363 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U2_ADDR_reg<0>_MC.D2_PT_3/IN4 \ ~wire 0 2364 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U2_ADDR_reg<0>_MC.D2_PT_3/IN6 \ ~wire 0 2365 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_N_PZ_947_MC.D1/IN0 \ ~wire 0 2366 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U2_AutoInc_MC.D/IN0 \ ~wire 0 2367 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U2__n0017_MC.D1/IN0 \ ~wire 0 2368 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U2__n0017_MC.D1/IN1 \ ~wire 0 2369 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_N_PZ_931_MC.D1/IN0 \ ~wire 0 2370 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_N_PZ_931_MC.D1/IN1 \ ~wire 0 2371 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_N_PZ_931_MC.D1/IN2 \ ~wire 0 2372 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_N_PZ_931_MC.D1/IN3 \ ~wire 0 2373 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U2_ADDR_reg<4>_MC.D2_PT_1/IN2 \ ~wire 0 2374 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U2_ADDR_reg<4>_MC.D2_PT_2/IN1 \ ~wire 0 2375 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U2_ADDR_reg<4>_MC.D2_PT_2/IN2 \ ~wire 0 2376 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U2_ADDR_reg<4>_MC.D2_PT_3/IN6 \ ~wire 0 2377 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U2_ADDR_reg<4>_MC.D2_PT_3/IN7 \ ~wire 0 2378 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U2_ADDR_reg<4>_MC.D2_PT_3/IN9 \ ~wire 0 2379 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U2_ADDR_reg<4>_MC.D2_PT_3/IN10 \ ~wire 0 2380 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U2_ADDR_reg<4>_MC.D2_PT_3/IN11 \ ~wire 0 2381 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U2_ADDR_reg<4>_MC.D2_PT_3/IN12 \ ~wire 0 2382 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U2_ADDR_reg<2>_MC.D2_PT_1/IN2 \ ~wire 0 2383 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U2_ADDR_reg<2>_MC.D2_PT_2/IN0 \ ~wire 0 2384 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U2_ADDR_reg<2>_MC.D2_PT_2/IN2 \ ~wire 0 2385 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U2_ADDR_reg<2>_MC.D2_PT_3/IN2 \ ~wire 0 2386 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U2_ADDR_reg<2>_MC.D2_PT_3/IN4 \ ~wire 0 2387 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U2_ADDR_reg<2>_MC.D2_PT_3/IN6 \ ~wire 0 2388 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U2_ADDR_reg<2>_MC.D2_PT_4/IN5 \ ~wire 0 2389 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U2_ADDR_reg<2>_MC.D2_PT_4/IN6 \ ~wire 0 2390 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U2_ADDR_reg<2>_MC.D2_PT_4/IN8 \ ~wire 0 2391 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U2_ADDR_reg<3>_MC.D2_PT_1/IN2 \ ~wire 0 2392 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U2_ADDR_reg<3>_MC.D2_PT_2/IN0 \ ~wire 0 2393 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U2_ADDR_reg<3>_MC.D2_PT_2/IN2 \ ~wire 0 2394 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U2_ADDR_reg<3>_MC.D2_PT_3/IN2 \ ~wire 0 2395 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U2_ADDR_reg<3>_MC.D2_PT_3/IN4 \ ~wire 0 2396 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U2_ADDR_reg<3>_MC.D2_PT_3/IN6 \ ~wire 0 2397 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U2_ADDR_reg<3>_MC.D2_PT_4/IN6 \ ~wire 0 2398 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U2_ADDR_reg<3>_MC.D2_PT_4/IN7 \ ~wire 0 2399 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U2_ADDR_reg<3>_MC.D2_PT_4/IN9 \ ~wire 0 2400 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U2_ADDR_reg<5>_MC.D2_PT_0/IN1 \ ~wire 0 2401 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U2_ADDR_reg<5>_MC.D2_PT_1/IN0 \ ~wire 0 2402 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U2_ADDR_reg<5>_MC.D2_PT_1/IN1 \ ~wire 0 2403 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_N_PZ_989_MC.D2_PT_1/IN2 \ ~wire 0 2404 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_N_PZ_989_MC.D2_PT_1/IN4 \ ~wire 0 2405 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U2_ADDR_reg<6>_MC.D2_PT_0/IN1 \ ~wire 0 2406 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U2_ADDR_reg<6>_MC.D2_PT_1/IN0 \ ~wire 0 2407 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U2_ADDR_reg<6>_MC.D2_PT_1/IN1 \ ~wire 0 2408 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U2_ADDR_reg<7>_MC.D2_PT_0/IN1 \ ~wire 0 2409 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U2_ADDR_reg<7>_MC.D2_PT_1/IN0 \ ~wire 0 2410 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U2_ADDR_reg<7>_MC.D2_PT_1/IN1 \ ~wire 0 2411 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U11_U3_counterr<5>_MC.D2_PT_1/IN0 \ ~wire 0 2412 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U11_U3_counterr<5>_MC.D2_PT_2/IN0 \ ~wire 0 2413 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U11_U3_counterr<5>_MC.D2_PT_2/IN6 \ ~wire 0 2414 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U11_U3_counterr<5>_MC.D2_PT_3/IN1 \ ~wire 0 2415 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U11_U3_counterr<5>_MC.D2_PT_3/IN2 \ ~wire 0 2416 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U11_U3_counterr<5>_MC.D2_PT_3/IN3 \ ~wire 0 2417 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
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		(_signal (_internal \NlwInverterSignal_U11_U3_counterr<3>_MC.D2_PT_2/IN0 \ ~wire 0 2424 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U11_U3_counterr<3>_MC.D2_PT_2/IN1 \ ~wire 0 2425 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U11_U3_counterr<3>_MC.D2_PT_3/IN0 \ ~wire 0 2426 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U11_U3_counterr<3>_MC.D2_PT_3/IN1 \ ~wire 0 2427 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
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		(_signal (_internal \NlwInverterSignal_U11_U3_counterr<3>_MC.D2_PT_4/IN1 \ ~wire 0 2429 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U11_U3_counterr<3>_MC.D2_PT_4/IN2 \ ~wire 0 2430 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
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		(_signal (_internal \NlwInverterSignal_U11_U3_counterr<3>_MC.D2_PT_5/IN1 \ ~wire 0 2432 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U11_U3_counterr<3>_MC.D2_PT_5/IN2 \ ~wire 0 2433 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U11_U3_counterr<3>_MC.D2_PT_5/IN3 \ ~wire 0 2434 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U11_U3_counterr<3>_MC.D2_PT_5/IN4 \ ~wire 0 2435 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
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		(_signal (_internal \NlwInverterSignal_U11_U3_counterr<3>_MC.D2_PT_6/IN4 \ ~wire 0 2437 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U11_U3_counterr<0>_MC.D/IN0 \ ~wire 0 2438 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
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		(_signal (_internal \NlwInverterSignal_U11_U3_counterr<0>_MC.D2_PT_2/IN0 \ ~wire 0 2440 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U11_U3_counterr<0>_MC.D2_PT_2/IN1 \ ~wire 0 2441 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U11_U3_counterr<0>_MC.D2_PT_2/IN2 \ ~wire 0 2442 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U11_U3_counterr<0>_MC.D2_PT_3/IN0 \ ~wire 0 2443 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U11_U3_counterr<0>_MC.D2_PT_3/IN1 \ ~wire 0 2444 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U11_U3_counterr<0>_MC.D2_PT_3/IN2 \ ~wire 0 2445 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
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		(_signal (_internal \NlwInverterSignal_U11_U3_counterr<0>_MC.D2_PT_3/IN4 \ ~wire 0 2447 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
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		(_signal (_internal \NlwInverterSignal_U11_U3_counterr<4>_MC.D2_PT_1/IN0 \ ~wire 0 2450 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U11_U3_counterr<4>_MC.D2_PT_2/IN0 \ ~wire 0 2451 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U11_U3_counterr<4>_MC.D2_PT_2/IN5 \ ~wire 0 2452 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U11_U3_counterr<4>_MC.D2_PT_3/IN0 \ ~wire 0 2453 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U11_U3_counterr<4>_MC.D2_PT_3/IN2 \ ~wire 0 2454 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U11_U3_counterr<4>_MC.D2_PT_3/IN3 \ ~wire 0 2455 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U11_U3_counterr<4>_MC.D2_PT_3/IN4 \ ~wire 0 2456 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U11_U3_counterr<4>_MC.D2_PT_3/IN5 \ ~wire 0 2457 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U11_U3_counterr<4>_MC.D2_PT_4/IN1 \ ~wire 0 2458 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U11_U3_counterr<4>_MC.D2_PT_4/IN2 \ ~wire 0 2459 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U11_U3_counterr<4>_MC.D2_PT_4/IN3 \ ~wire 0 2460 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U11_U3_counterr<4>_MC.D2_PT_4/IN4 \ ~wire 0 2461 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U11_U3_counterr<4>_MC.D2_PT_4/IN5 \ ~wire 0 2462 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U11_U3_counterr<4>_MC.D2_PT_4/IN6 \ ~wire 0 2463 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U11_Incdetect_MC.D1/IN0 \ ~wire 0 2464 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U11_U3_counterr<1>_MC.D/IN0 \ ~wire 0 2465 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U11_U3_counterr<1>_MC.D2_PT_0/IN1 \ ~wire 0 2466 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U11_U3_counterr<1>_MC.D2_PT_1/IN0 \ ~wire 0 2467 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U11_U3_counterr<1>_MC.D2_PT_2/IN0 \ ~wire 0 2468 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U11_U3_counterr<1>_MC.D2_PT_2/IN1 \ ~wire 0 2469 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U11_U3_counterr<1>_MC.D2_PT_3/IN0 \ ~wire 0 2470 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U11_U3_counterr<1>_MC.D2_PT_3/IN1 \ ~wire 0 2471 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
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		(_signal (_internal \NlwInverterSignal_U11_U3_counterr<1>_MC.D2_PT_4/IN2 \ ~wire 0 2475 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
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		(_signal (_internal \NlwInverterSignal_U11_U3_counterr<2>_MC.D2_PT_1/IN0 \ ~wire 0 2478 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
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		(_signal (_internal \NlwInverterSignal_U11_U3_counterr<2>_MC.D2_PT_2/IN0 \ ~wire 0 2480 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U11_U3_counterr<2>_MC.D2_PT_2/IN1 \ ~wire 0 2481 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
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		(_signal (_internal \NlwInverterSignal_U11_U3_counterr<2>_MC.D2_PT_3/IN1 \ ~wire 0 2483 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
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		(_signal (_internal \NlwInverterSignal_U11_U3_counterr<2>_MC.D2_PT_4/IN0 \ ~wire 0 2487 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
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		(_signal (_internal \NlwInverterSignal_NET2528_MC.D2_PT_2/IN0 \ ~wire 0 2499 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_NET2528_MC.D2_PT_2/IN1 \ ~wire 0 2500 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_NET2528_MC.D2_PT_3/IN0 \ ~wire 0 2501 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_NET2528_MC.D2_PT_3/IN2 \ ~wire 0 2502 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_N_PZ_978_MC.D2_PT_1/IN0 \ ~wire 0 2503 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
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		(_signal (_internal \NlwInverterSignal_U1/U3/holdingreg<5>_MC.D2_PT_1/IN0 \ ~wire 0 2506 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
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		(_signal (_internal \NlwInverterSignal_N_PZ_966_MC.D2_PT_0/IN4 \ ~wire 0 2511 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_N_PZ_966_MC.D2_PT_1/IN0 \ ~wire 0 2512 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_N_PZ_966_MC.D2_PT_1/IN1 \ ~wire 0 2513 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_N_PZ_966_MC.D2_PT_1/IN4 \ ~wire 0 2514 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U2_Enable_AD_MC.D1/IN1 \ ~wire 0 2515 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U1/Channel0<5>_MC.D2_PT_0/IN1 \ ~wire 0 2516 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U1/Channel0<5>_MC.D2_PT_1/IN4 \ ~wire 0 2517 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U1/Channel0<5>_MC.D2_PT_2/IN1 \ ~wire 0 2518 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U1/Channel0<5>_MC.D2_PT_2/IN3 \ ~wire 0 2519 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U1/Channel0<5>_MC.D2_PT_2/IN5 \ ~wire 0 2520 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U1/Channel0<5>_MC.D2_PT_2/IN6 \ ~wire 0 2521 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U1/Channel0<5>_MC.D2_PT_2/IN7 \ ~wire 0 2522 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_N_PZ_949_MC.D1/IN0 \ ~wire 0 2523 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_N_PZ_949_MC.D1/IN1 \ ~wire 0 2524 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U1/Zero0_MC.D2_PT_1/IN0 \ ~wire 0 2525 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U1/Zero0_MC.D2_PT_1/IN1 \ ~wire 0 2526 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U1/Zero0_MC.D2_PT_1/IN4 \ ~wire 0 2527 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U1/Zero0_MC.D2_PT_2/IN0 \ ~wire 0 2528 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U1/Zero0_MC.D2_PT_2/IN1 \ ~wire 0 2529 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U1/Zero0_MC.D2_PT_2/IN2 \ ~wire 0 2530 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U1/Zero0_MC.D2_PT_2/IN3 \ ~wire 0 2531 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_NET2482_MC.D2_PT_0/IN0 \ ~wire 0 2532 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_NET2482_MC.D2_PT_0/IN1 \ ~wire 0 2533 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_NET2482_MC.D2_PT_0/IN4 \ ~wire 0 2534 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_NET2482_MC.D2_PT_1/IN0 \ ~wire 0 2535 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_NET2482_MC.D2_PT_1/IN1 \ ~wire 0 2536 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_NET2482_MC.D2_PT_1/IN2 \ ~wire 0 2537 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_NET2482_MC.D2_PT_1/IN3 \ ~wire 0 2538 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_NET2482_MC.D2_PT_2/IN0 \ ~wire 0 2539 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_NET2482_MC.D2_PT_2/IN3 \ ~wire 0 2540 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_NET2482_MC.D2_PT_2/IN5 \ ~wire 0 2541 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_NET2482_MC.D2_PT_2/IN6 \ ~wire 0 2542 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_NET2482_MC.D2_PT_2/IN7 \ ~wire 0 2543 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_NET2482_MC.D2_PT_2/IN9 \ ~wire 0 2544 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_NET2482_MC.D2_PT_3/IN0 \ ~wire 0 2545 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_NET2482_MC.D2_PT_3/IN3 \ ~wire 0 2546 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_NET2482_MC.D2_PT_3/IN5 \ ~wire 0 2547 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_NET2482_MC.D2_PT_3/IN6 \ ~wire 0 2548 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_NET2482_MC.D2_PT_3/IN7 \ ~wire 0 2549 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_NET2482_MC.D2_PT_3/IN8 \ ~wire 0 2550 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U1/U4/RF0r_MC.D2_PT_1/IN0 \ ~wire 0 2551 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U1/U4/RF0r_MC.D2_PT_1/IN5 \ ~wire 0 2552 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U1/U4/RF0r_MC.D2_PT_1/IN6 \ ~wire 0 2553 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U1/U4/RF0r_MC.D2_PT_1/IN7 \ ~wire 0 2554 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U1/U4/RF0r_MC.D2_PT_2/IN0 \ ~wire 0 2555 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U1/U4/RF0r_MC.D2_PT_2/IN5 \ ~wire 0 2556 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U1/U4/RF0r_MC.D2_PT_2/IN6 \ ~wire 0 2557 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U1/U4/RF0r_MC.D2_PT_2/IN7 \ ~wire 0 2558 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U1/U4/RF0r_MC.D2_PT_2/IN9 \ ~wire 0 2559 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U1/U4/E0r_MC.D2_PT_1/IN0 \ ~wire 0 2560 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U1/U4/E0r_MC.D2_PT_1/IN5 \ ~wire 0 2561 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U1/U4/E0r_MC.D2_PT_1/IN6 \ ~wire 0 2562 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U1/U4/E0r_MC.D2_PT_1/IN7 \ ~wire 0 2563 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U1/U4/E0r_MC.D2_PT_2/IN0 \ ~wire 0 2564 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U1/U4/E0r_MC.D2_PT_2/IN5 \ ~wire 0 2565 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U1/U4/E0r_MC.D2_PT_2/IN6 \ ~wire 0 2566 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U1/U4/E0r_MC.D2_PT_2/IN8 \ ~wire 0 2567 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U1/U4/E0r_MC.D2_PT_2/IN9 \ ~wire 0 2568 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U1/Channel0<0>_MC.D2_PT_0/IN2 \ ~wire 0 2569 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U1/Channel0<0>_MC.D2_PT_1/IN1 \ ~wire 0 2570 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_N_PZ_1018_MC.D2_PT_0/IN1 \ ~wire 0 2571 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_N_PZ_1018_MC.D2_PT_0/IN3 \ ~wire 0 2572 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_N_PZ_1018_MC.D2_PT_1/IN1 \ ~wire 0 2573 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_N_PZ_1018_MC.D2_PT_1/IN2 \ ~wire 0 2574 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U1/U1/CurrState_Sreg0_FFD3_MC.D2_PT_0/IN0 \ ~wire 0 2575 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U1/U1/CurrState_Sreg0_FFD3_MC.D2_PT_0/IN3 \ ~wire 0 2576 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U1/U1/CurrState_Sreg0_FFD3_MC.D2_PT_0/IN4 \ ~wire 0 2577 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U1/U1/CurrState_Sreg0_FFD3_MC.D2_PT_1/IN0 \ ~wire 0 2578 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U1/U1/CurrState_Sreg0_FFD3_MC.D2_PT_1/IN2 \ ~wire 0 2579 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U1/U1/CurrState_Sreg0_FFD3_MC.D2_PT_1/IN3 \ ~wire 0 2580 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U1/U1/CurrState_Sreg0_FFD3_MC.D2_PT_1/IN4 \ ~wire 0 2581 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U1/U1/CurrState_Sreg0_FFD3_MC.D2_PT_2/IN0 \ ~wire 0 2582 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U1/U1/CurrState_Sreg0_FFD3_MC.D2_PT_2/IN2 \ ~wire 0 2583 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U1/U1/CurrState_Sreg0_FFD2_MC.D2_PT_0/IN0 \ ~wire 0 2584 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U1/U1/CurrState_Sreg0_FFD2_MC.D2_PT_0/IN3 \ ~wire 0 2585 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U1/U1/CurrState_Sreg0_FFD2_MC.D2_PT_0/IN4 \ ~wire 0 2586 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U1/U1/CurrState_Sreg0_FFD2_MC.D2_PT_1/IN0 \ ~wire 0 2587 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U1/U1/CurrState_Sreg0_FFD2_MC.D2_PT_1/IN1 \ ~wire 0 2588 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U1/U1/CurrState_Sreg0_FFD2_MC.D2_PT_1/IN3 \ ~wire 0 2589 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U1/U1/CurrState_Sreg0_FFD2_MC.D2_PT_2/IN0 \ ~wire 0 2590 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U1/U1/CurrState_Sreg0_FFD2_MC.D2_PT_2/IN1 \ ~wire 0 2591 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U1/U1/CurrState_Sreg0_FFD2_MC.D2_PT_2/IN2 \ ~wire 0 2592 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U1/U1/CurrState_Sreg0_FFD2_MC.D2_PT_2/IN4 \ ~wire 0 2593 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U1/U1/CurrState_Sreg0_FFD2_MC.D2_PT_3/IN0 \ ~wire 0 2594 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U1/U1/CurrState_Sreg0_FFD2_MC.D2_PT_3/IN1 \ ~wire 0 2595 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U1/U1/CurrState_Sreg0_FFD2_MC.D2_PT_3/IN3 \ ~wire 0 2596 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U1/U1/CurrState_Sreg0_FFD4_MC.D1/IN0 \ ~wire 0 2597 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U1/U1/CurrState_Sreg0_FFD4_MC.D1/IN2 \ ~wire 0 2598 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U1/U1/CurrState_Sreg0_FFD4_MC.D1/IN3 \ ~wire 0 2599 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U1/U1/CurrState_Sreg0_FFD4_MC.D1/IN4 \ ~wire 0 2600 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U1/U1/CurrState_Sreg0_FFD4_MC.D1/IN5 \ ~wire 0 2601 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U1/U1/CurrState_Sreg0_FFD4_MC.D1/IN6 \ ~wire 0 2602 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U1/U1/CurrState_Sreg0_FFD1_MC.D2_PT_0/IN0 \ ~wire 0 2603 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U1/U1/CurrState_Sreg0_FFD1_MC.D2_PT_0/IN2 \ ~wire 0 2604 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U1/U1/CurrState_Sreg0_FFD1_MC.D2_PT_1/IN0 \ ~wire 0 2605 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
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		(_signal (_internal \NlwInverterSignal_U1/Channel1<5>_MC.D2_PT_2/IN4 \ ~wire 0 2647 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U1/Channel1<5>_MC.D2_PT_2/IN5 \ ~wire 0 2648 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U1/Channel1<5>_MC.D2_PT_2/IN6 \ ~wire 0 2649 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
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		(_signal (_internal \NlwInverterSignal_N_PZ_948_MC.D1/IN1 \ ~wire 0 2652 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
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		(_signal (_internal \NlwInverterSignal_U1/Zero1_MC.D2_PT_1/IN1 \ ~wire 0 2654 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U1/Zero1_MC.D2_PT_1/IN5 \ ~wire 0 2655 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U1/Zero1_MC.D2_PT_2/IN0 \ ~wire 0 2656 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U1/Zero1_MC.D2_PT_2/IN1 \ ~wire 0 2657 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U1/Zero1_MC.D2_PT_2/IN2 \ ~wire 0 2658 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
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		(_signal (_internal \NlwInverterSignal_U1/U6/CurrState_Sreg0_FFD1_MC.D2_PT_0/IN2 \ ~wire 0 2732 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U1/U6/CurrState_Sreg0_FFD1_MC.D2_PT_1/IN0 \ ~wire 0 2733 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U1/U6/CurrState_Sreg0_FFD1_MC.D2_PT_1/IN1 \ ~wire 0 2734 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U1/U6/CurrState_Sreg0_FFD1_MC.D2_PT_1/IN2 \ ~wire 0 2735 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U1/U6/CurrState_Sreg0_FFD1_MC.D2_PT_2/IN0 \ ~wire 0 2736 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U1/U6/CurrState_Sreg0_FFD1_MC.D2_PT_2/IN1 \ ~wire 0 2737 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U1/U6/CurrState_Sreg0_FFD1_MC.D2_PT_2/IN2 \ ~wire 0 2738 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
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		(_signal (_internal \NlwInverterSignal_U1/U6/CurrState_Sreg0_FFD1_MC.D2_PT_2/IN4 \ ~wire 0 2740 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_N_PZ_1184_MC.D2_PT_0/IN1 \ ~wire 0 2741 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_N_PZ_1184_MC.D2_PT_1/IN0 \ ~wire 0 2742 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U1/Channel1<1>_MC.D2_PT_0/IN0 \ ~wire 0 2743 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U1/Channel1<1>_MC.D2_PT_1/IN3 \ ~wire 0 2744 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U1/Channel1<1>_MC.D2_PT_2/IN2 \ ~wire 0 2745 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_N_PZ_993_MC.D2_PT_1/IN0 \ ~wire 0 2746 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_N_PZ_993_MC.D2_PT_1/IN1 \ ~wire 0 2747 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U1/NET3720_MC.D2_PT_1/IN0 \ ~wire 0 2748 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U1/NET3720_MC.D2_PT_1/IN5 \ ~wire 0 2749 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U1/NET3720_MC.D2_PT_1/IN6 \ ~wire 0 2750 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U1/NET3720_MC.D2_PT_1/IN7 \ ~wire 0 2751 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U1/NET3720_MC.D2_PT_2/IN0 \ ~wire 0 2752 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U1/NET3720_MC.D2_PT_2/IN5 \ ~wire 0 2753 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U1/NET3720_MC.D2_PT_2/IN6 \ ~wire 0 2754 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U1/NET3720_MC.D2_PT_2/IN7 \ ~wire 0 2755 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U1/NET3720_MC.D2_PT_2/IN9 \ ~wire 0 2756 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U1/Channel1<2>_MC.D2_PT_0/IN0 \ ~wire 0 2757 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U1/Channel1<2>_MC.D2_PT_1/IN3 \ ~wire 0 2758 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U1/Channel1<2>_MC.D2_PT_1/IN4 \ ~wire 0 2759 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U1/Channel1<2>_MC.D2_PT_2/IN2 \ ~wire 0 2760 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U1/Channel1<3>_MC.D2_PT_0/IN0 \ ~wire 0 2761 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U1/Channel1<3>_MC.D2_PT_1/IN3 \ ~wire 0 2762 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U1/Channel1<3>_MC.D2_PT_1/IN4 \ ~wire 0 2763 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U1/Channel1<3>_MC.D2_PT_1/IN5 \ ~wire 0 2764 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U1/Channel1<3>_MC.D2_PT_2/IN2 \ ~wire 0 2765 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U1/Channel1<4>_MC.D2_PT_0/IN0 \ ~wire 0 2766 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U1/Channel1<4>_MC.D2_PT_1/IN1 \ ~wire 0 2767 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U1/Channel1<4>_MC.D2_PT_2/IN3 \ ~wire 0 2768 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U1/Channel1<4>_MC.D2_PT_2/IN4 \ ~wire 0 2769 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U1/Channel1<4>_MC.D2_PT_2/IN5 \ ~wire 0 2770 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U1/Channel1<4>_MC.D2_PT_2/IN6 \ ~wire 0 2771 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U1/Channel1<4>_MC.D2_PT_3/IN2 \ ~wire 0 2772 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U1/Channel1<4>_MC.D2_PT_3/IN3 \ ~wire 0 2773 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U1/Channel1<4>_MC.D2_PT_3/IN8 \ ~wire 0 2774 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_N_PZ_986_MC.D2_PT_0/IN0 \ ~wire 0 2775 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_N_PZ_986_MC.D2_PT_0/IN1 \ ~wire 0 2776 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_N_PZ_986_MC.D2_PT_0/IN2 \ ~wire 0 2777 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_N_PZ_986_MC.D2_PT_1/IN0 \ ~wire 0 2778 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_N_PZ_986_MC.D2_PT_1/IN2 \ ~wire 0 2779 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_N_PZ_1002_MC.D2_PT_0/IN0 \ ~wire 0 2780 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_N_PZ_1002_MC.D2_PT_0/IN1 \ ~wire 0 2781 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_N_PZ_1002_MC.D2_PT_1/IN1 \ ~wire 0 2782 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_N_PZ_1002_MC.D2_PT_2/IN1 \ ~wire 0 2783 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
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		(_signal (_internal \NlwInverterSignal_N_PZ_1061_MC.D2_PT_1/IN0 \ ~wire 0 2786 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_N_PZ_1061_MC.D2_PT_1/IN1 \ ~wire 0 2787 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
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		(_signal (_internal \NlwInverterSignal_N_PZ_964_MC.D2_PT_1/IN0 \ ~wire 0 2790 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_N_PZ_964_MC.D2_PT_1/IN2 \ ~wire 0 2791 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U1/U3/holdingreg<21>_MC.D2_PT_1/IN0 \ ~wire 0 2792 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U1/U3/holdingreg<21>_MC.D2_PT_2/IN1 \ ~wire 0 2793 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
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		(_signal (_internal \NlwInverterSignal_U1/Channel0<21>_MC.D2_PT_1/IN8 \ ~wire 0 2802 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
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		(_signal (_internal \NlwInverterSignal_U1/Channel0<13>_MC.D2_PT_2/IN2 \ ~wire 0 2809 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
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		(_signal (_internal \NlwInverterSignal_U1/U2/location_Maddsub__n0000__n0115<0>_MC.D2_PT_0/IN3 \ ~wire 0 2811 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U1/U2/location_Maddsub__n0000__n0115<0>_MC.D2_PT_1/IN0 \ ~wire 0 2812 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
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		(_signal (_internal \NlwInverterSignal_U1/U2/location_Maddsub__n0000__n0115<0>_MC.D2_PT_1/IN2 \ ~wire 0 2814 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U1/U2/location_Maddsub__n0000__n0115<0>_MC.D2_PT_1/IN4 \ ~wire 0 2815 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
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		(_signal (_internal \NlwInverterSignal_U1/U2/location_Maddsub__n0000__n0115<0>_MC.D2_PT_1/IN6 \ ~wire 0 2817 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U1/U2/location_Maddsub__n0000__n0115<0>_MC.D2_PT_1/IN7 \ ~wire 0 2818 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_N_PZ_967_MC.D2_PT_1/IN2 \ ~wire 0 2819 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_N_PZ_967_MC.D2_PT_2/IN0 \ ~wire 0 2820 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_N_PZ_967_MC.D2_PT_2/IN1 \ ~wire 0 2821 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_N_PZ_967_MC.D2_PT_3/IN1 \ ~wire 0 2822 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_N_PZ_967_MC.D2_PT_3/IN2 \ ~wire 0 2823 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_N_PZ_967_MC.D2_PT_3/IN3 \ ~wire 0 2824 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U1/Channel0<10>_MC.D/IN0 \ ~wire 0 2825 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U1/Channel0<10>_MC.D2_PT_0/IN0 \ ~wire 0 2826 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U1/Channel0<10>_MC.D2_PT_0/IN1 \ ~wire 0 2827 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U1/Channel0<10>_MC.D2_PT_1/IN0 \ ~wire 0 2828 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U1/Channel0<10>_MC.D2_PT_1/IN1 \ ~wire 0 2829 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U1/Channel0<10>_MC.D2_PT_2/IN0 \ ~wire 0 2830 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U1/Channel0<10>_MC.D2_PT_2/IN1 \ ~wire 0 2831 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U1/Channel0<10>_MC.D2_PT_2/IN2 \ ~wire 0 2832 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U1/Channel0<10>_MC.D2_PT_3/IN1 \ ~wire 0 2833 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U1/Channel0<10>_MC.D2_PT_3/IN4 \ ~wire 0 2834 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U1/Channel0<10>_MC.D2_PT_4/IN4 \ ~wire 0 2835 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U1/Channel0<10>_MC.D2_PT_4/IN6 \ ~wire 0 2836 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U1/Channel0<10>_MC.D2_PT_4/IN7 \ ~wire 0 2837 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U1/Channel0<7>_MC.D2_PT_0/IN0 \ ~wire 0 2838 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U1/Channel0<7>_MC.D2_PT_2/IN2 \ ~wire 0 2839 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U1/Channel0<7>_MC.D2_PT_2/IN3 \ ~wire 0 2840 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U1/U2/location_Maddsub__n0000__n0103<0>_MC.D2_PT_1/IN0 \ ~wire 0 2841 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U1/U2/location_Maddsub__n0000__n0103<0>_MC.D2_PT_1/IN1 \ ~wire 0 2842 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U1/U2/location_Maddsub__n0000__n0103<0>_MC.D2_PT_1/IN2 \ ~wire 0 2843 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U1/U2/location_Maddsub__n0000__n0103<0>_MC.D2_PT_1/IN3 \ ~wire 0 2844 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U1/U2/location_Maddsub__n0000__n0103<0>_MC.D2_PT_1/IN4 \ ~wire 0 2845 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U1/U2/location_Maddsub__n0000__n0103<0>_MC.D2_PT_1/IN5 \ ~wire 0 2846 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U1/U2/location_Maddsub__n0000__n0103<0>_MC.D2_PT_1/IN6 \ ~wire 0 2847 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U1/U2/location_Maddsub__n0000__n0103<0>_MC.D2_PT_1/IN7 \ ~wire 0 2848 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U1/Channel0<6>_MC.D2_PT_0/IN0 \ ~wire 0 2849 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U1/Channel0<6>_MC.D2_PT_1/IN0 \ ~wire 0 2850 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U1/Channel0<6>_MC.D2_PT_1/IN2 \ ~wire 0 2851 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U1/Channel0<6>_MC.D2_PT_1/IN3 \ ~wire 0 2852 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U1/Channel0<6>_MC.D2_PT_2/IN4 \ ~wire 0 2853 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U1/Channel0<6>_MC.D2_PT_3/IN0 \ ~wire 0 2854 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U1/Channel0<6>_MC.D2_PT_3/IN1 \ ~wire 0 2855 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U1/Channel0<6>_MC.D2_PT_3/IN3 \ ~wire 0 2856 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U1/Channel0<6>_MC.D2_PT_3/IN4 \ ~wire 0 2857 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U1/Channel0<6>_MC.D2_PT_3/IN5 \ ~wire 0 2858 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U1/Channel0<6>_MC.D2_PT_3/IN6 \ ~wire 0 2859 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U1/Channel0<6>_MC.D2_PT_3/IN7 \ ~wire 0 2860 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U1/Channel0<6>_MC.D2_PT_4/IN3 \ ~wire 0 2861 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U1/Channel0<6>_MC.D2_PT_4/IN7 \ ~wire 0 2862 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U1/Channel0<6>_MC.D2_PT_5/IN9 \ ~wire 0 2863 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U1/Channel0<8>_MC.D2_PT_0/IN0 \ ~wire 0 2864 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U1/Channel0<8>_MC.D2_PT_1/IN3 \ ~wire 0 2865 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U1/Channel0<8>_MC.D2_PT_2/IN2 \ ~wire 0 2866 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U1/Channel0<8>_MC.D2_PT_2/IN4 \ ~wire 0 2867 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U1/Channel0<9>_MC.D2_PT_0/IN0 \ ~wire 0 2868 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U1/Channel0<9>_MC.D2_PT_1/IN3 \ ~wire 0 2869 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U1/Channel0<9>_MC.D2_PT_1/IN5 \ ~wire 0 2870 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U1/Channel0<9>_MC.D2_PT_2/IN2 \ ~wire 0 2871 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U1/Channel0<9>_MC.D2_PT_2/IN4 \ ~wire 0 2872 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_N_PZ_1317_MC.D2_PT_0/IN2 \ ~wire 0 2873 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_N_PZ_1317_MC.D2_PT_0/IN3 \ ~wire 0 2874 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_N_PZ_1317_MC.D2_PT_0/IN4 \ ~wire 0 2875 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_N_PZ_1317_MC.D2_PT_1/IN1 \ ~wire 0 2876 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_N_PZ_1317_MC.D2_PT_1/IN2 \ ~wire 0 2877 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_N_PZ_1317_MC.D2_PT_2/IN1 \ ~wire 0 2878 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_N_PZ_1317_MC.D2_PT_2/IN2 \ ~wire 0 2879 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_N_PZ_1317_MC.D2_PT_2/IN3 \ ~wire 0 2880 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U1/Channel0<11>_MC.D/IN0 \ ~wire 0 2881 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U1/Channel0<11>_MC.D2_PT_0/IN0 \ ~wire 0 2882 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U1/Channel0<11>_MC.D2_PT_0/IN1 \ ~wire 0 2883 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U1/Channel0<11>_MC.D2_PT_1/IN0 \ ~wire 0 2884 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U1/Channel0<11>_MC.D2_PT_1/IN1 \ ~wire 0 2885 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U1/Channel0<11>_MC.D2_PT_2/IN1 \ ~wire 0 2886 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U1/Channel0<11>_MC.D2_PT_2/IN2 \ ~wire 0 2887 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
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		(_signal (_internal \NlwInverterSignal_N_PZ_968_MC.D2_PT_1/IN2 \ ~wire 0 3010 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
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		(_signal (_internal \NlwInverterSignal_U1/Channel1<10>_MC.D2_PT_1/IN6 \ ~wire 0 3019 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U1/Channel1<10>_MC.D2_PT_2/IN2 \ ~wire 0 3020 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U1/Channel1<10>_MC.D2_PT_2/IN4 \ ~wire 0 3021 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U1/Channel1<7>_MC.D2_PT_0/IN0 \ ~wire 0 3022 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U1/Channel1<7>_MC.D2_PT_2/IN2 \ ~wire 0 3023 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U1/Channel1<7>_MC.D2_PT_2/IN3 \ ~wire 0 3024 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U1/U5/location_Maddsub__n0000__n0103<0>_MC.D2_PT_1/IN0 \ ~wire 0 3025 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U1/U5/location_Maddsub__n0000__n0103<0>_MC.D2_PT_1/IN1 \ ~wire 0 3026 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U1/U5/location_Maddsub__n0000__n0103<0>_MC.D2_PT_1/IN2 \ ~wire 0 3027 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U1/U5/location_Maddsub__n0000__n0103<0>_MC.D2_PT_1/IN3 \ ~wire 0 3028 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U1/U5/location_Maddsub__n0000__n0103<0>_MC.D2_PT_1/IN4 \ ~wire 0 3029 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U1/U5/location_Maddsub__n0000__n0103<0>_MC.D2_PT_1/IN5 \ ~wire 0 3030 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U1/U5/location_Maddsub__n0000__n0103<0>_MC.D2_PT_1/IN6 \ ~wire 0 3031 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U1/U5/location_Maddsub__n0000__n0103<0>_MC.D2_PT_1/IN7 \ ~wire 0 3032 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U1/Channel1<6>_MC.D2_PT_0/IN0 \ ~wire 0 3033 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U1/Channel1<6>_MC.D2_PT_1/IN2 \ ~wire 0 3034 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U1/Channel1<6>_MC.D2_PT_1/IN3 \ ~wire 0 3035 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U1/Channel1<6>_MC.D2_PT_2/IN4 \ ~wire 0 3036 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U1/Channel1<6>_MC.D2_PT_3/IN1 \ ~wire 0 3037 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U1/Channel1<6>_MC.D2_PT_3/IN2 \ ~wire 0 3038 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U1/Channel1<6>_MC.D2_PT_3/IN3 \ ~wire 0 3039 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U1/Channel1<6>_MC.D2_PT_4/IN5 \ ~wire 0 3040 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U1/Channel1<6>_MC.D2_PT_5/IN0 \ ~wire 0 3041 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U1/Channel1<6>_MC.D2_PT_5/IN2 \ ~wire 0 3042 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U1/Channel1<6>_MC.D2_PT_5/IN3 \ ~wire 0 3043 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U1/Channel1<6>_MC.D2_PT_5/IN4 \ ~wire 0 3044 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U1/Channel1<6>_MC.D2_PT_5/IN5 \ ~wire 0 3045 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U1/Channel1<6>_MC.D2_PT_5/IN6 \ ~wire 0 3046 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U1/Channel1<6>_MC.D2_PT_5/IN7 \ ~wire 0 3047 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U1/Channel1<8>_MC.D2_PT_0/IN0 \ ~wire 0 3048 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U1/Channel1<8>_MC.D2_PT_1/IN3 \ ~wire 0 3049 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U1/Channel1<8>_MC.D2_PT_2/IN2 \ ~wire 0 3050 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U1/Channel1<8>_MC.D2_PT_2/IN4 \ ~wire 0 3051 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U1/Channel1<9>_MC.D2_PT_0/IN0 \ ~wire 0 3052 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U1/Channel1<9>_MC.D2_PT_1/IN3 \ ~wire 0 3053 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U1/Channel1<9>_MC.D2_PT_1/IN5 \ ~wire 0 3054 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U1/Channel1<9>_MC.D2_PT_2/IN2 \ ~wire 0 3055 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U1/Channel1<9>_MC.D2_PT_2/IN4 \ ~wire 0 3056 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U1/Channel1<11>_MC.D2_PT_0/IN0 \ ~wire 0 3057 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U1/Channel1<11>_MC.D2_PT_1/IN2 \ ~wire 0 3058 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U1/Channel1<11>_MC.D2_PT_2/IN2 \ ~wire 0 3059 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U1/Channel1<11>_MC.D2_PT_2/IN4 \ ~wire 0 3060 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U1/Channel1<11>_MC.D2_PT_3/IN3 \ ~wire 0 3061 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U1/Channel1<11>_MC.D2_PT_3/IN4 \ ~wire 0 3062 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U1/Channel1<11>_MC.D2_PT_3/IN6 \ ~wire 0 3063 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U1/Channel1<11>_MC.D2_PT_3/IN7 \ ~wire 0 3064 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_N_PZ_1055_MC.D1/IN2 \ ~wire 0 3065 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U1/Channel1<12>_MC.D2_PT_0/IN0 \ ~wire 0 3066 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U1/Channel1<12>_MC.D2_PT_1/IN4 \ ~wire 0 3067 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U1/Channel1<12>_MC.D2_PT_2/IN1 \ ~wire 0 3068 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U1/Channel1<12>_MC.D2_PT_2/IN2 \ ~wire 0 3069 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U1/Channel1<12>_MC.D2_PT_3/IN1 \ ~wire 0 3070 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U1/Channel1<12>_MC.D2_PT_3/IN2 \ ~wire 0 3071 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U1/Channel1<12>_MC.D2_PT_3/IN3 \ ~wire 0 3072 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U1/Channel1<12>_MC.D2_PT_4/IN5 \ ~wire 0 3073 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U1/Channel1<12>_MC.D2_PT_5/IN1 \ ~wire 0 3074 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U1/Channel1<12>_MC.D2_PT_5/IN2 \ ~wire 0 3075 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U1/Channel1<12>_MC.D2_PT_5/IN4 \ ~wire 0 3076 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U1/Channel1<12>_MC.D2_PT_5/IN5 \ ~wire 0 3077 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
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		(_signal (_internal \NlwInverterSignal_U1/U4/LatchEdge0r_MC.D2_PT_2/IN5 \ ~wire 0 3174 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U1/U4/LatchEdge0r_MC.D2_PT_2/IN6 \ ~wire 0 3175 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U1/U4/LatchEdge0r_MC.D2_PT_2/IN7 \ ~wire 0 3176 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U1/U4/LatchEdge0r_MC.D2_PT_2/IN9 \ ~wire 0 3177 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U1/U4/Latch0r<5>_MC.D2_PT_1/IN0 \ ~wire 0 3178 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U1/U4/Latch0r<5>_MC.D2_PT_1/IN2 \ ~wire 0 3179 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U1/U4/Latch1r<5>_MC.D2_PT_0/IN0 \ ~wire 0 3180 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U1/U4/Latch1r<5>_MC.D2_PT_1/IN0 \ ~wire 0 3181 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U1/U4/Latch1r<5>_MC.D2_PT_1/IN4 \ ~wire 0 3182 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U1/U4/Latch1r<5>_MC.D2_PT_1/IN5 \ ~wire 0 3183 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U1/U4/Latch1r<5>_MC.D2_PT_1/IN6 \ ~wire 0 3184 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U1/U4/Latch1r<13>_MC.D2_PT_0/IN0 \ ~wire 0 3185 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U1/U4/Latch1r<13>_MC.D2_PT_1/IN0 \ ~wire 0 3186 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U1/U4/Latch1r<13>_MC.D2_PT_1/IN4 \ ~wire 0 3187 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U1/U4/Latch1r<13>_MC.D2_PT_1/IN5 \ ~wire 0 3188 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U1/U4/Latch1r<13>_MC.D2_PT_1/IN6 \ ~wire 0 3189 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_N_PZ_1003_MC.D2_PT_0/IN0 \ ~wire 0 3190 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_N_PZ_1003_MC.D2_PT_0/IN1 \ ~wire 0 3191 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_N_PZ_1060_MC.D2_PT_0/IN2 \ ~wire 0 3192 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_N_PZ_1060_MC.D2_PT_1/IN0 \ ~wire 0 3193 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_AD<6>_MC.D/IN0 \ ~wire 0 3194 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_AD<6>_MC.D2_PT_0/IN1 \ ~wire 0 3195 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_AD<6>_MC.D2_PT_1/IN1 \ ~wire 0 3196 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_AD<6>_MC.D2_PT_2/IN1 \ ~wire 0 3197 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_AD<6>_MC.D2_PT_2/IN7 \ ~wire 0 3198 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_AD<6>_MC.D2_PT_3/IN1 \ ~wire 0 3199 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_AD<6>_MC.D2_PT_3/IN5 \ ~wire 0 3200 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_AD<6>_MC.D2_PT_3/IN6 \ ~wire 0 3201 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_AD<6>_MC.D2_PT_3/IN7 \ ~wire 0 3202 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_AD<6>_MC.D2_PT_4/IN1 \ ~wire 0 3203 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_AD<6>_MC.D2_PT_4/IN3 \ ~wire 0 3204 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_AD<6>_MC.D2_PT_4/IN7 \ ~wire 0 3205 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_AD<6>_MC.D2_PT_5/IN1 \ ~wire 0 3206 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_AD<6>_MC.D2_PT_5/IN2 \ ~wire 0 3207 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_AD<6>_MC.D2_PT_5/IN3 \ ~wire 0 3208 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_AD<6>_MC.D2_PT_5/IN5 \ ~wire 0 3209 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_AD<6>_MC.D2_PT_5/IN6 \ ~wire 0 3210 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_AD<6>_MC.D2_PT_5/IN7 \ ~wire 0 3211 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_outDATA<6>\\$WA3.UIM_MC.D2_PT_1/IN0 \ ~wire 0 3212 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U1/U3/holdingreg<6>_MC.D2_PT_1/IN0 \ ~wire 0 3213 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U1/U3/holdingreg<6>_MC.D2_PT_2/IN1 \ ~wire 0 3214 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U1/U3/holdingreg<6>_MC.D2_PT_2/IN6 \ ~wire 0 3215 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U1/U3/holdingreg<6>_MC.D2_PT_2/IN7 \ ~wire 0 3216 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U1/U3/holdingreg<6>_MC.D2_PT_2/IN8 \ ~wire 0 3217 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U1/U3/holdingreg<22>_MC.D2_PT_1/IN0 \ ~wire 0 3218 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U1/U3/holdingreg<22>_MC.D2_PT_2/IN1 \ ~wire 0 3219 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U1/U3/holdingreg<22>_MC.D2_PT_2/IN6 \ ~wire 0 3220 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U1/U3/holdingreg<22>_MC.D2_PT_2/IN7 \ ~wire 0 3221 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U1/U3/holdingreg<22>_MC.D2_PT_2/IN8 \ ~wire 0 3222 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U1/Channel0<22>_MC.D2_PT_0/IN0 \ ~wire 0 3223 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U1/Channel0<22>_MC.D2_PT_1/IN3 \ ~wire 0 3224 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U1/Channel0<22>_MC.D2_PT_1/IN4 \ ~wire 0 3225 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U1/Channel0<22>_MC.D2_PT_1/IN6 \ ~wire 0 3226 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U1/Channel0<22>_MC.D2_PT_1/IN7 \ ~wire 0 3227 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U1/Channel0<22>_MC.D2_PT_1/IN8 \ ~wire 0 3228 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U1/Channel0<22>_MC.D2_PT_1/IN9 \ ~wire 0 3229 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U1/Channel0<22>_MC.D2_PT_1/IN10 \ ~wire 0 3230 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U1/Channel0<22>_MC.D2_PT_1/IN11 \ ~wire 0 3231 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U1/Channel0<22>_MC.D2_PT_1/IN12 \ ~wire 0 3232 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U1/Channel0<22>_MC.D2_PT_2/IN2 \ ~wire 0 3233 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U1/Channel0<22>_MC.D2_PT_2/IN5 \ ~wire 0 3234 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U1/Channel1<22>_MC.D2_PT_0/IN0 \ ~wire 0 3235 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U1/Channel1<22>_MC.D2_PT_1/IN3 \ ~wire 0 3236 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U1/Channel1<22>_MC.D2_PT_1/IN4 \ ~wire 0 3237 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U1/Channel1<22>_MC.D2_PT_1/IN6 \ ~wire 0 3238 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U1/Channel1<22>_MC.D2_PT_1/IN7 \ ~wire 0 3239 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U1/Channel1<22>_MC.D2_PT_1/IN8 \ ~wire 0 3240 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U1/Channel1<22>_MC.D2_PT_1/IN9 \ ~wire 0 3241 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U1/Channel1<22>_MC.D2_PT_1/IN10 \ ~wire 0 3242 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U1/Channel1<22>_MC.D2_PT_1/IN11 \ ~wire 0 3243 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U1/Channel1<22>_MC.D2_PT_1/IN12 \ ~wire 0 3244 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U1/Channel1<22>_MC.D2_PT_2/IN2 \ ~wire 0 3245 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U1/Channel1<22>_MC.D2_PT_2/IN5 \ ~wire 0 3246 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U1/U3/holdingreg<14>_MC.D2_PT_1/IN0 \ ~wire 0 3247 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U1/U3/holdingreg<14>_MC.D2_PT_2/IN1 \ ~wire 0 3248 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U1/U3/holdingreg<14>_MC.D2_PT_2/IN6 \ ~wire 0 3249 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U1/U3/holdingreg<14>_MC.D2_PT_2/IN7 \ ~wire 0 3250 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U1/U3/holdingreg<14>_MC.D2_PT_2/IN8 \ ~wire 0 3251 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_outDATA<6>\\$WA4.UIM_MC.D2_PT_1/IN1 \ ~wire 0 3252 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_outDATA<6>\\$WA4.UIM_MC.D2_PT_1/IN5 \ ~wire 0 3253 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_outDATA<6>\\$WA4.UIM_MC.D2_PT_2/IN1 \ ~wire 0 3254 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_outDATA<6>\\$WA4.UIM_MC.D2_PT_2/IN3 \ ~wire 0 3255 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_outDATA<6>\\$WA4.UIM_MC.D2_PT_2/IN5 \ ~wire 0 3256 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_outDATA<6>\\$WA4.UIM_MC.D2_PT_3/IN1 \ ~wire 0 3257 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_outDATA<6>\\$WA4.UIM_MC.D2_PT_3/IN2 \ ~wire 0 3258 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_outDATA<6>\\$WA4.UIM_MC.D2_PT_3/IN3 \ ~wire 0 3259 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U1/U4/Latch0r<14>_MC.D2_PT_1/IN0 \ ~wire 0 3260 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U1/U4/Latch0r<14>_MC.D2_PT_1/IN2 \ ~wire 0 3261 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U1/U4/Latch0r<6>_MC.D2_PT_1/IN0 \ ~wire 0 3262 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U1/U4/Latch0r<6>_MC.D2_PT_1/IN2 \ ~wire 0 3263 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U1/U4/Latch1r<6>_MC.D2_PT_0/IN0 \ ~wire 0 3264 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U1/U4/Latch1r<6>_MC.D2_PT_1/IN0 \ ~wire 0 3265 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U1/U4/Latch1r<6>_MC.D2_PT_1/IN4 \ ~wire 0 3266 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U1/U4/Latch1r<6>_MC.D2_PT_1/IN5 \ ~wire 0 3267 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U1/U4/Latch1r<6>_MC.D2_PT_1/IN6 \ ~wire 0 3268 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U1/U4/Latch1r<14>_MC.D2_PT_0/IN0 \ ~wire 0 3269 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U1/U4/Latch1r<14>_MC.D2_PT_1/IN0 \ ~wire 0 3270 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U1/U4/Latch1r<14>_MC.D2_PT_1/IN4 \ ~wire 0 3271 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U1/U4/Latch1r<14>_MC.D2_PT_1/IN5 \ ~wire 0 3272 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U1/U4/Latch1r<14>_MC.D2_PT_1/IN6 \ ~wire 0 3273 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_AD<7>_MC.D/IN0 \ ~wire 0 3274 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_AD<7>_MC.D2_PT_0/IN1 \ ~wire 0 3275 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_AD<7>_MC.D2_PT_1/IN1 \ ~wire 0 3276 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_AD<7>_MC.D2_PT_2/IN1 \ ~wire 0 3277 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_AD<7>_MC.D2_PT_2/IN7 \ ~wire 0 3278 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_AD<7>_MC.D2_PT_3/IN1 \ ~wire 0 3279 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_AD<7>_MC.D2_PT_3/IN5 \ ~wire 0 3280 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_AD<7>_MC.D2_PT_3/IN6 \ ~wire 0 3281 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_AD<7>_MC.D2_PT_3/IN7 \ ~wire 0 3282 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_AD<7>_MC.D2_PT_4/IN1 \ ~wire 0 3283 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_AD<7>_MC.D2_PT_4/IN3 \ ~wire 0 3284 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_AD<7>_MC.D2_PT_4/IN7 \ ~wire 0 3285 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_AD<7>_MC.D2_PT_5/IN1 \ ~wire 0 3286 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_AD<7>_MC.D2_PT_5/IN2 \ ~wire 0 3287 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_AD<7>_MC.D2_PT_5/IN3 \ ~wire 0 3288 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_AD<7>_MC.D2_PT_5/IN5 \ ~wire 0 3289 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_AD<7>_MC.D2_PT_5/IN6 \ ~wire 0 3290 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_AD<7>_MC.D2_PT_5/IN7 \ ~wire 0 3291 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_NET3253_MC.D2_PT_0/IN0 \ ~wire 0 3292 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_NET3253_MC.D2_PT_1/IN0 \ ~wire 0 3293 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_NET3253_MC.D2_PT_1/IN2 \ ~wire 0 3294 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_NET3253_MC.D2_PT_1/IN3 \ ~wire 0 3295 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_N_PZ_1186_MC.D2_PT_0/IN0 \ ~wire 0 3296 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_N_PZ_1186_MC.D2_PT_1/IN0 \ ~wire 0 3297 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_N_PZ_1186_MC.D2_PT_1/IN1 \ ~wire 0 3298 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_outDATA<7>\\$WA3.UIM_MC.D2_PT_1/IN0 \ ~wire 0 3299 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U1/U3/holdingreg<7>_MC.D2_PT_1/IN0 \ ~wire 0 3300 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U1/U3/holdingreg<7>_MC.D2_PT_2/IN1 \ ~wire 0 3301 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U1/U3/holdingreg<7>_MC.D2_PT_2/IN6 \ ~wire 0 3302 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U1/U3/holdingreg<7>_MC.D2_PT_2/IN7 \ ~wire 0 3303 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U1/U3/holdingreg<7>_MC.D2_PT_2/IN8 \ ~wire 0 3304 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U1/U3/holdingreg<23>_MC.D2_PT_1/IN0 \ ~wire 0 3305 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U1/U3/holdingreg<23>_MC.D2_PT_2/IN1 \ ~wire 0 3306 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U1/U3/holdingreg<23>_MC.D2_PT_2/IN6 \ ~wire 0 3307 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U1/U3/holdingreg<23>_MC.D2_PT_2/IN7 \ ~wire 0 3308 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U1/U3/holdingreg<23>_MC.D2_PT_2/IN8 \ ~wire 0 3309 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U1/Channel0<23>_MC.D2_PT_0/IN0 \ ~wire 0 3310 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U1/Channel0<23>_MC.D2_PT_1/IN3 \ ~wire 0 3311 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U1/Channel0<23>_MC.D2_PT_1/IN4 \ ~wire 0 3312 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U1/Channel0<23>_MC.D2_PT_1/IN6 \ ~wire 0 3313 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U1/Channel0<23>_MC.D2_PT_1/IN7 \ ~wire 0 3314 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U1/Channel0<23>_MC.D2_PT_1/IN8 \ ~wire 0 3315 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U1/Channel0<23>_MC.D2_PT_1/IN9 \ ~wire 0 3316 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U1/Channel0<23>_MC.D2_PT_1/IN10 \ ~wire 0 3317 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U1/Channel0<23>_MC.D2_PT_1/IN11 \ ~wire 0 3318 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U1/Channel0<23>_MC.D2_PT_1/IN12 \ ~wire 0 3319 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U1/Channel0<23>_MC.D2_PT_1/IN13 \ ~wire 0 3320 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U1/Channel0<23>_MC.D2_PT_2/IN2 \ ~wire 0 3321 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U1/Channel0<23>_MC.D2_PT_2/IN5 \ ~wire 0 3322 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U1/Channel1<23>_MC.D2_PT_0/IN0 \ ~wire 0 3323 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U1/Channel1<23>_MC.D2_PT_1/IN3 \ ~wire 0 3324 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U1/Channel1<23>_MC.D2_PT_1/IN4 \ ~wire 0 3325 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U1/Channel1<23>_MC.D2_PT_1/IN6 \ ~wire 0 3326 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U1/Channel1<23>_MC.D2_PT_1/IN7 \ ~wire 0 3327 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U1/Channel1<23>_MC.D2_PT_1/IN8 \ ~wire 0 3328 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U1/Channel1<23>_MC.D2_PT_1/IN9 \ ~wire 0 3329 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U1/Channel1<23>_MC.D2_PT_1/IN10 \ ~wire 0 3330 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U1/Channel1<23>_MC.D2_PT_1/IN11 \ ~wire 0 3331 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U1/Channel1<23>_MC.D2_PT_1/IN12 \ ~wire 0 3332 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U1/Channel1<23>_MC.D2_PT_1/IN13 \ ~wire 0 3333 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U1/Channel1<23>_MC.D2_PT_2/IN2 \ ~wire 0 3334 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U1/Channel1<23>_MC.D2_PT_2/IN5 \ ~wire 0 3335 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U1/U3/holdingreg<15>_MC.D2_PT_1/IN0 \ ~wire 0 3336 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U1/U3/holdingreg<15>_MC.D2_PT_2/IN1 \ ~wire 0 3337 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U1/U3/holdingreg<15>_MC.D2_PT_2/IN6 \ ~wire 0 3338 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U1/U3/holdingreg<15>_MC.D2_PT_2/IN7 \ ~wire 0 3339 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U1/U3/holdingreg<15>_MC.D2_PT_2/IN8 \ ~wire 0 3340 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_outDATA<7>\\$WA4.UIM_MC.D2_PT_1/IN1 \ ~wire 0 3341 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_outDATA<7>\\$WA4.UIM_MC.D2_PT_1/IN5 \ ~wire 0 3342 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_outDATA<7>\\$WA4.UIM_MC.D2_PT_2/IN1 \ ~wire 0 3343 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_outDATA<7>\\$WA4.UIM_MC.D2_PT_2/IN3 \ ~wire 0 3344 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_outDATA<7>\\$WA4.UIM_MC.D2_PT_2/IN5 \ ~wire 0 3345 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_outDATA<7>\\$WA4.UIM_MC.D2_PT_3/IN1 \ ~wire 0 3346 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_outDATA<7>\\$WA4.UIM_MC.D2_PT_3/IN2 \ ~wire 0 3347 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_outDATA<7>\\$WA4.UIM_MC.D2_PT_3/IN3 \ ~wire 0 3348 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U1/U4/Latch0r<15>_MC.D2_PT_1/IN0 \ ~wire 0 3349 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U1/U4/Latch0r<15>_MC.D2_PT_1/IN2 \ ~wire 0 3350 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U1/U4/Latch0r<7>_MC.D2_PT_1/IN0 \ ~wire 0 3351 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U1/U4/Latch0r<7>_MC.D2_PT_1/IN2 \ ~wire 0 3352 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U1/U4/Latch1r<7>_MC.D2_PT_0/IN0 \ ~wire 0 3353 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U1/U4/Latch1r<7>_MC.D2_PT_1/IN0 \ ~wire 0 3354 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U1/U4/Latch1r<7>_MC.D2_PT_1/IN4 \ ~wire 0 3355 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U1/U4/Latch1r<7>_MC.D2_PT_1/IN5 \ ~wire 0 3356 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U1/U4/Latch1r<7>_MC.D2_PT_1/IN6 \ ~wire 0 3357 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U1/U4/Latch1r<15>_MC.D2_PT_0/IN0 \ ~wire 0 3358 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U1/U4/Latch1r<15>_MC.D2_PT_1/IN0 \ ~wire 0 3359 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U1/U4/Latch1r<15>_MC.D2_PT_1/IN4 \ ~wire 0 3360 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U1/U4/Latch1r<15>_MC.D2_PT_1/IN5 \ ~wire 0 3361 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U1/U4/Latch1r<15>_MC.D2_PT_1/IN6 \ ~wire 0 3362 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_Enc05ctrl_MC.CE/IN0 \ ~wire 0 3363 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_Enc05ctrl_MC.CE/IN3 \ ~wire 0 3364 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_Enc133ctrl_MC.CE/IN0 \ ~wire 0 3365 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_Enc133ctrl_MC.CE/IN3 \ ~wire 0 3366 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_Enc15ctrl_MC.CE/IN0 \ ~wire 0 3367 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_Enc15ctrl_MC.CE/IN3 \ ~wire 0 3368 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_Home033ctrl_MC.CE/IN0 \ ~wire 0 3369 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_Home033ctrl_MC.CE/IN3 \ ~wire 0 3370 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_Home15ctrl_MC.CE/IN0 \ ~wire 0 3371 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_Home15ctrl_MC.CE/IN3 \ ~wire 0 3372 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_INT_MC.D2_PT_7/IN0 \ ~wire 0 3373 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_INT_MC.D2_PT_7/IN1 \ ~wire 0 3374 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_INT_MC.D2_PT_7/IN2 \ ~wire 0 3375 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_INT_MC.D2_PT_7/IN3 \ ~wire 0 3376 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_INT_MC.D2_PT_7/IN4 \ ~wire 0 3377 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_INT_MC.D2_PT_7/IN5 \ ~wire 0 3378 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U3/DCORIE<0>_MC.D2_PT_1/IN0 \ ~wire 0 3379 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U3/DCORIE<0>_MC.D2_PT_1/IN2 \ ~wire 0 3380 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U3/DCORIE<0>_MC.D2_PT_1/IN5 \ ~wire 0 3381 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U3/DCORIE<0>_MC.D2_PT_1/IN6 \ ~wire 0 3382 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U3/DCORIE<0>_MC.D2_PT_1/IN7 \ ~wire 0 3383 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U3/DCORIE<0>_MC.D2_PT_2/IN0 \ ~wire 0 3384 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U3/DCORIE<0>_MC.D2_PT_2/IN2 \ ~wire 0 3385 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U3/DCORIE<0>_MC.D2_PT_2/IN5 \ ~wire 0 3386 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U3/DCORIE<0>_MC.D2_PT_2/IN6 \ ~wire 0 3387 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U3/DCORIE<0>_MC.D2_PT_2/IN7 \ ~wire 0 3388 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U3/DCORIE<0>_MC.D2_PT_2/IN9 \ ~wire 0 3389 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U3/DCORIE<1>_MC.D2_PT_1/IN0 \ ~wire 0 3390 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U3/DCORIE<1>_MC.D2_PT_1/IN2 \ ~wire 0 3391 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U3/DCORIE<1>_MC.D2_PT_1/IN5 \ ~wire 0 3392 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U3/DCORIE<1>_MC.D2_PT_1/IN6 \ ~wire 0 3393 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U3/DCORIE<1>_MC.D2_PT_1/IN7 \ ~wire 0 3394 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U3/DCORIE<1>_MC.D2_PT_2/IN0 \ ~wire 0 3395 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U3/DCORIE<1>_MC.D2_PT_2/IN2 \ ~wire 0 3396 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U3/DCORIE<1>_MC.D2_PT_2/IN5 \ ~wire 0 3397 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U3/DCORIE<1>_MC.D2_PT_2/IN6 \ ~wire 0 3398 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U3/DCORIE<1>_MC.D2_PT_2/IN8 \ ~wire 0 3399 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U3/DCORIE<1>_MC.D2_PT_2/IN9 \ ~wire 0 3400 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U3/DCORIE<2>_MC.D2_PT_1/IN0 \ ~wire 0 3401 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U3/DCORIE<2>_MC.D2_PT_1/IN2 \ ~wire 0 3402 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U3/DCORIE<2>_MC.D2_PT_1/IN5 \ ~wire 0 3403 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U3/DCORIE<2>_MC.D2_PT_1/IN6 \ ~wire 0 3404 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U3/DCORIE<2>_MC.D2_PT_1/IN7 \ ~wire 0 3405 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U3/DCORIE<2>_MC.D2_PT_2/IN0 \ ~wire 0 3406 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U3/DCORIE<2>_MC.D2_PT_2/IN2 \ ~wire 0 3407 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U3/DCORIE<2>_MC.D2_PT_2/IN5 \ ~wire 0 3408 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U3/DCORIE<2>_MC.D2_PT_2/IN6 \ ~wire 0 3409 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U3/DCORIE<2>_MC.D2_PT_2/IN7 \ ~wire 0 3410 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U3/DCORIE<2>_MC.D2_PT_2/IN9 \ ~wire 0 3411 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U3/DCORIE<3>_MC.D2_PT_1/IN0 \ ~wire 0 3412 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U3/DCORIE<3>_MC.D2_PT_1/IN2 \ ~wire 0 3413 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U3/DCORIE<3>_MC.D2_PT_1/IN5 \ ~wire 0 3414 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U3/DCORIE<3>_MC.D2_PT_1/IN6 \ ~wire 0 3415 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U3/DCORIE<3>_MC.D2_PT_1/IN7 \ ~wire 0 3416 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U3/DCORIE<3>_MC.D2_PT_2/IN0 \ ~wire 0 3417 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U3/DCORIE<3>_MC.D2_PT_2/IN2 \ ~wire 0 3418 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U3/DCORIE<3>_MC.D2_PT_2/IN5 \ ~wire 0 3419 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U3/DCORIE<3>_MC.D2_PT_2/IN6 \ ~wire 0 3420 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U3/DCORIE<3>_MC.D2_PT_2/IN7 \ ~wire 0 3421 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U3/DCORIE<3>_MC.D2_PT_2/IN9 \ ~wire 0 3422 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_NET2575_MC.D2_PT_1/IN0 \ ~wire 0 3423 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_NET2575_MC.D2_PT_1/IN2 \ ~wire 0 3424 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_NET2575_MC.D2_PT_2/IN0 \ ~wire 0 3425 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_NET2575_MC.D2_PT_2/IN2 \ ~wire 0 3426 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_NET2575_MC.D2_PT_2/IN3 \ ~wire 0 3427 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_NET2575_MC.D2_PT_3/IN0 \ ~wire 0 3428 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_NET2575_MC.D2_PT_3/IN1 \ ~wire 0 3429 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_NET2575_MC.D2_PT_3/IN2 \ ~wire 0 3430 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_NET2575_MC.D2_PT_3/IN3 \ ~wire 0 3431 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_NET2575_MC.D2_PT_4/IN0 \ ~wire 0 3432 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_NET2575_MC.D2_PT_4/IN3 \ ~wire 0 3433 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_NET2575_MC.D2_PT_4/IN5 \ ~wire 0 3434 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_NET2575_MC.D2_PT_4/IN6 \ ~wire 0 3435 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_NET2575_MC.D2_PT_4/IN7 \ ~wire 0 3436 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_NET2575_MC.D2_PT_4/IN9 \ ~wire 0 3437 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_NET2575_MC.D2_PT_5/IN0 \ ~wire 0 3438 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_NET2575_MC.D2_PT_5/IN3 \ ~wire 0 3439 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_NET2575_MC.D2_PT_5/IN5 \ ~wire 0 3440 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_NET2575_MC.D2_PT_5/IN6 \ ~wire 0 3441 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_NET2575_MC.D2_PT_5/IN7 \ ~wire 0 3442 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_NET2575_MC.D2_PT_5/IN8 \ ~wire 0 3443 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_NET2575_MC.D2_PT_6/IN0 \ ~wire 0 3444 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_NET2575_MC.D2_PT_6/IN3 \ ~wire 0 3445 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_NET2575_MC.D2_PT_6/IN5 \ ~wire 0 3446 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_NET2575_MC.D2_PT_6/IN6 \ ~wire 0 3447 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_NET2575_MC.D2_PT_6/IN7 \ ~wire 0 3448 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_NET2575_MC.D2_PT_6/IN8 \ ~wire 0 3449 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_NET2575_MC.D2_PT_6/IN9 \ ~wire 0 3450 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U3/DCORIE<4>_MC.D2_PT_1/IN0 \ ~wire 0 3451 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U3/DCORIE<4>_MC.D2_PT_1/IN2 \ ~wire 0 3452 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U3/DCORIE<4>_MC.D2_PT_1/IN5 \ ~wire 0 3453 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U3/DCORIE<4>_MC.D2_PT_1/IN6 \ ~wire 0 3454 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U3/DCORIE<4>_MC.D2_PT_1/IN7 \ ~wire 0 3455 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U3/DCORIE<4>_MC.D2_PT_2/IN0 \ ~wire 0 3456 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U3/DCORIE<4>_MC.D2_PT_2/IN2 \ ~wire 0 3457 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U3/DCORIE<4>_MC.D2_PT_2/IN5 \ ~wire 0 3458 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U3/DCORIE<4>_MC.D2_PT_2/IN6 \ ~wire 0 3459 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U3/DCORIE<4>_MC.D2_PT_2/IN7 \ ~wire 0 3460 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U3/DCORIE<4>_MC.D2_PT_2/IN9 \ ~wire 0 3461 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U3/DCORIE<5>_MC.D2_PT_1/IN0 \ ~wire 0 3462 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U3/DCORIE<5>_MC.D2_PT_1/IN2 \ ~wire 0 3463 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U3/DCORIE<5>_MC.D2_PT_1/IN5 \ ~wire 0 3464 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U3/DCORIE<5>_MC.D2_PT_1/IN6 \ ~wire 0 3465 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
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		(_signal (_internal \NlwInverterSignal_NET2512_MC.D2_PT_0/IN0 \ ~wire 0 3473 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_NET2512_MC.D2_PT_0/IN2 \ ~wire 0 3474 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_NET2512_MC.D2_PT_0/IN4 \ ~wire 0 3475 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_NET2512_MC.D2_PT_1/IN0 \ ~wire 0 3476 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
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		(_signal (_internal \NlwInverterSignal_NET2512_MC.D2_PT_1/IN2 \ ~wire 0 3478 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_NET2512_MC.D2_PT_1/IN3 \ ~wire 0 3479 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_NET2512_MC.D2_PT_2/IN0 \ ~wire 0 3480 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_NET2512_MC.D2_PT_2/IN3 \ ~wire 0 3481 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_NET2512_MC.D2_PT_2/IN5 \ ~wire 0 3482 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_NET2512_MC.D2_PT_2/IN6 \ ~wire 0 3483 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_NET2512_MC.D2_PT_2/IN7 \ ~wire 0 3484 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_NET2512_MC.D2_PT_2/IN9 \ ~wire 0 3485 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_NET2512_MC.D2_PT_3/IN0 \ ~wire 0 3486 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_NET2512_MC.D2_PT_3/IN3 \ ~wire 0 3487 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_NET2512_MC.D2_PT_3/IN5 \ ~wire 0 3488 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_NET2512_MC.D2_PT_3/IN6 \ ~wire 0 3489 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_NET2512_MC.D2_PT_3/IN7 \ ~wire 0 3490 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_NET2512_MC.D2_PT_3/IN8 \ ~wire 0 3491 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U1/U4/LatchEdge1r_MC.D2_PT_1/IN0 \ ~wire 0 3492 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U1/U4/LatchEdge1r_MC.D2_PT_1/IN5 \ ~wire 0 3493 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U1/U4/LatchEdge1r_MC.D2_PT_1/IN6 \ ~wire 0 3494 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U1/U4/LatchEdge1r_MC.D2_PT_1/IN7 \ ~wire 0 3495 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U1/U4/LatchEdge1r_MC.D2_PT_2/IN0 \ ~wire 0 3496 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U1/U4/LatchEdge1r_MC.D2_PT_2/IN5 \ ~wire 0 3497 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U1/U4/LatchEdge1r_MC.D2_PT_2/IN6 \ ~wire 0 3498 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U1/U4/LatchEdge1r_MC.D2_PT_2/IN7 \ ~wire 0 3499 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U1/U4/LatchEdge1r_MC.D2_PT_2/IN9 \ ~wire 0 3500 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U3/DCORIE<6>_MC.D2_PT_1/IN0 \ ~wire 0 3501 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U3/DCORIE<6>_MC.D2_PT_1/IN2 \ ~wire 0 3502 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U3/DCORIE<6>_MC.D2_PT_1/IN5 \ ~wire 0 3503 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U3/DCORIE<6>_MC.D2_PT_1/IN6 \ ~wire 0 3504 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U3/DCORIE<6>_MC.D2_PT_1/IN7 \ ~wire 0 3505 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U3/DCORIE<6>_MC.D2_PT_2/IN0 \ ~wire 0 3506 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U3/DCORIE<6>_MC.D2_PT_2/IN2 \ ~wire 0 3507 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U3/DCORIE<6>_MC.D2_PT_2/IN5 \ ~wire 0 3508 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U3/DCORIE<6>_MC.D2_PT_2/IN6 \ ~wire 0 3509 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U3/DCORIE<6>_MC.D2_PT_2/IN7 \ ~wire 0 3510 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U3/DCORIE<6>_MC.D2_PT_2/IN9 \ ~wire 0 3511 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U3/DCORIE<7>_MC.D2_PT_1/IN0 \ ~wire 0 3512 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U3/DCORIE<7>_MC.D2_PT_1/IN2 \ ~wire 0 3513 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U3/DCORIE<7>_MC.D2_PT_1/IN5 \ ~wire 0 3514 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U3/DCORIE<7>_MC.D2_PT_1/IN6 \ ~wire 0 3515 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U3/DCORIE<7>_MC.D2_PT_1/IN7 \ ~wire 0 3516 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U3/DCORIE<7>_MC.D2_PT_2/IN0 \ ~wire 0 3517 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U3/DCORIE<7>_MC.D2_PT_2/IN2 \ ~wire 0 3518 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U3/DCORIE<7>_MC.D2_PT_2/IN5 \ ~wire 0 3519 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U3/DCORIE<7>_MC.D2_PT_2/IN6 \ ~wire 0 3520 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U3/DCORIE<7>_MC.D2_PT_2/IN7 \ ~wire 0 3521 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U3/DCORIE<7>_MC.D2_PT_2/IN9 \ ~wire 0 3522 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_LED1_MC.D/IN0 \ ~wire 0 3523 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_LED1_MC.D1/IN1 \ ~wire 0 3524 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U9/MISCr<0>_MC.D/IN0 \ ~wire 0 3525 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U9/MISCr<0>_MC.D2_PT_0/IN1 \ ~wire 0 3526 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U9/MISCr<0>_MC.D2_PT_1/IN1 \ ~wire 0 3527 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U9/MISCr<0>_MC.D2_PT_2/IN1 \ ~wire 0 3528 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U9/MISCr<0>_MC.D2_PT_2/IN7 \ ~wire 0 3529 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U9/MISCr<0>_MC.D2_PT_3/IN1 \ ~wire 0 3530 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U9/MISCr<0>_MC.D2_PT_3/IN5 \ ~wire 0 3531 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U9/MISCr<0>_MC.D2_PT_3/IN6 \ ~wire 0 3532 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U9/MISCr<0>_MC.D2_PT_3/IN7 \ ~wire 0 3533 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U9/MISCr<0>_MC.D2_PT_4/IN1 \ ~wire 0 3534 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U9/MISCr<0>_MC.D2_PT_4/IN3 \ ~wire 0 3535 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U9/MISCr<0>_MC.D2_PT_4/IN7 \ ~wire 0 3536 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U9/MISCr<0>_MC.D2_PT_5/IN1 \ ~wire 0 3537 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U9/MISCr<0>_MC.D2_PT_5/IN2 \ ~wire 0 3538 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U9/MISCr<0>_MC.D2_PT_5/IN3 \ ~wire 0 3539 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U9/MISCr<0>_MC.D2_PT_5/IN5 \ ~wire 0 3540 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U9/MISCr<0>_MC.D2_PT_5/IN6 \ ~wire 0 3541 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U9/MISCr<0>_MC.D2_PT_5/IN7 \ ~wire 0 3542 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_LED2_MC.D/IN0 \ ~wire 0 3543 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_LED2_MC.D1/IN1 \ ~wire 0 3544 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
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		(_signal (_internal \NlwInverterSignal_U9/MISCr<1>_MC.D2_PT_5/IN4 \ ~wire 0 3558 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
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		(_signal (_internal \NlwInverterSignal_LED3_MC.D1/IN1 \ ~wire 0 3561 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U9/MISCr<2>_MC.D/IN0 \ ~wire 0 3562 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U9/MISCr<2>_MC.D2_PT_0/IN1 \ ~wire 0 3563 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U9/MISCr<2>_MC.D2_PT_1/IN1 \ ~wire 0 3564 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U9/MISCr<2>_MC.D2_PT_2/IN1 \ ~wire 0 3565 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U9/MISCr<2>_MC.D2_PT_2/IN7 \ ~wire 0 3566 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U9/MISCr<2>_MC.D2_PT_3/IN1 \ ~wire 0 3567 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U9/MISCr<2>_MC.D2_PT_3/IN5 \ ~wire 0 3568 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U9/MISCr<2>_MC.D2_PT_3/IN6 \ ~wire 0 3569 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U9/MISCr<2>_MC.D2_PT_3/IN7 \ ~wire 0 3570 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U9/MISCr<2>_MC.D2_PT_4/IN1 \ ~wire 0 3571 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U9/MISCr<2>_MC.D2_PT_4/IN3 \ ~wire 0 3572 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U9/MISCr<2>_MC.D2_PT_4/IN7 \ ~wire 0 3573 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U9/MISCr<2>_MC.D2_PT_5/IN1 \ ~wire 0 3574 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U9/MISCr<2>_MC.D2_PT_5/IN2 \ ~wire 0 3575 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U9/MISCr<2>_MC.D2_PT_5/IN3 \ ~wire 0 3576 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U9/MISCr<2>_MC.D2_PT_5/IN5 \ ~wire 0 3577 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U9/MISCr<2>_MC.D2_PT_5/IN6 \ ~wire 0 3578 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U9/MISCr<2>_MC.D2_PT_5/IN7 \ ~wire 0 3579 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_LED4_MC.D/IN0 \ ~wire 0 3580 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_LED4_MC.D1/IN1 \ ~wire 0 3581 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U9/MISCr<3>_MC.D/IN0 \ ~wire 0 3582 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U9/MISCr<3>_MC.D2_PT_0/IN1 \ ~wire 0 3583 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U9/MISCr<3>_MC.D2_PT_1/IN1 \ ~wire 0 3584 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U9/MISCr<3>_MC.D2_PT_2/IN1 \ ~wire 0 3585 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U9/MISCr<3>_MC.D2_PT_2/IN7 \ ~wire 0 3586 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U9/MISCr<3>_MC.D2_PT_3/IN1 \ ~wire 0 3587 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U9/MISCr<3>_MC.D2_PT_3/IN5 \ ~wire 0 3588 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U9/MISCr<3>_MC.D2_PT_3/IN6 \ ~wire 0 3589 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U9/MISCr<3>_MC.D2_PT_3/IN7 \ ~wire 0 3590 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U9/MISCr<3>_MC.D2_PT_4/IN1 \ ~wire 0 3591 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U9/MISCr<3>_MC.D2_PT_4/IN3 \ ~wire 0 3592 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U9/MISCr<3>_MC.D2_PT_4/IN7 \ ~wire 0 3593 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U9/MISCr<3>_MC.D2_PT_5/IN1 \ ~wire 0 3594 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U9/MISCr<3>_MC.D2_PT_5/IN2 \ ~wire 0 3595 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U9/MISCr<3>_MC.D2_PT_5/IN3 \ ~wire 0 3596 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U9/MISCr<3>_MC.D2_PT_5/IN5 \ ~wire 0 3597 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U9/MISCr<3>_MC.D2_PT_5/IN6 \ ~wire 0 3598 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U9/MISCr<3>_MC.D2_PT_5/IN7 \ ~wire 0 3599 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_LED5_MC.D/IN0 \ ~wire 0 3600 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_LED5_MC.D1/IN1 \ ~wire 0 3601 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U9/MISCr<4>_MC.D/IN0 \ ~wire 0 3602 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U9/MISCr<4>_MC.D2_PT_0/IN1 \ ~wire 0 3603 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U9/MISCr<4>_MC.D2_PT_1/IN1 \ ~wire 0 3604 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U9/MISCr<4>_MC.D2_PT_2/IN1 \ ~wire 0 3605 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U9/MISCr<4>_MC.D2_PT_2/IN7 \ ~wire 0 3606 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U9/MISCr<4>_MC.D2_PT_3/IN1 \ ~wire 0 3607 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U9/MISCr<4>_MC.D2_PT_3/IN5 \ ~wire 0 3608 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U9/MISCr<4>_MC.D2_PT_3/IN6 \ ~wire 0 3609 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U9/MISCr<4>_MC.D2_PT_3/IN7 \ ~wire 0 3610 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U9/MISCr<4>_MC.D2_PT_4/IN1 \ ~wire 0 3611 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U9/MISCr<4>_MC.D2_PT_4/IN3 \ ~wire 0 3612 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U9/MISCr<4>_MC.D2_PT_4/IN7 \ ~wire 0 3613 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U9/MISCr<4>_MC.D2_PT_5/IN1 \ ~wire 0 3614 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U9/MISCr<4>_MC.D2_PT_5/IN2 \ ~wire 0 3615 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U9/MISCr<4>_MC.D2_PT_5/IN3 \ ~wire 0 3616 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U9/MISCr<4>_MC.D2_PT_5/IN5 \ ~wire 0 3617 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U9/MISCr<4>_MC.D2_PT_5/IN6 \ ~wire 0 3618 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U9/MISCr<4>_MC.D2_PT_5/IN7 \ ~wire 0 3619 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_MTRpwrn_MC.D/IN0 \ ~wire 0 3620 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_PAH0_MC.D1/IN0 \ ~wire 0 3621 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_PAH0_MC.D1/IN1 \ ~wire 0 3622 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_PAH0_MC.D1/IN3 \ ~wire 0 3623 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_NET3248_MC.D2_PT_0/IN0 \ ~wire 0 3624 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_NET3248_MC.D2_PT_0/IN1 \ ~wire 0 3625 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_NET3248_MC.D2_PT_1/IN0 \ ~wire 0 3626 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_NET3248_MC.D2_PT_1/IN2 \ ~wire 0 3627 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_NET3248_MC.D2_PT_2/IN0 \ ~wire 0 3628 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_NET3248_MC.D2_PT_2/IN1 \ ~wire 0 3629 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_NET3248_MC.D2_PT_2/IN2 \ ~wire 0 3630 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_PAH1_MC.D2_PT_0/IN0 \ ~wire 0 3631 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_PAH1_MC.D2_PT_0/IN1 \ ~wire 0 3632 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_PAH1_MC.D2_PT_1/IN0 \ ~wire 0 3633 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_PAH1_MC.D2_PT_1/IN1 \ ~wire 0 3634 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_PAH1_MC.D2_PT_1/IN2 \ ~wire 0 3635 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_PAH1_MC.D2_PT_1/IN3 \ ~wire 0 3636 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_PAL0_MC.D2_PT_0/IN0 \ ~wire 0 3637 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_PAL0_MC.D2_PT_0/IN2 \ ~wire 0 3638 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_PAL0_MC.D2_PT_0/IN3 \ ~wire 0 3639 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_PAL0_MC.D2_PT_1/IN0 \ ~wire 0 3640 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_PAL0_MC.D2_PT_1/IN1 \ ~wire 0 3641 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_PAL0_MC.D2_PT_1/IN3 \ ~wire 0 3642 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_PAL1_MC.D1/IN0 \ ~wire 0 3643 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_PAL1_MC.D1/IN1 \ ~wire 0 3644 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_PBH0_MC.D1/IN0 \ ~wire 0 3645 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_PBH0_MC.D1/IN3 \ ~wire 0 3646 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_PBH1_MC.D2_PT_0/IN0 \ ~wire 0 3647 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_PBH1_MC.D2_PT_0/IN1 \ ~wire 0 3648 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_PBH1_MC.D2_PT_0/IN3 \ ~wire 0 3649 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_PBH1_MC.D2_PT_1/IN0 \ ~wire 0 3650 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_PBH1_MC.D2_PT_1/IN1 \ ~wire 0 3651 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_PBH1_MC.D2_PT_1/IN2 \ ~wire 0 3652 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_PBL0_MC.D2_PT_0/IN0 \ ~wire 0 3653 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_PBL0_MC.D2_PT_0/IN3 \ ~wire 0 3654 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_PBL0_MC.D2_PT_1/IN0 \ ~wire 0 3655 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_PBL0_MC.D2_PT_1/IN1 \ ~wire 0 3656 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_PBL0_MC.D2_PT_1/IN2 \ ~wire 0 3657 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_PBL0_MC.D2_PT_1/IN3 \ ~wire 0 3658 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_PBL1_MC.D1/IN0 \ ~wire 0 3659 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_PBL1_MC.D1/IN1 \ ~wire 0 3660 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_PBL1_MC.D1/IN2 \ ~wire 0 3661 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
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		(_signal (_internal \NlwInverterSignal_U1/U3/holdingreg<16>_MC.D2_PT_1/IN0 \ ~wire 0 3668 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U1/U3/holdingreg<16>_MC.D2_PT_2/IN1 \ ~wire 0 3669 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
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		(_signal (_internal \NlwInverterSignal_U1/U3/holdingreg<17>_MC.D2_PT_2/IN7 \ ~wire 0 3708 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U1/U3/holdingreg<17>_MC.D2_PT_2/IN8 \ ~wire 0 3709 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U1/U3/holdingreg<9>_MC.D2_PT_1/IN0 \ ~wire 0 3710 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U1/U3/holdingreg<9>_MC.D2_PT_2/IN1 \ ~wire 0 3711 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U1/U3/holdingreg<9>_MC.D2_PT_2/IN6 \ ~wire 0 3712 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
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		(_signal (_internal \NlwInverterSignal_outDATA<1>\\$WA3.UIM_MC.D2_PT_0/IN7 \ ~wire 0 3716 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_outDATA<1>\\$WA3.UIM_MC.D2_PT_1/IN1 \ ~wire 0 3717 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
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		(_signal (_internal \NlwInverterSignal_outDATA<1>\\$WA4.UIM_MC.D2_PT_2/IN1 \ ~wire 0 3721 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
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		(_signal (_internal \NlwInverterSignal_U1/U4/Latch0r<4>_MC.D2_PT_1/IN2 \ ~wire 0 3844 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U1/U4/Latch1r<4>_MC.D2_PT_0/IN0 \ ~wire 0 3845 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U1/U4/Latch1r<4>_MC.D2_PT_1/IN0 \ ~wire 0 3846 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U1/U4/Latch1r<4>_MC.D2_PT_1/IN4 \ ~wire 0 3847 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U1/U4/Latch1r<4>_MC.D2_PT_1/IN5 \ ~wire 0 3848 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U1/U4/Latch1r<4>_MC.D2_PT_1/IN6 \ ~wire 0 3849 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U1/U4/Latch1r<12>_MC.D2_PT_0/IN0 \ ~wire 0 3850 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U1/U4/Latch1r<12>_MC.D2_PT_1/IN0 \ ~wire 0 3851 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U1/U4/Latch1r<12>_MC.D2_PT_1/IN4 \ ~wire 0 3852 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U1/U4/Latch1r<12>_MC.D2_PT_1/IN5 \ ~wire 0 3853 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_U1/U4/Latch1r<12>_MC.D2_PT_1/IN6 \ ~wire 0 3854 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_FOOBAR4__ctinst/0/IN0 \ ~wire 0 3855 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_FOOBAR4__ctinst/0/IN1 \ ~wire 0 3856 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_FOOBAR4__ctinst/0/IN2 \ ~wire 0 3857 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_FOOBAR4__ctinst/0/IN3 \ ~wire 0 3858 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_FOOBAR4__ctinst/0/IN4 \ ~wire 0 3859 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_FOOBAR4__ctinst/0/IN5 \ ~wire 0 3860 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_FOOBAR7__ctinst/4/IN0 \ ~wire 0 3861 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_FOOBAR8__ctinst/4/IN0 \ ~wire 0 3862 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_FOOBAR10__ctinst/4/IN0 \ ~wire 0 3863 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_FOOBAR12__ctinst/4/IN0 \ ~wire 0 3864 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_FOOBAR14__ctinst/4/IN0 \ ~wire 0 3865 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_FOOBAR14__ctinst/4/IN3 \ ~wire 0 3866 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_FOOBAR15__ctinst/4/IN0 \ ~wire 0 3867 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_FOOBAR16__ctinst/4/IN0 \ ~wire 0 3868 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_FOOBAR16__ctinst/4/IN1 \ ~wire 0 3869 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_FOOBAR18__ctinst/4/IN0 \ ~wire 0 3870 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_FOOBAR21__ctinst/4/IN0 \ ~wire 0 3871 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_FOOBAR21__ctinst/4/IN1 \ ~wire 0 3872 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_FOOBAR23__ctinst/4/IN0 \ ~wire 0 3873 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_FOOBAR23__ctinst/4/IN3 \ ~wire 0 3874 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_FOOBAR24__ctinst/4/IN0 \ ~wire 0 3875 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \NlwInverterSignal_FOOBAR24__ctinst/4/IN1 \ ~wire 0 3876 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_type (_internal ~[4:0]wire~ 0 3877 (_array ~wire ((_downto (i 4) (i 0))))))
		(_signal (_internal \U9/MISCr \ ~[4:0]wire~ 0 3877 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NlwRenamedSig_IO_I2CS ~[5:0]wire~ 0 3878 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal \U4/Flgreg \ ~[7:0]wire~ 0 3879 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal U2_ADDR_reg ~[7:0]wire~ 0 3880 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal U11_U3_counterr ~[5:0]wire~ 0 3881 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_type (_internal ~[23:0]wire~ 0 3882 (_array ~wire ((_downto (i 23) (i 0))))))
		(_signal (_internal \U1/U3/holdingreg \ ~[23:0]wire~ 0 3882 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \U1/Channel1 \ ~[23:0]wire~ 0 3883 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \U1/Channel0 \ ~[23:0]wire~ 0 3884 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_type (_internal ~[0:0]wire~ 0 3885 (_array ~wire ((_to (i 0) (i 0))))))
		(_signal (_internal \U1/U2/location_Maddsub__n0000__n0115 \ ~[0:0]wire~ 0 3885 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \U1/U2/location_Maddsub__n0000__n0103 \ ~[0:0]wire~ 0 3886 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \U1/U5/location_Maddsub__n0000__n0115 \ ~[0:0]wire~ 0 3887 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \U1/U5/location_Maddsub__n0000__n0103 \ ~[0:0]wire~ 0 3888 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_type (_internal ~[15:0]wire~ 0 3889 (_array ~wire ((_downto (i 15) (i 0))))))
		(_signal (_internal \U1/U4/Latch1r \ ~[15:0]wire~ 0 3889 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \U1/U4/Latch0r \ ~[15:0]wire~ 0 3890 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal \U3/DCORIE \ ~[7:0]wire~ 0 3891 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_toward 0 glbl.PRLD) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_subprogram
			

		)
		(_type (_external ~wire (vl verilog_logic wire)))
		(_type (_external ~reg (vl verilog_logic reg)))
		(_type (_external ~event (vl verilog_logic event)))
		(_type (_external ~wand (vl verilog_logic wand)))
		(_type (_external ~wor (vl verilog_logic wor)))
		(_type (_external ~tri1 (vl verilog_logic tri1)))
		(_type (_external ~tri0 (vl verilog_logic tri0)))
		(_type (_external ~trireg (vl verilog_logic trireg)))
		(_type (_external ~supply0 (vl verilog_logic supply0)))
		(_type (_external ~supply1 (vl verilog_logic supply1)))
		(_type (_external ~real (vl verilog_logic real)))
		(_type (_external ~realtime (vl verilog_logic realtime)))
		(_type (_external ~tri (vl verilog_logic tri)))
		(_type (_external ~triand (vl verilog_logic triand)))
		(_type (_external ~trior (vl verilog_logic trior)))
		(_type (_external ~bit (vl verilog_logic bit)))
		(_type (_external ~extstd.standard.integer (std standard integer)))
		(_type (_external ~extstd.standard.bit (std standard bit)))
		(_process
			(#ASSIGN#104_0 (_architecture 0 0 104 (_process (_simple)
				(_target(79))
				(_sensitivity(3867))
			)))
			(#ASSIGN#3936_1 (_architecture 1 0 3936 (_process (_alias ((NlwRenamedSig_IO_WR)(WR)))(_simple)
				(_target(70))
				(_sensitivity(0))
			)))
			(#ASSIGN#3936_2 (_architecture 2 0 3936 (_process (_alias ((NlwRenamedSig_IO_RD)(RD)))(_simple)
				(_target(72))
				(_sensitivity(1))
			)))
			(#ASSIGN#3936_3 (_architecture 3 0 3936 (_process (_alias ((NlwRenamedSig_IO_Reset)(Reset)))(_simple)
				(_target(74))
				(_sensitivity(2))
			)))
			(#ASSIGN#3936_4 (_architecture 4 0 3936 (_process (_alias ((NlwRenamedSig_IO_AS)(AS)))(_simple)
				(_target(84))
				(_sensitivity(3))
			)))
			(#ASSIGN#3936_5 (_architecture 5 0 3936 (_process (_alias ((NlwRenamedSig_IO_Mclk)(Mclk)))(_simple)
				(_target(89))
				(_sensitivity(4))
			)))
			(#ASSIGN#3936_6 (_architecture 6 0 3936 (_process (_alias ((NlwRenamedSig_IO_SCLreset)(SCLreset)))(_simple)
				(_target(106))
				(_sensitivity(5))
			)))
			(#ASSIGN#3936_7 (_architecture 7 0 3936 (_process (_alias ((NlwRenamedSig_IO_SCLinc)(SCLinc)))(_simple)
				(_target(108))
				(_sensitivity(6))
			)))
			(#ASSIGN#3936_8 (_architecture 8 0 3936 (_process (_alias ((NlwRenamedSig_IO_I2CS(5))(I2CS(5))))(_simple)
				(_target(3853(5)))
				(_sensitivity(68(5)))
			)))
			(#ASSIGN#3936_9 (_architecture 9 0 3936 (_process (_alias ((NlwRenamedSig_IO_FLS1)(FLS1)))(_simple)
				(_target(118))
				(_sensitivity(7))
			)))
			(#ASSIGN#3936_10 (_architecture 10 0 3936 (_process (_alias ((NlwRenamedSig_IO_Home15FLG)(Home15FLG)))(_simple)
				(_target(120))
				(_sensitivity(8))
			)))
			(#ASSIGN#3936_11 (_architecture 11 0 3936 (_process (_alias ((NlwRenamedSig_IO_Home033FLG)(Home033FLG)))(_simple)
				(_target(124))
				(_sensitivity(9))
			)))
			(#ASSIGN#3936_12 (_architecture 12 0 3936 (_process (_alias ((NlwRenamedSig_IO_Home05FLG)(Home05FLG)))(_simple)
				(_target(127))
				(_sensitivity(10))
			)))
			(#ASSIGN#3936_13 (_architecture 13 0 3936 (_process (_alias ((NlwRenamedSig_IO_Enc033FLG)(Enc033FLG)))(_simple)
				(_target(130))
				(_sensitivity(11))
			)))
			(#ASSIGN#3936_14 (_architecture 14 0 3936 (_process (_alias ((NlwRenamedSig_IO_Enc05FLG)(Enc05FLG)))(_simple)
				(_target(134))
				(_sensitivity(12))
			)))
			(#ASSIGN#3936_15 (_architecture 15 0 3936 (_process (_alias ((NlwRenamedSig_IO_Home133FLG)(Home133FLG)))(_simple)
				(_target(137))
				(_sensitivity(13))
			)))
			(#ASSIGN#3936_16 (_architecture 16 0 3936 (_process (_alias ((NlwRenamedSig_IO_Enc133FLG)(Enc133FLG)))(_simple)
				(_target(140))
				(_sensitivity(14))
			)))
			(#ASSIGN#3936_17 (_architecture 17 0 3936 (_process (_alias ((NlwRenamedSig_IO_Enc15FLG)(Enc15FLG)))(_simple)
				(_target(143))
				(_sensitivity(15))
			)))
			(#ASSIGN#3936_18 (_architecture 18 0 3936 (_process (_alias ((NlwRenamedSig_IO_PhaseA_Encoder0)(PhaseA_Encoder0)))(_simple)
				(_target(146))
				(_sensitivity(16))
			)))
			(#ASSIGN#3936_19 (_architecture 19 0 3936 (_process (_alias ((NlwRenamedSig_IO_PhaseB_Encoder0)(PhaseB_Encoder0)))(_simple)
				(_target(148))
				(_sensitivity(17))
			)))
			(#ASSIGN#3936_20 (_architecture 20 0 3936 (_process (_alias ((NlwRenamedSig_IO_PhaseA_Encoder1)(PhaseA_Encoder1)))(_simple)
				(_target(150))
				(_sensitivity(18))
			)))
			(#ASSIGN#3936_21 (_architecture 21 0 3936 (_process (_alias ((NlwRenamedSig_IO_PhaseB_Encoder1)(PhaseB_Encoder1)))(_simple)
				(_target(152))
				(_sensitivity(19))
			)))
			(#ASSIGN#3936_22 (_architecture 22 0 3936 (_process (_alias ((NlwRenamedSig_IO_GP_Motor0_0)(GP_Motor0_0)))(_simple)
				(_target(154))
				(_sensitivity(20))
			)))
			(#ASSIGN#3936_23 (_architecture 23 0 3936 (_process (_alias ((NlwRenamedSig_IO_Home1)(Home1)))(_simple)
				(_target(159))
				(_sensitivity(21))
			)))
			(#ASSIGN#3936_24 (_architecture 24 0 3936 (_process (_alias ((NlwRenamedSig_IO_GP_Motor1_0)(GP_Motor1_0)))(_simple)
				(_target(164))
				(_sensitivity(22))
			)))
			(#ASSIGN#3936_25 (_architecture 25 0 3936 (_process (_alias ((NlwRenamedSig_IO_DIR1)(DIR1)))(_simple)
				(_target(169))
				(_sensitivity(23))
			)))
			(#ASSIGN#3936_26 (_architecture 26 0 3936 (_process (_alias ((NlwRenamedSig_IO_RLS1)(RLS1)))(_simple)
				(_target(171))
				(_sensitivity(24))
			)))
			(#ASSIGN#3936_27 (_architecture 27 0 3936 (_process (_alias ((NlwRenamedSig_IO_Brake1)(Brake1)))(_simple)
				(_target(173))
				(_sensitivity(25))
			)))
			(#ASSIGN#3936_28 (_architecture 28 0 3936 (_process (_alias ((NlwRenamedSig_IO_Brake0)(Brake0)))(_simple)
				(_target(175))
				(_sensitivity(26))
			)))
			(#ASSIGN#3936_29 (_architecture 29 0 3936 (_process (_alias ((NlwRenamedSig_IO_DIR0)(DIR0)))(_simple)
				(_target(177))
				(_sensitivity(27))
			)))
			(#ASSIGN#3936_30 (_architecture 30 0 3936 (_process (_alias ((NlwRenamedSig_IO_FLS0)(FLS0)))(_simple)
				(_target(179))
				(_sensitivity(28))
			)))
			(#ASSIGN#3936_31 (_architecture 31 0 3936 (_process (_alias ((NlwRenamedSig_IO_HSI)(HSI)))(_simple)
				(_target(181))
				(_sensitivity(29))
			)))
			(#ASSIGN#3936_32 (_architecture 32 0 3936 (_process (_alias ((NlwRenamedSig_IO_MHSO)(MHSO)))(_simple)
				(_target(183))
				(_sensitivity(30))
			)))
			(#ASSIGN#3936_33 (_architecture 33 0 3936 (_process (_alias ((NlwRenamedSig_IO_I2CS(0))(I2CS(0))))(_simple)
				(_target(3853(0)))
				(_sensitivity(68(0)))
			)))
			(#ASSIGN#3936_34 (_architecture 34 0 3936 (_process (_alias ((NlwRenamedSig_IO_I2CS(1))(I2CS(1))))(_simple)
				(_target(3853(1)))
				(_sensitivity(68(1)))
			)))
			(#ASSIGN#3936_35 (_architecture 35 0 3936 (_process (_alias ((NlwRenamedSig_IO_I2CS(2))(I2CS(2))))(_simple)
				(_target(3853(2)))
				(_sensitivity(68(2)))
			)))
			(#ASSIGN#3936_36 (_architecture 36 0 3936 (_process (_alias ((NlwRenamedSig_IO_I2CS(3))(I2CS(3))))(_simple)
				(_target(3853(3)))
				(_sensitivity(68(3)))
			)))
			(#ASSIGN#3936_37 (_architecture 37 0 3936 (_process (_alias ((NlwRenamedSig_IO_I2CS(4))(I2CS(4))))(_simple)
				(_target(3853(4)))
				(_sensitivity(68(4)))
			)))
			(#ASSIGN#3936_38 (_architecture 38 0 3936 (_process (_alias ((NlwRenamedSig_IO_INTbus)(INTbus)))(_simple)
				(_target(190))
				(_sensitivity(31))
			)))
			(#ASSIGN#3936_39 (_architecture 39 0 3936 (_process (_alias ((NlwRenamedSig_IO_RLS0)(RLS0)))(_simple)
				(_target(192))
				(_sensitivity(32))
			)))
			(#ASSIGN#3936_40 (_architecture 40 0 3936 (_process (_alias ((NlwRenamedSig_IO_LightSense)(LightSense)))(_simple)
				(_target(194))
				(_sensitivity(33))
			)))
			(#ASSIGN#3936_41 (_architecture 41 0 3936 (_process (_alias ((NlwRenamedSig_IO_TXI)(TXI)))(_simple)
				(_target(196))
				(_sensitivity(34))
			)))
			(#ASSIGN#3936_42 (_architecture 42 0 3936 (_process (_alias ((NlwRenamedSig_IO_PWM1)(PWM1)))(_simple)
				(_target(198))
				(_sensitivity(35))
			)))
			(#ASSIGN#3936_43 (_architecture 43 0 3936 (_process (_alias ((NlwRenamedSig_IO_PWM2)(PWM2)))(_simple)
				(_target(200))
				(_sensitivity(36))
			)))
			(#ASSIGN#3936_44 (_architecture 44 0 3936 (_process (_alias ((NlwRenamedSig_IO_Home0)(Home0)))(_simple)
				(_target(202))
				(_sensitivity(37))
			)))
			(#INITIAL#3937_45 (_architecture 45 0 3937 (_process 
			)))
			(#INTERNAL#0_46 (_internal 46 0 0 (_process (_virtual))))
		)
	)
	
	
	(_defparam
	)
	(_scope
	)
	(_instantiation \WR.PAD \ 0 3938 (_entity .  X_IPAD)
		(_port
			((PAD) (NlwRenamedSig_IO_WR))
		)
		(_strength strong0 strong1)
	)
	(_instantiation WR_tsimcreated__pullup_ 0 3941 (_entity .  X_PU)
		(_port
			((O) (NlwRenamedSig_IO_WR))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \WR_II/UIM_0 \ 0 3944 (_entity .  X_BUF)
		(_port
			((I) (NlwRenamedSig_IO_WR))
			((O) (\WR_II/UIM \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \RD.PAD \ 0 3948 (_entity .  X_IPAD)
		(_port
			((PAD) (NlwRenamedSig_IO_RD))
		)
		(_strength strong0 strong1)
	)
	(_instantiation RD_tsimcreated__pullup_ 0 3951 (_entity .  X_PU)
		(_port
			((O) (NlwRenamedSig_IO_RD))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \RD_II/UIM_1 \ 0 3954 (_entity .  X_BUF)
		(_port
			((I) (NlwRenamedSig_IO_RD))
			((O) (\RD_II/UIM \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \Reset.PAD \ 0 3958 (_entity .  X_IPAD)
		(_port
			((PAD) (NlwRenamedSig_IO_Reset))
		)
		(_strength strong0 strong1)
	)
	(_instantiation Reset_tsimcreated__pullup_ 0 3961 (_entity .  X_PU)
		(_port
			((O) (NlwRenamedSig_IO_Reset))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \Reset_II/UIM_2 \ 0 3964 (_entity .  X_BUF)
		(_port
			((I) (NlwRenamedSig_IO_Reset))
			((O) (\Reset_II/UIM \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \AD<0>_II/UIM_3 \ 0 3968 (_entity .  X_BUF)
		(_port
			((I) (AD(0)))
			((O) (\AD<0>_II/UIM \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \AD<0>_II/IREG_4 \ 0 3972 (_entity .  X_BUF)
		(_port
			((I) (\U9/MISCr \(0)))
			((O) (\AD<0>_II/IREG \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U9/MISCr<0>_MC_tsimcreated_prld__5 \ 0 3976 (_entity .  X_OR2)
		(_port
			((I0) (\FOOBAR1__ctinst/7 \))
			((I1) (PRLD))
			((O) (\U9/MISCr<0>_MC_tsimcreated_prld_ \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U9/MISCr<0>_MC.REG \ 0 3981 (_entity .  X_FF)
		(_port
			((I) (AD(0)))
			((CE) (\FOOBAR12__ctinst/4 \))
			((CLK) (\Mclk_II/FCLK \))
			((SET) (Gnd))
			((RST) (\U9/MISCr<0>_MC_tsimcreated_prld_ \))
			((O) (\U9/MISCr \(0)))
		)
		(_strength strong0 strong1)
	)
	(_instantiation Gnd_6 0 3989 (_entity .  X_ZERO)
		(_port
			((O) (Gnd))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \AS.PAD \ 0 3992 (_entity .  X_IPAD)
		(_port
			((PAD) (NlwRenamedSig_IO_AS))
		)
		(_strength strong0 strong1)
	)
	(_instantiation AS_tsimcreated__pullup_ 0 3995 (_entity .  X_PU)
		(_port
			((O) (NlwRenamedSig_IO_AS))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \AS_II/UIM_7 \ 0 3998 (_entity .  X_BUF)
		(_port
			((I) (NlwRenamedSig_IO_AS))
			((O) (\AS_II/UIM \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \AS_II/IREG_8 \ 0 4002 (_entity .  X_BUF)
		(_port
			((I) (U2_ASedge))
			((O) (\AS_II/IREG \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U2_ASedge_MC.REG \ 0 4006 (_entity .  X_FF)
		(_port
			((I) (NlwRenamedSig_IO_AS))
			((CE) (Vcc))
			((CLK) (\Mclk_II/FCLK \))
			((SET) (Gnd))
			((RST) (PRLD))
			((O) (U2_ASedge))
		)
		(_strength strong0 strong1)
	)
	(_instantiation Vcc_9 0 4014 (_entity .  X_ONE)
		(_port
			((O) (Vcc))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \Mclk.PAD \ 0 4017 (_entity .  X_IPAD)
		(_port
			((PAD) (NlwRenamedSig_IO_Mclk))
		)
		(_strength strong0 strong1)
	)
	(_instantiation Mclk_tsimcreated__pullup_ 0 4020 (_entity .  X_PU)
		(_port
			((O) (NlwRenamedSig_IO_Mclk))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \Mclk_II/FCLK_10 \ 0 4023 (_entity .  X_BUF)
		(_port
			((I) (NlwRenamedSig_IO_Mclk))
			((O) (\Mclk_II/FCLK \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \AD<4>_II/UIM_11 \ 0 4027 (_entity .  X_BUF)
		(_port
			((I) (AD(4)))
			((O) (\AD<4>_II/UIM \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \AD<4>_II/IREG_12 \ 0 4031 (_entity .  X_BUF)
		(_port
			((I) (\U9/MISCr \(4)))
			((O) (\AD<4>_II/IREG \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U9/MISCr<4>_MC_tsimcreated_prld__13 \ 0 4035 (_entity .  X_OR2)
		(_port
			((I0) (\FOOBAR1__ctinst/7 \))
			((I1) (PRLD))
			((O) (\U9/MISCr<4>_MC_tsimcreated_prld_ \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U9/MISCr<4>_MC.REG \ 0 4040 (_entity .  X_FF)
		(_port
			((I) (AD(4)))
			((CE) (\FOOBAR10__ctinst/4 \))
			((CLK) (\Mclk_II/FCLK \))
			((SET) (Gnd))
			((RST) (\U9/MISCr<4>_MC_tsimcreated_prld_ \))
			((O) (\U9/MISCr \(4)))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \AD<2>_II/UIM_14 \ 0 4048 (_entity .  X_BUF)
		(_port
			((I) (AD(2)))
			((O) (\AD<2>_II/UIM \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \AD<2>_II/IREG_15 \ 0 4052 (_entity .  X_BUF)
		(_port
			((I) (\U9/MISCr \(2)))
			((O) (\AD<2>_II/IREG \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U9/MISCr<2>_MC_tsimcreated_prld__16 \ 0 4056 (_entity .  X_OR2)
		(_port
			((I0) (\FOOBAR1__ctinst/7 \))
			((I1) (PRLD))
			((O) (\U9/MISCr<2>_MC_tsimcreated_prld_ \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U9/MISCr<2>_MC.REG \ 0 4061 (_entity .  X_FF)
		(_port
			((I) (AD(2)))
			((CE) (\FOOBAR12__ctinst/4 \))
			((CLK) (\Mclk_II/FCLK \))
			((SET) (Gnd))
			((RST) (\U9/MISCr<2>_MC_tsimcreated_prld_ \))
			((O) (\U9/MISCr \(2)))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \AD<3>_II/UIM_17 \ 0 4069 (_entity .  X_BUF)
		(_port
			((I) (AD(3)))
			((O) (\AD<3>_II/UIM \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \AD<3>_II/IREG_18 \ 0 4073 (_entity .  X_BUF)
		(_port
			((I) (\U9/MISCr \(3)))
			((O) (\AD<3>_II/IREG \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U9/MISCr<3>_MC_tsimcreated_prld__19 \ 0 4077 (_entity .  X_OR2)
		(_port
			((I0) (\FOOBAR1__ctinst/7 \))
			((I1) (PRLD))
			((O) (\U9/MISCr<3>_MC_tsimcreated_prld_ \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U9/MISCr<3>_MC.REG \ 0 4082 (_entity .  X_FF)
		(_port
			((I) (AD(3)))
			((CE) (\FOOBAR12__ctinst/4 \))
			((CLK) (\Mclk_II/FCLK \))
			((SET) (Gnd))
			((RST) (\U9/MISCr<3>_MC_tsimcreated_prld_ \))
			((O) (\U9/MISCr \(3)))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \AD<5>_II/UIM_20 \ 0 4090 (_entity .  X_BUF)
		(_port
			((I) (AD(5)))
			((O) (\AD<5>_II/UIM \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \AD<6>_II/UIM_21 \ 0 4094 (_entity .  X_BUF)
		(_port
			((I) (AD(6)))
			((O) (\AD<6>_II/UIM \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \AD<7>_II/UIM_22 \ 0 4098 (_entity .  X_BUF)
		(_port
			((I) (AD(7)))
			((O) (\AD<7>_II/UIM \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \AD<1>_II/UIM_23 \ 0 4102 (_entity .  X_BUF)
		(_port
			((I) (AD(1)))
			((O) (\AD<1>_II/UIM \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \AD<1>_II/IREG_24 \ 0 4106 (_entity .  X_BUF)
		(_port
			((I) (\U9/MISCr \(1)))
			((O) (\AD<1>_II/IREG \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U9/MISCr<1>_MC_tsimcreated_prld__25 \ 0 4110 (_entity .  X_OR2)
		(_port
			((I0) (\FOOBAR1__ctinst/7 \))
			((I1) (PRLD))
			((O) (\U9/MISCr<1>_MC_tsimcreated_prld_ \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U9/MISCr<1>_MC.REG \ 0 4115 (_entity .  X_FF)
		(_port
			((I) (AD(1)))
			((CE) (\FOOBAR12__ctinst/4 \))
			((CLK) (\Mclk_II/FCLK \))
			((SET) (Gnd))
			((RST) (\U9/MISCr<1>_MC_tsimcreated_prld_ \))
			((O) (\U9/MISCr \(1)))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \SCLreset.PAD \ 0 4123 (_entity .  X_IPAD)
		(_port
			((PAD) (NlwRenamedSig_IO_SCLreset))
		)
		(_strength strong0 strong1)
	)
	(_instantiation SCLreset_tsimcreated__pullup_ 0 4126 (_entity .  X_PU)
		(_port
			((O) (NlwRenamedSig_IO_SCLreset))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \SCLreset_II/UIM_26 \ 0 4129 (_entity .  X_BUF)
		(_port
			((I) (NlwRenamedSig_IO_SCLreset))
			((O) (\SCLreset_II/UIM \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \SCLinc.PAD \ 0 4133 (_entity .  X_IPAD)
		(_port
			((PAD) (NlwRenamedSig_IO_SCLinc))
		)
		(_strength strong0 strong1)
	)
	(_instantiation SCLinc_tsimcreated__pullup_ 0 4136 (_entity .  X_PU)
		(_port
			((O) (NlwRenamedSig_IO_SCLinc))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \SCLinc_II/UIM_27 \ 0 4139 (_entity .  X_BUF)
		(_port
			((I) (NlwRenamedSig_IO_SCLinc))
			((O) (\SCLinc_II/UIM \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \SCLinc_II/IREG_28 \ 0 4143 (_entity .  X_BUF)
		(_port
			((I) (\U11_U1/Line_last \))
			((O) (\SCLinc_II/IREG \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U11_U1/Line_last_MC.REG \ 0 4147 (_entity .  X_FF)
		(_port
			((I) (NlwRenamedSig_IO_SCLinc))
			((CE) (Vcc))
			((CLK) (\U11_U1/Line_last_MC.REG_tsimcreated_inv_Mclk_II/FCLK \))
			((SET) (Gnd))
			((RST) (PRLD))
			((O) (\U11_U1/Line_last \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U11_U1/Line_last_MC.REG_tsimcreated_inv_Mclk_II/FCLK_29 \ 0 4155 (_entity .  X_INV)
		(_port
			((I) (\Mclk_II/FCLK \))
			((O) (\U11_U1/Line_last_MC.REG_tsimcreated_inv_Mclk_II/FCLK \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \SCL_II/UIM_30 \ 0 4159 (_entity .  X_BUF)
		(_port
			((I) (SCL))
			((O) (\SCL_II/UIM \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \SCL_II/IREG_31 \ 0 4163 (_entity .  X_BUF)
		(_port
			((I) (\U11_U2/Line_last \))
			((O) (\SCL_II/IREG \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U11_U2/Line_last_MC.REG \ 0 4167 (_entity .  X_FF)
		(_port
			((I) (SCL))
			((CE) (Vcc))
			((CLK) (\U11_U2/Line_last_MC.REG_tsimcreated_inv_Mclk_II/FCLK \))
			((SET) (Gnd))
			((RST) (PRLD))
			((O) (\U11_U2/Line_last \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U11_U2/Line_last_MC.REG_tsimcreated_inv_Mclk_II/FCLK_32 \ 0 4175 (_entity .  X_INV)
		(_port
			((I) (\Mclk_II/FCLK \))
			((O) (\U11_U2/Line_last_MC.REG_tsimcreated_inv_Mclk_II/FCLK \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \I2CS<5>.PAD \ 0 4179 (_entity .  X_IPAD)
		(_port
			((PAD) (NlwRenamedSig_IO_I2CS(5)))
		)
		(_strength strong0 strong1)
	)
	(_instantiation I2CS<5>_tsimcreated__pullup_ 0 4182 (_entity .  X_PU)
		(_port
			((O) (NlwRenamedSig_IO_I2CS(5)))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \I2CS<5>_II/UIM_33 \ 0 4185 (_entity .  X_BUF)
		(_port
			((I) (NlwRenamedSig_IO_I2CS(5)))
			((O) (\I2CS<5>_II/UIM \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \FLS1.PAD \ 0 4189 (_entity .  X_IPAD)
		(_port
			((PAD) (NlwRenamedSig_IO_FLS1))
		)
		(_strength strong0 strong1)
	)
	(_instantiation FLS1_tsimcreated__pullup_ 0 4192 (_entity .  X_PU)
		(_port
			((O) (NlwRenamedSig_IO_FLS1))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \FLS1_II/UIM_34 \ 0 4195 (_entity .  X_BUF)
		(_port
			((I) (NlwRenamedSig_IO_FLS1))
			((O) (\FLS1_II/UIM \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \Home15FLG.PAD \ 0 4199 (_entity .  X_IPAD)
		(_port
			((PAD) (NlwRenamedSig_IO_Home15FLG))
		)
		(_strength strong0 strong1)
	)
	(_instantiation Home15FLG_tsimcreated__pullup_ 0 4202 (_entity .  X_PU)
		(_port
			((O) (NlwRenamedSig_IO_Home15FLG))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \Home15FLG_II/UIM_35 \ 0 4205 (_entity .  X_BUF)
		(_port
			((I) (NlwRenamedSig_IO_Home15FLG))
			((O) (\Home15FLG_II/UIM \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \Home15FLG_II/IREG_36 \ 0 4209 (_entity .  X_BUF)
		(_port
			((I) (\U4/Flgreg \(5)))
			((O) (\Home15FLG_II/IREG \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U4/Flgreg<5>_MC.REG \ 0 4213 (_entity .  X_FF)
		(_port
			((I) (NlwRenamedSig_IO_Home15FLG))
			((CE) (\FOOBAR21__ctinst/4 \))
			((CLK) (\Mclk_II/FCLK \))
			((SET) (Gnd))
			((RST) (PRLD))
			((O) (\U4/Flgreg \(5)))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \Home033FLG.PAD \ 0 4221 (_entity .  X_IPAD)
		(_port
			((PAD) (NlwRenamedSig_IO_Home033FLG))
		)
		(_strength strong0 strong1)
	)
	(_instantiation Home033FLG_tsimcreated__pullup_ 0 4224 (_entity .  X_PU)
		(_port
			((O) (NlwRenamedSig_IO_Home033FLG))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \Home033FLG_II/UIM_37 \ 0 4227 (_entity .  X_BUF)
		(_port
			((I) (NlwRenamedSig_IO_Home033FLG))
			((O) (\Home033FLG_II/UIM \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \Home033FLG_II/IREG_38 \ 0 4231 (_entity .  X_BUF)
		(_port
			((I) (\U4/Flgreg \(0)))
			((O) (\Home033FLG_II/IREG \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U4/Flgreg<0>_MC.REG \ 0 4235 (_entity .  X_FF)
		(_port
			((I) (NlwRenamedSig_IO_Home033FLG))
			((CE) (\FOOBAR21__ctinst/4 \))
			((CLK) (\Mclk_II/FCLK \))
			((SET) (Gnd))
			((RST) (PRLD))
			((O) (\U4/Flgreg \(0)))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \Home05FLG.PAD \ 0 4243 (_entity .  X_IPAD)
		(_port
			((PAD) (NlwRenamedSig_IO_Home05FLG))
		)
		(_strength strong0 strong1)
	)
	(_instantiation Home05FLG_tsimcreated__pullup_ 0 4246 (_entity .  X_PU)
		(_port
			((O) (NlwRenamedSig_IO_Home05FLG))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \Home05FLG_II/UIM_39 \ 0 4249 (_entity .  X_BUF)
		(_port
			((I) (NlwRenamedSig_IO_Home05FLG))
			((O) (\Home05FLG_II/UIM \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \Home05FLG_II/IREG_40 \ 0 4253 (_entity .  X_BUF)
		(_port
			((I) (\U4/Flgreg \(1)))
			((O) (\Home05FLG_II/IREG \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U4/Flgreg<1>_MC.REG \ 0 4257 (_entity .  X_FF)
		(_port
			((I) (NlwRenamedSig_IO_Home05FLG))
			((CE) (\FOOBAR21__ctinst/4 \))
			((CLK) (\Mclk_II/FCLK \))
			((SET) (Gnd))
			((RST) (PRLD))
			((O) (\U4/Flgreg \(1)))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \Enc033FLG.PAD \ 0 4265 (_entity .  X_IPAD)
		(_port
			((PAD) (NlwRenamedSig_IO_Enc033FLG))
		)
		(_strength strong0 strong1)
	)
	(_instantiation Enc033FLG_tsimcreated__pullup_ 0 4268 (_entity .  X_PU)
		(_port
			((O) (NlwRenamedSig_IO_Enc033FLG))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \Enc033FLG_II/UIM_41 \ 0 4271 (_entity .  X_BUF)
		(_port
			((I) (NlwRenamedSig_IO_Enc033FLG))
			((O) (\Enc033FLG_II/UIM \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \Enc033FLG_II/IREG_42 \ 0 4275 (_entity .  X_BUF)
		(_port
			((I) (\U4/Flgreg \(2)))
			((O) (\Enc033FLG_II/IREG \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U4/Flgreg<2>_MC.REG \ 0 4279 (_entity .  X_FF)
		(_port
			((I) (NlwRenamedSig_IO_Enc033FLG))
			((CE) (\FOOBAR24__ctinst/4 \))
			((CLK) (\Mclk_II/FCLK \))
			((SET) (Gnd))
			((RST) (PRLD))
			((O) (\U4/Flgreg \(2)))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \Enc05FLG.PAD \ 0 4287 (_entity .  X_IPAD)
		(_port
			((PAD) (NlwRenamedSig_IO_Enc05FLG))
		)
		(_strength strong0 strong1)
	)
	(_instantiation Enc05FLG_tsimcreated__pullup_ 0 4290 (_entity .  X_PU)
		(_port
			((O) (NlwRenamedSig_IO_Enc05FLG))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \Enc05FLG_II/UIM_43 \ 0 4293 (_entity .  X_BUF)
		(_port
			((I) (NlwRenamedSig_IO_Enc05FLG))
			((O) (\Enc05FLG_II/UIM \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \Enc05FLG_II/IREG_44 \ 0 4297 (_entity .  X_BUF)
		(_port
			((I) (\U4/Flgreg \(3)))
			((O) (\Enc05FLG_II/IREG \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U4/Flgreg<3>_MC.REG \ 0 4301 (_entity .  X_FF)
		(_port
			((I) (NlwRenamedSig_IO_Enc05FLG))
			((CE) (\FOOBAR24__ctinst/4 \))
			((CLK) (\Mclk_II/FCLK \))
			((SET) (Gnd))
			((RST) (PRLD))
			((O) (\U4/Flgreg \(3)))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \Home133FLG.PAD \ 0 4309 (_entity .  X_IPAD)
		(_port
			((PAD) (NlwRenamedSig_IO_Home133FLG))
		)
		(_strength strong0 strong1)
	)
	(_instantiation Home133FLG_tsimcreated__pullup_ 0 4312 (_entity .  X_PU)
		(_port
			((O) (NlwRenamedSig_IO_Home133FLG))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \Home133FLG_II/UIM_45 \ 0 4315 (_entity .  X_BUF)
		(_port
			((I) (NlwRenamedSig_IO_Home133FLG))
			((O) (\Home133FLG_II/UIM \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \Home133FLG_II/IREG_46 \ 0 4319 (_entity .  X_BUF)
		(_port
			((I) (\U4/Flgreg \(4)))
			((O) (\Home133FLG_II/IREG \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U4/Flgreg<4>_MC.REG \ 0 4323 (_entity .  X_FF)
		(_port
			((I) (NlwRenamedSig_IO_Home133FLG))
			((CE) (\FOOBAR21__ctinst/4 \))
			((CLK) (\Mclk_II/FCLK \))
			((SET) (Gnd))
			((RST) (PRLD))
			((O) (\U4/Flgreg \(4)))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \Enc133FLG.PAD \ 0 4331 (_entity .  X_IPAD)
		(_port
			((PAD) (NlwRenamedSig_IO_Enc133FLG))
		)
		(_strength strong0 strong1)
	)
	(_instantiation Enc133FLG_tsimcreated__pullup_ 0 4334 (_entity .  X_PU)
		(_port
			((O) (NlwRenamedSig_IO_Enc133FLG))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \Enc133FLG_II/UIM_47 \ 0 4337 (_entity .  X_BUF)
		(_port
			((I) (NlwRenamedSig_IO_Enc133FLG))
			((O) (\Enc133FLG_II/UIM \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \Enc133FLG_II/IREG_48 \ 0 4341 (_entity .  X_BUF)
		(_port
			((I) (\U4/Flgreg \(6)))
			((O) (\Enc133FLG_II/IREG \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U4/Flgreg<6>_MC.REG \ 0 4345 (_entity .  X_FF)
		(_port
			((I) (NlwRenamedSig_IO_Enc133FLG))
			((CE) (\FOOBAR24__ctinst/4 \))
			((CLK) (\Mclk_II/FCLK \))
			((SET) (Gnd))
			((RST) (PRLD))
			((O) (\U4/Flgreg \(6)))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \Enc15FLG.PAD \ 0 4353 (_entity .  X_IPAD)
		(_port
			((PAD) (NlwRenamedSig_IO_Enc15FLG))
		)
		(_strength strong0 strong1)
	)
	(_instantiation Enc15FLG_tsimcreated__pullup_ 0 4356 (_entity .  X_PU)
		(_port
			((O) (NlwRenamedSig_IO_Enc15FLG))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \Enc15FLG_II/UIM_49 \ 0 4359 (_entity .  X_BUF)
		(_port
			((I) (NlwRenamedSig_IO_Enc15FLG))
			((O) (\Enc15FLG_II/UIM \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \Enc15FLG_II/IREG_50 \ 0 4363 (_entity .  X_BUF)
		(_port
			((I) (\U4/Flgreg \(7)))
			((O) (\Enc15FLG_II/IREG \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U4/Flgreg<7>_MC.REG \ 0 4367 (_entity .  X_FF)
		(_port
			((I) (NlwRenamedSig_IO_Enc15FLG))
			((CE) (\FOOBAR24__ctinst/4 \))
			((CLK) (\Mclk_II/FCLK \))
			((SET) (Gnd))
			((RST) (PRLD))
			((O) (\U4/Flgreg \(7)))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \PhaseA_Encoder0.PAD \ 0 4375 (_entity .  X_IPAD)
		(_port
			((PAD) (NlwRenamedSig_IO_PhaseA_Encoder0))
		)
		(_strength strong0 strong1)
	)
	(_instantiation PhaseA_Encoder0_tsimcreated__pullup_ 0 4378 (_entity .  X_PU)
		(_port
			((O) (NlwRenamedSig_IO_PhaseA_Encoder0))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \PhaseA_Encoder0_II/UIM_51 \ 0 4381 (_entity .  X_BUF)
		(_port
			((I) (NlwRenamedSig_IO_PhaseA_Encoder0))
			((O) (\PhaseA_Encoder0_II/UIM \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \PhaseB_Encoder0.PAD \ 0 4385 (_entity .  X_IPAD)
		(_port
			((PAD) (NlwRenamedSig_IO_PhaseB_Encoder0))
		)
		(_strength strong0 strong1)
	)
	(_instantiation PhaseB_Encoder0_tsimcreated__pullup_ 0 4388 (_entity .  X_PU)
		(_port
			((O) (NlwRenamedSig_IO_PhaseB_Encoder0))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \PhaseB_Encoder0_II/UIM_52 \ 0 4391 (_entity .  X_BUF)
		(_port
			((I) (NlwRenamedSig_IO_PhaseB_Encoder0))
			((O) (\PhaseB_Encoder0_II/UIM \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \PhaseA_Encoder1.PAD \ 0 4395 (_entity .  X_IPAD)
		(_port
			((PAD) (NlwRenamedSig_IO_PhaseA_Encoder1))
		)
		(_strength strong0 strong1)
	)
	(_instantiation PhaseA_Encoder1_tsimcreated__pullup_ 0 4398 (_entity .  X_PU)
		(_port
			((O) (NlwRenamedSig_IO_PhaseA_Encoder1))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \PhaseA_Encoder1_II/UIM_53 \ 0 4401 (_entity .  X_BUF)
		(_port
			((I) (NlwRenamedSig_IO_PhaseA_Encoder1))
			((O) (\PhaseA_Encoder1_II/UIM \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \PhaseB_Encoder1.PAD \ 0 4405 (_entity .  X_IPAD)
		(_port
			((PAD) (NlwRenamedSig_IO_PhaseB_Encoder1))
		)
		(_strength strong0 strong1)
	)
	(_instantiation PhaseB_Encoder1_tsimcreated__pullup_ 0 4408 (_entity .  X_PU)
		(_port
			((O) (NlwRenamedSig_IO_PhaseB_Encoder1))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \PhaseB_Encoder1_II/UIM_54 \ 0 4411 (_entity .  X_BUF)
		(_port
			((I) (NlwRenamedSig_IO_PhaseB_Encoder1))
			((O) (\PhaseB_Encoder1_II/UIM \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \GP_Motor0_0.PAD \ 0 4415 (_entity .  X_IPAD)
		(_port
			((PAD) (NlwRenamedSig_IO_GP_Motor0_0))
		)
		(_strength strong0 strong1)
	)
	(_instantiation GP_Motor0_0_tsimcreated__pullup_ 0 4418 (_entity .  X_PU)
		(_port
			((O) (NlwRenamedSig_IO_GP_Motor0_0))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \GP_Motor0_0_II/UIM_55 \ 0 4421 (_entity .  X_BUF)
		(_port
			((I) (NlwRenamedSig_IO_GP_Motor0_0))
			((O) (\GP_Motor0_0_II/UIM \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \GP_Motor0_0_II/IREG_56 \ 0 4425 (_entity .  X_BUF)
		(_port
			((I) (\U1/U4/InEdge0r \))
			((O) (\GP_Motor0_0_II/IREG \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U4/InEdge0r_MC.REG \ 0 4429 (_entity .  X_FF)
		(_port
			((I) (NlwRenamedSig_IO_GP_Motor0_0))
			((CE) (Vcc))
			((CLK) (\U1/U4/InEdge0r_MC.REG_tsimcreated_inv_Mclk_II/FCLK \))
			((SET) (Gnd))
			((RST) (PRLD))
			((O) (\U1/U4/InEdge0r \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U4/InEdge0r_MC.REG_tsimcreated_inv_Mclk_II/FCLK_57 \ 0 4437 (_entity .  X_INV)
		(_port
			((I) (\Mclk_II/FCLK \))
			((O) (\U1/U4/InEdge0r_MC.REG_tsimcreated_inv_Mclk_II/FCLK \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \Home1.PAD \ 0 4441 (_entity .  X_IPAD)
		(_port
			((PAD) (NlwRenamedSig_IO_Home1))
		)
		(_strength strong0 strong1)
	)
	(_instantiation Home1_tsimcreated__pullup_ 0 4444 (_entity .  X_PU)
		(_port
			((O) (NlwRenamedSig_IO_Home1))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \Home1_II/UIM_58 \ 0 4447 (_entity .  X_BUF)
		(_port
			((I) (NlwRenamedSig_IO_Home1))
			((O) (\Home1_II/UIM \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \Home1_II/IREG_59 \ 0 4451 (_entity .  X_BUF)
		(_port
			((I) (\U1/U4/HE1stater \))
			((O) (\Home1_II/IREG \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U4/HE1stater_MC.REG \ 0 4455 (_entity .  X_FF)
		(_port
			((I) (NlwRenamedSig_IO_Home1))
			((CE) (Vcc))
			((CLK) (\U1/U4/HE1stater_MC.REG_tsimcreated_inv_Mclk_II/FCLK \))
			((SET) (Gnd))
			((RST) (PRLD))
			((O) (\U1/U4/HE1stater \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U4/HE1stater_MC.REG_tsimcreated_inv_Mclk_II/FCLK_60 \ 0 4463 (_entity .  X_INV)
		(_port
			((I) (\Mclk_II/FCLK \))
			((O) (\U1/U4/HE1stater_MC.REG_tsimcreated_inv_Mclk_II/FCLK \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \GP_Motor1_0.PAD \ 0 4467 (_entity .  X_IPAD)
		(_port
			((PAD) (NlwRenamedSig_IO_GP_Motor1_0))
		)
		(_strength strong0 strong1)
	)
	(_instantiation GP_Motor1_0_tsimcreated__pullup_ 0 4470 (_entity .  X_PU)
		(_port
			((O) (NlwRenamedSig_IO_GP_Motor1_0))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \GP_Motor1_0_II/UIM_61 \ 0 4473 (_entity .  X_BUF)
		(_port
			((I) (NlwRenamedSig_IO_GP_Motor1_0))
			((O) (\GP_Motor1_0_II/UIM \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \GP_Motor1_0_II/IREG_62 \ 0 4477 (_entity .  X_BUF)
		(_port
			((I) (\U1/U4/InEdge1r \))
			((O) (\GP_Motor1_0_II/IREG \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U4/InEdge1r_MC.REG \ 0 4481 (_entity .  X_FF)
		(_port
			((I) (NlwRenamedSig_IO_GP_Motor1_0))
			((CE) (Vcc))
			((CLK) (\U1/U4/InEdge1r_MC.REG_tsimcreated_inv_Mclk_II/FCLK \))
			((SET) (Gnd))
			((RST) (PRLD))
			((O) (\U1/U4/InEdge1r \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U4/InEdge1r_MC.REG_tsimcreated_inv_Mclk_II/FCLK_63 \ 0 4489 (_entity .  X_INV)
		(_port
			((I) (\Mclk_II/FCLK \))
			((O) (\U1/U4/InEdge1r_MC.REG_tsimcreated_inv_Mclk_II/FCLK \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \DIR1.PAD \ 0 4493 (_entity .  X_IPAD)
		(_port
			((PAD) (NlwRenamedSig_IO_DIR1))
		)
		(_strength strong0 strong1)
	)
	(_instantiation DIR1_tsimcreated__pullup_ 0 4496 (_entity .  X_PU)
		(_port
			((O) (NlwRenamedSig_IO_DIR1))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \DIR1_II/UIM_64 \ 0 4499 (_entity .  X_BUF)
		(_port
			((I) (NlwRenamedSig_IO_DIR1))
			((O) (\DIR1_II/UIM \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \RLS1.PAD \ 0 4503 (_entity .  X_IPAD)
		(_port
			((PAD) (NlwRenamedSig_IO_RLS1))
		)
		(_strength strong0 strong1)
	)
	(_instantiation RLS1_tsimcreated__pullup_ 0 4506 (_entity .  X_PU)
		(_port
			((O) (NlwRenamedSig_IO_RLS1))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \RLS1_II/UIM_65 \ 0 4509 (_entity .  X_BUF)
		(_port
			((I) (NlwRenamedSig_IO_RLS1))
			((O) (\RLS1_II/UIM \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \Brake1.PAD \ 0 4513 (_entity .  X_IPAD)
		(_port
			((PAD) (NlwRenamedSig_IO_Brake1))
		)
		(_strength strong0 strong1)
	)
	(_instantiation Brake1_tsimcreated__pullup_ 0 4516 (_entity .  X_PU)
		(_port
			((O) (NlwRenamedSig_IO_Brake1))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \Brake1_II/UIM_66 \ 0 4519 (_entity .  X_BUF)
		(_port
			((I) (NlwRenamedSig_IO_Brake1))
			((O) (\Brake1_II/UIM \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \Brake0.PAD \ 0 4523 (_entity .  X_IPAD)
		(_port
			((PAD) (NlwRenamedSig_IO_Brake0))
		)
		(_strength strong0 strong1)
	)
	(_instantiation Brake0_tsimcreated__pullup_ 0 4526 (_entity .  X_PU)
		(_port
			((O) (NlwRenamedSig_IO_Brake0))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \Brake0_II/UIM_67 \ 0 4529 (_entity .  X_BUF)
		(_port
			((I) (NlwRenamedSig_IO_Brake0))
			((O) (\Brake0_II/UIM \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \DIR0.PAD \ 0 4533 (_entity .  X_IPAD)
		(_port
			((PAD) (NlwRenamedSig_IO_DIR0))
		)
		(_strength strong0 strong1)
	)
	(_instantiation DIR0_tsimcreated__pullup_ 0 4536 (_entity .  X_PU)
		(_port
			((O) (NlwRenamedSig_IO_DIR0))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \DIR0_II/UIM_68 \ 0 4539 (_entity .  X_BUF)
		(_port
			((I) (NlwRenamedSig_IO_DIR0))
			((O) (\DIR0_II/UIM \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \FLS0.PAD \ 0 4543 (_entity .  X_IPAD)
		(_port
			((PAD) (NlwRenamedSig_IO_FLS0))
		)
		(_strength strong0 strong1)
	)
	(_instantiation FLS0_tsimcreated__pullup_ 0 4546 (_entity .  X_PU)
		(_port
			((O) (NlwRenamedSig_IO_FLS0))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \FLS0_II/UIM_69 \ 0 4549 (_entity .  X_BUF)
		(_port
			((I) (NlwRenamedSig_IO_FLS0))
			((O) (\FLS0_II/UIM \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \HSI.PAD \ 0 4553 (_entity .  X_IPAD)
		(_port
			((PAD) (NlwRenamedSig_IO_HSI))
		)
		(_strength strong0 strong1)
	)
	(_instantiation HSI_tsimcreated__pullup_ 0 4556 (_entity .  X_PU)
		(_port
			((O) (NlwRenamedSig_IO_HSI))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \HSI_II/UIM_70 \ 0 4559 (_entity .  X_BUF)
		(_port
			((I) (NlwRenamedSig_IO_HSI))
			((O) (\HSI_II/UIM \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \MHSO.PAD \ 0 4563 (_entity .  X_IPAD)
		(_port
			((PAD) (NlwRenamedSig_IO_MHSO))
		)
		(_strength strong0 strong1)
	)
	(_instantiation MHSO_tsimcreated__pullup_ 0 4566 (_entity .  X_PU)
		(_port
			((O) (NlwRenamedSig_IO_MHSO))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \MHSO_II/UIM_71 \ 0 4569 (_entity .  X_BUF)
		(_port
			((I) (NlwRenamedSig_IO_MHSO))
			((O) (\MHSO_II/UIM \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \I2CS<0>.PAD \ 0 4573 (_entity .  X_IPAD)
		(_port
			((PAD) (NlwRenamedSig_IO_I2CS(0)))
		)
		(_strength strong0 strong1)
	)
	(_instantiation I2CS<0>_tsimcreated__pullup_ 0 4576 (_entity .  X_PU)
		(_port
			((O) (NlwRenamedSig_IO_I2CS(0)))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \I2CS<0>_II/UIM_72 \ 0 4579 (_entity .  X_BUF)
		(_port
			((I) (NlwRenamedSig_IO_I2CS(0)))
			((O) (\I2CS<0>_II/UIM \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \I2CS<1>.PAD \ 0 4583 (_entity .  X_IPAD)
		(_port
			((PAD) (NlwRenamedSig_IO_I2CS(1)))
		)
		(_strength strong0 strong1)
	)
	(_instantiation I2CS<1>_tsimcreated__pullup_ 0 4586 (_entity .  X_PU)
		(_port
			((O) (NlwRenamedSig_IO_I2CS(1)))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \I2CS<1>_II/UIM_73 \ 0 4589 (_entity .  X_BUF)
		(_port
			((I) (NlwRenamedSig_IO_I2CS(1)))
			((O) (\I2CS<1>_II/UIM \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \I2CS<2>.PAD \ 0 4593 (_entity .  X_IPAD)
		(_port
			((PAD) (NlwRenamedSig_IO_I2CS(2)))
		)
		(_strength strong0 strong1)
	)
	(_instantiation I2CS<2>_tsimcreated__pullup_ 0 4596 (_entity .  X_PU)
		(_port
			((O) (NlwRenamedSig_IO_I2CS(2)))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \I2CS<2>_II/UIM_74 \ 0 4599 (_entity .  X_BUF)
		(_port
			((I) (NlwRenamedSig_IO_I2CS(2)))
			((O) (\I2CS<2>_II/UIM \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \I2CS<3>.PAD \ 0 4603 (_entity .  X_IPAD)
		(_port
			((PAD) (NlwRenamedSig_IO_I2CS(3)))
		)
		(_strength strong0 strong1)
	)
	(_instantiation I2CS<3>_tsimcreated__pullup_ 0 4606 (_entity .  X_PU)
		(_port
			((O) (NlwRenamedSig_IO_I2CS(3)))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \I2CS<3>_II/UIM_75 \ 0 4609 (_entity .  X_BUF)
		(_port
			((I) (NlwRenamedSig_IO_I2CS(3)))
			((O) (\I2CS<3>_II/UIM \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \I2CS<4>.PAD \ 0 4613 (_entity .  X_IPAD)
		(_port
			((PAD) (NlwRenamedSig_IO_I2CS(4)))
		)
		(_strength strong0 strong1)
	)
	(_instantiation I2CS<4>_tsimcreated__pullup_ 0 4616 (_entity .  X_PU)
		(_port
			((O) (NlwRenamedSig_IO_I2CS(4)))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \I2CS<4>_II/UIM_76 \ 0 4619 (_entity .  X_BUF)
		(_port
			((I) (NlwRenamedSig_IO_I2CS(4)))
			((O) (\I2CS<4>_II/UIM \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \INTbus.PAD \ 0 4623 (_entity .  X_IPAD)
		(_port
			((PAD) (NlwRenamedSig_IO_INTbus))
		)
		(_strength strong0 strong1)
	)
	(_instantiation INTbus_tsimcreated__pullup_ 0 4626 (_entity .  X_PU)
		(_port
			((O) (NlwRenamedSig_IO_INTbus))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \INTbus_II/UIM_77 \ 0 4629 (_entity .  X_BUF)
		(_port
			((I) (NlwRenamedSig_IO_INTbus))
			((O) (\INTbus_II/UIM \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \RLS0.PAD \ 0 4633 (_entity .  X_IPAD)
		(_port
			((PAD) (NlwRenamedSig_IO_RLS0))
		)
		(_strength strong0 strong1)
	)
	(_instantiation RLS0_tsimcreated__pullup_ 0 4636 (_entity .  X_PU)
		(_port
			((O) (NlwRenamedSig_IO_RLS0))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \RLS0_II/UIM_78 \ 0 4639 (_entity .  X_BUF)
		(_port
			((I) (NlwRenamedSig_IO_RLS0))
			((O) (\RLS0_II/UIM \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \LightSense.PAD \ 0 4643 (_entity .  X_IPAD)
		(_port
			((PAD) (NlwRenamedSig_IO_LightSense))
		)
		(_strength strong0 strong1)
	)
	(_instantiation LightSense_tsimcreated__pullup_ 0 4646 (_entity .  X_PU)
		(_port
			((O) (NlwRenamedSig_IO_LightSense))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \LightSense_II/UIM_79 \ 0 4649 (_entity .  X_BUF)
		(_port
			((I) (NlwRenamedSig_IO_LightSense))
			((O) (\LightSense_II/UIM \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \TXI.PAD \ 0 4653 (_entity .  X_IPAD)
		(_port
			((PAD) (NlwRenamedSig_IO_TXI))
		)
		(_strength strong0 strong1)
	)
	(_instantiation TXI_tsimcreated__pullup_ 0 4656 (_entity .  X_PU)
		(_port
			((O) (NlwRenamedSig_IO_TXI))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \TXI_II/UIM_80 \ 0 4659 (_entity .  X_BUF)
		(_port
			((I) (NlwRenamedSig_IO_TXI))
			((O) (\TXI_II/UIM \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \PWM1.PAD \ 0 4663 (_entity .  X_IPAD)
		(_port
			((PAD) (NlwRenamedSig_IO_PWM1))
		)
		(_strength strong0 strong1)
	)
	(_instantiation PWM1_tsimcreated__pullup_ 0 4666 (_entity .  X_PU)
		(_port
			((O) (NlwRenamedSig_IO_PWM1))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \PWM1_II/UIM_81 \ 0 4669 (_entity .  X_BUF)
		(_port
			((I) (NlwRenamedSig_IO_PWM1))
			((O) (\PWM1_II/UIM \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \PWM2.PAD \ 0 4673 (_entity .  X_IPAD)
		(_port
			((PAD) (NlwRenamedSig_IO_PWM2))
		)
		(_strength strong0 strong1)
	)
	(_instantiation PWM2_tsimcreated__pullup_ 0 4676 (_entity .  X_PU)
		(_port
			((O) (NlwRenamedSig_IO_PWM2))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \PWM2_II/UIM_82 \ 0 4679 (_entity .  X_BUF)
		(_port
			((I) (NlwRenamedSig_IO_PWM2))
			((O) (\PWM2_II/UIM \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \Home0.PAD \ 0 4683 (_entity .  X_IPAD)
		(_port
			((PAD) (NlwRenamedSig_IO_Home0))
		)
		(_strength strong0 strong1)
	)
	(_instantiation Home0_tsimcreated__pullup_ 0 4686 (_entity .  X_PU)
		(_port
			((O) (NlwRenamedSig_IO_Home0))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \Home0_II/UIM_83 \ 0 4689 (_entity .  X_BUF)
		(_port
			((I) (NlwRenamedSig_IO_Home0))
			((O) (\Home0_II/UIM \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \Home0_II/IREG_84 \ 0 4693 (_entity .  X_BUF)
		(_port
			((I) (\U1/U4/HE0stater \))
			((O) (\Home0_II/IREG \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U4/HE0stater_MC.REG \ 0 4697 (_entity .  X_FF)
		(_port
			((I) (NlwRenamedSig_IO_Home0))
			((CE) (Vcc))
			((CLK) (\U1/U4/HE0stater_MC.REG_tsimcreated_inv_Mclk_II/FCLK \))
			((SET) (Gnd))
			((RST) (PRLD))
			((O) (\U1/U4/HE0stater \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U4/HE0stater_MC.REG_tsimcreated_inv_Mclk_II/FCLK_85 \ 0 4705 (_entity .  X_INV)
		(_port
			((I) (\Mclk_II/FCLK \))
			((O) (\U1/U4/HE0stater_MC.REG_tsimcreated_inv_Mclk_II/FCLK \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \AD<5>.PAD \ 0 4709 (_entity .  X_BPAD)
		(_port
			((PAD) (AD(5)))
		)
		(_strength strong0 strong1)
	)
	(_instantiation AD<5> 0 4712 (_entity .  X_TRI)
		(_port
			((I) (\AD<5>_MC.Q \))
			((CTL) (\AD<5>_MC.OE \))
			((O) (AD(5)))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \AD<6>.PAD \ 0 4717 (_entity .  X_BPAD)
		(_port
			((PAD) (AD(6)))
		)
		(_strength strong0 strong1)
	)
	(_instantiation AD<6> 0 4720 (_entity .  X_TRI)
		(_port
			((I) (\AD<6>_MC.Q \))
			((CTL) (\AD<6>_MC.OE \))
			((O) (AD(6)))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \AD<7>.PAD \ 0 4725 (_entity .  X_BPAD)
		(_port
			((PAD) (AD(7)))
		)
		(_strength strong0 strong1)
	)
	(_instantiation AD<7> 0 4728 (_entity .  X_TRI)
		(_port
			((I) (\AD<7>_MC.Q \))
			((CTL) (\AD<7>_MC.OE \))
			((O) (AD(7)))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \Enc033ctrl.PAD \ 0 4733 (_entity .  X_OPAD)
		(_port
			((PAD) (Enc033ctrl))
		)
		(_strength strong0 strong1)
	)
	(_instantiation Enc033ctrl_86 0 4736 (_entity .  X_BUF)
		(_port
			((I) (\Enc033ctrl_MC.Q \))
			((O) (Enc033ctrl))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \Enc05ctrl.PAD \ 0 4740 (_entity .  X_OPAD)
		(_port
			((PAD) (Enc05ctrl))
		)
		(_strength strong0 strong1)
	)
	(_instantiation Enc05ctrl_87 0 4743 (_entity .  X_BUF)
		(_port
			((I) (\Enc05ctrl_MC.Q \))
			((O) (Enc05ctrl))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \Enc133ctrl.PAD \ 0 4747 (_entity .  X_OPAD)
		(_port
			((PAD) (Enc133ctrl))
		)
		(_strength strong0 strong1)
	)
	(_instantiation Enc133ctrl_88 0 4750 (_entity .  X_BUF)
		(_port
			((I) (\Enc133ctrl_MC.Q \))
			((O) (Enc133ctrl))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \Enc15ctrl.PAD \ 0 4754 (_entity .  X_OPAD)
		(_port
			((PAD) (Enc15ctrl))
		)
		(_strength strong0 strong1)
	)
	(_instantiation Enc15ctrl_89 0 4757 (_entity .  X_BUF)
		(_port
			((I) (\Enc15ctrl_MC.Q \))
			((O) (Enc15ctrl))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \GP_Motor0_1.PAD \ 0 4761 (_entity .  X_OPAD)
		(_port
			((PAD) (GP_Motor0_1))
		)
		(_strength strong0 strong1)
	)
	(_instantiation GP_Motor0_1_90 0 4764 (_entity .  X_BUF)
		(_port
			((I) (\GP_Motor0_1_MC.Q \))
			((O) (GP_Motor0_1))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \GP_Motor1_1.PAD \ 0 4768 (_entity .  X_OPAD)
		(_port
			((PAD) (GP_Motor1_1))
		)
		(_strength strong0 strong1)
	)
	(_instantiation GP_Motor1_1_91 0 4771 (_entity .  X_BUF)
		(_port
			((I) (\GP_Motor1_1_MC.Q \))
			((O) (GP_Motor1_1))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \HSO.PAD \ 0 4775 (_entity .  X_OPAD)
		(_port
			((PAD) (HSO))
		)
		(_strength strong0 strong1)
	)
	(_instantiation HSO_92 0 4778 (_entity .  X_BUF)
		(_port
			((I) (\HSO_MC.Q \))
			((O) (HSO))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \Home033ctrl.PAD \ 0 4782 (_entity .  X_OPAD)
		(_port
			((PAD) (Home033ctrl))
		)
		(_strength strong0 strong1)
	)
	(_instantiation Home033ctrl_93 0 4785 (_entity .  X_BUF)
		(_port
			((I) (\Home033ctrl_MC.Q \))
			((O) (Home033ctrl))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \Home05ctrl.PAD \ 0 4789 (_entity .  X_OPAD)
		(_port
			((PAD) (Home05ctrl))
		)
		(_strength strong0 strong1)
	)
	(_instantiation Home05ctrl_94 0 4792 (_entity .  X_BUF)
		(_port
			((I) (\Home05ctrl_MC.Q \))
			((O) (Home05ctrl))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \Home133ctrl.PAD \ 0 4796 (_entity .  X_OPAD)
		(_port
			((PAD) (Home133ctrl))
		)
		(_strength strong0 strong1)
	)
	(_instantiation Home133ctrl_95 0 4799 (_entity .  X_BUF)
		(_port
			((I) (\Home133ctrl_MC.Q \))
			((O) (Home133ctrl))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \Home15ctrl.PAD \ 0 4803 (_entity .  X_OPAD)
		(_port
			((PAD) (Home15ctrl))
		)
		(_strength strong0 strong1)
	)
	(_instantiation Home15ctrl_96 0 4806 (_entity .  X_BUF)
		(_port
			((I) (\Home15ctrl_MC.Q \))
			((O) (Home15ctrl))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \INT.PAD \ 0 4810 (_entity .  X_OPAD)
		(_port
			((PAD) (INT))
		)
		(_strength strong0 strong1)
	)
	(_instantiation INT_97 0 4813 (_entity .  X_BUF)
		(_port
			((I) (\INT_MC.Q \))
			((O) (INT))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \LED1.PAD \ 0 4817 (_entity .  X_OPAD)
		(_port
			((PAD) (LED1))
		)
		(_strength strong0 strong1)
	)
	(_instantiation LED1_98 0 4820 (_entity .  X_BUF)
		(_port
			((I) (\LED1_MC.Q \))
			((O) (LED1))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \LED2.PAD \ 0 4824 (_entity .  X_OPAD)
		(_port
			((PAD) (LED2))
		)
		(_strength strong0 strong1)
	)
	(_instantiation LED2_99 0 4827 (_entity .  X_BUF)
		(_port
			((I) (\LED2_MC.Q \))
			((O) (LED2))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \LED3.PAD \ 0 4831 (_entity .  X_OPAD)
		(_port
			((PAD) (LED3))
		)
		(_strength strong0 strong1)
	)
	(_instantiation LED3_100 0 4834 (_entity .  X_BUF)
		(_port
			((I) (\LED3_MC.Q \))
			((O) (LED3))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \LED4.PAD \ 0 4838 (_entity .  X_OPAD)
		(_port
			((PAD) (LED4))
		)
		(_strength strong0 strong1)
	)
	(_instantiation LED4_101 0 4841 (_entity .  X_BUF)
		(_port
			((I) (\LED4_MC.Q \))
			((O) (LED4))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \LED5.PAD \ 0 4845 (_entity .  X_OPAD)
		(_port
			((PAD) (LED5))
		)
		(_strength strong0 strong1)
	)
	(_instantiation LED5_102 0 4848 (_entity .  X_BUF)
		(_port
			((I) (\LED5_MC.Q \))
			((O) (LED5))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \MHSI.PAD \ 0 4852 (_entity .  X_OPAD)
		(_port
			((PAD) (MHSI))
		)
		(_strength strong0 strong1)
	)
	(_instantiation MHSI_103 0 4855 (_entity .  X_BUF)
		(_port
			((I) (\MHSI_MC.Q \))
			((O) (MHSI))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \MTRpwr.PAD \ 0 4859 (_entity .  X_OPAD)
		(_port
			((PAD) (MTRpwr))
		)
		(_strength strong0 strong1)
	)
	(_instantiation MTRpwr_104 0 4862 (_entity .  X_BUF)
		(_port
			((I) (\MTRpwr_MC.Q \))
			((O) (MTRpwr))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \MTRpwrn.PAD \ 0 4866 (_entity .  X_OPAD)
		(_port
			((PAD) (MTRpwrn))
		)
		(_strength strong0 strong1)
	)
	(_instantiation MTRpwrn_105 0 4869 (_entity .  X_BUF)
		(_port
			((I) (\MTRpwrn_MC.Q \))
			((O) (MTRpwrn))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \MTXI.PAD \ 0 4873 (_entity .  X_OPAD)
		(_port
			((PAD) (MTXI))
		)
		(_strength strong0 strong1)
	)
	(_instantiation MTXI_106 0 4876 (_entity .  X_BUF)
		(_port
			((I) (\MTXI_MC.Q \))
			((O) (MTXI))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \PAH0.PAD \ 0 4880 (_entity .  X_OPAD)
		(_port
			((PAD) (PAH0))
		)
		(_strength strong0 strong1)
	)
	(_instantiation PAH0_107 0 4883 (_entity .  X_BUF)
		(_port
			((I) (\PAH0_MC.Q \))
			((O) (PAH0))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \PAH1.PAD \ 0 4887 (_entity .  X_OPAD)
		(_port
			((PAD) (PAH1))
		)
		(_strength strong0 strong1)
	)
	(_instantiation PAH1_108 0 4890 (_entity .  X_BUF)
		(_port
			((I) (\PAH1_MC.Q \))
			((O) (PAH1))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \PAL0.PAD \ 0 4894 (_entity .  X_OPAD)
		(_port
			((PAD) (PAL0))
		)
		(_strength strong0 strong1)
	)
	(_instantiation PAL0_109 0 4897 (_entity .  X_BUF)
		(_port
			((I) (\PAL0_MC.Q \))
			((O) (PAL0))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \PAL1.PAD \ 0 4901 (_entity .  X_OPAD)
		(_port
			((PAD) (PAL1))
		)
		(_strength strong0 strong1)
	)
	(_instantiation PAL1_110 0 4904 (_entity .  X_BUF)
		(_port
			((I) (\PAL1_MC.Q \))
			((O) (PAL1))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \PBH0.PAD \ 0 4908 (_entity .  X_OPAD)
		(_port
			((PAD) (PBH0))
		)
		(_strength strong0 strong1)
	)
	(_instantiation PBH0_111 0 4911 (_entity .  X_BUF)
		(_port
			((I) (\PBH0_MC.Q \))
			((O) (PBH0))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \PBH1.PAD \ 0 4915 (_entity .  X_OPAD)
		(_port
			((PAD) (PBH1))
		)
		(_strength strong0 strong1)
	)
	(_instantiation PBH1_112 0 4918 (_entity .  X_BUF)
		(_port
			((I) (\PBH1_MC.Q \))
			((O) (PBH1))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \PBL0.PAD \ 0 4922 (_entity .  X_OPAD)
		(_port
			((PAD) (PBL0))
		)
		(_strength strong0 strong1)
	)
	(_instantiation PBL0_113 0 4925 (_entity .  X_BUF)
		(_port
			((I) (\PBL0_MC.Q \))
			((O) (PBL0))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \PBL1.PAD \ 0 4929 (_entity .  X_OPAD)
		(_port
			((PAD) (PBL1))
		)
		(_strength strong0 strong1)
	)
	(_instantiation PBL1_114 0 4932 (_entity .  X_BUF)
		(_port
			((I) (\PBL1_MC.Q \))
			((O) (PBL1))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \SCL.PAD \ 0 4936 (_entity .  X_BPAD)
		(_port
			((PAD) (SCL))
		)
		(_strength strong0 strong1)
	)
	(_instantiation SCL_115 0 4939 (_entity .  X_TRI)
		(_port
			((I) (\U11_U2/Line_last_MC.Q \))
			((CTL) (\U11_U2/Line_last_MC.OE \))
			((O) (SCL))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \AD<0>.PAD \ 0 4944 (_entity .  X_BPAD)
		(_port
			((PAD) (AD(0)))
		)
		(_strength strong0 strong1)
	)
	(_instantiation AD<0> 0 4947 (_entity .  X_TRI)
		(_port
			((I) (\U9/MISCr<0>_MC.Q \))
			((CTL) (\U9/MISCr<0>_MC.OE \))
			((O) (AD(0)))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \AD<1>.PAD \ 0 4952 (_entity .  X_BPAD)
		(_port
			((PAD) (AD(1)))
		)
		(_strength strong0 strong1)
	)
	(_instantiation AD<1> 0 4955 (_entity .  X_TRI)
		(_port
			((I) (\U9/MISCr<1>_MC.Q \))
			((CTL) (\U9/MISCr<1>_MC.OE \))
			((O) (AD(1)))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \AD<2>.PAD \ 0 4960 (_entity .  X_BPAD)
		(_port
			((PAD) (AD(2)))
		)
		(_strength strong0 strong1)
	)
	(_instantiation AD<2> 0 4963 (_entity .  X_TRI)
		(_port
			((I) (\U9/MISCr<2>_MC.Q \))
			((CTL) (\U9/MISCr<2>_MC.OE \))
			((O) (AD(2)))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \AD<3>.PAD \ 0 4968 (_entity .  X_BPAD)
		(_port
			((PAD) (AD(3)))
		)
		(_strength strong0 strong1)
	)
	(_instantiation AD<3> 0 4971 (_entity .  X_TRI)
		(_port
			((I) (\U9/MISCr<3>_MC.Q \))
			((CTL) (\U9/MISCr<3>_MC.OE \))
			((O) (AD(3)))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \AD<4>.PAD \ 0 4976 (_entity .  X_BPAD)
		(_port
			((PAD) (AD(4)))
		)
		(_strength strong0 strong1)
	)
	(_instantiation AD<4> 0 4979 (_entity .  X_TRI)
		(_port
			((I) (\U9/MISCr<4>_MC.Q \))
			((CTL) (\U9/MISCr<4>_MC.OE \))
			((O) (AD(4)))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \AD<5>_MC.Q_116 \ 0 4984 (_entity .  X_BUF)
		(_port
			((I) (\AD<5>_MC.Q_tsimrenamed_net_ \))
			((O) (\AD<5>_MC.Q \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \AD<5>_MC.OE_117 \ 0 4988 (_entity .  X_BUF)
		(_port
			((I) (\AD<5>_MC.BUFOE.OUT \))
			((O) (\AD<5>_MC.OE \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \AD<5>_MC.BUFOE.OUT_118 \ 0 4992 (_entity .  X_BUF)
		(_port
			((I) (\FOOBAR3__ctinst/7 \))
			((O) (\AD<5>_MC.BUFOE.OUT \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \AD<5>_MC.Q_tsimrenamed_net__119 \ 0 4996 (_entity .  X_BUF)
		(_port
			((I) (\AD<5>_MC.D \))
			((O) (\AD<5>_MC.Q_tsimrenamed_net_ \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \AD<5>_MC.D_120 \ 0 5000 (_entity .  X_XOR2)
		(_port
			((I0) (\NlwInverterSignal_AD<5>_MC.D/IN0 \))
			((I1) (\AD<5>_MC.D2 \))
			((O) (\AD<5>_MC.D \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \AD<5>_MC.D1_121 \ 0 5005 (_entity .  X_ZERO)
		(_port
			((O) (\AD<5>_MC.D1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \AD<5>_MC.D2_PT_0_122 \ 0 5008 (_entity .  X_AND2)
		(_port
			((I0) (\NlwInverterSignal_AD<5>_MC.D2_PT_0/IN0 \))
			((I1) (N_PZ_964))
			((O) (\AD<5>_MC.D2_PT_0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \AD<5>_MC.D2_PT_1_123 \ 0 5013 (_entity .  X_AND2)
		(_port
			((I0) (\NlwInverterSignal_AD<5>_MC.D2_PT_1/IN0 \))
			((I1) (N_PZ_1060))
			((O) (\AD<5>_MC.D2_PT_1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \AD<5>_MC.D2_PT_2_124 \ 0 5018 (_entity .  X_AND8)
		(_port
			((I0) (\WR_II/UIM \))
			((I1) (\NlwInverterSignal_AD<5>_MC.D2_PT_2/IN1 \))
			((I2) (U2_ADDR_reg(1)))
			((I3) (U2_ADDR_reg(0)))
			((I4) (N_PZ_931))
			((I5) (U2_ADDR_reg(2)))
			((I6) (U2_ADDR_reg(3)))
			((I7) (\NlwInverterSignal_AD<5>_MC.D2_PT_2/IN7 \))
			((O) (\AD<5>_MC.D2_PT_2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \AD<5>_MC.D2_PT_3_125 \ 0 5029 (_entity .  X_AND8)
		(_port
			((I0) (\WR_II/UIM \))
			((I1) (\NlwInverterSignal_AD<5>_MC.D2_PT_3/IN1 \))
			((I2) (U2_ADDR_reg(1)))
			((I3) (U2_ADDR_reg(0)))
			((I4) (N_PZ_931))
			((I5) (\NlwInverterSignal_AD<5>_MC.D2_PT_3/IN5 \))
			((I6) (\NlwInverterSignal_AD<5>_MC.D2_PT_3/IN6 \))
			((I7) (\NlwInverterSignal_AD<5>_MC.D2_PT_3/IN7 \))
			((O) (\AD<5>_MC.D2_PT_3 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \AD<5>_MC.D2_PT_4_126 \ 0 5040 (_entity .  X_AND8)
		(_port
			((I0) (\WR_II/UIM \))
			((I1) (\NlwInverterSignal_AD<5>_MC.D2_PT_4/IN1 \))
			((I2) (U2_ADDR_reg(1)))
			((I3) (\NlwInverterSignal_AD<5>_MC.D2_PT_4/IN3 \))
			((I4) (N_PZ_931))
			((I5) (U2_ADDR_reg(2)))
			((I6) (U2_ADDR_reg(3)))
			((I7) (\NlwInverterSignal_AD<5>_MC.D2_PT_4/IN7 \))
			((O) (\AD<5>_MC.D2_PT_4 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \AD<5>_MC.D2_PT_5_127 \ 0 5051 (_entity .  X_AND8)
		(_port
			((I0) (\WR_II/UIM \))
			((I1) (\NlwInverterSignal_AD<5>_MC.D2_PT_5/IN1 \))
			((I2) (\NlwInverterSignal_AD<5>_MC.D2_PT_5/IN2 \))
			((I3) (\NlwInverterSignal_AD<5>_MC.D2_PT_5/IN3 \))
			((I4) (N_PZ_931))
			((I5) (\NlwInverterSignal_AD<5>_MC.D2_PT_5/IN5 \))
			((I6) (\NlwInverterSignal_AD<5>_MC.D2_PT_5/IN6 \))
			((I7) (\NlwInverterSignal_AD<5>_MC.D2_PT_5/IN7 \))
			((O) (\AD<5>_MC.D2_PT_5 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \AD<5>_MC.D2_128 \ 0 5062 (_entity .  X_OR6)
		(_port
			((I0) (\AD<5>_MC.D2_PT_0 \))
			((I1) (\AD<5>_MC.D2_PT_1 \))
			((I2) (\AD<5>_MC.D2_PT_2 \))
			((I3) (\AD<5>_MC.D2_PT_3 \))
			((I4) (\AD<5>_MC.D2_PT_4 \))
			((I5) (\AD<5>_MC.D2_PT_5 \))
			((O) (\AD<5>_MC.D2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation U2_ADDR_reg<1> 0 5071 (_entity .  X_BUF)
		(_port
			((I) (\U2_ADDR_reg<1>_MC.Q \))
			((O) (U2_ADDR_reg(1)))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U2_ADDR_reg<1>_MC.REG \ 0 5075 (_entity .  X_FF)
		(_port
			((I) (\U2_ADDR_reg<1>_MC.D \))
			((CE) (Vcc))
			((CLK) (\Mclk_II/FCLK \))
			((SET) (Gnd))
			((RST) (PRLD))
			((O) (\U2_ADDR_reg<1>_MC.Q \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U2_ADDR_reg<1>_MC.D_129 \ 0 5083 (_entity .  X_XOR2)
		(_port
			((I0) (\U2_ADDR_reg<1>_MC.D1 \))
			((I1) (\U2_ADDR_reg<1>_MC.D2 \))
			((O) (\U2_ADDR_reg<1>_MC.D \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U2_ADDR_reg<1>_MC.D1_130 \ 0 5088 (_entity .  X_ZERO)
		(_port
			((O) (\U2_ADDR_reg<1>_MC.D1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U2_ADDR_reg<1>_MC.D2_PT_0_131 \ 0 5091 (_entity .  X_AND3)
		(_port
			((I0) (U2_ADDR_reg(1)))
			((I1) (\NlwInverterSignal_U2_ADDR_reg<1>_MC.D2_PT_0/IN1 \))
			((I2) (\NlwInverterSignal_U2_ADDR_reg<1>_MC.D2_PT_0/IN2 \))
			((O) (\U2_ADDR_reg<1>_MC.D2_PT_0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U2_ADDR_reg<1>_MC.D2_PT_1_132 \ 0 5097 (_entity .  X_AND3)
		(_port
			((I0) (N_PZ_947))
			((I1) (\NlwInverterSignal_U2_ADDR_reg<1>_MC.D2_PT_1/IN1 \))
			((I2) (\AD<1>_II/UIM \))
			((O) (\U2_ADDR_reg<1>_MC.D2_PT_1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U2_ADDR_reg<1>_MC.D2_PT_2_133 \ 0 5103 (_entity .  X_AND5)
		(_port
			((I0) (U2_ADDR_reg(1)))
			((I1) (\NlwInverterSignal_U2_ADDR_reg<1>_MC.D2_PT_2/IN1 \))
			((I2) (N_PZ_931))
			((I3) (N_PZ_989))
			((I4) (\NlwInverterSignal_U2_ADDR_reg<1>_MC.D2_PT_2/IN4 \))
			((O) (\U2_ADDR_reg<1>_MC.D2_PT_2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U2_ADDR_reg<1>_MC.D2_PT_3_134 \ 0 5111 (_entity .  X_AND5)
		(_port
			((I0) (\NlwInverterSignal_U2_ADDR_reg<1>_MC.D2_PT_3/IN0 \))
			((I1) (U2_ADDR_reg(0)))
			((I2) (N_PZ_931))
			((I3) (N_PZ_989))
			((I4) (\NlwInverterSignal_U2_ADDR_reg<1>_MC.D2_PT_3/IN4 \))
			((O) (\U2_ADDR_reg<1>_MC.D2_PT_3 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U2_ADDR_reg<1>_MC.D2_135 \ 0 5119 (_entity .  X_OR4)
		(_port
			((I0) (\U2_ADDR_reg<1>_MC.D2_PT_0 \))
			((I1) (\U2_ADDR_reg<1>_MC.D2_PT_1 \))
			((I2) (\U2_ADDR_reg<1>_MC.D2_PT_2 \))
			((I3) (\U2_ADDR_reg<1>_MC.D2_PT_3 \))
			((O) (\U2_ADDR_reg<1>_MC.D2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation U2_ADDR_reg<0> 0 5126 (_entity .  X_BUF)
		(_port
			((I) (\U2_ADDR_reg<0>_MC.Q \))
			((O) (U2_ADDR_reg(0)))
		)
		(_strength strong0 strong1)
	)
	(_instantiation U2_ADDR_reg<0>_MC_tsimcreated_xor__136 0 5130 (_entity .  X_XOR2)
		(_port
			((I0) (\U2_ADDR_reg<0>_MC.D \))
			((I1) (\U2_ADDR_reg<0>_MC.Q \))
			((O) (U2_ADDR_reg<0>_MC_tsimcreated_xor_))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U2_ADDR_reg<0>_MC.REG \ 0 5135 (_entity .  X_FF)
		(_port
			((I) (U2_ADDR_reg<0>_MC_tsimcreated_xor_))
			((CE) (Vcc))
			((CLK) (\Mclk_II/FCLK \))
			((SET) (Gnd))
			((RST) (PRLD))
			((O) (\U2_ADDR_reg<0>_MC.Q \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U2_ADDR_reg<0>_MC.D_137 \ 0 5143 (_entity .  X_XOR2)
		(_port
			((I0) (\U2_ADDR_reg<0>_MC.D1 \))
			((I1) (\U2_ADDR_reg<0>_MC.D2 \))
			((O) (\U2_ADDR_reg<0>_MC.D \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U2_ADDR_reg<0>_MC.D1_138 \ 0 5148 (_entity .  X_ZERO)
		(_port
			((O) (\U2_ADDR_reg<0>_MC.D1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U2_ADDR_reg<0>_MC.D2_PT_0_139 \ 0 5151 (_entity .  X_AND2)
		(_port
			((I0) (U2_ADDR_reg(0)))
			((I1) (N_PZ_989))
			((O) (\U2_ADDR_reg<0>_MC.D2_PT_0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U2_ADDR_reg<0>_MC.D2_PT_1_140 \ 0 5156 (_entity .  X_AND3)
		(_port
			((I0) (U2_ADDR_reg(0)))
			((I1) (N_PZ_947))
			((I2) (\NlwInverterSignal_U2_ADDR_reg<0>_MC.D2_PT_1/IN2 \))
			((O) (\U2_ADDR_reg<0>_MC.D2_PT_1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U2_ADDR_reg<0>_MC.D2_PT_2_141 \ 0 5162 (_entity .  X_AND4)
		(_port
			((I0) (\NlwInverterSignal_U2_ADDR_reg<0>_MC.D2_PT_2/IN0 \))
			((I1) (N_PZ_947))
			((I2) (\NlwInverterSignal_U2_ADDR_reg<0>_MC.D2_PT_2/IN2 \))
			((I3) (\AD<0>_II/UIM \))
			((O) (\U2_ADDR_reg<0>_MC.D2_PT_2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U2_ADDR_reg<0>_MC.D2_PT_3_142 \ 0 5169 (_entity .  X_AND7)
		(_port
			((I0) (\WR_II/UIM \))
			((I1) (\RD_II/UIM \))
			((I2) (N_PZ_931))
			((I3) (\NlwInverterSignal_U2_ADDR_reg<0>_MC.D2_PT_3/IN3 \))
			((I4) (\NlwInverterSignal_U2_ADDR_reg<0>_MC.D2_PT_3/IN4 \))
			((I5) (U2_AutoInc))
			((I6) (\NlwInverterSignal_U2_ADDR_reg<0>_MC.D2_PT_3/IN6 \))
			((O) (\U2_ADDR_reg<0>_MC.D2_PT_3 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U2_ADDR_reg<0>_MC.D2_143 \ 0 5179 (_entity .  X_OR4)
		(_port
			((I0) (\U2_ADDR_reg<0>_MC.D2_PT_0 \))
			((I1) (\U2_ADDR_reg<0>_MC.D2_PT_1 \))
			((I2) (\U2_ADDR_reg<0>_MC.D2_PT_2 \))
			((I3) (\U2_ADDR_reg<0>_MC.D2_PT_3 \))
			((O) (\U2_ADDR_reg<0>_MC.D2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation N_PZ_947_144 0 5186 (_entity .  X_BUF)
		(_port
			((I) (\N_PZ_947_MC.Q \))
			((O) (N_PZ_947))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \N_PZ_947_MC.Q_145 \ 0 5190 (_entity .  X_BUF)
		(_port
			((I) (\N_PZ_947_MC.D \))
			((O) (\N_PZ_947_MC.Q \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \N_PZ_947_MC.D_146 \ 0 5194 (_entity .  X_XOR2)
		(_port
			((I0) (\N_PZ_947_MC.D1 \))
			((I1) (\N_PZ_947_MC.D2 \))
			((O) (\N_PZ_947_MC.D \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \N_PZ_947_MC.D1_147 \ 0 5199 (_entity .  X_AND2)
		(_port
			((I0) (\NlwInverterSignal_N_PZ_947_MC.D1/IN0 \))
			((I1) (U2_ASedge))
			((O) (\N_PZ_947_MC.D1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \N_PZ_947_MC.D2_148 \ 0 5204 (_entity .  X_ZERO)
		(_port
			((O) (\N_PZ_947_MC.D2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation U2_AutoInc_149 0 5207 (_entity .  X_BUF)
		(_port
			((I) (\U2_AutoInc_MC.Q \))
			((O) (U2_AutoInc))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U2_AutoInc_MC.REG \ 0 5211 (_entity .  X_FF)
		(_port
			((I) (\U2_AutoInc_MC.D \))
			((CE) (\FOOBAR16__ctinst/4 \))
			((CLK) (\Mclk_II/FCLK \))
			((SET) (Gnd))
			((RST) (PRLD))
			((O) (\U2_AutoInc_MC.Q \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U2_AutoInc_MC.D_150 \ 0 5219 (_entity .  X_XOR2)
		(_port
			((I0) (\NlwInverterSignal_U2_AutoInc_MC.D/IN0 \))
			((I1) (\U2_AutoInc_MC.D2 \))
			((O) (\U2_AutoInc_MC.D \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U2_AutoInc_MC.D1_151 \ 0 5224 (_entity .  X_AND2)
		(_port
			((I0) (\AS_II/UIM \))
			((I1) (\AS_II/UIM \))
			((O) (\U2_AutoInc_MC.D1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U2_AutoInc_MC.D2_152 \ 0 5229 (_entity .  X_ZERO)
		(_port
			((O) (\U2_AutoInc_MC.D2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation U2_WRRDedge_153 0 5232 (_entity .  X_BUF)
		(_port
			((I) (\U2_WRRDedge_MC.Q \))
			((O) (U2_WRRDedge))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U2_WRRDedge_MC.REG \ 0 5236 (_entity .  X_FF)
		(_port
			((I) (\U2_WRRDedge_MC.D \))
			((CE) (Vcc))
			((CLK) (\Mclk_II/FCLK \))
			((SET) (Gnd))
			((RST) (PRLD))
			((O) (\U2_WRRDedge_MC.Q \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U2_WRRDedge_MC.D_154 \ 0 5244 (_entity .  X_XOR2)
		(_port
			((I0) (\U2_WRRDedge_MC.D1 \))
			((I1) (\U2_WRRDedge_MC.D2 \))
			((O) (\U2_WRRDedge_MC.D \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U2_WRRDedge_MC.D1_155 \ 0 5249 (_entity .  X_AND2)
		(_port
			((I0) (\WR_II/UIM \))
			((I1) (\RD_II/UIM \))
			((O) (\U2_WRRDedge_MC.D1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U2_WRRDedge_MC.D2_156 \ 0 5254 (_entity .  X_ZERO)
		(_port
			((O) (\U2_WRRDedge_MC.D2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation U2__n0017_157 0 5257 (_entity .  X_BUF)
		(_port
			((I) (\U2__n0017_MC.Q \))
			((O) (U2__n0017))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U2__n0017_MC.Q_158 \ 0 5261 (_entity .  X_BUF)
		(_port
			((I) (\U2__n0017_MC.D \))
			((O) (\U2__n0017_MC.Q \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U2__n0017_MC.D_159 \ 0 5265 (_entity .  X_XOR2)
		(_port
			((I0) (\U2__n0017_MC.D1 \))
			((I1) (\U2__n0017_MC.D2 \))
			((O) (\U2__n0017_MC.D \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U2__n0017_MC.D1_160 \ 0 5270 (_entity .  X_AND2)
		(_port
			((I0) (\NlwInverterSignal_U2__n0017_MC.D1/IN0 \))
			((I1) (\NlwInverterSignal_U2__n0017_MC.D1/IN1 \))
			((O) (\U2__n0017_MC.D1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U2__n0017_MC.D2_161 \ 0 5275 (_entity .  X_ZERO)
		(_port
			((O) (\U2__n0017_MC.D2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation N_PZ_931_162 0 5278 (_entity .  X_BUF)
		(_port
			((I) (\N_PZ_931_MC.Q \))
			((O) (N_PZ_931))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \N_PZ_931_MC.Q_163 \ 0 5282 (_entity .  X_BUF)
		(_port
			((I) (\N_PZ_931_MC.D \))
			((O) (\N_PZ_931_MC.Q \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \N_PZ_931_MC.D_164 \ 0 5286 (_entity .  X_XOR2)
		(_port
			((I0) (\N_PZ_931_MC.D1 \))
			((I1) (\N_PZ_931_MC.D2 \))
			((O) (\N_PZ_931_MC.D \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \N_PZ_931_MC.D1_165 \ 0 5291 (_entity .  X_AND4)
		(_port
			((I0) (\NlwInverterSignal_N_PZ_931_MC.D1/IN0 \))
			((I1) (\NlwInverterSignal_N_PZ_931_MC.D1/IN1 \))
			((I2) (\NlwInverterSignal_N_PZ_931_MC.D1/IN2 \))
			((I3) (\NlwInverterSignal_N_PZ_931_MC.D1/IN3 \))
			((O) (\N_PZ_931_MC.D1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \N_PZ_931_MC.D2_166 \ 0 5298 (_entity .  X_ZERO)
		(_port
			((O) (\N_PZ_931_MC.D2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation U2_ADDR_reg<4> 0 5301 (_entity .  X_BUF)
		(_port
			((I) (\U2_ADDR_reg<4>_MC.Q \))
			((O) (U2_ADDR_reg(4)))
		)
		(_strength strong0 strong1)
	)
	(_instantiation U2_ADDR_reg<4>_MC_tsimcreated_xor__167 0 5305 (_entity .  X_XOR2)
		(_port
			((I0) (\U2_ADDR_reg<4>_MC.D \))
			((I1) (\U2_ADDR_reg<4>_MC.Q \))
			((O) (U2_ADDR_reg<4>_MC_tsimcreated_xor_))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U2_ADDR_reg<4>_MC.REG \ 0 5310 (_entity .  X_FF)
		(_port
			((I) (U2_ADDR_reg<4>_MC_tsimcreated_xor_))
			((CE) (Vcc))
			((CLK) (\Mclk_II/FCLK \))
			((SET) (Gnd))
			((RST) (PRLD))
			((O) (\U2_ADDR_reg<4>_MC.Q \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U2_ADDR_reg<4>_MC.D_168 \ 0 5318 (_entity .  X_XOR2)
		(_port
			((I0) (\U2_ADDR_reg<4>_MC.D1 \))
			((I1) (\U2_ADDR_reg<4>_MC.D2 \))
			((O) (\U2_ADDR_reg<4>_MC.D \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U2_ADDR_reg<4>_MC.D1_169 \ 0 5323 (_entity .  X_ZERO)
		(_port
			((O) (\U2_ADDR_reg<4>_MC.D1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U2_ADDR_reg<4>_MC.D2_PT_0_170 \ 0 5326 (_entity .  X_AND2)
		(_port
			((I0) (N_PZ_989))
			((I1) (U2_ADDR_reg(4)))
			((O) (\U2_ADDR_reg<4>_MC.D2_PT_0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U2_ADDR_reg<4>_MC.D2_PT_1_171 \ 0 5331 (_entity .  X_AND3)
		(_port
			((I0) (N_PZ_947))
			((I1) (U2_ADDR_reg(4)))
			((I2) (\NlwInverterSignal_U2_ADDR_reg<4>_MC.D2_PT_1/IN2 \))
			((O) (\U2_ADDR_reg<4>_MC.D2_PT_1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U2_ADDR_reg<4>_MC.D2_PT_2_172 \ 0 5337 (_entity .  X_AND4)
		(_port
			((I0) (N_PZ_947))
			((I1) (\NlwInverterSignal_U2_ADDR_reg<4>_MC.D2_PT_2/IN1 \))
			((I2) (\NlwInverterSignal_U2_ADDR_reg<4>_MC.D2_PT_2/IN2 \))
			((I3) (\AD<4>_II/UIM \))
			((O) (\U2_ADDR_reg<4>_MC.D2_PT_2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U2_ADDR_reg<4>_MC.D2_PT_3_173 \ 0 5344 (_entity .  X_AND16)
		(_port
			((I0) (\WR_II/UIM \))
			((I1) (\RD_II/UIM \))
			((I2) (U2_ADDR_reg(1)))
			((I3) (U2_ADDR_reg(0)))
			((I4) (U2_ADDR_reg(2)))
			((I5) (U2_ADDR_reg(3)))
			((I6) (\NlwInverterSignal_U2_ADDR_reg<4>_MC.D2_PT_3/IN6 \))
			((I7) (\NlwInverterSignal_U2_ADDR_reg<4>_MC.D2_PT_3/IN7 \))
			((I8) (U2_AutoInc))
			((I9) (\NlwInverterSignal_U2_ADDR_reg<4>_MC.D2_PT_3/IN9 \))
			((I10) (\NlwInverterSignal_U2_ADDR_reg<4>_MC.D2_PT_3/IN10 \))
			((I11) (\NlwInverterSignal_U2_ADDR_reg<4>_MC.D2_PT_3/IN11 \))
			((I12) (\NlwInverterSignal_U2_ADDR_reg<4>_MC.D2_PT_3/IN12 \))
			((I13) (Vcc))
			((I14) (Vcc))
			((I15) (Vcc))
			((O) (\U2_ADDR_reg<4>_MC.D2_PT_3 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U2_ADDR_reg<4>_MC.D2_174 \ 0 5363 (_entity .  X_OR4)
		(_port
			((I0) (\U2_ADDR_reg<4>_MC.D2_PT_0 \))
			((I1) (\U2_ADDR_reg<4>_MC.D2_PT_1 \))
			((I2) (\U2_ADDR_reg<4>_MC.D2_PT_2 \))
			((I3) (\U2_ADDR_reg<4>_MC.D2_PT_3 \))
			((O) (\U2_ADDR_reg<4>_MC.D2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation U2_ADDR_reg<2> 0 5370 (_entity .  X_BUF)
		(_port
			((I) (\U2_ADDR_reg<2>_MC.Q \))
			((O) (U2_ADDR_reg(2)))
		)
		(_strength strong0 strong1)
	)
	(_instantiation U2_ADDR_reg<2>_MC_tsimcreated_xor__175 0 5374 (_entity .  X_XOR2)
		(_port
			((I0) (\U2_ADDR_reg<2>_MC.D \))
			((I1) (\U2_ADDR_reg<2>_MC.Q \))
			((O) (U2_ADDR_reg<2>_MC_tsimcreated_xor_))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U2_ADDR_reg<2>_MC.REG \ 0 5379 (_entity .  X_FF)
		(_port
			((I) (U2_ADDR_reg<2>_MC_tsimcreated_xor_))
			((CE) (Vcc))
			((CLK) (\Mclk_II/FCLK \))
			((SET) (Gnd))
			((RST) (PRLD))
			((O) (\U2_ADDR_reg<2>_MC.Q \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U2_ADDR_reg<2>_MC.D_176 \ 0 5387 (_entity .  X_XOR2)
		(_port
			((I0) (\U2_ADDR_reg<2>_MC.D1 \))
			((I1) (\U2_ADDR_reg<2>_MC.D2 \))
			((O) (\U2_ADDR_reg<2>_MC.D \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U2_ADDR_reg<2>_MC.D1_177 \ 0 5392 (_entity .  X_ZERO)
		(_port
			((O) (\U2_ADDR_reg<2>_MC.D1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U2_ADDR_reg<2>_MC.D2_PT_0_178 \ 0 5395 (_entity .  X_AND2)
		(_port
			((I0) (U2_ADDR_reg(2)))
			((I1) (\Reset_II/UIM \))
			((O) (\U2_ADDR_reg<2>_MC.D2_PT_0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U2_ADDR_reg<2>_MC.D2_PT_1_179 \ 0 5400 (_entity .  X_AND3)
		(_port
			((I0) (U2_ADDR_reg(2)))
			((I1) (N_PZ_947))
			((I2) (\NlwInverterSignal_U2_ADDR_reg<2>_MC.D2_PT_1/IN2 \))
			((O) (\U2_ADDR_reg<2>_MC.D2_PT_1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U2_ADDR_reg<2>_MC.D2_PT_2_180 \ 0 5406 (_entity .  X_AND4)
		(_port
			((I0) (\NlwInverterSignal_U2_ADDR_reg<2>_MC.D2_PT_2/IN0 \))
			((I1) (N_PZ_947))
			((I2) (\NlwInverterSignal_U2_ADDR_reg<2>_MC.D2_PT_2/IN2 \))
			((I3) (\AD<2>_II/UIM \))
			((O) (\U2_ADDR_reg<2>_MC.D2_PT_2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U2_ADDR_reg<2>_MC.D2_PT_3_181 \ 0 5413 (_entity .  X_AND7)
		(_port
			((I0) (\WR_II/UIM \))
			((I1) (\RD_II/UIM \))
			((I2) (\NlwInverterSignal_U2_ADDR_reg<2>_MC.D2_PT_3/IN2 \))
			((I3) (U2_ADDR_reg(2)))
			((I4) (\NlwInverterSignal_U2_ADDR_reg<2>_MC.D2_PT_3/IN4 \))
			((I5) (U2_AutoInc))
			((I6) (\NlwInverterSignal_U2_ADDR_reg<2>_MC.D2_PT_3/IN6 \))
			((O) (\U2_ADDR_reg<2>_MC.D2_PT_3 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U2_ADDR_reg<2>_MC.D2_PT_4_182 \ 0 5423 (_entity .  X_AND16)
		(_port
			((I0) (\WR_II/UIM \))
			((I1) (\RD_II/UIM \))
			((I2) (U2_ADDR_reg(1)))
			((I3) (U2_ADDR_reg(0)))
			((I4) (N_PZ_931))
			((I5) (\NlwInverterSignal_U2_ADDR_reg<2>_MC.D2_PT_4/IN5 \))
			((I6) (\NlwInverterSignal_U2_ADDR_reg<2>_MC.D2_PT_4/IN6 \))
			((I7) (U2_AutoInc))
			((I8) (\NlwInverterSignal_U2_ADDR_reg<2>_MC.D2_PT_4/IN8 \))
			((I9) (Vcc))
			((I10) (Vcc))
			((I11) (Vcc))
			((I12) (Vcc))
			((I13) (Vcc))
			((I14) (Vcc))
			((I15) (Vcc))
			((O) (\U2_ADDR_reg<2>_MC.D2_PT_4 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U2_ADDR_reg<2>_MC.D2_183 \ 0 5442 (_entity .  X_OR5)
		(_port
			((I0) (\U2_ADDR_reg<2>_MC.D2_PT_0 \))
			((I1) (\U2_ADDR_reg<2>_MC.D2_PT_1 \))
			((I2) (\U2_ADDR_reg<2>_MC.D2_PT_2 \))
			((I3) (\U2_ADDR_reg<2>_MC.D2_PT_3 \))
			((I4) (\U2_ADDR_reg<2>_MC.D2_PT_4 \))
			((O) (\U2_ADDR_reg<2>_MC.D2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation U2_ADDR_reg<3> 0 5450 (_entity .  X_BUF)
		(_port
			((I) (\U2_ADDR_reg<3>_MC.Q \))
			((O) (U2_ADDR_reg(3)))
		)
		(_strength strong0 strong1)
	)
	(_instantiation U2_ADDR_reg<3>_MC_tsimcreated_xor__184 0 5454 (_entity .  X_XOR2)
		(_port
			((I0) (\U2_ADDR_reg<3>_MC.D \))
			((I1) (\U2_ADDR_reg<3>_MC.Q \))
			((O) (U2_ADDR_reg<3>_MC_tsimcreated_xor_))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U2_ADDR_reg<3>_MC.REG \ 0 5459 (_entity .  X_FF)
		(_port
			((I) (U2_ADDR_reg<3>_MC_tsimcreated_xor_))
			((CE) (Vcc))
			((CLK) (\Mclk_II/FCLK \))
			((SET) (Gnd))
			((RST) (PRLD))
			((O) (\U2_ADDR_reg<3>_MC.Q \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U2_ADDR_reg<3>_MC.D_185 \ 0 5467 (_entity .  X_XOR2)
		(_port
			((I0) (\U2_ADDR_reg<3>_MC.D1 \))
			((I1) (\U2_ADDR_reg<3>_MC.D2 \))
			((O) (\U2_ADDR_reg<3>_MC.D \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U2_ADDR_reg<3>_MC.D1_186 \ 0 5472 (_entity .  X_ZERO)
		(_port
			((O) (\U2_ADDR_reg<3>_MC.D1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U2_ADDR_reg<3>_MC.D2_PT_0_187 \ 0 5475 (_entity .  X_AND2)
		(_port
			((I0) (U2_ADDR_reg(3)))
			((I1) (\Reset_II/UIM \))
			((O) (\U2_ADDR_reg<3>_MC.D2_PT_0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U2_ADDR_reg<3>_MC.D2_PT_1_188 \ 0 5480 (_entity .  X_AND3)
		(_port
			((I0) (U2_ADDR_reg(3)))
			((I1) (N_PZ_947))
			((I2) (\NlwInverterSignal_U2_ADDR_reg<3>_MC.D2_PT_1/IN2 \))
			((O) (\U2_ADDR_reg<3>_MC.D2_PT_1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U2_ADDR_reg<3>_MC.D2_PT_2_189 \ 0 5486 (_entity .  X_AND4)
		(_port
			((I0) (\NlwInverterSignal_U2_ADDR_reg<3>_MC.D2_PT_2/IN0 \))
			((I1) (N_PZ_947))
			((I2) (\NlwInverterSignal_U2_ADDR_reg<3>_MC.D2_PT_2/IN2 \))
			((I3) (\AD<3>_II/UIM \))
			((O) (\U2_ADDR_reg<3>_MC.D2_PT_2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U2_ADDR_reg<3>_MC.D2_PT_3_190 \ 0 5493 (_entity .  X_AND7)
		(_port
			((I0) (\WR_II/UIM \))
			((I1) (\RD_II/UIM \))
			((I2) (\NlwInverterSignal_U2_ADDR_reg<3>_MC.D2_PT_3/IN2 \))
			((I3) (U2_ADDR_reg(3)))
			((I4) (\NlwInverterSignal_U2_ADDR_reg<3>_MC.D2_PT_3/IN4 \))
			((I5) (U2_AutoInc))
			((I6) (\NlwInverterSignal_U2_ADDR_reg<3>_MC.D2_PT_3/IN6 \))
			((O) (\U2_ADDR_reg<3>_MC.D2_PT_3 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U2_ADDR_reg<3>_MC.D2_PT_4_191 \ 0 5503 (_entity .  X_AND16)
		(_port
			((I0) (\WR_II/UIM \))
			((I1) (\RD_II/UIM \))
			((I2) (U2_ADDR_reg(1)))
			((I3) (U2_ADDR_reg(0)))
			((I4) (N_PZ_931))
			((I5) (U2_ADDR_reg(2)))
			((I6) (\NlwInverterSignal_U2_ADDR_reg<3>_MC.D2_PT_4/IN6 \))
			((I7) (\NlwInverterSignal_U2_ADDR_reg<3>_MC.D2_PT_4/IN7 \))
			((I8) (U2_AutoInc))
			((I9) (\NlwInverterSignal_U2_ADDR_reg<3>_MC.D2_PT_4/IN9 \))
			((I10) (Vcc))
			((I11) (Vcc))
			((I12) (Vcc))
			((I13) (Vcc))
			((I14) (Vcc))
			((I15) (Vcc))
			((O) (\U2_ADDR_reg<3>_MC.D2_PT_4 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U2_ADDR_reg<3>_MC.D2_192 \ 0 5522 (_entity .  X_OR5)
		(_port
			((I0) (\U2_ADDR_reg<3>_MC.D2_PT_0 \))
			((I1) (\U2_ADDR_reg<3>_MC.D2_PT_1 \))
			((I2) (\U2_ADDR_reg<3>_MC.D2_PT_2 \))
			((I3) (\U2_ADDR_reg<3>_MC.D2_PT_3 \))
			((I4) (\U2_ADDR_reg<3>_MC.D2_PT_4 \))
			((O) (\U2_ADDR_reg<3>_MC.D2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation U2_ADDR_reg<5> 0 5530 (_entity .  X_BUF)
		(_port
			((I) (\U2_ADDR_reg<5>_MC.Q \))
			((O) (U2_ADDR_reg(5)))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U2_ADDR_reg<5>_MC.REG \ 0 5534 (_entity .  X_FF)
		(_port
			((I) (\U2_ADDR_reg<5>_MC.D \))
			((CE) (Vcc))
			((CLK) (\Mclk_II/FCLK \))
			((SET) (Gnd))
			((RST) (PRLD))
			((O) (\U2_ADDR_reg<5>_MC.Q \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U2_ADDR_reg<5>_MC.D_193 \ 0 5542 (_entity .  X_XOR2)
		(_port
			((I0) (\U2_ADDR_reg<5>_MC.D1 \))
			((I1) (\U2_ADDR_reg<5>_MC.D2 \))
			((O) (\U2_ADDR_reg<5>_MC.D \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U2_ADDR_reg<5>_MC.D1_194 \ 0 5547 (_entity .  X_ZERO)
		(_port
			((O) (\U2_ADDR_reg<5>_MC.D1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U2_ADDR_reg<5>_MC.D2_PT_0_195 \ 0 5550 (_entity .  X_AND3)
		(_port
			((I0) (N_PZ_947))
			((I1) (\NlwInverterSignal_U2_ADDR_reg<5>_MC.D2_PT_0/IN1 \))
			((I2) (\AD<5>_II/UIM \))
			((O) (\U2_ADDR_reg<5>_MC.D2_PT_0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U2_ADDR_reg<5>_MC.D2_PT_1_196 \ 0 5556 (_entity .  X_AND3)
		(_port
			((I0) (\NlwInverterSignal_U2_ADDR_reg<5>_MC.D2_PT_1/IN0 \))
			((I1) (\NlwInverterSignal_U2_ADDR_reg<5>_MC.D2_PT_1/IN1 \))
			((I2) (U2_ADDR_reg(5)))
			((O) (\U2_ADDR_reg<5>_MC.D2_PT_1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U2_ADDR_reg<5>_MC.D2_197 \ 0 5562 (_entity .  X_OR2)
		(_port
			((I0) (\U2_ADDR_reg<5>_MC.D2_PT_0 \))
			((I1) (\U2_ADDR_reg<5>_MC.D2_PT_1 \))
			((O) (\U2_ADDR_reg<5>_MC.D2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation N_PZ_989_198 0 5567 (_entity .  X_BUF)
		(_port
			((I) (\N_PZ_989_MC.Q \))
			((O) (N_PZ_989))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \N_PZ_989_MC.Q_199 \ 0 5571 (_entity .  X_BUF)
		(_port
			((I) (\N_PZ_989_MC.D \))
			((O) (\N_PZ_989_MC.Q \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \N_PZ_989_MC.D_200 \ 0 5575 (_entity .  X_XOR2)
		(_port
			((I0) (\N_PZ_989_MC.D1 \))
			((I1) (\N_PZ_989_MC.D2 \))
			((O) (\N_PZ_989_MC.D \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \N_PZ_989_MC.D1_201 \ 0 5580 (_entity .  X_ZERO)
		(_port
			((O) (\N_PZ_989_MC.D1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \N_PZ_989_MC.D2_PT_0_202 \ 0 5583 (_entity .  X_AND2)
		(_port
			((I0) (\Reset_II/UIM \))
			((I1) (\Reset_II/UIM \))
			((O) (\N_PZ_989_MC.D2_PT_0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \N_PZ_989_MC.D2_PT_1_203 \ 0 5588 (_entity .  X_AND5)
		(_port
			((I0) (\WR_II/UIM \))
			((I1) (\RD_II/UIM \))
			((I2) (\NlwInverterSignal_N_PZ_989_MC.D2_PT_1/IN2 \))
			((I3) (U2_AutoInc))
			((I4) (\NlwInverterSignal_N_PZ_989_MC.D2_PT_1/IN4 \))
			((O) (\N_PZ_989_MC.D2_PT_1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \N_PZ_989_MC.D2_204 \ 0 5596 (_entity .  X_OR2)
		(_port
			((I0) (\N_PZ_989_MC.D2_PT_0 \))
			((I1) (\N_PZ_989_MC.D2_PT_1 \))
			((O) (\N_PZ_989_MC.D2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation U2_ADDR_reg<6> 0 5601 (_entity .  X_BUF)
		(_port
			((I) (\U2_ADDR_reg<6>_MC.Q \))
			((O) (U2_ADDR_reg(6)))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U2_ADDR_reg<6>_MC.REG \ 0 5605 (_entity .  X_FF)
		(_port
			((I) (\U2_ADDR_reg<6>_MC.D \))
			((CE) (Vcc))
			((CLK) (\Mclk_II/FCLK \))
			((SET) (Gnd))
			((RST) (PRLD))
			((O) (\U2_ADDR_reg<6>_MC.Q \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U2_ADDR_reg<6>_MC.D_205 \ 0 5613 (_entity .  X_XOR2)
		(_port
			((I0) (\U2_ADDR_reg<6>_MC.D1 \))
			((I1) (\U2_ADDR_reg<6>_MC.D2 \))
			((O) (\U2_ADDR_reg<6>_MC.D \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U2_ADDR_reg<6>_MC.D1_206 \ 0 5618 (_entity .  X_ZERO)
		(_port
			((O) (\U2_ADDR_reg<6>_MC.D1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U2_ADDR_reg<6>_MC.D2_PT_0_207 \ 0 5621 (_entity .  X_AND3)
		(_port
			((I0) (N_PZ_947))
			((I1) (\NlwInverterSignal_U2_ADDR_reg<6>_MC.D2_PT_0/IN1 \))
			((I2) (\AD<6>_II/UIM \))
			((O) (\U2_ADDR_reg<6>_MC.D2_PT_0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U2_ADDR_reg<6>_MC.D2_PT_1_208 \ 0 5627 (_entity .  X_AND3)
		(_port
			((I0) (\NlwInverterSignal_U2_ADDR_reg<6>_MC.D2_PT_1/IN0 \))
			((I1) (\NlwInverterSignal_U2_ADDR_reg<6>_MC.D2_PT_1/IN1 \))
			((I2) (U2_ADDR_reg(6)))
			((O) (\U2_ADDR_reg<6>_MC.D2_PT_1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U2_ADDR_reg<6>_MC.D2_209 \ 0 5633 (_entity .  X_OR2)
		(_port
			((I0) (\U2_ADDR_reg<6>_MC.D2_PT_0 \))
			((I1) (\U2_ADDR_reg<6>_MC.D2_PT_1 \))
			((O) (\U2_ADDR_reg<6>_MC.D2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation U2_ADDR_reg<7> 0 5638 (_entity .  X_BUF)
		(_port
			((I) (\U2_ADDR_reg<7>_MC.Q \))
			((O) (U2_ADDR_reg(7)))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U2_ADDR_reg<7>_MC.REG \ 0 5642 (_entity .  X_FF)
		(_port
			((I) (\U2_ADDR_reg<7>_MC.D \))
			((CE) (Vcc))
			((CLK) (\Mclk_II/FCLK \))
			((SET) (Gnd))
			((RST) (PRLD))
			((O) (\U2_ADDR_reg<7>_MC.Q \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U2_ADDR_reg<7>_MC.D_210 \ 0 5650 (_entity .  X_XOR2)
		(_port
			((I0) (\U2_ADDR_reg<7>_MC.D1 \))
			((I1) (\U2_ADDR_reg<7>_MC.D2 \))
			((O) (\U2_ADDR_reg<7>_MC.D \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U2_ADDR_reg<7>_MC.D1_211 \ 0 5655 (_entity .  X_ZERO)
		(_port
			((O) (\U2_ADDR_reg<7>_MC.D1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U2_ADDR_reg<7>_MC.D2_PT_0_212 \ 0 5658 (_entity .  X_AND3)
		(_port
			((I0) (N_PZ_947))
			((I1) (\NlwInverterSignal_U2_ADDR_reg<7>_MC.D2_PT_0/IN1 \))
			((I2) (\AD<7>_II/UIM \))
			((O) (\U2_ADDR_reg<7>_MC.D2_PT_0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U2_ADDR_reg<7>_MC.D2_PT_1_213 \ 0 5664 (_entity .  X_AND3)
		(_port
			((I0) (\NlwInverterSignal_U2_ADDR_reg<7>_MC.D2_PT_1/IN0 \))
			((I1) (\NlwInverterSignal_U2_ADDR_reg<7>_MC.D2_PT_1/IN1 \))
			((I2) (U2_ADDR_reg(7)))
			((O) (\U2_ADDR_reg<7>_MC.D2_PT_1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U2_ADDR_reg<7>_MC.D2_214 \ 0 5670 (_entity .  X_OR2)
		(_port
			((I0) (\U2_ADDR_reg<7>_MC.D2_PT_0 \))
			((I1) (\U2_ADDR_reg<7>_MC.D2_PT_1 \))
			((O) (\U2_ADDR_reg<7>_MC.D2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \outDATA<5>\\$WA0.UIM_215 \ 0 5675 (_entity .  X_BUF)
		(_port
			((I) (\outDATA<5>\\$WA0.UIM_MC.Q \))
			((O) (\outDATA<5>\\$WA0.UIM \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \outDATA<5>\\$WA0.UIM_MC.Q_216 \ 0 5679 (_entity .  X_BUF)
		(_port
			((I) (\outDATA<5>\\$WA0.UIM_MC.D \))
			((O) (\outDATA<5>\\$WA0.UIM_MC.Q \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \outDATA<5>\\$WA0.UIM_MC.D_217 \ 0 5683 (_entity .  X_XOR2)
		(_port
			((I0) (\outDATA<5>\\$WA0.UIM_MC.D1 \))
			((I1) (\outDATA<5>\\$WA0.UIM_MC.D2 \))
			((O) (\outDATA<5>\\$WA0.UIM_MC.D \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \outDATA<5>\\$WA0.UIM_MC.D1_218 \ 0 5688 (_entity .  X_AND2)
		(_port
			((I0) (U11_U3_counterr(5)))
			((I1) (U11_U3_counterr(5)))
			((O) (\outDATA<5>\\$WA0.UIM_MC.D1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \outDATA<5>\\$WA0.UIM_MC.D2_219 \ 0 5693 (_entity .  X_ZERO)
		(_port
			((O) (\outDATA<5>\\$WA0.UIM_MC.D2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation U11_U3_counterr<5> 0 5696 (_entity .  X_BUF)
		(_port
			((I) (\U11_U3_counterr<5>_MC.Q \))
			((O) (U11_U3_counterr(5)))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U11_U3_counterr<5>_MC.REG \ 0 5700 (_entity .  X_FF)
		(_port
			((I) (\U11_U3_counterr<5>_MC.D \))
			((CE) (Vcc))
			((CLK) (\Mclk_II/FCLK \))
			((SET) (Gnd))
			((RST) (PRLD))
			((O) (\U11_U3_counterr<5>_MC.Q \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U11_U3_counterr<5>_MC.D_220 \ 0 5708 (_entity .  X_XOR2)
		(_port
			((I0) (\U11_U3_counterr<5>_MC.D1 \))
			((I1) (\U11_U3_counterr<5>_MC.D2 \))
			((O) (\U11_U3_counterr<5>_MC.D \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U11_U3_counterr<5>_MC.D1_221 \ 0 5713 (_entity .  X_AND2)
		(_port
			((I0) (U11_U3_counterr(5)))
			((I1) (U11_U3_counterr(5)))
			((O) (\U11_U3_counterr<5>_MC.D1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U11_U3_counterr<5>_MC.D2_PT_0_222 \ 0 5718 (_entity .  X_AND2)
		(_port
			((I0) (U11_U3_counterr(5)))
			((I1) (\SCLreset_II/UIM \))
			((O) (\U11_U3_counterr<5>_MC.D2_PT_0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U11_U3_counterr<5>_MC.D2_PT_1_223 \ 0 5723 (_entity .  X_AND4)
		(_port
			((I0) (\NlwInverterSignal_U11_U3_counterr<5>_MC.D2_PT_1/IN0 \))
			((I1) (U11_U3_counterr(3)))
			((I2) (U11_U3_counterr(4)))
			((I3) (U11_Incdetect))
			((O) (\U11_U3_counterr<5>_MC.D2_PT_1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U11_U3_counterr<5>_MC.D2_PT_2_224 \ 0 5730 (_entity .  X_AND7)
		(_port
			((I0) (\NlwInverterSignal_U11_U3_counterr<5>_MC.D2_PT_2/IN0 \))
			((I1) (U11_U3_counterr(4)))
			((I2) (U11_Incdetect))
			((I3) (U11_U3_counterr(0)))
			((I4) (U11_U3_counterr(1)))
			((I5) (U11_U3_counterr(2)))
			((I6) (\NlwInverterSignal_U11_U3_counterr<5>_MC.D2_PT_2/IN6 \))
			((O) (\U11_U3_counterr<5>_MC.D2_PT_2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U11_U3_counterr<5>_MC.D2_PT_3_225 \ 0 5740 (_entity .  X_AND8)
		(_port
			((I0) (U11_U3_counterr(5)))
			((I1) (\NlwInverterSignal_U11_U3_counterr<5>_MC.D2_PT_3/IN1 \))
			((I2) (\NlwInverterSignal_U11_U3_counterr<5>_MC.D2_PT_3/IN2 \))
			((I3) (\NlwInverterSignal_U11_U3_counterr<5>_MC.D2_PT_3/IN3 \))
			((I4) (\NlwInverterSignal_U11_U3_counterr<5>_MC.D2_PT_3/IN4 \))
			((I5) (\NlwInverterSignal_U11_U3_counterr<5>_MC.D2_PT_3/IN5 \))
			((I6) (\NlwInverterSignal_U11_U3_counterr<5>_MC.D2_PT_3/IN6 \))
			((I7) (U11_SCLdetect))
			((O) (\U11_U3_counterr<5>_MC.D2_PT_3 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U11_U3_counterr<5>_MC.D2_226 \ 0 5751 (_entity .  X_OR4)
		(_port
			((I0) (\U11_U3_counterr<5>_MC.D2_PT_0 \))
			((I1) (\U11_U3_counterr<5>_MC.D2_PT_1 \))
			((I2) (\U11_U3_counterr<5>_MC.D2_PT_2 \))
			((I3) (\U11_U3_counterr<5>_MC.D2_PT_3 \))
			((O) (\U11_U3_counterr<5>_MC.D2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation U11_U3_counterr<3> 0 5758 (_entity .  X_BUF)
		(_port
			((I) (\U11_U3_counterr<3>_MC.Q \))
			((O) (U11_U3_counterr(3)))
		)
		(_strength strong0 strong1)
	)
	(_instantiation U11_U3_counterr<3>_MC_tsimcreated_xor__227 0 5762 (_entity .  X_XOR2)
		(_port
			((I0) (\U11_U3_counterr<3>_MC.D \))
			((I1) (\U11_U3_counterr<3>_MC.Q \))
			((O) (U11_U3_counterr<3>_MC_tsimcreated_xor_))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U11_U3_counterr<3>_MC.REG \ 0 5767 (_entity .  X_FF)
		(_port
			((I) (U11_U3_counterr<3>_MC_tsimcreated_xor_))
			((CE) (Vcc))
			((CLK) (\Mclk_II/FCLK \))
			((SET) (Gnd))
			((RST) (PRLD))
			((O) (\U11_U3_counterr<3>_MC.Q \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U11_U3_counterr<3>_MC.D_228 \ 0 5775 (_entity .  X_XOR2)
		(_port
			((I0) (\NlwInverterSignal_U11_U3_counterr<3>_MC.D/IN0 \))
			((I1) (\U11_U3_counterr<3>_MC.D2 \))
			((O) (\U11_U3_counterr<3>_MC.D \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U11_U3_counterr<3>_MC.D1_229 \ 0 5780 (_entity .  X_ZERO)
		(_port
			((O) (\U11_U3_counterr<3>_MC.D1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U11_U3_counterr<3>_MC.D2_PT_0_230 \ 0 5783 (_entity .  X_AND2)
		(_port
			((I0) (\SCLreset_II/UIM \))
			((I1) (U11_U3_counterr(3)))
			((O) (\U11_U3_counterr<3>_MC.D2_PT_0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U11_U3_counterr<3>_MC.D2_PT_1_231 \ 0 5788 (_entity .  X_AND3)
		(_port
			((I0) (\NlwInverterSignal_U11_U3_counterr<3>_MC.D2_PT_1/IN0 \))
			((I1) (\NlwInverterSignal_U11_U3_counterr<3>_MC.D2_PT_1/IN1 \))
			((I2) (U11_U3_counterr(0)))
			((O) (\U11_U3_counterr<3>_MC.D2_PT_1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U11_U3_counterr<3>_MC.D2_PT_2_232 \ 0 5794 (_entity .  X_AND3)
		(_port
			((I0) (\NlwInverterSignal_U11_U3_counterr<3>_MC.D2_PT_2/IN0 \))
			((I1) (\NlwInverterSignal_U11_U3_counterr<3>_MC.D2_PT_2/IN1 \))
			((I2) (U11_U3_counterr(1)))
			((O) (\U11_U3_counterr<3>_MC.D2_PT_2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U11_U3_counterr<3>_MC.D2_PT_3_233 \ 0 5800 (_entity .  X_AND3)
		(_port
			((I0) (\NlwInverterSignal_U11_U3_counterr<3>_MC.D2_PT_3/IN0 \))
			((I1) (\NlwInverterSignal_U11_U3_counterr<3>_MC.D2_PT_3/IN1 \))
			((I2) (U11_U3_counterr(2)))
			((O) (\U11_U3_counterr<3>_MC.D2_PT_3 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U11_U3_counterr<3>_MC.D2_PT_4_234 \ 0 5806 (_entity .  X_AND3)
		(_port
			((I0) (\NlwInverterSignal_U11_U3_counterr<3>_MC.D2_PT_4/IN0 \))
			((I1) (\NlwInverterSignal_U11_U3_counterr<3>_MC.D2_PT_4/IN1 \))
			((I2) (\NlwInverterSignal_U11_U3_counterr<3>_MC.D2_PT_4/IN2 \))
			((O) (\U11_U3_counterr<3>_MC.D2_PT_4 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U11_U3_counterr<3>_MC.D2_PT_5_235 \ 0 5812 (_entity .  X_AND5)
		(_port
			((I0) (\NlwInverterSignal_U11_U3_counterr<3>_MC.D2_PT_5/IN0 \))
			((I1) (\NlwInverterSignal_U11_U3_counterr<3>_MC.D2_PT_5/IN1 \))
			((I2) (\NlwInverterSignal_U11_U3_counterr<3>_MC.D2_PT_5/IN2 \))
			((I3) (\NlwInverterSignal_U11_U3_counterr<3>_MC.D2_PT_5/IN3 \))
			((I4) (\NlwInverterSignal_U11_U3_counterr<3>_MC.D2_PT_5/IN4 \))
			((O) (\U11_U3_counterr<3>_MC.D2_PT_5 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U11_U3_counterr<3>_MC.D2_PT_6_236 \ 0 5820 (_entity .  X_AND5)
		(_port
			((I0) (\NlwInverterSignal_U11_U3_counterr<3>_MC.D2_PT_6/IN0 \))
			((I1) (U11_U3_counterr(0)))
			((I2) (U11_U3_counterr(1)))
			((I3) (U11_U3_counterr(2)))
			((I4) (\NlwInverterSignal_U11_U3_counterr<3>_MC.D2_PT_6/IN4 \))
			((O) (\U11_U3_counterr<3>_MC.D2_PT_6 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U11_U3_counterr<3>_MC.D2_237 \ 0 5828 (_entity .  X_OR7)
		(_port
			((I0) (\U11_U3_counterr<3>_MC.D2_PT_0 \))
			((I1) (\U11_U3_counterr<3>_MC.D2_PT_1 \))
			((I2) (\U11_U3_counterr<3>_MC.D2_PT_2 \))
			((I3) (\U11_U3_counterr<3>_MC.D2_PT_3 \))
			((I4) (\U11_U3_counterr<3>_MC.D2_PT_4 \))
			((I5) (\U11_U3_counterr<3>_MC.D2_PT_5 \))
			((I6) (\U11_U3_counterr<3>_MC.D2_PT_6 \))
			((O) (\U11_U3_counterr<3>_MC.D2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation U11_U3_counterr<0> 0 5838 (_entity .  X_BUF)
		(_port
			((I) (\U11_U3_counterr<0>_MC.Q \))
			((O) (U11_U3_counterr(0)))
		)
		(_strength strong0 strong1)
	)
	(_instantiation U11_U3_counterr<0>_MC_tsimcreated_xor__238 0 5842 (_entity .  X_XOR2)
		(_port
			((I0) (\U11_U3_counterr<0>_MC.D \))
			((I1) (\U11_U3_counterr<0>_MC.Q \))
			((O) (U11_U3_counterr<0>_MC_tsimcreated_xor_))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U11_U3_counterr<0>_MC.REG \ 0 5847 (_entity .  X_FF)
		(_port
			((I) (U11_U3_counterr<0>_MC_tsimcreated_xor_))
			((CE) (Vcc))
			((CLK) (\Mclk_II/FCLK \))
			((SET) (Gnd))
			((RST) (PRLD))
			((O) (\U11_U3_counterr<0>_MC.Q \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U11_U3_counterr<0>_MC.D_239 \ 0 5855 (_entity .  X_XOR2)
		(_port
			((I0) (\NlwInverterSignal_U11_U3_counterr<0>_MC.D/IN0 \))
			((I1) (\U11_U3_counterr<0>_MC.D2 \))
			((O) (\U11_U3_counterr<0>_MC.D \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U11_U3_counterr<0>_MC.D1_240 \ 0 5860 (_entity .  X_ZERO)
		(_port
			((O) (\U11_U3_counterr<0>_MC.D1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U11_U3_counterr<0>_MC.D2_PT_0_241 \ 0 5863 (_entity .  X_AND2)
		(_port
			((I0) (\SCLreset_II/UIM \))
			((I1) (U11_U3_counterr(0)))
			((O) (\U11_U3_counterr<0>_MC.D2_PT_0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U11_U3_counterr<0>_MC.D2_PT_1_242 \ 0 5868 (_entity .  X_AND3)
		(_port
			((I0) (\NlwInverterSignal_U11_U3_counterr<0>_MC.D2_PT_1/IN0 \))
			((I1) (U11_Incdetect))
			((I2) (U11_SCLdetect))
			((O) (\U11_U3_counterr<0>_MC.D2_PT_1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U11_U3_counterr<0>_MC.D2_PT_2_243 \ 0 5874 (_entity .  X_AND3)
		(_port
			((I0) (\NlwInverterSignal_U11_U3_counterr<0>_MC.D2_PT_2/IN0 \))
			((I1) (\NlwInverterSignal_U11_U3_counterr<0>_MC.D2_PT_2/IN1 \))
			((I2) (\NlwInverterSignal_U11_U3_counterr<0>_MC.D2_PT_2/IN2 \))
			((O) (\U11_U3_counterr<0>_MC.D2_PT_2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U11_U3_counterr<0>_MC.D2_PT_3_244 \ 0 5880 (_entity .  X_AND8)
		(_port
			((I0) (\NlwInverterSignal_U11_U3_counterr<0>_MC.D2_PT_3/IN0 \))
			((I1) (\NlwInverterSignal_U11_U3_counterr<0>_MC.D2_PT_3/IN1 \))
			((I2) (\NlwInverterSignal_U11_U3_counterr<0>_MC.D2_PT_3/IN2 \))
			((I3) (\NlwInverterSignal_U11_U3_counterr<0>_MC.D2_PT_3/IN3 \))
			((I4) (\NlwInverterSignal_U11_U3_counterr<0>_MC.D2_PT_3/IN4 \))
			((I5) (\NlwInverterSignal_U11_U3_counterr<0>_MC.D2_PT_3/IN5 \))
			((I6) (\NlwInverterSignal_U11_U3_counterr<0>_MC.D2_PT_3/IN6 \))
			((I7) (U11_SCLdetect))
			((O) (\U11_U3_counterr<0>_MC.D2_PT_3 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U11_U3_counterr<0>_MC.D2_245 \ 0 5891 (_entity .  X_OR4)
		(_port
			((I0) (\U11_U3_counterr<0>_MC.D2_PT_0 \))
			((I1) (\U11_U3_counterr<0>_MC.D2_PT_1 \))
			((I2) (\U11_U3_counterr<0>_MC.D2_PT_2 \))
			((I3) (\U11_U3_counterr<0>_MC.D2_PT_3 \))
			((O) (\U11_U3_counterr<0>_MC.D2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation U11_U3_counterr<4> 0 5898 (_entity .  X_BUF)
		(_port
			((I) (\U11_U3_counterr<4>_MC.Q \))
			((O) (U11_U3_counterr(4)))
		)
		(_strength strong0 strong1)
	)
	(_instantiation U11_U3_counterr<4>_MC_tsimcreated_xor__246 0 5902 (_entity .  X_XOR2)
		(_port
			((I0) (\U11_U3_counterr<4>_MC.D \))
			((I1) (\U11_U3_counterr<4>_MC.Q \))
			((O) (U11_U3_counterr<4>_MC_tsimcreated_xor_))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U11_U3_counterr<4>_MC.REG \ 0 5907 (_entity .  X_FF)
		(_port
			((I) (U11_U3_counterr<4>_MC_tsimcreated_xor_))
			((CE) (Vcc))
			((CLK) (\Mclk_II/FCLK \))
			((SET) (Gnd))
			((RST) (PRLD))
			((O) (\U11_U3_counterr<4>_MC.Q \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U11_U3_counterr<4>_MC.D_247 \ 0 5915 (_entity .  X_XOR2)
		(_port
			((I0) (\U11_U3_counterr<4>_MC.D1 \))
			((I1) (\U11_U3_counterr<4>_MC.D2 \))
			((O) (\U11_U3_counterr<4>_MC.D \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U11_U3_counterr<4>_MC.D1_248 \ 0 5920 (_entity .  X_ZERO)
		(_port
			((O) (\U11_U3_counterr<4>_MC.D1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U11_U3_counterr<4>_MC.D2_PT_0_249 \ 0 5923 (_entity .  X_AND2)
		(_port
			((I0) (\SCLreset_II/UIM \))
			((I1) (U11_U3_counterr(4)))
			((O) (\U11_U3_counterr<4>_MC.D2_PT_0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U11_U3_counterr<4>_MC.D2_PT_1_250 \ 0 5928 (_entity .  X_AND3)
		(_port
			((I0) (\NlwInverterSignal_U11_U3_counterr<4>_MC.D2_PT_1/IN0 \))
			((I1) (U11_U3_counterr(3)))
			((I2) (U11_Incdetect))
			((O) (\U11_U3_counterr<4>_MC.D2_PT_1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U11_U3_counterr<4>_MC.D2_PT_2_251 \ 0 5934 (_entity .  X_AND6)
		(_port
			((I0) (\NlwInverterSignal_U11_U3_counterr<4>_MC.D2_PT_2/IN0 \))
			((I1) (U11_Incdetect))
			((I2) (U11_U3_counterr(0)))
			((I3) (U11_U3_counterr(1)))
			((I4) (U11_U3_counterr(2)))
			((I5) (\NlwInverterSignal_U11_U3_counterr<4>_MC.D2_PT_2/IN5 \))
			((O) (\U11_U3_counterr<4>_MC.D2_PT_2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U11_U3_counterr<4>_MC.D2_PT_3_252 \ 0 5943 (_entity .  X_AND7)
		(_port
			((I0) (\NlwInverterSignal_U11_U3_counterr<4>_MC.D2_PT_3/IN0 \))
			((I1) (U11_U3_counterr(4)))
			((I2) (\NlwInverterSignal_U11_U3_counterr<4>_MC.D2_PT_3/IN2 \))
			((I3) (\NlwInverterSignal_U11_U3_counterr<4>_MC.D2_PT_3/IN3 \))
			((I4) (\NlwInverterSignal_U11_U3_counterr<4>_MC.D2_PT_3/IN4 \))
			((I5) (\NlwInverterSignal_U11_U3_counterr<4>_MC.D2_PT_3/IN5 \))
			((I6) (U11_SCLdetect))
			((O) (\U11_U3_counterr<4>_MC.D2_PT_3 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U11_U3_counterr<4>_MC.D2_PT_4_253 \ 0 5953 (_entity .  X_AND8)
		(_port
			((I0) (U11_U3_counterr(5)))
			((I1) (\NlwInverterSignal_U11_U3_counterr<4>_MC.D2_PT_4/IN1 \))
			((I2) (\NlwInverterSignal_U11_U3_counterr<4>_MC.D2_PT_4/IN2 \))
			((I3) (\NlwInverterSignal_U11_U3_counterr<4>_MC.D2_PT_4/IN3 \))
			((I4) (\NlwInverterSignal_U11_U3_counterr<4>_MC.D2_PT_4/IN4 \))
			((I5) (\NlwInverterSignal_U11_U3_counterr<4>_MC.D2_PT_4/IN5 \))
			((I6) (\NlwInverterSignal_U11_U3_counterr<4>_MC.D2_PT_4/IN6 \))
			((I7) (U11_SCLdetect))
			((O) (\U11_U3_counterr<4>_MC.D2_PT_4 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U11_U3_counterr<4>_MC.D2_254 \ 0 5964 (_entity .  X_OR5)
		(_port
			((I0) (\U11_U3_counterr<4>_MC.D2_PT_0 \))
			((I1) (\U11_U3_counterr<4>_MC.D2_PT_1 \))
			((I2) (\U11_U3_counterr<4>_MC.D2_PT_2 \))
			((I3) (\U11_U3_counterr<4>_MC.D2_PT_3 \))
			((I4) (\U11_U3_counterr<4>_MC.D2_PT_4 \))
			((O) (\U11_U3_counterr<4>_MC.D2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation U11_Incdetect_255 0 5972 (_entity .  X_BUF)
		(_port
			((I) (\U11_Incdetect_MC.Q \))
			((O) (U11_Incdetect))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U11_Incdetect_MC.REG \ 0 5976 (_entity .  X_FF)
		(_port
			((I) (\U11_Incdetect_MC.D \))
			((CE) (Vcc))
			((CLK) (\U11_Incdetect_MC.REG_tsimcreated_inv_Mclk_II/FCLK \))
			((SET) (Gnd))
			((RST) (PRLD))
			((O) (\U11_Incdetect_MC.Q \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U11_Incdetect_MC.REG_tsimcreated_inv_Mclk_II/FCLK_256 \ 0 5984 (_entity .  X_INV)
		(_port
			((I) (\Mclk_II/FCLK \))
			((O) (\U11_Incdetect_MC.REG_tsimcreated_inv_Mclk_II/FCLK \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U11_Incdetect_MC.D_257 \ 0 5988 (_entity .  X_XOR2)
		(_port
			((I0) (\U11_Incdetect_MC.D1 \))
			((I1) (\U11_Incdetect_MC.D2 \))
			((O) (\U11_Incdetect_MC.D \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U11_Incdetect_MC.D1_258 \ 0 5993 (_entity .  X_AND2)
		(_port
			((I0) (\NlwInverterSignal_U11_Incdetect_MC.D1/IN0 \))
			((I1) (\U11_U1/Line_last \))
			((O) (\U11_Incdetect_MC.D1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U11_Incdetect_MC.D2_259 \ 0 5998 (_entity .  X_ZERO)
		(_port
			((O) (\U11_Incdetect_MC.D2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation U11_U3_counterr<1> 0 6001 (_entity .  X_BUF)
		(_port
			((I) (\U11_U3_counterr<1>_MC.Q \))
			((O) (U11_U3_counterr(1)))
		)
		(_strength strong0 strong1)
	)
	(_instantiation U11_U3_counterr<1>_MC_tsimcreated_xor__260 0 6005 (_entity .  X_XOR2)
		(_port
			((I0) (\U11_U3_counterr<1>_MC.D \))
			((I1) (\U11_U3_counterr<1>_MC.Q \))
			((O) (U11_U3_counterr<1>_MC_tsimcreated_xor_))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U11_U3_counterr<1>_MC.REG \ 0 6010 (_entity .  X_FF)
		(_port
			((I) (U11_U3_counterr<1>_MC_tsimcreated_xor_))
			((CE) (Vcc))
			((CLK) (\Mclk_II/FCLK \))
			((SET) (Gnd))
			((RST) (PRLD))
			((O) (\U11_U3_counterr<1>_MC.Q \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U11_U3_counterr<1>_MC.D_261 \ 0 6018 (_entity .  X_XOR2)
		(_port
			((I0) (\NlwInverterSignal_U11_U3_counterr<1>_MC.D/IN0 \))
			((I1) (\U11_U3_counterr<1>_MC.D2 \))
			((O) (\U11_U3_counterr<1>_MC.D \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U11_U3_counterr<1>_MC.D1_262 \ 0 6023 (_entity .  X_ZERO)
		(_port
			((O) (\U11_U3_counterr<1>_MC.D1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U11_U3_counterr<1>_MC.D2_PT_0_263 \ 0 6026 (_entity .  X_AND2)
		(_port
			((I0) (\SCLreset_II/UIM \))
			((I1) (\NlwInverterSignal_U11_U3_counterr<1>_MC.D2_PT_0/IN1 \))
			((O) (\U11_U3_counterr<1>_MC.D2_PT_0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U11_U3_counterr<1>_MC.D2_PT_1_264 \ 0 6031 (_entity .  X_AND3)
		(_port
			((I0) (\NlwInverterSignal_U11_U3_counterr<1>_MC.D2_PT_1/IN0 \))
			((I1) (U11_Incdetect))
			((I2) (U11_SCLdetect))
			((O) (\U11_U3_counterr<1>_MC.D2_PT_1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U11_U3_counterr<1>_MC.D2_PT_2_265 \ 0 6037 (_entity .  X_AND3)
		(_port
			((I0) (\NlwInverterSignal_U11_U3_counterr<1>_MC.D2_PT_2/IN0 \))
			((I1) (\NlwInverterSignal_U11_U3_counterr<1>_MC.D2_PT_2/IN1 \))
			((I2) (U11_U3_counterr(0)))
			((O) (\U11_U3_counterr<1>_MC.D2_PT_2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U11_U3_counterr<1>_MC.D2_PT_3_266 \ 0 6043 (_entity .  X_AND3)
		(_port
			((I0) (\NlwInverterSignal_U11_U3_counterr<1>_MC.D2_PT_3/IN0 \))
			((I1) (\NlwInverterSignal_U11_U3_counterr<1>_MC.D2_PT_3/IN1 \))
			((I2) (\NlwInverterSignal_U11_U3_counterr<1>_MC.D2_PT_3/IN2 \))
			((O) (\U11_U3_counterr<1>_MC.D2_PT_3 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U11_U3_counterr<1>_MC.D2_PT_4_267 \ 0 6049 (_entity .  X_AND6)
		(_port
			((I0) (\NlwInverterSignal_U11_U3_counterr<1>_MC.D2_PT_4/IN0 \))
			((I1) (\NlwInverterSignal_U11_U3_counterr<1>_MC.D2_PT_4/IN1 \))
			((I2) (\NlwInverterSignal_U11_U3_counterr<1>_MC.D2_PT_4/IN2 \))
			((I3) (\NlwInverterSignal_U11_U3_counterr<1>_MC.D2_PT_4/IN3 \))
			((I4) (\NlwInverterSignal_U11_U3_counterr<1>_MC.D2_PT_4/IN4 \))
			((I5) (U11_SCLdetect))
			((O) (\U11_U3_counterr<1>_MC.D2_PT_4 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U11_U3_counterr<1>_MC.D2_268 \ 0 6058 (_entity .  X_OR5)
		(_port
			((I0) (\U11_U3_counterr<1>_MC.D2_PT_0 \))
			((I1) (\U11_U3_counterr<1>_MC.D2_PT_1 \))
			((I2) (\U11_U3_counterr<1>_MC.D2_PT_2 \))
			((I3) (\U11_U3_counterr<1>_MC.D2_PT_3 \))
			((I4) (\U11_U3_counterr<1>_MC.D2_PT_4 \))
			((O) (\U11_U3_counterr<1>_MC.D2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation U11_U3_counterr<2> 0 6066 (_entity .  X_BUF)
		(_port
			((I) (\U11_U3_counterr<2>_MC.Q \))
			((O) (U11_U3_counterr(2)))
		)
		(_strength strong0 strong1)
	)
	(_instantiation U11_U3_counterr<2>_MC_tsimcreated_xor__269 0 6070 (_entity .  X_XOR2)
		(_port
			((I0) (\U11_U3_counterr<2>_MC.D \))
			((I1) (\U11_U3_counterr<2>_MC.Q \))
			((O) (U11_U3_counterr<2>_MC_tsimcreated_xor_))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U11_U3_counterr<2>_MC.REG \ 0 6075 (_entity .  X_FF)
		(_port
			((I) (U11_U3_counterr<2>_MC_tsimcreated_xor_))
			((CE) (Vcc))
			((CLK) (\Mclk_II/FCLK \))
			((SET) (Gnd))
			((RST) (PRLD))
			((O) (\U11_U3_counterr<2>_MC.Q \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U11_U3_counterr<2>_MC.D_270 \ 0 6083 (_entity .  X_XOR2)
		(_port
			((I0) (\U11_U3_counterr<2>_MC.D1 \))
			((I1) (\U11_U3_counterr<2>_MC.D2 \))
			((O) (\U11_U3_counterr<2>_MC.D \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U11_U3_counterr<2>_MC.D1_271 \ 0 6088 (_entity .  X_ZERO)
		(_port
			((O) (\U11_U3_counterr<2>_MC.D1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U11_U3_counterr<2>_MC.D2_PT_0_272 \ 0 6091 (_entity .  X_AND2)
		(_port
			((I0) (\SCLreset_II/UIM \))
			((I1) (U11_U3_counterr(2)))
			((O) (\U11_U3_counterr<2>_MC.D2_PT_0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U11_U3_counterr<2>_MC.D2_PT_1_273 \ 0 6096 (_entity .  X_AND5)
		(_port
			((I0) (\NlwInverterSignal_U11_U3_counterr<2>_MC.D2_PT_1/IN0 \))
			((I1) (U11_Incdetect))
			((I2) (U11_U3_counterr(0)))
			((I3) (U11_U3_counterr(1)))
			((I4) (\NlwInverterSignal_U11_U3_counterr<2>_MC.D2_PT_1/IN4 \))
			((O) (\U11_U3_counterr<2>_MC.D2_PT_1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U11_U3_counterr<2>_MC.D2_PT_2_274 \ 0 6104 (_entity .  X_AND5)
		(_port
			((I0) (\NlwInverterSignal_U11_U3_counterr<2>_MC.D2_PT_2/IN0 \))
			((I1) (\NlwInverterSignal_U11_U3_counterr<2>_MC.D2_PT_2/IN1 \))
			((I2) (\NlwInverterSignal_U11_U3_counterr<2>_MC.D2_PT_2/IN2 \))
			((I3) (U11_U3_counterr(2)))
			((I4) (U11_SCLdetect))
			((O) (\U11_U3_counterr<2>_MC.D2_PT_2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U11_U3_counterr<2>_MC.D2_PT_3_275 \ 0 6112 (_entity .  X_AND6)
		(_port
			((I0) (U11_U3_counterr(5)))
			((I1) (\NlwInverterSignal_U11_U3_counterr<2>_MC.D2_PT_3/IN1 \))
			((I2) (\NlwInverterSignal_U11_U3_counterr<2>_MC.D2_PT_3/IN2 \))
			((I3) (\NlwInverterSignal_U11_U3_counterr<2>_MC.D2_PT_3/IN3 \))
			((I4) (\NlwInverterSignal_U11_U3_counterr<2>_MC.D2_PT_3/IN4 \))
			((I5) (U11_SCLdetect))
			((O) (\U11_U3_counterr<2>_MC.D2_PT_3 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U11_U3_counterr<2>_MC.D2_PT_4_276 \ 0 6121 (_entity .  X_AND6)
		(_port
			((I0) (\NlwInverterSignal_U11_U3_counterr<2>_MC.D2_PT_4/IN0 \))
			((I1) (U11_U3_counterr(3)))
			((I2) (\NlwInverterSignal_U11_U3_counterr<2>_MC.D2_PT_4/IN2 \))
			((I3) (\NlwInverterSignal_U11_U3_counterr<2>_MC.D2_PT_4/IN3 \))
			((I4) (\NlwInverterSignal_U11_U3_counterr<2>_MC.D2_PT_4/IN4 \))
			((I5) (U11_SCLdetect))
			((O) (\U11_U3_counterr<2>_MC.D2_PT_4 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U11_U3_counterr<2>_MC.D2_PT_5_277 \ 0 6130 (_entity .  X_AND6)
		(_port
			((I0) (\NlwInverterSignal_U11_U3_counterr<2>_MC.D2_PT_5/IN0 \))
			((I1) (U11_U3_counterr(4)))
			((I2) (\NlwInverterSignal_U11_U3_counterr<2>_MC.D2_PT_5/IN2 \))
			((I3) (\NlwInverterSignal_U11_U3_counterr<2>_MC.D2_PT_5/IN3 \))
			((I4) (\NlwInverterSignal_U11_U3_counterr<2>_MC.D2_PT_5/IN4 \))
			((I5) (U11_SCLdetect))
			((O) (\U11_U3_counterr<2>_MC.D2_PT_5 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U11_U3_counterr<2>_MC.D2_278 \ 0 6139 (_entity .  X_OR6)
		(_port
			((I0) (\U11_U3_counterr<2>_MC.D2_PT_0 \))
			((I1) (\U11_U3_counterr<2>_MC.D2_PT_1 \))
			((I2) (\U11_U3_counterr<2>_MC.D2_PT_2 \))
			((I3) (\U11_U3_counterr<2>_MC.D2_PT_3 \))
			((I4) (\U11_U3_counterr<2>_MC.D2_PT_4 \))
			((I5) (\U11_U3_counterr<2>_MC.D2_PT_5 \))
			((O) (\U11_U3_counterr<2>_MC.D2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation U11_SCLdetect_279 0 6148 (_entity .  X_BUF)
		(_port
			((I) (\U11_SCLdetect_MC.Q \))
			((O) (U11_SCLdetect))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U11_SCLdetect_MC.REG \ 0 6152 (_entity .  X_FF)
		(_port
			((I) (\U11_SCLdetect_MC.D \))
			((CE) (Vcc))
			((CLK) (\U11_SCLdetect_MC.REG_tsimcreated_inv_Mclk_II/FCLK \))
			((SET) (Gnd))
			((RST) (PRLD))
			((O) (\U11_SCLdetect_MC.Q \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U11_SCLdetect_MC.REG_tsimcreated_inv_Mclk_II/FCLK_280 \ 0 6160 (_entity .  X_INV)
		(_port
			((I) (\Mclk_II/FCLK \))
			((O) (\U11_SCLdetect_MC.REG_tsimcreated_inv_Mclk_II/FCLK \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U11_SCLdetect_MC.D_281 \ 0 6164 (_entity .  X_XOR2)
		(_port
			((I0) (\U11_SCLdetect_MC.D1 \))
			((I1) (\U11_SCLdetect_MC.D2 \))
			((O) (\U11_SCLdetect_MC.D \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U11_SCLdetect_MC.D1_282 \ 0 6169 (_entity .  X_AND2)
		(_port
			((I0) (\NlwInverterSignal_U11_SCLdetect_MC.D1/IN0 \))
			((I1) (\U11_U2/Line_last \))
			((O) (\U11_SCLdetect_MC.D1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U11_SCLdetect_MC.D2_283 \ 0 6174 (_entity .  X_ZERO)
		(_port
			((O) (\U11_SCLdetect_MC.D2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U11_U2/Line_last_MC.Q_284 \ 0 6177 (_entity .  X_BUF)
		(_port
			((I) (\U11_U2/Line_last_MC.D \))
			((O) (\U11_U2/Line_last_MC.Q \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U11_U2/Line_last_MC.OE_285 \ 0 6181 (_entity .  X_BUF)
		(_port
			((I) (\U11_U2/Line_last_MC.BUFOE.OUT \))
			((O) (\U11_U2/Line_last_MC.OE \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U11_U2/Line_last_MC.BUFOE.OUT_286 \ 0 6185 (_entity .  X_BUF)
		(_port
			((I) (\FOOBAR4__ctinst/0 \))
			((O) (\U11_U2/Line_last_MC.BUFOE.OUT \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U11_U2/Line_last_MC.D_287 \ 0 6189 (_entity .  X_XOR2)
		(_port
			((I0) (\U11_U2/Line_last_MC.D1 \))
			((I1) (\U11_U2/Line_last_MC.D2 \))
			((O) (\U11_U2/Line_last_MC.D \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U11_U2/Line_last_MC.D1_288 \ 0 6194 (_entity .  X_ZERO)
		(_port
			((O) (\U11_U2/Line_last_MC.D1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U11_U2/Line_last_MC.D2_289 \ 0 6197 (_entity .  X_ZERO)
		(_port
			((O) (\U11_U2/Line_last_MC.D2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \outDATA<5>\\$WA1.UIM_290 \ 0 6200 (_entity .  X_BUF)
		(_port
			((I) (\outDATA<5>\\$WA1.UIM_MC.Q \))
			((O) (\outDATA<5>\\$WA1.UIM \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \outDATA<5>\\$WA1.UIM_MC.Q_291 \ 0 6204 (_entity .  X_BUF)
		(_port
			((I) (\outDATA<5>\\$WA1.UIM_MC.D \))
			((O) (\outDATA<5>\\$WA1.UIM_MC.Q \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \outDATA<5>\\$WA1.UIM_MC.D_292 \ 0 6208 (_entity .  X_XOR2)
		(_port
			((I0) (\outDATA<5>\\$WA1.UIM_MC.D1 \))
			((I1) (\outDATA<5>\\$WA1.UIM_MC.D2 \))
			((O) (\outDATA<5>\\$WA1.UIM_MC.D \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \outDATA<5>\\$WA1.UIM_MC.D1_293 \ 0 6213 (_entity .  X_AND2)
		(_port
			((I0) (\I2CS<5>_II/UIM \))
			((I1) (\I2CS<5>_II/UIM \))
			((O) (\outDATA<5>\\$WA1.UIM_MC.D1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \outDATA<5>\\$WA1.UIM_MC.D2_294 \ 0 6218 (_entity .  X_ZERO)
		(_port
			((O) (\outDATA<5>\\$WA1.UIM_MC.D2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \outDATA<5>\\$WA2.UIM_295 \ 0 6221 (_entity .  X_BUF)
		(_port
			((I) (\outDATA<5>\\$WA2.UIM_MC.Q \))
			((O) (\outDATA<5>\\$WA2.UIM \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \outDATA<5>\\$WA2.UIM_MC.Q_296 \ 0 6225 (_entity .  X_BUF)
		(_port
			((I) (\outDATA<5>\\$WA2.UIM_MC.D \))
			((O) (\outDATA<5>\\$WA2.UIM_MC.Q \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \outDATA<5>\\$WA2.UIM_MC.D_297 \ 0 6229 (_entity .  X_XOR2)
		(_port
			((I0) (\outDATA<5>\\$WA2.UIM_MC.D1 \))
			((I1) (\outDATA<5>\\$WA2.UIM_MC.D2 \))
			((O) (\outDATA<5>\\$WA2.UIM_MC.D \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \outDATA<5>\\$WA2.UIM_MC.D1_298 \ 0 6234 (_entity .  X_AND2)
		(_port
			((I0) (\FLS1_II/UIM \))
			((I1) (\FLS1_II/UIM \))
			((O) (\outDATA<5>\\$WA2.UIM_MC.D1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \outDATA<5>\\$WA2.UIM_MC.D2_299 \ 0 6239 (_entity .  X_ZERO)
		(_port
			((O) (\outDATA<5>\\$WA2.UIM_MC.D2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \outDATA<5>\\$WA3.UIM_300 \ 0 6242 (_entity .  X_BUF)
		(_port
			((I) (\outDATA<5>\\$WA3.UIM_MC.Q \))
			((O) (\outDATA<5>\\$WA3.UIM \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \outDATA<5>\\$WA3.UIM_MC.Q_301 \ 0 6246 (_entity .  X_BUF)
		(_port
			((I) (\outDATA<5>\\$WA3.UIM_MC.D \))
			((O) (\outDATA<5>\\$WA3.UIM_MC.Q \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \outDATA<5>\\$WA3.UIM_MC.D_302 \ 0 6250 (_entity .  X_XOR2)
		(_port
			((I0) (\outDATA<5>\\$WA3.UIM_MC.D1 \))
			((I1) (\outDATA<5>\\$WA3.UIM_MC.D2 \))
			((O) (\outDATA<5>\\$WA3.UIM_MC.D \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \outDATA<5>\\$WA3.UIM_MC.D1_303 \ 0 6255 (_entity .  X_ZERO)
		(_port
			((O) (\outDATA<5>\\$WA3.UIM_MC.D1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \outDATA<5>\\$WA3.UIM_MC.D2_PT_0_304 \ 0 6258 (_entity .  X_AND2)
		(_port
			((I0) (\Home15FLG_II/UIM \))
			((I1) (\NlwInverterSignal_outDATA<5>\\$WA3.UIM_MC.D2_PT_0/IN1 \))
			((O) (\outDATA<5>\\$WA3.UIM_MC.D2_PT_0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \outDATA<5>\\$WA3.UIM_MC.D2_PT_1_305 \ 0 6263 (_entity .  X_AND2)
		(_port
			((I0) (NET2528))
			((I1) (\U4/Flgreg \(5)))
			((O) (\outDATA<5>\\$WA3.UIM_MC.D2_PT_1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \outDATA<5>\\$WA3.UIM_MC.D2_306 \ 0 6268 (_entity .  X_OR2)
		(_port
			((I0) (\outDATA<5>\\$WA3.UIM_MC.D2_PT_0 \))
			((I1) (\outDATA<5>\\$WA3.UIM_MC.D2_PT_1 \))
			((O) (\outDATA<5>\\$WA3.UIM_MC.D2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation NET2528_307 0 6273 (_entity .  X_BUF)
		(_port
			((I) (\NET2528_MC.Q \))
			((O) (NET2528))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NET2528_MC.REG \ 0 6277 (_entity .  X_FF)
		(_port
			((I) (\NET2528_MC.D \))
			((CE) (Vcc))
			((CLK) (\Mclk_II/FCLK \))
			((SET) (Gnd))
			((RST) (PRLD))
			((O) (\NET2528_MC.Q \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NET2528_MC.D_308 \ 0 6285 (_entity .  X_XOR2)
		(_port
			((I0) (\NlwInverterSignal_NET2528_MC.D/IN0 \))
			((I1) (\NET2528_MC.D2 \))
			((O) (\NET2528_MC.D \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NET2528_MC.D1_309 \ 0 6290 (_entity .  X_ZERO)
		(_port
			((O) (\NET2528_MC.D1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NET2528_MC.D2_PT_0_310 \ 0 6293 (_entity .  X_AND2)
		(_port
			((I0) (\Reset_II/UIM \))
			((I1) (\Reset_II/UIM \))
			((O) (\NET2528_MC.D2_PT_0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NET2528_MC.D2_PT_1_311 \ 0 6298 (_entity .  X_AND3)
		(_port
			((I0) (U2_ADDR_reg(0)))
			((I1) (\NlwInverterSignal_NET2528_MC.D2_PT_1/IN1 \))
			((I2) (\U4/orFLGs \))
			((O) (\NET2528_MC.D2_PT_1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NET2528_MC.D2_PT_2_312 \ 0 6304 (_entity .  X_AND3)
		(_port
			((I0) (\NlwInverterSignal_NET2528_MC.D2_PT_2/IN0 \))
			((I1) (\NlwInverterSignal_NET2528_MC.D2_PT_2/IN1 \))
			((I2) (N_PZ_978))
			((O) (\NET2528_MC.D2_PT_2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NET2528_MC.D2_PT_3_313 \ 0 6310 (_entity .  X_AND3)
		(_port
			((I0) (\NlwInverterSignal_NET2528_MC.D2_PT_3/IN0 \))
			((I1) (\U4/orFLGs \))
			((I2) (\NlwInverterSignal_NET2528_MC.D2_PT_3/IN2 \))
			((O) (\NET2528_MC.D2_PT_3 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NET2528_MC.D2_314 \ 0 6316 (_entity .  X_OR4)
		(_port
			((I0) (\NET2528_MC.D2_PT_0 \))
			((I1) (\NET2528_MC.D2_PT_1 \))
			((I2) (\NET2528_MC.D2_PT_2 \))
			((I3) (\NET2528_MC.D2_PT_3 \))
			((O) (\NET2528_MC.D2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U4/orFLGs_315 \ 0 6323 (_entity .  X_BUF)
		(_port
			((I) (\U4/orFLGs_MC.Q \))
			((O) (\U4/orFLGs \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U4/orFLGs_MC.Q_316 \ 0 6327 (_entity .  X_BUF)
		(_port
			((I) (\U4/orFLGs_MC.D \))
			((O) (\U4/orFLGs_MC.Q \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U4/orFLGs_MC.D_317 \ 0 6331 (_entity .  X_XOR2)
		(_port
			((I0) (\U4/orFLGs_MC.D1 \))
			((I1) (\U4/orFLGs_MC.D2 \))
			((O) (\U4/orFLGs_MC.D \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U4/orFLGs_MC.D1_318 \ 0 6336 (_entity .  X_AND8)
		(_port
			((I0) (\Home15FLG_II/UIM \))
			((I1) (\Home033FLG_II/UIM \))
			((I2) (\Home05FLG_II/UIM \))
			((I3) (\Enc033FLG_II/UIM \))
			((I4) (\Enc05FLG_II/UIM \))
			((I5) (\Home133FLG_II/UIM \))
			((I6) (\Enc133FLG_II/UIM \))
			((I7) (\Enc15FLG_II/UIM \))
			((O) (\U4/orFLGs_MC.D1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U4/orFLGs_MC.D2_319 \ 0 6347 (_entity .  X_ZERO)
		(_port
			((O) (\U4/orFLGs_MC.D2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation N_PZ_978_320 0 6350 (_entity .  X_BUF)
		(_port
			((I) (\N_PZ_978_MC.Q \))
			((O) (N_PZ_978))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \N_PZ_978_MC.Q_321 \ 0 6354 (_entity .  X_BUF)
		(_port
			((I) (\N_PZ_978_MC.D \))
			((O) (\N_PZ_978_MC.Q \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \N_PZ_978_MC.D_322 \ 0 6358 (_entity .  X_XOR2)
		(_port
			((I0) (\N_PZ_978_MC.D1 \))
			((I1) (\N_PZ_978_MC.D2 \))
			((O) (\N_PZ_978_MC.D \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \N_PZ_978_MC.D1_323 \ 0 6363 (_entity .  X_ZERO)
		(_port
			((O) (\N_PZ_978_MC.D1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \N_PZ_978_MC.D2_PT_0_324 \ 0 6366 (_entity .  X_AND2)
		(_port
			((I0) (\Reset_II/UIM \))
			((I1) (\Reset_II/UIM \))
			((O) (\N_PZ_978_MC.D2_PT_0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \N_PZ_978_MC.D2_PT_1_325 \ 0 6371 (_entity .  X_AND6)
		(_port
			((I0) (\NlwInverterSignal_N_PZ_978_MC.D2_PT_1/IN0 \))
			((I1) (\RD_II/UIM \))
			((I2) (U2_ADDR_reg(1)))
			((I3) (N_PZ_931))
			((I4) (\NlwInverterSignal_N_PZ_978_MC.D2_PT_1/IN4 \))
			((I5) (\NlwInverterSignal_N_PZ_978_MC.D2_PT_1/IN5 \))
			((O) (\N_PZ_978_MC.D2_PT_1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \N_PZ_978_MC.D2_326 \ 0 6380 (_entity .  X_OR2)
		(_port
			((I0) (\N_PZ_978_MC.D2_PT_0 \))
			((I1) (\N_PZ_978_MC.D2_PT_1 \))
			((O) (\N_PZ_978_MC.D2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \outDATA<5>\\$WA5.UIM_327 \ 0 6385 (_entity .  X_BUF)
		(_port
			((I) (\outDATA<5>\\$WA5.UIM_MC.Q \))
			((O) (\outDATA<5>\\$WA5.UIM \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \outDATA<5>\\$WA5.UIM_MC.Q_328 \ 0 6389 (_entity .  X_BUF)
		(_port
			((I) (\outDATA<5>\\$WA5.UIM_MC.D \))
			((O) (\outDATA<5>\\$WA5.UIM_MC.Q \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \outDATA<5>\\$WA5.UIM_MC.D_329 \ 0 6393 (_entity .  X_XOR2)
		(_port
			((I0) (\outDATA<5>\\$WA5.UIM_MC.D1 \))
			((I1) (\outDATA<5>\\$WA5.UIM_MC.D2 \))
			((O) (\outDATA<5>\\$WA5.UIM_MC.D \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \outDATA<5>\\$WA5.UIM_MC.D1_330 \ 0 6398 (_entity .  X_ZERO)
		(_port
			((O) (\outDATA<5>\\$WA5.UIM_MC.D1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \outDATA<5>\\$WA5.UIM_MC.D2_PT_0_331 \ 0 6401 (_entity .  X_AND2)
		(_port
			((I0) (\U1/U3/holdingreg \(5)))
			((I1) (N_PZ_966))
			((O) (\outDATA<5>\\$WA5.UIM_MC.D2_PT_0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \outDATA<5>\\$WA5.UIM_MC.D2_PT_1_332 \ 0 6406 (_entity .  X_AND2)
		(_port
			((I0) (N_PZ_1002))
			((I1) (\U1/U3/holdingreg \(21)))
			((O) (\outDATA<5>\\$WA5.UIM_MC.D2_PT_1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \outDATA<5>\\$WA5.UIM_MC.D2_PT_2_333 \ 0 6411 (_entity .  X_AND2)
		(_port
			((I0) (N_PZ_1061))
			((I1) (\U1/U3/holdingreg \(13)))
			((O) (\outDATA<5>\\$WA5.UIM_MC.D2_PT_2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \outDATA<5>\\$WA5.UIM_MC.D2_334 \ 0 6416 (_entity .  X_OR3)
		(_port
			((I0) (\outDATA<5>\\$WA5.UIM_MC.D2_PT_0 \))
			((I1) (\outDATA<5>\\$WA5.UIM_MC.D2_PT_1 \))
			((I2) (\outDATA<5>\\$WA5.UIM_MC.D2_PT_2 \))
			((O) (\outDATA<5>\\$WA5.UIM_MC.D2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U3/holdingreg<5> \ 0 6422 (_entity .  X_BUF)
		(_port
			((I) (\U1/U3/holdingreg<5>_MC.Q \))
			((O) (\U1/U3/holdingreg \(5)))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U3/holdingreg<5>_MC.REG \ 0 6426 (_entity .  X_FF)
		(_port
			((I) (\U1/U3/holdingreg<5>_MC.D \))
			((CE) (Vcc))
			((CLK) (\U1/U3/holdingreg<5>_MC.REG_tsimcreated_inv_Mclk_II/FCLK \))
			((SET) (Gnd))
			((RST) (PRLD))
			((O) (\U1/U3/holdingreg<5>_MC.Q \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U3/holdingreg<5>_MC.REG_tsimcreated_inv_Mclk_II/FCLK_335 \ 0 6434 (_entity .  X_INV)
		(_port
			((I) (\Mclk_II/FCLK \))
			((O) (\U1/U3/holdingreg<5>_MC.REG_tsimcreated_inv_Mclk_II/FCLK \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U3/holdingreg<5>_MC.D_336 \ 0 6438 (_entity .  X_XOR2)
		(_port
			((I0) (\U1/U3/holdingreg<5>_MC.D1 \))
			((I1) (\U1/U3/holdingreg<5>_MC.D2 \))
			((O) (\U1/U3/holdingreg<5>_MC.D \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U3/holdingreg<5>_MC.D1_337 \ 0 6443 (_entity .  X_ZERO)
		(_port
			((O) (\U1/U3/holdingreg<5>_MC.D1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U3/holdingreg<5>_MC.D2_PT_0_338 \ 0 6446 (_entity .  X_AND2)
		(_port
			((I0) (\U1/Channel1 \(5)))
			((I1) (N_PZ_986))
			((O) (\U1/U3/holdingreg<5>_MC.D2_PT_0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U3/holdingreg<5>_MC.D2_PT_1_339 \ 0 6451 (_entity .  X_AND3)
		(_port
			((I0) (\NlwInverterSignal_U1/U3/holdingreg<5>_MC.D2_PT_1/IN0 \))
			((I1) (\U1/U3/holdingreg \(5)))
			((I2) (\U1/U3/RDedge \))
			((O) (\U1/U3/holdingreg<5>_MC.D2_PT_1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U3/holdingreg<5>_MC.D2_PT_2_340 \ 0 6457 (_entity .  X_AND16)
		(_port
			((I0) (\WR_II/UIM \))
			((I1) (\NlwInverterSignal_U1/U3/holdingreg<5>_MC.D2_PT_2/IN1 \))
			((I2) (U2_ADDR_reg(1)))
			((I3) (U2_ADDR_reg(0)))
			((I4) (N_PZ_931))
			((I5) (U2_ADDR_reg(2)))
			((I6) (\NlwInverterSignal_U1/U3/holdingreg<5>_MC.D2_PT_2/IN6 \))
			((I7) (\NlwInverterSignal_U1/U3/holdingreg<5>_MC.D2_PT_2/IN7 \))
			((I8) (\NlwInverterSignal_U1/U3/holdingreg<5>_MC.D2_PT_2/IN8 \))
			((I9) (\U1/Channel0 \(5)))
			((I10) (Vcc))
			((I11) (Vcc))
			((I12) (Vcc))
			((I13) (Vcc))
			((I14) (Vcc))
			((I15) (Vcc))
			((O) (\U1/U3/holdingreg<5>_MC.D2_PT_2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U3/holdingreg<5>_MC.D2_341 \ 0 6476 (_entity .  X_OR3)
		(_port
			((I0) (\U1/U3/holdingreg<5>_MC.D2_PT_0 \))
			((I1) (\U1/U3/holdingreg<5>_MC.D2_PT_1 \))
			((I2) (\U1/U3/holdingreg<5>_MC.D2_PT_2 \))
			((O) (\U1/U3/holdingreg<5>_MC.D2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U3/RDedge_342 \ 0 6482 (_entity .  X_BUF)
		(_port
			((I) (\U1/U3/RDedge_MC.Q \))
			((O) (\U1/U3/RDedge \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U3/RDedge_MC.REG \ 0 6486 (_entity .  X_FF)
		(_port
			((I) (\U1/U3/RDedge_MC.D \))
			((CE) (Vcc))
			((CLK) (\U1/U3/RDedge_MC.REG_tsimcreated_inv_Mclk_II/FCLK \))
			((SET) (Gnd))
			((RST) (PRLD))
			((O) (\U1/U3/RDedge_MC.Q \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U3/RDedge_MC.REG_tsimcreated_inv_Mclk_II/FCLK_343 \ 0 6494 (_entity .  X_INV)
		(_port
			((I) (\Mclk_II/FCLK \))
			((O) (\U1/U3/RDedge_MC.REG_tsimcreated_inv_Mclk_II/FCLK \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U3/RDedge_MC.D_344 \ 0 6498 (_entity .  X_XOR2)
		(_port
			((I0) (\U1/U3/RDedge_MC.D1 \))
			((I1) (\U1/U3/RDedge_MC.D2 \))
			((O) (\U1/U3/RDedge_MC.D \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U3/RDedge_MC.D1_345 \ 0 6503 (_entity .  X_AND2)
		(_port
			((I0) (N_PZ_966))
			((I1) (N_PZ_966))
			((O) (\U1/U3/RDedge_MC.D1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U3/RDedge_MC.D2_346 \ 0 6508 (_entity .  X_ZERO)
		(_port
			((O) (\U1/U3/RDedge_MC.D2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation N_PZ_966_347 0 6511 (_entity .  X_BUF)
		(_port
			((I) (\N_PZ_966_MC.Q \))
			((O) (N_PZ_966))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \N_PZ_966_MC.Q_348 \ 0 6515 (_entity .  X_BUF)
		(_port
			((I) (\N_PZ_966_MC.D \))
			((O) (\N_PZ_966_MC.Q \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \N_PZ_966_MC.D_349 \ 0 6519 (_entity .  X_XOR2)
		(_port
			((I0) (\N_PZ_966_MC.D1 \))
			((I1) (\N_PZ_966_MC.D2 \))
			((O) (\N_PZ_966_MC.D \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \N_PZ_966_MC.D1_350 \ 0 6524 (_entity .  X_ZERO)
		(_port
			((O) (\N_PZ_966_MC.D1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \N_PZ_966_MC.D2_PT_0_351 \ 0 6527 (_entity .  X_AND6)
		(_port
			((I0) (U2_ADDR_reg(1)))
			((I1) (U2_ADDR_reg(0)))
			((I2) (N_PZ_931))
			((I3) (U2_ADDR_reg(2)))
			((I4) (\NlwInverterSignal_N_PZ_966_MC.D2_PT_0/IN4 \))
			((I5) (U2_Enable_AD))
			((O) (\N_PZ_966_MC.D2_PT_0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \N_PZ_966_MC.D2_PT_1_352 \ 0 6536 (_entity .  X_AND6)
		(_port
			((I0) (\NlwInverterSignal_N_PZ_966_MC.D2_PT_1/IN0 \))
			((I1) (\NlwInverterSignal_N_PZ_966_MC.D2_PT_1/IN1 \))
			((I2) (N_PZ_931))
			((I3) (U2_ADDR_reg(2)))
			((I4) (\NlwInverterSignal_N_PZ_966_MC.D2_PT_1/IN4 \))
			((I5) (U2_Enable_AD))
			((O) (\N_PZ_966_MC.D2_PT_1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \N_PZ_966_MC.D2_353 \ 0 6545 (_entity .  X_OR2)
		(_port
			((I0) (\N_PZ_966_MC.D2_PT_0 \))
			((I1) (\N_PZ_966_MC.D2_PT_1 \))
			((O) (\N_PZ_966_MC.D2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation U2_Enable_AD_354 0 6550 (_entity .  X_BUF)
		(_port
			((I) (\U2_Enable_AD_MC.Q \))
			((O) (U2_Enable_AD))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U2_Enable_AD_MC.Q_355 \ 0 6554 (_entity .  X_BUF)
		(_port
			((I) (\U2_Enable_AD_MC.D \))
			((O) (\U2_Enable_AD_MC.Q \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U2_Enable_AD_MC.D_356 \ 0 6558 (_entity .  X_XOR2)
		(_port
			((I0) (\U2_Enable_AD_MC.D1 \))
			((I1) (\U2_Enable_AD_MC.D2 \))
			((O) (\U2_Enable_AD_MC.D \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U2_Enable_AD_MC.D1_357 \ 0 6563 (_entity .  X_AND2)
		(_port
			((I0) (\WR_II/UIM \))
			((I1) (\NlwInverterSignal_U2_Enable_AD_MC.D1/IN1 \))
			((O) (\U2_Enable_AD_MC.D1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U2_Enable_AD_MC.D2_358 \ 0 6568 (_entity .  X_ZERO)
		(_port
			((O) (\U2_Enable_AD_MC.D2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/Channel0<5> \ 0 6571 (_entity .  X_BUF)
		(_port
			((I) (\U1/Channel0<5>_MC.Q \))
			((O) (\U1/Channel0 \(5)))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/Channel0<5>_MC_tsimcreated_xor__359 \ 0 6575 (_entity .  X_XOR2)
		(_port
			((I0) (\U1/Channel0<5>_MC.D \))
			((I1) (\U1/Channel0<5>_MC.Q \))
			((O) (\U1/Channel0<5>_MC_tsimcreated_xor_ \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/Channel0<5>_MC.REG \ 0 6580 (_entity .  X_FF)
		(_port
			((I) (\U1/Channel0<5>_MC_tsimcreated_xor_ \))
			((CE) (Vcc))
			((CLK) (\Mclk_II/FCLK \))
			((SET) (Gnd))
			((RST) (PRLD))
			((O) (\U1/Channel0<5>_MC.Q \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/Channel0<5>_MC.D_360 \ 0 6588 (_entity .  X_XOR2)
		(_port
			((I0) (\U1/Channel0<5>_MC.D1 \))
			((I1) (\U1/Channel0<5>_MC.D2 \))
			((O) (\U1/Channel0<5>_MC.D \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/Channel0<5>_MC.D1_361 \ 0 6593 (_entity .  X_ZERO)
		(_port
			((O) (\U1/Channel0<5>_MC.D1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/Channel0<5>_MC.D2_PT_0_362 \ 0 6596 (_entity .  X_AND2)
		(_port
			((I0) (\U1/Channel0 \(5)))
			((I1) (\NlwInverterSignal_U1/Channel0<5>_MC.D2_PT_0/IN1 \))
			((O) (\U1/Channel0<5>_MC.D2_PT_0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/Channel0<5>_MC.D2_PT_1_363 \ 0 6601 (_entity .  X_AND8)
		(_port
			((I0) (N_PZ_949))
			((I1) (\U1/Channel0 \(0)))
			((I2) (N_PZ_1018))
			((I3) (\U1/Channel0 \(1)))
			((I4) (\NlwInverterSignal_U1/Channel0<5>_MC.D2_PT_1/IN4 \))
			((I5) (\U1/Channel0 \(2)))
			((I6) (\U1/Channel0 \(3)))
			((I7) (\U1/Channel0 \(4)))
			((O) (\U1/Channel0<5>_MC.D2_PT_1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/Channel0<5>_MC.D2_PT_2_364 \ 0 6612 (_entity .  X_AND8)
		(_port
			((I0) (N_PZ_949))
			((I1) (\NlwInverterSignal_U1/Channel0<5>_MC.D2_PT_2/IN1 \))
			((I2) (N_PZ_1018))
			((I3) (\NlwInverterSignal_U1/Channel0<5>_MC.D2_PT_2/IN3 \))
			((I4) (N_PZ_961))
			((I5) (\NlwInverterSignal_U1/Channel0<5>_MC.D2_PT_2/IN5 \))
			((I6) (\NlwInverterSignal_U1/Channel0<5>_MC.D2_PT_2/IN6 \))
			((I7) (\NlwInverterSignal_U1/Channel0<5>_MC.D2_PT_2/IN7 \))
			((O) (\U1/Channel0<5>_MC.D2_PT_2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/Channel0<5>_MC.D2_365 \ 0 6623 (_entity .  X_OR3)
		(_port
			((I0) (\U1/Channel0<5>_MC.D2_PT_0 \))
			((I1) (\U1/Channel0<5>_MC.D2_PT_1 \))
			((I2) (\U1/Channel0<5>_MC.D2_PT_2 \))
			((O) (\U1/Channel0<5>_MC.D2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation N_PZ_949_366 0 6629 (_entity .  X_BUF)
		(_port
			((I) (\N_PZ_949_MC.Q \))
			((O) (N_PZ_949))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \N_PZ_949_MC.Q_367 \ 0 6633 (_entity .  X_BUF)
		(_port
			((I) (\N_PZ_949_MC.D \))
			((O) (\N_PZ_949_MC.Q \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \N_PZ_949_MC.D_368 \ 0 6637 (_entity .  X_XOR2)
		(_port
			((I0) (\N_PZ_949_MC.D1 \))
			((I1) (\N_PZ_949_MC.D2 \))
			((O) (\N_PZ_949_MC.D \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \N_PZ_949_MC.D1_369 \ 0 6642 (_entity .  X_AND2)
		(_port
			((I0) (\NlwInverterSignal_N_PZ_949_MC.D1/IN0 \))
			((I1) (\NlwInverterSignal_N_PZ_949_MC.D1/IN1 \))
			((O) (\N_PZ_949_MC.D1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \N_PZ_949_MC.D2_370 \ 0 6647 (_entity .  X_ZERO)
		(_port
			((O) (\N_PZ_949_MC.D2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/Zero0_371 \ 0 6650 (_entity .  X_BUF)
		(_port
			((I) (\U1/Zero0_MC.Q \))
			((O) (\U1/Zero0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/Zero0_MC.REG \ 0 6654 (_entity .  X_FF)
		(_port
			((I) (\U1/Zero0_MC.D \))
			((CE) (Vcc))
			((CLK) (\U1/Zero0_MC.REG_tsimcreated_inv_Mclk_II/FCLK \))
			((SET) (Gnd))
			((RST) (PRLD))
			((O) (\U1/Zero0_MC.Q \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/Zero0_MC.REG_tsimcreated_inv_Mclk_II/FCLK_372 \ 0 6662 (_entity .  X_INV)
		(_port
			((I) (\Mclk_II/FCLK \))
			((O) (\U1/Zero0_MC.REG_tsimcreated_inv_Mclk_II/FCLK \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/Zero0_MC.D_373 \ 0 6666 (_entity .  X_XOR2)
		(_port
			((I0) (\U1/Zero0_MC.D1 \))
			((I1) (\U1/Zero0_MC.D2 \))
			((O) (\U1/Zero0_MC.D \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/Zero0_MC.D1_374 \ 0 6671 (_entity .  X_ZERO)
		(_port
			((O) (\U1/Zero0_MC.D1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/Zero0_MC.D2_PT_0_375 \ 0 6674 (_entity .  X_AND2)
		(_port
			((I0) (N_PZ_978))
			((I1) (\U1/Zero0 \))
			((O) (\U1/Zero0_MC.D2_PT_0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/Zero0_MC.D2_PT_1_376 \ 0 6679 (_entity .  X_AND6)
		(_port
			((I0) (\NlwInverterSignal_U1/Zero0_MC.D2_PT_1/IN0 \))
			((I1) (\NlwInverterSignal_U1/Zero0_MC.D2_PT_1/IN1 \))
			((I2) (\U1/U4/RF0r \))
			((I3) (\U1/U4/HE0stater \))
			((I4) (\NlwInverterSignal_U1/Zero0_MC.D2_PT_1/IN4 \))
			((I5) (\U1/U4/E0r \))
			((O) (\U1/Zero0_MC.D2_PT_1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/Zero0_MC.D2_PT_2_377 \ 0 6688 (_entity .  X_AND6)
		(_port
			((I0) (\NlwInverterSignal_U1/Zero0_MC.D2_PT_2/IN0 \))
			((I1) (\NlwInverterSignal_U1/Zero0_MC.D2_PT_2/IN1 \))
			((I2) (\NlwInverterSignal_U1/Zero0_MC.D2_PT_2/IN2 \))
			((I3) (\NlwInverterSignal_U1/Zero0_MC.D2_PT_2/IN3 \))
			((I4) (\U1/U4/HE0statelastr \))
			((I5) (\U1/U4/E0r \))
			((O) (\U1/Zero0_MC.D2_PT_2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/Zero0_MC.D2_378 \ 0 6697 (_entity .  X_OR3)
		(_port
			((I0) (\U1/Zero0_MC.D2_PT_0 \))
			((I1) (\U1/Zero0_MC.D2_PT_1 \))
			((I2) (\U1/Zero0_MC.D2_PT_2 \))
			((O) (\U1/Zero0_MC.D2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation NET2482_379 0 6703 (_entity .  X_BUF)
		(_port
			((I) (\NET2482_MC.Q \))
			((O) (NET2482))
		)
		(_strength strong0 strong1)
	)
	(_instantiation NET2482_MC_tsimcreated_xor__380 0 6707 (_entity .  X_XOR2)
		(_port
			((I0) (\NET2482_MC.D \))
			((I1) (\NET2482_MC.Q \))
			((O) (NET2482_MC_tsimcreated_xor_))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NET2482_MC.REG \ 0 6712 (_entity .  X_FF)
		(_port
			((I) (NET2482_MC_tsimcreated_xor_))
			((CE) (Vcc))
			((CLK) (\NET2482_MC.REG_tsimcreated_inv_Mclk_II/FCLK \))
			((SET) (Gnd))
			((RST) (PRLD))
			((O) (\NET2482_MC.Q \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NET2482_MC.REG_tsimcreated_inv_Mclk_II/FCLK_381 \ 0 6720 (_entity .  X_INV)
		(_port
			((I) (\Mclk_II/FCLK \))
			((O) (\NET2482_MC.REG_tsimcreated_inv_Mclk_II/FCLK \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NET2482_MC.D_382 \ 0 6724 (_entity .  X_XOR2)
		(_port
			((I0) (\NET2482_MC.D1 \))
			((I1) (\NET2482_MC.D2 \))
			((O) (\NET2482_MC.D \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NET2482_MC.D1_383 \ 0 6729 (_entity .  X_ZERO)
		(_port
			((O) (\NET2482_MC.D1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NET2482_MC.D2_PT_0_384 \ 0 6732 (_entity .  X_AND5)
		(_port
			((I0) (\NlwInverterSignal_NET2482_MC.D2_PT_0/IN0 \))
			((I1) (\NlwInverterSignal_NET2482_MC.D2_PT_0/IN1 \))
			((I2) (\U1/U4/RF0r \))
			((I3) (\U1/U4/HE0stater \))
			((I4) (\NlwInverterSignal_NET2482_MC.D2_PT_0/IN4 \))
			((O) (\NET2482_MC.D2_PT_0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NET2482_MC.D2_PT_1_385 \ 0 6740 (_entity .  X_AND5)
		(_port
			((I0) (\NlwInverterSignal_NET2482_MC.D2_PT_1/IN0 \))
			((I1) (\NlwInverterSignal_NET2482_MC.D2_PT_1/IN1 \))
			((I2) (\NlwInverterSignal_NET2482_MC.D2_PT_1/IN2 \))
			((I3) (\NlwInverterSignal_NET2482_MC.D2_PT_1/IN3 \))
			((I4) (\U1/U4/HE0statelastr \))
			((O) (\NET2482_MC.D2_PT_1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NET2482_MC.D2_PT_2_386 \ 0 6748 (_entity .  X_AND16)
		(_port
			((I0) (\NlwInverterSignal_NET2482_MC.D2_PT_2/IN0 \))
			((I1) (\RD_II/UIM \))
			((I2) (U2_ADDR_reg(1)))
			((I3) (\NlwInverterSignal_NET2482_MC.D2_PT_2/IN3 \))
			((I4) (N_PZ_931))
			((I5) (\NlwInverterSignal_NET2482_MC.D2_PT_2/IN5 \))
			((I6) (\NlwInverterSignal_NET2482_MC.D2_PT_2/IN6 \))
			((I7) (\NlwInverterSignal_NET2482_MC.D2_PT_2/IN7 \))
			((I8) (\AD<2>_II/UIM \))
			((I9) (\NlwInverterSignal_NET2482_MC.D2_PT_2/IN9 \))
			((I10) (Vcc))
			((I11) (Vcc))
			((I12) (Vcc))
			((I13) (Vcc))
			((I14) (Vcc))
			((I15) (Vcc))
			((O) (\NET2482_MC.D2_PT_2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NET2482_MC.D2_PT_3_387 \ 0 6767 (_entity .  X_AND16)
		(_port
			((I0) (\NlwInverterSignal_NET2482_MC.D2_PT_3/IN0 \))
			((I1) (\RD_II/UIM \))
			((I2) (U2_ADDR_reg(1)))
			((I3) (\NlwInverterSignal_NET2482_MC.D2_PT_3/IN3 \))
			((I4) (N_PZ_931))
			((I5) (\NlwInverterSignal_NET2482_MC.D2_PT_3/IN5 \))
			((I6) (\NlwInverterSignal_NET2482_MC.D2_PT_3/IN6 \))
			((I7) (\NlwInverterSignal_NET2482_MC.D2_PT_3/IN7 \))
			((I8) (\NlwInverterSignal_NET2482_MC.D2_PT_3/IN8 \))
			((I9) (NET2482))
			((I10) (Vcc))
			((I11) (Vcc))
			((I12) (Vcc))
			((I13) (Vcc))
			((I14) (Vcc))
			((I15) (Vcc))
			((O) (\NET2482_MC.D2_PT_3 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NET2482_MC.D2_388 \ 0 6786 (_entity .  X_OR4)
		(_port
			((I0) (\NET2482_MC.D2_PT_0 \))
			((I1) (\NET2482_MC.D2_PT_1 \))
			((I2) (\NET2482_MC.D2_PT_2 \))
			((I3) (\NET2482_MC.D2_PT_3 \))
			((O) (\NET2482_MC.D2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U4/RF0r_389 \ 0 6793 (_entity .  X_BUF)
		(_port
			((I) (\U1/U4/RF0r_MC.Q \))
			((O) (\U1/U4/RF0r \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U4/RF0r_MC_tsimcreated_xor__390 \ 0 6797 (_entity .  X_XOR2)
		(_port
			((I0) (\U1/U4/RF0r_MC.D \))
			((I1) (\U1/U4/RF0r_MC.Q \))
			((O) (\U1/U4/RF0r_MC_tsimcreated_xor_ \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U4/RF0r_MC.REG \ 0 6802 (_entity .  X_FF)
		(_port
			((I) (\U1/U4/RF0r_MC_tsimcreated_xor_ \))
			((CE) (Vcc))
			((CLK) (\U1/U4/RF0r_MC.REG_tsimcreated_inv_Mclk_II/FCLK \))
			((SET) (Gnd))
			((RST) (PRLD))
			((O) (\U1/U4/RF0r_MC.Q \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U4/RF0r_MC.REG_tsimcreated_inv_Mclk_II/FCLK_391 \ 0 6810 (_entity .  X_INV)
		(_port
			((I) (\Mclk_II/FCLK \))
			((O) (\U1/U4/RF0r_MC.REG_tsimcreated_inv_Mclk_II/FCLK \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U4/RF0r_MC.D_392 \ 0 6814 (_entity .  X_XOR2)
		(_port
			((I0) (\U1/U4/RF0r_MC.D1 \))
			((I1) (\U1/U4/RF0r_MC.D2 \))
			((O) (\U1/U4/RF0r_MC.D \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U4/RF0r_MC.D1_393 \ 0 6819 (_entity .  X_ZERO)
		(_port
			((O) (\U1/U4/RF0r_MC.D1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U4/RF0r_MC.D2_PT_0_394 \ 0 6822 (_entity .  X_AND2)
		(_port
			((I0) (\Reset_II/UIM \))
			((I1) (\U1/U4/RF0r \))
			((O) (\U1/U4/RF0r_MC.D2_PT_0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U4/RF0r_MC.D2_PT_1_395 \ 0 6827 (_entity .  X_AND16)
		(_port
			((I0) (\NlwInverterSignal_U1/U4/RF0r_MC.D2_PT_1/IN0 \))
			((I1) (\RD_II/UIM \))
			((I2) (U2_ADDR_reg(1)))
			((I3) (U2_ADDR_reg(0)))
			((I4) (N_PZ_931))
			((I5) (\NlwInverterSignal_U1/U4/RF0r_MC.D2_PT_1/IN5 \))
			((I6) (\NlwInverterSignal_U1/U4/RF0r_MC.D2_PT_1/IN6 \))
			((I7) (\NlwInverterSignal_U1/U4/RF0r_MC.D2_PT_1/IN7 \))
			((I8) (\U1/U4/RF0r \))
			((I9) (Vcc))
			((I10) (Vcc))
			((I11) (Vcc))
			((I12) (Vcc))
			((I13) (Vcc))
			((I14) (Vcc))
			((I15) (Vcc))
			((O) (\U1/U4/RF0r_MC.D2_PT_1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U4/RF0r_MC.D2_PT_2_396 \ 0 6846 (_entity .  X_AND16)
		(_port
			((I0) (\NlwInverterSignal_U1/U4/RF0r_MC.D2_PT_2/IN0 \))
			((I1) (\RD_II/UIM \))
			((I2) (U2_ADDR_reg(1)))
			((I3) (U2_ADDR_reg(0)))
			((I4) (N_PZ_931))
			((I5) (\NlwInverterSignal_U1/U4/RF0r_MC.D2_PT_2/IN5 \))
			((I6) (\NlwInverterSignal_U1/U4/RF0r_MC.D2_PT_2/IN6 \))
			((I7) (\NlwInverterSignal_U1/U4/RF0r_MC.D2_PT_2/IN7 \))
			((I8) (\AD<0>_II/UIM \))
			((I9) (\NlwInverterSignal_U1/U4/RF0r_MC.D2_PT_2/IN9 \))
			((I10) (Vcc))
			((I11) (Vcc))
			((I12) (Vcc))
			((I13) (Vcc))
			((I14) (Vcc))
			((I15) (Vcc))
			((O) (\U1/U4/RF0r_MC.D2_PT_2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U4/RF0r_MC.D2_397 \ 0 6865 (_entity .  X_OR3)
		(_port
			((I0) (\U1/U4/RF0r_MC.D2_PT_0 \))
			((I1) (\U1/U4/RF0r_MC.D2_PT_1 \))
			((I2) (\U1/U4/RF0r_MC.D2_PT_2 \))
			((O) (\U1/U4/RF0r_MC.D2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U4/HE0statelastr_398 \ 0 6871 (_entity .  X_BUF)
		(_port
			((I) (\U1/U4/HE0statelastr_MC.Q \))
			((O) (\U1/U4/HE0statelastr \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U4/HE0statelastr_MC.REG \ 0 6875 (_entity .  X_FF)
		(_port
			((I) (\U1/U4/HE0statelastr_MC.D \))
			((CE) (Vcc))
			((CLK) (\U1/U4/HE0statelastr_MC.REG_tsimcreated_inv_Mclk_II/FCLK \))
			((SET) (Gnd))
			((RST) (PRLD))
			((O) (\U1/U4/HE0statelastr_MC.Q \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U4/HE0statelastr_MC.REG_tsimcreated_inv_Mclk_II/FCLK_399 \ 0 6883 (_entity .  X_INV)
		(_port
			((I) (\Mclk_II/FCLK \))
			((O) (\U1/U4/HE0statelastr_MC.REG_tsimcreated_inv_Mclk_II/FCLK \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U4/HE0statelastr_MC.D_400 \ 0 6887 (_entity .  X_XOR2)
		(_port
			((I0) (\U1/U4/HE0statelastr_MC.D1 \))
			((I1) (\U1/U4/HE0statelastr_MC.D2 \))
			((O) (\U1/U4/HE0statelastr_MC.D \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U4/HE0statelastr_MC.D1_401 \ 0 6892 (_entity .  X_AND2)
		(_port
			((I0) (\U1/U4/HE0stater \))
			((I1) (\U1/U4/HE0stater \))
			((O) (\U1/U4/HE0statelastr_MC.D1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U4/HE0statelastr_MC.D2_402 \ 0 6897 (_entity .  X_ZERO)
		(_port
			((O) (\U1/U4/HE0statelastr_MC.D2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U4/E0r_403 \ 0 6900 (_entity .  X_BUF)
		(_port
			((I) (\U1/U4/E0r_MC.Q \))
			((O) (\U1/U4/E0r \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U4/E0r_MC_tsimcreated_xor__404 \ 0 6904 (_entity .  X_XOR2)
		(_port
			((I0) (\U1/U4/E0r_MC.D \))
			((I1) (\U1/U4/E0r_MC.Q \))
			((O) (\U1/U4/E0r_MC_tsimcreated_xor_ \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U4/E0r_MC.REG \ 0 6909 (_entity .  X_FF)
		(_port
			((I) (\U1/U4/E0r_MC_tsimcreated_xor_ \))
			((CE) (Vcc))
			((CLK) (\U1/U4/E0r_MC.REG_tsimcreated_inv_Mclk_II/FCLK \))
			((SET) (Gnd))
			((RST) (PRLD))
			((O) (\U1/U4/E0r_MC.Q \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U4/E0r_MC.REG_tsimcreated_inv_Mclk_II/FCLK_405 \ 0 6917 (_entity .  X_INV)
		(_port
			((I) (\Mclk_II/FCLK \))
			((O) (\U1/U4/E0r_MC.REG_tsimcreated_inv_Mclk_II/FCLK \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U4/E0r_MC.D_406 \ 0 6921 (_entity .  X_XOR2)
		(_port
			((I0) (\U1/U4/E0r_MC.D1 \))
			((I1) (\U1/U4/E0r_MC.D2 \))
			((O) (\U1/U4/E0r_MC.D \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U4/E0r_MC.D1_407 \ 0 6926 (_entity .  X_ZERO)
		(_port
			((O) (\U1/U4/E0r_MC.D1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U4/E0r_MC.D2_PT_0_408 \ 0 6929 (_entity .  X_AND2)
		(_port
			((I0) (\Reset_II/UIM \))
			((I1) (\U1/U4/E0r \))
			((O) (\U1/U4/E0r_MC.D2_PT_0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U4/E0r_MC.D2_PT_1_409 \ 0 6934 (_entity .  X_AND16)
		(_port
			((I0) (\NlwInverterSignal_U1/U4/E0r_MC.D2_PT_1/IN0 \))
			((I1) (\RD_II/UIM \))
			((I2) (U2_ADDR_reg(1)))
			((I3) (U2_ADDR_reg(0)))
			((I4) (N_PZ_931))
			((I5) (\NlwInverterSignal_U1/U4/E0r_MC.D2_PT_1/IN5 \))
			((I6) (\NlwInverterSignal_U1/U4/E0r_MC.D2_PT_1/IN6 \))
			((I7) (\NlwInverterSignal_U1/U4/E0r_MC.D2_PT_1/IN7 \))
			((I8) (\U1/U4/E0r \))
			((I9) (Vcc))
			((I10) (Vcc))
			((I11) (Vcc))
			((I12) (Vcc))
			((I13) (Vcc))
			((I14) (Vcc))
			((I15) (Vcc))
			((O) (\U1/U4/E0r_MC.D2_PT_1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U4/E0r_MC.D2_PT_2_410 \ 0 6953 (_entity .  X_AND16)
		(_port
			((I0) (\NlwInverterSignal_U1/U4/E0r_MC.D2_PT_2/IN0 \))
			((I1) (\RD_II/UIM \))
			((I2) (U2_ADDR_reg(1)))
			((I3) (U2_ADDR_reg(0)))
			((I4) (N_PZ_931))
			((I5) (\NlwInverterSignal_U1/U4/E0r_MC.D2_PT_2/IN5 \))
			((I6) (\NlwInverterSignal_U1/U4/E0r_MC.D2_PT_2/IN6 \))
			((I7) (\AD<1>_II/UIM \))
			((I8) (\NlwInverterSignal_U1/U4/E0r_MC.D2_PT_2/IN8 \))
			((I9) (\NlwInverterSignal_U1/U4/E0r_MC.D2_PT_2/IN9 \))
			((I10) (Vcc))
			((I11) (Vcc))
			((I12) (Vcc))
			((I13) (Vcc))
			((I14) (Vcc))
			((I15) (Vcc))
			((O) (\U1/U4/E0r_MC.D2_PT_2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U4/E0r_MC.D2_411 \ 0 6972 (_entity .  X_OR3)
		(_port
			((I0) (\U1/U4/E0r_MC.D2_PT_0 \))
			((I1) (\U1/U4/E0r_MC.D2_PT_1 \))
			((I2) (\U1/U4/E0r_MC.D2_PT_2 \))
			((O) (\U1/U4/E0r_MC.D2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/Channel0<0> \ 0 6978 (_entity .  X_BUF)
		(_port
			((I) (\U1/Channel0<0>_MC.Q \))
			((O) (\U1/Channel0 \(0)))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/Channel0<0>_MC.REG \ 0 6982 (_entity .  X_FF)
		(_port
			((I) (\U1/Channel0<0>_MC.D \))
			((CE) (Vcc))
			((CLK) (\Mclk_II/FCLK \))
			((SET) (Gnd))
			((RST) (PRLD))
			((O) (\U1/Channel0<0>_MC.Q \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/Channel0<0>_MC.D_412 \ 0 6990 (_entity .  X_XOR2)
		(_port
			((I0) (\U1/Channel0<0>_MC.D1 \))
			((I1) (\U1/Channel0<0>_MC.D2 \))
			((O) (\U1/Channel0<0>_MC.D \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/Channel0<0>_MC.D1_413 \ 0 6995 (_entity .  X_ZERO)
		(_port
			((O) (\U1/Channel0<0>_MC.D1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/Channel0<0>_MC.D2_PT_0_414 \ 0 6998 (_entity .  X_AND3)
		(_port
			((I0) (N_PZ_949))
			((I1) (\U1/Channel0 \(0)))
			((I2) (\NlwInverterSignal_U1/Channel0<0>_MC.D2_PT_0/IN2 \))
			((O) (\U1/Channel0<0>_MC.D2_PT_0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/Channel0<0>_MC.D2_PT_1_415 \ 0 7004 (_entity .  X_AND3)
		(_port
			((I0) (N_PZ_949))
			((I1) (\NlwInverterSignal_U1/Channel0<0>_MC.D2_PT_1/IN1 \))
			((I2) (N_PZ_1018))
			((O) (\U1/Channel0<0>_MC.D2_PT_1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/Channel0<0>_MC.D2_416 \ 0 7010 (_entity .  X_OR2)
		(_port
			((I0) (\U1/Channel0<0>_MC.D2_PT_0 \))
			((I1) (\U1/Channel0<0>_MC.D2_PT_1 \))
			((O) (\U1/Channel0<0>_MC.D2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation N_PZ_1018_417 0 7015 (_entity .  X_BUF)
		(_port
			((I) (\N_PZ_1018_MC.Q \))
			((O) (N_PZ_1018))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \N_PZ_1018_MC.Q_418 \ 0 7019 (_entity .  X_BUF)
		(_port
			((I) (\N_PZ_1018_MC.D \))
			((O) (\N_PZ_1018_MC.Q \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \N_PZ_1018_MC.D_419 \ 0 7023 (_entity .  X_XOR2)
		(_port
			((I0) (\N_PZ_1018_MC.D1 \))
			((I1) (\N_PZ_1018_MC.D2 \))
			((O) (\N_PZ_1018_MC.D \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \N_PZ_1018_MC.D1_420 \ 0 7028 (_entity .  X_ZERO)
		(_port
			((O) (\N_PZ_1018_MC.D1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \N_PZ_1018_MC.D2_PT_0_421 \ 0 7031 (_entity .  X_AND4)
		(_port
			((I0) (\U1/U1/CurrState_Sreg0_FFD3 \))
			((I1) (\NlwInverterSignal_N_PZ_1018_MC.D2_PT_0/IN1 \))
			((I2) (\U1/U1/CurrState_Sreg0_FFD4 \))
			((I3) (\NlwInverterSignal_N_PZ_1018_MC.D2_PT_0/IN3 \))
			((O) (\N_PZ_1018_MC.D2_PT_0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \N_PZ_1018_MC.D2_PT_1_422 \ 0 7038 (_entity .  X_AND4)
		(_port
			((I0) (\U1/U1/CurrState_Sreg0_FFD3 \))
			((I1) (\NlwInverterSignal_N_PZ_1018_MC.D2_PT_1/IN1 \))
			((I2) (\NlwInverterSignal_N_PZ_1018_MC.D2_PT_1/IN2 \))
			((I3) (\U1/U1/CurrState_Sreg0_FFD1 \))
			((O) (\N_PZ_1018_MC.D2_PT_1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \N_PZ_1018_MC.D2_423 \ 0 7045 (_entity .  X_OR2)
		(_port
			((I0) (\N_PZ_1018_MC.D2_PT_0 \))
			((I1) (\N_PZ_1018_MC.D2_PT_1 \))
			((O) (\N_PZ_1018_MC.D2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U1/CurrState_Sreg0_FFD3_424 \ 0 7050 (_entity .  X_BUF)
		(_port
			((I) (\U1/U1/CurrState_Sreg0_FFD3_MC.Q \))
			((O) (\U1/U1/CurrState_Sreg0_FFD3 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U1/CurrState_Sreg0_FFD3_MC.REG \ 0 7054 (_entity .  X_FF)
		(_port
			((I) (\U1/U1/CurrState_Sreg0_FFD3_MC.D \))
			((CE) (Vcc))
			((CLK) (\Mclk_II/FCLK \))
			((SET) (Gnd))
			((RST) (PRLD))
			((O) (\U1/U1/CurrState_Sreg0_FFD3_MC.Q \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U1/CurrState_Sreg0_FFD3_MC.D_425 \ 0 7062 (_entity .  X_XOR2)
		(_port
			((I0) (\U1/U1/CurrState_Sreg0_FFD3_MC.D1 \))
			((I1) (\U1/U1/CurrState_Sreg0_FFD3_MC.D2 \))
			((O) (\U1/U1/CurrState_Sreg0_FFD3_MC.D \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U1/CurrState_Sreg0_FFD3_MC.D1_426 \ 0 7067 (_entity .  X_ZERO)
		(_port
			((O) (\U1/U1/CurrState_Sreg0_FFD3_MC.D1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U1/CurrState_Sreg0_FFD3_MC.D2_PT_0_427 \ 0 7070 (_entity .  X_AND5)
		(_port
			((I0) (\NlwInverterSignal_U1/U1/CurrState_Sreg0_FFD3_MC.D2_PT_0/IN0 \))
			((I1) (\U1/U1/CurrState_Sreg0_FFD3 \))
			((I2) (\U1/U1/CurrState_Sreg0_FFD2 \))
			((I3) (\NlwInverterSignal_U1/U1/CurrState_Sreg0_FFD3_MC.D2_PT_0/IN3 \))
			((I4) (\NlwInverterSignal_U1/U1/CurrState_Sreg0_FFD3_MC.D2_PT_0/IN4 \))
			((O) (\U1/U1/CurrState_Sreg0_FFD3_MC.D2_PT_0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U1/CurrState_Sreg0_FFD3_MC.D2_PT_1_428 \ 0 7078 (_entity .  X_AND5)
		(_port
			((I0) (\NlwInverterSignal_U1/U1/CurrState_Sreg0_FFD3_MC.D2_PT_1/IN0 \))
			((I1) (\U1/U1/CurrState_Sreg0_FFD3 \))
			((I2) (\NlwInverterSignal_U1/U1/CurrState_Sreg0_FFD3_MC.D2_PT_1/IN2 \))
			((I3) (\NlwInverterSignal_U1/U1/CurrState_Sreg0_FFD3_MC.D2_PT_1/IN3 \))
			((I4) (\NlwInverterSignal_U1/U1/CurrState_Sreg0_FFD3_MC.D2_PT_1/IN4 \))
			((O) (\U1/U1/CurrState_Sreg0_FFD3_MC.D2_PT_1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U1/CurrState_Sreg0_FFD3_MC.D2_PT_2_429 \ 0 7086 (_entity .  X_AND5)
		(_port
			((I0) (\NlwInverterSignal_U1/U1/CurrState_Sreg0_FFD3_MC.D2_PT_2/IN0 \))
			((I1) (\U1/U1/CurrState_Sreg0_FFD2 \))
			((I2) (\NlwInverterSignal_U1/U1/CurrState_Sreg0_FFD3_MC.D2_PT_2/IN2 \))
			((I3) (\PhaseA_Encoder0_II/UIM \))
			((I4) (N_PZ_1183))
			((O) (\U1/U1/CurrState_Sreg0_FFD3_MC.D2_PT_2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U1/CurrState_Sreg0_FFD3_MC.D2_430 \ 0 7094 (_entity .  X_OR3)
		(_port
			((I0) (\U1/U1/CurrState_Sreg0_FFD3_MC.D2_PT_0 \))
			((I1) (\U1/U1/CurrState_Sreg0_FFD3_MC.D2_PT_1 \))
			((I2) (\U1/U1/CurrState_Sreg0_FFD3_MC.D2_PT_2 \))
			((O) (\U1/U1/CurrState_Sreg0_FFD3_MC.D2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U1/CurrState_Sreg0_FFD2_431 \ 0 7100 (_entity .  X_BUF)
		(_port
			((I) (\U1/U1/CurrState_Sreg0_FFD2_MC.Q \))
			((O) (\U1/U1/CurrState_Sreg0_FFD2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U1/CurrState_Sreg0_FFD2_MC.REG \ 0 7104 (_entity .  X_FF)
		(_port
			((I) (\U1/U1/CurrState_Sreg0_FFD2_MC.D \))
			((CE) (Vcc))
			((CLK) (\Mclk_II/FCLK \))
			((SET) (Gnd))
			((RST) (PRLD))
			((O) (\U1/U1/CurrState_Sreg0_FFD2_MC.Q \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U1/CurrState_Sreg0_FFD2_MC.D_432 \ 0 7112 (_entity .  X_XOR2)
		(_port
			((I0) (\U1/U1/CurrState_Sreg0_FFD2_MC.D1 \))
			((I1) (\U1/U1/CurrState_Sreg0_FFD2_MC.D2 \))
			((O) (\U1/U1/CurrState_Sreg0_FFD2_MC.D \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U1/CurrState_Sreg0_FFD2_MC.D1_433 \ 0 7117 (_entity .  X_ZERO)
		(_port
			((O) (\U1/U1/CurrState_Sreg0_FFD2_MC.D1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U1/CurrState_Sreg0_FFD2_MC.D2_PT_0_434 \ 0 7120 (_entity .  X_AND5)
		(_port
			((I0) (\NlwInverterSignal_U1/U1/CurrState_Sreg0_FFD2_MC.D2_PT_0/IN0 \))
			((I1) (\U1/U1/CurrState_Sreg0_FFD3 \))
			((I2) (\U1/U1/CurrState_Sreg0_FFD2 \))
			((I3) (\NlwInverterSignal_U1/U1/CurrState_Sreg0_FFD2_MC.D2_PT_0/IN3 \))
			((I4) (\NlwInverterSignal_U1/U1/CurrState_Sreg0_FFD2_MC.D2_PT_0/IN4 \))
			((O) (\U1/U1/CurrState_Sreg0_FFD2_MC.D2_PT_0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U1/CurrState_Sreg0_FFD2_MC.D2_PT_1_435 \ 0 7128 (_entity .  X_AND5)
		(_port
			((I0) (\NlwInverterSignal_U1/U1/CurrState_Sreg0_FFD2_MC.D2_PT_1/IN0 \))
			((I1) (\NlwInverterSignal_U1/U1/CurrState_Sreg0_FFD2_MC.D2_PT_1/IN1 \))
			((I2) (\U1/U1/CurrState_Sreg0_FFD2 \))
			((I3) (\NlwInverterSignal_U1/U1/CurrState_Sreg0_FFD2_MC.D2_PT_1/IN3 \))
			((I4) (N_PZ_1183))
			((O) (\U1/U1/CurrState_Sreg0_FFD2_MC.D2_PT_1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U1/CurrState_Sreg0_FFD2_MC.D2_PT_2_436 \ 0 7136 (_entity .  X_AND5)
		(_port
			((I0) (\NlwInverterSignal_U1/U1/CurrState_Sreg0_FFD2_MC.D2_PT_2/IN0 \))
			((I1) (\NlwInverterSignal_U1/U1/CurrState_Sreg0_FFD2_MC.D2_PT_2/IN1 \))
			((I2) (\NlwInverterSignal_U1/U1/CurrState_Sreg0_FFD2_MC.D2_PT_2/IN2 \))
			((I3) (\PhaseA_Encoder0_II/UIM \))
			((I4) (\NlwInverterSignal_U1/U1/CurrState_Sreg0_FFD2_MC.D2_PT_2/IN4 \))
			((O) (\U1/U1/CurrState_Sreg0_FFD2_MC.D2_PT_2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U1/CurrState_Sreg0_FFD2_MC.D2_PT_3_437 \ 0 7144 (_entity .  X_AND6)
		(_port
			((I0) (\NlwInverterSignal_U1/U1/CurrState_Sreg0_FFD2_MC.D2_PT_3/IN0 \))
			((I1) (\NlwInverterSignal_U1/U1/CurrState_Sreg0_FFD2_MC.D2_PT_3/IN1 \))
			((I2) (\U1/U1/CurrState_Sreg0_FFD3 \))
			((I3) (\NlwInverterSignal_U1/U1/CurrState_Sreg0_FFD2_MC.D2_PT_3/IN3 \))
			((I4) (\PhaseA_Encoder0_II/UIM \))
			((I5) (N_PZ_1183))
			((O) (\U1/U1/CurrState_Sreg0_FFD2_MC.D2_PT_3 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U1/CurrState_Sreg0_FFD2_MC.D2_438 \ 0 7153 (_entity .  X_OR4)
		(_port
			((I0) (\U1/U1/CurrState_Sreg0_FFD2_MC.D2_PT_0 \))
			((I1) (\U1/U1/CurrState_Sreg0_FFD2_MC.D2_PT_1 \))
			((I2) (\U1/U1/CurrState_Sreg0_FFD2_MC.D2_PT_2 \))
			((I3) (\U1/U1/CurrState_Sreg0_FFD2_MC.D2_PT_3 \))
			((O) (\U1/U1/CurrState_Sreg0_FFD2_MC.D2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U1/CurrState_Sreg0_FFD4_439 \ 0 7160 (_entity .  X_BUF)
		(_port
			((I) (\U1/U1/CurrState_Sreg0_FFD4_MC.Q \))
			((O) (\U1/U1/CurrState_Sreg0_FFD4 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U1/CurrState_Sreg0_FFD4_MC.REG \ 0 7164 (_entity .  X_FF)
		(_port
			((I) (\U1/U1/CurrState_Sreg0_FFD4_MC.D \))
			((CE) (Vcc))
			((CLK) (\Mclk_II/FCLK \))
			((SET) (Gnd))
			((RST) (PRLD))
			((O) (\U1/U1/CurrState_Sreg0_FFD4_MC.Q \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U1/CurrState_Sreg0_FFD4_MC.D_440 \ 0 7172 (_entity .  X_XOR2)
		(_port
			((I0) (\U1/U1/CurrState_Sreg0_FFD4_MC.D1 \))
			((I1) (\U1/U1/CurrState_Sreg0_FFD4_MC.D2 \))
			((O) (\U1/U1/CurrState_Sreg0_FFD4_MC.D \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U1/CurrState_Sreg0_FFD4_MC.D1_441 \ 0 7177 (_entity .  X_AND7)
		(_port
			((I0) (\NlwInverterSignal_U1/U1/CurrState_Sreg0_FFD4_MC.D1/IN0 \))
			((I1) (\U1/U1/CurrState_Sreg0_FFD3 \))
			((I2) (\NlwInverterSignal_U1/U1/CurrState_Sreg0_FFD4_MC.D1/IN2 \))
			((I3) (\NlwInverterSignal_U1/U1/CurrState_Sreg0_FFD4_MC.D1/IN3 \))
			((I4) (\NlwInverterSignal_U1/U1/CurrState_Sreg0_FFD4_MC.D1/IN4 \))
			((I5) (\NlwInverterSignal_U1/U1/CurrState_Sreg0_FFD4_MC.D1/IN5 \))
			((I6) (\NlwInverterSignal_U1/U1/CurrState_Sreg0_FFD4_MC.D1/IN6 \))
			((O) (\U1/U1/CurrState_Sreg0_FFD4_MC.D1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U1/CurrState_Sreg0_FFD4_MC.D2_442 \ 0 7187 (_entity .  X_ZERO)
		(_port
			((O) (\U1/U1/CurrState_Sreg0_FFD4_MC.D2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U1/CurrState_Sreg0_FFD1_443 \ 0 7190 (_entity .  X_BUF)
		(_port
			((I) (\U1/U1/CurrState_Sreg0_FFD1_MC.Q \))
			((O) (\U1/U1/CurrState_Sreg0_FFD1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U1/CurrState_Sreg0_FFD1_MC.REG \ 0 7194 (_entity .  X_FF)
		(_port
			((I) (\U1/U1/CurrState_Sreg0_FFD1_MC.D \))
			((CE) (Vcc))
			((CLK) (\Mclk_II/FCLK \))
			((SET) (Gnd))
			((RST) (PRLD))
			((O) (\U1/U1/CurrState_Sreg0_FFD1_MC.Q \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U1/CurrState_Sreg0_FFD1_MC.D_444 \ 0 7202 (_entity .  X_XOR2)
		(_port
			((I0) (\U1/U1/CurrState_Sreg0_FFD1_MC.D1 \))
			((I1) (\U1/U1/CurrState_Sreg0_FFD1_MC.D2 \))
			((O) (\U1/U1/CurrState_Sreg0_FFD1_MC.D \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U1/CurrState_Sreg0_FFD1_MC.D1_445 \ 0 7207 (_entity .  X_ZERO)
		(_port
			((O) (\U1/U1/CurrState_Sreg0_FFD1_MC.D1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U1/CurrState_Sreg0_FFD1_MC.D2_PT_0_446 \ 0 7210 (_entity .  X_AND4)
		(_port
			((I0) (\NlwInverterSignal_U1/U1/CurrState_Sreg0_FFD1_MC.D2_PT_0/IN0 \))
			((I1) (\U1/U1/CurrState_Sreg0_FFD2 \))
			((I2) (\NlwInverterSignal_U1/U1/CurrState_Sreg0_FFD1_MC.D2_PT_0/IN2 \))
			((I3) (\U1/U1/CurrState_Sreg0_FFD1 \))
			((O) (\U1/U1/CurrState_Sreg0_FFD1_MC.D2_PT_0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U1/CurrState_Sreg0_FFD1_MC.D2_PT_1_447 \ 0 7217 (_entity .  X_AND5)
		(_port
			((I0) (\NlwInverterSignal_U1/U1/CurrState_Sreg0_FFD1_MC.D2_PT_1/IN0 \))
			((I1) (\NlwInverterSignal_U1/U1/CurrState_Sreg0_FFD1_MC.D2_PT_1/IN1 \))
			((I2) (\NlwInverterSignal_U1/U1/CurrState_Sreg0_FFD1_MC.D2_PT_1/IN2 \))
			((I3) (\U1/U1/CurrState_Sreg0_FFD1 \))
			((I4) (\PhaseA_Encoder0_II/UIM \))
			((O) (\U1/U1/CurrState_Sreg0_FFD1_MC.D2_PT_1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U1/CurrState_Sreg0_FFD1_MC.D2_PT_2_448 \ 0 7225 (_entity .  X_AND6)
		(_port
			((I0) (\NlwInverterSignal_U1/U1/CurrState_Sreg0_FFD1_MC.D2_PT_2/IN0 \))
			((I1) (\NlwInverterSignal_U1/U1/CurrState_Sreg0_FFD1_MC.D2_PT_2/IN1 \))
			((I2) (\NlwInverterSignal_U1/U1/CurrState_Sreg0_FFD1_MC.D2_PT_2/IN2 \))
			((I3) (\NlwInverterSignal_U1/U1/CurrState_Sreg0_FFD1_MC.D2_PT_2/IN3 \))
			((I4) (\NlwInverterSignal_U1/U1/CurrState_Sreg0_FFD1_MC.D2_PT_2/IN4 \))
			((I5) (\PhaseB_Encoder0_II/UIM \))
			((O) (\U1/U1/CurrState_Sreg0_FFD1_MC.D2_PT_2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U1/CurrState_Sreg0_FFD1_MC.D2_449 \ 0 7234 (_entity .  X_OR3)
		(_port
			((I0) (\U1/U1/CurrState_Sreg0_FFD1_MC.D2_PT_0 \))
			((I1) (\U1/U1/CurrState_Sreg0_FFD1_MC.D2_PT_1 \))
			((I2) (\U1/U1/CurrState_Sreg0_FFD1_MC.D2_PT_2 \))
			((O) (\U1/U1/CurrState_Sreg0_FFD1_MC.D2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation N_PZ_1183_450 0 7240 (_entity .  X_BUF)
		(_port
			((I) (\N_PZ_1183_MC.Q \))
			((O) (N_PZ_1183))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \N_PZ_1183_MC.Q_451 \ 0 7244 (_entity .  X_BUF)
		(_port
			((I) (\N_PZ_1183_MC.D \))
			((O) (\N_PZ_1183_MC.Q \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \N_PZ_1183_MC.D_452 \ 0 7248 (_entity .  X_XOR2)
		(_port
			((I0) (\N_PZ_1183_MC.D1 \))
			((I1) (\N_PZ_1183_MC.D2 \))
			((O) (\N_PZ_1183_MC.D \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \N_PZ_1183_MC.D1_453 \ 0 7253 (_entity .  X_ZERO)
		(_port
			((O) (\N_PZ_1183_MC.D1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \N_PZ_1183_MC.D2_PT_0_454 \ 0 7256 (_entity .  X_AND2)
		(_port
			((I0) (\U1/U1/CurrState_Sreg0_FFD1 \))
			((I1) (\NlwInverterSignal_N_PZ_1183_MC.D2_PT_0/IN1 \))
			((O) (\N_PZ_1183_MC.D2_PT_0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \N_PZ_1183_MC.D2_PT_1_455 \ 0 7261 (_entity .  X_AND2)
		(_port
			((I0) (\NlwInverterSignal_N_PZ_1183_MC.D2_PT_1/IN0 \))
			((I1) (\PhaseB_Encoder0_II/UIM \))
			((O) (\N_PZ_1183_MC.D2_PT_1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \N_PZ_1183_MC.D2_456 \ 0 7266 (_entity .  X_OR2)
		(_port
			((I0) (\N_PZ_1183_MC.D2_PT_0 \))
			((I1) (\N_PZ_1183_MC.D2_PT_1 \))
			((O) (\N_PZ_1183_MC.D2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/Channel0<1> \ 0 7271 (_entity .  X_BUF)
		(_port
			((I) (\U1/Channel0<1>_MC.Q \))
			((O) (\U1/Channel0 \(1)))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/Channel0<1>_MC_tsimcreated_xor__457 \ 0 7275 (_entity .  X_XOR2)
		(_port
			((I0) (\U1/Channel0<1>_MC.D \))
			((I1) (\U1/Channel0<1>_MC.Q \))
			((O) (\U1/Channel0<1>_MC_tsimcreated_xor_ \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/Channel0<1>_MC.REG \ 0 7280 (_entity .  X_FF)
		(_port
			((I) (\U1/Channel0<1>_MC_tsimcreated_xor_ \))
			((CE) (Vcc))
			((CLK) (\Mclk_II/FCLK \))
			((SET) (Gnd))
			((RST) (PRLD))
			((O) (\U1/Channel0<1>_MC.Q \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/Channel0<1>_MC.D_458 \ 0 7288 (_entity .  X_XOR2)
		(_port
			((I0) (\U1/Channel0<1>_MC.D1 \))
			((I1) (\U1/Channel0<1>_MC.D2 \))
			((O) (\U1/Channel0<1>_MC.D \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/Channel0<1>_MC.D1_459 \ 0 7293 (_entity .  X_ZERO)
		(_port
			((O) (\U1/Channel0<1>_MC.D1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/Channel0<1>_MC.D2_PT_0_460 \ 0 7296 (_entity .  X_AND2)
		(_port
			((I0) (\NlwInverterSignal_U1/Channel0<1>_MC.D2_PT_0/IN0 \))
			((I1) (\U1/Channel0 \(1)))
			((O) (\U1/Channel0<1>_MC.D2_PT_0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/Channel0<1>_MC.D2_PT_1_461 \ 0 7301 (_entity .  X_AND4)
		(_port
			((I0) (N_PZ_949))
			((I1) (\U1/Channel0 \(0)))
			((I2) (N_PZ_1018))
			((I3) (\NlwInverterSignal_U1/Channel0<1>_MC.D2_PT_1/IN3 \))
			((O) (\U1/Channel0<1>_MC.D2_PT_1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/Channel0<1>_MC.D2_PT_2_462 \ 0 7308 (_entity .  X_AND4)
		(_port
			((I0) (N_PZ_949))
			((I1) (\NlwInverterSignal_U1/Channel0<1>_MC.D2_PT_2/IN1 \))
			((I2) (N_PZ_1018))
			((I3) (N_PZ_961))
			((O) (\U1/Channel0<1>_MC.D2_PT_2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/Channel0<1>_MC.D2_463 \ 0 7315 (_entity .  X_OR3)
		(_port
			((I0) (\U1/Channel0<1>_MC.D2_PT_0 \))
			((I1) (\U1/Channel0<1>_MC.D2_PT_1 \))
			((I2) (\U1/Channel0<1>_MC.D2_PT_2 \))
			((O) (\U1/Channel0<1>_MC.D2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation N_PZ_961_464 0 7321 (_entity .  X_BUF)
		(_port
			((I) (\N_PZ_961_MC.Q \))
			((O) (N_PZ_961))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \N_PZ_961_MC.Q_465 \ 0 7325 (_entity .  X_BUF)
		(_port
			((I) (\N_PZ_961_MC.D \))
			((O) (\N_PZ_961_MC.Q \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \N_PZ_961_MC.D_466 \ 0 7329 (_entity .  X_XOR2)
		(_port
			((I0) (\N_PZ_961_MC.D1 \))
			((I1) (\N_PZ_961_MC.D2 \))
			((O) (\N_PZ_961_MC.D \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \N_PZ_961_MC.D1_467 \ 0 7334 (_entity .  X_ZERO)
		(_port
			((O) (\N_PZ_961_MC.D1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \N_PZ_961_MC.D2_PT_0_468 \ 0 7337 (_entity .  X_AND2)
		(_port
			((I0) (\U1/U1/CurrState_Sreg0_FFD4 \))
			((I1) (\U1/NET3721 \))
			((O) (\N_PZ_961_MC.D2_PT_0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \N_PZ_961_MC.D2_PT_1_469 \ 0 7342 (_entity .  X_AND2)
		(_port
			((I0) (\NlwInverterSignal_N_PZ_961_MC.D2_PT_1/IN0 \))
			((I1) (\NlwInverterSignal_N_PZ_961_MC.D2_PT_1/IN1 \))
			((O) (\N_PZ_961_MC.D2_PT_1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \N_PZ_961_MC.D2_470 \ 0 7347 (_entity .  X_OR2)
		(_port
			((I0) (\N_PZ_961_MC.D2_PT_0 \))
			((I1) (\N_PZ_961_MC.D2_PT_1 \))
			((O) (\N_PZ_961_MC.D2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/NET3721_471 \ 0 7352 (_entity .  X_BUF)
		(_port
			((I) (\U1/NET3721_MC.Q \))
			((O) (\U1/NET3721 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/NET3721_MC_tsimcreated_xor__472 \ 0 7356 (_entity .  X_XOR2)
		(_port
			((I0) (\U1/NET3721_MC.D \))
			((I1) (\U1/NET3721_MC.Q \))
			((O) (\U1/NET3721_MC_tsimcreated_xor_ \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/NET3721_MC.REG \ 0 7361 (_entity .  X_FF)
		(_port
			((I) (\U1/NET3721_MC_tsimcreated_xor_ \))
			((CE) (Vcc))
			((CLK) (\U1/NET3721_MC.REG_tsimcreated_inv_Mclk_II/FCLK \))
			((SET) (Gnd))
			((RST) (PRLD))
			((O) (\U1/NET3721_MC.Q \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/NET3721_MC.REG_tsimcreated_inv_Mclk_II/FCLK_473 \ 0 7369 (_entity .  X_INV)
		(_port
			((I) (\Mclk_II/FCLK \))
			((O) (\U1/NET3721_MC.REG_tsimcreated_inv_Mclk_II/FCLK \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/NET3721_MC.D_474 \ 0 7373 (_entity .  X_XOR2)
		(_port
			((I0) (\U1/NET3721_MC.D1 \))
			((I1) (\U1/NET3721_MC.D2 \))
			((O) (\U1/NET3721_MC.D \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/NET3721_MC.D1_475 \ 0 7378 (_entity .  X_ZERO)
		(_port
			((O) (\U1/NET3721_MC.D1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/NET3721_MC.D2_PT_0_476 \ 0 7381 (_entity .  X_AND2)
		(_port
			((I0) (\Reset_II/UIM \))
			((I1) (\U1/NET3721 \))
			((O) (\U1/NET3721_MC.D2_PT_0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/NET3721_MC.D2_PT_1_477 \ 0 7386 (_entity .  X_AND16)
		(_port
			((I0) (\NlwInverterSignal_U1/NET3721_MC.D2_PT_1/IN0 \))
			((I1) (\RD_II/UIM \))
			((I2) (U2_ADDR_reg(1)))
			((I3) (U2_ADDR_reg(0)))
			((I4) (N_PZ_931))
			((I5) (\NlwInverterSignal_U1/NET3721_MC.D2_PT_1/IN5 \))
			((I6) (\NlwInverterSignal_U1/NET3721_MC.D2_PT_1/IN6 \))
			((I7) (\NlwInverterSignal_U1/NET3721_MC.D2_PT_1/IN7 \))
			((I8) (\U1/NET3721 \))
			((I9) (Vcc))
			((I10) (Vcc))
			((I11) (Vcc))
			((I12) (Vcc))
			((I13) (Vcc))
			((I14) (Vcc))
			((I15) (Vcc))
			((O) (\U1/NET3721_MC.D2_PT_1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/NET3721_MC.D2_PT_2_478 \ 0 7405 (_entity .  X_AND16)
		(_port
			((I0) (\NlwInverterSignal_U1/NET3721_MC.D2_PT_2/IN0 \))
			((I1) (\RD_II/UIM \))
			((I2) (U2_ADDR_reg(1)))
			((I3) (U2_ADDR_reg(0)))
			((I4) (N_PZ_931))
			((I5) (\NlwInverterSignal_U1/NET3721_MC.D2_PT_2/IN5 \))
			((I6) (\NlwInverterSignal_U1/NET3721_MC.D2_PT_2/IN6 \))
			((I7) (\NlwInverterSignal_U1/NET3721_MC.D2_PT_2/IN7 \))
			((I8) (\AD<3>_II/UIM \))
			((I9) (\NlwInverterSignal_U1/NET3721_MC.D2_PT_2/IN9 \))
			((I10) (Vcc))
			((I11) (Vcc))
			((I12) (Vcc))
			((I13) (Vcc))
			((I14) (Vcc))
			((I15) (Vcc))
			((O) (\U1/NET3721_MC.D2_PT_2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/NET3721_MC.D2_479 \ 0 7424 (_entity .  X_OR3)
		(_port
			((I0) (\U1/NET3721_MC.D2_PT_0 \))
			((I1) (\U1/NET3721_MC.D2_PT_1 \))
			((I2) (\U1/NET3721_MC.D2_PT_2 \))
			((O) (\U1/NET3721_MC.D2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/Channel0<2> \ 0 7430 (_entity .  X_BUF)
		(_port
			((I) (\U1/Channel0<2>_MC.Q \))
			((O) (\U1/Channel0 \(2)))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/Channel0<2>_MC_tsimcreated_xor__480 \ 0 7434 (_entity .  X_XOR2)
		(_port
			((I0) (\U1/Channel0<2>_MC.D \))
			((I1) (\U1/Channel0<2>_MC.Q \))
			((O) (\U1/Channel0<2>_MC_tsimcreated_xor_ \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/Channel0<2>_MC.REG \ 0 7439 (_entity .  X_FF)
		(_port
			((I) (\U1/Channel0<2>_MC_tsimcreated_xor_ \))
			((CE) (Vcc))
			((CLK) (\Mclk_II/FCLK \))
			((SET) (Gnd))
			((RST) (PRLD))
			((O) (\U1/Channel0<2>_MC.Q \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/Channel0<2>_MC.D_481 \ 0 7447 (_entity .  X_XOR2)
		(_port
			((I0) (\U1/Channel0<2>_MC.D1 \))
			((I1) (\U1/Channel0<2>_MC.D2 \))
			((O) (\U1/Channel0<2>_MC.D \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/Channel0<2>_MC.D1_482 \ 0 7452 (_entity .  X_ZERO)
		(_port
			((O) (\U1/Channel0<2>_MC.D1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/Channel0<2>_MC.D2_PT_0_483 \ 0 7455 (_entity .  X_AND2)
		(_port
			((I0) (\NlwInverterSignal_U1/Channel0<2>_MC.D2_PT_0/IN0 \))
			((I1) (\U1/Channel0 \(2)))
			((O) (\U1/Channel0<2>_MC.D2_PT_0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/Channel0<2>_MC.D2_PT_1_484 \ 0 7460 (_entity .  X_AND5)
		(_port
			((I0) (N_PZ_949))
			((I1) (\U1/Channel0 \(0)))
			((I2) (N_PZ_1018))
			((I3) (\U1/Channel0 \(1)))
			((I4) (\NlwInverterSignal_U1/Channel0<2>_MC.D2_PT_1/IN4 \))
			((O) (\U1/Channel0<2>_MC.D2_PT_1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/Channel0<2>_MC.D2_PT_2_485 \ 0 7468 (_entity .  X_AND5)
		(_port
			((I0) (N_PZ_949))
			((I1) (\NlwInverterSignal_U1/Channel0<2>_MC.D2_PT_2/IN1 \))
			((I2) (N_PZ_1018))
			((I3) (\NlwInverterSignal_U1/Channel0<2>_MC.D2_PT_2/IN3 \))
			((I4) (N_PZ_961))
			((O) (\U1/Channel0<2>_MC.D2_PT_2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/Channel0<2>_MC.D2_486 \ 0 7476 (_entity .  X_OR3)
		(_port
			((I0) (\U1/Channel0<2>_MC.D2_PT_0 \))
			((I1) (\U1/Channel0<2>_MC.D2_PT_1 \))
			((I2) (\U1/Channel0<2>_MC.D2_PT_2 \))
			((O) (\U1/Channel0<2>_MC.D2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/Channel0<3> \ 0 7482 (_entity .  X_BUF)
		(_port
			((I) (\U1/Channel0<3>_MC.Q \))
			((O) (\U1/Channel0 \(3)))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/Channel0<3>_MC_tsimcreated_xor__487 \ 0 7486 (_entity .  X_XOR2)
		(_port
			((I0) (\U1/Channel0<3>_MC.D \))
			((I1) (\U1/Channel0<3>_MC.Q \))
			((O) (\U1/Channel0<3>_MC_tsimcreated_xor_ \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/Channel0<3>_MC.REG \ 0 7491 (_entity .  X_FF)
		(_port
			((I) (\U1/Channel0<3>_MC_tsimcreated_xor_ \))
			((CE) (Vcc))
			((CLK) (\Mclk_II/FCLK \))
			((SET) (Gnd))
			((RST) (PRLD))
			((O) (\U1/Channel0<3>_MC.Q \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/Channel0<3>_MC.D_488 \ 0 7499 (_entity .  X_XOR2)
		(_port
			((I0) (\U1/Channel0<3>_MC.D1 \))
			((I1) (\U1/Channel0<3>_MC.D2 \))
			((O) (\U1/Channel0<3>_MC.D \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/Channel0<3>_MC.D1_489 \ 0 7504 (_entity .  X_ZERO)
		(_port
			((O) (\U1/Channel0<3>_MC.D1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/Channel0<3>_MC.D2_PT_0_490 \ 0 7507 (_entity .  X_AND2)
		(_port
			((I0) (\NlwInverterSignal_U1/Channel0<3>_MC.D2_PT_0/IN0 \))
			((I1) (\U1/Channel0 \(3)))
			((O) (\U1/Channel0<3>_MC.D2_PT_0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/Channel0<3>_MC.D2_PT_1_491 \ 0 7512 (_entity .  X_AND6)
		(_port
			((I0) (N_PZ_949))
			((I1) (\U1/Channel0 \(0)))
			((I2) (N_PZ_1018))
			((I3) (\U1/Channel0 \(1)))
			((I4) (\NlwInverterSignal_U1/Channel0<3>_MC.D2_PT_1/IN4 \))
			((I5) (\U1/Channel0 \(2)))
			((O) (\U1/Channel0<3>_MC.D2_PT_1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/Channel0<3>_MC.D2_PT_2_492 \ 0 7521 (_entity .  X_AND6)
		(_port
			((I0) (N_PZ_949))
			((I1) (\NlwInverterSignal_U1/Channel0<3>_MC.D2_PT_2/IN1 \))
			((I2) (N_PZ_1018))
			((I3) (\NlwInverterSignal_U1/Channel0<3>_MC.D2_PT_2/IN3 \))
			((I4) (N_PZ_961))
			((I5) (\NlwInverterSignal_U1/Channel0<3>_MC.D2_PT_2/IN5 \))
			((O) (\U1/Channel0<3>_MC.D2_PT_2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/Channel0<3>_MC.D2_493 \ 0 7530 (_entity .  X_OR3)
		(_port
			((I0) (\U1/Channel0<3>_MC.D2_PT_0 \))
			((I1) (\U1/Channel0<3>_MC.D2_PT_1 \))
			((I2) (\U1/Channel0<3>_MC.D2_PT_2 \))
			((O) (\U1/Channel0<3>_MC.D2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/Channel0<4> \ 0 7536 (_entity .  X_BUF)
		(_port
			((I) (\U1/Channel0<4>_MC.Q \))
			((O) (\U1/Channel0 \(4)))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/Channel0<4>_MC_tsimcreated_xor__494 \ 0 7540 (_entity .  X_XOR2)
		(_port
			((I0) (\U1/Channel0<4>_MC.D \))
			((I1) (\U1/Channel0<4>_MC.Q \))
			((O) (\U1/Channel0<4>_MC_tsimcreated_xor_ \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/Channel0<4>_MC.REG \ 0 7545 (_entity .  X_FF)
		(_port
			((I) (\U1/Channel0<4>_MC_tsimcreated_xor_ \))
			((CE) (Vcc))
			((CLK) (\Mclk_II/FCLK \))
			((SET) (Gnd))
			((RST) (PRLD))
			((O) (\U1/Channel0<4>_MC.Q \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/Channel0<4>_MC.D_495 \ 0 7553 (_entity .  X_XOR2)
		(_port
			((I0) (\U1/Channel0<4>_MC.D1 \))
			((I1) (\U1/Channel0<4>_MC.D2 \))
			((O) (\U1/Channel0<4>_MC.D \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/Channel0<4>_MC.D1_496 \ 0 7558 (_entity .  X_ZERO)
		(_port
			((O) (\U1/Channel0<4>_MC.D1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/Channel0<4>_MC.D2_PT_0_497 \ 0 7561 (_entity .  X_AND2)
		(_port
			((I0) (\NlwInverterSignal_U1/Channel0<4>_MC.D2_PT_0/IN0 \))
			((I1) (\U1/Channel0 \(4)))
			((O) (\U1/Channel0<4>_MC.D2_PT_0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/Channel0<4>_MC.D2_PT_1_498 \ 0 7566 (_entity .  X_AND7)
		(_port
			((I0) (N_PZ_949))
			((I1) (\U1/Channel0 \(0)))
			((I2) (N_PZ_1018))
			((I3) (\U1/Channel0 \(1)))
			((I4) (\NlwInverterSignal_U1/Channel0<4>_MC.D2_PT_1/IN4 \))
			((I5) (\U1/Channel0 \(2)))
			((I6) (\U1/Channel0 \(3)))
			((O) (\U1/Channel0<4>_MC.D2_PT_1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/Channel0<4>_MC.D2_PT_2_499 \ 0 7576 (_entity .  X_AND7)
		(_port
			((I0) (N_PZ_949))
			((I1) (\NlwInverterSignal_U1/Channel0<4>_MC.D2_PT_2/IN1 \))
			((I2) (N_PZ_1018))
			((I3) (\NlwInverterSignal_U1/Channel0<4>_MC.D2_PT_2/IN3 \))
			((I4) (N_PZ_961))
			((I5) (\NlwInverterSignal_U1/Channel0<4>_MC.D2_PT_2/IN5 \))
			((I6) (\NlwInverterSignal_U1/Channel0<4>_MC.D2_PT_2/IN6 \))
			((O) (\U1/Channel0<4>_MC.D2_PT_2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/Channel0<4>_MC.D2_500 \ 0 7586 (_entity .  X_OR3)
		(_port
			((I0) (\U1/Channel0<4>_MC.D2_PT_0 \))
			((I1) (\U1/Channel0<4>_MC.D2_PT_1 \))
			((I2) (\U1/Channel0<4>_MC.D2_PT_2 \))
			((O) (\U1/Channel0<4>_MC.D2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/Channel1<5> \ 0 7592 (_entity .  X_BUF)
		(_port
			((I) (\U1/Channel1<5>_MC.Q \))
			((O) (\U1/Channel1 \(5)))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/Channel1<5>_MC_tsimcreated_xor__501 \ 0 7596 (_entity .  X_XOR2)
		(_port
			((I0) (\U1/Channel1<5>_MC.D \))
			((I1) (\U1/Channel1<5>_MC.Q \))
			((O) (\U1/Channel1<5>_MC_tsimcreated_xor_ \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/Channel1<5>_MC.REG \ 0 7601 (_entity .  X_FF)
		(_port
			((I) (\U1/Channel1<5>_MC_tsimcreated_xor_ \))
			((CE) (Vcc))
			((CLK) (\Mclk_II/FCLK \))
			((SET) (Gnd))
			((RST) (PRLD))
			((O) (\U1/Channel1<5>_MC.Q \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/Channel1<5>_MC.D_502 \ 0 7609 (_entity .  X_XOR2)
		(_port
			((I0) (\U1/Channel1<5>_MC.D1 \))
			((I1) (\U1/Channel1<5>_MC.D2 \))
			((O) (\U1/Channel1<5>_MC.D \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/Channel1<5>_MC.D1_503 \ 0 7614 (_entity .  X_ZERO)
		(_port
			((O) (\U1/Channel1<5>_MC.D1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/Channel1<5>_MC.D2_PT_0_504 \ 0 7617 (_entity .  X_AND2)
		(_port
			((I0) (\U1/Channel1 \(5)))
			((I1) (\NlwInverterSignal_U1/Channel1<5>_MC.D2_PT_0/IN1 \))
			((O) (\U1/Channel1<5>_MC.D2_PT_0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/Channel1<5>_MC.D2_PT_1_505 \ 0 7622 (_entity .  X_AND4)
		(_port
			((I0) (N_PZ_948))
			((I1) (N_PZ_1082))
			((I2) (\NlwInverterSignal_U1/Channel1<5>_MC.D2_PT_1/IN2 \))
			((I3) (N_PZ_1226))
			((O) (\U1/Channel1<5>_MC.D2_PT_1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/Channel1<5>_MC.D2_PT_2_506 \ 0 7629 (_entity .  X_AND8)
		(_port
			((I0) (N_PZ_948))
			((I1) (N_PZ_1082))
			((I2) (N_PZ_993))
			((I3) (\NlwInverterSignal_U1/Channel1<5>_MC.D2_PT_2/IN3 \))
			((I4) (\NlwInverterSignal_U1/Channel1<5>_MC.D2_PT_2/IN4 \))
			((I5) (\NlwInverterSignal_U1/Channel1<5>_MC.D2_PT_2/IN5 \))
			((I6) (\NlwInverterSignal_U1/Channel1<5>_MC.D2_PT_2/IN6 \))
			((I7) (\NlwInverterSignal_U1/Channel1<5>_MC.D2_PT_2/IN7 \))
			((O) (\U1/Channel1<5>_MC.D2_PT_2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/Channel1<5>_MC.D2_507 \ 0 7640 (_entity .  X_OR3)
		(_port
			((I0) (\U1/Channel1<5>_MC.D2_PT_0 \))
			((I1) (\U1/Channel1<5>_MC.D2_PT_1 \))
			((I2) (\U1/Channel1<5>_MC.D2_PT_2 \))
			((O) (\U1/Channel1<5>_MC.D2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation N_PZ_948_508 0 7646 (_entity .  X_BUF)
		(_port
			((I) (\N_PZ_948_MC.Q \))
			((O) (N_PZ_948))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \N_PZ_948_MC.Q_509 \ 0 7650 (_entity .  X_BUF)
		(_port
			((I) (\N_PZ_948_MC.D \))
			((O) (\N_PZ_948_MC.Q \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \N_PZ_948_MC.D_510 \ 0 7654 (_entity .  X_XOR2)
		(_port
			((I0) (\N_PZ_948_MC.D1 \))
			((I1) (\N_PZ_948_MC.D2 \))
			((O) (\N_PZ_948_MC.D \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \N_PZ_948_MC.D1_511 \ 0 7659 (_entity .  X_AND2)
		(_port
			((I0) (\NlwInverterSignal_N_PZ_948_MC.D1/IN0 \))
			((I1) (\NlwInverterSignal_N_PZ_948_MC.D1/IN1 \))
			((O) (\N_PZ_948_MC.D1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \N_PZ_948_MC.D2_512 \ 0 7664 (_entity .  X_ZERO)
		(_port
			((O) (\N_PZ_948_MC.D2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/Zero1_513 \ 0 7667 (_entity .  X_BUF)
		(_port
			((I) (\U1/Zero1_MC.Q \))
			((O) (\U1/Zero1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/Zero1_MC.REG \ 0 7671 (_entity .  X_FF)
		(_port
			((I) (\U1/Zero1_MC.D \))
			((CE) (Vcc))
			((CLK) (\U1/Zero1_MC.REG_tsimcreated_inv_Mclk_II/FCLK \))
			((SET) (Gnd))
			((RST) (PRLD))
			((O) (\U1/Zero1_MC.Q \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/Zero1_MC.REG_tsimcreated_inv_Mclk_II/FCLK_514 \ 0 7679 (_entity .  X_INV)
		(_port
			((I) (\Mclk_II/FCLK \))
			((O) (\U1/Zero1_MC.REG_tsimcreated_inv_Mclk_II/FCLK \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/Zero1_MC.D_515 \ 0 7683 (_entity .  X_XOR2)
		(_port
			((I0) (\U1/Zero1_MC.D1 \))
			((I1) (\U1/Zero1_MC.D2 \))
			((O) (\U1/Zero1_MC.D \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/Zero1_MC.D1_516 \ 0 7688 (_entity .  X_ZERO)
		(_port
			((O) (\U1/Zero1_MC.D1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/Zero1_MC.D2_PT_0_517 \ 0 7691 (_entity .  X_AND2)
		(_port
			((I0) (N_PZ_978))
			((I1) (\U1/Zero1 \))
			((O) (\U1/Zero1_MC.D2_PT_0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/Zero1_MC.D2_PT_1_518 \ 0 7696 (_entity .  X_AND6)
		(_port
			((I0) (\NlwInverterSignal_U1/Zero1_MC.D2_PT_1/IN0 \))
			((I1) (\NlwInverterSignal_U1/Zero1_MC.D2_PT_1/IN1 \))
			((I2) (\U1/U4/RF1r \))
			((I3) (\U1/U4/E1r \))
			((I4) (\U1/U4/HE1stater \))
			((I5) (\NlwInverterSignal_U1/Zero1_MC.D2_PT_1/IN5 \))
			((O) (\U1/Zero1_MC.D2_PT_1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/Zero1_MC.D2_PT_2_519 \ 0 7705 (_entity .  X_AND6)
		(_port
			((I0) (\NlwInverterSignal_U1/Zero1_MC.D2_PT_2/IN0 \))
			((I1) (\NlwInverterSignal_U1/Zero1_MC.D2_PT_2/IN1 \))
			((I2) (\NlwInverterSignal_U1/Zero1_MC.D2_PT_2/IN2 \))
			((I3) (\U1/U4/E1r \))
			((I4) (\NlwInverterSignal_U1/Zero1_MC.D2_PT_2/IN4 \))
			((I5) (\U1/U4/HE1statelastr \))
			((O) (\U1/Zero1_MC.D2_PT_2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/Zero1_MC.D2_520 \ 0 7714 (_entity .  X_OR3)
		(_port
			((I0) (\U1/Zero1_MC.D2_PT_0 \))
			((I1) (\U1/Zero1_MC.D2_PT_1 \))
			((I2) (\U1/Zero1_MC.D2_PT_2 \))
			((O) (\U1/Zero1_MC.D2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation NET2493_521 0 7720 (_entity .  X_BUF)
		(_port
			((I) (\NET2493_MC.Q \))
			((O) (NET2493))
		)
		(_strength strong0 strong1)
	)
	(_instantiation NET2493_MC_tsimcreated_xor__522 0 7724 (_entity .  X_XOR2)
		(_port
			((I0) (\NET2493_MC.D \))
			((I1) (\NET2493_MC.Q \))
			((O) (NET2493_MC_tsimcreated_xor_))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NET2493_MC.REG \ 0 7729 (_entity .  X_FF)
		(_port
			((I) (NET2493_MC_tsimcreated_xor_))
			((CE) (Vcc))
			((CLK) (\NET2493_MC.REG_tsimcreated_inv_Mclk_II/FCLK \))
			((SET) (Gnd))
			((RST) (PRLD))
			((O) (\NET2493_MC.Q \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NET2493_MC.REG_tsimcreated_inv_Mclk_II/FCLK_523 \ 0 7737 (_entity .  X_INV)
		(_port
			((I) (\Mclk_II/FCLK \))
			((O) (\NET2493_MC.REG_tsimcreated_inv_Mclk_II/FCLK \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NET2493_MC.D_524 \ 0 7741 (_entity .  X_XOR2)
		(_port
			((I0) (\NET2493_MC.D1 \))
			((I1) (\NET2493_MC.D2 \))
			((O) (\NET2493_MC.D \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NET2493_MC.D1_525 \ 0 7746 (_entity .  X_ZERO)
		(_port
			((O) (\NET2493_MC.D1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NET2493_MC.D2_PT_0_526 \ 0 7749 (_entity .  X_AND6)
		(_port
			((I0) (\NlwInverterSignal_NET2493_MC.D2_PT_0/IN0 \))
			((I1) (\NlwInverterSignal_NET2493_MC.D2_PT_0/IN1 \))
			((I2) (\U1/U4/RF1r \))
			((I3) (\U1/U4/E1r \))
			((I4) (\U1/U4/HE1stater \))
			((I5) (\NlwInverterSignal_NET2493_MC.D2_PT_0/IN5 \))
			((O) (\NET2493_MC.D2_PT_0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NET2493_MC.D2_PT_1_527 \ 0 7758 (_entity .  X_AND6)
		(_port
			((I0) (\NlwInverterSignal_NET2493_MC.D2_PT_1/IN0 \))
			((I1) (\NlwInverterSignal_NET2493_MC.D2_PT_1/IN1 \))
			((I2) (\NlwInverterSignal_NET2493_MC.D2_PT_1/IN2 \))
			((I3) (\U1/U4/E1r \))
			((I4) (\NlwInverterSignal_NET2493_MC.D2_PT_1/IN4 \))
			((I5) (\U1/U4/HE1statelastr \))
			((O) (\NET2493_MC.D2_PT_1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NET2493_MC.D2_PT_2_528 \ 0 7767 (_entity .  X_AND16)
		(_port
			((I0) (\NlwInverterSignal_NET2493_MC.D2_PT_2/IN0 \))
			((I1) (\RD_II/UIM \))
			((I2) (U2_ADDR_reg(1)))
			((I3) (\NlwInverterSignal_NET2493_MC.D2_PT_2/IN3 \))
			((I4) (N_PZ_931))
			((I5) (\NlwInverterSignal_NET2493_MC.D2_PT_2/IN5 \))
			((I6) (\NlwInverterSignal_NET2493_MC.D2_PT_2/IN6 \))
			((I7) (\NlwInverterSignal_NET2493_MC.D2_PT_2/IN7 \))
			((I8) (\AD<3>_II/UIM \))
			((I9) (\NlwInverterSignal_NET2493_MC.D2_PT_2/IN9 \))
			((I10) (Vcc))
			((I11) (Vcc))
			((I12) (Vcc))
			((I13) (Vcc))
			((I14) (Vcc))
			((I15) (Vcc))
			((O) (\NET2493_MC.D2_PT_2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NET2493_MC.D2_PT_3_529 \ 0 7786 (_entity .  X_AND16)
		(_port
			((I0) (\NlwInverterSignal_NET2493_MC.D2_PT_3/IN0 \))
			((I1) (\RD_II/UIM \))
			((I2) (U2_ADDR_reg(1)))
			((I3) (\NlwInverterSignal_NET2493_MC.D2_PT_3/IN3 \))
			((I4) (N_PZ_931))
			((I5) (\NlwInverterSignal_NET2493_MC.D2_PT_3/IN5 \))
			((I6) (\NlwInverterSignal_NET2493_MC.D2_PT_3/IN6 \))
			((I7) (\NlwInverterSignal_NET2493_MC.D2_PT_3/IN7 \))
			((I8) (\NlwInverterSignal_NET2493_MC.D2_PT_3/IN8 \))
			((I9) (NET2493))
			((I10) (Vcc))
			((I11) (Vcc))
			((I12) (Vcc))
			((I13) (Vcc))
			((I14) (Vcc))
			((I15) (Vcc))
			((O) (\NET2493_MC.D2_PT_3 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NET2493_MC.D2_530 \ 0 7805 (_entity .  X_OR4)
		(_port
			((I0) (\NET2493_MC.D2_PT_0 \))
			((I1) (\NET2493_MC.D2_PT_1 \))
			((I2) (\NET2493_MC.D2_PT_2 \))
			((I3) (\NET2493_MC.D2_PT_3 \))
			((O) (\NET2493_MC.D2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U4/RF1r_531 \ 0 7812 (_entity .  X_BUF)
		(_port
			((I) (\U1/U4/RF1r_MC.Q \))
			((O) (\U1/U4/RF1r \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U4/RF1r_MC_tsimcreated_xor__532 \ 0 7816 (_entity .  X_XOR2)
		(_port
			((I0) (\U1/U4/RF1r_MC.D \))
			((I1) (\U1/U4/RF1r_MC.Q \))
			((O) (\U1/U4/RF1r_MC_tsimcreated_xor_ \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U4/RF1r_MC.REG \ 0 7821 (_entity .  X_FF)
		(_port
			((I) (\U1/U4/RF1r_MC_tsimcreated_xor_ \))
			((CE) (Vcc))
			((CLK) (\U1/U4/RF1r_MC.REG_tsimcreated_inv_Mclk_II/FCLK \))
			((SET) (Gnd))
			((RST) (PRLD))
			((O) (\U1/U4/RF1r_MC.Q \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U4/RF1r_MC.REG_tsimcreated_inv_Mclk_II/FCLK_533 \ 0 7829 (_entity .  X_INV)
		(_port
			((I) (\Mclk_II/FCLK \))
			((O) (\U1/U4/RF1r_MC.REG_tsimcreated_inv_Mclk_II/FCLK \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U4/RF1r_MC.D_534 \ 0 7833 (_entity .  X_XOR2)
		(_port
			((I0) (\U1/U4/RF1r_MC.D1 \))
			((I1) (\U1/U4/RF1r_MC.D2 \))
			((O) (\U1/U4/RF1r_MC.D \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U4/RF1r_MC.D1_535 \ 0 7838 (_entity .  X_ZERO)
		(_port
			((O) (\U1/U4/RF1r_MC.D1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U4/RF1r_MC.D2_PT_0_536 \ 0 7841 (_entity .  X_AND2)
		(_port
			((I0) (\Reset_II/UIM \))
			((I1) (\U1/U4/RF1r \))
			((O) (\U1/U4/RF1r_MC.D2_PT_0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U4/RF1r_MC.D2_PT_1_537 \ 0 7846 (_entity .  X_AND16)
		(_port
			((I0) (\NlwInverterSignal_U1/U4/RF1r_MC.D2_PT_1/IN0 \))
			((I1) (\RD_II/UIM \))
			((I2) (U2_ADDR_reg(1)))
			((I3) (U2_ADDR_reg(0)))
			((I4) (N_PZ_931))
			((I5) (\NlwInverterSignal_U1/U4/RF1r_MC.D2_PT_1/IN5 \))
			((I6) (\NlwInverterSignal_U1/U4/RF1r_MC.D2_PT_1/IN6 \))
			((I7) (\NlwInverterSignal_U1/U4/RF1r_MC.D2_PT_1/IN7 \))
			((I8) (\U1/U4/RF1r \))
			((I9) (Vcc))
			((I10) (Vcc))
			((I11) (Vcc))
			((I12) (Vcc))
			((I13) (Vcc))
			((I14) (Vcc))
			((I15) (Vcc))
			((O) (\U1/U4/RF1r_MC.D2_PT_1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U4/RF1r_MC.D2_PT_2_538 \ 0 7865 (_entity .  X_AND16)
		(_port
			((I0) (\NlwInverterSignal_U1/U4/RF1r_MC.D2_PT_2/IN0 \))
			((I1) (\RD_II/UIM \))
			((I2) (U2_ADDR_reg(1)))
			((I3) (U2_ADDR_reg(0)))
			((I4) (N_PZ_931))
			((I5) (\NlwInverterSignal_U1/U4/RF1r_MC.D2_PT_2/IN5 \))
			((I6) (\NlwInverterSignal_U1/U4/RF1r_MC.D2_PT_2/IN6 \))
			((I7) (\NlwInverterSignal_U1/U4/RF1r_MC.D2_PT_2/IN7 \))
			((I8) (\AD<4>_II/UIM \))
			((I9) (\NlwInverterSignal_U1/U4/RF1r_MC.D2_PT_2/IN9 \))
			((I10) (Vcc))
			((I11) (Vcc))
			((I12) (Vcc))
			((I13) (Vcc))
			((I14) (Vcc))
			((I15) (Vcc))
			((O) (\U1/U4/RF1r_MC.D2_PT_2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U4/RF1r_MC.D2_539 \ 0 7884 (_entity .  X_OR3)
		(_port
			((I0) (\U1/U4/RF1r_MC.D2_PT_0 \))
			((I1) (\U1/U4/RF1r_MC.D2_PT_1 \))
			((I2) (\U1/U4/RF1r_MC.D2_PT_2 \))
			((O) (\U1/U4/RF1r_MC.D2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U4/E1r_540 \ 0 7890 (_entity .  X_BUF)
		(_port
			((I) (\U1/U4/E1r_MC.Q \))
			((O) (\U1/U4/E1r \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U4/E1r_MC_tsimcreated_xor__541 \ 0 7894 (_entity .  X_XOR2)
		(_port
			((I0) (\U1/U4/E1r_MC.D \))
			((I1) (\U1/U4/E1r_MC.Q \))
			((O) (\U1/U4/E1r_MC_tsimcreated_xor_ \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U4/E1r_MC.REG \ 0 7899 (_entity .  X_FF)
		(_port
			((I) (\U1/U4/E1r_MC_tsimcreated_xor_ \))
			((CE) (Vcc))
			((CLK) (\U1/U4/E1r_MC.REG_tsimcreated_inv_Mclk_II/FCLK \))
			((SET) (Gnd))
			((RST) (PRLD))
			((O) (\U1/U4/E1r_MC.Q \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U4/E1r_MC.REG_tsimcreated_inv_Mclk_II/FCLK_542 \ 0 7907 (_entity .  X_INV)
		(_port
			((I) (\Mclk_II/FCLK \))
			((O) (\U1/U4/E1r_MC.REG_tsimcreated_inv_Mclk_II/FCLK \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U4/E1r_MC.D_543 \ 0 7911 (_entity .  X_XOR2)
		(_port
			((I0) (\U1/U4/E1r_MC.D1 \))
			((I1) (\U1/U4/E1r_MC.D2 \))
			((O) (\U1/U4/E1r_MC.D \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U4/E1r_MC.D1_544 \ 0 7916 (_entity .  X_ZERO)
		(_port
			((O) (\U1/U4/E1r_MC.D1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U4/E1r_MC.D2_PT_0_545 \ 0 7919 (_entity .  X_AND2)
		(_port
			((I0) (\Reset_II/UIM \))
			((I1) (\U1/U4/E1r \))
			((O) (\U1/U4/E1r_MC.D2_PT_0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U4/E1r_MC.D2_PT_1_546 \ 0 7924 (_entity .  X_AND16)
		(_port
			((I0) (\NlwInverterSignal_U1/U4/E1r_MC.D2_PT_1/IN0 \))
			((I1) (\RD_II/UIM \))
			((I2) (U2_ADDR_reg(1)))
			((I3) (U2_ADDR_reg(0)))
			((I4) (N_PZ_931))
			((I5) (\NlwInverterSignal_U1/U4/E1r_MC.D2_PT_1/IN5 \))
			((I6) (\NlwInverterSignal_U1/U4/E1r_MC.D2_PT_1/IN6 \))
			((I7) (\NlwInverterSignal_U1/U4/E1r_MC.D2_PT_1/IN7 \))
			((I8) (\U1/U4/E1r \))
			((I9) (Vcc))
			((I10) (Vcc))
			((I11) (Vcc))
			((I12) (Vcc))
			((I13) (Vcc))
			((I14) (Vcc))
			((I15) (Vcc))
			((O) (\U1/U4/E1r_MC.D2_PT_1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U4/E1r_MC.D2_PT_2_547 \ 0 7943 (_entity .  X_AND16)
		(_port
			((I0) (\NlwInverterSignal_U1/U4/E1r_MC.D2_PT_2/IN0 \))
			((I1) (\RD_II/UIM \))
			((I2) (U2_ADDR_reg(1)))
			((I3) (U2_ADDR_reg(0)))
			((I4) (N_PZ_931))
			((I5) (\NlwInverterSignal_U1/U4/E1r_MC.D2_PT_2/IN5 \))
			((I6) (\NlwInverterSignal_U1/U4/E1r_MC.D2_PT_2/IN6 \))
			((I7) (\NlwInverterSignal_U1/U4/E1r_MC.D2_PT_2/IN7 \))
			((I8) (\AD<5>_II/UIM \))
			((I9) (\NlwInverterSignal_U1/U4/E1r_MC.D2_PT_2/IN9 \))
			((I10) (Vcc))
			((I11) (Vcc))
			((I12) (Vcc))
			((I13) (Vcc))
			((I14) (Vcc))
			((I15) (Vcc))
			((O) (\U1/U4/E1r_MC.D2_PT_2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U4/E1r_MC.D2_548 \ 0 7962 (_entity .  X_OR3)
		(_port
			((I0) (\U1/U4/E1r_MC.D2_PT_0 \))
			((I1) (\U1/U4/E1r_MC.D2_PT_1 \))
			((I2) (\U1/U4/E1r_MC.D2_PT_2 \))
			((O) (\U1/U4/E1r_MC.D2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U4/HE1statelastr_549 \ 0 7968 (_entity .  X_BUF)
		(_port
			((I) (\U1/U4/HE1statelastr_MC.Q \))
			((O) (\U1/U4/HE1statelastr \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U4/HE1statelastr_MC.REG \ 0 7972 (_entity .  X_FF)
		(_port
			((I) (\U1/U4/HE1statelastr_MC.D \))
			((CE) (Vcc))
			((CLK) (\U1/U4/HE1statelastr_MC.REG_tsimcreated_inv_Mclk_II/FCLK \))
			((SET) (Gnd))
			((RST) (PRLD))
			((O) (\U1/U4/HE1statelastr_MC.Q \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U4/HE1statelastr_MC.REG_tsimcreated_inv_Mclk_II/FCLK_550 \ 0 7980 (_entity .  X_INV)
		(_port
			((I) (\Mclk_II/FCLK \))
			((O) (\U1/U4/HE1statelastr_MC.REG_tsimcreated_inv_Mclk_II/FCLK \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U4/HE1statelastr_MC.D_551 \ 0 7984 (_entity .  X_XOR2)
		(_port
			((I0) (\U1/U4/HE1statelastr_MC.D1 \))
			((I1) (\U1/U4/HE1statelastr_MC.D2 \))
			((O) (\U1/U4/HE1statelastr_MC.D \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U4/HE1statelastr_MC.D1_552 \ 0 7989 (_entity .  X_AND2)
		(_port
			((I0) (\U1/U4/HE1stater \))
			((I1) (\U1/U4/HE1stater \))
			((O) (\U1/U4/HE1statelastr_MC.D1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U4/HE1statelastr_MC.D2_553 \ 0 7994 (_entity .  X_ZERO)
		(_port
			((O) (\U1/U4/HE1statelastr_MC.D2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/Channel1<0> \ 0 7997 (_entity .  X_BUF)
		(_port
			((I) (\U1/Channel1<0>_MC.Q \))
			((O) (\U1/Channel1 \(0)))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/Channel1<0>_MC.REG \ 0 8001 (_entity .  X_FF)
		(_port
			((I) (\U1/Channel1<0>_MC.D \))
			((CE) (Vcc))
			((CLK) (\Mclk_II/FCLK \))
			((SET) (Gnd))
			((RST) (PRLD))
			((O) (\U1/Channel1<0>_MC.Q \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/Channel1<0>_MC.D_554 \ 0 8009 (_entity .  X_XOR2)
		(_port
			((I0) (\U1/Channel1<0>_MC.D1 \))
			((I1) (\U1/Channel1<0>_MC.D2 \))
			((O) (\U1/Channel1<0>_MC.D \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/Channel1<0>_MC.D1_555 \ 0 8014 (_entity .  X_ZERO)
		(_port
			((O) (\U1/Channel1<0>_MC.D1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/Channel1<0>_MC.D2_PT_0_556 \ 0 8017 (_entity .  X_AND3)
		(_port
			((I0) (N_PZ_948))
			((I1) (N_PZ_1082))
			((I2) (\NlwInverterSignal_U1/Channel1<0>_MC.D2_PT_0/IN2 \))
			((O) (\U1/Channel1<0>_MC.D2_PT_0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/Channel1<0>_MC.D2_PT_1_557 \ 0 8023 (_entity .  X_AND3)
		(_port
			((I0) (N_PZ_948))
			((I1) (\NlwInverterSignal_U1/Channel1<0>_MC.D2_PT_1/IN1 \))
			((I2) (\U1/Channel1 \(0)))
			((O) (\U1/Channel1<0>_MC.D2_PT_1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/Channel1<0>_MC.D2_558 \ 0 8029 (_entity .  X_OR2)
		(_port
			((I0) (\U1/Channel1<0>_MC.D2_PT_0 \))
			((I1) (\U1/Channel1<0>_MC.D2_PT_1 \))
			((O) (\U1/Channel1<0>_MC.D2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation N_PZ_1082_559 0 8034 (_entity .  X_BUF)
		(_port
			((I) (\N_PZ_1082_MC.Q \))
			((O) (N_PZ_1082))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \N_PZ_1082_MC.Q_560 \ 0 8038 (_entity .  X_BUF)
		(_port
			((I) (\N_PZ_1082_MC.D \))
			((O) (\N_PZ_1082_MC.Q \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \N_PZ_1082_MC.D_561 \ 0 8042 (_entity .  X_XOR2)
		(_port
			((I0) (\N_PZ_1082_MC.D1 \))
			((I1) (\N_PZ_1082_MC.D2 \))
			((O) (\N_PZ_1082_MC.D \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \N_PZ_1082_MC.D1_562 \ 0 8047 (_entity .  X_ZERO)
		(_port
			((O) (\N_PZ_1082_MC.D1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \N_PZ_1082_MC.D2_PT_0_563 \ 0 8050 (_entity .  X_AND4)
		(_port
			((I0) (\U1/U6/CurrState_Sreg0_FFD3 \))
			((I1) (\NlwInverterSignal_N_PZ_1082_MC.D2_PT_0/IN1 \))
			((I2) (\U1/U6/CurrState_Sreg0_FFD4 \))
			((I3) (\NlwInverterSignal_N_PZ_1082_MC.D2_PT_0/IN3 \))
			((O) (\N_PZ_1082_MC.D2_PT_0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \N_PZ_1082_MC.D2_PT_1_564 \ 0 8057 (_entity .  X_AND4)
		(_port
			((I0) (\U1/U6/CurrState_Sreg0_FFD3 \))
			((I1) (\NlwInverterSignal_N_PZ_1082_MC.D2_PT_1/IN1 \))
			((I2) (\NlwInverterSignal_N_PZ_1082_MC.D2_PT_1/IN2 \))
			((I3) (\U1/U6/CurrState_Sreg0_FFD1 \))
			((O) (\N_PZ_1082_MC.D2_PT_1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \N_PZ_1082_MC.D2_565 \ 0 8064 (_entity .  X_OR2)
		(_port
			((I0) (\N_PZ_1082_MC.D2_PT_0 \))
			((I1) (\N_PZ_1082_MC.D2_PT_1 \))
			((O) (\N_PZ_1082_MC.D2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U6/CurrState_Sreg0_FFD3_566 \ 0 8069 (_entity .  X_BUF)
		(_port
			((I) (\U1/U6/CurrState_Sreg0_FFD3_MC.Q \))
			((O) (\U1/U6/CurrState_Sreg0_FFD3 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U6/CurrState_Sreg0_FFD3_MC.REG \ 0 8073 (_entity .  X_FF)
		(_port
			((I) (\U1/U6/CurrState_Sreg0_FFD3_MC.D \))
			((CE) (Vcc))
			((CLK) (\Mclk_II/FCLK \))
			((SET) (Gnd))
			((RST) (PRLD))
			((O) (\U1/U6/CurrState_Sreg0_FFD3_MC.Q \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U6/CurrState_Sreg0_FFD3_MC.D_567 \ 0 8081 (_entity .  X_XOR2)
		(_port
			((I0) (\U1/U6/CurrState_Sreg0_FFD3_MC.D1 \))
			((I1) (\U1/U6/CurrState_Sreg0_FFD3_MC.D2 \))
			((O) (\U1/U6/CurrState_Sreg0_FFD3_MC.D \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U6/CurrState_Sreg0_FFD3_MC.D1_568 \ 0 8086 (_entity .  X_ZERO)
		(_port
			((O) (\U1/U6/CurrState_Sreg0_FFD3_MC.D1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U6/CurrState_Sreg0_FFD3_MC.D2_PT_0_569 \ 0 8089 (_entity .  X_AND5)
		(_port
			((I0) (\NlwInverterSignal_U1/U6/CurrState_Sreg0_FFD3_MC.D2_PT_0/IN0 \))
			((I1) (\U1/U6/CurrState_Sreg0_FFD3 \))
			((I2) (\U1/U6/CurrState_Sreg0_FFD2 \))
			((I3) (\NlwInverterSignal_U1/U6/CurrState_Sreg0_FFD3_MC.D2_PT_0/IN3 \))
			((I4) (\NlwInverterSignal_U1/U6/CurrState_Sreg0_FFD3_MC.D2_PT_0/IN4 \))
			((O) (\U1/U6/CurrState_Sreg0_FFD3_MC.D2_PT_0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U6/CurrState_Sreg0_FFD3_MC.D2_PT_1_570 \ 0 8097 (_entity .  X_AND5)
		(_port
			((I0) (\NlwInverterSignal_U1/U6/CurrState_Sreg0_FFD3_MC.D2_PT_1/IN0 \))
			((I1) (\U1/U6/CurrState_Sreg0_FFD3 \))
			((I2) (\NlwInverterSignal_U1/U6/CurrState_Sreg0_FFD3_MC.D2_PT_1/IN2 \))
			((I3) (\NlwInverterSignal_U1/U6/CurrState_Sreg0_FFD3_MC.D2_PT_1/IN3 \))
			((I4) (\NlwInverterSignal_U1/U6/CurrState_Sreg0_FFD3_MC.D2_PT_1/IN4 \))
			((O) (\U1/U6/CurrState_Sreg0_FFD3_MC.D2_PT_1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U6/CurrState_Sreg0_FFD3_MC.D2_PT_2_571 \ 0 8105 (_entity .  X_AND5)
		(_port
			((I0) (\NlwInverterSignal_U1/U6/CurrState_Sreg0_FFD3_MC.D2_PT_2/IN0 \))
			((I1) (\U1/U6/CurrState_Sreg0_FFD2 \))
			((I2) (\NlwInverterSignal_U1/U6/CurrState_Sreg0_FFD3_MC.D2_PT_2/IN2 \))
			((I3) (\PhaseA_Encoder1_II/UIM \))
			((I4) (N_PZ_1184))
			((O) (\U1/U6/CurrState_Sreg0_FFD3_MC.D2_PT_2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U6/CurrState_Sreg0_FFD3_MC.D2_572 \ 0 8113 (_entity .  X_OR3)
		(_port
			((I0) (\U1/U6/CurrState_Sreg0_FFD3_MC.D2_PT_0 \))
			((I1) (\U1/U6/CurrState_Sreg0_FFD3_MC.D2_PT_1 \))
			((I2) (\U1/U6/CurrState_Sreg0_FFD3_MC.D2_PT_2 \))
			((O) (\U1/U6/CurrState_Sreg0_FFD3_MC.D2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U6/CurrState_Sreg0_FFD2_573 \ 0 8119 (_entity .  X_BUF)
		(_port
			((I) (\U1/U6/CurrState_Sreg0_FFD2_MC.Q \))
			((O) (\U1/U6/CurrState_Sreg0_FFD2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U6/CurrState_Sreg0_FFD2_MC.REG \ 0 8123 (_entity .  X_FF)
		(_port
			((I) (\U1/U6/CurrState_Sreg0_FFD2_MC.D \))
			((CE) (Vcc))
			((CLK) (\Mclk_II/FCLK \))
			((SET) (Gnd))
			((RST) (PRLD))
			((O) (\U1/U6/CurrState_Sreg0_FFD2_MC.Q \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U6/CurrState_Sreg0_FFD2_MC.D_574 \ 0 8131 (_entity .  X_XOR2)
		(_port
			((I0) (\U1/U6/CurrState_Sreg0_FFD2_MC.D1 \))
			((I1) (\U1/U6/CurrState_Sreg0_FFD2_MC.D2 \))
			((O) (\U1/U6/CurrState_Sreg0_FFD2_MC.D \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U6/CurrState_Sreg0_FFD2_MC.D1_575 \ 0 8136 (_entity .  X_ZERO)
		(_port
			((O) (\U1/U6/CurrState_Sreg0_FFD2_MC.D1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U6/CurrState_Sreg0_FFD2_MC.D2_PT_0_576 \ 0 8139 (_entity .  X_AND5)
		(_port
			((I0) (\NlwInverterSignal_U1/U6/CurrState_Sreg0_FFD2_MC.D2_PT_0/IN0 \))
			((I1) (\U1/U6/CurrState_Sreg0_FFD3 \))
			((I2) (\U1/U6/CurrState_Sreg0_FFD2 \))
			((I3) (\NlwInverterSignal_U1/U6/CurrState_Sreg0_FFD2_MC.D2_PT_0/IN3 \))
			((I4) (\NlwInverterSignal_U1/U6/CurrState_Sreg0_FFD2_MC.D2_PT_0/IN4 \))
			((O) (\U1/U6/CurrState_Sreg0_FFD2_MC.D2_PT_0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U6/CurrState_Sreg0_FFD2_MC.D2_PT_1_577 \ 0 8147 (_entity .  X_AND5)
		(_port
			((I0) (\NlwInverterSignal_U1/U6/CurrState_Sreg0_FFD2_MC.D2_PT_1/IN0 \))
			((I1) (\NlwInverterSignal_U1/U6/CurrState_Sreg0_FFD2_MC.D2_PT_1/IN1 \))
			((I2) (\U1/U6/CurrState_Sreg0_FFD2 \))
			((I3) (\NlwInverterSignal_U1/U6/CurrState_Sreg0_FFD2_MC.D2_PT_1/IN3 \))
			((I4) (N_PZ_1184))
			((O) (\U1/U6/CurrState_Sreg0_FFD2_MC.D2_PT_1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U6/CurrState_Sreg0_FFD2_MC.D2_PT_2_578 \ 0 8155 (_entity .  X_AND5)
		(_port
			((I0) (\NlwInverterSignal_U1/U6/CurrState_Sreg0_FFD2_MC.D2_PT_2/IN0 \))
			((I1) (\NlwInverterSignal_U1/U6/CurrState_Sreg0_FFD2_MC.D2_PT_2/IN1 \))
			((I2) (\NlwInverterSignal_U1/U6/CurrState_Sreg0_FFD2_MC.D2_PT_2/IN2 \))
			((I3) (\PhaseA_Encoder1_II/UIM \))
			((I4) (\NlwInverterSignal_U1/U6/CurrState_Sreg0_FFD2_MC.D2_PT_2/IN4 \))
			((O) (\U1/U6/CurrState_Sreg0_FFD2_MC.D2_PT_2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U6/CurrState_Sreg0_FFD2_MC.D2_PT_3_579 \ 0 8163 (_entity .  X_AND6)
		(_port
			((I0) (\NlwInverterSignal_U1/U6/CurrState_Sreg0_FFD2_MC.D2_PT_3/IN0 \))
			((I1) (\NlwInverterSignal_U1/U6/CurrState_Sreg0_FFD2_MC.D2_PT_3/IN1 \))
			((I2) (\U1/U6/CurrState_Sreg0_FFD3 \))
			((I3) (\NlwInverterSignal_U1/U6/CurrState_Sreg0_FFD2_MC.D2_PT_3/IN3 \))
			((I4) (\PhaseA_Encoder1_II/UIM \))
			((I5) (N_PZ_1184))
			((O) (\U1/U6/CurrState_Sreg0_FFD2_MC.D2_PT_3 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U6/CurrState_Sreg0_FFD2_MC.D2_580 \ 0 8172 (_entity .  X_OR4)
		(_port
			((I0) (\U1/U6/CurrState_Sreg0_FFD2_MC.D2_PT_0 \))
			((I1) (\U1/U6/CurrState_Sreg0_FFD2_MC.D2_PT_1 \))
			((I2) (\U1/U6/CurrState_Sreg0_FFD2_MC.D2_PT_2 \))
			((I3) (\U1/U6/CurrState_Sreg0_FFD2_MC.D2_PT_3 \))
			((O) (\U1/U6/CurrState_Sreg0_FFD2_MC.D2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U6/CurrState_Sreg0_FFD4_581 \ 0 8179 (_entity .  X_BUF)
		(_port
			((I) (\U1/U6/CurrState_Sreg0_FFD4_MC.Q \))
			((O) (\U1/U6/CurrState_Sreg0_FFD4 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U6/CurrState_Sreg0_FFD4_MC.REG \ 0 8183 (_entity .  X_FF)
		(_port
			((I) (\U1/U6/CurrState_Sreg0_FFD4_MC.D \))
			((CE) (Vcc))
			((CLK) (\Mclk_II/FCLK \))
			((SET) (Gnd))
			((RST) (PRLD))
			((O) (\U1/U6/CurrState_Sreg0_FFD4_MC.Q \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U6/CurrState_Sreg0_FFD4_MC.D_582 \ 0 8191 (_entity .  X_XOR2)
		(_port
			((I0) (\U1/U6/CurrState_Sreg0_FFD4_MC.D1 \))
			((I1) (\U1/U6/CurrState_Sreg0_FFD4_MC.D2 \))
			((O) (\U1/U6/CurrState_Sreg0_FFD4_MC.D \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U6/CurrState_Sreg0_FFD4_MC.D1_583 \ 0 8196 (_entity .  X_AND7)
		(_port
			((I0) (\NlwInverterSignal_U1/U6/CurrState_Sreg0_FFD4_MC.D1/IN0 \))
			((I1) (\U1/U6/CurrState_Sreg0_FFD3 \))
			((I2) (\NlwInverterSignal_U1/U6/CurrState_Sreg0_FFD4_MC.D1/IN2 \))
			((I3) (\NlwInverterSignal_U1/U6/CurrState_Sreg0_FFD4_MC.D1/IN3 \))
			((I4) (\NlwInverterSignal_U1/U6/CurrState_Sreg0_FFD4_MC.D1/IN4 \))
			((I5) (\NlwInverterSignal_U1/U6/CurrState_Sreg0_FFD4_MC.D1/IN5 \))
			((I6) (\NlwInverterSignal_U1/U6/CurrState_Sreg0_FFD4_MC.D1/IN6 \))
			((O) (\U1/U6/CurrState_Sreg0_FFD4_MC.D1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U6/CurrState_Sreg0_FFD4_MC.D2_584 \ 0 8206 (_entity .  X_ZERO)
		(_port
			((O) (\U1/U6/CurrState_Sreg0_FFD4_MC.D2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U6/CurrState_Sreg0_FFD1_585 \ 0 8209 (_entity .  X_BUF)
		(_port
			((I) (\U1/U6/CurrState_Sreg0_FFD1_MC.Q \))
			((O) (\U1/U6/CurrState_Sreg0_FFD1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U6/CurrState_Sreg0_FFD1_MC.REG \ 0 8213 (_entity .  X_FF)
		(_port
			((I) (\U1/U6/CurrState_Sreg0_FFD1_MC.D \))
			((CE) (Vcc))
			((CLK) (\Mclk_II/FCLK \))
			((SET) (Gnd))
			((RST) (PRLD))
			((O) (\U1/U6/CurrState_Sreg0_FFD1_MC.Q \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U6/CurrState_Sreg0_FFD1_MC.D_586 \ 0 8221 (_entity .  X_XOR2)
		(_port
			((I0) (\U1/U6/CurrState_Sreg0_FFD1_MC.D1 \))
			((I1) (\U1/U6/CurrState_Sreg0_FFD1_MC.D2 \))
			((O) (\U1/U6/CurrState_Sreg0_FFD1_MC.D \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U6/CurrState_Sreg0_FFD1_MC.D1_587 \ 0 8226 (_entity .  X_ZERO)
		(_port
			((O) (\U1/U6/CurrState_Sreg0_FFD1_MC.D1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U6/CurrState_Sreg0_FFD1_MC.D2_PT_0_588 \ 0 8229 (_entity .  X_AND4)
		(_port
			((I0) (\NlwInverterSignal_U1/U6/CurrState_Sreg0_FFD1_MC.D2_PT_0/IN0 \))
			((I1) (\U1/U6/CurrState_Sreg0_FFD2 \))
			((I2) (\NlwInverterSignal_U1/U6/CurrState_Sreg0_FFD1_MC.D2_PT_0/IN2 \))
			((I3) (\U1/U6/CurrState_Sreg0_FFD1 \))
			((O) (\U1/U6/CurrState_Sreg0_FFD1_MC.D2_PT_0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U6/CurrState_Sreg0_FFD1_MC.D2_PT_1_589 \ 0 8236 (_entity .  X_AND5)
		(_port
			((I0) (\NlwInverterSignal_U1/U6/CurrState_Sreg0_FFD1_MC.D2_PT_1/IN0 \))
			((I1) (\NlwInverterSignal_U1/U6/CurrState_Sreg0_FFD1_MC.D2_PT_1/IN1 \))
			((I2) (\NlwInverterSignal_U1/U6/CurrState_Sreg0_FFD1_MC.D2_PT_1/IN2 \))
			((I3) (\U1/U6/CurrState_Sreg0_FFD1 \))
			((I4) (\PhaseA_Encoder1_II/UIM \))
			((O) (\U1/U6/CurrState_Sreg0_FFD1_MC.D2_PT_1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U6/CurrState_Sreg0_FFD1_MC.D2_PT_2_590 \ 0 8244 (_entity .  X_AND6)
		(_port
			((I0) (\NlwInverterSignal_U1/U6/CurrState_Sreg0_FFD1_MC.D2_PT_2/IN0 \))
			((I1) (\NlwInverterSignal_U1/U6/CurrState_Sreg0_FFD1_MC.D2_PT_2/IN1 \))
			((I2) (\NlwInverterSignal_U1/U6/CurrState_Sreg0_FFD1_MC.D2_PT_2/IN2 \))
			((I3) (\NlwInverterSignal_U1/U6/CurrState_Sreg0_FFD1_MC.D2_PT_2/IN3 \))
			((I4) (\NlwInverterSignal_U1/U6/CurrState_Sreg0_FFD1_MC.D2_PT_2/IN4 \))
			((I5) (\PhaseB_Encoder1_II/UIM \))
			((O) (\U1/U6/CurrState_Sreg0_FFD1_MC.D2_PT_2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U6/CurrState_Sreg0_FFD1_MC.D2_591 \ 0 8253 (_entity .  X_OR3)
		(_port
			((I0) (\U1/U6/CurrState_Sreg0_FFD1_MC.D2_PT_0 \))
			((I1) (\U1/U6/CurrState_Sreg0_FFD1_MC.D2_PT_1 \))
			((I2) (\U1/U6/CurrState_Sreg0_FFD1_MC.D2_PT_2 \))
			((O) (\U1/U6/CurrState_Sreg0_FFD1_MC.D2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation N_PZ_1184_592 0 8259 (_entity .  X_BUF)
		(_port
			((I) (\N_PZ_1184_MC.Q \))
			((O) (N_PZ_1184))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \N_PZ_1184_MC.Q_593 \ 0 8263 (_entity .  X_BUF)
		(_port
			((I) (\N_PZ_1184_MC.D \))
			((O) (\N_PZ_1184_MC.Q \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \N_PZ_1184_MC.D_594 \ 0 8267 (_entity .  X_XOR2)
		(_port
			((I0) (\N_PZ_1184_MC.D1 \))
			((I1) (\N_PZ_1184_MC.D2 \))
			((O) (\N_PZ_1184_MC.D \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \N_PZ_1184_MC.D1_595 \ 0 8272 (_entity .  X_ZERO)
		(_port
			((O) (\N_PZ_1184_MC.D1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \N_PZ_1184_MC.D2_PT_0_596 \ 0 8275 (_entity .  X_AND2)
		(_port
			((I0) (\U1/U6/CurrState_Sreg0_FFD1 \))
			((I1) (\NlwInverterSignal_N_PZ_1184_MC.D2_PT_0/IN1 \))
			((O) (\N_PZ_1184_MC.D2_PT_0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \N_PZ_1184_MC.D2_PT_1_597 \ 0 8280 (_entity .  X_AND2)
		(_port
			((I0) (\NlwInverterSignal_N_PZ_1184_MC.D2_PT_1/IN0 \))
			((I1) (\PhaseB_Encoder1_II/UIM \))
			((O) (\N_PZ_1184_MC.D2_PT_1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \N_PZ_1184_MC.D2_598 \ 0 8285 (_entity .  X_OR2)
		(_port
			((I0) (\N_PZ_1184_MC.D2_PT_0 \))
			((I1) (\N_PZ_1184_MC.D2_PT_1 \))
			((O) (\N_PZ_1184_MC.D2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/Channel1<1> \ 0 8290 (_entity .  X_BUF)
		(_port
			((I) (\U1/Channel1<1>_MC.Q \))
			((O) (\U1/Channel1 \(1)))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/Channel1<1>_MC_tsimcreated_xor__599 \ 0 8294 (_entity .  X_XOR2)
		(_port
			((I0) (\U1/Channel1<1>_MC.D \))
			((I1) (\U1/Channel1<1>_MC.Q \))
			((O) (\U1/Channel1<1>_MC_tsimcreated_xor_ \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/Channel1<1>_MC.REG \ 0 8299 (_entity .  X_FF)
		(_port
			((I) (\U1/Channel1<1>_MC_tsimcreated_xor_ \))
			((CE) (Vcc))
			((CLK) (\Mclk_II/FCLK \))
			((SET) (Gnd))
			((RST) (PRLD))
			((O) (\U1/Channel1<1>_MC.Q \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/Channel1<1>_MC.D_600 \ 0 8307 (_entity .  X_XOR2)
		(_port
			((I0) (\U1/Channel1<1>_MC.D1 \))
			((I1) (\U1/Channel1<1>_MC.D2 \))
			((O) (\U1/Channel1<1>_MC.D \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/Channel1<1>_MC.D1_601 \ 0 8312 (_entity .  X_ZERO)
		(_port
			((O) (\U1/Channel1<1>_MC.D1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/Channel1<1>_MC.D2_PT_0_602 \ 0 8315 (_entity .  X_AND2)
		(_port
			((I0) (\NlwInverterSignal_U1/Channel1<1>_MC.D2_PT_0/IN0 \))
			((I1) (\U1/Channel1 \(1)))
			((O) (\U1/Channel1<1>_MC.D2_PT_0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/Channel1<1>_MC.D2_PT_1_603 \ 0 8320 (_entity .  X_AND4)
		(_port
			((I0) (N_PZ_948))
			((I1) (N_PZ_1082))
			((I2) (N_PZ_993))
			((I3) (\NlwInverterSignal_U1/Channel1<1>_MC.D2_PT_1/IN3 \))
			((O) (\U1/Channel1<1>_MC.D2_PT_1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/Channel1<1>_MC.D2_PT_2_604 \ 0 8327 (_entity .  X_AND4)
		(_port
			((I0) (N_PZ_948))
			((I1) (N_PZ_1082))
			((I2) (\NlwInverterSignal_U1/Channel1<1>_MC.D2_PT_2/IN2 \))
			((I3) (\U1/Channel1 \(0)))
			((O) (\U1/Channel1<1>_MC.D2_PT_2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/Channel1<1>_MC.D2_605 \ 0 8334 (_entity .  X_OR3)
		(_port
			((I0) (\U1/Channel1<1>_MC.D2_PT_0 \))
			((I1) (\U1/Channel1<1>_MC.D2_PT_1 \))
			((I2) (\U1/Channel1<1>_MC.D2_PT_2 \))
			((O) (\U1/Channel1<1>_MC.D2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation N_PZ_993_606 0 8340 (_entity .  X_BUF)
		(_port
			((I) (\N_PZ_993_MC.Q \))
			((O) (N_PZ_993))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \N_PZ_993_MC.Q_607 \ 0 8344 (_entity .  X_BUF)
		(_port
			((I) (\N_PZ_993_MC.D \))
			((O) (\N_PZ_993_MC.Q \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \N_PZ_993_MC.D_608 \ 0 8348 (_entity .  X_XOR2)
		(_port
			((I0) (\N_PZ_993_MC.D1 \))
			((I1) (\N_PZ_993_MC.D2 \))
			((O) (\N_PZ_993_MC.D \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \N_PZ_993_MC.D1_609 \ 0 8353 (_entity .  X_ZERO)
		(_port
			((O) (\N_PZ_993_MC.D1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \N_PZ_993_MC.D2_PT_0_610 \ 0 8356 (_entity .  X_AND2)
		(_port
			((I0) (\U1/U6/CurrState_Sreg0_FFD4 \))
			((I1) (\U1/NET3720 \))
			((O) (\N_PZ_993_MC.D2_PT_0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \N_PZ_993_MC.D2_PT_1_611 \ 0 8361 (_entity .  X_AND2)
		(_port
			((I0) (\NlwInverterSignal_N_PZ_993_MC.D2_PT_1/IN0 \))
			((I1) (\NlwInverterSignal_N_PZ_993_MC.D2_PT_1/IN1 \))
			((O) (\N_PZ_993_MC.D2_PT_1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \N_PZ_993_MC.D2_612 \ 0 8366 (_entity .  X_OR2)
		(_port
			((I0) (\N_PZ_993_MC.D2_PT_0 \))
			((I1) (\N_PZ_993_MC.D2_PT_1 \))
			((O) (\N_PZ_993_MC.D2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/NET3720_613 \ 0 8371 (_entity .  X_BUF)
		(_port
			((I) (\U1/NET3720_MC.Q \))
			((O) (\U1/NET3720 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/NET3720_MC_tsimcreated_xor__614 \ 0 8375 (_entity .  X_XOR2)
		(_port
			((I0) (\U1/NET3720_MC.D \))
			((I1) (\U1/NET3720_MC.Q \))
			((O) (\U1/NET3720_MC_tsimcreated_xor_ \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/NET3720_MC.REG \ 0 8380 (_entity .  X_FF)
		(_port
			((I) (\U1/NET3720_MC_tsimcreated_xor_ \))
			((CE) (Vcc))
			((CLK) (\U1/NET3720_MC.REG_tsimcreated_inv_Mclk_II/FCLK \))
			((SET) (Gnd))
			((RST) (PRLD))
			((O) (\U1/NET3720_MC.Q \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/NET3720_MC.REG_tsimcreated_inv_Mclk_II/FCLK_615 \ 0 8388 (_entity .  X_INV)
		(_port
			((I) (\Mclk_II/FCLK \))
			((O) (\U1/NET3720_MC.REG_tsimcreated_inv_Mclk_II/FCLK \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/NET3720_MC.D_616 \ 0 8392 (_entity .  X_XOR2)
		(_port
			((I0) (\U1/NET3720_MC.D1 \))
			((I1) (\U1/NET3720_MC.D2 \))
			((O) (\U1/NET3720_MC.D \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/NET3720_MC.D1_617 \ 0 8397 (_entity .  X_ZERO)
		(_port
			((O) (\U1/NET3720_MC.D1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/NET3720_MC.D2_PT_0_618 \ 0 8400 (_entity .  X_AND2)
		(_port
			((I0) (\Reset_II/UIM \))
			((I1) (\U1/NET3720 \))
			((O) (\U1/NET3720_MC.D2_PT_0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/NET3720_MC.D2_PT_1_619 \ 0 8405 (_entity .  X_AND16)
		(_port
			((I0) (\NlwInverterSignal_U1/NET3720_MC.D2_PT_1/IN0 \))
			((I1) (\RD_II/UIM \))
			((I2) (U2_ADDR_reg(1)))
			((I3) (U2_ADDR_reg(0)))
			((I4) (N_PZ_931))
			((I5) (\NlwInverterSignal_U1/NET3720_MC.D2_PT_1/IN5 \))
			((I6) (\NlwInverterSignal_U1/NET3720_MC.D2_PT_1/IN6 \))
			((I7) (\NlwInverterSignal_U1/NET3720_MC.D2_PT_1/IN7 \))
			((I8) (\U1/NET3720 \))
			((I9) (Vcc))
			((I10) (Vcc))
			((I11) (Vcc))
			((I12) (Vcc))
			((I13) (Vcc))
			((I14) (Vcc))
			((I15) (Vcc))
			((O) (\U1/NET3720_MC.D2_PT_1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/NET3720_MC.D2_PT_2_620 \ 0 8424 (_entity .  X_AND16)
		(_port
			((I0) (\NlwInverterSignal_U1/NET3720_MC.D2_PT_2/IN0 \))
			((I1) (\RD_II/UIM \))
			((I2) (U2_ADDR_reg(1)))
			((I3) (U2_ADDR_reg(0)))
			((I4) (N_PZ_931))
			((I5) (\NlwInverterSignal_U1/NET3720_MC.D2_PT_2/IN5 \))
			((I6) (\NlwInverterSignal_U1/NET3720_MC.D2_PT_2/IN6 \))
			((I7) (\NlwInverterSignal_U1/NET3720_MC.D2_PT_2/IN7 \))
			((I8) (\AD<7>_II/UIM \))
			((I9) (\NlwInverterSignal_U1/NET3720_MC.D2_PT_2/IN9 \))
			((I10) (Vcc))
			((I11) (Vcc))
			((I12) (Vcc))
			((I13) (Vcc))
			((I14) (Vcc))
			((I15) (Vcc))
			((O) (\U1/NET3720_MC.D2_PT_2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/NET3720_MC.D2_621 \ 0 8443 (_entity .  X_OR3)
		(_port
			((I0) (\U1/NET3720_MC.D2_PT_0 \))
			((I1) (\U1/NET3720_MC.D2_PT_1 \))
			((I2) (\U1/NET3720_MC.D2_PT_2 \))
			((O) (\U1/NET3720_MC.D2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/Channel1<2> \ 0 8449 (_entity .  X_BUF)
		(_port
			((I) (\U1/Channel1<2>_MC.Q \))
			((O) (\U1/Channel1 \(2)))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/Channel1<2>_MC_tsimcreated_xor__622 \ 0 8453 (_entity .  X_XOR2)
		(_port
			((I0) (\U1/Channel1<2>_MC.D \))
			((I1) (\U1/Channel1<2>_MC.Q \))
			((O) (\U1/Channel1<2>_MC_tsimcreated_xor_ \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/Channel1<2>_MC.REG \ 0 8458 (_entity .  X_FF)
		(_port
			((I) (\U1/Channel1<2>_MC_tsimcreated_xor_ \))
			((CE) (Vcc))
			((CLK) (\Mclk_II/FCLK \))
			((SET) (Gnd))
			((RST) (PRLD))
			((O) (\U1/Channel1<2>_MC.Q \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/Channel1<2>_MC.D_623 \ 0 8466 (_entity .  X_XOR2)
		(_port
			((I0) (\U1/Channel1<2>_MC.D1 \))
			((I1) (\U1/Channel1<2>_MC.D2 \))
			((O) (\U1/Channel1<2>_MC.D \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/Channel1<2>_MC.D1_624 \ 0 8471 (_entity .  X_ZERO)
		(_port
			((O) (\U1/Channel1<2>_MC.D1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/Channel1<2>_MC.D2_PT_0_625 \ 0 8474 (_entity .  X_AND2)
		(_port
			((I0) (\NlwInverterSignal_U1/Channel1<2>_MC.D2_PT_0/IN0 \))
			((I1) (\U1/Channel1 \(2)))
			((O) (\U1/Channel1<2>_MC.D2_PT_0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/Channel1<2>_MC.D2_PT_1_626 \ 0 8479 (_entity .  X_AND5)
		(_port
			((I0) (N_PZ_948))
			((I1) (N_PZ_1082))
			((I2) (N_PZ_993))
			((I3) (\NlwInverterSignal_U1/Channel1<2>_MC.D2_PT_1/IN3 \))
			((I4) (\NlwInverterSignal_U1/Channel1<2>_MC.D2_PT_1/IN4 \))
			((O) (\U1/Channel1<2>_MC.D2_PT_1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/Channel1<2>_MC.D2_PT_2_627 \ 0 8487 (_entity .  X_AND5)
		(_port
			((I0) (N_PZ_948))
			((I1) (N_PZ_1082))
			((I2) (\NlwInverterSignal_U1/Channel1<2>_MC.D2_PT_2/IN2 \))
			((I3) (\U1/Channel1 \(0)))
			((I4) (\U1/Channel1 \(1)))
			((O) (\U1/Channel1<2>_MC.D2_PT_2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/Channel1<2>_MC.D2_628 \ 0 8495 (_entity .  X_OR3)
		(_port
			((I0) (\U1/Channel1<2>_MC.D2_PT_0 \))
			((I1) (\U1/Channel1<2>_MC.D2_PT_1 \))
			((I2) (\U1/Channel1<2>_MC.D2_PT_2 \))
			((O) (\U1/Channel1<2>_MC.D2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/Channel1<3> \ 0 8501 (_entity .  X_BUF)
		(_port
			((I) (\U1/Channel1<3>_MC.Q \))
			((O) (\U1/Channel1 \(3)))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/Channel1<3>_MC_tsimcreated_xor__629 \ 0 8505 (_entity .  X_XOR2)
		(_port
			((I0) (\U1/Channel1<3>_MC.D \))
			((I1) (\U1/Channel1<3>_MC.Q \))
			((O) (\U1/Channel1<3>_MC_tsimcreated_xor_ \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/Channel1<3>_MC.REG \ 0 8510 (_entity .  X_FF)
		(_port
			((I) (\U1/Channel1<3>_MC_tsimcreated_xor_ \))
			((CE) (Vcc))
			((CLK) (\Mclk_II/FCLK \))
			((SET) (Gnd))
			((RST) (PRLD))
			((O) (\U1/Channel1<3>_MC.Q \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/Channel1<3>_MC.D_630 \ 0 8518 (_entity .  X_XOR2)
		(_port
			((I0) (\U1/Channel1<3>_MC.D1 \))
			((I1) (\U1/Channel1<3>_MC.D2 \))
			((O) (\U1/Channel1<3>_MC.D \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/Channel1<3>_MC.D1_631 \ 0 8523 (_entity .  X_ZERO)
		(_port
			((O) (\U1/Channel1<3>_MC.D1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/Channel1<3>_MC.D2_PT_0_632 \ 0 8526 (_entity .  X_AND2)
		(_port
			((I0) (\NlwInverterSignal_U1/Channel1<3>_MC.D2_PT_0/IN0 \))
			((I1) (\U1/Channel1 \(3)))
			((O) (\U1/Channel1<3>_MC.D2_PT_0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/Channel1<3>_MC.D2_PT_1_633 \ 0 8531 (_entity .  X_AND6)
		(_port
			((I0) (N_PZ_948))
			((I1) (N_PZ_1082))
			((I2) (N_PZ_993))
			((I3) (\NlwInverterSignal_U1/Channel1<3>_MC.D2_PT_1/IN3 \))
			((I4) (\NlwInverterSignal_U1/Channel1<3>_MC.D2_PT_1/IN4 \))
			((I5) (\NlwInverterSignal_U1/Channel1<3>_MC.D2_PT_1/IN5 \))
			((O) (\U1/Channel1<3>_MC.D2_PT_1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/Channel1<3>_MC.D2_PT_2_634 \ 0 8540 (_entity .  X_AND6)
		(_port
			((I0) (N_PZ_948))
			((I1) (N_PZ_1082))
			((I2) (\NlwInverterSignal_U1/Channel1<3>_MC.D2_PT_2/IN2 \))
			((I3) (\U1/Channel1 \(0)))
			((I4) (\U1/Channel1 \(1)))
			((I5) (\U1/Channel1 \(2)))
			((O) (\U1/Channel1<3>_MC.D2_PT_2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/Channel1<3>_MC.D2_635 \ 0 8549 (_entity .  X_OR3)
		(_port
			((I0) (\U1/Channel1<3>_MC.D2_PT_0 \))
			((I1) (\U1/Channel1<3>_MC.D2_PT_1 \))
			((I2) (\U1/Channel1<3>_MC.D2_PT_2 \))
			((O) (\U1/Channel1<3>_MC.D2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/Channel1<4> \ 0 8555 (_entity .  X_BUF)
		(_port
			((I) (\U1/Channel1<4>_MC.Q \))
			((O) (\U1/Channel1 \(4)))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/Channel1<4>_MC.REG \ 0 8559 (_entity .  X_FF)
		(_port
			((I) (\U1/Channel1<4>_MC.D \))
			((CE) (Vcc))
			((CLK) (\Mclk_II/FCLK \))
			((SET) (Gnd))
			((RST) (PRLD))
			((O) (\U1/Channel1<4>_MC.Q \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/Channel1<4>_MC.D_636 \ 0 8567 (_entity .  X_XOR2)
		(_port
			((I0) (\U1/Channel1<4>_MC.D1 \))
			((I1) (\U1/Channel1<4>_MC.D2 \))
			((O) (\U1/Channel1<4>_MC.D \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/Channel1<4>_MC.D1_637 \ 0 8572 (_entity .  X_AND2)
		(_port
			((I0) (\U1/Channel1 \(4)))
			((I1) (\U1/Channel1 \(4)))
			((O) (\U1/Channel1<4>_MC.D1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/Channel1<4>_MC.D2_PT_0_638 \ 0 8577 (_entity .  X_AND2)
		(_port
			((I0) (\NlwInverterSignal_U1/Channel1<4>_MC.D2_PT_0/IN0 \))
			((I1) (\U1/Channel1 \(4)))
			((O) (\U1/Channel1<4>_MC.D2_PT_0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/Channel1<4>_MC.D2_PT_1_639 \ 0 8582 (_entity .  X_AND4)
		(_port
			((I0) (N_PZ_1082))
			((I1) (\NlwInverterSignal_U1/Channel1<4>_MC.D2_PT_1/IN1 \))
			((I2) (N_PZ_1226))
			((I3) (\U1/Channel1 \(4)))
			((O) (\U1/Channel1<4>_MC.D2_PT_1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/Channel1<4>_MC.D2_PT_2_640 \ 0 8589 (_entity .  X_AND7)
		(_port
			((I0) (N_PZ_948))
			((I1) (N_PZ_1082))
			((I2) (N_PZ_993))
			((I3) (\NlwInverterSignal_U1/Channel1<4>_MC.D2_PT_2/IN3 \))
			((I4) (\NlwInverterSignal_U1/Channel1<4>_MC.D2_PT_2/IN4 \))
			((I5) (\NlwInverterSignal_U1/Channel1<4>_MC.D2_PT_2/IN5 \))
			((I6) (\NlwInverterSignal_U1/Channel1<4>_MC.D2_PT_2/IN6 \))
			((O) (\U1/Channel1<4>_MC.D2_PT_2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/Channel1<4>_MC.D2_PT_3_641 \ 0 8599 (_entity .  X_AND16)
		(_port
			((I0) (N_PZ_948))
			((I1) (N_PZ_1082))
			((I2) (\NlwInverterSignal_U1/Channel1<4>_MC.D2_PT_3/IN2 \))
			((I3) (\NlwInverterSignal_U1/Channel1<4>_MC.D2_PT_3/IN3 \))
			((I4) (\U1/Channel1 \(0)))
			((I5) (\U1/Channel1 \(1)))
			((I6) (\U1/Channel1 \(2)))
			((I7) (\U1/Channel1 \(3)))
			((I8) (\NlwInverterSignal_U1/Channel1<4>_MC.D2_PT_3/IN8 \))
			((I9) (Vcc))
			((I10) (Vcc))
			((I11) (Vcc))
			((I12) (Vcc))
			((I13) (Vcc))
			((I14) (Vcc))
			((I15) (Vcc))
			((O) (\U1/Channel1<4>_MC.D2_PT_3 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/Channel1<4>_MC.D2_642 \ 0 8618 (_entity .  X_OR4)
		(_port
			((I0) (\U1/Channel1<4>_MC.D2_PT_0 \))
			((I1) (\U1/Channel1<4>_MC.D2_PT_1 \))
			((I2) (\U1/Channel1<4>_MC.D2_PT_2 \))
			((I3) (\U1/Channel1<4>_MC.D2_PT_3 \))
			((O) (\U1/Channel1<4>_MC.D2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation N_PZ_1226_643 0 8625 (_entity .  X_BUF)
		(_port
			((I) (\N_PZ_1226_MC.Q \))
			((O) (N_PZ_1226))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \N_PZ_1226_MC.Q_644 \ 0 8629 (_entity .  X_BUF)
		(_port
			((I) (\N_PZ_1226_MC.D \))
			((O) (\N_PZ_1226_MC.Q \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \N_PZ_1226_MC.D_645 \ 0 8633 (_entity .  X_XOR2)
		(_port
			((I0) (\N_PZ_1226_MC.D1 \))
			((I1) (\N_PZ_1226_MC.D2 \))
			((O) (\N_PZ_1226_MC.D \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \N_PZ_1226_MC.D1_646 \ 0 8638 (_entity .  X_AND5)
		(_port
			((I0) (\U1/Channel1 \(0)))
			((I1) (\U1/Channel1 \(1)))
			((I2) (\U1/Channel1 \(2)))
			((I3) (\U1/Channel1 \(3)))
			((I4) (\U1/Channel1 \(4)))
			((O) (\N_PZ_1226_MC.D1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \N_PZ_1226_MC.D2_647 \ 0 8646 (_entity .  X_ZERO)
		(_port
			((O) (\N_PZ_1226_MC.D2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation N_PZ_986_648 0 8649 (_entity .  X_BUF)
		(_port
			((I) (\N_PZ_986_MC.Q \))
			((O) (N_PZ_986))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \N_PZ_986_MC.Q_649 \ 0 8653 (_entity .  X_BUF)
		(_port
			((I) (\N_PZ_986_MC.D \))
			((O) (\N_PZ_986_MC.Q \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \N_PZ_986_MC.D_650 \ 0 8657 (_entity .  X_XOR2)
		(_port
			((I0) (\N_PZ_986_MC.D1 \))
			((I1) (\N_PZ_986_MC.D2 \))
			((O) (\N_PZ_986_MC.D \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \N_PZ_986_MC.D1_651 \ 0 8662 (_entity .  X_ZERO)
		(_port
			((O) (\N_PZ_986_MC.D1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \N_PZ_986_MC.D2_PT_0_652 \ 0 8665 (_entity .  X_AND3)
		(_port
			((I0) (\NlwInverterSignal_N_PZ_986_MC.D2_PT_0/IN0 \))
			((I1) (\NlwInverterSignal_N_PZ_986_MC.D2_PT_0/IN1 \))
			((I2) (\NlwInverterSignal_N_PZ_986_MC.D2_PT_0/IN2 \))
			((O) (\N_PZ_986_MC.D2_PT_0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \N_PZ_986_MC.D2_PT_1_653 \ 0 8671 (_entity .  X_AND3)
		(_port
			((I0) (\NlwInverterSignal_N_PZ_986_MC.D2_PT_1/IN0 \))
			((I1) (N_PZ_1002))
			((I2) (\NlwInverterSignal_N_PZ_986_MC.D2_PT_1/IN2 \))
			((O) (\N_PZ_986_MC.D2_PT_1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \N_PZ_986_MC.D2_654 \ 0 8677 (_entity .  X_OR2)
		(_port
			((I0) (\N_PZ_986_MC.D2_PT_0 \))
			((I1) (\N_PZ_986_MC.D2_PT_1 \))
			((O) (\N_PZ_986_MC.D2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation N_PZ_1002_655 0 8682 (_entity .  X_BUF)
		(_port
			((I) (\N_PZ_1002_MC.Q \))
			((O) (N_PZ_1002))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \N_PZ_1002_MC.Q_656 \ 0 8686 (_entity .  X_BUF)
		(_port
			((I) (\N_PZ_1002_MC.D \))
			((O) (\N_PZ_1002_MC.Q \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \N_PZ_1002_MC.D_657 \ 0 8690 (_entity .  X_XOR2)
		(_port
			((I0) (\N_PZ_1002_MC.D1 \))
			((I1) (\N_PZ_1002_MC.D2 \))
			((O) (\N_PZ_1002_MC.D \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \N_PZ_1002_MC.D1_658 \ 0 8695 (_entity .  X_ZERO)
		(_port
			((O) (\N_PZ_1002_MC.D1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \N_PZ_1002_MC.D2_PT_0_659 \ 0 8698 (_entity .  X_AND2)
		(_port
			((I0) (\NlwInverterSignal_N_PZ_1002_MC.D2_PT_0/IN0 \))
			((I1) (\NlwInverterSignal_N_PZ_1002_MC.D2_PT_0/IN1 \))
			((O) (\N_PZ_1002_MC.D2_PT_0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \N_PZ_1002_MC.D2_PT_1_660 \ 0 8703 (_entity .  X_AND2)
		(_port
			((I0) (U2_ADDR_reg(3)))
			((I1) (\NlwInverterSignal_N_PZ_1002_MC.D2_PT_1/IN1 \))
			((O) (\N_PZ_1002_MC.D2_PT_1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \N_PZ_1002_MC.D2_PT_2_661 \ 0 8708 (_entity .  X_AND3)
		(_port
			((I0) (U2_ADDR_reg(1)))
			((I1) (\NlwInverterSignal_N_PZ_1002_MC.D2_PT_2/IN1 \))
			((I2) (N_PZ_931))
			((O) (\N_PZ_1002_MC.D2_PT_2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \N_PZ_1002_MC.D2_662 \ 0 8714 (_entity .  X_OR3)
		(_port
			((I0) (\N_PZ_1002_MC.D2_PT_0 \))
			((I1) (\N_PZ_1002_MC.D2_PT_1 \))
			((I2) (\N_PZ_1002_MC.D2_PT_2 \))
			((O) (\N_PZ_1002_MC.D2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation N_PZ_1061_663 0 8720 (_entity .  X_BUF)
		(_port
			((I) (\N_PZ_1061_MC.Q \))
			((O) (N_PZ_1061))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \N_PZ_1061_MC.Q_664 \ 0 8724 (_entity .  X_BUF)
		(_port
			((I) (\N_PZ_1061_MC.D \))
			((O) (\N_PZ_1061_MC.Q \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \N_PZ_1061_MC.D_665 \ 0 8728 (_entity .  X_XOR2)
		(_port
			((I0) (\N_PZ_1061_MC.D1 \))
			((I1) (\N_PZ_1061_MC.D2 \))
			((O) (\N_PZ_1061_MC.D \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \N_PZ_1061_MC.D1_666 \ 0 8733 (_entity .  X_ZERO)
		(_port
			((O) (\N_PZ_1061_MC.D1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \N_PZ_1061_MC.D2_PT_0_667 \ 0 8736 (_entity .  X_AND6)
		(_port
			((I0) (\NlwInverterSignal_N_PZ_1061_MC.D2_PT_0/IN0 \))
			((I1) (U2_ADDR_reg(0)))
			((I2) (N_PZ_931))
			((I3) (U2_ADDR_reg(2)))
			((I4) (\NlwInverterSignal_N_PZ_1061_MC.D2_PT_0/IN4 \))
			((I5) (U2_Enable_AD))
			((O) (\N_PZ_1061_MC.D2_PT_0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \N_PZ_1061_MC.D2_PT_1_668 \ 0 8745 (_entity .  X_AND6)
		(_port
			((I0) (\NlwInverterSignal_N_PZ_1061_MC.D2_PT_1/IN0 \))
			((I1) (\NlwInverterSignal_N_PZ_1061_MC.D2_PT_1/IN1 \))
			((I2) (N_PZ_931))
			((I3) (\NlwInverterSignal_N_PZ_1061_MC.D2_PT_1/IN3 \))
			((I4) (U2_ADDR_reg(3)))
			((I5) (U2_Enable_AD))
			((O) (\N_PZ_1061_MC.D2_PT_1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \N_PZ_1061_MC.D2_669 \ 0 8754 (_entity .  X_OR2)
		(_port
			((I0) (\N_PZ_1061_MC.D2_PT_0 \))
			((I1) (\N_PZ_1061_MC.D2_PT_1 \))
			((O) (\N_PZ_1061_MC.D2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation N_PZ_964_670 0 8759 (_entity .  X_BUF)
		(_port
			((I) (\N_PZ_964_MC.Q \))
			((O) (N_PZ_964))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \N_PZ_964_MC.Q_671 \ 0 8763 (_entity .  X_BUF)
		(_port
			((I) (\N_PZ_964_MC.D \))
			((O) (\N_PZ_964_MC.Q \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \N_PZ_964_MC.D_672 \ 0 8767 (_entity .  X_XOR2)
		(_port
			((I0) (\N_PZ_964_MC.D1 \))
			((I1) (\N_PZ_964_MC.D2 \))
			((O) (\N_PZ_964_MC.D \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \N_PZ_964_MC.D1_673 \ 0 8772 (_entity .  X_ZERO)
		(_port
			((O) (\N_PZ_964_MC.D1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \N_PZ_964_MC.D2_PT_0_674 \ 0 8775 (_entity .  X_AND4)
		(_port
			((I0) (N_PZ_931))
			((I1) (U2_ADDR_reg(2)))
			((I2) (\NlwInverterSignal_N_PZ_964_MC.D2_PT_0/IN2 \))
			((I3) (U2_Enable_AD))
			((O) (\N_PZ_964_MC.D2_PT_0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \N_PZ_964_MC.D2_PT_1_675 \ 0 8782 (_entity .  X_AND5)
		(_port
			((I0) (\NlwInverterSignal_N_PZ_964_MC.D2_PT_1/IN0 \))
			((I1) (N_PZ_931))
			((I2) (\NlwInverterSignal_N_PZ_964_MC.D2_PT_1/IN2 \))
			((I3) (U2_ADDR_reg(3)))
			((I4) (U2_Enable_AD))
			((O) (\N_PZ_964_MC.D2_PT_1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \N_PZ_964_MC.D2_676 \ 0 8790 (_entity .  X_OR2)
		(_port
			((I0) (\N_PZ_964_MC.D2_PT_0 \))
			((I1) (\N_PZ_964_MC.D2_PT_1 \))
			((O) (\N_PZ_964_MC.D2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U3/holdingreg<21> \ 0 8795 (_entity .  X_BUF)
		(_port
			((I) (\U1/U3/holdingreg<21>_MC.Q \))
			((O) (\U1/U3/holdingreg \(21)))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U3/holdingreg<21>_MC.REG \ 0 8799 (_entity .  X_FF)
		(_port
			((I) (\U1/U3/holdingreg<21>_MC.D \))
			((CE) (Vcc))
			((CLK) (\U1/U3/holdingreg<21>_MC.REG_tsimcreated_inv_Mclk_II/FCLK \))
			((SET) (Gnd))
			((RST) (PRLD))
			((O) (\U1/U3/holdingreg<21>_MC.Q \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U3/holdingreg<21>_MC.REG_tsimcreated_inv_Mclk_II/FCLK_677 \ 0 8807 (_entity .  X_INV)
		(_port
			((I) (\Mclk_II/FCLK \))
			((O) (\U1/U3/holdingreg<21>_MC.REG_tsimcreated_inv_Mclk_II/FCLK \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U3/holdingreg<21>_MC.D_678 \ 0 8811 (_entity .  X_XOR2)
		(_port
			((I0) (\U1/U3/holdingreg<21>_MC.D1 \))
			((I1) (\U1/U3/holdingreg<21>_MC.D2 \))
			((O) (\U1/U3/holdingreg<21>_MC.D \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U3/holdingreg<21>_MC.D1_679 \ 0 8816 (_entity .  X_ZERO)
		(_port
			((O) (\U1/U3/holdingreg<21>_MC.D1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U3/holdingreg<21>_MC.D2_PT_0_680 \ 0 8819 (_entity .  X_AND2)
		(_port
			((I0) (N_PZ_986))
			((I1) (\U1/Channel1 \(21)))
			((O) (\U1/U3/holdingreg<21>_MC.D2_PT_0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U3/holdingreg<21>_MC.D2_PT_1_681 \ 0 8824 (_entity .  X_AND3)
		(_port
			((I0) (\NlwInverterSignal_U1/U3/holdingreg<21>_MC.D2_PT_1/IN0 \))
			((I1) (\U1/U3/holdingreg \(21)))
			((I2) (\U1/U3/RDedge \))
			((O) (\U1/U3/holdingreg<21>_MC.D2_PT_1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U3/holdingreg<21>_MC.D2_PT_2_682 \ 0 8830 (_entity .  X_AND16)
		(_port
			((I0) (\WR_II/UIM \))
			((I1) (\NlwInverterSignal_U1/U3/holdingreg<21>_MC.D2_PT_2/IN1 \))
			((I2) (U2_ADDR_reg(1)))
			((I3) (U2_ADDR_reg(0)))
			((I4) (N_PZ_931))
			((I5) (U2_ADDR_reg(2)))
			((I6) (\NlwInverterSignal_U1/U3/holdingreg<21>_MC.D2_PT_2/IN6 \))
			((I7) (\NlwInverterSignal_U1/U3/holdingreg<21>_MC.D2_PT_2/IN7 \))
			((I8) (\NlwInverterSignal_U1/U3/holdingreg<21>_MC.D2_PT_2/IN8 \))
			((I9) (\U1/Channel0 \(21)))
			((I10) (Vcc))
			((I11) (Vcc))
			((I12) (Vcc))
			((I13) (Vcc))
			((I14) (Vcc))
			((I15) (Vcc))
			((O) (\U1/U3/holdingreg<21>_MC.D2_PT_2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U3/holdingreg<21>_MC.D2_683 \ 0 8849 (_entity .  X_OR3)
		(_port
			((I0) (\U1/U3/holdingreg<21>_MC.D2_PT_0 \))
			((I1) (\U1/U3/holdingreg<21>_MC.D2_PT_1 \))
			((I2) (\U1/U3/holdingreg<21>_MC.D2_PT_2 \))
			((O) (\U1/U3/holdingreg<21>_MC.D2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/Channel0<21> \ 0 8855 (_entity .  X_BUF)
		(_port
			((I) (\U1/Channel0<21>_MC.Q \))
			((O) (\U1/Channel0 \(21)))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/Channel0<21>_MC_tsimcreated_xor__684 \ 0 8859 (_entity .  X_XOR2)
		(_port
			((I0) (\U1/Channel0<21>_MC.D \))
			((I1) (\U1/Channel0<21>_MC.Q \))
			((O) (\U1/Channel0<21>_MC_tsimcreated_xor_ \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/Channel0<21>_MC.REG \ 0 8864 (_entity .  X_FF)
		(_port
			((I) (\U1/Channel0<21>_MC_tsimcreated_xor_ \))
			((CE) (Vcc))
			((CLK) (\Mclk_II/FCLK \))
			((SET) (Gnd))
			((RST) (PRLD))
			((O) (\U1/Channel0<21>_MC.Q \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/Channel0<21>_MC.D_685 \ 0 8872 (_entity .  X_XOR2)
		(_port
			((I0) (\U1/Channel0<21>_MC.D1 \))
			((I1) (\U1/Channel0<21>_MC.D2 \))
			((O) (\U1/Channel0<21>_MC.D \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/Channel0<21>_MC.D1_686 \ 0 8877 (_entity .  X_ZERO)
		(_port
			((O) (\U1/Channel0<21>_MC.D1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/Channel0<21>_MC.D2_PT_0_687 \ 0 8880 (_entity .  X_AND2)
		(_port
			((I0) (\NlwInverterSignal_U1/Channel0<21>_MC.D2_PT_0/IN0 \))
			((I1) (\U1/Channel0 \(21)))
			((O) (\U1/Channel0<21>_MC.D2_PT_0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/Channel0<21>_MC.D2_PT_1_688 \ 0 8885 (_entity .  X_AND16)
		(_port
			((I0) (N_PZ_949))
			((I1) (N_PZ_1018))
			((I2) (N_PZ_961))
			((I3) (\NlwInverterSignal_U1/Channel0<21>_MC.D2_PT_1/IN3 \))
			((I4) (\U1/U2/location_Maddsub__n0000__n0115 \(0)))
			((I5) (\NlwInverterSignal_U1/Channel0<21>_MC.D2_PT_1/IN5 \))
			((I6) (\NlwInverterSignal_U1/Channel0<21>_MC.D2_PT_1/IN6 \))
			((I7) (\NlwInverterSignal_U1/Channel0<21>_MC.D2_PT_1/IN7 \))
			((I8) (\NlwInverterSignal_U1/Channel0<21>_MC.D2_PT_1/IN8 \))
			((I9) (\NlwInverterSignal_U1/Channel0<21>_MC.D2_PT_1/IN9 \))
			((I10) (\NlwInverterSignal_U1/Channel0<21>_MC.D2_PT_1/IN10 \))
			((I11) (\NlwInverterSignal_U1/Channel0<21>_MC.D2_PT_1/IN11 \))
			((I12) (Vcc))
			((I13) (Vcc))
			((I14) (Vcc))
			((I15) (Vcc))
			((O) (\U1/Channel0<21>_MC.D2_PT_1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/Channel0<21>_MC.D2_PT_2_689 \ 0 8904 (_entity .  X_AND16)
		(_port
			((I0) (N_PZ_949))
			((I1) (N_PZ_1018))
			((I2) (\NlwInverterSignal_U1/Channel0<21>_MC.D2_PT_2/IN2 \))
			((I3) (\U1/Channel0 \(13)))
			((I4) (\NlwInverterSignal_U1/Channel0<21>_MC.D2_PT_2/IN4 \))
			((I5) (\U1/Channel0 \(14)))
			((I6) (\U1/Channel0 \(15)))
			((I7) (\U1/Channel0 \(16)))
			((I8) (\U1/Channel0 \(17)))
			((I9) (\U1/Channel0 \(18)))
			((I10) (\U1/Channel0 \(19)))
			((I11) (\U1/Channel0 \(20)))
			((I12) (Vcc))
			((I13) (Vcc))
			((I14) (Vcc))
			((I15) (Vcc))
			((O) (\U1/Channel0<21>_MC.D2_PT_2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/Channel0<21>_MC.D2_690 \ 0 8923 (_entity .  X_OR3)
		(_port
			((I0) (\U1/Channel0<21>_MC.D2_PT_0 \))
			((I1) (\U1/Channel0<21>_MC.D2_PT_1 \))
			((I2) (\U1/Channel0<21>_MC.D2_PT_2 \))
			((O) (\U1/Channel0<21>_MC.D2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/Channel0<13> \ 0 8929 (_entity .  X_BUF)
		(_port
			((I) (\U1/Channel0<13>_MC.Q \))
			((O) (\U1/Channel0 \(13)))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/Channel0<13>_MC_tsimcreated_xor__691 \ 0 8933 (_entity .  X_XOR2)
		(_port
			((I0) (\U1/Channel0<13>_MC.D \))
			((I1) (\U1/Channel0<13>_MC.Q \))
			((O) (\U1/Channel0<13>_MC_tsimcreated_xor_ \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/Channel0<13>_MC.REG \ 0 8938 (_entity .  X_FF)
		(_port
			((I) (\U1/Channel0<13>_MC_tsimcreated_xor_ \))
			((CE) (Vcc))
			((CLK) (\Mclk_II/FCLK \))
			((SET) (Gnd))
			((RST) (PRLD))
			((O) (\U1/Channel0<13>_MC.Q \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/Channel0<13>_MC.D_692 \ 0 8946 (_entity .  X_XOR2)
		(_port
			((I0) (\U1/Channel0<13>_MC.D1 \))
			((I1) (\U1/Channel0<13>_MC.D2 \))
			((O) (\U1/Channel0<13>_MC.D \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/Channel0<13>_MC.D1_693 \ 0 8951 (_entity .  X_ZERO)
		(_port
			((O) (\U1/Channel0<13>_MC.D1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/Channel0<13>_MC.D2_PT_0_694 \ 0 8954 (_entity .  X_AND2)
		(_port
			((I0) (\NlwInverterSignal_U1/Channel0<13>_MC.D2_PT_0/IN0 \))
			((I1) (\U1/Channel0 \(13)))
			((O) (\U1/Channel0<13>_MC.D2_PT_0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/Channel0<13>_MC.D2_PT_1_695 \ 0 8959 (_entity .  X_AND4)
		(_port
			((I0) (N_PZ_949))
			((I1) (N_PZ_1018))
			((I2) (N_PZ_961))
			((I3) (\U1/U2/location_Maddsub__n0000__n0115 \(0)))
			((O) (\U1/Channel0<13>_MC.D2_PT_1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/Channel0<13>_MC.D2_PT_2_696 \ 0 8966 (_entity .  X_AND4)
		(_port
			((I0) (N_PZ_949))
			((I1) (N_PZ_1018))
			((I2) (\NlwInverterSignal_U1/Channel0<13>_MC.D2_PT_2/IN2 \))
			((I3) (\NlwInverterSignal_U1/Channel0<13>_MC.D2_PT_2/IN3 \))
			((O) (\U1/Channel0<13>_MC.D2_PT_2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/Channel0<13>_MC.D2_697 \ 0 8973 (_entity .  X_OR3)
		(_port
			((I0) (\U1/Channel0<13>_MC.D2_PT_0 \))
			((I1) (\U1/Channel0<13>_MC.D2_PT_1 \))
			((I2) (\U1/Channel0<13>_MC.D2_PT_2 \))
			((O) (\U1/Channel0<13>_MC.D2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U2/location_Maddsub__n0000__n0115<0> \ 0 8979 (_entity .  X_BUF)
		(_port
			((I) (\U1/U2/location_Maddsub__n0000__n0115<0>_MC.Q \))
			((O) (\U1/U2/location_Maddsub__n0000__n0115 \(0)))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U2/location_Maddsub__n0000__n0115<0>_MC.Q_698 \ 0 8983 (_entity .  X_BUF)
		(_port
			((I) (\U1/U2/location_Maddsub__n0000__n0115<0>_MC.D \))
			((O) (\U1/U2/location_Maddsub__n0000__n0115<0>_MC.Q \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U2/location_Maddsub__n0000__n0115<0>_MC.D_699 \ 0 8987 (_entity .  X_XOR2)
		(_port
			((I0) (\U1/U2/location_Maddsub__n0000__n0115<0>_MC.D1 \))
			((I1) (\U1/U2/location_Maddsub__n0000__n0115<0>_MC.D2 \))
			((O) (\U1/U2/location_Maddsub__n0000__n0115<0>_MC.D \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U2/location_Maddsub__n0000__n0115<0>_MC.D1_700 \ 0 8992 (_entity .  X_AND2)
		(_port
			((I0) (N_PZ_967))
			((I1) (N_PZ_967))
			((O) (\U1/U2/location_Maddsub__n0000__n0115<0>_MC.D1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U2/location_Maddsub__n0000__n0115<0>_MC.D2_PT_0_701 \ 0 8997 (_entity .  X_AND8)
		(_port
			((I0) (N_PZ_967))
			((I1) (\U1/Channel0 \(10)))
			((I2) (\U1/Channel0 \(7)))
			((I3) (\NlwInverterSignal_U1/U2/location_Maddsub__n0000__n0115<0>_MC.D2_PT_0/IN3 \))
			((I4) (\U1/Channel0 \(8)))
			((I5) (\U1/Channel0 \(9)))
			((I6) (\U1/Channel0 \(11)))
			((I7) (\U1/Channel0 \(12)))
			((O) (\U1/U2/location_Maddsub__n0000__n0115<0>_MC.D2_PT_0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U2/location_Maddsub__n0000__n0115<0>_MC.D2_PT_1_702 \ 0 9008 (_entity .  X_AND8)
		(_port
			((I0) (\NlwInverterSignal_U1/U2/location_Maddsub__n0000__n0115<0>_MC.D2_PT_1/IN0 \))
			((I1) (\NlwInverterSignal_U1/U2/location_Maddsub__n0000__n0115<0>_MC.D2_PT_1/IN1 \))
			((I2) (\NlwInverterSignal_U1/U2/location_Maddsub__n0000__n0115<0>_MC.D2_PT_1/IN2 \))
			((I3) (\U1/U2/location_Maddsub__n0000__n0103 \(0)))
			((I4) (\NlwInverterSignal_U1/U2/location_Maddsub__n0000__n0115<0>_MC.D2_PT_1/IN4 \))
			((I5) (\NlwInverterSignal_U1/U2/location_Maddsub__n0000__n0115<0>_MC.D2_PT_1/IN5 \))
			((I6) (\NlwInverterSignal_U1/U2/location_Maddsub__n0000__n0115<0>_MC.D2_PT_1/IN6 \))
			((I7) (\NlwInverterSignal_U1/U2/location_Maddsub__n0000__n0115<0>_MC.D2_PT_1/IN7 \))
			((O) (\U1/U2/location_Maddsub__n0000__n0115<0>_MC.D2_PT_1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U2/location_Maddsub__n0000__n0115<0>_MC.D2_703 \ 0 9019 (_entity .  X_OR2)
		(_port
			((I0) (\U1/U2/location_Maddsub__n0000__n0115<0>_MC.D2_PT_0 \))
			((I1) (\U1/U2/location_Maddsub__n0000__n0115<0>_MC.D2_PT_1 \))
			((O) (\U1/U2/location_Maddsub__n0000__n0115<0>_MC.D2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation N_PZ_967_704 0 9024 (_entity .  X_BUF)
		(_port
			((I) (\N_PZ_967_MC.Q \))
			((O) (N_PZ_967))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \N_PZ_967_MC.Q_705 \ 0 9028 (_entity .  X_BUF)
		(_port
			((I) (\N_PZ_967_MC.D \))
			((O) (\N_PZ_967_MC.Q \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \N_PZ_967_MC.D_706 \ 0 9032 (_entity .  X_XOR2)
		(_port
			((I0) (\N_PZ_967_MC.D1 \))
			((I1) (\N_PZ_967_MC.D2 \))
			((O) (\N_PZ_967_MC.D \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \N_PZ_967_MC.D1_707 \ 0 9037 (_entity .  X_ZERO)
		(_port
			((O) (\N_PZ_967_MC.D1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \N_PZ_967_MC.D2_PT_0_708 \ 0 9040 (_entity .  X_AND2)
		(_port
			((I0) (\U1/U1/CurrState_Sreg0_FFD1 \))
			((I1) (\U1/NET3721 \))
			((O) (\N_PZ_967_MC.D2_PT_0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \N_PZ_967_MC.D2_PT_1_709 \ 0 9045 (_entity .  X_AND3)
		(_port
			((I0) (N_PZ_961))
			((I1) (\U1/U1/CurrState_Sreg0_FFD2 \))
			((I2) (\NlwInverterSignal_N_PZ_967_MC.D2_PT_1/IN2 \))
			((O) (\N_PZ_967_MC.D2_PT_1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \N_PZ_967_MC.D2_PT_2_710 \ 0 9051 (_entity .  X_AND3)
		(_port
			((I0) (\NlwInverterSignal_N_PZ_967_MC.D2_PT_2/IN0 \))
			((I1) (\NlwInverterSignal_N_PZ_967_MC.D2_PT_2/IN1 \))
			((I2) (\U1/NET3721 \))
			((O) (\N_PZ_967_MC.D2_PT_2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \N_PZ_967_MC.D2_PT_3_711 \ 0 9057 (_entity .  X_AND4)
		(_port
			((I0) (\U1/U1/CurrState_Sreg0_FFD3 \))
			((I1) (\NlwInverterSignal_N_PZ_967_MC.D2_PT_3/IN1 \))
			((I2) (\NlwInverterSignal_N_PZ_967_MC.D2_PT_3/IN2 \))
			((I3) (\NlwInverterSignal_N_PZ_967_MC.D2_PT_3/IN3 \))
			((O) (\N_PZ_967_MC.D2_PT_3 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \N_PZ_967_MC.D2_712 \ 0 9064 (_entity .  X_OR4)
		(_port
			((I0) (\N_PZ_967_MC.D2_PT_0 \))
			((I1) (\N_PZ_967_MC.D2_PT_1 \))
			((I2) (\N_PZ_967_MC.D2_PT_2 \))
			((I3) (\N_PZ_967_MC.D2_PT_3 \))
			((O) (\N_PZ_967_MC.D2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/Channel0<10> \ 0 9071 (_entity .  X_BUF)
		(_port
			((I) (\U1/Channel0<10>_MC.Q \))
			((O) (\U1/Channel0 \(10)))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/Channel0<10>_MC.REG \ 0 9075 (_entity .  X_FF)
		(_port
			((I) (\U1/Channel0<10>_MC.D \))
			((CE) (Vcc))
			((CLK) (\Mclk_II/FCLK \))
			((SET) (Gnd))
			((RST) (PRLD))
			((O) (\U1/Channel0<10>_MC.Q \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/Channel0<10>_MC.D_713 \ 0 9083 (_entity .  X_XOR2)
		(_port
			((I0) (\NlwInverterSignal_U1/Channel0<10>_MC.D/IN0 \))
			((I1) (\U1/Channel0<10>_MC.D2 \))
			((O) (\U1/Channel0<10>_MC.D \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/Channel0<10>_MC.D1_714 \ 0 9088 (_entity .  X_ZERO)
		(_port
			((O) (\U1/Channel0<10>_MC.D1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/Channel0<10>_MC.D2_PT_0_715 \ 0 9091 (_entity .  X_AND2)
		(_port
			((I0) (\NlwInverterSignal_U1/Channel0<10>_MC.D2_PT_0/IN0 \))
			((I1) (\NlwInverterSignal_U1/Channel0<10>_MC.D2_PT_0/IN1 \))
			((O) (\U1/Channel0<10>_MC.D2_PT_0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/Channel0<10>_MC.D2_PT_1_716 \ 0 9096 (_entity .  X_AND2)
		(_port
			((I0) (\NlwInverterSignal_U1/Channel0<10>_MC.D2_PT_1/IN0 \))
			((I1) (\NlwInverterSignal_U1/Channel0<10>_MC.D2_PT_1/IN1 \))
			((O) (\U1/Channel0<10>_MC.D2_PT_1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/Channel0<10>_MC.D2_PT_2_717 \ 0 9101 (_entity .  X_AND3)
		(_port
			((I0) (\NlwInverterSignal_U1/Channel0<10>_MC.D2_PT_2/IN0 \))
			((I1) (\NlwInverterSignal_U1/Channel0<10>_MC.D2_PT_2/IN1 \))
			((I2) (\NlwInverterSignal_U1/Channel0<10>_MC.D2_PT_2/IN2 \))
			((O) (\U1/Channel0<10>_MC.D2_PT_2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/Channel0<10>_MC.D2_PT_3_718 \ 0 9107 (_entity .  X_AND7)
		(_port
			((I0) (N_PZ_1018))
			((I1) (\NlwInverterSignal_U1/Channel0<10>_MC.D2_PT_3/IN1 \))
			((I2) (\U1/Channel0 \(10)))
			((I3) (\U1/Channel0 \(7)))
			((I4) (\NlwInverterSignal_U1/Channel0<10>_MC.D2_PT_3/IN4 \))
			((I5) (\U1/Channel0 \(8)))
			((I6) (\U1/Channel0 \(9)))
			((O) (\U1/Channel0<10>_MC.D2_PT_3 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/Channel0<10>_MC.D2_PT_4_719 \ 0 9117 (_entity .  X_AND8)
		(_port
			((I0) (N_PZ_949))
			((I1) (N_PZ_1018))
			((I2) (N_PZ_961))
			((I3) (\U1/Channel0 \(10)))
			((I4) (\NlwInverterSignal_U1/Channel0<10>_MC.D2_PT_4/IN4 \))
			((I5) (\U1/U2/location_Maddsub__n0000__n0103 \(0)))
			((I6) (\NlwInverterSignal_U1/Channel0<10>_MC.D2_PT_4/IN6 \))
			((I7) (\NlwInverterSignal_U1/Channel0<10>_MC.D2_PT_4/IN7 \))
			((O) (\U1/Channel0<10>_MC.D2_PT_4 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/Channel0<10>_MC.D2_720 \ 0 9128 (_entity .  X_OR5)
		(_port
			((I0) (\U1/Channel0<10>_MC.D2_PT_0 \))
			((I1) (\U1/Channel0<10>_MC.D2_PT_1 \))
			((I2) (\U1/Channel0<10>_MC.D2_PT_2 \))
			((I3) (\U1/Channel0<10>_MC.D2_PT_3 \))
			((I4) (\U1/Channel0<10>_MC.D2_PT_4 \))
			((O) (\U1/Channel0<10>_MC.D2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/Channel0<7> \ 0 9136 (_entity .  X_BUF)
		(_port
			((I) (\U1/Channel0<7>_MC.Q \))
			((O) (\U1/Channel0 \(7)))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/Channel0<7>_MC_tsimcreated_xor__721 \ 0 9140 (_entity .  X_XOR2)
		(_port
			((I0) (\U1/Channel0<7>_MC.D \))
			((I1) (\U1/Channel0<7>_MC.Q \))
			((O) (\U1/Channel0<7>_MC_tsimcreated_xor_ \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/Channel0<7>_MC.REG \ 0 9145 (_entity .  X_FF)
		(_port
			((I) (\U1/Channel0<7>_MC_tsimcreated_xor_ \))
			((CE) (Vcc))
			((CLK) (\Mclk_II/FCLK \))
			((SET) (Gnd))
			((RST) (PRLD))
			((O) (\U1/Channel0<7>_MC.Q \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/Channel0<7>_MC.D_722 \ 0 9153 (_entity .  X_XOR2)
		(_port
			((I0) (\U1/Channel0<7>_MC.D1 \))
			((I1) (\U1/Channel0<7>_MC.D2 \))
			((O) (\U1/Channel0<7>_MC.D \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/Channel0<7>_MC.D1_723 \ 0 9158 (_entity .  X_ZERO)
		(_port
			((O) (\U1/Channel0<7>_MC.D1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/Channel0<7>_MC.D2_PT_0_724 \ 0 9161 (_entity .  X_AND2)
		(_port
			((I0) (\NlwInverterSignal_U1/Channel0<7>_MC.D2_PT_0/IN0 \))
			((I1) (\U1/Channel0 \(7)))
			((O) (\U1/Channel0<7>_MC.D2_PT_0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/Channel0<7>_MC.D2_PT_1_725 \ 0 9166 (_entity .  X_AND4)
		(_port
			((I0) (N_PZ_949))
			((I1) (N_PZ_1018))
			((I2) (N_PZ_961))
			((I3) (\U1/U2/location_Maddsub__n0000__n0103 \(0)))
			((O) (\U1/Channel0<7>_MC.D2_PT_1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/Channel0<7>_MC.D2_PT_2_726 \ 0 9173 (_entity .  X_AND4)
		(_port
			((I0) (N_PZ_949))
			((I1) (N_PZ_1018))
			((I2) (\NlwInverterSignal_U1/Channel0<7>_MC.D2_PT_2/IN2 \))
			((I3) (\NlwInverterSignal_U1/Channel0<7>_MC.D2_PT_2/IN3 \))
			((O) (\U1/Channel0<7>_MC.D2_PT_2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/Channel0<7>_MC.D2_727 \ 0 9180 (_entity .  X_OR3)
		(_port
			((I0) (\U1/Channel0<7>_MC.D2_PT_0 \))
			((I1) (\U1/Channel0<7>_MC.D2_PT_1 \))
			((I2) (\U1/Channel0<7>_MC.D2_PT_2 \))
			((O) (\U1/Channel0<7>_MC.D2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U2/location_Maddsub__n0000__n0103<0> \ 0 9186 (_entity .  X_BUF)
		(_port
			((I) (\U1/U2/location_Maddsub__n0000__n0103<0>_MC.Q \))
			((O) (\U1/U2/location_Maddsub__n0000__n0103 \(0)))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U2/location_Maddsub__n0000__n0103<0>_MC.Q_728 \ 0 9190 (_entity .  X_BUF)
		(_port
			((I) (\U1/U2/location_Maddsub__n0000__n0103<0>_MC.D \))
			((O) (\U1/U2/location_Maddsub__n0000__n0103<0>_MC.Q \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U2/location_Maddsub__n0000__n0103<0>_MC.D_729 \ 0 9194 (_entity .  X_XOR2)
		(_port
			((I0) (\U1/U2/location_Maddsub__n0000__n0103<0>_MC.D1 \))
			((I1) (\U1/U2/location_Maddsub__n0000__n0103<0>_MC.D2 \))
			((O) (\U1/U2/location_Maddsub__n0000__n0103<0>_MC.D \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U2/location_Maddsub__n0000__n0103<0>_MC.D1_730 \ 0 9199 (_entity .  X_AND2)
		(_port
			((I0) (N_PZ_967))
			((I1) (N_PZ_967))
			((O) (\U1/U2/location_Maddsub__n0000__n0103<0>_MC.D1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U2/location_Maddsub__n0000__n0103<0>_MC.D2_PT_0_731 \ 0 9204 (_entity .  X_AND8)
		(_port
			((I0) (\U1/Channel0 \(5)))
			((I1) (\U1/Channel0 \(0)))
			((I2) (\U1/Channel0 \(1)))
			((I3) (\U1/Channel0 \(2)))
			((I4) (\U1/Channel0 \(3)))
			((I5) (\U1/Channel0 \(4)))
			((I6) (N_PZ_967))
			((I7) (\U1/Channel0 \(6)))
			((O) (\U1/U2/location_Maddsub__n0000__n0103<0>_MC.D2_PT_0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U2/location_Maddsub__n0000__n0103<0>_MC.D2_PT_1_732 \ 0 9215 (_entity .  X_AND8)
		(_port
			((I0) (\NlwInverterSignal_U1/U2/location_Maddsub__n0000__n0103<0>_MC.D2_PT_1/IN0 \))
			((I1) (\NlwInverterSignal_U1/U2/location_Maddsub__n0000__n0103<0>_MC.D2_PT_1/IN1 \))
			((I2) (\NlwInverterSignal_U1/U2/location_Maddsub__n0000__n0103<0>_MC.D2_PT_1/IN2 \))
			((I3) (\NlwInverterSignal_U1/U2/location_Maddsub__n0000__n0103<0>_MC.D2_PT_1/IN3 \))
			((I4) (\NlwInverterSignal_U1/U2/location_Maddsub__n0000__n0103<0>_MC.D2_PT_1/IN4 \))
			((I5) (\NlwInverterSignal_U1/U2/location_Maddsub__n0000__n0103<0>_MC.D2_PT_1/IN5 \))
			((I6) (\NlwInverterSignal_U1/U2/location_Maddsub__n0000__n0103<0>_MC.D2_PT_1/IN6 \))
			((I7) (\NlwInverterSignal_U1/U2/location_Maddsub__n0000__n0103<0>_MC.D2_PT_1/IN7 \))
			((O) (\U1/U2/location_Maddsub__n0000__n0103<0>_MC.D2_PT_1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U2/location_Maddsub__n0000__n0103<0>_MC.D2_733 \ 0 9226 (_entity .  X_OR2)
		(_port
			((I0) (\U1/U2/location_Maddsub__n0000__n0103<0>_MC.D2_PT_0 \))
			((I1) (\U1/U2/location_Maddsub__n0000__n0103<0>_MC.D2_PT_1 \))
			((O) (\U1/U2/location_Maddsub__n0000__n0103<0>_MC.D2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/Channel0<6> \ 0 9231 (_entity .  X_BUF)
		(_port
			((I) (\U1/Channel0<6>_MC.Q \))
			((O) (\U1/Channel0 \(6)))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/Channel0<6>_MC_tsimcreated_xor__734 \ 0 9235 (_entity .  X_XOR2)
		(_port
			((I0) (\U1/Channel0<6>_MC.D \))
			((I1) (\U1/Channel0<6>_MC.Q \))
			((O) (\U1/Channel0<6>_MC_tsimcreated_xor_ \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/Channel0<6>_MC.REG \ 0 9240 (_entity .  X_FF)
		(_port
			((I) (\U1/Channel0<6>_MC_tsimcreated_xor_ \))
			((CE) (Vcc))
			((CLK) (\Mclk_II/FCLK \))
			((SET) (Gnd))
			((RST) (PRLD))
			((O) (\U1/Channel0<6>_MC.Q \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/Channel0<6>_MC.D_735 \ 0 9248 (_entity .  X_XOR2)
		(_port
			((I0) (\U1/Channel0<6>_MC.D1 \))
			((I1) (\U1/Channel0<6>_MC.D2 \))
			((O) (\U1/Channel0<6>_MC.D \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/Channel0<6>_MC.D1_736 \ 0 9253 (_entity .  X_ZERO)
		(_port
			((O) (\U1/Channel0<6>_MC.D1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/Channel0<6>_MC.D2_PT_0_737 \ 0 9256 (_entity .  X_AND2)
		(_port
			((I0) (\NlwInverterSignal_U1/Channel0<6>_MC.D2_PT_0/IN0 \))
			((I1) (\U1/Channel0 \(6)))
			((O) (\U1/Channel0<6>_MC.D2_PT_0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/Channel0<6>_MC.D2_PT_1_738 \ 0 9261 (_entity .  X_AND5)
		(_port
			((I0) (\NlwInverterSignal_U1/Channel0<6>_MC.D2_PT_1/IN0 \))
			((I1) (N_PZ_1018))
			((I2) (\NlwInverterSignal_U1/Channel0<6>_MC.D2_PT_1/IN2 \))
			((I3) (\NlwInverterSignal_U1/Channel0<6>_MC.D2_PT_1/IN3 \))
			((I4) (\U1/Channel0 \(6)))
			((O) (\U1/Channel0<6>_MC.D2_PT_1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/Channel0<6>_MC.D2_PT_2_739 \ 0 9269 (_entity .  X_AND5)
		(_port
			((I0) (N_PZ_949))
			((I1) (N_PZ_1018))
			((I2) (N_PZ_961))
			((I3) (\U1/U2/location_Maddsub__n0000__n0103 \(0)))
			((I4) (\NlwInverterSignal_U1/Channel0<6>_MC.D2_PT_2/IN4 \))
			((O) (\U1/Channel0<6>_MC.D2_PT_2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/Channel0<6>_MC.D2_PT_3_740 \ 0 9277 (_entity .  X_AND16)
		(_port
			((I0) (\NlwInverterSignal_U1/Channel0<6>_MC.D2_PT_3/IN0 \))
			((I1) (\NlwInverterSignal_U1/Channel0<6>_MC.D2_PT_3/IN1 \))
			((I2) (N_PZ_1018))
			((I3) (\NlwInverterSignal_U1/Channel0<6>_MC.D2_PT_3/IN3 \))
			((I4) (\NlwInverterSignal_U1/Channel0<6>_MC.D2_PT_3/IN4 \))
			((I5) (\NlwInverterSignal_U1/Channel0<6>_MC.D2_PT_3/IN5 \))
			((I6) (\NlwInverterSignal_U1/Channel0<6>_MC.D2_PT_3/IN6 \))
			((I7) (\NlwInverterSignal_U1/Channel0<6>_MC.D2_PT_3/IN7 \))
			((I8) (\U1/Channel0 \(6)))
			((I9) (Vcc))
			((I10) (Vcc))
			((I11) (Vcc))
			((I12) (Vcc))
			((I13) (Vcc))
			((I14) (Vcc))
			((I15) (Vcc))
			((O) (\U1/Channel0<6>_MC.D2_PT_3 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/Channel0<6>_MC.D2_PT_4_741 \ 0 9296 (_entity .  X_AND16)
		(_port
			((I0) (\U1/Channel0 \(0)))
			((I1) (N_PZ_1018))
			((I2) (\U1/Channel0 \(1)))
			((I3) (\NlwInverterSignal_U1/Channel0<6>_MC.D2_PT_4/IN3 \))
			((I4) (\U1/Channel0 \(2)))
			((I5) (\U1/Channel0 \(3)))
			((I6) (\U1/Channel0 \(4)))
			((I7) (\NlwInverterSignal_U1/Channel0<6>_MC.D2_PT_4/IN7 \))
			((I8) (\U1/Channel0 \(6)))
			((I9) (Vcc))
			((I10) (Vcc))
			((I11) (Vcc))
			((I12) (Vcc))
			((I13) (Vcc))
			((I14) (Vcc))
			((I15) (Vcc))
			((O) (\U1/Channel0<6>_MC.D2_PT_4 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/Channel0<6>_MC.D2_PT_5_742 \ 0 9315 (_entity .  X_AND16)
		(_port
			((I0) (\U1/Channel0 \(5)))
			((I1) (N_PZ_949))
			((I2) (\U1/Channel0 \(0)))
			((I3) (N_PZ_1018))
			((I4) (\U1/Channel0 \(1)))
			((I5) (\U1/Channel0 \(2)))
			((I6) (\U1/Channel0 \(3)))
			((I7) (\U1/Channel0 \(4)))
			((I8) (\U1/U2/location_Maddsub__n0000__n0103 \(0)))
			((I9) (\NlwInverterSignal_U1/Channel0<6>_MC.D2_PT_5/IN9 \))
			((I10) (Vcc))
			((I11) (Vcc))
			((I12) (Vcc))
			((I13) (Vcc))
			((I14) (Vcc))
			((I15) (Vcc))
			((O) (\U1/Channel0<6>_MC.D2_PT_5 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/Channel0<6>_MC.D2_743 \ 0 9334 (_entity .  X_OR6)
		(_port
			((I0) (\U1/Channel0<6>_MC.D2_PT_0 \))
			((I1) (\U1/Channel0<6>_MC.D2_PT_1 \))
			((I2) (\U1/Channel0<6>_MC.D2_PT_2 \))
			((I3) (\U1/Channel0<6>_MC.D2_PT_3 \))
			((I4) (\U1/Channel0<6>_MC.D2_PT_4 \))
			((I5) (\U1/Channel0<6>_MC.D2_PT_5 \))
			((O) (\U1/Channel0<6>_MC.D2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/Channel0<8> \ 0 9343 (_entity .  X_BUF)
		(_port
			((I) (\U1/Channel0<8>_MC.Q \))
			((O) (\U1/Channel0 \(8)))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/Channel0<8>_MC_tsimcreated_xor__744 \ 0 9347 (_entity .  X_XOR2)
		(_port
			((I0) (\U1/Channel0<8>_MC.D \))
			((I1) (\U1/Channel0<8>_MC.Q \))
			((O) (\U1/Channel0<8>_MC_tsimcreated_xor_ \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/Channel0<8>_MC.REG \ 0 9352 (_entity .  X_FF)
		(_port
			((I) (\U1/Channel0<8>_MC_tsimcreated_xor_ \))
			((CE) (Vcc))
			((CLK) (\Mclk_II/FCLK \))
			((SET) (Gnd))
			((RST) (PRLD))
			((O) (\U1/Channel0<8>_MC.Q \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/Channel0<8>_MC.D_745 \ 0 9360 (_entity .  X_XOR2)
		(_port
			((I0) (\U1/Channel0<8>_MC.D1 \))
			((I1) (\U1/Channel0<8>_MC.D2 \))
			((O) (\U1/Channel0<8>_MC.D \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/Channel0<8>_MC.D1_746 \ 0 9365 (_entity .  X_ZERO)
		(_port
			((O) (\U1/Channel0<8>_MC.D1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/Channel0<8>_MC.D2_PT_0_747 \ 0 9368 (_entity .  X_AND2)
		(_port
			((I0) (\NlwInverterSignal_U1/Channel0<8>_MC.D2_PT_0/IN0 \))
			((I1) (\U1/Channel0 \(8)))
			((O) (\U1/Channel0<8>_MC.D2_PT_0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/Channel0<8>_MC.D2_PT_1_748 \ 0 9373 (_entity .  X_AND5)
		(_port
			((I0) (N_PZ_949))
			((I1) (N_PZ_1018))
			((I2) (N_PZ_961))
			((I3) (\NlwInverterSignal_U1/Channel0<8>_MC.D2_PT_1/IN3 \))
			((I4) (\U1/U2/location_Maddsub__n0000__n0103 \(0)))
			((O) (\U1/Channel0<8>_MC.D2_PT_1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/Channel0<8>_MC.D2_PT_2_749 \ 0 9381 (_entity .  X_AND5)
		(_port
			((I0) (N_PZ_949))
			((I1) (N_PZ_1018))
			((I2) (\NlwInverterSignal_U1/Channel0<8>_MC.D2_PT_2/IN2 \))
			((I3) (\U1/Channel0 \(7)))
			((I4) (\NlwInverterSignal_U1/Channel0<8>_MC.D2_PT_2/IN4 \))
			((O) (\U1/Channel0<8>_MC.D2_PT_2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/Channel0<8>_MC.D2_750 \ 0 9389 (_entity .  X_OR3)
		(_port
			((I0) (\U1/Channel0<8>_MC.D2_PT_0 \))
			((I1) (\U1/Channel0<8>_MC.D2_PT_1 \))
			((I2) (\U1/Channel0<8>_MC.D2_PT_2 \))
			((O) (\U1/Channel0<8>_MC.D2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/Channel0<9> \ 0 9395 (_entity .  X_BUF)
		(_port
			((I) (\U1/Channel0<9>_MC.Q \))
			((O) (\U1/Channel0 \(9)))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/Channel0<9>_MC_tsimcreated_xor__751 \ 0 9399 (_entity .  X_XOR2)
		(_port
			((I0) (\U1/Channel0<9>_MC.D \))
			((I1) (\U1/Channel0<9>_MC.Q \))
			((O) (\U1/Channel0<9>_MC_tsimcreated_xor_ \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/Channel0<9>_MC.REG \ 0 9404 (_entity .  X_FF)
		(_port
			((I) (\U1/Channel0<9>_MC_tsimcreated_xor_ \))
			((CE) (Vcc))
			((CLK) (\Mclk_II/FCLK \))
			((SET) (Gnd))
			((RST) (PRLD))
			((O) (\U1/Channel0<9>_MC.Q \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/Channel0<9>_MC.D_752 \ 0 9412 (_entity .  X_XOR2)
		(_port
			((I0) (\U1/Channel0<9>_MC.D1 \))
			((I1) (\U1/Channel0<9>_MC.D2 \))
			((O) (\U1/Channel0<9>_MC.D \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/Channel0<9>_MC.D1_753 \ 0 9417 (_entity .  X_ZERO)
		(_port
			((O) (\U1/Channel0<9>_MC.D1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/Channel0<9>_MC.D2_PT_0_754 \ 0 9420 (_entity .  X_AND2)
		(_port
			((I0) (\NlwInverterSignal_U1/Channel0<9>_MC.D2_PT_0/IN0 \))
			((I1) (\U1/Channel0 \(9)))
			((O) (\U1/Channel0<9>_MC.D2_PT_0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/Channel0<9>_MC.D2_PT_1_755 \ 0 9425 (_entity .  X_AND6)
		(_port
			((I0) (N_PZ_949))
			((I1) (N_PZ_1018))
			((I2) (N_PZ_961))
			((I3) (\NlwInverterSignal_U1/Channel0<9>_MC.D2_PT_1/IN3 \))
			((I4) (\U1/U2/location_Maddsub__n0000__n0103 \(0)))
			((I5) (\NlwInverterSignal_U1/Channel0<9>_MC.D2_PT_1/IN5 \))
			((O) (\U1/Channel0<9>_MC.D2_PT_1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/Channel0<9>_MC.D2_PT_2_756 \ 0 9434 (_entity .  X_AND6)
		(_port
			((I0) (N_PZ_949))
			((I1) (N_PZ_1018))
			((I2) (\NlwInverterSignal_U1/Channel0<9>_MC.D2_PT_2/IN2 \))
			((I3) (\U1/Channel0 \(7)))
			((I4) (\NlwInverterSignal_U1/Channel0<9>_MC.D2_PT_2/IN4 \))
			((I5) (\U1/Channel0 \(8)))
			((O) (\U1/Channel0<9>_MC.D2_PT_2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/Channel0<9>_MC.D2_757 \ 0 9443 (_entity .  X_OR3)
		(_port
			((I0) (\U1/Channel0<9>_MC.D2_PT_0 \))
			((I1) (\U1/Channel0<9>_MC.D2_PT_1 \))
			((I2) (\U1/Channel0<9>_MC.D2_PT_2 \))
			((O) (\U1/Channel0<9>_MC.D2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation N_PZ_1317_758 0 9449 (_entity .  X_BUF)
		(_port
			((I) (\N_PZ_1317_MC.Q \))
			((O) (N_PZ_1317))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \N_PZ_1317_MC.Q_759 \ 0 9453 (_entity .  X_BUF)
		(_port
			((I) (\N_PZ_1317_MC.D \))
			((O) (\N_PZ_1317_MC.Q \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \N_PZ_1317_MC.D_760 \ 0 9457 (_entity .  X_XOR2)
		(_port
			((I0) (\N_PZ_1317_MC.D1 \))
			((I1) (\N_PZ_1317_MC.D2 \))
			((O) (\N_PZ_1317_MC.D \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \N_PZ_1317_MC.D1_761 \ 0 9462 (_entity .  X_ZERO)
		(_port
			((O) (\N_PZ_1317_MC.D1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \N_PZ_1317_MC.D2_PT_0_762 \ 0 9465 (_entity .  X_AND5)
		(_port
			((I0) (N_PZ_1018))
			((I1) (N_PZ_961))
			((I2) (\NlwInverterSignal_N_PZ_1317_MC.D2_PT_0/IN2 \))
			((I3) (\NlwInverterSignal_N_PZ_1317_MC.D2_PT_0/IN3 \))
			((I4) (\NlwInverterSignal_N_PZ_1317_MC.D2_PT_0/IN4 \))
			((O) (\N_PZ_1317_MC.D2_PT_0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \N_PZ_1317_MC.D2_PT_1_763 \ 0 9473 (_entity .  X_AND5)
		(_port
			((I0) (N_PZ_1018))
			((I1) (\NlwInverterSignal_N_PZ_1317_MC.D2_PT_1/IN1 \))
			((I2) (\NlwInverterSignal_N_PZ_1317_MC.D2_PT_1/IN2 \))
			((I3) (\U1/Channel0 \(8)))
			((I4) (\U1/Channel0 \(9)))
			((O) (\N_PZ_1317_MC.D2_PT_1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \N_PZ_1317_MC.D2_PT_2_764 \ 0 9481 (_entity .  X_AND5)
		(_port
			((I0) (N_PZ_1018))
			((I1) (\NlwInverterSignal_N_PZ_1317_MC.D2_PT_2/IN1 \))
			((I2) (\NlwInverterSignal_N_PZ_1317_MC.D2_PT_2/IN2 \))
			((I3) (\NlwInverterSignal_N_PZ_1317_MC.D2_PT_2/IN3 \))
			((I4) (\U1/Channel0 \(9)))
			((O) (\N_PZ_1317_MC.D2_PT_2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \N_PZ_1317_MC.D2_765 \ 0 9489 (_entity .  X_OR3)
		(_port
			((I0) (\N_PZ_1317_MC.D2_PT_0 \))
			((I1) (\N_PZ_1317_MC.D2_PT_1 \))
			((I2) (\N_PZ_1317_MC.D2_PT_2 \))
			((O) (\N_PZ_1317_MC.D2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/Channel0<11> \ 0 9495 (_entity .  X_BUF)
		(_port
			((I) (\U1/Channel0<11>_MC.Q \))
			((O) (\U1/Channel0 \(11)))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/Channel0<11>_MC.REG \ 0 9499 (_entity .  X_FF)
		(_port
			((I) (\U1/Channel0<11>_MC.D \))
			((CE) (Vcc))
			((CLK) (\Mclk_II/FCLK \))
			((SET) (Gnd))
			((RST) (PRLD))
			((O) (\U1/Channel0<11>_MC.Q \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/Channel0<11>_MC.D_766 \ 0 9507 (_entity .  X_XOR2)
		(_port
			((I0) (\NlwInverterSignal_U1/Channel0<11>_MC.D/IN0 \))
			((I1) (\U1/Channel0<11>_MC.D2 \))
			((O) (\U1/Channel0<11>_MC.D \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/Channel0<11>_MC.D1_767 \ 0 9512 (_entity .  X_ZERO)
		(_port
			((O) (\U1/Channel0<11>_MC.D1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/Channel0<11>_MC.D2_PT_0_768 \ 0 9515 (_entity .  X_AND2)
		(_port
			((I0) (\NlwInverterSignal_U1/Channel0<11>_MC.D2_PT_0/IN0 \))
			((I1) (\NlwInverterSignal_U1/Channel0<11>_MC.D2_PT_0/IN1 \))
			((O) (\U1/Channel0<11>_MC.D2_PT_0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/Channel0<11>_MC.D2_PT_1_769 \ 0 9520 (_entity .  X_AND2)
		(_port
			((I0) (\NlwInverterSignal_U1/Channel0<11>_MC.D2_PT_1/IN0 \))
			((I1) (\NlwInverterSignal_U1/Channel0<11>_MC.D2_PT_1/IN1 \))
			((O) (\U1/Channel0<11>_MC.D2_PT_1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/Channel0<11>_MC.D2_PT_2_770 \ 0 9525 (_entity .  X_AND3)
		(_port
			((I0) (\U1/Channel0 \(10)))
			((I1) (\NlwInverterSignal_U1/Channel0<11>_MC.D2_PT_2/IN1 \))
			((I2) (\NlwInverterSignal_U1/Channel0<11>_MC.D2_PT_2/IN2 \))
			((O) (\U1/Channel0<11>_MC.D2_PT_2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/Channel0<11>_MC.D2_PT_3_771 \ 0 9531 (_entity .  X_AND3)
		(_port
			((I0) (\NlwInverterSignal_U1/Channel0<11>_MC.D2_PT_3/IN0 \))
			((I1) (\NlwInverterSignal_U1/Channel0<11>_MC.D2_PT_3/IN1 \))
			((I2) (\NlwInverterSignal_U1/Channel0<11>_MC.D2_PT_3/IN2 \))
			((O) (\U1/Channel0<11>_MC.D2_PT_3 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/Channel0<11>_MC.D2_PT_4_772 \ 0 9537 (_entity .  X_AND8)
		(_port
			((I0) (N_PZ_1018))
			((I1) (\NlwInverterSignal_U1/Channel0<11>_MC.D2_PT_4/IN1 \))
			((I2) (\U1/Channel0 \(10)))
			((I3) (\U1/Channel0 \(7)))
			((I4) (\NlwInverterSignal_U1/Channel0<11>_MC.D2_PT_4/IN4 \))
			((I5) (\U1/Channel0 \(8)))
			((I6) (\U1/Channel0 \(9)))
			((I7) (\U1/Channel0 \(11)))
			((O) (\U1/Channel0<11>_MC.D2_PT_4 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/Channel0<11>_MC.D2_PT_5_773 \ 0 9548 (_entity .  X_AND16)
		(_port
			((I0) (N_PZ_949))
			((I1) (N_PZ_1018))
			((I2) (N_PZ_961))
			((I3) (\NlwInverterSignal_U1/Channel0<11>_MC.D2_PT_5/IN3 \))
			((I4) (\NlwInverterSignal_U1/Channel0<11>_MC.D2_PT_5/IN4 \))
			((I5) (\U1/U2/location_Maddsub__n0000__n0103 \(0)))
			((I6) (\NlwInverterSignal_U1/Channel0<11>_MC.D2_PT_5/IN6 \))
			((I7) (\NlwInverterSignal_U1/Channel0<11>_MC.D2_PT_5/IN7 \))
			((I8) (\U1/Channel0 \(11)))
			((I9) (Vcc))
			((I10) (Vcc))
			((I11) (Vcc))
			((I12) (Vcc))
			((I13) (Vcc))
			((I14) (Vcc))
			((I15) (Vcc))
			((O) (\U1/Channel0<11>_MC.D2_PT_5 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/Channel0<11>_MC.D2_774 \ 0 9567 (_entity .  X_OR6)
		(_port
			((I0) (\U1/Channel0<11>_MC.D2_PT_0 \))
			((I1) (\U1/Channel0<11>_MC.D2_PT_1 \))
			((I2) (\U1/Channel0<11>_MC.D2_PT_2 \))
			((I3) (\U1/Channel0<11>_MC.D2_PT_3 \))
			((I4) (\U1/Channel0<11>_MC.D2_PT_4 \))
			((I5) (\U1/Channel0<11>_MC.D2_PT_5 \))
			((O) (\U1/Channel0<11>_MC.D2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/Channel0<12> \ 0 9576 (_entity .  X_BUF)
		(_port
			((I) (\U1/Channel0<12>_MC.Q \))
			((O) (\U1/Channel0 \(12)))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/Channel0<12>_MC_tsimcreated_xor__775 \ 0 9580 (_entity .  X_XOR2)
		(_port
			((I0) (\U1/Channel0<12>_MC.D \))
			((I1) (\U1/Channel0<12>_MC.Q \))
			((O) (\U1/Channel0<12>_MC_tsimcreated_xor_ \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/Channel0<12>_MC.REG \ 0 9585 (_entity .  X_FF)
		(_port
			((I) (\U1/Channel0<12>_MC_tsimcreated_xor_ \))
			((CE) (Vcc))
			((CLK) (\Mclk_II/FCLK \))
			((SET) (Gnd))
			((RST) (PRLD))
			((O) (\U1/Channel0<12>_MC.Q \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/Channel0<12>_MC.D_776 \ 0 9593 (_entity .  X_XOR2)
		(_port
			((I0) (\U1/Channel0<12>_MC.D1 \))
			((I1) (\U1/Channel0<12>_MC.D2 \))
			((O) (\U1/Channel0<12>_MC.D \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/Channel0<12>_MC.D1_777 \ 0 9598 (_entity .  X_ZERO)
		(_port
			((O) (\U1/Channel0<12>_MC.D1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/Channel0<12>_MC.D2_PT_0_778 \ 0 9601 (_entity .  X_AND2)
		(_port
			((I0) (\NlwInverterSignal_U1/Channel0<12>_MC.D2_PT_0/IN0 \))
			((I1) (\U1/Channel0 \(12)))
			((O) (\U1/Channel0<12>_MC.D2_PT_0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/Channel0<12>_MC.D2_PT_1_779 \ 0 9606 (_entity .  X_AND5)
		(_port
			((I0) (N_PZ_949))
			((I1) (N_PZ_1018))
			((I2) (N_PZ_961))
			((I3) (\U1/U2/location_Maddsub__n0000__n0115 \(0)))
			((I4) (\NlwInverterSignal_U1/Channel0<12>_MC.D2_PT_1/IN4 \))
			((O) (\U1/Channel0<12>_MC.D2_PT_1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/Channel0<12>_MC.D2_PT_2_780 \ 0 9614 (_entity .  X_AND5)
		(_port
			((I0) (N_PZ_1018))
			((I1) (\NlwInverterSignal_U1/Channel0<12>_MC.D2_PT_2/IN1 \))
			((I2) (\NlwInverterSignal_U1/Channel0<12>_MC.D2_PT_2/IN2 \))
			((I3) (\NlwInverterSignal_U1/Channel0<12>_MC.D2_PT_2/IN3 \))
			((I4) (\U1/Channel0 \(12)))
			((O) (\U1/Channel0<12>_MC.D2_PT_2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/Channel0<12>_MC.D2_PT_3_781 \ 0 9622 (_entity .  X_AND16)
		(_port
			((I0) (N_PZ_1018))
			((I1) (\NlwInverterSignal_U1/Channel0<12>_MC.D2_PT_3/IN1 \))
			((I2) (\NlwInverterSignal_U1/Channel0<12>_MC.D2_PT_3/IN2 \))
			((I3) (\U1/Channel0 \(10)))
			((I4) (\U1/Channel0 \(7)))
			((I5) (\NlwInverterSignal_U1/Channel0<12>_MC.D2_PT_3/IN5 \))
			((I6) (\U1/Channel0 \(8)))
			((I7) (\U1/Channel0 \(9)))
			((I8) (\U1/Channel0 \(12)))
			((I9) (Vcc))
			((I10) (Vcc))
			((I11) (Vcc))
			((I12) (Vcc))
			((I13) (Vcc))
			((I14) (Vcc))
			((I15) (Vcc))
			((O) (\U1/Channel0<12>_MC.D2_PT_3 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/Channel0<12>_MC.D2_PT_4_782 \ 0 9641 (_entity .  X_AND16)
		(_port
			((I0) (N_PZ_1018))
			((I1) (\NlwInverterSignal_U1/Channel0<12>_MC.D2_PT_4/IN1 \))
			((I2) (\NlwInverterSignal_U1/Channel0<12>_MC.D2_PT_4/IN2 \))
			((I3) (\NlwInverterSignal_U1/Channel0<12>_MC.D2_PT_4/IN3 \))
			((I4) (\U1/U2/location_Maddsub__n0000__n0103 \(0)))
			((I5) (\NlwInverterSignal_U1/Channel0<12>_MC.D2_PT_4/IN5 \))
			((I6) (\NlwInverterSignal_U1/Channel0<12>_MC.D2_PT_4/IN6 \))
			((I7) (\NlwInverterSignal_U1/Channel0<12>_MC.D2_PT_4/IN7 \))
			((I8) (\U1/Channel0 \(12)))
			((I9) (Vcc))
			((I10) (Vcc))
			((I11) (Vcc))
			((I12) (Vcc))
			((I13) (Vcc))
			((I14) (Vcc))
			((I15) (Vcc))
			((O) (\U1/Channel0<12>_MC.D2_PT_4 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/Channel0<12>_MC.D2_PT_5_783 \ 0 9660 (_entity .  X_AND16)
		(_port
			((I0) (N_PZ_949))
			((I1) (N_PZ_1018))
			((I2) (\U1/U2/location_Maddsub__n0000__n0115 \(0)))
			((I3) (\U1/Channel0 \(10)))
			((I4) (\U1/Channel0 \(7)))
			((I5) (\NlwInverterSignal_U1/Channel0<12>_MC.D2_PT_5/IN5 \))
			((I6) (\U1/Channel0 \(8)))
			((I7) (\U1/Channel0 \(9)))
			((I8) (\U1/Channel0 \(11)))
			((I9) (\NlwInverterSignal_U1/Channel0<12>_MC.D2_PT_5/IN9 \))
			((I10) (Vcc))
			((I11) (Vcc))
			((I12) (Vcc))
			((I13) (Vcc))
			((I14) (Vcc))
			((I15) (Vcc))
			((O) (\U1/Channel0<12>_MC.D2_PT_5 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/Channel0<12>_MC.D2_784 \ 0 9679 (_entity .  X_OR6)
		(_port
			((I0) (\U1/Channel0<12>_MC.D2_PT_0 \))
			((I1) (\U1/Channel0<12>_MC.D2_PT_1 \))
			((I2) (\U1/Channel0<12>_MC.D2_PT_2 \))
			((I3) (\U1/Channel0<12>_MC.D2_PT_3 \))
			((I4) (\U1/Channel0<12>_MC.D2_PT_4 \))
			((I5) (\U1/Channel0<12>_MC.D2_PT_5 \))
			((O) (\U1/Channel0<12>_MC.D2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/Channel0<14> \ 0 9688 (_entity .  X_BUF)
		(_port
			((I) (\U1/Channel0<14>_MC.Q \))
			((O) (\U1/Channel0 \(14)))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/Channel0<14>_MC_tsimcreated_xor__785 \ 0 9692 (_entity .  X_XOR2)
		(_port
			((I0) (\U1/Channel0<14>_MC.D \))
			((I1) (\U1/Channel0<14>_MC.Q \))
			((O) (\U1/Channel0<14>_MC_tsimcreated_xor_ \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/Channel0<14>_MC.REG \ 0 9697 (_entity .  X_FF)
		(_port
			((I) (\U1/Channel0<14>_MC_tsimcreated_xor_ \))
			((CE) (Vcc))
			((CLK) (\Mclk_II/FCLK \))
			((SET) (Gnd))
			((RST) (PRLD))
			((O) (\U1/Channel0<14>_MC.Q \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/Channel0<14>_MC.D_786 \ 0 9705 (_entity .  X_XOR2)
		(_port
			((I0) (\U1/Channel0<14>_MC.D1 \))
			((I1) (\U1/Channel0<14>_MC.D2 \))
			((O) (\U1/Channel0<14>_MC.D \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/Channel0<14>_MC.D1_787 \ 0 9710 (_entity .  X_ZERO)
		(_port
			((O) (\U1/Channel0<14>_MC.D1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/Channel0<14>_MC.D2_PT_0_788 \ 0 9713 (_entity .  X_AND2)
		(_port
			((I0) (\NlwInverterSignal_U1/Channel0<14>_MC.D2_PT_0/IN0 \))
			((I1) (\U1/Channel0 \(14)))
			((O) (\U1/Channel0<14>_MC.D2_PT_0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/Channel0<14>_MC.D2_PT_1_789 \ 0 9718 (_entity .  X_AND5)
		(_port
			((I0) (N_PZ_949))
			((I1) (N_PZ_1018))
			((I2) (N_PZ_961))
			((I3) (\NlwInverterSignal_U1/Channel0<14>_MC.D2_PT_1/IN3 \))
			((I4) (\U1/U2/location_Maddsub__n0000__n0115 \(0)))
			((O) (\U1/Channel0<14>_MC.D2_PT_1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/Channel0<14>_MC.D2_PT_2_790 \ 0 9726 (_entity .  X_AND5)
		(_port
			((I0) (N_PZ_949))
			((I1) (N_PZ_1018))
			((I2) (\NlwInverterSignal_U1/Channel0<14>_MC.D2_PT_2/IN2 \))
			((I3) (\U1/Channel0 \(13)))
			((I4) (\NlwInverterSignal_U1/Channel0<14>_MC.D2_PT_2/IN4 \))
			((O) (\U1/Channel0<14>_MC.D2_PT_2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/Channel0<14>_MC.D2_791 \ 0 9734 (_entity .  X_OR3)
		(_port
			((I0) (\U1/Channel0<14>_MC.D2_PT_0 \))
			((I1) (\U1/Channel0<14>_MC.D2_PT_1 \))
			((I2) (\U1/Channel0<14>_MC.D2_PT_2 \))
			((O) (\U1/Channel0<14>_MC.D2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/Channel0<15> \ 0 9740 (_entity .  X_BUF)
		(_port
			((I) (\U1/Channel0<15>_MC.Q \))
			((O) (\U1/Channel0 \(15)))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/Channel0<15>_MC_tsimcreated_xor__792 \ 0 9744 (_entity .  X_XOR2)
		(_port
			((I0) (\U1/Channel0<15>_MC.D \))
			((I1) (\U1/Channel0<15>_MC.Q \))
			((O) (\U1/Channel0<15>_MC_tsimcreated_xor_ \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/Channel0<15>_MC.REG \ 0 9749 (_entity .  X_FF)
		(_port
			((I) (\U1/Channel0<15>_MC_tsimcreated_xor_ \))
			((CE) (Vcc))
			((CLK) (\Mclk_II/FCLK \))
			((SET) (Gnd))
			((RST) (PRLD))
			((O) (\U1/Channel0<15>_MC.Q \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/Channel0<15>_MC.D_793 \ 0 9757 (_entity .  X_XOR2)
		(_port
			((I0) (\U1/Channel0<15>_MC.D1 \))
			((I1) (\U1/Channel0<15>_MC.D2 \))
			((O) (\U1/Channel0<15>_MC.D \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/Channel0<15>_MC.D1_794 \ 0 9762 (_entity .  X_ZERO)
		(_port
			((O) (\U1/Channel0<15>_MC.D1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/Channel0<15>_MC.D2_PT_0_795 \ 0 9765 (_entity .  X_AND2)
		(_port
			((I0) (\NlwInverterSignal_U1/Channel0<15>_MC.D2_PT_0/IN0 \))
			((I1) (\U1/Channel0 \(15)))
			((O) (\U1/Channel0<15>_MC.D2_PT_0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/Channel0<15>_MC.D2_PT_1_796 \ 0 9770 (_entity .  X_AND6)
		(_port
			((I0) (N_PZ_949))
			((I1) (N_PZ_1018))
			((I2) (N_PZ_961))
			((I3) (\NlwInverterSignal_U1/Channel0<15>_MC.D2_PT_1/IN3 \))
			((I4) (\U1/U2/location_Maddsub__n0000__n0115 \(0)))
			((I5) (\NlwInverterSignal_U1/Channel0<15>_MC.D2_PT_1/IN5 \))
			((O) (\U1/Channel0<15>_MC.D2_PT_1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/Channel0<15>_MC.D2_PT_2_797 \ 0 9779 (_entity .  X_AND6)
		(_port
			((I0) (N_PZ_949))
			((I1) (N_PZ_1018))
			((I2) (\NlwInverterSignal_U1/Channel0<15>_MC.D2_PT_2/IN2 \))
			((I3) (\U1/Channel0 \(13)))
			((I4) (\NlwInverterSignal_U1/Channel0<15>_MC.D2_PT_2/IN4 \))
			((I5) (\U1/Channel0 \(14)))
			((O) (\U1/Channel0<15>_MC.D2_PT_2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/Channel0<15>_MC.D2_798 \ 0 9788 (_entity .  X_OR3)
		(_port
			((I0) (\U1/Channel0<15>_MC.D2_PT_0 \))
			((I1) (\U1/Channel0<15>_MC.D2_PT_1 \))
			((I2) (\U1/Channel0<15>_MC.D2_PT_2 \))
			((O) (\U1/Channel0<15>_MC.D2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/Channel0<16> \ 0 9794 (_entity .  X_BUF)
		(_port
			((I) (\U1/Channel0<16>_MC.Q \))
			((O) (\U1/Channel0 \(16)))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/Channel0<16>_MC_tsimcreated_xor__799 \ 0 9798 (_entity .  X_XOR2)
		(_port
			((I0) (\U1/Channel0<16>_MC.D \))
			((I1) (\U1/Channel0<16>_MC.Q \))
			((O) (\U1/Channel0<16>_MC_tsimcreated_xor_ \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/Channel0<16>_MC.REG \ 0 9803 (_entity .  X_FF)
		(_port
			((I) (\U1/Channel0<16>_MC_tsimcreated_xor_ \))
			((CE) (Vcc))
			((CLK) (\Mclk_II/FCLK \))
			((SET) (Gnd))
			((RST) (PRLD))
			((O) (\U1/Channel0<16>_MC.Q \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/Channel0<16>_MC.D_800 \ 0 9811 (_entity .  X_XOR2)
		(_port
			((I0) (\U1/Channel0<16>_MC.D1 \))
			((I1) (\U1/Channel0<16>_MC.D2 \))
			((O) (\U1/Channel0<16>_MC.D \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/Channel0<16>_MC.D1_801 \ 0 9816 (_entity .  X_ZERO)
		(_port
			((O) (\U1/Channel0<16>_MC.D1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/Channel0<16>_MC.D2_PT_0_802 \ 0 9819 (_entity .  X_AND2)
		(_port
			((I0) (\NlwInverterSignal_U1/Channel0<16>_MC.D2_PT_0/IN0 \))
			((I1) (\U1/Channel0 \(16)))
			((O) (\U1/Channel0<16>_MC.D2_PT_0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/Channel0<16>_MC.D2_PT_1_803 \ 0 9824 (_entity .  X_AND7)
		(_port
			((I0) (N_PZ_949))
			((I1) (N_PZ_1018))
			((I2) (N_PZ_961))
			((I3) (\NlwInverterSignal_U1/Channel0<16>_MC.D2_PT_1/IN3 \))
			((I4) (\U1/U2/location_Maddsub__n0000__n0115 \(0)))
			((I5) (\NlwInverterSignal_U1/Channel0<16>_MC.D2_PT_1/IN5 \))
			((I6) (\NlwInverterSignal_U1/Channel0<16>_MC.D2_PT_1/IN6 \))
			((O) (\U1/Channel0<16>_MC.D2_PT_1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/Channel0<16>_MC.D2_PT_2_804 \ 0 9834 (_entity .  X_AND7)
		(_port
			((I0) (N_PZ_949))
			((I1) (N_PZ_1018))
			((I2) (\NlwInverterSignal_U1/Channel0<16>_MC.D2_PT_2/IN2 \))
			((I3) (\U1/Channel0 \(13)))
			((I4) (\NlwInverterSignal_U1/Channel0<16>_MC.D2_PT_2/IN4 \))
			((I5) (\U1/Channel0 \(14)))
			((I6) (\U1/Channel0 \(15)))
			((O) (\U1/Channel0<16>_MC.D2_PT_2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/Channel0<16>_MC.D2_805 \ 0 9844 (_entity .  X_OR3)
		(_port
			((I0) (\U1/Channel0<16>_MC.D2_PT_0 \))
			((I1) (\U1/Channel0<16>_MC.D2_PT_1 \))
			((I2) (\U1/Channel0<16>_MC.D2_PT_2 \))
			((O) (\U1/Channel0<16>_MC.D2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/Channel0<17> \ 0 9850 (_entity .  X_BUF)
		(_port
			((I) (\U1/Channel0<17>_MC.Q \))
			((O) (\U1/Channel0 \(17)))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/Channel0<17>_MC.REG \ 0 9854 (_entity .  X_FF)
		(_port
			((I) (\U1/Channel0<17>_MC.D \))
			((CE) (Vcc))
			((CLK) (\Mclk_II/FCLK \))
			((SET) (Gnd))
			((RST) (PRLD))
			((O) (\U1/Channel0<17>_MC.Q \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/Channel0<17>_MC.D_806 \ 0 9862 (_entity .  X_XOR2)
		(_port
			((I0) (\U1/Channel0<17>_MC.D1 \))
			((I1) (\U1/Channel0<17>_MC.D2 \))
			((O) (\U1/Channel0<17>_MC.D \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/Channel0<17>_MC.D1_807 \ 0 9867 (_entity .  X_AND2)
		(_port
			((I0) (\U1/Channel0 \(17)))
			((I1) (\U1/Channel0 \(17)))
			((O) (\U1/Channel0<17>_MC.D1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/Channel0<17>_MC.D2_PT_0_808 \ 0 9872 (_entity .  X_AND2)
		(_port
			((I0) (\NlwInverterSignal_U1/Channel0<17>_MC.D2_PT_0/IN0 \))
			((I1) (\U1/Channel0 \(17)))
			((O) (\U1/Channel0<17>_MC.D2_PT_0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/Channel0<17>_MC.D2_PT_1_809 \ 0 9877 (_entity .  X_AND8)
		(_port
			((I0) (N_PZ_1018))
			((I1) (\NlwInverterSignal_U1/Channel0<17>_MC.D2_PT_1/IN1 \))
			((I2) (\U1/Channel0 \(13)))
			((I3) (\NlwInverterSignal_U1/Channel0<17>_MC.D2_PT_1/IN3 \))
			((I4) (\U1/Channel0 \(14)))
			((I5) (\U1/Channel0 \(15)))
			((I6) (\U1/Channel0 \(16)))
			((I7) (\U1/Channel0 \(17)))
			((O) (\U1/Channel0<17>_MC.D2_PT_1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/Channel0<17>_MC.D2_PT_2_810 \ 0 9888 (_entity .  X_AND16)
		(_port
			((I0) (N_PZ_949))
			((I1) (N_PZ_1018))
			((I2) (N_PZ_961))
			((I3) (\NlwInverterSignal_U1/Channel0<17>_MC.D2_PT_2/IN3 \))
			((I4) (\U1/U2/location_Maddsub__n0000__n0115 \(0)))
			((I5) (\NlwInverterSignal_U1/Channel0<17>_MC.D2_PT_2/IN5 \))
			((I6) (\NlwInverterSignal_U1/Channel0<17>_MC.D2_PT_2/IN6 \))
			((I7) (\NlwInverterSignal_U1/Channel0<17>_MC.D2_PT_2/IN7 \))
			((I8) (\U1/Channel0 \(17)))
			((I9) (Vcc))
			((I10) (Vcc))
			((I11) (Vcc))
			((I12) (Vcc))
			((I13) (Vcc))
			((I14) (Vcc))
			((I15) (Vcc))
			((O) (\U1/Channel0<17>_MC.D2_PT_2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/Channel0<17>_MC.D2_PT_3_811 \ 0 9907 (_entity .  X_AND16)
		(_port
			((I0) (N_PZ_949))
			((I1) (N_PZ_1018))
			((I2) (N_PZ_961))
			((I3) (\NlwInverterSignal_U1/Channel0<17>_MC.D2_PT_3/IN3 \))
			((I4) (\U1/U2/location_Maddsub__n0000__n0115 \(0)))
			((I5) (\NlwInverterSignal_U1/Channel0<17>_MC.D2_PT_3/IN5 \))
			((I6) (\NlwInverterSignal_U1/Channel0<17>_MC.D2_PT_3/IN6 \))
			((I7) (\NlwInverterSignal_U1/Channel0<17>_MC.D2_PT_3/IN7 \))
			((I8) (\NlwInverterSignal_U1/Channel0<17>_MC.D2_PT_3/IN8 \))
			((I9) (Vcc))
			((I10) (Vcc))
			((I11) (Vcc))
			((I12) (Vcc))
			((I13) (Vcc))
			((I14) (Vcc))
			((I15) (Vcc))
			((O) (\U1/Channel0<17>_MC.D2_PT_3 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/Channel0<17>_MC.D2_PT_4_812 \ 0 9926 (_entity .  X_AND16)
		(_port
			((I0) (N_PZ_949))
			((I1) (N_PZ_1018))
			((I2) (\NlwInverterSignal_U1/Channel0<17>_MC.D2_PT_4/IN2 \))
			((I3) (\U1/Channel0 \(13)))
			((I4) (\NlwInverterSignal_U1/Channel0<17>_MC.D2_PT_4/IN4 \))
			((I5) (\U1/Channel0 \(14)))
			((I6) (\U1/Channel0 \(15)))
			((I7) (\U1/Channel0 \(16)))
			((I8) (\NlwInverterSignal_U1/Channel0<17>_MC.D2_PT_4/IN8 \))
			((I9) (Vcc))
			((I10) (Vcc))
			((I11) (Vcc))
			((I12) (Vcc))
			((I13) (Vcc))
			((I14) (Vcc))
			((I15) (Vcc))
			((O) (\U1/Channel0<17>_MC.D2_PT_4 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/Channel0<17>_MC.D2_813 \ 0 9945 (_entity .  X_OR5)
		(_port
			((I0) (\U1/Channel0<17>_MC.D2_PT_0 \))
			((I1) (\U1/Channel0<17>_MC.D2_PT_1 \))
			((I2) (\U1/Channel0<17>_MC.D2_PT_2 \))
			((I3) (\U1/Channel0<17>_MC.D2_PT_3 \))
			((I4) (\U1/Channel0<17>_MC.D2_PT_4 \))
			((O) (\U1/Channel0<17>_MC.D2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/Channel0<18> \ 0 9953 (_entity .  X_BUF)
		(_port
			((I) (\U1/Channel0<18>_MC.Q \))
			((O) (\U1/Channel0 \(18)))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/Channel0<18>_MC.REG \ 0 9957 (_entity .  X_FF)
		(_port
			((I) (\U1/Channel0<18>_MC.D \))
			((CE) (Vcc))
			((CLK) (\Mclk_II/FCLK \))
			((SET) (Gnd))
			((RST) (PRLD))
			((O) (\U1/Channel0<18>_MC.Q \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/Channel0<18>_MC.D_814 \ 0 9965 (_entity .  X_XOR2)
		(_port
			((I0) (\U1/Channel0<18>_MC.D1 \))
			((I1) (\U1/Channel0<18>_MC.D2 \))
			((O) (\U1/Channel0<18>_MC.D \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/Channel0<18>_MC.D1_815 \ 0 9970 (_entity .  X_AND2)
		(_port
			((I0) (\U1/Channel0 \(18)))
			((I1) (\U1/Channel0 \(18)))
			((O) (\U1/Channel0<18>_MC.D1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/Channel0<18>_MC.D2_PT_0_816 \ 0 9975 (_entity .  X_AND2)
		(_port
			((I0) (\NlwInverterSignal_U1/Channel0<18>_MC.D2_PT_0/IN0 \))
			((I1) (\U1/Channel0 \(18)))
			((O) (\U1/Channel0<18>_MC.D2_PT_0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/Channel0<18>_MC.D2_PT_1_817 \ 0 9980 (_entity .  X_AND16)
		(_port
			((I0) (N_PZ_1018))
			((I1) (N_PZ_961))
			((I2) (\NlwInverterSignal_U1/Channel0<18>_MC.D2_PT_1/IN2 \))
			((I3) (\U1/U2/location_Maddsub__n0000__n0115 \(0)))
			((I4) (\NlwInverterSignal_U1/Channel0<18>_MC.D2_PT_1/IN4 \))
			((I5) (\NlwInverterSignal_U1/Channel0<18>_MC.D2_PT_1/IN5 \))
			((I6) (\NlwInverterSignal_U1/Channel0<18>_MC.D2_PT_1/IN6 \))
			((I7) (\NlwInverterSignal_U1/Channel0<18>_MC.D2_PT_1/IN7 \))
			((I8) (\U1/Channel0 \(18)))
			((I9) (Vcc))
			((I10) (Vcc))
			((I11) (Vcc))
			((I12) (Vcc))
			((I13) (Vcc))
			((I14) (Vcc))
			((I15) (Vcc))
			((O) (\U1/Channel0<18>_MC.D2_PT_1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/Channel0<18>_MC.D2_PT_2_818 \ 0 9999 (_entity .  X_AND16)
		(_port
			((I0) (N_PZ_1018))
			((I1) (\NlwInverterSignal_U1/Channel0<18>_MC.D2_PT_2/IN1 \))
			((I2) (\U1/Channel0 \(13)))
			((I3) (\NlwInverterSignal_U1/Channel0<18>_MC.D2_PT_2/IN3 \))
			((I4) (\U1/Channel0 \(14)))
			((I5) (\U1/Channel0 \(15)))
			((I6) (\U1/Channel0 \(16)))
			((I7) (\U1/Channel0 \(17)))
			((I8) (\U1/Channel0 \(18)))
			((I9) (Vcc))
			((I10) (Vcc))
			((I11) (Vcc))
			((I12) (Vcc))
			((I13) (Vcc))
			((I14) (Vcc))
			((I15) (Vcc))
			((O) (\U1/Channel0<18>_MC.D2_PT_2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/Channel0<18>_MC.D2_PT_3_819 \ 0 10018 (_entity .  X_AND16)
		(_port
			((I0) (N_PZ_949))
			((I1) (N_PZ_1018))
			((I2) (N_PZ_961))
			((I3) (\NlwInverterSignal_U1/Channel0<18>_MC.D2_PT_3/IN3 \))
			((I4) (\U1/U2/location_Maddsub__n0000__n0115 \(0)))
			((I5) (\NlwInverterSignal_U1/Channel0<18>_MC.D2_PT_3/IN5 \))
			((I6) (\NlwInverterSignal_U1/Channel0<18>_MC.D2_PT_3/IN6 \))
			((I7) (\NlwInverterSignal_U1/Channel0<18>_MC.D2_PT_3/IN7 \))
			((I8) (\NlwInverterSignal_U1/Channel0<18>_MC.D2_PT_3/IN8 \))
			((I9) (\NlwInverterSignal_U1/Channel0<18>_MC.D2_PT_3/IN9 \))
			((I10) (Vcc))
			((I11) (Vcc))
			((I12) (Vcc))
			((I13) (Vcc))
			((I14) (Vcc))
			((I15) (Vcc))
			((O) (\U1/Channel0<18>_MC.D2_PT_3 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/Channel0<18>_MC.D2_PT_4_820 \ 0 10037 (_entity .  X_AND16)
		(_port
			((I0) (N_PZ_949))
			((I1) (N_PZ_1018))
			((I2) (\NlwInverterSignal_U1/Channel0<18>_MC.D2_PT_4/IN2 \))
			((I3) (\U1/Channel0 \(13)))
			((I4) (\NlwInverterSignal_U1/Channel0<18>_MC.D2_PT_4/IN4 \))
			((I5) (\U1/Channel0 \(14)))
			((I6) (\U1/Channel0 \(15)))
			((I7) (\U1/Channel0 \(16)))
			((I8) (\U1/Channel0 \(17)))
			((I9) (\NlwInverterSignal_U1/Channel0<18>_MC.D2_PT_4/IN9 \))
			((I10) (Vcc))
			((I11) (Vcc))
			((I12) (Vcc))
			((I13) (Vcc))
			((I14) (Vcc))
			((I15) (Vcc))
			((O) (\U1/Channel0<18>_MC.D2_PT_4 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/Channel0<18>_MC.D2_821 \ 0 10056 (_entity .  X_OR5)
		(_port
			((I0) (\U1/Channel0<18>_MC.D2_PT_0 \))
			((I1) (\U1/Channel0<18>_MC.D2_PT_1 \))
			((I2) (\U1/Channel0<18>_MC.D2_PT_2 \))
			((I3) (\U1/Channel0<18>_MC.D2_PT_3 \))
			((I4) (\U1/Channel0<18>_MC.D2_PT_4 \))
			((O) (\U1/Channel0<18>_MC.D2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/Channel0<19> \ 0 10064 (_entity .  X_BUF)
		(_port
			((I) (\U1/Channel0<19>_MC.Q \))
			((O) (\U1/Channel0 \(19)))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/Channel0<19>_MC.REG \ 0 10068 (_entity .  X_FF)
		(_port
			((I) (\U1/Channel0<19>_MC.D \))
			((CE) (Vcc))
			((CLK) (\Mclk_II/FCLK \))
			((SET) (Gnd))
			((RST) (PRLD))
			((O) (\U1/Channel0<19>_MC.Q \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/Channel0<19>_MC.D_822 \ 0 10076 (_entity .  X_XOR2)
		(_port
			((I0) (\U1/Channel0<19>_MC.D1 \))
			((I1) (\U1/Channel0<19>_MC.D2 \))
			((O) (\U1/Channel0<19>_MC.D \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/Channel0<19>_MC.D1_823 \ 0 10081 (_entity .  X_AND2)
		(_port
			((I0) (\U1/Channel0 \(19)))
			((I1) (\U1/Channel0 \(19)))
			((O) (\U1/Channel0<19>_MC.D1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/Channel0<19>_MC.D2_PT_0_824 \ 0 10086 (_entity .  X_AND2)
		(_port
			((I0) (\NlwInverterSignal_U1/Channel0<19>_MC.D2_PT_0/IN0 \))
			((I1) (\U1/Channel0 \(19)))
			((O) (\U1/Channel0<19>_MC.D2_PT_0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/Channel0<19>_MC.D2_PT_1_825 \ 0 10091 (_entity .  X_AND16)
		(_port
			((I0) (N_PZ_1018))
			((I1) (N_PZ_961))
			((I2) (\NlwInverterSignal_U1/Channel0<19>_MC.D2_PT_1/IN2 \))
			((I3) (\U1/U2/location_Maddsub__n0000__n0115 \(0)))
			((I4) (\NlwInverterSignal_U1/Channel0<19>_MC.D2_PT_1/IN4 \))
			((I5) (\NlwInverterSignal_U1/Channel0<19>_MC.D2_PT_1/IN5 \))
			((I6) (\NlwInverterSignal_U1/Channel0<19>_MC.D2_PT_1/IN6 \))
			((I7) (\NlwInverterSignal_U1/Channel0<19>_MC.D2_PT_1/IN7 \))
			((I8) (\NlwInverterSignal_U1/Channel0<19>_MC.D2_PT_1/IN8 \))
			((I9) (\U1/Channel0 \(19)))
			((I10) (Vcc))
			((I11) (Vcc))
			((I12) (Vcc))
			((I13) (Vcc))
			((I14) (Vcc))
			((I15) (Vcc))
			((O) (\U1/Channel0<19>_MC.D2_PT_1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/Channel0<19>_MC.D2_PT_2_826 \ 0 10110 (_entity .  X_AND16)
		(_port
			((I0) (N_PZ_1018))
			((I1) (\NlwInverterSignal_U1/Channel0<19>_MC.D2_PT_2/IN1 \))
			((I2) (\U1/Channel0 \(13)))
			((I3) (\NlwInverterSignal_U1/Channel0<19>_MC.D2_PT_2/IN3 \))
			((I4) (\U1/Channel0 \(14)))
			((I5) (\U1/Channel0 \(15)))
			((I6) (\U1/Channel0 \(16)))
			((I7) (\U1/Channel0 \(17)))
			((I8) (\U1/Channel0 \(18)))
			((I9) (\U1/Channel0 \(19)))
			((I10) (Vcc))
			((I11) (Vcc))
			((I12) (Vcc))
			((I13) (Vcc))
			((I14) (Vcc))
			((I15) (Vcc))
			((O) (\U1/Channel0<19>_MC.D2_PT_2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/Channel0<19>_MC.D2_PT_3_827 \ 0 10129 (_entity .  X_AND16)
		(_port
			((I0) (N_PZ_949))
			((I1) (N_PZ_1018))
			((I2) (N_PZ_961))
			((I3) (\NlwInverterSignal_U1/Channel0<19>_MC.D2_PT_3/IN3 \))
			((I4) (\U1/U2/location_Maddsub__n0000__n0115 \(0)))
			((I5) (\NlwInverterSignal_U1/Channel0<19>_MC.D2_PT_3/IN5 \))
			((I6) (\NlwInverterSignal_U1/Channel0<19>_MC.D2_PT_3/IN6 \))
			((I7) (\NlwInverterSignal_U1/Channel0<19>_MC.D2_PT_3/IN7 \))
			((I8) (\NlwInverterSignal_U1/Channel0<19>_MC.D2_PT_3/IN8 \))
			((I9) (\NlwInverterSignal_U1/Channel0<19>_MC.D2_PT_3/IN9 \))
			((I10) (\NlwInverterSignal_U1/Channel0<19>_MC.D2_PT_3/IN10 \))
			((I11) (Vcc))
			((I12) (Vcc))
			((I13) (Vcc))
			((I14) (Vcc))
			((I15) (Vcc))
			((O) (\U1/Channel0<19>_MC.D2_PT_3 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/Channel0<19>_MC.D2_PT_4_828 \ 0 10148 (_entity .  X_AND16)
		(_port
			((I0) (N_PZ_949))
			((I1) (N_PZ_1018))
			((I2) (\NlwInverterSignal_U1/Channel0<19>_MC.D2_PT_4/IN2 \))
			((I3) (\U1/Channel0 \(13)))
			((I4) (\NlwInverterSignal_U1/Channel0<19>_MC.D2_PT_4/IN4 \))
			((I5) (\U1/Channel0 \(14)))
			((I6) (\U1/Channel0 \(15)))
			((I7) (\U1/Channel0 \(16)))
			((I8) (\U1/Channel0 \(17)))
			((I9) (\U1/Channel0 \(18)))
			((I10) (\NlwInverterSignal_U1/Channel0<19>_MC.D2_PT_4/IN10 \))
			((I11) (Vcc))
			((I12) (Vcc))
			((I13) (Vcc))
			((I14) (Vcc))
			((I15) (Vcc))
			((O) (\U1/Channel0<19>_MC.D2_PT_4 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/Channel0<19>_MC.D2_829 \ 0 10167 (_entity .  X_OR5)
		(_port
			((I0) (\U1/Channel0<19>_MC.D2_PT_0 \))
			((I1) (\U1/Channel0<19>_MC.D2_PT_1 \))
			((I2) (\U1/Channel0<19>_MC.D2_PT_2 \))
			((I3) (\U1/Channel0<19>_MC.D2_PT_3 \))
			((I4) (\U1/Channel0<19>_MC.D2_PT_4 \))
			((O) (\U1/Channel0<19>_MC.D2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/Channel0<20> \ 0 10175 (_entity .  X_BUF)
		(_port
			((I) (\U1/Channel0<20>_MC.Q \))
			((O) (\U1/Channel0 \(20)))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/Channel0<20>_MC_tsimcreated_xor__830 \ 0 10179 (_entity .  X_XOR2)
		(_port
			((I0) (\U1/Channel0<20>_MC.D \))
			((I1) (\U1/Channel0<20>_MC.Q \))
			((O) (\U1/Channel0<20>_MC_tsimcreated_xor_ \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/Channel0<20>_MC.REG \ 0 10184 (_entity .  X_FF)
		(_port
			((I) (\U1/Channel0<20>_MC_tsimcreated_xor_ \))
			((CE) (Vcc))
			((CLK) (\Mclk_II/FCLK \))
			((SET) (Gnd))
			((RST) (PRLD))
			((O) (\U1/Channel0<20>_MC.Q \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/Channel0<20>_MC.D_831 \ 0 10192 (_entity .  X_XOR2)
		(_port
			((I0) (\U1/Channel0<20>_MC.D1 \))
			((I1) (\U1/Channel0<20>_MC.D2 \))
			((O) (\U1/Channel0<20>_MC.D \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/Channel0<20>_MC.D1_832 \ 0 10197 (_entity .  X_ZERO)
		(_port
			((O) (\U1/Channel0<20>_MC.D1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/Channel0<20>_MC.D2_PT_0_833 \ 0 10200 (_entity .  X_AND2)
		(_port
			((I0) (\NlwInverterSignal_U1/Channel0<20>_MC.D2_PT_0/IN0 \))
			((I1) (\U1/Channel0 \(20)))
			((O) (\U1/Channel0<20>_MC.D2_PT_0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/Channel0<20>_MC.D2_PT_1_834 \ 0 10205 (_entity .  X_AND16)
		(_port
			((I0) (N_PZ_949))
			((I1) (N_PZ_1018))
			((I2) (N_PZ_961))
			((I3) (\NlwInverterSignal_U1/Channel0<20>_MC.D2_PT_1/IN3 \))
			((I4) (\U1/U2/location_Maddsub__n0000__n0115 \(0)))
			((I5) (\NlwInverterSignal_U1/Channel0<20>_MC.D2_PT_1/IN5 \))
			((I6) (\NlwInverterSignal_U1/Channel0<20>_MC.D2_PT_1/IN6 \))
			((I7) (\NlwInverterSignal_U1/Channel0<20>_MC.D2_PT_1/IN7 \))
			((I8) (\NlwInverterSignal_U1/Channel0<20>_MC.D2_PT_1/IN8 \))
			((I9) (\NlwInverterSignal_U1/Channel0<20>_MC.D2_PT_1/IN9 \))
			((I10) (\NlwInverterSignal_U1/Channel0<20>_MC.D2_PT_1/IN10 \))
			((I11) (Vcc))
			((I12) (Vcc))
			((I13) (Vcc))
			((I14) (Vcc))
			((I15) (Vcc))
			((O) (\U1/Channel0<20>_MC.D2_PT_1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/Channel0<20>_MC.D2_PT_2_835 \ 0 10224 (_entity .  X_AND16)
		(_port
			((I0) (N_PZ_949))
			((I1) (N_PZ_1018))
			((I2) (\NlwInverterSignal_U1/Channel0<20>_MC.D2_PT_2/IN2 \))
			((I3) (\U1/Channel0 \(13)))
			((I4) (\NlwInverterSignal_U1/Channel0<20>_MC.D2_PT_2/IN4 \))
			((I5) (\U1/Channel0 \(14)))
			((I6) (\U1/Channel0 \(15)))
			((I7) (\U1/Channel0 \(16)))
			((I8) (\U1/Channel0 \(17)))
			((I9) (\U1/Channel0 \(18)))
			((I10) (\U1/Channel0 \(19)))
			((I11) (Vcc))
			((I12) (Vcc))
			((I13) (Vcc))
			((I14) (Vcc))
			((I15) (Vcc))
			((O) (\U1/Channel0<20>_MC.D2_PT_2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/Channel0<20>_MC.D2_836 \ 0 10243 (_entity .  X_OR3)
		(_port
			((I0) (\U1/Channel0<20>_MC.D2_PT_0 \))
			((I1) (\U1/Channel0<20>_MC.D2_PT_1 \))
			((I2) (\U1/Channel0<20>_MC.D2_PT_2 \))
			((O) (\U1/Channel0<20>_MC.D2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/Channel1<21> \ 0 10249 (_entity .  X_BUF)
		(_port
			((I) (\U1/Channel1<21>_MC.Q \))
			((O) (\U1/Channel1 \(21)))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/Channel1<21>_MC_tsimcreated_xor__837 \ 0 10253 (_entity .  X_XOR2)
		(_port
			((I0) (\U1/Channel1<21>_MC.D \))
			((I1) (\U1/Channel1<21>_MC.Q \))
			((O) (\U1/Channel1<21>_MC_tsimcreated_xor_ \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/Channel1<21>_MC.REG \ 0 10258 (_entity .  X_FF)
		(_port
			((I) (\U1/Channel1<21>_MC_tsimcreated_xor_ \))
			((CE) (Vcc))
			((CLK) (\Mclk_II/FCLK \))
			((SET) (Gnd))
			((RST) (PRLD))
			((O) (\U1/Channel1<21>_MC.Q \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/Channel1<21>_MC.D_838 \ 0 10266 (_entity .  X_XOR2)
		(_port
			((I0) (\U1/Channel1<21>_MC.D1 \))
			((I1) (\U1/Channel1<21>_MC.D2 \))
			((O) (\U1/Channel1<21>_MC.D \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/Channel1<21>_MC.D1_839 \ 0 10271 (_entity .  X_ZERO)
		(_port
			((O) (\U1/Channel1<21>_MC.D1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/Channel1<21>_MC.D2_PT_0_840 \ 0 10274 (_entity .  X_AND2)
		(_port
			((I0) (\NlwInverterSignal_U1/Channel1<21>_MC.D2_PT_0/IN0 \))
			((I1) (\U1/Channel1 \(21)))
			((O) (\U1/Channel1<21>_MC.D2_PT_0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/Channel1<21>_MC.D2_PT_1_841 \ 0 10279 (_entity .  X_AND16)
		(_port
			((I0) (N_PZ_948))
			((I1) (N_PZ_1082))
			((I2) (N_PZ_993))
			((I3) (\NlwInverterSignal_U1/Channel1<21>_MC.D2_PT_1/IN3 \))
			((I4) (\U1/U5/location_Maddsub__n0000__n0115 \(0)))
			((I5) (\NlwInverterSignal_U1/Channel1<21>_MC.D2_PT_1/IN5 \))
			((I6) (\NlwInverterSignal_U1/Channel1<21>_MC.D2_PT_1/IN6 \))
			((I7) (\NlwInverterSignal_U1/Channel1<21>_MC.D2_PT_1/IN7 \))
			((I8) (\NlwInverterSignal_U1/Channel1<21>_MC.D2_PT_1/IN8 \))
			((I9) (\NlwInverterSignal_U1/Channel1<21>_MC.D2_PT_1/IN9 \))
			((I10) (\NlwInverterSignal_U1/Channel1<21>_MC.D2_PT_1/IN10 \))
			((I11) (\NlwInverterSignal_U1/Channel1<21>_MC.D2_PT_1/IN11 \))
			((I12) (Vcc))
			((I13) (Vcc))
			((I14) (Vcc))
			((I15) (Vcc))
			((O) (\U1/Channel1<21>_MC.D2_PT_1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/Channel1<21>_MC.D2_PT_2_842 \ 0 10298 (_entity .  X_AND16)
		(_port
			((I0) (N_PZ_948))
			((I1) (N_PZ_1082))
			((I2) (\NlwInverterSignal_U1/Channel1<21>_MC.D2_PT_2/IN2 \))
			((I3) (\U1/Channel1 \(13)))
			((I4) (\NlwInverterSignal_U1/Channel1<21>_MC.D2_PT_2/IN4 \))
			((I5) (\U1/Channel1 \(14)))
			((I6) (\U1/Channel1 \(15)))
			((I7) (\U1/Channel1 \(16)))
			((I8) (\U1/Channel1 \(17)))
			((I9) (\U1/Channel1 \(18)))
			((I10) (\U1/Channel1 \(19)))
			((I11) (\U1/Channel1 \(20)))
			((I12) (Vcc))
			((I13) (Vcc))
			((I14) (Vcc))
			((I15) (Vcc))
			((O) (\U1/Channel1<21>_MC.D2_PT_2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/Channel1<21>_MC.D2_843 \ 0 10317 (_entity .  X_OR3)
		(_port
			((I0) (\U1/Channel1<21>_MC.D2_PT_0 \))
			((I1) (\U1/Channel1<21>_MC.D2_PT_1 \))
			((I2) (\U1/Channel1<21>_MC.D2_PT_2 \))
			((O) (\U1/Channel1<21>_MC.D2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/Channel1<13> \ 0 10323 (_entity .  X_BUF)
		(_port
			((I) (\U1/Channel1<13>_MC.Q \))
			((O) (\U1/Channel1 \(13)))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/Channel1<13>_MC_tsimcreated_xor__844 \ 0 10327 (_entity .  X_XOR2)
		(_port
			((I0) (\U1/Channel1<13>_MC.D \))
			((I1) (\U1/Channel1<13>_MC.Q \))
			((O) (\U1/Channel1<13>_MC_tsimcreated_xor_ \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/Channel1<13>_MC.REG \ 0 10332 (_entity .  X_FF)
		(_port
			((I) (\U1/Channel1<13>_MC_tsimcreated_xor_ \))
			((CE) (Vcc))
			((CLK) (\Mclk_II/FCLK \))
			((SET) (Gnd))
			((RST) (PRLD))
			((O) (\U1/Channel1<13>_MC.Q \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/Channel1<13>_MC.D_845 \ 0 10340 (_entity .  X_XOR2)
		(_port
			((I0) (\U1/Channel1<13>_MC.D1 \))
			((I1) (\U1/Channel1<13>_MC.D2 \))
			((O) (\U1/Channel1<13>_MC.D \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/Channel1<13>_MC.D1_846 \ 0 10345 (_entity .  X_ZERO)
		(_port
			((O) (\U1/Channel1<13>_MC.D1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/Channel1<13>_MC.D2_PT_0_847 \ 0 10348 (_entity .  X_AND2)
		(_port
			((I0) (\NlwInverterSignal_U1/Channel1<13>_MC.D2_PT_0/IN0 \))
			((I1) (\U1/Channel1 \(13)))
			((O) (\U1/Channel1<13>_MC.D2_PT_0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/Channel1<13>_MC.D2_PT_1_848 \ 0 10353 (_entity .  X_AND4)
		(_port
			((I0) (N_PZ_948))
			((I1) (N_PZ_1082))
			((I2) (N_PZ_993))
			((I3) (\U1/U5/location_Maddsub__n0000__n0115 \(0)))
			((O) (\U1/Channel1<13>_MC.D2_PT_1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/Channel1<13>_MC.D2_PT_2_849 \ 0 10360 (_entity .  X_AND4)
		(_port
			((I0) (N_PZ_948))
			((I1) (N_PZ_1082))
			((I2) (\NlwInverterSignal_U1/Channel1<13>_MC.D2_PT_2/IN2 \))
			((I3) (\NlwInverterSignal_U1/Channel1<13>_MC.D2_PT_2/IN3 \))
			((O) (\U1/Channel1<13>_MC.D2_PT_2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/Channel1<13>_MC.D2_850 \ 0 10367 (_entity .  X_OR3)
		(_port
			((I0) (\U1/Channel1<13>_MC.D2_PT_0 \))
			((I1) (\U1/Channel1<13>_MC.D2_PT_1 \))
			((I2) (\U1/Channel1<13>_MC.D2_PT_2 \))
			((O) (\U1/Channel1<13>_MC.D2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U5/location_Maddsub__n0000__n0115<0> \ 0 10373 (_entity .  X_BUF)
		(_port
			((I) (\U1/U5/location_Maddsub__n0000__n0115<0>_MC.Q \))
			((O) (\U1/U5/location_Maddsub__n0000__n0115 \(0)))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U5/location_Maddsub__n0000__n0115<0>_MC.Q_851 \ 0 10377 (_entity .  X_BUF)
		(_port
			((I) (\U1/U5/location_Maddsub__n0000__n0115<0>_MC.D \))
			((O) (\U1/U5/location_Maddsub__n0000__n0115<0>_MC.Q \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U5/location_Maddsub__n0000__n0115<0>_MC.D_852 \ 0 10381 (_entity .  X_XOR2)
		(_port
			((I0) (\U1/U5/location_Maddsub__n0000__n0115<0>_MC.D1 \))
			((I1) (\U1/U5/location_Maddsub__n0000__n0115<0>_MC.D2 \))
			((O) (\U1/U5/location_Maddsub__n0000__n0115<0>_MC.D \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U5/location_Maddsub__n0000__n0115<0>_MC.D1_853 \ 0 10386 (_entity .  X_AND2)
		(_port
			((I0) (N_PZ_968))
			((I1) (N_PZ_968))
			((O) (\U1/U5/location_Maddsub__n0000__n0115<0>_MC.D1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U5/location_Maddsub__n0000__n0115<0>_MC.D2_PT_0_854 \ 0 10391 (_entity .  X_AND4)
		(_port
			((I0) (N_PZ_968))
			((I1) (\U1/Channel1 \(11)))
			((I2) (N_PZ_1055))
			((I3) (\U1/Channel1 \(12)))
			((O) (\U1/U5/location_Maddsub__n0000__n0115<0>_MC.D2_PT_0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U5/location_Maddsub__n0000__n0115<0>_MC.D2_PT_1_855 \ 0 10398 (_entity .  X_AND8)
		(_port
			((I0) (\NlwInverterSignal_U1/U5/location_Maddsub__n0000__n0115<0>_MC.D2_PT_1/IN0 \))
			((I1) (\NlwInverterSignal_U1/U5/location_Maddsub__n0000__n0115<0>_MC.D2_PT_1/IN1 \))
			((I2) (\NlwInverterSignal_U1/U5/location_Maddsub__n0000__n0115<0>_MC.D2_PT_1/IN2 \))
			((I3) (\NlwInverterSignal_U1/U5/location_Maddsub__n0000__n0115<0>_MC.D2_PT_1/IN3 \))
			((I4) (\NlwInverterSignal_U1/U5/location_Maddsub__n0000__n0115<0>_MC.D2_PT_1/IN4 \))
			((I5) (\U1/U5/location_Maddsub__n0000__n0103 \(0)))
			((I6) (\NlwInverterSignal_U1/U5/location_Maddsub__n0000__n0115<0>_MC.D2_PT_1/IN6 \))
			((I7) (\NlwInverterSignal_U1/U5/location_Maddsub__n0000__n0115<0>_MC.D2_PT_1/IN7 \))
			((O) (\U1/U5/location_Maddsub__n0000__n0115<0>_MC.D2_PT_1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U5/location_Maddsub__n0000__n0115<0>_MC.D2_856 \ 0 10409 (_entity .  X_OR2)
		(_port
			((I0) (\U1/U5/location_Maddsub__n0000__n0115<0>_MC.D2_PT_0 \))
			((I1) (\U1/U5/location_Maddsub__n0000__n0115<0>_MC.D2_PT_1 \))
			((O) (\U1/U5/location_Maddsub__n0000__n0115<0>_MC.D2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation N_PZ_968_857 0 10414 (_entity .  X_BUF)
		(_port
			((I) (\N_PZ_968_MC.Q \))
			((O) (N_PZ_968))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \N_PZ_968_MC.Q_858 \ 0 10418 (_entity .  X_BUF)
		(_port
			((I) (\N_PZ_968_MC.D \))
			((O) (\N_PZ_968_MC.Q \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \N_PZ_968_MC.D_859 \ 0 10422 (_entity .  X_XOR2)
		(_port
			((I0) (\N_PZ_968_MC.D1 \))
			((I1) (\N_PZ_968_MC.D2 \))
			((O) (\N_PZ_968_MC.D \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \N_PZ_968_MC.D1_860 \ 0 10427 (_entity .  X_ZERO)
		(_port
			((O) (\N_PZ_968_MC.D1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \N_PZ_968_MC.D2_PT_0_861 \ 0 10430 (_entity .  X_AND2)
		(_port
			((I0) (\U1/U6/CurrState_Sreg0_FFD1 \))
			((I1) (\U1/NET3720 \))
			((O) (\N_PZ_968_MC.D2_PT_0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \N_PZ_968_MC.D2_PT_1_862 \ 0 10435 (_entity .  X_AND3)
		(_port
			((I0) (N_PZ_993))
			((I1) (\U1/U6/CurrState_Sreg0_FFD2 \))
			((I2) (\NlwInverterSignal_N_PZ_968_MC.D2_PT_1/IN2 \))
			((O) (\N_PZ_968_MC.D2_PT_1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \N_PZ_968_MC.D2_PT_2_863 \ 0 10441 (_entity .  X_AND3)
		(_port
			((I0) (\NlwInverterSignal_N_PZ_968_MC.D2_PT_2/IN0 \))
			((I1) (\NlwInverterSignal_N_PZ_968_MC.D2_PT_2/IN1 \))
			((I2) (\U1/NET3720 \))
			((O) (\N_PZ_968_MC.D2_PT_2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \N_PZ_968_MC.D2_PT_3_864 \ 0 10447 (_entity .  X_AND4)
		(_port
			((I0) (\U1/U6/CurrState_Sreg0_FFD3 \))
			((I1) (\NlwInverterSignal_N_PZ_968_MC.D2_PT_3/IN1 \))
			((I2) (\NlwInverterSignal_N_PZ_968_MC.D2_PT_3/IN2 \))
			((I3) (\NlwInverterSignal_N_PZ_968_MC.D2_PT_3/IN3 \))
			((O) (\N_PZ_968_MC.D2_PT_3 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \N_PZ_968_MC.D2_865 \ 0 10454 (_entity .  X_OR4)
		(_port
			((I0) (\N_PZ_968_MC.D2_PT_0 \))
			((I1) (\N_PZ_968_MC.D2_PT_1 \))
			((I2) (\N_PZ_968_MC.D2_PT_2 \))
			((I3) (\N_PZ_968_MC.D2_PT_3 \))
			((O) (\N_PZ_968_MC.D2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/Channel1<10> \ 0 10461 (_entity .  X_BUF)
		(_port
			((I) (\U1/Channel1<10>_MC.Q \))
			((O) (\U1/Channel1 \(10)))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/Channel1<10>_MC_tsimcreated_xor__866 \ 0 10465 (_entity .  X_XOR2)
		(_port
			((I0) (\U1/Channel1<10>_MC.D \))
			((I1) (\U1/Channel1<10>_MC.Q \))
			((O) (\U1/Channel1<10>_MC_tsimcreated_xor_ \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/Channel1<10>_MC.REG \ 0 10470 (_entity .  X_FF)
		(_port
			((I) (\U1/Channel1<10>_MC_tsimcreated_xor_ \))
			((CE) (Vcc))
			((CLK) (\Mclk_II/FCLK \))
			((SET) (Gnd))
			((RST) (PRLD))
			((O) (\U1/Channel1<10>_MC.Q \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/Channel1<10>_MC.D_867 \ 0 10478 (_entity .  X_XOR2)
		(_port
			((I0) (\U1/Channel1<10>_MC.D1 \))
			((I1) (\U1/Channel1<10>_MC.D2 \))
			((O) (\U1/Channel1<10>_MC.D \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/Channel1<10>_MC.D1_868 \ 0 10483 (_entity .  X_ZERO)
		(_port
			((O) (\U1/Channel1<10>_MC.D1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/Channel1<10>_MC.D2_PT_0_869 \ 0 10486 (_entity .  X_AND2)
		(_port
			((I0) (\NlwInverterSignal_U1/Channel1<10>_MC.D2_PT_0/IN0 \))
			((I1) (\U1/Channel1 \(10)))
			((O) (\U1/Channel1<10>_MC.D2_PT_0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/Channel1<10>_MC.D2_PT_1_870 \ 0 10491 (_entity .  X_AND7)
		(_port
			((I0) (N_PZ_948))
			((I1) (N_PZ_1082))
			((I2) (N_PZ_993))
			((I3) (\NlwInverterSignal_U1/Channel1<10>_MC.D2_PT_1/IN3 \))
			((I4) (\U1/U5/location_Maddsub__n0000__n0103 \(0)))
			((I5) (\NlwInverterSignal_U1/Channel1<10>_MC.D2_PT_1/IN5 \))
			((I6) (\NlwInverterSignal_U1/Channel1<10>_MC.D2_PT_1/IN6 \))
			((O) (\U1/Channel1<10>_MC.D2_PT_1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/Channel1<10>_MC.D2_PT_2_871 \ 0 10501 (_entity .  X_AND7)
		(_port
			((I0) (N_PZ_948))
			((I1) (N_PZ_1082))
			((I2) (\NlwInverterSignal_U1/Channel1<10>_MC.D2_PT_2/IN2 \))
			((I3) (\U1/Channel1 \(7)))
			((I4) (\NlwInverterSignal_U1/Channel1<10>_MC.D2_PT_2/IN4 \))
			((I5) (\U1/Channel1 \(8)))
			((I6) (\U1/Channel1 \(9)))
			((O) (\U1/Channel1<10>_MC.D2_PT_2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/Channel1<10>_MC.D2_872 \ 0 10511 (_entity .  X_OR3)
		(_port
			((I0) (\U1/Channel1<10>_MC.D2_PT_0 \))
			((I1) (\U1/Channel1<10>_MC.D2_PT_1 \))
			((I2) (\U1/Channel1<10>_MC.D2_PT_2 \))
			((O) (\U1/Channel1<10>_MC.D2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/Channel1<7> \ 0 10517 (_entity .  X_BUF)
		(_port
			((I) (\U1/Channel1<7>_MC.Q \))
			((O) (\U1/Channel1 \(7)))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/Channel1<7>_MC_tsimcreated_xor__873 \ 0 10521 (_entity .  X_XOR2)
		(_port
			((I0) (\U1/Channel1<7>_MC.D \))
			((I1) (\U1/Channel1<7>_MC.Q \))
			((O) (\U1/Channel1<7>_MC_tsimcreated_xor_ \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/Channel1<7>_MC.REG \ 0 10526 (_entity .  X_FF)
		(_port
			((I) (\U1/Channel1<7>_MC_tsimcreated_xor_ \))
			((CE) (Vcc))
			((CLK) (\Mclk_II/FCLK \))
			((SET) (Gnd))
			((RST) (PRLD))
			((O) (\U1/Channel1<7>_MC.Q \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/Channel1<7>_MC.D_874 \ 0 10534 (_entity .  X_XOR2)
		(_port
			((I0) (\U1/Channel1<7>_MC.D1 \))
			((I1) (\U1/Channel1<7>_MC.D2 \))
			((O) (\U1/Channel1<7>_MC.D \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/Channel1<7>_MC.D1_875 \ 0 10539 (_entity .  X_ZERO)
		(_port
			((O) (\U1/Channel1<7>_MC.D1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/Channel1<7>_MC.D2_PT_0_876 \ 0 10542 (_entity .  X_AND2)
		(_port
			((I0) (\NlwInverterSignal_U1/Channel1<7>_MC.D2_PT_0/IN0 \))
			((I1) (\U1/Channel1 \(7)))
			((O) (\U1/Channel1<7>_MC.D2_PT_0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/Channel1<7>_MC.D2_PT_1_877 \ 0 10547 (_entity .  X_AND4)
		(_port
			((I0) (N_PZ_948))
			((I1) (N_PZ_1082))
			((I2) (N_PZ_993))
			((I3) (\U1/U5/location_Maddsub__n0000__n0103 \(0)))
			((O) (\U1/Channel1<7>_MC.D2_PT_1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/Channel1<7>_MC.D2_PT_2_878 \ 0 10554 (_entity .  X_AND4)
		(_port
			((I0) (N_PZ_948))
			((I1) (N_PZ_1082))
			((I2) (\NlwInverterSignal_U1/Channel1<7>_MC.D2_PT_2/IN2 \))
			((I3) (\NlwInverterSignal_U1/Channel1<7>_MC.D2_PT_2/IN3 \))
			((O) (\U1/Channel1<7>_MC.D2_PT_2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/Channel1<7>_MC.D2_879 \ 0 10561 (_entity .  X_OR3)
		(_port
			((I0) (\U1/Channel1<7>_MC.D2_PT_0 \))
			((I1) (\U1/Channel1<7>_MC.D2_PT_1 \))
			((I2) (\U1/Channel1<7>_MC.D2_PT_2 \))
			((O) (\U1/Channel1<7>_MC.D2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U5/location_Maddsub__n0000__n0103<0> \ 0 10567 (_entity .  X_BUF)
		(_port
			((I) (\U1/U5/location_Maddsub__n0000__n0103<0>_MC.Q \))
			((O) (\U1/U5/location_Maddsub__n0000__n0103 \(0)))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U5/location_Maddsub__n0000__n0103<0>_MC.Q_880 \ 0 10571 (_entity .  X_BUF)
		(_port
			((I) (\U1/U5/location_Maddsub__n0000__n0103<0>_MC.D \))
			((O) (\U1/U5/location_Maddsub__n0000__n0103<0>_MC.Q \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U5/location_Maddsub__n0000__n0103<0>_MC.D_881 \ 0 10575 (_entity .  X_XOR2)
		(_port
			((I0) (\U1/U5/location_Maddsub__n0000__n0103<0>_MC.D1 \))
			((I1) (\U1/U5/location_Maddsub__n0000__n0103<0>_MC.D2 \))
			((O) (\U1/U5/location_Maddsub__n0000__n0103<0>_MC.D \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U5/location_Maddsub__n0000__n0103<0>_MC.D1_882 \ 0 10580 (_entity .  X_AND2)
		(_port
			((I0) (N_PZ_968))
			((I1) (N_PZ_968))
			((O) (\U1/U5/location_Maddsub__n0000__n0103<0>_MC.D1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U5/location_Maddsub__n0000__n0103<0>_MC.D2_PT_0_883 \ 0 10585 (_entity .  X_AND4)
		(_port
			((I0) (\U1/Channel1 \(5)))
			((I1) (N_PZ_1226))
			((I2) (N_PZ_968))
			((I3) (\U1/Channel1 \(6)))
			((O) (\U1/U5/location_Maddsub__n0000__n0103<0>_MC.D2_PT_0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U5/location_Maddsub__n0000__n0103<0>_MC.D2_PT_1_884 \ 0 10592 (_entity .  X_AND8)
		(_port
			((I0) (\NlwInverterSignal_U1/U5/location_Maddsub__n0000__n0103<0>_MC.D2_PT_1/IN0 \))
			((I1) (\NlwInverterSignal_U1/U5/location_Maddsub__n0000__n0103<0>_MC.D2_PT_1/IN1 \))
			((I2) (\NlwInverterSignal_U1/U5/location_Maddsub__n0000__n0103<0>_MC.D2_PT_1/IN2 \))
			((I3) (\NlwInverterSignal_U1/U5/location_Maddsub__n0000__n0103<0>_MC.D2_PT_1/IN3 \))
			((I4) (\NlwInverterSignal_U1/U5/location_Maddsub__n0000__n0103<0>_MC.D2_PT_1/IN4 \))
			((I5) (\NlwInverterSignal_U1/U5/location_Maddsub__n0000__n0103<0>_MC.D2_PT_1/IN5 \))
			((I6) (\NlwInverterSignal_U1/U5/location_Maddsub__n0000__n0103<0>_MC.D2_PT_1/IN6 \))
			((I7) (\NlwInverterSignal_U1/U5/location_Maddsub__n0000__n0103<0>_MC.D2_PT_1/IN7 \))
			((O) (\U1/U5/location_Maddsub__n0000__n0103<0>_MC.D2_PT_1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U5/location_Maddsub__n0000__n0103<0>_MC.D2_885 \ 0 10603 (_entity .  X_OR2)
		(_port
			((I0) (\U1/U5/location_Maddsub__n0000__n0103<0>_MC.D2_PT_0 \))
			((I1) (\U1/U5/location_Maddsub__n0000__n0103<0>_MC.D2_PT_1 \))
			((O) (\U1/U5/location_Maddsub__n0000__n0103<0>_MC.D2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/Channel1<6> \ 0 10608 (_entity .  X_BUF)
		(_port
			((I) (\U1/Channel1<6>_MC.Q \))
			((O) (\U1/Channel1 \(6)))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/Channel1<6>_MC_tsimcreated_xor__886 \ 0 10612 (_entity .  X_XOR2)
		(_port
			((I0) (\U1/Channel1<6>_MC.D \))
			((I1) (\U1/Channel1<6>_MC.Q \))
			((O) (\U1/Channel1<6>_MC_tsimcreated_xor_ \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/Channel1<6>_MC.REG \ 0 10617 (_entity .  X_FF)
		(_port
			((I) (\U1/Channel1<6>_MC_tsimcreated_xor_ \))
			((CE) (Vcc))
			((CLK) (\Mclk_II/FCLK \))
			((SET) (Gnd))
			((RST) (PRLD))
			((O) (\U1/Channel1<6>_MC.Q \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/Channel1<6>_MC.D_887 \ 0 10625 (_entity .  X_XOR2)
		(_port
			((I0) (\U1/Channel1<6>_MC.D1 \))
			((I1) (\U1/Channel1<6>_MC.D2 \))
			((O) (\U1/Channel1<6>_MC.D \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/Channel1<6>_MC.D1_888 \ 0 10630 (_entity .  X_ZERO)
		(_port
			((O) (\U1/Channel1<6>_MC.D1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/Channel1<6>_MC.D2_PT_0_889 \ 0 10633 (_entity .  X_AND2)
		(_port
			((I0) (\NlwInverterSignal_U1/Channel1<6>_MC.D2_PT_0/IN0 \))
			((I1) (\U1/Channel1 \(6)))
			((O) (\U1/Channel1<6>_MC.D2_PT_0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/Channel1<6>_MC.D2_PT_1_890 \ 0 10638 (_entity .  X_AND5)
		(_port
			((I0) (\U1/Channel1 \(5)))
			((I1) (N_PZ_1082))
			((I2) (\NlwInverterSignal_U1/Channel1<6>_MC.D2_PT_1/IN2 \))
			((I3) (\NlwInverterSignal_U1/Channel1<6>_MC.D2_PT_1/IN3 \))
			((I4) (\U1/Channel1 \(6)))
			((O) (\U1/Channel1<6>_MC.D2_PT_1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/Channel1<6>_MC.D2_PT_2_891 \ 0 10646 (_entity .  X_AND5)
		(_port
			((I0) (N_PZ_948))
			((I1) (N_PZ_1082))
			((I2) (N_PZ_993))
			((I3) (\U1/U5/location_Maddsub__n0000__n0103 \(0)))
			((I4) (\NlwInverterSignal_U1/Channel1<6>_MC.D2_PT_2/IN4 \))
			((O) (\U1/Channel1<6>_MC.D2_PT_2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/Channel1<6>_MC.D2_PT_3_892 \ 0 10654 (_entity .  X_AND5)
		(_port
			((I0) (N_PZ_1082))
			((I1) (\NlwInverterSignal_U1/Channel1<6>_MC.D2_PT_3/IN1 \))
			((I2) (\NlwInverterSignal_U1/Channel1<6>_MC.D2_PT_3/IN2 \))
			((I3) (\NlwInverterSignal_U1/Channel1<6>_MC.D2_PT_3/IN3 \))
			((I4) (\U1/Channel1 \(6)))
			((O) (\U1/Channel1<6>_MC.D2_PT_3 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/Channel1<6>_MC.D2_PT_4_893 \ 0 10662 (_entity .  X_AND6)
		(_port
			((I0) (\U1/Channel1 \(5)))
			((I1) (N_PZ_948))
			((I2) (N_PZ_1082))
			((I3) (N_PZ_1226))
			((I4) (\U1/U5/location_Maddsub__n0000__n0103 \(0)))
			((I5) (\NlwInverterSignal_U1/Channel1<6>_MC.D2_PT_4/IN5 \))
			((O) (\U1/Channel1<6>_MC.D2_PT_4 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/Channel1<6>_MC.D2_PT_5_894 \ 0 10671 (_entity .  X_AND16)
		(_port
			((I0) (\NlwInverterSignal_U1/Channel1<6>_MC.D2_PT_5/IN0 \))
			((I1) (N_PZ_1082))
			((I2) (\NlwInverterSignal_U1/Channel1<6>_MC.D2_PT_5/IN2 \))
			((I3) (\NlwInverterSignal_U1/Channel1<6>_MC.D2_PT_5/IN3 \))
			((I4) (\NlwInverterSignal_U1/Channel1<6>_MC.D2_PT_5/IN4 \))
			((I5) (\NlwInverterSignal_U1/Channel1<6>_MC.D2_PT_5/IN5 \))
			((I6) (\NlwInverterSignal_U1/Channel1<6>_MC.D2_PT_5/IN6 \))
			((I7) (\NlwInverterSignal_U1/Channel1<6>_MC.D2_PT_5/IN7 \))
			((I8) (\U1/Channel1 \(6)))
			((I9) (Vcc))
			((I10) (Vcc))
			((I11) (Vcc))
			((I12) (Vcc))
			((I13) (Vcc))
			((I14) (Vcc))
			((I15) (Vcc))
			((O) (\U1/Channel1<6>_MC.D2_PT_5 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/Channel1<6>_MC.D2_895 \ 0 10690 (_entity .  X_OR6)
		(_port
			((I0) (\U1/Channel1<6>_MC.D2_PT_0 \))
			((I1) (\U1/Channel1<6>_MC.D2_PT_1 \))
			((I2) (\U1/Channel1<6>_MC.D2_PT_2 \))
			((I3) (\U1/Channel1<6>_MC.D2_PT_3 \))
			((I4) (\U1/Channel1<6>_MC.D2_PT_4 \))
			((I5) (\U1/Channel1<6>_MC.D2_PT_5 \))
			((O) (\U1/Channel1<6>_MC.D2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/Channel1<8> \ 0 10699 (_entity .  X_BUF)
		(_port
			((I) (\U1/Channel1<8>_MC.Q \))
			((O) (\U1/Channel1 \(8)))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/Channel1<8>_MC_tsimcreated_xor__896 \ 0 10703 (_entity .  X_XOR2)
		(_port
			((I0) (\U1/Channel1<8>_MC.D \))
			((I1) (\U1/Channel1<8>_MC.Q \))
			((O) (\U1/Channel1<8>_MC_tsimcreated_xor_ \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/Channel1<8>_MC.REG \ 0 10708 (_entity .  X_FF)
		(_port
			((I) (\U1/Channel1<8>_MC_tsimcreated_xor_ \))
			((CE) (Vcc))
			((CLK) (\Mclk_II/FCLK \))
			((SET) (Gnd))
			((RST) (PRLD))
			((O) (\U1/Channel1<8>_MC.Q \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/Channel1<8>_MC.D_897 \ 0 10716 (_entity .  X_XOR2)
		(_port
			((I0) (\U1/Channel1<8>_MC.D1 \))
			((I1) (\U1/Channel1<8>_MC.D2 \))
			((O) (\U1/Channel1<8>_MC.D \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/Channel1<8>_MC.D1_898 \ 0 10721 (_entity .  X_ZERO)
		(_port
			((O) (\U1/Channel1<8>_MC.D1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/Channel1<8>_MC.D2_PT_0_899 \ 0 10724 (_entity .  X_AND2)
		(_port
			((I0) (\NlwInverterSignal_U1/Channel1<8>_MC.D2_PT_0/IN0 \))
			((I1) (\U1/Channel1 \(8)))
			((O) (\U1/Channel1<8>_MC.D2_PT_0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/Channel1<8>_MC.D2_PT_1_900 \ 0 10729 (_entity .  X_AND5)
		(_port
			((I0) (N_PZ_948))
			((I1) (N_PZ_1082))
			((I2) (N_PZ_993))
			((I3) (\NlwInverterSignal_U1/Channel1<8>_MC.D2_PT_1/IN3 \))
			((I4) (\U1/U5/location_Maddsub__n0000__n0103 \(0)))
			((O) (\U1/Channel1<8>_MC.D2_PT_1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/Channel1<8>_MC.D2_PT_2_901 \ 0 10737 (_entity .  X_AND5)
		(_port
			((I0) (N_PZ_948))
			((I1) (N_PZ_1082))
			((I2) (\NlwInverterSignal_U1/Channel1<8>_MC.D2_PT_2/IN2 \))
			((I3) (\U1/Channel1 \(7)))
			((I4) (\NlwInverterSignal_U1/Channel1<8>_MC.D2_PT_2/IN4 \))
			((O) (\U1/Channel1<8>_MC.D2_PT_2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/Channel1<8>_MC.D2_902 \ 0 10745 (_entity .  X_OR3)
		(_port
			((I0) (\U1/Channel1<8>_MC.D2_PT_0 \))
			((I1) (\U1/Channel1<8>_MC.D2_PT_1 \))
			((I2) (\U1/Channel1<8>_MC.D2_PT_2 \))
			((O) (\U1/Channel1<8>_MC.D2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/Channel1<9> \ 0 10751 (_entity .  X_BUF)
		(_port
			((I) (\U1/Channel1<9>_MC.Q \))
			((O) (\U1/Channel1 \(9)))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/Channel1<9>_MC_tsimcreated_xor__903 \ 0 10755 (_entity .  X_XOR2)
		(_port
			((I0) (\U1/Channel1<9>_MC.D \))
			((I1) (\U1/Channel1<9>_MC.Q \))
			((O) (\U1/Channel1<9>_MC_tsimcreated_xor_ \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/Channel1<9>_MC.REG \ 0 10760 (_entity .  X_FF)
		(_port
			((I) (\U1/Channel1<9>_MC_tsimcreated_xor_ \))
			((CE) (Vcc))
			((CLK) (\Mclk_II/FCLK \))
			((SET) (Gnd))
			((RST) (PRLD))
			((O) (\U1/Channel1<9>_MC.Q \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/Channel1<9>_MC.D_904 \ 0 10768 (_entity .  X_XOR2)
		(_port
			((I0) (\U1/Channel1<9>_MC.D1 \))
			((I1) (\U1/Channel1<9>_MC.D2 \))
			((O) (\U1/Channel1<9>_MC.D \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/Channel1<9>_MC.D1_905 \ 0 10773 (_entity .  X_ZERO)
		(_port
			((O) (\U1/Channel1<9>_MC.D1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/Channel1<9>_MC.D2_PT_0_906 \ 0 10776 (_entity .  X_AND2)
		(_port
			((I0) (\NlwInverterSignal_U1/Channel1<9>_MC.D2_PT_0/IN0 \))
			((I1) (\U1/Channel1 \(9)))
			((O) (\U1/Channel1<9>_MC.D2_PT_0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/Channel1<9>_MC.D2_PT_1_907 \ 0 10781 (_entity .  X_AND6)
		(_port
			((I0) (N_PZ_948))
			((I1) (N_PZ_1082))
			((I2) (N_PZ_993))
			((I3) (\NlwInverterSignal_U1/Channel1<9>_MC.D2_PT_1/IN3 \))
			((I4) (\U1/U5/location_Maddsub__n0000__n0103 \(0)))
			((I5) (\NlwInverterSignal_U1/Channel1<9>_MC.D2_PT_1/IN5 \))
			((O) (\U1/Channel1<9>_MC.D2_PT_1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/Channel1<9>_MC.D2_PT_2_908 \ 0 10790 (_entity .  X_AND6)
		(_port
			((I0) (N_PZ_948))
			((I1) (N_PZ_1082))
			((I2) (\NlwInverterSignal_U1/Channel1<9>_MC.D2_PT_2/IN2 \))
			((I3) (\U1/Channel1 \(7)))
			((I4) (\NlwInverterSignal_U1/Channel1<9>_MC.D2_PT_2/IN4 \))
			((I5) (\U1/Channel1 \(8)))
			((O) (\U1/Channel1<9>_MC.D2_PT_2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/Channel1<9>_MC.D2_909 \ 0 10799 (_entity .  X_OR3)
		(_port
			((I0) (\U1/Channel1<9>_MC.D2_PT_0 \))
			((I1) (\U1/Channel1<9>_MC.D2_PT_1 \))
			((I2) (\U1/Channel1<9>_MC.D2_PT_2 \))
			((O) (\U1/Channel1<9>_MC.D2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/Channel1<11> \ 0 10805 (_entity .  X_BUF)
		(_port
			((I) (\U1/Channel1<11>_MC.Q \))
			((O) (\U1/Channel1 \(11)))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/Channel1<11>_MC.REG \ 0 10809 (_entity .  X_FF)
		(_port
			((I) (\U1/Channel1<11>_MC.D \))
			((CE) (Vcc))
			((CLK) (\Mclk_II/FCLK \))
			((SET) (Gnd))
			((RST) (PRLD))
			((O) (\U1/Channel1<11>_MC.Q \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/Channel1<11>_MC.D_910 \ 0 10817 (_entity .  X_XOR2)
		(_port
			((I0) (\U1/Channel1<11>_MC.D1 \))
			((I1) (\U1/Channel1<11>_MC.D2 \))
			((O) (\U1/Channel1<11>_MC.D \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/Channel1<11>_MC.D1_911 \ 0 10822 (_entity .  X_AND2)
		(_port
			((I0) (\U1/Channel1 \(11)))
			((I1) (\U1/Channel1 \(11)))
			((O) (\U1/Channel1<11>_MC.D1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/Channel1<11>_MC.D2_PT_0_912 \ 0 10827 (_entity .  X_AND2)
		(_port
			((I0) (\NlwInverterSignal_U1/Channel1<11>_MC.D2_PT_0/IN0 \))
			((I1) (\U1/Channel1 \(11)))
			((O) (\U1/Channel1<11>_MC.D2_PT_0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/Channel1<11>_MC.D2_PT_1_913 \ 0 10832 (_entity .  X_AND4)
		(_port
			((I0) (N_PZ_948))
			((I1) (N_PZ_1082))
			((I2) (\NlwInverterSignal_U1/Channel1<11>_MC.D2_PT_1/IN2 \))
			((I3) (N_PZ_1055))
			((O) (\U1/Channel1<11>_MC.D2_PT_1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/Channel1<11>_MC.D2_PT_2_914 \ 0 10839 (_entity .  X_AND5)
		(_port
			((I0) (N_PZ_948))
			((I1) (N_PZ_1082))
			((I2) (\NlwInverterSignal_U1/Channel1<11>_MC.D2_PT_2/IN2 \))
			((I3) (N_PZ_1055))
			((I4) (\NlwInverterSignal_U1/Channel1<11>_MC.D2_PT_2/IN4 \))
			((O) (\U1/Channel1<11>_MC.D2_PT_2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/Channel1<11>_MC.D2_PT_3_915 \ 0 10847 (_entity .  X_AND8)
		(_port
			((I0) (N_PZ_948))
			((I1) (N_PZ_1082))
			((I2) (N_PZ_993))
			((I3) (\NlwInverterSignal_U1/Channel1<11>_MC.D2_PT_3/IN3 \))
			((I4) (\NlwInverterSignal_U1/Channel1<11>_MC.D2_PT_3/IN4 \))
			((I5) (\U1/U5/location_Maddsub__n0000__n0103 \(0)))
			((I6) (\NlwInverterSignal_U1/Channel1<11>_MC.D2_PT_3/IN6 \))
			((I7) (\NlwInverterSignal_U1/Channel1<11>_MC.D2_PT_3/IN7 \))
			((O) (\U1/Channel1<11>_MC.D2_PT_3 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/Channel1<11>_MC.D2_916 \ 0 10858 (_entity .  X_OR4)
		(_port
			((I0) (\U1/Channel1<11>_MC.D2_PT_0 \))
			((I1) (\U1/Channel1<11>_MC.D2_PT_1 \))
			((I2) (\U1/Channel1<11>_MC.D2_PT_2 \))
			((I3) (\U1/Channel1<11>_MC.D2_PT_3 \))
			((O) (\U1/Channel1<11>_MC.D2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation N_PZ_1055_917 0 10865 (_entity .  X_BUF)
		(_port
			((I) (\N_PZ_1055_MC.Q \))
			((O) (N_PZ_1055))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \N_PZ_1055_MC.Q_918 \ 0 10869 (_entity .  X_BUF)
		(_port
			((I) (\N_PZ_1055_MC.D \))
			((O) (\N_PZ_1055_MC.Q \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \N_PZ_1055_MC.D_919 \ 0 10873 (_entity .  X_XOR2)
		(_port
			((I0) (\N_PZ_1055_MC.D1 \))
			((I1) (\N_PZ_1055_MC.D2 \))
			((O) (\N_PZ_1055_MC.D \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \N_PZ_1055_MC.D1_920 \ 0 10878 (_entity .  X_AND5)
		(_port
			((I0) (\U1/Channel1 \(10)))
			((I1) (\U1/Channel1 \(7)))
			((I2) (\NlwInverterSignal_N_PZ_1055_MC.D1/IN2 \))
			((I3) (\U1/Channel1 \(8)))
			((I4) (\U1/Channel1 \(9)))
			((O) (\N_PZ_1055_MC.D1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \N_PZ_1055_MC.D2_921 \ 0 10886 (_entity .  X_ZERO)
		(_port
			((O) (\N_PZ_1055_MC.D2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/Channel1<12> \ 0 10889 (_entity .  X_BUF)
		(_port
			((I) (\U1/Channel1<12>_MC.Q \))
			((O) (\U1/Channel1 \(12)))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/Channel1<12>_MC_tsimcreated_xor__922 \ 0 10893 (_entity .  X_XOR2)
		(_port
			((I0) (\U1/Channel1<12>_MC.D \))
			((I1) (\U1/Channel1<12>_MC.Q \))
			((O) (\U1/Channel1<12>_MC_tsimcreated_xor_ \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/Channel1<12>_MC.REG \ 0 10898 (_entity .  X_FF)
		(_port
			((I) (\U1/Channel1<12>_MC_tsimcreated_xor_ \))
			((CE) (Vcc))
			((CLK) (\Mclk_II/FCLK \))
			((SET) (Gnd))
			((RST) (PRLD))
			((O) (\U1/Channel1<12>_MC.Q \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/Channel1<12>_MC.D_923 \ 0 10906 (_entity .  X_XOR2)
		(_port
			((I0) (\U1/Channel1<12>_MC.D1 \))
			((I1) (\U1/Channel1<12>_MC.D2 \))
			((O) (\U1/Channel1<12>_MC.D \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/Channel1<12>_MC.D1_924 \ 0 10911 (_entity .  X_ZERO)
		(_port
			((O) (\U1/Channel1<12>_MC.D1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/Channel1<12>_MC.D2_PT_0_925 \ 0 10914 (_entity .  X_AND2)
		(_port
			((I0) (\NlwInverterSignal_U1/Channel1<12>_MC.D2_PT_0/IN0 \))
			((I1) (\U1/Channel1 \(12)))
			((O) (\U1/Channel1<12>_MC.D2_PT_0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/Channel1<12>_MC.D2_PT_1_926 \ 0 10919 (_entity .  X_AND5)
		(_port
			((I0) (N_PZ_948))
			((I1) (N_PZ_1082))
			((I2) (N_PZ_993))
			((I3) (\U1/U5/location_Maddsub__n0000__n0115 \(0)))
			((I4) (\NlwInverterSignal_U1/Channel1<12>_MC.D2_PT_1/IN4 \))
			((O) (\U1/Channel1<12>_MC.D2_PT_1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/Channel1<12>_MC.D2_PT_2_927 \ 0 10927 (_entity .  X_AND5)
		(_port
			((I0) (N_PZ_1082))
			((I1) (\NlwInverterSignal_U1/Channel1<12>_MC.D2_PT_2/IN1 \))
			((I2) (\NlwInverterSignal_U1/Channel1<12>_MC.D2_PT_2/IN2 \))
			((I3) (\U1/Channel1 \(11)))
			((I4) (\U1/Channel1 \(12)))
			((O) (\U1/Channel1<12>_MC.D2_PT_2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/Channel1<12>_MC.D2_PT_3_928 \ 0 10935 (_entity .  X_AND5)
		(_port
			((I0) (N_PZ_1082))
			((I1) (\NlwInverterSignal_U1/Channel1<12>_MC.D2_PT_3/IN1 \))
			((I2) (\NlwInverterSignal_U1/Channel1<12>_MC.D2_PT_3/IN2 \))
			((I3) (\NlwInverterSignal_U1/Channel1<12>_MC.D2_PT_3/IN3 \))
			((I4) (\U1/Channel1 \(12)))
			((O) (\U1/Channel1<12>_MC.D2_PT_3 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/Channel1<12>_MC.D2_PT_4_929 \ 0 10943 (_entity .  X_AND6)
		(_port
			((I0) (N_PZ_948))
			((I1) (N_PZ_1082))
			((I2) (\U1/U5/location_Maddsub__n0000__n0115 \(0)))
			((I3) (\U1/Channel1 \(11)))
			((I4) (N_PZ_1055))
			((I5) (\NlwInverterSignal_U1/Channel1<12>_MC.D2_PT_4/IN5 \))
			((O) (\U1/Channel1<12>_MC.D2_PT_4 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/Channel1<12>_MC.D2_PT_5_930 \ 0 10952 (_entity .  X_AND16)
		(_port
			((I0) (N_PZ_1082))
			((I1) (\NlwInverterSignal_U1/Channel1<12>_MC.D2_PT_5/IN1 \))
			((I2) (\NlwInverterSignal_U1/Channel1<12>_MC.D2_PT_5/IN2 \))
			((I3) (\U1/Channel1 \(12)))
			((I4) (\NlwInverterSignal_U1/Channel1<12>_MC.D2_PT_5/IN4 \))
			((I5) (\NlwInverterSignal_U1/Channel1<12>_MC.D2_PT_5/IN5 \))
			((I6) (\U1/U5/location_Maddsub__n0000__n0103 \(0)))
			((I7) (\NlwInverterSignal_U1/Channel1<12>_MC.D2_PT_5/IN7 \))
			((I8) (\NlwInverterSignal_U1/Channel1<12>_MC.D2_PT_5/IN8 \))
			((I9) (Vcc))
			((I10) (Vcc))
			((I11) (Vcc))
			((I12) (Vcc))
			((I13) (Vcc))
			((I14) (Vcc))
			((I15) (Vcc))
			((O) (\U1/Channel1<12>_MC.D2_PT_5 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/Channel1<12>_MC.D2_931 \ 0 10971 (_entity .  X_OR6)
		(_port
			((I0) (\U1/Channel1<12>_MC.D2_PT_0 \))
			((I1) (\U1/Channel1<12>_MC.D2_PT_1 \))
			((I2) (\U1/Channel1<12>_MC.D2_PT_2 \))
			((I3) (\U1/Channel1<12>_MC.D2_PT_3 \))
			((I4) (\U1/Channel1<12>_MC.D2_PT_4 \))
			((I5) (\U1/Channel1<12>_MC.D2_PT_5 \))
			((O) (\U1/Channel1<12>_MC.D2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/Channel1<14> \ 0 10980 (_entity .  X_BUF)
		(_port
			((I) (\U1/Channel1<14>_MC.Q \))
			((O) (\U1/Channel1 \(14)))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/Channel1<14>_MC_tsimcreated_xor__932 \ 0 10984 (_entity .  X_XOR2)
		(_port
			((I0) (\U1/Channel1<14>_MC.D \))
			((I1) (\U1/Channel1<14>_MC.Q \))
			((O) (\U1/Channel1<14>_MC_tsimcreated_xor_ \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/Channel1<14>_MC.REG \ 0 10989 (_entity .  X_FF)
		(_port
			((I) (\U1/Channel1<14>_MC_tsimcreated_xor_ \))
			((CE) (Vcc))
			((CLK) (\Mclk_II/FCLK \))
			((SET) (Gnd))
			((RST) (PRLD))
			((O) (\U1/Channel1<14>_MC.Q \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/Channel1<14>_MC.D_933 \ 0 10997 (_entity .  X_XOR2)
		(_port
			((I0) (\U1/Channel1<14>_MC.D1 \))
			((I1) (\U1/Channel1<14>_MC.D2 \))
			((O) (\U1/Channel1<14>_MC.D \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/Channel1<14>_MC.D1_934 \ 0 11002 (_entity .  X_ZERO)
		(_port
			((O) (\U1/Channel1<14>_MC.D1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/Channel1<14>_MC.D2_PT_0_935 \ 0 11005 (_entity .  X_AND2)
		(_port
			((I0) (\NlwInverterSignal_U1/Channel1<14>_MC.D2_PT_0/IN0 \))
			((I1) (\U1/Channel1 \(14)))
			((O) (\U1/Channel1<14>_MC.D2_PT_0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/Channel1<14>_MC.D2_PT_1_936 \ 0 11010 (_entity .  X_AND5)
		(_port
			((I0) (N_PZ_948))
			((I1) (N_PZ_1082))
			((I2) (N_PZ_993))
			((I3) (\NlwInverterSignal_U1/Channel1<14>_MC.D2_PT_1/IN3 \))
			((I4) (\U1/U5/location_Maddsub__n0000__n0115 \(0)))
			((O) (\U1/Channel1<14>_MC.D2_PT_1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/Channel1<14>_MC.D2_PT_2_937 \ 0 11018 (_entity .  X_AND5)
		(_port
			((I0) (N_PZ_948))
			((I1) (N_PZ_1082))
			((I2) (\NlwInverterSignal_U1/Channel1<14>_MC.D2_PT_2/IN2 \))
			((I3) (\U1/Channel1 \(13)))
			((I4) (\NlwInverterSignal_U1/Channel1<14>_MC.D2_PT_2/IN4 \))
			((O) (\U1/Channel1<14>_MC.D2_PT_2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/Channel1<14>_MC.D2_938 \ 0 11026 (_entity .  X_OR3)
		(_port
			((I0) (\U1/Channel1<14>_MC.D2_PT_0 \))
			((I1) (\U1/Channel1<14>_MC.D2_PT_1 \))
			((I2) (\U1/Channel1<14>_MC.D2_PT_2 \))
			((O) (\U1/Channel1<14>_MC.D2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/Channel1<15> \ 0 11032 (_entity .  X_BUF)
		(_port
			((I) (\U1/Channel1<15>_MC.Q \))
			((O) (\U1/Channel1 \(15)))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/Channel1<15>_MC_tsimcreated_xor__939 \ 0 11036 (_entity .  X_XOR2)
		(_port
			((I0) (\U1/Channel1<15>_MC.D \))
			((I1) (\U1/Channel1<15>_MC.Q \))
			((O) (\U1/Channel1<15>_MC_tsimcreated_xor_ \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/Channel1<15>_MC.REG \ 0 11041 (_entity .  X_FF)
		(_port
			((I) (\U1/Channel1<15>_MC_tsimcreated_xor_ \))
			((CE) (Vcc))
			((CLK) (\Mclk_II/FCLK \))
			((SET) (Gnd))
			((RST) (PRLD))
			((O) (\U1/Channel1<15>_MC.Q \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/Channel1<15>_MC.D_940 \ 0 11049 (_entity .  X_XOR2)
		(_port
			((I0) (\U1/Channel1<15>_MC.D1 \))
			((I1) (\U1/Channel1<15>_MC.D2 \))
			((O) (\U1/Channel1<15>_MC.D \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/Channel1<15>_MC.D1_941 \ 0 11054 (_entity .  X_ZERO)
		(_port
			((O) (\U1/Channel1<15>_MC.D1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/Channel1<15>_MC.D2_PT_0_942 \ 0 11057 (_entity .  X_AND2)
		(_port
			((I0) (\NlwInverterSignal_U1/Channel1<15>_MC.D2_PT_0/IN0 \))
			((I1) (\U1/Channel1 \(15)))
			((O) (\U1/Channel1<15>_MC.D2_PT_0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/Channel1<15>_MC.D2_PT_1_943 \ 0 11062 (_entity .  X_AND6)
		(_port
			((I0) (N_PZ_948))
			((I1) (N_PZ_1082))
			((I2) (N_PZ_993))
			((I3) (\NlwInverterSignal_U1/Channel1<15>_MC.D2_PT_1/IN3 \))
			((I4) (\U1/U5/location_Maddsub__n0000__n0115 \(0)))
			((I5) (\NlwInverterSignal_U1/Channel1<15>_MC.D2_PT_1/IN5 \))
			((O) (\U1/Channel1<15>_MC.D2_PT_1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/Channel1<15>_MC.D2_PT_2_944 \ 0 11071 (_entity .  X_AND6)
		(_port
			((I0) (N_PZ_948))
			((I1) (N_PZ_1082))
			((I2) (\NlwInverterSignal_U1/Channel1<15>_MC.D2_PT_2/IN2 \))
			((I3) (\U1/Channel1 \(13)))
			((I4) (\NlwInverterSignal_U1/Channel1<15>_MC.D2_PT_2/IN4 \))
			((I5) (\U1/Channel1 \(14)))
			((O) (\U1/Channel1<15>_MC.D2_PT_2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/Channel1<15>_MC.D2_945 \ 0 11080 (_entity .  X_OR3)
		(_port
			((I0) (\U1/Channel1<15>_MC.D2_PT_0 \))
			((I1) (\U1/Channel1<15>_MC.D2_PT_1 \))
			((I2) (\U1/Channel1<15>_MC.D2_PT_2 \))
			((O) (\U1/Channel1<15>_MC.D2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/Channel1<16> \ 0 11086 (_entity .  X_BUF)
		(_port
			((I) (\U1/Channel1<16>_MC.Q \))
			((O) (\U1/Channel1 \(16)))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/Channel1<16>_MC_tsimcreated_xor__946 \ 0 11090 (_entity .  X_XOR2)
		(_port
			((I0) (\U1/Channel1<16>_MC.D \))
			((I1) (\U1/Channel1<16>_MC.Q \))
			((O) (\U1/Channel1<16>_MC_tsimcreated_xor_ \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/Channel1<16>_MC.REG \ 0 11095 (_entity .  X_FF)
		(_port
			((I) (\U1/Channel1<16>_MC_tsimcreated_xor_ \))
			((CE) (Vcc))
			((CLK) (\Mclk_II/FCLK \))
			((SET) (Gnd))
			((RST) (PRLD))
			((O) (\U1/Channel1<16>_MC.Q \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/Channel1<16>_MC.D_947 \ 0 11103 (_entity .  X_XOR2)
		(_port
			((I0) (\U1/Channel1<16>_MC.D1 \))
			((I1) (\U1/Channel1<16>_MC.D2 \))
			((O) (\U1/Channel1<16>_MC.D \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/Channel1<16>_MC.D1_948 \ 0 11108 (_entity .  X_ZERO)
		(_port
			((O) (\U1/Channel1<16>_MC.D1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/Channel1<16>_MC.D2_PT_0_949 \ 0 11111 (_entity .  X_AND2)
		(_port
			((I0) (\NlwInverterSignal_U1/Channel1<16>_MC.D2_PT_0/IN0 \))
			((I1) (\U1/Channel1 \(16)))
			((O) (\U1/Channel1<16>_MC.D2_PT_0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/Channel1<16>_MC.D2_PT_1_950 \ 0 11116 (_entity .  X_AND7)
		(_port
			((I0) (N_PZ_948))
			((I1) (N_PZ_1082))
			((I2) (N_PZ_993))
			((I3) (\NlwInverterSignal_U1/Channel1<16>_MC.D2_PT_1/IN3 \))
			((I4) (\U1/U5/location_Maddsub__n0000__n0115 \(0)))
			((I5) (\NlwInverterSignal_U1/Channel1<16>_MC.D2_PT_1/IN5 \))
			((I6) (\NlwInverterSignal_U1/Channel1<16>_MC.D2_PT_1/IN6 \))
			((O) (\U1/Channel1<16>_MC.D2_PT_1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/Channel1<16>_MC.D2_PT_2_951 \ 0 11126 (_entity .  X_AND7)
		(_port
			((I0) (N_PZ_948))
			((I1) (N_PZ_1082))
			((I2) (\NlwInverterSignal_U1/Channel1<16>_MC.D2_PT_2/IN2 \))
			((I3) (\U1/Channel1 \(13)))
			((I4) (\NlwInverterSignal_U1/Channel1<16>_MC.D2_PT_2/IN4 \))
			((I5) (\U1/Channel1 \(14)))
			((I6) (\U1/Channel1 \(15)))
			((O) (\U1/Channel1<16>_MC.D2_PT_2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/Channel1<16>_MC.D2_952 \ 0 11136 (_entity .  X_OR3)
		(_port
			((I0) (\U1/Channel1<16>_MC.D2_PT_0 \))
			((I1) (\U1/Channel1<16>_MC.D2_PT_1 \))
			((I2) (\U1/Channel1<16>_MC.D2_PT_2 \))
			((O) (\U1/Channel1<16>_MC.D2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/Channel1<17> \ 0 11142 (_entity .  X_BUF)
		(_port
			((I) (\U1/Channel1<17>_MC.Q \))
			((O) (\U1/Channel1 \(17)))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/Channel1<17>_MC_tsimcreated_xor__953 \ 0 11146 (_entity .  X_XOR2)
		(_port
			((I0) (\U1/Channel1<17>_MC.D \))
			((I1) (\U1/Channel1<17>_MC.Q \))
			((O) (\U1/Channel1<17>_MC_tsimcreated_xor_ \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/Channel1<17>_MC.REG \ 0 11151 (_entity .  X_FF)
		(_port
			((I) (\U1/Channel1<17>_MC_tsimcreated_xor_ \))
			((CE) (Vcc))
			((CLK) (\Mclk_II/FCLK \))
			((SET) (Gnd))
			((RST) (PRLD))
			((O) (\U1/Channel1<17>_MC.Q \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/Channel1<17>_MC.D_954 \ 0 11159 (_entity .  X_XOR2)
		(_port
			((I0) (\U1/Channel1<17>_MC.D1 \))
			((I1) (\U1/Channel1<17>_MC.D2 \))
			((O) (\U1/Channel1<17>_MC.D \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/Channel1<17>_MC.D1_955 \ 0 11164 (_entity .  X_ZERO)
		(_port
			((O) (\U1/Channel1<17>_MC.D1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/Channel1<17>_MC.D2_PT_0_956 \ 0 11167 (_entity .  X_AND2)
		(_port
			((I0) (\NlwInverterSignal_U1/Channel1<17>_MC.D2_PT_0/IN0 \))
			((I1) (\U1/Channel1 \(17)))
			((O) (\U1/Channel1<17>_MC.D2_PT_0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/Channel1<17>_MC.D2_PT_1_957 \ 0 11172 (_entity .  X_AND8)
		(_port
			((I0) (N_PZ_948))
			((I1) (N_PZ_1082))
			((I2) (N_PZ_993))
			((I3) (\NlwInverterSignal_U1/Channel1<17>_MC.D2_PT_1/IN3 \))
			((I4) (\U1/U5/location_Maddsub__n0000__n0115 \(0)))
			((I5) (\NlwInverterSignal_U1/Channel1<17>_MC.D2_PT_1/IN5 \))
			((I6) (\NlwInverterSignal_U1/Channel1<17>_MC.D2_PT_1/IN6 \))
			((I7) (\NlwInverterSignal_U1/Channel1<17>_MC.D2_PT_1/IN7 \))
			((O) (\U1/Channel1<17>_MC.D2_PT_1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/Channel1<17>_MC.D2_PT_2_958 \ 0 11183 (_entity .  X_AND8)
		(_port
			((I0) (N_PZ_948))
			((I1) (N_PZ_1082))
			((I2) (\NlwInverterSignal_U1/Channel1<17>_MC.D2_PT_2/IN2 \))
			((I3) (\U1/Channel1 \(13)))
			((I4) (\NlwInverterSignal_U1/Channel1<17>_MC.D2_PT_2/IN4 \))
			((I5) (\U1/Channel1 \(14)))
			((I6) (\U1/Channel1 \(15)))
			((I7) (\U1/Channel1 \(16)))
			((O) (\U1/Channel1<17>_MC.D2_PT_2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/Channel1<17>_MC.D2_959 \ 0 11194 (_entity .  X_OR3)
		(_port
			((I0) (\U1/Channel1<17>_MC.D2_PT_0 \))
			((I1) (\U1/Channel1<17>_MC.D2_PT_1 \))
			((I2) (\U1/Channel1<17>_MC.D2_PT_2 \))
			((O) (\U1/Channel1<17>_MC.D2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/Channel1<18> \ 0 11200 (_entity .  X_BUF)
		(_port
			((I) (\U1/Channel1<18>_MC.Q \))
			((O) (\U1/Channel1 \(18)))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/Channel1<18>_MC_tsimcreated_xor__960 \ 0 11204 (_entity .  X_XOR2)
		(_port
			((I0) (\U1/Channel1<18>_MC.D \))
			((I1) (\U1/Channel1<18>_MC.Q \))
			((O) (\U1/Channel1<18>_MC_tsimcreated_xor_ \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/Channel1<18>_MC.REG \ 0 11209 (_entity .  X_FF)
		(_port
			((I) (\U1/Channel1<18>_MC_tsimcreated_xor_ \))
			((CE) (Vcc))
			((CLK) (\Mclk_II/FCLK \))
			((SET) (Gnd))
			((RST) (PRLD))
			((O) (\U1/Channel1<18>_MC.Q \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/Channel1<18>_MC.D_961 \ 0 11217 (_entity .  X_XOR2)
		(_port
			((I0) (\U1/Channel1<18>_MC.D1 \))
			((I1) (\U1/Channel1<18>_MC.D2 \))
			((O) (\U1/Channel1<18>_MC.D \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/Channel1<18>_MC.D1_962 \ 0 11222 (_entity .  X_ZERO)
		(_port
			((O) (\U1/Channel1<18>_MC.D1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/Channel1<18>_MC.D2_PT_0_963 \ 0 11225 (_entity .  X_AND2)
		(_port
			((I0) (\NlwInverterSignal_U1/Channel1<18>_MC.D2_PT_0/IN0 \))
			((I1) (\U1/Channel1 \(18)))
			((O) (\U1/Channel1<18>_MC.D2_PT_0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/Channel1<18>_MC.D2_PT_1_964 \ 0 11230 (_entity .  X_AND16)
		(_port
			((I0) (N_PZ_948))
			((I1) (N_PZ_1082))
			((I2) (N_PZ_993))
			((I3) (\NlwInverterSignal_U1/Channel1<18>_MC.D2_PT_1/IN3 \))
			((I4) (\U1/U5/location_Maddsub__n0000__n0115 \(0)))
			((I5) (\NlwInverterSignal_U1/Channel1<18>_MC.D2_PT_1/IN5 \))
			((I6) (\NlwInverterSignal_U1/Channel1<18>_MC.D2_PT_1/IN6 \))
			((I7) (\NlwInverterSignal_U1/Channel1<18>_MC.D2_PT_1/IN7 \))
			((I8) (\NlwInverterSignal_U1/Channel1<18>_MC.D2_PT_1/IN8 \))
			((I9) (Vcc))
			((I10) (Vcc))
			((I11) (Vcc))
			((I12) (Vcc))
			((I13) (Vcc))
			((I14) (Vcc))
			((I15) (Vcc))
			((O) (\U1/Channel1<18>_MC.D2_PT_1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/Channel1<18>_MC.D2_PT_2_965 \ 0 11249 (_entity .  X_AND16)
		(_port
			((I0) (N_PZ_948))
			((I1) (N_PZ_1082))
			((I2) (\NlwInverterSignal_U1/Channel1<18>_MC.D2_PT_2/IN2 \))
			((I3) (\U1/Channel1 \(13)))
			((I4) (\NlwInverterSignal_U1/Channel1<18>_MC.D2_PT_2/IN4 \))
			((I5) (\U1/Channel1 \(14)))
			((I6) (\U1/Channel1 \(15)))
			((I7) (\U1/Channel1 \(16)))
			((I8) (\U1/Channel1 \(17)))
			((I9) (Vcc))
			((I10) (Vcc))
			((I11) (Vcc))
			((I12) (Vcc))
			((I13) (Vcc))
			((I14) (Vcc))
			((I15) (Vcc))
			((O) (\U1/Channel1<18>_MC.D2_PT_2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/Channel1<18>_MC.D2_966 \ 0 11268 (_entity .  X_OR3)
		(_port
			((I0) (\U1/Channel1<18>_MC.D2_PT_0 \))
			((I1) (\U1/Channel1<18>_MC.D2_PT_1 \))
			((I2) (\U1/Channel1<18>_MC.D2_PT_2 \))
			((O) (\U1/Channel1<18>_MC.D2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/Channel1<19> \ 0 11274 (_entity .  X_BUF)
		(_port
			((I) (\U1/Channel1<19>_MC.Q \))
			((O) (\U1/Channel1 \(19)))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/Channel1<19>_MC_tsimcreated_xor__967 \ 0 11278 (_entity .  X_XOR2)
		(_port
			((I0) (\U1/Channel1<19>_MC.D \))
			((I1) (\U1/Channel1<19>_MC.Q \))
			((O) (\U1/Channel1<19>_MC_tsimcreated_xor_ \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/Channel1<19>_MC.REG \ 0 11283 (_entity .  X_FF)
		(_port
			((I) (\U1/Channel1<19>_MC_tsimcreated_xor_ \))
			((CE) (Vcc))
			((CLK) (\Mclk_II/FCLK \))
			((SET) (Gnd))
			((RST) (PRLD))
			((O) (\U1/Channel1<19>_MC.Q \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/Channel1<19>_MC.D_968 \ 0 11291 (_entity .  X_XOR2)
		(_port
			((I0) (\U1/Channel1<19>_MC.D1 \))
			((I1) (\U1/Channel1<19>_MC.D2 \))
			((O) (\U1/Channel1<19>_MC.D \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/Channel1<19>_MC.D1_969 \ 0 11296 (_entity .  X_ZERO)
		(_port
			((O) (\U1/Channel1<19>_MC.D1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/Channel1<19>_MC.D2_PT_0_970 \ 0 11299 (_entity .  X_AND2)
		(_port
			((I0) (\NlwInverterSignal_U1/Channel1<19>_MC.D2_PT_0/IN0 \))
			((I1) (\U1/Channel1 \(19)))
			((O) (\U1/Channel1<19>_MC.D2_PT_0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/Channel1<19>_MC.D2_PT_1_971 \ 0 11304 (_entity .  X_AND16)
		(_port
			((I0) (N_PZ_948))
			((I1) (N_PZ_1082))
			((I2) (N_PZ_993))
			((I3) (\NlwInverterSignal_U1/Channel1<19>_MC.D2_PT_1/IN3 \))
			((I4) (\U1/U5/location_Maddsub__n0000__n0115 \(0)))
			((I5) (\NlwInverterSignal_U1/Channel1<19>_MC.D2_PT_1/IN5 \))
			((I6) (\NlwInverterSignal_U1/Channel1<19>_MC.D2_PT_1/IN6 \))
			((I7) (\NlwInverterSignal_U1/Channel1<19>_MC.D2_PT_1/IN7 \))
			((I8) (\NlwInverterSignal_U1/Channel1<19>_MC.D2_PT_1/IN8 \))
			((I9) (\NlwInverterSignal_U1/Channel1<19>_MC.D2_PT_1/IN9 \))
			((I10) (Vcc))
			((I11) (Vcc))
			((I12) (Vcc))
			((I13) (Vcc))
			((I14) (Vcc))
			((I15) (Vcc))
			((O) (\U1/Channel1<19>_MC.D2_PT_1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/Channel1<19>_MC.D2_PT_2_972 \ 0 11323 (_entity .  X_AND16)
		(_port
			((I0) (N_PZ_948))
			((I1) (N_PZ_1082))
			((I2) (\NlwInverterSignal_U1/Channel1<19>_MC.D2_PT_2/IN2 \))
			((I3) (\U1/Channel1 \(13)))
			((I4) (\NlwInverterSignal_U1/Channel1<19>_MC.D2_PT_2/IN4 \))
			((I5) (\U1/Channel1 \(14)))
			((I6) (\U1/Channel1 \(15)))
			((I7) (\U1/Channel1 \(16)))
			((I8) (\U1/Channel1 \(17)))
			((I9) (\U1/Channel1 \(18)))
			((I10) (Vcc))
			((I11) (Vcc))
			((I12) (Vcc))
			((I13) (Vcc))
			((I14) (Vcc))
			((I15) (Vcc))
			((O) (\U1/Channel1<19>_MC.D2_PT_2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/Channel1<19>_MC.D2_973 \ 0 11342 (_entity .  X_OR3)
		(_port
			((I0) (\U1/Channel1<19>_MC.D2_PT_0 \))
			((I1) (\U1/Channel1<19>_MC.D2_PT_1 \))
			((I2) (\U1/Channel1<19>_MC.D2_PT_2 \))
			((O) (\U1/Channel1<19>_MC.D2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/Channel1<20> \ 0 11348 (_entity .  X_BUF)
		(_port
			((I) (\U1/Channel1<20>_MC.Q \))
			((O) (\U1/Channel1 \(20)))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/Channel1<20>_MC_tsimcreated_xor__974 \ 0 11352 (_entity .  X_XOR2)
		(_port
			((I0) (\U1/Channel1<20>_MC.D \))
			((I1) (\U1/Channel1<20>_MC.Q \))
			((O) (\U1/Channel1<20>_MC_tsimcreated_xor_ \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/Channel1<20>_MC.REG \ 0 11357 (_entity .  X_FF)
		(_port
			((I) (\U1/Channel1<20>_MC_tsimcreated_xor_ \))
			((CE) (Vcc))
			((CLK) (\Mclk_II/FCLK \))
			((SET) (Gnd))
			((RST) (PRLD))
			((O) (\U1/Channel1<20>_MC.Q \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/Channel1<20>_MC.D_975 \ 0 11365 (_entity .  X_XOR2)
		(_port
			((I0) (\U1/Channel1<20>_MC.D1 \))
			((I1) (\U1/Channel1<20>_MC.D2 \))
			((O) (\U1/Channel1<20>_MC.D \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/Channel1<20>_MC.D1_976 \ 0 11370 (_entity .  X_ZERO)
		(_port
			((O) (\U1/Channel1<20>_MC.D1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/Channel1<20>_MC.D2_PT_0_977 \ 0 11373 (_entity .  X_AND2)
		(_port
			((I0) (\NlwInverterSignal_U1/Channel1<20>_MC.D2_PT_0/IN0 \))
			((I1) (\U1/Channel1 \(20)))
			((O) (\U1/Channel1<20>_MC.D2_PT_0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/Channel1<20>_MC.D2_PT_1_978 \ 0 11378 (_entity .  X_AND16)
		(_port
			((I0) (N_PZ_948))
			((I1) (N_PZ_1082))
			((I2) (N_PZ_993))
			((I3) (\NlwInverterSignal_U1/Channel1<20>_MC.D2_PT_1/IN3 \))
			((I4) (\U1/U5/location_Maddsub__n0000__n0115 \(0)))
			((I5) (\NlwInverterSignal_U1/Channel1<20>_MC.D2_PT_1/IN5 \))
			((I6) (\NlwInverterSignal_U1/Channel1<20>_MC.D2_PT_1/IN6 \))
			((I7) (\NlwInverterSignal_U1/Channel1<20>_MC.D2_PT_1/IN7 \))
			((I8) (\NlwInverterSignal_U1/Channel1<20>_MC.D2_PT_1/IN8 \))
			((I9) (\NlwInverterSignal_U1/Channel1<20>_MC.D2_PT_1/IN9 \))
			((I10) (\NlwInverterSignal_U1/Channel1<20>_MC.D2_PT_1/IN10 \))
			((I11) (Vcc))
			((I12) (Vcc))
			((I13) (Vcc))
			((I14) (Vcc))
			((I15) (Vcc))
			((O) (\U1/Channel1<20>_MC.D2_PT_1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/Channel1<20>_MC.D2_PT_2_979 \ 0 11397 (_entity .  X_AND16)
		(_port
			((I0) (N_PZ_948))
			((I1) (N_PZ_1082))
			((I2) (\NlwInverterSignal_U1/Channel1<20>_MC.D2_PT_2/IN2 \))
			((I3) (\U1/Channel1 \(13)))
			((I4) (\NlwInverterSignal_U1/Channel1<20>_MC.D2_PT_2/IN4 \))
			((I5) (\U1/Channel1 \(14)))
			((I6) (\U1/Channel1 \(15)))
			((I7) (\U1/Channel1 \(16)))
			((I8) (\U1/Channel1 \(17)))
			((I9) (\U1/Channel1 \(18)))
			((I10) (\U1/Channel1 \(19)))
			((I11) (Vcc))
			((I12) (Vcc))
			((I13) (Vcc))
			((I14) (Vcc))
			((I15) (Vcc))
			((O) (\U1/Channel1<20>_MC.D2_PT_2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/Channel1<20>_MC.D2_980 \ 0 11416 (_entity .  X_OR3)
		(_port
			((I0) (\U1/Channel1<20>_MC.D2_PT_0 \))
			((I1) (\U1/Channel1<20>_MC.D2_PT_1 \))
			((I2) (\U1/Channel1<20>_MC.D2_PT_2 \))
			((O) (\U1/Channel1<20>_MC.D2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U3/holdingreg<13> \ 0 11422 (_entity .  X_BUF)
		(_port
			((I) (\U1/U3/holdingreg<13>_MC.Q \))
			((O) (\U1/U3/holdingreg \(13)))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U3/holdingreg<13>_MC.REG \ 0 11426 (_entity .  X_FF)
		(_port
			((I) (\U1/U3/holdingreg<13>_MC.D \))
			((CE) (Vcc))
			((CLK) (\U1/U3/holdingreg<13>_MC.REG_tsimcreated_inv_Mclk_II/FCLK \))
			((SET) (Gnd))
			((RST) (PRLD))
			((O) (\U1/U3/holdingreg<13>_MC.Q \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U3/holdingreg<13>_MC.REG_tsimcreated_inv_Mclk_II/FCLK_981 \ 0 11434 (_entity .  X_INV)
		(_port
			((I) (\Mclk_II/FCLK \))
			((O) (\U1/U3/holdingreg<13>_MC.REG_tsimcreated_inv_Mclk_II/FCLK \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U3/holdingreg<13>_MC.D_982 \ 0 11438 (_entity .  X_XOR2)
		(_port
			((I0) (\U1/U3/holdingreg<13>_MC.D1 \))
			((I1) (\U1/U3/holdingreg<13>_MC.D2 \))
			((O) (\U1/U3/holdingreg<13>_MC.D \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U3/holdingreg<13>_MC.D1_983 \ 0 11443 (_entity .  X_ZERO)
		(_port
			((O) (\U1/U3/holdingreg<13>_MC.D1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U3/holdingreg<13>_MC.D2_PT_0_984 \ 0 11446 (_entity .  X_AND2)
		(_port
			((I0) (N_PZ_986))
			((I1) (\U1/Channel1 \(13)))
			((O) (\U1/U3/holdingreg<13>_MC.D2_PT_0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U3/holdingreg<13>_MC.D2_PT_1_985 \ 0 11451 (_entity .  X_AND3)
		(_port
			((I0) (\NlwInverterSignal_U1/U3/holdingreg<13>_MC.D2_PT_1/IN0 \))
			((I1) (\U1/U3/holdingreg \(13)))
			((I2) (\U1/U3/RDedge \))
			((O) (\U1/U3/holdingreg<13>_MC.D2_PT_1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U3/holdingreg<13>_MC.D2_PT_2_986 \ 0 11457 (_entity .  X_AND16)
		(_port
			((I0) (\WR_II/UIM \))
			((I1) (\NlwInverterSignal_U1/U3/holdingreg<13>_MC.D2_PT_2/IN1 \))
			((I2) (U2_ADDR_reg(1)))
			((I3) (U2_ADDR_reg(0)))
			((I4) (N_PZ_931))
			((I5) (U2_ADDR_reg(2)))
			((I6) (\NlwInverterSignal_U1/U3/holdingreg<13>_MC.D2_PT_2/IN6 \))
			((I7) (\NlwInverterSignal_U1/U3/holdingreg<13>_MC.D2_PT_2/IN7 \))
			((I8) (\NlwInverterSignal_U1/U3/holdingreg<13>_MC.D2_PT_2/IN8 \))
			((I9) (\U1/Channel0 \(13)))
			((I10) (Vcc))
			((I11) (Vcc))
			((I12) (Vcc))
			((I13) (Vcc))
			((I14) (Vcc))
			((I15) (Vcc))
			((O) (\U1/U3/holdingreg<13>_MC.D2_PT_2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U3/holdingreg<13>_MC.D2_987 \ 0 11476 (_entity .  X_OR3)
		(_port
			((I0) (\U1/U3/holdingreg<13>_MC.D2_PT_0 \))
			((I1) (\U1/U3/holdingreg<13>_MC.D2_PT_1 \))
			((I2) (\U1/U3/holdingreg<13>_MC.D2_PT_2 \))
			((O) (\U1/U3/holdingreg<13>_MC.D2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \outDATA<5>\\$WA4.UIM_988 \ 0 11482 (_entity .  X_BUF)
		(_port
			((I) (\outDATA<5>\\$WA4.UIM_MC.Q \))
			((O) (\outDATA<5>\\$WA4.UIM \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \outDATA<5>\\$WA4.UIM_MC.Q_989 \ 0 11486 (_entity .  X_BUF)
		(_port
			((I) (\outDATA<5>\\$WA4.UIM_MC.D \))
			((O) (\outDATA<5>\\$WA4.UIM_MC.Q \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \outDATA<5>\\$WA4.UIM_MC.D_990 \ 0 11490 (_entity .  X_XOR2)
		(_port
			((I0) (\outDATA<5>\\$WA4.UIM_MC.D1 \))
			((I1) (\outDATA<5>\\$WA4.UIM_MC.D2 \))
			((O) (\outDATA<5>\\$WA4.UIM_MC.D \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \outDATA<5>\\$WA4.UIM_MC.D1_991 \ 0 11495 (_entity .  X_ZERO)
		(_port
			((O) (\outDATA<5>\\$WA4.UIM_MC.D1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \outDATA<5>\\$WA4.UIM_MC.D2_PT_0_992 \ 0 11498 (_entity .  X_AND2)
		(_port
			((I0) (\U1/U4/Latch1r \(13)))
			((I1) (N_PZ_1003))
			((O) (\outDATA<5>\\$WA4.UIM_MC.D2_PT_0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \outDATA<5>\\$WA4.UIM_MC.D2_PT_1_993 \ 0 11503 (_entity .  X_AND8)
		(_port
			((I0) (\WR_II/UIM \))
			((I1) (\NlwInverterSignal_outDATA<5>\\$WA4.UIM_MC.D2_PT_1/IN1 \))
			((I2) (U2_ADDR_reg(1)))
			((I3) (U2_ADDR_reg(0)))
			((I4) (N_PZ_931))
			((I5) (\NlwInverterSignal_outDATA<5>\\$WA4.UIM_MC.D2_PT_1/IN5 \))
			((I6) (U2_ADDR_reg(3)))
			((I7) (\U1/U4/Latch0r \(13)))
			((O) (\outDATA<5>\\$WA4.UIM_MC.D2_PT_1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \outDATA<5>\\$WA4.UIM_MC.D2_PT_2_994 \ 0 11514 (_entity .  X_AND8)
		(_port
			((I0) (\WR_II/UIM \))
			((I1) (\NlwInverterSignal_outDATA<5>\\$WA4.UIM_MC.D2_PT_2/IN1 \))
			((I2) (U2_ADDR_reg(1)))
			((I3) (\NlwInverterSignal_outDATA<5>\\$WA4.UIM_MC.D2_PT_2/IN3 \))
			((I4) (N_PZ_931))
			((I5) (\NlwInverterSignal_outDATA<5>\\$WA4.UIM_MC.D2_PT_2/IN5 \))
			((I6) (U2_ADDR_reg(3)))
			((I7) (\U1/U4/Latch0r \(5)))
			((O) (\outDATA<5>\\$WA4.UIM_MC.D2_PT_2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \outDATA<5>\\$WA4.UIM_MC.D2_PT_3_995 \ 0 11525 (_entity .  X_AND8)
		(_port
			((I0) (\WR_II/UIM \))
			((I1) (\NlwInverterSignal_outDATA<5>\\$WA4.UIM_MC.D2_PT_3/IN1 \))
			((I2) (\NlwInverterSignal_outDATA<5>\\$WA4.UIM_MC.D2_PT_3/IN2 \))
			((I3) (\NlwInverterSignal_outDATA<5>\\$WA4.UIM_MC.D2_PT_3/IN3 \))
			((I4) (N_PZ_931))
			((I5) (U2_ADDR_reg(2)))
			((I6) (U2_ADDR_reg(3)))
			((I7) (\U1/U4/Latch1r \(5)))
			((O) (\outDATA<5>\\$WA4.UIM_MC.D2_PT_3 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \outDATA<5>\\$WA4.UIM_MC.D2_996 \ 0 11536 (_entity .  X_OR4)
		(_port
			((I0) (\outDATA<5>\\$WA4.UIM_MC.D2_PT_0 \))
			((I1) (\outDATA<5>\\$WA4.UIM_MC.D2_PT_1 \))
			((I2) (\outDATA<5>\\$WA4.UIM_MC.D2_PT_2 \))
			((I3) (\outDATA<5>\\$WA4.UIM_MC.D2_PT_3 \))
			((O) (\outDATA<5>\\$WA4.UIM_MC.D2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U4/Latch0r<13> \ 0 11543 (_entity .  X_BUF)
		(_port
			((I) (\U1/U4/Latch0r<13>_MC.Q \))
			((O) (\U1/U4/Latch0r \(13)))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U4/Latch0r<13>_MC.REG \ 0 11547 (_entity .  X_FF)
		(_port
			((I) (\U1/U4/Latch0r<13>_MC.D \))
			((CE) (Vcc))
			((CLK) (\U1/U4/Latch0r<13>_MC.REG_tsimcreated_inv_Mclk_II/FCLK \))
			((SET) (Gnd))
			((RST) (PRLD))
			((O) (\U1/U4/Latch0r<13>_MC.Q \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U4/Latch0r<13>_MC.REG_tsimcreated_inv_Mclk_II/FCLK_997 \ 0 11555 (_entity .  X_INV)
		(_port
			((I) (\Mclk_II/FCLK \))
			((O) (\U1/U4/Latch0r<13>_MC.REG_tsimcreated_inv_Mclk_II/FCLK \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U4/Latch0r<13>_MC.D_998 \ 0 11559 (_entity .  X_XOR2)
		(_port
			((I0) (\U1/U4/Latch0r<13>_MC.D1 \))
			((I1) (\U1/U4/Latch0r<13>_MC.D2 \))
			((O) (\U1/U4/Latch0r<13>_MC.D \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U4/Latch0r<13>_MC.D1_999 \ 0 11564 (_entity .  X_ZERO)
		(_port
			((O) (\U1/U4/Latch0r<13>_MC.D1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U4/Latch0r<13>_MC.D2_PT_0_1000 \ 0 11567 (_entity .  X_AND2)
		(_port
			((I0) (\U1/U4/Latch0r \(13)))
			((I1) (N_PZ_1059))
			((O) (\U1/U4/Latch0r<13>_MC.D2_PT_0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U4/Latch0r<13>_MC.D2_PT_1_1001 \ 0 11572 (_entity .  X_AND3)
		(_port
			((I0) (\NlwInverterSignal_U1/U4/Latch0r<13>_MC.D2_PT_1/IN0 \))
			((I1) (\U1/Channel0 \(13)))
			((I2) (\NlwInverterSignal_U1/U4/Latch0r<13>_MC.D2_PT_1/IN2 \))
			((O) (\U1/U4/Latch0r<13>_MC.D2_PT_1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U4/Latch0r<13>_MC.D2_1002 \ 0 11578 (_entity .  X_OR2)
		(_port
			((I0) (\U1/U4/Latch0r<13>_MC.D2_PT_0 \))
			((I1) (\U1/U4/Latch0r<13>_MC.D2_PT_1 \))
			((O) (\U1/U4/Latch0r<13>_MC.D2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation N_PZ_1059_1003 0 11583 (_entity .  X_BUF)
		(_port
			((I) (\N_PZ_1059_MC.Q \))
			((O) (N_PZ_1059))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \N_PZ_1059_MC.Q_1004 \ 0 11587 (_entity .  X_BUF)
		(_port
			((I) (\N_PZ_1059_MC.D \))
			((O) (\N_PZ_1059_MC.Q \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \N_PZ_1059_MC.D_1005 \ 0 11591 (_entity .  X_XOR2)
		(_port
			((I0) (\N_PZ_1059_MC.D1 \))
			((I1) (\N_PZ_1059_MC.D2 \))
			((O) (\N_PZ_1059_MC.D \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \N_PZ_1059_MC.D1_1006 \ 0 11596 (_entity .  X_ZERO)
		(_port
			((O) (\N_PZ_1059_MC.D1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \N_PZ_1059_MC.D2_PT_0_1007 \ 0 11599 (_entity .  X_AND2)
		(_port
			((I0) (\NlwInverterSignal_N_PZ_1059_MC.D2_PT_0/IN0 \))
			((I1) (NET2501))
			((O) (\N_PZ_1059_MC.D2_PT_0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \N_PZ_1059_MC.D2_PT_1_1008 \ 0 11604 (_entity .  X_AND3)
		(_port
			((I0) (\NlwInverterSignal_N_PZ_1059_MC.D2_PT_1/IN0 \))
			((I1) (\U1/U4/LatchEdge0r \))
			((I2) (\U1/U4/InEdge0r \))
			((O) (\N_PZ_1059_MC.D2_PT_1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \N_PZ_1059_MC.D2_PT_2_1009 \ 0 11610 (_entity .  X_AND3)
		(_port
			((I0) (\NlwInverterSignal_N_PZ_1059_MC.D2_PT_2/IN0 \))
			((I1) (\NlwInverterSignal_N_PZ_1059_MC.D2_PT_2/IN1 \))
			((I2) (\outDATA<6>\\$WA1.UIM \))
			((O) (\N_PZ_1059_MC.D2_PT_2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \N_PZ_1059_MC.D2_PT_3_1010 \ 0 11616 (_entity .  X_AND3)
		(_port
			((I0) (\NlwInverterSignal_N_PZ_1059_MC.D2_PT_3/IN0 \))
			((I1) (\NlwInverterSignal_N_PZ_1059_MC.D2_PT_3/IN1 \))
			((I2) (\NlwInverterSignal_N_PZ_1059_MC.D2_PT_3/IN2 \))
			((O) (\N_PZ_1059_MC.D2_PT_3 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \N_PZ_1059_MC.D2_PT_4_1011 \ 0 11622 (_entity .  X_AND7)
		(_port
			((I0) (\NlwInverterSignal_N_PZ_1059_MC.D2_PT_4/IN0 \))
			((I1) (\RD_II/UIM \))
			((I2) (U2_ADDR_reg(1)))
			((I3) (N_PZ_931))
			((I4) (\NlwInverterSignal_N_PZ_1059_MC.D2_PT_4/IN4 \))
			((I5) (\NlwInverterSignal_N_PZ_1059_MC.D2_PT_4/IN5 \))
			((I6) (\NlwInverterSignal_N_PZ_1059_MC.D2_PT_4/IN6 \))
			((O) (\N_PZ_1059_MC.D2_PT_4 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \N_PZ_1059_MC.D2_1012 \ 0 11632 (_entity .  X_OR5)
		(_port
			((I0) (\N_PZ_1059_MC.D2_PT_0 \))
			((I1) (\N_PZ_1059_MC.D2_PT_1 \))
			((I2) (\N_PZ_1059_MC.D2_PT_2 \))
			((I3) (\N_PZ_1059_MC.D2_PT_3 \))
			((I4) (\N_PZ_1059_MC.D2_PT_4 \))
			((O) (\N_PZ_1059_MC.D2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation NET2501_1013 0 11640 (_entity .  X_BUF)
		(_port
			((I) (\NET2501_MC.Q \))
			((O) (NET2501))
		)
		(_strength strong0 strong1)
	)
	(_instantiation NET2501_MC_tsimcreated_xor__1014 0 11644 (_entity .  X_XOR2)
		(_port
			((I0) (\NET2501_MC.D \))
			((I1) (\NET2501_MC.Q \))
			((O) (NET2501_MC_tsimcreated_xor_))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NET2501_MC.REG \ 0 11649 (_entity .  X_FF)
		(_port
			((I) (NET2501_MC_tsimcreated_xor_))
			((CE) (Vcc))
			((CLK) (\NET2501_MC.REG_tsimcreated_inv_Mclk_II/FCLK \))
			((SET) (Gnd))
			((RST) (PRLD))
			((O) (\NET2501_MC.Q \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NET2501_MC.REG_tsimcreated_inv_Mclk_II/FCLK_1015 \ 0 11657 (_entity .  X_INV)
		(_port
			((I) (\Mclk_II/FCLK \))
			((O) (\NET2501_MC.REG_tsimcreated_inv_Mclk_II/FCLK \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NET2501_MC.D_1016 \ 0 11661 (_entity .  X_XOR2)
		(_port
			((I0) (\NET2501_MC.D1 \))
			((I1) (\NET2501_MC.D2 \))
			((O) (\NET2501_MC.D \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NET2501_MC.D1_1017 \ 0 11666 (_entity .  X_ZERO)
		(_port
			((O) (\NET2501_MC.D1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NET2501_MC.D2_PT_0_1018 \ 0 11669 (_entity .  X_AND2)
		(_port
			((I0) (\NlwInverterSignal_NET2501_MC.D2_PT_0/IN0 \))
			((I1) (\NlwInverterSignal_NET2501_MC.D2_PT_0/IN1 \))
			((O) (\NET2501_MC.D2_PT_0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NET2501_MC.D2_PT_1_1019 \ 0 11674 (_entity .  X_AND16)
		(_port
			((I0) (\NlwInverterSignal_NET2501_MC.D2_PT_1/IN0 \))
			((I1) (\RD_II/UIM \))
			((I2) (U2_ADDR_reg(1)))
			((I3) (\NlwInverterSignal_NET2501_MC.D2_PT_1/IN3 \))
			((I4) (N_PZ_931))
			((I5) (\NlwInverterSignal_NET2501_MC.D2_PT_1/IN5 \))
			((I6) (\NlwInverterSignal_NET2501_MC.D2_PT_1/IN6 \))
			((I7) (\NlwInverterSignal_NET2501_MC.D2_PT_1/IN7 \))
			((I8) (\AD<5>_II/UIM \))
			((I9) (\NlwInverterSignal_NET2501_MC.D2_PT_1/IN9 \))
			((I10) (Vcc))
			((I11) (Vcc))
			((I12) (Vcc))
			((I13) (Vcc))
			((I14) (Vcc))
			((I15) (Vcc))
			((O) (\NET2501_MC.D2_PT_1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NET2501_MC.D2_PT_2_1020 \ 0 11693 (_entity .  X_AND16)
		(_port
			((I0) (\NlwInverterSignal_NET2501_MC.D2_PT_2/IN0 \))
			((I1) (\RD_II/UIM \))
			((I2) (U2_ADDR_reg(1)))
			((I3) (\NlwInverterSignal_NET2501_MC.D2_PT_2/IN3 \))
			((I4) (N_PZ_931))
			((I5) (\NlwInverterSignal_NET2501_MC.D2_PT_2/IN5 \))
			((I6) (\NlwInverterSignal_NET2501_MC.D2_PT_2/IN6 \))
			((I7) (\NlwInverterSignal_NET2501_MC.D2_PT_2/IN7 \))
			((I8) (\NlwInverterSignal_NET2501_MC.D2_PT_2/IN8 \))
			((I9) (NET2501))
			((I10) (Vcc))
			((I11) (Vcc))
			((I12) (Vcc))
			((I13) (Vcc))
			((I14) (Vcc))
			((I15) (Vcc))
			((O) (\NET2501_MC.D2_PT_2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NET2501_MC.D2_1021 \ 0 11712 (_entity .  X_OR3)
		(_port
			((I0) (\NET2501_MC.D2_PT_0 \))
			((I1) (\NET2501_MC.D2_PT_1 \))
			((I2) (\NET2501_MC.D2_PT_2 \))
			((O) (\NET2501_MC.D2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U4/LatchEdge0r_1022 \ 0 11718 (_entity .  X_BUF)
		(_port
			((I) (\U1/U4/LatchEdge0r_MC.Q \))
			((O) (\U1/U4/LatchEdge0r \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U4/LatchEdge0r_MC_tsimcreated_xor__1023 \ 0 11722 (_entity .  X_XOR2)
		(_port
			((I0) (\U1/U4/LatchEdge0r_MC.D \))
			((I1) (\U1/U4/LatchEdge0r_MC.Q \))
			((O) (\U1/U4/LatchEdge0r_MC_tsimcreated_xor_ \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U4/LatchEdge0r_MC.REG \ 0 11727 (_entity .  X_FF)
		(_port
			((I) (\U1/U4/LatchEdge0r_MC_tsimcreated_xor_ \))
			((CE) (Vcc))
			((CLK) (\U1/U4/LatchEdge0r_MC.REG_tsimcreated_inv_Mclk_II/FCLK \))
			((SET) (Gnd))
			((RST) (PRLD))
			((O) (\U1/U4/LatchEdge0r_MC.Q \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U4/LatchEdge0r_MC.REG_tsimcreated_inv_Mclk_II/FCLK_1024 \ 0 11735 (_entity .  X_INV)
		(_port
			((I) (\Mclk_II/FCLK \))
			((O) (\U1/U4/LatchEdge0r_MC.REG_tsimcreated_inv_Mclk_II/FCLK \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U4/LatchEdge0r_MC.D_1025 \ 0 11739 (_entity .  X_XOR2)
		(_port
			((I0) (\U1/U4/LatchEdge0r_MC.D1 \))
			((I1) (\U1/U4/LatchEdge0r_MC.D2 \))
			((O) (\U1/U4/LatchEdge0r_MC.D \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U4/LatchEdge0r_MC.D1_1026 \ 0 11744 (_entity .  X_ZERO)
		(_port
			((O) (\U1/U4/LatchEdge0r_MC.D1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U4/LatchEdge0r_MC.D2_PT_0_1027 \ 0 11747 (_entity .  X_AND2)
		(_port
			((I0) (\Reset_II/UIM \))
			((I1) (\U1/U4/LatchEdge0r \))
			((O) (\U1/U4/LatchEdge0r_MC.D2_PT_0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U4/LatchEdge0r_MC.D2_PT_1_1028 \ 0 11752 (_entity .  X_AND16)
		(_port
			((I0) (\NlwInverterSignal_U1/U4/LatchEdge0r_MC.D2_PT_1/IN0 \))
			((I1) (\RD_II/UIM \))
			((I2) (U2_ADDR_reg(1)))
			((I3) (U2_ADDR_reg(0)))
			((I4) (N_PZ_931))
			((I5) (\NlwInverterSignal_U1/U4/LatchEdge0r_MC.D2_PT_1/IN5 \))
			((I6) (\NlwInverterSignal_U1/U4/LatchEdge0r_MC.D2_PT_1/IN6 \))
			((I7) (\NlwInverterSignal_U1/U4/LatchEdge0r_MC.D2_PT_1/IN7 \))
			((I8) (\U1/U4/LatchEdge0r \))
			((I9) (Vcc))
			((I10) (Vcc))
			((I11) (Vcc))
			((I12) (Vcc))
			((I13) (Vcc))
			((I14) (Vcc))
			((I15) (Vcc))
			((O) (\U1/U4/LatchEdge0r_MC.D2_PT_1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U4/LatchEdge0r_MC.D2_PT_2_1029 \ 0 11771 (_entity .  X_AND16)
		(_port
			((I0) (\NlwInverterSignal_U1/U4/LatchEdge0r_MC.D2_PT_2/IN0 \))
			((I1) (\RD_II/UIM \))
			((I2) (U2_ADDR_reg(1)))
			((I3) (U2_ADDR_reg(0)))
			((I4) (N_PZ_931))
			((I5) (\NlwInverterSignal_U1/U4/LatchEdge0r_MC.D2_PT_2/IN5 \))
			((I6) (\NlwInverterSignal_U1/U4/LatchEdge0r_MC.D2_PT_2/IN6 \))
			((I7) (\NlwInverterSignal_U1/U4/LatchEdge0r_MC.D2_PT_2/IN7 \))
			((I8) (\AD<2>_II/UIM \))
			((I9) (\NlwInverterSignal_U1/U4/LatchEdge0r_MC.D2_PT_2/IN9 \))
			((I10) (Vcc))
			((I11) (Vcc))
			((I12) (Vcc))
			((I13) (Vcc))
			((I14) (Vcc))
			((I15) (Vcc))
			((O) (\U1/U4/LatchEdge0r_MC.D2_PT_2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U4/LatchEdge0r_MC.D2_1030 \ 0 11790 (_entity .  X_OR3)
		(_port
			((I0) (\U1/U4/LatchEdge0r_MC.D2_PT_0 \))
			((I1) (\U1/U4/LatchEdge0r_MC.D2_PT_1 \))
			((I2) (\U1/U4/LatchEdge0r_MC.D2_PT_2 \))
			((O) (\U1/U4/LatchEdge0r_MC.D2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \outDATA<6>\\$WA1.UIM_1031 \ 0 11796 (_entity .  X_BUF)
		(_port
			((I) (\outDATA<6>\\$WA1.UIM_MC.Q \))
			((O) (\outDATA<6>\\$WA1.UIM \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \outDATA<6>\\$WA1.UIM_MC.Q_1032 \ 0 11800 (_entity .  X_BUF)
		(_port
			((I) (\outDATA<6>\\$WA1.UIM_MC.D \))
			((O) (\outDATA<6>\\$WA1.UIM_MC.Q \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \outDATA<6>\\$WA1.UIM_MC.D_1033 \ 0 11804 (_entity .  X_XOR2)
		(_port
			((I0) (\outDATA<6>\\$WA1.UIM_MC.D1 \))
			((I1) (\outDATA<6>\\$WA1.UIM_MC.D2 \))
			((O) (\outDATA<6>\\$WA1.UIM_MC.D \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \outDATA<6>\\$WA1.UIM_MC.D1_1034 \ 0 11809 (_entity .  X_AND2)
		(_port
			((I0) (\GP_Motor0_0_II/UIM \))
			((I1) (\GP_Motor0_0_II/UIM \))
			((O) (\outDATA<6>\\$WA1.UIM_MC.D1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \outDATA<6>\\$WA1.UIM_MC.D2_1035 \ 0 11814 (_entity .  X_ZERO)
		(_port
			((O) (\outDATA<6>\\$WA1.UIM_MC.D2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U4/Latch0r<5> \ 0 11817 (_entity .  X_BUF)
		(_port
			((I) (\U1/U4/Latch0r<5>_MC.Q \))
			((O) (\U1/U4/Latch0r \(5)))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U4/Latch0r<5>_MC.REG \ 0 11821 (_entity .  X_FF)
		(_port
			((I) (\U1/U4/Latch0r<5>_MC.D \))
			((CE) (Vcc))
			((CLK) (\U1/U4/Latch0r<5>_MC.REG_tsimcreated_inv_Mclk_II/FCLK \))
			((SET) (Gnd))
			((RST) (PRLD))
			((O) (\U1/U4/Latch0r<5>_MC.Q \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U4/Latch0r<5>_MC.REG_tsimcreated_inv_Mclk_II/FCLK_1036 \ 0 11829 (_entity .  X_INV)
		(_port
			((I) (\Mclk_II/FCLK \))
			((O) (\U1/U4/Latch0r<5>_MC.REG_tsimcreated_inv_Mclk_II/FCLK \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U4/Latch0r<5>_MC.D_1037 \ 0 11833 (_entity .  X_XOR2)
		(_port
			((I0) (\U1/U4/Latch0r<5>_MC.D1 \))
			((I1) (\U1/U4/Latch0r<5>_MC.D2 \))
			((O) (\U1/U4/Latch0r<5>_MC.D \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U4/Latch0r<5>_MC.D1_1038 \ 0 11838 (_entity .  X_ZERO)
		(_port
			((O) (\U1/U4/Latch0r<5>_MC.D1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U4/Latch0r<5>_MC.D2_PT_0_1039 \ 0 11841 (_entity .  X_AND2)
		(_port
			((I0) (\U1/U4/Latch0r \(5)))
			((I1) (N_PZ_1059))
			((O) (\U1/U4/Latch0r<5>_MC.D2_PT_0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U4/Latch0r<5>_MC.D2_PT_1_1040 \ 0 11846 (_entity .  X_AND3)
		(_port
			((I0) (\NlwInverterSignal_U1/U4/Latch0r<5>_MC.D2_PT_1/IN0 \))
			((I1) (\U1/Channel0 \(5)))
			((I2) (\NlwInverterSignal_U1/U4/Latch0r<5>_MC.D2_PT_1/IN2 \))
			((O) (\U1/U4/Latch0r<5>_MC.D2_PT_1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U4/Latch0r<5>_MC.D2_1041 \ 0 11852 (_entity .  X_OR2)
		(_port
			((I0) (\U1/U4/Latch0r<5>_MC.D2_PT_0 \))
			((I1) (\U1/U4/Latch0r<5>_MC.D2_PT_1 \))
			((O) (\U1/U4/Latch0r<5>_MC.D2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U4/Latch1r<5> \ 0 11857 (_entity .  X_BUF)
		(_port
			((I) (\U1/U4/Latch1r<5>_MC.Q \))
			((O) (\U1/U4/Latch1r \(5)))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U4/Latch1r<5>_MC.REG \ 0 11861 (_entity .  X_FF)
		(_port
			((I) (\U1/U4/Latch1r<5>_MC.D \))
			((CE) (Vcc))
			((CLK) (\U1/U4/Latch1r<5>_MC.REG_tsimcreated_inv_Mclk_II/FCLK \))
			((SET) (Gnd))
			((RST) (PRLD))
			((O) (\U1/U4/Latch1r<5>_MC.Q \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U4/Latch1r<5>_MC.REG_tsimcreated_inv_Mclk_II/FCLK_1042 \ 0 11869 (_entity .  X_INV)
		(_port
			((I) (\Mclk_II/FCLK \))
			((O) (\U1/U4/Latch1r<5>_MC.REG_tsimcreated_inv_Mclk_II/FCLK \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U4/Latch1r<5>_MC.D_1043 \ 0 11873 (_entity .  X_XOR2)
		(_port
			((I0) (\U1/U4/Latch1r<5>_MC.D1 \))
			((I1) (\U1/U4/Latch1r<5>_MC.D2 \))
			((O) (\U1/U4/Latch1r<5>_MC.D \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U4/Latch1r<5>_MC.D1_1044 \ 0 11878 (_entity .  X_ZERO)
		(_port
			((O) (\U1/U4/Latch1r<5>_MC.D1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U4/Latch1r<5>_MC.D2_PT_0_1045 \ 0 11881 (_entity .  X_AND2)
		(_port
			((I0) (\NlwInverterSignal_U1/U4/Latch1r<5>_MC.D2_PT_0/IN0 \))
			((I1) (\U1/Channel1 \(5)))
			((O) (\U1/U4/Latch1r<5>_MC.D2_PT_0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U4/Latch1r<5>_MC.D2_PT_1_1046 \ 0 11886 (_entity .  X_AND8)
		(_port
			((I0) (\NlwInverterSignal_U1/U4/Latch1r<5>_MC.D2_PT_1/IN0 \))
			((I1) (\RD_II/UIM \))
			((I2) (U2_ADDR_reg(1)))
			((I3) (N_PZ_931))
			((I4) (\NlwInverterSignal_U1/U4/Latch1r<5>_MC.D2_PT_1/IN4 \))
			((I5) (\NlwInverterSignal_U1/U4/Latch1r<5>_MC.D2_PT_1/IN5 \))
			((I6) (\NlwInverterSignal_U1/U4/Latch1r<5>_MC.D2_PT_1/IN6 \))
			((I7) (\U1/U4/Latch1r \(5)))
			((O) (\U1/U4/Latch1r<5>_MC.D2_PT_1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U4/Latch1r<5>_MC.D2_1047 \ 0 11897 (_entity .  X_OR2)
		(_port
			((I0) (\U1/U4/Latch1r<5>_MC.D2_PT_0 \))
			((I1) (\U1/U4/Latch1r<5>_MC.D2_PT_1 \))
			((O) (\U1/U4/Latch1r<5>_MC.D2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U4/Latch1r<13> \ 0 11902 (_entity .  X_BUF)
		(_port
			((I) (\U1/U4/Latch1r<13>_MC.Q \))
			((O) (\U1/U4/Latch1r \(13)))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U4/Latch1r<13>_MC.REG \ 0 11906 (_entity .  X_FF)
		(_port
			((I) (\U1/U4/Latch1r<13>_MC.D \))
			((CE) (Vcc))
			((CLK) (\U1/U4/Latch1r<13>_MC.REG_tsimcreated_inv_Mclk_II/FCLK \))
			((SET) (Gnd))
			((RST) (PRLD))
			((O) (\U1/U4/Latch1r<13>_MC.Q \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U4/Latch1r<13>_MC.REG_tsimcreated_inv_Mclk_II/FCLK_1048 \ 0 11914 (_entity .  X_INV)
		(_port
			((I) (\Mclk_II/FCLK \))
			((O) (\U1/U4/Latch1r<13>_MC.REG_tsimcreated_inv_Mclk_II/FCLK \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U4/Latch1r<13>_MC.D_1049 \ 0 11918 (_entity .  X_XOR2)
		(_port
			((I0) (\U1/U4/Latch1r<13>_MC.D1 \))
			((I1) (\U1/U4/Latch1r<13>_MC.D2 \))
			((O) (\U1/U4/Latch1r<13>_MC.D \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U4/Latch1r<13>_MC.D1_1050 \ 0 11923 (_entity .  X_ZERO)
		(_port
			((O) (\U1/U4/Latch1r<13>_MC.D1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U4/Latch1r<13>_MC.D2_PT_0_1051 \ 0 11926 (_entity .  X_AND2)
		(_port
			((I0) (\NlwInverterSignal_U1/U4/Latch1r<13>_MC.D2_PT_0/IN0 \))
			((I1) (\U1/Channel1 \(13)))
			((O) (\U1/U4/Latch1r<13>_MC.D2_PT_0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U4/Latch1r<13>_MC.D2_PT_1_1052 \ 0 11931 (_entity .  X_AND8)
		(_port
			((I0) (\NlwInverterSignal_U1/U4/Latch1r<13>_MC.D2_PT_1/IN0 \))
			((I1) (\RD_II/UIM \))
			((I2) (U2_ADDR_reg(1)))
			((I3) (N_PZ_931))
			((I4) (\NlwInverterSignal_U1/U4/Latch1r<13>_MC.D2_PT_1/IN4 \))
			((I5) (\NlwInverterSignal_U1/U4/Latch1r<13>_MC.D2_PT_1/IN5 \))
			((I6) (\NlwInverterSignal_U1/U4/Latch1r<13>_MC.D2_PT_1/IN6 \))
			((I7) (\U1/U4/Latch1r \(13)))
			((O) (\U1/U4/Latch1r<13>_MC.D2_PT_1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U4/Latch1r<13>_MC.D2_1053 \ 0 11942 (_entity .  X_OR2)
		(_port
			((I0) (\U1/U4/Latch1r<13>_MC.D2_PT_0 \))
			((I1) (\U1/U4/Latch1r<13>_MC.D2_PT_1 \))
			((O) (\U1/U4/Latch1r<13>_MC.D2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation N_PZ_1003_1054 0 11947 (_entity .  X_BUF)
		(_port
			((I) (\N_PZ_1003_MC.Q \))
			((O) (N_PZ_1003))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \N_PZ_1003_MC.Q_1055 \ 0 11951 (_entity .  X_BUF)
		(_port
			((I) (\N_PZ_1003_MC.D \))
			((O) (\N_PZ_1003_MC.Q \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \N_PZ_1003_MC.D_1056 \ 0 11955 (_entity .  X_XOR2)
		(_port
			((I0) (\N_PZ_1003_MC.D1 \))
			((I1) (\N_PZ_1003_MC.D2 \))
			((O) (\N_PZ_1003_MC.D \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \N_PZ_1003_MC.D1_1057 \ 0 11960 (_entity .  X_ZERO)
		(_port
			((O) (\N_PZ_1003_MC.D1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \N_PZ_1003_MC.D2_PT_0_1058 \ 0 11963 (_entity .  X_AND2)
		(_port
			((I0) (\NlwInverterSignal_N_PZ_1003_MC.D2_PT_0/IN0 \))
			((I1) (\NlwInverterSignal_N_PZ_1003_MC.D2_PT_0/IN1 \))
			((O) (\N_PZ_1003_MC.D2_PT_0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \N_PZ_1003_MC.D2_PT_1_1059 \ 0 11968 (_entity .  X_AND2)
		(_port
			((I0) (U2_ADDR_reg(0)))
			((I1) (U2_ADDR_reg(2)))
			((O) (\N_PZ_1003_MC.D2_PT_1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \N_PZ_1003_MC.D2_1060 \ 0 11973 (_entity .  X_OR2)
		(_port
			((I0) (\N_PZ_1003_MC.D2_PT_0 \))
			((I1) (\N_PZ_1003_MC.D2_PT_1 \))
			((O) (\N_PZ_1003_MC.D2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation N_PZ_1060_1061 0 11978 (_entity .  X_BUF)
		(_port
			((I) (\N_PZ_1060_MC.Q \))
			((O) (N_PZ_1060))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \N_PZ_1060_MC.Q_1062 \ 0 11982 (_entity .  X_BUF)
		(_port
			((I) (\N_PZ_1060_MC.D \))
			((O) (\N_PZ_1060_MC.Q \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \N_PZ_1060_MC.D_1063 \ 0 11986 (_entity .  X_XOR2)
		(_port
			((I0) (\N_PZ_1060_MC.D1 \))
			((I1) (\N_PZ_1060_MC.D2 \))
			((O) (\N_PZ_1060_MC.D \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \N_PZ_1060_MC.D1_1064 \ 0 11991 (_entity .  X_ZERO)
		(_port
			((O) (\N_PZ_1060_MC.D1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \N_PZ_1060_MC.D2_PT_0_1065 \ 0 11994 (_entity .  X_AND5)
		(_port
			((I0) (U2_ADDR_reg(1)))
			((I1) (N_PZ_931))
			((I2) (\NlwInverterSignal_N_PZ_1060_MC.D2_PT_0/IN2 \))
			((I3) (U2_ADDR_reg(3)))
			((I4) (U2_Enable_AD))
			((O) (\N_PZ_1060_MC.D2_PT_0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \N_PZ_1060_MC.D2_PT_1_1066 \ 0 12002 (_entity .  X_AND5)
		(_port
			((I0) (\NlwInverterSignal_N_PZ_1060_MC.D2_PT_1/IN0 \))
			((I1) (N_PZ_931))
			((I2) (U2_ADDR_reg(2)))
			((I3) (U2_ADDR_reg(3)))
			((I4) (U2_Enable_AD))
			((O) (\N_PZ_1060_MC.D2_PT_1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \N_PZ_1060_MC.D2_1067 \ 0 12010 (_entity .  X_OR2)
		(_port
			((I0) (\N_PZ_1060_MC.D2_PT_0 \))
			((I1) (\N_PZ_1060_MC.D2_PT_1 \))
			((O) (\N_PZ_1060_MC.D2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \AD<6>_MC.Q_1068 \ 0 12015 (_entity .  X_BUF)
		(_port
			((I) (\AD<6>_MC.Q_tsimrenamed_net_ \))
			((O) (\AD<6>_MC.Q \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \AD<6>_MC.OE_1069 \ 0 12019 (_entity .  X_BUF)
		(_port
			((I) (\AD<6>_MC.BUFOE.OUT \))
			((O) (\AD<6>_MC.OE \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \AD<6>_MC.BUFOE.OUT_1070 \ 0 12023 (_entity .  X_BUF)
		(_port
			((I) (\FOOBAR3__ctinst/7 \))
			((O) (\AD<6>_MC.BUFOE.OUT \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \AD<6>_MC.Q_tsimrenamed_net__1071 \ 0 12027 (_entity .  X_BUF)
		(_port
			((I) (\AD<6>_MC.D \))
			((O) (\AD<6>_MC.Q_tsimrenamed_net_ \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \AD<6>_MC.D_1072 \ 0 12031 (_entity .  X_XOR2)
		(_port
			((I0) (\NlwInverterSignal_AD<6>_MC.D/IN0 \))
			((I1) (\AD<6>_MC.D2 \))
			((O) (\AD<6>_MC.D \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \AD<6>_MC.D1_1073 \ 0 12036 (_entity .  X_ZERO)
		(_port
			((O) (\AD<6>_MC.D1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \AD<6>_MC.D2_PT_0_1074 \ 0 12039 (_entity .  X_AND2)
		(_port
			((I0) (N_PZ_964))
			((I1) (\NlwInverterSignal_AD<6>_MC.D2_PT_0/IN1 \))
			((O) (\AD<6>_MC.D2_PT_0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \AD<6>_MC.D2_PT_1_1075 \ 0 12044 (_entity .  X_AND2)
		(_port
			((I0) (N_PZ_1060))
			((I1) (\NlwInverterSignal_AD<6>_MC.D2_PT_1/IN1 \))
			((O) (\AD<6>_MC.D2_PT_1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \AD<6>_MC.D2_PT_2_1076 \ 0 12049 (_entity .  X_AND8)
		(_port
			((I0) (\WR_II/UIM \))
			((I1) (\NlwInverterSignal_AD<6>_MC.D2_PT_2/IN1 \))
			((I2) (U2_ADDR_reg(1)))
			((I3) (U2_ADDR_reg(0)))
			((I4) (N_PZ_931))
			((I5) (U2_ADDR_reg(2)))
			((I6) (U2_ADDR_reg(3)))
			((I7) (\NlwInverterSignal_AD<6>_MC.D2_PT_2/IN7 \))
			((O) (\AD<6>_MC.D2_PT_2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \AD<6>_MC.D2_PT_3_1077 \ 0 12060 (_entity .  X_AND8)
		(_port
			((I0) (\WR_II/UIM \))
			((I1) (\NlwInverterSignal_AD<6>_MC.D2_PT_3/IN1 \))
			((I2) (U2_ADDR_reg(1)))
			((I3) (U2_ADDR_reg(0)))
			((I4) (N_PZ_931))
			((I5) (\NlwInverterSignal_AD<6>_MC.D2_PT_3/IN5 \))
			((I6) (\NlwInverterSignal_AD<6>_MC.D2_PT_3/IN6 \))
			((I7) (\NlwInverterSignal_AD<6>_MC.D2_PT_3/IN7 \))
			((O) (\AD<6>_MC.D2_PT_3 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \AD<6>_MC.D2_PT_4_1078 \ 0 12071 (_entity .  X_AND8)
		(_port
			((I0) (\WR_II/UIM \))
			((I1) (\NlwInverterSignal_AD<6>_MC.D2_PT_4/IN1 \))
			((I2) (U2_ADDR_reg(1)))
			((I3) (\NlwInverterSignal_AD<6>_MC.D2_PT_4/IN3 \))
			((I4) (N_PZ_931))
			((I5) (U2_ADDR_reg(2)))
			((I6) (U2_ADDR_reg(3)))
			((I7) (\NlwInverterSignal_AD<6>_MC.D2_PT_4/IN7 \))
			((O) (\AD<6>_MC.D2_PT_4 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \AD<6>_MC.D2_PT_5_1079 \ 0 12082 (_entity .  X_AND8)
		(_port
			((I0) (\WR_II/UIM \))
			((I1) (\NlwInverterSignal_AD<6>_MC.D2_PT_5/IN1 \))
			((I2) (\NlwInverterSignal_AD<6>_MC.D2_PT_5/IN2 \))
			((I3) (\NlwInverterSignal_AD<6>_MC.D2_PT_5/IN3 \))
			((I4) (N_PZ_931))
			((I5) (\NlwInverterSignal_AD<6>_MC.D2_PT_5/IN5 \))
			((I6) (\NlwInverterSignal_AD<6>_MC.D2_PT_5/IN6 \))
			((I7) (\NlwInverterSignal_AD<6>_MC.D2_PT_5/IN7 \))
			((O) (\AD<6>_MC.D2_PT_5 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \AD<6>_MC.D2_1080 \ 0 12093 (_entity .  X_OR6)
		(_port
			((I0) (\AD<6>_MC.D2_PT_0 \))
			((I1) (\AD<6>_MC.D2_PT_1 \))
			((I2) (\AD<6>_MC.D2_PT_2 \))
			((I3) (\AD<6>_MC.D2_PT_3 \))
			((I4) (\AD<6>_MC.D2_PT_4 \))
			((I5) (\AD<6>_MC.D2_PT_5 \))
			((O) (\AD<6>_MC.D2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \outDATA<6>\\$WA0.UIM_1081 \ 0 12102 (_entity .  X_BUF)
		(_port
			((I) (\outDATA<6>\\$WA0.UIM_MC.Q \))
			((O) (\outDATA<6>\\$WA0.UIM \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \outDATA<6>\\$WA0.UIM_MC.Q_1082 \ 0 12106 (_entity .  X_BUF)
		(_port
			((I) (\outDATA<6>\\$WA0.UIM_MC.D \))
			((O) (\outDATA<6>\\$WA0.UIM_MC.Q \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \outDATA<6>\\$WA0.UIM_MC.D_1083 \ 0 12110 (_entity .  X_XOR2)
		(_port
			((I0) (\outDATA<6>\\$WA0.UIM_MC.D1 \))
			((I1) (\outDATA<6>\\$WA0.UIM_MC.D2 \))
			((O) (\outDATA<6>\\$WA0.UIM_MC.D \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \outDATA<6>\\$WA0.UIM_MC.D1_1084 \ 0 12115 (_entity .  X_ZERO)
		(_port
			((O) (\outDATA<6>\\$WA0.UIM_MC.D1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \outDATA<6>\\$WA0.UIM_MC.D2_1085 \ 0 12118 (_entity .  X_ZERO)
		(_port
			((O) (\outDATA<6>\\$WA0.UIM_MC.D2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \outDATA<6>\\$WA2.UIM_1086 \ 0 12121 (_entity .  X_BUF)
		(_port
			((I) (\outDATA<6>\\$WA2.UIM_MC.Q \))
			((O) (\outDATA<6>\\$WA2.UIM \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \outDATA<6>\\$WA2.UIM_MC.Q_1087 \ 0 12125 (_entity .  X_BUF)
		(_port
			((I) (\outDATA<6>\\$WA2.UIM_MC.D \))
			((O) (\outDATA<6>\\$WA2.UIM_MC.Q \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \outDATA<6>\\$WA2.UIM_MC.D_1088 \ 0 12129 (_entity .  X_XOR2)
		(_port
			((I0) (\outDATA<6>\\$WA2.UIM_MC.D1 \))
			((I1) (\outDATA<6>\\$WA2.UIM_MC.D2 \))
			((O) (\outDATA<6>\\$WA2.UIM_MC.D \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \outDATA<6>\\$WA2.UIM_MC.D1_1089 \ 0 12134 (_entity .  X_AND2)
		(_port
			((I0) (\Home1_II/UIM \))
			((I1) (\Home1_II/UIM \))
			((O) (\outDATA<6>\\$WA2.UIM_MC.D1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \outDATA<6>\\$WA2.UIM_MC.D2_1090 \ 0 12139 (_entity .  X_ZERO)
		(_port
			((O) (\outDATA<6>\\$WA2.UIM_MC.D2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \outDATA<6>\\$WA3.UIM_1091 \ 0 12142 (_entity .  X_BUF)
		(_port
			((I) (\outDATA<6>\\$WA3.UIM_MC.Q \))
			((O) (\outDATA<6>\\$WA3.UIM \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \outDATA<6>\\$WA3.UIM_MC.Q_1092 \ 0 12146 (_entity .  X_BUF)
		(_port
			((I) (\outDATA<6>\\$WA3.UIM_MC.D \))
			((O) (\outDATA<6>\\$WA3.UIM_MC.Q \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \outDATA<6>\\$WA3.UIM_MC.D_1093 \ 0 12150 (_entity .  X_XOR2)
		(_port
			((I0) (\outDATA<6>\\$WA3.UIM_MC.D1 \))
			((I1) (\outDATA<6>\\$WA3.UIM_MC.D2 \))
			((O) (\outDATA<6>\\$WA3.UIM_MC.D \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \outDATA<6>\\$WA3.UIM_MC.D1_1094 \ 0 12155 (_entity .  X_ZERO)
		(_port
			((O) (\outDATA<6>\\$WA3.UIM_MC.D1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \outDATA<6>\\$WA3.UIM_MC.D2_PT_0_1095 \ 0 12158 (_entity .  X_AND2)
		(_port
			((I0) (NET2528))
			((I1) (\U4/Flgreg \(6)))
			((O) (\outDATA<6>\\$WA3.UIM_MC.D2_PT_0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \outDATA<6>\\$WA3.UIM_MC.D2_PT_1_1096 \ 0 12163 (_entity .  X_AND2)
		(_port
			((I0) (\NlwInverterSignal_outDATA<6>\\$WA3.UIM_MC.D2_PT_1/IN0 \))
			((I1) (\Enc133FLG_II/UIM \))
			((O) (\outDATA<6>\\$WA3.UIM_MC.D2_PT_1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \outDATA<6>\\$WA3.UIM_MC.D2_1097 \ 0 12168 (_entity .  X_OR2)
		(_port
			((I0) (\outDATA<6>\\$WA3.UIM_MC.D2_PT_0 \))
			((I1) (\outDATA<6>\\$WA3.UIM_MC.D2_PT_1 \))
			((O) (\outDATA<6>\\$WA3.UIM_MC.D2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \outDATA<6>\\$WA5.UIM_1098 \ 0 12173 (_entity .  X_BUF)
		(_port
			((I) (\outDATA<6>\\$WA5.UIM_MC.Q \))
			((O) (\outDATA<6>\\$WA5.UIM \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \outDATA<6>\\$WA5.UIM_MC.Q_1099 \ 0 12177 (_entity .  X_BUF)
		(_port
			((I) (\outDATA<6>\\$WA5.UIM_MC.D \))
			((O) (\outDATA<6>\\$WA5.UIM_MC.Q \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \outDATA<6>\\$WA5.UIM_MC.D_1100 \ 0 12181 (_entity .  X_XOR2)
		(_port
			((I0) (\outDATA<6>\\$WA5.UIM_MC.D1 \))
			((I1) (\outDATA<6>\\$WA5.UIM_MC.D2 \))
			((O) (\outDATA<6>\\$WA5.UIM_MC.D \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \outDATA<6>\\$WA5.UIM_MC.D1_1101 \ 0 12186 (_entity .  X_ZERO)
		(_port
			((O) (\outDATA<6>\\$WA5.UIM_MC.D1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \outDATA<6>\\$WA5.UIM_MC.D2_PT_0_1102 \ 0 12189 (_entity .  X_AND2)
		(_port
			((I0) (N_PZ_966))
			((I1) (\U1/U3/holdingreg \(6)))
			((O) (\outDATA<6>\\$WA5.UIM_MC.D2_PT_0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \outDATA<6>\\$WA5.UIM_MC.D2_PT_1_1103 \ 0 12194 (_entity .  X_AND2)
		(_port
			((I0) (N_PZ_1002))
			((I1) (\U1/U3/holdingreg \(22)))
			((O) (\outDATA<6>\\$WA5.UIM_MC.D2_PT_1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \outDATA<6>\\$WA5.UIM_MC.D2_PT_2_1104 \ 0 12199 (_entity .  X_AND2)
		(_port
			((I0) (N_PZ_1061))
			((I1) (\U1/U3/holdingreg \(14)))
			((O) (\outDATA<6>\\$WA5.UIM_MC.D2_PT_2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \outDATA<6>\\$WA5.UIM_MC.D2_1105 \ 0 12204 (_entity .  X_OR3)
		(_port
			((I0) (\outDATA<6>\\$WA5.UIM_MC.D2_PT_0 \))
			((I1) (\outDATA<6>\\$WA5.UIM_MC.D2_PT_1 \))
			((I2) (\outDATA<6>\\$WA5.UIM_MC.D2_PT_2 \))
			((O) (\outDATA<6>\\$WA5.UIM_MC.D2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U3/holdingreg<6> \ 0 12210 (_entity .  X_BUF)
		(_port
			((I) (\U1/U3/holdingreg<6>_MC.Q \))
			((O) (\U1/U3/holdingreg \(6)))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U3/holdingreg<6>_MC.REG \ 0 12214 (_entity .  X_FF)
		(_port
			((I) (\U1/U3/holdingreg<6>_MC.D \))
			((CE) (Vcc))
			((CLK) (\U1/U3/holdingreg<6>_MC.REG_tsimcreated_inv_Mclk_II/FCLK \))
			((SET) (Gnd))
			((RST) (PRLD))
			((O) (\U1/U3/holdingreg<6>_MC.Q \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U3/holdingreg<6>_MC.REG_tsimcreated_inv_Mclk_II/FCLK_1106 \ 0 12222 (_entity .  X_INV)
		(_port
			((I) (\Mclk_II/FCLK \))
			((O) (\U1/U3/holdingreg<6>_MC.REG_tsimcreated_inv_Mclk_II/FCLK \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U3/holdingreg<6>_MC.D_1107 \ 0 12226 (_entity .  X_XOR2)
		(_port
			((I0) (\U1/U3/holdingreg<6>_MC.D1 \))
			((I1) (\U1/U3/holdingreg<6>_MC.D2 \))
			((O) (\U1/U3/holdingreg<6>_MC.D \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U3/holdingreg<6>_MC.D1_1108 \ 0 12231 (_entity .  X_ZERO)
		(_port
			((O) (\U1/U3/holdingreg<6>_MC.D1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U3/holdingreg<6>_MC.D2_PT_0_1109 \ 0 12234 (_entity .  X_AND2)
		(_port
			((I0) (N_PZ_986))
			((I1) (\U1/Channel1 \(6)))
			((O) (\U1/U3/holdingreg<6>_MC.D2_PT_0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U3/holdingreg<6>_MC.D2_PT_1_1110 \ 0 12239 (_entity .  X_AND3)
		(_port
			((I0) (\NlwInverterSignal_U1/U3/holdingreg<6>_MC.D2_PT_1/IN0 \))
			((I1) (\U1/U3/RDedge \))
			((I2) (\U1/U3/holdingreg \(6)))
			((O) (\U1/U3/holdingreg<6>_MC.D2_PT_1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U3/holdingreg<6>_MC.D2_PT_2_1111 \ 0 12245 (_entity .  X_AND16)
		(_port
			((I0) (\WR_II/UIM \))
			((I1) (\NlwInverterSignal_U1/U3/holdingreg<6>_MC.D2_PT_2/IN1 \))
			((I2) (U2_ADDR_reg(1)))
			((I3) (U2_ADDR_reg(0)))
			((I4) (N_PZ_931))
			((I5) (U2_ADDR_reg(2)))
			((I6) (\NlwInverterSignal_U1/U3/holdingreg<6>_MC.D2_PT_2/IN6 \))
			((I7) (\NlwInverterSignal_U1/U3/holdingreg<6>_MC.D2_PT_2/IN7 \))
			((I8) (\NlwInverterSignal_U1/U3/holdingreg<6>_MC.D2_PT_2/IN8 \))
			((I9) (\U1/Channel0 \(6)))
			((I10) (Vcc))
			((I11) (Vcc))
			((I12) (Vcc))
			((I13) (Vcc))
			((I14) (Vcc))
			((I15) (Vcc))
			((O) (\U1/U3/holdingreg<6>_MC.D2_PT_2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U3/holdingreg<6>_MC.D2_1112 \ 0 12264 (_entity .  X_OR3)
		(_port
			((I0) (\U1/U3/holdingreg<6>_MC.D2_PT_0 \))
			((I1) (\U1/U3/holdingreg<6>_MC.D2_PT_1 \))
			((I2) (\U1/U3/holdingreg<6>_MC.D2_PT_2 \))
			((O) (\U1/U3/holdingreg<6>_MC.D2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U3/holdingreg<22> \ 0 12270 (_entity .  X_BUF)
		(_port
			((I) (\U1/U3/holdingreg<22>_MC.Q \))
			((O) (\U1/U3/holdingreg \(22)))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U3/holdingreg<22>_MC.REG \ 0 12274 (_entity .  X_FF)
		(_port
			((I) (\U1/U3/holdingreg<22>_MC.D \))
			((CE) (Vcc))
			((CLK) (\U1/U3/holdingreg<22>_MC.REG_tsimcreated_inv_Mclk_II/FCLK \))
			((SET) (Gnd))
			((RST) (PRLD))
			((O) (\U1/U3/holdingreg<22>_MC.Q \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U3/holdingreg<22>_MC.REG_tsimcreated_inv_Mclk_II/FCLK_1113 \ 0 12282 (_entity .  X_INV)
		(_port
			((I) (\Mclk_II/FCLK \))
			((O) (\U1/U3/holdingreg<22>_MC.REG_tsimcreated_inv_Mclk_II/FCLK \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U3/holdingreg<22>_MC.D_1114 \ 0 12286 (_entity .  X_XOR2)
		(_port
			((I0) (\U1/U3/holdingreg<22>_MC.D1 \))
			((I1) (\U1/U3/holdingreg<22>_MC.D2 \))
			((O) (\U1/U3/holdingreg<22>_MC.D \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U3/holdingreg<22>_MC.D1_1115 \ 0 12291 (_entity .  X_ZERO)
		(_port
			((O) (\U1/U3/holdingreg<22>_MC.D1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U3/holdingreg<22>_MC.D2_PT_0_1116 \ 0 12294 (_entity .  X_AND2)
		(_port
			((I0) (N_PZ_986))
			((I1) (\U1/Channel1 \(22)))
			((O) (\U1/U3/holdingreg<22>_MC.D2_PT_0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U3/holdingreg<22>_MC.D2_PT_1_1117 \ 0 12299 (_entity .  X_AND3)
		(_port
			((I0) (\NlwInverterSignal_U1/U3/holdingreg<22>_MC.D2_PT_1/IN0 \))
			((I1) (\U1/U3/RDedge \))
			((I2) (\U1/U3/holdingreg \(22)))
			((O) (\U1/U3/holdingreg<22>_MC.D2_PT_1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U3/holdingreg<22>_MC.D2_PT_2_1118 \ 0 12305 (_entity .  X_AND16)
		(_port
			((I0) (\WR_II/UIM \))
			((I1) (\NlwInverterSignal_U1/U3/holdingreg<22>_MC.D2_PT_2/IN1 \))
			((I2) (U2_ADDR_reg(1)))
			((I3) (U2_ADDR_reg(0)))
			((I4) (N_PZ_931))
			((I5) (U2_ADDR_reg(2)))
			((I6) (\NlwInverterSignal_U1/U3/holdingreg<22>_MC.D2_PT_2/IN6 \))
			((I7) (\NlwInverterSignal_U1/U3/holdingreg<22>_MC.D2_PT_2/IN7 \))
			((I8) (\NlwInverterSignal_U1/U3/holdingreg<22>_MC.D2_PT_2/IN8 \))
			((I9) (\U1/Channel0 \(22)))
			((I10) (Vcc))
			((I11) (Vcc))
			((I12) (Vcc))
			((I13) (Vcc))
			((I14) (Vcc))
			((I15) (Vcc))
			((O) (\U1/U3/holdingreg<22>_MC.D2_PT_2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U3/holdingreg<22>_MC.D2_1119 \ 0 12324 (_entity .  X_OR3)
		(_port
			((I0) (\U1/U3/holdingreg<22>_MC.D2_PT_0 \))
			((I1) (\U1/U3/holdingreg<22>_MC.D2_PT_1 \))
			((I2) (\U1/U3/holdingreg<22>_MC.D2_PT_2 \))
			((O) (\U1/U3/holdingreg<22>_MC.D2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/Channel0<22> \ 0 12330 (_entity .  X_BUF)
		(_port
			((I) (\U1/Channel0<22>_MC.Q \))
			((O) (\U1/Channel0 \(22)))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/Channel0<22>_MC_tsimcreated_xor__1120 \ 0 12334 (_entity .  X_XOR2)
		(_port
			((I0) (\U1/Channel0<22>_MC.D \))
			((I1) (\U1/Channel0<22>_MC.Q \))
			((O) (\U1/Channel0<22>_MC_tsimcreated_xor_ \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/Channel0<22>_MC.REG \ 0 12339 (_entity .  X_FF)
		(_port
			((I) (\U1/Channel0<22>_MC_tsimcreated_xor_ \))
			((CE) (Vcc))
			((CLK) (\Mclk_II/FCLK \))
			((SET) (Gnd))
			((RST) (PRLD))
			((O) (\U1/Channel0<22>_MC.Q \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/Channel0<22>_MC.D_1121 \ 0 12347 (_entity .  X_XOR2)
		(_port
			((I0) (\U1/Channel0<22>_MC.D1 \))
			((I1) (\U1/Channel0<22>_MC.D2 \))
			((O) (\U1/Channel0<22>_MC.D \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/Channel0<22>_MC.D1_1122 \ 0 12352 (_entity .  X_ZERO)
		(_port
			((O) (\U1/Channel0<22>_MC.D1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/Channel0<22>_MC.D2_PT_0_1123 \ 0 12355 (_entity .  X_AND2)
		(_port
			((I0) (\NlwInverterSignal_U1/Channel0<22>_MC.D2_PT_0/IN0 \))
			((I1) (\U1/Channel0 \(22)))
			((O) (\U1/Channel0<22>_MC.D2_PT_0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/Channel0<22>_MC.D2_PT_1_1124 \ 0 12360 (_entity .  X_AND16)
		(_port
			((I0) (N_PZ_949))
			((I1) (N_PZ_1018))
			((I2) (N_PZ_961))
			((I3) (\NlwInverterSignal_U1/Channel0<22>_MC.D2_PT_1/IN3 \))
			((I4) (\NlwInverterSignal_U1/Channel0<22>_MC.D2_PT_1/IN4 \))
			((I5) (\U1/U2/location_Maddsub__n0000__n0115 \(0)))
			((I6) (\NlwInverterSignal_U1/Channel0<22>_MC.D2_PT_1/IN6 \))
			((I7) (\NlwInverterSignal_U1/Channel0<22>_MC.D2_PT_1/IN7 \))
			((I8) (\NlwInverterSignal_U1/Channel0<22>_MC.D2_PT_1/IN8 \))
			((I9) (\NlwInverterSignal_U1/Channel0<22>_MC.D2_PT_1/IN9 \))
			((I10) (\NlwInverterSignal_U1/Channel0<22>_MC.D2_PT_1/IN10 \))
			((I11) (\NlwInverterSignal_U1/Channel0<22>_MC.D2_PT_1/IN11 \))
			((I12) (\NlwInverterSignal_U1/Channel0<22>_MC.D2_PT_1/IN12 \))
			((I13) (Vcc))
			((I14) (Vcc))
			((I15) (Vcc))
			((O) (\U1/Channel0<22>_MC.D2_PT_1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/Channel0<22>_MC.D2_PT_2_1125 \ 0 12379 (_entity .  X_AND16)
		(_port
			((I0) (N_PZ_949))
			((I1) (N_PZ_1018))
			((I2) (\NlwInverterSignal_U1/Channel0<22>_MC.D2_PT_2/IN2 \))
			((I3) (\U1/Channel0 \(21)))
			((I4) (\U1/Channel0 \(13)))
			((I5) (\NlwInverterSignal_U1/Channel0<22>_MC.D2_PT_2/IN5 \))
			((I6) (\U1/Channel0 \(14)))
			((I7) (\U1/Channel0 \(15)))
			((I8) (\U1/Channel0 \(16)))
			((I9) (\U1/Channel0 \(17)))
			((I10) (\U1/Channel0 \(18)))
			((I11) (\U1/Channel0 \(19)))
			((I12) (\U1/Channel0 \(20)))
			((I13) (Vcc))
			((I14) (Vcc))
			((I15) (Vcc))
			((O) (\U1/Channel0<22>_MC.D2_PT_2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/Channel0<22>_MC.D2_1126 \ 0 12398 (_entity .  X_OR3)
		(_port
			((I0) (\U1/Channel0<22>_MC.D2_PT_0 \))
			((I1) (\U1/Channel0<22>_MC.D2_PT_1 \))
			((I2) (\U1/Channel0<22>_MC.D2_PT_2 \))
			((O) (\U1/Channel0<22>_MC.D2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/Channel1<22> \ 0 12404 (_entity .  X_BUF)
		(_port
			((I) (\U1/Channel1<22>_MC.Q \))
			((O) (\U1/Channel1 \(22)))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/Channel1<22>_MC_tsimcreated_xor__1127 \ 0 12408 (_entity .  X_XOR2)
		(_port
			((I0) (\U1/Channel1<22>_MC.D \))
			((I1) (\U1/Channel1<22>_MC.Q \))
			((O) (\U1/Channel1<22>_MC_tsimcreated_xor_ \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/Channel1<22>_MC.REG \ 0 12413 (_entity .  X_FF)
		(_port
			((I) (\U1/Channel1<22>_MC_tsimcreated_xor_ \))
			((CE) (Vcc))
			((CLK) (\Mclk_II/FCLK \))
			((SET) (Gnd))
			((RST) (PRLD))
			((O) (\U1/Channel1<22>_MC.Q \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/Channel1<22>_MC.D_1128 \ 0 12421 (_entity .  X_XOR2)
		(_port
			((I0) (\U1/Channel1<22>_MC.D1 \))
			((I1) (\U1/Channel1<22>_MC.D2 \))
			((O) (\U1/Channel1<22>_MC.D \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/Channel1<22>_MC.D1_1129 \ 0 12426 (_entity .  X_ZERO)
		(_port
			((O) (\U1/Channel1<22>_MC.D1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/Channel1<22>_MC.D2_PT_0_1130 \ 0 12429 (_entity .  X_AND2)
		(_port
			((I0) (\NlwInverterSignal_U1/Channel1<22>_MC.D2_PT_0/IN0 \))
			((I1) (\U1/Channel1 \(22)))
			((O) (\U1/Channel1<22>_MC.D2_PT_0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/Channel1<22>_MC.D2_PT_1_1131 \ 0 12434 (_entity .  X_AND16)
		(_port
			((I0) (N_PZ_948))
			((I1) (N_PZ_1082))
			((I2) (N_PZ_993))
			((I3) (\NlwInverterSignal_U1/Channel1<22>_MC.D2_PT_1/IN3 \))
			((I4) (\NlwInverterSignal_U1/Channel1<22>_MC.D2_PT_1/IN4 \))
			((I5) (\U1/U5/location_Maddsub__n0000__n0115 \(0)))
			((I6) (\NlwInverterSignal_U1/Channel1<22>_MC.D2_PT_1/IN6 \))
			((I7) (\NlwInverterSignal_U1/Channel1<22>_MC.D2_PT_1/IN7 \))
			((I8) (\NlwInverterSignal_U1/Channel1<22>_MC.D2_PT_1/IN8 \))
			((I9) (\NlwInverterSignal_U1/Channel1<22>_MC.D2_PT_1/IN9 \))
			((I10) (\NlwInverterSignal_U1/Channel1<22>_MC.D2_PT_1/IN10 \))
			((I11) (\NlwInverterSignal_U1/Channel1<22>_MC.D2_PT_1/IN11 \))
			((I12) (\NlwInverterSignal_U1/Channel1<22>_MC.D2_PT_1/IN12 \))
			((I13) (Vcc))
			((I14) (Vcc))
			((I15) (Vcc))
			((O) (\U1/Channel1<22>_MC.D2_PT_1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/Channel1<22>_MC.D2_PT_2_1132 \ 0 12453 (_entity .  X_AND16)
		(_port
			((I0) (N_PZ_948))
			((I1) (N_PZ_1082))
			((I2) (\NlwInverterSignal_U1/Channel1<22>_MC.D2_PT_2/IN2 \))
			((I3) (\U1/Channel1 \(21)))
			((I4) (\U1/Channel1 \(13)))
			((I5) (\NlwInverterSignal_U1/Channel1<22>_MC.D2_PT_2/IN5 \))
			((I6) (\U1/Channel1 \(14)))
			((I7) (\U1/Channel1 \(15)))
			((I8) (\U1/Channel1 \(16)))
			((I9) (\U1/Channel1 \(17)))
			((I10) (\U1/Channel1 \(18)))
			((I11) (\U1/Channel1 \(19)))
			((I12) (\U1/Channel1 \(20)))
			((I13) (Vcc))
			((I14) (Vcc))
			((I15) (Vcc))
			((O) (\U1/Channel1<22>_MC.D2_PT_2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/Channel1<22>_MC.D2_1133 \ 0 12472 (_entity .  X_OR3)
		(_port
			((I0) (\U1/Channel1<22>_MC.D2_PT_0 \))
			((I1) (\U1/Channel1<22>_MC.D2_PT_1 \))
			((I2) (\U1/Channel1<22>_MC.D2_PT_2 \))
			((O) (\U1/Channel1<22>_MC.D2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U3/holdingreg<14> \ 0 12478 (_entity .  X_BUF)
		(_port
			((I) (\U1/U3/holdingreg<14>_MC.Q \))
			((O) (\U1/U3/holdingreg \(14)))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U3/holdingreg<14>_MC.REG \ 0 12482 (_entity .  X_FF)
		(_port
			((I) (\U1/U3/holdingreg<14>_MC.D \))
			((CE) (Vcc))
			((CLK) (\U1/U3/holdingreg<14>_MC.REG_tsimcreated_inv_Mclk_II/FCLK \))
			((SET) (Gnd))
			((RST) (PRLD))
			((O) (\U1/U3/holdingreg<14>_MC.Q \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U3/holdingreg<14>_MC.REG_tsimcreated_inv_Mclk_II/FCLK_1134 \ 0 12490 (_entity .  X_INV)
		(_port
			((I) (\Mclk_II/FCLK \))
			((O) (\U1/U3/holdingreg<14>_MC.REG_tsimcreated_inv_Mclk_II/FCLK \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U3/holdingreg<14>_MC.D_1135 \ 0 12494 (_entity .  X_XOR2)
		(_port
			((I0) (\U1/U3/holdingreg<14>_MC.D1 \))
			((I1) (\U1/U3/holdingreg<14>_MC.D2 \))
			((O) (\U1/U3/holdingreg<14>_MC.D \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U3/holdingreg<14>_MC.D1_1136 \ 0 12499 (_entity .  X_ZERO)
		(_port
			((O) (\U1/U3/holdingreg<14>_MC.D1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U3/holdingreg<14>_MC.D2_PT_0_1137 \ 0 12502 (_entity .  X_AND2)
		(_port
			((I0) (N_PZ_986))
			((I1) (\U1/Channel1 \(14)))
			((O) (\U1/U3/holdingreg<14>_MC.D2_PT_0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U3/holdingreg<14>_MC.D2_PT_1_1138 \ 0 12507 (_entity .  X_AND3)
		(_port
			((I0) (\NlwInverterSignal_U1/U3/holdingreg<14>_MC.D2_PT_1/IN0 \))
			((I1) (\U1/U3/RDedge \))
			((I2) (\U1/U3/holdingreg \(14)))
			((O) (\U1/U3/holdingreg<14>_MC.D2_PT_1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U3/holdingreg<14>_MC.D2_PT_2_1139 \ 0 12513 (_entity .  X_AND16)
		(_port
			((I0) (\WR_II/UIM \))
			((I1) (\NlwInverterSignal_U1/U3/holdingreg<14>_MC.D2_PT_2/IN1 \))
			((I2) (U2_ADDR_reg(1)))
			((I3) (U2_ADDR_reg(0)))
			((I4) (N_PZ_931))
			((I5) (U2_ADDR_reg(2)))
			((I6) (\NlwInverterSignal_U1/U3/holdingreg<14>_MC.D2_PT_2/IN6 \))
			((I7) (\NlwInverterSignal_U1/U3/holdingreg<14>_MC.D2_PT_2/IN7 \))
			((I8) (\NlwInverterSignal_U1/U3/holdingreg<14>_MC.D2_PT_2/IN8 \))
			((I9) (\U1/Channel0 \(14)))
			((I10) (Vcc))
			((I11) (Vcc))
			((I12) (Vcc))
			((I13) (Vcc))
			((I14) (Vcc))
			((I15) (Vcc))
			((O) (\U1/U3/holdingreg<14>_MC.D2_PT_2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U3/holdingreg<14>_MC.D2_1140 \ 0 12532 (_entity .  X_OR3)
		(_port
			((I0) (\U1/U3/holdingreg<14>_MC.D2_PT_0 \))
			((I1) (\U1/U3/holdingreg<14>_MC.D2_PT_1 \))
			((I2) (\U1/U3/holdingreg<14>_MC.D2_PT_2 \))
			((O) (\U1/U3/holdingreg<14>_MC.D2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \outDATA<6>\\$WA4.UIM_1141 \ 0 12538 (_entity .  X_BUF)
		(_port
			((I) (\outDATA<6>\\$WA4.UIM_MC.Q \))
			((O) (\outDATA<6>\\$WA4.UIM \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \outDATA<6>\\$WA4.UIM_MC.Q_1142 \ 0 12542 (_entity .  X_BUF)
		(_port
			((I) (\outDATA<6>\\$WA4.UIM_MC.D \))
			((O) (\outDATA<6>\\$WA4.UIM_MC.Q \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \outDATA<6>\\$WA4.UIM_MC.D_1143 \ 0 12546 (_entity .  X_XOR2)
		(_port
			((I0) (\outDATA<6>\\$WA4.UIM_MC.D1 \))
			((I1) (\outDATA<6>\\$WA4.UIM_MC.D2 \))
			((O) (\outDATA<6>\\$WA4.UIM_MC.D \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \outDATA<6>\\$WA4.UIM_MC.D1_1144 \ 0 12551 (_entity .  X_ZERO)
		(_port
			((O) (\outDATA<6>\\$WA4.UIM_MC.D1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \outDATA<6>\\$WA4.UIM_MC.D2_PT_0_1145 \ 0 12554 (_entity .  X_AND2)
		(_port
			((I0) (N_PZ_1003))
			((I1) (\U1/U4/Latch1r \(14)))
			((O) (\outDATA<6>\\$WA4.UIM_MC.D2_PT_0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \outDATA<6>\\$WA4.UIM_MC.D2_PT_1_1146 \ 0 12559 (_entity .  X_AND8)
		(_port
			((I0) (\WR_II/UIM \))
			((I1) (\NlwInverterSignal_outDATA<6>\\$WA4.UIM_MC.D2_PT_1/IN1 \))
			((I2) (U2_ADDR_reg(1)))
			((I3) (U2_ADDR_reg(0)))
			((I4) (N_PZ_931))
			((I5) (\NlwInverterSignal_outDATA<6>\\$WA4.UIM_MC.D2_PT_1/IN5 \))
			((I6) (U2_ADDR_reg(3)))
			((I7) (\U1/U4/Latch0r \(14)))
			((O) (\outDATA<6>\\$WA4.UIM_MC.D2_PT_1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \outDATA<6>\\$WA4.UIM_MC.D2_PT_2_1147 \ 0 12570 (_entity .  X_AND8)
		(_port
			((I0) (\WR_II/UIM \))
			((I1) (\NlwInverterSignal_outDATA<6>\\$WA4.UIM_MC.D2_PT_2/IN1 \))
			((I2) (U2_ADDR_reg(1)))
			((I3) (\NlwInverterSignal_outDATA<6>\\$WA4.UIM_MC.D2_PT_2/IN3 \))
			((I4) (N_PZ_931))
			((I5) (\NlwInverterSignal_outDATA<6>\\$WA4.UIM_MC.D2_PT_2/IN5 \))
			((I6) (U2_ADDR_reg(3)))
			((I7) (\U1/U4/Latch0r \(6)))
			((O) (\outDATA<6>\\$WA4.UIM_MC.D2_PT_2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \outDATA<6>\\$WA4.UIM_MC.D2_PT_3_1148 \ 0 12581 (_entity .  X_AND8)
		(_port
			((I0) (\WR_II/UIM \))
			((I1) (\NlwInverterSignal_outDATA<6>\\$WA4.UIM_MC.D2_PT_3/IN1 \))
			((I2) (\NlwInverterSignal_outDATA<6>\\$WA4.UIM_MC.D2_PT_3/IN2 \))
			((I3) (\NlwInverterSignal_outDATA<6>\\$WA4.UIM_MC.D2_PT_3/IN3 \))
			((I4) (N_PZ_931))
			((I5) (U2_ADDR_reg(2)))
			((I6) (U2_ADDR_reg(3)))
			((I7) (\U1/U4/Latch1r \(6)))
			((O) (\outDATA<6>\\$WA4.UIM_MC.D2_PT_3 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \outDATA<6>\\$WA4.UIM_MC.D2_1149 \ 0 12592 (_entity .  X_OR4)
		(_port
			((I0) (\outDATA<6>\\$WA4.UIM_MC.D2_PT_0 \))
			((I1) (\outDATA<6>\\$WA4.UIM_MC.D2_PT_1 \))
			((I2) (\outDATA<6>\\$WA4.UIM_MC.D2_PT_2 \))
			((I3) (\outDATA<6>\\$WA4.UIM_MC.D2_PT_3 \))
			((O) (\outDATA<6>\\$WA4.UIM_MC.D2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U4/Latch0r<14> \ 0 12599 (_entity .  X_BUF)
		(_port
			((I) (\U1/U4/Latch0r<14>_MC.Q \))
			((O) (\U1/U4/Latch0r \(14)))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U4/Latch0r<14>_MC.REG \ 0 12603 (_entity .  X_FF)
		(_port
			((I) (\U1/U4/Latch0r<14>_MC.D \))
			((CE) (Vcc))
			((CLK) (\U1/U4/Latch0r<14>_MC.REG_tsimcreated_inv_Mclk_II/FCLK \))
			((SET) (Gnd))
			((RST) (PRLD))
			((O) (\U1/U4/Latch0r<14>_MC.Q \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U4/Latch0r<14>_MC.REG_tsimcreated_inv_Mclk_II/FCLK_1150 \ 0 12611 (_entity .  X_INV)
		(_port
			((I) (\Mclk_II/FCLK \))
			((O) (\U1/U4/Latch0r<14>_MC.REG_tsimcreated_inv_Mclk_II/FCLK \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U4/Latch0r<14>_MC.D_1151 \ 0 12615 (_entity .  X_XOR2)
		(_port
			((I0) (\U1/U4/Latch0r<14>_MC.D1 \))
			((I1) (\U1/U4/Latch0r<14>_MC.D2 \))
			((O) (\U1/U4/Latch0r<14>_MC.D \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U4/Latch0r<14>_MC.D1_1152 \ 0 12620 (_entity .  X_ZERO)
		(_port
			((O) (\U1/U4/Latch0r<14>_MC.D1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U4/Latch0r<14>_MC.D2_PT_0_1153 \ 0 12623 (_entity .  X_AND2)
		(_port
			((I0) (N_PZ_1059))
			((I1) (\U1/U4/Latch0r \(14)))
			((O) (\U1/U4/Latch0r<14>_MC.D2_PT_0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U4/Latch0r<14>_MC.D2_PT_1_1154 \ 0 12628 (_entity .  X_AND3)
		(_port
			((I0) (\NlwInverterSignal_U1/U4/Latch0r<14>_MC.D2_PT_1/IN0 \))
			((I1) (\U1/Channel0 \(14)))
			((I2) (\NlwInverterSignal_U1/U4/Latch0r<14>_MC.D2_PT_1/IN2 \))
			((O) (\U1/U4/Latch0r<14>_MC.D2_PT_1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U4/Latch0r<14>_MC.D2_1155 \ 0 12634 (_entity .  X_OR2)
		(_port
			((I0) (\U1/U4/Latch0r<14>_MC.D2_PT_0 \))
			((I1) (\U1/U4/Latch0r<14>_MC.D2_PT_1 \))
			((O) (\U1/U4/Latch0r<14>_MC.D2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U4/Latch0r<6> \ 0 12639 (_entity .  X_BUF)
		(_port
			((I) (\U1/U4/Latch0r<6>_MC.Q \))
			((O) (\U1/U4/Latch0r \(6)))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U4/Latch0r<6>_MC.REG \ 0 12643 (_entity .  X_FF)
		(_port
			((I) (\U1/U4/Latch0r<6>_MC.D \))
			((CE) (Vcc))
			((CLK) (\U1/U4/Latch0r<6>_MC.REG_tsimcreated_inv_Mclk_II/FCLK \))
			((SET) (Gnd))
			((RST) (PRLD))
			((O) (\U1/U4/Latch0r<6>_MC.Q \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U4/Latch0r<6>_MC.REG_tsimcreated_inv_Mclk_II/FCLK_1156 \ 0 12651 (_entity .  X_INV)
		(_port
			((I) (\Mclk_II/FCLK \))
			((O) (\U1/U4/Latch0r<6>_MC.REG_tsimcreated_inv_Mclk_II/FCLK \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U4/Latch0r<6>_MC.D_1157 \ 0 12655 (_entity .  X_XOR2)
		(_port
			((I0) (\U1/U4/Latch0r<6>_MC.D1 \))
			((I1) (\U1/U4/Latch0r<6>_MC.D2 \))
			((O) (\U1/U4/Latch0r<6>_MC.D \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U4/Latch0r<6>_MC.D1_1158 \ 0 12660 (_entity .  X_ZERO)
		(_port
			((O) (\U1/U4/Latch0r<6>_MC.D1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U4/Latch0r<6>_MC.D2_PT_0_1159 \ 0 12663 (_entity .  X_AND2)
		(_port
			((I0) (N_PZ_1059))
			((I1) (\U1/U4/Latch0r \(6)))
			((O) (\U1/U4/Latch0r<6>_MC.D2_PT_0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U4/Latch0r<6>_MC.D2_PT_1_1160 \ 0 12668 (_entity .  X_AND3)
		(_port
			((I0) (\NlwInverterSignal_U1/U4/Latch0r<6>_MC.D2_PT_1/IN0 \))
			((I1) (\U1/Channel0 \(6)))
			((I2) (\NlwInverterSignal_U1/U4/Latch0r<6>_MC.D2_PT_1/IN2 \))
			((O) (\U1/U4/Latch0r<6>_MC.D2_PT_1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U4/Latch0r<6>_MC.D2_1161 \ 0 12674 (_entity .  X_OR2)
		(_port
			((I0) (\U1/U4/Latch0r<6>_MC.D2_PT_0 \))
			((I1) (\U1/U4/Latch0r<6>_MC.D2_PT_1 \))
			((O) (\U1/U4/Latch0r<6>_MC.D2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U4/Latch1r<6> \ 0 12679 (_entity .  X_BUF)
		(_port
			((I) (\U1/U4/Latch1r<6>_MC.Q \))
			((O) (\U1/U4/Latch1r \(6)))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U4/Latch1r<6>_MC.REG \ 0 12683 (_entity .  X_FF)
		(_port
			((I) (\U1/U4/Latch1r<6>_MC.D \))
			((CE) (Vcc))
			((CLK) (\U1/U4/Latch1r<6>_MC.REG_tsimcreated_inv_Mclk_II/FCLK \))
			((SET) (Gnd))
			((RST) (PRLD))
			((O) (\U1/U4/Latch1r<6>_MC.Q \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U4/Latch1r<6>_MC.REG_tsimcreated_inv_Mclk_II/FCLK_1162 \ 0 12691 (_entity .  X_INV)
		(_port
			((I) (\Mclk_II/FCLK \))
			((O) (\U1/U4/Latch1r<6>_MC.REG_tsimcreated_inv_Mclk_II/FCLK \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U4/Latch1r<6>_MC.D_1163 \ 0 12695 (_entity .  X_XOR2)
		(_port
			((I0) (\U1/U4/Latch1r<6>_MC.D1 \))
			((I1) (\U1/U4/Latch1r<6>_MC.D2 \))
			((O) (\U1/U4/Latch1r<6>_MC.D \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U4/Latch1r<6>_MC.D1_1164 \ 0 12700 (_entity .  X_ZERO)
		(_port
			((O) (\U1/U4/Latch1r<6>_MC.D1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U4/Latch1r<6>_MC.D2_PT_0_1165 \ 0 12703 (_entity .  X_AND2)
		(_port
			((I0) (\NlwInverterSignal_U1/U4/Latch1r<6>_MC.D2_PT_0/IN0 \))
			((I1) (\U1/Channel1 \(6)))
			((O) (\U1/U4/Latch1r<6>_MC.D2_PT_0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U4/Latch1r<6>_MC.D2_PT_1_1166 \ 0 12708 (_entity .  X_AND8)
		(_port
			((I0) (\NlwInverterSignal_U1/U4/Latch1r<6>_MC.D2_PT_1/IN0 \))
			((I1) (\RD_II/UIM \))
			((I2) (U2_ADDR_reg(1)))
			((I3) (N_PZ_931))
			((I4) (\NlwInverterSignal_U1/U4/Latch1r<6>_MC.D2_PT_1/IN4 \))
			((I5) (\NlwInverterSignal_U1/U4/Latch1r<6>_MC.D2_PT_1/IN5 \))
			((I6) (\NlwInverterSignal_U1/U4/Latch1r<6>_MC.D2_PT_1/IN6 \))
			((I7) (\U1/U4/Latch1r \(6)))
			((O) (\U1/U4/Latch1r<6>_MC.D2_PT_1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U4/Latch1r<6>_MC.D2_1167 \ 0 12719 (_entity .  X_OR2)
		(_port
			((I0) (\U1/U4/Latch1r<6>_MC.D2_PT_0 \))
			((I1) (\U1/U4/Latch1r<6>_MC.D2_PT_1 \))
			((O) (\U1/U4/Latch1r<6>_MC.D2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U4/Latch1r<14> \ 0 12724 (_entity .  X_BUF)
		(_port
			((I) (\U1/U4/Latch1r<14>_MC.Q \))
			((O) (\U1/U4/Latch1r \(14)))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U4/Latch1r<14>_MC.REG \ 0 12728 (_entity .  X_FF)
		(_port
			((I) (\U1/U4/Latch1r<14>_MC.D \))
			((CE) (Vcc))
			((CLK) (\U1/U4/Latch1r<14>_MC.REG_tsimcreated_inv_Mclk_II/FCLK \))
			((SET) (Gnd))
			((RST) (PRLD))
			((O) (\U1/U4/Latch1r<14>_MC.Q \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U4/Latch1r<14>_MC.REG_tsimcreated_inv_Mclk_II/FCLK_1168 \ 0 12736 (_entity .  X_INV)
		(_port
			((I) (\Mclk_II/FCLK \))
			((O) (\U1/U4/Latch1r<14>_MC.REG_tsimcreated_inv_Mclk_II/FCLK \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U4/Latch1r<14>_MC.D_1169 \ 0 12740 (_entity .  X_XOR2)
		(_port
			((I0) (\U1/U4/Latch1r<14>_MC.D1 \))
			((I1) (\U1/U4/Latch1r<14>_MC.D2 \))
			((O) (\U1/U4/Latch1r<14>_MC.D \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U4/Latch1r<14>_MC.D1_1170 \ 0 12745 (_entity .  X_ZERO)
		(_port
			((O) (\U1/U4/Latch1r<14>_MC.D1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U4/Latch1r<14>_MC.D2_PT_0_1171 \ 0 12748 (_entity .  X_AND2)
		(_port
			((I0) (\NlwInverterSignal_U1/U4/Latch1r<14>_MC.D2_PT_0/IN0 \))
			((I1) (\U1/Channel1 \(14)))
			((O) (\U1/U4/Latch1r<14>_MC.D2_PT_0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U4/Latch1r<14>_MC.D2_PT_1_1172 \ 0 12753 (_entity .  X_AND8)
		(_port
			((I0) (\NlwInverterSignal_U1/U4/Latch1r<14>_MC.D2_PT_1/IN0 \))
			((I1) (\RD_II/UIM \))
			((I2) (U2_ADDR_reg(1)))
			((I3) (N_PZ_931))
			((I4) (\NlwInverterSignal_U1/U4/Latch1r<14>_MC.D2_PT_1/IN4 \))
			((I5) (\NlwInverterSignal_U1/U4/Latch1r<14>_MC.D2_PT_1/IN5 \))
			((I6) (\NlwInverterSignal_U1/U4/Latch1r<14>_MC.D2_PT_1/IN6 \))
			((I7) (\U1/U4/Latch1r \(14)))
			((O) (\U1/U4/Latch1r<14>_MC.D2_PT_1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U4/Latch1r<14>_MC.D2_1173 \ 0 12764 (_entity .  X_OR2)
		(_port
			((I0) (\U1/U4/Latch1r<14>_MC.D2_PT_0 \))
			((I1) (\U1/U4/Latch1r<14>_MC.D2_PT_1 \))
			((O) (\U1/U4/Latch1r<14>_MC.D2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \AD<7>_MC.Q_1174 \ 0 12769 (_entity .  X_BUF)
		(_port
			((I) (\AD<7>_MC.Q_tsimrenamed_net_ \))
			((O) (\AD<7>_MC.Q \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \AD<7>_MC.OE_1175 \ 0 12773 (_entity .  X_BUF)
		(_port
			((I) (\AD<7>_MC.BUFOE.OUT \))
			((O) (\AD<7>_MC.OE \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \AD<7>_MC.BUFOE.OUT_1176 \ 0 12777 (_entity .  X_BUF)
		(_port
			((I) (\FOOBAR3__ctinst/7 \))
			((O) (\AD<7>_MC.BUFOE.OUT \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \AD<7>_MC.Q_tsimrenamed_net__1177 \ 0 12781 (_entity .  X_BUF)
		(_port
			((I) (\AD<7>_MC.D \))
			((O) (\AD<7>_MC.Q_tsimrenamed_net_ \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \AD<7>_MC.D_1178 \ 0 12785 (_entity .  X_XOR2)
		(_port
			((I0) (\NlwInverterSignal_AD<7>_MC.D/IN0 \))
			((I1) (\AD<7>_MC.D2 \))
			((O) (\AD<7>_MC.D \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \AD<7>_MC.D1_1179 \ 0 12790 (_entity .  X_ZERO)
		(_port
			((O) (\AD<7>_MC.D1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \AD<7>_MC.D2_PT_0_1180 \ 0 12793 (_entity .  X_AND2)
		(_port
			((I0) (N_PZ_964))
			((I1) (\NlwInverterSignal_AD<7>_MC.D2_PT_0/IN1 \))
			((O) (\AD<7>_MC.D2_PT_0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \AD<7>_MC.D2_PT_1_1181 \ 0 12798 (_entity .  X_AND2)
		(_port
			((I0) (N_PZ_1060))
			((I1) (\NlwInverterSignal_AD<7>_MC.D2_PT_1/IN1 \))
			((O) (\AD<7>_MC.D2_PT_1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \AD<7>_MC.D2_PT_2_1182 \ 0 12803 (_entity .  X_AND8)
		(_port
			((I0) (\WR_II/UIM \))
			((I1) (\NlwInverterSignal_AD<7>_MC.D2_PT_2/IN1 \))
			((I2) (U2_ADDR_reg(1)))
			((I3) (U2_ADDR_reg(0)))
			((I4) (N_PZ_931))
			((I5) (U2_ADDR_reg(2)))
			((I6) (U2_ADDR_reg(3)))
			((I7) (\NlwInverterSignal_AD<7>_MC.D2_PT_2/IN7 \))
			((O) (\AD<7>_MC.D2_PT_2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \AD<7>_MC.D2_PT_3_1183 \ 0 12814 (_entity .  X_AND8)
		(_port
			((I0) (\WR_II/UIM \))
			((I1) (\NlwInverterSignal_AD<7>_MC.D2_PT_3/IN1 \))
			((I2) (U2_ADDR_reg(1)))
			((I3) (U2_ADDR_reg(0)))
			((I4) (N_PZ_931))
			((I5) (\NlwInverterSignal_AD<7>_MC.D2_PT_3/IN5 \))
			((I6) (\NlwInverterSignal_AD<7>_MC.D2_PT_3/IN6 \))
			((I7) (\NlwInverterSignal_AD<7>_MC.D2_PT_3/IN7 \))
			((O) (\AD<7>_MC.D2_PT_3 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \AD<7>_MC.D2_PT_4_1184 \ 0 12825 (_entity .  X_AND8)
		(_port
			((I0) (\WR_II/UIM \))
			((I1) (\NlwInverterSignal_AD<7>_MC.D2_PT_4/IN1 \))
			((I2) (U2_ADDR_reg(1)))
			((I3) (\NlwInverterSignal_AD<7>_MC.D2_PT_4/IN3 \))
			((I4) (N_PZ_931))
			((I5) (U2_ADDR_reg(2)))
			((I6) (U2_ADDR_reg(3)))
			((I7) (\NlwInverterSignal_AD<7>_MC.D2_PT_4/IN7 \))
			((O) (\AD<7>_MC.D2_PT_4 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \AD<7>_MC.D2_PT_5_1185 \ 0 12836 (_entity .  X_AND8)
		(_port
			((I0) (\WR_II/UIM \))
			((I1) (\NlwInverterSignal_AD<7>_MC.D2_PT_5/IN1 \))
			((I2) (\NlwInverterSignal_AD<7>_MC.D2_PT_5/IN2 \))
			((I3) (\NlwInverterSignal_AD<7>_MC.D2_PT_5/IN3 \))
			((I4) (N_PZ_931))
			((I5) (\NlwInverterSignal_AD<7>_MC.D2_PT_5/IN5 \))
			((I6) (\NlwInverterSignal_AD<7>_MC.D2_PT_5/IN6 \))
			((I7) (\NlwInverterSignal_AD<7>_MC.D2_PT_5/IN7 \))
			((O) (\AD<7>_MC.D2_PT_5 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \AD<7>_MC.D2_1186 \ 0 12847 (_entity .  X_OR6)
		(_port
			((I0) (\AD<7>_MC.D2_PT_0 \))
			((I1) (\AD<7>_MC.D2_PT_1 \))
			((I2) (\AD<7>_MC.D2_PT_2 \))
			((I3) (\AD<7>_MC.D2_PT_3 \))
			((I4) (\AD<7>_MC.D2_PT_4 \))
			((I5) (\AD<7>_MC.D2_PT_5 \))
			((O) (\AD<7>_MC.D2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \outDATA<7>\\$WA0.UIM_1187 \ 0 12856 (_entity .  X_BUF)
		(_port
			((I) (\outDATA<7>\\$WA0.UIM_MC.Q \))
			((O) (\outDATA<7>\\$WA0.UIM \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \outDATA<7>\\$WA0.UIM_MC.Q_1188 \ 0 12860 (_entity .  X_BUF)
		(_port
			((I) (\outDATA<7>\\$WA0.UIM_MC.D \))
			((O) (\outDATA<7>\\$WA0.UIM_MC.Q \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \outDATA<7>\\$WA0.UIM_MC.D_1189 \ 0 12864 (_entity .  X_XOR2)
		(_port
			((I0) (\outDATA<7>\\$WA0.UIM_MC.D1 \))
			((I1) (\outDATA<7>\\$WA0.UIM_MC.D2 \))
			((O) (\outDATA<7>\\$WA0.UIM_MC.D \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \outDATA<7>\\$WA0.UIM_MC.D1_1190 \ 0 12869 (_entity .  X_ZERO)
		(_port
			((O) (\outDATA<7>\\$WA0.UIM_MC.D1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \outDATA<7>\\$WA0.UIM_MC.D2_1191 \ 0 12872 (_entity .  X_ZERO)
		(_port
			((O) (\outDATA<7>\\$WA0.UIM_MC.D2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \outDATA<7>\\$WA1.UIM_1192 \ 0 12875 (_entity .  X_BUF)
		(_port
			((I) (\outDATA<7>\\$WA1.UIM_MC.Q \))
			((O) (\outDATA<7>\\$WA1.UIM \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \outDATA<7>\\$WA1.UIM_MC.Q_1193 \ 0 12879 (_entity .  X_BUF)
		(_port
			((I) (\outDATA<7>\\$WA1.UIM_MC.D \))
			((O) (\outDATA<7>\\$WA1.UIM_MC.Q \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \outDATA<7>\\$WA1.UIM_MC.D_1194 \ 0 12883 (_entity .  X_XOR2)
		(_port
			((I0) (\outDATA<7>\\$WA1.UIM_MC.D1 \))
			((I1) (\outDATA<7>\\$WA1.UIM_MC.D2 \))
			((O) (\outDATA<7>\\$WA1.UIM_MC.D \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \outDATA<7>\\$WA1.UIM_MC.D1_1195 \ 0 12888 (_entity .  X_AND2)
		(_port
			((I0) (\GP_Motor1_0_II/UIM \))
			((I1) (\GP_Motor1_0_II/UIM \))
			((O) (\outDATA<7>\\$WA1.UIM_MC.D1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \outDATA<7>\\$WA1.UIM_MC.D2_1196 \ 0 12893 (_entity .  X_ZERO)
		(_port
			((O) (\outDATA<7>\\$WA1.UIM_MC.D2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \outDATA<7>\\$WA2.UIM_1197 \ 0 12896 (_entity .  X_BUF)
		(_port
			((I) (\outDATA<7>\\$WA2.UIM_MC.Q \))
			((O) (\outDATA<7>\\$WA2.UIM \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \outDATA<7>\\$WA2.UIM_MC.Q_1198 \ 0 12900 (_entity .  X_BUF)
		(_port
			((I) (\outDATA<7>\\$WA2.UIM_MC.D \))
			((O) (\outDATA<7>\\$WA2.UIM_MC.Q \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \outDATA<7>\\$WA2.UIM_MC.D_1199 \ 0 12904 (_entity .  X_XOR2)
		(_port
			((I0) (\outDATA<7>\\$WA2.UIM_MC.D1 \))
			((I1) (\outDATA<7>\\$WA2.UIM_MC.D2 \))
			((O) (\outDATA<7>\\$WA2.UIM_MC.D \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \outDATA<7>\\$WA2.UIM_MC.D1_1200 \ 0 12909 (_entity .  X_AND2)
		(_port
			((I0) (NET3253))
			((I1) (NET3253))
			((O) (\outDATA<7>\\$WA2.UIM_MC.D1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \outDATA<7>\\$WA2.UIM_MC.D2_1201 \ 0 12914 (_entity .  X_ZERO)
		(_port
			((O) (\outDATA<7>\\$WA2.UIM_MC.D2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation NET3253_1202 0 12917 (_entity .  X_BUF)
		(_port
			((I) (\NET3253_MC.Q \))
			((O) (NET3253))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NET3253_MC.REG \ 0 12921 (_entity .  X_FF)
		(_port
			((I) (\NET3253_MC.D \))
			((CE) (Vcc))
			((CLK) (\Mclk_II/FCLK \))
			((SET) (Gnd))
			((RST) (PRLD))
			((O) (\NET3253_MC.Q \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NET3253_MC.D_1203 \ 0 12929 (_entity .  X_XOR2)
		(_port
			((I0) (\NET3253_MC.D1 \))
			((I1) (\NET3253_MC.D2 \))
			((O) (\NET3253_MC.D \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NET3253_MC.D1_1204 \ 0 12934 (_entity .  X_ZERO)
		(_port
			((O) (\NET3253_MC.D1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NET3253_MC.D2_PT_0_1205 \ 0 12937 (_entity .  X_AND2)
		(_port
			((I0) (\NlwInverterSignal_NET3253_MC.D2_PT_0/IN0 \))
			((I1) (N_PZ_1186))
			((O) (\NET3253_MC.D2_PT_0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NET3253_MC.D2_PT_1_1206 \ 0 12942 (_entity .  X_AND4)
		(_port
			((I0) (\NlwInverterSignal_NET3253_MC.D2_PT_1/IN0 \))
			((I1) (NET3253))
			((I2) (\NlwInverterSignal_NET3253_MC.D2_PT_1/IN2 \))
			((I3) (\NlwInverterSignal_NET3253_MC.D2_PT_1/IN3 \))
			((O) (\NET3253_MC.D2_PT_1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NET3253_MC.D2_1207 \ 0 12949 (_entity .  X_OR2)
		(_port
			((I0) (\NET3253_MC.D2_PT_0 \))
			((I1) (\NET3253_MC.D2_PT_1 \))
			((O) (\NET3253_MC.D2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation N_PZ_1186_1208 0 12954 (_entity .  X_BUF)
		(_port
			((I) (\N_PZ_1186_MC.Q \))
			((O) (N_PZ_1186))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \N_PZ_1186_MC.Q_1209 \ 0 12958 (_entity .  X_BUF)
		(_port
			((I) (\N_PZ_1186_MC.D \))
			((O) (\N_PZ_1186_MC.Q \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \N_PZ_1186_MC.D_1210 \ 0 12962 (_entity .  X_XOR2)
		(_port
			((I0) (\N_PZ_1186_MC.D1 \))
			((I1) (\N_PZ_1186_MC.D2 \))
			((O) (\N_PZ_1186_MC.D \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \N_PZ_1186_MC.D1_1211 \ 0 12967 (_entity .  X_ZERO)
		(_port
			((O) (\N_PZ_1186_MC.D1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \N_PZ_1186_MC.D2_PT_0_1212 \ 0 12970 (_entity .  X_AND2)
		(_port
			((I0) (\NlwInverterSignal_N_PZ_1186_MC.D2_PT_0/IN0 \))
			((I1) (\DIR1_II/UIM \))
			((O) (\N_PZ_1186_MC.D2_PT_0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \N_PZ_1186_MC.D2_PT_1_1213 \ 0 12975 (_entity .  X_AND2)
		(_port
			((I0) (\NlwInverterSignal_N_PZ_1186_MC.D2_PT_1/IN0 \))
			((I1) (\NlwInverterSignal_N_PZ_1186_MC.D2_PT_1/IN1 \))
			((O) (\N_PZ_1186_MC.D2_PT_1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \N_PZ_1186_MC.D2_1214 \ 0 12980 (_entity .  X_OR2)
		(_port
			((I0) (\N_PZ_1186_MC.D2_PT_0 \))
			((I1) (\N_PZ_1186_MC.D2_PT_1 \))
			((O) (\N_PZ_1186_MC.D2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \outDATA<7>\\$WA3.UIM_1215 \ 0 12985 (_entity .  X_BUF)
		(_port
			((I) (\outDATA<7>\\$WA3.UIM_MC.Q \))
			((O) (\outDATA<7>\\$WA3.UIM \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \outDATA<7>\\$WA3.UIM_MC.Q_1216 \ 0 12989 (_entity .  X_BUF)
		(_port
			((I) (\outDATA<7>\\$WA3.UIM_MC.D \))
			((O) (\outDATA<7>\\$WA3.UIM_MC.Q \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \outDATA<7>\\$WA3.UIM_MC.D_1217 \ 0 12993 (_entity .  X_XOR2)
		(_port
			((I0) (\outDATA<7>\\$WA3.UIM_MC.D1 \))
			((I1) (\outDATA<7>\\$WA3.UIM_MC.D2 \))
			((O) (\outDATA<7>\\$WA3.UIM_MC.D \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \outDATA<7>\\$WA3.UIM_MC.D1_1218 \ 0 12998 (_entity .  X_ZERO)
		(_port
			((O) (\outDATA<7>\\$WA3.UIM_MC.D1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \outDATA<7>\\$WA3.UIM_MC.D2_PT_0_1219 \ 0 13001 (_entity .  X_AND2)
		(_port
			((I0) (NET2528))
			((I1) (\U4/Flgreg \(7)))
			((O) (\outDATA<7>\\$WA3.UIM_MC.D2_PT_0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \outDATA<7>\\$WA3.UIM_MC.D2_PT_1_1220 \ 0 13006 (_entity .  X_AND2)
		(_port
			((I0) (\NlwInverterSignal_outDATA<7>\\$WA3.UIM_MC.D2_PT_1/IN0 \))
			((I1) (\Enc15FLG_II/UIM \))
			((O) (\outDATA<7>\\$WA3.UIM_MC.D2_PT_1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \outDATA<7>\\$WA3.UIM_MC.D2_1221 \ 0 13011 (_entity .  X_OR2)
		(_port
			((I0) (\outDATA<7>\\$WA3.UIM_MC.D2_PT_0 \))
			((I1) (\outDATA<7>\\$WA3.UIM_MC.D2_PT_1 \))
			((O) (\outDATA<7>\\$WA3.UIM_MC.D2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \outDATA<7>\\$WA5.UIM_1222 \ 0 13016 (_entity .  X_BUF)
		(_port
			((I) (\outDATA<7>\\$WA5.UIM_MC.Q \))
			((O) (\outDATA<7>\\$WA5.UIM \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \outDATA<7>\\$WA5.UIM_MC.Q_1223 \ 0 13020 (_entity .  X_BUF)
		(_port
			((I) (\outDATA<7>\\$WA5.UIM_MC.D \))
			((O) (\outDATA<7>\\$WA5.UIM_MC.Q \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \outDATA<7>\\$WA5.UIM_MC.D_1224 \ 0 13024 (_entity .  X_XOR2)
		(_port
			((I0) (\outDATA<7>\\$WA5.UIM_MC.D1 \))
			((I1) (\outDATA<7>\\$WA5.UIM_MC.D2 \))
			((O) (\outDATA<7>\\$WA5.UIM_MC.D \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \outDATA<7>\\$WA5.UIM_MC.D1_1225 \ 0 13029 (_entity .  X_ZERO)
		(_port
			((O) (\outDATA<7>\\$WA5.UIM_MC.D1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \outDATA<7>\\$WA5.UIM_MC.D2_PT_0_1226 \ 0 13032 (_entity .  X_AND2)
		(_port
			((I0) (N_PZ_966))
			((I1) (\U1/U3/holdingreg \(7)))
			((O) (\outDATA<7>\\$WA5.UIM_MC.D2_PT_0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \outDATA<7>\\$WA5.UIM_MC.D2_PT_1_1227 \ 0 13037 (_entity .  X_AND2)
		(_port
			((I0) (N_PZ_1002))
			((I1) (\U1/U3/holdingreg \(23)))
			((O) (\outDATA<7>\\$WA5.UIM_MC.D2_PT_1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \outDATA<7>\\$WA5.UIM_MC.D2_PT_2_1228 \ 0 13042 (_entity .  X_AND2)
		(_port
			((I0) (N_PZ_1061))
			((I1) (\U1/U3/holdingreg \(15)))
			((O) (\outDATA<7>\\$WA5.UIM_MC.D2_PT_2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \outDATA<7>\\$WA5.UIM_MC.D2_1229 \ 0 13047 (_entity .  X_OR3)
		(_port
			((I0) (\outDATA<7>\\$WA5.UIM_MC.D2_PT_0 \))
			((I1) (\outDATA<7>\\$WA5.UIM_MC.D2_PT_1 \))
			((I2) (\outDATA<7>\\$WA5.UIM_MC.D2_PT_2 \))
			((O) (\outDATA<7>\\$WA5.UIM_MC.D2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U3/holdingreg<7> \ 0 13053 (_entity .  X_BUF)
		(_port
			((I) (\U1/U3/holdingreg<7>_MC.Q \))
			((O) (\U1/U3/holdingreg \(7)))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U3/holdingreg<7>_MC.REG \ 0 13057 (_entity .  X_FF)
		(_port
			((I) (\U1/U3/holdingreg<7>_MC.D \))
			((CE) (Vcc))
			((CLK) (\U1/U3/holdingreg<7>_MC.REG_tsimcreated_inv_Mclk_II/FCLK \))
			((SET) (Gnd))
			((RST) (PRLD))
			((O) (\U1/U3/holdingreg<7>_MC.Q \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U3/holdingreg<7>_MC.REG_tsimcreated_inv_Mclk_II/FCLK_1230 \ 0 13065 (_entity .  X_INV)
		(_port
			((I) (\Mclk_II/FCLK \))
			((O) (\U1/U3/holdingreg<7>_MC.REG_tsimcreated_inv_Mclk_II/FCLK \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U3/holdingreg<7>_MC.D_1231 \ 0 13069 (_entity .  X_XOR2)
		(_port
			((I0) (\U1/U3/holdingreg<7>_MC.D1 \))
			((I1) (\U1/U3/holdingreg<7>_MC.D2 \))
			((O) (\U1/U3/holdingreg<7>_MC.D \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U3/holdingreg<7>_MC.D1_1232 \ 0 13074 (_entity .  X_ZERO)
		(_port
			((O) (\U1/U3/holdingreg<7>_MC.D1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U3/holdingreg<7>_MC.D2_PT_0_1233 \ 0 13077 (_entity .  X_AND2)
		(_port
			((I0) (N_PZ_986))
			((I1) (\U1/Channel1 \(7)))
			((O) (\U1/U3/holdingreg<7>_MC.D2_PT_0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U3/holdingreg<7>_MC.D2_PT_1_1234 \ 0 13082 (_entity .  X_AND3)
		(_port
			((I0) (\NlwInverterSignal_U1/U3/holdingreg<7>_MC.D2_PT_1/IN0 \))
			((I1) (\U1/U3/RDedge \))
			((I2) (\U1/U3/holdingreg \(7)))
			((O) (\U1/U3/holdingreg<7>_MC.D2_PT_1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U3/holdingreg<7>_MC.D2_PT_2_1235 \ 0 13088 (_entity .  X_AND16)
		(_port
			((I0) (\WR_II/UIM \))
			((I1) (\NlwInverterSignal_U1/U3/holdingreg<7>_MC.D2_PT_2/IN1 \))
			((I2) (U2_ADDR_reg(1)))
			((I3) (U2_ADDR_reg(0)))
			((I4) (N_PZ_931))
			((I5) (U2_ADDR_reg(2)))
			((I6) (\NlwInverterSignal_U1/U3/holdingreg<7>_MC.D2_PT_2/IN6 \))
			((I7) (\NlwInverterSignal_U1/U3/holdingreg<7>_MC.D2_PT_2/IN7 \))
			((I8) (\NlwInverterSignal_U1/U3/holdingreg<7>_MC.D2_PT_2/IN8 \))
			((I9) (\U1/Channel0 \(7)))
			((I10) (Vcc))
			((I11) (Vcc))
			((I12) (Vcc))
			((I13) (Vcc))
			((I14) (Vcc))
			((I15) (Vcc))
			((O) (\U1/U3/holdingreg<7>_MC.D2_PT_2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U3/holdingreg<7>_MC.D2_1236 \ 0 13107 (_entity .  X_OR3)
		(_port
			((I0) (\U1/U3/holdingreg<7>_MC.D2_PT_0 \))
			((I1) (\U1/U3/holdingreg<7>_MC.D2_PT_1 \))
			((I2) (\U1/U3/holdingreg<7>_MC.D2_PT_2 \))
			((O) (\U1/U3/holdingreg<7>_MC.D2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U3/holdingreg<23> \ 0 13113 (_entity .  X_BUF)
		(_port
			((I) (\U1/U3/holdingreg<23>_MC.Q \))
			((O) (\U1/U3/holdingreg \(23)))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U3/holdingreg<23>_MC.REG \ 0 13117 (_entity .  X_FF)
		(_port
			((I) (\U1/U3/holdingreg<23>_MC.D \))
			((CE) (Vcc))
			((CLK) (\U1/U3/holdingreg<23>_MC.REG_tsimcreated_inv_Mclk_II/FCLK \))
			((SET) (Gnd))
			((RST) (PRLD))
			((O) (\U1/U3/holdingreg<23>_MC.Q \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U3/holdingreg<23>_MC.REG_tsimcreated_inv_Mclk_II/FCLK_1237 \ 0 13125 (_entity .  X_INV)
		(_port
			((I) (\Mclk_II/FCLK \))
			((O) (\U1/U3/holdingreg<23>_MC.REG_tsimcreated_inv_Mclk_II/FCLK \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U3/holdingreg<23>_MC.D_1238 \ 0 13129 (_entity .  X_XOR2)
		(_port
			((I0) (\U1/U3/holdingreg<23>_MC.D1 \))
			((I1) (\U1/U3/holdingreg<23>_MC.D2 \))
			((O) (\U1/U3/holdingreg<23>_MC.D \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U3/holdingreg<23>_MC.D1_1239 \ 0 13134 (_entity .  X_ZERO)
		(_port
			((O) (\U1/U3/holdingreg<23>_MC.D1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U3/holdingreg<23>_MC.D2_PT_0_1240 \ 0 13137 (_entity .  X_AND2)
		(_port
			((I0) (N_PZ_986))
			((I1) (\U1/Channel1 \(23)))
			((O) (\U1/U3/holdingreg<23>_MC.D2_PT_0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U3/holdingreg<23>_MC.D2_PT_1_1241 \ 0 13142 (_entity .  X_AND3)
		(_port
			((I0) (\NlwInverterSignal_U1/U3/holdingreg<23>_MC.D2_PT_1/IN0 \))
			((I1) (\U1/U3/RDedge \))
			((I2) (\U1/U3/holdingreg \(23)))
			((O) (\U1/U3/holdingreg<23>_MC.D2_PT_1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U3/holdingreg<23>_MC.D2_PT_2_1242 \ 0 13148 (_entity .  X_AND16)
		(_port
			((I0) (\WR_II/UIM \))
			((I1) (\NlwInverterSignal_U1/U3/holdingreg<23>_MC.D2_PT_2/IN1 \))
			((I2) (U2_ADDR_reg(1)))
			((I3) (U2_ADDR_reg(0)))
			((I4) (N_PZ_931))
			((I5) (U2_ADDR_reg(2)))
			((I6) (\NlwInverterSignal_U1/U3/holdingreg<23>_MC.D2_PT_2/IN6 \))
			((I7) (\NlwInverterSignal_U1/U3/holdingreg<23>_MC.D2_PT_2/IN7 \))
			((I8) (\NlwInverterSignal_U1/U3/holdingreg<23>_MC.D2_PT_2/IN8 \))
			((I9) (\U1/Channel0 \(23)))
			((I10) (Vcc))
			((I11) (Vcc))
			((I12) (Vcc))
			((I13) (Vcc))
			((I14) (Vcc))
			((I15) (Vcc))
			((O) (\U1/U3/holdingreg<23>_MC.D2_PT_2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U3/holdingreg<23>_MC.D2_1243 \ 0 13167 (_entity .  X_OR3)
		(_port
			((I0) (\U1/U3/holdingreg<23>_MC.D2_PT_0 \))
			((I1) (\U1/U3/holdingreg<23>_MC.D2_PT_1 \))
			((I2) (\U1/U3/holdingreg<23>_MC.D2_PT_2 \))
			((O) (\U1/U3/holdingreg<23>_MC.D2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/Channel0<23> \ 0 13173 (_entity .  X_BUF)
		(_port
			((I) (\U1/Channel0<23>_MC.Q \))
			((O) (\U1/Channel0 \(23)))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/Channel0<23>_MC_tsimcreated_xor__1244 \ 0 13177 (_entity .  X_XOR2)
		(_port
			((I0) (\U1/Channel0<23>_MC.D \))
			((I1) (\U1/Channel0<23>_MC.Q \))
			((O) (\U1/Channel0<23>_MC_tsimcreated_xor_ \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/Channel0<23>_MC.REG \ 0 13182 (_entity .  X_FF)
		(_port
			((I) (\U1/Channel0<23>_MC_tsimcreated_xor_ \))
			((CE) (Vcc))
			((CLK) (\Mclk_II/FCLK \))
			((SET) (Gnd))
			((RST) (PRLD))
			((O) (\U1/Channel0<23>_MC.Q \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/Channel0<23>_MC.D_1245 \ 0 13190 (_entity .  X_XOR2)
		(_port
			((I0) (\U1/Channel0<23>_MC.D1 \))
			((I1) (\U1/Channel0<23>_MC.D2 \))
			((O) (\U1/Channel0<23>_MC.D \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/Channel0<23>_MC.D1_1246 \ 0 13195 (_entity .  X_ZERO)
		(_port
			((O) (\U1/Channel0<23>_MC.D1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/Channel0<23>_MC.D2_PT_0_1247 \ 0 13198 (_entity .  X_AND2)
		(_port
			((I0) (\NlwInverterSignal_U1/Channel0<23>_MC.D2_PT_0/IN0 \))
			((I1) (\U1/Channel0 \(23)))
			((O) (\U1/Channel0<23>_MC.D2_PT_0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/Channel0<23>_MC.D2_PT_1_1248 \ 0 13203 (_entity .  X_AND16)
		(_port
			((I0) (N_PZ_949))
			((I1) (N_PZ_1018))
			((I2) (N_PZ_961))
			((I3) (\NlwInverterSignal_U1/Channel0<23>_MC.D2_PT_1/IN3 \))
			((I4) (\NlwInverterSignal_U1/Channel0<23>_MC.D2_PT_1/IN4 \))
			((I5) (\U1/U2/location_Maddsub__n0000__n0115 \(0)))
			((I6) (\NlwInverterSignal_U1/Channel0<23>_MC.D2_PT_1/IN6 \))
			((I7) (\NlwInverterSignal_U1/Channel0<23>_MC.D2_PT_1/IN7 \))
			((I8) (\NlwInverterSignal_U1/Channel0<23>_MC.D2_PT_1/IN8 \))
			((I9) (\NlwInverterSignal_U1/Channel0<23>_MC.D2_PT_1/IN9 \))
			((I10) (\NlwInverterSignal_U1/Channel0<23>_MC.D2_PT_1/IN10 \))
			((I11) (\NlwInverterSignal_U1/Channel0<23>_MC.D2_PT_1/IN11 \))
			((I12) (\NlwInverterSignal_U1/Channel0<23>_MC.D2_PT_1/IN12 \))
			((I13) (\NlwInverterSignal_U1/Channel0<23>_MC.D2_PT_1/IN13 \))
			((I14) (Vcc))
			((I15) (Vcc))
			((O) (\U1/Channel0<23>_MC.D2_PT_1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/Channel0<23>_MC.D2_PT_2_1249 \ 0 13222 (_entity .  X_AND16)
		(_port
			((I0) (N_PZ_949))
			((I1) (N_PZ_1018))
			((I2) (\NlwInverterSignal_U1/Channel0<23>_MC.D2_PT_2/IN2 \))
			((I3) (\U1/Channel0 \(21)))
			((I4) (\U1/Channel0 \(13)))
			((I5) (\NlwInverterSignal_U1/Channel0<23>_MC.D2_PT_2/IN5 \))
			((I6) (\U1/Channel0 \(14)))
			((I7) (\U1/Channel0 \(15)))
			((I8) (\U1/Channel0 \(16)))
			((I9) (\U1/Channel0 \(17)))
			((I10) (\U1/Channel0 \(18)))
			((I11) (\U1/Channel0 \(19)))
			((I12) (\U1/Channel0 \(20)))
			((I13) (\U1/Channel0 \(22)))
			((I14) (Vcc))
			((I15) (Vcc))
			((O) (\U1/Channel0<23>_MC.D2_PT_2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/Channel0<23>_MC.D2_1250 \ 0 13241 (_entity .  X_OR3)
		(_port
			((I0) (\U1/Channel0<23>_MC.D2_PT_0 \))
			((I1) (\U1/Channel0<23>_MC.D2_PT_1 \))
			((I2) (\U1/Channel0<23>_MC.D2_PT_2 \))
			((O) (\U1/Channel0<23>_MC.D2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/Channel1<23> \ 0 13247 (_entity .  X_BUF)
		(_port
			((I) (\U1/Channel1<23>_MC.Q \))
			((O) (\U1/Channel1 \(23)))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/Channel1<23>_MC_tsimcreated_xor__1251 \ 0 13251 (_entity .  X_XOR2)
		(_port
			((I0) (\U1/Channel1<23>_MC.D \))
			((I1) (\U1/Channel1<23>_MC.Q \))
			((O) (\U1/Channel1<23>_MC_tsimcreated_xor_ \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/Channel1<23>_MC.REG \ 0 13256 (_entity .  X_FF)
		(_port
			((I) (\U1/Channel1<23>_MC_tsimcreated_xor_ \))
			((CE) (Vcc))
			((CLK) (\Mclk_II/FCLK \))
			((SET) (Gnd))
			((RST) (PRLD))
			((O) (\U1/Channel1<23>_MC.Q \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/Channel1<23>_MC.D_1252 \ 0 13264 (_entity .  X_XOR2)
		(_port
			((I0) (\U1/Channel1<23>_MC.D1 \))
			((I1) (\U1/Channel1<23>_MC.D2 \))
			((O) (\U1/Channel1<23>_MC.D \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/Channel1<23>_MC.D1_1253 \ 0 13269 (_entity .  X_ZERO)
		(_port
			((O) (\U1/Channel1<23>_MC.D1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/Channel1<23>_MC.D2_PT_0_1254 \ 0 13272 (_entity .  X_AND2)
		(_port
			((I0) (\NlwInverterSignal_U1/Channel1<23>_MC.D2_PT_0/IN0 \))
			((I1) (\U1/Channel1 \(23)))
			((O) (\U1/Channel1<23>_MC.D2_PT_0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/Channel1<23>_MC.D2_PT_1_1255 \ 0 13277 (_entity .  X_AND16)
		(_port
			((I0) (N_PZ_948))
			((I1) (N_PZ_1082))
			((I2) (N_PZ_993))
			((I3) (\NlwInverterSignal_U1/Channel1<23>_MC.D2_PT_1/IN3 \))
			((I4) (\NlwInverterSignal_U1/Channel1<23>_MC.D2_PT_1/IN4 \))
			((I5) (\U1/U5/location_Maddsub__n0000__n0115 \(0)))
			((I6) (\NlwInverterSignal_U1/Channel1<23>_MC.D2_PT_1/IN6 \))
			((I7) (\NlwInverterSignal_U1/Channel1<23>_MC.D2_PT_1/IN7 \))
			((I8) (\NlwInverterSignal_U1/Channel1<23>_MC.D2_PT_1/IN8 \))
			((I9) (\NlwInverterSignal_U1/Channel1<23>_MC.D2_PT_1/IN9 \))
			((I10) (\NlwInverterSignal_U1/Channel1<23>_MC.D2_PT_1/IN10 \))
			((I11) (\NlwInverterSignal_U1/Channel1<23>_MC.D2_PT_1/IN11 \))
			((I12) (\NlwInverterSignal_U1/Channel1<23>_MC.D2_PT_1/IN12 \))
			((I13) (\NlwInverterSignal_U1/Channel1<23>_MC.D2_PT_1/IN13 \))
			((I14) (Vcc))
			((I15) (Vcc))
			((O) (\U1/Channel1<23>_MC.D2_PT_1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/Channel1<23>_MC.D2_PT_2_1256 \ 0 13296 (_entity .  X_AND16)
		(_port
			((I0) (N_PZ_948))
			((I1) (N_PZ_1082))
			((I2) (\NlwInverterSignal_U1/Channel1<23>_MC.D2_PT_2/IN2 \))
			((I3) (\U1/Channel1 \(21)))
			((I4) (\U1/Channel1 \(13)))
			((I5) (\NlwInverterSignal_U1/Channel1<23>_MC.D2_PT_2/IN5 \))
			((I6) (\U1/Channel1 \(14)))
			((I7) (\U1/Channel1 \(15)))
			((I8) (\U1/Channel1 \(16)))
			((I9) (\U1/Channel1 \(17)))
			((I10) (\U1/Channel1 \(18)))
			((I11) (\U1/Channel1 \(19)))
			((I12) (\U1/Channel1 \(20)))
			((I13) (\U1/Channel1 \(22)))
			((I14) (Vcc))
			((I15) (Vcc))
			((O) (\U1/Channel1<23>_MC.D2_PT_2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/Channel1<23>_MC.D2_1257 \ 0 13315 (_entity .  X_OR3)
		(_port
			((I0) (\U1/Channel1<23>_MC.D2_PT_0 \))
			((I1) (\U1/Channel1<23>_MC.D2_PT_1 \))
			((I2) (\U1/Channel1<23>_MC.D2_PT_2 \))
			((O) (\U1/Channel1<23>_MC.D2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U3/holdingreg<15> \ 0 13321 (_entity .  X_BUF)
		(_port
			((I) (\U1/U3/holdingreg<15>_MC.Q \))
			((O) (\U1/U3/holdingreg \(15)))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U3/holdingreg<15>_MC.REG \ 0 13325 (_entity .  X_FF)
		(_port
			((I) (\U1/U3/holdingreg<15>_MC.D \))
			((CE) (Vcc))
			((CLK) (\U1/U3/holdingreg<15>_MC.REG_tsimcreated_inv_Mclk_II/FCLK \))
			((SET) (Gnd))
			((RST) (PRLD))
			((O) (\U1/U3/holdingreg<15>_MC.Q \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U3/holdingreg<15>_MC.REG_tsimcreated_inv_Mclk_II/FCLK_1258 \ 0 13333 (_entity .  X_INV)
		(_port
			((I) (\Mclk_II/FCLK \))
			((O) (\U1/U3/holdingreg<15>_MC.REG_tsimcreated_inv_Mclk_II/FCLK \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U3/holdingreg<15>_MC.D_1259 \ 0 13337 (_entity .  X_XOR2)
		(_port
			((I0) (\U1/U3/holdingreg<15>_MC.D1 \))
			((I1) (\U1/U3/holdingreg<15>_MC.D2 \))
			((O) (\U1/U3/holdingreg<15>_MC.D \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U3/holdingreg<15>_MC.D1_1260 \ 0 13342 (_entity .  X_ZERO)
		(_port
			((O) (\U1/U3/holdingreg<15>_MC.D1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U3/holdingreg<15>_MC.D2_PT_0_1261 \ 0 13345 (_entity .  X_AND2)
		(_port
			((I0) (N_PZ_986))
			((I1) (\U1/Channel1 \(15)))
			((O) (\U1/U3/holdingreg<15>_MC.D2_PT_0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U3/holdingreg<15>_MC.D2_PT_1_1262 \ 0 13350 (_entity .  X_AND3)
		(_port
			((I0) (\NlwInverterSignal_U1/U3/holdingreg<15>_MC.D2_PT_1/IN0 \))
			((I1) (\U1/U3/RDedge \))
			((I2) (\U1/U3/holdingreg \(15)))
			((O) (\U1/U3/holdingreg<15>_MC.D2_PT_1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U3/holdingreg<15>_MC.D2_PT_2_1263 \ 0 13356 (_entity .  X_AND16)
		(_port
			((I0) (\WR_II/UIM \))
			((I1) (\NlwInverterSignal_U1/U3/holdingreg<15>_MC.D2_PT_2/IN1 \))
			((I2) (U2_ADDR_reg(1)))
			((I3) (U2_ADDR_reg(0)))
			((I4) (N_PZ_931))
			((I5) (U2_ADDR_reg(2)))
			((I6) (\NlwInverterSignal_U1/U3/holdingreg<15>_MC.D2_PT_2/IN6 \))
			((I7) (\NlwInverterSignal_U1/U3/holdingreg<15>_MC.D2_PT_2/IN7 \))
			((I8) (\NlwInverterSignal_U1/U3/holdingreg<15>_MC.D2_PT_2/IN8 \))
			((I9) (\U1/Channel0 \(15)))
			((I10) (Vcc))
			((I11) (Vcc))
			((I12) (Vcc))
			((I13) (Vcc))
			((I14) (Vcc))
			((I15) (Vcc))
			((O) (\U1/U3/holdingreg<15>_MC.D2_PT_2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U3/holdingreg<15>_MC.D2_1264 \ 0 13375 (_entity .  X_OR3)
		(_port
			((I0) (\U1/U3/holdingreg<15>_MC.D2_PT_0 \))
			((I1) (\U1/U3/holdingreg<15>_MC.D2_PT_1 \))
			((I2) (\U1/U3/holdingreg<15>_MC.D2_PT_2 \))
			((O) (\U1/U3/holdingreg<15>_MC.D2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \outDATA<7>\\$WA4.UIM_1265 \ 0 13381 (_entity .  X_BUF)
		(_port
			((I) (\outDATA<7>\\$WA4.UIM_MC.Q \))
			((O) (\outDATA<7>\\$WA4.UIM \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \outDATA<7>\\$WA4.UIM_MC.Q_1266 \ 0 13385 (_entity .  X_BUF)
		(_port
			((I) (\outDATA<7>\\$WA4.UIM_MC.D \))
			((O) (\outDATA<7>\\$WA4.UIM_MC.Q \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \outDATA<7>\\$WA4.UIM_MC.D_1267 \ 0 13389 (_entity .  X_XOR2)
		(_port
			((I0) (\outDATA<7>\\$WA4.UIM_MC.D1 \))
			((I1) (\outDATA<7>\\$WA4.UIM_MC.D2 \))
			((O) (\outDATA<7>\\$WA4.UIM_MC.D \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \outDATA<7>\\$WA4.UIM_MC.D1_1268 \ 0 13394 (_entity .  X_ZERO)
		(_port
			((O) (\outDATA<7>\\$WA4.UIM_MC.D1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \outDATA<7>\\$WA4.UIM_MC.D2_PT_0_1269 \ 0 13397 (_entity .  X_AND2)
		(_port
			((I0) (N_PZ_1003))
			((I1) (\U1/U4/Latch1r \(15)))
			((O) (\outDATA<7>\\$WA4.UIM_MC.D2_PT_0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \outDATA<7>\\$WA4.UIM_MC.D2_PT_1_1270 \ 0 13402 (_entity .  X_AND8)
		(_port
			((I0) (\WR_II/UIM \))
			((I1) (\NlwInverterSignal_outDATA<7>\\$WA4.UIM_MC.D2_PT_1/IN1 \))
			((I2) (U2_ADDR_reg(1)))
			((I3) (U2_ADDR_reg(0)))
			((I4) (N_PZ_931))
			((I5) (\NlwInverterSignal_outDATA<7>\\$WA4.UIM_MC.D2_PT_1/IN5 \))
			((I6) (U2_ADDR_reg(3)))
			((I7) (\U1/U4/Latch0r \(15)))
			((O) (\outDATA<7>\\$WA4.UIM_MC.D2_PT_1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \outDATA<7>\\$WA4.UIM_MC.D2_PT_2_1271 \ 0 13413 (_entity .  X_AND8)
		(_port
			((I0) (\WR_II/UIM \))
			((I1) (\NlwInverterSignal_outDATA<7>\\$WA4.UIM_MC.D2_PT_2/IN1 \))
			((I2) (U2_ADDR_reg(1)))
			((I3) (\NlwInverterSignal_outDATA<7>\\$WA4.UIM_MC.D2_PT_2/IN3 \))
			((I4) (N_PZ_931))
			((I5) (\NlwInverterSignal_outDATA<7>\\$WA4.UIM_MC.D2_PT_2/IN5 \))
			((I6) (U2_ADDR_reg(3)))
			((I7) (\U1/U4/Latch0r \(7)))
			((O) (\outDATA<7>\\$WA4.UIM_MC.D2_PT_2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \outDATA<7>\\$WA4.UIM_MC.D2_PT_3_1272 \ 0 13424 (_entity .  X_AND8)
		(_port
			((I0) (\WR_II/UIM \))
			((I1) (\NlwInverterSignal_outDATA<7>\\$WA4.UIM_MC.D2_PT_3/IN1 \))
			((I2) (\NlwInverterSignal_outDATA<7>\\$WA4.UIM_MC.D2_PT_3/IN2 \))
			((I3) (\NlwInverterSignal_outDATA<7>\\$WA4.UIM_MC.D2_PT_3/IN3 \))
			((I4) (N_PZ_931))
			((I5) (U2_ADDR_reg(2)))
			((I6) (U2_ADDR_reg(3)))
			((I7) (\U1/U4/Latch1r \(7)))
			((O) (\outDATA<7>\\$WA4.UIM_MC.D2_PT_3 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \outDATA<7>\\$WA4.UIM_MC.D2_1273 \ 0 13435 (_entity .  X_OR4)
		(_port
			((I0) (\outDATA<7>\\$WA4.UIM_MC.D2_PT_0 \))
			((I1) (\outDATA<7>\\$WA4.UIM_MC.D2_PT_1 \))
			((I2) (\outDATA<7>\\$WA4.UIM_MC.D2_PT_2 \))
			((I3) (\outDATA<7>\\$WA4.UIM_MC.D2_PT_3 \))
			((O) (\outDATA<7>\\$WA4.UIM_MC.D2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U4/Latch0r<15> \ 0 13442 (_entity .  X_BUF)
		(_port
			((I) (\U1/U4/Latch0r<15>_MC.Q \))
			((O) (\U1/U4/Latch0r \(15)))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U4/Latch0r<15>_MC.REG \ 0 13446 (_entity .  X_FF)
		(_port
			((I) (\U1/U4/Latch0r<15>_MC.D \))
			((CE) (Vcc))
			((CLK) (\U1/U4/Latch0r<15>_MC.REG_tsimcreated_inv_Mclk_II/FCLK \))
			((SET) (Gnd))
			((RST) (PRLD))
			((O) (\U1/U4/Latch0r<15>_MC.Q \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U4/Latch0r<15>_MC.REG_tsimcreated_inv_Mclk_II/FCLK_1274 \ 0 13454 (_entity .  X_INV)
		(_port
			((I) (\Mclk_II/FCLK \))
			((O) (\U1/U4/Latch0r<15>_MC.REG_tsimcreated_inv_Mclk_II/FCLK \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U4/Latch0r<15>_MC.D_1275 \ 0 13458 (_entity .  X_XOR2)
		(_port
			((I0) (\U1/U4/Latch0r<15>_MC.D1 \))
			((I1) (\U1/U4/Latch0r<15>_MC.D2 \))
			((O) (\U1/U4/Latch0r<15>_MC.D \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U4/Latch0r<15>_MC.D1_1276 \ 0 13463 (_entity .  X_ZERO)
		(_port
			((O) (\U1/U4/Latch0r<15>_MC.D1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U4/Latch0r<15>_MC.D2_PT_0_1277 \ 0 13466 (_entity .  X_AND2)
		(_port
			((I0) (N_PZ_1059))
			((I1) (\U1/U4/Latch0r \(15)))
			((O) (\U1/U4/Latch0r<15>_MC.D2_PT_0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U4/Latch0r<15>_MC.D2_PT_1_1278 \ 0 13471 (_entity .  X_AND3)
		(_port
			((I0) (\NlwInverterSignal_U1/U4/Latch0r<15>_MC.D2_PT_1/IN0 \))
			((I1) (\U1/Channel0 \(15)))
			((I2) (\NlwInverterSignal_U1/U4/Latch0r<15>_MC.D2_PT_1/IN2 \))
			((O) (\U1/U4/Latch0r<15>_MC.D2_PT_1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U4/Latch0r<15>_MC.D2_1279 \ 0 13477 (_entity .  X_OR2)
		(_port
			((I0) (\U1/U4/Latch0r<15>_MC.D2_PT_0 \))
			((I1) (\U1/U4/Latch0r<15>_MC.D2_PT_1 \))
			((O) (\U1/U4/Latch0r<15>_MC.D2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U4/Latch0r<7> \ 0 13482 (_entity .  X_BUF)
		(_port
			((I) (\U1/U4/Latch0r<7>_MC.Q \))
			((O) (\U1/U4/Latch0r \(7)))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U4/Latch0r<7>_MC.REG \ 0 13486 (_entity .  X_FF)
		(_port
			((I) (\U1/U4/Latch0r<7>_MC.D \))
			((CE) (Vcc))
			((CLK) (\U1/U4/Latch0r<7>_MC.REG_tsimcreated_inv_Mclk_II/FCLK \))
			((SET) (Gnd))
			((RST) (PRLD))
			((O) (\U1/U4/Latch0r<7>_MC.Q \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U4/Latch0r<7>_MC.REG_tsimcreated_inv_Mclk_II/FCLK_1280 \ 0 13494 (_entity .  X_INV)
		(_port
			((I) (\Mclk_II/FCLK \))
			((O) (\U1/U4/Latch0r<7>_MC.REG_tsimcreated_inv_Mclk_II/FCLK \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U4/Latch0r<7>_MC.D_1281 \ 0 13498 (_entity .  X_XOR2)
		(_port
			((I0) (\U1/U4/Latch0r<7>_MC.D1 \))
			((I1) (\U1/U4/Latch0r<7>_MC.D2 \))
			((O) (\U1/U4/Latch0r<7>_MC.D \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U4/Latch0r<7>_MC.D1_1282 \ 0 13503 (_entity .  X_ZERO)
		(_port
			((O) (\U1/U4/Latch0r<7>_MC.D1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U4/Latch0r<7>_MC.D2_PT_0_1283 \ 0 13506 (_entity .  X_AND2)
		(_port
			((I0) (N_PZ_1059))
			((I1) (\U1/U4/Latch0r \(7)))
			((O) (\U1/U4/Latch0r<7>_MC.D2_PT_0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U4/Latch0r<7>_MC.D2_PT_1_1284 \ 0 13511 (_entity .  X_AND3)
		(_port
			((I0) (\NlwInverterSignal_U1/U4/Latch0r<7>_MC.D2_PT_1/IN0 \))
			((I1) (\U1/Channel0 \(7)))
			((I2) (\NlwInverterSignal_U1/U4/Latch0r<7>_MC.D2_PT_1/IN2 \))
			((O) (\U1/U4/Latch0r<7>_MC.D2_PT_1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U4/Latch0r<7>_MC.D2_1285 \ 0 13517 (_entity .  X_OR2)
		(_port
			((I0) (\U1/U4/Latch0r<7>_MC.D2_PT_0 \))
			((I1) (\U1/U4/Latch0r<7>_MC.D2_PT_1 \))
			((O) (\U1/U4/Latch0r<7>_MC.D2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U4/Latch1r<7> \ 0 13522 (_entity .  X_BUF)
		(_port
			((I) (\U1/U4/Latch1r<7>_MC.Q \))
			((O) (\U1/U4/Latch1r \(7)))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U4/Latch1r<7>_MC.REG \ 0 13526 (_entity .  X_FF)
		(_port
			((I) (\U1/U4/Latch1r<7>_MC.D \))
			((CE) (Vcc))
			((CLK) (\U1/U4/Latch1r<7>_MC.REG_tsimcreated_inv_Mclk_II/FCLK \))
			((SET) (Gnd))
			((RST) (PRLD))
			((O) (\U1/U4/Latch1r<7>_MC.Q \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U4/Latch1r<7>_MC.REG_tsimcreated_inv_Mclk_II/FCLK_1286 \ 0 13534 (_entity .  X_INV)
		(_port
			((I) (\Mclk_II/FCLK \))
			((O) (\U1/U4/Latch1r<7>_MC.REG_tsimcreated_inv_Mclk_II/FCLK \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U4/Latch1r<7>_MC.D_1287 \ 0 13538 (_entity .  X_XOR2)
		(_port
			((I0) (\U1/U4/Latch1r<7>_MC.D1 \))
			((I1) (\U1/U4/Latch1r<7>_MC.D2 \))
			((O) (\U1/U4/Latch1r<7>_MC.D \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U4/Latch1r<7>_MC.D1_1288 \ 0 13543 (_entity .  X_ZERO)
		(_port
			((O) (\U1/U4/Latch1r<7>_MC.D1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U4/Latch1r<7>_MC.D2_PT_0_1289 \ 0 13546 (_entity .  X_AND2)
		(_port
			((I0) (\NlwInverterSignal_U1/U4/Latch1r<7>_MC.D2_PT_0/IN0 \))
			((I1) (\U1/Channel1 \(7)))
			((O) (\U1/U4/Latch1r<7>_MC.D2_PT_0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U4/Latch1r<7>_MC.D2_PT_1_1290 \ 0 13551 (_entity .  X_AND8)
		(_port
			((I0) (\NlwInverterSignal_U1/U4/Latch1r<7>_MC.D2_PT_1/IN0 \))
			((I1) (\RD_II/UIM \))
			((I2) (U2_ADDR_reg(1)))
			((I3) (N_PZ_931))
			((I4) (\NlwInverterSignal_U1/U4/Latch1r<7>_MC.D2_PT_1/IN4 \))
			((I5) (\NlwInverterSignal_U1/U4/Latch1r<7>_MC.D2_PT_1/IN5 \))
			((I6) (\NlwInverterSignal_U1/U4/Latch1r<7>_MC.D2_PT_1/IN6 \))
			((I7) (\U1/U4/Latch1r \(7)))
			((O) (\U1/U4/Latch1r<7>_MC.D2_PT_1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U4/Latch1r<7>_MC.D2_1291 \ 0 13562 (_entity .  X_OR2)
		(_port
			((I0) (\U1/U4/Latch1r<7>_MC.D2_PT_0 \))
			((I1) (\U1/U4/Latch1r<7>_MC.D2_PT_1 \))
			((O) (\U1/U4/Latch1r<7>_MC.D2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U4/Latch1r<15> \ 0 13567 (_entity .  X_BUF)
		(_port
			((I) (\U1/U4/Latch1r<15>_MC.Q \))
			((O) (\U1/U4/Latch1r \(15)))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U4/Latch1r<15>_MC.REG \ 0 13571 (_entity .  X_FF)
		(_port
			((I) (\U1/U4/Latch1r<15>_MC.D \))
			((CE) (Vcc))
			((CLK) (\U1/U4/Latch1r<15>_MC.REG_tsimcreated_inv_Mclk_II/FCLK \))
			((SET) (Gnd))
			((RST) (PRLD))
			((O) (\U1/U4/Latch1r<15>_MC.Q \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U4/Latch1r<15>_MC.REG_tsimcreated_inv_Mclk_II/FCLK_1292 \ 0 13579 (_entity .  X_INV)
		(_port
			((I) (\Mclk_II/FCLK \))
			((O) (\U1/U4/Latch1r<15>_MC.REG_tsimcreated_inv_Mclk_II/FCLK \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U4/Latch1r<15>_MC.D_1293 \ 0 13583 (_entity .  X_XOR2)
		(_port
			((I0) (\U1/U4/Latch1r<15>_MC.D1 \))
			((I1) (\U1/U4/Latch1r<15>_MC.D2 \))
			((O) (\U1/U4/Latch1r<15>_MC.D \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U4/Latch1r<15>_MC.D1_1294 \ 0 13588 (_entity .  X_ZERO)
		(_port
			((O) (\U1/U4/Latch1r<15>_MC.D1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U4/Latch1r<15>_MC.D2_PT_0_1295 \ 0 13591 (_entity .  X_AND2)
		(_port
			((I0) (\NlwInverterSignal_U1/U4/Latch1r<15>_MC.D2_PT_0/IN0 \))
			((I1) (\U1/Channel1 \(15)))
			((O) (\U1/U4/Latch1r<15>_MC.D2_PT_0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U4/Latch1r<15>_MC.D2_PT_1_1296 \ 0 13596 (_entity .  X_AND8)
		(_port
			((I0) (\NlwInverterSignal_U1/U4/Latch1r<15>_MC.D2_PT_1/IN0 \))
			((I1) (\RD_II/UIM \))
			((I2) (U2_ADDR_reg(1)))
			((I3) (N_PZ_931))
			((I4) (\NlwInverterSignal_U1/U4/Latch1r<15>_MC.D2_PT_1/IN4 \))
			((I5) (\NlwInverterSignal_U1/U4/Latch1r<15>_MC.D2_PT_1/IN5 \))
			((I6) (\NlwInverterSignal_U1/U4/Latch1r<15>_MC.D2_PT_1/IN6 \))
			((I7) (\U1/U4/Latch1r \(15)))
			((O) (\U1/U4/Latch1r<15>_MC.D2_PT_1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U4/Latch1r<15>_MC.D2_1297 \ 0 13607 (_entity .  X_OR2)
		(_port
			((I0) (\U1/U4/Latch1r<15>_MC.D2_PT_0 \))
			((I1) (\U1/U4/Latch1r<15>_MC.D2_PT_1 \))
			((O) (\U1/U4/Latch1r<15>_MC.D2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \Enc033ctrl_MC.Q_1298 \ 0 13612 (_entity .  X_BUF)
		(_port
			((I) (\Enc033ctrl_MC.Q_tsimrenamed_net_ \))
			((O) (\Enc033ctrl_MC.Q \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation Enc033ctrl_MC_tsimcreated_prld__1299 0 13616 (_entity .  X_OR2)
		(_port
			((I0) (\FOOBAR1__ctinst/7 \))
			((I1) (PRLD))
			((O) (Enc033ctrl_MC_tsimcreated_prld_))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \Enc033ctrl_MC.REG \ 0 13621 (_entity .  X_FF)
		(_port
			((I) (\Enc033ctrl_MC.D \))
			((CE) (\FOOBAR23__ctinst/4 \))
			((CLK) (\Mclk_II/FCLK \))
			((SET) (Gnd))
			((RST) (Enc033ctrl_MC_tsimcreated_prld_))
			((O) (\Enc033ctrl_MC.Q_tsimrenamed_net_ \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \Enc033ctrl_MC.D_1300 \ 0 13629 (_entity .  X_XOR2)
		(_port
			((I0) (\Enc033ctrl_MC.D1 \))
			((I1) (\Enc033ctrl_MC.D2 \))
			((O) (\Enc033ctrl_MC.D \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \Enc033ctrl_MC.D1_1301 \ 0 13634 (_entity .  X_AND2)
		(_port
			((I0) (\AD<5>_II/UIM \))
			((I1) (\AD<5>_II/UIM \))
			((O) (\Enc033ctrl_MC.D1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \Enc033ctrl_MC.D2_1302 \ 0 13639 (_entity .  X_ZERO)
		(_port
			((O) (\Enc033ctrl_MC.D2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \Enc05ctrl_MC.Q_1303 \ 0 13642 (_entity .  X_BUF)
		(_port
			((I) (\Enc05ctrl_MC.Q_tsimrenamed_net_ \))
			((O) (\Enc05ctrl_MC.Q \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation Enc05ctrl_MC_tsimcreated_prld__1304 0 13646 (_entity .  X_OR2)
		(_port
			((I0) (\FOOBAR1__ctinst/7 \))
			((I1) (PRLD))
			((O) (Enc05ctrl_MC_tsimcreated_prld_))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \Enc05ctrl_MC.REG \ 0 13651 (_entity .  X_FF)
		(_port
			((I) (\Enc05ctrl_MC.D \))
			((CE) (\Enc05ctrl_MC.CE \))
			((CLK) (\Mclk_II/FCLK \))
			((SET) (Gnd))
			((RST) (Enc05ctrl_MC_tsimcreated_prld_))
			((O) (\Enc05ctrl_MC.Q_tsimrenamed_net_ \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \Enc05ctrl_MC.D_1305 \ 0 13659 (_entity .  X_XOR2)
		(_port
			((I0) (\Enc05ctrl_MC.D1 \))
			((I1) (\Enc05ctrl_MC.D2 \))
			((O) (\Enc05ctrl_MC.D \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \Enc05ctrl_MC.D1_1306 \ 0 13664 (_entity .  X_AND2)
		(_port
			((I0) (\AD<4>_II/UIM \))
			((I1) (\AD<4>_II/UIM \))
			((O) (\Enc05ctrl_MC.D1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \Enc05ctrl_MC.D2_1307 \ 0 13669 (_entity .  X_ZERO)
		(_port
			((O) (\Enc05ctrl_MC.D2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \Enc05ctrl_MC.CE_1308 \ 0 13672 (_entity .  X_AND7)
		(_port
			((I0) (\NlwInverterSignal_Enc05ctrl_MC.CE/IN0 \))
			((I1) (\RD_II/UIM \))
			((I2) (U2_ADDR_reg(1)))
			((I3) (\NlwInverterSignal_Enc05ctrl_MC.CE/IN3 \))
			((I4) (N_PZ_931))
			((I5) (U2_ADDR_reg(2)))
			((I6) (U2_ADDR_reg(3)))
			((O) (\Enc05ctrl_MC.CE \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \Enc133ctrl_MC.Q_1309 \ 0 13682 (_entity .  X_BUF)
		(_port
			((I) (\Enc133ctrl_MC.Q_tsimrenamed_net_ \))
			((O) (\Enc133ctrl_MC.Q \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation Enc133ctrl_MC_tsimcreated_prld__1310 0 13686 (_entity .  X_OR2)
		(_port
			((I0) (\FOOBAR1__ctinst/7 \))
			((I1) (PRLD))
			((O) (Enc133ctrl_MC_tsimcreated_prld_))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \Enc133ctrl_MC.REG \ 0 13691 (_entity .  X_FF)
		(_port
			((I) (\Enc133ctrl_MC.D \))
			((CE) (\Enc133ctrl_MC.CE \))
			((CLK) (\Mclk_II/FCLK \))
			((SET) (Gnd))
			((RST) (Enc133ctrl_MC_tsimcreated_prld_))
			((O) (\Enc133ctrl_MC.Q_tsimrenamed_net_ \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \Enc133ctrl_MC.D_1311 \ 0 13699 (_entity .  X_XOR2)
		(_port
			((I0) (\Enc133ctrl_MC.D1 \))
			((I1) (\Enc133ctrl_MC.D2 \))
			((O) (\Enc133ctrl_MC.D \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \Enc133ctrl_MC.D1_1312 \ 0 13704 (_entity .  X_AND2)
		(_port
			((I0) (\AD<1>_II/UIM \))
			((I1) (\AD<1>_II/UIM \))
			((O) (\Enc133ctrl_MC.D1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \Enc133ctrl_MC.D2_1313 \ 0 13709 (_entity .  X_ZERO)
		(_port
			((O) (\Enc133ctrl_MC.D2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \Enc133ctrl_MC.CE_1314 \ 0 13712 (_entity .  X_AND7)
		(_port
			((I0) (\NlwInverterSignal_Enc133ctrl_MC.CE/IN0 \))
			((I1) (\RD_II/UIM \))
			((I2) (U2_ADDR_reg(1)))
			((I3) (\NlwInverterSignal_Enc133ctrl_MC.CE/IN3 \))
			((I4) (N_PZ_931))
			((I5) (U2_ADDR_reg(2)))
			((I6) (U2_ADDR_reg(3)))
			((O) (\Enc133ctrl_MC.CE \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \Enc15ctrl_MC.Q_1315 \ 0 13722 (_entity .  X_BUF)
		(_port
			((I) (\Enc15ctrl_MC.Q_tsimrenamed_net_ \))
			((O) (\Enc15ctrl_MC.Q \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation Enc15ctrl_MC_tsimcreated_prld__1316 0 13726 (_entity .  X_OR2)
		(_port
			((I0) (\FOOBAR1__ctinst/7 \))
			((I1) (PRLD))
			((O) (Enc15ctrl_MC_tsimcreated_prld_))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \Enc15ctrl_MC.REG \ 0 13731 (_entity .  X_FF)
		(_port
			((I) (\Enc15ctrl_MC.D \))
			((CE) (\Enc15ctrl_MC.CE \))
			((CLK) (\Mclk_II/FCLK \))
			((SET) (Gnd))
			((RST) (Enc15ctrl_MC_tsimcreated_prld_))
			((O) (\Enc15ctrl_MC.Q_tsimrenamed_net_ \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \Enc15ctrl_MC.D_1317 \ 0 13739 (_entity .  X_XOR2)
		(_port
			((I0) (\Enc15ctrl_MC.D1 \))
			((I1) (\Enc15ctrl_MC.D2 \))
			((O) (\Enc15ctrl_MC.D \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \Enc15ctrl_MC.D1_1318 \ 0 13744 (_entity .  X_AND2)
		(_port
			((I0) (\AD<0>_II/UIM \))
			((I1) (\AD<0>_II/UIM \))
			((O) (\Enc15ctrl_MC.D1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \Enc15ctrl_MC.D2_1319 \ 0 13749 (_entity .  X_ZERO)
		(_port
			((O) (\Enc15ctrl_MC.D2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \Enc15ctrl_MC.CE_1320 \ 0 13752 (_entity .  X_AND7)
		(_port
			((I0) (\NlwInverterSignal_Enc15ctrl_MC.CE/IN0 \))
			((I1) (\RD_II/UIM \))
			((I2) (U2_ADDR_reg(1)))
			((I3) (\NlwInverterSignal_Enc15ctrl_MC.CE/IN3 \))
			((I4) (N_PZ_931))
			((I5) (U2_ADDR_reg(2)))
			((I6) (U2_ADDR_reg(3)))
			((O) (\Enc15ctrl_MC.CE \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \GP_Motor0_1_MC.Q_1321 \ 0 13762 (_entity .  X_BUF)
		(_port
			((I) (\GP_Motor0_1_MC.Q_tsimrenamed_net_ \))
			((O) (\GP_Motor0_1_MC.Q \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation GP_Motor0_1_MC_tsimcreated_prld__1322 0 13766 (_entity .  X_OR2)
		(_port
			((I0) (\FOOBAR1__ctinst/7 \))
			((I1) (PRLD))
			((O) (GP_Motor0_1_MC_tsimcreated_prld_))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \GP_Motor0_1_MC.REG \ 0 13771 (_entity .  X_FF)
		(_port
			((I) (\GP_Motor0_1_MC.D \))
			((CE) (\FOOBAR8__ctinst/4 \))
			((CLK) (\Mclk_II/FCLK \))
			((SET) (Gnd))
			((RST) (GP_Motor0_1_MC_tsimcreated_prld_))
			((O) (\GP_Motor0_1_MC.Q_tsimrenamed_net_ \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \GP_Motor0_1_MC.D_1323 \ 0 13779 (_entity .  X_XOR2)
		(_port
			((I0) (\GP_Motor0_1_MC.D1 \))
			((I1) (\GP_Motor0_1_MC.D2 \))
			((O) (\GP_Motor0_1_MC.D \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \GP_Motor0_1_MC.D1_1324 \ 0 13784 (_entity .  X_AND2)
		(_port
			((I0) (\AD<5>_II/UIM \))
			((I1) (\AD<5>_II/UIM \))
			((O) (\GP_Motor0_1_MC.D1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \GP_Motor0_1_MC.D2_1325 \ 0 13789 (_entity .  X_ZERO)
		(_port
			((O) (\GP_Motor0_1_MC.D2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \GP_Motor1_1_MC.Q_1326 \ 0 13792 (_entity .  X_BUF)
		(_port
			((I) (\GP_Motor1_1_MC.Q_tsimrenamed_net_ \))
			((O) (\GP_Motor1_1_MC.Q \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation GP_Motor1_1_MC_tsimcreated_prld__1327 0 13796 (_entity .  X_OR2)
		(_port
			((I0) (\FOOBAR1__ctinst/7 \))
			((I1) (PRLD))
			((O) (GP_Motor1_1_MC_tsimcreated_prld_))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \GP_Motor1_1_MC.REG \ 0 13801 (_entity .  X_FF)
		(_port
			((I) (\GP_Motor1_1_MC.D \))
			((CE) (\FOOBAR15__ctinst/4 \))
			((CLK) (\Mclk_II/FCLK \))
			((SET) (Gnd))
			((RST) (GP_Motor1_1_MC_tsimcreated_prld_))
			((O) (\GP_Motor1_1_MC.Q_tsimrenamed_net_ \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \GP_Motor1_1_MC.D_1328 \ 0 13809 (_entity .  X_XOR2)
		(_port
			((I0) (\GP_Motor1_1_MC.D1 \))
			((I1) (\GP_Motor1_1_MC.D2 \))
			((O) (\GP_Motor1_1_MC.D \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \GP_Motor1_1_MC.D1_1329 \ 0 13814 (_entity .  X_AND2)
		(_port
			((I0) (\AD<6>_II/UIM \))
			((I1) (\AD<6>_II/UIM \))
			((O) (\GP_Motor1_1_MC.D1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \GP_Motor1_1_MC.D2_1330 \ 0 13819 (_entity .  X_ZERO)
		(_port
			((O) (\GP_Motor1_1_MC.D2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \HSO_MC.Q_1331 \ 0 13822 (_entity .  X_BUF)
		(_port
			((I) (\HSO_MC.Q_tsimrenamed_net_ \))
			((O) (\HSO_MC.Q \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \HSO_MC.Q_tsimrenamed_net__1332 \ 0 13826 (_entity .  X_BUF)
		(_port
			((I) (\HSO_MC.D \))
			((O) (\HSO_MC.Q_tsimrenamed_net_ \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \HSO_MC.D_1333 \ 0 13830 (_entity .  X_XOR2)
		(_port
			((I0) (\HSO_MC.D1 \))
			((I1) (\HSO_MC.D2 \))
			((O) (\HSO_MC.D \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \HSO_MC.D1_1334 \ 0 13835 (_entity .  X_AND2)
		(_port
			((I0) (\MHSO_II/UIM \))
			((I1) (\MHSO_II/UIM \))
			((O) (\HSO_MC.D1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \HSO_MC.D2_1335 \ 0 13840 (_entity .  X_ZERO)
		(_port
			((O) (\HSO_MC.D2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \Home033ctrl_MC.Q_1336 \ 0 13843 (_entity .  X_BUF)
		(_port
			((I) (\Home033ctrl_MC.Q_tsimrenamed_net_ \))
			((O) (\Home033ctrl_MC.Q \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation Home033ctrl_MC_tsimcreated_prld__1337 0 13847 (_entity .  X_OR2)
		(_port
			((I0) (\FOOBAR1__ctinst/7 \))
			((I1) (PRLD))
			((O) (Home033ctrl_MC_tsimcreated_prld_))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \Home033ctrl_MC.REG \ 0 13852 (_entity .  X_FF)
		(_port
			((I) (\Home033ctrl_MC.D \))
			((CE) (\Home033ctrl_MC.CE \))
			((CLK) (\Mclk_II/FCLK \))
			((SET) (Gnd))
			((RST) (Home033ctrl_MC_tsimcreated_prld_))
			((O) (\Home033ctrl_MC.Q_tsimrenamed_net_ \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \Home033ctrl_MC.D_1338 \ 0 13860 (_entity .  X_XOR2)
		(_port
			((I0) (\Home033ctrl_MC.D1 \))
			((I1) (\Home033ctrl_MC.D2 \))
			((O) (\Home033ctrl_MC.D \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \Home033ctrl_MC.D1_1339 \ 0 13865 (_entity .  X_AND2)
		(_port
			((I0) (\AD<7>_II/UIM \))
			((I1) (\AD<7>_II/UIM \))
			((O) (\Home033ctrl_MC.D1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \Home033ctrl_MC.D2_1340 \ 0 13870 (_entity .  X_ZERO)
		(_port
			((O) (\Home033ctrl_MC.D2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \Home033ctrl_MC.CE_1341 \ 0 13873 (_entity .  X_AND7)
		(_port
			((I0) (\NlwInverterSignal_Home033ctrl_MC.CE/IN0 \))
			((I1) (\RD_II/UIM \))
			((I2) (U2_ADDR_reg(1)))
			((I3) (\NlwInverterSignal_Home033ctrl_MC.CE/IN3 \))
			((I4) (N_PZ_931))
			((I5) (U2_ADDR_reg(2)))
			((I6) (U2_ADDR_reg(3)))
			((O) (\Home033ctrl_MC.CE \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \Home05ctrl_MC.Q_1342 \ 0 13883 (_entity .  X_BUF)
		(_port
			((I) (\Home05ctrl_MC.Q_tsimrenamed_net_ \))
			((O) (\Home05ctrl_MC.Q \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation Home05ctrl_MC_tsimcreated_prld__1343 0 13887 (_entity .  X_OR2)
		(_port
			((I0) (\FOOBAR1__ctinst/7 \))
			((I1) (PRLD))
			((O) (Home05ctrl_MC_tsimcreated_prld_))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \Home05ctrl_MC.REG \ 0 13892 (_entity .  X_FF)
		(_port
			((I) (\Home05ctrl_MC.D \))
			((CE) (\FOOBAR14__ctinst/4 \))
			((CLK) (\Mclk_II/FCLK \))
			((SET) (Gnd))
			((RST) (Home05ctrl_MC_tsimcreated_prld_))
			((O) (\Home05ctrl_MC.Q_tsimrenamed_net_ \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \Home05ctrl_MC.D_1344 \ 0 13900 (_entity .  X_XOR2)
		(_port
			((I0) (\Home05ctrl_MC.D1 \))
			((I1) (\Home05ctrl_MC.D2 \))
			((O) (\Home05ctrl_MC.D \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \Home05ctrl_MC.D1_1345 \ 0 13905 (_entity .  X_AND2)
		(_port
			((I0) (\AD<6>_II/UIM \))
			((I1) (\AD<6>_II/UIM \))
			((O) (\Home05ctrl_MC.D1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \Home05ctrl_MC.D2_1346 \ 0 13910 (_entity .  X_ZERO)
		(_port
			((O) (\Home05ctrl_MC.D2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \Home133ctrl_MC.Q_1347 \ 0 13913 (_entity .  X_BUF)
		(_port
			((I) (\Home133ctrl_MC.Q_tsimrenamed_net_ \))
			((O) (\Home133ctrl_MC.Q \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation Home133ctrl_MC_tsimcreated_prld__1348 0 13917 (_entity .  X_OR2)
		(_port
			((I0) (\FOOBAR1__ctinst/7 \))
			((I1) (PRLD))
			((O) (Home133ctrl_MC_tsimcreated_prld_))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \Home133ctrl_MC.REG \ 0 13922 (_entity .  X_FF)
		(_port
			((I) (\Home133ctrl_MC.D \))
			((CE) (\FOOBAR23__ctinst/4 \))
			((CLK) (\Mclk_II/FCLK \))
			((SET) (Gnd))
			((RST) (Home133ctrl_MC_tsimcreated_prld_))
			((O) (\Home133ctrl_MC.Q_tsimrenamed_net_ \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \Home133ctrl_MC.D_1349 \ 0 13930 (_entity .  X_XOR2)
		(_port
			((I0) (\Home133ctrl_MC.D1 \))
			((I1) (\Home133ctrl_MC.D2 \))
			((O) (\Home133ctrl_MC.D \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \Home133ctrl_MC.D1_1350 \ 0 13935 (_entity .  X_AND2)
		(_port
			((I0) (\AD<3>_II/UIM \))
			((I1) (\AD<3>_II/UIM \))
			((O) (\Home133ctrl_MC.D1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \Home133ctrl_MC.D2_1351 \ 0 13940 (_entity .  X_ZERO)
		(_port
			((O) (\Home133ctrl_MC.D2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \Home15ctrl_MC.Q_1352 \ 0 13943 (_entity .  X_BUF)
		(_port
			((I) (\Home15ctrl_MC.Q_tsimrenamed_net_ \))
			((O) (\Home15ctrl_MC.Q \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation Home15ctrl_MC_tsimcreated_prld__1353 0 13947 (_entity .  X_OR2)
		(_port
			((I0) (\FOOBAR1__ctinst/7 \))
			((I1) (PRLD))
			((O) (Home15ctrl_MC_tsimcreated_prld_))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \Home15ctrl_MC.REG \ 0 13952 (_entity .  X_FF)
		(_port
			((I) (\Home15ctrl_MC.D \))
			((CE) (\Home15ctrl_MC.CE \))
			((CLK) (\Mclk_II/FCLK \))
			((SET) (Gnd))
			((RST) (Home15ctrl_MC_tsimcreated_prld_))
			((O) (\Home15ctrl_MC.Q_tsimrenamed_net_ \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \Home15ctrl_MC.D_1354 \ 0 13960 (_entity .  X_XOR2)
		(_port
			((I0) (\Home15ctrl_MC.D1 \))
			((I1) (\Home15ctrl_MC.D2 \))
			((O) (\Home15ctrl_MC.D \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \Home15ctrl_MC.D1_1355 \ 0 13965 (_entity .  X_AND2)
		(_port
			((I0) (\AD<2>_II/UIM \))
			((I1) (\AD<2>_II/UIM \))
			((O) (\Home15ctrl_MC.D1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \Home15ctrl_MC.D2_1356 \ 0 13970 (_entity .  X_ZERO)
		(_port
			((O) (\Home15ctrl_MC.D2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \Home15ctrl_MC.CE_1357 \ 0 13973 (_entity .  X_AND7)
		(_port
			((I0) (\NlwInverterSignal_Home15ctrl_MC.CE/IN0 \))
			((I1) (\RD_II/UIM \))
			((I2) (U2_ADDR_reg(1)))
			((I3) (\NlwInverterSignal_Home15ctrl_MC.CE/IN3 \))
			((I4) (N_PZ_931))
			((I5) (U2_ADDR_reg(2)))
			((I6) (U2_ADDR_reg(3)))
			((O) (\Home15ctrl_MC.CE \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \INT_MC.Q_1358 \ 0 13983 (_entity .  X_BUF)
		(_port
			((I) (\INT_MC.Q_tsimrenamed_net_ \))
			((O) (\INT_MC.Q \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \INT_MC.Q_tsimrenamed_net__1359 \ 0 13987 (_entity .  X_BUF)
		(_port
			((I) (\INT_MC.D \))
			((O) (\INT_MC.Q_tsimrenamed_net_ \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \INT_MC.D_1360 \ 0 13991 (_entity .  X_XOR2)
		(_port
			((I0) (\INT_MC.D1 \))
			((I1) (\INT_MC.D2 \))
			((O) (\INT_MC.D \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \INT_MC.D1_1361 \ 0 13996 (_entity .  X_ZERO)
		(_port
			((O) (\INT_MC.D1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \INT_MC.D2_PT_0_1362 \ 0 13999 (_entity .  X_AND2)
		(_port
			((I0) (NET2528))
			((I1) (\U3/DCORIE \(1)))
			((O) (\INT_MC.D2_PT_0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \INT_MC.D2_PT_1_1363 \ 0 14004 (_entity .  X_AND2)
		(_port
			((I0) (NET2482))
			((I1) (\U3/DCORIE \(2)))
			((O) (\INT_MC.D2_PT_1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \INT_MC.D2_PT_2_1364 \ 0 14009 (_entity .  X_AND2)
		(_port
			((I0) (NET2493))
			((I1) (\U3/DCORIE \(3)))
			((O) (\INT_MC.D2_PT_2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \INT_MC.D2_PT_3_1365 \ 0 14014 (_entity .  X_AND2)
		(_port
			((I0) (NET2501))
			((I1) (\U3/DCORIE \(5)))
			((O) (\INT_MC.D2_PT_3 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \INT_MC.D2_PT_4_1366 \ 0 14019 (_entity .  X_AND2)
		(_port
			((I0) (\INTbus_II/UIM \))
			((I1) (\U3/DCORIE \(0)))
			((O) (\INT_MC.D2_PT_4 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \INT_MC.D2_PT_5_1367 \ 0 14024 (_entity .  X_AND2)
		(_port
			((I0) (NET2575))
			((I1) (\U3/DCORIE \(4)))
			((O) (\INT_MC.D2_PT_5 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \INT_MC.D2_PT_6_1368 \ 0 14029 (_entity .  X_AND2)
		(_port
			((I0) (NET2512))
			((I1) (\U3/DCORIE \(6)))
			((O) (\INT_MC.D2_PT_6 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \INT_MC.D2_PT_7_1369 \ 0 14034 (_entity .  X_AND7)
		(_port
			((I0) (\NlwInverterSignal_INT_MC.D2_PT_7/IN0 \))
			((I1) (\NlwInverterSignal_INT_MC.D2_PT_7/IN1 \))
			((I2) (\NlwInverterSignal_INT_MC.D2_PT_7/IN2 \))
			((I3) (\NlwInverterSignal_INT_MC.D2_PT_7/IN3 \))
			((I4) (\NlwInverterSignal_INT_MC.D2_PT_7/IN4 \))
			((I5) (\NlwInverterSignal_INT_MC.D2_PT_7/IN5 \))
			((I6) (\U3/DCORIE \(7)))
			((O) (\INT_MC.D2_PT_7 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \INT_MC.D2_1370 \ 0 14044 (_entity .  X_OR8)
		(_port
			((I0) (\INT_MC.D2_PT_0 \))
			((I1) (\INT_MC.D2_PT_1 \))
			((I2) (\INT_MC.D2_PT_2 \))
			((I3) (\INT_MC.D2_PT_3 \))
			((I4) (\INT_MC.D2_PT_4 \))
			((I5) (\INT_MC.D2_PT_5 \))
			((I6) (\INT_MC.D2_PT_6 \))
			((I7) (\INT_MC.D2_PT_7 \))
			((O) (\INT_MC.D2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U3/DCORIE<0> \ 0 14055 (_entity .  X_BUF)
		(_port
			((I) (\U3/DCORIE<0>_MC.Q \))
			((O) (\U3/DCORIE \(0)))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U3/DCORIE<0>_MC_tsimcreated_xor__1371 \ 0 14059 (_entity .  X_XOR2)
		(_port
			((I0) (\U3/DCORIE<0>_MC.D \))
			((I1) (\U3/DCORIE<0>_MC.Q \))
			((O) (\U3/DCORIE<0>_MC_tsimcreated_xor_ \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U3/DCORIE<0>_MC.REG \ 0 14064 (_entity .  X_FF)
		(_port
			((I) (\U3/DCORIE<0>_MC_tsimcreated_xor_ \))
			((CE) (Vcc))
			((CLK) (\Mclk_II/FCLK \))
			((SET) (Gnd))
			((RST) (PRLD))
			((O) (\U3/DCORIE<0>_MC.Q \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U3/DCORIE<0>_MC.D_1372 \ 0 14072 (_entity .  X_XOR2)
		(_port
			((I0) (\U3/DCORIE<0>_MC.D1 \))
			((I1) (\U3/DCORIE<0>_MC.D2 \))
			((O) (\U3/DCORIE<0>_MC.D \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U3/DCORIE<0>_MC.D1_1373 \ 0 14077 (_entity .  X_ZERO)
		(_port
			((O) (\U3/DCORIE<0>_MC.D1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U3/DCORIE<0>_MC.D2_PT_0_1374 \ 0 14080 (_entity .  X_AND2)
		(_port
			((I0) (\Reset_II/UIM \))
			((I1) (\U3/DCORIE \(0)))
			((O) (\U3/DCORIE<0>_MC.D2_PT_0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U3/DCORIE<0>_MC.D2_PT_1_1375 \ 0 14085 (_entity .  X_AND16)
		(_port
			((I0) (\NlwInverterSignal_U3/DCORIE<0>_MC.D2_PT_1/IN0 \))
			((I1) (\RD_II/UIM \))
			((I2) (\NlwInverterSignal_U3/DCORIE<0>_MC.D2_PT_1/IN2 \))
			((I3) (U2_ADDR_reg(0)))
			((I4) (N_PZ_931))
			((I5) (\NlwInverterSignal_U3/DCORIE<0>_MC.D2_PT_1/IN5 \))
			((I6) (\NlwInverterSignal_U3/DCORIE<0>_MC.D2_PT_1/IN6 \))
			((I7) (\NlwInverterSignal_U3/DCORIE<0>_MC.D2_PT_1/IN7 \))
			((I8) (\U3/DCORIE \(0)))
			((I9) (Vcc))
			((I10) (Vcc))
			((I11) (Vcc))
			((I12) (Vcc))
			((I13) (Vcc))
			((I14) (Vcc))
			((I15) (Vcc))
			((O) (\U3/DCORIE<0>_MC.D2_PT_1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U3/DCORIE<0>_MC.D2_PT_2_1376 \ 0 14104 (_entity .  X_AND16)
		(_port
			((I0) (\NlwInverterSignal_U3/DCORIE<0>_MC.D2_PT_2/IN0 \))
			((I1) (\RD_II/UIM \))
			((I2) (\NlwInverterSignal_U3/DCORIE<0>_MC.D2_PT_2/IN2 \))
			((I3) (U2_ADDR_reg(0)))
			((I4) (N_PZ_931))
			((I5) (\NlwInverterSignal_U3/DCORIE<0>_MC.D2_PT_2/IN5 \))
			((I6) (\NlwInverterSignal_U3/DCORIE<0>_MC.D2_PT_2/IN6 \))
			((I7) (\NlwInverterSignal_U3/DCORIE<0>_MC.D2_PT_2/IN7 \))
			((I8) (\AD<0>_II/UIM \))
			((I9) (\NlwInverterSignal_U3/DCORIE<0>_MC.D2_PT_2/IN9 \))
			((I10) (Vcc))
			((I11) (Vcc))
			((I12) (Vcc))
			((I13) (Vcc))
			((I14) (Vcc))
			((I15) (Vcc))
			((O) (\U3/DCORIE<0>_MC.D2_PT_2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U3/DCORIE<0>_MC.D2_1377 \ 0 14123 (_entity .  X_OR3)
		(_port
			((I0) (\U3/DCORIE<0>_MC.D2_PT_0 \))
			((I1) (\U3/DCORIE<0>_MC.D2_PT_1 \))
			((I2) (\U3/DCORIE<0>_MC.D2_PT_2 \))
			((O) (\U3/DCORIE<0>_MC.D2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U3/DCORIE<1> \ 0 14129 (_entity .  X_BUF)
		(_port
			((I) (\U3/DCORIE<1>_MC.Q \))
			((O) (\U3/DCORIE \(1)))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U3/DCORIE<1>_MC_tsimcreated_xor__1378 \ 0 14133 (_entity .  X_XOR2)
		(_port
			((I0) (\U3/DCORIE<1>_MC.D \))
			((I1) (\U3/DCORIE<1>_MC.Q \))
			((O) (\U3/DCORIE<1>_MC_tsimcreated_xor_ \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U3/DCORIE<1>_MC.REG \ 0 14138 (_entity .  X_FF)
		(_port
			((I) (\U3/DCORIE<1>_MC_tsimcreated_xor_ \))
			((CE) (Vcc))
			((CLK) (\Mclk_II/FCLK \))
			((SET) (Gnd))
			((RST) (PRLD))
			((O) (\U3/DCORIE<1>_MC.Q \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U3/DCORIE<1>_MC.D_1379 \ 0 14146 (_entity .  X_XOR2)
		(_port
			((I0) (\U3/DCORIE<1>_MC.D1 \))
			((I1) (\U3/DCORIE<1>_MC.D2 \))
			((O) (\U3/DCORIE<1>_MC.D \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U3/DCORIE<1>_MC.D1_1380 \ 0 14151 (_entity .  X_ZERO)
		(_port
			((O) (\U3/DCORIE<1>_MC.D1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U3/DCORIE<1>_MC.D2_PT_0_1381 \ 0 14154 (_entity .  X_AND2)
		(_port
			((I0) (\Reset_II/UIM \))
			((I1) (\U3/DCORIE \(1)))
			((O) (\U3/DCORIE<1>_MC.D2_PT_0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U3/DCORIE<1>_MC.D2_PT_1_1382 \ 0 14159 (_entity .  X_AND16)
		(_port
			((I0) (\NlwInverterSignal_U3/DCORIE<1>_MC.D2_PT_1/IN0 \))
			((I1) (\RD_II/UIM \))
			((I2) (\NlwInverterSignal_U3/DCORIE<1>_MC.D2_PT_1/IN2 \))
			((I3) (U2_ADDR_reg(0)))
			((I4) (N_PZ_931))
			((I5) (\NlwInverterSignal_U3/DCORIE<1>_MC.D2_PT_1/IN5 \))
			((I6) (\NlwInverterSignal_U3/DCORIE<1>_MC.D2_PT_1/IN6 \))
			((I7) (\NlwInverterSignal_U3/DCORIE<1>_MC.D2_PT_1/IN7 \))
			((I8) (\U3/DCORIE \(1)))
			((I9) (Vcc))
			((I10) (Vcc))
			((I11) (Vcc))
			((I12) (Vcc))
			((I13) (Vcc))
			((I14) (Vcc))
			((I15) (Vcc))
			((O) (\U3/DCORIE<1>_MC.D2_PT_1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U3/DCORIE<1>_MC.D2_PT_2_1383 \ 0 14178 (_entity .  X_AND16)
		(_port
			((I0) (\NlwInverterSignal_U3/DCORIE<1>_MC.D2_PT_2/IN0 \))
			((I1) (\RD_II/UIM \))
			((I2) (\NlwInverterSignal_U3/DCORIE<1>_MC.D2_PT_2/IN2 \))
			((I3) (U2_ADDR_reg(0)))
			((I4) (N_PZ_931))
			((I5) (\NlwInverterSignal_U3/DCORIE<1>_MC.D2_PT_2/IN5 \))
			((I6) (\NlwInverterSignal_U3/DCORIE<1>_MC.D2_PT_2/IN6 \))
			((I7) (\AD<1>_II/UIM \))
			((I8) (\NlwInverterSignal_U3/DCORIE<1>_MC.D2_PT_2/IN8 \))
			((I9) (\NlwInverterSignal_U3/DCORIE<1>_MC.D2_PT_2/IN9 \))
			((I10) (Vcc))
			((I11) (Vcc))
			((I12) (Vcc))
			((I13) (Vcc))
			((I14) (Vcc))
			((I15) (Vcc))
			((O) (\U3/DCORIE<1>_MC.D2_PT_2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U3/DCORIE<1>_MC.D2_1384 \ 0 14197 (_entity .  X_OR3)
		(_port
			((I0) (\U3/DCORIE<1>_MC.D2_PT_0 \))
			((I1) (\U3/DCORIE<1>_MC.D2_PT_1 \))
			((I2) (\U3/DCORIE<1>_MC.D2_PT_2 \))
			((O) (\U3/DCORIE<1>_MC.D2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U3/DCORIE<2> \ 0 14203 (_entity .  X_BUF)
		(_port
			((I) (\U3/DCORIE<2>_MC.Q \))
			((O) (\U3/DCORIE \(2)))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U3/DCORIE<2>_MC_tsimcreated_xor__1385 \ 0 14207 (_entity .  X_XOR2)
		(_port
			((I0) (\U3/DCORIE<2>_MC.D \))
			((I1) (\U3/DCORIE<2>_MC.Q \))
			((O) (\U3/DCORIE<2>_MC_tsimcreated_xor_ \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U3/DCORIE<2>_MC.REG \ 0 14212 (_entity .  X_FF)
		(_port
			((I) (\U3/DCORIE<2>_MC_tsimcreated_xor_ \))
			((CE) (Vcc))
			((CLK) (\Mclk_II/FCLK \))
			((SET) (Gnd))
			((RST) (PRLD))
			((O) (\U3/DCORIE<2>_MC.Q \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U3/DCORIE<2>_MC.D_1386 \ 0 14220 (_entity .  X_XOR2)
		(_port
			((I0) (\U3/DCORIE<2>_MC.D1 \))
			((I1) (\U3/DCORIE<2>_MC.D2 \))
			((O) (\U3/DCORIE<2>_MC.D \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U3/DCORIE<2>_MC.D1_1387 \ 0 14225 (_entity .  X_ZERO)
		(_port
			((O) (\U3/DCORIE<2>_MC.D1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U3/DCORIE<2>_MC.D2_PT_0_1388 \ 0 14228 (_entity .  X_AND2)
		(_port
			((I0) (\Reset_II/UIM \))
			((I1) (\U3/DCORIE \(2)))
			((O) (\U3/DCORIE<2>_MC.D2_PT_0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U3/DCORIE<2>_MC.D2_PT_1_1389 \ 0 14233 (_entity .  X_AND16)
		(_port
			((I0) (\NlwInverterSignal_U3/DCORIE<2>_MC.D2_PT_1/IN0 \))
			((I1) (\RD_II/UIM \))
			((I2) (\NlwInverterSignal_U3/DCORIE<2>_MC.D2_PT_1/IN2 \))
			((I3) (U2_ADDR_reg(0)))
			((I4) (N_PZ_931))
			((I5) (\NlwInverterSignal_U3/DCORIE<2>_MC.D2_PT_1/IN5 \))
			((I6) (\NlwInverterSignal_U3/DCORIE<2>_MC.D2_PT_1/IN6 \))
			((I7) (\NlwInverterSignal_U3/DCORIE<2>_MC.D2_PT_1/IN7 \))
			((I8) (\U3/DCORIE \(2)))
			((I9) (Vcc))
			((I10) (Vcc))
			((I11) (Vcc))
			((I12) (Vcc))
			((I13) (Vcc))
			((I14) (Vcc))
			((I15) (Vcc))
			((O) (\U3/DCORIE<2>_MC.D2_PT_1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U3/DCORIE<2>_MC.D2_PT_2_1390 \ 0 14252 (_entity .  X_AND16)
		(_port
			((I0) (\NlwInverterSignal_U3/DCORIE<2>_MC.D2_PT_2/IN0 \))
			((I1) (\RD_II/UIM \))
			((I2) (\NlwInverterSignal_U3/DCORIE<2>_MC.D2_PT_2/IN2 \))
			((I3) (U2_ADDR_reg(0)))
			((I4) (N_PZ_931))
			((I5) (\NlwInverterSignal_U3/DCORIE<2>_MC.D2_PT_2/IN5 \))
			((I6) (\NlwInverterSignal_U3/DCORIE<2>_MC.D2_PT_2/IN6 \))
			((I7) (\NlwInverterSignal_U3/DCORIE<2>_MC.D2_PT_2/IN7 \))
			((I8) (\AD<2>_II/UIM \))
			((I9) (\NlwInverterSignal_U3/DCORIE<2>_MC.D2_PT_2/IN9 \))
			((I10) (Vcc))
			((I11) (Vcc))
			((I12) (Vcc))
			((I13) (Vcc))
			((I14) (Vcc))
			((I15) (Vcc))
			((O) (\U3/DCORIE<2>_MC.D2_PT_2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U3/DCORIE<2>_MC.D2_1391 \ 0 14271 (_entity .  X_OR3)
		(_port
			((I0) (\U3/DCORIE<2>_MC.D2_PT_0 \))
			((I1) (\U3/DCORIE<2>_MC.D2_PT_1 \))
			((I2) (\U3/DCORIE<2>_MC.D2_PT_2 \))
			((O) (\U3/DCORIE<2>_MC.D2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U3/DCORIE<3> \ 0 14277 (_entity .  X_BUF)
		(_port
			((I) (\U3/DCORIE<3>_MC.Q \))
			((O) (\U3/DCORIE \(3)))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U3/DCORIE<3>_MC_tsimcreated_xor__1392 \ 0 14281 (_entity .  X_XOR2)
		(_port
			((I0) (\U3/DCORIE<3>_MC.D \))
			((I1) (\U3/DCORIE<3>_MC.Q \))
			((O) (\U3/DCORIE<3>_MC_tsimcreated_xor_ \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U3/DCORIE<3>_MC.REG \ 0 14286 (_entity .  X_FF)
		(_port
			((I) (\U3/DCORIE<3>_MC_tsimcreated_xor_ \))
			((CE) (Vcc))
			((CLK) (\Mclk_II/FCLK \))
			((SET) (Gnd))
			((RST) (PRLD))
			((O) (\U3/DCORIE<3>_MC.Q \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U3/DCORIE<3>_MC.D_1393 \ 0 14294 (_entity .  X_XOR2)
		(_port
			((I0) (\U3/DCORIE<3>_MC.D1 \))
			((I1) (\U3/DCORIE<3>_MC.D2 \))
			((O) (\U3/DCORIE<3>_MC.D \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U3/DCORIE<3>_MC.D1_1394 \ 0 14299 (_entity .  X_ZERO)
		(_port
			((O) (\U3/DCORIE<3>_MC.D1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U3/DCORIE<3>_MC.D2_PT_0_1395 \ 0 14302 (_entity .  X_AND2)
		(_port
			((I0) (\Reset_II/UIM \))
			((I1) (\U3/DCORIE \(3)))
			((O) (\U3/DCORIE<3>_MC.D2_PT_0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U3/DCORIE<3>_MC.D2_PT_1_1396 \ 0 14307 (_entity .  X_AND16)
		(_port
			((I0) (\NlwInverterSignal_U3/DCORIE<3>_MC.D2_PT_1/IN0 \))
			((I1) (\RD_II/UIM \))
			((I2) (\NlwInverterSignal_U3/DCORIE<3>_MC.D2_PT_1/IN2 \))
			((I3) (U2_ADDR_reg(0)))
			((I4) (N_PZ_931))
			((I5) (\NlwInverterSignal_U3/DCORIE<3>_MC.D2_PT_1/IN5 \))
			((I6) (\NlwInverterSignal_U3/DCORIE<3>_MC.D2_PT_1/IN6 \))
			((I7) (\NlwInverterSignal_U3/DCORIE<3>_MC.D2_PT_1/IN7 \))
			((I8) (\U3/DCORIE \(3)))
			((I9) (Vcc))
			((I10) (Vcc))
			((I11) (Vcc))
			((I12) (Vcc))
			((I13) (Vcc))
			((I14) (Vcc))
			((I15) (Vcc))
			((O) (\U3/DCORIE<3>_MC.D2_PT_1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U3/DCORIE<3>_MC.D2_PT_2_1397 \ 0 14326 (_entity .  X_AND16)
		(_port
			((I0) (\NlwInverterSignal_U3/DCORIE<3>_MC.D2_PT_2/IN0 \))
			((I1) (\RD_II/UIM \))
			((I2) (\NlwInverterSignal_U3/DCORIE<3>_MC.D2_PT_2/IN2 \))
			((I3) (U2_ADDR_reg(0)))
			((I4) (N_PZ_931))
			((I5) (\NlwInverterSignal_U3/DCORIE<3>_MC.D2_PT_2/IN5 \))
			((I6) (\NlwInverterSignal_U3/DCORIE<3>_MC.D2_PT_2/IN6 \))
			((I7) (\NlwInverterSignal_U3/DCORIE<3>_MC.D2_PT_2/IN7 \))
			((I8) (\AD<3>_II/UIM \))
			((I9) (\NlwInverterSignal_U3/DCORIE<3>_MC.D2_PT_2/IN9 \))
			((I10) (Vcc))
			((I11) (Vcc))
			((I12) (Vcc))
			((I13) (Vcc))
			((I14) (Vcc))
			((I15) (Vcc))
			((O) (\U3/DCORIE<3>_MC.D2_PT_2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U3/DCORIE<3>_MC.D2_1398 \ 0 14345 (_entity .  X_OR3)
		(_port
			((I0) (\U3/DCORIE<3>_MC.D2_PT_0 \))
			((I1) (\U3/DCORIE<3>_MC.D2_PT_1 \))
			((I2) (\U3/DCORIE<3>_MC.D2_PT_2 \))
			((O) (\U3/DCORIE<3>_MC.D2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation NET2575_1399 0 14351 (_entity .  X_BUF)
		(_port
			((I) (\NET2575_MC.Q \))
			((O) (NET2575))
		)
		(_strength strong0 strong1)
	)
	(_instantiation NET2575_MC_tsimcreated_xor__1400 0 14355 (_entity .  X_XOR2)
		(_port
			((I0) (\NET2575_MC.D \))
			((I1) (\NET2575_MC.Q \))
			((O) (NET2575_MC_tsimcreated_xor_))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NET2575_MC.REG \ 0 14360 (_entity .  X_FF)
		(_port
			((I) (NET2575_MC_tsimcreated_xor_))
			((CE) (Vcc))
			((CLK) (\Mclk_II/FCLK \))
			((SET) (Gnd))
			((RST) (PRLD))
			((O) (\NET2575_MC.Q \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NET2575_MC.D_1401 \ 0 14368 (_entity .  X_XOR2)
		(_port
			((I0) (\NET2575_MC.D1 \))
			((I1) (\NET2575_MC.D2 \))
			((O) (\NET2575_MC.D \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NET2575_MC.D1_1402 \ 0 14373 (_entity .  X_ZERO)
		(_port
			((O) (\NET2575_MC.D1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NET2575_MC.D2_PT_0_1403 \ 0 14376 (_entity .  X_AND2)
		(_port
			((I0) (\Reset_II/UIM \))
			((I1) (NET2575))
			((O) (\NET2575_MC.D2_PT_0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NET2575_MC.D2_PT_1_1404 \ 0 14381 (_entity .  X_AND3)
		(_port
			((I0) (\NlwInverterSignal_NET2575_MC.D2_PT_1/IN0 \))
			((I1) (N_PZ_1186))
			((I2) (\NlwInverterSignal_NET2575_MC.D2_PT_1/IN2 \))
			((O) (\NET2575_MC.D2_PT_1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NET2575_MC.D2_PT_2_1405 \ 0 14387 (_entity .  X_AND4)
		(_port
			((I0) (\NlwInverterSignal_NET2575_MC.D2_PT_2/IN0 \))
			((I1) (\DIR0_II/UIM \))
			((I2) (\NlwInverterSignal_NET2575_MC.D2_PT_2/IN2 \))
			((I3) (\NlwInverterSignal_NET2575_MC.D2_PT_2/IN3 \))
			((O) (\NET2575_MC.D2_PT_2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NET2575_MC.D2_PT_3_1406 \ 0 14394 (_entity .  X_AND4)
		(_port
			((I0) (\NlwInverterSignal_NET2575_MC.D2_PT_3/IN0 \))
			((I1) (\NlwInverterSignal_NET2575_MC.D2_PT_3/IN1 \))
			((I2) (\NlwInverterSignal_NET2575_MC.D2_PT_3/IN2 \))
			((I3) (\NlwInverterSignal_NET2575_MC.D2_PT_3/IN3 \))
			((O) (\NET2575_MC.D2_PT_3 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NET2575_MC.D2_PT_4_1407 \ 0 14401 (_entity .  X_AND16)
		(_port
			((I0) (\NlwInverterSignal_NET2575_MC.D2_PT_4/IN0 \))
			((I1) (\RD_II/UIM \))
			((I2) (U2_ADDR_reg(1)))
			((I3) (\NlwInverterSignal_NET2575_MC.D2_PT_4/IN3 \))
			((I4) (N_PZ_931))
			((I5) (\NlwInverterSignal_NET2575_MC.D2_PT_4/IN5 \))
			((I6) (\NlwInverterSignal_NET2575_MC.D2_PT_4/IN6 \))
			((I7) (\NlwInverterSignal_NET2575_MC.D2_PT_4/IN7 \))
			((I8) (\AD<4>_II/UIM \))
			((I9) (\NlwInverterSignal_NET2575_MC.D2_PT_4/IN9 \))
			((I10) (Vcc))
			((I11) (Vcc))
			((I12) (Vcc))
			((I13) (Vcc))
			((I14) (Vcc))
			((I15) (Vcc))
			((O) (\NET2575_MC.D2_PT_4 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NET2575_MC.D2_PT_5_1408 \ 0 14420 (_entity .  X_AND16)
		(_port
			((I0) (\NlwInverterSignal_NET2575_MC.D2_PT_5/IN0 \))
			((I1) (\RD_II/UIM \))
			((I2) (U2_ADDR_reg(1)))
			((I3) (\NlwInverterSignal_NET2575_MC.D2_PT_5/IN3 \))
			((I4) (N_PZ_931))
			((I5) (\NlwInverterSignal_NET2575_MC.D2_PT_5/IN5 \))
			((I6) (\NlwInverterSignal_NET2575_MC.D2_PT_5/IN6 \))
			((I7) (\NlwInverterSignal_NET2575_MC.D2_PT_5/IN7 \))
			((I8) (\NlwInverterSignal_NET2575_MC.D2_PT_5/IN8 \))
			((I9) (\DIR0_II/UIM \))
			((I10) (\FLS0_II/UIM \))
			((I11) (NET2575))
			((I12) (Vcc))
			((I13) (Vcc))
			((I14) (Vcc))
			((I15) (Vcc))
			((O) (\NET2575_MC.D2_PT_5 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NET2575_MC.D2_PT_6_1409 \ 0 14439 (_entity .  X_AND16)
		(_port
			((I0) (\NlwInverterSignal_NET2575_MC.D2_PT_6/IN0 \))
			((I1) (\RD_II/UIM \))
			((I2) (U2_ADDR_reg(1)))
			((I3) (\NlwInverterSignal_NET2575_MC.D2_PT_6/IN3 \))
			((I4) (N_PZ_931))
			((I5) (\NlwInverterSignal_NET2575_MC.D2_PT_6/IN5 \))
			((I6) (\NlwInverterSignal_NET2575_MC.D2_PT_6/IN6 \))
			((I7) (\NlwInverterSignal_NET2575_MC.D2_PT_6/IN7 \))
			((I8) (\NlwInverterSignal_NET2575_MC.D2_PT_6/IN8 \))
			((I9) (\NlwInverterSignal_NET2575_MC.D2_PT_6/IN9 \))
			((I10) (NET2575))
			((I11) (\RLS0_II/UIM \))
			((I12) (Vcc))
			((I13) (Vcc))
			((I14) (Vcc))
			((I15) (Vcc))
			((O) (\NET2575_MC.D2_PT_6 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NET2575_MC.D2_1410 \ 0 14458 (_entity .  X_OR7)
		(_port
			((I0) (\NET2575_MC.D2_PT_0 \))
			((I1) (\NET2575_MC.D2_PT_1 \))
			((I2) (\NET2575_MC.D2_PT_2 \))
			((I3) (\NET2575_MC.D2_PT_3 \))
			((I4) (\NET2575_MC.D2_PT_4 \))
			((I5) (\NET2575_MC.D2_PT_5 \))
			((I6) (\NET2575_MC.D2_PT_6 \))
			((O) (\NET2575_MC.D2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U3/DCORIE<4> \ 0 14468 (_entity .  X_BUF)
		(_port
			((I) (\U3/DCORIE<4>_MC.Q \))
			((O) (\U3/DCORIE \(4)))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U3/DCORIE<4>_MC_tsimcreated_xor__1411 \ 0 14472 (_entity .  X_XOR2)
		(_port
			((I0) (\U3/DCORIE<4>_MC.D \))
			((I1) (\U3/DCORIE<4>_MC.Q \))
			((O) (\U3/DCORIE<4>_MC_tsimcreated_xor_ \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U3/DCORIE<4>_MC.REG \ 0 14477 (_entity .  X_FF)
		(_port
			((I) (\U3/DCORIE<4>_MC_tsimcreated_xor_ \))
			((CE) (Vcc))
			((CLK) (\Mclk_II/FCLK \))
			((SET) (Gnd))
			((RST) (PRLD))
			((O) (\U3/DCORIE<4>_MC.Q \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U3/DCORIE<4>_MC.D_1412 \ 0 14485 (_entity .  X_XOR2)
		(_port
			((I0) (\U3/DCORIE<4>_MC.D1 \))
			((I1) (\U3/DCORIE<4>_MC.D2 \))
			((O) (\U3/DCORIE<4>_MC.D \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U3/DCORIE<4>_MC.D1_1413 \ 0 14490 (_entity .  X_ZERO)
		(_port
			((O) (\U3/DCORIE<4>_MC.D1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U3/DCORIE<4>_MC.D2_PT_0_1414 \ 0 14493 (_entity .  X_AND2)
		(_port
			((I0) (\Reset_II/UIM \))
			((I1) (\U3/DCORIE \(4)))
			((O) (\U3/DCORIE<4>_MC.D2_PT_0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U3/DCORIE<4>_MC.D2_PT_1_1415 \ 0 14498 (_entity .  X_AND16)
		(_port
			((I0) (\NlwInverterSignal_U3/DCORIE<4>_MC.D2_PT_1/IN0 \))
			((I1) (\RD_II/UIM \))
			((I2) (\NlwInverterSignal_U3/DCORIE<4>_MC.D2_PT_1/IN2 \))
			((I3) (U2_ADDR_reg(0)))
			((I4) (N_PZ_931))
			((I5) (\NlwInverterSignal_U3/DCORIE<4>_MC.D2_PT_1/IN5 \))
			((I6) (\NlwInverterSignal_U3/DCORIE<4>_MC.D2_PT_1/IN6 \))
			((I7) (\NlwInverterSignal_U3/DCORIE<4>_MC.D2_PT_1/IN7 \))
			((I8) (\U3/DCORIE \(4)))
			((I9) (Vcc))
			((I10) (Vcc))
			((I11) (Vcc))
			((I12) (Vcc))
			((I13) (Vcc))
			((I14) (Vcc))
			((I15) (Vcc))
			((O) (\U3/DCORIE<4>_MC.D2_PT_1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U3/DCORIE<4>_MC.D2_PT_2_1416 \ 0 14517 (_entity .  X_AND16)
		(_port
			((I0) (\NlwInverterSignal_U3/DCORIE<4>_MC.D2_PT_2/IN0 \))
			((I1) (\RD_II/UIM \))
			((I2) (\NlwInverterSignal_U3/DCORIE<4>_MC.D2_PT_2/IN2 \))
			((I3) (U2_ADDR_reg(0)))
			((I4) (N_PZ_931))
			((I5) (\NlwInverterSignal_U3/DCORIE<4>_MC.D2_PT_2/IN5 \))
			((I6) (\NlwInverterSignal_U3/DCORIE<4>_MC.D2_PT_2/IN6 \))
			((I7) (\NlwInverterSignal_U3/DCORIE<4>_MC.D2_PT_2/IN7 \))
			((I8) (\AD<4>_II/UIM \))
			((I9) (\NlwInverterSignal_U3/DCORIE<4>_MC.D2_PT_2/IN9 \))
			((I10) (Vcc))
			((I11) (Vcc))
			((I12) (Vcc))
			((I13) (Vcc))
			((I14) (Vcc))
			((I15) (Vcc))
			((O) (\U3/DCORIE<4>_MC.D2_PT_2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U3/DCORIE<4>_MC.D2_1417 \ 0 14536 (_entity .  X_OR3)
		(_port
			((I0) (\U3/DCORIE<4>_MC.D2_PT_0 \))
			((I1) (\U3/DCORIE<4>_MC.D2_PT_1 \))
			((I2) (\U3/DCORIE<4>_MC.D2_PT_2 \))
			((O) (\U3/DCORIE<4>_MC.D2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U3/DCORIE<5> \ 0 14542 (_entity .  X_BUF)
		(_port
			((I) (\U3/DCORIE<5>_MC.Q \))
			((O) (\U3/DCORIE \(5)))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U3/DCORIE<5>_MC_tsimcreated_xor__1418 \ 0 14546 (_entity .  X_XOR2)
		(_port
			((I0) (\U3/DCORIE<5>_MC.D \))
			((I1) (\U3/DCORIE<5>_MC.Q \))
			((O) (\U3/DCORIE<5>_MC_tsimcreated_xor_ \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U3/DCORIE<5>_MC.REG \ 0 14551 (_entity .  X_FF)
		(_port
			((I) (\U3/DCORIE<5>_MC_tsimcreated_xor_ \))
			((CE) (Vcc))
			((CLK) (\Mclk_II/FCLK \))
			((SET) (Gnd))
			((RST) (PRLD))
			((O) (\U3/DCORIE<5>_MC.Q \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U3/DCORIE<5>_MC.D_1419 \ 0 14559 (_entity .  X_XOR2)
		(_port
			((I0) (\U3/DCORIE<5>_MC.D1 \))
			((I1) (\U3/DCORIE<5>_MC.D2 \))
			((O) (\U3/DCORIE<5>_MC.D \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U3/DCORIE<5>_MC.D1_1420 \ 0 14564 (_entity .  X_ZERO)
		(_port
			((O) (\U3/DCORIE<5>_MC.D1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U3/DCORIE<5>_MC.D2_PT_0_1421 \ 0 14567 (_entity .  X_AND2)
		(_port
			((I0) (\Reset_II/UIM \))
			((I1) (\U3/DCORIE \(5)))
			((O) (\U3/DCORIE<5>_MC.D2_PT_0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U3/DCORIE<5>_MC.D2_PT_1_1422 \ 0 14572 (_entity .  X_AND16)
		(_port
			((I0) (\NlwInverterSignal_U3/DCORIE<5>_MC.D2_PT_1/IN0 \))
			((I1) (\RD_II/UIM \))
			((I2) (\NlwInverterSignal_U3/DCORIE<5>_MC.D2_PT_1/IN2 \))
			((I3) (U2_ADDR_reg(0)))
			((I4) (N_PZ_931))
			((I5) (\NlwInverterSignal_U3/DCORIE<5>_MC.D2_PT_1/IN5 \))
			((I6) (\NlwInverterSignal_U3/DCORIE<5>_MC.D2_PT_1/IN6 \))
			((I7) (\NlwInverterSignal_U3/DCORIE<5>_MC.D2_PT_1/IN7 \))
			((I8) (\U3/DCORIE \(5)))
			((I9) (Vcc))
			((I10) (Vcc))
			((I11) (Vcc))
			((I12) (Vcc))
			((I13) (Vcc))
			((I14) (Vcc))
			((I15) (Vcc))
			((O) (\U3/DCORIE<5>_MC.D2_PT_1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U3/DCORIE<5>_MC.D2_PT_2_1423 \ 0 14591 (_entity .  X_AND16)
		(_port
			((I0) (\NlwInverterSignal_U3/DCORIE<5>_MC.D2_PT_2/IN0 \))
			((I1) (\RD_II/UIM \))
			((I2) (\NlwInverterSignal_U3/DCORIE<5>_MC.D2_PT_2/IN2 \))
			((I3) (U2_ADDR_reg(0)))
			((I4) (N_PZ_931))
			((I5) (\NlwInverterSignal_U3/DCORIE<5>_MC.D2_PT_2/IN5 \))
			((I6) (\NlwInverterSignal_U3/DCORIE<5>_MC.D2_PT_2/IN6 \))
			((I7) (\NlwInverterSignal_U3/DCORIE<5>_MC.D2_PT_2/IN7 \))
			((I8) (\AD<5>_II/UIM \))
			((I9) (\NlwInverterSignal_U3/DCORIE<5>_MC.D2_PT_2/IN9 \))
			((I10) (Vcc))
			((I11) (Vcc))
			((I12) (Vcc))
			((I13) (Vcc))
			((I14) (Vcc))
			((I15) (Vcc))
			((O) (\U3/DCORIE<5>_MC.D2_PT_2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U3/DCORIE<5>_MC.D2_1424 \ 0 14610 (_entity .  X_OR3)
		(_port
			((I0) (\U3/DCORIE<5>_MC.D2_PT_0 \))
			((I1) (\U3/DCORIE<5>_MC.D2_PT_1 \))
			((I2) (\U3/DCORIE<5>_MC.D2_PT_2 \))
			((O) (\U3/DCORIE<5>_MC.D2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation NET2512_1425 0 14616 (_entity .  X_BUF)
		(_port
			((I) (\NET2512_MC.Q \))
			((O) (NET2512))
		)
		(_strength strong0 strong1)
	)
	(_instantiation NET2512_MC_tsimcreated_xor__1426 0 14620 (_entity .  X_XOR2)
		(_port
			((I0) (\NET2512_MC.D \))
			((I1) (\NET2512_MC.Q \))
			((O) (NET2512_MC_tsimcreated_xor_))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NET2512_MC.REG \ 0 14625 (_entity .  X_FF)
		(_port
			((I) (NET2512_MC_tsimcreated_xor_))
			((CE) (Vcc))
			((CLK) (\NET2512_MC.REG_tsimcreated_inv_Mclk_II/FCLK \))
			((SET) (Gnd))
			((RST) (PRLD))
			((O) (\NET2512_MC.Q \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NET2512_MC.REG_tsimcreated_inv_Mclk_II/FCLK_1427 \ 0 14633 (_entity .  X_INV)
		(_port
			((I) (\Mclk_II/FCLK \))
			((O) (\NET2512_MC.REG_tsimcreated_inv_Mclk_II/FCLK \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NET2512_MC.D_1428 \ 0 14637 (_entity .  X_XOR2)
		(_port
			((I0) (\NET2512_MC.D1 \))
			((I1) (\NET2512_MC.D2 \))
			((O) (\NET2512_MC.D \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NET2512_MC.D1_1429 \ 0 14642 (_entity .  X_ZERO)
		(_port
			((O) (\NET2512_MC.D1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NET2512_MC.D2_PT_0_1430 \ 0 14645 (_entity .  X_AND5)
		(_port
			((I0) (\NlwInverterSignal_NET2512_MC.D2_PT_0/IN0 \))
			((I1) (\GP_Motor1_0_II/UIM \))
			((I2) (\NlwInverterSignal_NET2512_MC.D2_PT_0/IN2 \))
			((I3) (\U1/U4/LatchEdge1r \))
			((I4) (\NlwInverterSignal_NET2512_MC.D2_PT_0/IN4 \))
			((O) (\NET2512_MC.D2_PT_0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NET2512_MC.D2_PT_1_1431 \ 0 14653 (_entity .  X_AND5)
		(_port
			((I0) (\NlwInverterSignal_NET2512_MC.D2_PT_1/IN0 \))
			((I1) (\NlwInverterSignal_NET2512_MC.D2_PT_1/IN1 \))
			((I2) (\NlwInverterSignal_NET2512_MC.D2_PT_1/IN2 \))
			((I3) (\NlwInverterSignal_NET2512_MC.D2_PT_1/IN3 \))
			((I4) (\U1/U4/InEdge1r \))
			((O) (\NET2512_MC.D2_PT_1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NET2512_MC.D2_PT_2_1432 \ 0 14661 (_entity .  X_AND16)
		(_port
			((I0) (\NlwInverterSignal_NET2512_MC.D2_PT_2/IN0 \))
			((I1) (\RD_II/UIM \))
			((I2) (U2_ADDR_reg(1)))
			((I3) (\NlwInverterSignal_NET2512_MC.D2_PT_2/IN3 \))
			((I4) (N_PZ_931))
			((I5) (\NlwInverterSignal_NET2512_MC.D2_PT_2/IN5 \))
			((I6) (\NlwInverterSignal_NET2512_MC.D2_PT_2/IN6 \))
			((I7) (\NlwInverterSignal_NET2512_MC.D2_PT_2/IN7 \))
			((I8) (\AD<6>_II/UIM \))
			((I9) (\NlwInverterSignal_NET2512_MC.D2_PT_2/IN9 \))
			((I10) (Vcc))
			((I11) (Vcc))
			((I12) (Vcc))
			((I13) (Vcc))
			((I14) (Vcc))
			((I15) (Vcc))
			((O) (\NET2512_MC.D2_PT_2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NET2512_MC.D2_PT_3_1433 \ 0 14680 (_entity .  X_AND16)
		(_port
			((I0) (\NlwInverterSignal_NET2512_MC.D2_PT_3/IN0 \))
			((I1) (\RD_II/UIM \))
			((I2) (U2_ADDR_reg(1)))
			((I3) (\NlwInverterSignal_NET2512_MC.D2_PT_3/IN3 \))
			((I4) (N_PZ_931))
			((I5) (\NlwInverterSignal_NET2512_MC.D2_PT_3/IN5 \))
			((I6) (\NlwInverterSignal_NET2512_MC.D2_PT_3/IN6 \))
			((I7) (\NlwInverterSignal_NET2512_MC.D2_PT_3/IN7 \))
			((I8) (\NlwInverterSignal_NET2512_MC.D2_PT_3/IN8 \))
			((I9) (NET2512))
			((I10) (Vcc))
			((I11) (Vcc))
			((I12) (Vcc))
			((I13) (Vcc))
			((I14) (Vcc))
			((I15) (Vcc))
			((O) (\NET2512_MC.D2_PT_3 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NET2512_MC.D2_1434 \ 0 14699 (_entity .  X_OR4)
		(_port
			((I0) (\NET2512_MC.D2_PT_0 \))
			((I1) (\NET2512_MC.D2_PT_1 \))
			((I2) (\NET2512_MC.D2_PT_2 \))
			((I3) (\NET2512_MC.D2_PT_3 \))
			((O) (\NET2512_MC.D2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U4/LatchEdge1r_1435 \ 0 14706 (_entity .  X_BUF)
		(_port
			((I) (\U1/U4/LatchEdge1r_MC.Q \))
			((O) (\U1/U4/LatchEdge1r \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U4/LatchEdge1r_MC_tsimcreated_xor__1436 \ 0 14710 (_entity .  X_XOR2)
		(_port
			((I0) (\U1/U4/LatchEdge1r_MC.D \))
			((I1) (\U1/U4/LatchEdge1r_MC.Q \))
			((O) (\U1/U4/LatchEdge1r_MC_tsimcreated_xor_ \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U4/LatchEdge1r_MC.REG \ 0 14715 (_entity .  X_FF)
		(_port
			((I) (\U1/U4/LatchEdge1r_MC_tsimcreated_xor_ \))
			((CE) (Vcc))
			((CLK) (\U1/U4/LatchEdge1r_MC.REG_tsimcreated_inv_Mclk_II/FCLK \))
			((SET) (Gnd))
			((RST) (PRLD))
			((O) (\U1/U4/LatchEdge1r_MC.Q \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U4/LatchEdge1r_MC.REG_tsimcreated_inv_Mclk_II/FCLK_1437 \ 0 14723 (_entity .  X_INV)
		(_port
			((I) (\Mclk_II/FCLK \))
			((O) (\U1/U4/LatchEdge1r_MC.REG_tsimcreated_inv_Mclk_II/FCLK \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U4/LatchEdge1r_MC.D_1438 \ 0 14727 (_entity .  X_XOR2)
		(_port
			((I0) (\U1/U4/LatchEdge1r_MC.D1 \))
			((I1) (\U1/U4/LatchEdge1r_MC.D2 \))
			((O) (\U1/U4/LatchEdge1r_MC.D \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U4/LatchEdge1r_MC.D1_1439 \ 0 14732 (_entity .  X_ZERO)
		(_port
			((O) (\U1/U4/LatchEdge1r_MC.D1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U4/LatchEdge1r_MC.D2_PT_0_1440 \ 0 14735 (_entity .  X_AND2)
		(_port
			((I0) (\Reset_II/UIM \))
			((I1) (\U1/U4/LatchEdge1r \))
			((O) (\U1/U4/LatchEdge1r_MC.D2_PT_0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U4/LatchEdge1r_MC.D2_PT_1_1441 \ 0 14740 (_entity .  X_AND16)
		(_port
			((I0) (\NlwInverterSignal_U1/U4/LatchEdge1r_MC.D2_PT_1/IN0 \))
			((I1) (\RD_II/UIM \))
			((I2) (U2_ADDR_reg(1)))
			((I3) (U2_ADDR_reg(0)))
			((I4) (N_PZ_931))
			((I5) (\NlwInverterSignal_U1/U4/LatchEdge1r_MC.D2_PT_1/IN5 \))
			((I6) (\NlwInverterSignal_U1/U4/LatchEdge1r_MC.D2_PT_1/IN6 \))
			((I7) (\NlwInverterSignal_U1/U4/LatchEdge1r_MC.D2_PT_1/IN7 \))
			((I8) (\U1/U4/LatchEdge1r \))
			((I9) (Vcc))
			((I10) (Vcc))
			((I11) (Vcc))
			((I12) (Vcc))
			((I13) (Vcc))
			((I14) (Vcc))
			((I15) (Vcc))
			((O) (\U1/U4/LatchEdge1r_MC.D2_PT_1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U4/LatchEdge1r_MC.D2_PT_2_1442 \ 0 14759 (_entity .  X_AND16)
		(_port
			((I0) (\NlwInverterSignal_U1/U4/LatchEdge1r_MC.D2_PT_2/IN0 \))
			((I1) (\RD_II/UIM \))
			((I2) (U2_ADDR_reg(1)))
			((I3) (U2_ADDR_reg(0)))
			((I4) (N_PZ_931))
			((I5) (\NlwInverterSignal_U1/U4/LatchEdge1r_MC.D2_PT_2/IN5 \))
			((I6) (\NlwInverterSignal_U1/U4/LatchEdge1r_MC.D2_PT_2/IN6 \))
			((I7) (\NlwInverterSignal_U1/U4/LatchEdge1r_MC.D2_PT_2/IN7 \))
			((I8) (\AD<6>_II/UIM \))
			((I9) (\NlwInverterSignal_U1/U4/LatchEdge1r_MC.D2_PT_2/IN9 \))
			((I10) (Vcc))
			((I11) (Vcc))
			((I12) (Vcc))
			((I13) (Vcc))
			((I14) (Vcc))
			((I15) (Vcc))
			((O) (\U1/U4/LatchEdge1r_MC.D2_PT_2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U4/LatchEdge1r_MC.D2_1443 \ 0 14778 (_entity .  X_OR3)
		(_port
			((I0) (\U1/U4/LatchEdge1r_MC.D2_PT_0 \))
			((I1) (\U1/U4/LatchEdge1r_MC.D2_PT_1 \))
			((I2) (\U1/U4/LatchEdge1r_MC.D2_PT_2 \))
			((O) (\U1/U4/LatchEdge1r_MC.D2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U3/DCORIE<6> \ 0 14784 (_entity .  X_BUF)
		(_port
			((I) (\U3/DCORIE<6>_MC.Q \))
			((O) (\U3/DCORIE \(6)))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U3/DCORIE<6>_MC_tsimcreated_xor__1444 \ 0 14788 (_entity .  X_XOR2)
		(_port
			((I0) (\U3/DCORIE<6>_MC.D \))
			((I1) (\U3/DCORIE<6>_MC.Q \))
			((O) (\U3/DCORIE<6>_MC_tsimcreated_xor_ \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U3/DCORIE<6>_MC.REG \ 0 14793 (_entity .  X_FF)
		(_port
			((I) (\U3/DCORIE<6>_MC_tsimcreated_xor_ \))
			((CE) (Vcc))
			((CLK) (\Mclk_II/FCLK \))
			((SET) (Gnd))
			((RST) (PRLD))
			((O) (\U3/DCORIE<6>_MC.Q \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U3/DCORIE<6>_MC.D_1445 \ 0 14801 (_entity .  X_XOR2)
		(_port
			((I0) (\U3/DCORIE<6>_MC.D1 \))
			((I1) (\U3/DCORIE<6>_MC.D2 \))
			((O) (\U3/DCORIE<6>_MC.D \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U3/DCORIE<6>_MC.D1_1446 \ 0 14806 (_entity .  X_ZERO)
		(_port
			((O) (\U3/DCORIE<6>_MC.D1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U3/DCORIE<6>_MC.D2_PT_0_1447 \ 0 14809 (_entity .  X_AND2)
		(_port
			((I0) (\Reset_II/UIM \))
			((I1) (\U3/DCORIE \(6)))
			((O) (\U3/DCORIE<6>_MC.D2_PT_0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U3/DCORIE<6>_MC.D2_PT_1_1448 \ 0 14814 (_entity .  X_AND16)
		(_port
			((I0) (\NlwInverterSignal_U3/DCORIE<6>_MC.D2_PT_1/IN0 \))
			((I1) (\RD_II/UIM \))
			((I2) (\NlwInverterSignal_U3/DCORIE<6>_MC.D2_PT_1/IN2 \))
			((I3) (U2_ADDR_reg(0)))
			((I4) (N_PZ_931))
			((I5) (\NlwInverterSignal_U3/DCORIE<6>_MC.D2_PT_1/IN5 \))
			((I6) (\NlwInverterSignal_U3/DCORIE<6>_MC.D2_PT_1/IN6 \))
			((I7) (\NlwInverterSignal_U3/DCORIE<6>_MC.D2_PT_1/IN7 \))
			((I8) (\U3/DCORIE \(6)))
			((I9) (Vcc))
			((I10) (Vcc))
			((I11) (Vcc))
			((I12) (Vcc))
			((I13) (Vcc))
			((I14) (Vcc))
			((I15) (Vcc))
			((O) (\U3/DCORIE<6>_MC.D2_PT_1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U3/DCORIE<6>_MC.D2_PT_2_1449 \ 0 14833 (_entity .  X_AND16)
		(_port
			((I0) (\NlwInverterSignal_U3/DCORIE<6>_MC.D2_PT_2/IN0 \))
			((I1) (\RD_II/UIM \))
			((I2) (\NlwInverterSignal_U3/DCORIE<6>_MC.D2_PT_2/IN2 \))
			((I3) (U2_ADDR_reg(0)))
			((I4) (N_PZ_931))
			((I5) (\NlwInverterSignal_U3/DCORIE<6>_MC.D2_PT_2/IN5 \))
			((I6) (\NlwInverterSignal_U3/DCORIE<6>_MC.D2_PT_2/IN6 \))
			((I7) (\NlwInverterSignal_U3/DCORIE<6>_MC.D2_PT_2/IN7 \))
			((I8) (\AD<6>_II/UIM \))
			((I9) (\NlwInverterSignal_U3/DCORIE<6>_MC.D2_PT_2/IN9 \))
			((I10) (Vcc))
			((I11) (Vcc))
			((I12) (Vcc))
			((I13) (Vcc))
			((I14) (Vcc))
			((I15) (Vcc))
			((O) (\U3/DCORIE<6>_MC.D2_PT_2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U3/DCORIE<6>_MC.D2_1450 \ 0 14852 (_entity .  X_OR3)
		(_port
			((I0) (\U3/DCORIE<6>_MC.D2_PT_0 \))
			((I1) (\U3/DCORIE<6>_MC.D2_PT_1 \))
			((I2) (\U3/DCORIE<6>_MC.D2_PT_2 \))
			((O) (\U3/DCORIE<6>_MC.D2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U3/DCORIE<7> \ 0 14858 (_entity .  X_BUF)
		(_port
			((I) (\U3/DCORIE<7>_MC.Q \))
			((O) (\U3/DCORIE \(7)))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U3/DCORIE<7>_MC_tsimcreated_xor__1451 \ 0 14862 (_entity .  X_XOR2)
		(_port
			((I0) (\U3/DCORIE<7>_MC.D \))
			((I1) (\U3/DCORIE<7>_MC.Q \))
			((O) (\U3/DCORIE<7>_MC_tsimcreated_xor_ \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U3/DCORIE<7>_MC.REG \ 0 14867 (_entity .  X_FF)
		(_port
			((I) (\U3/DCORIE<7>_MC_tsimcreated_xor_ \))
			((CE) (Vcc))
			((CLK) (\Mclk_II/FCLK \))
			((SET) (Gnd))
			((RST) (PRLD))
			((O) (\U3/DCORIE<7>_MC.Q \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U3/DCORIE<7>_MC.D_1452 \ 0 14875 (_entity .  X_XOR2)
		(_port
			((I0) (\U3/DCORIE<7>_MC.D1 \))
			((I1) (\U3/DCORIE<7>_MC.D2 \))
			((O) (\U3/DCORIE<7>_MC.D \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U3/DCORIE<7>_MC.D1_1453 \ 0 14880 (_entity .  X_ZERO)
		(_port
			((O) (\U3/DCORIE<7>_MC.D1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U3/DCORIE<7>_MC.D2_PT_0_1454 \ 0 14883 (_entity .  X_AND2)
		(_port
			((I0) (\Reset_II/UIM \))
			((I1) (\U3/DCORIE \(7)))
			((O) (\U3/DCORIE<7>_MC.D2_PT_0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U3/DCORIE<7>_MC.D2_PT_1_1455 \ 0 14888 (_entity .  X_AND16)
		(_port
			((I0) (\NlwInverterSignal_U3/DCORIE<7>_MC.D2_PT_1/IN0 \))
			((I1) (\RD_II/UIM \))
			((I2) (\NlwInverterSignal_U3/DCORIE<7>_MC.D2_PT_1/IN2 \))
			((I3) (U2_ADDR_reg(0)))
			((I4) (N_PZ_931))
			((I5) (\NlwInverterSignal_U3/DCORIE<7>_MC.D2_PT_1/IN5 \))
			((I6) (\NlwInverterSignal_U3/DCORIE<7>_MC.D2_PT_1/IN6 \))
			((I7) (\NlwInverterSignal_U3/DCORIE<7>_MC.D2_PT_1/IN7 \))
			((I8) (\U3/DCORIE \(7)))
			((I9) (Vcc))
			((I10) (Vcc))
			((I11) (Vcc))
			((I12) (Vcc))
			((I13) (Vcc))
			((I14) (Vcc))
			((I15) (Vcc))
			((O) (\U3/DCORIE<7>_MC.D2_PT_1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U3/DCORIE<7>_MC.D2_PT_2_1456 \ 0 14907 (_entity .  X_AND16)
		(_port
			((I0) (\NlwInverterSignal_U3/DCORIE<7>_MC.D2_PT_2/IN0 \))
			((I1) (\RD_II/UIM \))
			((I2) (\NlwInverterSignal_U3/DCORIE<7>_MC.D2_PT_2/IN2 \))
			((I3) (U2_ADDR_reg(0)))
			((I4) (N_PZ_931))
			((I5) (\NlwInverterSignal_U3/DCORIE<7>_MC.D2_PT_2/IN5 \))
			((I6) (\NlwInverterSignal_U3/DCORIE<7>_MC.D2_PT_2/IN6 \))
			((I7) (\NlwInverterSignal_U3/DCORIE<7>_MC.D2_PT_2/IN7 \))
			((I8) (\AD<7>_II/UIM \))
			((I9) (\NlwInverterSignal_U3/DCORIE<7>_MC.D2_PT_2/IN9 \))
			((I10) (Vcc))
			((I11) (Vcc))
			((I12) (Vcc))
			((I13) (Vcc))
			((I14) (Vcc))
			((I15) (Vcc))
			((O) (\U3/DCORIE<7>_MC.D2_PT_2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U3/DCORIE<7>_MC.D2_1457 \ 0 14926 (_entity .  X_OR3)
		(_port
			((I0) (\U3/DCORIE<7>_MC.D2_PT_0 \))
			((I1) (\U3/DCORIE<7>_MC.D2_PT_1 \))
			((I2) (\U3/DCORIE<7>_MC.D2_PT_2 \))
			((O) (\U3/DCORIE<7>_MC.D2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \LED1_MC.Q_1458 \ 0 14932 (_entity .  X_BUF)
		(_port
			((I) (\LED1_MC.Q_tsimrenamed_net_ \))
			((O) (\LED1_MC.Q \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \LED1_MC.Q_tsimrenamed_net__1459 \ 0 14936 (_entity .  X_BUF)
		(_port
			((I) (\LED1_MC.D \))
			((O) (\LED1_MC.Q_tsimrenamed_net_ \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \LED1_MC.D_1460 \ 0 14940 (_entity .  X_XOR2)
		(_port
			((I0) (\NlwInverterSignal_LED1_MC.D/IN0 \))
			((I1) (\LED1_MC.D2 \))
			((O) (\LED1_MC.D \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \LED1_MC.D1_1461 \ 0 14945 (_entity .  X_AND2)
		(_port
			((I0) (\LightSense_II/UIM \))
			((I1) (\NlwInverterSignal_LED1_MC.D1/IN1 \))
			((O) (\LED1_MC.D1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \LED1_MC.D2_1462 \ 0 14950 (_entity .  X_ZERO)
		(_port
			((O) (\LED1_MC.D2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U9/MISCr<0>_MC.Q_1463 \ 0 14953 (_entity .  X_BUF)
		(_port
			((I) (\U9/MISCr<0>_MC.D \))
			((O) (\U9/MISCr<0>_MC.Q \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U9/MISCr<0>_MC.OE_1464 \ 0 14957 (_entity .  X_BUF)
		(_port
			((I) (\U9/MISCr<0>_MC.BUFOE.OUT \))
			((O) (\U9/MISCr<0>_MC.OE \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U9/MISCr<0>_MC.BUFOE.OUT_1465 \ 0 14961 (_entity .  X_BUF)
		(_port
			((I) (\FOOBAR3__ctinst/7 \))
			((O) (\U9/MISCr<0>_MC.BUFOE.OUT \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U9/MISCr<0>_MC.D_1466 \ 0 14965 (_entity .  X_XOR2)
		(_port
			((I0) (\NlwInverterSignal_U9/MISCr<0>_MC.D/IN0 \))
			((I1) (\U9/MISCr<0>_MC.D2 \))
			((O) (\U9/MISCr<0>_MC.D \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U9/MISCr<0>_MC.D1_1467 \ 0 14970 (_entity .  X_ZERO)
		(_port
			((O) (\U9/MISCr<0>_MC.D1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U9/MISCr<0>_MC.D2_PT_0_1468 \ 0 14973 (_entity .  X_AND2)
		(_port
			((I0) (N_PZ_964))
			((I1) (\NlwInverterSignal_U9/MISCr<0>_MC.D2_PT_0/IN1 \))
			((O) (\U9/MISCr<0>_MC.D2_PT_0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U9/MISCr<0>_MC.D2_PT_1_1469 \ 0 14978 (_entity .  X_AND2)
		(_port
			((I0) (N_PZ_1060))
			((I1) (\NlwInverterSignal_U9/MISCr<0>_MC.D2_PT_1/IN1 \))
			((O) (\U9/MISCr<0>_MC.D2_PT_1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U9/MISCr<0>_MC.D2_PT_2_1470 \ 0 14983 (_entity .  X_AND8)
		(_port
			((I0) (\WR_II/UIM \))
			((I1) (\NlwInverterSignal_U9/MISCr<0>_MC.D2_PT_2/IN1 \))
			((I2) (U2_ADDR_reg(1)))
			((I3) (U2_ADDR_reg(0)))
			((I4) (N_PZ_931))
			((I5) (U2_ADDR_reg(2)))
			((I6) (U2_ADDR_reg(3)))
			((I7) (\NlwInverterSignal_U9/MISCr<0>_MC.D2_PT_2/IN7 \))
			((O) (\U9/MISCr<0>_MC.D2_PT_2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U9/MISCr<0>_MC.D2_PT_3_1471 \ 0 14994 (_entity .  X_AND8)
		(_port
			((I0) (\WR_II/UIM \))
			((I1) (\NlwInverterSignal_U9/MISCr<0>_MC.D2_PT_3/IN1 \))
			((I2) (U2_ADDR_reg(1)))
			((I3) (U2_ADDR_reg(0)))
			((I4) (N_PZ_931))
			((I5) (\NlwInverterSignal_U9/MISCr<0>_MC.D2_PT_3/IN5 \))
			((I6) (\NlwInverterSignal_U9/MISCr<0>_MC.D2_PT_3/IN6 \))
			((I7) (\NlwInverterSignal_U9/MISCr<0>_MC.D2_PT_3/IN7 \))
			((O) (\U9/MISCr<0>_MC.D2_PT_3 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U9/MISCr<0>_MC.D2_PT_4_1472 \ 0 15005 (_entity .  X_AND8)
		(_port
			((I0) (\WR_II/UIM \))
			((I1) (\NlwInverterSignal_U9/MISCr<0>_MC.D2_PT_4/IN1 \))
			((I2) (U2_ADDR_reg(1)))
			((I3) (\NlwInverterSignal_U9/MISCr<0>_MC.D2_PT_4/IN3 \))
			((I4) (N_PZ_931))
			((I5) (U2_ADDR_reg(2)))
			((I6) (U2_ADDR_reg(3)))
			((I7) (\NlwInverterSignal_U9/MISCr<0>_MC.D2_PT_4/IN7 \))
			((O) (\U9/MISCr<0>_MC.D2_PT_4 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U9/MISCr<0>_MC.D2_PT_5_1473 \ 0 15016 (_entity .  X_AND8)
		(_port
			((I0) (\WR_II/UIM \))
			((I1) (\NlwInverterSignal_U9/MISCr<0>_MC.D2_PT_5/IN1 \))
			((I2) (\NlwInverterSignal_U9/MISCr<0>_MC.D2_PT_5/IN2 \))
			((I3) (\NlwInverterSignal_U9/MISCr<0>_MC.D2_PT_5/IN3 \))
			((I4) (N_PZ_931))
			((I5) (\NlwInverterSignal_U9/MISCr<0>_MC.D2_PT_5/IN5 \))
			((I6) (\NlwInverterSignal_U9/MISCr<0>_MC.D2_PT_5/IN6 \))
			((I7) (\NlwInverterSignal_U9/MISCr<0>_MC.D2_PT_5/IN7 \))
			((O) (\U9/MISCr<0>_MC.D2_PT_5 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U9/MISCr<0>_MC.D2_1474 \ 0 15027 (_entity .  X_OR6)
		(_port
			((I0) (\U9/MISCr<0>_MC.D2_PT_0 \))
			((I1) (\U9/MISCr<0>_MC.D2_PT_1 \))
			((I2) (\U9/MISCr<0>_MC.D2_PT_2 \))
			((I3) (\U9/MISCr<0>_MC.D2_PT_3 \))
			((I4) (\U9/MISCr<0>_MC.D2_PT_4 \))
			((I5) (\U9/MISCr<0>_MC.D2_PT_5 \))
			((O) (\U9/MISCr<0>_MC.D2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \LED2_MC.Q_1475 \ 0 15036 (_entity .  X_BUF)
		(_port
			((I) (\LED2_MC.Q_tsimrenamed_net_ \))
			((O) (\LED2_MC.Q \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \LED2_MC.Q_tsimrenamed_net__1476 \ 0 15040 (_entity .  X_BUF)
		(_port
			((I) (\LED2_MC.D \))
			((O) (\LED2_MC.Q_tsimrenamed_net_ \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \LED2_MC.D_1477 \ 0 15044 (_entity .  X_XOR2)
		(_port
			((I0) (\NlwInverterSignal_LED2_MC.D/IN0 \))
			((I1) (\LED2_MC.D2 \))
			((O) (\LED2_MC.D \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \LED2_MC.D1_1478 \ 0 15049 (_entity .  X_AND2)
		(_port
			((I0) (\LightSense_II/UIM \))
			((I1) (\NlwInverterSignal_LED2_MC.D1/IN1 \))
			((O) (\LED2_MC.D1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \LED2_MC.D2_1479 \ 0 15054 (_entity .  X_ZERO)
		(_port
			((O) (\LED2_MC.D2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U9/MISCr<1>_MC.Q_1480 \ 0 15057 (_entity .  X_BUF)
		(_port
			((I) (\U9/MISCr<1>_MC.D \))
			((O) (\U9/MISCr<1>_MC.Q \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U9/MISCr<1>_MC.OE_1481 \ 0 15061 (_entity .  X_BUF)
		(_port
			((I) (\U9/MISCr<1>_MC.BUFOE.OUT \))
			((O) (\U9/MISCr<1>_MC.OE \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U9/MISCr<1>_MC.BUFOE.OUT_1482 \ 0 15065 (_entity .  X_BUF)
		(_port
			((I) (\FOOBAR3__ctinst/7 \))
			((O) (\U9/MISCr<1>_MC.BUFOE.OUT \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U9/MISCr<1>_MC.D_1483 \ 0 15069 (_entity .  X_XOR2)
		(_port
			((I0) (\NlwInverterSignal_U9/MISCr<1>_MC.D/IN0 \))
			((I1) (\U9/MISCr<1>_MC.D2 \))
			((O) (\U9/MISCr<1>_MC.D \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U9/MISCr<1>_MC.D1_1484 \ 0 15074 (_entity .  X_ZERO)
		(_port
			((O) (\U9/MISCr<1>_MC.D1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U9/MISCr<1>_MC.D2_PT_0_1485 \ 0 15077 (_entity .  X_AND2)
		(_port
			((I0) (N_PZ_964))
			((I1) (\NlwInverterSignal_U9/MISCr<1>_MC.D2_PT_0/IN1 \))
			((O) (\U9/MISCr<1>_MC.D2_PT_0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U9/MISCr<1>_MC.D2_PT_1_1486 \ 0 15082 (_entity .  X_AND2)
		(_port
			((I0) (N_PZ_1060))
			((I1) (\NlwInverterSignal_U9/MISCr<1>_MC.D2_PT_1/IN1 \))
			((O) (\U9/MISCr<1>_MC.D2_PT_1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U9/MISCr<1>_MC.D2_PT_2_1487 \ 0 15087 (_entity .  X_AND7)
		(_port
			((I0) (\NlwInverterSignal_U9/MISCr<1>_MC.D2_PT_2/IN0 \))
			((I1) (U2_ADDR_reg(1)))
			((I2) (\NlwInverterSignal_U9/MISCr<1>_MC.D2_PT_2/IN2 \))
			((I3) (N_PZ_931))
			((I4) (U2_Enable_AD))
			((I5) (N_PZ_1003))
			((I6) (\NlwInverterSignal_U9/MISCr<1>_MC.D2_PT_2/IN6 \))
			((O) (\U9/MISCr<1>_MC.D2_PT_2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U9/MISCr<1>_MC.D2_PT_3_1488 \ 0 15097 (_entity .  X_AND7)
		(_port
			((I0) (\NlwInverterSignal_U9/MISCr<1>_MC.D2_PT_3/IN0 \))
			((I1) (\NlwInverterSignal_U9/MISCr<1>_MC.D2_PT_3/IN1 \))
			((I2) (\NlwInverterSignal_U9/MISCr<1>_MC.D2_PT_3/IN2 \))
			((I3) (N_PZ_931))
			((I4) (\NlwInverterSignal_U9/MISCr<1>_MC.D2_PT_3/IN4 \))
			((I5) (U2_Enable_AD))
			((I6) (\NlwInverterSignal_U9/MISCr<1>_MC.D2_PT_3/IN6 \))
			((O) (\U9/MISCr<1>_MC.D2_PT_3 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U9/MISCr<1>_MC.D2_PT_4_1489 \ 0 15107 (_entity .  X_AND7)
		(_port
			((I0) (U2_ADDR_reg(1)))
			((I1) (U2_ADDR_reg(0)))
			((I2) (N_PZ_931))
			((I3) (U2_ADDR_reg(2)))
			((I4) (U2_ADDR_reg(3)))
			((I5) (U2_Enable_AD))
			((I6) (\NlwInverterSignal_U9/MISCr<1>_MC.D2_PT_4/IN6 \))
			((O) (\U9/MISCr<1>_MC.D2_PT_4 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U9/MISCr<1>_MC.D2_PT_5_1490 \ 0 15117 (_entity .  X_AND7)
		(_port
			((I0) (U2_ADDR_reg(1)))
			((I1) (U2_ADDR_reg(0)))
			((I2) (N_PZ_931))
			((I3) (\NlwInverterSignal_U9/MISCr<1>_MC.D2_PT_5/IN3 \))
			((I4) (\NlwInverterSignal_U9/MISCr<1>_MC.D2_PT_5/IN4 \))
			((I5) (U2_Enable_AD))
			((I6) (\NlwInverterSignal_U9/MISCr<1>_MC.D2_PT_5/IN6 \))
			((O) (\U9/MISCr<1>_MC.D2_PT_5 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U9/MISCr<1>_MC.D2_1491 \ 0 15127 (_entity .  X_OR6)
		(_port
			((I0) (\U9/MISCr<1>_MC.D2_PT_0 \))
			((I1) (\U9/MISCr<1>_MC.D2_PT_1 \))
			((I2) (\U9/MISCr<1>_MC.D2_PT_2 \))
			((I3) (\U9/MISCr<1>_MC.D2_PT_3 \))
			((I4) (\U9/MISCr<1>_MC.D2_PT_4 \))
			((I5) (\U9/MISCr<1>_MC.D2_PT_5 \))
			((O) (\U9/MISCr<1>_MC.D2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \LED3_MC.Q_1492 \ 0 15136 (_entity .  X_BUF)
		(_port
			((I) (\LED3_MC.Q_tsimrenamed_net_ \))
			((O) (\LED3_MC.Q \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \LED3_MC.Q_tsimrenamed_net__1493 \ 0 15140 (_entity .  X_BUF)
		(_port
			((I) (\LED3_MC.D \))
			((O) (\LED3_MC.Q_tsimrenamed_net_ \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \LED3_MC.D_1494 \ 0 15144 (_entity .  X_XOR2)
		(_port
			((I0) (\NlwInverterSignal_LED3_MC.D/IN0 \))
			((I1) (\LED3_MC.D2 \))
			((O) (\LED3_MC.D \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \LED3_MC.D1_1495 \ 0 15149 (_entity .  X_AND2)
		(_port
			((I0) (\LightSense_II/UIM \))
			((I1) (\NlwInverterSignal_LED3_MC.D1/IN1 \))
			((O) (\LED3_MC.D1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \LED3_MC.D2_1496 \ 0 15154 (_entity .  X_ZERO)
		(_port
			((O) (\LED3_MC.D2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U9/MISCr<2>_MC.Q_1497 \ 0 15157 (_entity .  X_BUF)
		(_port
			((I) (\U9/MISCr<2>_MC.D \))
			((O) (\U9/MISCr<2>_MC.Q \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U9/MISCr<2>_MC.OE_1498 \ 0 15161 (_entity .  X_BUF)
		(_port
			((I) (\U9/MISCr<2>_MC.BUFOE.OUT \))
			((O) (\U9/MISCr<2>_MC.OE \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U9/MISCr<2>_MC.BUFOE.OUT_1499 \ 0 15165 (_entity .  X_BUF)
		(_port
			((I) (\FOOBAR3__ctinst/7 \))
			((O) (\U9/MISCr<2>_MC.BUFOE.OUT \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U9/MISCr<2>_MC.D_1500 \ 0 15169 (_entity .  X_XOR2)
		(_port
			((I0) (\NlwInverterSignal_U9/MISCr<2>_MC.D/IN0 \))
			((I1) (\U9/MISCr<2>_MC.D2 \))
			((O) (\U9/MISCr<2>_MC.D \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U9/MISCr<2>_MC.D1_1501 \ 0 15174 (_entity .  X_ZERO)
		(_port
			((O) (\U9/MISCr<2>_MC.D1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U9/MISCr<2>_MC.D2_PT_0_1502 \ 0 15177 (_entity .  X_AND2)
		(_port
			((I0) (N_PZ_964))
			((I1) (\NlwInverterSignal_U9/MISCr<2>_MC.D2_PT_0/IN1 \))
			((O) (\U9/MISCr<2>_MC.D2_PT_0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U9/MISCr<2>_MC.D2_PT_1_1503 \ 0 15182 (_entity .  X_AND2)
		(_port
			((I0) (N_PZ_1060))
			((I1) (\NlwInverterSignal_U9/MISCr<2>_MC.D2_PT_1/IN1 \))
			((O) (\U9/MISCr<2>_MC.D2_PT_1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U9/MISCr<2>_MC.D2_PT_2_1504 \ 0 15187 (_entity .  X_AND8)
		(_port
			((I0) (\WR_II/UIM \))
			((I1) (\NlwInverterSignal_U9/MISCr<2>_MC.D2_PT_2/IN1 \))
			((I2) (U2_ADDR_reg(1)))
			((I3) (U2_ADDR_reg(0)))
			((I4) (N_PZ_931))
			((I5) (U2_ADDR_reg(2)))
			((I6) (U2_ADDR_reg(3)))
			((I7) (\NlwInverterSignal_U9/MISCr<2>_MC.D2_PT_2/IN7 \))
			((O) (\U9/MISCr<2>_MC.D2_PT_2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U9/MISCr<2>_MC.D2_PT_3_1505 \ 0 15198 (_entity .  X_AND8)
		(_port
			((I0) (\WR_II/UIM \))
			((I1) (\NlwInverterSignal_U9/MISCr<2>_MC.D2_PT_3/IN1 \))
			((I2) (U2_ADDR_reg(1)))
			((I3) (U2_ADDR_reg(0)))
			((I4) (N_PZ_931))
			((I5) (\NlwInverterSignal_U9/MISCr<2>_MC.D2_PT_3/IN5 \))
			((I6) (\NlwInverterSignal_U9/MISCr<2>_MC.D2_PT_3/IN6 \))
			((I7) (\NlwInverterSignal_U9/MISCr<2>_MC.D2_PT_3/IN7 \))
			((O) (\U9/MISCr<2>_MC.D2_PT_3 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U9/MISCr<2>_MC.D2_PT_4_1506 \ 0 15209 (_entity .  X_AND8)
		(_port
			((I0) (\WR_II/UIM \))
			((I1) (\NlwInverterSignal_U9/MISCr<2>_MC.D2_PT_4/IN1 \))
			((I2) (U2_ADDR_reg(1)))
			((I3) (\NlwInverterSignal_U9/MISCr<2>_MC.D2_PT_4/IN3 \))
			((I4) (N_PZ_931))
			((I5) (U2_ADDR_reg(2)))
			((I6) (U2_ADDR_reg(3)))
			((I7) (\NlwInverterSignal_U9/MISCr<2>_MC.D2_PT_4/IN7 \))
			((O) (\U9/MISCr<2>_MC.D2_PT_4 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U9/MISCr<2>_MC.D2_PT_5_1507 \ 0 15220 (_entity .  X_AND8)
		(_port
			((I0) (\WR_II/UIM \))
			((I1) (\NlwInverterSignal_U9/MISCr<2>_MC.D2_PT_5/IN1 \))
			((I2) (\NlwInverterSignal_U9/MISCr<2>_MC.D2_PT_5/IN2 \))
			((I3) (\NlwInverterSignal_U9/MISCr<2>_MC.D2_PT_5/IN3 \))
			((I4) (N_PZ_931))
			((I5) (\NlwInverterSignal_U9/MISCr<2>_MC.D2_PT_5/IN5 \))
			((I6) (\NlwInverterSignal_U9/MISCr<2>_MC.D2_PT_5/IN6 \))
			((I7) (\NlwInverterSignal_U9/MISCr<2>_MC.D2_PT_5/IN7 \))
			((O) (\U9/MISCr<2>_MC.D2_PT_5 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U9/MISCr<2>_MC.D2_1508 \ 0 15231 (_entity .  X_OR6)
		(_port
			((I0) (\U9/MISCr<2>_MC.D2_PT_0 \))
			((I1) (\U9/MISCr<2>_MC.D2_PT_1 \))
			((I2) (\U9/MISCr<2>_MC.D2_PT_2 \))
			((I3) (\U9/MISCr<2>_MC.D2_PT_3 \))
			((I4) (\U9/MISCr<2>_MC.D2_PT_4 \))
			((I5) (\U9/MISCr<2>_MC.D2_PT_5 \))
			((O) (\U9/MISCr<2>_MC.D2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \LED4_MC.Q_1509 \ 0 15240 (_entity .  X_BUF)
		(_port
			((I) (\LED4_MC.Q_tsimrenamed_net_ \))
			((O) (\LED4_MC.Q \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \LED4_MC.Q_tsimrenamed_net__1510 \ 0 15244 (_entity .  X_BUF)
		(_port
			((I) (\LED4_MC.D \))
			((O) (\LED4_MC.Q_tsimrenamed_net_ \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \LED4_MC.D_1511 \ 0 15248 (_entity .  X_XOR2)
		(_port
			((I0) (\NlwInverterSignal_LED4_MC.D/IN0 \))
			((I1) (\LED4_MC.D2 \))
			((O) (\LED4_MC.D \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \LED4_MC.D1_1512 \ 0 15253 (_entity .  X_AND2)
		(_port
			((I0) (\LightSense_II/UIM \))
			((I1) (\NlwInverterSignal_LED4_MC.D1/IN1 \))
			((O) (\LED4_MC.D1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \LED4_MC.D2_1513 \ 0 15258 (_entity .  X_ZERO)
		(_port
			((O) (\LED4_MC.D2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U9/MISCr<3>_MC.Q_1514 \ 0 15261 (_entity .  X_BUF)
		(_port
			((I) (\U9/MISCr<3>_MC.D \))
			((O) (\U9/MISCr<3>_MC.Q \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U9/MISCr<3>_MC.OE_1515 \ 0 15265 (_entity .  X_BUF)
		(_port
			((I) (\U9/MISCr<3>_MC.BUFOE.OUT \))
			((O) (\U9/MISCr<3>_MC.OE \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U9/MISCr<3>_MC.BUFOE.OUT_1516 \ 0 15269 (_entity .  X_BUF)
		(_port
			((I) (\FOOBAR3__ctinst/7 \))
			((O) (\U9/MISCr<3>_MC.BUFOE.OUT \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U9/MISCr<3>_MC.D_1517 \ 0 15273 (_entity .  X_XOR2)
		(_port
			((I0) (\NlwInverterSignal_U9/MISCr<3>_MC.D/IN0 \))
			((I1) (\U9/MISCr<3>_MC.D2 \))
			((O) (\U9/MISCr<3>_MC.D \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U9/MISCr<3>_MC.D1_1518 \ 0 15278 (_entity .  X_ZERO)
		(_port
			((O) (\U9/MISCr<3>_MC.D1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U9/MISCr<3>_MC.D2_PT_0_1519 \ 0 15281 (_entity .  X_AND2)
		(_port
			((I0) (N_PZ_964))
			((I1) (\NlwInverterSignal_U9/MISCr<3>_MC.D2_PT_0/IN1 \))
			((O) (\U9/MISCr<3>_MC.D2_PT_0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U9/MISCr<3>_MC.D2_PT_1_1520 \ 0 15286 (_entity .  X_AND2)
		(_port
			((I0) (N_PZ_1060))
			((I1) (\NlwInverterSignal_U9/MISCr<3>_MC.D2_PT_1/IN1 \))
			((O) (\U9/MISCr<3>_MC.D2_PT_1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U9/MISCr<3>_MC.D2_PT_2_1521 \ 0 15291 (_entity .  X_AND8)
		(_port
			((I0) (\WR_II/UIM \))
			((I1) (\NlwInverterSignal_U9/MISCr<3>_MC.D2_PT_2/IN1 \))
			((I2) (U2_ADDR_reg(1)))
			((I3) (U2_ADDR_reg(0)))
			((I4) (N_PZ_931))
			((I5) (U2_ADDR_reg(2)))
			((I6) (U2_ADDR_reg(3)))
			((I7) (\NlwInverterSignal_U9/MISCr<3>_MC.D2_PT_2/IN7 \))
			((O) (\U9/MISCr<3>_MC.D2_PT_2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U9/MISCr<3>_MC.D2_PT_3_1522 \ 0 15302 (_entity .  X_AND8)
		(_port
			((I0) (\WR_II/UIM \))
			((I1) (\NlwInverterSignal_U9/MISCr<3>_MC.D2_PT_3/IN1 \))
			((I2) (U2_ADDR_reg(1)))
			((I3) (U2_ADDR_reg(0)))
			((I4) (N_PZ_931))
			((I5) (\NlwInverterSignal_U9/MISCr<3>_MC.D2_PT_3/IN5 \))
			((I6) (\NlwInverterSignal_U9/MISCr<3>_MC.D2_PT_3/IN6 \))
			((I7) (\NlwInverterSignal_U9/MISCr<3>_MC.D2_PT_3/IN7 \))
			((O) (\U9/MISCr<3>_MC.D2_PT_3 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U9/MISCr<3>_MC.D2_PT_4_1523 \ 0 15313 (_entity .  X_AND8)
		(_port
			((I0) (\WR_II/UIM \))
			((I1) (\NlwInverterSignal_U9/MISCr<3>_MC.D2_PT_4/IN1 \))
			((I2) (U2_ADDR_reg(1)))
			((I3) (\NlwInverterSignal_U9/MISCr<3>_MC.D2_PT_4/IN3 \))
			((I4) (N_PZ_931))
			((I5) (U2_ADDR_reg(2)))
			((I6) (U2_ADDR_reg(3)))
			((I7) (\NlwInverterSignal_U9/MISCr<3>_MC.D2_PT_4/IN7 \))
			((O) (\U9/MISCr<3>_MC.D2_PT_4 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U9/MISCr<3>_MC.D2_PT_5_1524 \ 0 15324 (_entity .  X_AND8)
		(_port
			((I0) (\WR_II/UIM \))
			((I1) (\NlwInverterSignal_U9/MISCr<3>_MC.D2_PT_5/IN1 \))
			((I2) (\NlwInverterSignal_U9/MISCr<3>_MC.D2_PT_5/IN2 \))
			((I3) (\NlwInverterSignal_U9/MISCr<3>_MC.D2_PT_5/IN3 \))
			((I4) (N_PZ_931))
			((I5) (\NlwInverterSignal_U9/MISCr<3>_MC.D2_PT_5/IN5 \))
			((I6) (\NlwInverterSignal_U9/MISCr<3>_MC.D2_PT_5/IN6 \))
			((I7) (\NlwInverterSignal_U9/MISCr<3>_MC.D2_PT_5/IN7 \))
			((O) (\U9/MISCr<3>_MC.D2_PT_5 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U9/MISCr<3>_MC.D2_1525 \ 0 15335 (_entity .  X_OR6)
		(_port
			((I0) (\U9/MISCr<3>_MC.D2_PT_0 \))
			((I1) (\U9/MISCr<3>_MC.D2_PT_1 \))
			((I2) (\U9/MISCr<3>_MC.D2_PT_2 \))
			((I3) (\U9/MISCr<3>_MC.D2_PT_3 \))
			((I4) (\U9/MISCr<3>_MC.D2_PT_4 \))
			((I5) (\U9/MISCr<3>_MC.D2_PT_5 \))
			((O) (\U9/MISCr<3>_MC.D2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \LED5_MC.Q_1526 \ 0 15344 (_entity .  X_BUF)
		(_port
			((I) (\LED5_MC.Q_tsimrenamed_net_ \))
			((O) (\LED5_MC.Q \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \LED5_MC.Q_tsimrenamed_net__1527 \ 0 15348 (_entity .  X_BUF)
		(_port
			((I) (\LED5_MC.D \))
			((O) (\LED5_MC.Q_tsimrenamed_net_ \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \LED5_MC.D_1528 \ 0 15352 (_entity .  X_XOR2)
		(_port
			((I0) (\NlwInverterSignal_LED5_MC.D/IN0 \))
			((I1) (\LED5_MC.D2 \))
			((O) (\LED5_MC.D \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \LED5_MC.D1_1529 \ 0 15357 (_entity .  X_AND2)
		(_port
			((I0) (\LightSense_II/UIM \))
			((I1) (\NlwInverterSignal_LED5_MC.D1/IN1 \))
			((O) (\LED5_MC.D1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \LED5_MC.D2_1530 \ 0 15362 (_entity .  X_ZERO)
		(_port
			((O) (\LED5_MC.D2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U9/MISCr<4>_MC.Q_1531 \ 0 15365 (_entity .  X_BUF)
		(_port
			((I) (\U9/MISCr<4>_MC.D \))
			((O) (\U9/MISCr<4>_MC.Q \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U9/MISCr<4>_MC.OE_1532 \ 0 15369 (_entity .  X_BUF)
		(_port
			((I) (\U9/MISCr<4>_MC.BUFOE.OUT \))
			((O) (\U9/MISCr<4>_MC.OE \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U9/MISCr<4>_MC.BUFOE.OUT_1533 \ 0 15373 (_entity .  X_BUF)
		(_port
			((I) (\FOOBAR3__ctinst/7 \))
			((O) (\U9/MISCr<4>_MC.BUFOE.OUT \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U9/MISCr<4>_MC.D_1534 \ 0 15377 (_entity .  X_XOR2)
		(_port
			((I0) (\NlwInverterSignal_U9/MISCr<4>_MC.D/IN0 \))
			((I1) (\U9/MISCr<4>_MC.D2 \))
			((O) (\U9/MISCr<4>_MC.D \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U9/MISCr<4>_MC.D1_1535 \ 0 15382 (_entity .  X_ZERO)
		(_port
			((O) (\U9/MISCr<4>_MC.D1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U9/MISCr<4>_MC.D2_PT_0_1536 \ 0 15385 (_entity .  X_AND2)
		(_port
			((I0) (N_PZ_964))
			((I1) (\NlwInverterSignal_U9/MISCr<4>_MC.D2_PT_0/IN1 \))
			((O) (\U9/MISCr<4>_MC.D2_PT_0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U9/MISCr<4>_MC.D2_PT_1_1537 \ 0 15390 (_entity .  X_AND2)
		(_port
			((I0) (N_PZ_1060))
			((I1) (\NlwInverterSignal_U9/MISCr<4>_MC.D2_PT_1/IN1 \))
			((O) (\U9/MISCr<4>_MC.D2_PT_1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U9/MISCr<4>_MC.D2_PT_2_1538 \ 0 15395 (_entity .  X_AND8)
		(_port
			((I0) (\WR_II/UIM \))
			((I1) (\NlwInverterSignal_U9/MISCr<4>_MC.D2_PT_2/IN1 \))
			((I2) (U2_ADDR_reg(1)))
			((I3) (U2_ADDR_reg(0)))
			((I4) (N_PZ_931))
			((I5) (U2_ADDR_reg(2)))
			((I6) (U2_ADDR_reg(3)))
			((I7) (\NlwInverterSignal_U9/MISCr<4>_MC.D2_PT_2/IN7 \))
			((O) (\U9/MISCr<4>_MC.D2_PT_2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U9/MISCr<4>_MC.D2_PT_3_1539 \ 0 15406 (_entity .  X_AND8)
		(_port
			((I0) (\WR_II/UIM \))
			((I1) (\NlwInverterSignal_U9/MISCr<4>_MC.D2_PT_3/IN1 \))
			((I2) (U2_ADDR_reg(1)))
			((I3) (U2_ADDR_reg(0)))
			((I4) (N_PZ_931))
			((I5) (\NlwInverterSignal_U9/MISCr<4>_MC.D2_PT_3/IN5 \))
			((I6) (\NlwInverterSignal_U9/MISCr<4>_MC.D2_PT_3/IN6 \))
			((I7) (\NlwInverterSignal_U9/MISCr<4>_MC.D2_PT_3/IN7 \))
			((O) (\U9/MISCr<4>_MC.D2_PT_3 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U9/MISCr<4>_MC.D2_PT_4_1540 \ 0 15417 (_entity .  X_AND8)
		(_port
			((I0) (\WR_II/UIM \))
			((I1) (\NlwInverterSignal_U9/MISCr<4>_MC.D2_PT_4/IN1 \))
			((I2) (U2_ADDR_reg(1)))
			((I3) (\NlwInverterSignal_U9/MISCr<4>_MC.D2_PT_4/IN3 \))
			((I4) (N_PZ_931))
			((I5) (U2_ADDR_reg(2)))
			((I6) (U2_ADDR_reg(3)))
			((I7) (\NlwInverterSignal_U9/MISCr<4>_MC.D2_PT_4/IN7 \))
			((O) (\U9/MISCr<4>_MC.D2_PT_4 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U9/MISCr<4>_MC.D2_PT_5_1541 \ 0 15428 (_entity .  X_AND8)
		(_port
			((I0) (\WR_II/UIM \))
			((I1) (\NlwInverterSignal_U9/MISCr<4>_MC.D2_PT_5/IN1 \))
			((I2) (\NlwInverterSignal_U9/MISCr<4>_MC.D2_PT_5/IN2 \))
			((I3) (\NlwInverterSignal_U9/MISCr<4>_MC.D2_PT_5/IN3 \))
			((I4) (N_PZ_931))
			((I5) (\NlwInverterSignal_U9/MISCr<4>_MC.D2_PT_5/IN5 \))
			((I6) (\NlwInverterSignal_U9/MISCr<4>_MC.D2_PT_5/IN6 \))
			((I7) (\NlwInverterSignal_U9/MISCr<4>_MC.D2_PT_5/IN7 \))
			((O) (\U9/MISCr<4>_MC.D2_PT_5 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U9/MISCr<4>_MC.D2_1542 \ 0 15439 (_entity .  X_OR6)
		(_port
			((I0) (\U9/MISCr<4>_MC.D2_PT_0 \))
			((I1) (\U9/MISCr<4>_MC.D2_PT_1 \))
			((I2) (\U9/MISCr<4>_MC.D2_PT_2 \))
			((I3) (\U9/MISCr<4>_MC.D2_PT_3 \))
			((I4) (\U9/MISCr<4>_MC.D2_PT_4 \))
			((I5) (\U9/MISCr<4>_MC.D2_PT_5 \))
			((O) (\U9/MISCr<4>_MC.D2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \MHSI_MC.Q_1543 \ 0 15448 (_entity .  X_BUF)
		(_port
			((I) (\MHSI_MC.Q_tsimrenamed_net_ \))
			((O) (\MHSI_MC.Q \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \MHSI_MC.Q_tsimrenamed_net__1544 \ 0 15452 (_entity .  X_BUF)
		(_port
			((I) (\MHSI_MC.D \))
			((O) (\MHSI_MC.Q_tsimrenamed_net_ \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \MHSI_MC.D_1545 \ 0 15456 (_entity .  X_XOR2)
		(_port
			((I0) (\MHSI_MC.D1 \))
			((I1) (\MHSI_MC.D2 \))
			((O) (\MHSI_MC.D \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \MHSI_MC.D1_1546 \ 0 15461 (_entity .  X_AND2)
		(_port
			((I0) (\HSI_II/UIM \))
			((I1) (\HSI_II/UIM \))
			((O) (\MHSI_MC.D1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \MHSI_MC.D2_1547 \ 0 15466 (_entity .  X_ZERO)
		(_port
			((O) (\MHSI_MC.D2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \MTRpwr_MC.Q_1548 \ 0 15469 (_entity .  X_BUF)
		(_port
			((I) (\MTRpwr_MC.Q_tsimrenamed_net_ \))
			((O) (\MTRpwr_MC.Q \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation MTRpwr_MC_tsimcreated_prld__1549 0 15473 (_entity .  X_OR2)
		(_port
			((I0) (\FOOBAR1__ctinst/7 \))
			((I1) (PRLD))
			((O) (MTRpwr_MC_tsimcreated_prld_))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \MTRpwr_MC.REG \ 0 15478 (_entity .  X_FF)
		(_port
			((I) (\MTRpwr_MC.D \))
			((CE) (\FOOBAR18__ctinst/4 \))
			((CLK) (\Mclk_II/FCLK \))
			((SET) (Gnd))
			((RST) (MTRpwr_MC_tsimcreated_prld_))
			((O) (\MTRpwr_MC.Q_tsimrenamed_net_ \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \MTRpwr_MC.D_1550 \ 0 15486 (_entity .  X_XOR2)
		(_port
			((I0) (\MTRpwr_MC.D1 \))
			((I1) (\MTRpwr_MC.D2 \))
			((O) (\MTRpwr_MC.D \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \MTRpwr_MC.D1_1551 \ 0 15491 (_entity .  X_AND2)
		(_port
			((I0) (\AD<7>_II/UIM \))
			((I1) (\AD<7>_II/UIM \))
			((O) (\MTRpwr_MC.D1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \MTRpwr_MC.D2_1552 \ 0 15496 (_entity .  X_ZERO)
		(_port
			((O) (\MTRpwr_MC.D2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \MTRpwrn_MC.Q_1553 \ 0 15499 (_entity .  X_BUF)
		(_port
			((I) (\MTRpwrn_MC.Q_tsimrenamed_net_ \))
			((O) (\MTRpwrn_MC.Q \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation MTRpwrn_MC_tsimcreated_prld__1554 0 15503 (_entity .  X_OR2)
		(_port
			((I0) (\FOOBAR4__ctinst/7 \))
			((I1) (PRLD))
			((O) (MTRpwrn_MC_tsimcreated_prld_))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \MTRpwrn_MC.REG \ 0 15508 (_entity .  X_FF)
		(_port
			((I) (\MTRpwrn_MC.D \))
			((CE) (\FOOBAR7__ctinst/4 \))
			((CLK) (\Mclk_II/FCLK \))
			((SET) (MTRpwrn_MC_tsimcreated_prld_))
			((RST) (Gnd))
			((O) (\MTRpwrn_MC.Q_tsimrenamed_net_ \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \MTRpwrn_MC.D_1555 \ 0 15516 (_entity .  X_XOR2)
		(_port
			((I0) (\NlwInverterSignal_MTRpwrn_MC.D/IN0 \))
			((I1) (\MTRpwrn_MC.D2 \))
			((O) (\MTRpwrn_MC.D \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \MTRpwrn_MC.D1_1556 \ 0 15521 (_entity .  X_AND2)
		(_port
			((I0) (\AD<7>_II/UIM \))
			((I1) (\AD<7>_II/UIM \))
			((O) (\MTRpwrn_MC.D1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \MTRpwrn_MC.D2_1557 \ 0 15526 (_entity .  X_ZERO)
		(_port
			((O) (\MTRpwrn_MC.D2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \MTXI_MC.Q_1558 \ 0 15529 (_entity .  X_BUF)
		(_port
			((I) (\MTXI_MC.Q_tsimrenamed_net_ \))
			((O) (\MTXI_MC.Q \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \MTXI_MC.Q_tsimrenamed_net__1559 \ 0 15533 (_entity .  X_BUF)
		(_port
			((I) (\MTXI_MC.D \))
			((O) (\MTXI_MC.Q_tsimrenamed_net_ \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \MTXI_MC.D_1560 \ 0 15537 (_entity .  X_XOR2)
		(_port
			((I0) (\MTXI_MC.D1 \))
			((I1) (\MTXI_MC.D2 \))
			((O) (\MTXI_MC.D \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \MTXI_MC.D1_1561 \ 0 15542 (_entity .  X_AND2)
		(_port
			((I0) (\TXI_II/UIM \))
			((I1) (\TXI_II/UIM \))
			((O) (\MTXI_MC.D1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \MTXI_MC.D2_1562 \ 0 15547 (_entity .  X_ZERO)
		(_port
			((O) (\MTXI_MC.D2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \PAH0_MC.Q_1563 \ 0 15550 (_entity .  X_BUF)
		(_port
			((I) (\PAH0_MC.Q_tsimrenamed_net_ \))
			((O) (\PAH0_MC.Q \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \PAH0_MC.Q_tsimrenamed_net__1564 \ 0 15554 (_entity .  X_BUF)
		(_port
			((I) (\PAH0_MC.D \))
			((O) (\PAH0_MC.Q_tsimrenamed_net_ \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \PAH0_MC.D_1565 \ 0 15558 (_entity .  X_XOR2)
		(_port
			((I0) (\PAH0_MC.D1 \))
			((I1) (\PAH0_MC.D2 \))
			((O) (\PAH0_MC.D \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \PAH0_MC.D1_1566 \ 0 15563 (_entity .  X_AND4)
		(_port
			((I0) (\NlwInverterSignal_PAH0_MC.D1/IN0 \))
			((I1) (\NlwInverterSignal_PAH0_MC.D1/IN1 \))
			((I2) (\PWM1_II/UIM \))
			((I3) (\NlwInverterSignal_PAH0_MC.D1/IN3 \))
			((O) (\PAH0_MC.D1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \PAH0_MC.D2_1567 \ 0 15570 (_entity .  X_ZERO)
		(_port
			((O) (\PAH0_MC.D2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation NET3248_1568 0 15573 (_entity .  X_BUF)
		(_port
			((I) (\NET3248_MC.Q \))
			((O) (NET3248))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NET3248_MC.REG \ 0 15577 (_entity .  X_FF)
		(_port
			((I) (\NET3248_MC.D \))
			((CE) (Vcc))
			((CLK) (\Mclk_II/FCLK \))
			((SET) (Gnd))
			((RST) (PRLD))
			((O) (\NET3248_MC.Q \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NET3248_MC.D_1569 \ 0 15585 (_entity .  X_XOR2)
		(_port
			((I0) (\NET3248_MC.D1 \))
			((I1) (\NET3248_MC.D2 \))
			((O) (\NET3248_MC.D \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NET3248_MC.D1_1570 \ 0 15590 (_entity .  X_ZERO)
		(_port
			((O) (\NET3248_MC.D1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NET3248_MC.D2_PT_0_1571 \ 0 15593 (_entity .  X_AND3)
		(_port
			((I0) (\NlwInverterSignal_NET3248_MC.D2_PT_0/IN0 \))
			((I1) (\NlwInverterSignal_NET3248_MC.D2_PT_0/IN1 \))
			((I2) (NET3248))
			((O) (\NET3248_MC.D2_PT_0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NET3248_MC.D2_PT_1_1572 \ 0 15599 (_entity .  X_AND3)
		(_port
			((I0) (\NlwInverterSignal_NET3248_MC.D2_PT_1/IN0 \))
			((I1) (\DIR0_II/UIM \))
			((I2) (\NlwInverterSignal_NET3248_MC.D2_PT_1/IN2 \))
			((O) (\NET3248_MC.D2_PT_1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NET3248_MC.D2_PT_2_1573 \ 0 15605 (_entity .  X_AND3)
		(_port
			((I0) (\NlwInverterSignal_NET3248_MC.D2_PT_2/IN0 \))
			((I1) (\NlwInverterSignal_NET3248_MC.D2_PT_2/IN1 \))
			((I2) (\NlwInverterSignal_NET3248_MC.D2_PT_2/IN2 \))
			((O) (\NET3248_MC.D2_PT_2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NET3248_MC.D2_1574 \ 0 15611 (_entity .  X_OR3)
		(_port
			((I0) (\NET3248_MC.D2_PT_0 \))
			((I1) (\NET3248_MC.D2_PT_1 \))
			((I2) (\NET3248_MC.D2_PT_2 \))
			((O) (\NET3248_MC.D2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \PAH1_MC.Q_1575 \ 0 15617 (_entity .  X_BUF)
		(_port
			((I) (\PAH1_MC.Q_tsimrenamed_net_ \))
			((O) (\PAH1_MC.Q \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \PAH1_MC.Q_tsimrenamed_net__1576 \ 0 15621 (_entity .  X_BUF)
		(_port
			((I) (\PAH1_MC.D \))
			((O) (\PAH1_MC.Q_tsimrenamed_net_ \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \PAH1_MC.D_1577 \ 0 15625 (_entity .  X_XOR2)
		(_port
			((I0) (\PAH1_MC.D1 \))
			((I1) (\PAH1_MC.D2 \))
			((O) (\PAH1_MC.D \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \PAH1_MC.D1_1578 \ 0 15630 (_entity .  X_ZERO)
		(_port
			((O) (\PAH1_MC.D1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \PAH1_MC.D2_PT_0_1579 \ 0 15633 (_entity .  X_AND4)
		(_port
			((I0) (\NlwInverterSignal_PAH1_MC.D2_PT_0/IN0 \))
			((I1) (\NlwInverterSignal_PAH1_MC.D2_PT_0/IN1 \))
			((I2) (\DIR1_II/UIM \))
			((I3) (\PWM2_II/UIM \))
			((O) (\PAH1_MC.D2_PT_0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \PAH1_MC.D2_PT_1_1580 \ 0 15640 (_entity .  X_AND4)
		(_port
			((I0) (\NlwInverterSignal_PAH1_MC.D2_PT_1/IN0 \))
			((I1) (\NlwInverterSignal_PAH1_MC.D2_PT_1/IN1 \))
			((I2) (\NlwInverterSignal_PAH1_MC.D2_PT_1/IN2 \))
			((I3) (\NlwInverterSignal_PAH1_MC.D2_PT_1/IN3 \))
			((O) (\PAH1_MC.D2_PT_1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \PAH1_MC.D2_1581 \ 0 15647 (_entity .  X_OR2)
		(_port
			((I0) (\PAH1_MC.D2_PT_0 \))
			((I1) (\PAH1_MC.D2_PT_1 \))
			((O) (\PAH1_MC.D2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \PAL0_MC.Q_1582 \ 0 15652 (_entity .  X_BUF)
		(_port
			((I) (\PAL0_MC.Q_tsimrenamed_net_ \))
			((O) (\PAL0_MC.Q \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \PAL0_MC.Q_tsimrenamed_net__1583 \ 0 15656 (_entity .  X_BUF)
		(_port
			((I) (\PAL0_MC.D \))
			((O) (\PAL0_MC.Q_tsimrenamed_net_ \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \PAL0_MC.D_1584 \ 0 15660 (_entity .  X_XOR2)
		(_port
			((I0) (\PAL0_MC.D1 \))
			((I1) (\PAL0_MC.D2 \))
			((O) (\PAL0_MC.D \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \PAL0_MC.D1_1585 \ 0 15665 (_entity .  X_ZERO)
		(_port
			((O) (\PAL0_MC.D1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \PAL0_MC.D2_PT_0_1586 \ 0 15668 (_entity .  X_AND4)
		(_port
			((I0) (\NlwInverterSignal_PAL0_MC.D2_PT_0/IN0 \))
			((I1) (\DIR0_II/UIM \))
			((I2) (\NlwInverterSignal_PAL0_MC.D2_PT_0/IN2 \))
			((I3) (\NlwInverterSignal_PAL0_MC.D2_PT_0/IN3 \))
			((O) (\PAL0_MC.D2_PT_0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \PAL0_MC.D2_PT_1_1587 \ 0 15675 (_entity .  X_AND4)
		(_port
			((I0) (\NlwInverterSignal_PAL0_MC.D2_PT_1/IN0 \))
			((I1) (\NlwInverterSignal_PAL0_MC.D2_PT_1/IN1 \))
			((I2) (\PWM1_II/UIM \))
			((I3) (\NlwInverterSignal_PAL0_MC.D2_PT_1/IN3 \))
			((O) (\PAL0_MC.D2_PT_1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \PAL0_MC.D2_1588 \ 0 15682 (_entity .  X_OR2)
		(_port
			((I0) (\PAL0_MC.D2_PT_0 \))
			((I1) (\PAL0_MC.D2_PT_1 \))
			((O) (\PAL0_MC.D2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \PAL1_MC.Q_1589 \ 0 15687 (_entity .  X_BUF)
		(_port
			((I) (\PAL1_MC.Q_tsimrenamed_net_ \))
			((O) (\PAL1_MC.Q \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \PAL1_MC.Q_tsimrenamed_net__1590 \ 0 15691 (_entity .  X_BUF)
		(_port
			((I) (\PAL1_MC.D \))
			((O) (\PAL1_MC.Q_tsimrenamed_net_ \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \PAL1_MC.D_1591 \ 0 15695 (_entity .  X_XOR2)
		(_port
			((I0) (\PAL1_MC.D1 \))
			((I1) (\PAL1_MC.D2 \))
			((O) (\PAL1_MC.D \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \PAL1_MC.D1_1592 \ 0 15700 (_entity .  X_AND4)
		(_port
			((I0) (\NlwInverterSignal_PAL1_MC.D1/IN0 \))
			((I1) (\NlwInverterSignal_PAL1_MC.D1/IN1 \))
			((I2) (\DIR1_II/UIM \))
			((I3) (\PWM2_II/UIM \))
			((O) (\PAL1_MC.D1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \PAL1_MC.D2_1593 \ 0 15707 (_entity .  X_ZERO)
		(_port
			((O) (\PAL1_MC.D2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \PBH0_MC.Q_1594 \ 0 15710 (_entity .  X_BUF)
		(_port
			((I) (\PBH0_MC.Q_tsimrenamed_net_ \))
			((O) (\PBH0_MC.Q \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \PBH0_MC.Q_tsimrenamed_net__1595 \ 0 15714 (_entity .  X_BUF)
		(_port
			((I) (\PBH0_MC.D \))
			((O) (\PBH0_MC.Q_tsimrenamed_net_ \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \PBH0_MC.D_1596 \ 0 15718 (_entity .  X_XOR2)
		(_port
			((I0) (\PBH0_MC.D1 \))
			((I1) (\PBH0_MC.D2 \))
			((O) (\PBH0_MC.D \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \PBH0_MC.D1_1597 \ 0 15723 (_entity .  X_AND4)
		(_port
			((I0) (\NlwInverterSignal_PBH0_MC.D1/IN0 \))
			((I1) (\DIR0_II/UIM \))
			((I2) (\PWM1_II/UIM \))
			((I3) (\NlwInverterSignal_PBH0_MC.D1/IN3 \))
			((O) (\PBH0_MC.D1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \PBH0_MC.D2_1598 \ 0 15730 (_entity .  X_ZERO)
		(_port
			((O) (\PBH0_MC.D2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \PBH1_MC.Q_1599 \ 0 15733 (_entity .  X_BUF)
		(_port
			((I) (\PBH1_MC.Q_tsimrenamed_net_ \))
			((O) (\PBH1_MC.Q \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \PBH1_MC.Q_tsimrenamed_net__1600 \ 0 15737 (_entity .  X_BUF)
		(_port
			((I) (\PBH1_MC.D \))
			((O) (\PBH1_MC.Q_tsimrenamed_net_ \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \PBH1_MC.D_1601 \ 0 15741 (_entity .  X_XOR2)
		(_port
			((I0) (\PBH1_MC.D1 \))
			((I1) (\PBH1_MC.D2 \))
			((O) (\PBH1_MC.D \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \PBH1_MC.D1_1602 \ 0 15746 (_entity .  X_ZERO)
		(_port
			((O) (\PBH1_MC.D1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \PBH1_MC.D2_PT_0_1603 \ 0 15749 (_entity .  X_AND4)
		(_port
			((I0) (\NlwInverterSignal_PBH1_MC.D2_PT_0/IN0 \))
			((I1) (\NlwInverterSignal_PBH1_MC.D2_PT_0/IN1 \))
			((I2) (\DIR1_II/UIM \))
			((I3) (\NlwInverterSignal_PBH1_MC.D2_PT_0/IN3 \))
			((O) (\PBH1_MC.D2_PT_0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \PBH1_MC.D2_PT_1_1604 \ 0 15756 (_entity .  X_AND4)
		(_port
			((I0) (\NlwInverterSignal_PBH1_MC.D2_PT_1/IN0 \))
			((I1) (\NlwInverterSignal_PBH1_MC.D2_PT_1/IN1 \))
			((I2) (\NlwInverterSignal_PBH1_MC.D2_PT_1/IN2 \))
			((I3) (\PWM2_II/UIM \))
			((O) (\PBH1_MC.D2_PT_1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \PBH1_MC.D2_1605 \ 0 15763 (_entity .  X_OR2)
		(_port
			((I0) (\PBH1_MC.D2_PT_0 \))
			((I1) (\PBH1_MC.D2_PT_1 \))
			((O) (\PBH1_MC.D2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \PBL0_MC.Q_1606 \ 0 15768 (_entity .  X_BUF)
		(_port
			((I) (\PBL0_MC.Q_tsimrenamed_net_ \))
			((O) (\PBL0_MC.Q \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \PBL0_MC.Q_tsimrenamed_net__1607 \ 0 15772 (_entity .  X_BUF)
		(_port
			((I) (\PBL0_MC.D \))
			((O) (\PBL0_MC.Q_tsimrenamed_net_ \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \PBL0_MC.D_1608 \ 0 15776 (_entity .  X_XOR2)
		(_port
			((I0) (\PBL0_MC.D1 \))
			((I1) (\PBL0_MC.D2 \))
			((O) (\PBL0_MC.D \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \PBL0_MC.D1_1609 \ 0 15781 (_entity .  X_ZERO)
		(_port
			((O) (\PBL0_MC.D1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \PBL0_MC.D2_PT_0_1610 \ 0 15784 (_entity .  X_AND4)
		(_port
			((I0) (\NlwInverterSignal_PBL0_MC.D2_PT_0/IN0 \))
			((I1) (\DIR0_II/UIM \))
			((I2) (\PWM1_II/UIM \))
			((I3) (\NlwInverterSignal_PBL0_MC.D2_PT_0/IN3 \))
			((O) (\PBL0_MC.D2_PT_0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \PBL0_MC.D2_PT_1_1611 \ 0 15791 (_entity .  X_AND4)
		(_port
			((I0) (\NlwInverterSignal_PBL0_MC.D2_PT_1/IN0 \))
			((I1) (\NlwInverterSignal_PBL0_MC.D2_PT_1/IN1 \))
			((I2) (\NlwInverterSignal_PBL0_MC.D2_PT_1/IN2 \))
			((I3) (\NlwInverterSignal_PBL0_MC.D2_PT_1/IN3 \))
			((O) (\PBL0_MC.D2_PT_1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \PBL0_MC.D2_1612 \ 0 15798 (_entity .  X_OR2)
		(_port
			((I0) (\PBL0_MC.D2_PT_0 \))
			((I1) (\PBL0_MC.D2_PT_1 \))
			((O) (\PBL0_MC.D2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \PBL1_MC.Q_1613 \ 0 15803 (_entity .  X_BUF)
		(_port
			((I) (\PBL1_MC.Q_tsimrenamed_net_ \))
			((O) (\PBL1_MC.Q \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \PBL1_MC.Q_tsimrenamed_net__1614 \ 0 15807 (_entity .  X_BUF)
		(_port
			((I) (\PBL1_MC.D \))
			((O) (\PBL1_MC.Q_tsimrenamed_net_ \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \PBL1_MC.D_1615 \ 0 15811 (_entity .  X_XOR2)
		(_port
			((I0) (\PBL1_MC.D1 \))
			((I1) (\PBL1_MC.D2 \))
			((O) (\PBL1_MC.D \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \PBL1_MC.D1_1616 \ 0 15816 (_entity .  X_AND4)
		(_port
			((I0) (\NlwInverterSignal_PBL1_MC.D1/IN0 \))
			((I1) (\NlwInverterSignal_PBL1_MC.D1/IN1 \))
			((I2) (\NlwInverterSignal_PBL1_MC.D1/IN2 \))
			((I3) (\PWM2_II/UIM \))
			((O) (\PBL1_MC.D1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \PBL1_MC.D2_1617 \ 0 15823 (_entity .  X_ZERO)
		(_port
			((O) (\PBL1_MC.D2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \outDATA<0>\\$WA0.UIM_1618 \ 0 15826 (_entity .  X_BUF)
		(_port
			((I) (\outDATA<0>\\$WA0.UIM_MC.Q \))
			((O) (\outDATA<0>\\$WA0.UIM \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \outDATA<0>\\$WA0.UIM_MC.Q_1619 \ 0 15830 (_entity .  X_BUF)
		(_port
			((I) (\outDATA<0>\\$WA0.UIM_MC.D \))
			((O) (\outDATA<0>\\$WA0.UIM_MC.Q \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \outDATA<0>\\$WA0.UIM_MC.D_1620 \ 0 15834 (_entity .  X_XOR2)
		(_port
			((I0) (\outDATA<0>\\$WA0.UIM_MC.D1 \))
			((I1) (\outDATA<0>\\$WA0.UIM_MC.D2 \))
			((O) (\outDATA<0>\\$WA0.UIM_MC.D \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \outDATA<0>\\$WA0.UIM_MC.D1_1621 \ 0 15839 (_entity .  X_AND2)
		(_port
			((I0) (U11_U3_counterr(0)))
			((I1) (U11_U3_counterr(0)))
			((O) (\outDATA<0>\\$WA0.UIM_MC.D1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \outDATA<0>\\$WA0.UIM_MC.D2_1622 \ 0 15844 (_entity .  X_ZERO)
		(_port
			((O) (\outDATA<0>\\$WA0.UIM_MC.D2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \outDATA<0>\\$WA1.UIM_1623 \ 0 15847 (_entity .  X_BUF)
		(_port
			((I) (\outDATA<0>\\$WA1.UIM_MC.Q \))
			((O) (\outDATA<0>\\$WA1.UIM \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \outDATA<0>\\$WA1.UIM_MC.Q_1624 \ 0 15851 (_entity .  X_BUF)
		(_port
			((I) (\outDATA<0>\\$WA1.UIM_MC.D \))
			((O) (\outDATA<0>\\$WA1.UIM_MC.Q \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \outDATA<0>\\$WA1.UIM_MC.D_1625 \ 0 15855 (_entity .  X_XOR2)
		(_port
			((I0) (\outDATA<0>\\$WA1.UIM_MC.D1 \))
			((I1) (\outDATA<0>\\$WA1.UIM_MC.D2 \))
			((O) (\outDATA<0>\\$WA1.UIM_MC.D \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \outDATA<0>\\$WA1.UIM_MC.D1_1626 \ 0 15860 (_entity .  X_AND2)
		(_port
			((I0) (\I2CS<0>_II/UIM \))
			((I1) (\I2CS<0>_II/UIM \))
			((O) (\outDATA<0>\\$WA1.UIM_MC.D1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \outDATA<0>\\$WA1.UIM_MC.D2_1627 \ 0 15865 (_entity .  X_ZERO)
		(_port
			((O) (\outDATA<0>\\$WA1.UIM_MC.D2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \outDATA<0>\\$WA2.UIM_1628 \ 0 15868 (_entity .  X_BUF)
		(_port
			((I) (\outDATA<0>\\$WA2.UIM_MC.Q \))
			((O) (\outDATA<0>\\$WA2.UIM \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \outDATA<0>\\$WA2.UIM_MC.Q_1629 \ 0 15872 (_entity .  X_BUF)
		(_port
			((I) (\outDATA<0>\\$WA2.UIM_MC.D \))
			((O) (\outDATA<0>\\$WA2.UIM_MC.Q \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \outDATA<0>\\$WA2.UIM_MC.D_1630 \ 0 15876 (_entity .  X_XOR2)
		(_port
			((I0) (\outDATA<0>\\$WA2.UIM_MC.D1 \))
			((I1) (\outDATA<0>\\$WA2.UIM_MC.D2 \))
			((O) (\outDATA<0>\\$WA2.UIM_MC.D \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \outDATA<0>\\$WA2.UIM_MC.D1_1631 \ 0 15881 (_entity .  X_AND2)
		(_port
			((I0) (\RLS0_II/UIM \))
			((I1) (\RLS0_II/UIM \))
			((O) (\outDATA<0>\\$WA2.UIM_MC.D1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \outDATA<0>\\$WA2.UIM_MC.D2_1632 \ 0 15886 (_entity .  X_ZERO)
		(_port
			((O) (\outDATA<0>\\$WA2.UIM_MC.D2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \outDATA<0>\\$WA3.UIM_1633 \ 0 15889 (_entity .  X_BUF)
		(_port
			((I) (\outDATA<0>\\$WA3.UIM_MC.Q \))
			((O) (\outDATA<0>\\$WA3.UIM \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \outDATA<0>\\$WA3.UIM_MC.Q_1634 \ 0 15893 (_entity .  X_BUF)
		(_port
			((I) (\outDATA<0>\\$WA3.UIM_MC.D \))
			((O) (\outDATA<0>\\$WA3.UIM_MC.Q \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \outDATA<0>\\$WA3.UIM_MC.D_1635 \ 0 15897 (_entity .  X_XOR2)
		(_port
			((I0) (\outDATA<0>\\$WA3.UIM_MC.D1 \))
			((I1) (\outDATA<0>\\$WA3.UIM_MC.D2 \))
			((O) (\outDATA<0>\\$WA3.UIM_MC.D \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \outDATA<0>\\$WA3.UIM_MC.D1_1636 \ 0 15902 (_entity .  X_ZERO)
		(_port
			((O) (\outDATA<0>\\$WA3.UIM_MC.D1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \outDATA<0>\\$WA3.UIM_MC.D2_PT_0_1637 \ 0 15905 (_entity .  X_AND2)
		(_port
			((I0) (NET2528))
			((I1) (\U4/Flgreg \(0)))
			((O) (\outDATA<0>\\$WA3.UIM_MC.D2_PT_0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \outDATA<0>\\$WA3.UIM_MC.D2_PT_1_1638 \ 0 15910 (_entity .  X_AND2)
		(_port
			((I0) (\NlwInverterSignal_outDATA<0>\\$WA3.UIM_MC.D2_PT_1/IN0 \))
			((I1) (\Home033FLG_II/UIM \))
			((O) (\outDATA<0>\\$WA3.UIM_MC.D2_PT_1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \outDATA<0>\\$WA3.UIM_MC.D2_1639 \ 0 15915 (_entity .  X_OR2)
		(_port
			((I0) (\outDATA<0>\\$WA3.UIM_MC.D2_PT_0 \))
			((I1) (\outDATA<0>\\$WA3.UIM_MC.D2_PT_1 \))
			((O) (\outDATA<0>\\$WA3.UIM_MC.D2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \outDATA<0>\\$WA5.UIM_1640 \ 0 15920 (_entity .  X_BUF)
		(_port
			((I) (\outDATA<0>\\$WA5.UIM_MC.Q \))
			((O) (\outDATA<0>\\$WA5.UIM \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \outDATA<0>\\$WA5.UIM_MC.Q_1641 \ 0 15924 (_entity .  X_BUF)
		(_port
			((I) (\outDATA<0>\\$WA5.UIM_MC.D \))
			((O) (\outDATA<0>\\$WA5.UIM_MC.Q \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \outDATA<0>\\$WA5.UIM_MC.D_1642 \ 0 15928 (_entity .  X_XOR2)
		(_port
			((I0) (\outDATA<0>\\$WA5.UIM_MC.D1 \))
			((I1) (\outDATA<0>\\$WA5.UIM_MC.D2 \))
			((O) (\outDATA<0>\\$WA5.UIM_MC.D \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \outDATA<0>\\$WA5.UIM_MC.D1_1643 \ 0 15933 (_entity .  X_ZERO)
		(_port
			((O) (\outDATA<0>\\$WA5.UIM_MC.D1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \outDATA<0>\\$WA5.UIM_MC.D2_PT_0_1644 \ 0 15936 (_entity .  X_AND2)
		(_port
			((I0) (N_PZ_966))
			((I1) (\U1/U3/holdingreg \(0)))
			((O) (\outDATA<0>\\$WA5.UIM_MC.D2_PT_0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \outDATA<0>\\$WA5.UIM_MC.D2_PT_1_1645 \ 0 15941 (_entity .  X_AND2)
		(_port
			((I0) (N_PZ_1002))
			((I1) (\U1/U3/holdingreg \(16)))
			((O) (\outDATA<0>\\$WA5.UIM_MC.D2_PT_1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \outDATA<0>\\$WA5.UIM_MC.D2_PT_2_1646 \ 0 15946 (_entity .  X_AND2)
		(_port
			((I0) (N_PZ_1061))
			((I1) (\U1/U3/holdingreg \(8)))
			((O) (\outDATA<0>\\$WA5.UIM_MC.D2_PT_2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \outDATA<0>\\$WA5.UIM_MC.D2_1647 \ 0 15951 (_entity .  X_OR3)
		(_port
			((I0) (\outDATA<0>\\$WA5.UIM_MC.D2_PT_0 \))
			((I1) (\outDATA<0>\\$WA5.UIM_MC.D2_PT_1 \))
			((I2) (\outDATA<0>\\$WA5.UIM_MC.D2_PT_2 \))
			((O) (\outDATA<0>\\$WA5.UIM_MC.D2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U3/holdingreg<0> \ 0 15957 (_entity .  X_BUF)
		(_port
			((I) (\U1/U3/holdingreg<0>_MC.Q \))
			((O) (\U1/U3/holdingreg \(0)))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U3/holdingreg<0>_MC.REG \ 0 15961 (_entity .  X_FF)
		(_port
			((I) (\U1/U3/holdingreg<0>_MC.D \))
			((CE) (Vcc))
			((CLK) (\U1/U3/holdingreg<0>_MC.REG_tsimcreated_inv_Mclk_II/FCLK \))
			((SET) (Gnd))
			((RST) (PRLD))
			((O) (\U1/U3/holdingreg<0>_MC.Q \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U3/holdingreg<0>_MC.REG_tsimcreated_inv_Mclk_II/FCLK_1648 \ 0 15969 (_entity .  X_INV)
		(_port
			((I) (\Mclk_II/FCLK \))
			((O) (\U1/U3/holdingreg<0>_MC.REG_tsimcreated_inv_Mclk_II/FCLK \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U3/holdingreg<0>_MC.D_1649 \ 0 15973 (_entity .  X_XOR2)
		(_port
			((I0) (\U1/U3/holdingreg<0>_MC.D1 \))
			((I1) (\U1/U3/holdingreg<0>_MC.D2 \))
			((O) (\U1/U3/holdingreg<0>_MC.D \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U3/holdingreg<0>_MC.D1_1650 \ 0 15978 (_entity .  X_ZERO)
		(_port
			((O) (\U1/U3/holdingreg<0>_MC.D1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U3/holdingreg<0>_MC.D2_PT_0_1651 \ 0 15981 (_entity .  X_AND2)
		(_port
			((I0) (N_PZ_986))
			((I1) (\U1/Channel1 \(0)))
			((O) (\U1/U3/holdingreg<0>_MC.D2_PT_0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U3/holdingreg<0>_MC.D2_PT_1_1652 \ 0 15986 (_entity .  X_AND3)
		(_port
			((I0) (\NlwInverterSignal_U1/U3/holdingreg<0>_MC.D2_PT_1/IN0 \))
			((I1) (\U1/U3/RDedge \))
			((I2) (\U1/U3/holdingreg \(0)))
			((O) (\U1/U3/holdingreg<0>_MC.D2_PT_1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U3/holdingreg<0>_MC.D2_PT_2_1653 \ 0 15992 (_entity .  X_AND16)
		(_port
			((I0) (\WR_II/UIM \))
			((I1) (\NlwInverterSignal_U1/U3/holdingreg<0>_MC.D2_PT_2/IN1 \))
			((I2) (U2_ADDR_reg(1)))
			((I3) (U2_ADDR_reg(0)))
			((I4) (N_PZ_931))
			((I5) (U2_ADDR_reg(2)))
			((I6) (\NlwInverterSignal_U1/U3/holdingreg<0>_MC.D2_PT_2/IN6 \))
			((I7) (\NlwInverterSignal_U1/U3/holdingreg<0>_MC.D2_PT_2/IN7 \))
			((I8) (\NlwInverterSignal_U1/U3/holdingreg<0>_MC.D2_PT_2/IN8 \))
			((I9) (\U1/Channel0 \(0)))
			((I10) (Vcc))
			((I11) (Vcc))
			((I12) (Vcc))
			((I13) (Vcc))
			((I14) (Vcc))
			((I15) (Vcc))
			((O) (\U1/U3/holdingreg<0>_MC.D2_PT_2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U3/holdingreg<0>_MC.D2_1654 \ 0 16011 (_entity .  X_OR3)
		(_port
			((I0) (\U1/U3/holdingreg<0>_MC.D2_PT_0 \))
			((I1) (\U1/U3/holdingreg<0>_MC.D2_PT_1 \))
			((I2) (\U1/U3/holdingreg<0>_MC.D2_PT_2 \))
			((O) (\U1/U3/holdingreg<0>_MC.D2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U3/holdingreg<16> \ 0 16017 (_entity .  X_BUF)
		(_port
			((I) (\U1/U3/holdingreg<16>_MC.Q \))
			((O) (\U1/U3/holdingreg \(16)))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U3/holdingreg<16>_MC.REG \ 0 16021 (_entity .  X_FF)
		(_port
			((I) (\U1/U3/holdingreg<16>_MC.D \))
			((CE) (Vcc))
			((CLK) (\U1/U3/holdingreg<16>_MC.REG_tsimcreated_inv_Mclk_II/FCLK \))
			((SET) (Gnd))
			((RST) (PRLD))
			((O) (\U1/U3/holdingreg<16>_MC.Q \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U3/holdingreg<16>_MC.REG_tsimcreated_inv_Mclk_II/FCLK_1655 \ 0 16029 (_entity .  X_INV)
		(_port
			((I) (\Mclk_II/FCLK \))
			((O) (\U1/U3/holdingreg<16>_MC.REG_tsimcreated_inv_Mclk_II/FCLK \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U3/holdingreg<16>_MC.D_1656 \ 0 16033 (_entity .  X_XOR2)
		(_port
			((I0) (\U1/U3/holdingreg<16>_MC.D1 \))
			((I1) (\U1/U3/holdingreg<16>_MC.D2 \))
			((O) (\U1/U3/holdingreg<16>_MC.D \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U3/holdingreg<16>_MC.D1_1657 \ 0 16038 (_entity .  X_ZERO)
		(_port
			((O) (\U1/U3/holdingreg<16>_MC.D1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U3/holdingreg<16>_MC.D2_PT_0_1658 \ 0 16041 (_entity .  X_AND2)
		(_port
			((I0) (N_PZ_986))
			((I1) (\U1/Channel1 \(16)))
			((O) (\U1/U3/holdingreg<16>_MC.D2_PT_0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U3/holdingreg<16>_MC.D2_PT_1_1659 \ 0 16046 (_entity .  X_AND3)
		(_port
			((I0) (\NlwInverterSignal_U1/U3/holdingreg<16>_MC.D2_PT_1/IN0 \))
			((I1) (\U1/U3/RDedge \))
			((I2) (\U1/U3/holdingreg \(16)))
			((O) (\U1/U3/holdingreg<16>_MC.D2_PT_1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U3/holdingreg<16>_MC.D2_PT_2_1660 \ 0 16052 (_entity .  X_AND16)
		(_port
			((I0) (\WR_II/UIM \))
			((I1) (\NlwInverterSignal_U1/U3/holdingreg<16>_MC.D2_PT_2/IN1 \))
			((I2) (U2_ADDR_reg(1)))
			((I3) (U2_ADDR_reg(0)))
			((I4) (N_PZ_931))
			((I5) (U2_ADDR_reg(2)))
			((I6) (\NlwInverterSignal_U1/U3/holdingreg<16>_MC.D2_PT_2/IN6 \))
			((I7) (\NlwInverterSignal_U1/U3/holdingreg<16>_MC.D2_PT_2/IN7 \))
			((I8) (\NlwInverterSignal_U1/U3/holdingreg<16>_MC.D2_PT_2/IN8 \))
			((I9) (\U1/Channel0 \(16)))
			((I10) (Vcc))
			((I11) (Vcc))
			((I12) (Vcc))
			((I13) (Vcc))
			((I14) (Vcc))
			((I15) (Vcc))
			((O) (\U1/U3/holdingreg<16>_MC.D2_PT_2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U3/holdingreg<16>_MC.D2_1661 \ 0 16071 (_entity .  X_OR3)
		(_port
			((I0) (\U1/U3/holdingreg<16>_MC.D2_PT_0 \))
			((I1) (\U1/U3/holdingreg<16>_MC.D2_PT_1 \))
			((I2) (\U1/U3/holdingreg<16>_MC.D2_PT_2 \))
			((O) (\U1/U3/holdingreg<16>_MC.D2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U3/holdingreg<8> \ 0 16077 (_entity .  X_BUF)
		(_port
			((I) (\U1/U3/holdingreg<8>_MC.Q \))
			((O) (\U1/U3/holdingreg \(8)))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U3/holdingreg<8>_MC.REG \ 0 16081 (_entity .  X_FF)
		(_port
			((I) (\U1/U3/holdingreg<8>_MC.D \))
			((CE) (Vcc))
			((CLK) (\U1/U3/holdingreg<8>_MC.REG_tsimcreated_inv_Mclk_II/FCLK \))
			((SET) (Gnd))
			((RST) (PRLD))
			((O) (\U1/U3/holdingreg<8>_MC.Q \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U3/holdingreg<8>_MC.REG_tsimcreated_inv_Mclk_II/FCLK_1662 \ 0 16089 (_entity .  X_INV)
		(_port
			((I) (\Mclk_II/FCLK \))
			((O) (\U1/U3/holdingreg<8>_MC.REG_tsimcreated_inv_Mclk_II/FCLK \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U3/holdingreg<8>_MC.D_1663 \ 0 16093 (_entity .  X_XOR2)
		(_port
			((I0) (\U1/U3/holdingreg<8>_MC.D1 \))
			((I1) (\U1/U3/holdingreg<8>_MC.D2 \))
			((O) (\U1/U3/holdingreg<8>_MC.D \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U3/holdingreg<8>_MC.D1_1664 \ 0 16098 (_entity .  X_ZERO)
		(_port
			((O) (\U1/U3/holdingreg<8>_MC.D1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U3/holdingreg<8>_MC.D2_PT_0_1665 \ 0 16101 (_entity .  X_AND2)
		(_port
			((I0) (N_PZ_986))
			((I1) (\U1/Channel1 \(8)))
			((O) (\U1/U3/holdingreg<8>_MC.D2_PT_0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U3/holdingreg<8>_MC.D2_PT_1_1666 \ 0 16106 (_entity .  X_AND3)
		(_port
			((I0) (\NlwInverterSignal_U1/U3/holdingreg<8>_MC.D2_PT_1/IN0 \))
			((I1) (\U1/U3/RDedge \))
			((I2) (\U1/U3/holdingreg \(8)))
			((O) (\U1/U3/holdingreg<8>_MC.D2_PT_1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U3/holdingreg<8>_MC.D2_PT_2_1667 \ 0 16112 (_entity .  X_AND16)
		(_port
			((I0) (\WR_II/UIM \))
			((I1) (\NlwInverterSignal_U1/U3/holdingreg<8>_MC.D2_PT_2/IN1 \))
			((I2) (U2_ADDR_reg(1)))
			((I3) (U2_ADDR_reg(0)))
			((I4) (N_PZ_931))
			((I5) (U2_ADDR_reg(2)))
			((I6) (\NlwInverterSignal_U1/U3/holdingreg<8>_MC.D2_PT_2/IN6 \))
			((I7) (\NlwInverterSignal_U1/U3/holdingreg<8>_MC.D2_PT_2/IN7 \))
			((I8) (\NlwInverterSignal_U1/U3/holdingreg<8>_MC.D2_PT_2/IN8 \))
			((I9) (\U1/Channel0 \(8)))
			((I10) (Vcc))
			((I11) (Vcc))
			((I12) (Vcc))
			((I13) (Vcc))
			((I14) (Vcc))
			((I15) (Vcc))
			((O) (\U1/U3/holdingreg<8>_MC.D2_PT_2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U3/holdingreg<8>_MC.D2_1668 \ 0 16131 (_entity .  X_OR3)
		(_port
			((I0) (\U1/U3/holdingreg<8>_MC.D2_PT_0 \))
			((I1) (\U1/U3/holdingreg<8>_MC.D2_PT_1 \))
			((I2) (\U1/U3/holdingreg<8>_MC.D2_PT_2 \))
			((O) (\U1/U3/holdingreg<8>_MC.D2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \outDATA<0>\\$WA4.UIM_1669 \ 0 16137 (_entity .  X_BUF)
		(_port
			((I) (\outDATA<0>\\$WA4.UIM_MC.Q \))
			((O) (\outDATA<0>\\$WA4.UIM \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \outDATA<0>\\$WA4.UIM_MC.Q_1670 \ 0 16141 (_entity .  X_BUF)
		(_port
			((I) (\outDATA<0>\\$WA4.UIM_MC.D \))
			((O) (\outDATA<0>\\$WA4.UIM_MC.Q \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \outDATA<0>\\$WA4.UIM_MC.D_1671 \ 0 16145 (_entity .  X_XOR2)
		(_port
			((I0) (\outDATA<0>\\$WA4.UIM_MC.D1 \))
			((I1) (\outDATA<0>\\$WA4.UIM_MC.D2 \))
			((O) (\outDATA<0>\\$WA4.UIM_MC.D \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \outDATA<0>\\$WA4.UIM_MC.D1_1672 \ 0 16150 (_entity .  X_ZERO)
		(_port
			((O) (\outDATA<0>\\$WA4.UIM_MC.D1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \outDATA<0>\\$WA4.UIM_MC.D2_PT_0_1673 \ 0 16153 (_entity .  X_AND2)
		(_port
			((I0) (N_PZ_1003))
			((I1) (\U1/U4/Latch1r \(8)))
			((O) (\outDATA<0>\\$WA4.UIM_MC.D2_PT_0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \outDATA<0>\\$WA4.UIM_MC.D2_PT_1_1674 \ 0 16158 (_entity .  X_AND8)
		(_port
			((I0) (\WR_II/UIM \))
			((I1) (\NlwInverterSignal_outDATA<0>\\$WA4.UIM_MC.D2_PT_1/IN1 \))
			((I2) (U2_ADDR_reg(1)))
			((I3) (U2_ADDR_reg(0)))
			((I4) (N_PZ_931))
			((I5) (\NlwInverterSignal_outDATA<0>\\$WA4.UIM_MC.D2_PT_1/IN5 \))
			((I6) (U2_ADDR_reg(3)))
			((I7) (\U1/U4/Latch0r \(8)))
			((O) (\outDATA<0>\\$WA4.UIM_MC.D2_PT_1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \outDATA<0>\\$WA4.UIM_MC.D2_PT_2_1675 \ 0 16169 (_entity .  X_AND8)
		(_port
			((I0) (\WR_II/UIM \))
			((I1) (\NlwInverterSignal_outDATA<0>\\$WA4.UIM_MC.D2_PT_2/IN1 \))
			((I2) (U2_ADDR_reg(1)))
			((I3) (\NlwInverterSignal_outDATA<0>\\$WA4.UIM_MC.D2_PT_2/IN3 \))
			((I4) (N_PZ_931))
			((I5) (\NlwInverterSignal_outDATA<0>\\$WA4.UIM_MC.D2_PT_2/IN5 \))
			((I6) (U2_ADDR_reg(3)))
			((I7) (\U1/U4/Latch0r \(0)))
			((O) (\outDATA<0>\\$WA4.UIM_MC.D2_PT_2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \outDATA<0>\\$WA4.UIM_MC.D2_PT_3_1676 \ 0 16180 (_entity .  X_AND8)
		(_port
			((I0) (\WR_II/UIM \))
			((I1) (\NlwInverterSignal_outDATA<0>\\$WA4.UIM_MC.D2_PT_3/IN1 \))
			((I2) (\NlwInverterSignal_outDATA<0>\\$WA4.UIM_MC.D2_PT_3/IN2 \))
			((I3) (\NlwInverterSignal_outDATA<0>\\$WA4.UIM_MC.D2_PT_3/IN3 \))
			((I4) (N_PZ_931))
			((I5) (U2_ADDR_reg(2)))
			((I6) (U2_ADDR_reg(3)))
			((I7) (\U1/U4/Latch1r \(0)))
			((O) (\outDATA<0>\\$WA4.UIM_MC.D2_PT_3 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \outDATA<0>\\$WA4.UIM_MC.D2_1677 \ 0 16191 (_entity .  X_OR4)
		(_port
			((I0) (\outDATA<0>\\$WA4.UIM_MC.D2_PT_0 \))
			((I1) (\outDATA<0>\\$WA4.UIM_MC.D2_PT_1 \))
			((I2) (\outDATA<0>\\$WA4.UIM_MC.D2_PT_2 \))
			((I3) (\outDATA<0>\\$WA4.UIM_MC.D2_PT_3 \))
			((O) (\outDATA<0>\\$WA4.UIM_MC.D2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U4/Latch0r<0> \ 0 16198 (_entity .  X_BUF)
		(_port
			((I) (\U1/U4/Latch0r<0>_MC.Q \))
			((O) (\U1/U4/Latch0r \(0)))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U4/Latch0r<0>_MC.REG \ 0 16202 (_entity .  X_FF)
		(_port
			((I) (\U1/U4/Latch0r<0>_MC.D \))
			((CE) (Vcc))
			((CLK) (\U1/U4/Latch0r<0>_MC.REG_tsimcreated_inv_Mclk_II/FCLK \))
			((SET) (Gnd))
			((RST) (PRLD))
			((O) (\U1/U4/Latch0r<0>_MC.Q \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U4/Latch0r<0>_MC.REG_tsimcreated_inv_Mclk_II/FCLK_1678 \ 0 16210 (_entity .  X_INV)
		(_port
			((I) (\Mclk_II/FCLK \))
			((O) (\U1/U4/Latch0r<0>_MC.REG_tsimcreated_inv_Mclk_II/FCLK \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U4/Latch0r<0>_MC.D_1679 \ 0 16214 (_entity .  X_XOR2)
		(_port
			((I0) (\U1/U4/Latch0r<0>_MC.D1 \))
			((I1) (\U1/U4/Latch0r<0>_MC.D2 \))
			((O) (\U1/U4/Latch0r<0>_MC.D \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U4/Latch0r<0>_MC.D1_1680 \ 0 16219 (_entity .  X_ZERO)
		(_port
			((O) (\U1/U4/Latch0r<0>_MC.D1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U4/Latch0r<0>_MC.D2_PT_0_1681 \ 0 16222 (_entity .  X_AND2)
		(_port
			((I0) (N_PZ_1059))
			((I1) (\U1/U4/Latch0r \(0)))
			((O) (\U1/U4/Latch0r<0>_MC.D2_PT_0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U4/Latch0r<0>_MC.D2_PT_1_1682 \ 0 16227 (_entity .  X_AND3)
		(_port
			((I0) (\NlwInverterSignal_U1/U4/Latch0r<0>_MC.D2_PT_1/IN0 \))
			((I1) (\U1/Channel0 \(0)))
			((I2) (\NlwInverterSignal_U1/U4/Latch0r<0>_MC.D2_PT_1/IN2 \))
			((O) (\U1/U4/Latch0r<0>_MC.D2_PT_1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U4/Latch0r<0>_MC.D2_1683 \ 0 16233 (_entity .  X_OR2)
		(_port
			((I0) (\U1/U4/Latch0r<0>_MC.D2_PT_0 \))
			((I1) (\U1/U4/Latch0r<0>_MC.D2_PT_1 \))
			((O) (\U1/U4/Latch0r<0>_MC.D2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U4/Latch0r<8> \ 0 16238 (_entity .  X_BUF)
		(_port
			((I) (\U1/U4/Latch0r<8>_MC.Q \))
			((O) (\U1/U4/Latch0r \(8)))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U4/Latch0r<8>_MC.REG \ 0 16242 (_entity .  X_FF)
		(_port
			((I) (\U1/U4/Latch0r<8>_MC.D \))
			((CE) (Vcc))
			((CLK) (\U1/U4/Latch0r<8>_MC.REG_tsimcreated_inv_Mclk_II/FCLK \))
			((SET) (Gnd))
			((RST) (PRLD))
			((O) (\U1/U4/Latch0r<8>_MC.Q \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U4/Latch0r<8>_MC.REG_tsimcreated_inv_Mclk_II/FCLK_1684 \ 0 16250 (_entity .  X_INV)
		(_port
			((I) (\Mclk_II/FCLK \))
			((O) (\U1/U4/Latch0r<8>_MC.REG_tsimcreated_inv_Mclk_II/FCLK \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U4/Latch0r<8>_MC.D_1685 \ 0 16254 (_entity .  X_XOR2)
		(_port
			((I0) (\U1/U4/Latch0r<8>_MC.D1 \))
			((I1) (\U1/U4/Latch0r<8>_MC.D2 \))
			((O) (\U1/U4/Latch0r<8>_MC.D \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U4/Latch0r<8>_MC.D1_1686 \ 0 16259 (_entity .  X_ZERO)
		(_port
			((O) (\U1/U4/Latch0r<8>_MC.D1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U4/Latch0r<8>_MC.D2_PT_0_1687 \ 0 16262 (_entity .  X_AND2)
		(_port
			((I0) (N_PZ_1059))
			((I1) (\U1/U4/Latch0r \(8)))
			((O) (\U1/U4/Latch0r<8>_MC.D2_PT_0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U4/Latch0r<8>_MC.D2_PT_1_1688 \ 0 16267 (_entity .  X_AND3)
		(_port
			((I0) (\NlwInverterSignal_U1/U4/Latch0r<8>_MC.D2_PT_1/IN0 \))
			((I1) (\U1/Channel0 \(8)))
			((I2) (\NlwInverterSignal_U1/U4/Latch0r<8>_MC.D2_PT_1/IN2 \))
			((O) (\U1/U4/Latch0r<8>_MC.D2_PT_1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U4/Latch0r<8>_MC.D2_1689 \ 0 16273 (_entity .  X_OR2)
		(_port
			((I0) (\U1/U4/Latch0r<8>_MC.D2_PT_0 \))
			((I1) (\U1/U4/Latch0r<8>_MC.D2_PT_1 \))
			((O) (\U1/U4/Latch0r<8>_MC.D2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U4/Latch1r<0> \ 0 16278 (_entity .  X_BUF)
		(_port
			((I) (\U1/U4/Latch1r<0>_MC.Q \))
			((O) (\U1/U4/Latch1r \(0)))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U4/Latch1r<0>_MC.REG \ 0 16282 (_entity .  X_FF)
		(_port
			((I) (\U1/U4/Latch1r<0>_MC.D \))
			((CE) (Vcc))
			((CLK) (\U1/U4/Latch1r<0>_MC.REG_tsimcreated_inv_Mclk_II/FCLK \))
			((SET) (Gnd))
			((RST) (PRLD))
			((O) (\U1/U4/Latch1r<0>_MC.Q \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U4/Latch1r<0>_MC.REG_tsimcreated_inv_Mclk_II/FCLK_1690 \ 0 16290 (_entity .  X_INV)
		(_port
			((I) (\Mclk_II/FCLK \))
			((O) (\U1/U4/Latch1r<0>_MC.REG_tsimcreated_inv_Mclk_II/FCLK \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U4/Latch1r<0>_MC.D_1691 \ 0 16294 (_entity .  X_XOR2)
		(_port
			((I0) (\U1/U4/Latch1r<0>_MC.D1 \))
			((I1) (\U1/U4/Latch1r<0>_MC.D2 \))
			((O) (\U1/U4/Latch1r<0>_MC.D \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U4/Latch1r<0>_MC.D1_1692 \ 0 16299 (_entity .  X_ZERO)
		(_port
			((O) (\U1/U4/Latch1r<0>_MC.D1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U4/Latch1r<0>_MC.D2_PT_0_1693 \ 0 16302 (_entity .  X_AND2)
		(_port
			((I0) (\NlwInverterSignal_U1/U4/Latch1r<0>_MC.D2_PT_0/IN0 \))
			((I1) (\U1/Channel1 \(0)))
			((O) (\U1/U4/Latch1r<0>_MC.D2_PT_0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U4/Latch1r<0>_MC.D2_PT_1_1694 \ 0 16307 (_entity .  X_AND8)
		(_port
			((I0) (\NlwInverterSignal_U1/U4/Latch1r<0>_MC.D2_PT_1/IN0 \))
			((I1) (\RD_II/UIM \))
			((I2) (U2_ADDR_reg(1)))
			((I3) (N_PZ_931))
			((I4) (\NlwInverterSignal_U1/U4/Latch1r<0>_MC.D2_PT_1/IN4 \))
			((I5) (\NlwInverterSignal_U1/U4/Latch1r<0>_MC.D2_PT_1/IN5 \))
			((I6) (\NlwInverterSignal_U1/U4/Latch1r<0>_MC.D2_PT_1/IN6 \))
			((I7) (\U1/U4/Latch1r \(0)))
			((O) (\U1/U4/Latch1r<0>_MC.D2_PT_1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U4/Latch1r<0>_MC.D2_1695 \ 0 16318 (_entity .  X_OR2)
		(_port
			((I0) (\U1/U4/Latch1r<0>_MC.D2_PT_0 \))
			((I1) (\U1/U4/Latch1r<0>_MC.D2_PT_1 \))
			((O) (\U1/U4/Latch1r<0>_MC.D2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U4/Latch1r<8> \ 0 16323 (_entity .  X_BUF)
		(_port
			((I) (\U1/U4/Latch1r<8>_MC.Q \))
			((O) (\U1/U4/Latch1r \(8)))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U4/Latch1r<8>_MC.REG \ 0 16327 (_entity .  X_FF)
		(_port
			((I) (\U1/U4/Latch1r<8>_MC.D \))
			((CE) (Vcc))
			((CLK) (\U1/U4/Latch1r<8>_MC.REG_tsimcreated_inv_Mclk_II/FCLK \))
			((SET) (Gnd))
			((RST) (PRLD))
			((O) (\U1/U4/Latch1r<8>_MC.Q \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U4/Latch1r<8>_MC.REG_tsimcreated_inv_Mclk_II/FCLK_1696 \ 0 16335 (_entity .  X_INV)
		(_port
			((I) (\Mclk_II/FCLK \))
			((O) (\U1/U4/Latch1r<8>_MC.REG_tsimcreated_inv_Mclk_II/FCLK \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U4/Latch1r<8>_MC.D_1697 \ 0 16339 (_entity .  X_XOR2)
		(_port
			((I0) (\U1/U4/Latch1r<8>_MC.D1 \))
			((I1) (\U1/U4/Latch1r<8>_MC.D2 \))
			((O) (\U1/U4/Latch1r<8>_MC.D \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U4/Latch1r<8>_MC.D1_1698 \ 0 16344 (_entity .  X_ZERO)
		(_port
			((O) (\U1/U4/Latch1r<8>_MC.D1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U4/Latch1r<8>_MC.D2_PT_0_1699 \ 0 16347 (_entity .  X_AND2)
		(_port
			((I0) (\NlwInverterSignal_U1/U4/Latch1r<8>_MC.D2_PT_0/IN0 \))
			((I1) (\U1/Channel1 \(8)))
			((O) (\U1/U4/Latch1r<8>_MC.D2_PT_0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U4/Latch1r<8>_MC.D2_PT_1_1700 \ 0 16352 (_entity .  X_AND8)
		(_port
			((I0) (\NlwInverterSignal_U1/U4/Latch1r<8>_MC.D2_PT_1/IN0 \))
			((I1) (\RD_II/UIM \))
			((I2) (U2_ADDR_reg(1)))
			((I3) (N_PZ_931))
			((I4) (\NlwInverterSignal_U1/U4/Latch1r<8>_MC.D2_PT_1/IN4 \))
			((I5) (\NlwInverterSignal_U1/U4/Latch1r<8>_MC.D2_PT_1/IN5 \))
			((I6) (\NlwInverterSignal_U1/U4/Latch1r<8>_MC.D2_PT_1/IN6 \))
			((I7) (\U1/U4/Latch1r \(8)))
			((O) (\U1/U4/Latch1r<8>_MC.D2_PT_1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U4/Latch1r<8>_MC.D2_1701 \ 0 16363 (_entity .  X_OR2)
		(_port
			((I0) (\U1/U4/Latch1r<8>_MC.D2_PT_0 \))
			((I1) (\U1/U4/Latch1r<8>_MC.D2_PT_1 \))
			((O) (\U1/U4/Latch1r<8>_MC.D2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \outDATA<1>\\$WA1.UIM_1702 \ 0 16368 (_entity .  X_BUF)
		(_port
			((I) (\outDATA<1>\\$WA1.UIM_MC.Q \))
			((O) (\outDATA<1>\\$WA1.UIM \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \outDATA<1>\\$WA1.UIM_MC.Q_1703 \ 0 16372 (_entity .  X_BUF)
		(_port
			((I) (\outDATA<1>\\$WA1.UIM_MC.D \))
			((O) (\outDATA<1>\\$WA1.UIM_MC.Q \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \outDATA<1>\\$WA1.UIM_MC.D_1704 \ 0 16376 (_entity .  X_XOR2)
		(_port
			((I0) (\outDATA<1>\\$WA1.UIM_MC.D1 \))
			((I1) (\outDATA<1>\\$WA1.UIM_MC.D2 \))
			((O) (\outDATA<1>\\$WA1.UIM_MC.D \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \outDATA<1>\\$WA1.UIM_MC.D1_1705 \ 0 16381 (_entity .  X_AND2)
		(_port
			((I0) (\I2CS<1>_II/UIM \))
			((I1) (\I2CS<1>_II/UIM \))
			((O) (\outDATA<1>\\$WA1.UIM_MC.D1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \outDATA<1>\\$WA1.UIM_MC.D2_1706 \ 0 16386 (_entity .  X_ZERO)
		(_port
			((O) (\outDATA<1>\\$WA1.UIM_MC.D2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \outDATA<1>\\$WA2.UIM_1707 \ 0 16389 (_entity .  X_BUF)
		(_port
			((I) (\outDATA<1>\\$WA2.UIM_MC.Q \))
			((O) (\outDATA<1>\\$WA2.UIM \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \outDATA<1>\\$WA2.UIM_MC.Q_1708 \ 0 16393 (_entity .  X_BUF)
		(_port
			((I) (\outDATA<1>\\$WA2.UIM_MC.D \))
			((O) (\outDATA<1>\\$WA2.UIM_MC.Q \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \outDATA<1>\\$WA2.UIM_MC.D_1709 \ 0 16397 (_entity .  X_XOR2)
		(_port
			((I0) (\outDATA<1>\\$WA2.UIM_MC.D1 \))
			((I1) (\outDATA<1>\\$WA2.UIM_MC.D2 \))
			((O) (\outDATA<1>\\$WA2.UIM_MC.D \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \outDATA<1>\\$WA2.UIM_MC.D1_1710 \ 0 16402 (_entity .  X_AND2)
		(_port
			((I0) (\FLS0_II/UIM \))
			((I1) (\FLS0_II/UIM \))
			((O) (\outDATA<1>\\$WA2.UIM_MC.D1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \outDATA<1>\\$WA2.UIM_MC.D2_1711 \ 0 16407 (_entity .  X_ZERO)
		(_port
			((O) (\outDATA<1>\\$WA2.UIM_MC.D2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \outDATA<1>\\$WA5.UIM_1712 \ 0 16410 (_entity .  X_BUF)
		(_port
			((I) (\outDATA<1>\\$WA5.UIM_MC.Q \))
			((O) (\outDATA<1>\\$WA5.UIM \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \outDATA<1>\\$WA5.UIM_MC.Q_1713 \ 0 16414 (_entity .  X_BUF)
		(_port
			((I) (\outDATA<1>\\$WA5.UIM_MC.D \))
			((O) (\outDATA<1>\\$WA5.UIM_MC.Q \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \outDATA<1>\\$WA5.UIM_MC.D_1714 \ 0 16418 (_entity .  X_XOR2)
		(_port
			((I0) (\outDATA<1>\\$WA5.UIM_MC.D1 \))
			((I1) (\outDATA<1>\\$WA5.UIM_MC.D2 \))
			((O) (\outDATA<1>\\$WA5.UIM_MC.D \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \outDATA<1>\\$WA5.UIM_MC.D1_1715 \ 0 16423 (_entity .  X_ZERO)
		(_port
			((O) (\outDATA<1>\\$WA5.UIM_MC.D1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \outDATA<1>\\$WA5.UIM_MC.D2_PT_0_1716 \ 0 16426 (_entity .  X_AND2)
		(_port
			((I0) (N_PZ_966))
			((I1) (\U1/U3/holdingreg \(1)))
			((O) (\outDATA<1>\\$WA5.UIM_MC.D2_PT_0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \outDATA<1>\\$WA5.UIM_MC.D2_PT_1_1717 \ 0 16431 (_entity .  X_AND2)
		(_port
			((I0) (N_PZ_1002))
			((I1) (\U1/U3/holdingreg \(17)))
			((O) (\outDATA<1>\\$WA5.UIM_MC.D2_PT_1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \outDATA<1>\\$WA5.UIM_MC.D2_PT_2_1718 \ 0 16436 (_entity .  X_AND2)
		(_port
			((I0) (N_PZ_1061))
			((I1) (\U1/U3/holdingreg \(9)))
			((O) (\outDATA<1>\\$WA5.UIM_MC.D2_PT_2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \outDATA<1>\\$WA5.UIM_MC.D2_1719 \ 0 16441 (_entity .  X_OR3)
		(_port
			((I0) (\outDATA<1>\\$WA5.UIM_MC.D2_PT_0 \))
			((I1) (\outDATA<1>\\$WA5.UIM_MC.D2_PT_1 \))
			((I2) (\outDATA<1>\\$WA5.UIM_MC.D2_PT_2 \))
			((O) (\outDATA<1>\\$WA5.UIM_MC.D2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U3/holdingreg<1> \ 0 16447 (_entity .  X_BUF)
		(_port
			((I) (\U1/U3/holdingreg<1>_MC.Q \))
			((O) (\U1/U3/holdingreg \(1)))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U3/holdingreg<1>_MC.REG \ 0 16451 (_entity .  X_FF)
		(_port
			((I) (\U1/U3/holdingreg<1>_MC.D \))
			((CE) (Vcc))
			((CLK) (\U1/U3/holdingreg<1>_MC.REG_tsimcreated_inv_Mclk_II/FCLK \))
			((SET) (Gnd))
			((RST) (PRLD))
			((O) (\U1/U3/holdingreg<1>_MC.Q \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U3/holdingreg<1>_MC.REG_tsimcreated_inv_Mclk_II/FCLK_1720 \ 0 16459 (_entity .  X_INV)
		(_port
			((I) (\Mclk_II/FCLK \))
			((O) (\U1/U3/holdingreg<1>_MC.REG_tsimcreated_inv_Mclk_II/FCLK \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U3/holdingreg<1>_MC.D_1721 \ 0 16463 (_entity .  X_XOR2)
		(_port
			((I0) (\U1/U3/holdingreg<1>_MC.D1 \))
			((I1) (\U1/U3/holdingreg<1>_MC.D2 \))
			((O) (\U1/U3/holdingreg<1>_MC.D \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U3/holdingreg<1>_MC.D1_1722 \ 0 16468 (_entity .  X_ZERO)
		(_port
			((O) (\U1/U3/holdingreg<1>_MC.D1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U3/holdingreg<1>_MC.D2_PT_0_1723 \ 0 16471 (_entity .  X_AND2)
		(_port
			((I0) (N_PZ_986))
			((I1) (\U1/Channel1 \(1)))
			((O) (\U1/U3/holdingreg<1>_MC.D2_PT_0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U3/holdingreg<1>_MC.D2_PT_1_1724 \ 0 16476 (_entity .  X_AND3)
		(_port
			((I0) (\NlwInverterSignal_U1/U3/holdingreg<1>_MC.D2_PT_1/IN0 \))
			((I1) (\U1/U3/RDedge \))
			((I2) (\U1/U3/holdingreg \(1)))
			((O) (\U1/U3/holdingreg<1>_MC.D2_PT_1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U3/holdingreg<1>_MC.D2_PT_2_1725 \ 0 16482 (_entity .  X_AND16)
		(_port
			((I0) (\WR_II/UIM \))
			((I1) (\NlwInverterSignal_U1/U3/holdingreg<1>_MC.D2_PT_2/IN1 \))
			((I2) (U2_ADDR_reg(1)))
			((I3) (U2_ADDR_reg(0)))
			((I4) (N_PZ_931))
			((I5) (U2_ADDR_reg(2)))
			((I6) (\NlwInverterSignal_U1/U3/holdingreg<1>_MC.D2_PT_2/IN6 \))
			((I7) (\NlwInverterSignal_U1/U3/holdingreg<1>_MC.D2_PT_2/IN7 \))
			((I8) (\NlwInverterSignal_U1/U3/holdingreg<1>_MC.D2_PT_2/IN8 \))
			((I9) (\U1/Channel0 \(1)))
			((I10) (Vcc))
			((I11) (Vcc))
			((I12) (Vcc))
			((I13) (Vcc))
			((I14) (Vcc))
			((I15) (Vcc))
			((O) (\U1/U3/holdingreg<1>_MC.D2_PT_2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U3/holdingreg<1>_MC.D2_1726 \ 0 16501 (_entity .  X_OR3)
		(_port
			((I0) (\U1/U3/holdingreg<1>_MC.D2_PT_0 \))
			((I1) (\U1/U3/holdingreg<1>_MC.D2_PT_1 \))
			((I2) (\U1/U3/holdingreg<1>_MC.D2_PT_2 \))
			((O) (\U1/U3/holdingreg<1>_MC.D2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U3/holdingreg<17> \ 0 16507 (_entity .  X_BUF)
		(_port
			((I) (\U1/U3/holdingreg<17>_MC.Q \))
			((O) (\U1/U3/holdingreg \(17)))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U3/holdingreg<17>_MC.REG \ 0 16511 (_entity .  X_FF)
		(_port
			((I) (\U1/U3/holdingreg<17>_MC.D \))
			((CE) (Vcc))
			((CLK) (\U1/U3/holdingreg<17>_MC.REG_tsimcreated_inv_Mclk_II/FCLK \))
			((SET) (Gnd))
			((RST) (PRLD))
			((O) (\U1/U3/holdingreg<17>_MC.Q \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U3/holdingreg<17>_MC.REG_tsimcreated_inv_Mclk_II/FCLK_1727 \ 0 16519 (_entity .  X_INV)
		(_port
			((I) (\Mclk_II/FCLK \))
			((O) (\U1/U3/holdingreg<17>_MC.REG_tsimcreated_inv_Mclk_II/FCLK \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U3/holdingreg<17>_MC.D_1728 \ 0 16523 (_entity .  X_XOR2)
		(_port
			((I0) (\U1/U3/holdingreg<17>_MC.D1 \))
			((I1) (\U1/U3/holdingreg<17>_MC.D2 \))
			((O) (\U1/U3/holdingreg<17>_MC.D \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U3/holdingreg<17>_MC.D1_1729 \ 0 16528 (_entity .  X_ZERO)
		(_port
			((O) (\U1/U3/holdingreg<17>_MC.D1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U3/holdingreg<17>_MC.D2_PT_0_1730 \ 0 16531 (_entity .  X_AND2)
		(_port
			((I0) (N_PZ_986))
			((I1) (\U1/Channel1 \(17)))
			((O) (\U1/U3/holdingreg<17>_MC.D2_PT_0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U3/holdingreg<17>_MC.D2_PT_1_1731 \ 0 16536 (_entity .  X_AND3)
		(_port
			((I0) (\NlwInverterSignal_U1/U3/holdingreg<17>_MC.D2_PT_1/IN0 \))
			((I1) (\U1/U3/RDedge \))
			((I2) (\U1/U3/holdingreg \(17)))
			((O) (\U1/U3/holdingreg<17>_MC.D2_PT_1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U3/holdingreg<17>_MC.D2_PT_2_1732 \ 0 16542 (_entity .  X_AND16)
		(_port
			((I0) (\WR_II/UIM \))
			((I1) (\NlwInverterSignal_U1/U3/holdingreg<17>_MC.D2_PT_2/IN1 \))
			((I2) (U2_ADDR_reg(1)))
			((I3) (U2_ADDR_reg(0)))
			((I4) (N_PZ_931))
			((I5) (U2_ADDR_reg(2)))
			((I6) (\NlwInverterSignal_U1/U3/holdingreg<17>_MC.D2_PT_2/IN6 \))
			((I7) (\NlwInverterSignal_U1/U3/holdingreg<17>_MC.D2_PT_2/IN7 \))
			((I8) (\NlwInverterSignal_U1/U3/holdingreg<17>_MC.D2_PT_2/IN8 \))
			((I9) (\U1/Channel0 \(17)))
			((I10) (Vcc))
			((I11) (Vcc))
			((I12) (Vcc))
			((I13) (Vcc))
			((I14) (Vcc))
			((I15) (Vcc))
			((O) (\U1/U3/holdingreg<17>_MC.D2_PT_2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U3/holdingreg<17>_MC.D2_1733 \ 0 16561 (_entity .  X_OR3)
		(_port
			((I0) (\U1/U3/holdingreg<17>_MC.D2_PT_0 \))
			((I1) (\U1/U3/holdingreg<17>_MC.D2_PT_1 \))
			((I2) (\U1/U3/holdingreg<17>_MC.D2_PT_2 \))
			((O) (\U1/U3/holdingreg<17>_MC.D2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U3/holdingreg<9> \ 0 16567 (_entity .  X_BUF)
		(_port
			((I) (\U1/U3/holdingreg<9>_MC.Q \))
			((O) (\U1/U3/holdingreg \(9)))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U3/holdingreg<9>_MC.REG \ 0 16571 (_entity .  X_FF)
		(_port
			((I) (\U1/U3/holdingreg<9>_MC.D \))
			((CE) (Vcc))
			((CLK) (\U1/U3/holdingreg<9>_MC.REG_tsimcreated_inv_Mclk_II/FCLK \))
			((SET) (Gnd))
			((RST) (PRLD))
			((O) (\U1/U3/holdingreg<9>_MC.Q \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U3/holdingreg<9>_MC.REG_tsimcreated_inv_Mclk_II/FCLK_1734 \ 0 16579 (_entity .  X_INV)
		(_port
			((I) (\Mclk_II/FCLK \))
			((O) (\U1/U3/holdingreg<9>_MC.REG_tsimcreated_inv_Mclk_II/FCLK \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U3/holdingreg<9>_MC.D_1735 \ 0 16583 (_entity .  X_XOR2)
		(_port
			((I0) (\U1/U3/holdingreg<9>_MC.D1 \))
			((I1) (\U1/U3/holdingreg<9>_MC.D2 \))
			((O) (\U1/U3/holdingreg<9>_MC.D \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U3/holdingreg<9>_MC.D1_1736 \ 0 16588 (_entity .  X_ZERO)
		(_port
			((O) (\U1/U3/holdingreg<9>_MC.D1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U3/holdingreg<9>_MC.D2_PT_0_1737 \ 0 16591 (_entity .  X_AND2)
		(_port
			((I0) (N_PZ_986))
			((I1) (\U1/Channel1 \(9)))
			((O) (\U1/U3/holdingreg<9>_MC.D2_PT_0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U3/holdingreg<9>_MC.D2_PT_1_1738 \ 0 16596 (_entity .  X_AND3)
		(_port
			((I0) (\NlwInverterSignal_U1/U3/holdingreg<9>_MC.D2_PT_1/IN0 \))
			((I1) (\U1/U3/RDedge \))
			((I2) (\U1/U3/holdingreg \(9)))
			((O) (\U1/U3/holdingreg<9>_MC.D2_PT_1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U3/holdingreg<9>_MC.D2_PT_2_1739 \ 0 16602 (_entity .  X_AND16)
		(_port
			((I0) (\WR_II/UIM \))
			((I1) (\NlwInverterSignal_U1/U3/holdingreg<9>_MC.D2_PT_2/IN1 \))
			((I2) (U2_ADDR_reg(1)))
			((I3) (U2_ADDR_reg(0)))
			((I4) (N_PZ_931))
			((I5) (U2_ADDR_reg(2)))
			((I6) (\NlwInverterSignal_U1/U3/holdingreg<9>_MC.D2_PT_2/IN6 \))
			((I7) (\NlwInverterSignal_U1/U3/holdingreg<9>_MC.D2_PT_2/IN7 \))
			((I8) (\NlwInverterSignal_U1/U3/holdingreg<9>_MC.D2_PT_2/IN8 \))
			((I9) (\U1/Channel0 \(9)))
			((I10) (Vcc))
			((I11) (Vcc))
			((I12) (Vcc))
			((I13) (Vcc))
			((I14) (Vcc))
			((I15) (Vcc))
			((O) (\U1/U3/holdingreg<9>_MC.D2_PT_2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U3/holdingreg<9>_MC.D2_1740 \ 0 16621 (_entity .  X_OR3)
		(_port
			((I0) (\U1/U3/holdingreg<9>_MC.D2_PT_0 \))
			((I1) (\U1/U3/holdingreg<9>_MC.D2_PT_1 \))
			((I2) (\U1/U3/holdingreg<9>_MC.D2_PT_2 \))
			((O) (\U1/U3/holdingreg<9>_MC.D2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \outDATA<1>\\$WA3.UIM_1741 \ 0 16627 (_entity .  X_BUF)
		(_port
			((I) (\outDATA<1>\\$WA3.UIM_MC.Q \))
			((O) (\outDATA<1>\\$WA3.UIM \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \outDATA<1>\\$WA3.UIM_MC.Q_1742 \ 0 16631 (_entity .  X_BUF)
		(_port
			((I) (\outDATA<1>\\$WA3.UIM_MC.D \))
			((O) (\outDATA<1>\\$WA3.UIM_MC.Q \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \outDATA<1>\\$WA3.UIM_MC.D_1743 \ 0 16635 (_entity .  X_XOR2)
		(_port
			((I0) (\outDATA<1>\\$WA3.UIM_MC.D1 \))
			((I1) (\outDATA<1>\\$WA3.UIM_MC.D2 \))
			((O) (\outDATA<1>\\$WA3.UIM_MC.D \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \outDATA<1>\\$WA3.UIM_MC.D1_1744 \ 0 16640 (_entity .  X_AND2)
		(_port
			((I0) (NET2528))
			((I1) (NET2528))
			((O) (\outDATA<1>\\$WA3.UIM_MC.D1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \outDATA<1>\\$WA3.UIM_MC.D2_PT_0_1745 \ 0 16645 (_entity .  X_AND8)
		(_port
			((I0) (U2_ADDR_reg(1)))
			((I1) (\NlwInverterSignal_outDATA<1>\\$WA3.UIM_MC.D2_PT_0/IN1 \))
			((I2) (N_PZ_931))
			((I3) (U2_ADDR_reg(2)))
			((I4) (U2_ADDR_reg(3)))
			((I5) (NET2528))
			((I6) (U2_Enable_AD))
			((I7) (\NlwInverterSignal_outDATA<1>\\$WA3.UIM_MC.D2_PT_0/IN7 \))
			((O) (\outDATA<1>\\$WA3.UIM_MC.D2_PT_0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \outDATA<1>\\$WA3.UIM_MC.D2_PT_1_1746 \ 0 16656 (_entity .  X_AND8)
		(_port
			((I0) (U2_ADDR_reg(1)))
			((I1) (\NlwInverterSignal_outDATA<1>\\$WA3.UIM_MC.D2_PT_1/IN1 \))
			((I2) (N_PZ_931))
			((I3) (U2_ADDR_reg(2)))
			((I4) (U2_ADDR_reg(3)))
			((I5) (\NlwInverterSignal_outDATA<1>\\$WA3.UIM_MC.D2_PT_1/IN5 \))
			((I6) (\Home05FLG_II/UIM \))
			((I7) (U2_Enable_AD))
			((O) (\outDATA<1>\\$WA3.UIM_MC.D2_PT_1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \outDATA<1>\\$WA3.UIM_MC.D2_1747 \ 0 16667 (_entity .  X_OR2)
		(_port
			((I0) (\outDATA<1>\\$WA3.UIM_MC.D2_PT_0 \))
			((I1) (\outDATA<1>\\$WA3.UIM_MC.D2_PT_1 \))
			((O) (\outDATA<1>\\$WA3.UIM_MC.D2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \outDATA<1>\\$WA0.UIM_1748 \ 0 16672 (_entity .  X_BUF)
		(_port
			((I) (\outDATA<1>\\$WA0.UIM_MC.Q \))
			((O) (\outDATA<1>\\$WA0.UIM \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \outDATA<1>\\$WA0.UIM_MC.Q_1749 \ 0 16676 (_entity .  X_BUF)
		(_port
			((I) (\outDATA<1>\\$WA0.UIM_MC.D \))
			((O) (\outDATA<1>\\$WA0.UIM_MC.Q \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \outDATA<1>\\$WA0.UIM_MC.D_1750 \ 0 16680 (_entity .  X_XOR2)
		(_port
			((I0) (\outDATA<1>\\$WA0.UIM_MC.D1 \))
			((I1) (\outDATA<1>\\$WA0.UIM_MC.D2 \))
			((O) (\outDATA<1>\\$WA0.UIM_MC.D \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \outDATA<1>\\$WA0.UIM_MC.D1_1751 \ 0 16685 (_entity .  X_AND2)
		(_port
			((I0) (U11_U3_counterr(1)))
			((I1) (U11_U3_counterr(1)))
			((O) (\outDATA<1>\\$WA0.UIM_MC.D1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \outDATA<1>\\$WA0.UIM_MC.D2_1752 \ 0 16690 (_entity .  X_ZERO)
		(_port
			((O) (\outDATA<1>\\$WA0.UIM_MC.D2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \outDATA<1>\\$WA4.UIM_1753 \ 0 16693 (_entity .  X_BUF)
		(_port
			((I) (\outDATA<1>\\$WA4.UIM_MC.Q \))
			((O) (\outDATA<1>\\$WA4.UIM \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \outDATA<1>\\$WA4.UIM_MC.Q_1754 \ 0 16697 (_entity .  X_BUF)
		(_port
			((I) (\outDATA<1>\\$WA4.UIM_MC.D \))
			((O) (\outDATA<1>\\$WA4.UIM_MC.Q \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \outDATA<1>\\$WA4.UIM_MC.D_1755 \ 0 16701 (_entity .  X_XOR2)
		(_port
			((I0) (\outDATA<1>\\$WA4.UIM_MC.D1 \))
			((I1) (\outDATA<1>\\$WA4.UIM_MC.D2 \))
			((O) (\outDATA<1>\\$WA4.UIM_MC.D \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \outDATA<1>\\$WA4.UIM_MC.D1_1756 \ 0 16706 (_entity .  X_ZERO)
		(_port
			((O) (\outDATA<1>\\$WA4.UIM_MC.D1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \outDATA<1>\\$WA4.UIM_MC.D2_PT_0_1757 \ 0 16709 (_entity .  X_AND2)
		(_port
			((I0) (N_PZ_1003))
			((I1) (\U1/U4/Latch1r \(9)))
			((O) (\outDATA<1>\\$WA4.UIM_MC.D2_PT_0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \outDATA<1>\\$WA4.UIM_MC.D2_PT_1_1758 \ 0 16714 (_entity .  X_AND8)
		(_port
			((I0) (\WR_II/UIM \))
			((I1) (\NlwInverterSignal_outDATA<1>\\$WA4.UIM_MC.D2_PT_1/IN1 \))
			((I2) (U2_ADDR_reg(1)))
			((I3) (U2_ADDR_reg(0)))
			((I4) (N_PZ_931))
			((I5) (\NlwInverterSignal_outDATA<1>\\$WA4.UIM_MC.D2_PT_1/IN5 \))
			((I6) (U2_ADDR_reg(3)))
			((I7) (\U1/U4/Latch0r \(9)))
			((O) (\outDATA<1>\\$WA4.UIM_MC.D2_PT_1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \outDATA<1>\\$WA4.UIM_MC.D2_PT_2_1759 \ 0 16725 (_entity .  X_AND8)
		(_port
			((I0) (\WR_II/UIM \))
			((I1) (\NlwInverterSignal_outDATA<1>\\$WA4.UIM_MC.D2_PT_2/IN1 \))
			((I2) (U2_ADDR_reg(1)))
			((I3) (\NlwInverterSignal_outDATA<1>\\$WA4.UIM_MC.D2_PT_2/IN3 \))
			((I4) (N_PZ_931))
			((I5) (\NlwInverterSignal_outDATA<1>\\$WA4.UIM_MC.D2_PT_2/IN5 \))
			((I6) (U2_ADDR_reg(3)))
			((I7) (\U1/U4/Latch0r \(1)))
			((O) (\outDATA<1>\\$WA4.UIM_MC.D2_PT_2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \outDATA<1>\\$WA4.UIM_MC.D2_PT_3_1760 \ 0 16736 (_entity .  X_AND8)
		(_port
			((I0) (\WR_II/UIM \))
			((I1) (\NlwInverterSignal_outDATA<1>\\$WA4.UIM_MC.D2_PT_3/IN1 \))
			((I2) (\NlwInverterSignal_outDATA<1>\\$WA4.UIM_MC.D2_PT_3/IN2 \))
			((I3) (\NlwInverterSignal_outDATA<1>\\$WA4.UIM_MC.D2_PT_3/IN3 \))
			((I4) (N_PZ_931))
			((I5) (U2_ADDR_reg(2)))
			((I6) (U2_ADDR_reg(3)))
			((I7) (\U1/U4/Latch1r \(1)))
			((O) (\outDATA<1>\\$WA4.UIM_MC.D2_PT_3 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \outDATA<1>\\$WA4.UIM_MC.D2_1761 \ 0 16747 (_entity .  X_OR4)
		(_port
			((I0) (\outDATA<1>\\$WA4.UIM_MC.D2_PT_0 \))
			((I1) (\outDATA<1>\\$WA4.UIM_MC.D2_PT_1 \))
			((I2) (\outDATA<1>\\$WA4.UIM_MC.D2_PT_2 \))
			((I3) (\outDATA<1>\\$WA4.UIM_MC.D2_PT_3 \))
			((O) (\outDATA<1>\\$WA4.UIM_MC.D2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U4/Latch0r<1> \ 0 16754 (_entity .  X_BUF)
		(_port
			((I) (\U1/U4/Latch0r<1>_MC.Q \))
			((O) (\U1/U4/Latch0r \(1)))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U4/Latch0r<1>_MC.REG \ 0 16758 (_entity .  X_FF)
		(_port
			((I) (\U1/U4/Latch0r<1>_MC.D \))
			((CE) (Vcc))
			((CLK) (\U1/U4/Latch0r<1>_MC.REG_tsimcreated_inv_Mclk_II/FCLK \))
			((SET) (Gnd))
			((RST) (PRLD))
			((O) (\U1/U4/Latch0r<1>_MC.Q \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U4/Latch0r<1>_MC.REG_tsimcreated_inv_Mclk_II/FCLK_1762 \ 0 16766 (_entity .  X_INV)
		(_port
			((I) (\Mclk_II/FCLK \))
			((O) (\U1/U4/Latch0r<1>_MC.REG_tsimcreated_inv_Mclk_II/FCLK \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U4/Latch0r<1>_MC.D_1763 \ 0 16770 (_entity .  X_XOR2)
		(_port
			((I0) (\U1/U4/Latch0r<1>_MC.D1 \))
			((I1) (\U1/U4/Latch0r<1>_MC.D2 \))
			((O) (\U1/U4/Latch0r<1>_MC.D \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U4/Latch0r<1>_MC.D1_1764 \ 0 16775 (_entity .  X_ZERO)
		(_port
			((O) (\U1/U4/Latch0r<1>_MC.D1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U4/Latch0r<1>_MC.D2_PT_0_1765 \ 0 16778 (_entity .  X_AND2)
		(_port
			((I0) (N_PZ_1059))
			((I1) (\U1/U4/Latch0r \(1)))
			((O) (\U1/U4/Latch0r<1>_MC.D2_PT_0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U4/Latch0r<1>_MC.D2_PT_1_1766 \ 0 16783 (_entity .  X_AND3)
		(_port
			((I0) (\NlwInverterSignal_U1/U4/Latch0r<1>_MC.D2_PT_1/IN0 \))
			((I1) (\U1/Channel0 \(1)))
			((I2) (\NlwInverterSignal_U1/U4/Latch0r<1>_MC.D2_PT_1/IN2 \))
			((O) (\U1/U4/Latch0r<1>_MC.D2_PT_1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U4/Latch0r<1>_MC.D2_1767 \ 0 16789 (_entity .  X_OR2)
		(_port
			((I0) (\U1/U4/Latch0r<1>_MC.D2_PT_0 \))
			((I1) (\U1/U4/Latch0r<1>_MC.D2_PT_1 \))
			((O) (\U1/U4/Latch0r<1>_MC.D2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U4/Latch0r<9> \ 0 16794 (_entity .  X_BUF)
		(_port
			((I) (\U1/U4/Latch0r<9>_MC.Q \))
			((O) (\U1/U4/Latch0r \(9)))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U4/Latch0r<9>_MC.REG \ 0 16798 (_entity .  X_FF)
		(_port
			((I) (\U1/U4/Latch0r<9>_MC.D \))
			((CE) (Vcc))
			((CLK) (\U1/U4/Latch0r<9>_MC.REG_tsimcreated_inv_Mclk_II/FCLK \))
			((SET) (Gnd))
			((RST) (PRLD))
			((O) (\U1/U4/Latch0r<9>_MC.Q \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U4/Latch0r<9>_MC.REG_tsimcreated_inv_Mclk_II/FCLK_1768 \ 0 16806 (_entity .  X_INV)
		(_port
			((I) (\Mclk_II/FCLK \))
			((O) (\U1/U4/Latch0r<9>_MC.REG_tsimcreated_inv_Mclk_II/FCLK \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U4/Latch0r<9>_MC.D_1769 \ 0 16810 (_entity .  X_XOR2)
		(_port
			((I0) (\U1/U4/Latch0r<9>_MC.D1 \))
			((I1) (\U1/U4/Latch0r<9>_MC.D2 \))
			((O) (\U1/U4/Latch0r<9>_MC.D \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U4/Latch0r<9>_MC.D1_1770 \ 0 16815 (_entity .  X_ZERO)
		(_port
			((O) (\U1/U4/Latch0r<9>_MC.D1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U4/Latch0r<9>_MC.D2_PT_0_1771 \ 0 16818 (_entity .  X_AND2)
		(_port
			((I0) (N_PZ_1059))
			((I1) (\U1/U4/Latch0r \(9)))
			((O) (\U1/U4/Latch0r<9>_MC.D2_PT_0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U4/Latch0r<9>_MC.D2_PT_1_1772 \ 0 16823 (_entity .  X_AND3)
		(_port
			((I0) (\NlwInverterSignal_U1/U4/Latch0r<9>_MC.D2_PT_1/IN0 \))
			((I1) (\U1/Channel0 \(9)))
			((I2) (\NlwInverterSignal_U1/U4/Latch0r<9>_MC.D2_PT_1/IN2 \))
			((O) (\U1/U4/Latch0r<9>_MC.D2_PT_1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U4/Latch0r<9>_MC.D2_1773 \ 0 16829 (_entity .  X_OR2)
		(_port
			((I0) (\U1/U4/Latch0r<9>_MC.D2_PT_0 \))
			((I1) (\U1/U4/Latch0r<9>_MC.D2_PT_1 \))
			((O) (\U1/U4/Latch0r<9>_MC.D2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U4/Latch1r<1> \ 0 16834 (_entity .  X_BUF)
		(_port
			((I) (\U1/U4/Latch1r<1>_MC.Q \))
			((O) (\U1/U4/Latch1r \(1)))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U4/Latch1r<1>_MC.REG \ 0 16838 (_entity .  X_FF)
		(_port
			((I) (\U1/U4/Latch1r<1>_MC.D \))
			((CE) (Vcc))
			((CLK) (\U1/U4/Latch1r<1>_MC.REG_tsimcreated_inv_Mclk_II/FCLK \))
			((SET) (Gnd))
			((RST) (PRLD))
			((O) (\U1/U4/Latch1r<1>_MC.Q \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U4/Latch1r<1>_MC.REG_tsimcreated_inv_Mclk_II/FCLK_1774 \ 0 16846 (_entity .  X_INV)
		(_port
			((I) (\Mclk_II/FCLK \))
			((O) (\U1/U4/Latch1r<1>_MC.REG_tsimcreated_inv_Mclk_II/FCLK \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U4/Latch1r<1>_MC.D_1775 \ 0 16850 (_entity .  X_XOR2)
		(_port
			((I0) (\U1/U4/Latch1r<1>_MC.D1 \))
			((I1) (\U1/U4/Latch1r<1>_MC.D2 \))
			((O) (\U1/U4/Latch1r<1>_MC.D \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U4/Latch1r<1>_MC.D1_1776 \ 0 16855 (_entity .  X_ZERO)
		(_port
			((O) (\U1/U4/Latch1r<1>_MC.D1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U4/Latch1r<1>_MC.D2_PT_0_1777 \ 0 16858 (_entity .  X_AND2)
		(_port
			((I0) (\NlwInverterSignal_U1/U4/Latch1r<1>_MC.D2_PT_0/IN0 \))
			((I1) (\U1/Channel1 \(1)))
			((O) (\U1/U4/Latch1r<1>_MC.D2_PT_0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U4/Latch1r<1>_MC.D2_PT_1_1778 \ 0 16863 (_entity .  X_AND8)
		(_port
			((I0) (\NlwInverterSignal_U1/U4/Latch1r<1>_MC.D2_PT_1/IN0 \))
			((I1) (\RD_II/UIM \))
			((I2) (U2_ADDR_reg(1)))
			((I3) (N_PZ_931))
			((I4) (\NlwInverterSignal_U1/U4/Latch1r<1>_MC.D2_PT_1/IN4 \))
			((I5) (\NlwInverterSignal_U1/U4/Latch1r<1>_MC.D2_PT_1/IN5 \))
			((I6) (\NlwInverterSignal_U1/U4/Latch1r<1>_MC.D2_PT_1/IN6 \))
			((I7) (\U1/U4/Latch1r \(1)))
			((O) (\U1/U4/Latch1r<1>_MC.D2_PT_1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U4/Latch1r<1>_MC.D2_1779 \ 0 16874 (_entity .  X_OR2)
		(_port
			((I0) (\U1/U4/Latch1r<1>_MC.D2_PT_0 \))
			((I1) (\U1/U4/Latch1r<1>_MC.D2_PT_1 \))
			((O) (\U1/U4/Latch1r<1>_MC.D2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U4/Latch1r<9> \ 0 16879 (_entity .  X_BUF)
		(_port
			((I) (\U1/U4/Latch1r<9>_MC.Q \))
			((O) (\U1/U4/Latch1r \(9)))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U4/Latch1r<9>_MC.REG \ 0 16883 (_entity .  X_FF)
		(_port
			((I) (\U1/U4/Latch1r<9>_MC.D \))
			((CE) (Vcc))
			((CLK) (\U1/U4/Latch1r<9>_MC.REG_tsimcreated_inv_Mclk_II/FCLK \))
			((SET) (Gnd))
			((RST) (PRLD))
			((O) (\U1/U4/Latch1r<9>_MC.Q \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U4/Latch1r<9>_MC.REG_tsimcreated_inv_Mclk_II/FCLK_1780 \ 0 16891 (_entity .  X_INV)
		(_port
			((I) (\Mclk_II/FCLK \))
			((O) (\U1/U4/Latch1r<9>_MC.REG_tsimcreated_inv_Mclk_II/FCLK \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U4/Latch1r<9>_MC.D_1781 \ 0 16895 (_entity .  X_XOR2)
		(_port
			((I0) (\U1/U4/Latch1r<9>_MC.D1 \))
			((I1) (\U1/U4/Latch1r<9>_MC.D2 \))
			((O) (\U1/U4/Latch1r<9>_MC.D \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U4/Latch1r<9>_MC.D1_1782 \ 0 16900 (_entity .  X_ZERO)
		(_port
			((O) (\U1/U4/Latch1r<9>_MC.D1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U4/Latch1r<9>_MC.D2_PT_0_1783 \ 0 16903 (_entity .  X_AND2)
		(_port
			((I0) (\NlwInverterSignal_U1/U4/Latch1r<9>_MC.D2_PT_0/IN0 \))
			((I1) (\U1/Channel1 \(9)))
			((O) (\U1/U4/Latch1r<9>_MC.D2_PT_0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U4/Latch1r<9>_MC.D2_PT_1_1784 \ 0 16908 (_entity .  X_AND8)
		(_port
			((I0) (\NlwInverterSignal_U1/U4/Latch1r<9>_MC.D2_PT_1/IN0 \))
			((I1) (\RD_II/UIM \))
			((I2) (U2_ADDR_reg(1)))
			((I3) (N_PZ_931))
			((I4) (\NlwInverterSignal_U1/U4/Latch1r<9>_MC.D2_PT_1/IN4 \))
			((I5) (\NlwInverterSignal_U1/U4/Latch1r<9>_MC.D2_PT_1/IN5 \))
			((I6) (\NlwInverterSignal_U1/U4/Latch1r<9>_MC.D2_PT_1/IN6 \))
			((I7) (\U1/U4/Latch1r \(9)))
			((O) (\U1/U4/Latch1r<9>_MC.D2_PT_1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U4/Latch1r<9>_MC.D2_1785 \ 0 16919 (_entity .  X_OR2)
		(_port
			((I0) (\U1/U4/Latch1r<9>_MC.D2_PT_0 \))
			((I1) (\U1/U4/Latch1r<9>_MC.D2_PT_1 \))
			((O) (\U1/U4/Latch1r<9>_MC.D2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \outDATA<2>\\$WA0.UIM_1786 \ 0 16924 (_entity .  X_BUF)
		(_port
			((I) (\outDATA<2>\\$WA0.UIM_MC.Q \))
			((O) (\outDATA<2>\\$WA0.UIM \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \outDATA<2>\\$WA0.UIM_MC.Q_1787 \ 0 16928 (_entity .  X_BUF)
		(_port
			((I) (\outDATA<2>\\$WA0.UIM_MC.D \))
			((O) (\outDATA<2>\\$WA0.UIM_MC.Q \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \outDATA<2>\\$WA0.UIM_MC.D_1788 \ 0 16932 (_entity .  X_XOR2)
		(_port
			((I0) (\outDATA<2>\\$WA0.UIM_MC.D1 \))
			((I1) (\outDATA<2>\\$WA0.UIM_MC.D2 \))
			((O) (\outDATA<2>\\$WA0.UIM_MC.D \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \outDATA<2>\\$WA0.UIM_MC.D1_1789 \ 0 16937 (_entity .  X_AND2)
		(_port
			((I0) (U11_U3_counterr(2)))
			((I1) (U11_U3_counterr(2)))
			((O) (\outDATA<2>\\$WA0.UIM_MC.D1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \outDATA<2>\\$WA0.UIM_MC.D2_1790 \ 0 16942 (_entity .  X_ZERO)
		(_port
			((O) (\outDATA<2>\\$WA0.UIM_MC.D2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \outDATA<2>\\$WA1.UIM_1791 \ 0 16945 (_entity .  X_BUF)
		(_port
			((I) (\outDATA<2>\\$WA1.UIM_MC.Q \))
			((O) (\outDATA<2>\\$WA1.UIM \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \outDATA<2>\\$WA1.UIM_MC.Q_1792 \ 0 16949 (_entity .  X_BUF)
		(_port
			((I) (\outDATA<2>\\$WA1.UIM_MC.D \))
			((O) (\outDATA<2>\\$WA1.UIM_MC.Q \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \outDATA<2>\\$WA1.UIM_MC.D_1793 \ 0 16953 (_entity .  X_XOR2)
		(_port
			((I0) (\outDATA<2>\\$WA1.UIM_MC.D1 \))
			((I1) (\outDATA<2>\\$WA1.UIM_MC.D2 \))
			((O) (\outDATA<2>\\$WA1.UIM_MC.D \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \outDATA<2>\\$WA1.UIM_MC.D1_1794 \ 0 16958 (_entity .  X_AND2)
		(_port
			((I0) (\I2CS<2>_II/UIM \))
			((I1) (\I2CS<2>_II/UIM \))
			((O) (\outDATA<2>\\$WA1.UIM_MC.D1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \outDATA<2>\\$WA1.UIM_MC.D2_1795 \ 0 16963 (_entity .  X_ZERO)
		(_port
			((O) (\outDATA<2>\\$WA1.UIM_MC.D2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \outDATA<2>\\$WA2.UIM_1796 \ 0 16966 (_entity .  X_BUF)
		(_port
			((I) (\outDATA<2>\\$WA2.UIM_MC.Q \))
			((O) (\outDATA<2>\\$WA2.UIM \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \outDATA<2>\\$WA2.UIM_MC.Q_1797 \ 0 16970 (_entity .  X_BUF)
		(_port
			((I) (\outDATA<2>\\$WA2.UIM_MC.D \))
			((O) (\outDATA<2>\\$WA2.UIM_MC.Q \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \outDATA<2>\\$WA2.UIM_MC.D_1798 \ 0 16974 (_entity .  X_XOR2)
		(_port
			((I0) (\outDATA<2>\\$WA2.UIM_MC.D1 \))
			((I1) (\outDATA<2>\\$WA2.UIM_MC.D2 \))
			((O) (\outDATA<2>\\$WA2.UIM_MC.D \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \outDATA<2>\\$WA2.UIM_MC.D1_1799 \ 0 16979 (_entity .  X_AND2)
		(_port
			((I0) (\Home0_II/UIM \))
			((I1) (\Home0_II/UIM \))
			((O) (\outDATA<2>\\$WA2.UIM_MC.D1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \outDATA<2>\\$WA2.UIM_MC.D2_1800 \ 0 16984 (_entity .  X_ZERO)
		(_port
			((O) (\outDATA<2>\\$WA2.UIM_MC.D2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \outDATA<2>\\$WA3.UIM_1801 \ 0 16987 (_entity .  X_BUF)
		(_port
			((I) (\outDATA<2>\\$WA3.UIM_MC.Q \))
			((O) (\outDATA<2>\\$WA3.UIM \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \outDATA<2>\\$WA3.UIM_MC.Q_1802 \ 0 16991 (_entity .  X_BUF)
		(_port
			((I) (\outDATA<2>\\$WA3.UIM_MC.D \))
			((O) (\outDATA<2>\\$WA3.UIM_MC.Q \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \outDATA<2>\\$WA3.UIM_MC.D_1803 \ 0 16995 (_entity .  X_XOR2)
		(_port
			((I0) (\outDATA<2>\\$WA3.UIM_MC.D1 \))
			((I1) (\outDATA<2>\\$WA3.UIM_MC.D2 \))
			((O) (\outDATA<2>\\$WA3.UIM_MC.D \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \outDATA<2>\\$WA3.UIM_MC.D1_1804 \ 0 17000 (_entity .  X_ZERO)
		(_port
			((O) (\outDATA<2>\\$WA3.UIM_MC.D1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \outDATA<2>\\$WA3.UIM_MC.D2_PT_0_1805 \ 0 17003 (_entity .  X_AND2)
		(_port
			((I0) (NET2528))
			((I1) (\U4/Flgreg \(2)))
			((O) (\outDATA<2>\\$WA3.UIM_MC.D2_PT_0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \outDATA<2>\\$WA3.UIM_MC.D2_PT_1_1806 \ 0 17008 (_entity .  X_AND2)
		(_port
			((I0) (\NlwInverterSignal_outDATA<2>\\$WA3.UIM_MC.D2_PT_1/IN0 \))
			((I1) (\Enc033FLG_II/UIM \))
			((O) (\outDATA<2>\\$WA3.UIM_MC.D2_PT_1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \outDATA<2>\\$WA3.UIM_MC.D2_1807 \ 0 17013 (_entity .  X_OR2)
		(_port
			((I0) (\outDATA<2>\\$WA3.UIM_MC.D2_PT_0 \))
			((I1) (\outDATA<2>\\$WA3.UIM_MC.D2_PT_1 \))
			((O) (\outDATA<2>\\$WA3.UIM_MC.D2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \outDATA<2>\\$WA5.UIM_1808 \ 0 17018 (_entity .  X_BUF)
		(_port
			((I) (\outDATA<2>\\$WA5.UIM_MC.Q \))
			((O) (\outDATA<2>\\$WA5.UIM \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \outDATA<2>\\$WA5.UIM_MC.Q_1809 \ 0 17022 (_entity .  X_BUF)
		(_port
			((I) (\outDATA<2>\\$WA5.UIM_MC.D \))
			((O) (\outDATA<2>\\$WA5.UIM_MC.Q \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \outDATA<2>\\$WA5.UIM_MC.D_1810 \ 0 17026 (_entity .  X_XOR2)
		(_port
			((I0) (\outDATA<2>\\$WA5.UIM_MC.D1 \))
			((I1) (\outDATA<2>\\$WA5.UIM_MC.D2 \))
			((O) (\outDATA<2>\\$WA5.UIM_MC.D \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \outDATA<2>\\$WA5.UIM_MC.D1_1811 \ 0 17031 (_entity .  X_ZERO)
		(_port
			((O) (\outDATA<2>\\$WA5.UIM_MC.D1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \outDATA<2>\\$WA5.UIM_MC.D2_PT_0_1812 \ 0 17034 (_entity .  X_AND2)
		(_port
			((I0) (N_PZ_966))
			((I1) (\U1/U3/holdingreg \(2)))
			((O) (\outDATA<2>\\$WA5.UIM_MC.D2_PT_0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \outDATA<2>\\$WA5.UIM_MC.D2_PT_1_1813 \ 0 17039 (_entity .  X_AND2)
		(_port
			((I0) (N_PZ_1002))
			((I1) (\U1/U3/holdingreg \(18)))
			((O) (\outDATA<2>\\$WA5.UIM_MC.D2_PT_1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \outDATA<2>\\$WA5.UIM_MC.D2_PT_2_1814 \ 0 17044 (_entity .  X_AND2)
		(_port
			((I0) (N_PZ_1061))
			((I1) (\U1/U3/holdingreg \(10)))
			((O) (\outDATA<2>\\$WA5.UIM_MC.D2_PT_2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \outDATA<2>\\$WA5.UIM_MC.D2_1815 \ 0 17049 (_entity .  X_OR3)
		(_port
			((I0) (\outDATA<2>\\$WA5.UIM_MC.D2_PT_0 \))
			((I1) (\outDATA<2>\\$WA5.UIM_MC.D2_PT_1 \))
			((I2) (\outDATA<2>\\$WA5.UIM_MC.D2_PT_2 \))
			((O) (\outDATA<2>\\$WA5.UIM_MC.D2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U3/holdingreg<2> \ 0 17055 (_entity .  X_BUF)
		(_port
			((I) (\U1/U3/holdingreg<2>_MC.Q \))
			((O) (\U1/U3/holdingreg \(2)))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U3/holdingreg<2>_MC.REG \ 0 17059 (_entity .  X_FF)
		(_port
			((I) (\U1/U3/holdingreg<2>_MC.D \))
			((CE) (Vcc))
			((CLK) (\U1/U3/holdingreg<2>_MC.REG_tsimcreated_inv_Mclk_II/FCLK \))
			((SET) (Gnd))
			((RST) (PRLD))
			((O) (\U1/U3/holdingreg<2>_MC.Q \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U3/holdingreg<2>_MC.REG_tsimcreated_inv_Mclk_II/FCLK_1816 \ 0 17067 (_entity .  X_INV)
		(_port
			((I) (\Mclk_II/FCLK \))
			((O) (\U1/U3/holdingreg<2>_MC.REG_tsimcreated_inv_Mclk_II/FCLK \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U3/holdingreg<2>_MC.D_1817 \ 0 17071 (_entity .  X_XOR2)
		(_port
			((I0) (\U1/U3/holdingreg<2>_MC.D1 \))
			((I1) (\U1/U3/holdingreg<2>_MC.D2 \))
			((O) (\U1/U3/holdingreg<2>_MC.D \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U3/holdingreg<2>_MC.D1_1818 \ 0 17076 (_entity .  X_ZERO)
		(_port
			((O) (\U1/U3/holdingreg<2>_MC.D1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U3/holdingreg<2>_MC.D2_PT_0_1819 \ 0 17079 (_entity .  X_AND2)
		(_port
			((I0) (N_PZ_986))
			((I1) (\U1/Channel1 \(2)))
			((O) (\U1/U3/holdingreg<2>_MC.D2_PT_0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U3/holdingreg<2>_MC.D2_PT_1_1820 \ 0 17084 (_entity .  X_AND3)
		(_port
			((I0) (\NlwInverterSignal_U1/U3/holdingreg<2>_MC.D2_PT_1/IN0 \))
			((I1) (\U1/U3/RDedge \))
			((I2) (\U1/U3/holdingreg \(2)))
			((O) (\U1/U3/holdingreg<2>_MC.D2_PT_1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U3/holdingreg<2>_MC.D2_PT_2_1821 \ 0 17090 (_entity .  X_AND16)
		(_port
			((I0) (\WR_II/UIM \))
			((I1) (\NlwInverterSignal_U1/U3/holdingreg<2>_MC.D2_PT_2/IN1 \))
			((I2) (U2_ADDR_reg(1)))
			((I3) (U2_ADDR_reg(0)))
			((I4) (N_PZ_931))
			((I5) (U2_ADDR_reg(2)))
			((I6) (\NlwInverterSignal_U1/U3/holdingreg<2>_MC.D2_PT_2/IN6 \))
			((I7) (\NlwInverterSignal_U1/U3/holdingreg<2>_MC.D2_PT_2/IN7 \))
			((I8) (\NlwInverterSignal_U1/U3/holdingreg<2>_MC.D2_PT_2/IN8 \))
			((I9) (\U1/Channel0 \(2)))
			((I10) (Vcc))
			((I11) (Vcc))
			((I12) (Vcc))
			((I13) (Vcc))
			((I14) (Vcc))
			((I15) (Vcc))
			((O) (\U1/U3/holdingreg<2>_MC.D2_PT_2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U3/holdingreg<2>_MC.D2_1822 \ 0 17109 (_entity .  X_OR3)
		(_port
			((I0) (\U1/U3/holdingreg<2>_MC.D2_PT_0 \))
			((I1) (\U1/U3/holdingreg<2>_MC.D2_PT_1 \))
			((I2) (\U1/U3/holdingreg<2>_MC.D2_PT_2 \))
			((O) (\U1/U3/holdingreg<2>_MC.D2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U3/holdingreg<18> \ 0 17115 (_entity .  X_BUF)
		(_port
			((I) (\U1/U3/holdingreg<18>_MC.Q \))
			((O) (\U1/U3/holdingreg \(18)))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U3/holdingreg<18>_MC.REG \ 0 17119 (_entity .  X_FF)
		(_port
			((I) (\U1/U3/holdingreg<18>_MC.D \))
			((CE) (Vcc))
			((CLK) (\U1/U3/holdingreg<18>_MC.REG_tsimcreated_inv_Mclk_II/FCLK \))
			((SET) (Gnd))
			((RST) (PRLD))
			((O) (\U1/U3/holdingreg<18>_MC.Q \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U3/holdingreg<18>_MC.REG_tsimcreated_inv_Mclk_II/FCLK_1823 \ 0 17127 (_entity .  X_INV)
		(_port
			((I) (\Mclk_II/FCLK \))
			((O) (\U1/U3/holdingreg<18>_MC.REG_tsimcreated_inv_Mclk_II/FCLK \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U3/holdingreg<18>_MC.D_1824 \ 0 17131 (_entity .  X_XOR2)
		(_port
			((I0) (\U1/U3/holdingreg<18>_MC.D1 \))
			((I1) (\U1/U3/holdingreg<18>_MC.D2 \))
			((O) (\U1/U3/holdingreg<18>_MC.D \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U3/holdingreg<18>_MC.D1_1825 \ 0 17136 (_entity .  X_ZERO)
		(_port
			((O) (\U1/U3/holdingreg<18>_MC.D1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U3/holdingreg<18>_MC.D2_PT_0_1826 \ 0 17139 (_entity .  X_AND2)
		(_port
			((I0) (N_PZ_986))
			((I1) (\U1/Channel1 \(18)))
			((O) (\U1/U3/holdingreg<18>_MC.D2_PT_0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U3/holdingreg<18>_MC.D2_PT_1_1827 \ 0 17144 (_entity .  X_AND3)
		(_port
			((I0) (\NlwInverterSignal_U1/U3/holdingreg<18>_MC.D2_PT_1/IN0 \))
			((I1) (\U1/U3/RDedge \))
			((I2) (\U1/U3/holdingreg \(18)))
			((O) (\U1/U3/holdingreg<18>_MC.D2_PT_1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U3/holdingreg<18>_MC.D2_PT_2_1828 \ 0 17150 (_entity .  X_AND16)
		(_port
			((I0) (\WR_II/UIM \))
			((I1) (\NlwInverterSignal_U1/U3/holdingreg<18>_MC.D2_PT_2/IN1 \))
			((I2) (U2_ADDR_reg(1)))
			((I3) (U2_ADDR_reg(0)))
			((I4) (N_PZ_931))
			((I5) (U2_ADDR_reg(2)))
			((I6) (\NlwInverterSignal_U1/U3/holdingreg<18>_MC.D2_PT_2/IN6 \))
			((I7) (\NlwInverterSignal_U1/U3/holdingreg<18>_MC.D2_PT_2/IN7 \))
			((I8) (\NlwInverterSignal_U1/U3/holdingreg<18>_MC.D2_PT_2/IN8 \))
			((I9) (\U1/Channel0 \(18)))
			((I10) (Vcc))
			((I11) (Vcc))
			((I12) (Vcc))
			((I13) (Vcc))
			((I14) (Vcc))
			((I15) (Vcc))
			((O) (\U1/U3/holdingreg<18>_MC.D2_PT_2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U3/holdingreg<18>_MC.D2_1829 \ 0 17169 (_entity .  X_OR3)
		(_port
			((I0) (\U1/U3/holdingreg<18>_MC.D2_PT_0 \))
			((I1) (\U1/U3/holdingreg<18>_MC.D2_PT_1 \))
			((I2) (\U1/U3/holdingreg<18>_MC.D2_PT_2 \))
			((O) (\U1/U3/holdingreg<18>_MC.D2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U3/holdingreg<10> \ 0 17175 (_entity .  X_BUF)
		(_port
			((I) (\U1/U3/holdingreg<10>_MC.Q \))
			((O) (\U1/U3/holdingreg \(10)))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U3/holdingreg<10>_MC.REG \ 0 17179 (_entity .  X_FF)
		(_port
			((I) (\U1/U3/holdingreg<10>_MC.D \))
			((CE) (Vcc))
			((CLK) (\U1/U3/holdingreg<10>_MC.REG_tsimcreated_inv_Mclk_II/FCLK \))
			((SET) (Gnd))
			((RST) (PRLD))
			((O) (\U1/U3/holdingreg<10>_MC.Q \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U3/holdingreg<10>_MC.REG_tsimcreated_inv_Mclk_II/FCLK_1830 \ 0 17187 (_entity .  X_INV)
		(_port
			((I) (\Mclk_II/FCLK \))
			((O) (\U1/U3/holdingreg<10>_MC.REG_tsimcreated_inv_Mclk_II/FCLK \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U3/holdingreg<10>_MC.D_1831 \ 0 17191 (_entity .  X_XOR2)
		(_port
			((I0) (\U1/U3/holdingreg<10>_MC.D1 \))
			((I1) (\U1/U3/holdingreg<10>_MC.D2 \))
			((O) (\U1/U3/holdingreg<10>_MC.D \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U3/holdingreg<10>_MC.D1_1832 \ 0 17196 (_entity .  X_ZERO)
		(_port
			((O) (\U1/U3/holdingreg<10>_MC.D1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U3/holdingreg<10>_MC.D2_PT_0_1833 \ 0 17199 (_entity .  X_AND2)
		(_port
			((I0) (N_PZ_986))
			((I1) (\U1/Channel1 \(10)))
			((O) (\U1/U3/holdingreg<10>_MC.D2_PT_0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U3/holdingreg<10>_MC.D2_PT_1_1834 \ 0 17204 (_entity .  X_AND3)
		(_port
			((I0) (\NlwInverterSignal_U1/U3/holdingreg<10>_MC.D2_PT_1/IN0 \))
			((I1) (\U1/U3/RDedge \))
			((I2) (\U1/U3/holdingreg \(10)))
			((O) (\U1/U3/holdingreg<10>_MC.D2_PT_1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U3/holdingreg<10>_MC.D2_PT_2_1835 \ 0 17210 (_entity .  X_AND16)
		(_port
			((I0) (\WR_II/UIM \))
			((I1) (\NlwInverterSignal_U1/U3/holdingreg<10>_MC.D2_PT_2/IN1 \))
			((I2) (U2_ADDR_reg(1)))
			((I3) (U2_ADDR_reg(0)))
			((I4) (N_PZ_931))
			((I5) (U2_ADDR_reg(2)))
			((I6) (\NlwInverterSignal_U1/U3/holdingreg<10>_MC.D2_PT_2/IN6 \))
			((I7) (\NlwInverterSignal_U1/U3/holdingreg<10>_MC.D2_PT_2/IN7 \))
			((I8) (\NlwInverterSignal_U1/U3/holdingreg<10>_MC.D2_PT_2/IN8 \))
			((I9) (\U1/Channel0 \(10)))
			((I10) (Vcc))
			((I11) (Vcc))
			((I12) (Vcc))
			((I13) (Vcc))
			((I14) (Vcc))
			((I15) (Vcc))
			((O) (\U1/U3/holdingreg<10>_MC.D2_PT_2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U3/holdingreg<10>_MC.D2_1836 \ 0 17229 (_entity .  X_OR3)
		(_port
			((I0) (\U1/U3/holdingreg<10>_MC.D2_PT_0 \))
			((I1) (\U1/U3/holdingreg<10>_MC.D2_PT_1 \))
			((I2) (\U1/U3/holdingreg<10>_MC.D2_PT_2 \))
			((O) (\U1/U3/holdingreg<10>_MC.D2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \outDATA<2>\\$WA4.UIM_1837 \ 0 17235 (_entity .  X_BUF)
		(_port
			((I) (\outDATA<2>\\$WA4.UIM_MC.Q \))
			((O) (\outDATA<2>\\$WA4.UIM \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \outDATA<2>\\$WA4.UIM_MC.Q_1838 \ 0 17239 (_entity .  X_BUF)
		(_port
			((I) (\outDATA<2>\\$WA4.UIM_MC.D \))
			((O) (\outDATA<2>\\$WA4.UIM_MC.Q \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \outDATA<2>\\$WA4.UIM_MC.D_1839 \ 0 17243 (_entity .  X_XOR2)
		(_port
			((I0) (\outDATA<2>\\$WA4.UIM_MC.D1 \))
			((I1) (\outDATA<2>\\$WA4.UIM_MC.D2 \))
			((O) (\outDATA<2>\\$WA4.UIM_MC.D \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \outDATA<2>\\$WA4.UIM_MC.D1_1840 \ 0 17248 (_entity .  X_ZERO)
		(_port
			((O) (\outDATA<2>\\$WA4.UIM_MC.D1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \outDATA<2>\\$WA4.UIM_MC.D2_PT_0_1841 \ 0 17251 (_entity .  X_AND2)
		(_port
			((I0) (N_PZ_1003))
			((I1) (\U1/U4/Latch1r \(10)))
			((O) (\outDATA<2>\\$WA4.UIM_MC.D2_PT_0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \outDATA<2>\\$WA4.UIM_MC.D2_PT_1_1842 \ 0 17256 (_entity .  X_AND8)
		(_port
			((I0) (\WR_II/UIM \))
			((I1) (\NlwInverterSignal_outDATA<2>\\$WA4.UIM_MC.D2_PT_1/IN1 \))
			((I2) (U2_ADDR_reg(1)))
			((I3) (U2_ADDR_reg(0)))
			((I4) (N_PZ_931))
			((I5) (\NlwInverterSignal_outDATA<2>\\$WA4.UIM_MC.D2_PT_1/IN5 \))
			((I6) (U2_ADDR_reg(3)))
			((I7) (\U1/U4/Latch0r \(10)))
			((O) (\outDATA<2>\\$WA4.UIM_MC.D2_PT_1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \outDATA<2>\\$WA4.UIM_MC.D2_PT_2_1843 \ 0 17267 (_entity .  X_AND8)
		(_port
			((I0) (\WR_II/UIM \))
			((I1) (\NlwInverterSignal_outDATA<2>\\$WA4.UIM_MC.D2_PT_2/IN1 \))
			((I2) (U2_ADDR_reg(1)))
			((I3) (\NlwInverterSignal_outDATA<2>\\$WA4.UIM_MC.D2_PT_2/IN3 \))
			((I4) (N_PZ_931))
			((I5) (\NlwInverterSignal_outDATA<2>\\$WA4.UIM_MC.D2_PT_2/IN5 \))
			((I6) (U2_ADDR_reg(3)))
			((I7) (\U1/U4/Latch0r \(2)))
			((O) (\outDATA<2>\\$WA4.UIM_MC.D2_PT_2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \outDATA<2>\\$WA4.UIM_MC.D2_PT_3_1844 \ 0 17278 (_entity .  X_AND8)
		(_port
			((I0) (\WR_II/UIM \))
			((I1) (\NlwInverterSignal_outDATA<2>\\$WA4.UIM_MC.D2_PT_3/IN1 \))
			((I2) (\NlwInverterSignal_outDATA<2>\\$WA4.UIM_MC.D2_PT_3/IN2 \))
			((I3) (\NlwInverterSignal_outDATA<2>\\$WA4.UIM_MC.D2_PT_3/IN3 \))
			((I4) (N_PZ_931))
			((I5) (U2_ADDR_reg(2)))
			((I6) (U2_ADDR_reg(3)))
			((I7) (\U1/U4/Latch1r \(2)))
			((O) (\outDATA<2>\\$WA4.UIM_MC.D2_PT_3 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \outDATA<2>\\$WA4.UIM_MC.D2_1845 \ 0 17289 (_entity .  X_OR4)
		(_port
			((I0) (\outDATA<2>\\$WA4.UIM_MC.D2_PT_0 \))
			((I1) (\outDATA<2>\\$WA4.UIM_MC.D2_PT_1 \))
			((I2) (\outDATA<2>\\$WA4.UIM_MC.D2_PT_2 \))
			((I3) (\outDATA<2>\\$WA4.UIM_MC.D2_PT_3 \))
			((O) (\outDATA<2>\\$WA4.UIM_MC.D2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U4/Latch0r<10> \ 0 17296 (_entity .  X_BUF)
		(_port
			((I) (\U1/U4/Latch0r<10>_MC.Q \))
			((O) (\U1/U4/Latch0r \(10)))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U4/Latch0r<10>_MC.REG \ 0 17300 (_entity .  X_FF)
		(_port
			((I) (\U1/U4/Latch0r<10>_MC.D \))
			((CE) (Vcc))
			((CLK) (\U1/U4/Latch0r<10>_MC.REG_tsimcreated_inv_Mclk_II/FCLK \))
			((SET) (Gnd))
			((RST) (PRLD))
			((O) (\U1/U4/Latch0r<10>_MC.Q \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U4/Latch0r<10>_MC.REG_tsimcreated_inv_Mclk_II/FCLK_1846 \ 0 17308 (_entity .  X_INV)
		(_port
			((I) (\Mclk_II/FCLK \))
			((O) (\U1/U4/Latch0r<10>_MC.REG_tsimcreated_inv_Mclk_II/FCLK \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U4/Latch0r<10>_MC.D_1847 \ 0 17312 (_entity .  X_XOR2)
		(_port
			((I0) (\U1/U4/Latch0r<10>_MC.D1 \))
			((I1) (\U1/U4/Latch0r<10>_MC.D2 \))
			((O) (\U1/U4/Latch0r<10>_MC.D \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U4/Latch0r<10>_MC.D1_1848 \ 0 17317 (_entity .  X_ZERO)
		(_port
			((O) (\U1/U4/Latch0r<10>_MC.D1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U4/Latch0r<10>_MC.D2_PT_0_1849 \ 0 17320 (_entity .  X_AND2)
		(_port
			((I0) (N_PZ_1059))
			((I1) (\U1/U4/Latch0r \(10)))
			((O) (\U1/U4/Latch0r<10>_MC.D2_PT_0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U4/Latch0r<10>_MC.D2_PT_1_1850 \ 0 17325 (_entity .  X_AND3)
		(_port
			((I0) (\NlwInverterSignal_U1/U4/Latch0r<10>_MC.D2_PT_1/IN0 \))
			((I1) (\U1/Channel0 \(10)))
			((I2) (\NlwInverterSignal_U1/U4/Latch0r<10>_MC.D2_PT_1/IN2 \))
			((O) (\U1/U4/Latch0r<10>_MC.D2_PT_1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U4/Latch0r<10>_MC.D2_1851 \ 0 17331 (_entity .  X_OR2)
		(_port
			((I0) (\U1/U4/Latch0r<10>_MC.D2_PT_0 \))
			((I1) (\U1/U4/Latch0r<10>_MC.D2_PT_1 \))
			((O) (\U1/U4/Latch0r<10>_MC.D2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U4/Latch0r<2> \ 0 17336 (_entity .  X_BUF)
		(_port
			((I) (\U1/U4/Latch0r<2>_MC.Q \))
			((O) (\U1/U4/Latch0r \(2)))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U4/Latch0r<2>_MC.REG \ 0 17340 (_entity .  X_FF)
		(_port
			((I) (\U1/U4/Latch0r<2>_MC.D \))
			((CE) (Vcc))
			((CLK) (\U1/U4/Latch0r<2>_MC.REG_tsimcreated_inv_Mclk_II/FCLK \))
			((SET) (Gnd))
			((RST) (PRLD))
			((O) (\U1/U4/Latch0r<2>_MC.Q \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U4/Latch0r<2>_MC.REG_tsimcreated_inv_Mclk_II/FCLK_1852 \ 0 17348 (_entity .  X_INV)
		(_port
			((I) (\Mclk_II/FCLK \))
			((O) (\U1/U4/Latch0r<2>_MC.REG_tsimcreated_inv_Mclk_II/FCLK \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U4/Latch0r<2>_MC.D_1853 \ 0 17352 (_entity .  X_XOR2)
		(_port
			((I0) (\U1/U4/Latch0r<2>_MC.D1 \))
			((I1) (\U1/U4/Latch0r<2>_MC.D2 \))
			((O) (\U1/U4/Latch0r<2>_MC.D \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U4/Latch0r<2>_MC.D1_1854 \ 0 17357 (_entity .  X_ZERO)
		(_port
			((O) (\U1/U4/Latch0r<2>_MC.D1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U4/Latch0r<2>_MC.D2_PT_0_1855 \ 0 17360 (_entity .  X_AND2)
		(_port
			((I0) (N_PZ_1059))
			((I1) (\U1/U4/Latch0r \(2)))
			((O) (\U1/U4/Latch0r<2>_MC.D2_PT_0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U4/Latch0r<2>_MC.D2_PT_1_1856 \ 0 17365 (_entity .  X_AND3)
		(_port
			((I0) (\NlwInverterSignal_U1/U4/Latch0r<2>_MC.D2_PT_1/IN0 \))
			((I1) (\U1/Channel0 \(2)))
			((I2) (\NlwInverterSignal_U1/U4/Latch0r<2>_MC.D2_PT_1/IN2 \))
			((O) (\U1/U4/Latch0r<2>_MC.D2_PT_1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U4/Latch0r<2>_MC.D2_1857 \ 0 17371 (_entity .  X_OR2)
		(_port
			((I0) (\U1/U4/Latch0r<2>_MC.D2_PT_0 \))
			((I1) (\U1/U4/Latch0r<2>_MC.D2_PT_1 \))
			((O) (\U1/U4/Latch0r<2>_MC.D2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U4/Latch1r<2> \ 0 17376 (_entity .  X_BUF)
		(_port
			((I) (\U1/U4/Latch1r<2>_MC.Q \))
			((O) (\U1/U4/Latch1r \(2)))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U4/Latch1r<2>_MC.REG \ 0 17380 (_entity .  X_FF)
		(_port
			((I) (\U1/U4/Latch1r<2>_MC.D \))
			((CE) (Vcc))
			((CLK) (\U1/U4/Latch1r<2>_MC.REG_tsimcreated_inv_Mclk_II/FCLK \))
			((SET) (Gnd))
			((RST) (PRLD))
			((O) (\U1/U4/Latch1r<2>_MC.Q \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U4/Latch1r<2>_MC.REG_tsimcreated_inv_Mclk_II/FCLK_1858 \ 0 17388 (_entity .  X_INV)
		(_port
			((I) (\Mclk_II/FCLK \))
			((O) (\U1/U4/Latch1r<2>_MC.REG_tsimcreated_inv_Mclk_II/FCLK \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U4/Latch1r<2>_MC.D_1859 \ 0 17392 (_entity .  X_XOR2)
		(_port
			((I0) (\U1/U4/Latch1r<2>_MC.D1 \))
			((I1) (\U1/U4/Latch1r<2>_MC.D2 \))
			((O) (\U1/U4/Latch1r<2>_MC.D \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U4/Latch1r<2>_MC.D1_1860 \ 0 17397 (_entity .  X_ZERO)
		(_port
			((O) (\U1/U4/Latch1r<2>_MC.D1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U4/Latch1r<2>_MC.D2_PT_0_1861 \ 0 17400 (_entity .  X_AND2)
		(_port
			((I0) (\NlwInverterSignal_U1/U4/Latch1r<2>_MC.D2_PT_0/IN0 \))
			((I1) (\U1/Channel1 \(2)))
			((O) (\U1/U4/Latch1r<2>_MC.D2_PT_0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U4/Latch1r<2>_MC.D2_PT_1_1862 \ 0 17405 (_entity .  X_AND8)
		(_port
			((I0) (\NlwInverterSignal_U1/U4/Latch1r<2>_MC.D2_PT_1/IN0 \))
			((I1) (\RD_II/UIM \))
			((I2) (U2_ADDR_reg(1)))
			((I3) (N_PZ_931))
			((I4) (\NlwInverterSignal_U1/U4/Latch1r<2>_MC.D2_PT_1/IN4 \))
			((I5) (\NlwInverterSignal_U1/U4/Latch1r<2>_MC.D2_PT_1/IN5 \))
			((I6) (\NlwInverterSignal_U1/U4/Latch1r<2>_MC.D2_PT_1/IN6 \))
			((I7) (\U1/U4/Latch1r \(2)))
			((O) (\U1/U4/Latch1r<2>_MC.D2_PT_1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U4/Latch1r<2>_MC.D2_1863 \ 0 17416 (_entity .  X_OR2)
		(_port
			((I0) (\U1/U4/Latch1r<2>_MC.D2_PT_0 \))
			((I1) (\U1/U4/Latch1r<2>_MC.D2_PT_1 \))
			((O) (\U1/U4/Latch1r<2>_MC.D2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U4/Latch1r<10> \ 0 17421 (_entity .  X_BUF)
		(_port
			((I) (\U1/U4/Latch1r<10>_MC.Q \))
			((O) (\U1/U4/Latch1r \(10)))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U4/Latch1r<10>_MC.REG \ 0 17425 (_entity .  X_FF)
		(_port
			((I) (\U1/U4/Latch1r<10>_MC.D \))
			((CE) (Vcc))
			((CLK) (\U1/U4/Latch1r<10>_MC.REG_tsimcreated_inv_Mclk_II/FCLK \))
			((SET) (Gnd))
			((RST) (PRLD))
			((O) (\U1/U4/Latch1r<10>_MC.Q \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U4/Latch1r<10>_MC.REG_tsimcreated_inv_Mclk_II/FCLK_1864 \ 0 17433 (_entity .  X_INV)
		(_port
			((I) (\Mclk_II/FCLK \))
			((O) (\U1/U4/Latch1r<10>_MC.REG_tsimcreated_inv_Mclk_II/FCLK \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U4/Latch1r<10>_MC.D_1865 \ 0 17437 (_entity .  X_XOR2)
		(_port
			((I0) (\U1/U4/Latch1r<10>_MC.D1 \))
			((I1) (\U1/U4/Latch1r<10>_MC.D2 \))
			((O) (\U1/U4/Latch1r<10>_MC.D \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U4/Latch1r<10>_MC.D1_1866 \ 0 17442 (_entity .  X_ZERO)
		(_port
			((O) (\U1/U4/Latch1r<10>_MC.D1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U4/Latch1r<10>_MC.D2_PT_0_1867 \ 0 17445 (_entity .  X_AND2)
		(_port
			((I0) (\NlwInverterSignal_U1/U4/Latch1r<10>_MC.D2_PT_0/IN0 \))
			((I1) (\U1/Channel1 \(10)))
			((O) (\U1/U4/Latch1r<10>_MC.D2_PT_0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U4/Latch1r<10>_MC.D2_PT_1_1868 \ 0 17450 (_entity .  X_AND8)
		(_port
			((I0) (\NlwInverterSignal_U1/U4/Latch1r<10>_MC.D2_PT_1/IN0 \))
			((I1) (\RD_II/UIM \))
			((I2) (U2_ADDR_reg(1)))
			((I3) (N_PZ_931))
			((I4) (\NlwInverterSignal_U1/U4/Latch1r<10>_MC.D2_PT_1/IN4 \))
			((I5) (\NlwInverterSignal_U1/U4/Latch1r<10>_MC.D2_PT_1/IN5 \))
			((I6) (\NlwInverterSignal_U1/U4/Latch1r<10>_MC.D2_PT_1/IN6 \))
			((I7) (\U1/U4/Latch1r \(10)))
			((O) (\U1/U4/Latch1r<10>_MC.D2_PT_1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U4/Latch1r<10>_MC.D2_1869 \ 0 17461 (_entity .  X_OR2)
		(_port
			((I0) (\U1/U4/Latch1r<10>_MC.D2_PT_0 \))
			((I1) (\U1/U4/Latch1r<10>_MC.D2_PT_1 \))
			((O) (\U1/U4/Latch1r<10>_MC.D2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \outDATA<3>\\$WA0.UIM_1870 \ 0 17466 (_entity .  X_BUF)
		(_port
			((I) (\outDATA<3>\\$WA0.UIM_MC.Q \))
			((O) (\outDATA<3>\\$WA0.UIM \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \outDATA<3>\\$WA0.UIM_MC.Q_1871 \ 0 17470 (_entity .  X_BUF)
		(_port
			((I) (\outDATA<3>\\$WA0.UIM_MC.D \))
			((O) (\outDATA<3>\\$WA0.UIM_MC.Q \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \outDATA<3>\\$WA0.UIM_MC.D_1872 \ 0 17474 (_entity .  X_XOR2)
		(_port
			((I0) (\outDATA<3>\\$WA0.UIM_MC.D1 \))
			((I1) (\outDATA<3>\\$WA0.UIM_MC.D2 \))
			((O) (\outDATA<3>\\$WA0.UIM_MC.D \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \outDATA<3>\\$WA0.UIM_MC.D1_1873 \ 0 17479 (_entity .  X_AND2)
		(_port
			((I0) (U11_U3_counterr(3)))
			((I1) (U11_U3_counterr(3)))
			((O) (\outDATA<3>\\$WA0.UIM_MC.D1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \outDATA<3>\\$WA0.UIM_MC.D2_1874 \ 0 17484 (_entity .  X_ZERO)
		(_port
			((O) (\outDATA<3>\\$WA0.UIM_MC.D2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \outDATA<3>\\$WA1.UIM_1875 \ 0 17487 (_entity .  X_BUF)
		(_port
			((I) (\outDATA<3>\\$WA1.UIM_MC.Q \))
			((O) (\outDATA<3>\\$WA1.UIM \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \outDATA<3>\\$WA1.UIM_MC.Q_1876 \ 0 17491 (_entity .  X_BUF)
		(_port
			((I) (\outDATA<3>\\$WA1.UIM_MC.D \))
			((O) (\outDATA<3>\\$WA1.UIM_MC.Q \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \outDATA<3>\\$WA1.UIM_MC.D_1877 \ 0 17495 (_entity .  X_XOR2)
		(_port
			((I0) (\outDATA<3>\\$WA1.UIM_MC.D1 \))
			((I1) (\outDATA<3>\\$WA1.UIM_MC.D2 \))
			((O) (\outDATA<3>\\$WA1.UIM_MC.D \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \outDATA<3>\\$WA1.UIM_MC.D1_1878 \ 0 17500 (_entity .  X_AND2)
		(_port
			((I0) (\I2CS<3>_II/UIM \))
			((I1) (\I2CS<3>_II/UIM \))
			((O) (\outDATA<3>\\$WA1.UIM_MC.D1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \outDATA<3>\\$WA1.UIM_MC.D2_1879 \ 0 17505 (_entity .  X_ZERO)
		(_port
			((O) (\outDATA<3>\\$WA1.UIM_MC.D2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \outDATA<3>\\$WA2.UIM_1880 \ 0 17508 (_entity .  X_BUF)
		(_port
			((I) (\outDATA<3>\\$WA2.UIM_MC.Q \))
			((O) (\outDATA<3>\\$WA2.UIM \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \outDATA<3>\\$WA2.UIM_MC.Q_1881 \ 0 17512 (_entity .  X_BUF)
		(_port
			((I) (\outDATA<3>\\$WA2.UIM_MC.D \))
			((O) (\outDATA<3>\\$WA2.UIM_MC.Q \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \outDATA<3>\\$WA2.UIM_MC.D_1882 \ 0 17516 (_entity .  X_XOR2)
		(_port
			((I0) (\outDATA<3>\\$WA2.UIM_MC.D1 \))
			((I1) (\outDATA<3>\\$WA2.UIM_MC.D2 \))
			((O) (\outDATA<3>\\$WA2.UIM_MC.D \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \outDATA<3>\\$WA2.UIM_MC.D1_1883 \ 0 17521 (_entity .  X_AND2)
		(_port
			((I0) (NET3248))
			((I1) (NET3248))
			((O) (\outDATA<3>\\$WA2.UIM_MC.D1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \outDATA<3>\\$WA2.UIM_MC.D2_1884 \ 0 17526 (_entity .  X_ZERO)
		(_port
			((O) (\outDATA<3>\\$WA2.UIM_MC.D2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \outDATA<3>\\$WA3.UIM_1885 \ 0 17529 (_entity .  X_BUF)
		(_port
			((I) (\outDATA<3>\\$WA3.UIM_MC.Q \))
			((O) (\outDATA<3>\\$WA3.UIM \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \outDATA<3>\\$WA3.UIM_MC.Q_1886 \ 0 17533 (_entity .  X_BUF)
		(_port
			((I) (\outDATA<3>\\$WA3.UIM_MC.D \))
			((O) (\outDATA<3>\\$WA3.UIM_MC.Q \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \outDATA<3>\\$WA3.UIM_MC.D_1887 \ 0 17537 (_entity .  X_XOR2)
		(_port
			((I0) (\outDATA<3>\\$WA3.UIM_MC.D1 \))
			((I1) (\outDATA<3>\\$WA3.UIM_MC.D2 \))
			((O) (\outDATA<3>\\$WA3.UIM_MC.D \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \outDATA<3>\\$WA3.UIM_MC.D1_1888 \ 0 17542 (_entity .  X_ZERO)
		(_port
			((O) (\outDATA<3>\\$WA3.UIM_MC.D1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \outDATA<3>\\$WA3.UIM_MC.D2_PT_0_1889 \ 0 17545 (_entity .  X_AND2)
		(_port
			((I0) (NET2528))
			((I1) (\U4/Flgreg \(3)))
			((O) (\outDATA<3>\\$WA3.UIM_MC.D2_PT_0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \outDATA<3>\\$WA3.UIM_MC.D2_PT_1_1890 \ 0 17550 (_entity .  X_AND2)
		(_port
			((I0) (\NlwInverterSignal_outDATA<3>\\$WA3.UIM_MC.D2_PT_1/IN0 \))
			((I1) (\Enc05FLG_II/UIM \))
			((O) (\outDATA<3>\\$WA3.UIM_MC.D2_PT_1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \outDATA<3>\\$WA3.UIM_MC.D2_1891 \ 0 17555 (_entity .  X_OR2)
		(_port
			((I0) (\outDATA<3>\\$WA3.UIM_MC.D2_PT_0 \))
			((I1) (\outDATA<3>\\$WA3.UIM_MC.D2_PT_1 \))
			((O) (\outDATA<3>\\$WA3.UIM_MC.D2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \outDATA<3>\\$WA5.UIM_1892 \ 0 17560 (_entity .  X_BUF)
		(_port
			((I) (\outDATA<3>\\$WA5.UIM_MC.Q \))
			((O) (\outDATA<3>\\$WA5.UIM \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \outDATA<3>\\$WA5.UIM_MC.Q_1893 \ 0 17564 (_entity .  X_BUF)
		(_port
			((I) (\outDATA<3>\\$WA5.UIM_MC.D \))
			((O) (\outDATA<3>\\$WA5.UIM_MC.Q \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \outDATA<3>\\$WA5.UIM_MC.D_1894 \ 0 17568 (_entity .  X_XOR2)
		(_port
			((I0) (\outDATA<3>\\$WA5.UIM_MC.D1 \))
			((I1) (\outDATA<3>\\$WA5.UIM_MC.D2 \))
			((O) (\outDATA<3>\\$WA5.UIM_MC.D \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \outDATA<3>\\$WA5.UIM_MC.D1_1895 \ 0 17573 (_entity .  X_ZERO)
		(_port
			((O) (\outDATA<3>\\$WA5.UIM_MC.D1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \outDATA<3>\\$WA5.UIM_MC.D2_PT_0_1896 \ 0 17576 (_entity .  X_AND2)
		(_port
			((I0) (N_PZ_966))
			((I1) (\U1/U3/holdingreg \(3)))
			((O) (\outDATA<3>\\$WA5.UIM_MC.D2_PT_0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \outDATA<3>\\$WA5.UIM_MC.D2_PT_1_1897 \ 0 17581 (_entity .  X_AND2)
		(_port
			((I0) (N_PZ_1002))
			((I1) (\U1/U3/holdingreg \(19)))
			((O) (\outDATA<3>\\$WA5.UIM_MC.D2_PT_1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \outDATA<3>\\$WA5.UIM_MC.D2_PT_2_1898 \ 0 17586 (_entity .  X_AND2)
		(_port
			((I0) (N_PZ_1061))
			((I1) (\U1/U3/holdingreg \(11)))
			((O) (\outDATA<3>\\$WA5.UIM_MC.D2_PT_2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \outDATA<3>\\$WA5.UIM_MC.D2_1899 \ 0 17591 (_entity .  X_OR3)
		(_port
			((I0) (\outDATA<3>\\$WA5.UIM_MC.D2_PT_0 \))
			((I1) (\outDATA<3>\\$WA5.UIM_MC.D2_PT_1 \))
			((I2) (\outDATA<3>\\$WA5.UIM_MC.D2_PT_2 \))
			((O) (\outDATA<3>\\$WA5.UIM_MC.D2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U3/holdingreg<3> \ 0 17597 (_entity .  X_BUF)
		(_port
			((I) (\U1/U3/holdingreg<3>_MC.Q \))
			((O) (\U1/U3/holdingreg \(3)))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U3/holdingreg<3>_MC.REG \ 0 17601 (_entity .  X_FF)
		(_port
			((I) (\U1/U3/holdingreg<3>_MC.D \))
			((CE) (Vcc))
			((CLK) (\U1/U3/holdingreg<3>_MC.REG_tsimcreated_inv_Mclk_II/FCLK \))
			((SET) (Gnd))
			((RST) (PRLD))
			((O) (\U1/U3/holdingreg<3>_MC.Q \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U3/holdingreg<3>_MC.REG_tsimcreated_inv_Mclk_II/FCLK_1900 \ 0 17609 (_entity .  X_INV)
		(_port
			((I) (\Mclk_II/FCLK \))
			((O) (\U1/U3/holdingreg<3>_MC.REG_tsimcreated_inv_Mclk_II/FCLK \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U3/holdingreg<3>_MC.D_1901 \ 0 17613 (_entity .  X_XOR2)
		(_port
			((I0) (\U1/U3/holdingreg<3>_MC.D1 \))
			((I1) (\U1/U3/holdingreg<3>_MC.D2 \))
			((O) (\U1/U3/holdingreg<3>_MC.D \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U3/holdingreg<3>_MC.D1_1902 \ 0 17618 (_entity .  X_ZERO)
		(_port
			((O) (\U1/U3/holdingreg<3>_MC.D1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U3/holdingreg<3>_MC.D2_PT_0_1903 \ 0 17621 (_entity .  X_AND2)
		(_port
			((I0) (N_PZ_986))
			((I1) (\U1/Channel1 \(3)))
			((O) (\U1/U3/holdingreg<3>_MC.D2_PT_0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U3/holdingreg<3>_MC.D2_PT_1_1904 \ 0 17626 (_entity .  X_AND3)
		(_port
			((I0) (\NlwInverterSignal_U1/U3/holdingreg<3>_MC.D2_PT_1/IN0 \))
			((I1) (\U1/U3/RDedge \))
			((I2) (\U1/U3/holdingreg \(3)))
			((O) (\U1/U3/holdingreg<3>_MC.D2_PT_1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U3/holdingreg<3>_MC.D2_PT_2_1905 \ 0 17632 (_entity .  X_AND16)
		(_port
			((I0) (\WR_II/UIM \))
			((I1) (\NlwInverterSignal_U1/U3/holdingreg<3>_MC.D2_PT_2/IN1 \))
			((I2) (U2_ADDR_reg(1)))
			((I3) (U2_ADDR_reg(0)))
			((I4) (N_PZ_931))
			((I5) (U2_ADDR_reg(2)))
			((I6) (\NlwInverterSignal_U1/U3/holdingreg<3>_MC.D2_PT_2/IN6 \))
			((I7) (\NlwInverterSignal_U1/U3/holdingreg<3>_MC.D2_PT_2/IN7 \))
			((I8) (\NlwInverterSignal_U1/U3/holdingreg<3>_MC.D2_PT_2/IN8 \))
			((I9) (\U1/Channel0 \(3)))
			((I10) (Vcc))
			((I11) (Vcc))
			((I12) (Vcc))
			((I13) (Vcc))
			((I14) (Vcc))
			((I15) (Vcc))
			((O) (\U1/U3/holdingreg<3>_MC.D2_PT_2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U3/holdingreg<3>_MC.D2_1906 \ 0 17651 (_entity .  X_OR3)
		(_port
			((I0) (\U1/U3/holdingreg<3>_MC.D2_PT_0 \))
			((I1) (\U1/U3/holdingreg<3>_MC.D2_PT_1 \))
			((I2) (\U1/U3/holdingreg<3>_MC.D2_PT_2 \))
			((O) (\U1/U3/holdingreg<3>_MC.D2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U3/holdingreg<19> \ 0 17657 (_entity .  X_BUF)
		(_port
			((I) (\U1/U3/holdingreg<19>_MC.Q \))
			((O) (\U1/U3/holdingreg \(19)))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U3/holdingreg<19>_MC.REG \ 0 17661 (_entity .  X_FF)
		(_port
			((I) (\U1/U3/holdingreg<19>_MC.D \))
			((CE) (Vcc))
			((CLK) (\U1/U3/holdingreg<19>_MC.REG_tsimcreated_inv_Mclk_II/FCLK \))
			((SET) (Gnd))
			((RST) (PRLD))
			((O) (\U1/U3/holdingreg<19>_MC.Q \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U3/holdingreg<19>_MC.REG_tsimcreated_inv_Mclk_II/FCLK_1907 \ 0 17669 (_entity .  X_INV)
		(_port
			((I) (\Mclk_II/FCLK \))
			((O) (\U1/U3/holdingreg<19>_MC.REG_tsimcreated_inv_Mclk_II/FCLK \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U3/holdingreg<19>_MC.D_1908 \ 0 17673 (_entity .  X_XOR2)
		(_port
			((I0) (\U1/U3/holdingreg<19>_MC.D1 \))
			((I1) (\U1/U3/holdingreg<19>_MC.D2 \))
			((O) (\U1/U3/holdingreg<19>_MC.D \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U3/holdingreg<19>_MC.D1_1909 \ 0 17678 (_entity .  X_ZERO)
		(_port
			((O) (\U1/U3/holdingreg<19>_MC.D1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U3/holdingreg<19>_MC.D2_PT_0_1910 \ 0 17681 (_entity .  X_AND2)
		(_port
			((I0) (N_PZ_986))
			((I1) (\U1/Channel1 \(19)))
			((O) (\U1/U3/holdingreg<19>_MC.D2_PT_0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U3/holdingreg<19>_MC.D2_PT_1_1911 \ 0 17686 (_entity .  X_AND3)
		(_port
			((I0) (\NlwInverterSignal_U1/U3/holdingreg<19>_MC.D2_PT_1/IN0 \))
			((I1) (\U1/U3/RDedge \))
			((I2) (\U1/U3/holdingreg \(19)))
			((O) (\U1/U3/holdingreg<19>_MC.D2_PT_1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U3/holdingreg<19>_MC.D2_PT_2_1912 \ 0 17692 (_entity .  X_AND16)
		(_port
			((I0) (\WR_II/UIM \))
			((I1) (\NlwInverterSignal_U1/U3/holdingreg<19>_MC.D2_PT_2/IN1 \))
			((I2) (U2_ADDR_reg(1)))
			((I3) (U2_ADDR_reg(0)))
			((I4) (N_PZ_931))
			((I5) (U2_ADDR_reg(2)))
			((I6) (\NlwInverterSignal_U1/U3/holdingreg<19>_MC.D2_PT_2/IN6 \))
			((I7) (\NlwInverterSignal_U1/U3/holdingreg<19>_MC.D2_PT_2/IN7 \))
			((I8) (\NlwInverterSignal_U1/U3/holdingreg<19>_MC.D2_PT_2/IN8 \))
			((I9) (\U1/Channel0 \(19)))
			((I10) (Vcc))
			((I11) (Vcc))
			((I12) (Vcc))
			((I13) (Vcc))
			((I14) (Vcc))
			((I15) (Vcc))
			((O) (\U1/U3/holdingreg<19>_MC.D2_PT_2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U3/holdingreg<19>_MC.D2_1913 \ 0 17711 (_entity .  X_OR3)
		(_port
			((I0) (\U1/U3/holdingreg<19>_MC.D2_PT_0 \))
			((I1) (\U1/U3/holdingreg<19>_MC.D2_PT_1 \))
			((I2) (\U1/U3/holdingreg<19>_MC.D2_PT_2 \))
			((O) (\U1/U3/holdingreg<19>_MC.D2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U3/holdingreg<11> \ 0 17717 (_entity .  X_BUF)
		(_port
			((I) (\U1/U3/holdingreg<11>_MC.Q \))
			((O) (\U1/U3/holdingreg \(11)))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U3/holdingreg<11>_MC.REG \ 0 17721 (_entity .  X_FF)
		(_port
			((I) (\U1/U3/holdingreg<11>_MC.D \))
			((CE) (Vcc))
			((CLK) (\U1/U3/holdingreg<11>_MC.REG_tsimcreated_inv_Mclk_II/FCLK \))
			((SET) (Gnd))
			((RST) (PRLD))
			((O) (\U1/U3/holdingreg<11>_MC.Q \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U3/holdingreg<11>_MC.REG_tsimcreated_inv_Mclk_II/FCLK_1914 \ 0 17729 (_entity .  X_INV)
		(_port
			((I) (\Mclk_II/FCLK \))
			((O) (\U1/U3/holdingreg<11>_MC.REG_tsimcreated_inv_Mclk_II/FCLK \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U3/holdingreg<11>_MC.D_1915 \ 0 17733 (_entity .  X_XOR2)
		(_port
			((I0) (\U1/U3/holdingreg<11>_MC.D1 \))
			((I1) (\U1/U3/holdingreg<11>_MC.D2 \))
			((O) (\U1/U3/holdingreg<11>_MC.D \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U3/holdingreg<11>_MC.D1_1916 \ 0 17738 (_entity .  X_ZERO)
		(_port
			((O) (\U1/U3/holdingreg<11>_MC.D1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U3/holdingreg<11>_MC.D2_PT_0_1917 \ 0 17741 (_entity .  X_AND2)
		(_port
			((I0) (N_PZ_986))
			((I1) (\U1/Channel1 \(11)))
			((O) (\U1/U3/holdingreg<11>_MC.D2_PT_0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U3/holdingreg<11>_MC.D2_PT_1_1918 \ 0 17746 (_entity .  X_AND3)
		(_port
			((I0) (\NlwInverterSignal_U1/U3/holdingreg<11>_MC.D2_PT_1/IN0 \))
			((I1) (\U1/U3/RDedge \))
			((I2) (\U1/U3/holdingreg \(11)))
			((O) (\U1/U3/holdingreg<11>_MC.D2_PT_1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U3/holdingreg<11>_MC.D2_PT_2_1919 \ 0 17752 (_entity .  X_AND16)
		(_port
			((I0) (\WR_II/UIM \))
			((I1) (\NlwInverterSignal_U1/U3/holdingreg<11>_MC.D2_PT_2/IN1 \))
			((I2) (U2_ADDR_reg(1)))
			((I3) (U2_ADDR_reg(0)))
			((I4) (N_PZ_931))
			((I5) (U2_ADDR_reg(2)))
			((I6) (\NlwInverterSignal_U1/U3/holdingreg<11>_MC.D2_PT_2/IN6 \))
			((I7) (\NlwInverterSignal_U1/U3/holdingreg<11>_MC.D2_PT_2/IN7 \))
			((I8) (\NlwInverterSignal_U1/U3/holdingreg<11>_MC.D2_PT_2/IN8 \))
			((I9) (\U1/Channel0 \(11)))
			((I10) (Vcc))
			((I11) (Vcc))
			((I12) (Vcc))
			((I13) (Vcc))
			((I14) (Vcc))
			((I15) (Vcc))
			((O) (\U1/U3/holdingreg<11>_MC.D2_PT_2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U3/holdingreg<11>_MC.D2_1920 \ 0 17771 (_entity .  X_OR3)
		(_port
			((I0) (\U1/U3/holdingreg<11>_MC.D2_PT_0 \))
			((I1) (\U1/U3/holdingreg<11>_MC.D2_PT_1 \))
			((I2) (\U1/U3/holdingreg<11>_MC.D2_PT_2 \))
			((O) (\U1/U3/holdingreg<11>_MC.D2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \outDATA<3>\\$WA4.UIM_1921 \ 0 17777 (_entity .  X_BUF)
		(_port
			((I) (\outDATA<3>\\$WA4.UIM_MC.Q \))
			((O) (\outDATA<3>\\$WA4.UIM \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \outDATA<3>\\$WA4.UIM_MC.Q_1922 \ 0 17781 (_entity .  X_BUF)
		(_port
			((I) (\outDATA<3>\\$WA4.UIM_MC.D \))
			((O) (\outDATA<3>\\$WA4.UIM_MC.Q \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \outDATA<3>\\$WA4.UIM_MC.D_1923 \ 0 17785 (_entity .  X_XOR2)
		(_port
			((I0) (\outDATA<3>\\$WA4.UIM_MC.D1 \))
			((I1) (\outDATA<3>\\$WA4.UIM_MC.D2 \))
			((O) (\outDATA<3>\\$WA4.UIM_MC.D \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \outDATA<3>\\$WA4.UIM_MC.D1_1924 \ 0 17790 (_entity .  X_ZERO)
		(_port
			((O) (\outDATA<3>\\$WA4.UIM_MC.D1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \outDATA<3>\\$WA4.UIM_MC.D2_PT_0_1925 \ 0 17793 (_entity .  X_AND2)
		(_port
			((I0) (N_PZ_1003))
			((I1) (\U1/U4/Latch1r \(11)))
			((O) (\outDATA<3>\\$WA4.UIM_MC.D2_PT_0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \outDATA<3>\\$WA4.UIM_MC.D2_PT_1_1926 \ 0 17798 (_entity .  X_AND8)
		(_port
			((I0) (\WR_II/UIM \))
			((I1) (\NlwInverterSignal_outDATA<3>\\$WA4.UIM_MC.D2_PT_1/IN1 \))
			((I2) (U2_ADDR_reg(1)))
			((I3) (U2_ADDR_reg(0)))
			((I4) (N_PZ_931))
			((I5) (\NlwInverterSignal_outDATA<3>\\$WA4.UIM_MC.D2_PT_1/IN5 \))
			((I6) (U2_ADDR_reg(3)))
			((I7) (\U1/U4/Latch0r \(11)))
			((O) (\outDATA<3>\\$WA4.UIM_MC.D2_PT_1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \outDATA<3>\\$WA4.UIM_MC.D2_PT_2_1927 \ 0 17809 (_entity .  X_AND8)
		(_port
			((I0) (\WR_II/UIM \))
			((I1) (\NlwInverterSignal_outDATA<3>\\$WA4.UIM_MC.D2_PT_2/IN1 \))
			((I2) (U2_ADDR_reg(1)))
			((I3) (\NlwInverterSignal_outDATA<3>\\$WA4.UIM_MC.D2_PT_2/IN3 \))
			((I4) (N_PZ_931))
			((I5) (\NlwInverterSignal_outDATA<3>\\$WA4.UIM_MC.D2_PT_2/IN5 \))
			((I6) (U2_ADDR_reg(3)))
			((I7) (\U1/U4/Latch0r \(3)))
			((O) (\outDATA<3>\\$WA4.UIM_MC.D2_PT_2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \outDATA<3>\\$WA4.UIM_MC.D2_PT_3_1928 \ 0 17820 (_entity .  X_AND8)
		(_port
			((I0) (\WR_II/UIM \))
			((I1) (\NlwInverterSignal_outDATA<3>\\$WA4.UIM_MC.D2_PT_3/IN1 \))
			((I2) (\NlwInverterSignal_outDATA<3>\\$WA4.UIM_MC.D2_PT_3/IN2 \))
			((I3) (\NlwInverterSignal_outDATA<3>\\$WA4.UIM_MC.D2_PT_3/IN3 \))
			((I4) (N_PZ_931))
			((I5) (U2_ADDR_reg(2)))
			((I6) (U2_ADDR_reg(3)))
			((I7) (\U1/U4/Latch1r \(3)))
			((O) (\outDATA<3>\\$WA4.UIM_MC.D2_PT_3 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \outDATA<3>\\$WA4.UIM_MC.D2_1929 \ 0 17831 (_entity .  X_OR4)
		(_port
			((I0) (\outDATA<3>\\$WA4.UIM_MC.D2_PT_0 \))
			((I1) (\outDATA<3>\\$WA4.UIM_MC.D2_PT_1 \))
			((I2) (\outDATA<3>\\$WA4.UIM_MC.D2_PT_2 \))
			((I3) (\outDATA<3>\\$WA4.UIM_MC.D2_PT_3 \))
			((O) (\outDATA<3>\\$WA4.UIM_MC.D2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U4/Latch0r<11> \ 0 17838 (_entity .  X_BUF)
		(_port
			((I) (\U1/U4/Latch0r<11>_MC.Q \))
			((O) (\U1/U4/Latch0r \(11)))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U4/Latch0r<11>_MC.REG \ 0 17842 (_entity .  X_FF)
		(_port
			((I) (\U1/U4/Latch0r<11>_MC.D \))
			((CE) (Vcc))
			((CLK) (\U1/U4/Latch0r<11>_MC.REG_tsimcreated_inv_Mclk_II/FCLK \))
			((SET) (Gnd))
			((RST) (PRLD))
			((O) (\U1/U4/Latch0r<11>_MC.Q \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U4/Latch0r<11>_MC.REG_tsimcreated_inv_Mclk_II/FCLK_1930 \ 0 17850 (_entity .  X_INV)
		(_port
			((I) (\Mclk_II/FCLK \))
			((O) (\U1/U4/Latch0r<11>_MC.REG_tsimcreated_inv_Mclk_II/FCLK \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U4/Latch0r<11>_MC.D_1931 \ 0 17854 (_entity .  X_XOR2)
		(_port
			((I0) (\U1/U4/Latch0r<11>_MC.D1 \))
			((I1) (\U1/U4/Latch0r<11>_MC.D2 \))
			((O) (\U1/U4/Latch0r<11>_MC.D \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U4/Latch0r<11>_MC.D1_1932 \ 0 17859 (_entity .  X_ZERO)
		(_port
			((O) (\U1/U4/Latch0r<11>_MC.D1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U4/Latch0r<11>_MC.D2_PT_0_1933 \ 0 17862 (_entity .  X_AND2)
		(_port
			((I0) (N_PZ_1059))
			((I1) (\U1/U4/Latch0r \(11)))
			((O) (\U1/U4/Latch0r<11>_MC.D2_PT_0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U4/Latch0r<11>_MC.D2_PT_1_1934 \ 0 17867 (_entity .  X_AND3)
		(_port
			((I0) (\NlwInverterSignal_U1/U4/Latch0r<11>_MC.D2_PT_1/IN0 \))
			((I1) (\U1/Channel0 \(11)))
			((I2) (\NlwInverterSignal_U1/U4/Latch0r<11>_MC.D2_PT_1/IN2 \))
			((O) (\U1/U4/Latch0r<11>_MC.D2_PT_1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U4/Latch0r<11>_MC.D2_1935 \ 0 17873 (_entity .  X_OR2)
		(_port
			((I0) (\U1/U4/Latch0r<11>_MC.D2_PT_0 \))
			((I1) (\U1/U4/Latch0r<11>_MC.D2_PT_1 \))
			((O) (\U1/U4/Latch0r<11>_MC.D2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U4/Latch0r<3> \ 0 17878 (_entity .  X_BUF)
		(_port
			((I) (\U1/U4/Latch0r<3>_MC.Q \))
			((O) (\U1/U4/Latch0r \(3)))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U4/Latch0r<3>_MC.REG \ 0 17882 (_entity .  X_FF)
		(_port
			((I) (\U1/U4/Latch0r<3>_MC.D \))
			((CE) (Vcc))
			((CLK) (\U1/U4/Latch0r<3>_MC.REG_tsimcreated_inv_Mclk_II/FCLK \))
			((SET) (Gnd))
			((RST) (PRLD))
			((O) (\U1/U4/Latch0r<3>_MC.Q \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U4/Latch0r<3>_MC.REG_tsimcreated_inv_Mclk_II/FCLK_1936 \ 0 17890 (_entity .  X_INV)
		(_port
			((I) (\Mclk_II/FCLK \))
			((O) (\U1/U4/Latch0r<3>_MC.REG_tsimcreated_inv_Mclk_II/FCLK \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U4/Latch0r<3>_MC.D_1937 \ 0 17894 (_entity .  X_XOR2)
		(_port
			((I0) (\U1/U4/Latch0r<3>_MC.D1 \))
			((I1) (\U1/U4/Latch0r<3>_MC.D2 \))
			((O) (\U1/U4/Latch0r<3>_MC.D \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U4/Latch0r<3>_MC.D1_1938 \ 0 17899 (_entity .  X_ZERO)
		(_port
			((O) (\U1/U4/Latch0r<3>_MC.D1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U4/Latch0r<3>_MC.D2_PT_0_1939 \ 0 17902 (_entity .  X_AND2)
		(_port
			((I0) (N_PZ_1059))
			((I1) (\U1/U4/Latch0r \(3)))
			((O) (\U1/U4/Latch0r<3>_MC.D2_PT_0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U4/Latch0r<3>_MC.D2_PT_1_1940 \ 0 17907 (_entity .  X_AND3)
		(_port
			((I0) (\NlwInverterSignal_U1/U4/Latch0r<3>_MC.D2_PT_1/IN0 \))
			((I1) (\U1/Channel0 \(3)))
			((I2) (\NlwInverterSignal_U1/U4/Latch0r<3>_MC.D2_PT_1/IN2 \))
			((O) (\U1/U4/Latch0r<3>_MC.D2_PT_1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U4/Latch0r<3>_MC.D2_1941 \ 0 17913 (_entity .  X_OR2)
		(_port
			((I0) (\U1/U4/Latch0r<3>_MC.D2_PT_0 \))
			((I1) (\U1/U4/Latch0r<3>_MC.D2_PT_1 \))
			((O) (\U1/U4/Latch0r<3>_MC.D2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U4/Latch1r<3> \ 0 17918 (_entity .  X_BUF)
		(_port
			((I) (\U1/U4/Latch1r<3>_MC.Q \))
			((O) (\U1/U4/Latch1r \(3)))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U4/Latch1r<3>_MC.REG \ 0 17922 (_entity .  X_FF)
		(_port
			((I) (\U1/U4/Latch1r<3>_MC.D \))
			((CE) (Vcc))
			((CLK) (\U1/U4/Latch1r<3>_MC.REG_tsimcreated_inv_Mclk_II/FCLK \))
			((SET) (Gnd))
			((RST) (PRLD))
			((O) (\U1/U4/Latch1r<3>_MC.Q \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U4/Latch1r<3>_MC.REG_tsimcreated_inv_Mclk_II/FCLK_1942 \ 0 17930 (_entity .  X_INV)
		(_port
			((I) (\Mclk_II/FCLK \))
			((O) (\U1/U4/Latch1r<3>_MC.REG_tsimcreated_inv_Mclk_II/FCLK \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U4/Latch1r<3>_MC.D_1943 \ 0 17934 (_entity .  X_XOR2)
		(_port
			((I0) (\U1/U4/Latch1r<3>_MC.D1 \))
			((I1) (\U1/U4/Latch1r<3>_MC.D2 \))
			((O) (\U1/U4/Latch1r<3>_MC.D \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U4/Latch1r<3>_MC.D1_1944 \ 0 17939 (_entity .  X_ZERO)
		(_port
			((O) (\U1/U4/Latch1r<3>_MC.D1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U4/Latch1r<3>_MC.D2_PT_0_1945 \ 0 17942 (_entity .  X_AND2)
		(_port
			((I0) (\NlwInverterSignal_U1/U4/Latch1r<3>_MC.D2_PT_0/IN0 \))
			((I1) (\U1/Channel1 \(3)))
			((O) (\U1/U4/Latch1r<3>_MC.D2_PT_0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U4/Latch1r<3>_MC.D2_PT_1_1946 \ 0 17947 (_entity .  X_AND8)
		(_port
			((I0) (\NlwInverterSignal_U1/U4/Latch1r<3>_MC.D2_PT_1/IN0 \))
			((I1) (\RD_II/UIM \))
			((I2) (U2_ADDR_reg(1)))
			((I3) (N_PZ_931))
			((I4) (\NlwInverterSignal_U1/U4/Latch1r<3>_MC.D2_PT_1/IN4 \))
			((I5) (\NlwInverterSignal_U1/U4/Latch1r<3>_MC.D2_PT_1/IN5 \))
			((I6) (\NlwInverterSignal_U1/U4/Latch1r<3>_MC.D2_PT_1/IN6 \))
			((I7) (\U1/U4/Latch1r \(3)))
			((O) (\U1/U4/Latch1r<3>_MC.D2_PT_1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U4/Latch1r<3>_MC.D2_1947 \ 0 17958 (_entity .  X_OR2)
		(_port
			((I0) (\U1/U4/Latch1r<3>_MC.D2_PT_0 \))
			((I1) (\U1/U4/Latch1r<3>_MC.D2_PT_1 \))
			((O) (\U1/U4/Latch1r<3>_MC.D2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U4/Latch1r<11> \ 0 17963 (_entity .  X_BUF)
		(_port
			((I) (\U1/U4/Latch1r<11>_MC.Q \))
			((O) (\U1/U4/Latch1r \(11)))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U4/Latch1r<11>_MC.REG \ 0 17967 (_entity .  X_FF)
		(_port
			((I) (\U1/U4/Latch1r<11>_MC.D \))
			((CE) (Vcc))
			((CLK) (\U1/U4/Latch1r<11>_MC.REG_tsimcreated_inv_Mclk_II/FCLK \))
			((SET) (Gnd))
			((RST) (PRLD))
			((O) (\U1/U4/Latch1r<11>_MC.Q \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U4/Latch1r<11>_MC.REG_tsimcreated_inv_Mclk_II/FCLK_1948 \ 0 17975 (_entity .  X_INV)
		(_port
			((I) (\Mclk_II/FCLK \))
			((O) (\U1/U4/Latch1r<11>_MC.REG_tsimcreated_inv_Mclk_II/FCLK \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U4/Latch1r<11>_MC.D_1949 \ 0 17979 (_entity .  X_XOR2)
		(_port
			((I0) (\U1/U4/Latch1r<11>_MC.D1 \))
			((I1) (\U1/U4/Latch1r<11>_MC.D2 \))
			((O) (\U1/U4/Latch1r<11>_MC.D \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U4/Latch1r<11>_MC.D1_1950 \ 0 17984 (_entity .  X_ZERO)
		(_port
			((O) (\U1/U4/Latch1r<11>_MC.D1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U4/Latch1r<11>_MC.D2_PT_0_1951 \ 0 17987 (_entity .  X_AND2)
		(_port
			((I0) (\NlwInverterSignal_U1/U4/Latch1r<11>_MC.D2_PT_0/IN0 \))
			((I1) (\U1/Channel1 \(11)))
			((O) (\U1/U4/Latch1r<11>_MC.D2_PT_0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U4/Latch1r<11>_MC.D2_PT_1_1952 \ 0 17992 (_entity .  X_AND8)
		(_port
			((I0) (\NlwInverterSignal_U1/U4/Latch1r<11>_MC.D2_PT_1/IN0 \))
			((I1) (\RD_II/UIM \))
			((I2) (U2_ADDR_reg(1)))
			((I3) (N_PZ_931))
			((I4) (\NlwInverterSignal_U1/U4/Latch1r<11>_MC.D2_PT_1/IN4 \))
			((I5) (\NlwInverterSignal_U1/U4/Latch1r<11>_MC.D2_PT_1/IN5 \))
			((I6) (\NlwInverterSignal_U1/U4/Latch1r<11>_MC.D2_PT_1/IN6 \))
			((I7) (\U1/U4/Latch1r \(11)))
			((O) (\U1/U4/Latch1r<11>_MC.D2_PT_1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U4/Latch1r<11>_MC.D2_1953 \ 0 18003 (_entity .  X_OR2)
		(_port
			((I0) (\U1/U4/Latch1r<11>_MC.D2_PT_0 \))
			((I1) (\U1/U4/Latch1r<11>_MC.D2_PT_1 \))
			((O) (\U1/U4/Latch1r<11>_MC.D2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \outDATA<4>\\$WA0.UIM_1954 \ 0 18008 (_entity .  X_BUF)
		(_port
			((I) (\outDATA<4>\\$WA0.UIM_MC.Q \))
			((O) (\outDATA<4>\\$WA0.UIM \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \outDATA<4>\\$WA0.UIM_MC.Q_1955 \ 0 18012 (_entity .  X_BUF)
		(_port
			((I) (\outDATA<4>\\$WA0.UIM_MC.D \))
			((O) (\outDATA<4>\\$WA0.UIM_MC.Q \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \outDATA<4>\\$WA0.UIM_MC.D_1956 \ 0 18016 (_entity .  X_XOR2)
		(_port
			((I0) (\outDATA<4>\\$WA0.UIM_MC.D1 \))
			((I1) (\outDATA<4>\\$WA0.UIM_MC.D2 \))
			((O) (\outDATA<4>\\$WA0.UIM_MC.D \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \outDATA<4>\\$WA0.UIM_MC.D1_1957 \ 0 18021 (_entity .  X_AND2)
		(_port
			((I0) (U11_U3_counterr(4)))
			((I1) (U11_U3_counterr(4)))
			((O) (\outDATA<4>\\$WA0.UIM_MC.D1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \outDATA<4>\\$WA0.UIM_MC.D2_1958 \ 0 18026 (_entity .  X_ZERO)
		(_port
			((O) (\outDATA<4>\\$WA0.UIM_MC.D2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \outDATA<4>\\$WA1.UIM_1959 \ 0 18029 (_entity .  X_BUF)
		(_port
			((I) (\outDATA<4>\\$WA1.UIM_MC.Q \))
			((O) (\outDATA<4>\\$WA1.UIM \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \outDATA<4>\\$WA1.UIM_MC.Q_1960 \ 0 18033 (_entity .  X_BUF)
		(_port
			((I) (\outDATA<4>\\$WA1.UIM_MC.D \))
			((O) (\outDATA<4>\\$WA1.UIM_MC.Q \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \outDATA<4>\\$WA1.UIM_MC.D_1961 \ 0 18037 (_entity .  X_XOR2)
		(_port
			((I0) (\outDATA<4>\\$WA1.UIM_MC.D1 \))
			((I1) (\outDATA<4>\\$WA1.UIM_MC.D2 \))
			((O) (\outDATA<4>\\$WA1.UIM_MC.D \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \outDATA<4>\\$WA1.UIM_MC.D1_1962 \ 0 18042 (_entity .  X_AND2)
		(_port
			((I0) (\I2CS<4>_II/UIM \))
			((I1) (\I2CS<4>_II/UIM \))
			((O) (\outDATA<4>\\$WA1.UIM_MC.D1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \outDATA<4>\\$WA1.UIM_MC.D2_1963 \ 0 18047 (_entity .  X_ZERO)
		(_port
			((O) (\outDATA<4>\\$WA1.UIM_MC.D2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \outDATA<4>\\$WA2.UIM_1964 \ 0 18050 (_entity .  X_BUF)
		(_port
			((I) (\outDATA<4>\\$WA2.UIM_MC.Q \))
			((O) (\outDATA<4>\\$WA2.UIM \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \outDATA<4>\\$WA2.UIM_MC.Q_1965 \ 0 18054 (_entity .  X_BUF)
		(_port
			((I) (\outDATA<4>\\$WA2.UIM_MC.D \))
			((O) (\outDATA<4>\\$WA2.UIM_MC.Q \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \outDATA<4>\\$WA2.UIM_MC.D_1966 \ 0 18058 (_entity .  X_XOR2)
		(_port
			((I0) (\outDATA<4>\\$WA2.UIM_MC.D1 \))
			((I1) (\outDATA<4>\\$WA2.UIM_MC.D2 \))
			((O) (\outDATA<4>\\$WA2.UIM_MC.D \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \outDATA<4>\\$WA2.UIM_MC.D1_1967 \ 0 18063 (_entity .  X_AND2)
		(_port
			((I0) (\RLS1_II/UIM \))
			((I1) (\RLS1_II/UIM \))
			((O) (\outDATA<4>\\$WA2.UIM_MC.D1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \outDATA<4>\\$WA2.UIM_MC.D2_1968 \ 0 18068 (_entity .  X_ZERO)
		(_port
			((O) (\outDATA<4>\\$WA2.UIM_MC.D2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \outDATA<4>\\$WA3.UIM_1969 \ 0 18071 (_entity .  X_BUF)
		(_port
			((I) (\outDATA<4>\\$WA3.UIM_MC.Q \))
			((O) (\outDATA<4>\\$WA3.UIM \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \outDATA<4>\\$WA3.UIM_MC.Q_1970 \ 0 18075 (_entity .  X_BUF)
		(_port
			((I) (\outDATA<4>\\$WA3.UIM_MC.D \))
			((O) (\outDATA<4>\\$WA3.UIM_MC.Q \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \outDATA<4>\\$WA3.UIM_MC.D_1971 \ 0 18079 (_entity .  X_XOR2)
		(_port
			((I0) (\outDATA<4>\\$WA3.UIM_MC.D1 \))
			((I1) (\outDATA<4>\\$WA3.UIM_MC.D2 \))
			((O) (\outDATA<4>\\$WA3.UIM_MC.D \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \outDATA<4>\\$WA3.UIM_MC.D1_1972 \ 0 18084 (_entity .  X_ZERO)
		(_port
			((O) (\outDATA<4>\\$WA3.UIM_MC.D1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \outDATA<4>\\$WA3.UIM_MC.D2_PT_0_1973 \ 0 18087 (_entity .  X_AND2)
		(_port
			((I0) (NET2528))
			((I1) (\U4/Flgreg \(4)))
			((O) (\outDATA<4>\\$WA3.UIM_MC.D2_PT_0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \outDATA<4>\\$WA3.UIM_MC.D2_PT_1_1974 \ 0 18092 (_entity .  X_AND2)
		(_port
			((I0) (\NlwInverterSignal_outDATA<4>\\$WA3.UIM_MC.D2_PT_1/IN0 \))
			((I1) (\Home133FLG_II/UIM \))
			((O) (\outDATA<4>\\$WA3.UIM_MC.D2_PT_1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \outDATA<4>\\$WA3.UIM_MC.D2_1975 \ 0 18097 (_entity .  X_OR2)
		(_port
			((I0) (\outDATA<4>\\$WA3.UIM_MC.D2_PT_0 \))
			((I1) (\outDATA<4>\\$WA3.UIM_MC.D2_PT_1 \))
			((O) (\outDATA<4>\\$WA3.UIM_MC.D2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \outDATA<4>\\$WA5.UIM_1976 \ 0 18102 (_entity .  X_BUF)
		(_port
			((I) (\outDATA<4>\\$WA5.UIM_MC.Q \))
			((O) (\outDATA<4>\\$WA5.UIM \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \outDATA<4>\\$WA5.UIM_MC.Q_1977 \ 0 18106 (_entity .  X_BUF)
		(_port
			((I) (\outDATA<4>\\$WA5.UIM_MC.D \))
			((O) (\outDATA<4>\\$WA5.UIM_MC.Q \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \outDATA<4>\\$WA5.UIM_MC.D_1978 \ 0 18110 (_entity .  X_XOR2)
		(_port
			((I0) (\outDATA<4>\\$WA5.UIM_MC.D1 \))
			((I1) (\outDATA<4>\\$WA5.UIM_MC.D2 \))
			((O) (\outDATA<4>\\$WA5.UIM_MC.D \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \outDATA<4>\\$WA5.UIM_MC.D1_1979 \ 0 18115 (_entity .  X_ZERO)
		(_port
			((O) (\outDATA<4>\\$WA5.UIM_MC.D1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \outDATA<4>\\$WA5.UIM_MC.D2_PT_0_1980 \ 0 18118 (_entity .  X_AND2)
		(_port
			((I0) (N_PZ_966))
			((I1) (\U1/U3/holdingreg \(4)))
			((O) (\outDATA<4>\\$WA5.UIM_MC.D2_PT_0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \outDATA<4>\\$WA5.UIM_MC.D2_PT_1_1981 \ 0 18123 (_entity .  X_AND2)
		(_port
			((I0) (N_PZ_1002))
			((I1) (\U1/U3/holdingreg \(20)))
			((O) (\outDATA<4>\\$WA5.UIM_MC.D2_PT_1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \outDATA<4>\\$WA5.UIM_MC.D2_PT_2_1982 \ 0 18128 (_entity .  X_AND2)
		(_port
			((I0) (N_PZ_1061))
			((I1) (\U1/U3/holdingreg \(12)))
			((O) (\outDATA<4>\\$WA5.UIM_MC.D2_PT_2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \outDATA<4>\\$WA5.UIM_MC.D2_1983 \ 0 18133 (_entity .  X_OR3)
		(_port
			((I0) (\outDATA<4>\\$WA5.UIM_MC.D2_PT_0 \))
			((I1) (\outDATA<4>\\$WA5.UIM_MC.D2_PT_1 \))
			((I2) (\outDATA<4>\\$WA5.UIM_MC.D2_PT_2 \))
			((O) (\outDATA<4>\\$WA5.UIM_MC.D2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U3/holdingreg<4> \ 0 18139 (_entity .  X_BUF)
		(_port
			((I) (\U1/U3/holdingreg<4>_MC.Q \))
			((O) (\U1/U3/holdingreg \(4)))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U3/holdingreg<4>_MC.REG \ 0 18143 (_entity .  X_FF)
		(_port
			((I) (\U1/U3/holdingreg<4>_MC.D \))
			((CE) (Vcc))
			((CLK) (\U1/U3/holdingreg<4>_MC.REG_tsimcreated_inv_Mclk_II/FCLK \))
			((SET) (Gnd))
			((RST) (PRLD))
			((O) (\U1/U3/holdingreg<4>_MC.Q \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U3/holdingreg<4>_MC.REG_tsimcreated_inv_Mclk_II/FCLK_1984 \ 0 18151 (_entity .  X_INV)
		(_port
			((I) (\Mclk_II/FCLK \))
			((O) (\U1/U3/holdingreg<4>_MC.REG_tsimcreated_inv_Mclk_II/FCLK \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U3/holdingreg<4>_MC.D_1985 \ 0 18155 (_entity .  X_XOR2)
		(_port
			((I0) (\U1/U3/holdingreg<4>_MC.D1 \))
			((I1) (\U1/U3/holdingreg<4>_MC.D2 \))
			((O) (\U1/U3/holdingreg<4>_MC.D \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U3/holdingreg<4>_MC.D1_1986 \ 0 18160 (_entity .  X_ZERO)
		(_port
			((O) (\U1/U3/holdingreg<4>_MC.D1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U3/holdingreg<4>_MC.D2_PT_0_1987 \ 0 18163 (_entity .  X_AND2)
		(_port
			((I0) (N_PZ_986))
			((I1) (\U1/Channel1 \(4)))
			((O) (\U1/U3/holdingreg<4>_MC.D2_PT_0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U3/holdingreg<4>_MC.D2_PT_1_1988 \ 0 18168 (_entity .  X_AND3)
		(_port
			((I0) (\NlwInverterSignal_U1/U3/holdingreg<4>_MC.D2_PT_1/IN0 \))
			((I1) (\U1/U3/RDedge \))
			((I2) (\U1/U3/holdingreg \(4)))
			((O) (\U1/U3/holdingreg<4>_MC.D2_PT_1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U3/holdingreg<4>_MC.D2_PT_2_1989 \ 0 18174 (_entity .  X_AND16)
		(_port
			((I0) (\WR_II/UIM \))
			((I1) (\NlwInverterSignal_U1/U3/holdingreg<4>_MC.D2_PT_2/IN1 \))
			((I2) (U2_ADDR_reg(1)))
			((I3) (U2_ADDR_reg(0)))
			((I4) (N_PZ_931))
			((I5) (U2_ADDR_reg(2)))
			((I6) (\NlwInverterSignal_U1/U3/holdingreg<4>_MC.D2_PT_2/IN6 \))
			((I7) (\NlwInverterSignal_U1/U3/holdingreg<4>_MC.D2_PT_2/IN7 \))
			((I8) (\NlwInverterSignal_U1/U3/holdingreg<4>_MC.D2_PT_2/IN8 \))
			((I9) (\U1/Channel0 \(4)))
			((I10) (Vcc))
			((I11) (Vcc))
			((I12) (Vcc))
			((I13) (Vcc))
			((I14) (Vcc))
			((I15) (Vcc))
			((O) (\U1/U3/holdingreg<4>_MC.D2_PT_2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U3/holdingreg<4>_MC.D2_1990 \ 0 18193 (_entity .  X_OR3)
		(_port
			((I0) (\U1/U3/holdingreg<4>_MC.D2_PT_0 \))
			((I1) (\U1/U3/holdingreg<4>_MC.D2_PT_1 \))
			((I2) (\U1/U3/holdingreg<4>_MC.D2_PT_2 \))
			((O) (\U1/U3/holdingreg<4>_MC.D2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U3/holdingreg<20> \ 0 18199 (_entity .  X_BUF)
		(_port
			((I) (\U1/U3/holdingreg<20>_MC.Q \))
			((O) (\U1/U3/holdingreg \(20)))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U3/holdingreg<20>_MC.REG \ 0 18203 (_entity .  X_FF)
		(_port
			((I) (\U1/U3/holdingreg<20>_MC.D \))
			((CE) (Vcc))
			((CLK) (\U1/U3/holdingreg<20>_MC.REG_tsimcreated_inv_Mclk_II/FCLK \))
			((SET) (Gnd))
			((RST) (PRLD))
			((O) (\U1/U3/holdingreg<20>_MC.Q \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U3/holdingreg<20>_MC.REG_tsimcreated_inv_Mclk_II/FCLK_1991 \ 0 18211 (_entity .  X_INV)
		(_port
			((I) (\Mclk_II/FCLK \))
			((O) (\U1/U3/holdingreg<20>_MC.REG_tsimcreated_inv_Mclk_II/FCLK \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U3/holdingreg<20>_MC.D_1992 \ 0 18215 (_entity .  X_XOR2)
		(_port
			((I0) (\U1/U3/holdingreg<20>_MC.D1 \))
			((I1) (\U1/U3/holdingreg<20>_MC.D2 \))
			((O) (\U1/U3/holdingreg<20>_MC.D \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U3/holdingreg<20>_MC.D1_1993 \ 0 18220 (_entity .  X_ZERO)
		(_port
			((O) (\U1/U3/holdingreg<20>_MC.D1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U3/holdingreg<20>_MC.D2_PT_0_1994 \ 0 18223 (_entity .  X_AND2)
		(_port
			((I0) (N_PZ_986))
			((I1) (\U1/Channel1 \(20)))
			((O) (\U1/U3/holdingreg<20>_MC.D2_PT_0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U3/holdingreg<20>_MC.D2_PT_1_1995 \ 0 18228 (_entity .  X_AND3)
		(_port
			((I0) (\NlwInverterSignal_U1/U3/holdingreg<20>_MC.D2_PT_1/IN0 \))
			((I1) (\U1/U3/RDedge \))
			((I2) (\U1/U3/holdingreg \(20)))
			((O) (\U1/U3/holdingreg<20>_MC.D2_PT_1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U3/holdingreg<20>_MC.D2_PT_2_1996 \ 0 18234 (_entity .  X_AND16)
		(_port
			((I0) (\WR_II/UIM \))
			((I1) (\NlwInverterSignal_U1/U3/holdingreg<20>_MC.D2_PT_2/IN1 \))
			((I2) (U2_ADDR_reg(1)))
			((I3) (U2_ADDR_reg(0)))
			((I4) (N_PZ_931))
			((I5) (U2_ADDR_reg(2)))
			((I6) (\NlwInverterSignal_U1/U3/holdingreg<20>_MC.D2_PT_2/IN6 \))
			((I7) (\NlwInverterSignal_U1/U3/holdingreg<20>_MC.D2_PT_2/IN7 \))
			((I8) (\NlwInverterSignal_U1/U3/holdingreg<20>_MC.D2_PT_2/IN8 \))
			((I9) (\U1/Channel0 \(20)))
			((I10) (Vcc))
			((I11) (Vcc))
			((I12) (Vcc))
			((I13) (Vcc))
			((I14) (Vcc))
			((I15) (Vcc))
			((O) (\U1/U3/holdingreg<20>_MC.D2_PT_2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U3/holdingreg<20>_MC.D2_1997 \ 0 18253 (_entity .  X_OR3)
		(_port
			((I0) (\U1/U3/holdingreg<20>_MC.D2_PT_0 \))
			((I1) (\U1/U3/holdingreg<20>_MC.D2_PT_1 \))
			((I2) (\U1/U3/holdingreg<20>_MC.D2_PT_2 \))
			((O) (\U1/U3/holdingreg<20>_MC.D2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U3/holdingreg<12> \ 0 18259 (_entity .  X_BUF)
		(_port
			((I) (\U1/U3/holdingreg<12>_MC.Q \))
			((O) (\U1/U3/holdingreg \(12)))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U3/holdingreg<12>_MC.REG \ 0 18263 (_entity .  X_FF)
		(_port
			((I) (\U1/U3/holdingreg<12>_MC.D \))
			((CE) (Vcc))
			((CLK) (\U1/U3/holdingreg<12>_MC.REG_tsimcreated_inv_Mclk_II/FCLK \))
			((SET) (Gnd))
			((RST) (PRLD))
			((O) (\U1/U3/holdingreg<12>_MC.Q \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U3/holdingreg<12>_MC.REG_tsimcreated_inv_Mclk_II/FCLK_1998 \ 0 18271 (_entity .  X_INV)
		(_port
			((I) (\Mclk_II/FCLK \))
			((O) (\U1/U3/holdingreg<12>_MC.REG_tsimcreated_inv_Mclk_II/FCLK \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U3/holdingreg<12>_MC.D_1999 \ 0 18275 (_entity .  X_XOR2)
		(_port
			((I0) (\U1/U3/holdingreg<12>_MC.D1 \))
			((I1) (\U1/U3/holdingreg<12>_MC.D2 \))
			((O) (\U1/U3/holdingreg<12>_MC.D \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U3/holdingreg<12>_MC.D1_2000 \ 0 18280 (_entity .  X_ZERO)
		(_port
			((O) (\U1/U3/holdingreg<12>_MC.D1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U3/holdingreg<12>_MC.D2_PT_0_2001 \ 0 18283 (_entity .  X_AND2)
		(_port
			((I0) (N_PZ_986))
			((I1) (\U1/Channel1 \(12)))
			((O) (\U1/U3/holdingreg<12>_MC.D2_PT_0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U3/holdingreg<12>_MC.D2_PT_1_2002 \ 0 18288 (_entity .  X_AND3)
		(_port
			((I0) (\NlwInverterSignal_U1/U3/holdingreg<12>_MC.D2_PT_1/IN0 \))
			((I1) (\U1/U3/RDedge \))
			((I2) (\U1/U3/holdingreg \(12)))
			((O) (\U1/U3/holdingreg<12>_MC.D2_PT_1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U3/holdingreg<12>_MC.D2_PT_2_2003 \ 0 18294 (_entity .  X_AND16)
		(_port
			((I0) (\WR_II/UIM \))
			((I1) (\NlwInverterSignal_U1/U3/holdingreg<12>_MC.D2_PT_2/IN1 \))
			((I2) (U2_ADDR_reg(1)))
			((I3) (U2_ADDR_reg(0)))
			((I4) (N_PZ_931))
			((I5) (U2_ADDR_reg(2)))
			((I6) (\NlwInverterSignal_U1/U3/holdingreg<12>_MC.D2_PT_2/IN6 \))
			((I7) (\NlwInverterSignal_U1/U3/holdingreg<12>_MC.D2_PT_2/IN7 \))
			((I8) (\NlwInverterSignal_U1/U3/holdingreg<12>_MC.D2_PT_2/IN8 \))
			((I9) (\U1/Channel0 \(12)))
			((I10) (Vcc))
			((I11) (Vcc))
			((I12) (Vcc))
			((I13) (Vcc))
			((I14) (Vcc))
			((I15) (Vcc))
			((O) (\U1/U3/holdingreg<12>_MC.D2_PT_2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U3/holdingreg<12>_MC.D2_2004 \ 0 18313 (_entity .  X_OR3)
		(_port
			((I0) (\U1/U3/holdingreg<12>_MC.D2_PT_0 \))
			((I1) (\U1/U3/holdingreg<12>_MC.D2_PT_1 \))
			((I2) (\U1/U3/holdingreg<12>_MC.D2_PT_2 \))
			((O) (\U1/U3/holdingreg<12>_MC.D2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \outDATA<4>\\$WA4.UIM_2005 \ 0 18319 (_entity .  X_BUF)
		(_port
			((I) (\outDATA<4>\\$WA4.UIM_MC.Q \))
			((O) (\outDATA<4>\\$WA4.UIM \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \outDATA<4>\\$WA4.UIM_MC.Q_2006 \ 0 18323 (_entity .  X_BUF)
		(_port
			((I) (\outDATA<4>\\$WA4.UIM_MC.D \))
			((O) (\outDATA<4>\\$WA4.UIM_MC.Q \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \outDATA<4>\\$WA4.UIM_MC.D_2007 \ 0 18327 (_entity .  X_XOR2)
		(_port
			((I0) (\outDATA<4>\\$WA4.UIM_MC.D1 \))
			((I1) (\outDATA<4>\\$WA4.UIM_MC.D2 \))
			((O) (\outDATA<4>\\$WA4.UIM_MC.D \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \outDATA<4>\\$WA4.UIM_MC.D1_2008 \ 0 18332 (_entity .  X_ZERO)
		(_port
			((O) (\outDATA<4>\\$WA4.UIM_MC.D1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \outDATA<4>\\$WA4.UIM_MC.D2_PT_0_2009 \ 0 18335 (_entity .  X_AND2)
		(_port
			((I0) (N_PZ_1003))
			((I1) (\U1/U4/Latch1r \(12)))
			((O) (\outDATA<4>\\$WA4.UIM_MC.D2_PT_0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \outDATA<4>\\$WA4.UIM_MC.D2_PT_1_2010 \ 0 18340 (_entity .  X_AND8)
		(_port
			((I0) (\WR_II/UIM \))
			((I1) (\NlwInverterSignal_outDATA<4>\\$WA4.UIM_MC.D2_PT_1/IN1 \))
			((I2) (U2_ADDR_reg(1)))
			((I3) (U2_ADDR_reg(0)))
			((I4) (N_PZ_931))
			((I5) (\NlwInverterSignal_outDATA<4>\\$WA4.UIM_MC.D2_PT_1/IN5 \))
			((I6) (U2_ADDR_reg(3)))
			((I7) (\U1/U4/Latch0r \(12)))
			((O) (\outDATA<4>\\$WA4.UIM_MC.D2_PT_1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \outDATA<4>\\$WA4.UIM_MC.D2_PT_2_2011 \ 0 18351 (_entity .  X_AND8)
		(_port
			((I0) (\WR_II/UIM \))
			((I1) (\NlwInverterSignal_outDATA<4>\\$WA4.UIM_MC.D2_PT_2/IN1 \))
			((I2) (U2_ADDR_reg(1)))
			((I3) (\NlwInverterSignal_outDATA<4>\\$WA4.UIM_MC.D2_PT_2/IN3 \))
			((I4) (N_PZ_931))
			((I5) (\NlwInverterSignal_outDATA<4>\\$WA4.UIM_MC.D2_PT_2/IN5 \))
			((I6) (U2_ADDR_reg(3)))
			((I7) (\U1/U4/Latch0r \(4)))
			((O) (\outDATA<4>\\$WA4.UIM_MC.D2_PT_2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \outDATA<4>\\$WA4.UIM_MC.D2_PT_3_2012 \ 0 18362 (_entity .  X_AND8)
		(_port
			((I0) (\WR_II/UIM \))
			((I1) (\NlwInverterSignal_outDATA<4>\\$WA4.UIM_MC.D2_PT_3/IN1 \))
			((I2) (\NlwInverterSignal_outDATA<4>\\$WA4.UIM_MC.D2_PT_3/IN2 \))
			((I3) (\NlwInverterSignal_outDATA<4>\\$WA4.UIM_MC.D2_PT_3/IN3 \))
			((I4) (N_PZ_931))
			((I5) (U2_ADDR_reg(2)))
			((I6) (U2_ADDR_reg(3)))
			((I7) (\U1/U4/Latch1r \(4)))
			((O) (\outDATA<4>\\$WA4.UIM_MC.D2_PT_3 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \outDATA<4>\\$WA4.UIM_MC.D2_2013 \ 0 18373 (_entity .  X_OR4)
		(_port
			((I0) (\outDATA<4>\\$WA4.UIM_MC.D2_PT_0 \))
			((I1) (\outDATA<4>\\$WA4.UIM_MC.D2_PT_1 \))
			((I2) (\outDATA<4>\\$WA4.UIM_MC.D2_PT_2 \))
			((I3) (\outDATA<4>\\$WA4.UIM_MC.D2_PT_3 \))
			((O) (\outDATA<4>\\$WA4.UIM_MC.D2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U4/Latch0r<12> \ 0 18380 (_entity .  X_BUF)
		(_port
			((I) (\U1/U4/Latch0r<12>_MC.Q \))
			((O) (\U1/U4/Latch0r \(12)))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U4/Latch0r<12>_MC.REG \ 0 18384 (_entity .  X_FF)
		(_port
			((I) (\U1/U4/Latch0r<12>_MC.D \))
			((CE) (Vcc))
			((CLK) (\U1/U4/Latch0r<12>_MC.REG_tsimcreated_inv_Mclk_II/FCLK \))
			((SET) (Gnd))
			((RST) (PRLD))
			((O) (\U1/U4/Latch0r<12>_MC.Q \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U4/Latch0r<12>_MC.REG_tsimcreated_inv_Mclk_II/FCLK_2014 \ 0 18392 (_entity .  X_INV)
		(_port
			((I) (\Mclk_II/FCLK \))
			((O) (\U1/U4/Latch0r<12>_MC.REG_tsimcreated_inv_Mclk_II/FCLK \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U4/Latch0r<12>_MC.D_2015 \ 0 18396 (_entity .  X_XOR2)
		(_port
			((I0) (\U1/U4/Latch0r<12>_MC.D1 \))
			((I1) (\U1/U4/Latch0r<12>_MC.D2 \))
			((O) (\U1/U4/Latch0r<12>_MC.D \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U4/Latch0r<12>_MC.D1_2016 \ 0 18401 (_entity .  X_ZERO)
		(_port
			((O) (\U1/U4/Latch0r<12>_MC.D1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U4/Latch0r<12>_MC.D2_PT_0_2017 \ 0 18404 (_entity .  X_AND2)
		(_port
			((I0) (N_PZ_1059))
			((I1) (\U1/U4/Latch0r \(12)))
			((O) (\U1/U4/Latch0r<12>_MC.D2_PT_0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U4/Latch0r<12>_MC.D2_PT_1_2018 \ 0 18409 (_entity .  X_AND3)
		(_port
			((I0) (\NlwInverterSignal_U1/U4/Latch0r<12>_MC.D2_PT_1/IN0 \))
			((I1) (\U1/Channel0 \(12)))
			((I2) (\NlwInverterSignal_U1/U4/Latch0r<12>_MC.D2_PT_1/IN2 \))
			((O) (\U1/U4/Latch0r<12>_MC.D2_PT_1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U4/Latch0r<12>_MC.D2_2019 \ 0 18415 (_entity .  X_OR2)
		(_port
			((I0) (\U1/U4/Latch0r<12>_MC.D2_PT_0 \))
			((I1) (\U1/U4/Latch0r<12>_MC.D2_PT_1 \))
			((O) (\U1/U4/Latch0r<12>_MC.D2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U4/Latch0r<4> \ 0 18420 (_entity .  X_BUF)
		(_port
			((I) (\U1/U4/Latch0r<4>_MC.Q \))
			((O) (\U1/U4/Latch0r \(4)))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U4/Latch0r<4>_MC.REG \ 0 18424 (_entity .  X_FF)
		(_port
			((I) (\U1/U4/Latch0r<4>_MC.D \))
			((CE) (Vcc))
			((CLK) (\U1/U4/Latch0r<4>_MC.REG_tsimcreated_inv_Mclk_II/FCLK \))
			((SET) (Gnd))
			((RST) (PRLD))
			((O) (\U1/U4/Latch0r<4>_MC.Q \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U4/Latch0r<4>_MC.REG_tsimcreated_inv_Mclk_II/FCLK_2020 \ 0 18432 (_entity .  X_INV)
		(_port
			((I) (\Mclk_II/FCLK \))
			((O) (\U1/U4/Latch0r<4>_MC.REG_tsimcreated_inv_Mclk_II/FCLK \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U4/Latch0r<4>_MC.D_2021 \ 0 18436 (_entity .  X_XOR2)
		(_port
			((I0) (\U1/U4/Latch0r<4>_MC.D1 \))
			((I1) (\U1/U4/Latch0r<4>_MC.D2 \))
			((O) (\U1/U4/Latch0r<4>_MC.D \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U4/Latch0r<4>_MC.D1_2022 \ 0 18441 (_entity .  X_ZERO)
		(_port
			((O) (\U1/U4/Latch0r<4>_MC.D1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U4/Latch0r<4>_MC.D2_PT_0_2023 \ 0 18444 (_entity .  X_AND2)
		(_port
			((I0) (N_PZ_1059))
			((I1) (\U1/U4/Latch0r \(4)))
			((O) (\U1/U4/Latch0r<4>_MC.D2_PT_0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U4/Latch0r<4>_MC.D2_PT_1_2024 \ 0 18449 (_entity .  X_AND3)
		(_port
			((I0) (\NlwInverterSignal_U1/U4/Latch0r<4>_MC.D2_PT_1/IN0 \))
			((I1) (\U1/Channel0 \(4)))
			((I2) (\NlwInverterSignal_U1/U4/Latch0r<4>_MC.D2_PT_1/IN2 \))
			((O) (\U1/U4/Latch0r<4>_MC.D2_PT_1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U4/Latch0r<4>_MC.D2_2025 \ 0 18455 (_entity .  X_OR2)
		(_port
			((I0) (\U1/U4/Latch0r<4>_MC.D2_PT_0 \))
			((I1) (\U1/U4/Latch0r<4>_MC.D2_PT_1 \))
			((O) (\U1/U4/Latch0r<4>_MC.D2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U4/Latch1r<4> \ 0 18460 (_entity .  X_BUF)
		(_port
			((I) (\U1/U4/Latch1r<4>_MC.Q \))
			((O) (\U1/U4/Latch1r \(4)))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U4/Latch1r<4>_MC.REG \ 0 18464 (_entity .  X_FF)
		(_port
			((I) (\U1/U4/Latch1r<4>_MC.D \))
			((CE) (Vcc))
			((CLK) (\U1/U4/Latch1r<4>_MC.REG_tsimcreated_inv_Mclk_II/FCLK \))
			((SET) (Gnd))
			((RST) (PRLD))
			((O) (\U1/U4/Latch1r<4>_MC.Q \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U4/Latch1r<4>_MC.REG_tsimcreated_inv_Mclk_II/FCLK_2026 \ 0 18472 (_entity .  X_INV)
		(_port
			((I) (\Mclk_II/FCLK \))
			((O) (\U1/U4/Latch1r<4>_MC.REG_tsimcreated_inv_Mclk_II/FCLK \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U4/Latch1r<4>_MC.D_2027 \ 0 18476 (_entity .  X_XOR2)
		(_port
			((I0) (\U1/U4/Latch1r<4>_MC.D1 \))
			((I1) (\U1/U4/Latch1r<4>_MC.D2 \))
			((O) (\U1/U4/Latch1r<4>_MC.D \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U4/Latch1r<4>_MC.D1_2028 \ 0 18481 (_entity .  X_ZERO)
		(_port
			((O) (\U1/U4/Latch1r<4>_MC.D1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U4/Latch1r<4>_MC.D2_PT_0_2029 \ 0 18484 (_entity .  X_AND2)
		(_port
			((I0) (\NlwInverterSignal_U1/U4/Latch1r<4>_MC.D2_PT_0/IN0 \))
			((I1) (\U1/Channel1 \(4)))
			((O) (\U1/U4/Latch1r<4>_MC.D2_PT_0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U4/Latch1r<4>_MC.D2_PT_1_2030 \ 0 18489 (_entity .  X_AND8)
		(_port
			((I0) (\NlwInverterSignal_U1/U4/Latch1r<4>_MC.D2_PT_1/IN0 \))
			((I1) (\RD_II/UIM \))
			((I2) (U2_ADDR_reg(1)))
			((I3) (N_PZ_931))
			((I4) (\NlwInverterSignal_U1/U4/Latch1r<4>_MC.D2_PT_1/IN4 \))
			((I5) (\NlwInverterSignal_U1/U4/Latch1r<4>_MC.D2_PT_1/IN5 \))
			((I6) (\NlwInverterSignal_U1/U4/Latch1r<4>_MC.D2_PT_1/IN6 \))
			((I7) (\U1/U4/Latch1r \(4)))
			((O) (\U1/U4/Latch1r<4>_MC.D2_PT_1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U4/Latch1r<4>_MC.D2_2031 \ 0 18500 (_entity .  X_OR2)
		(_port
			((I0) (\U1/U4/Latch1r<4>_MC.D2_PT_0 \))
			((I1) (\U1/U4/Latch1r<4>_MC.D2_PT_1 \))
			((O) (\U1/U4/Latch1r<4>_MC.D2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U4/Latch1r<12> \ 0 18505 (_entity .  X_BUF)
		(_port
			((I) (\U1/U4/Latch1r<12>_MC.Q \))
			((O) (\U1/U4/Latch1r \(12)))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U4/Latch1r<12>_MC.REG \ 0 18509 (_entity .  X_FF)
		(_port
			((I) (\U1/U4/Latch1r<12>_MC.D \))
			((CE) (Vcc))
			((CLK) (\U1/U4/Latch1r<12>_MC.REG_tsimcreated_inv_Mclk_II/FCLK \))
			((SET) (Gnd))
			((RST) (PRLD))
			((O) (\U1/U4/Latch1r<12>_MC.Q \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U4/Latch1r<12>_MC.REG_tsimcreated_inv_Mclk_II/FCLK_2032 \ 0 18517 (_entity .  X_INV)
		(_port
			((I) (\Mclk_II/FCLK \))
			((O) (\U1/U4/Latch1r<12>_MC.REG_tsimcreated_inv_Mclk_II/FCLK \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U4/Latch1r<12>_MC.D_2033 \ 0 18521 (_entity .  X_XOR2)
		(_port
			((I0) (\U1/U4/Latch1r<12>_MC.D1 \))
			((I1) (\U1/U4/Latch1r<12>_MC.D2 \))
			((O) (\U1/U4/Latch1r<12>_MC.D \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U4/Latch1r<12>_MC.D1_2034 \ 0 18526 (_entity .  X_ZERO)
		(_port
			((O) (\U1/U4/Latch1r<12>_MC.D1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U4/Latch1r<12>_MC.D2_PT_0_2035 \ 0 18529 (_entity .  X_AND2)
		(_port
			((I0) (\NlwInverterSignal_U1/U4/Latch1r<12>_MC.D2_PT_0/IN0 \))
			((I1) (\U1/Channel1 \(12)))
			((O) (\U1/U4/Latch1r<12>_MC.D2_PT_0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U4/Latch1r<12>_MC.D2_PT_1_2036 \ 0 18534 (_entity .  X_AND8)
		(_port
			((I0) (\NlwInverterSignal_U1/U4/Latch1r<12>_MC.D2_PT_1/IN0 \))
			((I1) (\RD_II/UIM \))
			((I2) (U2_ADDR_reg(1)))
			((I3) (N_PZ_931))
			((I4) (\NlwInverterSignal_U1/U4/Latch1r<12>_MC.D2_PT_1/IN4 \))
			((I5) (\NlwInverterSignal_U1/U4/Latch1r<12>_MC.D2_PT_1/IN5 \))
			((I6) (\NlwInverterSignal_U1/U4/Latch1r<12>_MC.D2_PT_1/IN6 \))
			((I7) (\U1/U4/Latch1r \(12)))
			((O) (\U1/U4/Latch1r<12>_MC.D2_PT_1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \U1/U4/Latch1r<12>_MC.D2_2037 \ 0 18545 (_entity .  X_OR2)
		(_port
			((I0) (\U1/U4/Latch1r<12>_MC.D2_PT_0 \))
			((I1) (\U1/U4/Latch1r<12>_MC.D2_PT_1 \))
			((O) (\U1/U4/Latch1r<12>_MC.D2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \FOOBAR1__ctinst/7_2038 \ 0 18550 (_entity .  X_AND2)
		(_port
			((I0) (\Reset_II/UIM \))
			((I1) (\Reset_II/UIM \))
			((O) (\FOOBAR1__ctinst/7 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \FOOBAR3__ctinst/7_2039 \ 0 18555 (_entity .  X_AND2)
		(_port
			((I0) (U2_Enable_AD))
			((I1) (U2_Enable_AD))
			((O) (\FOOBAR3__ctinst/7 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \FOOBAR4__ctinst/0_2040 \ 0 18560 (_entity .  X_AND6)
		(_port
			((I0) (\NlwInverterSignal_FOOBAR4__ctinst/0/IN0 \))
			((I1) (\NlwInverterSignal_FOOBAR4__ctinst/0/IN1 \))
			((I2) (\NlwInverterSignal_FOOBAR4__ctinst/0/IN2 \))
			((I3) (\NlwInverterSignal_FOOBAR4__ctinst/0/IN3 \))
			((I4) (\NlwInverterSignal_FOOBAR4__ctinst/0/IN4 \))
			((I5) (\NlwInverterSignal_FOOBAR4__ctinst/0/IN5 \))
			((O) (\FOOBAR4__ctinst/0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \FOOBAR4__ctinst/7_2041 \ 0 18569 (_entity .  X_AND2)
		(_port
			((I0) (\Reset_II/UIM \))
			((I1) (\Reset_II/UIM \))
			((O) (\FOOBAR4__ctinst/7 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \FOOBAR7__ctinst/4_2042 \ 0 18574 (_entity .  X_AND7)
		(_port
			((I0) (\NlwInverterSignal_FOOBAR7__ctinst/4/IN0 \))
			((I1) (\RD_II/UIM \))
			((I2) (U2_ADDR_reg(1)))
			((I3) (U2_ADDR_reg(0)))
			((I4) (N_PZ_931))
			((I5) (U2_ADDR_reg(2)))
			((I6) (U2_ADDR_reg(3)))
			((O) (\FOOBAR7__ctinst/4 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \FOOBAR8__ctinst/4_2043 \ 0 18584 (_entity .  X_AND7)
		(_port
			((I0) (\NlwInverterSignal_FOOBAR8__ctinst/4/IN0 \))
			((I1) (\RD_II/UIM \))
			((I2) (U2_ADDR_reg(1)))
			((I3) (U2_ADDR_reg(0)))
			((I4) (N_PZ_931))
			((I5) (U2_ADDR_reg(2)))
			((I6) (U2_ADDR_reg(3)))
			((O) (\FOOBAR8__ctinst/4 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \FOOBAR10__ctinst/4_2044 \ 0 18594 (_entity .  X_AND7)
		(_port
			((I0) (\NlwInverterSignal_FOOBAR10__ctinst/4/IN0 \))
			((I1) (\RD_II/UIM \))
			((I2) (U2_ADDR_reg(1)))
			((I3) (U2_ADDR_reg(0)))
			((I4) (N_PZ_931))
			((I5) (U2_ADDR_reg(2)))
			((I6) (U2_ADDR_reg(3)))
			((O) (\FOOBAR10__ctinst/4 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \FOOBAR12__ctinst/4_2045 \ 0 18604 (_entity .  X_AND7)
		(_port
			((I0) (\NlwInverterSignal_FOOBAR12__ctinst/4/IN0 \))
			((I1) (\RD_II/UIM \))
			((I2) (U2_ADDR_reg(1)))
			((I3) (U2_ADDR_reg(0)))
			((I4) (N_PZ_931))
			((I5) (U2_ADDR_reg(2)))
			((I6) (U2_ADDR_reg(3)))
			((O) (\FOOBAR12__ctinst/4 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \FOOBAR14__ctinst/4_2046 \ 0 18614 (_entity .  X_AND7)
		(_port
			((I0) (\NlwInverterSignal_FOOBAR14__ctinst/4/IN0 \))
			((I1) (\RD_II/UIM \))
			((I2) (U2_ADDR_reg(1)))
			((I3) (\NlwInverterSignal_FOOBAR14__ctinst/4/IN3 \))
			((I4) (N_PZ_931))
			((I5) (U2_ADDR_reg(2)))
			((I6) (U2_ADDR_reg(3)))
			((O) (\FOOBAR14__ctinst/4 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \FOOBAR15__ctinst/4_2047 \ 0 18624 (_entity .  X_AND7)
		(_port
			((I0) (\NlwInverterSignal_FOOBAR15__ctinst/4/IN0 \))
			((I1) (\RD_II/UIM \))
			((I2) (U2_ADDR_reg(1)))
			((I3) (U2_ADDR_reg(0)))
			((I4) (N_PZ_931))
			((I5) (U2_ADDR_reg(2)))
			((I6) (U2_ADDR_reg(3)))
			((O) (\FOOBAR15__ctinst/4 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \FOOBAR16__ctinst/4_2048 \ 0 18634 (_entity .  X_AND2)
		(_port
			((I0) (\NlwInverterSignal_FOOBAR16__ctinst/4/IN0 \))
			((I1) (\NlwInverterSignal_FOOBAR16__ctinst/4/IN1 \))
			((O) (\FOOBAR16__ctinst/4 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \FOOBAR18__ctinst/4_2049 \ 0 18639 (_entity .  X_AND7)
		(_port
			((I0) (\NlwInverterSignal_FOOBAR18__ctinst/4/IN0 \))
			((I1) (\RD_II/UIM \))
			((I2) (U2_ADDR_reg(1)))
			((I3) (U2_ADDR_reg(0)))
			((I4) (N_PZ_931))
			((I5) (U2_ADDR_reg(2)))
			((I6) (U2_ADDR_reg(3)))
			((O) (\FOOBAR18__ctinst/4 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \FOOBAR21__ctinst/4_2050 \ 0 18649 (_entity .  X_AND2)
		(_port
			((I0) (\NlwInverterSignal_FOOBAR21__ctinst/4/IN0 \))
			((I1) (\NlwInverterSignal_FOOBAR21__ctinst/4/IN1 \))
			((O) (\FOOBAR21__ctinst/4 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \FOOBAR23__ctinst/4_2051 \ 0 18654 (_entity .  X_AND7)
		(_port
			((I0) (\NlwInverterSignal_FOOBAR23__ctinst/4/IN0 \))
			((I1) (\RD_II/UIM \))
			((I2) (U2_ADDR_reg(1)))
			((I3) (\NlwInverterSignal_FOOBAR23__ctinst/4/IN3 \))
			((I4) (N_PZ_931))
			((I5) (U2_ADDR_reg(2)))
			((I6) (U2_ADDR_reg(3)))
			((O) (\FOOBAR23__ctinst/4 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \FOOBAR24__ctinst/4_2052 \ 0 18664 (_entity .  X_AND2)
		(_port
			((I0) (\NlwInverterSignal_FOOBAR24__ctinst/4/IN0 \))
			((I1) (\NlwInverterSignal_FOOBAR24__ctinst/4/IN1 \))
			((O) (\FOOBAR24__ctinst/4 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_AD<5>_MC.D/IN0 \ 0 18669 (_entity .  X_INV)
		(_port
			((I) (\AD<5>_MC.D1 \))
			((O) (\NlwInverterSignal_AD<5>_MC.D/IN0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_AD<5>_MC.D2_PT_0/IN0 \ 0 18673 (_entity .  X_INV)
		(_port
			((I) (\outDATA<5>\\$WA5.UIM \))
			((O) (\NlwInverterSignal_AD<5>_MC.D2_PT_0/IN0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_AD<5>_MC.D2_PT_1/IN0 \ 0 18677 (_entity .  X_INV)
		(_port
			((I) (\outDATA<5>\\$WA4.UIM \))
			((O) (\NlwInverterSignal_AD<5>_MC.D2_PT_1/IN0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_AD<5>_MC.D2_PT_2/IN1 \ 0 18681 (_entity .  X_INV)
		(_port
			((I) (\RD_II/UIM \))
			((O) (\NlwInverterSignal_AD<5>_MC.D2_PT_2/IN1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_AD<5>_MC.D2_PT_2/IN7 \ 0 18685 (_entity .  X_INV)
		(_port
			((I) (\outDATA<5>\\$WA1.UIM \))
			((O) (\NlwInverterSignal_AD<5>_MC.D2_PT_2/IN7 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_AD<5>_MC.D2_PT_3/IN1 \ 0 18689 (_entity .  X_INV)
		(_port
			((I) (\RD_II/UIM \))
			((O) (\NlwInverterSignal_AD<5>_MC.D2_PT_3/IN1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_AD<5>_MC.D2_PT_3/IN5 \ 0 18693 (_entity .  X_INV)
		(_port
			((I) (U2_ADDR_reg(2)))
			((O) (\NlwInverterSignal_AD<5>_MC.D2_PT_3/IN5 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_AD<5>_MC.D2_PT_3/IN6 \ 0 18697 (_entity .  X_INV)
		(_port
			((I) (U2_ADDR_reg(3)))
			((O) (\NlwInverterSignal_AD<5>_MC.D2_PT_3/IN6 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_AD<5>_MC.D2_PT_3/IN7 \ 0 18701 (_entity .  X_INV)
		(_port
			((I) (\outDATA<5>\\$WA2.UIM \))
			((O) (\NlwInverterSignal_AD<5>_MC.D2_PT_3/IN7 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_AD<5>_MC.D2_PT_4/IN1 \ 0 18705 (_entity .  X_INV)
		(_port
			((I) (\RD_II/UIM \))
			((O) (\NlwInverterSignal_AD<5>_MC.D2_PT_4/IN1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_AD<5>_MC.D2_PT_4/IN3 \ 0 18709 (_entity .  X_INV)
		(_port
			((I) (U2_ADDR_reg(0)))
			((O) (\NlwInverterSignal_AD<5>_MC.D2_PT_4/IN3 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_AD<5>_MC.D2_PT_4/IN7 \ 0 18713 (_entity .  X_INV)
		(_port
			((I) (\outDATA<5>\\$WA3.UIM \))
			((O) (\NlwInverterSignal_AD<5>_MC.D2_PT_4/IN7 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_AD<5>_MC.D2_PT_5/IN1 \ 0 18717 (_entity .  X_INV)
		(_port
			((I) (\RD_II/UIM \))
			((O) (\NlwInverterSignal_AD<5>_MC.D2_PT_5/IN1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_AD<5>_MC.D2_PT_5/IN2 \ 0 18721 (_entity .  X_INV)
		(_port
			((I) (U2_ADDR_reg(1)))
			((O) (\NlwInverterSignal_AD<5>_MC.D2_PT_5/IN2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_AD<5>_MC.D2_PT_5/IN3 \ 0 18725 (_entity .  X_INV)
		(_port
			((I) (U2_ADDR_reg(0)))
			((O) (\NlwInverterSignal_AD<5>_MC.D2_PT_5/IN3 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_AD<5>_MC.D2_PT_5/IN5 \ 0 18729 (_entity .  X_INV)
		(_port
			((I) (U2_ADDR_reg(2)))
			((O) (\NlwInverterSignal_AD<5>_MC.D2_PT_5/IN5 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_AD<5>_MC.D2_PT_5/IN6 \ 0 18733 (_entity .  X_INV)
		(_port
			((I) (U2_ADDR_reg(3)))
			((O) (\NlwInverterSignal_AD<5>_MC.D2_PT_5/IN6 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_AD<5>_MC.D2_PT_5/IN7 \ 0 18737 (_entity .  X_INV)
		(_port
			((I) (\outDATA<5>\\$WA0.UIM \))
			((O) (\NlwInverterSignal_AD<5>_MC.D2_PT_5/IN7 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U2_ADDR_reg<1>_MC.D2_PT_0/IN1 \ 0 18741 (_entity .  X_INV)
		(_port
			((I) (N_PZ_947))
			((O) (\NlwInverterSignal_U2_ADDR_reg<1>_MC.D2_PT_0/IN1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U2_ADDR_reg<1>_MC.D2_PT_0/IN2 \ 0 18745 (_entity .  X_INV)
		(_port
			((I) (N_PZ_989))
			((O) (\NlwInverterSignal_U2_ADDR_reg<1>_MC.D2_PT_0/IN2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U2_ADDR_reg<1>_MC.D2_PT_1/IN1 \ 0 18749 (_entity .  X_INV)
		(_port
			((I) (N_PZ_989))
			((O) (\NlwInverterSignal_U2_ADDR_reg<1>_MC.D2_PT_1/IN1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U2_ADDR_reg<1>_MC.D2_PT_2/IN1 \ 0 18753 (_entity .  X_INV)
		(_port
			((I) (U2_ADDR_reg(0)))
			((O) (\NlwInverterSignal_U2_ADDR_reg<1>_MC.D2_PT_2/IN1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U2_ADDR_reg<1>_MC.D2_PT_2/IN4 \ 0 18757 (_entity .  X_INV)
		(_port
			((I) (\Reset_II/UIM \))
			((O) (\NlwInverterSignal_U2_ADDR_reg<1>_MC.D2_PT_2/IN4 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U2_ADDR_reg<1>_MC.D2_PT_3/IN0 \ 0 18761 (_entity .  X_INV)
		(_port
			((I) (U2_ADDR_reg(1)))
			((O) (\NlwInverterSignal_U2_ADDR_reg<1>_MC.D2_PT_3/IN0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U2_ADDR_reg<1>_MC.D2_PT_3/IN4 \ 0 18765 (_entity .  X_INV)
		(_port
			((I) (\Reset_II/UIM \))
			((O) (\NlwInverterSignal_U2_ADDR_reg<1>_MC.D2_PT_3/IN4 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U2_ADDR_reg<0>_MC.D2_PT_1/IN2 \ 0 18769 (_entity .  X_INV)
		(_port
			((I) (\AD<0>_II/UIM \))
			((O) (\NlwInverterSignal_U2_ADDR_reg<0>_MC.D2_PT_1/IN2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U2_ADDR_reg<0>_MC.D2_PT_2/IN0 \ 0 18773 (_entity .  X_INV)
		(_port
			((I) (U2_ADDR_reg(0)))
			((O) (\NlwInverterSignal_U2_ADDR_reg<0>_MC.D2_PT_2/IN0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U2_ADDR_reg<0>_MC.D2_PT_2/IN2 \ 0 18777 (_entity .  X_INV)
		(_port
			((I) (\Reset_II/UIM \))
			((O) (\NlwInverterSignal_U2_ADDR_reg<0>_MC.D2_PT_2/IN2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U2_ADDR_reg<0>_MC.D2_PT_3/IN3 \ 0 18781 (_entity .  X_INV)
		(_port
			((I) (N_PZ_947))
			((O) (\NlwInverterSignal_U2_ADDR_reg<0>_MC.D2_PT_3/IN3 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U2_ADDR_reg<0>_MC.D2_PT_3/IN4 \ 0 18785 (_entity .  X_INV)
		(_port
			((I) (\Reset_II/UIM \))
			((O) (\NlwInverterSignal_U2_ADDR_reg<0>_MC.D2_PT_3/IN4 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U2_ADDR_reg<0>_MC.D2_PT_3/IN6 \ 0 18789 (_entity .  X_INV)
		(_port
			((I) (U2_WRRDedge))
			((O) (\NlwInverterSignal_U2_ADDR_reg<0>_MC.D2_PT_3/IN6 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_N_PZ_947_MC.D1/IN0 \ 0 18793 (_entity .  X_INV)
		(_port
			((I) (\AS_II/UIM \))
			((O) (\NlwInverterSignal_N_PZ_947_MC.D1/IN0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U2_AutoInc_MC.D/IN0 \ 0 18797 (_entity .  X_INV)
		(_port
			((I) (\U2_AutoInc_MC.D1 \))
			((O) (\NlwInverterSignal_U2_AutoInc_MC.D/IN0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U2__n0017_MC.D1/IN0 \ 0 18801 (_entity .  X_INV)
		(_port
			((I) (\WR_II/UIM \))
			((O) (\NlwInverterSignal_U2__n0017_MC.D1/IN0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U2__n0017_MC.D1/IN1 \ 0 18805 (_entity .  X_INV)
		(_port
			((I) (\RD_II/UIM \))
			((O) (\NlwInverterSignal_U2__n0017_MC.D1/IN1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_N_PZ_931_MC.D1/IN0 \ 0 18809 (_entity .  X_INV)
		(_port
			((I) (U2_ADDR_reg(4)))
			((O) (\NlwInverterSignal_N_PZ_931_MC.D1/IN0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_N_PZ_931_MC.D1/IN1 \ 0 18813 (_entity .  X_INV)
		(_port
			((I) (U2_ADDR_reg(5)))
			((O) (\NlwInverterSignal_N_PZ_931_MC.D1/IN1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_N_PZ_931_MC.D1/IN2 \ 0 18817 (_entity .  X_INV)
		(_port
			((I) (U2_ADDR_reg(6)))
			((O) (\NlwInverterSignal_N_PZ_931_MC.D1/IN2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_N_PZ_931_MC.D1/IN3 \ 0 18821 (_entity .  X_INV)
		(_port
			((I) (U2_ADDR_reg(7)))
			((O) (\NlwInverterSignal_N_PZ_931_MC.D1/IN3 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U2_ADDR_reg<4>_MC.D2_PT_1/IN2 \ 0 18825 (_entity .  X_INV)
		(_port
			((I) (\AD<4>_II/UIM \))
			((O) (\NlwInverterSignal_U2_ADDR_reg<4>_MC.D2_PT_1/IN2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U2_ADDR_reg<4>_MC.D2_PT_2/IN1 \ 0 18829 (_entity .  X_INV)
		(_port
			((I) (\Reset_II/UIM \))
			((O) (\NlwInverterSignal_U2_ADDR_reg<4>_MC.D2_PT_2/IN1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U2_ADDR_reg<4>_MC.D2_PT_2/IN2 \ 0 18833 (_entity .  X_INV)
		(_port
			((I) (U2_ADDR_reg(4)))
			((O) (\NlwInverterSignal_U2_ADDR_reg<4>_MC.D2_PT_2/IN2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U2_ADDR_reg<4>_MC.D2_PT_3/IN6 \ 0 18837 (_entity .  X_INV)
		(_port
			((I) (N_PZ_947))
			((O) (\NlwInverterSignal_U2_ADDR_reg<4>_MC.D2_PT_3/IN6 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U2_ADDR_reg<4>_MC.D2_PT_3/IN7 \ 0 18841 (_entity .  X_INV)
		(_port
			((I) (\Reset_II/UIM \))
			((O) (\NlwInverterSignal_U2_ADDR_reg<4>_MC.D2_PT_3/IN7 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U2_ADDR_reg<4>_MC.D2_PT_3/IN9 \ 0 18845 (_entity .  X_INV)
		(_port
			((I) (U2_WRRDedge))
			((O) (\NlwInverterSignal_U2_ADDR_reg<4>_MC.D2_PT_3/IN9 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U2_ADDR_reg<4>_MC.D2_PT_3/IN10 \ 0 18849 (_entity .  X_INV)
		(_port
			((I) (U2_ADDR_reg(5)))
			((O) (\NlwInverterSignal_U2_ADDR_reg<4>_MC.D2_PT_3/IN10 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U2_ADDR_reg<4>_MC.D2_PT_3/IN11 \ 0 18853 (_entity .  X_INV)
		(_port
			((I) (U2_ADDR_reg(6)))
			((O) (\NlwInverterSignal_U2_ADDR_reg<4>_MC.D2_PT_3/IN11 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U2_ADDR_reg<4>_MC.D2_PT_3/IN12 \ 0 18857 (_entity .  X_INV)
		(_port
			((I) (U2_ADDR_reg(7)))
			((O) (\NlwInverterSignal_U2_ADDR_reg<4>_MC.D2_PT_3/IN12 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U2_ADDR_reg<2>_MC.D2_PT_1/IN2 \ 0 18861 (_entity .  X_INV)
		(_port
			((I) (\AD<2>_II/UIM \))
			((O) (\NlwInverterSignal_U2_ADDR_reg<2>_MC.D2_PT_1/IN2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U2_ADDR_reg<2>_MC.D2_PT_2/IN0 \ 0 18865 (_entity .  X_INV)
		(_port
			((I) (U2_ADDR_reg(2)))
			((O) (\NlwInverterSignal_U2_ADDR_reg<2>_MC.D2_PT_2/IN0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U2_ADDR_reg<2>_MC.D2_PT_2/IN2 \ 0 18869 (_entity .  X_INV)
		(_port
			((I) (\Reset_II/UIM \))
			((O) (\NlwInverterSignal_U2_ADDR_reg<2>_MC.D2_PT_2/IN2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U2_ADDR_reg<2>_MC.D2_PT_3/IN2 \ 0 18873 (_entity .  X_INV)
		(_port
			((I) (N_PZ_931))
			((O) (\NlwInverterSignal_U2_ADDR_reg<2>_MC.D2_PT_3/IN2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U2_ADDR_reg<2>_MC.D2_PT_3/IN4 \ 0 18877 (_entity .  X_INV)
		(_port
			((I) (N_PZ_947))
			((O) (\NlwInverterSignal_U2_ADDR_reg<2>_MC.D2_PT_3/IN4 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U2_ADDR_reg<2>_MC.D2_PT_3/IN6 \ 0 18881 (_entity .  X_INV)
		(_port
			((I) (U2_WRRDedge))
			((O) (\NlwInverterSignal_U2_ADDR_reg<2>_MC.D2_PT_3/IN6 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U2_ADDR_reg<2>_MC.D2_PT_4/IN5 \ 0 18885 (_entity .  X_INV)
		(_port
			((I) (N_PZ_947))
			((O) (\NlwInverterSignal_U2_ADDR_reg<2>_MC.D2_PT_4/IN5 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U2_ADDR_reg<2>_MC.D2_PT_4/IN6 \ 0 18889 (_entity .  X_INV)
		(_port
			((I) (\Reset_II/UIM \))
			((O) (\NlwInverterSignal_U2_ADDR_reg<2>_MC.D2_PT_4/IN6 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U2_ADDR_reg<2>_MC.D2_PT_4/IN8 \ 0 18893 (_entity .  X_INV)
		(_port
			((I) (U2_WRRDedge))
			((O) (\NlwInverterSignal_U2_ADDR_reg<2>_MC.D2_PT_4/IN8 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U2_ADDR_reg<3>_MC.D2_PT_1/IN2 \ 0 18897 (_entity .  X_INV)
		(_port
			((I) (\AD<3>_II/UIM \))
			((O) (\NlwInverterSignal_U2_ADDR_reg<3>_MC.D2_PT_1/IN2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U2_ADDR_reg<3>_MC.D2_PT_2/IN0 \ 0 18901 (_entity .  X_INV)
		(_port
			((I) (U2_ADDR_reg(3)))
			((O) (\NlwInverterSignal_U2_ADDR_reg<3>_MC.D2_PT_2/IN0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U2_ADDR_reg<3>_MC.D2_PT_2/IN2 \ 0 18905 (_entity .  X_INV)
		(_port
			((I) (\Reset_II/UIM \))
			((O) (\NlwInverterSignal_U2_ADDR_reg<3>_MC.D2_PT_2/IN2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U2_ADDR_reg<3>_MC.D2_PT_3/IN2 \ 0 18909 (_entity .  X_INV)
		(_port
			((I) (N_PZ_931))
			((O) (\NlwInverterSignal_U2_ADDR_reg<3>_MC.D2_PT_3/IN2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U2_ADDR_reg<3>_MC.D2_PT_3/IN4 \ 0 18913 (_entity .  X_INV)
		(_port
			((I) (N_PZ_947))
			((O) (\NlwInverterSignal_U2_ADDR_reg<3>_MC.D2_PT_3/IN4 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U2_ADDR_reg<3>_MC.D2_PT_3/IN6 \ 0 18917 (_entity .  X_INV)
		(_port
			((I) (U2_WRRDedge))
			((O) (\NlwInverterSignal_U2_ADDR_reg<3>_MC.D2_PT_3/IN6 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U2_ADDR_reg<3>_MC.D2_PT_4/IN6 \ 0 18921 (_entity .  X_INV)
		(_port
			((I) (N_PZ_947))
			((O) (\NlwInverterSignal_U2_ADDR_reg<3>_MC.D2_PT_4/IN6 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U2_ADDR_reg<3>_MC.D2_PT_4/IN7 \ 0 18925 (_entity .  X_INV)
		(_port
			((I) (\Reset_II/UIM \))
			((O) (\NlwInverterSignal_U2_ADDR_reg<3>_MC.D2_PT_4/IN7 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U2_ADDR_reg<3>_MC.D2_PT_4/IN9 \ 0 18929 (_entity .  X_INV)
		(_port
			((I) (U2_WRRDedge))
			((O) (\NlwInverterSignal_U2_ADDR_reg<3>_MC.D2_PT_4/IN9 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U2_ADDR_reg<5>_MC.D2_PT_0/IN1 \ 0 18933 (_entity .  X_INV)
		(_port
			((I) (N_PZ_989))
			((O) (\NlwInverterSignal_U2_ADDR_reg<5>_MC.D2_PT_0/IN1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U2_ADDR_reg<5>_MC.D2_PT_1/IN0 \ 0 18937 (_entity .  X_INV)
		(_port
			((I) (N_PZ_947))
			((O) (\NlwInverterSignal_U2_ADDR_reg<5>_MC.D2_PT_1/IN0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U2_ADDR_reg<5>_MC.D2_PT_1/IN1 \ 0 18941 (_entity .  X_INV)
		(_port
			((I) (N_PZ_989))
			((O) (\NlwInverterSignal_U2_ADDR_reg<5>_MC.D2_PT_1/IN1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_N_PZ_989_MC.D2_PT_1/IN2 \ 0 18945 (_entity .  X_INV)
		(_port
			((I) (N_PZ_947))
			((O) (\NlwInverterSignal_N_PZ_989_MC.D2_PT_1/IN2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_N_PZ_989_MC.D2_PT_1/IN4 \ 0 18949 (_entity .  X_INV)
		(_port
			((I) (U2_WRRDedge))
			((O) (\NlwInverterSignal_N_PZ_989_MC.D2_PT_1/IN4 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U2_ADDR_reg<6>_MC.D2_PT_0/IN1 \ 0 18953 (_entity .  X_INV)
		(_port
			((I) (N_PZ_989))
			((O) (\NlwInverterSignal_U2_ADDR_reg<6>_MC.D2_PT_0/IN1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U2_ADDR_reg<6>_MC.D2_PT_1/IN0 \ 0 18957 (_entity .  X_INV)
		(_port
			((I) (N_PZ_947))
			((O) (\NlwInverterSignal_U2_ADDR_reg<6>_MC.D2_PT_1/IN0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U2_ADDR_reg<6>_MC.D2_PT_1/IN1 \ 0 18961 (_entity .  X_INV)
		(_port
			((I) (N_PZ_989))
			((O) (\NlwInverterSignal_U2_ADDR_reg<6>_MC.D2_PT_1/IN1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U2_ADDR_reg<7>_MC.D2_PT_0/IN1 \ 0 18965 (_entity .  X_INV)
		(_port
			((I) (N_PZ_989))
			((O) (\NlwInverterSignal_U2_ADDR_reg<7>_MC.D2_PT_0/IN1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U2_ADDR_reg<7>_MC.D2_PT_1/IN0 \ 0 18969 (_entity .  X_INV)
		(_port
			((I) (N_PZ_947))
			((O) (\NlwInverterSignal_U2_ADDR_reg<7>_MC.D2_PT_1/IN0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U2_ADDR_reg<7>_MC.D2_PT_1/IN1 \ 0 18973 (_entity .  X_INV)
		(_port
			((I) (N_PZ_989))
			((O) (\NlwInverterSignal_U2_ADDR_reg<7>_MC.D2_PT_1/IN1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U11_U3_counterr<5>_MC.D2_PT_1/IN0 \ 0 18977 (_entity .  X_INV)
		(_port
			((I) (\SCLreset_II/UIM \))
			((O) (\NlwInverterSignal_U11_U3_counterr<5>_MC.D2_PT_1/IN0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U11_U3_counterr<5>_MC.D2_PT_2/IN0 \ 0 18981 (_entity .  X_INV)
		(_port
			((I) (\SCLreset_II/UIM \))
			((O) (\NlwInverterSignal_U11_U3_counterr<5>_MC.D2_PT_2/IN0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U11_U3_counterr<5>_MC.D2_PT_2/IN6 \ 0 18985 (_entity .  X_INV)
		(_port
			((I) (U11_SCLdetect))
			((O) (\NlwInverterSignal_U11_U3_counterr<5>_MC.D2_PT_2/IN6 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U11_U3_counterr<5>_MC.D2_PT_3/IN1 \ 0 18989 (_entity .  X_INV)
		(_port
			((I) (U11_U3_counterr(3)))
			((O) (\NlwInverterSignal_U11_U3_counterr<5>_MC.D2_PT_3/IN1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U11_U3_counterr<5>_MC.D2_PT_3/IN2 \ 0 18993 (_entity .  X_INV)
		(_port
			((I) (U11_U3_counterr(4)))
			((O) (\NlwInverterSignal_U11_U3_counterr<5>_MC.D2_PT_3/IN2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U11_U3_counterr<5>_MC.D2_PT_3/IN3 \ 0 18997 (_entity .  X_INV)
		(_port
			((I) (U11_Incdetect))
			((O) (\NlwInverterSignal_U11_U3_counterr<5>_MC.D2_PT_3/IN3 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U11_U3_counterr<5>_MC.D2_PT_3/IN4 \ 0 19001 (_entity .  X_INV)
		(_port
			((I) (U11_U3_counterr(0)))
			((O) (\NlwInverterSignal_U11_U3_counterr<5>_MC.D2_PT_3/IN4 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U11_U3_counterr<5>_MC.D2_PT_3/IN5 \ 0 19005 (_entity .  X_INV)
		(_port
			((I) (U11_U3_counterr(1)))
			((O) (\NlwInverterSignal_U11_U3_counterr<5>_MC.D2_PT_3/IN5 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U11_U3_counterr<5>_MC.D2_PT_3/IN6 \ 0 19009 (_entity .  X_INV)
		(_port
			((I) (U11_U3_counterr(2)))
			((O) (\NlwInverterSignal_U11_U3_counterr<5>_MC.D2_PT_3/IN6 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U11_U3_counterr<3>_MC.D/IN0 \ 0 19013 (_entity .  X_INV)
		(_port
			((I) (\U11_U3_counterr<3>_MC.D1 \))
			((O) (\NlwInverterSignal_U11_U3_counterr<3>_MC.D/IN0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U11_U3_counterr<3>_MC.D2_PT_1/IN0 \ 0 19017 (_entity .  X_INV)
		(_port
			((I) (\SCLreset_II/UIM \))
			((O) (\NlwInverterSignal_U11_U3_counterr<3>_MC.D2_PT_1/IN0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U11_U3_counterr<3>_MC.D2_PT_1/IN1 \ 0 19021 (_entity .  X_INV)
		(_port
			((I) (U11_Incdetect))
			((O) (\NlwInverterSignal_U11_U3_counterr<3>_MC.D2_PT_1/IN1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U11_U3_counterr<3>_MC.D2_PT_2/IN0 \ 0 19025 (_entity .  X_INV)
		(_port
			((I) (\SCLreset_II/UIM \))
			((O) (\NlwInverterSignal_U11_U3_counterr<3>_MC.D2_PT_2/IN0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U11_U3_counterr<3>_MC.D2_PT_2/IN1 \ 0 19029 (_entity .  X_INV)
		(_port
			((I) (U11_Incdetect))
			((O) (\NlwInverterSignal_U11_U3_counterr<3>_MC.D2_PT_2/IN1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U11_U3_counterr<3>_MC.D2_PT_3/IN0 \ 0 19033 (_entity .  X_INV)
		(_port
			((I) (\SCLreset_II/UIM \))
			((O) (\NlwInverterSignal_U11_U3_counterr<3>_MC.D2_PT_3/IN0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U11_U3_counterr<3>_MC.D2_PT_3/IN1 \ 0 19037 (_entity .  X_INV)
		(_port
			((I) (U11_Incdetect))
			((O) (\NlwInverterSignal_U11_U3_counterr<3>_MC.D2_PT_3/IN1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U11_U3_counterr<3>_MC.D2_PT_4/IN0 \ 0 19041 (_entity .  X_INV)
		(_port
			((I) (\SCLreset_II/UIM \))
			((O) (\NlwInverterSignal_U11_U3_counterr<3>_MC.D2_PT_4/IN0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U11_U3_counterr<3>_MC.D2_PT_4/IN1 \ 0 19045 (_entity .  X_INV)
		(_port
			((I) (U11_Incdetect))
			((O) (\NlwInverterSignal_U11_U3_counterr<3>_MC.D2_PT_4/IN1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U11_U3_counterr<3>_MC.D2_PT_4/IN2 \ 0 19049 (_entity .  X_INV)
		(_port
			((I) (U11_SCLdetect))
			((O) (\NlwInverterSignal_U11_U3_counterr<3>_MC.D2_PT_4/IN2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U11_U3_counterr<3>_MC.D2_PT_5/IN0 \ 0 19053 (_entity .  X_INV)
		(_port
			((I) (U11_U3_counterr(5)))
			((O) (\NlwInverterSignal_U11_U3_counterr<3>_MC.D2_PT_5/IN0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U11_U3_counterr<3>_MC.D2_PT_5/IN1 \ 0 19057 (_entity .  X_INV)
		(_port
			((I) (\SCLreset_II/UIM \))
			((O) (\NlwInverterSignal_U11_U3_counterr<3>_MC.D2_PT_5/IN1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U11_U3_counterr<3>_MC.D2_PT_5/IN2 \ 0 19061 (_entity .  X_INV)
		(_port
			((I) (U11_U3_counterr(3)))
			((O) (\NlwInverterSignal_U11_U3_counterr<3>_MC.D2_PT_5/IN2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U11_U3_counterr<3>_MC.D2_PT_5/IN3 \ 0 19065 (_entity .  X_INV)
		(_port
			((I) (U11_U3_counterr(4)))
			((O) (\NlwInverterSignal_U11_U3_counterr<3>_MC.D2_PT_5/IN3 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U11_U3_counterr<3>_MC.D2_PT_5/IN4 \ 0 19069 (_entity .  X_INV)
		(_port
			((I) (U11_Incdetect))
			((O) (\NlwInverterSignal_U11_U3_counterr<3>_MC.D2_PT_5/IN4 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U11_U3_counterr<3>_MC.D2_PT_6/IN0 \ 0 19073 (_entity .  X_INV)
		(_port
			((I) (\SCLreset_II/UIM \))
			((O) (\NlwInverterSignal_U11_U3_counterr<3>_MC.D2_PT_6/IN0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U11_U3_counterr<3>_MC.D2_PT_6/IN4 \ 0 19077 (_entity .  X_INV)
		(_port
			((I) (U11_SCLdetect))
			((O) (\NlwInverterSignal_U11_U3_counterr<3>_MC.D2_PT_6/IN4 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U11_U3_counterr<0>_MC.D/IN0 \ 0 19081 (_entity .  X_INV)
		(_port
			((I) (\U11_U3_counterr<0>_MC.D1 \))
			((O) (\NlwInverterSignal_U11_U3_counterr<0>_MC.D/IN0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U11_U3_counterr<0>_MC.D2_PT_1/IN0 \ 0 19085 (_entity .  X_INV)
		(_port
			((I) (\SCLreset_II/UIM \))
			((O) (\NlwInverterSignal_U11_U3_counterr<0>_MC.D2_PT_1/IN0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U11_U3_counterr<0>_MC.D2_PT_2/IN0 \ 0 19089 (_entity .  X_INV)
		(_port
			((I) (\SCLreset_II/UIM \))
			((O) (\NlwInverterSignal_U11_U3_counterr<0>_MC.D2_PT_2/IN0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U11_U3_counterr<0>_MC.D2_PT_2/IN1 \ 0 19093 (_entity .  X_INV)
		(_port
			((I) (U11_Incdetect))
			((O) (\NlwInverterSignal_U11_U3_counterr<0>_MC.D2_PT_2/IN1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U11_U3_counterr<0>_MC.D2_PT_2/IN2 \ 0 19097 (_entity .  X_INV)
		(_port
			((I) (U11_SCLdetect))
			((O) (\NlwInverterSignal_U11_U3_counterr<0>_MC.D2_PT_2/IN2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U11_U3_counterr<0>_MC.D2_PT_3/IN0 \ 0 19101 (_entity .  X_INV)
		(_port
			((I) (U11_U3_counterr(5)))
			((O) (\NlwInverterSignal_U11_U3_counterr<0>_MC.D2_PT_3/IN0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U11_U3_counterr<0>_MC.D2_PT_3/IN1 \ 0 19105 (_entity .  X_INV)
		(_port
			((I) (\SCLreset_II/UIM \))
			((O) (\NlwInverterSignal_U11_U3_counterr<0>_MC.D2_PT_3/IN1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U11_U3_counterr<0>_MC.D2_PT_3/IN2 \ 0 19109 (_entity .  X_INV)
		(_port
			((I) (U11_U3_counterr(3)))
			((O) (\NlwInverterSignal_U11_U3_counterr<0>_MC.D2_PT_3/IN2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U11_U3_counterr<0>_MC.D2_PT_3/IN3 \ 0 19113 (_entity .  X_INV)
		(_port
			((I) (U11_U3_counterr(4)))
			((O) (\NlwInverterSignal_U11_U3_counterr<0>_MC.D2_PT_3/IN3 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U11_U3_counterr<0>_MC.D2_PT_3/IN4 \ 0 19117 (_entity .  X_INV)
		(_port
			((I) (U11_U3_counterr(0)))
			((O) (\NlwInverterSignal_U11_U3_counterr<0>_MC.D2_PT_3/IN4 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U11_U3_counterr<0>_MC.D2_PT_3/IN5 \ 0 19121 (_entity .  X_INV)
		(_port
			((I) (U11_U3_counterr(1)))
			((O) (\NlwInverterSignal_U11_U3_counterr<0>_MC.D2_PT_3/IN5 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U11_U3_counterr<0>_MC.D2_PT_3/IN6 \ 0 19125 (_entity .  X_INV)
		(_port
			((I) (U11_U3_counterr(2)))
			((O) (\NlwInverterSignal_U11_U3_counterr<0>_MC.D2_PT_3/IN6 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U11_U3_counterr<4>_MC.D2_PT_1/IN0 \ 0 19129 (_entity .  X_INV)
		(_port
			((I) (\SCLreset_II/UIM \))
			((O) (\NlwInverterSignal_U11_U3_counterr<4>_MC.D2_PT_1/IN0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U11_U3_counterr<4>_MC.D2_PT_2/IN0 \ 0 19133 (_entity .  X_INV)
		(_port
			((I) (\SCLreset_II/UIM \))
			((O) (\NlwInverterSignal_U11_U3_counterr<4>_MC.D2_PT_2/IN0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U11_U3_counterr<4>_MC.D2_PT_2/IN5 \ 0 19137 (_entity .  X_INV)
		(_port
			((I) (U11_SCLdetect))
			((O) (\NlwInverterSignal_U11_U3_counterr<4>_MC.D2_PT_2/IN5 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U11_U3_counterr<4>_MC.D2_PT_3/IN0 \ 0 19141 (_entity .  X_INV)
		(_port
			((I) (U11_U3_counterr(3)))
			((O) (\NlwInverterSignal_U11_U3_counterr<4>_MC.D2_PT_3/IN0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U11_U3_counterr<4>_MC.D2_PT_3/IN2 \ 0 19145 (_entity .  X_INV)
		(_port
			((I) (U11_Incdetect))
			((O) (\NlwInverterSignal_U11_U3_counterr<4>_MC.D2_PT_3/IN2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U11_U3_counterr<4>_MC.D2_PT_3/IN3 \ 0 19149 (_entity .  X_INV)
		(_port
			((I) (U11_U3_counterr(0)))
			((O) (\NlwInverterSignal_U11_U3_counterr<4>_MC.D2_PT_3/IN3 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U11_U3_counterr<4>_MC.D2_PT_3/IN4 \ 0 19153 (_entity .  X_INV)
		(_port
			((I) (U11_U3_counterr(1)))
			((O) (\NlwInverterSignal_U11_U3_counterr<4>_MC.D2_PT_3/IN4 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U11_U3_counterr<4>_MC.D2_PT_3/IN5 \ 0 19157 (_entity .  X_INV)
		(_port
			((I) (U11_U3_counterr(2)))
			((O) (\NlwInverterSignal_U11_U3_counterr<4>_MC.D2_PT_3/IN5 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U11_U3_counterr<4>_MC.D2_PT_4/IN1 \ 0 19161 (_entity .  X_INV)
		(_port
			((I) (\SCLreset_II/UIM \))
			((O) (\NlwInverterSignal_U11_U3_counterr<4>_MC.D2_PT_4/IN1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U11_U3_counterr<4>_MC.D2_PT_4/IN2 \ 0 19165 (_entity .  X_INV)
		(_port
			((I) (U11_U3_counterr(3)))
			((O) (\NlwInverterSignal_U11_U3_counterr<4>_MC.D2_PT_4/IN2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U11_U3_counterr<4>_MC.D2_PT_4/IN3 \ 0 19169 (_entity .  X_INV)
		(_port
			((I) (U11_Incdetect))
			((O) (\NlwInverterSignal_U11_U3_counterr<4>_MC.D2_PT_4/IN3 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U11_U3_counterr<4>_MC.D2_PT_4/IN4 \ 0 19173 (_entity .  X_INV)
		(_port
			((I) (U11_U3_counterr(0)))
			((O) (\NlwInverterSignal_U11_U3_counterr<4>_MC.D2_PT_4/IN4 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U11_U3_counterr<4>_MC.D2_PT_4/IN5 \ 0 19177 (_entity .  X_INV)
		(_port
			((I) (U11_U3_counterr(1)))
			((O) (\NlwInverterSignal_U11_U3_counterr<4>_MC.D2_PT_4/IN5 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U11_U3_counterr<4>_MC.D2_PT_4/IN6 \ 0 19181 (_entity .  X_INV)
		(_port
			((I) (U11_U3_counterr(2)))
			((O) (\NlwInverterSignal_U11_U3_counterr<4>_MC.D2_PT_4/IN6 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U11_Incdetect_MC.D1/IN0 \ 0 19185 (_entity .  X_INV)
		(_port
			((I) (\SCLinc_II/UIM \))
			((O) (\NlwInverterSignal_U11_Incdetect_MC.D1/IN0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U11_U3_counterr<1>_MC.D/IN0 \ 0 19189 (_entity .  X_INV)
		(_port
			((I) (\U11_U3_counterr<1>_MC.D1 \))
			((O) (\NlwInverterSignal_U11_U3_counterr<1>_MC.D/IN0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U11_U3_counterr<1>_MC.D2_PT_0/IN1 \ 0 19193 (_entity .  X_INV)
		(_port
			((I) (U11_U3_counterr(1)))
			((O) (\NlwInverterSignal_U11_U3_counterr<1>_MC.D2_PT_0/IN1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U11_U3_counterr<1>_MC.D2_PT_1/IN0 \ 0 19197 (_entity .  X_INV)
		(_port
			((I) (\SCLreset_II/UIM \))
			((O) (\NlwInverterSignal_U11_U3_counterr<1>_MC.D2_PT_1/IN0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U11_U3_counterr<1>_MC.D2_PT_2/IN0 \ 0 19201 (_entity .  X_INV)
		(_port
			((I) (\SCLreset_II/UIM \))
			((O) (\NlwInverterSignal_U11_U3_counterr<1>_MC.D2_PT_2/IN0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U11_U3_counterr<1>_MC.D2_PT_2/IN1 \ 0 19205 (_entity .  X_INV)
		(_port
			((I) (U11_Incdetect))
			((O) (\NlwInverterSignal_U11_U3_counterr<1>_MC.D2_PT_2/IN1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U11_U3_counterr<1>_MC.D2_PT_3/IN0 \ 0 19209 (_entity .  X_INV)
		(_port
			((I) (\SCLreset_II/UIM \))
			((O) (\NlwInverterSignal_U11_U3_counterr<1>_MC.D2_PT_3/IN0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U11_U3_counterr<1>_MC.D2_PT_3/IN1 \ 0 19213 (_entity .  X_INV)
		(_port
			((I) (U11_U3_counterr(0)))
			((O) (\NlwInverterSignal_U11_U3_counterr<1>_MC.D2_PT_3/IN1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U11_U3_counterr<1>_MC.D2_PT_3/IN2 \ 0 19217 (_entity .  X_INV)
		(_port
			((I) (U11_SCLdetect))
			((O) (\NlwInverterSignal_U11_U3_counterr<1>_MC.D2_PT_3/IN2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U11_U3_counterr<1>_MC.D2_PT_4/IN0 \ 0 19221 (_entity .  X_INV)
		(_port
			((I) (U11_U3_counterr(5)))
			((O) (\NlwInverterSignal_U11_U3_counterr<1>_MC.D2_PT_4/IN0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U11_U3_counterr<1>_MC.D2_PT_4/IN1 \ 0 19225 (_entity .  X_INV)
		(_port
			((I) (U11_U3_counterr(3)))
			((O) (\NlwInverterSignal_U11_U3_counterr<1>_MC.D2_PT_4/IN1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U11_U3_counterr<1>_MC.D2_PT_4/IN2 \ 0 19229 (_entity .  X_INV)
		(_port
			((I) (U11_U3_counterr(4)))
			((O) (\NlwInverterSignal_U11_U3_counterr<1>_MC.D2_PT_4/IN2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U11_U3_counterr<1>_MC.D2_PT_4/IN3 \ 0 19233 (_entity .  X_INV)
		(_port
			((I) (U11_U3_counterr(1)))
			((O) (\NlwInverterSignal_U11_U3_counterr<1>_MC.D2_PT_4/IN3 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U11_U3_counterr<1>_MC.D2_PT_4/IN4 \ 0 19237 (_entity .  X_INV)
		(_port
			((I) (U11_U3_counterr(2)))
			((O) (\NlwInverterSignal_U11_U3_counterr<1>_MC.D2_PT_4/IN4 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U11_U3_counterr<2>_MC.D2_PT_1/IN0 \ 0 19241 (_entity .  X_INV)
		(_port
			((I) (\SCLreset_II/UIM \))
			((O) (\NlwInverterSignal_U11_U3_counterr<2>_MC.D2_PT_1/IN0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U11_U3_counterr<2>_MC.D2_PT_1/IN4 \ 0 19245 (_entity .  X_INV)
		(_port
			((I) (U11_SCLdetect))
			((O) (\NlwInverterSignal_U11_U3_counterr<2>_MC.D2_PT_1/IN4 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U11_U3_counterr<2>_MC.D2_PT_2/IN0 \ 0 19249 (_entity .  X_INV)
		(_port
			((I) (U11_Incdetect))
			((O) (\NlwInverterSignal_U11_U3_counterr<2>_MC.D2_PT_2/IN0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U11_U3_counterr<2>_MC.D2_PT_2/IN1 \ 0 19253 (_entity .  X_INV)
		(_port
			((I) (U11_U3_counterr(0)))
			((O) (\NlwInverterSignal_U11_U3_counterr<2>_MC.D2_PT_2/IN1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U11_U3_counterr<2>_MC.D2_PT_2/IN2 \ 0 19257 (_entity .  X_INV)
		(_port
			((I) (U11_U3_counterr(1)))
			((O) (\NlwInverterSignal_U11_U3_counterr<2>_MC.D2_PT_2/IN2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U11_U3_counterr<2>_MC.D2_PT_3/IN1 \ 0 19261 (_entity .  X_INV)
		(_port
			((I) (\SCLreset_II/UIM \))
			((O) (\NlwInverterSignal_U11_U3_counterr<2>_MC.D2_PT_3/IN1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U11_U3_counterr<2>_MC.D2_PT_3/IN2 \ 0 19265 (_entity .  X_INV)
		(_port
			((I) (U11_Incdetect))
			((O) (\NlwInverterSignal_U11_U3_counterr<2>_MC.D2_PT_3/IN2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U11_U3_counterr<2>_MC.D2_PT_3/IN3 \ 0 19269 (_entity .  X_INV)
		(_port
			((I) (U11_U3_counterr(0)))
			((O) (\NlwInverterSignal_U11_U3_counterr<2>_MC.D2_PT_3/IN3 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U11_U3_counterr<2>_MC.D2_PT_3/IN4 \ 0 19273 (_entity .  X_INV)
		(_port
			((I) (U11_U3_counterr(1)))
			((O) (\NlwInverterSignal_U11_U3_counterr<2>_MC.D2_PT_3/IN4 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U11_U3_counterr<2>_MC.D2_PT_4/IN0 \ 0 19277 (_entity .  X_INV)
		(_port
			((I) (\SCLreset_II/UIM \))
			((O) (\NlwInverterSignal_U11_U3_counterr<2>_MC.D2_PT_4/IN0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U11_U3_counterr<2>_MC.D2_PT_4/IN2 \ 0 19281 (_entity .  X_INV)
		(_port
			((I) (U11_Incdetect))
			((O) (\NlwInverterSignal_U11_U3_counterr<2>_MC.D2_PT_4/IN2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U11_U3_counterr<2>_MC.D2_PT_4/IN3 \ 0 19285 (_entity .  X_INV)
		(_port
			((I) (U11_U3_counterr(0)))
			((O) (\NlwInverterSignal_U11_U3_counterr<2>_MC.D2_PT_4/IN3 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U11_U3_counterr<2>_MC.D2_PT_4/IN4 \ 0 19289 (_entity .  X_INV)
		(_port
			((I) (U11_U3_counterr(1)))
			((O) (\NlwInverterSignal_U11_U3_counterr<2>_MC.D2_PT_4/IN4 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U11_U3_counterr<2>_MC.D2_PT_5/IN0 \ 0 19293 (_entity .  X_INV)
		(_port
			((I) (\SCLreset_II/UIM \))
			((O) (\NlwInverterSignal_U11_U3_counterr<2>_MC.D2_PT_5/IN0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U11_U3_counterr<2>_MC.D2_PT_5/IN2 \ 0 19297 (_entity .  X_INV)
		(_port
			((I) (U11_Incdetect))
			((O) (\NlwInverterSignal_U11_U3_counterr<2>_MC.D2_PT_5/IN2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U11_U3_counterr<2>_MC.D2_PT_5/IN3 \ 0 19301 (_entity .  X_INV)
		(_port
			((I) (U11_U3_counterr(0)))
			((O) (\NlwInverterSignal_U11_U3_counterr<2>_MC.D2_PT_5/IN3 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U11_U3_counterr<2>_MC.D2_PT_5/IN4 \ 0 19305 (_entity .  X_INV)
		(_port
			((I) (U11_U3_counterr(1)))
			((O) (\NlwInverterSignal_U11_U3_counterr<2>_MC.D2_PT_5/IN4 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U11_SCLdetect_MC.D1/IN0 \ 0 19309 (_entity .  X_INV)
		(_port
			((I) (\SCL_II/UIM \))
			((O) (\NlwInverterSignal_U11_SCLdetect_MC.D1/IN0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_outDATA<5>\\$WA3.UIM_MC.D2_PT_0/IN1 \ 0 19313 (_entity .  X_INV)
		(_port
			((I) (NET2528))
			((O) (\NlwInverterSignal_outDATA<5>\\$WA3.UIM_MC.D2_PT_0/IN1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_NET2528_MC.D/IN0 \ 0 19317 (_entity .  X_INV)
		(_port
			((I) (\NET2528_MC.D1 \))
			((O) (\NlwInverterSignal_NET2528_MC.D/IN0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_NET2528_MC.D2_PT_1/IN1 \ 0 19321 (_entity .  X_INV)
		(_port
			((I) (NET2528))
			((O) (\NlwInverterSignal_NET2528_MC.D2_PT_1/IN1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_NET2528_MC.D2_PT_2/IN0 \ 0 19325 (_entity .  X_INV)
		(_port
			((I) (U2_ADDR_reg(0)))
			((O) (\NlwInverterSignal_NET2528_MC.D2_PT_2/IN0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_NET2528_MC.D2_PT_2/IN1 \ 0 19329 (_entity .  X_INV)
		(_port
			((I) (\AD<1>_II/UIM \))
			((O) (\NlwInverterSignal_NET2528_MC.D2_PT_2/IN1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_NET2528_MC.D2_PT_3/IN0 \ 0 19333 (_entity .  X_INV)
		(_port
			((I) (NET2528))
			((O) (\NlwInverterSignal_NET2528_MC.D2_PT_3/IN0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_NET2528_MC.D2_PT_3/IN2 \ 0 19337 (_entity .  X_INV)
		(_port
			((I) (N_PZ_978))
			((O) (\NlwInverterSignal_NET2528_MC.D2_PT_3/IN2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_N_PZ_978_MC.D2_PT_1/IN0 \ 0 19341 (_entity .  X_INV)
		(_port
			((I) (\WR_II/UIM \))
			((O) (\NlwInverterSignal_N_PZ_978_MC.D2_PT_1/IN0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_N_PZ_978_MC.D2_PT_1/IN4 \ 0 19345 (_entity .  X_INV)
		(_port
			((I) (U2_ADDR_reg(2)))
			((O) (\NlwInverterSignal_N_PZ_978_MC.D2_PT_1/IN4 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_N_PZ_978_MC.D2_PT_1/IN5 \ 0 19349 (_entity .  X_INV)
		(_port
			((I) (U2_ADDR_reg(3)))
			((O) (\NlwInverterSignal_N_PZ_978_MC.D2_PT_1/IN5 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/U3/holdingreg<5>_MC.D2_PT_1/IN0 \ 0 19353 (_entity .  X_INV)
		(_port
			((I) (\Reset_II/UIM \))
			((O) (\NlwInverterSignal_U1/U3/holdingreg<5>_MC.D2_PT_1/IN0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/U3/holdingreg<5>_MC.D2_PT_2/IN1 \ 0 19357 (_entity .  X_INV)
		(_port
			((I) (\RD_II/UIM \))
			((O) (\NlwInverterSignal_U1/U3/holdingreg<5>_MC.D2_PT_2/IN1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/U3/holdingreg<5>_MC.D2_PT_2/IN6 \ 0 19361 (_entity .  X_INV)
		(_port
			((I) (U2_ADDR_reg(3)))
			((O) (\NlwInverterSignal_U1/U3/holdingreg<5>_MC.D2_PT_2/IN6 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/U3/holdingreg<5>_MC.D2_PT_2/IN7 \ 0 19365 (_entity .  X_INV)
		(_port
			((I) (\Reset_II/UIM \))
			((O) (\NlwInverterSignal_U1/U3/holdingreg<5>_MC.D2_PT_2/IN7 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/U3/holdingreg<5>_MC.D2_PT_2/IN8 \ 0 19369 (_entity .  X_INV)
		(_port
			((I) (\U1/U3/RDedge \))
			((O) (\NlwInverterSignal_U1/U3/holdingreg<5>_MC.D2_PT_2/IN8 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_N_PZ_966_MC.D2_PT_0/IN4 \ 0 19373 (_entity .  X_INV)
		(_port
			((I) (U2_ADDR_reg(3)))
			((O) (\NlwInverterSignal_N_PZ_966_MC.D2_PT_0/IN4 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_N_PZ_966_MC.D2_PT_1/IN0 \ 0 19377 (_entity .  X_INV)
		(_port
			((I) (U2_ADDR_reg(1)))
			((O) (\NlwInverterSignal_N_PZ_966_MC.D2_PT_1/IN0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_N_PZ_966_MC.D2_PT_1/IN1 \ 0 19381 (_entity .  X_INV)
		(_port
			((I) (U2_ADDR_reg(0)))
			((O) (\NlwInverterSignal_N_PZ_966_MC.D2_PT_1/IN1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_N_PZ_966_MC.D2_PT_1/IN4 \ 0 19385 (_entity .  X_INV)
		(_port
			((I) (U2_ADDR_reg(3)))
			((O) (\NlwInverterSignal_N_PZ_966_MC.D2_PT_1/IN4 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U2_Enable_AD_MC.D1/IN1 \ 0 19389 (_entity .  X_INV)
		(_port
			((I) (\RD_II/UIM \))
			((O) (\NlwInverterSignal_U2_Enable_AD_MC.D1/IN1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/Channel0<5>_MC.D2_PT_0/IN1 \ 0 19393 (_entity .  X_INV)
		(_port
			((I) (N_PZ_949))
			((O) (\NlwInverterSignal_U1/Channel0<5>_MC.D2_PT_0/IN1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/Channel0<5>_MC.D2_PT_1/IN4 \ 0 19397 (_entity .  X_INV)
		(_port
			((I) (N_PZ_961))
			((O) (\NlwInverterSignal_U1/Channel0<5>_MC.D2_PT_1/IN4 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/Channel0<5>_MC.D2_PT_2/IN1 \ 0 19401 (_entity .  X_INV)
		(_port
			((I) (\U1/Channel0 \(0)))
			((O) (\NlwInverterSignal_U1/Channel0<5>_MC.D2_PT_2/IN1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/Channel0<5>_MC.D2_PT_2/IN3 \ 0 19405 (_entity .  X_INV)
		(_port
			((I) (\U1/Channel0 \(1)))
			((O) (\NlwInverterSignal_U1/Channel0<5>_MC.D2_PT_2/IN3 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/Channel0<5>_MC.D2_PT_2/IN5 \ 0 19409 (_entity .  X_INV)
		(_port
			((I) (\U1/Channel0 \(2)))
			((O) (\NlwInverterSignal_U1/Channel0<5>_MC.D2_PT_2/IN5 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/Channel0<5>_MC.D2_PT_2/IN6 \ 0 19413 (_entity .  X_INV)
		(_port
			((I) (\U1/Channel0 \(3)))
			((O) (\NlwInverterSignal_U1/Channel0<5>_MC.D2_PT_2/IN6 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/Channel0<5>_MC.D2_PT_2/IN7 \ 0 19417 (_entity .  X_INV)
		(_port
			((I) (\U1/Channel0 \(4)))
			((O) (\NlwInverterSignal_U1/Channel0<5>_MC.D2_PT_2/IN7 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_N_PZ_949_MC.D1/IN0 \ 0 19421 (_entity .  X_INV)
		(_port
			((I) (\Reset_II/UIM \))
			((O) (\NlwInverterSignal_N_PZ_949_MC.D1/IN0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_N_PZ_949_MC.D1/IN1 \ 0 19425 (_entity .  X_INV)
		(_port
			((I) (\U1/Zero0 \))
			((O) (\NlwInverterSignal_N_PZ_949_MC.D1/IN1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/Zero0_MC.D2_PT_1/IN0 \ 0 19429 (_entity .  X_INV)
		(_port
			((I) (N_PZ_978))
			((O) (\NlwInverterSignal_U1/Zero0_MC.D2_PT_1/IN0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/Zero0_MC.D2_PT_1/IN1 \ 0 19433 (_entity .  X_INV)
		(_port
			((I) (NET2482))
			((O) (\NlwInverterSignal_U1/Zero0_MC.D2_PT_1/IN1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/Zero0_MC.D2_PT_1/IN4 \ 0 19437 (_entity .  X_INV)
		(_port
			((I) (\U1/U4/HE0statelastr \))
			((O) (\NlwInverterSignal_U1/Zero0_MC.D2_PT_1/IN4 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/Zero0_MC.D2_PT_2/IN0 \ 0 19441 (_entity .  X_INV)
		(_port
			((I) (N_PZ_978))
			((O) (\NlwInverterSignal_U1/Zero0_MC.D2_PT_2/IN0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/Zero0_MC.D2_PT_2/IN1 \ 0 19445 (_entity .  X_INV)
		(_port
			((I) (NET2482))
			((O) (\NlwInverterSignal_U1/Zero0_MC.D2_PT_2/IN1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/Zero0_MC.D2_PT_2/IN2 \ 0 19449 (_entity .  X_INV)
		(_port
			((I) (\U1/U4/RF0r \))
			((O) (\NlwInverterSignal_U1/Zero0_MC.D2_PT_2/IN2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/Zero0_MC.D2_PT_2/IN3 \ 0 19453 (_entity .  X_INV)
		(_port
			((I) (\U1/U4/HE0stater \))
			((O) (\NlwInverterSignal_U1/Zero0_MC.D2_PT_2/IN3 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_NET2482_MC.D2_PT_0/IN0 \ 0 19457 (_entity .  X_INV)
		(_port
			((I) (N_PZ_978))
			((O) (\NlwInverterSignal_NET2482_MC.D2_PT_0/IN0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_NET2482_MC.D2_PT_0/IN1 \ 0 19461 (_entity .  X_INV)
		(_port
			((I) (NET2482))
			((O) (\NlwInverterSignal_NET2482_MC.D2_PT_0/IN1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_NET2482_MC.D2_PT_0/IN4 \ 0 19465 (_entity .  X_INV)
		(_port
			((I) (\U1/U4/HE0statelastr \))
			((O) (\NlwInverterSignal_NET2482_MC.D2_PT_0/IN4 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_NET2482_MC.D2_PT_1/IN0 \ 0 19469 (_entity .  X_INV)
		(_port
			((I) (N_PZ_978))
			((O) (\NlwInverterSignal_NET2482_MC.D2_PT_1/IN0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_NET2482_MC.D2_PT_1/IN1 \ 0 19473 (_entity .  X_INV)
		(_port
			((I) (NET2482))
			((O) (\NlwInverterSignal_NET2482_MC.D2_PT_1/IN1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_NET2482_MC.D2_PT_1/IN2 \ 0 19477 (_entity .  X_INV)
		(_port
			((I) (\U1/U4/RF0r \))
			((O) (\NlwInverterSignal_NET2482_MC.D2_PT_1/IN2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_NET2482_MC.D2_PT_1/IN3 \ 0 19481 (_entity .  X_INV)
		(_port
			((I) (\U1/U4/HE0stater \))
			((O) (\NlwInverterSignal_NET2482_MC.D2_PT_1/IN3 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_NET2482_MC.D2_PT_2/IN0 \ 0 19485 (_entity .  X_INV)
		(_port
			((I) (\WR_II/UIM \))
			((O) (\NlwInverterSignal_NET2482_MC.D2_PT_2/IN0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_NET2482_MC.D2_PT_2/IN3 \ 0 19489 (_entity .  X_INV)
		(_port
			((I) (U2_ADDR_reg(0)))
			((O) (\NlwInverterSignal_NET2482_MC.D2_PT_2/IN3 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_NET2482_MC.D2_PT_2/IN5 \ 0 19493 (_entity .  X_INV)
		(_port
			((I) (U2_ADDR_reg(2)))
			((O) (\NlwInverterSignal_NET2482_MC.D2_PT_2/IN5 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_NET2482_MC.D2_PT_2/IN6 \ 0 19497 (_entity .  X_INV)
		(_port
			((I) (U2_ADDR_reg(3)))
			((O) (\NlwInverterSignal_NET2482_MC.D2_PT_2/IN6 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_NET2482_MC.D2_PT_2/IN7 \ 0 19501 (_entity .  X_INV)
		(_port
			((I) (\Reset_II/UIM \))
			((O) (\NlwInverterSignal_NET2482_MC.D2_PT_2/IN7 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_NET2482_MC.D2_PT_2/IN9 \ 0 19505 (_entity .  X_INV)
		(_port
			((I) (NET2482))
			((O) (\NlwInverterSignal_NET2482_MC.D2_PT_2/IN9 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_NET2482_MC.D2_PT_3/IN0 \ 0 19509 (_entity .  X_INV)
		(_port
			((I) (\WR_II/UIM \))
			((O) (\NlwInverterSignal_NET2482_MC.D2_PT_3/IN0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_NET2482_MC.D2_PT_3/IN3 \ 0 19513 (_entity .  X_INV)
		(_port
			((I) (U2_ADDR_reg(0)))
			((O) (\NlwInverterSignal_NET2482_MC.D2_PT_3/IN3 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_NET2482_MC.D2_PT_3/IN5 \ 0 19517 (_entity .  X_INV)
		(_port
			((I) (U2_ADDR_reg(2)))
			((O) (\NlwInverterSignal_NET2482_MC.D2_PT_3/IN5 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_NET2482_MC.D2_PT_3/IN6 \ 0 19521 (_entity .  X_INV)
		(_port
			((I) (U2_ADDR_reg(3)))
			((O) (\NlwInverterSignal_NET2482_MC.D2_PT_3/IN6 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_NET2482_MC.D2_PT_3/IN7 \ 0 19525 (_entity .  X_INV)
		(_port
			((I) (\Reset_II/UIM \))
			((O) (\NlwInverterSignal_NET2482_MC.D2_PT_3/IN7 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_NET2482_MC.D2_PT_3/IN8 \ 0 19529 (_entity .  X_INV)
		(_port
			((I) (\AD<2>_II/UIM \))
			((O) (\NlwInverterSignal_NET2482_MC.D2_PT_3/IN8 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/U4/RF0r_MC.D2_PT_1/IN0 \ 0 19533 (_entity .  X_INV)
		(_port
			((I) (\WR_II/UIM \))
			((O) (\NlwInverterSignal_U1/U4/RF0r_MC.D2_PT_1/IN0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/U4/RF0r_MC.D2_PT_1/IN5 \ 0 19537 (_entity .  X_INV)
		(_port
			((I) (U2_ADDR_reg(2)))
			((O) (\NlwInverterSignal_U1/U4/RF0r_MC.D2_PT_1/IN5 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/U4/RF0r_MC.D2_PT_1/IN6 \ 0 19541 (_entity .  X_INV)
		(_port
			((I) (U2_ADDR_reg(3)))
			((O) (\NlwInverterSignal_U1/U4/RF0r_MC.D2_PT_1/IN6 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/U4/RF0r_MC.D2_PT_1/IN7 \ 0 19545 (_entity .  X_INV)
		(_port
			((I) (\AD<0>_II/UIM \))
			((O) (\NlwInverterSignal_U1/U4/RF0r_MC.D2_PT_1/IN7 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/U4/RF0r_MC.D2_PT_2/IN0 \ 0 19549 (_entity .  X_INV)
		(_port
			((I) (\WR_II/UIM \))
			((O) (\NlwInverterSignal_U1/U4/RF0r_MC.D2_PT_2/IN0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/U4/RF0r_MC.D2_PT_2/IN5 \ 0 19553 (_entity .  X_INV)
		(_port
			((I) (U2_ADDR_reg(2)))
			((O) (\NlwInverterSignal_U1/U4/RF0r_MC.D2_PT_2/IN5 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/U4/RF0r_MC.D2_PT_2/IN6 \ 0 19557 (_entity .  X_INV)
		(_port
			((I) (U2_ADDR_reg(3)))
			((O) (\NlwInverterSignal_U1/U4/RF0r_MC.D2_PT_2/IN6 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/U4/RF0r_MC.D2_PT_2/IN7 \ 0 19561 (_entity .  X_INV)
		(_port
			((I) (\Reset_II/UIM \))
			((O) (\NlwInverterSignal_U1/U4/RF0r_MC.D2_PT_2/IN7 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/U4/RF0r_MC.D2_PT_2/IN9 \ 0 19565 (_entity .  X_INV)
		(_port
			((I) (\U1/U4/RF0r \))
			((O) (\NlwInverterSignal_U1/U4/RF0r_MC.D2_PT_2/IN9 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/U4/E0r_MC.D2_PT_1/IN0 \ 0 19569 (_entity .  X_INV)
		(_port
			((I) (\WR_II/UIM \))
			((O) (\NlwInverterSignal_U1/U4/E0r_MC.D2_PT_1/IN0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/U4/E0r_MC.D2_PT_1/IN5 \ 0 19573 (_entity .  X_INV)
		(_port
			((I) (U2_ADDR_reg(2)))
			((O) (\NlwInverterSignal_U1/U4/E0r_MC.D2_PT_1/IN5 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/U4/E0r_MC.D2_PT_1/IN6 \ 0 19577 (_entity .  X_INV)
		(_port
			((I) (U2_ADDR_reg(3)))
			((O) (\NlwInverterSignal_U1/U4/E0r_MC.D2_PT_1/IN6 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/U4/E0r_MC.D2_PT_1/IN7 \ 0 19581 (_entity .  X_INV)
		(_port
			((I) (\AD<1>_II/UIM \))
			((O) (\NlwInverterSignal_U1/U4/E0r_MC.D2_PT_1/IN7 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/U4/E0r_MC.D2_PT_2/IN0 \ 0 19585 (_entity .  X_INV)
		(_port
			((I) (\WR_II/UIM \))
			((O) (\NlwInverterSignal_U1/U4/E0r_MC.D2_PT_2/IN0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/U4/E0r_MC.D2_PT_2/IN5 \ 0 19589 (_entity .  X_INV)
		(_port
			((I) (U2_ADDR_reg(2)))
			((O) (\NlwInverterSignal_U1/U4/E0r_MC.D2_PT_2/IN5 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/U4/E0r_MC.D2_PT_2/IN6 \ 0 19593 (_entity .  X_INV)
		(_port
			((I) (U2_ADDR_reg(3)))
			((O) (\NlwInverterSignal_U1/U4/E0r_MC.D2_PT_2/IN6 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/U4/E0r_MC.D2_PT_2/IN8 \ 0 19597 (_entity .  X_INV)
		(_port
			((I) (\Reset_II/UIM \))
			((O) (\NlwInverterSignal_U1/U4/E0r_MC.D2_PT_2/IN8 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/U4/E0r_MC.D2_PT_2/IN9 \ 0 19601 (_entity .  X_INV)
		(_port
			((I) (\U1/U4/E0r \))
			((O) (\NlwInverterSignal_U1/U4/E0r_MC.D2_PT_2/IN9 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/Channel0<0>_MC.D2_PT_0/IN2 \ 0 19605 (_entity .  X_INV)
		(_port
			((I) (N_PZ_1018))
			((O) (\NlwInverterSignal_U1/Channel0<0>_MC.D2_PT_0/IN2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/Channel0<0>_MC.D2_PT_1/IN1 \ 0 19609 (_entity .  X_INV)
		(_port
			((I) (\U1/Channel0 \(0)))
			((O) (\NlwInverterSignal_U1/Channel0<0>_MC.D2_PT_1/IN1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_N_PZ_1018_MC.D2_PT_0/IN1 \ 0 19613 (_entity .  X_INV)
		(_port
			((I) (\U1/U1/CurrState_Sreg0_FFD2 \))
			((O) (\NlwInverterSignal_N_PZ_1018_MC.D2_PT_0/IN1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_N_PZ_1018_MC.D2_PT_0/IN3 \ 0 19617 (_entity .  X_INV)
		(_port
			((I) (\U1/U1/CurrState_Sreg0_FFD1 \))
			((O) (\NlwInverterSignal_N_PZ_1018_MC.D2_PT_0/IN3 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_N_PZ_1018_MC.D2_PT_1/IN1 \ 0 19621 (_entity .  X_INV)
		(_port
			((I) (\U1/U1/CurrState_Sreg0_FFD2 \))
			((O) (\NlwInverterSignal_N_PZ_1018_MC.D2_PT_1/IN1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_N_PZ_1018_MC.D2_PT_1/IN2 \ 0 19625 (_entity .  X_INV)
		(_port
			((I) (\U1/U1/CurrState_Sreg0_FFD4 \))
			((O) (\NlwInverterSignal_N_PZ_1018_MC.D2_PT_1/IN2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/U1/CurrState_Sreg0_FFD3_MC.D2_PT_0/IN0 \ 0 19629 (_entity .  X_INV)
		(_port
			((I) (\Reset_II/UIM \))
			((O) (\NlwInverterSignal_U1/U1/CurrState_Sreg0_FFD3_MC.D2_PT_0/IN0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/U1/CurrState_Sreg0_FFD3_MC.D2_PT_0/IN3 \ 0 19633 (_entity .  X_INV)
		(_port
			((I) (\U1/U1/CurrState_Sreg0_FFD4 \))
			((O) (\NlwInverterSignal_U1/U1/CurrState_Sreg0_FFD3_MC.D2_PT_0/IN3 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/U1/CurrState_Sreg0_FFD3_MC.D2_PT_0/IN4 \ 0 19637 (_entity .  X_INV)
		(_port
			((I) (\PhaseA_Encoder0_II/UIM \))
			((O) (\NlwInverterSignal_U1/U1/CurrState_Sreg0_FFD3_MC.D2_PT_0/IN4 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/U1/CurrState_Sreg0_FFD3_MC.D2_PT_1/IN0 \ 0 19641 (_entity .  X_INV)
		(_port
			((I) (\Reset_II/UIM \))
			((O) (\NlwInverterSignal_U1/U1/CurrState_Sreg0_FFD3_MC.D2_PT_1/IN0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/U1/CurrState_Sreg0_FFD3_MC.D2_PT_1/IN2 \ 0 19645 (_entity .  X_INV)
		(_port
			((I) (\U1/U1/CurrState_Sreg0_FFD2 \))
			((O) (\NlwInverterSignal_U1/U1/CurrState_Sreg0_FFD3_MC.D2_PT_1/IN2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/U1/CurrState_Sreg0_FFD3_MC.D2_PT_1/IN3 \ 0 19649 (_entity .  X_INV)
		(_port
			((I) (\U1/U1/CurrState_Sreg0_FFD4 \))
			((O) (\NlwInverterSignal_U1/U1/CurrState_Sreg0_FFD3_MC.D2_PT_1/IN3 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/U1/CurrState_Sreg0_FFD3_MC.D2_PT_1/IN4 \ 0 19653 (_entity .  X_INV)
		(_port
			((I) (\U1/U1/CurrState_Sreg0_FFD1 \))
			((O) (\NlwInverterSignal_U1/U1/CurrState_Sreg0_FFD3_MC.D2_PT_1/IN4 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/U1/CurrState_Sreg0_FFD3_MC.D2_PT_2/IN0 \ 0 19657 (_entity .  X_INV)
		(_port
			((I) (\Reset_II/UIM \))
			((O) (\NlwInverterSignal_U1/U1/CurrState_Sreg0_FFD3_MC.D2_PT_2/IN0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/U1/CurrState_Sreg0_FFD3_MC.D2_PT_2/IN2 \ 0 19661 (_entity .  X_INV)
		(_port
			((I) (\U1/U1/CurrState_Sreg0_FFD4 \))
			((O) (\NlwInverterSignal_U1/U1/CurrState_Sreg0_FFD3_MC.D2_PT_2/IN2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/U1/CurrState_Sreg0_FFD2_MC.D2_PT_0/IN0 \ 0 19665 (_entity .  X_INV)
		(_port
			((I) (\Reset_II/UIM \))
			((O) (\NlwInverterSignal_U1/U1/CurrState_Sreg0_FFD2_MC.D2_PT_0/IN0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/U1/CurrState_Sreg0_FFD2_MC.D2_PT_0/IN3 \ 0 19669 (_entity .  X_INV)
		(_port
			((I) (\U1/U1/CurrState_Sreg0_FFD4 \))
			((O) (\NlwInverterSignal_U1/U1/CurrState_Sreg0_FFD2_MC.D2_PT_0/IN3 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/U1/CurrState_Sreg0_FFD2_MC.D2_PT_0/IN4 \ 0 19673 (_entity .  X_INV)
		(_port
			((I) (N_PZ_1183))
			((O) (\NlwInverterSignal_U1/U1/CurrState_Sreg0_FFD2_MC.D2_PT_0/IN4 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/U1/CurrState_Sreg0_FFD2_MC.D2_PT_1/IN0 \ 0 19677 (_entity .  X_INV)
		(_port
			((I) (\Reset_II/UIM \))
			((O) (\NlwInverterSignal_U1/U1/CurrState_Sreg0_FFD2_MC.D2_PT_1/IN0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/U1/CurrState_Sreg0_FFD2_MC.D2_PT_1/IN1 \ 0 19681 (_entity .  X_INV)
		(_port
			((I) (\U1/U1/CurrState_Sreg0_FFD3 \))
			((O) (\NlwInverterSignal_U1/U1/CurrState_Sreg0_FFD2_MC.D2_PT_1/IN1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/U1/CurrState_Sreg0_FFD2_MC.D2_PT_1/IN3 \ 0 19685 (_entity .  X_INV)
		(_port
			((I) (\U1/U1/CurrState_Sreg0_FFD4 \))
			((O) (\NlwInverterSignal_U1/U1/CurrState_Sreg0_FFD2_MC.D2_PT_1/IN3 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/U1/CurrState_Sreg0_FFD2_MC.D2_PT_2/IN0 \ 0 19689 (_entity .  X_INV)
		(_port
			((I) (\Reset_II/UIM \))
			((O) (\NlwInverterSignal_U1/U1/CurrState_Sreg0_FFD2_MC.D2_PT_2/IN0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/U1/CurrState_Sreg0_FFD2_MC.D2_PT_2/IN1 \ 0 19693 (_entity .  X_INV)
		(_port
			((I) (\U1/U1/CurrState_Sreg0_FFD3 \))
			((O) (\NlwInverterSignal_U1/U1/CurrState_Sreg0_FFD2_MC.D2_PT_2/IN1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/U1/CurrState_Sreg0_FFD2_MC.D2_PT_2/IN2 \ 0 19697 (_entity .  X_INV)
		(_port
			((I) (\U1/U1/CurrState_Sreg0_FFD4 \))
			((O) (\NlwInverterSignal_U1/U1/CurrState_Sreg0_FFD2_MC.D2_PT_2/IN2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/U1/CurrState_Sreg0_FFD2_MC.D2_PT_2/IN4 \ 0 19701 (_entity .  X_INV)
		(_port
			((I) (N_PZ_1183))
			((O) (\NlwInverterSignal_U1/U1/CurrState_Sreg0_FFD2_MC.D2_PT_2/IN4 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/U1/CurrState_Sreg0_FFD2_MC.D2_PT_3/IN0 \ 0 19705 (_entity .  X_INV)
		(_port
			((I) (\Reset_II/UIM \))
			((O) (\NlwInverterSignal_U1/U1/CurrState_Sreg0_FFD2_MC.D2_PT_3/IN0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/U1/CurrState_Sreg0_FFD2_MC.D2_PT_3/IN1 \ 0 19709 (_entity .  X_INV)
		(_port
			((I) (N_PZ_1018))
			((O) (\NlwInverterSignal_U1/U1/CurrState_Sreg0_FFD2_MC.D2_PT_3/IN1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/U1/CurrState_Sreg0_FFD2_MC.D2_PT_3/IN3 \ 0 19713 (_entity .  X_INV)
		(_port
			((I) (\U1/U1/CurrState_Sreg0_FFD4 \))
			((O) (\NlwInverterSignal_U1/U1/CurrState_Sreg0_FFD2_MC.D2_PT_3/IN3 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/U1/CurrState_Sreg0_FFD4_MC.D1/IN0 \ 0 19717 (_entity .  X_INV)
		(_port
			((I) (\Reset_II/UIM \))
			((O) (\NlwInverterSignal_U1/U1/CurrState_Sreg0_FFD4_MC.D1/IN0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/U1/CurrState_Sreg0_FFD4_MC.D1/IN2 \ 0 19721 (_entity .  X_INV)
		(_port
			((I) (\U1/U1/CurrState_Sreg0_FFD2 \))
			((O) (\NlwInverterSignal_U1/U1/CurrState_Sreg0_FFD4_MC.D1/IN2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/U1/CurrState_Sreg0_FFD4_MC.D1/IN3 \ 0 19725 (_entity .  X_INV)
		(_port
			((I) (\U1/U1/CurrState_Sreg0_FFD4 \))
			((O) (\NlwInverterSignal_U1/U1/CurrState_Sreg0_FFD4_MC.D1/IN3 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/U1/CurrState_Sreg0_FFD4_MC.D1/IN4 \ 0 19729 (_entity .  X_INV)
		(_port
			((I) (\U1/U1/CurrState_Sreg0_FFD1 \))
			((O) (\NlwInverterSignal_U1/U1/CurrState_Sreg0_FFD4_MC.D1/IN4 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/U1/CurrState_Sreg0_FFD4_MC.D1/IN5 \ 0 19733 (_entity .  X_INV)
		(_port
			((I) (\PhaseA_Encoder0_II/UIM \))
			((O) (\NlwInverterSignal_U1/U1/CurrState_Sreg0_FFD4_MC.D1/IN5 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/U1/CurrState_Sreg0_FFD4_MC.D1/IN6 \ 0 19737 (_entity .  X_INV)
		(_port
			((I) (\PhaseB_Encoder0_II/UIM \))
			((O) (\NlwInverterSignal_U1/U1/CurrState_Sreg0_FFD4_MC.D1/IN6 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/U1/CurrState_Sreg0_FFD1_MC.D2_PT_0/IN0 \ 0 19741 (_entity .  X_INV)
		(_port
			((I) (\Reset_II/UIM \))
			((O) (\NlwInverterSignal_U1/U1/CurrState_Sreg0_FFD1_MC.D2_PT_0/IN0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/U1/CurrState_Sreg0_FFD1_MC.D2_PT_0/IN2 \ 0 19745 (_entity .  X_INV)
		(_port
			((I) (\U1/U1/CurrState_Sreg0_FFD4 \))
			((O) (\NlwInverterSignal_U1/U1/CurrState_Sreg0_FFD1_MC.D2_PT_0/IN2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/U1/CurrState_Sreg0_FFD1_MC.D2_PT_1/IN0 \ 0 19749 (_entity .  X_INV)
		(_port
			((I) (\Reset_II/UIM \))
			((O) (\NlwInverterSignal_U1/U1/CurrState_Sreg0_FFD1_MC.D2_PT_1/IN0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/U1/CurrState_Sreg0_FFD1_MC.D2_PT_1/IN1 \ 0 19753 (_entity .  X_INV)
		(_port
			((I) (\U1/U1/CurrState_Sreg0_FFD3 \))
			((O) (\NlwInverterSignal_U1/U1/CurrState_Sreg0_FFD1_MC.D2_PT_1/IN1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/U1/CurrState_Sreg0_FFD1_MC.D2_PT_1/IN2 \ 0 19757 (_entity .  X_INV)
		(_port
			((I) (\U1/U1/CurrState_Sreg0_FFD4 \))
			((O) (\NlwInverterSignal_U1/U1/CurrState_Sreg0_FFD1_MC.D2_PT_1/IN2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/U1/CurrState_Sreg0_FFD1_MC.D2_PT_2/IN0 \ 0 19761 (_entity .  X_INV)
		(_port
			((I) (\Reset_II/UIM \))
			((O) (\NlwInverterSignal_U1/U1/CurrState_Sreg0_FFD1_MC.D2_PT_2/IN0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/U1/CurrState_Sreg0_FFD1_MC.D2_PT_2/IN1 \ 0 19765 (_entity .  X_INV)
		(_port
			((I) (\U1/U1/CurrState_Sreg0_FFD3 \))
			((O) (\NlwInverterSignal_U1/U1/CurrState_Sreg0_FFD1_MC.D2_PT_2/IN1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/U1/CurrState_Sreg0_FFD1_MC.D2_PT_2/IN2 \ 0 19769 (_entity .  X_INV)
		(_port
			((I) (\U1/U1/CurrState_Sreg0_FFD2 \))
			((O) (\NlwInverterSignal_U1/U1/CurrState_Sreg0_FFD1_MC.D2_PT_2/IN2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/U1/CurrState_Sreg0_FFD1_MC.D2_PT_2/IN3 \ 0 19773 (_entity .  X_INV)
		(_port
			((I) (\U1/U1/CurrState_Sreg0_FFD4 \))
			((O) (\NlwInverterSignal_U1/U1/CurrState_Sreg0_FFD1_MC.D2_PT_2/IN3 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/U1/CurrState_Sreg0_FFD1_MC.D2_PT_2/IN4 \ 0 19777 (_entity .  X_INV)
		(_port
			((I) (\PhaseA_Encoder0_II/UIM \))
			((O) (\NlwInverterSignal_U1/U1/CurrState_Sreg0_FFD1_MC.D2_PT_2/IN4 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_N_PZ_1183_MC.D2_PT_0/IN1 \ 0 19781 (_entity .  X_INV)
		(_port
			((I) (\PhaseB_Encoder0_II/UIM \))
			((O) (\NlwInverterSignal_N_PZ_1183_MC.D2_PT_0/IN1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_N_PZ_1183_MC.D2_PT_1/IN0 \ 0 19785 (_entity .  X_INV)
		(_port
			((I) (\U1/U1/CurrState_Sreg0_FFD1 \))
			((O) (\NlwInverterSignal_N_PZ_1183_MC.D2_PT_1/IN0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/Channel0<1>_MC.D2_PT_0/IN0 \ 0 19789 (_entity .  X_INV)
		(_port
			((I) (N_PZ_949))
			((O) (\NlwInverterSignal_U1/Channel0<1>_MC.D2_PT_0/IN0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/Channel0<1>_MC.D2_PT_1/IN3 \ 0 19793 (_entity .  X_INV)
		(_port
			((I) (N_PZ_961))
			((O) (\NlwInverterSignal_U1/Channel0<1>_MC.D2_PT_1/IN3 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/Channel0<1>_MC.D2_PT_2/IN1 \ 0 19797 (_entity .  X_INV)
		(_port
			((I) (\U1/Channel0 \(0)))
			((O) (\NlwInverterSignal_U1/Channel0<1>_MC.D2_PT_2/IN1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_N_PZ_961_MC.D2_PT_1/IN0 \ 0 19801 (_entity .  X_INV)
		(_port
			((I) (\U1/U1/CurrState_Sreg0_FFD4 \))
			((O) (\NlwInverterSignal_N_PZ_961_MC.D2_PT_1/IN0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_N_PZ_961_MC.D2_PT_1/IN1 \ 0 19805 (_entity .  X_INV)
		(_port
			((I) (\U1/NET3721 \))
			((O) (\NlwInverterSignal_N_PZ_961_MC.D2_PT_1/IN1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/NET3721_MC.D2_PT_1/IN0 \ 0 19809 (_entity .  X_INV)
		(_port
			((I) (\WR_II/UIM \))
			((O) (\NlwInverterSignal_U1/NET3721_MC.D2_PT_1/IN0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/NET3721_MC.D2_PT_1/IN5 \ 0 19813 (_entity .  X_INV)
		(_port
			((I) (U2_ADDR_reg(2)))
			((O) (\NlwInverterSignal_U1/NET3721_MC.D2_PT_1/IN5 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/NET3721_MC.D2_PT_1/IN6 \ 0 19817 (_entity .  X_INV)
		(_port
			((I) (U2_ADDR_reg(3)))
			((O) (\NlwInverterSignal_U1/NET3721_MC.D2_PT_1/IN6 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/NET3721_MC.D2_PT_1/IN7 \ 0 19821 (_entity .  X_INV)
		(_port
			((I) (\AD<3>_II/UIM \))
			((O) (\NlwInverterSignal_U1/NET3721_MC.D2_PT_1/IN7 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/NET3721_MC.D2_PT_2/IN0 \ 0 19825 (_entity .  X_INV)
		(_port
			((I) (\WR_II/UIM \))
			((O) (\NlwInverterSignal_U1/NET3721_MC.D2_PT_2/IN0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/NET3721_MC.D2_PT_2/IN5 \ 0 19829 (_entity .  X_INV)
		(_port
			((I) (U2_ADDR_reg(2)))
			((O) (\NlwInverterSignal_U1/NET3721_MC.D2_PT_2/IN5 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/NET3721_MC.D2_PT_2/IN6 \ 0 19833 (_entity .  X_INV)
		(_port
			((I) (U2_ADDR_reg(3)))
			((O) (\NlwInverterSignal_U1/NET3721_MC.D2_PT_2/IN6 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/NET3721_MC.D2_PT_2/IN7 \ 0 19837 (_entity .  X_INV)
		(_port
			((I) (\Reset_II/UIM \))
			((O) (\NlwInverterSignal_U1/NET3721_MC.D2_PT_2/IN7 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/NET3721_MC.D2_PT_2/IN9 \ 0 19841 (_entity .  X_INV)
		(_port
			((I) (\U1/NET3721 \))
			((O) (\NlwInverterSignal_U1/NET3721_MC.D2_PT_2/IN9 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/Channel0<2>_MC.D2_PT_0/IN0 \ 0 19845 (_entity .  X_INV)
		(_port
			((I) (N_PZ_949))
			((O) (\NlwInverterSignal_U1/Channel0<2>_MC.D2_PT_0/IN0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/Channel0<2>_MC.D2_PT_1/IN4 \ 0 19849 (_entity .  X_INV)
		(_port
			((I) (N_PZ_961))
			((O) (\NlwInverterSignal_U1/Channel0<2>_MC.D2_PT_1/IN4 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/Channel0<2>_MC.D2_PT_2/IN1 \ 0 19853 (_entity .  X_INV)
		(_port
			((I) (\U1/Channel0 \(0)))
			((O) (\NlwInverterSignal_U1/Channel0<2>_MC.D2_PT_2/IN1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/Channel0<2>_MC.D2_PT_2/IN3 \ 0 19857 (_entity .  X_INV)
		(_port
			((I) (\U1/Channel0 \(1)))
			((O) (\NlwInverterSignal_U1/Channel0<2>_MC.D2_PT_2/IN3 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/Channel0<3>_MC.D2_PT_0/IN0 \ 0 19861 (_entity .  X_INV)
		(_port
			((I) (N_PZ_949))
			((O) (\NlwInverterSignal_U1/Channel0<3>_MC.D2_PT_0/IN0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/Channel0<3>_MC.D2_PT_1/IN4 \ 0 19865 (_entity .  X_INV)
		(_port
			((I) (N_PZ_961))
			((O) (\NlwInverterSignal_U1/Channel0<3>_MC.D2_PT_1/IN4 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/Channel0<3>_MC.D2_PT_2/IN1 \ 0 19869 (_entity .  X_INV)
		(_port
			((I) (\U1/Channel0 \(0)))
			((O) (\NlwInverterSignal_U1/Channel0<3>_MC.D2_PT_2/IN1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/Channel0<3>_MC.D2_PT_2/IN3 \ 0 19873 (_entity .  X_INV)
		(_port
			((I) (\U1/Channel0 \(1)))
			((O) (\NlwInverterSignal_U1/Channel0<3>_MC.D2_PT_2/IN3 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/Channel0<3>_MC.D2_PT_2/IN5 \ 0 19877 (_entity .  X_INV)
		(_port
			((I) (\U1/Channel0 \(2)))
			((O) (\NlwInverterSignal_U1/Channel0<3>_MC.D2_PT_2/IN5 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/Channel0<4>_MC.D2_PT_0/IN0 \ 0 19881 (_entity .  X_INV)
		(_port
			((I) (N_PZ_949))
			((O) (\NlwInverterSignal_U1/Channel0<4>_MC.D2_PT_0/IN0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/Channel0<4>_MC.D2_PT_1/IN4 \ 0 19885 (_entity .  X_INV)
		(_port
			((I) (N_PZ_961))
			((O) (\NlwInverterSignal_U1/Channel0<4>_MC.D2_PT_1/IN4 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/Channel0<4>_MC.D2_PT_2/IN1 \ 0 19889 (_entity .  X_INV)
		(_port
			((I) (\U1/Channel0 \(0)))
			((O) (\NlwInverterSignal_U1/Channel0<4>_MC.D2_PT_2/IN1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/Channel0<4>_MC.D2_PT_2/IN3 \ 0 19893 (_entity .  X_INV)
		(_port
			((I) (\U1/Channel0 \(1)))
			((O) (\NlwInverterSignal_U1/Channel0<4>_MC.D2_PT_2/IN3 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/Channel0<4>_MC.D2_PT_2/IN5 \ 0 19897 (_entity .  X_INV)
		(_port
			((I) (\U1/Channel0 \(2)))
			((O) (\NlwInverterSignal_U1/Channel0<4>_MC.D2_PT_2/IN5 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/Channel0<4>_MC.D2_PT_2/IN6 \ 0 19901 (_entity .  X_INV)
		(_port
			((I) (\U1/Channel0 \(3)))
			((O) (\NlwInverterSignal_U1/Channel0<4>_MC.D2_PT_2/IN6 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/Channel1<5>_MC.D2_PT_0/IN1 \ 0 19905 (_entity .  X_INV)
		(_port
			((I) (N_PZ_948))
			((O) (\NlwInverterSignal_U1/Channel1<5>_MC.D2_PT_0/IN1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/Channel1<5>_MC.D2_PT_1/IN2 \ 0 19909 (_entity .  X_INV)
		(_port
			((I) (N_PZ_993))
			((O) (\NlwInverterSignal_U1/Channel1<5>_MC.D2_PT_1/IN2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/Channel1<5>_MC.D2_PT_2/IN3 \ 0 19913 (_entity .  X_INV)
		(_port
			((I) (\U1/Channel1 \(0)))
			((O) (\NlwInverterSignal_U1/Channel1<5>_MC.D2_PT_2/IN3 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/Channel1<5>_MC.D2_PT_2/IN4 \ 0 19917 (_entity .  X_INV)
		(_port
			((I) (\U1/Channel1 \(1)))
			((O) (\NlwInverterSignal_U1/Channel1<5>_MC.D2_PT_2/IN4 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/Channel1<5>_MC.D2_PT_2/IN5 \ 0 19921 (_entity .  X_INV)
		(_port
			((I) (\U1/Channel1 \(2)))
			((O) (\NlwInverterSignal_U1/Channel1<5>_MC.D2_PT_2/IN5 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/Channel1<5>_MC.D2_PT_2/IN6 \ 0 19925 (_entity .  X_INV)
		(_port
			((I) (\U1/Channel1 \(3)))
			((O) (\NlwInverterSignal_U1/Channel1<5>_MC.D2_PT_2/IN6 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/Channel1<5>_MC.D2_PT_2/IN7 \ 0 19929 (_entity .  X_INV)
		(_port
			((I) (\U1/Channel1 \(4)))
			((O) (\NlwInverterSignal_U1/Channel1<5>_MC.D2_PT_2/IN7 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_N_PZ_948_MC.D1/IN0 \ 0 19933 (_entity .  X_INV)
		(_port
			((I) (\Reset_II/UIM \))
			((O) (\NlwInverterSignal_N_PZ_948_MC.D1/IN0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_N_PZ_948_MC.D1/IN1 \ 0 19937 (_entity .  X_INV)
		(_port
			((I) (\U1/Zero1 \))
			((O) (\NlwInverterSignal_N_PZ_948_MC.D1/IN1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/Zero1_MC.D2_PT_1/IN0 \ 0 19941 (_entity .  X_INV)
		(_port
			((I) (N_PZ_978))
			((O) (\NlwInverterSignal_U1/Zero1_MC.D2_PT_1/IN0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/Zero1_MC.D2_PT_1/IN1 \ 0 19945 (_entity .  X_INV)
		(_port
			((I) (NET2493))
			((O) (\NlwInverterSignal_U1/Zero1_MC.D2_PT_1/IN1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/Zero1_MC.D2_PT_1/IN5 \ 0 19949 (_entity .  X_INV)
		(_port
			((I) (\U1/U4/HE1statelastr \))
			((O) (\NlwInverterSignal_U1/Zero1_MC.D2_PT_1/IN5 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/Zero1_MC.D2_PT_2/IN0 \ 0 19953 (_entity .  X_INV)
		(_port
			((I) (N_PZ_978))
			((O) (\NlwInverterSignal_U1/Zero1_MC.D2_PT_2/IN0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/Zero1_MC.D2_PT_2/IN1 \ 0 19957 (_entity .  X_INV)
		(_port
			((I) (NET2493))
			((O) (\NlwInverterSignal_U1/Zero1_MC.D2_PT_2/IN1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/Zero1_MC.D2_PT_2/IN2 \ 0 19961 (_entity .  X_INV)
		(_port
			((I) (\U1/U4/RF1r \))
			((O) (\NlwInverterSignal_U1/Zero1_MC.D2_PT_2/IN2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/Zero1_MC.D2_PT_2/IN4 \ 0 19965 (_entity .  X_INV)
		(_port
			((I) (\U1/U4/HE1stater \))
			((O) (\NlwInverterSignal_U1/Zero1_MC.D2_PT_2/IN4 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_NET2493_MC.D2_PT_0/IN0 \ 0 19969 (_entity .  X_INV)
		(_port
			((I) (N_PZ_978))
			((O) (\NlwInverterSignal_NET2493_MC.D2_PT_0/IN0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_NET2493_MC.D2_PT_0/IN1 \ 0 19973 (_entity .  X_INV)
		(_port
			((I) (NET2493))
			((O) (\NlwInverterSignal_NET2493_MC.D2_PT_0/IN1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_NET2493_MC.D2_PT_0/IN5 \ 0 19977 (_entity .  X_INV)
		(_port
			((I) (\U1/U4/HE1statelastr \))
			((O) (\NlwInverterSignal_NET2493_MC.D2_PT_0/IN5 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_NET2493_MC.D2_PT_1/IN0 \ 0 19981 (_entity .  X_INV)
		(_port
			((I) (N_PZ_978))
			((O) (\NlwInverterSignal_NET2493_MC.D2_PT_1/IN0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_NET2493_MC.D2_PT_1/IN1 \ 0 19985 (_entity .  X_INV)
		(_port
			((I) (NET2493))
			((O) (\NlwInverterSignal_NET2493_MC.D2_PT_1/IN1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_NET2493_MC.D2_PT_1/IN2 \ 0 19989 (_entity .  X_INV)
		(_port
			((I) (\U1/U4/RF1r \))
			((O) (\NlwInverterSignal_NET2493_MC.D2_PT_1/IN2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_NET2493_MC.D2_PT_1/IN4 \ 0 19993 (_entity .  X_INV)
		(_port
			((I) (\U1/U4/HE1stater \))
			((O) (\NlwInverterSignal_NET2493_MC.D2_PT_1/IN4 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_NET2493_MC.D2_PT_2/IN0 \ 0 19997 (_entity .  X_INV)
		(_port
			((I) (\WR_II/UIM \))
			((O) (\NlwInverterSignal_NET2493_MC.D2_PT_2/IN0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_NET2493_MC.D2_PT_2/IN3 \ 0 20001 (_entity .  X_INV)
		(_port
			((I) (U2_ADDR_reg(0)))
			((O) (\NlwInverterSignal_NET2493_MC.D2_PT_2/IN3 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_NET2493_MC.D2_PT_2/IN5 \ 0 20005 (_entity .  X_INV)
		(_port
			((I) (U2_ADDR_reg(2)))
			((O) (\NlwInverterSignal_NET2493_MC.D2_PT_2/IN5 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_NET2493_MC.D2_PT_2/IN6 \ 0 20009 (_entity .  X_INV)
		(_port
			((I) (U2_ADDR_reg(3)))
			((O) (\NlwInverterSignal_NET2493_MC.D2_PT_2/IN6 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_NET2493_MC.D2_PT_2/IN7 \ 0 20013 (_entity .  X_INV)
		(_port
			((I) (\Reset_II/UIM \))
			((O) (\NlwInverterSignal_NET2493_MC.D2_PT_2/IN7 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_NET2493_MC.D2_PT_2/IN9 \ 0 20017 (_entity .  X_INV)
		(_port
			((I) (NET2493))
			((O) (\NlwInverterSignal_NET2493_MC.D2_PT_2/IN9 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_NET2493_MC.D2_PT_3/IN0 \ 0 20021 (_entity .  X_INV)
		(_port
			((I) (\WR_II/UIM \))
			((O) (\NlwInverterSignal_NET2493_MC.D2_PT_3/IN0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_NET2493_MC.D2_PT_3/IN3 \ 0 20025 (_entity .  X_INV)
		(_port
			((I) (U2_ADDR_reg(0)))
			((O) (\NlwInverterSignal_NET2493_MC.D2_PT_3/IN3 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_NET2493_MC.D2_PT_3/IN5 \ 0 20029 (_entity .  X_INV)
		(_port
			((I) (U2_ADDR_reg(2)))
			((O) (\NlwInverterSignal_NET2493_MC.D2_PT_3/IN5 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_NET2493_MC.D2_PT_3/IN6 \ 0 20033 (_entity .  X_INV)
		(_port
			((I) (U2_ADDR_reg(3)))
			((O) (\NlwInverterSignal_NET2493_MC.D2_PT_3/IN6 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_NET2493_MC.D2_PT_3/IN7 \ 0 20037 (_entity .  X_INV)
		(_port
			((I) (\Reset_II/UIM \))
			((O) (\NlwInverterSignal_NET2493_MC.D2_PT_3/IN7 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_NET2493_MC.D2_PT_3/IN8 \ 0 20041 (_entity .  X_INV)
		(_port
			((I) (\AD<3>_II/UIM \))
			((O) (\NlwInverterSignal_NET2493_MC.D2_PT_3/IN8 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/U4/RF1r_MC.D2_PT_1/IN0 \ 0 20045 (_entity .  X_INV)
		(_port
			((I) (\WR_II/UIM \))
			((O) (\NlwInverterSignal_U1/U4/RF1r_MC.D2_PT_1/IN0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/U4/RF1r_MC.D2_PT_1/IN5 \ 0 20049 (_entity .  X_INV)
		(_port
			((I) (U2_ADDR_reg(2)))
			((O) (\NlwInverterSignal_U1/U4/RF1r_MC.D2_PT_1/IN5 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/U4/RF1r_MC.D2_PT_1/IN6 \ 0 20053 (_entity .  X_INV)
		(_port
			((I) (U2_ADDR_reg(3)))
			((O) (\NlwInverterSignal_U1/U4/RF1r_MC.D2_PT_1/IN6 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/U4/RF1r_MC.D2_PT_1/IN7 \ 0 20057 (_entity .  X_INV)
		(_port
			((I) (\AD<4>_II/UIM \))
			((O) (\NlwInverterSignal_U1/U4/RF1r_MC.D2_PT_1/IN7 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/U4/RF1r_MC.D2_PT_2/IN0 \ 0 20061 (_entity .  X_INV)
		(_port
			((I) (\WR_II/UIM \))
			((O) (\NlwInverterSignal_U1/U4/RF1r_MC.D2_PT_2/IN0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/U4/RF1r_MC.D2_PT_2/IN5 \ 0 20065 (_entity .  X_INV)
		(_port
			((I) (U2_ADDR_reg(2)))
			((O) (\NlwInverterSignal_U1/U4/RF1r_MC.D2_PT_2/IN5 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/U4/RF1r_MC.D2_PT_2/IN6 \ 0 20069 (_entity .  X_INV)
		(_port
			((I) (U2_ADDR_reg(3)))
			((O) (\NlwInverterSignal_U1/U4/RF1r_MC.D2_PT_2/IN6 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/U4/RF1r_MC.D2_PT_2/IN7 \ 0 20073 (_entity .  X_INV)
		(_port
			((I) (\Reset_II/UIM \))
			((O) (\NlwInverterSignal_U1/U4/RF1r_MC.D2_PT_2/IN7 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/U4/RF1r_MC.D2_PT_2/IN9 \ 0 20077 (_entity .  X_INV)
		(_port
			((I) (\U1/U4/RF1r \))
			((O) (\NlwInverterSignal_U1/U4/RF1r_MC.D2_PT_2/IN9 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/U4/E1r_MC.D2_PT_1/IN0 \ 0 20081 (_entity .  X_INV)
		(_port
			((I) (\WR_II/UIM \))
			((O) (\NlwInverterSignal_U1/U4/E1r_MC.D2_PT_1/IN0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/U4/E1r_MC.D2_PT_1/IN5 \ 0 20085 (_entity .  X_INV)
		(_port
			((I) (U2_ADDR_reg(2)))
			((O) (\NlwInverterSignal_U1/U4/E1r_MC.D2_PT_1/IN5 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/U4/E1r_MC.D2_PT_1/IN6 \ 0 20089 (_entity .  X_INV)
		(_port
			((I) (U2_ADDR_reg(3)))
			((O) (\NlwInverterSignal_U1/U4/E1r_MC.D2_PT_1/IN6 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/U4/E1r_MC.D2_PT_1/IN7 \ 0 20093 (_entity .  X_INV)
		(_port
			((I) (\AD<5>_II/UIM \))
			((O) (\NlwInverterSignal_U1/U4/E1r_MC.D2_PT_1/IN7 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/U4/E1r_MC.D2_PT_2/IN0 \ 0 20097 (_entity .  X_INV)
		(_port
			((I) (\WR_II/UIM \))
			((O) (\NlwInverterSignal_U1/U4/E1r_MC.D2_PT_2/IN0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/U4/E1r_MC.D2_PT_2/IN5 \ 0 20101 (_entity .  X_INV)
		(_port
			((I) (U2_ADDR_reg(2)))
			((O) (\NlwInverterSignal_U1/U4/E1r_MC.D2_PT_2/IN5 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/U4/E1r_MC.D2_PT_2/IN6 \ 0 20105 (_entity .  X_INV)
		(_port
			((I) (U2_ADDR_reg(3)))
			((O) (\NlwInverterSignal_U1/U4/E1r_MC.D2_PT_2/IN6 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/U4/E1r_MC.D2_PT_2/IN7 \ 0 20109 (_entity .  X_INV)
		(_port
			((I) (\Reset_II/UIM \))
			((O) (\NlwInverterSignal_U1/U4/E1r_MC.D2_PT_2/IN7 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/U4/E1r_MC.D2_PT_2/IN9 \ 0 20113 (_entity .  X_INV)
		(_port
			((I) (\U1/U4/E1r \))
			((O) (\NlwInverterSignal_U1/U4/E1r_MC.D2_PT_2/IN9 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/Channel1<0>_MC.D2_PT_0/IN2 \ 0 20117 (_entity .  X_INV)
		(_port
			((I) (\U1/Channel1 \(0)))
			((O) (\NlwInverterSignal_U1/Channel1<0>_MC.D2_PT_0/IN2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/Channel1<0>_MC.D2_PT_1/IN1 \ 0 20121 (_entity .  X_INV)
		(_port
			((I) (N_PZ_1082))
			((O) (\NlwInverterSignal_U1/Channel1<0>_MC.D2_PT_1/IN1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_N_PZ_1082_MC.D2_PT_0/IN1 \ 0 20125 (_entity .  X_INV)
		(_port
			((I) (\U1/U6/CurrState_Sreg0_FFD2 \))
			((O) (\NlwInverterSignal_N_PZ_1082_MC.D2_PT_0/IN1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_N_PZ_1082_MC.D2_PT_0/IN3 \ 0 20129 (_entity .  X_INV)
		(_port
			((I) (\U1/U6/CurrState_Sreg0_FFD1 \))
			((O) (\NlwInverterSignal_N_PZ_1082_MC.D2_PT_0/IN3 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_N_PZ_1082_MC.D2_PT_1/IN1 \ 0 20133 (_entity .  X_INV)
		(_port
			((I) (\U1/U6/CurrState_Sreg0_FFD2 \))
			((O) (\NlwInverterSignal_N_PZ_1082_MC.D2_PT_1/IN1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_N_PZ_1082_MC.D2_PT_1/IN2 \ 0 20137 (_entity .  X_INV)
		(_port
			((I) (\U1/U6/CurrState_Sreg0_FFD4 \))
			((O) (\NlwInverterSignal_N_PZ_1082_MC.D2_PT_1/IN2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/U6/CurrState_Sreg0_FFD3_MC.D2_PT_0/IN0 \ 0 20141 (_entity .  X_INV)
		(_port
			((I) (\Reset_II/UIM \))
			((O) (\NlwInverterSignal_U1/U6/CurrState_Sreg0_FFD3_MC.D2_PT_0/IN0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/U6/CurrState_Sreg0_FFD3_MC.D2_PT_0/IN3 \ 0 20145 (_entity .  X_INV)
		(_port
			((I) (\U1/U6/CurrState_Sreg0_FFD4 \))
			((O) (\NlwInverterSignal_U1/U6/CurrState_Sreg0_FFD3_MC.D2_PT_0/IN3 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/U6/CurrState_Sreg0_FFD3_MC.D2_PT_0/IN4 \ 0 20149 (_entity .  X_INV)
		(_port
			((I) (\PhaseA_Encoder1_II/UIM \))
			((O) (\NlwInverterSignal_U1/U6/CurrState_Sreg0_FFD3_MC.D2_PT_0/IN4 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/U6/CurrState_Sreg0_FFD3_MC.D2_PT_1/IN0 \ 0 20153 (_entity .  X_INV)
		(_port
			((I) (\Reset_II/UIM \))
			((O) (\NlwInverterSignal_U1/U6/CurrState_Sreg0_FFD3_MC.D2_PT_1/IN0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/U6/CurrState_Sreg0_FFD3_MC.D2_PT_1/IN2 \ 0 20157 (_entity .  X_INV)
		(_port
			((I) (\U1/U6/CurrState_Sreg0_FFD2 \))
			((O) (\NlwInverterSignal_U1/U6/CurrState_Sreg0_FFD3_MC.D2_PT_1/IN2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/U6/CurrState_Sreg0_FFD3_MC.D2_PT_1/IN3 \ 0 20161 (_entity .  X_INV)
		(_port
			((I) (\U1/U6/CurrState_Sreg0_FFD4 \))
			((O) (\NlwInverterSignal_U1/U6/CurrState_Sreg0_FFD3_MC.D2_PT_1/IN3 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/U6/CurrState_Sreg0_FFD3_MC.D2_PT_1/IN4 \ 0 20165 (_entity .  X_INV)
		(_port
			((I) (\U1/U6/CurrState_Sreg0_FFD1 \))
			((O) (\NlwInverterSignal_U1/U6/CurrState_Sreg0_FFD3_MC.D2_PT_1/IN4 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/U6/CurrState_Sreg0_FFD3_MC.D2_PT_2/IN0 \ 0 20169 (_entity .  X_INV)
		(_port
			((I) (\Reset_II/UIM \))
			((O) (\NlwInverterSignal_U1/U6/CurrState_Sreg0_FFD3_MC.D2_PT_2/IN0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/U6/CurrState_Sreg0_FFD3_MC.D2_PT_2/IN2 \ 0 20173 (_entity .  X_INV)
		(_port
			((I) (\U1/U6/CurrState_Sreg0_FFD4 \))
			((O) (\NlwInverterSignal_U1/U6/CurrState_Sreg0_FFD3_MC.D2_PT_2/IN2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/U6/CurrState_Sreg0_FFD2_MC.D2_PT_0/IN0 \ 0 20177 (_entity .  X_INV)
		(_port
			((I) (\Reset_II/UIM \))
			((O) (\NlwInverterSignal_U1/U6/CurrState_Sreg0_FFD2_MC.D2_PT_0/IN0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/U6/CurrState_Sreg0_FFD2_MC.D2_PT_0/IN3 \ 0 20181 (_entity .  X_INV)
		(_port
			((I) (\U1/U6/CurrState_Sreg0_FFD4 \))
			((O) (\NlwInverterSignal_U1/U6/CurrState_Sreg0_FFD2_MC.D2_PT_0/IN3 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/U6/CurrState_Sreg0_FFD2_MC.D2_PT_0/IN4 \ 0 20185 (_entity .  X_INV)
		(_port
			((I) (N_PZ_1184))
			((O) (\NlwInverterSignal_U1/U6/CurrState_Sreg0_FFD2_MC.D2_PT_0/IN4 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/U6/CurrState_Sreg0_FFD2_MC.D2_PT_1/IN0 \ 0 20189 (_entity .  X_INV)
		(_port
			((I) (\Reset_II/UIM \))
			((O) (\NlwInverterSignal_U1/U6/CurrState_Sreg0_FFD2_MC.D2_PT_1/IN0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/U6/CurrState_Sreg0_FFD2_MC.D2_PT_1/IN1 \ 0 20193 (_entity .  X_INV)
		(_port
			((I) (\U1/U6/CurrState_Sreg0_FFD3 \))
			((O) (\NlwInverterSignal_U1/U6/CurrState_Sreg0_FFD2_MC.D2_PT_1/IN1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/U6/CurrState_Sreg0_FFD2_MC.D2_PT_1/IN3 \ 0 20197 (_entity .  X_INV)
		(_port
			((I) (\U1/U6/CurrState_Sreg0_FFD4 \))
			((O) (\NlwInverterSignal_U1/U6/CurrState_Sreg0_FFD2_MC.D2_PT_1/IN3 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/U6/CurrState_Sreg0_FFD2_MC.D2_PT_2/IN0 \ 0 20201 (_entity .  X_INV)
		(_port
			((I) (\Reset_II/UIM \))
			((O) (\NlwInverterSignal_U1/U6/CurrState_Sreg0_FFD2_MC.D2_PT_2/IN0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/U6/CurrState_Sreg0_FFD2_MC.D2_PT_2/IN1 \ 0 20205 (_entity .  X_INV)
		(_port
			((I) (\U1/U6/CurrState_Sreg0_FFD3 \))
			((O) (\NlwInverterSignal_U1/U6/CurrState_Sreg0_FFD2_MC.D2_PT_2/IN1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/U6/CurrState_Sreg0_FFD2_MC.D2_PT_2/IN2 \ 0 20209 (_entity .  X_INV)
		(_port
			((I) (\U1/U6/CurrState_Sreg0_FFD4 \))
			((O) (\NlwInverterSignal_U1/U6/CurrState_Sreg0_FFD2_MC.D2_PT_2/IN2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/U6/CurrState_Sreg0_FFD2_MC.D2_PT_2/IN4 \ 0 20213 (_entity .  X_INV)
		(_port
			((I) (N_PZ_1184))
			((O) (\NlwInverterSignal_U1/U6/CurrState_Sreg0_FFD2_MC.D2_PT_2/IN4 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/U6/CurrState_Sreg0_FFD2_MC.D2_PT_3/IN0 \ 0 20217 (_entity .  X_INV)
		(_port
			((I) (\Reset_II/UIM \))
			((O) (\NlwInverterSignal_U1/U6/CurrState_Sreg0_FFD2_MC.D2_PT_3/IN0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/U6/CurrState_Sreg0_FFD2_MC.D2_PT_3/IN1 \ 0 20221 (_entity .  X_INV)
		(_port
			((I) (N_PZ_1082))
			((O) (\NlwInverterSignal_U1/U6/CurrState_Sreg0_FFD2_MC.D2_PT_3/IN1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/U6/CurrState_Sreg0_FFD2_MC.D2_PT_3/IN3 \ 0 20225 (_entity .  X_INV)
		(_port
			((I) (\U1/U6/CurrState_Sreg0_FFD4 \))
			((O) (\NlwInverterSignal_U1/U6/CurrState_Sreg0_FFD2_MC.D2_PT_3/IN3 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/U6/CurrState_Sreg0_FFD4_MC.D1/IN0 \ 0 20229 (_entity .  X_INV)
		(_port
			((I) (\Reset_II/UIM \))
			((O) (\NlwInverterSignal_U1/U6/CurrState_Sreg0_FFD4_MC.D1/IN0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/U6/CurrState_Sreg0_FFD4_MC.D1/IN2 \ 0 20233 (_entity .  X_INV)
		(_port
			((I) (\U1/U6/CurrState_Sreg0_FFD2 \))
			((O) (\NlwInverterSignal_U1/U6/CurrState_Sreg0_FFD4_MC.D1/IN2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/U6/CurrState_Sreg0_FFD4_MC.D1/IN3 \ 0 20237 (_entity .  X_INV)
		(_port
			((I) (\U1/U6/CurrState_Sreg0_FFD4 \))
			((O) (\NlwInverterSignal_U1/U6/CurrState_Sreg0_FFD4_MC.D1/IN3 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/U6/CurrState_Sreg0_FFD4_MC.D1/IN4 \ 0 20241 (_entity .  X_INV)
		(_port
			((I) (\U1/U6/CurrState_Sreg0_FFD1 \))
			((O) (\NlwInverterSignal_U1/U6/CurrState_Sreg0_FFD4_MC.D1/IN4 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/U6/CurrState_Sreg0_FFD4_MC.D1/IN5 \ 0 20245 (_entity .  X_INV)
		(_port
			((I) (\PhaseA_Encoder1_II/UIM \))
			((O) (\NlwInverterSignal_U1/U6/CurrState_Sreg0_FFD4_MC.D1/IN5 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/U6/CurrState_Sreg0_FFD4_MC.D1/IN6 \ 0 20249 (_entity .  X_INV)
		(_port
			((I) (\PhaseB_Encoder1_II/UIM \))
			((O) (\NlwInverterSignal_U1/U6/CurrState_Sreg0_FFD4_MC.D1/IN6 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/U6/CurrState_Sreg0_FFD1_MC.D2_PT_0/IN0 \ 0 20253 (_entity .  X_INV)
		(_port
			((I) (\Reset_II/UIM \))
			((O) (\NlwInverterSignal_U1/U6/CurrState_Sreg0_FFD1_MC.D2_PT_0/IN0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/U6/CurrState_Sreg0_FFD1_MC.D2_PT_0/IN2 \ 0 20257 (_entity .  X_INV)
		(_port
			((I) (\U1/U6/CurrState_Sreg0_FFD4 \))
			((O) (\NlwInverterSignal_U1/U6/CurrState_Sreg0_FFD1_MC.D2_PT_0/IN2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/U6/CurrState_Sreg0_FFD1_MC.D2_PT_1/IN0 \ 0 20261 (_entity .  X_INV)
		(_port
			((I) (\Reset_II/UIM \))
			((O) (\NlwInverterSignal_U1/U6/CurrState_Sreg0_FFD1_MC.D2_PT_1/IN0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/U6/CurrState_Sreg0_FFD1_MC.D2_PT_1/IN1 \ 0 20265 (_entity .  X_INV)
		(_port
			((I) (\U1/U6/CurrState_Sreg0_FFD3 \))
			((O) (\NlwInverterSignal_U1/U6/CurrState_Sreg0_FFD1_MC.D2_PT_1/IN1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/U6/CurrState_Sreg0_FFD1_MC.D2_PT_1/IN2 \ 0 20269 (_entity .  X_INV)
		(_port
			((I) (\U1/U6/CurrState_Sreg0_FFD4 \))
			((O) (\NlwInverterSignal_U1/U6/CurrState_Sreg0_FFD1_MC.D2_PT_1/IN2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/U6/CurrState_Sreg0_FFD1_MC.D2_PT_2/IN0 \ 0 20273 (_entity .  X_INV)
		(_port
			((I) (\Reset_II/UIM \))
			((O) (\NlwInverterSignal_U1/U6/CurrState_Sreg0_FFD1_MC.D2_PT_2/IN0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/U6/CurrState_Sreg0_FFD1_MC.D2_PT_2/IN1 \ 0 20277 (_entity .  X_INV)
		(_port
			((I) (\U1/U6/CurrState_Sreg0_FFD3 \))
			((O) (\NlwInverterSignal_U1/U6/CurrState_Sreg0_FFD1_MC.D2_PT_2/IN1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/U6/CurrState_Sreg0_FFD1_MC.D2_PT_2/IN2 \ 0 20281 (_entity .  X_INV)
		(_port
			((I) (\U1/U6/CurrState_Sreg0_FFD2 \))
			((O) (\NlwInverterSignal_U1/U6/CurrState_Sreg0_FFD1_MC.D2_PT_2/IN2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/U6/CurrState_Sreg0_FFD1_MC.D2_PT_2/IN3 \ 0 20285 (_entity .  X_INV)
		(_port
			((I) (\U1/U6/CurrState_Sreg0_FFD4 \))
			((O) (\NlwInverterSignal_U1/U6/CurrState_Sreg0_FFD1_MC.D2_PT_2/IN3 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/U6/CurrState_Sreg0_FFD1_MC.D2_PT_2/IN4 \ 0 20289 (_entity .  X_INV)
		(_port
			((I) (\PhaseA_Encoder1_II/UIM \))
			((O) (\NlwInverterSignal_U1/U6/CurrState_Sreg0_FFD1_MC.D2_PT_2/IN4 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_N_PZ_1184_MC.D2_PT_0/IN1 \ 0 20293 (_entity .  X_INV)
		(_port
			((I) (\PhaseB_Encoder1_II/UIM \))
			((O) (\NlwInverterSignal_N_PZ_1184_MC.D2_PT_0/IN1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_N_PZ_1184_MC.D2_PT_1/IN0 \ 0 20297 (_entity .  X_INV)
		(_port
			((I) (\U1/U6/CurrState_Sreg0_FFD1 \))
			((O) (\NlwInverterSignal_N_PZ_1184_MC.D2_PT_1/IN0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/Channel1<1>_MC.D2_PT_0/IN0 \ 0 20301 (_entity .  X_INV)
		(_port
			((I) (N_PZ_948))
			((O) (\NlwInverterSignal_U1/Channel1<1>_MC.D2_PT_0/IN0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/Channel1<1>_MC.D2_PT_1/IN3 \ 0 20305 (_entity .  X_INV)
		(_port
			((I) (\U1/Channel1 \(0)))
			((O) (\NlwInverterSignal_U1/Channel1<1>_MC.D2_PT_1/IN3 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/Channel1<1>_MC.D2_PT_2/IN2 \ 0 20309 (_entity .  X_INV)
		(_port
			((I) (N_PZ_993))
			((O) (\NlwInverterSignal_U1/Channel1<1>_MC.D2_PT_2/IN2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_N_PZ_993_MC.D2_PT_1/IN0 \ 0 20313 (_entity .  X_INV)
		(_port
			((I) (\U1/U6/CurrState_Sreg0_FFD4 \))
			((O) (\NlwInverterSignal_N_PZ_993_MC.D2_PT_1/IN0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_N_PZ_993_MC.D2_PT_1/IN1 \ 0 20317 (_entity .  X_INV)
		(_port
			((I) (\U1/NET3720 \))
			((O) (\NlwInverterSignal_N_PZ_993_MC.D2_PT_1/IN1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/NET3720_MC.D2_PT_1/IN0 \ 0 20321 (_entity .  X_INV)
		(_port
			((I) (\WR_II/UIM \))
			((O) (\NlwInverterSignal_U1/NET3720_MC.D2_PT_1/IN0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/NET3720_MC.D2_PT_1/IN5 \ 0 20325 (_entity .  X_INV)
		(_port
			((I) (U2_ADDR_reg(2)))
			((O) (\NlwInverterSignal_U1/NET3720_MC.D2_PT_1/IN5 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/NET3720_MC.D2_PT_1/IN6 \ 0 20329 (_entity .  X_INV)
		(_port
			((I) (U2_ADDR_reg(3)))
			((O) (\NlwInverterSignal_U1/NET3720_MC.D2_PT_1/IN6 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/NET3720_MC.D2_PT_1/IN7 \ 0 20333 (_entity .  X_INV)
		(_port
			((I) (\AD<7>_II/UIM \))
			((O) (\NlwInverterSignal_U1/NET3720_MC.D2_PT_1/IN7 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/NET3720_MC.D2_PT_2/IN0 \ 0 20337 (_entity .  X_INV)
		(_port
			((I) (\WR_II/UIM \))
			((O) (\NlwInverterSignal_U1/NET3720_MC.D2_PT_2/IN0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/NET3720_MC.D2_PT_2/IN5 \ 0 20341 (_entity .  X_INV)
		(_port
			((I) (U2_ADDR_reg(2)))
			((O) (\NlwInverterSignal_U1/NET3720_MC.D2_PT_2/IN5 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/NET3720_MC.D2_PT_2/IN6 \ 0 20345 (_entity .  X_INV)
		(_port
			((I) (U2_ADDR_reg(3)))
			((O) (\NlwInverterSignal_U1/NET3720_MC.D2_PT_2/IN6 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/NET3720_MC.D2_PT_2/IN7 \ 0 20349 (_entity .  X_INV)
		(_port
			((I) (\Reset_II/UIM \))
			((O) (\NlwInverterSignal_U1/NET3720_MC.D2_PT_2/IN7 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/NET3720_MC.D2_PT_2/IN9 \ 0 20353 (_entity .  X_INV)
		(_port
			((I) (\U1/NET3720 \))
			((O) (\NlwInverterSignal_U1/NET3720_MC.D2_PT_2/IN9 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/Channel1<2>_MC.D2_PT_0/IN0 \ 0 20357 (_entity .  X_INV)
		(_port
			((I) (N_PZ_948))
			((O) (\NlwInverterSignal_U1/Channel1<2>_MC.D2_PT_0/IN0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/Channel1<2>_MC.D2_PT_1/IN3 \ 0 20361 (_entity .  X_INV)
		(_port
			((I) (\U1/Channel1 \(0)))
			((O) (\NlwInverterSignal_U1/Channel1<2>_MC.D2_PT_1/IN3 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/Channel1<2>_MC.D2_PT_1/IN4 \ 0 20365 (_entity .  X_INV)
		(_port
			((I) (\U1/Channel1 \(1)))
			((O) (\NlwInverterSignal_U1/Channel1<2>_MC.D2_PT_1/IN4 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/Channel1<2>_MC.D2_PT_2/IN2 \ 0 20369 (_entity .  X_INV)
		(_port
			((I) (N_PZ_993))
			((O) (\NlwInverterSignal_U1/Channel1<2>_MC.D2_PT_2/IN2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/Channel1<3>_MC.D2_PT_0/IN0 \ 0 20373 (_entity .  X_INV)
		(_port
			((I) (N_PZ_948))
			((O) (\NlwInverterSignal_U1/Channel1<3>_MC.D2_PT_0/IN0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/Channel1<3>_MC.D2_PT_1/IN3 \ 0 20377 (_entity .  X_INV)
		(_port
			((I) (\U1/Channel1 \(0)))
			((O) (\NlwInverterSignal_U1/Channel1<3>_MC.D2_PT_1/IN3 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/Channel1<3>_MC.D2_PT_1/IN4 \ 0 20381 (_entity .  X_INV)
		(_port
			((I) (\U1/Channel1 \(1)))
			((O) (\NlwInverterSignal_U1/Channel1<3>_MC.D2_PT_1/IN4 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/Channel1<3>_MC.D2_PT_1/IN5 \ 0 20385 (_entity .  X_INV)
		(_port
			((I) (\U1/Channel1 \(2)))
			((O) (\NlwInverterSignal_U1/Channel1<3>_MC.D2_PT_1/IN5 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/Channel1<3>_MC.D2_PT_2/IN2 \ 0 20389 (_entity .  X_INV)
		(_port
			((I) (N_PZ_993))
			((O) (\NlwInverterSignal_U1/Channel1<3>_MC.D2_PT_2/IN2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/Channel1<4>_MC.D2_PT_0/IN0 \ 0 20393 (_entity .  X_INV)
		(_port
			((I) (N_PZ_948))
			((O) (\NlwInverterSignal_U1/Channel1<4>_MC.D2_PT_0/IN0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/Channel1<4>_MC.D2_PT_1/IN1 \ 0 20397 (_entity .  X_INV)
		(_port
			((I) (N_PZ_993))
			((O) (\NlwInverterSignal_U1/Channel1<4>_MC.D2_PT_1/IN1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/Channel1<4>_MC.D2_PT_2/IN3 \ 0 20401 (_entity .  X_INV)
		(_port
			((I) (\U1/Channel1 \(0)))
			((O) (\NlwInverterSignal_U1/Channel1<4>_MC.D2_PT_2/IN3 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/Channel1<4>_MC.D2_PT_2/IN4 \ 0 20405 (_entity .  X_INV)
		(_port
			((I) (\U1/Channel1 \(1)))
			((O) (\NlwInverterSignal_U1/Channel1<4>_MC.D2_PT_2/IN4 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/Channel1<4>_MC.D2_PT_2/IN5 \ 0 20409 (_entity .  X_INV)
		(_port
			((I) (\U1/Channel1 \(2)))
			((O) (\NlwInverterSignal_U1/Channel1<4>_MC.D2_PT_2/IN5 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/Channel1<4>_MC.D2_PT_2/IN6 \ 0 20413 (_entity .  X_INV)
		(_port
			((I) (\U1/Channel1 \(3)))
			((O) (\NlwInverterSignal_U1/Channel1<4>_MC.D2_PT_2/IN6 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/Channel1<4>_MC.D2_PT_3/IN2 \ 0 20417 (_entity .  X_INV)
		(_port
			((I) (N_PZ_993))
			((O) (\NlwInverterSignal_U1/Channel1<4>_MC.D2_PT_3/IN2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/Channel1<4>_MC.D2_PT_3/IN3 \ 0 20421 (_entity .  X_INV)
		(_port
			((I) (N_PZ_1226))
			((O) (\NlwInverterSignal_U1/Channel1<4>_MC.D2_PT_3/IN3 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/Channel1<4>_MC.D2_PT_3/IN8 \ 0 20425 (_entity .  X_INV)
		(_port
			((I) (\U1/Channel1 \(4)))
			((O) (\NlwInverterSignal_U1/Channel1<4>_MC.D2_PT_3/IN8 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_N_PZ_986_MC.D2_PT_0/IN0 \ 0 20429 (_entity .  X_INV)
		(_port
			((I) (U2_ADDR_reg(1)))
			((O) (\NlwInverterSignal_N_PZ_986_MC.D2_PT_0/IN0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_N_PZ_986_MC.D2_PT_0/IN1 \ 0 20433 (_entity .  X_INV)
		(_port
			((I) (\Reset_II/UIM \))
			((O) (\NlwInverterSignal_N_PZ_986_MC.D2_PT_0/IN1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_N_PZ_986_MC.D2_PT_0/IN2 \ 0 20437 (_entity .  X_INV)
		(_port
			((I) (\U1/U3/RDedge \))
			((O) (\NlwInverterSignal_N_PZ_986_MC.D2_PT_0/IN2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_N_PZ_986_MC.D2_PT_1/IN0 \ 0 20441 (_entity .  X_INV)
		(_port
			((I) (\Reset_II/UIM \))
			((O) (\NlwInverterSignal_N_PZ_986_MC.D2_PT_1/IN0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_N_PZ_986_MC.D2_PT_1/IN2 \ 0 20445 (_entity .  X_INV)
		(_port
			((I) (\U1/U3/RDedge \))
			((O) (\NlwInverterSignal_N_PZ_986_MC.D2_PT_1/IN2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_N_PZ_1002_MC.D2_PT_0/IN0 \ 0 20449 (_entity .  X_INV)
		(_port
			((I) (N_PZ_964))
			((O) (\NlwInverterSignal_N_PZ_1002_MC.D2_PT_0/IN0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_N_PZ_1002_MC.D2_PT_0/IN1 \ 0 20453 (_entity .  X_INV)
		(_port
			((I) (N_PZ_964))
			((O) (\NlwInverterSignal_N_PZ_1002_MC.D2_PT_0/IN1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_N_PZ_1002_MC.D2_PT_1/IN1 \ 0 20457 (_entity .  X_INV)
		(_port
			((I) (N_PZ_1061))
			((O) (\NlwInverterSignal_N_PZ_1002_MC.D2_PT_1/IN1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_N_PZ_1002_MC.D2_PT_2/IN1 \ 0 20461 (_entity .  X_INV)
		(_port
			((I) (U2_ADDR_reg(0)))
			((O) (\NlwInverterSignal_N_PZ_1002_MC.D2_PT_2/IN1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_N_PZ_1061_MC.D2_PT_0/IN0 \ 0 20465 (_entity .  X_INV)
		(_port
			((I) (U2_ADDR_reg(1)))
			((O) (\NlwInverterSignal_N_PZ_1061_MC.D2_PT_0/IN0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_N_PZ_1061_MC.D2_PT_0/IN4 \ 0 20469 (_entity .  X_INV)
		(_port
			((I) (U2_ADDR_reg(3)))
			((O) (\NlwInverterSignal_N_PZ_1061_MC.D2_PT_0/IN4 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_N_PZ_1061_MC.D2_PT_1/IN0 \ 0 20473 (_entity .  X_INV)
		(_port
			((I) (U2_ADDR_reg(1)))
			((O) (\NlwInverterSignal_N_PZ_1061_MC.D2_PT_1/IN0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_N_PZ_1061_MC.D2_PT_1/IN1 \ 0 20477 (_entity .  X_INV)
		(_port
			((I) (U2_ADDR_reg(0)))
			((O) (\NlwInverterSignal_N_PZ_1061_MC.D2_PT_1/IN1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_N_PZ_1061_MC.D2_PT_1/IN3 \ 0 20481 (_entity .  X_INV)
		(_port
			((I) (U2_ADDR_reg(2)))
			((O) (\NlwInverterSignal_N_PZ_1061_MC.D2_PT_1/IN3 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_N_PZ_964_MC.D2_PT_0/IN2 \ 0 20485 (_entity .  X_INV)
		(_port
			((I) (U2_ADDR_reg(3)))
			((O) (\NlwInverterSignal_N_PZ_964_MC.D2_PT_0/IN2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_N_PZ_964_MC.D2_PT_1/IN0 \ 0 20489 (_entity .  X_INV)
		(_port
			((I) (U2_ADDR_reg(1)))
			((O) (\NlwInverterSignal_N_PZ_964_MC.D2_PT_1/IN0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_N_PZ_964_MC.D2_PT_1/IN2 \ 0 20493 (_entity .  X_INV)
		(_port
			((I) (U2_ADDR_reg(2)))
			((O) (\NlwInverterSignal_N_PZ_964_MC.D2_PT_1/IN2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/U3/holdingreg<21>_MC.D2_PT_1/IN0 \ 0 20497 (_entity .  X_INV)
		(_port
			((I) (\Reset_II/UIM \))
			((O) (\NlwInverterSignal_U1/U3/holdingreg<21>_MC.D2_PT_1/IN0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/U3/holdingreg<21>_MC.D2_PT_2/IN1 \ 0 20501 (_entity .  X_INV)
		(_port
			((I) (\RD_II/UIM \))
			((O) (\NlwInverterSignal_U1/U3/holdingreg<21>_MC.D2_PT_2/IN1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/U3/holdingreg<21>_MC.D2_PT_2/IN6 \ 0 20505 (_entity .  X_INV)
		(_port
			((I) (U2_ADDR_reg(3)))
			((O) (\NlwInverterSignal_U1/U3/holdingreg<21>_MC.D2_PT_2/IN6 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/U3/holdingreg<21>_MC.D2_PT_2/IN7 \ 0 20509 (_entity .  X_INV)
		(_port
			((I) (\Reset_II/UIM \))
			((O) (\NlwInverterSignal_U1/U3/holdingreg<21>_MC.D2_PT_2/IN7 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/U3/holdingreg<21>_MC.D2_PT_2/IN8 \ 0 20513 (_entity .  X_INV)
		(_port
			((I) (\U1/U3/RDedge \))
			((O) (\NlwInverterSignal_U1/U3/holdingreg<21>_MC.D2_PT_2/IN8 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/Channel0<21>_MC.D2_PT_0/IN0 \ 0 20517 (_entity .  X_INV)
		(_port
			((I) (N_PZ_949))
			((O) (\NlwInverterSignal_U1/Channel0<21>_MC.D2_PT_0/IN0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/Channel0<21>_MC.D2_PT_1/IN3 \ 0 20521 (_entity .  X_INV)
		(_port
			((I) (\U1/Channel0 \(13)))
			((O) (\NlwInverterSignal_U1/Channel0<21>_MC.D2_PT_1/IN3 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/Channel0<21>_MC.D2_PT_1/IN5 \ 0 20525 (_entity .  X_INV)
		(_port
			((I) (\U1/Channel0 \(14)))
			((O) (\NlwInverterSignal_U1/Channel0<21>_MC.D2_PT_1/IN5 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/Channel0<21>_MC.D2_PT_1/IN6 \ 0 20529 (_entity .  X_INV)
		(_port
			((I) (\U1/Channel0 \(15)))
			((O) (\NlwInverterSignal_U1/Channel0<21>_MC.D2_PT_1/IN6 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/Channel0<21>_MC.D2_PT_1/IN7 \ 0 20533 (_entity .  X_INV)
		(_port
			((I) (\U1/Channel0 \(16)))
			((O) (\NlwInverterSignal_U1/Channel0<21>_MC.D2_PT_1/IN7 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/Channel0<21>_MC.D2_PT_1/IN8 \ 0 20537 (_entity .  X_INV)
		(_port
			((I) (\U1/Channel0 \(17)))
			((O) (\NlwInverterSignal_U1/Channel0<21>_MC.D2_PT_1/IN8 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/Channel0<21>_MC.D2_PT_1/IN9 \ 0 20541 (_entity .  X_INV)
		(_port
			((I) (\U1/Channel0 \(18)))
			((O) (\NlwInverterSignal_U1/Channel0<21>_MC.D2_PT_1/IN9 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/Channel0<21>_MC.D2_PT_1/IN10 \ 0 20545 (_entity .  X_INV)
		(_port
			((I) (\U1/Channel0 \(19)))
			((O) (\NlwInverterSignal_U1/Channel0<21>_MC.D2_PT_1/IN10 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/Channel0<21>_MC.D2_PT_1/IN11 \ 0 20549 (_entity .  X_INV)
		(_port
			((I) (\U1/Channel0 \(20)))
			((O) (\NlwInverterSignal_U1/Channel0<21>_MC.D2_PT_1/IN11 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/Channel0<21>_MC.D2_PT_2/IN2 \ 0 20553 (_entity .  X_INV)
		(_port
			((I) (N_PZ_961))
			((O) (\NlwInverterSignal_U1/Channel0<21>_MC.D2_PT_2/IN2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/Channel0<21>_MC.D2_PT_2/IN4 \ 0 20557 (_entity .  X_INV)
		(_port
			((I) (\U1/U2/location_Maddsub__n0000__n0115 \(0)))
			((O) (\NlwInverterSignal_U1/Channel0<21>_MC.D2_PT_2/IN4 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/Channel0<13>_MC.D2_PT_0/IN0 \ 0 20561 (_entity .  X_INV)
		(_port
			((I) (N_PZ_949))
			((O) (\NlwInverterSignal_U1/Channel0<13>_MC.D2_PT_0/IN0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/Channel0<13>_MC.D2_PT_2/IN2 \ 0 20565 (_entity .  X_INV)
		(_port
			((I) (N_PZ_961))
			((O) (\NlwInverterSignal_U1/Channel0<13>_MC.D2_PT_2/IN2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/Channel0<13>_MC.D2_PT_2/IN3 \ 0 20569 (_entity .  X_INV)
		(_port
			((I) (\U1/U2/location_Maddsub__n0000__n0115 \(0)))
			((O) (\NlwInverterSignal_U1/Channel0<13>_MC.D2_PT_2/IN3 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/U2/location_Maddsub__n0000__n0115<0>_MC.D2_PT_0/IN3 \ 0 20573 (_entity .  X_INV)
		(_port
			((I) (\U1/U2/location_Maddsub__n0000__n0103 \(0)))
			((O) (\NlwInverterSignal_U1/U2/location_Maddsub__n0000__n0115<0>_MC.D2_PT_0/IN3 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/U2/location_Maddsub__n0000__n0115<0>_MC.D2_PT_1/IN0 \ 0 20577 (_entity .  X_INV)
		(_port
			((I) (N_PZ_967))
			((O) (\NlwInverterSignal_U1/U2/location_Maddsub__n0000__n0115<0>_MC.D2_PT_1/IN0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/U2/location_Maddsub__n0000__n0115<0>_MC.D2_PT_1/IN1 \ 0 20581 (_entity .  X_INV)
		(_port
			((I) (\U1/Channel0 \(10)))
			((O) (\NlwInverterSignal_U1/U2/location_Maddsub__n0000__n0115<0>_MC.D2_PT_1/IN1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/U2/location_Maddsub__n0000__n0115<0>_MC.D2_PT_1/IN2 \ 0 20585 (_entity .  X_INV)
		(_port
			((I) (\U1/Channel0 \(7)))
			((O) (\NlwInverterSignal_U1/U2/location_Maddsub__n0000__n0115<0>_MC.D2_PT_1/IN2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/U2/location_Maddsub__n0000__n0115<0>_MC.D2_PT_1/IN4 \ 0 20589 (_entity .  X_INV)
		(_port
			((I) (\U1/Channel0 \(8)))
			((O) (\NlwInverterSignal_U1/U2/location_Maddsub__n0000__n0115<0>_MC.D2_PT_1/IN4 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/U2/location_Maddsub__n0000__n0115<0>_MC.D2_PT_1/IN5 \ 0 20593 (_entity .  X_INV)
		(_port
			((I) (\U1/Channel0 \(9)))
			((O) (\NlwInverterSignal_U1/U2/location_Maddsub__n0000__n0115<0>_MC.D2_PT_1/IN5 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/U2/location_Maddsub__n0000__n0115<0>_MC.D2_PT_1/IN6 \ 0 20597 (_entity .  X_INV)
		(_port
			((I) (\U1/Channel0 \(11)))
			((O) (\NlwInverterSignal_U1/U2/location_Maddsub__n0000__n0115<0>_MC.D2_PT_1/IN6 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/U2/location_Maddsub__n0000__n0115<0>_MC.D2_PT_1/IN7 \ 0 20601 (_entity .  X_INV)
		(_port
			((I) (\U1/Channel0 \(12)))
			((O) (\NlwInverterSignal_U1/U2/location_Maddsub__n0000__n0115<0>_MC.D2_PT_1/IN7 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_N_PZ_967_MC.D2_PT_1/IN2 \ 0 20605 (_entity .  X_INV)
		(_port
			((I) (\U1/U1/CurrState_Sreg0_FFD1 \))
			((O) (\NlwInverterSignal_N_PZ_967_MC.D2_PT_1/IN2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_N_PZ_967_MC.D2_PT_2/IN0 \ 0 20609 (_entity .  X_INV)
		(_port
			((I) (\U1/U1/CurrState_Sreg0_FFD3 \))
			((O) (\NlwInverterSignal_N_PZ_967_MC.D2_PT_2/IN0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_N_PZ_967_MC.D2_PT_2/IN1 \ 0 20613 (_entity .  X_INV)
		(_port
			((I) (\U1/U1/CurrState_Sreg0_FFD2 \))
			((O) (\NlwInverterSignal_N_PZ_967_MC.D2_PT_2/IN1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_N_PZ_967_MC.D2_PT_3/IN1 \ 0 20617 (_entity .  X_INV)
		(_port
			((I) (\U1/U1/CurrState_Sreg0_FFD2 \))
			((O) (\NlwInverterSignal_N_PZ_967_MC.D2_PT_3/IN1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_N_PZ_967_MC.D2_PT_3/IN2 \ 0 20621 (_entity .  X_INV)
		(_port
			((I) (\U1/U1/CurrState_Sreg0_FFD1 \))
			((O) (\NlwInverterSignal_N_PZ_967_MC.D2_PT_3/IN2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_N_PZ_967_MC.D2_PT_3/IN3 \ 0 20625 (_entity .  X_INV)
		(_port
			((I) (\U1/NET3721 \))
			((O) (\NlwInverterSignal_N_PZ_967_MC.D2_PT_3/IN3 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/Channel0<10>_MC.D/IN0 \ 0 20629 (_entity .  X_INV)
		(_port
			((I) (\U1/Channel0<10>_MC.D1 \))
			((O) (\NlwInverterSignal_U1/Channel0<10>_MC.D/IN0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/Channel0<10>_MC.D2_PT_0/IN0 \ 0 20633 (_entity .  X_INV)
		(_port
			((I) (N_PZ_949))
			((O) (\NlwInverterSignal_U1/Channel0<10>_MC.D2_PT_0/IN0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/Channel0<10>_MC.D2_PT_0/IN1 \ 0 20637 (_entity .  X_INV)
		(_port
			((I) (N_PZ_949))
			((O) (\NlwInverterSignal_U1/Channel0<10>_MC.D2_PT_0/IN1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/Channel0<10>_MC.D2_PT_1/IN0 \ 0 20641 (_entity .  X_INV)
		(_port
			((I) (\U1/Channel0 \(10)))
			((O) (\NlwInverterSignal_U1/Channel0<10>_MC.D2_PT_1/IN0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/Channel0<10>_MC.D2_PT_1/IN1 \ 0 20645 (_entity .  X_INV)
		(_port
			((I) (N_PZ_1317))
			((O) (\NlwInverterSignal_U1/Channel0<10>_MC.D2_PT_1/IN1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/Channel0<10>_MC.D2_PT_2/IN0 \ 0 20649 (_entity .  X_INV)
		(_port
			((I) (\U1/Channel0 \(10)))
			((O) (\NlwInverterSignal_U1/Channel0<10>_MC.D2_PT_2/IN0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/Channel0<10>_MC.D2_PT_2/IN1 \ 0 20653 (_entity .  X_INV)
		(_port
			((I) (\U1/Channel0 \(7)))
			((O) (\NlwInverterSignal_U1/Channel0<10>_MC.D2_PT_2/IN1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/Channel0<10>_MC.D2_PT_2/IN2 \ 0 20657 (_entity .  X_INV)
		(_port
			((I) (\U1/U2/location_Maddsub__n0000__n0103 \(0)))
			((O) (\NlwInverterSignal_U1/Channel0<10>_MC.D2_PT_2/IN2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/Channel0<10>_MC.D2_PT_3/IN1 \ 0 20661 (_entity .  X_INV)
		(_port
			((I) (N_PZ_961))
			((O) (\NlwInverterSignal_U1/Channel0<10>_MC.D2_PT_3/IN1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/Channel0<10>_MC.D2_PT_3/IN4 \ 0 20665 (_entity .  X_INV)
		(_port
			((I) (\U1/U2/location_Maddsub__n0000__n0103 \(0)))
			((O) (\NlwInverterSignal_U1/Channel0<10>_MC.D2_PT_3/IN4 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/Channel0<10>_MC.D2_PT_4/IN4 \ 0 20669 (_entity .  X_INV)
		(_port
			((I) (\U1/Channel0 \(7)))
			((O) (\NlwInverterSignal_U1/Channel0<10>_MC.D2_PT_4/IN4 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/Channel0<10>_MC.D2_PT_4/IN6 \ 0 20673 (_entity .  X_INV)
		(_port
			((I) (\U1/Channel0 \(8)))
			((O) (\NlwInverterSignal_U1/Channel0<10>_MC.D2_PT_4/IN6 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/Channel0<10>_MC.D2_PT_4/IN7 \ 0 20677 (_entity .  X_INV)
		(_port
			((I) (\U1/Channel0 \(9)))
			((O) (\NlwInverterSignal_U1/Channel0<10>_MC.D2_PT_4/IN7 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/Channel0<7>_MC.D2_PT_0/IN0 \ 0 20681 (_entity .  X_INV)
		(_port
			((I) (N_PZ_949))
			((O) (\NlwInverterSignal_U1/Channel0<7>_MC.D2_PT_0/IN0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/Channel0<7>_MC.D2_PT_2/IN2 \ 0 20685 (_entity .  X_INV)
		(_port
			((I) (N_PZ_961))
			((O) (\NlwInverterSignal_U1/Channel0<7>_MC.D2_PT_2/IN2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/Channel0<7>_MC.D2_PT_2/IN3 \ 0 20689 (_entity .  X_INV)
		(_port
			((I) (\U1/U2/location_Maddsub__n0000__n0103 \(0)))
			((O) (\NlwInverterSignal_U1/Channel0<7>_MC.D2_PT_2/IN3 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/U2/location_Maddsub__n0000__n0103<0>_MC.D2_PT_1/IN0 \ 0 20693 (_entity .  X_INV)
		(_port
			((I) (\U1/Channel0 \(5)))
			((O) (\NlwInverterSignal_U1/U2/location_Maddsub__n0000__n0103<0>_MC.D2_PT_1/IN0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/U2/location_Maddsub__n0000__n0103<0>_MC.D2_PT_1/IN1 \ 0 20697 (_entity .  X_INV)
		(_port
			((I) (\U1/Channel0 \(0)))
			((O) (\NlwInverterSignal_U1/U2/location_Maddsub__n0000__n0103<0>_MC.D2_PT_1/IN1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/U2/location_Maddsub__n0000__n0103<0>_MC.D2_PT_1/IN2 \ 0 20701 (_entity .  X_INV)
		(_port
			((I) (\U1/Channel0 \(1)))
			((O) (\NlwInverterSignal_U1/U2/location_Maddsub__n0000__n0103<0>_MC.D2_PT_1/IN2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/U2/location_Maddsub__n0000__n0103<0>_MC.D2_PT_1/IN3 \ 0 20705 (_entity .  X_INV)
		(_port
			((I) (\U1/Channel0 \(2)))
			((O) (\NlwInverterSignal_U1/U2/location_Maddsub__n0000__n0103<0>_MC.D2_PT_1/IN3 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/U2/location_Maddsub__n0000__n0103<0>_MC.D2_PT_1/IN4 \ 0 20709 (_entity .  X_INV)
		(_port
			((I) (\U1/Channel0 \(3)))
			((O) (\NlwInverterSignal_U1/U2/location_Maddsub__n0000__n0103<0>_MC.D2_PT_1/IN4 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/U2/location_Maddsub__n0000__n0103<0>_MC.D2_PT_1/IN5 \ 0 20713 (_entity .  X_INV)
		(_port
			((I) (\U1/Channel0 \(4)))
			((O) (\NlwInverterSignal_U1/U2/location_Maddsub__n0000__n0103<0>_MC.D2_PT_1/IN5 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/U2/location_Maddsub__n0000__n0103<0>_MC.D2_PT_1/IN6 \ 0 20717 (_entity .  X_INV)
		(_port
			((I) (N_PZ_967))
			((O) (\NlwInverterSignal_U1/U2/location_Maddsub__n0000__n0103<0>_MC.D2_PT_1/IN6 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/U2/location_Maddsub__n0000__n0103<0>_MC.D2_PT_1/IN7 \ 0 20721 (_entity .  X_INV)
		(_port
			((I) (\U1/Channel0 \(6)))
			((O) (\NlwInverterSignal_U1/U2/location_Maddsub__n0000__n0103<0>_MC.D2_PT_1/IN7 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/Channel0<6>_MC.D2_PT_0/IN0 \ 0 20725 (_entity .  X_INV)
		(_port
			((I) (N_PZ_949))
			((O) (\NlwInverterSignal_U1/Channel0<6>_MC.D2_PT_0/IN0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/Channel0<6>_MC.D2_PT_1/IN0 \ 0 20729 (_entity .  X_INV)
		(_port
			((I) (\U1/Channel0 \(5)))
			((O) (\NlwInverterSignal_U1/Channel0<6>_MC.D2_PT_1/IN0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/Channel0<6>_MC.D2_PT_1/IN2 \ 0 20733 (_entity .  X_INV)
		(_port
			((I) (N_PZ_961))
			((O) (\NlwInverterSignal_U1/Channel0<6>_MC.D2_PT_1/IN2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/Channel0<6>_MC.D2_PT_1/IN3 \ 0 20737 (_entity .  X_INV)
		(_port
			((I) (\U1/U2/location_Maddsub__n0000__n0103 \(0)))
			((O) (\NlwInverterSignal_U1/Channel0<6>_MC.D2_PT_1/IN3 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/Channel0<6>_MC.D2_PT_2/IN4 \ 0 20741 (_entity .  X_INV)
		(_port
			((I) (\U1/Channel0 \(6)))
			((O) (\NlwInverterSignal_U1/Channel0<6>_MC.D2_PT_2/IN4 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/Channel0<6>_MC.D2_PT_3/IN0 \ 0 20745 (_entity .  X_INV)
		(_port
			((I) (\U1/Channel0 \(5)))
			((O) (\NlwInverterSignal_U1/Channel0<6>_MC.D2_PT_3/IN0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/Channel0<6>_MC.D2_PT_3/IN1 \ 0 20749 (_entity .  X_INV)
		(_port
			((I) (\U1/Channel0 \(0)))
			((O) (\NlwInverterSignal_U1/Channel0<6>_MC.D2_PT_3/IN1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/Channel0<6>_MC.D2_PT_3/IN3 \ 0 20753 (_entity .  X_INV)
		(_port
			((I) (\U1/Channel0 \(1)))
			((O) (\NlwInverterSignal_U1/Channel0<6>_MC.D2_PT_3/IN3 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/Channel0<6>_MC.D2_PT_3/IN4 \ 0 20757 (_entity .  X_INV)
		(_port
			((I) (\U1/Channel0 \(2)))
			((O) (\NlwInverterSignal_U1/Channel0<6>_MC.D2_PT_3/IN4 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/Channel0<6>_MC.D2_PT_3/IN5 \ 0 20761 (_entity .  X_INV)
		(_port
			((I) (\U1/Channel0 \(3)))
			((O) (\NlwInverterSignal_U1/Channel0<6>_MC.D2_PT_3/IN5 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/Channel0<6>_MC.D2_PT_3/IN6 \ 0 20765 (_entity .  X_INV)
		(_port
			((I) (\U1/Channel0 \(4)))
			((O) (\NlwInverterSignal_U1/Channel0<6>_MC.D2_PT_3/IN6 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/Channel0<6>_MC.D2_PT_3/IN7 \ 0 20769 (_entity .  X_INV)
		(_port
			((I) (\U1/U2/location_Maddsub__n0000__n0103 \(0)))
			((O) (\NlwInverterSignal_U1/Channel0<6>_MC.D2_PT_3/IN7 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/Channel0<6>_MC.D2_PT_4/IN3 \ 0 20773 (_entity .  X_INV)
		(_port
			((I) (N_PZ_961))
			((O) (\NlwInverterSignal_U1/Channel0<6>_MC.D2_PT_4/IN3 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/Channel0<6>_MC.D2_PT_4/IN7 \ 0 20777 (_entity .  X_INV)
		(_port
			((I) (\U1/U2/location_Maddsub__n0000__n0103 \(0)))
			((O) (\NlwInverterSignal_U1/Channel0<6>_MC.D2_PT_4/IN7 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/Channel0<6>_MC.D2_PT_5/IN9 \ 0 20781 (_entity .  X_INV)
		(_port
			((I) (\U1/Channel0 \(6)))
			((O) (\NlwInverterSignal_U1/Channel0<6>_MC.D2_PT_5/IN9 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/Channel0<8>_MC.D2_PT_0/IN0 \ 0 20785 (_entity .  X_INV)
		(_port
			((I) (N_PZ_949))
			((O) (\NlwInverterSignal_U1/Channel0<8>_MC.D2_PT_0/IN0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/Channel0<8>_MC.D2_PT_1/IN3 \ 0 20789 (_entity .  X_INV)
		(_port
			((I) (\U1/Channel0 \(7)))
			((O) (\NlwInverterSignal_U1/Channel0<8>_MC.D2_PT_1/IN3 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/Channel0<8>_MC.D2_PT_2/IN2 \ 0 20793 (_entity .  X_INV)
		(_port
			((I) (N_PZ_961))
			((O) (\NlwInverterSignal_U1/Channel0<8>_MC.D2_PT_2/IN2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/Channel0<8>_MC.D2_PT_2/IN4 \ 0 20797 (_entity .  X_INV)
		(_port
			((I) (\U1/U2/location_Maddsub__n0000__n0103 \(0)))
			((O) (\NlwInverterSignal_U1/Channel0<8>_MC.D2_PT_2/IN4 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/Channel0<9>_MC.D2_PT_0/IN0 \ 0 20801 (_entity .  X_INV)
		(_port
			((I) (N_PZ_949))
			((O) (\NlwInverterSignal_U1/Channel0<9>_MC.D2_PT_0/IN0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/Channel0<9>_MC.D2_PT_1/IN3 \ 0 20805 (_entity .  X_INV)
		(_port
			((I) (\U1/Channel0 \(7)))
			((O) (\NlwInverterSignal_U1/Channel0<9>_MC.D2_PT_1/IN3 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/Channel0<9>_MC.D2_PT_1/IN5 \ 0 20809 (_entity .  X_INV)
		(_port
			((I) (\U1/Channel0 \(8)))
			((O) (\NlwInverterSignal_U1/Channel0<9>_MC.D2_PT_1/IN5 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/Channel0<9>_MC.D2_PT_2/IN2 \ 0 20813 (_entity .  X_INV)
		(_port
			((I) (N_PZ_961))
			((O) (\NlwInverterSignal_U1/Channel0<9>_MC.D2_PT_2/IN2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/Channel0<9>_MC.D2_PT_2/IN4 \ 0 20817 (_entity .  X_INV)
		(_port
			((I) (\U1/U2/location_Maddsub__n0000__n0103 \(0)))
			((O) (\NlwInverterSignal_U1/Channel0<9>_MC.D2_PT_2/IN4 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_N_PZ_1317_MC.D2_PT_0/IN2 \ 0 20821 (_entity .  X_INV)
		(_port
			((I) (\U1/Channel0 \(7)))
			((O) (\NlwInverterSignal_N_PZ_1317_MC.D2_PT_0/IN2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_N_PZ_1317_MC.D2_PT_0/IN3 \ 0 20825 (_entity .  X_INV)
		(_port
			((I) (\U1/Channel0 \(8)))
			((O) (\NlwInverterSignal_N_PZ_1317_MC.D2_PT_0/IN3 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_N_PZ_1317_MC.D2_PT_0/IN4 \ 0 20829 (_entity .  X_INV)
		(_port
			((I) (\U1/Channel0 \(9)))
			((O) (\NlwInverterSignal_N_PZ_1317_MC.D2_PT_0/IN4 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_N_PZ_1317_MC.D2_PT_1/IN1 \ 0 20833 (_entity .  X_INV)
		(_port
			((I) (N_PZ_961))
			((O) (\NlwInverterSignal_N_PZ_1317_MC.D2_PT_1/IN1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_N_PZ_1317_MC.D2_PT_1/IN2 \ 0 20837 (_entity .  X_INV)
		(_port
			((I) (\U1/U2/location_Maddsub__n0000__n0103 \(0)))
			((O) (\NlwInverterSignal_N_PZ_1317_MC.D2_PT_1/IN2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_N_PZ_1317_MC.D2_PT_2/IN1 \ 0 20841 (_entity .  X_INV)
		(_port
			((I) (\U1/Channel0 \(7)))
			((O) (\NlwInverterSignal_N_PZ_1317_MC.D2_PT_2/IN1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_N_PZ_1317_MC.D2_PT_2/IN2 \ 0 20845 (_entity .  X_INV)
		(_port
			((I) (\U1/U2/location_Maddsub__n0000__n0103 \(0)))
			((O) (\NlwInverterSignal_N_PZ_1317_MC.D2_PT_2/IN2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_N_PZ_1317_MC.D2_PT_2/IN3 \ 0 20849 (_entity .  X_INV)
		(_port
			((I) (\U1/Channel0 \(8)))
			((O) (\NlwInverterSignal_N_PZ_1317_MC.D2_PT_2/IN3 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/Channel0<11>_MC.D/IN0 \ 0 20853 (_entity .  X_INV)
		(_port
			((I) (\U1/Channel0<11>_MC.D1 \))
			((O) (\NlwInverterSignal_U1/Channel0<11>_MC.D/IN0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/Channel0<11>_MC.D2_PT_0/IN0 \ 0 20857 (_entity .  X_INV)
		(_port
			((I) (N_PZ_949))
			((O) (\NlwInverterSignal_U1/Channel0<11>_MC.D2_PT_0/IN0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/Channel0<11>_MC.D2_PT_0/IN1 \ 0 20861 (_entity .  X_INV)
		(_port
			((I) (N_PZ_949))
			((O) (\NlwInverterSignal_U1/Channel0<11>_MC.D2_PT_0/IN1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/Channel0<11>_MC.D2_PT_1/IN0 \ 0 20865 (_entity .  X_INV)
		(_port
			((I) (\U1/Channel0 \(11)))
			((O) (\NlwInverterSignal_U1/Channel0<11>_MC.D2_PT_1/IN0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/Channel0<11>_MC.D2_PT_1/IN1 \ 0 20869 (_entity .  X_INV)
		(_port
			((I) (N_PZ_1317))
			((O) (\NlwInverterSignal_U1/Channel0<11>_MC.D2_PT_1/IN1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/Channel0<11>_MC.D2_PT_2/IN1 \ 0 20873 (_entity .  X_INV)
		(_port
			((I) (\U1/Channel0 \(7)))
			((O) (\NlwInverterSignal_U1/Channel0<11>_MC.D2_PT_2/IN1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/Channel0<11>_MC.D2_PT_2/IN2 \ 0 20877 (_entity .  X_INV)
		(_port
			((I) (\U1/Channel0 \(11)))
			((O) (\NlwInverterSignal_U1/Channel0<11>_MC.D2_PT_2/IN2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/Channel0<11>_MC.D2_PT_3/IN0 \ 0 20881 (_entity .  X_INV)
		(_port
			((I) (\U1/Channel0 \(10)))
			((O) (\NlwInverterSignal_U1/Channel0<11>_MC.D2_PT_3/IN0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/Channel0<11>_MC.D2_PT_3/IN1 \ 0 20885 (_entity .  X_INV)
		(_port
			((I) (\U1/U2/location_Maddsub__n0000__n0103 \(0)))
			((O) (\NlwInverterSignal_U1/Channel0<11>_MC.D2_PT_3/IN1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/Channel0<11>_MC.D2_PT_3/IN2 \ 0 20889 (_entity .  X_INV)
		(_port
			((I) (\U1/Channel0 \(11)))
			((O) (\NlwInverterSignal_U1/Channel0<11>_MC.D2_PT_3/IN2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/Channel0<11>_MC.D2_PT_4/IN1 \ 0 20893 (_entity .  X_INV)
		(_port
			((I) (N_PZ_961))
			((O) (\NlwInverterSignal_U1/Channel0<11>_MC.D2_PT_4/IN1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/Channel0<11>_MC.D2_PT_4/IN4 \ 0 20897 (_entity .  X_INV)
		(_port
			((I) (\U1/U2/location_Maddsub__n0000__n0103 \(0)))
			((O) (\NlwInverterSignal_U1/Channel0<11>_MC.D2_PT_4/IN4 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/Channel0<11>_MC.D2_PT_5/IN3 \ 0 20901 (_entity .  X_INV)
		(_port
			((I) (\U1/Channel0 \(10)))
			((O) (\NlwInverterSignal_U1/Channel0<11>_MC.D2_PT_5/IN3 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/Channel0<11>_MC.D2_PT_5/IN4 \ 0 20905 (_entity .  X_INV)
		(_port
			((I) (\U1/Channel0 \(7)))
			((O) (\NlwInverterSignal_U1/Channel0<11>_MC.D2_PT_5/IN4 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/Channel0<11>_MC.D2_PT_5/IN6 \ 0 20909 (_entity .  X_INV)
		(_port
			((I) (\U1/Channel0 \(8)))
			((O) (\NlwInverterSignal_U1/Channel0<11>_MC.D2_PT_5/IN6 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/Channel0<11>_MC.D2_PT_5/IN7 \ 0 20913 (_entity .  X_INV)
		(_port
			((I) (\U1/Channel0 \(9)))
			((O) (\NlwInverterSignal_U1/Channel0<11>_MC.D2_PT_5/IN7 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/Channel0<12>_MC.D2_PT_0/IN0 \ 0 20917 (_entity .  X_INV)
		(_port
			((I) (N_PZ_949))
			((O) (\NlwInverterSignal_U1/Channel0<12>_MC.D2_PT_0/IN0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/Channel0<12>_MC.D2_PT_1/IN4 \ 0 20921 (_entity .  X_INV)
		(_port
			((I) (\U1/Channel0 \(12)))
			((O) (\NlwInverterSignal_U1/Channel0<12>_MC.D2_PT_1/IN4 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/Channel0<12>_MC.D2_PT_2/IN1 \ 0 20925 (_entity .  X_INV)
		(_port
			((I) (N_PZ_961))
			((O) (\NlwInverterSignal_U1/Channel0<12>_MC.D2_PT_2/IN1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/Channel0<12>_MC.D2_PT_2/IN2 \ 0 20929 (_entity .  X_INV)
		(_port
			((I) (\U1/U2/location_Maddsub__n0000__n0115 \(0)))
			((O) (\NlwInverterSignal_U1/Channel0<12>_MC.D2_PT_2/IN2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/Channel0<12>_MC.D2_PT_2/IN3 \ 0 20933 (_entity .  X_INV)
		(_port
			((I) (\U1/Channel0 \(11)))
			((O) (\NlwInverterSignal_U1/Channel0<12>_MC.D2_PT_2/IN3 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/Channel0<12>_MC.D2_PT_3/IN1 \ 0 20937 (_entity .  X_INV)
		(_port
			((I) (N_PZ_961))
			((O) (\NlwInverterSignal_U1/Channel0<12>_MC.D2_PT_3/IN1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/Channel0<12>_MC.D2_PT_3/IN2 \ 0 20941 (_entity .  X_INV)
		(_port
			((I) (\U1/U2/location_Maddsub__n0000__n0115 \(0)))
			((O) (\NlwInverterSignal_U1/Channel0<12>_MC.D2_PT_3/IN2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/Channel0<12>_MC.D2_PT_3/IN5 \ 0 20945 (_entity .  X_INV)
		(_port
			((I) (\U1/U2/location_Maddsub__n0000__n0103 \(0)))
			((O) (\NlwInverterSignal_U1/Channel0<12>_MC.D2_PT_3/IN5 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/Channel0<12>_MC.D2_PT_4/IN1 \ 0 20949 (_entity .  X_INV)
		(_port
			((I) (\U1/U2/location_Maddsub__n0000__n0115 \(0)))
			((O) (\NlwInverterSignal_U1/Channel0<12>_MC.D2_PT_4/IN1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/Channel0<12>_MC.D2_PT_4/IN2 \ 0 20953 (_entity .  X_INV)
		(_port
			((I) (\U1/Channel0 \(10)))
			((O) (\NlwInverterSignal_U1/Channel0<12>_MC.D2_PT_4/IN2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/Channel0<12>_MC.D2_PT_4/IN3 \ 0 20957 (_entity .  X_INV)
		(_port
			((I) (\U1/Channel0 \(7)))
			((O) (\NlwInverterSignal_U1/Channel0<12>_MC.D2_PT_4/IN3 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/Channel0<12>_MC.D2_PT_4/IN5 \ 0 20961 (_entity .  X_INV)
		(_port
			((I) (\U1/Channel0 \(8)))
			((O) (\NlwInverterSignal_U1/Channel0<12>_MC.D2_PT_4/IN5 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/Channel0<12>_MC.D2_PT_4/IN6 \ 0 20965 (_entity .  X_INV)
		(_port
			((I) (\U1/Channel0 \(9)))
			((O) (\NlwInverterSignal_U1/Channel0<12>_MC.D2_PT_4/IN6 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/Channel0<12>_MC.D2_PT_4/IN7 \ 0 20969 (_entity .  X_INV)
		(_port
			((I) (\U1/Channel0 \(11)))
			((O) (\NlwInverterSignal_U1/Channel0<12>_MC.D2_PT_4/IN7 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/Channel0<12>_MC.D2_PT_5/IN5 \ 0 20973 (_entity .  X_INV)
		(_port
			((I) (\U1/U2/location_Maddsub__n0000__n0103 \(0)))
			((O) (\NlwInverterSignal_U1/Channel0<12>_MC.D2_PT_5/IN5 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/Channel0<12>_MC.D2_PT_5/IN9 \ 0 20977 (_entity .  X_INV)
		(_port
			((I) (\U1/Channel0 \(12)))
			((O) (\NlwInverterSignal_U1/Channel0<12>_MC.D2_PT_5/IN9 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/Channel0<14>_MC.D2_PT_0/IN0 \ 0 20981 (_entity .  X_INV)
		(_port
			((I) (N_PZ_949))
			((O) (\NlwInverterSignal_U1/Channel0<14>_MC.D2_PT_0/IN0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/Channel0<14>_MC.D2_PT_1/IN3 \ 0 20985 (_entity .  X_INV)
		(_port
			((I) (\U1/Channel0 \(13)))
			((O) (\NlwInverterSignal_U1/Channel0<14>_MC.D2_PT_1/IN3 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/Channel0<14>_MC.D2_PT_2/IN2 \ 0 20989 (_entity .  X_INV)
		(_port
			((I) (N_PZ_961))
			((O) (\NlwInverterSignal_U1/Channel0<14>_MC.D2_PT_2/IN2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/Channel0<14>_MC.D2_PT_2/IN4 \ 0 20993 (_entity .  X_INV)
		(_port
			((I) (\U1/U2/location_Maddsub__n0000__n0115 \(0)))
			((O) (\NlwInverterSignal_U1/Channel0<14>_MC.D2_PT_2/IN4 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/Channel0<15>_MC.D2_PT_0/IN0 \ 0 20997 (_entity .  X_INV)
		(_port
			((I) (N_PZ_949))
			((O) (\NlwInverterSignal_U1/Channel0<15>_MC.D2_PT_0/IN0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/Channel0<15>_MC.D2_PT_1/IN3 \ 0 21001 (_entity .  X_INV)
		(_port
			((I) (\U1/Channel0 \(13)))
			((O) (\NlwInverterSignal_U1/Channel0<15>_MC.D2_PT_1/IN3 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/Channel0<15>_MC.D2_PT_1/IN5 \ 0 21005 (_entity .  X_INV)
		(_port
			((I) (\U1/Channel0 \(14)))
			((O) (\NlwInverterSignal_U1/Channel0<15>_MC.D2_PT_1/IN5 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/Channel0<15>_MC.D2_PT_2/IN2 \ 0 21009 (_entity .  X_INV)
		(_port
			((I) (N_PZ_961))
			((O) (\NlwInverterSignal_U1/Channel0<15>_MC.D2_PT_2/IN2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/Channel0<15>_MC.D2_PT_2/IN4 \ 0 21013 (_entity .  X_INV)
		(_port
			((I) (\U1/U2/location_Maddsub__n0000__n0115 \(0)))
			((O) (\NlwInverterSignal_U1/Channel0<15>_MC.D2_PT_2/IN4 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/Channel0<16>_MC.D2_PT_0/IN0 \ 0 21017 (_entity .  X_INV)
		(_port
			((I) (N_PZ_949))
			((O) (\NlwInverterSignal_U1/Channel0<16>_MC.D2_PT_0/IN0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/Channel0<16>_MC.D2_PT_1/IN3 \ 0 21021 (_entity .  X_INV)
		(_port
			((I) (\U1/Channel0 \(13)))
			((O) (\NlwInverterSignal_U1/Channel0<16>_MC.D2_PT_1/IN3 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/Channel0<16>_MC.D2_PT_1/IN5 \ 0 21025 (_entity .  X_INV)
		(_port
			((I) (\U1/Channel0 \(14)))
			((O) (\NlwInverterSignal_U1/Channel0<16>_MC.D2_PT_1/IN5 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/Channel0<16>_MC.D2_PT_1/IN6 \ 0 21029 (_entity .  X_INV)
		(_port
			((I) (\U1/Channel0 \(15)))
			((O) (\NlwInverterSignal_U1/Channel0<16>_MC.D2_PT_1/IN6 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/Channel0<16>_MC.D2_PT_2/IN2 \ 0 21033 (_entity .  X_INV)
		(_port
			((I) (N_PZ_961))
			((O) (\NlwInverterSignal_U1/Channel0<16>_MC.D2_PT_2/IN2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/Channel0<16>_MC.D2_PT_2/IN4 \ 0 21037 (_entity .  X_INV)
		(_port
			((I) (\U1/U2/location_Maddsub__n0000__n0115 \(0)))
			((O) (\NlwInverterSignal_U1/Channel0<16>_MC.D2_PT_2/IN4 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/Channel0<17>_MC.D2_PT_0/IN0 \ 0 21041 (_entity .  X_INV)
		(_port
			((I) (N_PZ_949))
			((O) (\NlwInverterSignal_U1/Channel0<17>_MC.D2_PT_0/IN0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/Channel0<17>_MC.D2_PT_1/IN1 \ 0 21045 (_entity .  X_INV)
		(_port
			((I) (N_PZ_961))
			((O) (\NlwInverterSignal_U1/Channel0<17>_MC.D2_PT_1/IN1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/Channel0<17>_MC.D2_PT_1/IN3 \ 0 21049 (_entity .  X_INV)
		(_port
			((I) (\U1/U2/location_Maddsub__n0000__n0115 \(0)))
			((O) (\NlwInverterSignal_U1/Channel0<17>_MC.D2_PT_1/IN3 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/Channel0<17>_MC.D2_PT_2/IN3 \ 0 21053 (_entity .  X_INV)
		(_port
			((I) (\U1/Channel0 \(13)))
			((O) (\NlwInverterSignal_U1/Channel0<17>_MC.D2_PT_2/IN3 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/Channel0<17>_MC.D2_PT_2/IN5 \ 0 21057 (_entity .  X_INV)
		(_port
			((I) (\U1/Channel0 \(14)))
			((O) (\NlwInverterSignal_U1/Channel0<17>_MC.D2_PT_2/IN5 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/Channel0<17>_MC.D2_PT_2/IN6 \ 0 21061 (_entity .  X_INV)
		(_port
			((I) (\U1/Channel0 \(15)))
			((O) (\NlwInverterSignal_U1/Channel0<17>_MC.D2_PT_2/IN6 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/Channel0<17>_MC.D2_PT_2/IN7 \ 0 21065 (_entity .  X_INV)
		(_port
			((I) (\U1/Channel0 \(16)))
			((O) (\NlwInverterSignal_U1/Channel0<17>_MC.D2_PT_2/IN7 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/Channel0<17>_MC.D2_PT_3/IN3 \ 0 21069 (_entity .  X_INV)
		(_port
			((I) (\U1/Channel0 \(13)))
			((O) (\NlwInverterSignal_U1/Channel0<17>_MC.D2_PT_3/IN3 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/Channel0<17>_MC.D2_PT_3/IN5 \ 0 21073 (_entity .  X_INV)
		(_port
			((I) (\U1/Channel0 \(14)))
			((O) (\NlwInverterSignal_U1/Channel0<17>_MC.D2_PT_3/IN5 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/Channel0<17>_MC.D2_PT_3/IN6 \ 0 21077 (_entity .  X_INV)
		(_port
			((I) (\U1/Channel0 \(15)))
			((O) (\NlwInverterSignal_U1/Channel0<17>_MC.D2_PT_3/IN6 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/Channel0<17>_MC.D2_PT_3/IN7 \ 0 21081 (_entity .  X_INV)
		(_port
			((I) (\U1/Channel0 \(16)))
			((O) (\NlwInverterSignal_U1/Channel0<17>_MC.D2_PT_3/IN7 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/Channel0<17>_MC.D2_PT_3/IN8 \ 0 21085 (_entity .  X_INV)
		(_port
			((I) (\U1/Channel0 \(17)))
			((O) (\NlwInverterSignal_U1/Channel0<17>_MC.D2_PT_3/IN8 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/Channel0<17>_MC.D2_PT_4/IN2 \ 0 21089 (_entity .  X_INV)
		(_port
			((I) (N_PZ_961))
			((O) (\NlwInverterSignal_U1/Channel0<17>_MC.D2_PT_4/IN2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/Channel0<17>_MC.D2_PT_4/IN4 \ 0 21093 (_entity .  X_INV)
		(_port
			((I) (\U1/U2/location_Maddsub__n0000__n0115 \(0)))
			((O) (\NlwInverterSignal_U1/Channel0<17>_MC.D2_PT_4/IN4 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/Channel0<17>_MC.D2_PT_4/IN8 \ 0 21097 (_entity .  X_INV)
		(_port
			((I) (\U1/Channel0 \(17)))
			((O) (\NlwInverterSignal_U1/Channel0<17>_MC.D2_PT_4/IN8 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/Channel0<18>_MC.D2_PT_0/IN0 \ 0 21101 (_entity .  X_INV)
		(_port
			((I) (N_PZ_949))
			((O) (\NlwInverterSignal_U1/Channel0<18>_MC.D2_PT_0/IN0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/Channel0<18>_MC.D2_PT_1/IN2 \ 0 21105 (_entity .  X_INV)
		(_port
			((I) (\U1/Channel0 \(13)))
			((O) (\NlwInverterSignal_U1/Channel0<18>_MC.D2_PT_1/IN2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/Channel0<18>_MC.D2_PT_1/IN4 \ 0 21109 (_entity .  X_INV)
		(_port
			((I) (\U1/Channel0 \(14)))
			((O) (\NlwInverterSignal_U1/Channel0<18>_MC.D2_PT_1/IN4 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/Channel0<18>_MC.D2_PT_1/IN5 \ 0 21113 (_entity .  X_INV)
		(_port
			((I) (\U1/Channel0 \(15)))
			((O) (\NlwInverterSignal_U1/Channel0<18>_MC.D2_PT_1/IN5 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/Channel0<18>_MC.D2_PT_1/IN6 \ 0 21117 (_entity .  X_INV)
		(_port
			((I) (\U1/Channel0 \(16)))
			((O) (\NlwInverterSignal_U1/Channel0<18>_MC.D2_PT_1/IN6 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/Channel0<18>_MC.D2_PT_1/IN7 \ 0 21121 (_entity .  X_INV)
		(_port
			((I) (\U1/Channel0 \(17)))
			((O) (\NlwInverterSignal_U1/Channel0<18>_MC.D2_PT_1/IN7 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/Channel0<18>_MC.D2_PT_2/IN1 \ 0 21125 (_entity .  X_INV)
		(_port
			((I) (N_PZ_961))
			((O) (\NlwInverterSignal_U1/Channel0<18>_MC.D2_PT_2/IN1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/Channel0<18>_MC.D2_PT_2/IN3 \ 0 21129 (_entity .  X_INV)
		(_port
			((I) (\U1/U2/location_Maddsub__n0000__n0115 \(0)))
			((O) (\NlwInverterSignal_U1/Channel0<18>_MC.D2_PT_2/IN3 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/Channel0<18>_MC.D2_PT_3/IN3 \ 0 21133 (_entity .  X_INV)
		(_port
			((I) (\U1/Channel0 \(13)))
			((O) (\NlwInverterSignal_U1/Channel0<18>_MC.D2_PT_3/IN3 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/Channel0<18>_MC.D2_PT_3/IN5 \ 0 21137 (_entity .  X_INV)
		(_port
			((I) (\U1/Channel0 \(14)))
			((O) (\NlwInverterSignal_U1/Channel0<18>_MC.D2_PT_3/IN5 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/Channel0<18>_MC.D2_PT_3/IN6 \ 0 21141 (_entity .  X_INV)
		(_port
			((I) (\U1/Channel0 \(15)))
			((O) (\NlwInverterSignal_U1/Channel0<18>_MC.D2_PT_3/IN6 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/Channel0<18>_MC.D2_PT_3/IN7 \ 0 21145 (_entity .  X_INV)
		(_port
			((I) (\U1/Channel0 \(16)))
			((O) (\NlwInverterSignal_U1/Channel0<18>_MC.D2_PT_3/IN7 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/Channel0<18>_MC.D2_PT_3/IN8 \ 0 21149 (_entity .  X_INV)
		(_port
			((I) (\U1/Channel0 \(17)))
			((O) (\NlwInverterSignal_U1/Channel0<18>_MC.D2_PT_3/IN8 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/Channel0<18>_MC.D2_PT_3/IN9 \ 0 21153 (_entity .  X_INV)
		(_port
			((I) (\U1/Channel0 \(18)))
			((O) (\NlwInverterSignal_U1/Channel0<18>_MC.D2_PT_3/IN9 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/Channel0<18>_MC.D2_PT_4/IN2 \ 0 21157 (_entity .  X_INV)
		(_port
			((I) (N_PZ_961))
			((O) (\NlwInverterSignal_U1/Channel0<18>_MC.D2_PT_4/IN2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/Channel0<18>_MC.D2_PT_4/IN4 \ 0 21161 (_entity .  X_INV)
		(_port
			((I) (\U1/U2/location_Maddsub__n0000__n0115 \(0)))
			((O) (\NlwInverterSignal_U1/Channel0<18>_MC.D2_PT_4/IN4 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/Channel0<18>_MC.D2_PT_4/IN9 \ 0 21165 (_entity .  X_INV)
		(_port
			((I) (\U1/Channel0 \(18)))
			((O) (\NlwInverterSignal_U1/Channel0<18>_MC.D2_PT_4/IN9 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/Channel0<19>_MC.D2_PT_0/IN0 \ 0 21169 (_entity .  X_INV)
		(_port
			((I) (N_PZ_949))
			((O) (\NlwInverterSignal_U1/Channel0<19>_MC.D2_PT_0/IN0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/Channel0<19>_MC.D2_PT_1/IN2 \ 0 21173 (_entity .  X_INV)
		(_port
			((I) (\U1/Channel0 \(13)))
			((O) (\NlwInverterSignal_U1/Channel0<19>_MC.D2_PT_1/IN2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/Channel0<19>_MC.D2_PT_1/IN4 \ 0 21177 (_entity .  X_INV)
		(_port
			((I) (\U1/Channel0 \(14)))
			((O) (\NlwInverterSignal_U1/Channel0<19>_MC.D2_PT_1/IN4 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/Channel0<19>_MC.D2_PT_1/IN5 \ 0 21181 (_entity .  X_INV)
		(_port
			((I) (\U1/Channel0 \(15)))
			((O) (\NlwInverterSignal_U1/Channel0<19>_MC.D2_PT_1/IN5 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/Channel0<19>_MC.D2_PT_1/IN6 \ 0 21185 (_entity .  X_INV)
		(_port
			((I) (\U1/Channel0 \(16)))
			((O) (\NlwInverterSignal_U1/Channel0<19>_MC.D2_PT_1/IN6 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/Channel0<19>_MC.D2_PT_1/IN7 \ 0 21189 (_entity .  X_INV)
		(_port
			((I) (\U1/Channel0 \(17)))
			((O) (\NlwInverterSignal_U1/Channel0<19>_MC.D2_PT_1/IN7 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/Channel0<19>_MC.D2_PT_1/IN8 \ 0 21193 (_entity .  X_INV)
		(_port
			((I) (\U1/Channel0 \(18)))
			((O) (\NlwInverterSignal_U1/Channel0<19>_MC.D2_PT_1/IN8 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/Channel0<19>_MC.D2_PT_2/IN1 \ 0 21197 (_entity .  X_INV)
		(_port
			((I) (N_PZ_961))
			((O) (\NlwInverterSignal_U1/Channel0<19>_MC.D2_PT_2/IN1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/Channel0<19>_MC.D2_PT_2/IN3 \ 0 21201 (_entity .  X_INV)
		(_port
			((I) (\U1/U2/location_Maddsub__n0000__n0115 \(0)))
			((O) (\NlwInverterSignal_U1/Channel0<19>_MC.D2_PT_2/IN3 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/Channel0<19>_MC.D2_PT_3/IN3 \ 0 21205 (_entity .  X_INV)
		(_port
			((I) (\U1/Channel0 \(13)))
			((O) (\NlwInverterSignal_U1/Channel0<19>_MC.D2_PT_3/IN3 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/Channel0<19>_MC.D2_PT_3/IN5 \ 0 21209 (_entity .  X_INV)
		(_port
			((I) (\U1/Channel0 \(14)))
			((O) (\NlwInverterSignal_U1/Channel0<19>_MC.D2_PT_3/IN5 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/Channel0<19>_MC.D2_PT_3/IN6 \ 0 21213 (_entity .  X_INV)
		(_port
			((I) (\U1/Channel0 \(15)))
			((O) (\NlwInverterSignal_U1/Channel0<19>_MC.D2_PT_3/IN6 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/Channel0<19>_MC.D2_PT_3/IN7 \ 0 21217 (_entity .  X_INV)
		(_port
			((I) (\U1/Channel0 \(16)))
			((O) (\NlwInverterSignal_U1/Channel0<19>_MC.D2_PT_3/IN7 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/Channel0<19>_MC.D2_PT_3/IN8 \ 0 21221 (_entity .  X_INV)
		(_port
			((I) (\U1/Channel0 \(17)))
			((O) (\NlwInverterSignal_U1/Channel0<19>_MC.D2_PT_3/IN8 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/Channel0<19>_MC.D2_PT_3/IN9 \ 0 21225 (_entity .  X_INV)
		(_port
			((I) (\U1/Channel0 \(18)))
			((O) (\NlwInverterSignal_U1/Channel0<19>_MC.D2_PT_3/IN9 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/Channel0<19>_MC.D2_PT_3/IN10 \ 0 21229 (_entity .  X_INV)
		(_port
			((I) (\U1/Channel0 \(19)))
			((O) (\NlwInverterSignal_U1/Channel0<19>_MC.D2_PT_3/IN10 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/Channel0<19>_MC.D2_PT_4/IN2 \ 0 21233 (_entity .  X_INV)
		(_port
			((I) (N_PZ_961))
			((O) (\NlwInverterSignal_U1/Channel0<19>_MC.D2_PT_4/IN2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/Channel0<19>_MC.D2_PT_4/IN4 \ 0 21237 (_entity .  X_INV)
		(_port
			((I) (\U1/U2/location_Maddsub__n0000__n0115 \(0)))
			((O) (\NlwInverterSignal_U1/Channel0<19>_MC.D2_PT_4/IN4 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/Channel0<19>_MC.D2_PT_4/IN10 \ 0 21241 (_entity .  X_INV)
		(_port
			((I) (\U1/Channel0 \(19)))
			((O) (\NlwInverterSignal_U1/Channel0<19>_MC.D2_PT_4/IN10 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/Channel0<20>_MC.D2_PT_0/IN0 \ 0 21245 (_entity .  X_INV)
		(_port
			((I) (N_PZ_949))
			((O) (\NlwInverterSignal_U1/Channel0<20>_MC.D2_PT_0/IN0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/Channel0<20>_MC.D2_PT_1/IN3 \ 0 21249 (_entity .  X_INV)
		(_port
			((I) (\U1/Channel0 \(13)))
			((O) (\NlwInverterSignal_U1/Channel0<20>_MC.D2_PT_1/IN3 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/Channel0<20>_MC.D2_PT_1/IN5 \ 0 21253 (_entity .  X_INV)
		(_port
			((I) (\U1/Channel0 \(14)))
			((O) (\NlwInverterSignal_U1/Channel0<20>_MC.D2_PT_1/IN5 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/Channel0<20>_MC.D2_PT_1/IN6 \ 0 21257 (_entity .  X_INV)
		(_port
			((I) (\U1/Channel0 \(15)))
			((O) (\NlwInverterSignal_U1/Channel0<20>_MC.D2_PT_1/IN6 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/Channel0<20>_MC.D2_PT_1/IN7 \ 0 21261 (_entity .  X_INV)
		(_port
			((I) (\U1/Channel0 \(16)))
			((O) (\NlwInverterSignal_U1/Channel0<20>_MC.D2_PT_1/IN7 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/Channel0<20>_MC.D2_PT_1/IN8 \ 0 21265 (_entity .  X_INV)
		(_port
			((I) (\U1/Channel0 \(17)))
			((O) (\NlwInverterSignal_U1/Channel0<20>_MC.D2_PT_1/IN8 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/Channel0<20>_MC.D2_PT_1/IN9 \ 0 21269 (_entity .  X_INV)
		(_port
			((I) (\U1/Channel0 \(18)))
			((O) (\NlwInverterSignal_U1/Channel0<20>_MC.D2_PT_1/IN9 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/Channel0<20>_MC.D2_PT_1/IN10 \ 0 21273 (_entity .  X_INV)
		(_port
			((I) (\U1/Channel0 \(19)))
			((O) (\NlwInverterSignal_U1/Channel0<20>_MC.D2_PT_1/IN10 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/Channel0<20>_MC.D2_PT_2/IN2 \ 0 21277 (_entity .  X_INV)
		(_port
			((I) (N_PZ_961))
			((O) (\NlwInverterSignal_U1/Channel0<20>_MC.D2_PT_2/IN2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/Channel0<20>_MC.D2_PT_2/IN4 \ 0 21281 (_entity .  X_INV)
		(_port
			((I) (\U1/U2/location_Maddsub__n0000__n0115 \(0)))
			((O) (\NlwInverterSignal_U1/Channel0<20>_MC.D2_PT_2/IN4 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/Channel1<21>_MC.D2_PT_0/IN0 \ 0 21285 (_entity .  X_INV)
		(_port
			((I) (N_PZ_948))
			((O) (\NlwInverterSignal_U1/Channel1<21>_MC.D2_PT_0/IN0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/Channel1<21>_MC.D2_PT_1/IN3 \ 0 21289 (_entity .  X_INV)
		(_port
			((I) (\U1/Channel1 \(13)))
			((O) (\NlwInverterSignal_U1/Channel1<21>_MC.D2_PT_1/IN3 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/Channel1<21>_MC.D2_PT_1/IN5 \ 0 21293 (_entity .  X_INV)
		(_port
			((I) (\U1/Channel1 \(14)))
			((O) (\NlwInverterSignal_U1/Channel1<21>_MC.D2_PT_1/IN5 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/Channel1<21>_MC.D2_PT_1/IN6 \ 0 21297 (_entity .  X_INV)
		(_port
			((I) (\U1/Channel1 \(15)))
			((O) (\NlwInverterSignal_U1/Channel1<21>_MC.D2_PT_1/IN6 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/Channel1<21>_MC.D2_PT_1/IN7 \ 0 21301 (_entity .  X_INV)
		(_port
			((I) (\U1/Channel1 \(16)))
			((O) (\NlwInverterSignal_U1/Channel1<21>_MC.D2_PT_1/IN7 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/Channel1<21>_MC.D2_PT_1/IN8 \ 0 21305 (_entity .  X_INV)
		(_port
			((I) (\U1/Channel1 \(17)))
			((O) (\NlwInverterSignal_U1/Channel1<21>_MC.D2_PT_1/IN8 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/Channel1<21>_MC.D2_PT_1/IN9 \ 0 21309 (_entity .  X_INV)
		(_port
			((I) (\U1/Channel1 \(18)))
			((O) (\NlwInverterSignal_U1/Channel1<21>_MC.D2_PT_1/IN9 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/Channel1<21>_MC.D2_PT_1/IN10 \ 0 21313 (_entity .  X_INV)
		(_port
			((I) (\U1/Channel1 \(19)))
			((O) (\NlwInverterSignal_U1/Channel1<21>_MC.D2_PT_1/IN10 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/Channel1<21>_MC.D2_PT_1/IN11 \ 0 21317 (_entity .  X_INV)
		(_port
			((I) (\U1/Channel1 \(20)))
			((O) (\NlwInverterSignal_U1/Channel1<21>_MC.D2_PT_1/IN11 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/Channel1<21>_MC.D2_PT_2/IN2 \ 0 21321 (_entity .  X_INV)
		(_port
			((I) (N_PZ_993))
			((O) (\NlwInverterSignal_U1/Channel1<21>_MC.D2_PT_2/IN2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/Channel1<21>_MC.D2_PT_2/IN4 \ 0 21325 (_entity .  X_INV)
		(_port
			((I) (\U1/U5/location_Maddsub__n0000__n0115 \(0)))
			((O) (\NlwInverterSignal_U1/Channel1<21>_MC.D2_PT_2/IN4 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/Channel1<13>_MC.D2_PT_0/IN0 \ 0 21329 (_entity .  X_INV)
		(_port
			((I) (N_PZ_948))
			((O) (\NlwInverterSignal_U1/Channel1<13>_MC.D2_PT_0/IN0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/Channel1<13>_MC.D2_PT_2/IN2 \ 0 21333 (_entity .  X_INV)
		(_port
			((I) (N_PZ_993))
			((O) (\NlwInverterSignal_U1/Channel1<13>_MC.D2_PT_2/IN2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/Channel1<13>_MC.D2_PT_2/IN3 \ 0 21337 (_entity .  X_INV)
		(_port
			((I) (\U1/U5/location_Maddsub__n0000__n0115 \(0)))
			((O) (\NlwInverterSignal_U1/Channel1<13>_MC.D2_PT_2/IN3 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/U5/location_Maddsub__n0000__n0115<0>_MC.D2_PT_1/IN0 \ 0 21341 (_entity .  X_INV)
		(_port
			((I) (N_PZ_968))
			((O) (\NlwInverterSignal_U1/U5/location_Maddsub__n0000__n0115<0>_MC.D2_PT_1/IN0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/U5/location_Maddsub__n0000__n0115<0>_MC.D2_PT_1/IN1 \ 0 21345 (_entity .  X_INV)
		(_port
			((I) (\U1/Channel1 \(11)))
			((O) (\NlwInverterSignal_U1/U5/location_Maddsub__n0000__n0115<0>_MC.D2_PT_1/IN1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/U5/location_Maddsub__n0000__n0115<0>_MC.D2_PT_1/IN2 \ 0 21349 (_entity .  X_INV)
		(_port
			((I) (\U1/Channel1 \(12)))
			((O) (\NlwInverterSignal_U1/U5/location_Maddsub__n0000__n0115<0>_MC.D2_PT_1/IN2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/U5/location_Maddsub__n0000__n0115<0>_MC.D2_PT_1/IN3 \ 0 21353 (_entity .  X_INV)
		(_port
			((I) (\U1/Channel1 \(10)))
			((O) (\NlwInverterSignal_U1/U5/location_Maddsub__n0000__n0115<0>_MC.D2_PT_1/IN3 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/U5/location_Maddsub__n0000__n0115<0>_MC.D2_PT_1/IN4 \ 0 21357 (_entity .  X_INV)
		(_port
			((I) (\U1/Channel1 \(7)))
			((O) (\NlwInverterSignal_U1/U5/location_Maddsub__n0000__n0115<0>_MC.D2_PT_1/IN4 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/U5/location_Maddsub__n0000__n0115<0>_MC.D2_PT_1/IN6 \ 0 21361 (_entity .  X_INV)
		(_port
			((I) (\U1/Channel1 \(8)))
			((O) (\NlwInverterSignal_U1/U5/location_Maddsub__n0000__n0115<0>_MC.D2_PT_1/IN6 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/U5/location_Maddsub__n0000__n0115<0>_MC.D2_PT_1/IN7 \ 0 21365 (_entity .  X_INV)
		(_port
			((I) (\U1/Channel1 \(9)))
			((O) (\NlwInverterSignal_U1/U5/location_Maddsub__n0000__n0115<0>_MC.D2_PT_1/IN7 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_N_PZ_968_MC.D2_PT_1/IN2 \ 0 21369 (_entity .  X_INV)
		(_port
			((I) (\U1/U6/CurrState_Sreg0_FFD1 \))
			((O) (\NlwInverterSignal_N_PZ_968_MC.D2_PT_1/IN2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_N_PZ_968_MC.D2_PT_2/IN0 \ 0 21373 (_entity .  X_INV)
		(_port
			((I) (\U1/U6/CurrState_Sreg0_FFD3 \))
			((O) (\NlwInverterSignal_N_PZ_968_MC.D2_PT_2/IN0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_N_PZ_968_MC.D2_PT_2/IN1 \ 0 21377 (_entity .  X_INV)
		(_port
			((I) (\U1/U6/CurrState_Sreg0_FFD2 \))
			((O) (\NlwInverterSignal_N_PZ_968_MC.D2_PT_2/IN1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_N_PZ_968_MC.D2_PT_3/IN1 \ 0 21381 (_entity .  X_INV)
		(_port
			((I) (\U1/U6/CurrState_Sreg0_FFD2 \))
			((O) (\NlwInverterSignal_N_PZ_968_MC.D2_PT_3/IN1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_N_PZ_968_MC.D2_PT_3/IN2 \ 0 21385 (_entity .  X_INV)
		(_port
			((I) (\U1/U6/CurrState_Sreg0_FFD1 \))
			((O) (\NlwInverterSignal_N_PZ_968_MC.D2_PT_3/IN2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_N_PZ_968_MC.D2_PT_3/IN3 \ 0 21389 (_entity .  X_INV)
		(_port
			((I) (\U1/NET3720 \))
			((O) (\NlwInverterSignal_N_PZ_968_MC.D2_PT_3/IN3 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/Channel1<10>_MC.D2_PT_0/IN0 \ 0 21393 (_entity .  X_INV)
		(_port
			((I) (N_PZ_948))
			((O) (\NlwInverterSignal_U1/Channel1<10>_MC.D2_PT_0/IN0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/Channel1<10>_MC.D2_PT_1/IN3 \ 0 21397 (_entity .  X_INV)
		(_port
			((I) (\U1/Channel1 \(7)))
			((O) (\NlwInverterSignal_U1/Channel1<10>_MC.D2_PT_1/IN3 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/Channel1<10>_MC.D2_PT_1/IN5 \ 0 21401 (_entity .  X_INV)
		(_port
			((I) (\U1/Channel1 \(8)))
			((O) (\NlwInverterSignal_U1/Channel1<10>_MC.D2_PT_1/IN5 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/Channel1<10>_MC.D2_PT_1/IN6 \ 0 21405 (_entity .  X_INV)
		(_port
			((I) (\U1/Channel1 \(9)))
			((O) (\NlwInverterSignal_U1/Channel1<10>_MC.D2_PT_1/IN6 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/Channel1<10>_MC.D2_PT_2/IN2 \ 0 21409 (_entity .  X_INV)
		(_port
			((I) (N_PZ_993))
			((O) (\NlwInverterSignal_U1/Channel1<10>_MC.D2_PT_2/IN2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/Channel1<10>_MC.D2_PT_2/IN4 \ 0 21413 (_entity .  X_INV)
		(_port
			((I) (\U1/U5/location_Maddsub__n0000__n0103 \(0)))
			((O) (\NlwInverterSignal_U1/Channel1<10>_MC.D2_PT_2/IN4 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/Channel1<7>_MC.D2_PT_0/IN0 \ 0 21417 (_entity .  X_INV)
		(_port
			((I) (N_PZ_948))
			((O) (\NlwInverterSignal_U1/Channel1<7>_MC.D2_PT_0/IN0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/Channel1<7>_MC.D2_PT_2/IN2 \ 0 21421 (_entity .  X_INV)
		(_port
			((I) (N_PZ_993))
			((O) (\NlwInverterSignal_U1/Channel1<7>_MC.D2_PT_2/IN2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/Channel1<7>_MC.D2_PT_2/IN3 \ 0 21425 (_entity .  X_INV)
		(_port
			((I) (\U1/U5/location_Maddsub__n0000__n0103 \(0)))
			((O) (\NlwInverterSignal_U1/Channel1<7>_MC.D2_PT_2/IN3 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/U5/location_Maddsub__n0000__n0103<0>_MC.D2_PT_1/IN0 \ 0 21429 (_entity .  X_INV)
		(_port
			((I) (\U1/Channel1 \(5)))
			((O) (\NlwInverterSignal_U1/U5/location_Maddsub__n0000__n0103<0>_MC.D2_PT_1/IN0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/U5/location_Maddsub__n0000__n0103<0>_MC.D2_PT_1/IN1 \ 0 21433 (_entity .  X_INV)
		(_port
			((I) (\U1/Channel1 \(0)))
			((O) (\NlwInverterSignal_U1/U5/location_Maddsub__n0000__n0103<0>_MC.D2_PT_1/IN1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/U5/location_Maddsub__n0000__n0103<0>_MC.D2_PT_1/IN2 \ 0 21437 (_entity .  X_INV)
		(_port
			((I) (\U1/Channel1 \(1)))
			((O) (\NlwInverterSignal_U1/U5/location_Maddsub__n0000__n0103<0>_MC.D2_PT_1/IN2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/U5/location_Maddsub__n0000__n0103<0>_MC.D2_PT_1/IN3 \ 0 21441 (_entity .  X_INV)
		(_port
			((I) (\U1/Channel1 \(2)))
			((O) (\NlwInverterSignal_U1/U5/location_Maddsub__n0000__n0103<0>_MC.D2_PT_1/IN3 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/U5/location_Maddsub__n0000__n0103<0>_MC.D2_PT_1/IN4 \ 0 21445 (_entity .  X_INV)
		(_port
			((I) (\U1/Channel1 \(3)))
			((O) (\NlwInverterSignal_U1/U5/location_Maddsub__n0000__n0103<0>_MC.D2_PT_1/IN4 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/U5/location_Maddsub__n0000__n0103<0>_MC.D2_PT_1/IN5 \ 0 21449 (_entity .  X_INV)
		(_port
			((I) (\U1/Channel1 \(4)))
			((O) (\NlwInverterSignal_U1/U5/location_Maddsub__n0000__n0103<0>_MC.D2_PT_1/IN5 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/U5/location_Maddsub__n0000__n0103<0>_MC.D2_PT_1/IN6 \ 0 21453 (_entity .  X_INV)
		(_port
			((I) (N_PZ_968))
			((O) (\NlwInverterSignal_U1/U5/location_Maddsub__n0000__n0103<0>_MC.D2_PT_1/IN6 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/U5/location_Maddsub__n0000__n0103<0>_MC.D2_PT_1/IN7 \ 0 21457 (_entity .  X_INV)
		(_port
			((I) (\U1/Channel1 \(6)))
			((O) (\NlwInverterSignal_U1/U5/location_Maddsub__n0000__n0103<0>_MC.D2_PT_1/IN7 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/Channel1<6>_MC.D2_PT_0/IN0 \ 0 21461 (_entity .  X_INV)
		(_port
			((I) (N_PZ_948))
			((O) (\NlwInverterSignal_U1/Channel1<6>_MC.D2_PT_0/IN0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/Channel1<6>_MC.D2_PT_1/IN2 \ 0 21465 (_entity .  X_INV)
		(_port
			((I) (N_PZ_993))
			((O) (\NlwInverterSignal_U1/Channel1<6>_MC.D2_PT_1/IN2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/Channel1<6>_MC.D2_PT_1/IN3 \ 0 21469 (_entity .  X_INV)
		(_port
			((I) (\U1/U5/location_Maddsub__n0000__n0103 \(0)))
			((O) (\NlwInverterSignal_U1/Channel1<6>_MC.D2_PT_1/IN3 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/Channel1<6>_MC.D2_PT_2/IN4 \ 0 21473 (_entity .  X_INV)
		(_port
			((I) (\U1/Channel1 \(6)))
			((O) (\NlwInverterSignal_U1/Channel1<6>_MC.D2_PT_2/IN4 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/Channel1<6>_MC.D2_PT_3/IN1 \ 0 21477 (_entity .  X_INV)
		(_port
			((I) (N_PZ_993))
			((O) (\NlwInverterSignal_U1/Channel1<6>_MC.D2_PT_3/IN1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/Channel1<6>_MC.D2_PT_3/IN2 \ 0 21481 (_entity .  X_INV)
		(_port
			((I) (N_PZ_1226))
			((O) (\NlwInverterSignal_U1/Channel1<6>_MC.D2_PT_3/IN2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/Channel1<6>_MC.D2_PT_3/IN3 \ 0 21485 (_entity .  X_INV)
		(_port
			((I) (\U1/U5/location_Maddsub__n0000__n0103 \(0)))
			((O) (\NlwInverterSignal_U1/Channel1<6>_MC.D2_PT_3/IN3 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/Channel1<6>_MC.D2_PT_4/IN5 \ 0 21489 (_entity .  X_INV)
		(_port
			((I) (\U1/Channel1 \(6)))
			((O) (\NlwInverterSignal_U1/Channel1<6>_MC.D2_PT_4/IN5 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/Channel1<6>_MC.D2_PT_5/IN0 \ 0 21493 (_entity .  X_INV)
		(_port
			((I) (\U1/Channel1 \(5)))
			((O) (\NlwInverterSignal_U1/Channel1<6>_MC.D2_PT_5/IN0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/Channel1<6>_MC.D2_PT_5/IN2 \ 0 21497 (_entity .  X_INV)
		(_port
			((I) (\U1/Channel1 \(0)))
			((O) (\NlwInverterSignal_U1/Channel1<6>_MC.D2_PT_5/IN2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/Channel1<6>_MC.D2_PT_5/IN3 \ 0 21501 (_entity .  X_INV)
		(_port
			((I) (\U1/Channel1 \(1)))
			((O) (\NlwInverterSignal_U1/Channel1<6>_MC.D2_PT_5/IN3 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/Channel1<6>_MC.D2_PT_5/IN4 \ 0 21505 (_entity .  X_INV)
		(_port
			((I) (\U1/Channel1 \(2)))
			((O) (\NlwInverterSignal_U1/Channel1<6>_MC.D2_PT_5/IN4 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/Channel1<6>_MC.D2_PT_5/IN5 \ 0 21509 (_entity .  X_INV)
		(_port
			((I) (\U1/Channel1 \(3)))
			((O) (\NlwInverterSignal_U1/Channel1<6>_MC.D2_PT_5/IN5 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/Channel1<6>_MC.D2_PT_5/IN6 \ 0 21513 (_entity .  X_INV)
		(_port
			((I) (\U1/Channel1 \(4)))
			((O) (\NlwInverterSignal_U1/Channel1<6>_MC.D2_PT_5/IN6 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/Channel1<6>_MC.D2_PT_5/IN7 \ 0 21517 (_entity .  X_INV)
		(_port
			((I) (\U1/U5/location_Maddsub__n0000__n0103 \(0)))
			((O) (\NlwInverterSignal_U1/Channel1<6>_MC.D2_PT_5/IN7 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/Channel1<8>_MC.D2_PT_0/IN0 \ 0 21521 (_entity .  X_INV)
		(_port
			((I) (N_PZ_948))
			((O) (\NlwInverterSignal_U1/Channel1<8>_MC.D2_PT_0/IN0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/Channel1<8>_MC.D2_PT_1/IN3 \ 0 21525 (_entity .  X_INV)
		(_port
			((I) (\U1/Channel1 \(7)))
			((O) (\NlwInverterSignal_U1/Channel1<8>_MC.D2_PT_1/IN3 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/Channel1<8>_MC.D2_PT_2/IN2 \ 0 21529 (_entity .  X_INV)
		(_port
			((I) (N_PZ_993))
			((O) (\NlwInverterSignal_U1/Channel1<8>_MC.D2_PT_2/IN2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/Channel1<8>_MC.D2_PT_2/IN4 \ 0 21533 (_entity .  X_INV)
		(_port
			((I) (\U1/U5/location_Maddsub__n0000__n0103 \(0)))
			((O) (\NlwInverterSignal_U1/Channel1<8>_MC.D2_PT_2/IN4 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/Channel1<9>_MC.D2_PT_0/IN0 \ 0 21537 (_entity .  X_INV)
		(_port
			((I) (N_PZ_948))
			((O) (\NlwInverterSignal_U1/Channel1<9>_MC.D2_PT_0/IN0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/Channel1<9>_MC.D2_PT_1/IN3 \ 0 21541 (_entity .  X_INV)
		(_port
			((I) (\U1/Channel1 \(7)))
			((O) (\NlwInverterSignal_U1/Channel1<9>_MC.D2_PT_1/IN3 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/Channel1<9>_MC.D2_PT_1/IN5 \ 0 21545 (_entity .  X_INV)
		(_port
			((I) (\U1/Channel1 \(8)))
			((O) (\NlwInverterSignal_U1/Channel1<9>_MC.D2_PT_1/IN5 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/Channel1<9>_MC.D2_PT_2/IN2 \ 0 21549 (_entity .  X_INV)
		(_port
			((I) (N_PZ_993))
			((O) (\NlwInverterSignal_U1/Channel1<9>_MC.D2_PT_2/IN2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/Channel1<9>_MC.D2_PT_2/IN4 \ 0 21553 (_entity .  X_INV)
		(_port
			((I) (\U1/U5/location_Maddsub__n0000__n0103 \(0)))
			((O) (\NlwInverterSignal_U1/Channel1<9>_MC.D2_PT_2/IN4 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/Channel1<11>_MC.D2_PT_0/IN0 \ 0 21557 (_entity .  X_INV)
		(_port
			((I) (N_PZ_948))
			((O) (\NlwInverterSignal_U1/Channel1<11>_MC.D2_PT_0/IN0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/Channel1<11>_MC.D2_PT_1/IN2 \ 0 21561 (_entity .  X_INV)
		(_port
			((I) (N_PZ_993))
			((O) (\NlwInverterSignal_U1/Channel1<11>_MC.D2_PT_1/IN2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/Channel1<11>_MC.D2_PT_2/IN2 \ 0 21565 (_entity .  X_INV)
		(_port
			((I) (\U1/Channel1 \(11)))
			((O) (\NlwInverterSignal_U1/Channel1<11>_MC.D2_PT_2/IN2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/Channel1<11>_MC.D2_PT_2/IN4 \ 0 21569 (_entity .  X_INV)
		(_port
			((I) (\U1/Channel1 \(9)))
			((O) (\NlwInverterSignal_U1/Channel1<11>_MC.D2_PT_2/IN4 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/Channel1<11>_MC.D2_PT_3/IN3 \ 0 21573 (_entity .  X_INV)
		(_port
			((I) (\U1/Channel1 \(10)))
			((O) (\NlwInverterSignal_U1/Channel1<11>_MC.D2_PT_3/IN3 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/Channel1<11>_MC.D2_PT_3/IN4 \ 0 21577 (_entity .  X_INV)
		(_port
			((I) (\U1/Channel1 \(7)))
			((O) (\NlwInverterSignal_U1/Channel1<11>_MC.D2_PT_3/IN4 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/Channel1<11>_MC.D2_PT_3/IN6 \ 0 21581 (_entity .  X_INV)
		(_port
			((I) (\U1/Channel1 \(8)))
			((O) (\NlwInverterSignal_U1/Channel1<11>_MC.D2_PT_3/IN6 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/Channel1<11>_MC.D2_PT_3/IN7 \ 0 21585 (_entity .  X_INV)
		(_port
			((I) (\U1/Channel1 \(9)))
			((O) (\NlwInverterSignal_U1/Channel1<11>_MC.D2_PT_3/IN7 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_N_PZ_1055_MC.D1/IN2 \ 0 21589 (_entity .  X_INV)
		(_port
			((I) (\U1/U5/location_Maddsub__n0000__n0103 \(0)))
			((O) (\NlwInverterSignal_N_PZ_1055_MC.D1/IN2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/Channel1<12>_MC.D2_PT_0/IN0 \ 0 21593 (_entity .  X_INV)
		(_port
			((I) (N_PZ_948))
			((O) (\NlwInverterSignal_U1/Channel1<12>_MC.D2_PT_0/IN0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/Channel1<12>_MC.D2_PT_1/IN4 \ 0 21597 (_entity .  X_INV)
		(_port
			((I) (\U1/Channel1 \(12)))
			((O) (\NlwInverterSignal_U1/Channel1<12>_MC.D2_PT_1/IN4 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/Channel1<12>_MC.D2_PT_2/IN1 \ 0 21601 (_entity .  X_INV)
		(_port
			((I) (N_PZ_993))
			((O) (\NlwInverterSignal_U1/Channel1<12>_MC.D2_PT_2/IN1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/Channel1<12>_MC.D2_PT_2/IN2 \ 0 21605 (_entity .  X_INV)
		(_port
			((I) (\U1/U5/location_Maddsub__n0000__n0115 \(0)))
			((O) (\NlwInverterSignal_U1/Channel1<12>_MC.D2_PT_2/IN2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/Channel1<12>_MC.D2_PT_3/IN1 \ 0 21609 (_entity .  X_INV)
		(_port
			((I) (N_PZ_993))
			((O) (\NlwInverterSignal_U1/Channel1<12>_MC.D2_PT_3/IN1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/Channel1<12>_MC.D2_PT_3/IN2 \ 0 21613 (_entity .  X_INV)
		(_port
			((I) (\U1/U5/location_Maddsub__n0000__n0115 \(0)))
			((O) (\NlwInverterSignal_U1/Channel1<12>_MC.D2_PT_3/IN2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/Channel1<12>_MC.D2_PT_3/IN3 \ 0 21617 (_entity .  X_INV)
		(_port
			((I) (N_PZ_1055))
			((O) (\NlwInverterSignal_U1/Channel1<12>_MC.D2_PT_3/IN3 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/Channel1<12>_MC.D2_PT_4/IN5 \ 0 21621 (_entity .  X_INV)
		(_port
			((I) (\U1/Channel1 \(12)))
			((O) (\NlwInverterSignal_U1/Channel1<12>_MC.D2_PT_4/IN5 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/Channel1<12>_MC.D2_PT_5/IN1 \ 0 21625 (_entity .  X_INV)
		(_port
			((I) (\U1/U5/location_Maddsub__n0000__n0115 \(0)))
			((O) (\NlwInverterSignal_U1/Channel1<12>_MC.D2_PT_5/IN1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/Channel1<12>_MC.D2_PT_5/IN2 \ 0 21629 (_entity .  X_INV)
		(_port
			((I) (\U1/Channel1 \(11)))
			((O) (\NlwInverterSignal_U1/Channel1<12>_MC.D2_PT_5/IN2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/Channel1<12>_MC.D2_PT_5/IN4 \ 0 21633 (_entity .  X_INV)
		(_port
			((I) (\U1/Channel1 \(10)))
			((O) (\NlwInverterSignal_U1/Channel1<12>_MC.D2_PT_5/IN4 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/Channel1<12>_MC.D2_PT_5/IN5 \ 0 21637 (_entity .  X_INV)
		(_port
			((I) (\U1/Channel1 \(7)))
			((O) (\NlwInverterSignal_U1/Channel1<12>_MC.D2_PT_5/IN5 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/Channel1<12>_MC.D2_PT_5/IN7 \ 0 21641 (_entity .  X_INV)
		(_port
			((I) (\U1/Channel1 \(8)))
			((O) (\NlwInverterSignal_U1/Channel1<12>_MC.D2_PT_5/IN7 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/Channel1<12>_MC.D2_PT_5/IN8 \ 0 21645 (_entity .  X_INV)
		(_port
			((I) (\U1/Channel1 \(9)))
			((O) (\NlwInverterSignal_U1/Channel1<12>_MC.D2_PT_5/IN8 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/Channel1<14>_MC.D2_PT_0/IN0 \ 0 21649 (_entity .  X_INV)
		(_port
			((I) (N_PZ_948))
			((O) (\NlwInverterSignal_U1/Channel1<14>_MC.D2_PT_0/IN0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/Channel1<14>_MC.D2_PT_1/IN3 \ 0 21653 (_entity .  X_INV)
		(_port
			((I) (\U1/Channel1 \(13)))
			((O) (\NlwInverterSignal_U1/Channel1<14>_MC.D2_PT_1/IN3 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/Channel1<14>_MC.D2_PT_2/IN2 \ 0 21657 (_entity .  X_INV)
		(_port
			((I) (N_PZ_993))
			((O) (\NlwInverterSignal_U1/Channel1<14>_MC.D2_PT_2/IN2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/Channel1<14>_MC.D2_PT_2/IN4 \ 0 21661 (_entity .  X_INV)
		(_port
			((I) (\U1/U5/location_Maddsub__n0000__n0115 \(0)))
			((O) (\NlwInverterSignal_U1/Channel1<14>_MC.D2_PT_2/IN4 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/Channel1<15>_MC.D2_PT_0/IN0 \ 0 21665 (_entity .  X_INV)
		(_port
			((I) (N_PZ_948))
			((O) (\NlwInverterSignal_U1/Channel1<15>_MC.D2_PT_0/IN0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/Channel1<15>_MC.D2_PT_1/IN3 \ 0 21669 (_entity .  X_INV)
		(_port
			((I) (\U1/Channel1 \(13)))
			((O) (\NlwInverterSignal_U1/Channel1<15>_MC.D2_PT_1/IN3 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/Channel1<15>_MC.D2_PT_1/IN5 \ 0 21673 (_entity .  X_INV)
		(_port
			((I) (\U1/Channel1 \(14)))
			((O) (\NlwInverterSignal_U1/Channel1<15>_MC.D2_PT_1/IN5 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/Channel1<15>_MC.D2_PT_2/IN2 \ 0 21677 (_entity .  X_INV)
		(_port
			((I) (N_PZ_993))
			((O) (\NlwInverterSignal_U1/Channel1<15>_MC.D2_PT_2/IN2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/Channel1<15>_MC.D2_PT_2/IN4 \ 0 21681 (_entity .  X_INV)
		(_port
			((I) (\U1/U5/location_Maddsub__n0000__n0115 \(0)))
			((O) (\NlwInverterSignal_U1/Channel1<15>_MC.D2_PT_2/IN4 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/Channel1<16>_MC.D2_PT_0/IN0 \ 0 21685 (_entity .  X_INV)
		(_port
			((I) (N_PZ_948))
			((O) (\NlwInverterSignal_U1/Channel1<16>_MC.D2_PT_0/IN0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/Channel1<16>_MC.D2_PT_1/IN3 \ 0 21689 (_entity .  X_INV)
		(_port
			((I) (\U1/Channel1 \(13)))
			((O) (\NlwInverterSignal_U1/Channel1<16>_MC.D2_PT_1/IN3 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/Channel1<16>_MC.D2_PT_1/IN5 \ 0 21693 (_entity .  X_INV)
		(_port
			((I) (\U1/Channel1 \(14)))
			((O) (\NlwInverterSignal_U1/Channel1<16>_MC.D2_PT_1/IN5 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/Channel1<16>_MC.D2_PT_1/IN6 \ 0 21697 (_entity .  X_INV)
		(_port
			((I) (\U1/Channel1 \(15)))
			((O) (\NlwInverterSignal_U1/Channel1<16>_MC.D2_PT_1/IN6 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/Channel1<16>_MC.D2_PT_2/IN2 \ 0 21701 (_entity .  X_INV)
		(_port
			((I) (N_PZ_993))
			((O) (\NlwInverterSignal_U1/Channel1<16>_MC.D2_PT_2/IN2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/Channel1<16>_MC.D2_PT_2/IN4 \ 0 21705 (_entity .  X_INV)
		(_port
			((I) (\U1/U5/location_Maddsub__n0000__n0115 \(0)))
			((O) (\NlwInverterSignal_U1/Channel1<16>_MC.D2_PT_2/IN4 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/Channel1<17>_MC.D2_PT_0/IN0 \ 0 21709 (_entity .  X_INV)
		(_port
			((I) (N_PZ_948))
			((O) (\NlwInverterSignal_U1/Channel1<17>_MC.D2_PT_0/IN0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/Channel1<17>_MC.D2_PT_1/IN3 \ 0 21713 (_entity .  X_INV)
		(_port
			((I) (\U1/Channel1 \(13)))
			((O) (\NlwInverterSignal_U1/Channel1<17>_MC.D2_PT_1/IN3 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/Channel1<17>_MC.D2_PT_1/IN5 \ 0 21717 (_entity .  X_INV)
		(_port
			((I) (\U1/Channel1 \(14)))
			((O) (\NlwInverterSignal_U1/Channel1<17>_MC.D2_PT_1/IN5 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/Channel1<17>_MC.D2_PT_1/IN6 \ 0 21721 (_entity .  X_INV)
		(_port
			((I) (\U1/Channel1 \(15)))
			((O) (\NlwInverterSignal_U1/Channel1<17>_MC.D2_PT_1/IN6 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/Channel1<17>_MC.D2_PT_1/IN7 \ 0 21725 (_entity .  X_INV)
		(_port
			((I) (\U1/Channel1 \(16)))
			((O) (\NlwInverterSignal_U1/Channel1<17>_MC.D2_PT_1/IN7 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/Channel1<17>_MC.D2_PT_2/IN2 \ 0 21729 (_entity .  X_INV)
		(_port
			((I) (N_PZ_993))
			((O) (\NlwInverterSignal_U1/Channel1<17>_MC.D2_PT_2/IN2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/Channel1<17>_MC.D2_PT_2/IN4 \ 0 21733 (_entity .  X_INV)
		(_port
			((I) (\U1/U5/location_Maddsub__n0000__n0115 \(0)))
			((O) (\NlwInverterSignal_U1/Channel1<17>_MC.D2_PT_2/IN4 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/Channel1<18>_MC.D2_PT_0/IN0 \ 0 21737 (_entity .  X_INV)
		(_port
			((I) (N_PZ_948))
			((O) (\NlwInverterSignal_U1/Channel1<18>_MC.D2_PT_0/IN0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/Channel1<18>_MC.D2_PT_1/IN3 \ 0 21741 (_entity .  X_INV)
		(_port
			((I) (\U1/Channel1 \(13)))
			((O) (\NlwInverterSignal_U1/Channel1<18>_MC.D2_PT_1/IN3 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/Channel1<18>_MC.D2_PT_1/IN5 \ 0 21745 (_entity .  X_INV)
		(_port
			((I) (\U1/Channel1 \(14)))
			((O) (\NlwInverterSignal_U1/Channel1<18>_MC.D2_PT_1/IN5 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/Channel1<18>_MC.D2_PT_1/IN6 \ 0 21749 (_entity .  X_INV)
		(_port
			((I) (\U1/Channel1 \(15)))
			((O) (\NlwInverterSignal_U1/Channel1<18>_MC.D2_PT_1/IN6 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/Channel1<18>_MC.D2_PT_1/IN7 \ 0 21753 (_entity .  X_INV)
		(_port
			((I) (\U1/Channel1 \(16)))
			((O) (\NlwInverterSignal_U1/Channel1<18>_MC.D2_PT_1/IN7 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/Channel1<18>_MC.D2_PT_1/IN8 \ 0 21757 (_entity .  X_INV)
		(_port
			((I) (\U1/Channel1 \(17)))
			((O) (\NlwInverterSignal_U1/Channel1<18>_MC.D2_PT_1/IN8 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/Channel1<18>_MC.D2_PT_2/IN2 \ 0 21761 (_entity .  X_INV)
		(_port
			((I) (N_PZ_993))
			((O) (\NlwInverterSignal_U1/Channel1<18>_MC.D2_PT_2/IN2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/Channel1<18>_MC.D2_PT_2/IN4 \ 0 21765 (_entity .  X_INV)
		(_port
			((I) (\U1/U5/location_Maddsub__n0000__n0115 \(0)))
			((O) (\NlwInverterSignal_U1/Channel1<18>_MC.D2_PT_2/IN4 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/Channel1<19>_MC.D2_PT_0/IN0 \ 0 21769 (_entity .  X_INV)
		(_port
			((I) (N_PZ_948))
			((O) (\NlwInverterSignal_U1/Channel1<19>_MC.D2_PT_0/IN0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/Channel1<19>_MC.D2_PT_1/IN3 \ 0 21773 (_entity .  X_INV)
		(_port
			((I) (\U1/Channel1 \(13)))
			((O) (\NlwInverterSignal_U1/Channel1<19>_MC.D2_PT_1/IN3 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/Channel1<19>_MC.D2_PT_1/IN5 \ 0 21777 (_entity .  X_INV)
		(_port
			((I) (\U1/Channel1 \(14)))
			((O) (\NlwInverterSignal_U1/Channel1<19>_MC.D2_PT_1/IN5 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/Channel1<19>_MC.D2_PT_1/IN6 \ 0 21781 (_entity .  X_INV)
		(_port
			((I) (\U1/Channel1 \(15)))
			((O) (\NlwInverterSignal_U1/Channel1<19>_MC.D2_PT_1/IN6 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/Channel1<19>_MC.D2_PT_1/IN7 \ 0 21785 (_entity .  X_INV)
		(_port
			((I) (\U1/Channel1 \(16)))
			((O) (\NlwInverterSignal_U1/Channel1<19>_MC.D2_PT_1/IN7 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/Channel1<19>_MC.D2_PT_1/IN8 \ 0 21789 (_entity .  X_INV)
		(_port
			((I) (\U1/Channel1 \(17)))
			((O) (\NlwInverterSignal_U1/Channel1<19>_MC.D2_PT_1/IN8 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/Channel1<19>_MC.D2_PT_1/IN9 \ 0 21793 (_entity .  X_INV)
		(_port
			((I) (\U1/Channel1 \(18)))
			((O) (\NlwInverterSignal_U1/Channel1<19>_MC.D2_PT_1/IN9 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/Channel1<19>_MC.D2_PT_2/IN2 \ 0 21797 (_entity .  X_INV)
		(_port
			((I) (N_PZ_993))
			((O) (\NlwInverterSignal_U1/Channel1<19>_MC.D2_PT_2/IN2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/Channel1<19>_MC.D2_PT_2/IN4 \ 0 21801 (_entity .  X_INV)
		(_port
			((I) (\U1/U5/location_Maddsub__n0000__n0115 \(0)))
			((O) (\NlwInverterSignal_U1/Channel1<19>_MC.D2_PT_2/IN4 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/Channel1<20>_MC.D2_PT_0/IN0 \ 0 21805 (_entity .  X_INV)
		(_port
			((I) (N_PZ_948))
			((O) (\NlwInverterSignal_U1/Channel1<20>_MC.D2_PT_0/IN0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/Channel1<20>_MC.D2_PT_1/IN3 \ 0 21809 (_entity .  X_INV)
		(_port
			((I) (\U1/Channel1 \(13)))
			((O) (\NlwInverterSignal_U1/Channel1<20>_MC.D2_PT_1/IN3 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/Channel1<20>_MC.D2_PT_1/IN5 \ 0 21813 (_entity .  X_INV)
		(_port
			((I) (\U1/Channel1 \(14)))
			((O) (\NlwInverterSignal_U1/Channel1<20>_MC.D2_PT_1/IN5 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/Channel1<20>_MC.D2_PT_1/IN6 \ 0 21817 (_entity .  X_INV)
		(_port
			((I) (\U1/Channel1 \(15)))
			((O) (\NlwInverterSignal_U1/Channel1<20>_MC.D2_PT_1/IN6 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/Channel1<20>_MC.D2_PT_1/IN7 \ 0 21821 (_entity .  X_INV)
		(_port
			((I) (\U1/Channel1 \(16)))
			((O) (\NlwInverterSignal_U1/Channel1<20>_MC.D2_PT_1/IN7 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/Channel1<20>_MC.D2_PT_1/IN8 \ 0 21825 (_entity .  X_INV)
		(_port
			((I) (\U1/Channel1 \(17)))
			((O) (\NlwInverterSignal_U1/Channel1<20>_MC.D2_PT_1/IN8 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/Channel1<20>_MC.D2_PT_1/IN9 \ 0 21829 (_entity .  X_INV)
		(_port
			((I) (\U1/Channel1 \(18)))
			((O) (\NlwInverterSignal_U1/Channel1<20>_MC.D2_PT_1/IN9 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/Channel1<20>_MC.D2_PT_1/IN10 \ 0 21833 (_entity .  X_INV)
		(_port
			((I) (\U1/Channel1 \(19)))
			((O) (\NlwInverterSignal_U1/Channel1<20>_MC.D2_PT_1/IN10 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/Channel1<20>_MC.D2_PT_2/IN2 \ 0 21837 (_entity .  X_INV)
		(_port
			((I) (N_PZ_993))
			((O) (\NlwInverterSignal_U1/Channel1<20>_MC.D2_PT_2/IN2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/Channel1<20>_MC.D2_PT_2/IN4 \ 0 21841 (_entity .  X_INV)
		(_port
			((I) (\U1/U5/location_Maddsub__n0000__n0115 \(0)))
			((O) (\NlwInverterSignal_U1/Channel1<20>_MC.D2_PT_2/IN4 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/U3/holdingreg<13>_MC.D2_PT_1/IN0 \ 0 21845 (_entity .  X_INV)
		(_port
			((I) (\Reset_II/UIM \))
			((O) (\NlwInverterSignal_U1/U3/holdingreg<13>_MC.D2_PT_1/IN0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/U3/holdingreg<13>_MC.D2_PT_2/IN1 \ 0 21849 (_entity .  X_INV)
		(_port
			((I) (\RD_II/UIM \))
			((O) (\NlwInverterSignal_U1/U3/holdingreg<13>_MC.D2_PT_2/IN1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/U3/holdingreg<13>_MC.D2_PT_2/IN6 \ 0 21853 (_entity .  X_INV)
		(_port
			((I) (U2_ADDR_reg(3)))
			((O) (\NlwInverterSignal_U1/U3/holdingreg<13>_MC.D2_PT_2/IN6 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/U3/holdingreg<13>_MC.D2_PT_2/IN7 \ 0 21857 (_entity .  X_INV)
		(_port
			((I) (\Reset_II/UIM \))
			((O) (\NlwInverterSignal_U1/U3/holdingreg<13>_MC.D2_PT_2/IN7 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/U3/holdingreg<13>_MC.D2_PT_2/IN8 \ 0 21861 (_entity .  X_INV)
		(_port
			((I) (\U1/U3/RDedge \))
			((O) (\NlwInverterSignal_U1/U3/holdingreg<13>_MC.D2_PT_2/IN8 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_outDATA<5>\\$WA4.UIM_MC.D2_PT_1/IN1 \ 0 21865 (_entity .  X_INV)
		(_port
			((I) (\RD_II/UIM \))
			((O) (\NlwInverterSignal_outDATA<5>\\$WA4.UIM_MC.D2_PT_1/IN1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_outDATA<5>\\$WA4.UIM_MC.D2_PT_1/IN5 \ 0 21869 (_entity .  X_INV)
		(_port
			((I) (U2_ADDR_reg(2)))
			((O) (\NlwInverterSignal_outDATA<5>\\$WA4.UIM_MC.D2_PT_1/IN5 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_outDATA<5>\\$WA4.UIM_MC.D2_PT_2/IN1 \ 0 21873 (_entity .  X_INV)
		(_port
			((I) (\RD_II/UIM \))
			((O) (\NlwInverterSignal_outDATA<5>\\$WA4.UIM_MC.D2_PT_2/IN1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_outDATA<5>\\$WA4.UIM_MC.D2_PT_2/IN3 \ 0 21877 (_entity .  X_INV)
		(_port
			((I) (U2_ADDR_reg(0)))
			((O) (\NlwInverterSignal_outDATA<5>\\$WA4.UIM_MC.D2_PT_2/IN3 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_outDATA<5>\\$WA4.UIM_MC.D2_PT_2/IN5 \ 0 21881 (_entity .  X_INV)
		(_port
			((I) (U2_ADDR_reg(2)))
			((O) (\NlwInverterSignal_outDATA<5>\\$WA4.UIM_MC.D2_PT_2/IN5 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_outDATA<5>\\$WA4.UIM_MC.D2_PT_3/IN1 \ 0 21885 (_entity .  X_INV)
		(_port
			((I) (\RD_II/UIM \))
			((O) (\NlwInverterSignal_outDATA<5>\\$WA4.UIM_MC.D2_PT_3/IN1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_outDATA<5>\\$WA4.UIM_MC.D2_PT_3/IN2 \ 0 21889 (_entity .  X_INV)
		(_port
			((I) (U2_ADDR_reg(1)))
			((O) (\NlwInverterSignal_outDATA<5>\\$WA4.UIM_MC.D2_PT_3/IN2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_outDATA<5>\\$WA4.UIM_MC.D2_PT_3/IN3 \ 0 21893 (_entity .  X_INV)
		(_port
			((I) (U2_ADDR_reg(0)))
			((O) (\NlwInverterSignal_outDATA<5>\\$WA4.UIM_MC.D2_PT_3/IN3 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/U4/Latch0r<13>_MC.D2_PT_1/IN0 \ 0 21897 (_entity .  X_INV)
		(_port
			((I) (\Reset_II/UIM \))
			((O) (\NlwInverterSignal_U1/U4/Latch0r<13>_MC.D2_PT_1/IN0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/U4/Latch0r<13>_MC.D2_PT_1/IN2 \ 0 21901 (_entity .  X_INV)
		(_port
			((I) (N_PZ_1059))
			((O) (\NlwInverterSignal_U1/U4/Latch0r<13>_MC.D2_PT_1/IN2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_N_PZ_1059_MC.D2_PT_0/IN0 \ 0 21905 (_entity .  X_INV)
		(_port
			((I) (\Reset_II/UIM \))
			((O) (\NlwInverterSignal_N_PZ_1059_MC.D2_PT_0/IN0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_N_PZ_1059_MC.D2_PT_1/IN0 \ 0 21909 (_entity .  X_INV)
		(_port
			((I) (\Reset_II/UIM \))
			((O) (\NlwInverterSignal_N_PZ_1059_MC.D2_PT_1/IN0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_N_PZ_1059_MC.D2_PT_2/IN0 \ 0 21913 (_entity .  X_INV)
		(_port
			((I) (\Reset_II/UIM \))
			((O) (\NlwInverterSignal_N_PZ_1059_MC.D2_PT_2/IN0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_N_PZ_1059_MC.D2_PT_2/IN1 \ 0 21917 (_entity .  X_INV)
		(_port
			((I) (\U1/U4/LatchEdge0r \))
			((O) (\NlwInverterSignal_N_PZ_1059_MC.D2_PT_2/IN1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_N_PZ_1059_MC.D2_PT_3/IN0 \ 0 21921 (_entity .  X_INV)
		(_port
			((I) (\Reset_II/UIM \))
			((O) (\NlwInverterSignal_N_PZ_1059_MC.D2_PT_3/IN0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_N_PZ_1059_MC.D2_PT_3/IN1 \ 0 21925 (_entity .  X_INV)
		(_port
			((I) (\U1/U4/InEdge0r \))
			((O) (\NlwInverterSignal_N_PZ_1059_MC.D2_PT_3/IN1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_N_PZ_1059_MC.D2_PT_3/IN2 \ 0 21929 (_entity .  X_INV)
		(_port
			((I) (\outDATA<6>\\$WA1.UIM \))
			((O) (\NlwInverterSignal_N_PZ_1059_MC.D2_PT_3/IN2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_N_PZ_1059_MC.D2_PT_4/IN0 \ 0 21933 (_entity .  X_INV)
		(_port
			((I) (\WR_II/UIM \))
			((O) (\NlwInverterSignal_N_PZ_1059_MC.D2_PT_4/IN0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_N_PZ_1059_MC.D2_PT_4/IN4 \ 0 21937 (_entity .  X_INV)
		(_port
			((I) (U2_ADDR_reg(2)))
			((O) (\NlwInverterSignal_N_PZ_1059_MC.D2_PT_4/IN4 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_N_PZ_1059_MC.D2_PT_4/IN5 \ 0 21941 (_entity .  X_INV)
		(_port
			((I) (U2_ADDR_reg(3)))
			((O) (\NlwInverterSignal_N_PZ_1059_MC.D2_PT_4/IN5 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_N_PZ_1059_MC.D2_PT_4/IN6 \ 0 21945 (_entity .  X_INV)
		(_port
			((I) (\Reset_II/UIM \))
			((O) (\NlwInverterSignal_N_PZ_1059_MC.D2_PT_4/IN6 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_NET2501_MC.D2_PT_0/IN0 \ 0 21949 (_entity .  X_INV)
		(_port
			((I) (\Reset_II/UIM \))
			((O) (\NlwInverterSignal_NET2501_MC.D2_PT_0/IN0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_NET2501_MC.D2_PT_0/IN1 \ 0 21953 (_entity .  X_INV)
		(_port
			((I) (N_PZ_1059))
			((O) (\NlwInverterSignal_NET2501_MC.D2_PT_0/IN1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_NET2501_MC.D2_PT_1/IN0 \ 0 21957 (_entity .  X_INV)
		(_port
			((I) (\WR_II/UIM \))
			((O) (\NlwInverterSignal_NET2501_MC.D2_PT_1/IN0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_NET2501_MC.D2_PT_1/IN3 \ 0 21961 (_entity .  X_INV)
		(_port
			((I) (U2_ADDR_reg(0)))
			((O) (\NlwInverterSignal_NET2501_MC.D2_PT_1/IN3 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_NET2501_MC.D2_PT_1/IN5 \ 0 21965 (_entity .  X_INV)
		(_port
			((I) (U2_ADDR_reg(2)))
			((O) (\NlwInverterSignal_NET2501_MC.D2_PT_1/IN5 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_NET2501_MC.D2_PT_1/IN6 \ 0 21969 (_entity .  X_INV)
		(_port
			((I) (U2_ADDR_reg(3)))
			((O) (\NlwInverterSignal_NET2501_MC.D2_PT_1/IN6 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_NET2501_MC.D2_PT_1/IN7 \ 0 21973 (_entity .  X_INV)
		(_port
			((I) (\Reset_II/UIM \))
			((O) (\NlwInverterSignal_NET2501_MC.D2_PT_1/IN7 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_NET2501_MC.D2_PT_1/IN9 \ 0 21977 (_entity .  X_INV)
		(_port
			((I) (NET2501))
			((O) (\NlwInverterSignal_NET2501_MC.D2_PT_1/IN9 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_NET2501_MC.D2_PT_2/IN0 \ 0 21981 (_entity .  X_INV)
		(_port
			((I) (\WR_II/UIM \))
			((O) (\NlwInverterSignal_NET2501_MC.D2_PT_2/IN0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_NET2501_MC.D2_PT_2/IN3 \ 0 21985 (_entity .  X_INV)
		(_port
			((I) (U2_ADDR_reg(0)))
			((O) (\NlwInverterSignal_NET2501_MC.D2_PT_2/IN3 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_NET2501_MC.D2_PT_2/IN5 \ 0 21989 (_entity .  X_INV)
		(_port
			((I) (U2_ADDR_reg(2)))
			((O) (\NlwInverterSignal_NET2501_MC.D2_PT_2/IN5 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_NET2501_MC.D2_PT_2/IN6 \ 0 21993 (_entity .  X_INV)
		(_port
			((I) (U2_ADDR_reg(3)))
			((O) (\NlwInverterSignal_NET2501_MC.D2_PT_2/IN6 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_NET2501_MC.D2_PT_2/IN7 \ 0 21997 (_entity .  X_INV)
		(_port
			((I) (\Reset_II/UIM \))
			((O) (\NlwInverterSignal_NET2501_MC.D2_PT_2/IN7 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_NET2501_MC.D2_PT_2/IN8 \ 0 22001 (_entity .  X_INV)
		(_port
			((I) (\AD<5>_II/UIM \))
			((O) (\NlwInverterSignal_NET2501_MC.D2_PT_2/IN8 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/U4/LatchEdge0r_MC.D2_PT_1/IN0 \ 0 22005 (_entity .  X_INV)
		(_port
			((I) (\WR_II/UIM \))
			((O) (\NlwInverterSignal_U1/U4/LatchEdge0r_MC.D2_PT_1/IN0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/U4/LatchEdge0r_MC.D2_PT_1/IN5 \ 0 22009 (_entity .  X_INV)
		(_port
			((I) (U2_ADDR_reg(2)))
			((O) (\NlwInverterSignal_U1/U4/LatchEdge0r_MC.D2_PT_1/IN5 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/U4/LatchEdge0r_MC.D2_PT_1/IN6 \ 0 22013 (_entity .  X_INV)
		(_port
			((I) (U2_ADDR_reg(3)))
			((O) (\NlwInverterSignal_U1/U4/LatchEdge0r_MC.D2_PT_1/IN6 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/U4/LatchEdge0r_MC.D2_PT_1/IN7 \ 0 22017 (_entity .  X_INV)
		(_port
			((I) (\AD<2>_II/UIM \))
			((O) (\NlwInverterSignal_U1/U4/LatchEdge0r_MC.D2_PT_1/IN7 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/U4/LatchEdge0r_MC.D2_PT_2/IN0 \ 0 22021 (_entity .  X_INV)
		(_port
			((I) (\WR_II/UIM \))
			((O) (\NlwInverterSignal_U1/U4/LatchEdge0r_MC.D2_PT_2/IN0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/U4/LatchEdge0r_MC.D2_PT_2/IN5 \ 0 22025 (_entity .  X_INV)
		(_port
			((I) (U2_ADDR_reg(2)))
			((O) (\NlwInverterSignal_U1/U4/LatchEdge0r_MC.D2_PT_2/IN5 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/U4/LatchEdge0r_MC.D2_PT_2/IN6 \ 0 22029 (_entity .  X_INV)
		(_port
			((I) (U2_ADDR_reg(3)))
			((O) (\NlwInverterSignal_U1/U4/LatchEdge0r_MC.D2_PT_2/IN6 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/U4/LatchEdge0r_MC.D2_PT_2/IN7 \ 0 22033 (_entity .  X_INV)
		(_port
			((I) (\Reset_II/UIM \))
			((O) (\NlwInverterSignal_U1/U4/LatchEdge0r_MC.D2_PT_2/IN7 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/U4/LatchEdge0r_MC.D2_PT_2/IN9 \ 0 22037 (_entity .  X_INV)
		(_port
			((I) (\U1/U4/LatchEdge0r \))
			((O) (\NlwInverterSignal_U1/U4/LatchEdge0r_MC.D2_PT_2/IN9 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/U4/Latch0r<5>_MC.D2_PT_1/IN0 \ 0 22041 (_entity .  X_INV)
		(_port
			((I) (\Reset_II/UIM \))
			((O) (\NlwInverterSignal_U1/U4/Latch0r<5>_MC.D2_PT_1/IN0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/U4/Latch0r<5>_MC.D2_PT_1/IN2 \ 0 22045 (_entity .  X_INV)
		(_port
			((I) (N_PZ_1059))
			((O) (\NlwInverterSignal_U1/U4/Latch0r<5>_MC.D2_PT_1/IN2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/U4/Latch1r<5>_MC.D2_PT_0/IN0 \ 0 22049 (_entity .  X_INV)
		(_port
			((I) (N_PZ_978))
			((O) (\NlwInverterSignal_U1/U4/Latch1r<5>_MC.D2_PT_0/IN0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/U4/Latch1r<5>_MC.D2_PT_1/IN0 \ 0 22053 (_entity .  X_INV)
		(_port
			((I) (\WR_II/UIM \))
			((O) (\NlwInverterSignal_U1/U4/Latch1r<5>_MC.D2_PT_1/IN0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/U4/Latch1r<5>_MC.D2_PT_1/IN4 \ 0 22057 (_entity .  X_INV)
		(_port
			((I) (U2_ADDR_reg(2)))
			((O) (\NlwInverterSignal_U1/U4/Latch1r<5>_MC.D2_PT_1/IN4 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/U4/Latch1r<5>_MC.D2_PT_1/IN5 \ 0 22061 (_entity .  X_INV)
		(_port
			((I) (U2_ADDR_reg(3)))
			((O) (\NlwInverterSignal_U1/U4/Latch1r<5>_MC.D2_PT_1/IN5 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/U4/Latch1r<5>_MC.D2_PT_1/IN6 \ 0 22065 (_entity .  X_INV)
		(_port
			((I) (\Reset_II/UIM \))
			((O) (\NlwInverterSignal_U1/U4/Latch1r<5>_MC.D2_PT_1/IN6 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/U4/Latch1r<13>_MC.D2_PT_0/IN0 \ 0 22069 (_entity .  X_INV)
		(_port
			((I) (N_PZ_978))
			((O) (\NlwInverterSignal_U1/U4/Latch1r<13>_MC.D2_PT_0/IN0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/U4/Latch1r<13>_MC.D2_PT_1/IN0 \ 0 22073 (_entity .  X_INV)
		(_port
			((I) (\WR_II/UIM \))
			((O) (\NlwInverterSignal_U1/U4/Latch1r<13>_MC.D2_PT_1/IN0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/U4/Latch1r<13>_MC.D2_PT_1/IN4 \ 0 22077 (_entity .  X_INV)
		(_port
			((I) (U2_ADDR_reg(2)))
			((O) (\NlwInverterSignal_U1/U4/Latch1r<13>_MC.D2_PT_1/IN4 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/U4/Latch1r<13>_MC.D2_PT_1/IN5 \ 0 22081 (_entity .  X_INV)
		(_port
			((I) (U2_ADDR_reg(3)))
			((O) (\NlwInverterSignal_U1/U4/Latch1r<13>_MC.D2_PT_1/IN5 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/U4/Latch1r<13>_MC.D2_PT_1/IN6 \ 0 22085 (_entity .  X_INV)
		(_port
			((I) (\Reset_II/UIM \))
			((O) (\NlwInverterSignal_U1/U4/Latch1r<13>_MC.D2_PT_1/IN6 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_N_PZ_1003_MC.D2_PT_0/IN0 \ 0 22089 (_entity .  X_INV)
		(_port
			((I) (N_PZ_1060))
			((O) (\NlwInverterSignal_N_PZ_1003_MC.D2_PT_0/IN0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_N_PZ_1003_MC.D2_PT_0/IN1 \ 0 22093 (_entity .  X_INV)
		(_port
			((I) (N_PZ_1060))
			((O) (\NlwInverterSignal_N_PZ_1003_MC.D2_PT_0/IN1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_N_PZ_1060_MC.D2_PT_0/IN2 \ 0 22097 (_entity .  X_INV)
		(_port
			((I) (U2_ADDR_reg(2)))
			((O) (\NlwInverterSignal_N_PZ_1060_MC.D2_PT_0/IN2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_N_PZ_1060_MC.D2_PT_1/IN0 \ 0 22101 (_entity .  X_INV)
		(_port
			((I) (U2_ADDR_reg(1)))
			((O) (\NlwInverterSignal_N_PZ_1060_MC.D2_PT_1/IN0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_AD<6>_MC.D/IN0 \ 0 22105 (_entity .  X_INV)
		(_port
			((I) (\AD<6>_MC.D1 \))
			((O) (\NlwInverterSignal_AD<6>_MC.D/IN0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_AD<6>_MC.D2_PT_0/IN1 \ 0 22109 (_entity .  X_INV)
		(_port
			((I) (\outDATA<6>\\$WA5.UIM \))
			((O) (\NlwInverterSignal_AD<6>_MC.D2_PT_0/IN1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_AD<6>_MC.D2_PT_1/IN1 \ 0 22113 (_entity .  X_INV)
		(_port
			((I) (\outDATA<6>\\$WA4.UIM \))
			((O) (\NlwInverterSignal_AD<6>_MC.D2_PT_1/IN1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_AD<6>_MC.D2_PT_2/IN1 \ 0 22117 (_entity .  X_INV)
		(_port
			((I) (\RD_II/UIM \))
			((O) (\NlwInverterSignal_AD<6>_MC.D2_PT_2/IN1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_AD<6>_MC.D2_PT_2/IN7 \ 0 22121 (_entity .  X_INV)
		(_port
			((I) (\outDATA<6>\\$WA1.UIM \))
			((O) (\NlwInverterSignal_AD<6>_MC.D2_PT_2/IN7 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_AD<6>_MC.D2_PT_3/IN1 \ 0 22125 (_entity .  X_INV)
		(_port
			((I) (\RD_II/UIM \))
			((O) (\NlwInverterSignal_AD<6>_MC.D2_PT_3/IN1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_AD<6>_MC.D2_PT_3/IN5 \ 0 22129 (_entity .  X_INV)
		(_port
			((I) (U2_ADDR_reg(2)))
			((O) (\NlwInverterSignal_AD<6>_MC.D2_PT_3/IN5 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_AD<6>_MC.D2_PT_3/IN6 \ 0 22133 (_entity .  X_INV)
		(_port
			((I) (U2_ADDR_reg(3)))
			((O) (\NlwInverterSignal_AD<6>_MC.D2_PT_3/IN6 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_AD<6>_MC.D2_PT_3/IN7 \ 0 22137 (_entity .  X_INV)
		(_port
			((I) (\outDATA<6>\\$WA2.UIM \))
			((O) (\NlwInverterSignal_AD<6>_MC.D2_PT_3/IN7 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_AD<6>_MC.D2_PT_4/IN1 \ 0 22141 (_entity .  X_INV)
		(_port
			((I) (\RD_II/UIM \))
			((O) (\NlwInverterSignal_AD<6>_MC.D2_PT_4/IN1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_AD<6>_MC.D2_PT_4/IN3 \ 0 22145 (_entity .  X_INV)
		(_port
			((I) (U2_ADDR_reg(0)))
			((O) (\NlwInverterSignal_AD<6>_MC.D2_PT_4/IN3 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_AD<6>_MC.D2_PT_4/IN7 \ 0 22149 (_entity .  X_INV)
		(_port
			((I) (\outDATA<6>\\$WA3.UIM \))
			((O) (\NlwInverterSignal_AD<6>_MC.D2_PT_4/IN7 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_AD<6>_MC.D2_PT_5/IN1 \ 0 22153 (_entity .  X_INV)
		(_port
			((I) (\RD_II/UIM \))
			((O) (\NlwInverterSignal_AD<6>_MC.D2_PT_5/IN1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_AD<6>_MC.D2_PT_5/IN2 \ 0 22157 (_entity .  X_INV)
		(_port
			((I) (U2_ADDR_reg(1)))
			((O) (\NlwInverterSignal_AD<6>_MC.D2_PT_5/IN2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_AD<6>_MC.D2_PT_5/IN3 \ 0 22161 (_entity .  X_INV)
		(_port
			((I) (U2_ADDR_reg(0)))
			((O) (\NlwInverterSignal_AD<6>_MC.D2_PT_5/IN3 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_AD<6>_MC.D2_PT_5/IN5 \ 0 22165 (_entity .  X_INV)
		(_port
			((I) (U2_ADDR_reg(2)))
			((O) (\NlwInverterSignal_AD<6>_MC.D2_PT_5/IN5 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_AD<6>_MC.D2_PT_5/IN6 \ 0 22169 (_entity .  X_INV)
		(_port
			((I) (U2_ADDR_reg(3)))
			((O) (\NlwInverterSignal_AD<6>_MC.D2_PT_5/IN6 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_AD<6>_MC.D2_PT_5/IN7 \ 0 22173 (_entity .  X_INV)
		(_port
			((I) (\outDATA<6>\\$WA0.UIM \))
			((O) (\NlwInverterSignal_AD<6>_MC.D2_PT_5/IN7 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_outDATA<6>\\$WA3.UIM_MC.D2_PT_1/IN0 \ 0 22177 (_entity .  X_INV)
		(_port
			((I) (NET2528))
			((O) (\NlwInverterSignal_outDATA<6>\\$WA3.UIM_MC.D2_PT_1/IN0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/U3/holdingreg<6>_MC.D2_PT_1/IN0 \ 0 22181 (_entity .  X_INV)
		(_port
			((I) (\Reset_II/UIM \))
			((O) (\NlwInverterSignal_U1/U3/holdingreg<6>_MC.D2_PT_1/IN0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/U3/holdingreg<6>_MC.D2_PT_2/IN1 \ 0 22185 (_entity .  X_INV)
		(_port
			((I) (\RD_II/UIM \))
			((O) (\NlwInverterSignal_U1/U3/holdingreg<6>_MC.D2_PT_2/IN1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/U3/holdingreg<6>_MC.D2_PT_2/IN6 \ 0 22189 (_entity .  X_INV)
		(_port
			((I) (U2_ADDR_reg(3)))
			((O) (\NlwInverterSignal_U1/U3/holdingreg<6>_MC.D2_PT_2/IN6 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/U3/holdingreg<6>_MC.D2_PT_2/IN7 \ 0 22193 (_entity .  X_INV)
		(_port
			((I) (\Reset_II/UIM \))
			((O) (\NlwInverterSignal_U1/U3/holdingreg<6>_MC.D2_PT_2/IN7 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/U3/holdingreg<6>_MC.D2_PT_2/IN8 \ 0 22197 (_entity .  X_INV)
		(_port
			((I) (\U1/U3/RDedge \))
			((O) (\NlwInverterSignal_U1/U3/holdingreg<6>_MC.D2_PT_2/IN8 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/U3/holdingreg<22>_MC.D2_PT_1/IN0 \ 0 22201 (_entity .  X_INV)
		(_port
			((I) (\Reset_II/UIM \))
			((O) (\NlwInverterSignal_U1/U3/holdingreg<22>_MC.D2_PT_1/IN0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/U3/holdingreg<22>_MC.D2_PT_2/IN1 \ 0 22205 (_entity .  X_INV)
		(_port
			((I) (\RD_II/UIM \))
			((O) (\NlwInverterSignal_U1/U3/holdingreg<22>_MC.D2_PT_2/IN1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/U3/holdingreg<22>_MC.D2_PT_2/IN6 \ 0 22209 (_entity .  X_INV)
		(_port
			((I) (U2_ADDR_reg(3)))
			((O) (\NlwInverterSignal_U1/U3/holdingreg<22>_MC.D2_PT_2/IN6 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/U3/holdingreg<22>_MC.D2_PT_2/IN7 \ 0 22213 (_entity .  X_INV)
		(_port
			((I) (\Reset_II/UIM \))
			((O) (\NlwInverterSignal_U1/U3/holdingreg<22>_MC.D2_PT_2/IN7 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/U3/holdingreg<22>_MC.D2_PT_2/IN8 \ 0 22217 (_entity .  X_INV)
		(_port
			((I) (\U1/U3/RDedge \))
			((O) (\NlwInverterSignal_U1/U3/holdingreg<22>_MC.D2_PT_2/IN8 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/Channel0<22>_MC.D2_PT_0/IN0 \ 0 22221 (_entity .  X_INV)
		(_port
			((I) (N_PZ_949))
			((O) (\NlwInverterSignal_U1/Channel0<22>_MC.D2_PT_0/IN0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/Channel0<22>_MC.D2_PT_1/IN3 \ 0 22225 (_entity .  X_INV)
		(_port
			((I) (\U1/Channel0 \(21)))
			((O) (\NlwInverterSignal_U1/Channel0<22>_MC.D2_PT_1/IN3 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/Channel0<22>_MC.D2_PT_1/IN4 \ 0 22229 (_entity .  X_INV)
		(_port
			((I) (\U1/Channel0 \(13)))
			((O) (\NlwInverterSignal_U1/Channel0<22>_MC.D2_PT_1/IN4 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/Channel0<22>_MC.D2_PT_1/IN6 \ 0 22233 (_entity .  X_INV)
		(_port
			((I) (\U1/Channel0 \(14)))
			((O) (\NlwInverterSignal_U1/Channel0<22>_MC.D2_PT_1/IN6 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/Channel0<22>_MC.D2_PT_1/IN7 \ 0 22237 (_entity .  X_INV)
		(_port
			((I) (\U1/Channel0 \(15)))
			((O) (\NlwInverterSignal_U1/Channel0<22>_MC.D2_PT_1/IN7 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/Channel0<22>_MC.D2_PT_1/IN8 \ 0 22241 (_entity .  X_INV)
		(_port
			((I) (\U1/Channel0 \(16)))
			((O) (\NlwInverterSignal_U1/Channel0<22>_MC.D2_PT_1/IN8 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/Channel0<22>_MC.D2_PT_1/IN9 \ 0 22245 (_entity .  X_INV)
		(_port
			((I) (\U1/Channel0 \(17)))
			((O) (\NlwInverterSignal_U1/Channel0<22>_MC.D2_PT_1/IN9 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/Channel0<22>_MC.D2_PT_1/IN10 \ 0 22249 (_entity .  X_INV)
		(_port
			((I) (\U1/Channel0 \(18)))
			((O) (\NlwInverterSignal_U1/Channel0<22>_MC.D2_PT_1/IN10 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/Channel0<22>_MC.D2_PT_1/IN11 \ 0 22253 (_entity .  X_INV)
		(_port
			((I) (\U1/Channel0 \(19)))
			((O) (\NlwInverterSignal_U1/Channel0<22>_MC.D2_PT_1/IN11 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/Channel0<22>_MC.D2_PT_1/IN12 \ 0 22257 (_entity .  X_INV)
		(_port
			((I) (\U1/Channel0 \(20)))
			((O) (\NlwInverterSignal_U1/Channel0<22>_MC.D2_PT_1/IN12 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/Channel0<22>_MC.D2_PT_2/IN2 \ 0 22261 (_entity .  X_INV)
		(_port
			((I) (N_PZ_961))
			((O) (\NlwInverterSignal_U1/Channel0<22>_MC.D2_PT_2/IN2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/Channel0<22>_MC.D2_PT_2/IN5 \ 0 22265 (_entity .  X_INV)
		(_port
			((I) (\U1/U2/location_Maddsub__n0000__n0115 \(0)))
			((O) (\NlwInverterSignal_U1/Channel0<22>_MC.D2_PT_2/IN5 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/Channel1<22>_MC.D2_PT_0/IN0 \ 0 22269 (_entity .  X_INV)
		(_port
			((I) (N_PZ_948))
			((O) (\NlwInverterSignal_U1/Channel1<22>_MC.D2_PT_0/IN0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/Channel1<22>_MC.D2_PT_1/IN3 \ 0 22273 (_entity .  X_INV)
		(_port
			((I) (\U1/Channel1 \(21)))
			((O) (\NlwInverterSignal_U1/Channel1<22>_MC.D2_PT_1/IN3 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/Channel1<22>_MC.D2_PT_1/IN4 \ 0 22277 (_entity .  X_INV)
		(_port
			((I) (\U1/Channel1 \(13)))
			((O) (\NlwInverterSignal_U1/Channel1<22>_MC.D2_PT_1/IN4 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/Channel1<22>_MC.D2_PT_1/IN6 \ 0 22281 (_entity .  X_INV)
		(_port
			((I) (\U1/Channel1 \(14)))
			((O) (\NlwInverterSignal_U1/Channel1<22>_MC.D2_PT_1/IN6 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/Channel1<22>_MC.D2_PT_1/IN7 \ 0 22285 (_entity .  X_INV)
		(_port
			((I) (\U1/Channel1 \(15)))
			((O) (\NlwInverterSignal_U1/Channel1<22>_MC.D2_PT_1/IN7 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/Channel1<22>_MC.D2_PT_1/IN8 \ 0 22289 (_entity .  X_INV)
		(_port
			((I) (\U1/Channel1 \(16)))
			((O) (\NlwInverterSignal_U1/Channel1<22>_MC.D2_PT_1/IN8 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/Channel1<22>_MC.D2_PT_1/IN9 \ 0 22293 (_entity .  X_INV)
		(_port
			((I) (\U1/Channel1 \(17)))
			((O) (\NlwInverterSignal_U1/Channel1<22>_MC.D2_PT_1/IN9 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/Channel1<22>_MC.D2_PT_1/IN10 \ 0 22297 (_entity .  X_INV)
		(_port
			((I) (\U1/Channel1 \(18)))
			((O) (\NlwInverterSignal_U1/Channel1<22>_MC.D2_PT_1/IN10 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/Channel1<22>_MC.D2_PT_1/IN11 \ 0 22301 (_entity .  X_INV)
		(_port
			((I) (\U1/Channel1 \(19)))
			((O) (\NlwInverterSignal_U1/Channel1<22>_MC.D2_PT_1/IN11 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/Channel1<22>_MC.D2_PT_1/IN12 \ 0 22305 (_entity .  X_INV)
		(_port
			((I) (\U1/Channel1 \(20)))
			((O) (\NlwInverterSignal_U1/Channel1<22>_MC.D2_PT_1/IN12 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/Channel1<22>_MC.D2_PT_2/IN2 \ 0 22309 (_entity .  X_INV)
		(_port
			((I) (N_PZ_993))
			((O) (\NlwInverterSignal_U1/Channel1<22>_MC.D2_PT_2/IN2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/Channel1<22>_MC.D2_PT_2/IN5 \ 0 22313 (_entity .  X_INV)
		(_port
			((I) (\U1/U5/location_Maddsub__n0000__n0115 \(0)))
			((O) (\NlwInverterSignal_U1/Channel1<22>_MC.D2_PT_2/IN5 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/U3/holdingreg<14>_MC.D2_PT_1/IN0 \ 0 22317 (_entity .  X_INV)
		(_port
			((I) (\Reset_II/UIM \))
			((O) (\NlwInverterSignal_U1/U3/holdingreg<14>_MC.D2_PT_1/IN0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/U3/holdingreg<14>_MC.D2_PT_2/IN1 \ 0 22321 (_entity .  X_INV)
		(_port
			((I) (\RD_II/UIM \))
			((O) (\NlwInverterSignal_U1/U3/holdingreg<14>_MC.D2_PT_2/IN1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/U3/holdingreg<14>_MC.D2_PT_2/IN6 \ 0 22325 (_entity .  X_INV)
		(_port
			((I) (U2_ADDR_reg(3)))
			((O) (\NlwInverterSignal_U1/U3/holdingreg<14>_MC.D2_PT_2/IN6 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/U3/holdingreg<14>_MC.D2_PT_2/IN7 \ 0 22329 (_entity .  X_INV)
		(_port
			((I) (\Reset_II/UIM \))
			((O) (\NlwInverterSignal_U1/U3/holdingreg<14>_MC.D2_PT_2/IN7 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/U3/holdingreg<14>_MC.D2_PT_2/IN8 \ 0 22333 (_entity .  X_INV)
		(_port
			((I) (\U1/U3/RDedge \))
			((O) (\NlwInverterSignal_U1/U3/holdingreg<14>_MC.D2_PT_2/IN8 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_outDATA<6>\\$WA4.UIM_MC.D2_PT_1/IN1 \ 0 22337 (_entity .  X_INV)
		(_port
			((I) (\RD_II/UIM \))
			((O) (\NlwInverterSignal_outDATA<6>\\$WA4.UIM_MC.D2_PT_1/IN1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_outDATA<6>\\$WA4.UIM_MC.D2_PT_1/IN5 \ 0 22341 (_entity .  X_INV)
		(_port
			((I) (U2_ADDR_reg(2)))
			((O) (\NlwInverterSignal_outDATA<6>\\$WA4.UIM_MC.D2_PT_1/IN5 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_outDATA<6>\\$WA4.UIM_MC.D2_PT_2/IN1 \ 0 22345 (_entity .  X_INV)
		(_port
			((I) (\RD_II/UIM \))
			((O) (\NlwInverterSignal_outDATA<6>\\$WA4.UIM_MC.D2_PT_2/IN1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_outDATA<6>\\$WA4.UIM_MC.D2_PT_2/IN3 \ 0 22349 (_entity .  X_INV)
		(_port
			((I) (U2_ADDR_reg(0)))
			((O) (\NlwInverterSignal_outDATA<6>\\$WA4.UIM_MC.D2_PT_2/IN3 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_outDATA<6>\\$WA4.UIM_MC.D2_PT_2/IN5 \ 0 22353 (_entity .  X_INV)
		(_port
			((I) (U2_ADDR_reg(2)))
			((O) (\NlwInverterSignal_outDATA<6>\\$WA4.UIM_MC.D2_PT_2/IN5 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_outDATA<6>\\$WA4.UIM_MC.D2_PT_3/IN1 \ 0 22357 (_entity .  X_INV)
		(_port
			((I) (\RD_II/UIM \))
			((O) (\NlwInverterSignal_outDATA<6>\\$WA4.UIM_MC.D2_PT_3/IN1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_outDATA<6>\\$WA4.UIM_MC.D2_PT_3/IN2 \ 0 22361 (_entity .  X_INV)
		(_port
			((I) (U2_ADDR_reg(1)))
			((O) (\NlwInverterSignal_outDATA<6>\\$WA4.UIM_MC.D2_PT_3/IN2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_outDATA<6>\\$WA4.UIM_MC.D2_PT_3/IN3 \ 0 22365 (_entity .  X_INV)
		(_port
			((I) (U2_ADDR_reg(0)))
			((O) (\NlwInverterSignal_outDATA<6>\\$WA4.UIM_MC.D2_PT_3/IN3 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/U4/Latch0r<14>_MC.D2_PT_1/IN0 \ 0 22369 (_entity .  X_INV)
		(_port
			((I) (\Reset_II/UIM \))
			((O) (\NlwInverterSignal_U1/U4/Latch0r<14>_MC.D2_PT_1/IN0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/U4/Latch0r<14>_MC.D2_PT_1/IN2 \ 0 22373 (_entity .  X_INV)
		(_port
			((I) (N_PZ_1059))
			((O) (\NlwInverterSignal_U1/U4/Latch0r<14>_MC.D2_PT_1/IN2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/U4/Latch0r<6>_MC.D2_PT_1/IN0 \ 0 22377 (_entity .  X_INV)
		(_port
			((I) (\Reset_II/UIM \))
			((O) (\NlwInverterSignal_U1/U4/Latch0r<6>_MC.D2_PT_1/IN0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/U4/Latch0r<6>_MC.D2_PT_1/IN2 \ 0 22381 (_entity .  X_INV)
		(_port
			((I) (N_PZ_1059))
			((O) (\NlwInverterSignal_U1/U4/Latch0r<6>_MC.D2_PT_1/IN2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/U4/Latch1r<6>_MC.D2_PT_0/IN0 \ 0 22385 (_entity .  X_INV)
		(_port
			((I) (N_PZ_978))
			((O) (\NlwInverterSignal_U1/U4/Latch1r<6>_MC.D2_PT_0/IN0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/U4/Latch1r<6>_MC.D2_PT_1/IN0 \ 0 22389 (_entity .  X_INV)
		(_port
			((I) (\WR_II/UIM \))
			((O) (\NlwInverterSignal_U1/U4/Latch1r<6>_MC.D2_PT_1/IN0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/U4/Latch1r<6>_MC.D2_PT_1/IN4 \ 0 22393 (_entity .  X_INV)
		(_port
			((I) (U2_ADDR_reg(2)))
			((O) (\NlwInverterSignal_U1/U4/Latch1r<6>_MC.D2_PT_1/IN4 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/U4/Latch1r<6>_MC.D2_PT_1/IN5 \ 0 22397 (_entity .  X_INV)
		(_port
			((I) (U2_ADDR_reg(3)))
			((O) (\NlwInverterSignal_U1/U4/Latch1r<6>_MC.D2_PT_1/IN5 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/U4/Latch1r<6>_MC.D2_PT_1/IN6 \ 0 22401 (_entity .  X_INV)
		(_port
			((I) (\Reset_II/UIM \))
			((O) (\NlwInverterSignal_U1/U4/Latch1r<6>_MC.D2_PT_1/IN6 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/U4/Latch1r<14>_MC.D2_PT_0/IN0 \ 0 22405 (_entity .  X_INV)
		(_port
			((I) (N_PZ_978))
			((O) (\NlwInverterSignal_U1/U4/Latch1r<14>_MC.D2_PT_0/IN0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/U4/Latch1r<14>_MC.D2_PT_1/IN0 \ 0 22409 (_entity .  X_INV)
		(_port
			((I) (\WR_II/UIM \))
			((O) (\NlwInverterSignal_U1/U4/Latch1r<14>_MC.D2_PT_1/IN0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/U4/Latch1r<14>_MC.D2_PT_1/IN4 \ 0 22413 (_entity .  X_INV)
		(_port
			((I) (U2_ADDR_reg(2)))
			((O) (\NlwInverterSignal_U1/U4/Latch1r<14>_MC.D2_PT_1/IN4 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/U4/Latch1r<14>_MC.D2_PT_1/IN5 \ 0 22417 (_entity .  X_INV)
		(_port
			((I) (U2_ADDR_reg(3)))
			((O) (\NlwInverterSignal_U1/U4/Latch1r<14>_MC.D2_PT_1/IN5 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/U4/Latch1r<14>_MC.D2_PT_1/IN6 \ 0 22421 (_entity .  X_INV)
		(_port
			((I) (\Reset_II/UIM \))
			((O) (\NlwInverterSignal_U1/U4/Latch1r<14>_MC.D2_PT_1/IN6 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_AD<7>_MC.D/IN0 \ 0 22425 (_entity .  X_INV)
		(_port
			((I) (\AD<7>_MC.D1 \))
			((O) (\NlwInverterSignal_AD<7>_MC.D/IN0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_AD<7>_MC.D2_PT_0/IN1 \ 0 22429 (_entity .  X_INV)
		(_port
			((I) (\outDATA<7>\\$WA5.UIM \))
			((O) (\NlwInverterSignal_AD<7>_MC.D2_PT_0/IN1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_AD<7>_MC.D2_PT_1/IN1 \ 0 22433 (_entity .  X_INV)
		(_port
			((I) (\outDATA<7>\\$WA4.UIM \))
			((O) (\NlwInverterSignal_AD<7>_MC.D2_PT_1/IN1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_AD<7>_MC.D2_PT_2/IN1 \ 0 22437 (_entity .  X_INV)
		(_port
			((I) (\RD_II/UIM \))
			((O) (\NlwInverterSignal_AD<7>_MC.D2_PT_2/IN1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_AD<7>_MC.D2_PT_2/IN7 \ 0 22441 (_entity .  X_INV)
		(_port
			((I) (\outDATA<7>\\$WA1.UIM \))
			((O) (\NlwInverterSignal_AD<7>_MC.D2_PT_2/IN7 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_AD<7>_MC.D2_PT_3/IN1 \ 0 22445 (_entity .  X_INV)
		(_port
			((I) (\RD_II/UIM \))
			((O) (\NlwInverterSignal_AD<7>_MC.D2_PT_3/IN1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_AD<7>_MC.D2_PT_3/IN5 \ 0 22449 (_entity .  X_INV)
		(_port
			((I) (U2_ADDR_reg(2)))
			((O) (\NlwInverterSignal_AD<7>_MC.D2_PT_3/IN5 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_AD<7>_MC.D2_PT_3/IN6 \ 0 22453 (_entity .  X_INV)
		(_port
			((I) (U2_ADDR_reg(3)))
			((O) (\NlwInverterSignal_AD<7>_MC.D2_PT_3/IN6 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_AD<7>_MC.D2_PT_3/IN7 \ 0 22457 (_entity .  X_INV)
		(_port
			((I) (\outDATA<7>\\$WA2.UIM \))
			((O) (\NlwInverterSignal_AD<7>_MC.D2_PT_3/IN7 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_AD<7>_MC.D2_PT_4/IN1 \ 0 22461 (_entity .  X_INV)
		(_port
			((I) (\RD_II/UIM \))
			((O) (\NlwInverterSignal_AD<7>_MC.D2_PT_4/IN1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_AD<7>_MC.D2_PT_4/IN3 \ 0 22465 (_entity .  X_INV)
		(_port
			((I) (U2_ADDR_reg(0)))
			((O) (\NlwInverterSignal_AD<7>_MC.D2_PT_4/IN3 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_AD<7>_MC.D2_PT_4/IN7 \ 0 22469 (_entity .  X_INV)
		(_port
			((I) (\outDATA<7>\\$WA3.UIM \))
			((O) (\NlwInverterSignal_AD<7>_MC.D2_PT_4/IN7 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_AD<7>_MC.D2_PT_5/IN1 \ 0 22473 (_entity .  X_INV)
		(_port
			((I) (\RD_II/UIM \))
			((O) (\NlwInverterSignal_AD<7>_MC.D2_PT_5/IN1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_AD<7>_MC.D2_PT_5/IN2 \ 0 22477 (_entity .  X_INV)
		(_port
			((I) (U2_ADDR_reg(1)))
			((O) (\NlwInverterSignal_AD<7>_MC.D2_PT_5/IN2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_AD<7>_MC.D2_PT_5/IN3 \ 0 22481 (_entity .  X_INV)
		(_port
			((I) (U2_ADDR_reg(0)))
			((O) (\NlwInverterSignal_AD<7>_MC.D2_PT_5/IN3 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_AD<7>_MC.D2_PT_5/IN5 \ 0 22485 (_entity .  X_INV)
		(_port
			((I) (U2_ADDR_reg(2)))
			((O) (\NlwInverterSignal_AD<7>_MC.D2_PT_5/IN5 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_AD<7>_MC.D2_PT_5/IN6 \ 0 22489 (_entity .  X_INV)
		(_port
			((I) (U2_ADDR_reg(3)))
			((O) (\NlwInverterSignal_AD<7>_MC.D2_PT_5/IN6 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_AD<7>_MC.D2_PT_5/IN7 \ 0 22493 (_entity .  X_INV)
		(_port
			((I) (\outDATA<7>\\$WA0.UIM \))
			((O) (\NlwInverterSignal_AD<7>_MC.D2_PT_5/IN7 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_NET3253_MC.D2_PT_0/IN0 \ 0 22497 (_entity .  X_INV)
		(_port
			((I) (\Reset_II/UIM \))
			((O) (\NlwInverterSignal_NET3253_MC.D2_PT_0/IN0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_NET3253_MC.D2_PT_1/IN0 \ 0 22501 (_entity .  X_INV)
		(_port
			((I) (\Reset_II/UIM \))
			((O) (\NlwInverterSignal_NET3253_MC.D2_PT_1/IN0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_NET3253_MC.D2_PT_1/IN2 \ 0 22505 (_entity .  X_INV)
		(_port
			((I) (N_PZ_1186))
			((O) (\NlwInverterSignal_NET3253_MC.D2_PT_1/IN2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_NET3253_MC.D2_PT_1/IN3 \ 0 22509 (_entity .  X_INV)
		(_port
			((I) (\Brake1_II/UIM \))
			((O) (\NlwInverterSignal_NET3253_MC.D2_PT_1/IN3 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_N_PZ_1186_MC.D2_PT_0/IN0 \ 0 22513 (_entity .  X_INV)
		(_port
			((I) (\FLS1_II/UIM \))
			((O) (\NlwInverterSignal_N_PZ_1186_MC.D2_PT_0/IN0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_N_PZ_1186_MC.D2_PT_1/IN0 \ 0 22517 (_entity .  X_INV)
		(_port
			((I) (\DIR1_II/UIM \))
			((O) (\NlwInverterSignal_N_PZ_1186_MC.D2_PT_1/IN0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_N_PZ_1186_MC.D2_PT_1/IN1 \ 0 22521 (_entity .  X_INV)
		(_port
			((I) (\RLS1_II/UIM \))
			((O) (\NlwInverterSignal_N_PZ_1186_MC.D2_PT_1/IN1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_outDATA<7>\\$WA3.UIM_MC.D2_PT_1/IN0 \ 0 22525 (_entity .  X_INV)
		(_port
			((I) (NET2528))
			((O) (\NlwInverterSignal_outDATA<7>\\$WA3.UIM_MC.D2_PT_1/IN0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/U3/holdingreg<7>_MC.D2_PT_1/IN0 \ 0 22529 (_entity .  X_INV)
		(_port
			((I) (\Reset_II/UIM \))
			((O) (\NlwInverterSignal_U1/U3/holdingreg<7>_MC.D2_PT_1/IN0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/U3/holdingreg<7>_MC.D2_PT_2/IN1 \ 0 22533 (_entity .  X_INV)
		(_port
			((I) (\RD_II/UIM \))
			((O) (\NlwInverterSignal_U1/U3/holdingreg<7>_MC.D2_PT_2/IN1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/U3/holdingreg<7>_MC.D2_PT_2/IN6 \ 0 22537 (_entity .  X_INV)
		(_port
			((I) (U2_ADDR_reg(3)))
			((O) (\NlwInverterSignal_U1/U3/holdingreg<7>_MC.D2_PT_2/IN6 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/U3/holdingreg<7>_MC.D2_PT_2/IN7 \ 0 22541 (_entity .  X_INV)
		(_port
			((I) (\Reset_II/UIM \))
			((O) (\NlwInverterSignal_U1/U3/holdingreg<7>_MC.D2_PT_2/IN7 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/U3/holdingreg<7>_MC.D2_PT_2/IN8 \ 0 22545 (_entity .  X_INV)
		(_port
			((I) (\U1/U3/RDedge \))
			((O) (\NlwInverterSignal_U1/U3/holdingreg<7>_MC.D2_PT_2/IN8 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/U3/holdingreg<23>_MC.D2_PT_1/IN0 \ 0 22549 (_entity .  X_INV)
		(_port
			((I) (\Reset_II/UIM \))
			((O) (\NlwInverterSignal_U1/U3/holdingreg<23>_MC.D2_PT_1/IN0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/U3/holdingreg<23>_MC.D2_PT_2/IN1 \ 0 22553 (_entity .  X_INV)
		(_port
			((I) (\RD_II/UIM \))
			((O) (\NlwInverterSignal_U1/U3/holdingreg<23>_MC.D2_PT_2/IN1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/U3/holdingreg<23>_MC.D2_PT_2/IN6 \ 0 22557 (_entity .  X_INV)
		(_port
			((I) (U2_ADDR_reg(3)))
			((O) (\NlwInverterSignal_U1/U3/holdingreg<23>_MC.D2_PT_2/IN6 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/U3/holdingreg<23>_MC.D2_PT_2/IN7 \ 0 22561 (_entity .  X_INV)
		(_port
			((I) (\Reset_II/UIM \))
			((O) (\NlwInverterSignal_U1/U3/holdingreg<23>_MC.D2_PT_2/IN7 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/U3/holdingreg<23>_MC.D2_PT_2/IN8 \ 0 22565 (_entity .  X_INV)
		(_port
			((I) (\U1/U3/RDedge \))
			((O) (\NlwInverterSignal_U1/U3/holdingreg<23>_MC.D2_PT_2/IN8 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/Channel0<23>_MC.D2_PT_0/IN0 \ 0 22569 (_entity .  X_INV)
		(_port
			((I) (N_PZ_949))
			((O) (\NlwInverterSignal_U1/Channel0<23>_MC.D2_PT_0/IN0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/Channel0<23>_MC.D2_PT_1/IN3 \ 0 22573 (_entity .  X_INV)
		(_port
			((I) (\U1/Channel0 \(21)))
			((O) (\NlwInverterSignal_U1/Channel0<23>_MC.D2_PT_1/IN3 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/Channel0<23>_MC.D2_PT_1/IN4 \ 0 22577 (_entity .  X_INV)
		(_port
			((I) (\U1/Channel0 \(13)))
			((O) (\NlwInverterSignal_U1/Channel0<23>_MC.D2_PT_1/IN4 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/Channel0<23>_MC.D2_PT_1/IN6 \ 0 22581 (_entity .  X_INV)
		(_port
			((I) (\U1/Channel0 \(14)))
			((O) (\NlwInverterSignal_U1/Channel0<23>_MC.D2_PT_1/IN6 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/Channel0<23>_MC.D2_PT_1/IN7 \ 0 22585 (_entity .  X_INV)
		(_port
			((I) (\U1/Channel0 \(15)))
			((O) (\NlwInverterSignal_U1/Channel0<23>_MC.D2_PT_1/IN7 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/Channel0<23>_MC.D2_PT_1/IN8 \ 0 22589 (_entity .  X_INV)
		(_port
			((I) (\U1/Channel0 \(16)))
			((O) (\NlwInverterSignal_U1/Channel0<23>_MC.D2_PT_1/IN8 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/Channel0<23>_MC.D2_PT_1/IN9 \ 0 22593 (_entity .  X_INV)
		(_port
			((I) (\U1/Channel0 \(17)))
			((O) (\NlwInverterSignal_U1/Channel0<23>_MC.D2_PT_1/IN9 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/Channel0<23>_MC.D2_PT_1/IN10 \ 0 22597 (_entity .  X_INV)
		(_port
			((I) (\U1/Channel0 \(18)))
			((O) (\NlwInverterSignal_U1/Channel0<23>_MC.D2_PT_1/IN10 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/Channel0<23>_MC.D2_PT_1/IN11 \ 0 22601 (_entity .  X_INV)
		(_port
			((I) (\U1/Channel0 \(19)))
			((O) (\NlwInverterSignal_U1/Channel0<23>_MC.D2_PT_1/IN11 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/Channel0<23>_MC.D2_PT_1/IN12 \ 0 22605 (_entity .  X_INV)
		(_port
			((I) (\U1/Channel0 \(20)))
			((O) (\NlwInverterSignal_U1/Channel0<23>_MC.D2_PT_1/IN12 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/Channel0<23>_MC.D2_PT_1/IN13 \ 0 22609 (_entity .  X_INV)
		(_port
			((I) (\U1/Channel0 \(22)))
			((O) (\NlwInverterSignal_U1/Channel0<23>_MC.D2_PT_1/IN13 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/Channel0<23>_MC.D2_PT_2/IN2 \ 0 22613 (_entity .  X_INV)
		(_port
			((I) (N_PZ_961))
			((O) (\NlwInverterSignal_U1/Channel0<23>_MC.D2_PT_2/IN2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/Channel0<23>_MC.D2_PT_2/IN5 \ 0 22617 (_entity .  X_INV)
		(_port
			((I) (\U1/U2/location_Maddsub__n0000__n0115 \(0)))
			((O) (\NlwInverterSignal_U1/Channel0<23>_MC.D2_PT_2/IN5 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/Channel1<23>_MC.D2_PT_0/IN0 \ 0 22621 (_entity .  X_INV)
		(_port
			((I) (N_PZ_948))
			((O) (\NlwInverterSignal_U1/Channel1<23>_MC.D2_PT_0/IN0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/Channel1<23>_MC.D2_PT_1/IN3 \ 0 22625 (_entity .  X_INV)
		(_port
			((I) (\U1/Channel1 \(21)))
			((O) (\NlwInverterSignal_U1/Channel1<23>_MC.D2_PT_1/IN3 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/Channel1<23>_MC.D2_PT_1/IN4 \ 0 22629 (_entity .  X_INV)
		(_port
			((I) (\U1/Channel1 \(13)))
			((O) (\NlwInverterSignal_U1/Channel1<23>_MC.D2_PT_1/IN4 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/Channel1<23>_MC.D2_PT_1/IN6 \ 0 22633 (_entity .  X_INV)
		(_port
			((I) (\U1/Channel1 \(14)))
			((O) (\NlwInverterSignal_U1/Channel1<23>_MC.D2_PT_1/IN6 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/Channel1<23>_MC.D2_PT_1/IN7 \ 0 22637 (_entity .  X_INV)
		(_port
			((I) (\U1/Channel1 \(15)))
			((O) (\NlwInverterSignal_U1/Channel1<23>_MC.D2_PT_1/IN7 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/Channel1<23>_MC.D2_PT_1/IN8 \ 0 22641 (_entity .  X_INV)
		(_port
			((I) (\U1/Channel1 \(16)))
			((O) (\NlwInverterSignal_U1/Channel1<23>_MC.D2_PT_1/IN8 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/Channel1<23>_MC.D2_PT_1/IN9 \ 0 22645 (_entity .  X_INV)
		(_port
			((I) (\U1/Channel1 \(17)))
			((O) (\NlwInverterSignal_U1/Channel1<23>_MC.D2_PT_1/IN9 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/Channel1<23>_MC.D2_PT_1/IN10 \ 0 22649 (_entity .  X_INV)
		(_port
			((I) (\U1/Channel1 \(18)))
			((O) (\NlwInverterSignal_U1/Channel1<23>_MC.D2_PT_1/IN10 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/Channel1<23>_MC.D2_PT_1/IN11 \ 0 22653 (_entity .  X_INV)
		(_port
			((I) (\U1/Channel1 \(19)))
			((O) (\NlwInverterSignal_U1/Channel1<23>_MC.D2_PT_1/IN11 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/Channel1<23>_MC.D2_PT_1/IN12 \ 0 22657 (_entity .  X_INV)
		(_port
			((I) (\U1/Channel1 \(20)))
			((O) (\NlwInverterSignal_U1/Channel1<23>_MC.D2_PT_1/IN12 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/Channel1<23>_MC.D2_PT_1/IN13 \ 0 22661 (_entity .  X_INV)
		(_port
			((I) (\U1/Channel1 \(22)))
			((O) (\NlwInverterSignal_U1/Channel1<23>_MC.D2_PT_1/IN13 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/Channel1<23>_MC.D2_PT_2/IN2 \ 0 22665 (_entity .  X_INV)
		(_port
			((I) (N_PZ_993))
			((O) (\NlwInverterSignal_U1/Channel1<23>_MC.D2_PT_2/IN2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/Channel1<23>_MC.D2_PT_2/IN5 \ 0 22669 (_entity .  X_INV)
		(_port
			((I) (\U1/U5/location_Maddsub__n0000__n0115 \(0)))
			((O) (\NlwInverterSignal_U1/Channel1<23>_MC.D2_PT_2/IN5 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/U3/holdingreg<15>_MC.D2_PT_1/IN0 \ 0 22673 (_entity .  X_INV)
		(_port
			((I) (\Reset_II/UIM \))
			((O) (\NlwInverterSignal_U1/U3/holdingreg<15>_MC.D2_PT_1/IN0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/U3/holdingreg<15>_MC.D2_PT_2/IN1 \ 0 22677 (_entity .  X_INV)
		(_port
			((I) (\RD_II/UIM \))
			((O) (\NlwInverterSignal_U1/U3/holdingreg<15>_MC.D2_PT_2/IN1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/U3/holdingreg<15>_MC.D2_PT_2/IN6 \ 0 22681 (_entity .  X_INV)
		(_port
			((I) (U2_ADDR_reg(3)))
			((O) (\NlwInverterSignal_U1/U3/holdingreg<15>_MC.D2_PT_2/IN6 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/U3/holdingreg<15>_MC.D2_PT_2/IN7 \ 0 22685 (_entity .  X_INV)
		(_port
			((I) (\Reset_II/UIM \))
			((O) (\NlwInverterSignal_U1/U3/holdingreg<15>_MC.D2_PT_2/IN7 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/U3/holdingreg<15>_MC.D2_PT_2/IN8 \ 0 22689 (_entity .  X_INV)
		(_port
			((I) (\U1/U3/RDedge \))
			((O) (\NlwInverterSignal_U1/U3/holdingreg<15>_MC.D2_PT_2/IN8 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_outDATA<7>\\$WA4.UIM_MC.D2_PT_1/IN1 \ 0 22693 (_entity .  X_INV)
		(_port
			((I) (\RD_II/UIM \))
			((O) (\NlwInverterSignal_outDATA<7>\\$WA4.UIM_MC.D2_PT_1/IN1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_outDATA<7>\\$WA4.UIM_MC.D2_PT_1/IN5 \ 0 22697 (_entity .  X_INV)
		(_port
			((I) (U2_ADDR_reg(2)))
			((O) (\NlwInverterSignal_outDATA<7>\\$WA4.UIM_MC.D2_PT_1/IN5 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_outDATA<7>\\$WA4.UIM_MC.D2_PT_2/IN1 \ 0 22701 (_entity .  X_INV)
		(_port
			((I) (\RD_II/UIM \))
			((O) (\NlwInverterSignal_outDATA<7>\\$WA4.UIM_MC.D2_PT_2/IN1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_outDATA<7>\\$WA4.UIM_MC.D2_PT_2/IN3 \ 0 22705 (_entity .  X_INV)
		(_port
			((I) (U2_ADDR_reg(0)))
			((O) (\NlwInverterSignal_outDATA<7>\\$WA4.UIM_MC.D2_PT_2/IN3 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_outDATA<7>\\$WA4.UIM_MC.D2_PT_2/IN5 \ 0 22709 (_entity .  X_INV)
		(_port
			((I) (U2_ADDR_reg(2)))
			((O) (\NlwInverterSignal_outDATA<7>\\$WA4.UIM_MC.D2_PT_2/IN5 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_outDATA<7>\\$WA4.UIM_MC.D2_PT_3/IN1 \ 0 22713 (_entity .  X_INV)
		(_port
			((I) (\RD_II/UIM \))
			((O) (\NlwInverterSignal_outDATA<7>\\$WA4.UIM_MC.D2_PT_3/IN1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_outDATA<7>\\$WA4.UIM_MC.D2_PT_3/IN2 \ 0 22717 (_entity .  X_INV)
		(_port
			((I) (U2_ADDR_reg(1)))
			((O) (\NlwInverterSignal_outDATA<7>\\$WA4.UIM_MC.D2_PT_3/IN2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_outDATA<7>\\$WA4.UIM_MC.D2_PT_3/IN3 \ 0 22721 (_entity .  X_INV)
		(_port
			((I) (U2_ADDR_reg(0)))
			((O) (\NlwInverterSignal_outDATA<7>\\$WA4.UIM_MC.D2_PT_3/IN3 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/U4/Latch0r<15>_MC.D2_PT_1/IN0 \ 0 22725 (_entity .  X_INV)
		(_port
			((I) (\Reset_II/UIM \))
			((O) (\NlwInverterSignal_U1/U4/Latch0r<15>_MC.D2_PT_1/IN0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/U4/Latch0r<15>_MC.D2_PT_1/IN2 \ 0 22729 (_entity .  X_INV)
		(_port
			((I) (N_PZ_1059))
			((O) (\NlwInverterSignal_U1/U4/Latch0r<15>_MC.D2_PT_1/IN2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/U4/Latch0r<7>_MC.D2_PT_1/IN0 \ 0 22733 (_entity .  X_INV)
		(_port
			((I) (\Reset_II/UIM \))
			((O) (\NlwInverterSignal_U1/U4/Latch0r<7>_MC.D2_PT_1/IN0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/U4/Latch0r<7>_MC.D2_PT_1/IN2 \ 0 22737 (_entity .  X_INV)
		(_port
			((I) (N_PZ_1059))
			((O) (\NlwInverterSignal_U1/U4/Latch0r<7>_MC.D2_PT_1/IN2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/U4/Latch1r<7>_MC.D2_PT_0/IN0 \ 0 22741 (_entity .  X_INV)
		(_port
			((I) (N_PZ_978))
			((O) (\NlwInverterSignal_U1/U4/Latch1r<7>_MC.D2_PT_0/IN0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/U4/Latch1r<7>_MC.D2_PT_1/IN0 \ 0 22745 (_entity .  X_INV)
		(_port
			((I) (\WR_II/UIM \))
			((O) (\NlwInverterSignal_U1/U4/Latch1r<7>_MC.D2_PT_1/IN0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/U4/Latch1r<7>_MC.D2_PT_1/IN4 \ 0 22749 (_entity .  X_INV)
		(_port
			((I) (U2_ADDR_reg(2)))
			((O) (\NlwInverterSignal_U1/U4/Latch1r<7>_MC.D2_PT_1/IN4 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/U4/Latch1r<7>_MC.D2_PT_1/IN5 \ 0 22753 (_entity .  X_INV)
		(_port
			((I) (U2_ADDR_reg(3)))
			((O) (\NlwInverterSignal_U1/U4/Latch1r<7>_MC.D2_PT_1/IN5 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/U4/Latch1r<7>_MC.D2_PT_1/IN6 \ 0 22757 (_entity .  X_INV)
		(_port
			((I) (\Reset_II/UIM \))
			((O) (\NlwInverterSignal_U1/U4/Latch1r<7>_MC.D2_PT_1/IN6 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/U4/Latch1r<15>_MC.D2_PT_0/IN0 \ 0 22761 (_entity .  X_INV)
		(_port
			((I) (N_PZ_978))
			((O) (\NlwInverterSignal_U1/U4/Latch1r<15>_MC.D2_PT_0/IN0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/U4/Latch1r<15>_MC.D2_PT_1/IN0 \ 0 22765 (_entity .  X_INV)
		(_port
			((I) (\WR_II/UIM \))
			((O) (\NlwInverterSignal_U1/U4/Latch1r<15>_MC.D2_PT_1/IN0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/U4/Latch1r<15>_MC.D2_PT_1/IN4 \ 0 22769 (_entity .  X_INV)
		(_port
			((I) (U2_ADDR_reg(2)))
			((O) (\NlwInverterSignal_U1/U4/Latch1r<15>_MC.D2_PT_1/IN4 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/U4/Latch1r<15>_MC.D2_PT_1/IN5 \ 0 22773 (_entity .  X_INV)
		(_port
			((I) (U2_ADDR_reg(3)))
			((O) (\NlwInverterSignal_U1/U4/Latch1r<15>_MC.D2_PT_1/IN5 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/U4/Latch1r<15>_MC.D2_PT_1/IN6 \ 0 22777 (_entity .  X_INV)
		(_port
			((I) (\Reset_II/UIM \))
			((O) (\NlwInverterSignal_U1/U4/Latch1r<15>_MC.D2_PT_1/IN6 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_Enc05ctrl_MC.CE/IN0 \ 0 22781 (_entity .  X_INV)
		(_port
			((I) (\WR_II/UIM \))
			((O) (\NlwInverterSignal_Enc05ctrl_MC.CE/IN0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_Enc05ctrl_MC.CE/IN3 \ 0 22785 (_entity .  X_INV)
		(_port
			((I) (U2_ADDR_reg(0)))
			((O) (\NlwInverterSignal_Enc05ctrl_MC.CE/IN3 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_Enc133ctrl_MC.CE/IN0 \ 0 22789 (_entity .  X_INV)
		(_port
			((I) (\WR_II/UIM \))
			((O) (\NlwInverterSignal_Enc133ctrl_MC.CE/IN0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_Enc133ctrl_MC.CE/IN3 \ 0 22793 (_entity .  X_INV)
		(_port
			((I) (U2_ADDR_reg(0)))
			((O) (\NlwInverterSignal_Enc133ctrl_MC.CE/IN3 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_Enc15ctrl_MC.CE/IN0 \ 0 22797 (_entity .  X_INV)
		(_port
			((I) (\WR_II/UIM \))
			((O) (\NlwInverterSignal_Enc15ctrl_MC.CE/IN0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_Enc15ctrl_MC.CE/IN3 \ 0 22801 (_entity .  X_INV)
		(_port
			((I) (U2_ADDR_reg(0)))
			((O) (\NlwInverterSignal_Enc15ctrl_MC.CE/IN3 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_Home033ctrl_MC.CE/IN0 \ 0 22805 (_entity .  X_INV)
		(_port
			((I) (\WR_II/UIM \))
			((O) (\NlwInverterSignal_Home033ctrl_MC.CE/IN0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_Home033ctrl_MC.CE/IN3 \ 0 22809 (_entity .  X_INV)
		(_port
			((I) (U2_ADDR_reg(0)))
			((O) (\NlwInverterSignal_Home033ctrl_MC.CE/IN3 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_Home15ctrl_MC.CE/IN0 \ 0 22813 (_entity .  X_INV)
		(_port
			((I) (\WR_II/UIM \))
			((O) (\NlwInverterSignal_Home15ctrl_MC.CE/IN0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_Home15ctrl_MC.CE/IN3 \ 0 22817 (_entity .  X_INV)
		(_port
			((I) (U2_ADDR_reg(0)))
			((O) (\NlwInverterSignal_Home15ctrl_MC.CE/IN3 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_INT_MC.D2_PT_7/IN0 \ 0 22821 (_entity .  X_INV)
		(_port
			((I) (U11_U3_counterr(5)))
			((O) (\NlwInverterSignal_INT_MC.D2_PT_7/IN0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_INT_MC.D2_PT_7/IN1 \ 0 22825 (_entity .  X_INV)
		(_port
			((I) (U11_U3_counterr(3)))
			((O) (\NlwInverterSignal_INT_MC.D2_PT_7/IN1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_INT_MC.D2_PT_7/IN2 \ 0 22829 (_entity .  X_INV)
		(_port
			((I) (U11_U3_counterr(4)))
			((O) (\NlwInverterSignal_INT_MC.D2_PT_7/IN2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_INT_MC.D2_PT_7/IN3 \ 0 22833 (_entity .  X_INV)
		(_port
			((I) (U11_U3_counterr(0)))
			((O) (\NlwInverterSignal_INT_MC.D2_PT_7/IN3 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_INT_MC.D2_PT_7/IN4 \ 0 22837 (_entity .  X_INV)
		(_port
			((I) (U11_U3_counterr(1)))
			((O) (\NlwInverterSignal_INT_MC.D2_PT_7/IN4 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_INT_MC.D2_PT_7/IN5 \ 0 22841 (_entity .  X_INV)
		(_port
			((I) (U11_U3_counterr(2)))
			((O) (\NlwInverterSignal_INT_MC.D2_PT_7/IN5 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U3/DCORIE<0>_MC.D2_PT_1/IN0 \ 0 22845 (_entity .  X_INV)
		(_port
			((I) (\WR_II/UIM \))
			((O) (\NlwInverterSignal_U3/DCORIE<0>_MC.D2_PT_1/IN0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U3/DCORIE<0>_MC.D2_PT_1/IN2 \ 0 22849 (_entity .  X_INV)
		(_port
			((I) (U2_ADDR_reg(1)))
			((O) (\NlwInverterSignal_U3/DCORIE<0>_MC.D2_PT_1/IN2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U3/DCORIE<0>_MC.D2_PT_1/IN5 \ 0 22853 (_entity .  X_INV)
		(_port
			((I) (U2_ADDR_reg(2)))
			((O) (\NlwInverterSignal_U3/DCORIE<0>_MC.D2_PT_1/IN5 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U3/DCORIE<0>_MC.D2_PT_1/IN6 \ 0 22857 (_entity .  X_INV)
		(_port
			((I) (U2_ADDR_reg(3)))
			((O) (\NlwInverterSignal_U3/DCORIE<0>_MC.D2_PT_1/IN6 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U3/DCORIE<0>_MC.D2_PT_1/IN7 \ 0 22861 (_entity .  X_INV)
		(_port
			((I) (\AD<0>_II/UIM \))
			((O) (\NlwInverterSignal_U3/DCORIE<0>_MC.D2_PT_1/IN7 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U3/DCORIE<0>_MC.D2_PT_2/IN0 \ 0 22865 (_entity .  X_INV)
		(_port
			((I) (\WR_II/UIM \))
			((O) (\NlwInverterSignal_U3/DCORIE<0>_MC.D2_PT_2/IN0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U3/DCORIE<0>_MC.D2_PT_2/IN2 \ 0 22869 (_entity .  X_INV)
		(_port
			((I) (U2_ADDR_reg(1)))
			((O) (\NlwInverterSignal_U3/DCORIE<0>_MC.D2_PT_2/IN2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U3/DCORIE<0>_MC.D2_PT_2/IN5 \ 0 22873 (_entity .  X_INV)
		(_port
			((I) (U2_ADDR_reg(2)))
			((O) (\NlwInverterSignal_U3/DCORIE<0>_MC.D2_PT_2/IN5 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U3/DCORIE<0>_MC.D2_PT_2/IN6 \ 0 22877 (_entity .  X_INV)
		(_port
			((I) (U2_ADDR_reg(3)))
			((O) (\NlwInverterSignal_U3/DCORIE<0>_MC.D2_PT_2/IN6 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U3/DCORIE<0>_MC.D2_PT_2/IN7 \ 0 22881 (_entity .  X_INV)
		(_port
			((I) (\Reset_II/UIM \))
			((O) (\NlwInverterSignal_U3/DCORIE<0>_MC.D2_PT_2/IN7 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U3/DCORIE<0>_MC.D2_PT_2/IN9 \ 0 22885 (_entity .  X_INV)
		(_port
			((I) (\U3/DCORIE \(0)))
			((O) (\NlwInverterSignal_U3/DCORIE<0>_MC.D2_PT_2/IN9 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U3/DCORIE<1>_MC.D2_PT_1/IN0 \ 0 22889 (_entity .  X_INV)
		(_port
			((I) (\WR_II/UIM \))
			((O) (\NlwInverterSignal_U3/DCORIE<1>_MC.D2_PT_1/IN0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U3/DCORIE<1>_MC.D2_PT_1/IN2 \ 0 22893 (_entity .  X_INV)
		(_port
			((I) (U2_ADDR_reg(1)))
			((O) (\NlwInverterSignal_U3/DCORIE<1>_MC.D2_PT_1/IN2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U3/DCORIE<1>_MC.D2_PT_1/IN5 \ 0 22897 (_entity .  X_INV)
		(_port
			((I) (U2_ADDR_reg(2)))
			((O) (\NlwInverterSignal_U3/DCORIE<1>_MC.D2_PT_1/IN5 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U3/DCORIE<1>_MC.D2_PT_1/IN6 \ 0 22901 (_entity .  X_INV)
		(_port
			((I) (U2_ADDR_reg(3)))
			((O) (\NlwInverterSignal_U3/DCORIE<1>_MC.D2_PT_1/IN6 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U3/DCORIE<1>_MC.D2_PT_1/IN7 \ 0 22905 (_entity .  X_INV)
		(_port
			((I) (\AD<1>_II/UIM \))
			((O) (\NlwInverterSignal_U3/DCORIE<1>_MC.D2_PT_1/IN7 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U3/DCORIE<1>_MC.D2_PT_2/IN0 \ 0 22909 (_entity .  X_INV)
		(_port
			((I) (\WR_II/UIM \))
			((O) (\NlwInverterSignal_U3/DCORIE<1>_MC.D2_PT_2/IN0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U3/DCORIE<1>_MC.D2_PT_2/IN2 \ 0 22913 (_entity .  X_INV)
		(_port
			((I) (U2_ADDR_reg(1)))
			((O) (\NlwInverterSignal_U3/DCORIE<1>_MC.D2_PT_2/IN2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U3/DCORIE<1>_MC.D2_PT_2/IN5 \ 0 22917 (_entity .  X_INV)
		(_port
			((I) (U2_ADDR_reg(2)))
			((O) (\NlwInverterSignal_U3/DCORIE<1>_MC.D2_PT_2/IN5 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U3/DCORIE<1>_MC.D2_PT_2/IN6 \ 0 22921 (_entity .  X_INV)
		(_port
			((I) (U2_ADDR_reg(3)))
			((O) (\NlwInverterSignal_U3/DCORIE<1>_MC.D2_PT_2/IN6 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U3/DCORIE<1>_MC.D2_PT_2/IN8 \ 0 22925 (_entity .  X_INV)
		(_port
			((I) (\Reset_II/UIM \))
			((O) (\NlwInverterSignal_U3/DCORIE<1>_MC.D2_PT_2/IN8 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U3/DCORIE<1>_MC.D2_PT_2/IN9 \ 0 22929 (_entity .  X_INV)
		(_port
			((I) (\U3/DCORIE \(1)))
			((O) (\NlwInverterSignal_U3/DCORIE<1>_MC.D2_PT_2/IN9 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U3/DCORIE<2>_MC.D2_PT_1/IN0 \ 0 22933 (_entity .  X_INV)
		(_port
			((I) (\WR_II/UIM \))
			((O) (\NlwInverterSignal_U3/DCORIE<2>_MC.D2_PT_1/IN0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U3/DCORIE<2>_MC.D2_PT_1/IN2 \ 0 22937 (_entity .  X_INV)
		(_port
			((I) (U2_ADDR_reg(1)))
			((O) (\NlwInverterSignal_U3/DCORIE<2>_MC.D2_PT_1/IN2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U3/DCORIE<2>_MC.D2_PT_1/IN5 \ 0 22941 (_entity .  X_INV)
		(_port
			((I) (U2_ADDR_reg(2)))
			((O) (\NlwInverterSignal_U3/DCORIE<2>_MC.D2_PT_1/IN5 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U3/DCORIE<2>_MC.D2_PT_1/IN6 \ 0 22945 (_entity .  X_INV)
		(_port
			((I) (U2_ADDR_reg(3)))
			((O) (\NlwInverterSignal_U3/DCORIE<2>_MC.D2_PT_1/IN6 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U3/DCORIE<2>_MC.D2_PT_1/IN7 \ 0 22949 (_entity .  X_INV)
		(_port
			((I) (\AD<2>_II/UIM \))
			((O) (\NlwInverterSignal_U3/DCORIE<2>_MC.D2_PT_1/IN7 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U3/DCORIE<2>_MC.D2_PT_2/IN0 \ 0 22953 (_entity .  X_INV)
		(_port
			((I) (\WR_II/UIM \))
			((O) (\NlwInverterSignal_U3/DCORIE<2>_MC.D2_PT_2/IN0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U3/DCORIE<2>_MC.D2_PT_2/IN2 \ 0 22957 (_entity .  X_INV)
		(_port
			((I) (U2_ADDR_reg(1)))
			((O) (\NlwInverterSignal_U3/DCORIE<2>_MC.D2_PT_2/IN2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U3/DCORIE<2>_MC.D2_PT_2/IN5 \ 0 22961 (_entity .  X_INV)
		(_port
			((I) (U2_ADDR_reg(2)))
			((O) (\NlwInverterSignal_U3/DCORIE<2>_MC.D2_PT_2/IN5 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U3/DCORIE<2>_MC.D2_PT_2/IN6 \ 0 22965 (_entity .  X_INV)
		(_port
			((I) (U2_ADDR_reg(3)))
			((O) (\NlwInverterSignal_U3/DCORIE<2>_MC.D2_PT_2/IN6 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U3/DCORIE<2>_MC.D2_PT_2/IN7 \ 0 22969 (_entity .  X_INV)
		(_port
			((I) (\Reset_II/UIM \))
			((O) (\NlwInverterSignal_U3/DCORIE<2>_MC.D2_PT_2/IN7 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U3/DCORIE<2>_MC.D2_PT_2/IN9 \ 0 22973 (_entity .  X_INV)
		(_port
			((I) (\U3/DCORIE \(2)))
			((O) (\NlwInverterSignal_U3/DCORIE<2>_MC.D2_PT_2/IN9 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U3/DCORIE<3>_MC.D2_PT_1/IN0 \ 0 22977 (_entity .  X_INV)
		(_port
			((I) (\WR_II/UIM \))
			((O) (\NlwInverterSignal_U3/DCORIE<3>_MC.D2_PT_1/IN0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U3/DCORIE<3>_MC.D2_PT_1/IN2 \ 0 22981 (_entity .  X_INV)
		(_port
			((I) (U2_ADDR_reg(1)))
			((O) (\NlwInverterSignal_U3/DCORIE<3>_MC.D2_PT_1/IN2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U3/DCORIE<3>_MC.D2_PT_1/IN5 \ 0 22985 (_entity .  X_INV)
		(_port
			((I) (U2_ADDR_reg(2)))
			((O) (\NlwInverterSignal_U3/DCORIE<3>_MC.D2_PT_1/IN5 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U3/DCORIE<3>_MC.D2_PT_1/IN6 \ 0 22989 (_entity .  X_INV)
		(_port
			((I) (U2_ADDR_reg(3)))
			((O) (\NlwInverterSignal_U3/DCORIE<3>_MC.D2_PT_1/IN6 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U3/DCORIE<3>_MC.D2_PT_1/IN7 \ 0 22993 (_entity .  X_INV)
		(_port
			((I) (\AD<3>_II/UIM \))
			((O) (\NlwInverterSignal_U3/DCORIE<3>_MC.D2_PT_1/IN7 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U3/DCORIE<3>_MC.D2_PT_2/IN0 \ 0 22997 (_entity .  X_INV)
		(_port
			((I) (\WR_II/UIM \))
			((O) (\NlwInverterSignal_U3/DCORIE<3>_MC.D2_PT_2/IN0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U3/DCORIE<3>_MC.D2_PT_2/IN2 \ 0 23001 (_entity .  X_INV)
		(_port
			((I) (U2_ADDR_reg(1)))
			((O) (\NlwInverterSignal_U3/DCORIE<3>_MC.D2_PT_2/IN2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U3/DCORIE<3>_MC.D2_PT_2/IN5 \ 0 23005 (_entity .  X_INV)
		(_port
			((I) (U2_ADDR_reg(2)))
			((O) (\NlwInverterSignal_U3/DCORIE<3>_MC.D2_PT_2/IN5 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U3/DCORIE<3>_MC.D2_PT_2/IN6 \ 0 23009 (_entity .  X_INV)
		(_port
			((I) (U2_ADDR_reg(3)))
			((O) (\NlwInverterSignal_U3/DCORIE<3>_MC.D2_PT_2/IN6 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U3/DCORIE<3>_MC.D2_PT_2/IN7 \ 0 23013 (_entity .  X_INV)
		(_port
			((I) (\Reset_II/UIM \))
			((O) (\NlwInverterSignal_U3/DCORIE<3>_MC.D2_PT_2/IN7 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U3/DCORIE<3>_MC.D2_PT_2/IN9 \ 0 23017 (_entity .  X_INV)
		(_port
			((I) (\U3/DCORIE \(3)))
			((O) (\NlwInverterSignal_U3/DCORIE<3>_MC.D2_PT_2/IN9 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_NET2575_MC.D2_PT_1/IN0 \ 0 23021 (_entity .  X_INV)
		(_port
			((I) (\Reset_II/UIM \))
			((O) (\NlwInverterSignal_NET2575_MC.D2_PT_1/IN0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_NET2575_MC.D2_PT_1/IN2 \ 0 23025 (_entity .  X_INV)
		(_port
			((I) (NET2575))
			((O) (\NlwInverterSignal_NET2575_MC.D2_PT_1/IN2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_NET2575_MC.D2_PT_2/IN0 \ 0 23029 (_entity .  X_INV)
		(_port
			((I) (\Reset_II/UIM \))
			((O) (\NlwInverterSignal_NET2575_MC.D2_PT_2/IN0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_NET2575_MC.D2_PT_2/IN2 \ 0 23033 (_entity .  X_INV)
		(_port
			((I) (\FLS0_II/UIM \))
			((O) (\NlwInverterSignal_NET2575_MC.D2_PT_2/IN2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_NET2575_MC.D2_PT_2/IN3 \ 0 23037 (_entity .  X_INV)
		(_port
			((I) (NET2575))
			((O) (\NlwInverterSignal_NET2575_MC.D2_PT_2/IN3 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_NET2575_MC.D2_PT_3/IN0 \ 0 23041 (_entity .  X_INV)
		(_port
			((I) (\Reset_II/UIM \))
			((O) (\NlwInverterSignal_NET2575_MC.D2_PT_3/IN0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_NET2575_MC.D2_PT_3/IN1 \ 0 23045 (_entity .  X_INV)
		(_port
			((I) (\DIR0_II/UIM \))
			((O) (\NlwInverterSignal_NET2575_MC.D2_PT_3/IN1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_NET2575_MC.D2_PT_3/IN2 \ 0 23049 (_entity .  X_INV)
		(_port
			((I) (NET2575))
			((O) (\NlwInverterSignal_NET2575_MC.D2_PT_3/IN2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_NET2575_MC.D2_PT_3/IN3 \ 0 23053 (_entity .  X_INV)
		(_port
			((I) (\RLS0_II/UIM \))
			((O) (\NlwInverterSignal_NET2575_MC.D2_PT_3/IN3 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_NET2575_MC.D2_PT_4/IN0 \ 0 23057 (_entity .  X_INV)
		(_port
			((I) (\WR_II/UIM \))
			((O) (\NlwInverterSignal_NET2575_MC.D2_PT_4/IN0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_NET2575_MC.D2_PT_4/IN3 \ 0 23061 (_entity .  X_INV)
		(_port
			((I) (U2_ADDR_reg(0)))
			((O) (\NlwInverterSignal_NET2575_MC.D2_PT_4/IN3 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_NET2575_MC.D2_PT_4/IN5 \ 0 23065 (_entity .  X_INV)
		(_port
			((I) (U2_ADDR_reg(2)))
			((O) (\NlwInverterSignal_NET2575_MC.D2_PT_4/IN5 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_NET2575_MC.D2_PT_4/IN6 \ 0 23069 (_entity .  X_INV)
		(_port
			((I) (U2_ADDR_reg(3)))
			((O) (\NlwInverterSignal_NET2575_MC.D2_PT_4/IN6 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_NET2575_MC.D2_PT_4/IN7 \ 0 23073 (_entity .  X_INV)
		(_port
			((I) (\Reset_II/UIM \))
			((O) (\NlwInverterSignal_NET2575_MC.D2_PT_4/IN7 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_NET2575_MC.D2_PT_4/IN9 \ 0 23077 (_entity .  X_INV)
		(_port
			((I) (NET2575))
			((O) (\NlwInverterSignal_NET2575_MC.D2_PT_4/IN9 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_NET2575_MC.D2_PT_5/IN0 \ 0 23081 (_entity .  X_INV)
		(_port
			((I) (\WR_II/UIM \))
			((O) (\NlwInverterSignal_NET2575_MC.D2_PT_5/IN0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_NET2575_MC.D2_PT_5/IN3 \ 0 23085 (_entity .  X_INV)
		(_port
			((I) (U2_ADDR_reg(0)))
			((O) (\NlwInverterSignal_NET2575_MC.D2_PT_5/IN3 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_NET2575_MC.D2_PT_5/IN5 \ 0 23089 (_entity .  X_INV)
		(_port
			((I) (U2_ADDR_reg(2)))
			((O) (\NlwInverterSignal_NET2575_MC.D2_PT_5/IN5 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_NET2575_MC.D2_PT_5/IN6 \ 0 23093 (_entity .  X_INV)
		(_port
			((I) (U2_ADDR_reg(3)))
			((O) (\NlwInverterSignal_NET2575_MC.D2_PT_5/IN6 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_NET2575_MC.D2_PT_5/IN7 \ 0 23097 (_entity .  X_INV)
		(_port
			((I) (\AD<4>_II/UIM \))
			((O) (\NlwInverterSignal_NET2575_MC.D2_PT_5/IN7 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_NET2575_MC.D2_PT_5/IN8 \ 0 23101 (_entity .  X_INV)
		(_port
			((I) (N_PZ_1186))
			((O) (\NlwInverterSignal_NET2575_MC.D2_PT_5/IN8 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_NET2575_MC.D2_PT_6/IN0 \ 0 23105 (_entity .  X_INV)
		(_port
			((I) (\WR_II/UIM \))
			((O) (\NlwInverterSignal_NET2575_MC.D2_PT_6/IN0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_NET2575_MC.D2_PT_6/IN3 \ 0 23109 (_entity .  X_INV)
		(_port
			((I) (U2_ADDR_reg(0)))
			((O) (\NlwInverterSignal_NET2575_MC.D2_PT_6/IN3 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_NET2575_MC.D2_PT_6/IN5 \ 0 23113 (_entity .  X_INV)
		(_port
			((I) (U2_ADDR_reg(2)))
			((O) (\NlwInverterSignal_NET2575_MC.D2_PT_6/IN5 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_NET2575_MC.D2_PT_6/IN6 \ 0 23117 (_entity .  X_INV)
		(_port
			((I) (U2_ADDR_reg(3)))
			((O) (\NlwInverterSignal_NET2575_MC.D2_PT_6/IN6 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_NET2575_MC.D2_PT_6/IN7 \ 0 23121 (_entity .  X_INV)
		(_port
			((I) (\AD<4>_II/UIM \))
			((O) (\NlwInverterSignal_NET2575_MC.D2_PT_6/IN7 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_NET2575_MC.D2_PT_6/IN8 \ 0 23125 (_entity .  X_INV)
		(_port
			((I) (N_PZ_1186))
			((O) (\NlwInverterSignal_NET2575_MC.D2_PT_6/IN8 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_NET2575_MC.D2_PT_6/IN9 \ 0 23129 (_entity .  X_INV)
		(_port
			((I) (\DIR0_II/UIM \))
			((O) (\NlwInverterSignal_NET2575_MC.D2_PT_6/IN9 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U3/DCORIE<4>_MC.D2_PT_1/IN0 \ 0 23133 (_entity .  X_INV)
		(_port
			((I) (\WR_II/UIM \))
			((O) (\NlwInverterSignal_U3/DCORIE<4>_MC.D2_PT_1/IN0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U3/DCORIE<4>_MC.D2_PT_1/IN2 \ 0 23137 (_entity .  X_INV)
		(_port
			((I) (U2_ADDR_reg(1)))
			((O) (\NlwInverterSignal_U3/DCORIE<4>_MC.D2_PT_1/IN2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U3/DCORIE<4>_MC.D2_PT_1/IN5 \ 0 23141 (_entity .  X_INV)
		(_port
			((I) (U2_ADDR_reg(2)))
			((O) (\NlwInverterSignal_U3/DCORIE<4>_MC.D2_PT_1/IN5 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U3/DCORIE<4>_MC.D2_PT_1/IN6 \ 0 23145 (_entity .  X_INV)
		(_port
			((I) (U2_ADDR_reg(3)))
			((O) (\NlwInverterSignal_U3/DCORIE<4>_MC.D2_PT_1/IN6 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U3/DCORIE<4>_MC.D2_PT_1/IN7 \ 0 23149 (_entity .  X_INV)
		(_port
			((I) (\AD<4>_II/UIM \))
			((O) (\NlwInverterSignal_U3/DCORIE<4>_MC.D2_PT_1/IN7 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U3/DCORIE<4>_MC.D2_PT_2/IN0 \ 0 23153 (_entity .  X_INV)
		(_port
			((I) (\WR_II/UIM \))
			((O) (\NlwInverterSignal_U3/DCORIE<4>_MC.D2_PT_2/IN0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U3/DCORIE<4>_MC.D2_PT_2/IN2 \ 0 23157 (_entity .  X_INV)
		(_port
			((I) (U2_ADDR_reg(1)))
			((O) (\NlwInverterSignal_U3/DCORIE<4>_MC.D2_PT_2/IN2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U3/DCORIE<4>_MC.D2_PT_2/IN5 \ 0 23161 (_entity .  X_INV)
		(_port
			((I) (U2_ADDR_reg(2)))
			((O) (\NlwInverterSignal_U3/DCORIE<4>_MC.D2_PT_2/IN5 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U3/DCORIE<4>_MC.D2_PT_2/IN6 \ 0 23165 (_entity .  X_INV)
		(_port
			((I) (U2_ADDR_reg(3)))
			((O) (\NlwInverterSignal_U3/DCORIE<4>_MC.D2_PT_2/IN6 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U3/DCORIE<4>_MC.D2_PT_2/IN7 \ 0 23169 (_entity .  X_INV)
		(_port
			((I) (\Reset_II/UIM \))
			((O) (\NlwInverterSignal_U3/DCORIE<4>_MC.D2_PT_2/IN7 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U3/DCORIE<4>_MC.D2_PT_2/IN9 \ 0 23173 (_entity .  X_INV)
		(_port
			((I) (\U3/DCORIE \(4)))
			((O) (\NlwInverterSignal_U3/DCORIE<4>_MC.D2_PT_2/IN9 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U3/DCORIE<5>_MC.D2_PT_1/IN0 \ 0 23177 (_entity .  X_INV)
		(_port
			((I) (\WR_II/UIM \))
			((O) (\NlwInverterSignal_U3/DCORIE<5>_MC.D2_PT_1/IN0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U3/DCORIE<5>_MC.D2_PT_1/IN2 \ 0 23181 (_entity .  X_INV)
		(_port
			((I) (U2_ADDR_reg(1)))
			((O) (\NlwInverterSignal_U3/DCORIE<5>_MC.D2_PT_1/IN2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U3/DCORIE<5>_MC.D2_PT_1/IN5 \ 0 23185 (_entity .  X_INV)
		(_port
			((I) (U2_ADDR_reg(2)))
			((O) (\NlwInverterSignal_U3/DCORIE<5>_MC.D2_PT_1/IN5 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U3/DCORIE<5>_MC.D2_PT_1/IN6 \ 0 23189 (_entity .  X_INV)
		(_port
			((I) (U2_ADDR_reg(3)))
			((O) (\NlwInverterSignal_U3/DCORIE<5>_MC.D2_PT_1/IN6 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U3/DCORIE<5>_MC.D2_PT_1/IN7 \ 0 23193 (_entity .  X_INV)
		(_port
			((I) (\AD<5>_II/UIM \))
			((O) (\NlwInverterSignal_U3/DCORIE<5>_MC.D2_PT_1/IN7 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U3/DCORIE<5>_MC.D2_PT_2/IN0 \ 0 23197 (_entity .  X_INV)
		(_port
			((I) (\WR_II/UIM \))
			((O) (\NlwInverterSignal_U3/DCORIE<5>_MC.D2_PT_2/IN0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U3/DCORIE<5>_MC.D2_PT_2/IN2 \ 0 23201 (_entity .  X_INV)
		(_port
			((I) (U2_ADDR_reg(1)))
			((O) (\NlwInverterSignal_U3/DCORIE<5>_MC.D2_PT_2/IN2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U3/DCORIE<5>_MC.D2_PT_2/IN5 \ 0 23205 (_entity .  X_INV)
		(_port
			((I) (U2_ADDR_reg(2)))
			((O) (\NlwInverterSignal_U3/DCORIE<5>_MC.D2_PT_2/IN5 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U3/DCORIE<5>_MC.D2_PT_2/IN6 \ 0 23209 (_entity .  X_INV)
		(_port
			((I) (U2_ADDR_reg(3)))
			((O) (\NlwInverterSignal_U3/DCORIE<5>_MC.D2_PT_2/IN6 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U3/DCORIE<5>_MC.D2_PT_2/IN7 \ 0 23213 (_entity .  X_INV)
		(_port
			((I) (\Reset_II/UIM \))
			((O) (\NlwInverterSignal_U3/DCORIE<5>_MC.D2_PT_2/IN7 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U3/DCORIE<5>_MC.D2_PT_2/IN9 \ 0 23217 (_entity .  X_INV)
		(_port
			((I) (\U3/DCORIE \(5)))
			((O) (\NlwInverterSignal_U3/DCORIE<5>_MC.D2_PT_2/IN9 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_NET2512_MC.D2_PT_0/IN0 \ 0 23221 (_entity .  X_INV)
		(_port
			((I) (N_PZ_978))
			((O) (\NlwInverterSignal_NET2512_MC.D2_PT_0/IN0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_NET2512_MC.D2_PT_0/IN2 \ 0 23225 (_entity .  X_INV)
		(_port
			((I) (NET2512))
			((O) (\NlwInverterSignal_NET2512_MC.D2_PT_0/IN2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_NET2512_MC.D2_PT_0/IN4 \ 0 23229 (_entity .  X_INV)
		(_port
			((I) (\U1/U4/InEdge1r \))
			((O) (\NlwInverterSignal_NET2512_MC.D2_PT_0/IN4 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_NET2512_MC.D2_PT_1/IN0 \ 0 23233 (_entity .  X_INV)
		(_port
			((I) (N_PZ_978))
			((O) (\NlwInverterSignal_NET2512_MC.D2_PT_1/IN0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_NET2512_MC.D2_PT_1/IN1 \ 0 23237 (_entity .  X_INV)
		(_port
			((I) (\GP_Motor1_0_II/UIM \))
			((O) (\NlwInverterSignal_NET2512_MC.D2_PT_1/IN1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_NET2512_MC.D2_PT_1/IN2 \ 0 23241 (_entity .  X_INV)
		(_port
			((I) (NET2512))
			((O) (\NlwInverterSignal_NET2512_MC.D2_PT_1/IN2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_NET2512_MC.D2_PT_1/IN3 \ 0 23245 (_entity .  X_INV)
		(_port
			((I) (\U1/U4/LatchEdge1r \))
			((O) (\NlwInverterSignal_NET2512_MC.D2_PT_1/IN3 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_NET2512_MC.D2_PT_2/IN0 \ 0 23249 (_entity .  X_INV)
		(_port
			((I) (\WR_II/UIM \))
			((O) (\NlwInverterSignal_NET2512_MC.D2_PT_2/IN0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_NET2512_MC.D2_PT_2/IN3 \ 0 23253 (_entity .  X_INV)
		(_port
			((I) (U2_ADDR_reg(0)))
			((O) (\NlwInverterSignal_NET2512_MC.D2_PT_2/IN3 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_NET2512_MC.D2_PT_2/IN5 \ 0 23257 (_entity .  X_INV)
		(_port
			((I) (U2_ADDR_reg(2)))
			((O) (\NlwInverterSignal_NET2512_MC.D2_PT_2/IN5 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_NET2512_MC.D2_PT_2/IN6 \ 0 23261 (_entity .  X_INV)
		(_port
			((I) (U2_ADDR_reg(3)))
			((O) (\NlwInverterSignal_NET2512_MC.D2_PT_2/IN6 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_NET2512_MC.D2_PT_2/IN7 \ 0 23265 (_entity .  X_INV)
		(_port
			((I) (\Reset_II/UIM \))
			((O) (\NlwInverterSignal_NET2512_MC.D2_PT_2/IN7 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_NET2512_MC.D2_PT_2/IN9 \ 0 23269 (_entity .  X_INV)
		(_port
			((I) (NET2512))
			((O) (\NlwInverterSignal_NET2512_MC.D2_PT_2/IN9 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_NET2512_MC.D2_PT_3/IN0 \ 0 23273 (_entity .  X_INV)
		(_port
			((I) (\WR_II/UIM \))
			((O) (\NlwInverterSignal_NET2512_MC.D2_PT_3/IN0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_NET2512_MC.D2_PT_3/IN3 \ 0 23277 (_entity .  X_INV)
		(_port
			((I) (U2_ADDR_reg(0)))
			((O) (\NlwInverterSignal_NET2512_MC.D2_PT_3/IN3 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_NET2512_MC.D2_PT_3/IN5 \ 0 23281 (_entity .  X_INV)
		(_port
			((I) (U2_ADDR_reg(2)))
			((O) (\NlwInverterSignal_NET2512_MC.D2_PT_3/IN5 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_NET2512_MC.D2_PT_3/IN6 \ 0 23285 (_entity .  X_INV)
		(_port
			((I) (U2_ADDR_reg(3)))
			((O) (\NlwInverterSignal_NET2512_MC.D2_PT_3/IN6 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_NET2512_MC.D2_PT_3/IN7 \ 0 23289 (_entity .  X_INV)
		(_port
			((I) (\Reset_II/UIM \))
			((O) (\NlwInverterSignal_NET2512_MC.D2_PT_3/IN7 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_NET2512_MC.D2_PT_3/IN8 \ 0 23293 (_entity .  X_INV)
		(_port
			((I) (\AD<6>_II/UIM \))
			((O) (\NlwInverterSignal_NET2512_MC.D2_PT_3/IN8 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/U4/LatchEdge1r_MC.D2_PT_1/IN0 \ 0 23297 (_entity .  X_INV)
		(_port
			((I) (\WR_II/UIM \))
			((O) (\NlwInverterSignal_U1/U4/LatchEdge1r_MC.D2_PT_1/IN0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/U4/LatchEdge1r_MC.D2_PT_1/IN5 \ 0 23301 (_entity .  X_INV)
		(_port
			((I) (U2_ADDR_reg(2)))
			((O) (\NlwInverterSignal_U1/U4/LatchEdge1r_MC.D2_PT_1/IN5 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/U4/LatchEdge1r_MC.D2_PT_1/IN6 \ 0 23305 (_entity .  X_INV)
		(_port
			((I) (U2_ADDR_reg(3)))
			((O) (\NlwInverterSignal_U1/U4/LatchEdge1r_MC.D2_PT_1/IN6 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/U4/LatchEdge1r_MC.D2_PT_1/IN7 \ 0 23309 (_entity .  X_INV)
		(_port
			((I) (\AD<6>_II/UIM \))
			((O) (\NlwInverterSignal_U1/U4/LatchEdge1r_MC.D2_PT_1/IN7 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/U4/LatchEdge1r_MC.D2_PT_2/IN0 \ 0 23313 (_entity .  X_INV)
		(_port
			((I) (\WR_II/UIM \))
			((O) (\NlwInverterSignal_U1/U4/LatchEdge1r_MC.D2_PT_2/IN0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/U4/LatchEdge1r_MC.D2_PT_2/IN5 \ 0 23317 (_entity .  X_INV)
		(_port
			((I) (U2_ADDR_reg(2)))
			((O) (\NlwInverterSignal_U1/U4/LatchEdge1r_MC.D2_PT_2/IN5 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/U4/LatchEdge1r_MC.D2_PT_2/IN6 \ 0 23321 (_entity .  X_INV)
		(_port
			((I) (U2_ADDR_reg(3)))
			((O) (\NlwInverterSignal_U1/U4/LatchEdge1r_MC.D2_PT_2/IN6 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/U4/LatchEdge1r_MC.D2_PT_2/IN7 \ 0 23325 (_entity .  X_INV)
		(_port
			((I) (\Reset_II/UIM \))
			((O) (\NlwInverterSignal_U1/U4/LatchEdge1r_MC.D2_PT_2/IN7 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/U4/LatchEdge1r_MC.D2_PT_2/IN9 \ 0 23329 (_entity .  X_INV)
		(_port
			((I) (\U1/U4/LatchEdge1r \))
			((O) (\NlwInverterSignal_U1/U4/LatchEdge1r_MC.D2_PT_2/IN9 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U3/DCORIE<6>_MC.D2_PT_1/IN0 \ 0 23333 (_entity .  X_INV)
		(_port
			((I) (\WR_II/UIM \))
			((O) (\NlwInverterSignal_U3/DCORIE<6>_MC.D2_PT_1/IN0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U3/DCORIE<6>_MC.D2_PT_1/IN2 \ 0 23337 (_entity .  X_INV)
		(_port
			((I) (U2_ADDR_reg(1)))
			((O) (\NlwInverterSignal_U3/DCORIE<6>_MC.D2_PT_1/IN2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U3/DCORIE<6>_MC.D2_PT_1/IN5 \ 0 23341 (_entity .  X_INV)
		(_port
			((I) (U2_ADDR_reg(2)))
			((O) (\NlwInverterSignal_U3/DCORIE<6>_MC.D2_PT_1/IN5 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U3/DCORIE<6>_MC.D2_PT_1/IN6 \ 0 23345 (_entity .  X_INV)
		(_port
			((I) (U2_ADDR_reg(3)))
			((O) (\NlwInverterSignal_U3/DCORIE<6>_MC.D2_PT_1/IN6 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U3/DCORIE<6>_MC.D2_PT_1/IN7 \ 0 23349 (_entity .  X_INV)
		(_port
			((I) (\AD<6>_II/UIM \))
			((O) (\NlwInverterSignal_U3/DCORIE<6>_MC.D2_PT_1/IN7 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U3/DCORIE<6>_MC.D2_PT_2/IN0 \ 0 23353 (_entity .  X_INV)
		(_port
			((I) (\WR_II/UIM \))
			((O) (\NlwInverterSignal_U3/DCORIE<6>_MC.D2_PT_2/IN0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U3/DCORIE<6>_MC.D2_PT_2/IN2 \ 0 23357 (_entity .  X_INV)
		(_port
			((I) (U2_ADDR_reg(1)))
			((O) (\NlwInverterSignal_U3/DCORIE<6>_MC.D2_PT_2/IN2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U3/DCORIE<6>_MC.D2_PT_2/IN5 \ 0 23361 (_entity .  X_INV)
		(_port
			((I) (U2_ADDR_reg(2)))
			((O) (\NlwInverterSignal_U3/DCORIE<6>_MC.D2_PT_2/IN5 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U3/DCORIE<6>_MC.D2_PT_2/IN6 \ 0 23365 (_entity .  X_INV)
		(_port
			((I) (U2_ADDR_reg(3)))
			((O) (\NlwInverterSignal_U3/DCORIE<6>_MC.D2_PT_2/IN6 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U3/DCORIE<6>_MC.D2_PT_2/IN7 \ 0 23369 (_entity .  X_INV)
		(_port
			((I) (\Reset_II/UIM \))
			((O) (\NlwInverterSignal_U3/DCORIE<6>_MC.D2_PT_2/IN7 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U3/DCORIE<6>_MC.D2_PT_2/IN9 \ 0 23373 (_entity .  X_INV)
		(_port
			((I) (\U3/DCORIE \(6)))
			((O) (\NlwInverterSignal_U3/DCORIE<6>_MC.D2_PT_2/IN9 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U3/DCORIE<7>_MC.D2_PT_1/IN0 \ 0 23377 (_entity .  X_INV)
		(_port
			((I) (\WR_II/UIM \))
			((O) (\NlwInverterSignal_U3/DCORIE<7>_MC.D2_PT_1/IN0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U3/DCORIE<7>_MC.D2_PT_1/IN2 \ 0 23381 (_entity .  X_INV)
		(_port
			((I) (U2_ADDR_reg(1)))
			((O) (\NlwInverterSignal_U3/DCORIE<7>_MC.D2_PT_1/IN2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U3/DCORIE<7>_MC.D2_PT_1/IN5 \ 0 23385 (_entity .  X_INV)
		(_port
			((I) (U2_ADDR_reg(2)))
			((O) (\NlwInverterSignal_U3/DCORIE<7>_MC.D2_PT_1/IN5 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U3/DCORIE<7>_MC.D2_PT_1/IN6 \ 0 23389 (_entity .  X_INV)
		(_port
			((I) (U2_ADDR_reg(3)))
			((O) (\NlwInverterSignal_U3/DCORIE<7>_MC.D2_PT_1/IN6 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U3/DCORIE<7>_MC.D2_PT_1/IN7 \ 0 23393 (_entity .  X_INV)
		(_port
			((I) (\AD<7>_II/UIM \))
			((O) (\NlwInverterSignal_U3/DCORIE<7>_MC.D2_PT_1/IN7 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U3/DCORIE<7>_MC.D2_PT_2/IN0 \ 0 23397 (_entity .  X_INV)
		(_port
			((I) (\WR_II/UIM \))
			((O) (\NlwInverterSignal_U3/DCORIE<7>_MC.D2_PT_2/IN0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U3/DCORIE<7>_MC.D2_PT_2/IN2 \ 0 23401 (_entity .  X_INV)
		(_port
			((I) (U2_ADDR_reg(1)))
			((O) (\NlwInverterSignal_U3/DCORIE<7>_MC.D2_PT_2/IN2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U3/DCORIE<7>_MC.D2_PT_2/IN5 \ 0 23405 (_entity .  X_INV)
		(_port
			((I) (U2_ADDR_reg(2)))
			((O) (\NlwInverterSignal_U3/DCORIE<7>_MC.D2_PT_2/IN5 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U3/DCORIE<7>_MC.D2_PT_2/IN6 \ 0 23409 (_entity .  X_INV)
		(_port
			((I) (U2_ADDR_reg(3)))
			((O) (\NlwInverterSignal_U3/DCORIE<7>_MC.D2_PT_2/IN6 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U3/DCORIE<7>_MC.D2_PT_2/IN7 \ 0 23413 (_entity .  X_INV)
		(_port
			((I) (\Reset_II/UIM \))
			((O) (\NlwInverterSignal_U3/DCORIE<7>_MC.D2_PT_2/IN7 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U3/DCORIE<7>_MC.D2_PT_2/IN9 \ 0 23417 (_entity .  X_INV)
		(_port
			((I) (\U3/DCORIE \(7)))
			((O) (\NlwInverterSignal_U3/DCORIE<7>_MC.D2_PT_2/IN9 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_LED1_MC.D/IN0 \ 0 23421 (_entity .  X_INV)
		(_port
			((I) (\LED1_MC.D1 \))
			((O) (\NlwInverterSignal_LED1_MC.D/IN0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_LED1_MC.D1/IN1 \ 0 23425 (_entity .  X_INV)
		(_port
			((I) (\U9/MISCr \(0)))
			((O) (\NlwInverterSignal_LED1_MC.D1/IN1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U9/MISCr<0>_MC.D/IN0 \ 0 23429 (_entity .  X_INV)
		(_port
			((I) (\U9/MISCr<0>_MC.D1 \))
			((O) (\NlwInverterSignal_U9/MISCr<0>_MC.D/IN0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U9/MISCr<0>_MC.D2_PT_0/IN1 \ 0 23433 (_entity .  X_INV)
		(_port
			((I) (\outDATA<0>\\$WA5.UIM \))
			((O) (\NlwInverterSignal_U9/MISCr<0>_MC.D2_PT_0/IN1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U9/MISCr<0>_MC.D2_PT_1/IN1 \ 0 23437 (_entity .  X_INV)
		(_port
			((I) (\outDATA<0>\\$WA4.UIM \))
			((O) (\NlwInverterSignal_U9/MISCr<0>_MC.D2_PT_1/IN1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U9/MISCr<0>_MC.D2_PT_2/IN1 \ 0 23441 (_entity .  X_INV)
		(_port
			((I) (\RD_II/UIM \))
			((O) (\NlwInverterSignal_U9/MISCr<0>_MC.D2_PT_2/IN1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U9/MISCr<0>_MC.D2_PT_2/IN7 \ 0 23445 (_entity .  X_INV)
		(_port
			((I) (\outDATA<0>\\$WA1.UIM \))
			((O) (\NlwInverterSignal_U9/MISCr<0>_MC.D2_PT_2/IN7 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U9/MISCr<0>_MC.D2_PT_3/IN1 \ 0 23449 (_entity .  X_INV)
		(_port
			((I) (\RD_II/UIM \))
			((O) (\NlwInverterSignal_U9/MISCr<0>_MC.D2_PT_3/IN1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U9/MISCr<0>_MC.D2_PT_3/IN5 \ 0 23453 (_entity .  X_INV)
		(_port
			((I) (U2_ADDR_reg(2)))
			((O) (\NlwInverterSignal_U9/MISCr<0>_MC.D2_PT_3/IN5 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U9/MISCr<0>_MC.D2_PT_3/IN6 \ 0 23457 (_entity .  X_INV)
		(_port
			((I) (U2_ADDR_reg(3)))
			((O) (\NlwInverterSignal_U9/MISCr<0>_MC.D2_PT_3/IN6 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U9/MISCr<0>_MC.D2_PT_3/IN7 \ 0 23461 (_entity .  X_INV)
		(_port
			((I) (\outDATA<0>\\$WA2.UIM \))
			((O) (\NlwInverterSignal_U9/MISCr<0>_MC.D2_PT_3/IN7 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U9/MISCr<0>_MC.D2_PT_4/IN1 \ 0 23465 (_entity .  X_INV)
		(_port
			((I) (\RD_II/UIM \))
			((O) (\NlwInverterSignal_U9/MISCr<0>_MC.D2_PT_4/IN1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U9/MISCr<0>_MC.D2_PT_4/IN3 \ 0 23469 (_entity .  X_INV)
		(_port
			((I) (U2_ADDR_reg(0)))
			((O) (\NlwInverterSignal_U9/MISCr<0>_MC.D2_PT_4/IN3 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U9/MISCr<0>_MC.D2_PT_4/IN7 \ 0 23473 (_entity .  X_INV)
		(_port
			((I) (\outDATA<0>\\$WA3.UIM \))
			((O) (\NlwInverterSignal_U9/MISCr<0>_MC.D2_PT_4/IN7 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U9/MISCr<0>_MC.D2_PT_5/IN1 \ 0 23477 (_entity .  X_INV)
		(_port
			((I) (\RD_II/UIM \))
			((O) (\NlwInverterSignal_U9/MISCr<0>_MC.D2_PT_5/IN1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U9/MISCr<0>_MC.D2_PT_5/IN2 \ 0 23481 (_entity .  X_INV)
		(_port
			((I) (U2_ADDR_reg(1)))
			((O) (\NlwInverterSignal_U9/MISCr<0>_MC.D2_PT_5/IN2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U9/MISCr<0>_MC.D2_PT_5/IN3 \ 0 23485 (_entity .  X_INV)
		(_port
			((I) (U2_ADDR_reg(0)))
			((O) (\NlwInverterSignal_U9/MISCr<0>_MC.D2_PT_5/IN3 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U9/MISCr<0>_MC.D2_PT_5/IN5 \ 0 23489 (_entity .  X_INV)
		(_port
			((I) (U2_ADDR_reg(2)))
			((O) (\NlwInverterSignal_U9/MISCr<0>_MC.D2_PT_5/IN5 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U9/MISCr<0>_MC.D2_PT_5/IN6 \ 0 23493 (_entity .  X_INV)
		(_port
			((I) (U2_ADDR_reg(3)))
			((O) (\NlwInverterSignal_U9/MISCr<0>_MC.D2_PT_5/IN6 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U9/MISCr<0>_MC.D2_PT_5/IN7 \ 0 23497 (_entity .  X_INV)
		(_port
			((I) (\outDATA<0>\\$WA0.UIM \))
			((O) (\NlwInverterSignal_U9/MISCr<0>_MC.D2_PT_5/IN7 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_LED2_MC.D/IN0 \ 0 23501 (_entity .  X_INV)
		(_port
			((I) (\LED2_MC.D1 \))
			((O) (\NlwInverterSignal_LED2_MC.D/IN0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_LED2_MC.D1/IN1 \ 0 23505 (_entity .  X_INV)
		(_port
			((I) (\U9/MISCr \(1)))
			((O) (\NlwInverterSignal_LED2_MC.D1/IN1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U9/MISCr<1>_MC.D/IN0 \ 0 23509 (_entity .  X_INV)
		(_port
			((I) (\U9/MISCr<1>_MC.D1 \))
			((O) (\NlwInverterSignal_U9/MISCr<1>_MC.D/IN0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U9/MISCr<1>_MC.D2_PT_0/IN1 \ 0 23513 (_entity .  X_INV)
		(_port
			((I) (\outDATA<1>\\$WA5.UIM \))
			((O) (\NlwInverterSignal_U9/MISCr<1>_MC.D2_PT_0/IN1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U9/MISCr<1>_MC.D2_PT_1/IN1 \ 0 23517 (_entity .  X_INV)
		(_port
			((I) (\outDATA<1>\\$WA4.UIM \))
			((O) (\NlwInverterSignal_U9/MISCr<1>_MC.D2_PT_1/IN1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U9/MISCr<1>_MC.D2_PT_2/IN0 \ 0 23521 (_entity .  X_INV)
		(_port
			((I) (N_PZ_964))
			((O) (\NlwInverterSignal_U9/MISCr<1>_MC.D2_PT_2/IN0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U9/MISCr<1>_MC.D2_PT_2/IN2 \ 0 23525 (_entity .  X_INV)
		(_port
			((I) (U2_ADDR_reg(0)))
			((O) (\NlwInverterSignal_U9/MISCr<1>_MC.D2_PT_2/IN2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U9/MISCr<1>_MC.D2_PT_2/IN6 \ 0 23529 (_entity .  X_INV)
		(_port
			((I) (\outDATA<1>\\$WA3.UIM \))
			((O) (\NlwInverterSignal_U9/MISCr<1>_MC.D2_PT_2/IN6 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U9/MISCr<1>_MC.D2_PT_3/IN0 \ 0 23533 (_entity .  X_INV)
		(_port
			((I) (N_PZ_964))
			((O) (\NlwInverterSignal_U9/MISCr<1>_MC.D2_PT_3/IN0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U9/MISCr<1>_MC.D2_PT_3/IN1 \ 0 23537 (_entity .  X_INV)
		(_port
			((I) (U2_ADDR_reg(1)))
			((O) (\NlwInverterSignal_U9/MISCr<1>_MC.D2_PT_3/IN1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U9/MISCr<1>_MC.D2_PT_3/IN2 \ 0 23541 (_entity .  X_INV)
		(_port
			((I) (U2_ADDR_reg(0)))
			((O) (\NlwInverterSignal_U9/MISCr<1>_MC.D2_PT_3/IN2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U9/MISCr<1>_MC.D2_PT_3/IN4 \ 0 23545 (_entity .  X_INV)
		(_port
			((I) (U2_ADDR_reg(2)))
			((O) (\NlwInverterSignal_U9/MISCr<1>_MC.D2_PT_3/IN4 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U9/MISCr<1>_MC.D2_PT_3/IN6 \ 0 23549 (_entity .  X_INV)
		(_port
			((I) (\outDATA<1>\\$WA0.UIM \))
			((O) (\NlwInverterSignal_U9/MISCr<1>_MC.D2_PT_3/IN6 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U9/MISCr<1>_MC.D2_PT_4/IN6 \ 0 23553 (_entity .  X_INV)
		(_port
			((I) (\outDATA<1>\\$WA1.UIM \))
			((O) (\NlwInverterSignal_U9/MISCr<1>_MC.D2_PT_4/IN6 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U9/MISCr<1>_MC.D2_PT_5/IN3 \ 0 23557 (_entity .  X_INV)
		(_port
			((I) (U2_ADDR_reg(2)))
			((O) (\NlwInverterSignal_U9/MISCr<1>_MC.D2_PT_5/IN3 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U9/MISCr<1>_MC.D2_PT_5/IN4 \ 0 23561 (_entity .  X_INV)
		(_port
			((I) (U2_ADDR_reg(3)))
			((O) (\NlwInverterSignal_U9/MISCr<1>_MC.D2_PT_5/IN4 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U9/MISCr<1>_MC.D2_PT_5/IN6 \ 0 23565 (_entity .  X_INV)
		(_port
			((I) (\outDATA<1>\\$WA2.UIM \))
			((O) (\NlwInverterSignal_U9/MISCr<1>_MC.D2_PT_5/IN6 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_LED3_MC.D/IN0 \ 0 23569 (_entity .  X_INV)
		(_port
			((I) (\LED3_MC.D1 \))
			((O) (\NlwInverterSignal_LED3_MC.D/IN0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_LED3_MC.D1/IN1 \ 0 23573 (_entity .  X_INV)
		(_port
			((I) (\U9/MISCr \(2)))
			((O) (\NlwInverterSignal_LED3_MC.D1/IN1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U9/MISCr<2>_MC.D/IN0 \ 0 23577 (_entity .  X_INV)
		(_port
			((I) (\U9/MISCr<2>_MC.D1 \))
			((O) (\NlwInverterSignal_U9/MISCr<2>_MC.D/IN0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U9/MISCr<2>_MC.D2_PT_0/IN1 \ 0 23581 (_entity .  X_INV)
		(_port
			((I) (\outDATA<2>\\$WA5.UIM \))
			((O) (\NlwInverterSignal_U9/MISCr<2>_MC.D2_PT_0/IN1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U9/MISCr<2>_MC.D2_PT_1/IN1 \ 0 23585 (_entity .  X_INV)
		(_port
			((I) (\outDATA<2>\\$WA4.UIM \))
			((O) (\NlwInverterSignal_U9/MISCr<2>_MC.D2_PT_1/IN1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U9/MISCr<2>_MC.D2_PT_2/IN1 \ 0 23589 (_entity .  X_INV)
		(_port
			((I) (\RD_II/UIM \))
			((O) (\NlwInverterSignal_U9/MISCr<2>_MC.D2_PT_2/IN1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U9/MISCr<2>_MC.D2_PT_2/IN7 \ 0 23593 (_entity .  X_INV)
		(_port
			((I) (\outDATA<2>\\$WA1.UIM \))
			((O) (\NlwInverterSignal_U9/MISCr<2>_MC.D2_PT_2/IN7 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U9/MISCr<2>_MC.D2_PT_3/IN1 \ 0 23597 (_entity .  X_INV)
		(_port
			((I) (\RD_II/UIM \))
			((O) (\NlwInverterSignal_U9/MISCr<2>_MC.D2_PT_3/IN1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U9/MISCr<2>_MC.D2_PT_3/IN5 \ 0 23601 (_entity .  X_INV)
		(_port
			((I) (U2_ADDR_reg(2)))
			((O) (\NlwInverterSignal_U9/MISCr<2>_MC.D2_PT_3/IN5 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U9/MISCr<2>_MC.D2_PT_3/IN6 \ 0 23605 (_entity .  X_INV)
		(_port
			((I) (U2_ADDR_reg(3)))
			((O) (\NlwInverterSignal_U9/MISCr<2>_MC.D2_PT_3/IN6 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U9/MISCr<2>_MC.D2_PT_3/IN7 \ 0 23609 (_entity .  X_INV)
		(_port
			((I) (\outDATA<2>\\$WA2.UIM \))
			((O) (\NlwInverterSignal_U9/MISCr<2>_MC.D2_PT_3/IN7 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U9/MISCr<2>_MC.D2_PT_4/IN1 \ 0 23613 (_entity .  X_INV)
		(_port
			((I) (\RD_II/UIM \))
			((O) (\NlwInverterSignal_U9/MISCr<2>_MC.D2_PT_4/IN1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U9/MISCr<2>_MC.D2_PT_4/IN3 \ 0 23617 (_entity .  X_INV)
		(_port
			((I) (U2_ADDR_reg(0)))
			((O) (\NlwInverterSignal_U9/MISCr<2>_MC.D2_PT_4/IN3 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U9/MISCr<2>_MC.D2_PT_4/IN7 \ 0 23621 (_entity .  X_INV)
		(_port
			((I) (\outDATA<2>\\$WA3.UIM \))
			((O) (\NlwInverterSignal_U9/MISCr<2>_MC.D2_PT_4/IN7 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U9/MISCr<2>_MC.D2_PT_5/IN1 \ 0 23625 (_entity .  X_INV)
		(_port
			((I) (\RD_II/UIM \))
			((O) (\NlwInverterSignal_U9/MISCr<2>_MC.D2_PT_5/IN1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U9/MISCr<2>_MC.D2_PT_5/IN2 \ 0 23629 (_entity .  X_INV)
		(_port
			((I) (U2_ADDR_reg(1)))
			((O) (\NlwInverterSignal_U9/MISCr<2>_MC.D2_PT_5/IN2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U9/MISCr<2>_MC.D2_PT_5/IN3 \ 0 23633 (_entity .  X_INV)
		(_port
			((I) (U2_ADDR_reg(0)))
			((O) (\NlwInverterSignal_U9/MISCr<2>_MC.D2_PT_5/IN3 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U9/MISCr<2>_MC.D2_PT_5/IN5 \ 0 23637 (_entity .  X_INV)
		(_port
			((I) (U2_ADDR_reg(2)))
			((O) (\NlwInverterSignal_U9/MISCr<2>_MC.D2_PT_5/IN5 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U9/MISCr<2>_MC.D2_PT_5/IN6 \ 0 23641 (_entity .  X_INV)
		(_port
			((I) (U2_ADDR_reg(3)))
			((O) (\NlwInverterSignal_U9/MISCr<2>_MC.D2_PT_5/IN6 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U9/MISCr<2>_MC.D2_PT_5/IN7 \ 0 23645 (_entity .  X_INV)
		(_port
			((I) (\outDATA<2>\\$WA0.UIM \))
			((O) (\NlwInverterSignal_U9/MISCr<2>_MC.D2_PT_5/IN7 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_LED4_MC.D/IN0 \ 0 23649 (_entity .  X_INV)
		(_port
			((I) (\LED4_MC.D1 \))
			((O) (\NlwInverterSignal_LED4_MC.D/IN0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_LED4_MC.D1/IN1 \ 0 23653 (_entity .  X_INV)
		(_port
			((I) (\U9/MISCr \(3)))
			((O) (\NlwInverterSignal_LED4_MC.D1/IN1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U9/MISCr<3>_MC.D/IN0 \ 0 23657 (_entity .  X_INV)
		(_port
			((I) (\U9/MISCr<3>_MC.D1 \))
			((O) (\NlwInverterSignal_U9/MISCr<3>_MC.D/IN0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U9/MISCr<3>_MC.D2_PT_0/IN1 \ 0 23661 (_entity .  X_INV)
		(_port
			((I) (\outDATA<3>\\$WA5.UIM \))
			((O) (\NlwInverterSignal_U9/MISCr<3>_MC.D2_PT_0/IN1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U9/MISCr<3>_MC.D2_PT_1/IN1 \ 0 23665 (_entity .  X_INV)
		(_port
			((I) (\outDATA<3>\\$WA4.UIM \))
			((O) (\NlwInverterSignal_U9/MISCr<3>_MC.D2_PT_1/IN1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U9/MISCr<3>_MC.D2_PT_2/IN1 \ 0 23669 (_entity .  X_INV)
		(_port
			((I) (\RD_II/UIM \))
			((O) (\NlwInverterSignal_U9/MISCr<3>_MC.D2_PT_2/IN1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U9/MISCr<3>_MC.D2_PT_2/IN7 \ 0 23673 (_entity .  X_INV)
		(_port
			((I) (\outDATA<3>\\$WA1.UIM \))
			((O) (\NlwInverterSignal_U9/MISCr<3>_MC.D2_PT_2/IN7 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U9/MISCr<3>_MC.D2_PT_3/IN1 \ 0 23677 (_entity .  X_INV)
		(_port
			((I) (\RD_II/UIM \))
			((O) (\NlwInverterSignal_U9/MISCr<3>_MC.D2_PT_3/IN1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U9/MISCr<3>_MC.D2_PT_3/IN5 \ 0 23681 (_entity .  X_INV)
		(_port
			((I) (U2_ADDR_reg(2)))
			((O) (\NlwInverterSignal_U9/MISCr<3>_MC.D2_PT_3/IN5 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U9/MISCr<3>_MC.D2_PT_3/IN6 \ 0 23685 (_entity .  X_INV)
		(_port
			((I) (U2_ADDR_reg(3)))
			((O) (\NlwInverterSignal_U9/MISCr<3>_MC.D2_PT_3/IN6 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U9/MISCr<3>_MC.D2_PT_3/IN7 \ 0 23689 (_entity .  X_INV)
		(_port
			((I) (\outDATA<3>\\$WA2.UIM \))
			((O) (\NlwInverterSignal_U9/MISCr<3>_MC.D2_PT_3/IN7 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U9/MISCr<3>_MC.D2_PT_4/IN1 \ 0 23693 (_entity .  X_INV)
		(_port
			((I) (\RD_II/UIM \))
			((O) (\NlwInverterSignal_U9/MISCr<3>_MC.D2_PT_4/IN1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U9/MISCr<3>_MC.D2_PT_4/IN3 \ 0 23697 (_entity .  X_INV)
		(_port
			((I) (U2_ADDR_reg(0)))
			((O) (\NlwInverterSignal_U9/MISCr<3>_MC.D2_PT_4/IN3 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U9/MISCr<3>_MC.D2_PT_4/IN7 \ 0 23701 (_entity .  X_INV)
		(_port
			((I) (\outDATA<3>\\$WA3.UIM \))
			((O) (\NlwInverterSignal_U9/MISCr<3>_MC.D2_PT_4/IN7 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U9/MISCr<3>_MC.D2_PT_5/IN1 \ 0 23705 (_entity .  X_INV)
		(_port
			((I) (\RD_II/UIM \))
			((O) (\NlwInverterSignal_U9/MISCr<3>_MC.D2_PT_5/IN1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U9/MISCr<3>_MC.D2_PT_5/IN2 \ 0 23709 (_entity .  X_INV)
		(_port
			((I) (U2_ADDR_reg(1)))
			((O) (\NlwInverterSignal_U9/MISCr<3>_MC.D2_PT_5/IN2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U9/MISCr<3>_MC.D2_PT_5/IN3 \ 0 23713 (_entity .  X_INV)
		(_port
			((I) (U2_ADDR_reg(0)))
			((O) (\NlwInverterSignal_U9/MISCr<3>_MC.D2_PT_5/IN3 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U9/MISCr<3>_MC.D2_PT_5/IN5 \ 0 23717 (_entity .  X_INV)
		(_port
			((I) (U2_ADDR_reg(2)))
			((O) (\NlwInverterSignal_U9/MISCr<3>_MC.D2_PT_5/IN5 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U9/MISCr<3>_MC.D2_PT_5/IN6 \ 0 23721 (_entity .  X_INV)
		(_port
			((I) (U2_ADDR_reg(3)))
			((O) (\NlwInverterSignal_U9/MISCr<3>_MC.D2_PT_5/IN6 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U9/MISCr<3>_MC.D2_PT_5/IN7 \ 0 23725 (_entity .  X_INV)
		(_port
			((I) (\outDATA<3>\\$WA0.UIM \))
			((O) (\NlwInverterSignal_U9/MISCr<3>_MC.D2_PT_5/IN7 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_LED5_MC.D/IN0 \ 0 23729 (_entity .  X_INV)
		(_port
			((I) (\LED5_MC.D1 \))
			((O) (\NlwInverterSignal_LED5_MC.D/IN0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_LED5_MC.D1/IN1 \ 0 23733 (_entity .  X_INV)
		(_port
			((I) (\U9/MISCr \(4)))
			((O) (\NlwInverterSignal_LED5_MC.D1/IN1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U9/MISCr<4>_MC.D/IN0 \ 0 23737 (_entity .  X_INV)
		(_port
			((I) (\U9/MISCr<4>_MC.D1 \))
			((O) (\NlwInverterSignal_U9/MISCr<4>_MC.D/IN0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U9/MISCr<4>_MC.D2_PT_0/IN1 \ 0 23741 (_entity .  X_INV)
		(_port
			((I) (\outDATA<4>\\$WA5.UIM \))
			((O) (\NlwInverterSignal_U9/MISCr<4>_MC.D2_PT_0/IN1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U9/MISCr<4>_MC.D2_PT_1/IN1 \ 0 23745 (_entity .  X_INV)
		(_port
			((I) (\outDATA<4>\\$WA4.UIM \))
			((O) (\NlwInverterSignal_U9/MISCr<4>_MC.D2_PT_1/IN1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U9/MISCr<4>_MC.D2_PT_2/IN1 \ 0 23749 (_entity .  X_INV)
		(_port
			((I) (\RD_II/UIM \))
			((O) (\NlwInverterSignal_U9/MISCr<4>_MC.D2_PT_2/IN1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U9/MISCr<4>_MC.D2_PT_2/IN7 \ 0 23753 (_entity .  X_INV)
		(_port
			((I) (\outDATA<4>\\$WA1.UIM \))
			((O) (\NlwInverterSignal_U9/MISCr<4>_MC.D2_PT_2/IN7 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U9/MISCr<4>_MC.D2_PT_3/IN1 \ 0 23757 (_entity .  X_INV)
		(_port
			((I) (\RD_II/UIM \))
			((O) (\NlwInverterSignal_U9/MISCr<4>_MC.D2_PT_3/IN1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U9/MISCr<4>_MC.D2_PT_3/IN5 \ 0 23761 (_entity .  X_INV)
		(_port
			((I) (U2_ADDR_reg(2)))
			((O) (\NlwInverterSignal_U9/MISCr<4>_MC.D2_PT_3/IN5 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U9/MISCr<4>_MC.D2_PT_3/IN6 \ 0 23765 (_entity .  X_INV)
		(_port
			((I) (U2_ADDR_reg(3)))
			((O) (\NlwInverterSignal_U9/MISCr<4>_MC.D2_PT_3/IN6 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U9/MISCr<4>_MC.D2_PT_3/IN7 \ 0 23769 (_entity .  X_INV)
		(_port
			((I) (\outDATA<4>\\$WA2.UIM \))
			((O) (\NlwInverterSignal_U9/MISCr<4>_MC.D2_PT_3/IN7 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U9/MISCr<4>_MC.D2_PT_4/IN1 \ 0 23773 (_entity .  X_INV)
		(_port
			((I) (\RD_II/UIM \))
			((O) (\NlwInverterSignal_U9/MISCr<4>_MC.D2_PT_4/IN1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U9/MISCr<4>_MC.D2_PT_4/IN3 \ 0 23777 (_entity .  X_INV)
		(_port
			((I) (U2_ADDR_reg(0)))
			((O) (\NlwInverterSignal_U9/MISCr<4>_MC.D2_PT_4/IN3 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U9/MISCr<4>_MC.D2_PT_4/IN7 \ 0 23781 (_entity .  X_INV)
		(_port
			((I) (\outDATA<4>\\$WA3.UIM \))
			((O) (\NlwInverterSignal_U9/MISCr<4>_MC.D2_PT_4/IN7 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U9/MISCr<4>_MC.D2_PT_5/IN1 \ 0 23785 (_entity .  X_INV)
		(_port
			((I) (\RD_II/UIM \))
			((O) (\NlwInverterSignal_U9/MISCr<4>_MC.D2_PT_5/IN1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U9/MISCr<4>_MC.D2_PT_5/IN2 \ 0 23789 (_entity .  X_INV)
		(_port
			((I) (U2_ADDR_reg(1)))
			((O) (\NlwInverterSignal_U9/MISCr<4>_MC.D2_PT_5/IN2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U9/MISCr<4>_MC.D2_PT_5/IN3 \ 0 23793 (_entity .  X_INV)
		(_port
			((I) (U2_ADDR_reg(0)))
			((O) (\NlwInverterSignal_U9/MISCr<4>_MC.D2_PT_5/IN3 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U9/MISCr<4>_MC.D2_PT_5/IN5 \ 0 23797 (_entity .  X_INV)
		(_port
			((I) (U2_ADDR_reg(2)))
			((O) (\NlwInverterSignal_U9/MISCr<4>_MC.D2_PT_5/IN5 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U9/MISCr<4>_MC.D2_PT_5/IN6 \ 0 23801 (_entity .  X_INV)
		(_port
			((I) (U2_ADDR_reg(3)))
			((O) (\NlwInverterSignal_U9/MISCr<4>_MC.D2_PT_5/IN6 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U9/MISCr<4>_MC.D2_PT_5/IN7 \ 0 23805 (_entity .  X_INV)
		(_port
			((I) (\outDATA<4>\\$WA0.UIM \))
			((O) (\NlwInverterSignal_U9/MISCr<4>_MC.D2_PT_5/IN7 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_MTRpwrn_MC.D/IN0 \ 0 23809 (_entity .  X_INV)
		(_port
			((I) (\MTRpwrn_MC.D1 \))
			((O) (\NlwInverterSignal_MTRpwrn_MC.D/IN0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_PAH0_MC.D1/IN0 \ 0 23813 (_entity .  X_INV)
		(_port
			((I) (\Brake0_II/UIM \))
			((O) (\NlwInverterSignal_PAH0_MC.D1/IN0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_PAH0_MC.D1/IN1 \ 0 23817 (_entity .  X_INV)
		(_port
			((I) (\DIR0_II/UIM \))
			((O) (\NlwInverterSignal_PAH0_MC.D1/IN1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_PAH0_MC.D1/IN3 \ 0 23821 (_entity .  X_INV)
		(_port
			((I) (NET3248))
			((O) (\NlwInverterSignal_PAH0_MC.D1/IN3 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_NET3248_MC.D2_PT_0/IN0 \ 0 23825 (_entity .  X_INV)
		(_port
			((I) (\Reset_II/UIM \))
			((O) (\NlwInverterSignal_NET3248_MC.D2_PT_0/IN0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_NET3248_MC.D2_PT_0/IN1 \ 0 23829 (_entity .  X_INV)
		(_port
			((I) (\Brake0_II/UIM \))
			((O) (\NlwInverterSignal_NET3248_MC.D2_PT_0/IN1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_NET3248_MC.D2_PT_1/IN0 \ 0 23833 (_entity .  X_INV)
		(_port
			((I) (\Reset_II/UIM \))
			((O) (\NlwInverterSignal_NET3248_MC.D2_PT_1/IN0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_NET3248_MC.D2_PT_1/IN2 \ 0 23837 (_entity .  X_INV)
		(_port
			((I) (\FLS0_II/UIM \))
			((O) (\NlwInverterSignal_NET3248_MC.D2_PT_1/IN2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_NET3248_MC.D2_PT_2/IN0 \ 0 23841 (_entity .  X_INV)
		(_port
			((I) (\Reset_II/UIM \))
			((O) (\NlwInverterSignal_NET3248_MC.D2_PT_2/IN0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_NET3248_MC.D2_PT_2/IN1 \ 0 23845 (_entity .  X_INV)
		(_port
			((I) (\DIR0_II/UIM \))
			((O) (\NlwInverterSignal_NET3248_MC.D2_PT_2/IN1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_NET3248_MC.D2_PT_2/IN2 \ 0 23849 (_entity .  X_INV)
		(_port
			((I) (\RLS0_II/UIM \))
			((O) (\NlwInverterSignal_NET3248_MC.D2_PT_2/IN2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_PAH1_MC.D2_PT_0/IN0 \ 0 23853 (_entity .  X_INV)
		(_port
			((I) (NET3253))
			((O) (\NlwInverterSignal_PAH1_MC.D2_PT_0/IN0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_PAH1_MC.D2_PT_0/IN1 \ 0 23857 (_entity .  X_INV)
		(_port
			((I) (\Brake1_II/UIM \))
			((O) (\NlwInverterSignal_PAH1_MC.D2_PT_0/IN1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_PAH1_MC.D2_PT_1/IN0 \ 0 23861 (_entity .  X_INV)
		(_port
			((I) (NET3253))
			((O) (\NlwInverterSignal_PAH1_MC.D2_PT_1/IN0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_PAH1_MC.D2_PT_1/IN1 \ 0 23865 (_entity .  X_INV)
		(_port
			((I) (\Brake1_II/UIM \))
			((O) (\NlwInverterSignal_PAH1_MC.D2_PT_1/IN1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_PAH1_MC.D2_PT_1/IN2 \ 0 23869 (_entity .  X_INV)
		(_port
			((I) (\DIR1_II/UIM \))
			((O) (\NlwInverterSignal_PAH1_MC.D2_PT_1/IN2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_PAH1_MC.D2_PT_1/IN3 \ 0 23873 (_entity .  X_INV)
		(_port
			((I) (\PWM2_II/UIM \))
			((O) (\NlwInverterSignal_PAH1_MC.D2_PT_1/IN3 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_PAL0_MC.D2_PT_0/IN0 \ 0 23877 (_entity .  X_INV)
		(_port
			((I) (\Brake0_II/UIM \))
			((O) (\NlwInverterSignal_PAL0_MC.D2_PT_0/IN0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_PAL0_MC.D2_PT_0/IN2 \ 0 23881 (_entity .  X_INV)
		(_port
			((I) (\PWM1_II/UIM \))
			((O) (\NlwInverterSignal_PAL0_MC.D2_PT_0/IN2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_PAL0_MC.D2_PT_0/IN3 \ 0 23885 (_entity .  X_INV)
		(_port
			((I) (NET3248))
			((O) (\NlwInverterSignal_PAL0_MC.D2_PT_0/IN3 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_PAL0_MC.D2_PT_1/IN0 \ 0 23889 (_entity .  X_INV)
		(_port
			((I) (\Brake0_II/UIM \))
			((O) (\NlwInverterSignal_PAL0_MC.D2_PT_1/IN0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_PAL0_MC.D2_PT_1/IN1 \ 0 23893 (_entity .  X_INV)
		(_port
			((I) (\DIR0_II/UIM \))
			((O) (\NlwInverterSignal_PAL0_MC.D2_PT_1/IN1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_PAL0_MC.D2_PT_1/IN3 \ 0 23897 (_entity .  X_INV)
		(_port
			((I) (NET3248))
			((O) (\NlwInverterSignal_PAL0_MC.D2_PT_1/IN3 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_PAL1_MC.D1/IN0 \ 0 23901 (_entity .  X_INV)
		(_port
			((I) (NET3253))
			((O) (\NlwInverterSignal_PAL1_MC.D1/IN0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_PAL1_MC.D1/IN1 \ 0 23905 (_entity .  X_INV)
		(_port
			((I) (\Brake1_II/UIM \))
			((O) (\NlwInverterSignal_PAL1_MC.D1/IN1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_PBH0_MC.D1/IN0 \ 0 23909 (_entity .  X_INV)
		(_port
			((I) (\Brake0_II/UIM \))
			((O) (\NlwInverterSignal_PBH0_MC.D1/IN0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_PBH0_MC.D1/IN3 \ 0 23913 (_entity .  X_INV)
		(_port
			((I) (NET3248))
			((O) (\NlwInverterSignal_PBH0_MC.D1/IN3 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_PBH1_MC.D2_PT_0/IN0 \ 0 23917 (_entity .  X_INV)
		(_port
			((I) (NET3253))
			((O) (\NlwInverterSignal_PBH1_MC.D2_PT_0/IN0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_PBH1_MC.D2_PT_0/IN1 \ 0 23921 (_entity .  X_INV)
		(_port
			((I) (\Brake1_II/UIM \))
			((O) (\NlwInverterSignal_PBH1_MC.D2_PT_0/IN1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_PBH1_MC.D2_PT_0/IN3 \ 0 23925 (_entity .  X_INV)
		(_port
			((I) (\PWM2_II/UIM \))
			((O) (\NlwInverterSignal_PBH1_MC.D2_PT_0/IN3 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_PBH1_MC.D2_PT_1/IN0 \ 0 23929 (_entity .  X_INV)
		(_port
			((I) (NET3253))
			((O) (\NlwInverterSignal_PBH1_MC.D2_PT_1/IN0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_PBH1_MC.D2_PT_1/IN1 \ 0 23933 (_entity .  X_INV)
		(_port
			((I) (\Brake1_II/UIM \))
			((O) (\NlwInverterSignal_PBH1_MC.D2_PT_1/IN1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_PBH1_MC.D2_PT_1/IN2 \ 0 23937 (_entity .  X_INV)
		(_port
			((I) (\DIR1_II/UIM \))
			((O) (\NlwInverterSignal_PBH1_MC.D2_PT_1/IN2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_PBL0_MC.D2_PT_0/IN0 \ 0 23941 (_entity .  X_INV)
		(_port
			((I) (\Brake0_II/UIM \))
			((O) (\NlwInverterSignal_PBL0_MC.D2_PT_0/IN0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_PBL0_MC.D2_PT_0/IN3 \ 0 23945 (_entity .  X_INV)
		(_port
			((I) (NET3248))
			((O) (\NlwInverterSignal_PBL0_MC.D2_PT_0/IN3 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_PBL0_MC.D2_PT_1/IN0 \ 0 23949 (_entity .  X_INV)
		(_port
			((I) (\Brake0_II/UIM \))
			((O) (\NlwInverterSignal_PBL0_MC.D2_PT_1/IN0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_PBL0_MC.D2_PT_1/IN1 \ 0 23953 (_entity .  X_INV)
		(_port
			((I) (\DIR0_II/UIM \))
			((O) (\NlwInverterSignal_PBL0_MC.D2_PT_1/IN1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_PBL0_MC.D2_PT_1/IN2 \ 0 23957 (_entity .  X_INV)
		(_port
			((I) (\PWM1_II/UIM \))
			((O) (\NlwInverterSignal_PBL0_MC.D2_PT_1/IN2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_PBL0_MC.D2_PT_1/IN3 \ 0 23961 (_entity .  X_INV)
		(_port
			((I) (NET3248))
			((O) (\NlwInverterSignal_PBL0_MC.D2_PT_1/IN3 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_PBL1_MC.D1/IN0 \ 0 23965 (_entity .  X_INV)
		(_port
			((I) (NET3253))
			((O) (\NlwInverterSignal_PBL1_MC.D1/IN0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_PBL1_MC.D1/IN1 \ 0 23969 (_entity .  X_INV)
		(_port
			((I) (\Brake1_II/UIM \))
			((O) (\NlwInverterSignal_PBL1_MC.D1/IN1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_PBL1_MC.D1/IN2 \ 0 23973 (_entity .  X_INV)
		(_port
			((I) (\DIR1_II/UIM \))
			((O) (\NlwInverterSignal_PBL1_MC.D1/IN2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_outDATA<0>\\$WA3.UIM_MC.D2_PT_1/IN0 \ 0 23977 (_entity .  X_INV)
		(_port
			((I) (NET2528))
			((O) (\NlwInverterSignal_outDATA<0>\\$WA3.UIM_MC.D2_PT_1/IN0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/U3/holdingreg<0>_MC.D2_PT_1/IN0 \ 0 23981 (_entity .  X_INV)
		(_port
			((I) (\Reset_II/UIM \))
			((O) (\NlwInverterSignal_U1/U3/holdingreg<0>_MC.D2_PT_1/IN0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/U3/holdingreg<0>_MC.D2_PT_2/IN1 \ 0 23985 (_entity .  X_INV)
		(_port
			((I) (\RD_II/UIM \))
			((O) (\NlwInverterSignal_U1/U3/holdingreg<0>_MC.D2_PT_2/IN1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/U3/holdingreg<0>_MC.D2_PT_2/IN6 \ 0 23989 (_entity .  X_INV)
		(_port
			((I) (U2_ADDR_reg(3)))
			((O) (\NlwInverterSignal_U1/U3/holdingreg<0>_MC.D2_PT_2/IN6 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/U3/holdingreg<0>_MC.D2_PT_2/IN7 \ 0 23993 (_entity .  X_INV)
		(_port
			((I) (\Reset_II/UIM \))
			((O) (\NlwInverterSignal_U1/U3/holdingreg<0>_MC.D2_PT_2/IN7 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/U3/holdingreg<0>_MC.D2_PT_2/IN8 \ 0 23997 (_entity .  X_INV)
		(_port
			((I) (\U1/U3/RDedge \))
			((O) (\NlwInverterSignal_U1/U3/holdingreg<0>_MC.D2_PT_2/IN8 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/U3/holdingreg<16>_MC.D2_PT_1/IN0 \ 0 24001 (_entity .  X_INV)
		(_port
			((I) (\Reset_II/UIM \))
			((O) (\NlwInverterSignal_U1/U3/holdingreg<16>_MC.D2_PT_1/IN0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/U3/holdingreg<16>_MC.D2_PT_2/IN1 \ 0 24005 (_entity .  X_INV)
		(_port
			((I) (\RD_II/UIM \))
			((O) (\NlwInverterSignal_U1/U3/holdingreg<16>_MC.D2_PT_2/IN1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/U3/holdingreg<16>_MC.D2_PT_2/IN6 \ 0 24009 (_entity .  X_INV)
		(_port
			((I) (U2_ADDR_reg(3)))
			((O) (\NlwInverterSignal_U1/U3/holdingreg<16>_MC.D2_PT_2/IN6 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/U3/holdingreg<16>_MC.D2_PT_2/IN7 \ 0 24013 (_entity .  X_INV)
		(_port
			((I) (\Reset_II/UIM \))
			((O) (\NlwInverterSignal_U1/U3/holdingreg<16>_MC.D2_PT_2/IN7 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/U3/holdingreg<16>_MC.D2_PT_2/IN8 \ 0 24017 (_entity .  X_INV)
		(_port
			((I) (\U1/U3/RDedge \))
			((O) (\NlwInverterSignal_U1/U3/holdingreg<16>_MC.D2_PT_2/IN8 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/U3/holdingreg<8>_MC.D2_PT_1/IN0 \ 0 24021 (_entity .  X_INV)
		(_port
			((I) (\Reset_II/UIM \))
			((O) (\NlwInverterSignal_U1/U3/holdingreg<8>_MC.D2_PT_1/IN0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/U3/holdingreg<8>_MC.D2_PT_2/IN1 \ 0 24025 (_entity .  X_INV)
		(_port
			((I) (\RD_II/UIM \))
			((O) (\NlwInverterSignal_U1/U3/holdingreg<8>_MC.D2_PT_2/IN1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/U3/holdingreg<8>_MC.D2_PT_2/IN6 \ 0 24029 (_entity .  X_INV)
		(_port
			((I) (U2_ADDR_reg(3)))
			((O) (\NlwInverterSignal_U1/U3/holdingreg<8>_MC.D2_PT_2/IN6 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/U3/holdingreg<8>_MC.D2_PT_2/IN7 \ 0 24033 (_entity .  X_INV)
		(_port
			((I) (\Reset_II/UIM \))
			((O) (\NlwInverterSignal_U1/U3/holdingreg<8>_MC.D2_PT_2/IN7 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/U3/holdingreg<8>_MC.D2_PT_2/IN8 \ 0 24037 (_entity .  X_INV)
		(_port
			((I) (\U1/U3/RDedge \))
			((O) (\NlwInverterSignal_U1/U3/holdingreg<8>_MC.D2_PT_2/IN8 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_outDATA<0>\\$WA4.UIM_MC.D2_PT_1/IN1 \ 0 24041 (_entity .  X_INV)
		(_port
			((I) (\RD_II/UIM \))
			((O) (\NlwInverterSignal_outDATA<0>\\$WA4.UIM_MC.D2_PT_1/IN1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_outDATA<0>\\$WA4.UIM_MC.D2_PT_1/IN5 \ 0 24045 (_entity .  X_INV)
		(_port
			((I) (U2_ADDR_reg(2)))
			((O) (\NlwInverterSignal_outDATA<0>\\$WA4.UIM_MC.D2_PT_1/IN5 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_outDATA<0>\\$WA4.UIM_MC.D2_PT_2/IN1 \ 0 24049 (_entity .  X_INV)
		(_port
			((I) (\RD_II/UIM \))
			((O) (\NlwInverterSignal_outDATA<0>\\$WA4.UIM_MC.D2_PT_2/IN1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_outDATA<0>\\$WA4.UIM_MC.D2_PT_2/IN3 \ 0 24053 (_entity .  X_INV)
		(_port
			((I) (U2_ADDR_reg(0)))
			((O) (\NlwInverterSignal_outDATA<0>\\$WA4.UIM_MC.D2_PT_2/IN3 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_outDATA<0>\\$WA4.UIM_MC.D2_PT_2/IN5 \ 0 24057 (_entity .  X_INV)
		(_port
			((I) (U2_ADDR_reg(2)))
			((O) (\NlwInverterSignal_outDATA<0>\\$WA4.UIM_MC.D2_PT_2/IN5 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_outDATA<0>\\$WA4.UIM_MC.D2_PT_3/IN1 \ 0 24061 (_entity .  X_INV)
		(_port
			((I) (\RD_II/UIM \))
			((O) (\NlwInverterSignal_outDATA<0>\\$WA4.UIM_MC.D2_PT_3/IN1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_outDATA<0>\\$WA4.UIM_MC.D2_PT_3/IN2 \ 0 24065 (_entity .  X_INV)
		(_port
			((I) (U2_ADDR_reg(1)))
			((O) (\NlwInverterSignal_outDATA<0>\\$WA4.UIM_MC.D2_PT_3/IN2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_outDATA<0>\\$WA4.UIM_MC.D2_PT_3/IN3 \ 0 24069 (_entity .  X_INV)
		(_port
			((I) (U2_ADDR_reg(0)))
			((O) (\NlwInverterSignal_outDATA<0>\\$WA4.UIM_MC.D2_PT_3/IN3 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/U4/Latch0r<0>_MC.D2_PT_1/IN0 \ 0 24073 (_entity .  X_INV)
		(_port
			((I) (\Reset_II/UIM \))
			((O) (\NlwInverterSignal_U1/U4/Latch0r<0>_MC.D2_PT_1/IN0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/U4/Latch0r<0>_MC.D2_PT_1/IN2 \ 0 24077 (_entity .  X_INV)
		(_port
			((I) (N_PZ_1059))
			((O) (\NlwInverterSignal_U1/U4/Latch0r<0>_MC.D2_PT_1/IN2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/U4/Latch0r<8>_MC.D2_PT_1/IN0 \ 0 24081 (_entity .  X_INV)
		(_port
			((I) (\Reset_II/UIM \))
			((O) (\NlwInverterSignal_U1/U4/Latch0r<8>_MC.D2_PT_1/IN0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/U4/Latch0r<8>_MC.D2_PT_1/IN2 \ 0 24085 (_entity .  X_INV)
		(_port
			((I) (N_PZ_1059))
			((O) (\NlwInverterSignal_U1/U4/Latch0r<8>_MC.D2_PT_1/IN2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/U4/Latch1r<0>_MC.D2_PT_0/IN0 \ 0 24089 (_entity .  X_INV)
		(_port
			((I) (N_PZ_978))
			((O) (\NlwInverterSignal_U1/U4/Latch1r<0>_MC.D2_PT_0/IN0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/U4/Latch1r<0>_MC.D2_PT_1/IN0 \ 0 24093 (_entity .  X_INV)
		(_port
			((I) (\WR_II/UIM \))
			((O) (\NlwInverterSignal_U1/U4/Latch1r<0>_MC.D2_PT_1/IN0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/U4/Latch1r<0>_MC.D2_PT_1/IN4 \ 0 24097 (_entity .  X_INV)
		(_port
			((I) (U2_ADDR_reg(2)))
			((O) (\NlwInverterSignal_U1/U4/Latch1r<0>_MC.D2_PT_1/IN4 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/U4/Latch1r<0>_MC.D2_PT_1/IN5 \ 0 24101 (_entity .  X_INV)
		(_port
			((I) (U2_ADDR_reg(3)))
			((O) (\NlwInverterSignal_U1/U4/Latch1r<0>_MC.D2_PT_1/IN5 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/U4/Latch1r<0>_MC.D2_PT_1/IN6 \ 0 24105 (_entity .  X_INV)
		(_port
			((I) (\Reset_II/UIM \))
			((O) (\NlwInverterSignal_U1/U4/Latch1r<0>_MC.D2_PT_1/IN6 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/U4/Latch1r<8>_MC.D2_PT_0/IN0 \ 0 24109 (_entity .  X_INV)
		(_port
			((I) (N_PZ_978))
			((O) (\NlwInverterSignal_U1/U4/Latch1r<8>_MC.D2_PT_0/IN0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/U4/Latch1r<8>_MC.D2_PT_1/IN0 \ 0 24113 (_entity .  X_INV)
		(_port
			((I) (\WR_II/UIM \))
			((O) (\NlwInverterSignal_U1/U4/Latch1r<8>_MC.D2_PT_1/IN0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/U4/Latch1r<8>_MC.D2_PT_1/IN4 \ 0 24117 (_entity .  X_INV)
		(_port
			((I) (U2_ADDR_reg(2)))
			((O) (\NlwInverterSignal_U1/U4/Latch1r<8>_MC.D2_PT_1/IN4 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/U4/Latch1r<8>_MC.D2_PT_1/IN5 \ 0 24121 (_entity .  X_INV)
		(_port
			((I) (U2_ADDR_reg(3)))
			((O) (\NlwInverterSignal_U1/U4/Latch1r<8>_MC.D2_PT_1/IN5 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/U4/Latch1r<8>_MC.D2_PT_1/IN6 \ 0 24125 (_entity .  X_INV)
		(_port
			((I) (\Reset_II/UIM \))
			((O) (\NlwInverterSignal_U1/U4/Latch1r<8>_MC.D2_PT_1/IN6 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/U3/holdingreg<1>_MC.D2_PT_1/IN0 \ 0 24129 (_entity .  X_INV)
		(_port
			((I) (\Reset_II/UIM \))
			((O) (\NlwInverterSignal_U1/U3/holdingreg<1>_MC.D2_PT_1/IN0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/U3/holdingreg<1>_MC.D2_PT_2/IN1 \ 0 24133 (_entity .  X_INV)
		(_port
			((I) (\RD_II/UIM \))
			((O) (\NlwInverterSignal_U1/U3/holdingreg<1>_MC.D2_PT_2/IN1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/U3/holdingreg<1>_MC.D2_PT_2/IN6 \ 0 24137 (_entity .  X_INV)
		(_port
			((I) (U2_ADDR_reg(3)))
			((O) (\NlwInverterSignal_U1/U3/holdingreg<1>_MC.D2_PT_2/IN6 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/U3/holdingreg<1>_MC.D2_PT_2/IN7 \ 0 24141 (_entity .  X_INV)
		(_port
			((I) (\Reset_II/UIM \))
			((O) (\NlwInverterSignal_U1/U3/holdingreg<1>_MC.D2_PT_2/IN7 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/U3/holdingreg<1>_MC.D2_PT_2/IN8 \ 0 24145 (_entity .  X_INV)
		(_port
			((I) (\U1/U3/RDedge \))
			((O) (\NlwInverterSignal_U1/U3/holdingreg<1>_MC.D2_PT_2/IN8 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/U3/holdingreg<17>_MC.D2_PT_1/IN0 \ 0 24149 (_entity .  X_INV)
		(_port
			((I) (\Reset_II/UIM \))
			((O) (\NlwInverterSignal_U1/U3/holdingreg<17>_MC.D2_PT_1/IN0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/U3/holdingreg<17>_MC.D2_PT_2/IN1 \ 0 24153 (_entity .  X_INV)
		(_port
			((I) (\RD_II/UIM \))
			((O) (\NlwInverterSignal_U1/U3/holdingreg<17>_MC.D2_PT_2/IN1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/U3/holdingreg<17>_MC.D2_PT_2/IN6 \ 0 24157 (_entity .  X_INV)
		(_port
			((I) (U2_ADDR_reg(3)))
			((O) (\NlwInverterSignal_U1/U3/holdingreg<17>_MC.D2_PT_2/IN6 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/U3/holdingreg<17>_MC.D2_PT_2/IN7 \ 0 24161 (_entity .  X_INV)
		(_port
			((I) (\Reset_II/UIM \))
			((O) (\NlwInverterSignal_U1/U3/holdingreg<17>_MC.D2_PT_2/IN7 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/U3/holdingreg<17>_MC.D2_PT_2/IN8 \ 0 24165 (_entity .  X_INV)
		(_port
			((I) (\U1/U3/RDedge \))
			((O) (\NlwInverterSignal_U1/U3/holdingreg<17>_MC.D2_PT_2/IN8 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/U3/holdingreg<9>_MC.D2_PT_1/IN0 \ 0 24169 (_entity .  X_INV)
		(_port
			((I) (\Reset_II/UIM \))
			((O) (\NlwInverterSignal_U1/U3/holdingreg<9>_MC.D2_PT_1/IN0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/U3/holdingreg<9>_MC.D2_PT_2/IN1 \ 0 24173 (_entity .  X_INV)
		(_port
			((I) (\RD_II/UIM \))
			((O) (\NlwInverterSignal_U1/U3/holdingreg<9>_MC.D2_PT_2/IN1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/U3/holdingreg<9>_MC.D2_PT_2/IN6 \ 0 24177 (_entity .  X_INV)
		(_port
			((I) (U2_ADDR_reg(3)))
			((O) (\NlwInverterSignal_U1/U3/holdingreg<9>_MC.D2_PT_2/IN6 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/U3/holdingreg<9>_MC.D2_PT_2/IN7 \ 0 24181 (_entity .  X_INV)
		(_port
			((I) (\Reset_II/UIM \))
			((O) (\NlwInverterSignal_U1/U3/holdingreg<9>_MC.D2_PT_2/IN7 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/U3/holdingreg<9>_MC.D2_PT_2/IN8 \ 0 24185 (_entity .  X_INV)
		(_port
			((I) (\U1/U3/RDedge \))
			((O) (\NlwInverterSignal_U1/U3/holdingreg<9>_MC.D2_PT_2/IN8 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_outDATA<1>\\$WA3.UIM_MC.D2_PT_0/IN1 \ 0 24189 (_entity .  X_INV)
		(_port
			((I) (U2_ADDR_reg(0)))
			((O) (\NlwInverterSignal_outDATA<1>\\$WA3.UIM_MC.D2_PT_0/IN1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_outDATA<1>\\$WA3.UIM_MC.D2_PT_0/IN7 \ 0 24193 (_entity .  X_INV)
		(_port
			((I) (\U4/Flgreg \(1)))
			((O) (\NlwInverterSignal_outDATA<1>\\$WA3.UIM_MC.D2_PT_0/IN7 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_outDATA<1>\\$WA3.UIM_MC.D2_PT_1/IN1 \ 0 24197 (_entity .  X_INV)
		(_port
			((I) (U2_ADDR_reg(0)))
			((O) (\NlwInverterSignal_outDATA<1>\\$WA3.UIM_MC.D2_PT_1/IN1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_outDATA<1>\\$WA3.UIM_MC.D2_PT_1/IN5 \ 0 24201 (_entity .  X_INV)
		(_port
			((I) (NET2528))
			((O) (\NlwInverterSignal_outDATA<1>\\$WA3.UIM_MC.D2_PT_1/IN5 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_outDATA<1>\\$WA4.UIM_MC.D2_PT_1/IN1 \ 0 24205 (_entity .  X_INV)
		(_port
			((I) (\RD_II/UIM \))
			((O) (\NlwInverterSignal_outDATA<1>\\$WA4.UIM_MC.D2_PT_1/IN1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_outDATA<1>\\$WA4.UIM_MC.D2_PT_1/IN5 \ 0 24209 (_entity .  X_INV)
		(_port
			((I) (U2_ADDR_reg(2)))
			((O) (\NlwInverterSignal_outDATA<1>\\$WA4.UIM_MC.D2_PT_1/IN5 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_outDATA<1>\\$WA4.UIM_MC.D2_PT_2/IN1 \ 0 24213 (_entity .  X_INV)
		(_port
			((I) (\RD_II/UIM \))
			((O) (\NlwInverterSignal_outDATA<1>\\$WA4.UIM_MC.D2_PT_2/IN1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_outDATA<1>\\$WA4.UIM_MC.D2_PT_2/IN3 \ 0 24217 (_entity .  X_INV)
		(_port
			((I) (U2_ADDR_reg(0)))
			((O) (\NlwInverterSignal_outDATA<1>\\$WA4.UIM_MC.D2_PT_2/IN3 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_outDATA<1>\\$WA4.UIM_MC.D2_PT_2/IN5 \ 0 24221 (_entity .  X_INV)
		(_port
			((I) (U2_ADDR_reg(2)))
			((O) (\NlwInverterSignal_outDATA<1>\\$WA4.UIM_MC.D2_PT_2/IN5 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_outDATA<1>\\$WA4.UIM_MC.D2_PT_3/IN1 \ 0 24225 (_entity .  X_INV)
		(_port
			((I) (\RD_II/UIM \))
			((O) (\NlwInverterSignal_outDATA<1>\\$WA4.UIM_MC.D2_PT_3/IN1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_outDATA<1>\\$WA4.UIM_MC.D2_PT_3/IN2 \ 0 24229 (_entity .  X_INV)
		(_port
			((I) (U2_ADDR_reg(1)))
			((O) (\NlwInverterSignal_outDATA<1>\\$WA4.UIM_MC.D2_PT_3/IN2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_outDATA<1>\\$WA4.UIM_MC.D2_PT_3/IN3 \ 0 24233 (_entity .  X_INV)
		(_port
			((I) (U2_ADDR_reg(0)))
			((O) (\NlwInverterSignal_outDATA<1>\\$WA4.UIM_MC.D2_PT_3/IN3 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/U4/Latch0r<1>_MC.D2_PT_1/IN0 \ 0 24237 (_entity .  X_INV)
		(_port
			((I) (\Reset_II/UIM \))
			((O) (\NlwInverterSignal_U1/U4/Latch0r<1>_MC.D2_PT_1/IN0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/U4/Latch0r<1>_MC.D2_PT_1/IN2 \ 0 24241 (_entity .  X_INV)
		(_port
			((I) (N_PZ_1059))
			((O) (\NlwInverterSignal_U1/U4/Latch0r<1>_MC.D2_PT_1/IN2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/U4/Latch0r<9>_MC.D2_PT_1/IN0 \ 0 24245 (_entity .  X_INV)
		(_port
			((I) (\Reset_II/UIM \))
			((O) (\NlwInverterSignal_U1/U4/Latch0r<9>_MC.D2_PT_1/IN0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/U4/Latch0r<9>_MC.D2_PT_1/IN2 \ 0 24249 (_entity .  X_INV)
		(_port
			((I) (N_PZ_1059))
			((O) (\NlwInverterSignal_U1/U4/Latch0r<9>_MC.D2_PT_1/IN2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/U4/Latch1r<1>_MC.D2_PT_0/IN0 \ 0 24253 (_entity .  X_INV)
		(_port
			((I) (N_PZ_978))
			((O) (\NlwInverterSignal_U1/U4/Latch1r<1>_MC.D2_PT_0/IN0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/U4/Latch1r<1>_MC.D2_PT_1/IN0 \ 0 24257 (_entity .  X_INV)
		(_port
			((I) (\WR_II/UIM \))
			((O) (\NlwInverterSignal_U1/U4/Latch1r<1>_MC.D2_PT_1/IN0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/U4/Latch1r<1>_MC.D2_PT_1/IN4 \ 0 24261 (_entity .  X_INV)
		(_port
			((I) (U2_ADDR_reg(2)))
			((O) (\NlwInverterSignal_U1/U4/Latch1r<1>_MC.D2_PT_1/IN4 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/U4/Latch1r<1>_MC.D2_PT_1/IN5 \ 0 24265 (_entity .  X_INV)
		(_port
			((I) (U2_ADDR_reg(3)))
			((O) (\NlwInverterSignal_U1/U4/Latch1r<1>_MC.D2_PT_1/IN5 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/U4/Latch1r<1>_MC.D2_PT_1/IN6 \ 0 24269 (_entity .  X_INV)
		(_port
			((I) (\Reset_II/UIM \))
			((O) (\NlwInverterSignal_U1/U4/Latch1r<1>_MC.D2_PT_1/IN6 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/U4/Latch1r<9>_MC.D2_PT_0/IN0 \ 0 24273 (_entity .  X_INV)
		(_port
			((I) (N_PZ_978))
			((O) (\NlwInverterSignal_U1/U4/Latch1r<9>_MC.D2_PT_0/IN0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/U4/Latch1r<9>_MC.D2_PT_1/IN0 \ 0 24277 (_entity .  X_INV)
		(_port
			((I) (\WR_II/UIM \))
			((O) (\NlwInverterSignal_U1/U4/Latch1r<9>_MC.D2_PT_1/IN0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/U4/Latch1r<9>_MC.D2_PT_1/IN4 \ 0 24281 (_entity .  X_INV)
		(_port
			((I) (U2_ADDR_reg(2)))
			((O) (\NlwInverterSignal_U1/U4/Latch1r<9>_MC.D2_PT_1/IN4 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/U4/Latch1r<9>_MC.D2_PT_1/IN5 \ 0 24285 (_entity .  X_INV)
		(_port
			((I) (U2_ADDR_reg(3)))
			((O) (\NlwInverterSignal_U1/U4/Latch1r<9>_MC.D2_PT_1/IN5 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/U4/Latch1r<9>_MC.D2_PT_1/IN6 \ 0 24289 (_entity .  X_INV)
		(_port
			((I) (\Reset_II/UIM \))
			((O) (\NlwInverterSignal_U1/U4/Latch1r<9>_MC.D2_PT_1/IN6 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_outDATA<2>\\$WA3.UIM_MC.D2_PT_1/IN0 \ 0 24293 (_entity .  X_INV)
		(_port
			((I) (NET2528))
			((O) (\NlwInverterSignal_outDATA<2>\\$WA3.UIM_MC.D2_PT_1/IN0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/U3/holdingreg<2>_MC.D2_PT_1/IN0 \ 0 24297 (_entity .  X_INV)
		(_port
			((I) (\Reset_II/UIM \))
			((O) (\NlwInverterSignal_U1/U3/holdingreg<2>_MC.D2_PT_1/IN0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/U3/holdingreg<2>_MC.D2_PT_2/IN1 \ 0 24301 (_entity .  X_INV)
		(_port
			((I) (\RD_II/UIM \))
			((O) (\NlwInverterSignal_U1/U3/holdingreg<2>_MC.D2_PT_2/IN1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/U3/holdingreg<2>_MC.D2_PT_2/IN6 \ 0 24305 (_entity .  X_INV)
		(_port
			((I) (U2_ADDR_reg(3)))
			((O) (\NlwInverterSignal_U1/U3/holdingreg<2>_MC.D2_PT_2/IN6 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/U3/holdingreg<2>_MC.D2_PT_2/IN7 \ 0 24309 (_entity .  X_INV)
		(_port
			((I) (\Reset_II/UIM \))
			((O) (\NlwInverterSignal_U1/U3/holdingreg<2>_MC.D2_PT_2/IN7 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/U3/holdingreg<2>_MC.D2_PT_2/IN8 \ 0 24313 (_entity .  X_INV)
		(_port
			((I) (\U1/U3/RDedge \))
			((O) (\NlwInverterSignal_U1/U3/holdingreg<2>_MC.D2_PT_2/IN8 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/U3/holdingreg<18>_MC.D2_PT_1/IN0 \ 0 24317 (_entity .  X_INV)
		(_port
			((I) (\Reset_II/UIM \))
			((O) (\NlwInverterSignal_U1/U3/holdingreg<18>_MC.D2_PT_1/IN0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/U3/holdingreg<18>_MC.D2_PT_2/IN1 \ 0 24321 (_entity .  X_INV)
		(_port
			((I) (\RD_II/UIM \))
			((O) (\NlwInverterSignal_U1/U3/holdingreg<18>_MC.D2_PT_2/IN1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/U3/holdingreg<18>_MC.D2_PT_2/IN6 \ 0 24325 (_entity .  X_INV)
		(_port
			((I) (U2_ADDR_reg(3)))
			((O) (\NlwInverterSignal_U1/U3/holdingreg<18>_MC.D2_PT_2/IN6 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/U3/holdingreg<18>_MC.D2_PT_2/IN7 \ 0 24329 (_entity .  X_INV)
		(_port
			((I) (\Reset_II/UIM \))
			((O) (\NlwInverterSignal_U1/U3/holdingreg<18>_MC.D2_PT_2/IN7 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/U3/holdingreg<18>_MC.D2_PT_2/IN8 \ 0 24333 (_entity .  X_INV)
		(_port
			((I) (\U1/U3/RDedge \))
			((O) (\NlwInverterSignal_U1/U3/holdingreg<18>_MC.D2_PT_2/IN8 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/U3/holdingreg<10>_MC.D2_PT_1/IN0 \ 0 24337 (_entity .  X_INV)
		(_port
			((I) (\Reset_II/UIM \))
			((O) (\NlwInverterSignal_U1/U3/holdingreg<10>_MC.D2_PT_1/IN0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/U3/holdingreg<10>_MC.D2_PT_2/IN1 \ 0 24341 (_entity .  X_INV)
		(_port
			((I) (\RD_II/UIM \))
			((O) (\NlwInverterSignal_U1/U3/holdingreg<10>_MC.D2_PT_2/IN1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/U3/holdingreg<10>_MC.D2_PT_2/IN6 \ 0 24345 (_entity .  X_INV)
		(_port
			((I) (U2_ADDR_reg(3)))
			((O) (\NlwInverterSignal_U1/U3/holdingreg<10>_MC.D2_PT_2/IN6 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/U3/holdingreg<10>_MC.D2_PT_2/IN7 \ 0 24349 (_entity .  X_INV)
		(_port
			((I) (\Reset_II/UIM \))
			((O) (\NlwInverterSignal_U1/U3/holdingreg<10>_MC.D2_PT_2/IN7 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/U3/holdingreg<10>_MC.D2_PT_2/IN8 \ 0 24353 (_entity .  X_INV)
		(_port
			((I) (\U1/U3/RDedge \))
			((O) (\NlwInverterSignal_U1/U3/holdingreg<10>_MC.D2_PT_2/IN8 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_outDATA<2>\\$WA4.UIM_MC.D2_PT_1/IN1 \ 0 24357 (_entity .  X_INV)
		(_port
			((I) (\RD_II/UIM \))
			((O) (\NlwInverterSignal_outDATA<2>\\$WA4.UIM_MC.D2_PT_1/IN1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_outDATA<2>\\$WA4.UIM_MC.D2_PT_1/IN5 \ 0 24361 (_entity .  X_INV)
		(_port
			((I) (U2_ADDR_reg(2)))
			((O) (\NlwInverterSignal_outDATA<2>\\$WA4.UIM_MC.D2_PT_1/IN5 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_outDATA<2>\\$WA4.UIM_MC.D2_PT_2/IN1 \ 0 24365 (_entity .  X_INV)
		(_port
			((I) (\RD_II/UIM \))
			((O) (\NlwInverterSignal_outDATA<2>\\$WA4.UIM_MC.D2_PT_2/IN1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_outDATA<2>\\$WA4.UIM_MC.D2_PT_2/IN3 \ 0 24369 (_entity .  X_INV)
		(_port
			((I) (U2_ADDR_reg(0)))
			((O) (\NlwInverterSignal_outDATA<2>\\$WA4.UIM_MC.D2_PT_2/IN3 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_outDATA<2>\\$WA4.UIM_MC.D2_PT_2/IN5 \ 0 24373 (_entity .  X_INV)
		(_port
			((I) (U2_ADDR_reg(2)))
			((O) (\NlwInverterSignal_outDATA<2>\\$WA4.UIM_MC.D2_PT_2/IN5 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_outDATA<2>\\$WA4.UIM_MC.D2_PT_3/IN1 \ 0 24377 (_entity .  X_INV)
		(_port
			((I) (\RD_II/UIM \))
			((O) (\NlwInverterSignal_outDATA<2>\\$WA4.UIM_MC.D2_PT_3/IN1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_outDATA<2>\\$WA4.UIM_MC.D2_PT_3/IN2 \ 0 24381 (_entity .  X_INV)
		(_port
			((I) (U2_ADDR_reg(1)))
			((O) (\NlwInverterSignal_outDATA<2>\\$WA4.UIM_MC.D2_PT_3/IN2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_outDATA<2>\\$WA4.UIM_MC.D2_PT_3/IN3 \ 0 24385 (_entity .  X_INV)
		(_port
			((I) (U2_ADDR_reg(0)))
			((O) (\NlwInverterSignal_outDATA<2>\\$WA4.UIM_MC.D2_PT_3/IN3 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/U4/Latch0r<10>_MC.D2_PT_1/IN0 \ 0 24389 (_entity .  X_INV)
		(_port
			((I) (\Reset_II/UIM \))
			((O) (\NlwInverterSignal_U1/U4/Latch0r<10>_MC.D2_PT_1/IN0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/U4/Latch0r<10>_MC.D2_PT_1/IN2 \ 0 24393 (_entity .  X_INV)
		(_port
			((I) (N_PZ_1059))
			((O) (\NlwInverterSignal_U1/U4/Latch0r<10>_MC.D2_PT_1/IN2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/U4/Latch0r<2>_MC.D2_PT_1/IN0 \ 0 24397 (_entity .  X_INV)
		(_port
			((I) (\Reset_II/UIM \))
			((O) (\NlwInverterSignal_U1/U4/Latch0r<2>_MC.D2_PT_1/IN0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/U4/Latch0r<2>_MC.D2_PT_1/IN2 \ 0 24401 (_entity .  X_INV)
		(_port
			((I) (N_PZ_1059))
			((O) (\NlwInverterSignal_U1/U4/Latch0r<2>_MC.D2_PT_1/IN2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/U4/Latch1r<2>_MC.D2_PT_0/IN0 \ 0 24405 (_entity .  X_INV)
		(_port
			((I) (N_PZ_978))
			((O) (\NlwInverterSignal_U1/U4/Latch1r<2>_MC.D2_PT_0/IN0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/U4/Latch1r<2>_MC.D2_PT_1/IN0 \ 0 24409 (_entity .  X_INV)
		(_port
			((I) (\WR_II/UIM \))
			((O) (\NlwInverterSignal_U1/U4/Latch1r<2>_MC.D2_PT_1/IN0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/U4/Latch1r<2>_MC.D2_PT_1/IN4 \ 0 24413 (_entity .  X_INV)
		(_port
			((I) (U2_ADDR_reg(2)))
			((O) (\NlwInverterSignal_U1/U4/Latch1r<2>_MC.D2_PT_1/IN4 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/U4/Latch1r<2>_MC.D2_PT_1/IN5 \ 0 24417 (_entity .  X_INV)
		(_port
			((I) (U2_ADDR_reg(3)))
			((O) (\NlwInverterSignal_U1/U4/Latch1r<2>_MC.D2_PT_1/IN5 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/U4/Latch1r<2>_MC.D2_PT_1/IN6 \ 0 24421 (_entity .  X_INV)
		(_port
			((I) (\Reset_II/UIM \))
			((O) (\NlwInverterSignal_U1/U4/Latch1r<2>_MC.D2_PT_1/IN6 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/U4/Latch1r<10>_MC.D2_PT_0/IN0 \ 0 24425 (_entity .  X_INV)
		(_port
			((I) (N_PZ_978))
			((O) (\NlwInverterSignal_U1/U4/Latch1r<10>_MC.D2_PT_0/IN0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/U4/Latch1r<10>_MC.D2_PT_1/IN0 \ 0 24429 (_entity .  X_INV)
		(_port
			((I) (\WR_II/UIM \))
			((O) (\NlwInverterSignal_U1/U4/Latch1r<10>_MC.D2_PT_1/IN0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/U4/Latch1r<10>_MC.D2_PT_1/IN4 \ 0 24433 (_entity .  X_INV)
		(_port
			((I) (U2_ADDR_reg(2)))
			((O) (\NlwInverterSignal_U1/U4/Latch1r<10>_MC.D2_PT_1/IN4 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/U4/Latch1r<10>_MC.D2_PT_1/IN5 \ 0 24437 (_entity .  X_INV)
		(_port
			((I) (U2_ADDR_reg(3)))
			((O) (\NlwInverterSignal_U1/U4/Latch1r<10>_MC.D2_PT_1/IN5 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/U4/Latch1r<10>_MC.D2_PT_1/IN6 \ 0 24441 (_entity .  X_INV)
		(_port
			((I) (\Reset_II/UIM \))
			((O) (\NlwInverterSignal_U1/U4/Latch1r<10>_MC.D2_PT_1/IN6 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_outDATA<3>\\$WA3.UIM_MC.D2_PT_1/IN0 \ 0 24445 (_entity .  X_INV)
		(_port
			((I) (NET2528))
			((O) (\NlwInverterSignal_outDATA<3>\\$WA3.UIM_MC.D2_PT_1/IN0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/U3/holdingreg<3>_MC.D2_PT_1/IN0 \ 0 24449 (_entity .  X_INV)
		(_port
			((I) (\Reset_II/UIM \))
			((O) (\NlwInverterSignal_U1/U3/holdingreg<3>_MC.D2_PT_1/IN0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/U3/holdingreg<3>_MC.D2_PT_2/IN1 \ 0 24453 (_entity .  X_INV)
		(_port
			((I) (\RD_II/UIM \))
			((O) (\NlwInverterSignal_U1/U3/holdingreg<3>_MC.D2_PT_2/IN1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/U3/holdingreg<3>_MC.D2_PT_2/IN6 \ 0 24457 (_entity .  X_INV)
		(_port
			((I) (U2_ADDR_reg(3)))
			((O) (\NlwInverterSignal_U1/U3/holdingreg<3>_MC.D2_PT_2/IN6 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/U3/holdingreg<3>_MC.D2_PT_2/IN7 \ 0 24461 (_entity .  X_INV)
		(_port
			((I) (\Reset_II/UIM \))
			((O) (\NlwInverterSignal_U1/U3/holdingreg<3>_MC.D2_PT_2/IN7 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/U3/holdingreg<3>_MC.D2_PT_2/IN8 \ 0 24465 (_entity .  X_INV)
		(_port
			((I) (\U1/U3/RDedge \))
			((O) (\NlwInverterSignal_U1/U3/holdingreg<3>_MC.D2_PT_2/IN8 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/U3/holdingreg<19>_MC.D2_PT_1/IN0 \ 0 24469 (_entity .  X_INV)
		(_port
			((I) (\Reset_II/UIM \))
			((O) (\NlwInverterSignal_U1/U3/holdingreg<19>_MC.D2_PT_1/IN0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/U3/holdingreg<19>_MC.D2_PT_2/IN1 \ 0 24473 (_entity .  X_INV)
		(_port
			((I) (\RD_II/UIM \))
			((O) (\NlwInverterSignal_U1/U3/holdingreg<19>_MC.D2_PT_2/IN1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/U3/holdingreg<19>_MC.D2_PT_2/IN6 \ 0 24477 (_entity .  X_INV)
		(_port
			((I) (U2_ADDR_reg(3)))
			((O) (\NlwInverterSignal_U1/U3/holdingreg<19>_MC.D2_PT_2/IN6 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/U3/holdingreg<19>_MC.D2_PT_2/IN7 \ 0 24481 (_entity .  X_INV)
		(_port
			((I) (\Reset_II/UIM \))
			((O) (\NlwInverterSignal_U1/U3/holdingreg<19>_MC.D2_PT_2/IN7 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/U3/holdingreg<19>_MC.D2_PT_2/IN8 \ 0 24485 (_entity .  X_INV)
		(_port
			((I) (\U1/U3/RDedge \))
			((O) (\NlwInverterSignal_U1/U3/holdingreg<19>_MC.D2_PT_2/IN8 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/U3/holdingreg<11>_MC.D2_PT_1/IN0 \ 0 24489 (_entity .  X_INV)
		(_port
			((I) (\Reset_II/UIM \))
			((O) (\NlwInverterSignal_U1/U3/holdingreg<11>_MC.D2_PT_1/IN0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/U3/holdingreg<11>_MC.D2_PT_2/IN1 \ 0 24493 (_entity .  X_INV)
		(_port
			((I) (\RD_II/UIM \))
			((O) (\NlwInverterSignal_U1/U3/holdingreg<11>_MC.D2_PT_2/IN1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/U3/holdingreg<11>_MC.D2_PT_2/IN6 \ 0 24497 (_entity .  X_INV)
		(_port
			((I) (U2_ADDR_reg(3)))
			((O) (\NlwInverterSignal_U1/U3/holdingreg<11>_MC.D2_PT_2/IN6 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/U3/holdingreg<11>_MC.D2_PT_2/IN7 \ 0 24501 (_entity .  X_INV)
		(_port
			((I) (\Reset_II/UIM \))
			((O) (\NlwInverterSignal_U1/U3/holdingreg<11>_MC.D2_PT_2/IN7 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/U3/holdingreg<11>_MC.D2_PT_2/IN8 \ 0 24505 (_entity .  X_INV)
		(_port
			((I) (\U1/U3/RDedge \))
			((O) (\NlwInverterSignal_U1/U3/holdingreg<11>_MC.D2_PT_2/IN8 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_outDATA<3>\\$WA4.UIM_MC.D2_PT_1/IN1 \ 0 24509 (_entity .  X_INV)
		(_port
			((I) (\RD_II/UIM \))
			((O) (\NlwInverterSignal_outDATA<3>\\$WA4.UIM_MC.D2_PT_1/IN1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_outDATA<3>\\$WA4.UIM_MC.D2_PT_1/IN5 \ 0 24513 (_entity .  X_INV)
		(_port
			((I) (U2_ADDR_reg(2)))
			((O) (\NlwInverterSignal_outDATA<3>\\$WA4.UIM_MC.D2_PT_1/IN5 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_outDATA<3>\\$WA4.UIM_MC.D2_PT_2/IN1 \ 0 24517 (_entity .  X_INV)
		(_port
			((I) (\RD_II/UIM \))
			((O) (\NlwInverterSignal_outDATA<3>\\$WA4.UIM_MC.D2_PT_2/IN1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_outDATA<3>\\$WA4.UIM_MC.D2_PT_2/IN3 \ 0 24521 (_entity .  X_INV)
		(_port
			((I) (U2_ADDR_reg(0)))
			((O) (\NlwInverterSignal_outDATA<3>\\$WA4.UIM_MC.D2_PT_2/IN3 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_outDATA<3>\\$WA4.UIM_MC.D2_PT_2/IN5 \ 0 24525 (_entity .  X_INV)
		(_port
			((I) (U2_ADDR_reg(2)))
			((O) (\NlwInverterSignal_outDATA<3>\\$WA4.UIM_MC.D2_PT_2/IN5 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_outDATA<3>\\$WA4.UIM_MC.D2_PT_3/IN1 \ 0 24529 (_entity .  X_INV)
		(_port
			((I) (\RD_II/UIM \))
			((O) (\NlwInverterSignal_outDATA<3>\\$WA4.UIM_MC.D2_PT_3/IN1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_outDATA<3>\\$WA4.UIM_MC.D2_PT_3/IN2 \ 0 24533 (_entity .  X_INV)
		(_port
			((I) (U2_ADDR_reg(1)))
			((O) (\NlwInverterSignal_outDATA<3>\\$WA4.UIM_MC.D2_PT_3/IN2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_outDATA<3>\\$WA4.UIM_MC.D2_PT_3/IN3 \ 0 24537 (_entity .  X_INV)
		(_port
			((I) (U2_ADDR_reg(0)))
			((O) (\NlwInverterSignal_outDATA<3>\\$WA4.UIM_MC.D2_PT_3/IN3 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/U4/Latch0r<11>_MC.D2_PT_1/IN0 \ 0 24541 (_entity .  X_INV)
		(_port
			((I) (\Reset_II/UIM \))
			((O) (\NlwInverterSignal_U1/U4/Latch0r<11>_MC.D2_PT_1/IN0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/U4/Latch0r<11>_MC.D2_PT_1/IN2 \ 0 24545 (_entity .  X_INV)
		(_port
			((I) (N_PZ_1059))
			((O) (\NlwInverterSignal_U1/U4/Latch0r<11>_MC.D2_PT_1/IN2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/U4/Latch0r<3>_MC.D2_PT_1/IN0 \ 0 24549 (_entity .  X_INV)
		(_port
			((I) (\Reset_II/UIM \))
			((O) (\NlwInverterSignal_U1/U4/Latch0r<3>_MC.D2_PT_1/IN0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/U4/Latch0r<3>_MC.D2_PT_1/IN2 \ 0 24553 (_entity .  X_INV)
		(_port
			((I) (N_PZ_1059))
			((O) (\NlwInverterSignal_U1/U4/Latch0r<3>_MC.D2_PT_1/IN2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/U4/Latch1r<3>_MC.D2_PT_0/IN0 \ 0 24557 (_entity .  X_INV)
		(_port
			((I) (N_PZ_978))
			((O) (\NlwInverterSignal_U1/U4/Latch1r<3>_MC.D2_PT_0/IN0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/U4/Latch1r<3>_MC.D2_PT_1/IN0 \ 0 24561 (_entity .  X_INV)
		(_port
			((I) (\WR_II/UIM \))
			((O) (\NlwInverterSignal_U1/U4/Latch1r<3>_MC.D2_PT_1/IN0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/U4/Latch1r<3>_MC.D2_PT_1/IN4 \ 0 24565 (_entity .  X_INV)
		(_port
			((I) (U2_ADDR_reg(2)))
			((O) (\NlwInverterSignal_U1/U4/Latch1r<3>_MC.D2_PT_1/IN4 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/U4/Latch1r<3>_MC.D2_PT_1/IN5 \ 0 24569 (_entity .  X_INV)
		(_port
			((I) (U2_ADDR_reg(3)))
			((O) (\NlwInverterSignal_U1/U4/Latch1r<3>_MC.D2_PT_1/IN5 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/U4/Latch1r<3>_MC.D2_PT_1/IN6 \ 0 24573 (_entity .  X_INV)
		(_port
			((I) (\Reset_II/UIM \))
			((O) (\NlwInverterSignal_U1/U4/Latch1r<3>_MC.D2_PT_1/IN6 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/U4/Latch1r<11>_MC.D2_PT_0/IN0 \ 0 24577 (_entity .  X_INV)
		(_port
			((I) (N_PZ_978))
			((O) (\NlwInverterSignal_U1/U4/Latch1r<11>_MC.D2_PT_0/IN0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/U4/Latch1r<11>_MC.D2_PT_1/IN0 \ 0 24581 (_entity .  X_INV)
		(_port
			((I) (\WR_II/UIM \))
			((O) (\NlwInverterSignal_U1/U4/Latch1r<11>_MC.D2_PT_1/IN0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/U4/Latch1r<11>_MC.D2_PT_1/IN4 \ 0 24585 (_entity .  X_INV)
		(_port
			((I) (U2_ADDR_reg(2)))
			((O) (\NlwInverterSignal_U1/U4/Latch1r<11>_MC.D2_PT_1/IN4 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/U4/Latch1r<11>_MC.D2_PT_1/IN5 \ 0 24589 (_entity .  X_INV)
		(_port
			((I) (U2_ADDR_reg(3)))
			((O) (\NlwInverterSignal_U1/U4/Latch1r<11>_MC.D2_PT_1/IN5 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/U4/Latch1r<11>_MC.D2_PT_1/IN6 \ 0 24593 (_entity .  X_INV)
		(_port
			((I) (\Reset_II/UIM \))
			((O) (\NlwInverterSignal_U1/U4/Latch1r<11>_MC.D2_PT_1/IN6 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_outDATA<4>\\$WA3.UIM_MC.D2_PT_1/IN0 \ 0 24597 (_entity .  X_INV)
		(_port
			((I) (NET2528))
			((O) (\NlwInverterSignal_outDATA<4>\\$WA3.UIM_MC.D2_PT_1/IN0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/U3/holdingreg<4>_MC.D2_PT_1/IN0 \ 0 24601 (_entity .  X_INV)
		(_port
			((I) (\Reset_II/UIM \))
			((O) (\NlwInverterSignal_U1/U3/holdingreg<4>_MC.D2_PT_1/IN0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/U3/holdingreg<4>_MC.D2_PT_2/IN1 \ 0 24605 (_entity .  X_INV)
		(_port
			((I) (\RD_II/UIM \))
			((O) (\NlwInverterSignal_U1/U3/holdingreg<4>_MC.D2_PT_2/IN1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/U3/holdingreg<4>_MC.D2_PT_2/IN6 \ 0 24609 (_entity .  X_INV)
		(_port
			((I) (U2_ADDR_reg(3)))
			((O) (\NlwInverterSignal_U1/U3/holdingreg<4>_MC.D2_PT_2/IN6 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/U3/holdingreg<4>_MC.D2_PT_2/IN7 \ 0 24613 (_entity .  X_INV)
		(_port
			((I) (\Reset_II/UIM \))
			((O) (\NlwInverterSignal_U1/U3/holdingreg<4>_MC.D2_PT_2/IN7 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/U3/holdingreg<4>_MC.D2_PT_2/IN8 \ 0 24617 (_entity .  X_INV)
		(_port
			((I) (\U1/U3/RDedge \))
			((O) (\NlwInverterSignal_U1/U3/holdingreg<4>_MC.D2_PT_2/IN8 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/U3/holdingreg<20>_MC.D2_PT_1/IN0 \ 0 24621 (_entity .  X_INV)
		(_port
			((I) (\Reset_II/UIM \))
			((O) (\NlwInverterSignal_U1/U3/holdingreg<20>_MC.D2_PT_1/IN0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/U3/holdingreg<20>_MC.D2_PT_2/IN1 \ 0 24625 (_entity .  X_INV)
		(_port
			((I) (\RD_II/UIM \))
			((O) (\NlwInverterSignal_U1/U3/holdingreg<20>_MC.D2_PT_2/IN1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/U3/holdingreg<20>_MC.D2_PT_2/IN6 \ 0 24629 (_entity .  X_INV)
		(_port
			((I) (U2_ADDR_reg(3)))
			((O) (\NlwInverterSignal_U1/U3/holdingreg<20>_MC.D2_PT_2/IN6 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/U3/holdingreg<20>_MC.D2_PT_2/IN7 \ 0 24633 (_entity .  X_INV)
		(_port
			((I) (\Reset_II/UIM \))
			((O) (\NlwInverterSignal_U1/U3/holdingreg<20>_MC.D2_PT_2/IN7 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/U3/holdingreg<20>_MC.D2_PT_2/IN8 \ 0 24637 (_entity .  X_INV)
		(_port
			((I) (\U1/U3/RDedge \))
			((O) (\NlwInverterSignal_U1/U3/holdingreg<20>_MC.D2_PT_2/IN8 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/U3/holdingreg<12>_MC.D2_PT_1/IN0 \ 0 24641 (_entity .  X_INV)
		(_port
			((I) (\Reset_II/UIM \))
			((O) (\NlwInverterSignal_U1/U3/holdingreg<12>_MC.D2_PT_1/IN0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/U3/holdingreg<12>_MC.D2_PT_2/IN1 \ 0 24645 (_entity .  X_INV)
		(_port
			((I) (\RD_II/UIM \))
			((O) (\NlwInverterSignal_U1/U3/holdingreg<12>_MC.D2_PT_2/IN1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/U3/holdingreg<12>_MC.D2_PT_2/IN6 \ 0 24649 (_entity .  X_INV)
		(_port
			((I) (U2_ADDR_reg(3)))
			((O) (\NlwInverterSignal_U1/U3/holdingreg<12>_MC.D2_PT_2/IN6 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/U3/holdingreg<12>_MC.D2_PT_2/IN7 \ 0 24653 (_entity .  X_INV)
		(_port
			((I) (\Reset_II/UIM \))
			((O) (\NlwInverterSignal_U1/U3/holdingreg<12>_MC.D2_PT_2/IN7 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/U3/holdingreg<12>_MC.D2_PT_2/IN8 \ 0 24657 (_entity .  X_INV)
		(_port
			((I) (\U1/U3/RDedge \))
			((O) (\NlwInverterSignal_U1/U3/holdingreg<12>_MC.D2_PT_2/IN8 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_outDATA<4>\\$WA4.UIM_MC.D2_PT_1/IN1 \ 0 24661 (_entity .  X_INV)
		(_port
			((I) (\RD_II/UIM \))
			((O) (\NlwInverterSignal_outDATA<4>\\$WA4.UIM_MC.D2_PT_1/IN1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_outDATA<4>\\$WA4.UIM_MC.D2_PT_1/IN5 \ 0 24665 (_entity .  X_INV)
		(_port
			((I) (U2_ADDR_reg(2)))
			((O) (\NlwInverterSignal_outDATA<4>\\$WA4.UIM_MC.D2_PT_1/IN5 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_outDATA<4>\\$WA4.UIM_MC.D2_PT_2/IN1 \ 0 24669 (_entity .  X_INV)
		(_port
			((I) (\RD_II/UIM \))
			((O) (\NlwInverterSignal_outDATA<4>\\$WA4.UIM_MC.D2_PT_2/IN1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_outDATA<4>\\$WA4.UIM_MC.D2_PT_2/IN3 \ 0 24673 (_entity .  X_INV)
		(_port
			((I) (U2_ADDR_reg(0)))
			((O) (\NlwInverterSignal_outDATA<4>\\$WA4.UIM_MC.D2_PT_2/IN3 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_outDATA<4>\\$WA4.UIM_MC.D2_PT_2/IN5 \ 0 24677 (_entity .  X_INV)
		(_port
			((I) (U2_ADDR_reg(2)))
			((O) (\NlwInverterSignal_outDATA<4>\\$WA4.UIM_MC.D2_PT_2/IN5 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_outDATA<4>\\$WA4.UIM_MC.D2_PT_3/IN1 \ 0 24681 (_entity .  X_INV)
		(_port
			((I) (\RD_II/UIM \))
			((O) (\NlwInverterSignal_outDATA<4>\\$WA4.UIM_MC.D2_PT_3/IN1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_outDATA<4>\\$WA4.UIM_MC.D2_PT_3/IN2 \ 0 24685 (_entity .  X_INV)
		(_port
			((I) (U2_ADDR_reg(1)))
			((O) (\NlwInverterSignal_outDATA<4>\\$WA4.UIM_MC.D2_PT_3/IN2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_outDATA<4>\\$WA4.UIM_MC.D2_PT_3/IN3 \ 0 24689 (_entity .  X_INV)
		(_port
			((I) (U2_ADDR_reg(0)))
			((O) (\NlwInverterSignal_outDATA<4>\\$WA4.UIM_MC.D2_PT_3/IN3 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/U4/Latch0r<12>_MC.D2_PT_1/IN0 \ 0 24693 (_entity .  X_INV)
		(_port
			((I) (\Reset_II/UIM \))
			((O) (\NlwInverterSignal_U1/U4/Latch0r<12>_MC.D2_PT_1/IN0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/U4/Latch0r<12>_MC.D2_PT_1/IN2 \ 0 24697 (_entity .  X_INV)
		(_port
			((I) (N_PZ_1059))
			((O) (\NlwInverterSignal_U1/U4/Latch0r<12>_MC.D2_PT_1/IN2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/U4/Latch0r<4>_MC.D2_PT_1/IN0 \ 0 24701 (_entity .  X_INV)
		(_port
			((I) (\Reset_II/UIM \))
			((O) (\NlwInverterSignal_U1/U4/Latch0r<4>_MC.D2_PT_1/IN0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/U4/Latch0r<4>_MC.D2_PT_1/IN2 \ 0 24705 (_entity .  X_INV)
		(_port
			((I) (N_PZ_1059))
			((O) (\NlwInverterSignal_U1/U4/Latch0r<4>_MC.D2_PT_1/IN2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/U4/Latch1r<4>_MC.D2_PT_0/IN0 \ 0 24709 (_entity .  X_INV)
		(_port
			((I) (N_PZ_978))
			((O) (\NlwInverterSignal_U1/U4/Latch1r<4>_MC.D2_PT_0/IN0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/U4/Latch1r<4>_MC.D2_PT_1/IN0 \ 0 24713 (_entity .  X_INV)
		(_port
			((I) (\WR_II/UIM \))
			((O) (\NlwInverterSignal_U1/U4/Latch1r<4>_MC.D2_PT_1/IN0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/U4/Latch1r<4>_MC.D2_PT_1/IN4 \ 0 24717 (_entity .  X_INV)
		(_port
			((I) (U2_ADDR_reg(2)))
			((O) (\NlwInverterSignal_U1/U4/Latch1r<4>_MC.D2_PT_1/IN4 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/U4/Latch1r<4>_MC.D2_PT_1/IN5 \ 0 24721 (_entity .  X_INV)
		(_port
			((I) (U2_ADDR_reg(3)))
			((O) (\NlwInverterSignal_U1/U4/Latch1r<4>_MC.D2_PT_1/IN5 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/U4/Latch1r<4>_MC.D2_PT_1/IN6 \ 0 24725 (_entity .  X_INV)
		(_port
			((I) (\Reset_II/UIM \))
			((O) (\NlwInverterSignal_U1/U4/Latch1r<4>_MC.D2_PT_1/IN6 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/U4/Latch1r<12>_MC.D2_PT_0/IN0 \ 0 24729 (_entity .  X_INV)
		(_port
			((I) (N_PZ_978))
			((O) (\NlwInverterSignal_U1/U4/Latch1r<12>_MC.D2_PT_0/IN0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/U4/Latch1r<12>_MC.D2_PT_1/IN0 \ 0 24733 (_entity .  X_INV)
		(_port
			((I) (\WR_II/UIM \))
			((O) (\NlwInverterSignal_U1/U4/Latch1r<12>_MC.D2_PT_1/IN0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/U4/Latch1r<12>_MC.D2_PT_1/IN4 \ 0 24737 (_entity .  X_INV)
		(_port
			((I) (U2_ADDR_reg(2)))
			((O) (\NlwInverterSignal_U1/U4/Latch1r<12>_MC.D2_PT_1/IN4 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/U4/Latch1r<12>_MC.D2_PT_1/IN5 \ 0 24741 (_entity .  X_INV)
		(_port
			((I) (U2_ADDR_reg(3)))
			((O) (\NlwInverterSignal_U1/U4/Latch1r<12>_MC.D2_PT_1/IN5 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_U1/U4/Latch1r<12>_MC.D2_PT_1/IN6 \ 0 24745 (_entity .  X_INV)
		(_port
			((I) (\Reset_II/UIM \))
			((O) (\NlwInverterSignal_U1/U4/Latch1r<12>_MC.D2_PT_1/IN6 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_FOOBAR4__ctinst/0/IN0 \ 0 24749 (_entity .  X_INV)
		(_port
			((I) (U11_U3_counterr(5)))
			((O) (\NlwInverterSignal_FOOBAR4__ctinst/0/IN0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_FOOBAR4__ctinst/0/IN1 \ 0 24753 (_entity .  X_INV)
		(_port
			((I) (U11_U3_counterr(3)))
			((O) (\NlwInverterSignal_FOOBAR4__ctinst/0/IN1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_FOOBAR4__ctinst/0/IN2 \ 0 24757 (_entity .  X_INV)
		(_port
			((I) (U11_U3_counterr(4)))
			((O) (\NlwInverterSignal_FOOBAR4__ctinst/0/IN2 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_FOOBAR4__ctinst/0/IN3 \ 0 24761 (_entity .  X_INV)
		(_port
			((I) (U11_U3_counterr(0)))
			((O) (\NlwInverterSignal_FOOBAR4__ctinst/0/IN3 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_FOOBAR4__ctinst/0/IN4 \ 0 24765 (_entity .  X_INV)
		(_port
			((I) (U11_U3_counterr(1)))
			((O) (\NlwInverterSignal_FOOBAR4__ctinst/0/IN4 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_FOOBAR4__ctinst/0/IN5 \ 0 24769 (_entity .  X_INV)
		(_port
			((I) (U11_U3_counterr(2)))
			((O) (\NlwInverterSignal_FOOBAR4__ctinst/0/IN5 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_FOOBAR7__ctinst/4/IN0 \ 0 24773 (_entity .  X_INV)
		(_port
			((I) (\WR_II/UIM \))
			((O) (\NlwInverterSignal_FOOBAR7__ctinst/4/IN0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_FOOBAR8__ctinst/4/IN0 \ 0 24777 (_entity .  X_INV)
		(_port
			((I) (\WR_II/UIM \))
			((O) (\NlwInverterSignal_FOOBAR8__ctinst/4/IN0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_FOOBAR10__ctinst/4/IN0 \ 0 24781 (_entity .  X_INV)
		(_port
			((I) (\WR_II/UIM \))
			((O) (\NlwInverterSignal_FOOBAR10__ctinst/4/IN0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_FOOBAR12__ctinst/4/IN0 \ 0 24785 (_entity .  X_INV)
		(_port
			((I) (\WR_II/UIM \))
			((O) (\NlwInverterSignal_FOOBAR12__ctinst/4/IN0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_FOOBAR14__ctinst/4/IN0 \ 0 24789 (_entity .  X_INV)
		(_port
			((I) (\WR_II/UIM \))
			((O) (\NlwInverterSignal_FOOBAR14__ctinst/4/IN0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_FOOBAR14__ctinst/4/IN3 \ 0 24793 (_entity .  X_INV)
		(_port
			((I) (U2_ADDR_reg(0)))
			((O) (\NlwInverterSignal_FOOBAR14__ctinst/4/IN3 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_FOOBAR15__ctinst/4/IN0 \ 0 24797 (_entity .  X_INV)
		(_port
			((I) (\WR_II/UIM \))
			((O) (\NlwInverterSignal_FOOBAR15__ctinst/4/IN0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_FOOBAR16__ctinst/4/IN0 \ 0 24801 (_entity .  X_INV)
		(_port
			((I) (U2_WRRDedge))
			((O) (\NlwInverterSignal_FOOBAR16__ctinst/4/IN0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_FOOBAR16__ctinst/4/IN1 \ 0 24805 (_entity .  X_INV)
		(_port
			((I) (U2__n0017))
			((O) (\NlwInverterSignal_FOOBAR16__ctinst/4/IN1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_FOOBAR18__ctinst/4/IN0 \ 0 24809 (_entity .  X_INV)
		(_port
			((I) (\WR_II/UIM \))
			((O) (\NlwInverterSignal_FOOBAR18__ctinst/4/IN0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_FOOBAR21__ctinst/4/IN0 \ 0 24813 (_entity .  X_INV)
		(_port
			((I) (NET2528))
			((O) (\NlwInverterSignal_FOOBAR21__ctinst/4/IN0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_FOOBAR21__ctinst/4/IN1 \ 0 24817 (_entity .  X_INV)
		(_port
			((I) (\U4/orFLGs \))
			((O) (\NlwInverterSignal_FOOBAR21__ctinst/4/IN1 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_FOOBAR23__ctinst/4/IN0 \ 0 24821 (_entity .  X_INV)
		(_port
			((I) (\WR_II/UIM \))
			((O) (\NlwInverterSignal_FOOBAR23__ctinst/4/IN0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_FOOBAR23__ctinst/4/IN3 \ 0 24825 (_entity .  X_INV)
		(_port
			((I) (U2_ADDR_reg(0)))
			((O) (\NlwInverterSignal_FOOBAR23__ctinst/4/IN3 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_FOOBAR24__ctinst/4/IN0 \ 0 24829 (_entity .  X_INV)
		(_port
			((I) (NET2528))
			((O) (\NlwInverterSignal_FOOBAR24__ctinst/4/IN0 \))
		)
		(_strength strong0 strong1)
	)
	(_instantiation \NlwInverterBlock_FOOBAR24__ctinst/4/IN1 \ 0 24833 (_entity .  X_INV)
		(_port
			((I) (\U4/orFLGs \))
			((O) (\NlwInverterSignal_FOOBAR24__ctinst/4/IN1 \))
		)
		(_strength strong0 strong1)
	)
	(_model . U21 47 -1)

)
I 000050 55 4044          1078759214645 Interrupt
(_unit VERILOG 6.349C.6.256 (Interrupt 0 25 (Interrupt 0 25 ))
	(_version v32)
	(_time 1078759214550 2004.03.08 07:20:14)
	(_source (\./src/interrupt.v\ VERILOG (\./src/interrupt.v\ VERILOG)))
	(_use (std(standard))(vl(verilog_logic)))
	(_base (E 3))
	(_entity
		(_time 1078759214550)
		(_use )
	)
	(_timescale 1ps 1ps)
	(_parameters    dbg   accs  )
	(_attribute nb_assign )
	(_object
		(_type (_internal ~[7:0]wire~ 0 25 (_array ~wire ((_downto (i 7) (i 0))))))
		(_port (_internal inDATA ~[7:0]wire~ 0 25 (_architecture (_in ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal Reset ~wire 0 25 (_architecture (_in ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal PWRint ~wire 0 25 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal BusInt ~wire 0 25 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal Thres0 ~wire 0 25 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal Mclk ~wire 0 25 (_architecture (_in ))) (_net  ) (_nonbaction) (_noforceassign))
		(_port (_internal Thres1 ~wire 0 25 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal I2Cint ~wire 0 25 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal LSwitchInt ~wire 0 25 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal INT ~wire 0 25 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal DCORIEw ~wire 0 25 (_architecture (_in ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal Homed0 ~wire 0 25 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal Homed1 ~wire 0 25 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_type (_internal ~[7:0]reg~ 0 59 (_array ~reg ((_downto (i 7) (i 0))))))
		(_signal (_internal DCORIE ~[7:0]reg~ 0 59 (_architecture (_uni ))) (_reg ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_subprogram
			

		)
		(_type (_external ~wire (vl verilog_logic wire)))
		(_type (_external ~reg (vl verilog_logic reg)))
		(_type (_external ~event (vl verilog_logic event)))
		(_type (_external ~wand (vl verilog_logic wand)))
		(_type (_external ~wor (vl verilog_logic wor)))
		(_type (_external ~tri1 (vl verilog_logic tri1)))
		(_type (_external ~tri0 (vl verilog_logic tri0)))
		(_type (_external ~trireg (vl verilog_logic trireg)))
		(_type (_external ~supply0 (vl verilog_logic supply0)))
		(_type (_external ~supply1 (vl verilog_logic supply1)))
		(_type (_external ~real (vl verilog_logic real)))
		(_type (_external ~realtime (vl verilog_logic realtime)))
		(_type (_external ~tri (vl verilog_logic tri)))
		(_type (_external ~triand (vl verilog_logic triand)))
		(_type (_external ~trior (vl verilog_logic trior)))
		(_type (_external ~bit (vl verilog_logic bit)))
		(_type (_external ~extstd.standard.integer (std standard integer)))
		(_type (_external ~extstd.standard.bit (std standard bit)))
		(_process
			(#ASSIGN#68_0 (_architecture 0 0 68 (_process (_alias ((INT)(DCORIE(7))(I2Cint)(DCORIE(6))(Thres1)(DCORIE(5))(Thres0)(DCORIE(4))(LSwitchInt)(DCORIE(3))(Homed1)(DCORIE(2))(Homed0)(DCORIE(1))(PWRint)(DCORIE(0))(BusInt)))(_simple)
				(_target(9))
				(_sensitivity(13(7))(7)(13(6))(6)(13(5))(4)(13(4))(8)(13(3))(12)(13(2))(11)(13(1))(2)(13(0))(3))
			)))
			(#ALWAYS#70_1 (_architecture 1 0 70 (_process 
				(_target(13))
				(_read(5)(1)(10)(13)(0))
			)))
		)
	)
	
	
	(_defparam
	)
	(_model . Interrupt 3 -1)

)
V 000044 55 23696         1078761095706 U21
(_unit VERILOG 6.349C.6.256 (U21 0 32 (U21 0 32 ))
	(_version v32)
	(_time 1078761095628 2004.03.08 07:51:35)
	(_source (\./compile/u21.v\ VERILOG (\./compile/u21.v\ VERILOG)))
	(_use (std(standard))(vl(verilog_logic)))
	(_base (E 7))
	(_entity
		(_time 1078761095628)
		(_use )
	)
	(_timescale 1ns 1ns)
	(_parameters    dbg   accs  )
	(_attribute )
	(_object
		(_port (_internal AS ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Brake0 ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Brake1 ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal DIR0 ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal DIR1 ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Enc033FLG ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Enc05FLG ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Enc133FLG ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Enc15FLG ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal FLS0 ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal FLS1 ~wire 0 33 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal GP_Motor0_0 ~wire 0 33 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal GP_Motor1_0 ~wire 0 33 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal HSI ~wire 0 33 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal Home0 ~wire 0 33 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Home033FLG ~wire 0 33 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Home05FLG ~wire 0 33 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Home1 ~wire 0 33 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Home133FLG ~wire 0 33 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Home15FLG ~wire 0 33 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal INTbus ~wire 0 34 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal LightSense ~wire 0 34 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal MHSO ~wire 0 34 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal Mclk ~wire 0 34 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PWM1 ~wire 0 34 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PWM2 ~wire 0 34 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PhaseA_Encoder0 ~wire 0 34 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PhaseA_Encoder1 ~wire 0 34 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PhaseB_Encoder0 ~wire 0 34 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PhaseB_Encoder1 ~wire 0 34 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal RD ~wire 0 35 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal RLS0 ~wire 0 35 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal RLS1 ~wire 0 35 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Reset ~wire 0 35 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal SCLinc ~wire 0 35 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal SCLreset ~wire 0 35 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal TXI ~wire 0 35 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal WR ~wire 0 35 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_type (_internal ~[5:0]wire~ 0 35 (_array ~wire ((_downto (i 5) (i 0))))))
		(_port (_internal I2CS ~[5:0]wire~ 0 35 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Enc033ctrl ~wire 0 35 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Enc05ctrl ~wire 0 36 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Enc133ctrl ~wire 0 36 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Enc15ctrl ~wire 0 36 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal GP_Motor0_1 ~wire 0 36 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal GP_Motor1_1 ~wire 0 36 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal HSO ~wire 0 36 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal Home033ctrl ~wire 0 36 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Home05ctrl ~wire 0 36 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Home133ctrl ~wire 0 36 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Home15ctrl ~wire 0 36 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal INT ~wire 0 37 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal LED1 ~wire 0 37 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal LED2 ~wire 0 37 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal LED3 ~wire 0 37 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal LED4 ~wire 0 37 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal LED5 ~wire 0 37 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal MHSI ~wire 0 37 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal MTRpwr ~wire 0 37 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal MTRpwrn ~wire 0 37 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal MTXI ~wire 0 37 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal PAH0 ~wire 0 38 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PAH1 ~wire 0 38 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PAL0 ~wire 0 38 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PAL1 ~wire 0 38 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PBH0 ~wire 0 38 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PBH1 ~wire 0 38 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PBL0 ~wire 0 38 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PBL1 ~wire 0 38 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal SCL ~wire 0 38 (_architecture (_inout ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_type (_internal ~[7:0]wire~ 0 38 (_array ~wire ((_downto (i 7) (i 0))))))
		(_port (_internal AD ~[7:0]wire~ 0 38 (_architecture (_inout ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET1635 ~wire 0 183 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET1643 ~wire 0 184 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET1651 ~wire 0 185 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET1659 ~wire 0 186 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET1667 ~wire 0 187 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET1675 ~wire 0 188 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET1683 ~wire 0 189 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET1691 ~wire 0 190 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET1699 ~wire 0 191 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET1707 ~wire 0 192 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET1970 ~wire 0 193 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET1978 ~wire 0 194 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET1989 ~wire 0 195 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET2017 ~wire 0 196 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET2025 ~wire 0 197 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET2036 ~wire 0 198 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET2047 ~wire 0 199 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET2064 ~wire 0 200 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET2078 ~wire 0 201 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET2311 ~wire 0 202 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET2482 ~wire 0 203 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET2493 ~wire 0 204 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET2501 ~wire 0 205 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET2512 ~wire 0 206 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET2528 ~wire 0 207 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET2539 ~wire 0 208 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET2575 ~wire 0 209 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET3248 ~wire 0 210 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET3253 ~wire 0 211 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET615 ~wire 0 212 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal NET621 ~wire 0 213 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal NET629 ~wire 0 214 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal BUS1564 ~[7:0]wire~ 0 215 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal inDATA ~[7:0]wire~ 0 216 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal outDATA ~[7:0]wire~ 0 217 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_subprogram
			

		)
		(_type (_external ~wire (vl verilog_logic wire)))
		(_type (_external ~reg (vl verilog_logic reg)))
		(_type (_external ~event (vl verilog_logic event)))
		(_type (_external ~wand (vl verilog_logic wand)))
		(_type (_external ~wor (vl verilog_logic wor)))
		(_type (_external ~tri1 (vl verilog_logic tri1)))
		(_type (_external ~tri0 (vl verilog_logic tri0)))
		(_type (_external ~trireg (vl verilog_logic trireg)))
		(_type (_external ~supply0 (vl verilog_logic supply0)))
		(_type (_external ~supply1 (vl verilog_logic supply1)))
		(_type (_external ~real (vl verilog_logic real)))
		(_type (_external ~realtime (vl verilog_logic realtime)))
		(_type (_external ~tri (vl verilog_logic tri)))
		(_type (_external ~triand (vl verilog_logic triand)))
		(_type (_external ~trior (vl verilog_logic trior)))
		(_type (_external ~bit (vl verilog_logic bit)))
		(_type (_external ~extstd.standard.integer (std standard integer)))
		(_type (_external ~extstd.standard.bit (std standard bit)))
		(_process
			(#ASSIGN#447_0 (_architecture 0 0 447 (_process (_alias ((NET615)(MHSO)))(_simple)
				(_target(99))
				(_sensitivity(22))
			)))
			(#ASSIGN#448_1 (_architecture 1 0 448 (_process (_alias ((NET621)(HSI)))(_simple)
				(_target(100))
				(_sensitivity(13))
			)))
			(#ASSIGN#449_2 (_architecture 2 0 449 (_process (_alias ((NET629)(TXI)))(_simple)
				(_target(101))
				(_sensitivity(36))
			)))
			(#ASSIGN#452_3 (_architecture 3 0 452 (_process (_alias ((HSO)(NET615)))(_simple)
				(_target(45))
				(_sensitivity(99))
			)))
			(#ASSIGN#453_4 (_architecture 4 0 453 (_process (_alias ((MHSI)(NET621)))(_simple)
				(_target(56))
				(_sensitivity(100))
			)))
			(#ASSIGN#454_5 (_architecture 5 0 454 (_process (_alias ((MTXI)(NET629)))(_simple)
				(_target(59))
				(_sensitivity(101))
			)))
		)
	)
	
	
	(_defparam
	)
	(_scope
	)
	(_instantiation U1 0 221 (_entity .  Servos)
		(_port
			((DCOR0CNTHIGHr) (NET1667))
			((DCOR0CNTLOWr) (NET1651))
			((DCOR0CNTMIDr) (NET1659))
			((DCOR0THRESLOWr) (NET1635))
			((DCOR0THRESMIDr) (NET1643))
			((DCOR1CNTHIGHr) (NET1675))
			((DCOR1CNTLOWr) (NET1683))
			((DCOR1CNTMIDr) (NET1691))
			((DCOR1THRESLOWr) (NET1707))
			((DCOR1THRESMIDr) (NET1699))
			((DCORENCCTLw) (NET1970))
			((DCORIFGr) (NET1978))
			((DCORIFGw) (NET1989))
			((Hfound0) (NET2482))
			((Hfound1) (NET2493))
			((Home_Encoder0) (Home0))
			((Home_Encoder1) (Home1))
			((Mclk) (Mclk))
			((MotorIn0) (GP_Motor0_0))
			((Motorin1) (GP_Motor1_0))
			((PhaseA_Encoder0) (PhaseA_Encoder0))
			((PhaseA_Encoder1) (PhaseA_Encoder1))
			((PhaseB_Encoder0) (PhaseB_Encoder0))
			((PhaseB_Encoder1) (PhaseB_Encoder1))
			((Reset) (Reset))
			((Tfound0) (NET2501))
			((Tfound1) (NET2512))
			((inDATA) (inDATA))
			((outDATA) (outDATA))
		)
		(_strength strong0 strong1)
	)
	(_instantiation U11 0 256 (_entity .  I2Cfix)
		(_port
			((DCORI2CCNTr) (NET2311))
			((Inc) (SCLinc))
			((Mclk) (Mclk))
			((SCL) (SCL))
			((SCLint) (NET2539))
			((SCLreset) (SCLreset))
			((outDATA) (outDATA))
		)
		(_strength strong0 strong1)
	)
	(_instantiation U12 0 269 (_entity .  U21AddDecode)
		(_port
			((ADDR) (BUS1564))
			((AS) (AS))
			((DCOR0CNTHIGHr) (NET1667))
			((DCOR0CNTLOWr) (NET1651))
			((DCOR0CNTMIDr) (NET1659))
			((DCOR0THRESLOWr) (NET1635))
			((DCOR0THRESMIDr) (NET1643))
			((DCOR1CNTHIGHr) (NET1675))
			((DCOR1CNTLOWr) (NET1683))
			((DCOR1CNTMIDr) (NET1691))
			((DCOR1THRESLOWr) (NET1707))
			((DCOR1THRESMIDr) (NET1699))
			((DCORCONFIGr) (NET2064))
			((DCORENCCTLw) (NET1970))
			((DCORENCPWRr) (NET2036))
			((DCORENCPWRw) (NET2025))
			((DCORI2CCNTr) (NET2311))
			((DCORIEw) (NET2078))
			((DCORIFGr) (NET1978))
			((DCORIFGw) (NET1989))
			((DCORLIMITSr) (NET2047))
			((DCOROUTw) (NET2017))
			((RD) (RD))
			((WR) (WR))
		)
		(_strength strong0 strong1)
	)
	(_instantiation U2 0 299 (_entity .  Interface)
		(_port
			((AD) (AD))
			((ADDR) (BUS1564))
			((AS) (AS))
			((Mclk) (Mclk))
			((RD) (RD))
			((Reset) (Reset))
			((WR) (WR))
			((inDATA) (inDATA))
			((outDATA) (outDATA))
		)
		(_strength strong0 strong1)
	)
	(_instantiation U3 0 314 (_entity .  Interrupt)
		(_port
			((BusInt) (INTbus))
			((DCORIEw) (NET2078))
			((Homed0) (NET2482))
			((Homed1) (NET2493))
			((I2Cint) (NET2539))
			((INT) (INT))
			((LSwitchInt) (NET2575))
			((Mclk) (Mclk))
			((PWRint) (NET2528))
			((Reset) (Reset))
			((Thres0) (NET2501))
			((Thres1) (NET2512))
			((inDATA) (inDATA))
		)
		(_strength strong0 strong1)
	)
	(_instantiation U4 0 333 (_entity .  PWRreg)
		(_port
			((DCORENCPWRr) (NET2036))
			((DCORENCPWRw) (NET2025))
			((DCORIFGr) (NET1978))
			((DCORIFGw) (NET1989))
			((Enc033ctl) (Home15ctrl))
			((Enc033flg) (Enc033FLG))
			((Enc05ctl) (Home133ctrl))
			((Enc05flg) (Enc05FLG))
			((Enc133ctl) (Home05ctrl))
			((Enc133flg) (Enc133FLG))
			((Enc15ctl) (Home033ctrl))
			((Enc15flg) (Enc15FLG))
			((Hme033ctl) (Enc15ctrl))
			((Hme033flg) (Home033FLG))
			((Hme05ctl) (Enc133ctrl))
			((Hme05flg) (Home05FLG))
			((Hme133ctl) (Enc05ctrl))
			((Hme133flg) (Home133FLG))
			((Hme15ctl) (Enc033ctrl))
			((Hme15flg) (Home15FLG))
			((Mclk) (Mclk))
			((PWRint) (NET2528))
			((Reset) (Reset))
			((inDATA) (inDATA))
			((outDATA) (outDATA))
		)
		(_strength strong0 strong1)
	)
	(_instantiation U5 0 364 (_entity .  Lswitch)
		(_port
			((Brake0) (Brake0))
			((Brake1) (Brake1))
			((DCORIFGr) (NET1978))
			((DCORIFGw) (NET1989))
			((DCORLIMITSr) (NET2047))
			((DIR0) (DIR0))
			((DIR1) (DIR1))
			((FLS0) (FLS0))
			((FLS1) (FLS1))
			((Home0) (Home0))
			((Home1) (Home1))
			((LSwitchInt) (NET2575))
			((Mclk) (Mclk))
			((RLS0) (RLS0))
			((RLS1) (RLS1))
			((Reset) (Reset))
			((fBRK0) (NET3248))
			((fBRK1) (NET3253))
			((inDATA) (inDATA))
			((outDATA) (outDATA))
		)
		(_strength strong0 strong1)
	)
	(_instantiation U6 0 390 (_entity .  I2CAddress)
		(_port
			((DCORCONFIGr) (NET2064))
			((I2CS) (I2CS))
			((MotorIn0) (GP_Motor0_0))
			((MotorIn1) (GP_Motor1_0))
			((outDATA) (outDATA))
		)
		(_strength strong0 strong1)
	)
	(_instantiation U7 0 401 (_entity .  PWMcontrol)
		(_port
			((Brake1) (Brake0))
			((Brake2) (Brake1))
			((DIR1) (DIR0))
			((DIR2) (DIR1))
			((HBRK1) (NET3248))
			((HBRK2) (NET3253))
			((PAH1) (PAH0))
			((PAH2) (PBL1))
			((PAL1) (PAL0))
			((PAL2) (PBH1))
			((PBH1) (PBH0))
			((PBH2) (PAL1))
			((PBL1) (PBL0))
			((PBL2) (PAH1))
			((PWM1) (PWM1))
			((PWM2) (PWM2))
			((fBRK1) (NET3248))
			((fBRK2) (NET3253))
		)
		(_strength strong0 strong1)
	)
	(_instantiation U9 0 425 (_entity .  MISCouts)
		(_port
			((DCOROUTw) (NET2017))
			((GP_Motor0_1) (GP_Motor0_1))
			((GP_Motor1_1) (GP_Motor1_1))
			((LED1) (LED1))
			((LED2) (LED2))
			((LED3) (LED3))
			((LED4) (LED4))
			((LED5) (LED5))
			((LightSense) (LightSense))
			((MTRpwr) (MTRpwr))
			((MTRpwrn) (MTRpwrn))
			((Mclk) (Mclk))
			((Reset) (Reset))
			((inDATA) (inDATA))
		)
		(_strength strong0 strong1)
	)
	(_model . U21 7 -1)

)
V 000046 55 8057          1078761441956 U4_TB
(_unit VERILOG 6.349C.6.256 (U4_TB 0 32 (U4_TB 0 32 ))
	(_version v32)
	(_time 1078761441753 2004.03.08 07:57:21)
	(_source (\./compile/u21_tb.v\ VERILOG (\./compile/u21_tb.v\ VERILOG)))
	(_use (std(standard))(vl(verilog_logic)))
	(_base (E 3))
	(_entity
		(_time 1078761441753)
		(_use )
	)
	(_timescale 1ns 1ns)
	(_parameters    dbg   accs  )
	(_attribute )
	(_object
		(_type (_internal ~vector~0 0 72 (_array ~bit ((_uto (i 0) (i 0))))))
		(_generic (_internal DANGLING_INPUT_CONSTANT ~vector~0 0 72 \1'bZ\ (_entity -1 (_constant \1'bZ\))))
		(_port (_internal Enc133FLG ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Enc15FLG ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal FLS1 ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal FLS2 ~wire 0 32 (_architecture (_in ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Home1 ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Home133FLG ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Home15FLG ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Home2 ~wire 0 32 (_architecture (_in ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PhaseA_Encoder1 ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PhaseB_Encoder1 ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal RLS1 ~wire 0 33 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal RLS2 ~wire 0 33 (_architecture (_in ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Reset ~wire 0 33 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Enc133ctrl ~wire 0 33 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Enc15ctrl ~wire 0 33 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Home133ctrl ~wire 0 33 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Home15ctrl ~wire 0 33 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal AS ~wire 0 75 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal Mclk ~wire 0 76 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal RD ~wire 0 77 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal WR ~wire 0 78 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_type (_internal ~[7:0]wire~ 0 79 (_array ~wire ((_downto (i 7) (i 0))))))
		(_signal (_internal AD ~[7:0]wire~ 0 79 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal Dangling_Input_Signal ~wire 0 82 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_type (_internal ~[5:0]wire~ 0 113 (_array ~wire ((_downto (i 5) (i 0))))))
		(_signal (_internal \1 \ ~[5:0]wire~ -1 113 (_internal (_uni ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_subprogram
			

		)
		(_type (_external ~wire (vl verilog_logic wire)))
		(_type (_external ~reg (vl verilog_logic reg)))
		(_type (_external ~event (vl verilog_logic event)))
		(_type (_external ~wand (vl verilog_logic wand)))
		(_type (_external ~wor (vl verilog_logic wor)))
		(_type (_external ~tri1 (vl verilog_logic tri1)))
		(_type (_external ~tri0 (vl verilog_logic tri0)))
		(_type (_external ~trireg (vl verilog_logic trireg)))
		(_type (_external ~supply0 (vl verilog_logic supply0)))
		(_type (_external ~supply1 (vl verilog_logic supply1)))
		(_type (_external ~real (vl verilog_logic real)))
		(_type (_external ~realtime (vl verilog_logic realtime)))
		(_type (_external ~tri (vl verilog_logic tri)))
		(_type (_external ~triand (vl verilog_logic triand)))
		(_type (_external ~trior (vl verilog_logic trior)))
		(_type (_external ~bit (vl verilog_logic bit)))
		(_type (_external ~extstd.standard.integer (std standard integer)))
		(_type (_external ~extstd.standard.bit (std standard bit)))
		(_process
			(#INTERNAL#113_0 (_internal 0 0 113 (_process (_simple)
				(_target(23))
				(_sensitivity(22))
			)))
			(#ASSIGN#82_1 (_architecture 1 0 82 (_process (_simple)
				(_target(22))
			)))
			(#INTERNAL#0_2 (_internal 2 0 0 (_process (_virtual))))
		)
	)
	
	
	(_defparam
	)
	(_scope
	)
	(_instantiation U1 0 86 (_entity .  U21)
		(_port
			((AD) (AD))
			((AS) (AS))
			((Brake0) (Dangling_Input_Signal))
			((Brake1) (Dangling_Input_Signal))
			((DIR0) (Dangling_Input_Signal))
			((DIR1) (Dangling_Input_Signal))
			((Enc033FLG) (Dangling_Input_Signal))
			((Enc05FLG) (Dangling_Input_Signal))
			((Enc133FLG) (Enc133FLG))
			((Enc133ctrl) (Enc133ctrl))
			((Enc15FLG) (Enc15FLG))
			((Enc15ctrl) (Enc15ctrl))
			((FLS0) (Dangling_Input_Signal))
			((FLS1) (FLS1))
			((GP_Motor0_0) (Dangling_Input_Signal))
			((GP_Motor1_0) (Dangling_Input_Signal))
			((HSI) (Dangling_Input_Signal))
			((Home0) (Dangling_Input_Signal))
			((Home033FLG) (Dangling_Input_Signal))
			((Home05FLG) (Dangling_Input_Signal))
			((Home1) (Home1))
			((Home133FLG) (Home133FLG))
			((Home133ctrl) (Home133ctrl))
			((Home15FLG) (Home15FLG))
			((Home15ctrl) (Home15ctrl))
			((I2CS) (\1 \))
			((INTbus) (Dangling_Input_Signal))
			((LightSense) (Dangling_Input_Signal))
			((MHSO) (Dangling_Input_Signal))
			((Mclk) (Mclk))
			((PWM1) (Dangling_Input_Signal))
			((PWM2) (Dangling_Input_Signal))
			((PhaseA_Encoder0) (Dangling_Input_Signal))
			((PhaseA_Encoder1) (PhaseA_Encoder1))
			((PhaseB_Encoder0) (Dangling_Input_Signal))
			((PhaseB_Encoder1) (PhaseB_Encoder1))
			((RD) (RD))
			((RLS0) (Dangling_Input_Signal))
			((RLS1) (RLS1))
			((Reset) (Reset))
			((SCLinc) (Dangling_Input_Signal))
			((SCLreset) (Dangling_Input_Signal))
			((TXI) (Dangling_Input_Signal))
			((WR) (WR))
			((Enc033ctrl) (_open))
			((Enc05ctrl) (_open))
			((GP_Motor0_1) (_open))
			((GP_Motor1_1) (_open))
			((HSO) (_open))
			((Home033ctrl) (_open))
			((Home05ctrl) (_open))
			((INT) (_open))
			((LED1) (_open))
			((LED2) (_open))
			((LED3) (_open))
			((LED4) (_open))
			((LED5) (_open))
			((MHSI) (_open))
			((MTRpwr) (_open))
			((MTRpwrn) (_open))
			((MTXI) (_open))
			((PAH0) (_open))
			((PAH1) (_open))
			((PAL0) (_open))
			((PAL1) (_open))
			((PBH0) (_open))
			((PBH1) (_open))
			((PBL0) (_open))
			((PBL1) (_open))
			((SCL) (_open))
		)
		(_strength strong0 strong1)
	)
	(_instantiation U2 0 136 (_entity .  MSP)
		(_port
			((AD) (AD))
			((AS) (AS))
			((Mclk) (Mclk))
			((RD) (RD))
			((WR) (WR))
		)
		(_strength strong0 strong1)
	)
	(_model . U4_TB 3 -1)

)
I 000050 55 4270          1078763556223 Interface
(_unit VERILOG 6.349C.6.256 (Interface 0 25 (Interface 0 25 ))
	(_version v32)
	(_time 1078763556160 2004.03.08 08:32:36)
	(_source (\./src/interface.v\ VERILOG (\./src/interface.v\ VERILOG)))
	(_use (std(standard))(vl(verilog_logic)))
	(_base (E 6))
	(_entity
		(_time 1078763556160)
		(_use )
	)
	(_timescale 1ps 1ps)
	(_parameters    dbg   accs  )
	(_attribute nb_assign )
	(_object
		(_type (_internal ~[7:0]wire~ 0 25 (_array ~wire ((_downto (i 7) (i 0))))))
		(_port (_internal inDATA ~[7:0]wire~ 0 25 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal outDATA ~[7:0]wire~ 0 25 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal Reset ~wire 0 25 (_architecture (_in ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal AS ~wire 0 25 (_architecture (_in ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal AD ~[7:0]wire~ 0 25 (_architecture (_inout ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal RD ~wire 0 25 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal Mclk ~wire 0 25 (_architecture (_in ))) (_net  ) (_nonbaction) (_noforceassign))
		(_port (_internal WR ~wire 0 25 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal ADDR ~[7:0]wire~ 0 25 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_type (_internal ~[7:0]reg~ 0 56 (_array ~reg ((_downto (i 7) (i 0))))))
		(_signal (_internal ADDR_reg ~[7:0]reg~ 0 56 (_architecture (_uni ))) (_reg ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal AutoInc ~reg 0 64 (_architecture (_uni ))) (_reg ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal ASedge ~reg 0 66 (_architecture (_uni ))) (_reg ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal WRRDedge ~reg 0 68 (_architecture (_uni ))) (_reg ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal Enable_AD ~wire 0 72 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_subprogram
			

		)
		(_type (_external ~wire (vl verilog_logic wire)))
		(_type (_external ~reg (vl verilog_logic reg)))
		(_type (_external ~event (vl verilog_logic event)))
		(_type (_external ~wand (vl verilog_logic wand)))
		(_type (_external ~wor (vl verilog_logic wor)))
		(_type (_external ~tri1 (vl verilog_logic tri1)))
		(_type (_external ~tri0 (vl verilog_logic tri0)))
		(_type (_external ~trireg (vl verilog_logic trireg)))
		(_type (_external ~supply0 (vl verilog_logic supply0)))
		(_type (_external ~supply1 (vl verilog_logic supply1)))
		(_type (_external ~real (vl verilog_logic real)))
		(_type (_external ~realtime (vl verilog_logic realtime)))
		(_type (_external ~tri (vl verilog_logic tri)))
		(_type (_external ~triand (vl verilog_logic triand)))
		(_type (_external ~trior (vl verilog_logic trior)))
		(_type (_external ~bit (vl verilog_logic bit)))
		(_type (_external ~extstd.standard.integer (std standard integer)))
		(_type (_external ~extstd.standard.bit (std standard bit)))
		(_process
			(#ASSIGN#75_0 (_architecture 0 0 75 (_process (_alias ((ADDR)(ADDR_reg)))(_simple)
				(_target(8))
				(_sensitivity(9))
			)))
			(#ASSIGN#78_1 (_architecture 1 0 78 (_process (_alias ((Enable_AD)(WR)(RD)))(_simple)
				(_target(13))
				(_sensitivity(7)(5))
			)))
			(#ASSIGN#85_2 (_architecture 2 0 85 (_process (_alias ((inDATA)(AD)))(_simple)
				(_target(0))
				(_sensitivity(4))
			)))
			(#ASSIGN#86_3 (_architecture 3 0 86 (_process (_simple)
				(_target(4))
				(_sensitivity(13)(1))
			)))
			(#ALWAYS#88_4 (_architecture 4 0 88 (_process 
				(_target(11)(12)(9)(10))
				(_read(6)(3)(7)(5)(2)(11)(4)(12)(10)(9))
			)))
		)
	)
	
	
	(_defparam
	)
	(_model . Interface 6 -1)

)
I 000049 55 5191          1078767436941 MISCouts
(_unit VERILOG 6.349C.6.256 (MISCouts 0 25 (MISCouts 0 25 ))
	(_version v32)
	(_time 1078767436878 2004.03.08 09:37:16)
	(_source (\./src/miscouts.v\ VERILOG (\./src/miscouts.v\ VERILOG)))
	(_use (std(standard))(vl(verilog_logic)))
	(_base (E 11))
	(_entity
		(_time 1078767436878)
		(_use )
	)
	(_timescale 1ps 1ps)
	(_parameters    dbg   accs  )
	(_attribute nb_assign )
	(_object
		(_type (_internal ~[7:0]wire~ 0 25 (_array ~wire ((_downto (i 7) (i 0))))))
		(_port (_internal inDATA ~[7:0]wire~ 0 25 (_architecture (_in ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal Reset ~wire 0 25 (_architecture (_in ))) (_net  ) (_nonbaction) (_noforceassign))
		(_port (_internal LED1 ~wire 0 25 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal LightSense ~wire 0 25 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal GP_Motor0_1 ~wire 0 25 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal LED2 ~wire 0 25 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal DCOROUTw ~wire 0 25 (_architecture (_in ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal Mclk ~wire 0 25 (_architecture (_in ))) (_net  ) (_nonbaction) (_noforceassign))
		(_port (_internal GP_Motor1_1 ~wire 0 25 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal LED3 ~wire 0 25 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal LED4 ~wire 0 25 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal MTRpwrn ~wire 0 25 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal LED5 ~wire 0 25 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal MTRpwr ~wire 0 25 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_type (_internal ~[7:0]reg~ 0 63 (_array ~reg ((_downto (i 7) (i 0))))))
		(_signal (_internal MISCr ~[7:0]reg~ 0 63 (_architecture (_uni ))) (_reg ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_subprogram
			

		)
		(_type (_external ~wire (vl verilog_logic wire)))
		(_type (_external ~reg (vl verilog_logic reg)))
		(_type (_external ~event (vl verilog_logic event)))
		(_type (_external ~wand (vl verilog_logic wand)))
		(_type (_external ~wor (vl verilog_logic wor)))
		(_type (_external ~tri1 (vl verilog_logic tri1)))
		(_type (_external ~tri0 (vl verilog_logic tri0)))
		(_type (_external ~trireg (vl verilog_logic trireg)))
		(_type (_external ~supply0 (vl verilog_logic supply0)))
		(_type (_external ~supply1 (vl verilog_logic supply1)))
		(_type (_external ~real (vl verilog_logic real)))
		(_type (_external ~realtime (vl verilog_logic realtime)))
		(_type (_external ~tri (vl verilog_logic tri)))
		(_type (_external ~triand (vl verilog_logic triand)))
		(_type (_external ~trior (vl verilog_logic trior)))
		(_type (_external ~bit (vl verilog_logic bit)))
		(_type (_external ~extstd.standard.integer (std standard integer)))
		(_type (_external ~extstd.standard.bit (std standard bit)))
		(_process
			(#ASSIGN#65_0 (_architecture 0 0 65 (_process (_alias ((LED1)(MISCr(0))(LightSense)))(_simple)
				(_target(2))
				(_sensitivity(14(0))(3))
			)))
			(#ASSIGN#66_1 (_architecture 1 0 66 (_process (_alias ((LED2)(MISCr(1))(LightSense)))(_simple)
				(_target(5))
				(_sensitivity(14(1))(3))
			)))
			(#ASSIGN#67_2 (_architecture 2 0 67 (_process (_alias ((LED3)(MISCr(2))(LightSense)))(_simple)
				(_target(9))
				(_sensitivity(14(2))(3))
			)))
			(#ASSIGN#68_3 (_architecture 3 0 68 (_process (_alias ((LED4)(MISCr(3))(LightSense)))(_simple)
				(_target(10))
				(_sensitivity(14(3))(3))
			)))
			(#ASSIGN#69_4 (_architecture 4 0 69 (_process (_alias ((LED5)(MISCr(4))(LightSense)))(_simple)
				(_target(12))
				(_sensitivity(14(4))(3))
			)))
			(#ASSIGN#70_5 (_architecture 5 0 70 (_process (_alias ((GP_Motor0_1)(MISCr(6))))(_simple)
				(_target(4))
				(_sensitivity(14(6)))
			)))
			(#ASSIGN#71_6 (_architecture 6 0 71 (_process (_alias ((GP_Motor1_1)(MISCr(7))))(_simple)
				(_target(8))
				(_sensitivity(14(7)))
			)))
			(#ASSIGN#72_7 (_architecture 7 0 72 (_process (_alias ((MTRpwr)(MISCr(5))))(_simple)
				(_target(13))
				(_sensitivity(14(5)))
			)))
			(#ASSIGN#73_8 (_architecture 8 0 73 (_process (_alias ((MTRpwrn)(MISCr(5))))(_simple)
				(_target(11))
				(_sensitivity(14(5)))
			)))
			(#ALWAYS#75_9 (_architecture 9 0 75 (_process 
				(_target(14))
				(_read(7)(1)(6)(0)(14))
			)))
		)
	)
	
	
	(_defparam
	)
	(_model . MISCouts 11 -1)

)
I 000051 55 3348          1078843973436 BitCounter
(_unit VERILOG 6.349C.6.256 (BitCounter 0 25 (BitCounter 0 25 ))
	(_version v32)
	(_time 1078843973155 2004.03.09 06:52:53)
	(_source (\./src/bitcounter.v\ VERILOG (\./src/bitcounter.v\ VERILOG)))
	(_use (std(standard))(vl(verilog_logic)))
	(_base (E 5))
	(_entity
		(_time 1078843973155)
		(_use )
	)
	(_timescale 1ps 1ps)
	(_parameters    dbg   accs  )
	(_attribute nb_assign )
	(_object
		(_type (_internal ~[7:0]wire~ 0 25 (_array ~wire ((_downto (i 7) (i 0))))))
		(_port (_internal outDATA ~[7:0]wire~ 0 25 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal DriveSCL ~wire 0 25 (_architecture (_inout ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal NegSCL ~wire 0 25 (_architecture (_in ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal NegInc ~wire 0 25 (_architecture (_in ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal SCLint ~wire 0 25 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal DCORI2CCNTr ~wire 0 25 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal SCLreset ~wire 0 25 (_architecture (_in ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal Mclk ~wire 0 25 (_architecture (_in ))) (_net  ) (_nonbaction) (_noforceassign))
		(_type (_internal ~[5:0]reg~ 0 50 (_array ~reg ((_downto (i 5) (i 0))))))
		(_signal (_internal counterr ~[5:0]reg~ 0 50 (_architecture (_uni ))) (_reg ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_subprogram
			

		)
		(_type (_external ~wire (vl verilog_logic wire)))
		(_type (_external ~reg (vl verilog_logic reg)))
		(_type (_external ~event (vl verilog_logic event)))
		(_type (_external ~wand (vl verilog_logic wand)))
		(_type (_external ~wor (vl verilog_logic wor)))
		(_type (_external ~tri1 (vl verilog_logic tri1)))
		(_type (_external ~tri0 (vl verilog_logic tri0)))
		(_type (_external ~trireg (vl verilog_logic trireg)))
		(_type (_external ~supply0 (vl verilog_logic supply0)))
		(_type (_external ~supply1 (vl verilog_logic supply1)))
		(_type (_external ~real (vl verilog_logic real)))
		(_type (_external ~realtime (vl verilog_logic realtime)))
		(_type (_external ~tri (vl verilog_logic tri)))
		(_type (_external ~triand (vl verilog_logic triand)))
		(_type (_external ~trior (vl verilog_logic trior)))
		(_type (_external ~bit (vl verilog_logic bit)))
		(_type (_external ~extstd.standard.integer (std standard integer)))
		(_type (_external ~extstd.standard.bit (std standard bit)))
		(_process
			(#ASSIGN#52_0 (_architecture 0 0 52 (_process (_simple)
				(_target(4))
				(_sensitivity(8))
			)))
			(#ASSIGN#54_1 (_architecture 1 0 54 (_process (_simple)
				(_target(1))
				(_sensitivity(8))
			)))
			(#ASSIGN#56_2 (_architecture 2 0 56 (_process (_simple)
				(_target(0))
				(_sensitivity(5)(8))
			)))
			(#ALWAYS#58_3 (_architecture 3 0 58 (_process 
				(_target(8))
				(_read(7)(6)(3)(2)(8))
			)))
		)
	)
	
	
	(_defparam
	)
	(_model . BitCounter 5 -1)

)
V 000046 55 8485          1078844534920 U4_TB
(_unit VERILOG 6.349C.6.256 (U4_TB 0 32 (U4_TB 0 32 ))
	(_version v32)
	(_time 1078844534842 2004.03.09 07:02:14)
	(_source (\./compile/u21_tb.v\ VERILOG (\./compile/u21_tb.v\ VERILOG)))
	(_use (std(standard))(vl(verilog_logic)))
	(_base (E 3))
	(_entity
		(_time 1078844534842)
		(_use )
	)
	(_timescale 1ns 1ns)
	(_parameters    dbg   accs  )
	(_attribute )
	(_object
		(_type (_internal ~vector~0 0 78 (_array ~bit ((_uto (i 0) (i 0))))))
		(_generic (_internal DANGLING_INPUT_CONSTANT ~vector~0 0 78 \1'bZ\ (_entity -1 (_constant \1'bZ\))))
		(_port (_internal Enc133FLG ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Enc15FLG ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal FLS1 ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal FLS2 ~wire 0 32 (_architecture (_in ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Home1 ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Home133FLG ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Home15FLG ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Home2 ~wire 0 32 (_architecture (_in ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PhaseA_Encoder1 ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PhaseB_Encoder1 ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal RLS1 ~wire 0 33 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal RLS2 ~wire 0 33 (_architecture (_in ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Reset ~wire 0 33 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal SCL ~wire 0 33 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal SCLinc ~wire 0 33 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal SCLreset ~wire 0 33 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Enc133ctrl ~wire 0 33 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Enc15ctrl ~wire 0 33 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Home133ctrl ~wire 0 33 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Home15ctrl ~wire 0 33 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal AS ~wire 0 81 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal Mclk ~wire 0 82 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal RD ~wire 0 83 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal WR ~wire 0 84 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_type (_internal ~[7:0]wire~ 0 85 (_array ~wire ((_downto (i 7) (i 0))))))
		(_signal (_internal AD ~[7:0]wire~ 0 85 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal Dangling_Input_Signal ~wire 0 88 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_type (_internal ~[5:0]wire~ 0 119 (_array ~wire ((_downto (i 5) (i 0))))))
		(_signal (_internal \1 \ ~[5:0]wire~ -1 119 (_internal (_uni ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_subprogram
			

		)
		(_type (_external ~wire (vl verilog_logic wire)))
		(_type (_external ~reg (vl verilog_logic reg)))
		(_type (_external ~event (vl verilog_logic event)))
		(_type (_external ~wand (vl verilog_logic wand)))
		(_type (_external ~wor (vl verilog_logic wor)))
		(_type (_external ~tri1 (vl verilog_logic tri1)))
		(_type (_external ~tri0 (vl verilog_logic tri0)))
		(_type (_external ~trireg (vl verilog_logic trireg)))
		(_type (_external ~supply0 (vl verilog_logic supply0)))
		(_type (_external ~supply1 (vl verilog_logic supply1)))
		(_type (_external ~real (vl verilog_logic real)))
		(_type (_external ~realtime (vl verilog_logic realtime)))
		(_type (_external ~tri (vl verilog_logic tri)))
		(_type (_external ~triand (vl verilog_logic triand)))
		(_type (_external ~trior (vl verilog_logic trior)))
		(_type (_external ~bit (vl verilog_logic bit)))
		(_type (_external ~extstd.standard.integer (std standard integer)))
		(_type (_external ~extstd.standard.bit (std standard bit)))
		(_process
			(#INTERNAL#119_0 (_internal 0 0 119 (_process (_simple)
				(_target(26))
				(_sensitivity(25))
			)))
			(#ASSIGN#88_1 (_architecture 1 0 88 (_process (_simple)
				(_target(25))
			)))
			(#INTERNAL#0_2 (_internal 2 0 0 (_process (_virtual))))
		)
	)
	
	
	(_defparam
	)
	(_scope
	)
	(_instantiation U1 0 92 (_entity .  U21)
		(_port
			((AD) (AD))
			((AS) (AS))
			((Brake0) (Dangling_Input_Signal))
			((Brake1) (Dangling_Input_Signal))
			((DIR0) (Dangling_Input_Signal))
			((DIR1) (Dangling_Input_Signal))
			((Enc033FLG) (Dangling_Input_Signal))
			((Enc05FLG) (Dangling_Input_Signal))
			((Enc133FLG) (Enc133FLG))
			((Enc133ctrl) (Enc133ctrl))
			((Enc15FLG) (Enc15FLG))
			((Enc15ctrl) (Enc15ctrl))
			((FLS0) (Dangling_Input_Signal))
			((FLS1) (FLS1))
			((GP_Motor0_0) (Dangling_Input_Signal))
			((GP_Motor1_0) (Dangling_Input_Signal))
			((HSI) (Dangling_Input_Signal))
			((Home0) (Dangling_Input_Signal))
			((Home033FLG) (Dangling_Input_Signal))
			((Home05FLG) (Dangling_Input_Signal))
			((Home1) (Home1))
			((Home133FLG) (Home133FLG))
			((Home133ctrl) (Home133ctrl))
			((Home15FLG) (Home15FLG))
			((Home15ctrl) (Home15ctrl))
			((I2CS) (\1 \))
			((INTbus) (Dangling_Input_Signal))
			((LightSense) (Dangling_Input_Signal))
			((MHSO) (Dangling_Input_Signal))
			((Mclk) (Mclk))
			((PWM1) (Dangling_Input_Signal))
			((PWM2) (Dangling_Input_Signal))
			((PhaseA_Encoder0) (Dangling_Input_Signal))
			((PhaseA_Encoder1) (PhaseA_Encoder1))
			((PhaseB_Encoder0) (Dangling_Input_Signal))
			((PhaseB_Encoder1) (PhaseB_Encoder1))
			((RD) (RD))
			((RLS0) (Dangling_Input_Signal))
			((RLS1) (RLS1))
			((Reset) (Reset))
			((SCL) (SCL))
			((SCLinc) (SCLinc))
			((SCLreset) (SCLreset))
			((TXI) (Dangling_Input_Signal))
			((WR) (WR))
			((Enc033ctrl) (_open))
			((Enc05ctrl) (_open))
			((GP_Motor0_1) (_open))
			((GP_Motor1_1) (_open))
			((HSO) (_open))
			((Home033ctrl) (_open))
			((Home05ctrl) (_open))
			((INT) (_open))
			((LED1) (_open))
			((LED2) (_open))
			((LED3) (_open))
			((LED4) (_open))
			((LED5) (_open))
			((MHSI) (_open))
			((MTRpwr) (_open))
			((MTRpwrn) (_open))
			((MTXI) (_open))
			((PAH0) (_open))
			((PAH1) (_open))
			((PAL0) (_open))
			((PAL1) (_open))
			((PBH0) (_open))
			((PBH1) (_open))
			((PBL0) (_open))
			((PBL1) (_open))
		)
		(_strength strong0 strong1)
	)
	(_instantiation U2 0 143 (_entity .  MSP)
		(_port
			((AD) (AD))
			((AS) (AS))
			((Mclk) (Mclk))
			((RD) (RD))
			((WR) (WR))
		)
		(_strength strong0 strong1)
	)
	(_model . U4_TB 3 -1)

)
I 000051 55 3348          1078852605749 BitCounter
(_unit VERILOG 6.349C.6.256 (BitCounter 0 25 (BitCounter 0 25 ))
	(_version v32)
	(_time 1078852605686 2004.03.09 09:16:45)
	(_source (\./src/bitcounter.v\ VERILOG (\./src/bitcounter.v\ VERILOG)))
	(_use (std(standard))(vl(verilog_logic)))
	(_base (E 5))
	(_entity
		(_time 1078852605686)
		(_use )
	)
	(_timescale 1ps 1ps)
	(_parameters    dbg   accs  )
	(_attribute nb_assign )
	(_object
		(_type (_internal ~[7:0]wire~ 0 25 (_array ~wire ((_downto (i 7) (i 0))))))
		(_port (_internal outDATA ~[7:0]wire~ 0 25 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal DriveSCL ~wire 0 25 (_architecture (_inout ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal NegSCL ~wire 0 25 (_architecture (_in ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal NegInc ~wire 0 25 (_architecture (_in ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal SCLint ~wire 0 25 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal DCORI2CCNTr ~wire 0 25 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal SCLreset ~wire 0 25 (_architecture (_in ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal Mclk ~wire 0 25 (_architecture (_in ))) (_net  ) (_nonbaction) (_noforceassign))
		(_type (_internal ~[5:0]reg~ 0 50 (_array ~reg ((_downto (i 5) (i 0))))))
		(_signal (_internal counterr ~[5:0]reg~ 0 50 (_architecture (_uni ))) (_reg ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_subprogram
			

		)
		(_type (_external ~wire (vl verilog_logic wire)))
		(_type (_external ~reg (vl verilog_logic reg)))
		(_type (_external ~event (vl verilog_logic event)))
		(_type (_external ~wand (vl verilog_logic wand)))
		(_type (_external ~wor (vl verilog_logic wor)))
		(_type (_external ~tri1 (vl verilog_logic tri1)))
		(_type (_external ~tri0 (vl verilog_logic tri0)))
		(_type (_external ~trireg (vl verilog_logic trireg)))
		(_type (_external ~supply0 (vl verilog_logic supply0)))
		(_type (_external ~supply1 (vl verilog_logic supply1)))
		(_type (_external ~real (vl verilog_logic real)))
		(_type (_external ~realtime (vl verilog_logic realtime)))
		(_type (_external ~tri (vl verilog_logic tri)))
		(_type (_external ~triand (vl verilog_logic triand)))
		(_type (_external ~trior (vl verilog_logic trior)))
		(_type (_external ~bit (vl verilog_logic bit)))
		(_type (_external ~extstd.standard.integer (std standard integer)))
		(_type (_external ~extstd.standard.bit (std standard bit)))
		(_process
			(#ASSIGN#52_0 (_architecture 0 0 52 (_process (_simple)
				(_target(4))
				(_sensitivity(8))
			)))
			(#ASSIGN#54_1 (_architecture 1 0 54 (_process (_simple)
				(_target(1))
				(_sensitivity(8))
			)))
			(#ASSIGN#56_2 (_architecture 2 0 56 (_process (_simple)
				(_target(0))
				(_sensitivity(5)(8))
			)))
			(#ALWAYS#58_3 (_architecture 3 0 58 (_process 
				(_target(8))
				(_read(7)(6)(3)(2)(8))
			)))
		)
	)
	
	
	(_defparam
	)
	(_model . BitCounter 5 -1)

)
V 000044 55 24806         1078854454842 U21
(_unit VERILOG 6.349C.6.256 (U21 0 32 (U21 0 32 ))
	(_version v32)
	(_time 1078854454639 2004.03.09 09:47:34)
	(_source (\./compile/u21.v\ VERILOG (\./compile/u21.v\ VERILOG)))
	(_use (std(standard))(vl(verilog_logic)))
	(_base (E 11))
	(_entity
		(_time 1078854454639)
		(_use )
	)
	(_timescale 1ns 1ns)
	(_parameters    dbg   accs  )
	(_attribute )
	(_object
		(_port (_internal AS ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Brake0 ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Brake1 ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal DIR0 ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal DIR1 ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Enc033FLG ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Enc05FLG ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Enc133FLG ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Enc15FLG ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal FLS0 ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal FLS1 ~wire 0 33 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal GP_Motor0_0 ~wire 0 33 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal GP_Motor1_0 ~wire 0 33 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal HSI ~wire 0 33 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal Home0 ~wire 0 33 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Home033FLG ~wire 0 33 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Home05FLG ~wire 0 33 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Home1 ~wire 0 33 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Home133FLG ~wire 0 33 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Home15FLG ~wire 0 33 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal INTbus ~wire 0 34 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal LightSense ~wire 0 34 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal MHSO ~wire 0 34 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal Mclk ~wire 0 34 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PWM1 ~wire 0 34 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PWM2 ~wire 0 34 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PhaseA_Encoder0 ~wire 0 34 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PhaseA_Encoder1 ~wire 0 34 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PhaseB_Encoder0 ~wire 0 34 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PhaseB_Encoder1 ~wire 0 34 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal RD ~wire 0 35 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal RLS0 ~wire 0 35 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal RLS1 ~wire 0 35 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Reset ~wire 0 35 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal SCLinc ~wire 0 35 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal SCLreset ~wire 0 35 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal TXI ~wire 0 35 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal WR ~wire 0 35 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_type (_internal ~[5:0]wire~ 0 35 (_array ~wire ((_downto (i 5) (i 0))))))
		(_port (_internal I2CS ~[5:0]wire~ 0 35 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Enc033ctrl ~wire 0 35 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Enc05ctrl ~wire 0 36 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Enc133ctrl ~wire 0 36 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Enc15ctrl ~wire 0 36 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal GP_Motor0_1 ~wire 0 36 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal GP_Motor1_1 ~wire 0 36 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal HSO ~wire 0 36 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal Home033ctrl ~wire 0 36 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Home05ctrl ~wire 0 36 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Home133ctrl ~wire 0 36 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Home15ctrl ~wire 0 36 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal INT ~wire 0 37 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal LED1 ~wire 0 37 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal LED2 ~wire 0 37 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal LED3 ~wire 0 37 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal LED4 ~wire 0 37 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal LED5 ~wire 0 37 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal MHSI ~wire 0 37 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal MTRpwr ~wire 0 37 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal MTRpwrn ~wire 0 37 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal MTXI ~wire 0 37 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal PAH0 ~wire 0 38 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PAH1 ~wire 0 38 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PAL0 ~wire 0 38 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PAL1 ~wire 0 38 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PBH0 ~wire 0 38 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PBH1 ~wire 0 38 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PBL0 ~wire 0 38 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PBL1 ~wire 0 38 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal TP10 ~wire 0 38 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal TP11 ~wire 0 38 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal SCL ~wire 0 39 (_architecture (_inout ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_type (_internal ~[7:0]wire~ 0 39 (_array ~wire ((_downto (i 7) (i 0))))))
		(_port (_internal AD ~[7:0]wire~ 0 39 (_architecture (_inout ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET1635 ~wire 0 188 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET1643 ~wire 0 189 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET1651 ~wire 0 190 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET1659 ~wire 0 191 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET1667 ~wire 0 192 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET1675 ~wire 0 193 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET1683 ~wire 0 194 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET1691 ~wire 0 195 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET1699 ~wire 0 196 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET1707 ~wire 0 197 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET1970 ~wire 0 198 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET1978 ~wire 0 199 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET1989 ~wire 0 200 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET2017 ~wire 0 201 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET2025 ~wire 0 202 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET2036 ~wire 0 203 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET2047 ~wire 0 204 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET2064 ~wire 0 205 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET2078 ~wire 0 206 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET2311 ~wire 0 207 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET2482 ~wire 0 208 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET2493 ~wire 0 209 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET2501 ~wire 0 210 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET2512 ~wire 0 211 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET2528 ~wire 0 212 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET2539 ~wire 0 213 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET2575 ~wire 0 214 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET3248 ~wire 0 215 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET3253 ~wire 0 216 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET3919 ~wire 0 217 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal NET3926 ~wire 0 218 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal NET615 ~wire 0 219 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal NET621 ~wire 0 220 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal NET629 ~wire 0 221 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal BUS1564 ~[7:0]wire~ 0 222 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal inDATA ~[7:0]wire~ 0 223 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal outDATA ~[7:0]wire~ 0 224 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_subprogram
			

		)
		(_type (_external ~wire (vl verilog_logic wire)))
		(_type (_external ~reg (vl verilog_logic reg)))
		(_type (_external ~event (vl verilog_logic event)))
		(_type (_external ~wand (vl verilog_logic wand)))
		(_type (_external ~wor (vl verilog_logic wor)))
		(_type (_external ~tri1 (vl verilog_logic tri1)))
		(_type (_external ~tri0 (vl verilog_logic tri0)))
		(_type (_external ~trireg (vl verilog_logic trireg)))
		(_type (_external ~supply0 (vl verilog_logic supply0)))
		(_type (_external ~supply1 (vl verilog_logic supply1)))
		(_type (_external ~real (vl verilog_logic real)))
		(_type (_external ~realtime (vl verilog_logic realtime)))
		(_type (_external ~tri (vl verilog_logic tri)))
		(_type (_external ~triand (vl verilog_logic triand)))
		(_type (_external ~trior (vl verilog_logic trior)))
		(_type (_external ~bit (vl verilog_logic bit)))
		(_type (_external ~extstd.standard.integer (std standard integer)))
		(_type (_external ~extstd.standard.bit (std standard bit)))
		(_process
			(#ASSIGN#454_0 (_architecture 0 0 454 (_process (_alias ((NET3919)(SCLreset)))(_simple)
				(_target(101))
				(_sensitivity(35))
			)))
			(#ASSIGN#455_1 (_architecture 1 0 455 (_process (_alias ((NET3926)(SCLinc)))(_simple)
				(_target(102))
				(_sensitivity(34))
			)))
			(#ASSIGN#456_2 (_architecture 2 0 456 (_process (_alias ((NET615)(MHSO)))(_simple)
				(_target(103))
				(_sensitivity(22))
			)))
			(#ASSIGN#457_3 (_architecture 3 0 457 (_process (_alias ((NET621)(HSI)))(_simple)
				(_target(104))
				(_sensitivity(13))
			)))
			(#ASSIGN#458_4 (_architecture 4 0 458 (_process (_alias ((NET629)(TXI)))(_simple)
				(_target(105))
				(_sensitivity(36))
			)))
			(#ASSIGN#461_5 (_architecture 5 0 461 (_process (_alias ((HSO)(NET615)))(_simple)
				(_target(45))
				(_sensitivity(103))
			)))
			(#ASSIGN#462_6 (_architecture 6 0 462 (_process (_alias ((MHSI)(NET621)))(_simple)
				(_target(56))
				(_sensitivity(104))
			)))
			(#ASSIGN#463_7 (_architecture 7 0 463 (_process (_alias ((MTXI)(NET629)))(_simple)
				(_target(59))
				(_sensitivity(105))
			)))
			(#ASSIGN#464_8 (_architecture 8 0 464 (_process (_alias ((TP10)(NET3919)))(_simple)
				(_target(68))
				(_sensitivity(101))
			)))
			(#ASSIGN#465_9 (_architecture 9 0 465 (_process (_alias ((TP11)(NET3926)))(_simple)
				(_target(69))
				(_sensitivity(102))
			)))
		)
	)
	
	
	(_defparam
	)
	(_scope
	)
	(_instantiation U1 0 228 (_entity .  Servos)
		(_port
			((DCOR0CNTHIGHr) (NET1667))
			((DCOR0CNTLOWr) (NET1651))
			((DCOR0CNTMIDr) (NET1659))
			((DCOR0THRESLOWr) (NET1635))
			((DCOR0THRESMIDr) (NET1643))
			((DCOR1CNTHIGHr) (NET1675))
			((DCOR1CNTLOWr) (NET1683))
			((DCOR1CNTMIDr) (NET1691))
			((DCOR1THRESLOWr) (NET1707))
			((DCOR1THRESMIDr) (NET1699))
			((DCORENCCTLw) (NET1970))
			((DCORIFGr) (NET1978))
			((DCORIFGw) (NET1989))
			((Hfound0) (NET2482))
			((Hfound1) (NET2493))
			((Home_Encoder0) (Home0))
			((Home_Encoder1) (Home1))
			((Mclk) (Mclk))
			((MotorIn0) (GP_Motor0_0))
			((Motorin1) (GP_Motor1_0))
			((PhaseA_Encoder0) (PhaseA_Encoder0))
			((PhaseA_Encoder1) (PhaseA_Encoder1))
			((PhaseB_Encoder0) (PhaseB_Encoder0))
			((PhaseB_Encoder1) (PhaseB_Encoder1))
			((Reset) (Reset))
			((Tfound0) (NET2501))
			((Tfound1) (NET2512))
			((inDATA) (inDATA))
			((outDATA) (outDATA))
		)
		(_strength strong0 strong1)
	)
	(_instantiation U11 0 263 (_entity .  I2Cfix)
		(_port
			((DCORI2CCNTr) (NET2311))
			((Inc) (NET3926))
			((Mclk) (Mclk))
			((SCL) (SCL))
			((SCLint) (NET2539))
			((SCLreset) (NET3919))
			((outDATA) (outDATA))
		)
		(_strength strong0 strong1)
	)
	(_instantiation U12 0 276 (_entity .  U21AddDecode)
		(_port
			((ADDR) (BUS1564))
			((AS) (AS))
			((DCOR0CNTHIGHr) (NET1667))
			((DCOR0CNTLOWr) (NET1651))
			((DCOR0CNTMIDr) (NET1659))
			((DCOR0THRESLOWr) (NET1635))
			((DCOR0THRESMIDr) (NET1643))
			((DCOR1CNTHIGHr) (NET1675))
			((DCOR1CNTLOWr) (NET1683))
			((DCOR1CNTMIDr) (NET1691))
			((DCOR1THRESLOWr) (NET1707))
			((DCOR1THRESMIDr) (NET1699))
			((DCORCONFIGr) (NET2064))
			((DCORENCCTLw) (NET1970))
			((DCORENCPWRr) (NET2036))
			((DCORENCPWRw) (NET2025))
			((DCORI2CCNTr) (NET2311))
			((DCORIEw) (NET2078))
			((DCORIFGr) (NET1978))
			((DCORIFGw) (NET1989))
			((DCORLIMITSr) (NET2047))
			((DCOROUTw) (NET2017))
			((RD) (RD))
			((WR) (WR))
		)
		(_strength strong0 strong1)
	)
	(_instantiation U2 0 306 (_entity .  Interface)
		(_port
			((AD) (AD))
			((ADDR) (BUS1564))
			((AS) (AS))
			((Mclk) (Mclk))
			((RD) (RD))
			((Reset) (Reset))
			((WR) (WR))
			((inDATA) (inDATA))
			((outDATA) (outDATA))
		)
		(_strength strong0 strong1)
	)
	(_instantiation U3 0 321 (_entity .  Interrupt)
		(_port
			((BusInt) (INTbus))
			((DCORIEw) (NET2078))
			((Homed0) (NET2482))
			((Homed1) (NET2493))
			((I2Cint) (NET2539))
			((INT) (INT))
			((LSwitchInt) (NET2575))
			((Mclk) (Mclk))
			((PWRint) (NET2528))
			((Reset) (Reset))
			((Thres0) (NET2501))
			((Thres1) (NET2512))
			((inDATA) (inDATA))
		)
		(_strength strong0 strong1)
	)
	(_instantiation U4 0 340 (_entity .  PWRreg)
		(_port
			((DCORENCPWRr) (NET2036))
			((DCORENCPWRw) (NET2025))
			((DCORIFGr) (NET1978))
			((DCORIFGw) (NET1989))
			((Enc033ctl) (Home15ctrl))
			((Enc033flg) (Enc033FLG))
			((Enc05ctl) (Home133ctrl))
			((Enc05flg) (Enc05FLG))
			((Enc133ctl) (Home05ctrl))
			((Enc133flg) (Enc133FLG))
			((Enc15ctl) (Home033ctrl))
			((Enc15flg) (Enc15FLG))
			((Hme033ctl) (Enc15ctrl))
			((Hme033flg) (Home033FLG))
			((Hme05ctl) (Enc133ctrl))
			((Hme05flg) (Home05FLG))
			((Hme133ctl) (Enc05ctrl))
			((Hme133flg) (Home133FLG))
			((Hme15ctl) (Enc033ctrl))
			((Hme15flg) (Home15FLG))
			((Mclk) (Mclk))
			((PWRint) (NET2528))
			((Reset) (Reset))
			((inDATA) (inDATA))
			((outDATA) (outDATA))
		)
		(_strength strong0 strong1)
	)
	(_instantiation U5 0 371 (_entity .  Lswitch)
		(_port
			((Brake0) (Brake0))
			((Brake1) (Brake1))
			((DCORIFGr) (NET1978))
			((DCORIFGw) (NET1989))
			((DCORLIMITSr) (NET2047))
			((DIR0) (DIR0))
			((DIR1) (DIR1))
			((FLS0) (FLS0))
			((FLS1) (FLS1))
			((Home0) (Home0))
			((Home1) (Home1))
			((LSwitchInt) (NET2575))
			((Mclk) (Mclk))
			((RLS0) (RLS0))
			((RLS1) (RLS1))
			((Reset) (Reset))
			((fBRK0) (NET3248))
			((fBRK1) (NET3253))
			((inDATA) (inDATA))
			((outDATA) (outDATA))
		)
		(_strength strong0 strong1)
	)
	(_instantiation U6 0 397 (_entity .  I2CAddress)
		(_port
			((DCORCONFIGr) (NET2064))
			((I2CS) (I2CS))
			((MotorIn0) (GP_Motor0_0))
			((MotorIn1) (GP_Motor1_0))
			((outDATA) (outDATA))
		)
		(_strength strong0 strong1)
	)
	(_instantiation U7 0 408 (_entity .  PWMcontrol)
		(_port
			((Brake1) (Brake0))
			((Brake2) (Brake1))
			((DIR1) (DIR0))
			((DIR2) (DIR1))
			((HBRK1) (NET3248))
			((HBRK2) (NET3253))
			((PAH1) (PAH0))
			((PAH2) (PBL1))
			((PAL1) (PAL0))
			((PAL2) (PBH1))
			((PBH1) (PBH0))
			((PBH2) (PAL1))
			((PBL1) (PBL0))
			((PBL2) (PAH1))
			((PWM1) (PWM1))
			((PWM2) (PWM2))
			((fBRK1) (NET3248))
			((fBRK2) (NET3253))
		)
		(_strength strong0 strong1)
	)
	(_instantiation U9 0 432 (_entity .  MISCouts)
		(_port
			((DCOROUTw) (NET2017))
			((GP_Motor0_1) (GP_Motor0_1))
			((GP_Motor1_1) (GP_Motor1_1))
			((LED1) (LED1))
			((LED2) (LED2))
			((LED3) (LED3))
			((LED4) (LED4))
			((LED5) (LED5))
			((LightSense) (LightSense))
			((MTRpwr) (MTRpwr))
			((MTRpwrn) (MTRpwrn))
			((Mclk) (Mclk))
			((Reset) (Reset))
			((inDATA) (inDATA))
		)
		(_strength strong0 strong1)
	)
	(_model . U21 11 -1)

)
I 000051 55 3596          1078857334592 BitCounter
(_unit VERILOG 6.349C.6.256 (BitCounter 0 25 (BitCounter 0 25 ))
	(_version v32)
	(_time 1078857334389 2004.03.09 10:35:34)
	(_source (\./src/bitcounter.v\ VERILOG (\./src/bitcounter.v\ VERILOG)))
	(_use (std(standard))(vl(verilog_logic)))
	(_base (E 6))
	(_entity
		(_time 1078857334389)
		(_use )
	)
	(_timescale 1ps 1ps)
	(_parameters    dbg   accs  )
	(_attribute nb_assign )
	(_object
		(_type (_internal ~[7:0]wire~ 0 25 (_array ~wire ((_downto (i 7) (i 0))))))
		(_port (_internal outDATA ~[7:0]wire~ 0 25 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal NegInc ~wire 0 25 (_architecture (_in ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal SCLreset ~wire 0 25 (_architecture (_in ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal Mclk ~wire 0 25 (_architecture (_in ))) (_net  ) (_nonbaction) (_noforceassign))
		(_port (_internal SCLenable ~wire 0 25 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal DriveSCL ~wire 0 25 (_architecture (_inout ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal NegSCL ~wire 0 25 (_architecture (_in ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal DCORI2CCNTr ~wire 0 25 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal SCLint ~wire 0 25 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_type (_internal ~[5:0]reg~ 0 52 (_array ~reg ((_downto (i 5) (i 0))))))
		(_signal (_internal counterr ~[5:0]reg~ 0 52 (_architecture (_uni ))) (_reg ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_subprogram
			

		)
		(_type (_external ~wire (vl verilog_logic wire)))
		(_type (_external ~reg (vl verilog_logic reg)))
		(_type (_external ~event (vl verilog_logic event)))
		(_type (_external ~wand (vl verilog_logic wand)))
		(_type (_external ~wor (vl verilog_logic wor)))
		(_type (_external ~tri1 (vl verilog_logic tri1)))
		(_type (_external ~tri0 (vl verilog_logic tri0)))
		(_type (_external ~trireg (vl verilog_logic trireg)))
		(_type (_external ~supply0 (vl verilog_logic supply0)))
		(_type (_external ~supply1 (vl verilog_logic supply1)))
		(_type (_external ~real (vl verilog_logic real)))
		(_type (_external ~realtime (vl verilog_logic realtime)))
		(_type (_external ~tri (vl verilog_logic tri)))
		(_type (_external ~triand (vl verilog_logic triand)))
		(_type (_external ~trior (vl verilog_logic trior)))
		(_type (_external ~bit (vl verilog_logic bit)))
		(_type (_external ~extstd.standard.integer (std standard integer)))
		(_type (_external ~extstd.standard.bit (std standard bit)))
		(_process
			(#ASSIGN#54_0 (_architecture 0 0 54 (_process (_simple)
				(_target(8))
				(_sensitivity(9))
			)))
			(#ASSIGN#56_1 (_architecture 1 0 56 (_process (_simple)
				(_target(4))
				(_sensitivity(9))
			)))
			(#ASSIGN#58_2 (_architecture 2 0 58 (_process (_simple)
				(_target(5))
				(_sensitivity(4))
			)))
			(#ASSIGN#60_3 (_architecture 3 0 60 (_process (_simple)
				(_target(0))
				(_sensitivity(7)(9))
			)))
			(#ALWAYS#62_4 (_architecture 4 0 62 (_process 
				(_target(9))
				(_read(3)(2)(1)(6)(9))
			)))
		)
	)
	
	
	(_defparam
	)
	(_model . BitCounter 6 -1)

)
V 000047 55 3722          1078857354140 I2Cfix
(_unit VERILOG 6.349C.6.256 (I2Cfix 0 32 (I2Cfix 0 32 ))
	(_version v32)
	(_time 1078857354092 2004.03.09 10:35:54)
	(_source (\./compile/i2cfix.v\ VERILOG (\./compile/i2cfix.v\ VERILOG)))
	(_use (std(standard))(vl(verilog_logic)))
	(_base (E 1))
	(_entity
		(_time 1078857354092)
		(_use )
	)
	(_timescale 1ns 1ns)
	(_parameters    dbg   accs  )
	(_attribute )
	(_object
		(_port (_internal DCORI2CCNTr ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Inc ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Mclk ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal SCLreset ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal SCLenable ~wire 0 32 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal SCLint ~wire 0 32 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_type (_internal ~[7:0]wire~ 0 32 (_array ~wire ((_downto (i 7) (i 0))))))
		(_port (_internal outDATA ~[7:0]wire~ 0 32 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal SCL ~wire 0 32 (_architecture (_inout ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal Incdetect ~wire 0 53 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal SCLdetect ~wire 0 54 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_subprogram
			

		)
		(_type (_external ~wire (vl verilog_logic wire)))
		(_type (_external ~reg (vl verilog_logic reg)))
		(_type (_external ~event (vl verilog_logic event)))
		(_type (_external ~wand (vl verilog_logic wand)))
		(_type (_external ~wor (vl verilog_logic wor)))
		(_type (_external ~tri1 (vl verilog_logic tri1)))
		(_type (_external ~tri0 (vl verilog_logic tri0)))
		(_type (_external ~trireg (vl verilog_logic trireg)))
		(_type (_external ~supply0 (vl verilog_logic supply0)))
		(_type (_external ~supply1 (vl verilog_logic supply1)))
		(_type (_external ~real (vl verilog_logic real)))
		(_type (_external ~realtime (vl verilog_logic realtime)))
		(_type (_external ~tri (vl verilog_logic tri)))
		(_type (_external ~triand (vl verilog_logic triand)))
		(_type (_external ~trior (vl verilog_logic trior)))
		(_type (_external ~bit (vl verilog_logic bit)))
		(_type (_external ~extstd.standard.integer (std standard integer)))
		(_type (_external ~extstd.standard.bit (std standard bit)))
	)
	
	
	(_defparam
	)
	(_scope
	)
	(_instantiation U1 0 58 (_entity .  NegDetect)
		(_port
			((Line) (Inc))
			((Mclk) (Mclk))
			((Ndetect) (Incdetect))
		)
		(_strength strong0 strong1)
	)
	(_instantiation U2 0 67 (_entity .  NegDetect)
		(_port
			((Line) (SCL))
			((Mclk) (Mclk))
			((Ndetect) (SCLdetect))
		)
		(_strength strong0 strong1)
	)
	(_instantiation U3 0 76 (_entity .  BitCounter)
		(_port
			((DCORI2CCNTr) (DCORI2CCNTr))
			((DriveSCL) (SCL))
			((Mclk) (Mclk))
			((NegInc) (Incdetect))
			((NegSCL) (SCLdetect))
			((SCLenable) (SCLenable))
			((SCLint) (SCLint))
			((SCLreset) (SCLreset))
			((outDATA) (outDATA))
		)
		(_strength strong0 strong1)
	)
	(_model . I2Cfix 1 -1)

)
V 000044 55 24982         1078857480545 U21
(_unit VERILOG 6.349C.6.256 (U21 0 32 (U21 0 32 ))
	(_version v32)
	(_time 1078857480451 2004.03.09 10:38:00)
	(_source (\./compile/u21.v\ VERILOG (\./compile/u21.v\ VERILOG)))
	(_use (std(standard))(vl(verilog_logic)))
	(_base (E 11))
	(_entity
		(_time 1078857480451)
		(_use )
	)
	(_timescale 1ns 1ns)
	(_parameters    dbg   accs  )
	(_attribute )
	(_object
		(_port (_internal AS ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Brake0 ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Brake1 ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal DIR0 ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal DIR1 ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Enc033FLG ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Enc05FLG ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Enc133FLG ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Enc15FLG ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal FLS0 ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal FLS1 ~wire 0 33 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal GP_Motor0_0 ~wire 0 33 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal GP_Motor1_0 ~wire 0 33 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal HSI ~wire 0 33 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal Home0 ~wire 0 33 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Home033FLG ~wire 0 33 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Home05FLG ~wire 0 33 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Home1 ~wire 0 33 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Home133FLG ~wire 0 33 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Home15FLG ~wire 0 33 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal INTbus ~wire 0 34 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal LightSense ~wire 0 34 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal MHSO ~wire 0 34 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal Mclk ~wire 0 34 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PWM1 ~wire 0 34 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PWM2 ~wire 0 34 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PhaseA_Encoder0 ~wire 0 34 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PhaseA_Encoder1 ~wire 0 34 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PhaseB_Encoder0 ~wire 0 34 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PhaseB_Encoder1 ~wire 0 34 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal RD ~wire 0 35 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal RLS0 ~wire 0 35 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal RLS1 ~wire 0 35 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Reset ~wire 0 35 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal SCLinc ~wire 0 35 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal SCLreset ~wire 0 35 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal TXI ~wire 0 35 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal WR ~wire 0 35 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_type (_internal ~[5:0]wire~ 0 35 (_array ~wire ((_downto (i 5) (i 0))))))
		(_port (_internal I2CS ~[5:0]wire~ 0 35 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Enc033ctrl ~wire 0 35 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Enc05ctrl ~wire 0 36 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Enc133ctrl ~wire 0 36 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Enc15ctrl ~wire 0 36 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal GP_Motor0_1 ~wire 0 36 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal GP_Motor1_1 ~wire 0 36 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal HSO ~wire 0 36 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal Home033ctrl ~wire 0 36 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Home05ctrl ~wire 0 36 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Home133ctrl ~wire 0 36 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Home15ctrl ~wire 0 36 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal INT ~wire 0 37 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal LED1 ~wire 0 37 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal LED2 ~wire 0 37 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal LED3 ~wire 0 37 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal LED4 ~wire 0 37 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal LED5 ~wire 0 37 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal MHSI ~wire 0 37 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal MTRpwr ~wire 0 37 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal MTRpwrn ~wire 0 37 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal MTXI ~wire 0 37 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal PAH0 ~wire 0 38 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PAH1 ~wire 0 38 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PAL0 ~wire 0 38 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PAL1 ~wire 0 38 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PBH0 ~wire 0 38 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PBH1 ~wire 0 38 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PBL0 ~wire 0 38 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PBL1 ~wire 0 38 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal TP10 ~wire 0 38 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal TP11 ~wire 0 38 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal TP12 ~wire 0 39 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal SCL ~wire 0 39 (_architecture (_inout ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_type (_internal ~[7:0]wire~ 0 39 (_array ~wire ((_downto (i 7) (i 0))))))
		(_port (_internal AD ~[7:0]wire~ 0 39 (_architecture (_inout ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET1635 ~wire 0 190 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET1643 ~wire 0 191 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET1651 ~wire 0 192 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET1659 ~wire 0 193 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET1667 ~wire 0 194 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET1675 ~wire 0 195 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET1683 ~wire 0 196 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET1691 ~wire 0 197 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET1699 ~wire 0 198 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET1707 ~wire 0 199 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET1970 ~wire 0 200 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET1978 ~wire 0 201 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET1989 ~wire 0 202 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET2017 ~wire 0 203 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET2025 ~wire 0 204 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET2036 ~wire 0 205 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET2047 ~wire 0 206 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET2064 ~wire 0 207 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET2078 ~wire 0 208 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET2311 ~wire 0 209 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET2482 ~wire 0 210 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET2493 ~wire 0 211 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET2501 ~wire 0 212 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET2512 ~wire 0 213 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET2528 ~wire 0 214 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET2539 ~wire 0 215 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET2575 ~wire 0 216 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET3248 ~wire 0 217 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET3253 ~wire 0 218 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET3919 ~wire 0 219 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal NET3926 ~wire 0 220 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal NET615 ~wire 0 221 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal NET621 ~wire 0 222 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal NET629 ~wire 0 223 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal BUS1564 ~[7:0]wire~ 0 224 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal inDATA ~[7:0]wire~ 0 225 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal outDATA ~[7:0]wire~ 0 226 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_subprogram
			

		)
		(_type (_external ~wire (vl verilog_logic wire)))
		(_type (_external ~reg (vl verilog_logic reg)))
		(_type (_external ~event (vl verilog_logic event)))
		(_type (_external ~wand (vl verilog_logic wand)))
		(_type (_external ~wor (vl verilog_logic wor)))
		(_type (_external ~tri1 (vl verilog_logic tri1)))
		(_type (_external ~tri0 (vl verilog_logic tri0)))
		(_type (_external ~trireg (vl verilog_logic trireg)))
		(_type (_external ~supply0 (vl verilog_logic supply0)))
		(_type (_external ~supply1 (vl verilog_logic supply1)))
		(_type (_external ~real (vl verilog_logic real)))
		(_type (_external ~realtime (vl verilog_logic realtime)))
		(_type (_external ~tri (vl verilog_logic tri)))
		(_type (_external ~triand (vl verilog_logic triand)))
		(_type (_external ~trior (vl verilog_logic trior)))
		(_type (_external ~bit (vl verilog_logic bit)))
		(_type (_external ~extstd.standard.integer (std standard integer)))
		(_type (_external ~extstd.standard.bit (std standard bit)))
		(_process
			(#ASSIGN#457_0 (_architecture 0 0 457 (_process (_alias ((NET3919)(SCLreset)))(_simple)
				(_target(102))
				(_sensitivity(35))
			)))
			(#ASSIGN#458_1 (_architecture 1 0 458 (_process (_alias ((NET3926)(SCLinc)))(_simple)
				(_target(103))
				(_sensitivity(34))
			)))
			(#ASSIGN#459_2 (_architecture 2 0 459 (_process (_alias ((NET615)(MHSO)))(_simple)
				(_target(104))
				(_sensitivity(22))
			)))
			(#ASSIGN#460_3 (_architecture 3 0 460 (_process (_alias ((NET621)(HSI)))(_simple)
				(_target(105))
				(_sensitivity(13))
			)))
			(#ASSIGN#461_4 (_architecture 4 0 461 (_process (_alias ((NET629)(TXI)))(_simple)
				(_target(106))
				(_sensitivity(36))
			)))
			(#ASSIGN#464_5 (_architecture 5 0 464 (_process (_alias ((HSO)(NET615)))(_simple)
				(_target(45))
				(_sensitivity(104))
			)))
			(#ASSIGN#465_6 (_architecture 6 0 465 (_process (_alias ((MHSI)(NET621)))(_simple)
				(_target(56))
				(_sensitivity(105))
			)))
			(#ASSIGN#466_7 (_architecture 7 0 466 (_process (_alias ((MTXI)(NET629)))(_simple)
				(_target(59))
				(_sensitivity(106))
			)))
			(#ASSIGN#467_8 (_architecture 8 0 467 (_process (_alias ((TP10)(NET3919)))(_simple)
				(_target(68))
				(_sensitivity(102))
			)))
			(#ASSIGN#468_9 (_architecture 9 0 468 (_process (_alias ((TP11)(NET3926)))(_simple)
				(_target(69))
				(_sensitivity(103))
			)))
		)
	)
	
	
	(_defparam
	)
	(_scope
	)
	(_instantiation U1 0 230 (_entity .  Servos)
		(_port
			((DCOR0CNTHIGHr) (NET1667))
			((DCOR0CNTLOWr) (NET1651))
			((DCOR0CNTMIDr) (NET1659))
			((DCOR0THRESLOWr) (NET1635))
			((DCOR0THRESMIDr) (NET1643))
			((DCOR1CNTHIGHr) (NET1675))
			((DCOR1CNTLOWr) (NET1683))
			((DCOR1CNTMIDr) (NET1691))
			((DCOR1THRESLOWr) (NET1707))
			((DCOR1THRESMIDr) (NET1699))
			((DCORENCCTLw) (NET1970))
			((DCORIFGr) (NET1978))
			((DCORIFGw) (NET1989))
			((Hfound0) (NET2482))
			((Hfound1) (NET2493))
			((Home_Encoder0) (Home0))
			((Home_Encoder1) (Home1))
			((Mclk) (Mclk))
			((MotorIn0) (GP_Motor0_0))
			((Motorin1) (GP_Motor1_0))
			((PhaseA_Encoder0) (PhaseA_Encoder0))
			((PhaseA_Encoder1) (PhaseA_Encoder1))
			((PhaseB_Encoder0) (PhaseB_Encoder0))
			((PhaseB_Encoder1) (PhaseB_Encoder1))
			((Reset) (Reset))
			((Tfound0) (NET2501))
			((Tfound1) (NET2512))
			((inDATA) (inDATA))
			((outDATA) (outDATA))
		)
		(_strength strong0 strong1)
	)
	(_instantiation U11 0 265 (_entity .  I2Cfix)
		(_port
			((DCORI2CCNTr) (NET2311))
			((Inc) (NET3926))
			((Mclk) (Mclk))
			((SCL) (SCL))
			((SCLenable) (TP12))
			((SCLint) (NET2539))
			((SCLreset) (NET3919))
			((outDATA) (outDATA))
		)
		(_strength strong0 strong1)
	)
	(_instantiation U12 0 279 (_entity .  U21AddDecode)
		(_port
			((ADDR) (BUS1564))
			((AS) (AS))
			((DCOR0CNTHIGHr) (NET1667))
			((DCOR0CNTLOWr) (NET1651))
			((DCOR0CNTMIDr) (NET1659))
			((DCOR0THRESLOWr) (NET1635))
			((DCOR0THRESMIDr) (NET1643))
			((DCOR1CNTHIGHr) (NET1675))
			((DCOR1CNTLOWr) (NET1683))
			((DCOR1CNTMIDr) (NET1691))
			((DCOR1THRESLOWr) (NET1707))
			((DCOR1THRESMIDr) (NET1699))
			((DCORCONFIGr) (NET2064))
			((DCORENCCTLw) (NET1970))
			((DCORENCPWRr) (NET2036))
			((DCORENCPWRw) (NET2025))
			((DCORI2CCNTr) (NET2311))
			((DCORIEw) (NET2078))
			((DCORIFGr) (NET1978))
			((DCORIFGw) (NET1989))
			((DCORLIMITSr) (NET2047))
			((DCOROUTw) (NET2017))
			((RD) (RD))
			((WR) (WR))
		)
		(_strength strong0 strong1)
	)
	(_instantiation U2 0 309 (_entity .  Interface)
		(_port
			((AD) (AD))
			((ADDR) (BUS1564))
			((AS) (AS))
			((Mclk) (Mclk))
			((RD) (RD))
			((Reset) (Reset))
			((WR) (WR))
			((inDATA) (inDATA))
			((outDATA) (outDATA))
		)
		(_strength strong0 strong1)
	)
	(_instantiation U3 0 324 (_entity .  Interrupt)
		(_port
			((BusInt) (INTbus))
			((DCORIEw) (NET2078))
			((Homed0) (NET2482))
			((Homed1) (NET2493))
			((I2Cint) (NET2539))
			((INT) (INT))
			((LSwitchInt) (NET2575))
			((Mclk) (Mclk))
			((PWRint) (NET2528))
			((Reset) (Reset))
			((Thres0) (NET2501))
			((Thres1) (NET2512))
			((inDATA) (inDATA))
		)
		(_strength strong0 strong1)
	)
	(_instantiation U4 0 343 (_entity .  PWRreg)
		(_port
			((DCORENCPWRr) (NET2036))
			((DCORENCPWRw) (NET2025))
			((DCORIFGr) (NET1978))
			((DCORIFGw) (NET1989))
			((Enc033ctl) (Home15ctrl))
			((Enc033flg) (Enc033FLG))
			((Enc05ctl) (Home133ctrl))
			((Enc05flg) (Enc05FLG))
			((Enc133ctl) (Home05ctrl))
			((Enc133flg) (Enc133FLG))
			((Enc15ctl) (Home033ctrl))
			((Enc15flg) (Enc15FLG))
			((Hme033ctl) (Enc15ctrl))
			((Hme033flg) (Home033FLG))
			((Hme05ctl) (Enc133ctrl))
			((Hme05flg) (Home05FLG))
			((Hme133ctl) (Enc05ctrl))
			((Hme133flg) (Home133FLG))
			((Hme15ctl) (Enc033ctrl))
			((Hme15flg) (Home15FLG))
			((Mclk) (Mclk))
			((PWRint) (NET2528))
			((Reset) (Reset))
			((inDATA) (inDATA))
			((outDATA) (outDATA))
		)
		(_strength strong0 strong1)
	)
	(_instantiation U5 0 374 (_entity .  Lswitch)
		(_port
			((Brake0) (Brake0))
			((Brake1) (Brake1))
			((DCORIFGr) (NET1978))
			((DCORIFGw) (NET1989))
			((DCORLIMITSr) (NET2047))
			((DIR0) (DIR0))
			((DIR1) (DIR1))
			((FLS0) (FLS0))
			((FLS1) (FLS1))
			((Home0) (Home0))
			((Home1) (Home1))
			((LSwitchInt) (NET2575))
			((Mclk) (Mclk))
			((RLS0) (RLS0))
			((RLS1) (RLS1))
			((Reset) (Reset))
			((fBRK0) (NET3248))
			((fBRK1) (NET3253))
			((inDATA) (inDATA))
			((outDATA) (outDATA))
		)
		(_strength strong0 strong1)
	)
	(_instantiation U6 0 400 (_entity .  I2CAddress)
		(_port
			((DCORCONFIGr) (NET2064))
			((I2CS) (I2CS))
			((MotorIn0) (GP_Motor0_0))
			((MotorIn1) (GP_Motor1_0))
			((outDATA) (outDATA))
		)
		(_strength strong0 strong1)
	)
	(_instantiation U7 0 411 (_entity .  PWMcontrol)
		(_port
			((Brake1) (Brake0))
			((Brake2) (Brake1))
			((DIR1) (DIR0))
			((DIR2) (DIR1))
			((HBRK1) (NET3248))
			((HBRK2) (NET3253))
			((PAH1) (PAH0))
			((PAH2) (PBL1))
			((PAL1) (PAL0))
			((PAL2) (PBH1))
			((PBH1) (PBH0))
			((PBH2) (PAL1))
			((PBL1) (PBL0))
			((PBL2) (PAH1))
			((PWM1) (PWM1))
			((PWM2) (PWM2))
			((fBRK1) (NET3248))
			((fBRK2) (NET3253))
		)
		(_strength strong0 strong1)
	)
	(_instantiation U9 0 435 (_entity .  MISCouts)
		(_port
			((DCOROUTw) (NET2017))
			((GP_Motor0_1) (GP_Motor0_1))
			((GP_Motor1_1) (GP_Motor1_1))
			((LED1) (LED1))
			((LED2) (LED2))
			((LED3) (LED3))
			((LED4) (LED4))
			((LED5) (LED5))
			((LightSense) (LightSense))
			((MTRpwr) (MTRpwr))
			((MTRpwrn) (MTRpwrn))
			((Mclk) (Mclk))
			((Reset) (Reset))
			((inDATA) (inDATA))
		)
		(_strength strong0 strong1)
	)
	(_model . U21 11 -1)

)
V 000044 55 25525         1078861277781 U21
(_unit VERILOG 6.349C.6.256 (U21 0 32 (U21 0 32 ))
	(_version v32)
	(_time 1078861277701 2004.03.09 11:41:17)
	(_source (\./compile/u21.v\ VERILOG (\./compile/u21.v\ VERILOG)))
	(_use (std(standard))(vl(verilog_logic)))
	(_base (E 14))
	(_entity
		(_time 1078861277701)
		(_use )
	)
	(_timescale 1ns 1ns)
	(_parameters    dbg   accs  )
	(_attribute )
	(_object
		(_port (_internal AS ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Brake0 ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Brake1 ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal DIR0 ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal DIR1 ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Enc033FLG ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Enc05FLG ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Enc133FLG ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Enc15FLG ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal FLS0 ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal FLS1 ~wire 0 33 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal GP_Motor0_0 ~wire 0 33 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal GP_Motor1_0 ~wire 0 33 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal HSI ~wire 0 33 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal Home0 ~wire 0 33 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Home033FLG ~wire 0 33 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Home05FLG ~wire 0 33 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Home1 ~wire 0 33 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Home133FLG ~wire 0 33 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Home15FLG ~wire 0 33 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal INTbus ~wire 0 34 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal LightSense ~wire 0 34 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal MHSO ~wire 0 34 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal Mclk ~wire 0 34 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PWM1 ~wire 0 34 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PWM2 ~wire 0 34 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PhaseA_Encoder0 ~wire 0 34 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PhaseA_Encoder1 ~wire 0 34 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PhaseB_Encoder0 ~wire 0 34 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PhaseB_Encoder1 ~wire 0 34 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal RD ~wire 0 35 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal RLS0 ~wire 0 35 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal RLS1 ~wire 0 35 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Reset ~wire 0 35 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal SCLinc ~wire 0 35 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal SCLreset ~wire 0 35 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal TXI ~wire 0 35 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal WR ~wire 0 35 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_type (_internal ~[5:0]wire~ 0 35 (_array ~wire ((_downto (i 5) (i 0))))))
		(_port (_internal I2CS ~[5:0]wire~ 0 35 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Enc033ctrl ~wire 0 35 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Enc05ctrl ~wire 0 36 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Enc133ctrl ~wire 0 36 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Enc15ctrl ~wire 0 36 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal GP_Motor0_1 ~wire 0 36 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal GP_Motor1_1 ~wire 0 36 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal HSO ~wire 0 36 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal Home033ctrl ~wire 0 36 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Home05ctrl ~wire 0 36 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Home133ctrl ~wire 0 36 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Home15ctrl ~wire 0 36 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal INT ~wire 0 37 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal LED1 ~wire 0 37 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal LED2 ~wire 0 37 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal LED3 ~wire 0 37 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal LED4 ~wire 0 37 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal LED5 ~wire 0 37 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal MHSI ~wire 0 37 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal MTRpwr ~wire 0 37 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal MTRpwrn ~wire 0 37 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal MTXI ~wire 0 37 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal PAH0 ~wire 0 38 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PAH1 ~wire 0 38 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PAL0 ~wire 0 38 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PAL1 ~wire 0 38 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PBH0 ~wire 0 38 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PBH1 ~wire 0 38 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PBL0 ~wire 0 38 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PBL1 ~wire 0 38 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal TP10 ~wire 0 38 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal TP11 ~wire 0 38 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal TP12 ~wire 0 39 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal SCL ~wire 0 39 (_architecture (_inout ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_type (_internal ~[7:0]wire~ 0 39 (_array ~wire ((_downto (i 7) (i 0))))))
		(_port (_internal AD ~[7:0]wire~ 0 39 (_architecture (_inout ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET1635 ~wire 0 190 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET1643 ~wire 0 191 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET1651 ~wire 0 192 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET1659 ~wire 0 193 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET1667 ~wire 0 194 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET1675 ~wire 0 195 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET1683 ~wire 0 196 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET1691 ~wire 0 197 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET1699 ~wire 0 198 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET1707 ~wire 0 199 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET1970 ~wire 0 200 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET1978 ~wire 0 201 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET1989 ~wire 0 202 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET2017 ~wire 0 203 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET2025 ~wire 0 204 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET2036 ~wire 0 205 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET2047 ~wire 0 206 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET2064 ~wire 0 207 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET2078 ~wire 0 208 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET2311 ~wire 0 209 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET2482 ~wire 0 210 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET2493 ~wire 0 211 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET2501 ~wire 0 212 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET2512 ~wire 0 213 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET2528 ~wire 0 214 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET2539 ~wire 0 215 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET2575 ~wire 0 216 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET3248 ~wire 0 217 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET3253 ~wire 0 218 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET3919 ~wire 0 219 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal NET3926 ~wire 0 220 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal NET4248 ~wire 0 221 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal NET615 ~wire 0 222 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal NET621 ~wire 0 223 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal NET629 ~wire 0 224 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal BUS1564 ~[7:0]wire~ 0 225 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal inDATA ~[7:0]wire~ 0 226 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal outDATA ~[7:0]wire~ 0 227 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_subprogram
			

		)
		(_type (_external ~wire (vl verilog_logic wire)))
		(_type (_external ~reg (vl verilog_logic reg)))
		(_type (_external ~event (vl verilog_logic event)))
		(_type (_external ~wand (vl verilog_logic wand)))
		(_type (_external ~wor (vl verilog_logic wor)))
		(_type (_external ~tri1 (vl verilog_logic tri1)))
		(_type (_external ~tri0 (vl verilog_logic tri0)))
		(_type (_external ~trireg (vl verilog_logic trireg)))
		(_type (_external ~supply0 (vl verilog_logic supply0)))
		(_type (_external ~supply1 (vl verilog_logic supply1)))
		(_type (_external ~real (vl verilog_logic real)))
		(_type (_external ~realtime (vl verilog_logic realtime)))
		(_type (_external ~tri (vl verilog_logic tri)))
		(_type (_external ~triand (vl verilog_logic triand)))
		(_type (_external ~trior (vl verilog_logic trior)))
		(_type (_external ~bit (vl verilog_logic bit)))
		(_type (_external ~extstd.standard.integer (std standard integer)))
		(_type (_external ~extstd.standard.bit (std standard bit)))
		(_process
			(#ASSIGN#457_0 (_architecture 0 0 457 (_process (_alias ((NET3919)(SCLreset)))(_simple)
				(_target(102))
				(_sensitivity(35))
			)))
			(#ASSIGN#458_1 (_architecture 1 0 458 (_process (_alias ((NET3926)(SCLinc)))(_simple)
				(_target(103))
				(_sensitivity(34))
			)))
			(#ASSIGN#459_2 (_architecture 2 0 459 (_process (_alias ((NET615)(MHSO)))(_simple)
				(_target(105))
				(_sensitivity(22))
			)))
			(#ASSIGN#460_3 (_architecture 3 0 460 (_process (_alias ((NET621)(HSI)))(_simple)
				(_target(106))
				(_sensitivity(13))
			)))
			(#ASSIGN#461_4 (_architecture 4 0 461 (_process (_alias ((NET629)(TXI)))(_simple)
				(_target(107))
				(_sensitivity(36))
			)))
			(#ASSIGN#464_5 (_architecture 5 0 464 (_process (_alias ((HSO)(NET615)))(_simple)
				(_target(45))
				(_sensitivity(105))
			)))
			(#ASSIGN#465_6 (_architecture 6 0 465 (_process (_alias ((MHSI)(NET621)))(_simple)
				(_target(56))
				(_sensitivity(106))
			)))
			(#ASSIGN#466_7 (_architecture 7 0 466 (_process (_alias ((MTXI)(NET629)))(_simple)
				(_target(59))
				(_sensitivity(107))
			)))
			(#ASSIGN#467_8 (_architecture 8 0 467 (_process (_alias ((TP10)(NET3919)))(_simple)
				(_target(68))
				(_sensitivity(102))
			)))
			(#ASSIGN#468_9 (_architecture 9 0 468 (_process (_alias ((TP11)(NET3926)))(_simple)
				(_target(69))
				(_sensitivity(103))
			)))
			(#ASSIGN#469_10 (_architecture 10 0 469 (_process (_alias ((TP12)(NET4248)))(_simple)
				(_target(70))
				(_sensitivity(104))
			)))
			(#ASSIGN#472_11 (_architecture 11 0 472 (_process (_alias ((NET4248)(SCL)))(_simple)
				(_target(104))
				(_sensitivity(71))
			)))
			(#ASSIGN#473_12 (_architecture 12 0 473 (_process (_alias ((SCL)(NET4248)))(_simple)
				(_target(71))
				(_sensitivity(104))
			)))
		)
	)
	
	
	(_defparam
	)
	(_scope
	)
	(_instantiation U1 0 231 (_entity .  Servos)
		(_port
			((DCOR0CNTHIGHr) (NET1667))
			((DCOR0CNTLOWr) (NET1651))
			((DCOR0CNTMIDr) (NET1659))
			((DCOR0THRESLOWr) (NET1635))
			((DCOR0THRESMIDr) (NET1643))
			((DCOR1CNTHIGHr) (NET1675))
			((DCOR1CNTLOWr) (NET1683))
			((DCOR1CNTMIDr) (NET1691))
			((DCOR1THRESLOWr) (NET1707))
			((DCOR1THRESMIDr) (NET1699))
			((DCORENCCTLw) (NET1970))
			((DCORIFGr) (NET1978))
			((DCORIFGw) (NET1989))
			((Hfound0) (NET2482))
			((Hfound1) (NET2493))
			((Home_Encoder0) (Home0))
			((Home_Encoder1) (Home1))
			((Mclk) (Mclk))
			((MotorIn0) (GP_Motor0_0))
			((Motorin1) (GP_Motor1_0))
			((PhaseA_Encoder0) (PhaseA_Encoder0))
			((PhaseA_Encoder1) (PhaseA_Encoder1))
			((PhaseB_Encoder0) (PhaseB_Encoder0))
			((PhaseB_Encoder1) (PhaseB_Encoder1))
			((Reset) (Reset))
			((Tfound0) (NET2501))
			((Tfound1) (NET2512))
			((inDATA) (inDATA))
			((outDATA) (outDATA))
		)
		(_strength strong0 strong1)
	)
	(_instantiation U11 0 266 (_entity .  I2Cfix)
		(_port
			((DCORI2CCNTr) (NET2311))
			((Inc) (NET3926))
			((Mclk) (Mclk))
			((SCL) (NET4248))
			((SCLint) (NET2539))
			((SCLreset) (NET3919))
			((outDATA) (outDATA))
			((SCLenable) (_open))
		)
		(_strength strong0 strong1)
	)
	(_instantiation U12 0 279 (_entity .  U21AddDecode)
		(_port
			((ADDR) (BUS1564))
			((AS) (AS))
			((DCOR0CNTHIGHr) (NET1667))
			((DCOR0CNTLOWr) (NET1651))
			((DCOR0CNTMIDr) (NET1659))
			((DCOR0THRESLOWr) (NET1635))
			((DCOR0THRESMIDr) (NET1643))
			((DCOR1CNTHIGHr) (NET1675))
			((DCOR1CNTLOWr) (NET1683))
			((DCOR1CNTMIDr) (NET1691))
			((DCOR1THRESLOWr) (NET1707))
			((DCOR1THRESMIDr) (NET1699))
			((DCORCONFIGr) (NET2064))
			((DCORENCCTLw) (NET1970))
			((DCORENCPWRr) (NET2036))
			((DCORENCPWRw) (NET2025))
			((DCORI2CCNTr) (NET2311))
			((DCORIEw) (NET2078))
			((DCORIFGr) (NET1978))
			((DCORIFGw) (NET1989))
			((DCORLIMITSr) (NET2047))
			((DCOROUTw) (NET2017))
			((RD) (RD))
			((WR) (WR))
		)
		(_strength strong0 strong1)
	)
	(_instantiation U2 0 309 (_entity .  Interface)
		(_port
			((AD) (AD))
			((ADDR) (BUS1564))
			((AS) (AS))
			((Mclk) (Mclk))
			((RD) (RD))
			((Reset) (Reset))
			((WR) (WR))
			((inDATA) (inDATA))
			((outDATA) (outDATA))
		)
		(_strength strong0 strong1)
	)
	(_instantiation U3 0 324 (_entity .  Interrupt)
		(_port
			((BusInt) (INTbus))
			((DCORIEw) (NET2078))
			((Homed0) (NET2482))
			((Homed1) (NET2493))
			((I2Cint) (NET2539))
			((INT) (INT))
			((LSwitchInt) (NET2575))
			((Mclk) (Mclk))
			((PWRint) (NET2528))
			((Reset) (Reset))
			((Thres0) (NET2501))
			((Thres1) (NET2512))
			((inDATA) (inDATA))
		)
		(_strength strong0 strong1)
	)
	(_instantiation U4 0 343 (_entity .  PWRreg)
		(_port
			((DCORENCPWRr) (NET2036))
			((DCORENCPWRw) (NET2025))
			((DCORIFGr) (NET1978))
			((DCORIFGw) (NET1989))
			((Enc033ctl) (Home15ctrl))
			((Enc033flg) (Enc033FLG))
			((Enc05ctl) (Home133ctrl))
			((Enc05flg) (Enc05FLG))
			((Enc133ctl) (Home05ctrl))
			((Enc133flg) (Enc133FLG))
			((Enc15ctl) (Home033ctrl))
			((Enc15flg) (Enc15FLG))
			((Hme033ctl) (Enc15ctrl))
			((Hme033flg) (Home033FLG))
			((Hme05ctl) (Enc133ctrl))
			((Hme05flg) (Home05FLG))
			((Hme133ctl) (Enc05ctrl))
			((Hme133flg) (Home133FLG))
			((Hme15ctl) (Enc033ctrl))
			((Hme15flg) (Home15FLG))
			((Mclk) (Mclk))
			((PWRint) (NET2528))
			((Reset) (Reset))
			((inDATA) (inDATA))
			((outDATA) (outDATA))
		)
		(_strength strong0 strong1)
	)
	(_instantiation U5 0 374 (_entity .  Lswitch)
		(_port
			((Brake0) (Brake0))
			((Brake1) (Brake1))
			((DCORIFGr) (NET1978))
			((DCORIFGw) (NET1989))
			((DCORLIMITSr) (NET2047))
			((DIR0) (DIR0))
			((DIR1) (DIR1))
			((FLS0) (FLS0))
			((FLS1) (FLS1))
			((Home0) (Home0))
			((Home1) (Home1))
			((LSwitchInt) (NET2575))
			((Mclk) (Mclk))
			((RLS0) (RLS0))
			((RLS1) (RLS1))
			((Reset) (Reset))
			((fBRK0) (NET3248))
			((fBRK1) (NET3253))
			((inDATA) (inDATA))
			((outDATA) (outDATA))
		)
		(_strength strong0 strong1)
	)
	(_instantiation U6 0 400 (_entity .  I2CAddress)
		(_port
			((DCORCONFIGr) (NET2064))
			((I2CS) (I2CS))
			((MotorIn0) (GP_Motor0_0))
			((MotorIn1) (GP_Motor1_0))
			((outDATA) (outDATA))
		)
		(_strength strong0 strong1)
	)
	(_instantiation U7 0 411 (_entity .  PWMcontrol)
		(_port
			((Brake1) (Brake0))
			((Brake2) (Brake1))
			((DIR1) (DIR0))
			((DIR2) (DIR1))
			((HBRK1) (NET3248))
			((HBRK2) (NET3253))
			((PAH1) (PAH0))
			((PAH2) (PBL1))
			((PAL1) (PAL0))
			((PAL2) (PBH1))
			((PBH1) (PBH0))
			((PBH2) (PAL1))
			((PBL1) (PBL0))
			((PBL2) (PAH1))
			((PWM1) (PWM1))
			((PWM2) (PWM2))
			((fBRK1) (NET3248))
			((fBRK2) (NET3253))
		)
		(_strength strong0 strong1)
	)
	(_instantiation U9 0 435 (_entity .  MISCouts)
		(_port
			((DCOROUTw) (NET2017))
			((GP_Motor0_1) (GP_Motor0_1))
			((GP_Motor1_1) (GP_Motor1_1))
			((LED1) (LED1))
			((LED2) (LED2))
			((LED3) (LED3))
			((LED4) (LED4))
			((LED5) (LED5))
			((LightSense) (LightSense))
			((MTRpwr) (MTRpwr))
			((MTRpwrn) (MTRpwrn))
			((Mclk) (Mclk))
			((Reset) (Reset))
			((inDATA) (inDATA))
		)
		(_strength strong0 strong1)
	)
	(_model . U21 14 -1)

)
V 000044 55 25525         1078861311951 U21
(_unit VERILOG 6.349C.6.256 (U21 0 32 (U21 0 32 ))
	(_version v32)
	(_time 1078861311873 2004.03.09 11:41:51)
	(_source (\./compile/u21.v\ VERILOG (\./compile/u21.v\ VERILOG)))
	(_use (std(standard))(vl(verilog_logic)))
	(_base (E 14))
	(_entity
		(_time 1078861311873)
		(_use )
	)
	(_timescale 1ns 1ns)
	(_parameters    dbg   accs  )
	(_attribute )
	(_object
		(_port (_internal AS ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Brake0 ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Brake1 ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal DIR0 ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal DIR1 ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Enc033FLG ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Enc05FLG ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Enc133FLG ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Enc15FLG ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal FLS0 ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal FLS1 ~wire 0 33 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal GP_Motor0_0 ~wire 0 33 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal GP_Motor1_0 ~wire 0 33 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal HSI ~wire 0 33 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal Home0 ~wire 0 33 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Home033FLG ~wire 0 33 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Home05FLG ~wire 0 33 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Home1 ~wire 0 33 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Home133FLG ~wire 0 33 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Home15FLG ~wire 0 33 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal INTbus ~wire 0 34 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal LightSense ~wire 0 34 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal MHSO ~wire 0 34 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal Mclk ~wire 0 34 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PWM1 ~wire 0 34 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PWM2 ~wire 0 34 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PhaseA_Encoder0 ~wire 0 34 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PhaseA_Encoder1 ~wire 0 34 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PhaseB_Encoder0 ~wire 0 34 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PhaseB_Encoder1 ~wire 0 34 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal RD ~wire 0 35 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal RLS0 ~wire 0 35 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal RLS1 ~wire 0 35 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Reset ~wire 0 35 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal SCLinc ~wire 0 35 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal SCLreset ~wire 0 35 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal TXI ~wire 0 35 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal WR ~wire 0 35 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_type (_internal ~[5:0]wire~ 0 35 (_array ~wire ((_downto (i 5) (i 0))))))
		(_port (_internal I2CS ~[5:0]wire~ 0 35 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Enc033ctrl ~wire 0 35 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Enc05ctrl ~wire 0 36 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Enc133ctrl ~wire 0 36 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Enc15ctrl ~wire 0 36 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal GP_Motor0_1 ~wire 0 36 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal GP_Motor1_1 ~wire 0 36 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal HSO ~wire 0 36 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal Home033ctrl ~wire 0 36 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Home05ctrl ~wire 0 36 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Home133ctrl ~wire 0 36 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Home15ctrl ~wire 0 36 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal INT ~wire 0 37 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal LED1 ~wire 0 37 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal LED2 ~wire 0 37 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal LED3 ~wire 0 37 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal LED4 ~wire 0 37 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal LED5 ~wire 0 37 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal MHSI ~wire 0 37 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal MTRpwr ~wire 0 37 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal MTRpwrn ~wire 0 37 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal MTXI ~wire 0 37 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal PAH0 ~wire 0 38 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PAH1 ~wire 0 38 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PAL0 ~wire 0 38 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PAL1 ~wire 0 38 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PBH0 ~wire 0 38 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PBH1 ~wire 0 38 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PBL0 ~wire 0 38 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PBL1 ~wire 0 38 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal TP10 ~wire 0 38 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal TP11 ~wire 0 38 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal TP12 ~wire 0 39 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal SCL ~wire 0 39 (_architecture (_inout ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_type (_internal ~[7:0]wire~ 0 39 (_array ~wire ((_downto (i 7) (i 0))))))
		(_port (_internal AD ~[7:0]wire~ 0 39 (_architecture (_inout ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET1635 ~wire 0 190 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET1643 ~wire 0 191 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET1651 ~wire 0 192 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET1659 ~wire 0 193 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET1667 ~wire 0 194 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET1675 ~wire 0 195 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET1683 ~wire 0 196 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET1691 ~wire 0 197 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET1699 ~wire 0 198 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET1707 ~wire 0 199 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET1970 ~wire 0 200 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET1978 ~wire 0 201 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET1989 ~wire 0 202 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET2017 ~wire 0 203 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET2025 ~wire 0 204 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET2036 ~wire 0 205 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET2047 ~wire 0 206 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET2064 ~wire 0 207 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET2078 ~wire 0 208 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET2311 ~wire 0 209 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET2482 ~wire 0 210 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET2493 ~wire 0 211 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET2501 ~wire 0 212 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET2512 ~wire 0 213 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET2528 ~wire 0 214 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET2539 ~wire 0 215 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET2575 ~wire 0 216 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET3248 ~wire 0 217 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET3253 ~wire 0 218 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET3919 ~wire 0 219 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal NET3926 ~wire 0 220 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal NET4248 ~wire 0 221 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal NET615 ~wire 0 222 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal NET621 ~wire 0 223 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal NET629 ~wire 0 224 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal BUS1564 ~[7:0]wire~ 0 225 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal inDATA ~[7:0]wire~ 0 226 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal outDATA ~[7:0]wire~ 0 227 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_subprogram
			

		)
		(_type (_external ~wire (vl verilog_logic wire)))
		(_type (_external ~reg (vl verilog_logic reg)))
		(_type (_external ~event (vl verilog_logic event)))
		(_type (_external ~wand (vl verilog_logic wand)))
		(_type (_external ~wor (vl verilog_logic wor)))
		(_type (_external ~tri1 (vl verilog_logic tri1)))
		(_type (_external ~tri0 (vl verilog_logic tri0)))
		(_type (_external ~trireg (vl verilog_logic trireg)))
		(_type (_external ~supply0 (vl verilog_logic supply0)))
		(_type (_external ~supply1 (vl verilog_logic supply1)))
		(_type (_external ~real (vl verilog_logic real)))
		(_type (_external ~realtime (vl verilog_logic realtime)))
		(_type (_external ~tri (vl verilog_logic tri)))
		(_type (_external ~triand (vl verilog_logic triand)))
		(_type (_external ~trior (vl verilog_logic trior)))
		(_type (_external ~bit (vl verilog_logic bit)))
		(_type (_external ~extstd.standard.integer (std standard integer)))
		(_type (_external ~extstd.standard.bit (std standard bit)))
		(_process
			(#ASSIGN#457_0 (_architecture 0 0 457 (_process (_alias ((NET3919)(SCLreset)))(_simple)
				(_target(102))
				(_sensitivity(35))
			)))
			(#ASSIGN#458_1 (_architecture 1 0 458 (_process (_alias ((NET3926)(SCLinc)))(_simple)
				(_target(103))
				(_sensitivity(34))
			)))
			(#ASSIGN#459_2 (_architecture 2 0 459 (_process (_alias ((NET615)(MHSO)))(_simple)
				(_target(105))
				(_sensitivity(22))
			)))
			(#ASSIGN#460_3 (_architecture 3 0 460 (_process (_alias ((NET621)(HSI)))(_simple)
				(_target(106))
				(_sensitivity(13))
			)))
			(#ASSIGN#461_4 (_architecture 4 0 461 (_process (_alias ((NET629)(TXI)))(_simple)
				(_target(107))
				(_sensitivity(36))
			)))
			(#ASSIGN#464_5 (_architecture 5 0 464 (_process (_alias ((HSO)(NET615)))(_simple)
				(_target(45))
				(_sensitivity(105))
			)))
			(#ASSIGN#465_6 (_architecture 6 0 465 (_process (_alias ((MHSI)(NET621)))(_simple)
				(_target(56))
				(_sensitivity(106))
			)))
			(#ASSIGN#466_7 (_architecture 7 0 466 (_process (_alias ((MTXI)(NET629)))(_simple)
				(_target(59))
				(_sensitivity(107))
			)))
			(#ASSIGN#467_8 (_architecture 8 0 467 (_process (_alias ((TP10)(NET3919)))(_simple)
				(_target(68))
				(_sensitivity(102))
			)))
			(#ASSIGN#468_9 (_architecture 9 0 468 (_process (_alias ((TP11)(NET3926)))(_simple)
				(_target(69))
				(_sensitivity(103))
			)))
			(#ASSIGN#469_10 (_architecture 10 0 469 (_process (_alias ((TP12)(NET4248)))(_simple)
				(_target(70))
				(_sensitivity(104))
			)))
			(#ASSIGN#472_11 (_architecture 11 0 472 (_process (_alias ((NET4248)(SCL)))(_simple)
				(_target(104))
				(_sensitivity(71))
			)))
			(#ASSIGN#473_12 (_architecture 12 0 473 (_process (_alias ((SCL)(NET4248)))(_simple)
				(_target(71))
				(_sensitivity(104))
			)))
		)
	)
	
	
	(_defparam
	)
	(_scope
	)
	(_instantiation U1 0 231 (_entity .  Servos)
		(_port
			((DCOR0CNTHIGHr) (NET1667))
			((DCOR0CNTLOWr) (NET1651))
			((DCOR0CNTMIDr) (NET1659))
			((DCOR0THRESLOWr) (NET1635))
			((DCOR0THRESMIDr) (NET1643))
			((DCOR1CNTHIGHr) (NET1675))
			((DCOR1CNTLOWr) (NET1683))
			((DCOR1CNTMIDr) (NET1691))
			((DCOR1THRESLOWr) (NET1707))
			((DCOR1THRESMIDr) (NET1699))
			((DCORENCCTLw) (NET1970))
			((DCORIFGr) (NET1978))
			((DCORIFGw) (NET1989))
			((Hfound0) (NET2482))
			((Hfound1) (NET2493))
			((Home_Encoder0) (Home0))
			((Home_Encoder1) (Home1))
			((Mclk) (Mclk))
			((MotorIn0) (GP_Motor0_0))
			((Motorin1) (GP_Motor1_0))
			((PhaseA_Encoder0) (PhaseA_Encoder0))
			((PhaseA_Encoder1) (PhaseA_Encoder1))
			((PhaseB_Encoder0) (PhaseB_Encoder0))
			((PhaseB_Encoder1) (PhaseB_Encoder1))
			((Reset) (Reset))
			((Tfound0) (NET2501))
			((Tfound1) (NET2512))
			((inDATA) (inDATA))
			((outDATA) (outDATA))
		)
		(_strength strong0 strong1)
	)
	(_instantiation U11 0 266 (_entity .  I2Cfix)
		(_port
			((DCORI2CCNTr) (NET2311))
			((Inc) (NET3926))
			((Mclk) (Mclk))
			((SCL) (NET4248))
			((SCLint) (NET2539))
			((SCLreset) (NET3919))
			((outDATA) (outDATA))
			((SCLenable) (_open))
		)
		(_strength strong0 strong1)
	)
	(_instantiation U12 0 279 (_entity .  U21AddDecode)
		(_port
			((ADDR) (BUS1564))
			((AS) (AS))
			((DCOR0CNTHIGHr) (NET1667))
			((DCOR0CNTLOWr) (NET1651))
			((DCOR0CNTMIDr) (NET1659))
			((DCOR0THRESLOWr) (NET1635))
			((DCOR0THRESMIDr) (NET1643))
			((DCOR1CNTHIGHr) (NET1675))
			((DCOR1CNTLOWr) (NET1683))
			((DCOR1CNTMIDr) (NET1691))
			((DCOR1THRESLOWr) (NET1707))
			((DCOR1THRESMIDr) (NET1699))
			((DCORCONFIGr) (NET2064))
			((DCORENCCTLw) (NET1970))
			((DCORENCPWRr) (NET2036))
			((DCORENCPWRw) (NET2025))
			((DCORI2CCNTr) (NET2311))
			((DCORIEw) (NET2078))
			((DCORIFGr) (NET1978))
			((DCORIFGw) (NET1989))
			((DCORLIMITSr) (NET2047))
			((DCOROUTw) (NET2017))
			((RD) (RD))
			((WR) (WR))
		)
		(_strength strong0 strong1)
	)
	(_instantiation U2 0 309 (_entity .  Interface)
		(_port
			((AD) (AD))
			((ADDR) (BUS1564))
			((AS) (AS))
			((Mclk) (Mclk))
			((RD) (RD))
			((Reset) (Reset))
			((WR) (WR))
			((inDATA) (inDATA))
			((outDATA) (outDATA))
		)
		(_strength strong0 strong1)
	)
	(_instantiation U3 0 324 (_entity .  Interrupt)
		(_port
			((BusInt) (INTbus))
			((DCORIEw) (NET2078))
			((Homed0) (NET2482))
			((Homed1) (NET2493))
			((I2Cint) (NET2539))
			((INT) (INT))
			((LSwitchInt) (NET2575))
			((Mclk) (Mclk))
			((PWRint) (NET2528))
			((Reset) (Reset))
			((Thres0) (NET2501))
			((Thres1) (NET2512))
			((inDATA) (inDATA))
		)
		(_strength strong0 strong1)
	)
	(_instantiation U4 0 343 (_entity .  PWRreg)
		(_port
			((DCORENCPWRr) (NET2036))
			((DCORENCPWRw) (NET2025))
			((DCORIFGr) (NET1978))
			((DCORIFGw) (NET1989))
			((Enc033ctl) (Home15ctrl))
			((Enc033flg) (Enc033FLG))
			((Enc05ctl) (Home133ctrl))
			((Enc05flg) (Enc05FLG))
			((Enc133ctl) (Home05ctrl))
			((Enc133flg) (Enc133FLG))
			((Enc15ctl) (Home033ctrl))
			((Enc15flg) (Enc15FLG))
			((Hme033ctl) (Enc15ctrl))
			((Hme033flg) (Home033FLG))
			((Hme05ctl) (Enc133ctrl))
			((Hme05flg) (Home05FLG))
			((Hme133ctl) (Enc05ctrl))
			((Hme133flg) (Home133FLG))
			((Hme15ctl) (Enc033ctrl))
			((Hme15flg) (Home15FLG))
			((Mclk) (Mclk))
			((PWRint) (NET2528))
			((Reset) (Reset))
			((inDATA) (inDATA))
			((outDATA) (outDATA))
		)
		(_strength strong0 strong1)
	)
	(_instantiation U5 0 374 (_entity .  Lswitch)
		(_port
			((Brake0) (Brake0))
			((Brake1) (Brake1))
			((DCORIFGr) (NET1978))
			((DCORIFGw) (NET1989))
			((DCORLIMITSr) (NET2047))
			((DIR0) (DIR0))
			((DIR1) (DIR1))
			((FLS0) (FLS0))
			((FLS1) (FLS1))
			((Home0) (Home0))
			((Home1) (Home1))
			((LSwitchInt) (NET2575))
			((Mclk) (Mclk))
			((RLS0) (RLS0))
			((RLS1) (RLS1))
			((Reset) (Reset))
			((fBRK0) (NET3248))
			((fBRK1) (NET3253))
			((inDATA) (inDATA))
			((outDATA) (outDATA))
		)
		(_strength strong0 strong1)
	)
	(_instantiation U6 0 400 (_entity .  I2CAddress)
		(_port
			((DCORCONFIGr) (NET2064))
			((I2CS) (I2CS))
			((MotorIn0) (GP_Motor0_0))
			((MotorIn1) (GP_Motor1_0))
			((outDATA) (outDATA))
		)
		(_strength strong0 strong1)
	)
	(_instantiation U7 0 411 (_entity .  PWMcontrol)
		(_port
			((Brake1) (Brake0))
			((Brake2) (Brake1))
			((DIR1) (DIR0))
			((DIR2) (DIR1))
			((HBRK1) (NET3248))
			((HBRK2) (NET3253))
			((PAH1) (PAH0))
			((PAH2) (PBL1))
			((PAL1) (PAL0))
			((PAL2) (PBH1))
			((PBH1) (PBH0))
			((PBH2) (PAL1))
			((PBL1) (PBL0))
			((PBL2) (PAH1))
			((PWM1) (PWM1))
			((PWM2) (PWM2))
			((fBRK1) (NET3248))
			((fBRK2) (NET3253))
		)
		(_strength strong0 strong1)
	)
	(_instantiation U9 0 435 (_entity .  MISCouts)
		(_port
			((DCOROUTw) (NET2017))
			((GP_Motor0_1) (GP_Motor0_1))
			((GP_Motor1_1) (GP_Motor1_1))
			((LED1) (LED1))
			((LED2) (LED2))
			((LED3) (LED3))
			((LED4) (LED4))
			((LED5) (LED5))
			((LightSense) (LightSense))
			((MTRpwr) (MTRpwr))
			((MTRpwrn) (MTRpwrn))
			((Mclk) (Mclk))
			((Reset) (Reset))
			((inDATA) (inDATA))
		)
		(_strength strong0 strong1)
	)
	(_model . U21 14 -1)

)
V 000044 55 25098         1078861416452 U21
(_unit VERILOG 6.349C.6.256 (U21 0 32 (U21 0 32 ))
	(_version v32)
	(_time 1078861416373 2004.03.09 11:43:36)
	(_source (\./compile/u21.v\ VERILOG (\./compile/u21.v\ VERILOG)))
	(_use (std(standard))(vl(verilog_logic)))
	(_base (E 12))
	(_entity
		(_time 1078861416373)
		(_use )
	)
	(_timescale 1ns 1ns)
	(_parameters    dbg   accs  )
	(_attribute )
	(_object
		(_port (_internal AS ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Brake0 ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Brake1 ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal DIR0 ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal DIR1 ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Enc033FLG ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Enc05FLG ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Enc133FLG ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Enc15FLG ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal FLS0 ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal FLS1 ~wire 0 33 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal GP_Motor0_0 ~wire 0 33 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal GP_Motor1_0 ~wire 0 33 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal HSI ~wire 0 33 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal Home0 ~wire 0 33 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Home033FLG ~wire 0 33 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Home05FLG ~wire 0 33 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Home1 ~wire 0 33 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Home133FLG ~wire 0 33 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Home15FLG ~wire 0 33 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal INTbus ~wire 0 34 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal LightSense ~wire 0 34 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal MHSO ~wire 0 34 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal Mclk ~wire 0 34 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PWM1 ~wire 0 34 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PWM2 ~wire 0 34 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PhaseA_Encoder0 ~wire 0 34 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PhaseA_Encoder1 ~wire 0 34 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PhaseB_Encoder0 ~wire 0 34 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PhaseB_Encoder1 ~wire 0 34 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal RD ~wire 0 35 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal RLS0 ~wire 0 35 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal RLS1 ~wire 0 35 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Reset ~wire 0 35 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal SCLinc ~wire 0 35 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal SCLreset ~wire 0 35 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal TXI ~wire 0 35 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal WR ~wire 0 35 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_type (_internal ~[5:0]wire~ 0 35 (_array ~wire ((_downto (i 5) (i 0))))))
		(_port (_internal I2CS ~[5:0]wire~ 0 35 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Enc033ctrl ~wire 0 35 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Enc05ctrl ~wire 0 36 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Enc133ctrl ~wire 0 36 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Enc15ctrl ~wire 0 36 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal GP_Motor0_1 ~wire 0 36 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal GP_Motor1_1 ~wire 0 36 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal HSO ~wire 0 36 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal Home033ctrl ~wire 0 36 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Home05ctrl ~wire 0 36 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Home133ctrl ~wire 0 36 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Home15ctrl ~wire 0 36 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal INT ~wire 0 37 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal LED1 ~wire 0 37 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal LED2 ~wire 0 37 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal LED3 ~wire 0 37 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal LED4 ~wire 0 37 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal LED5 ~wire 0 37 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal MHSI ~wire 0 37 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal MTRpwr ~wire 0 37 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal MTRpwrn ~wire 0 37 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal MTXI ~wire 0 37 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal PAH0 ~wire 0 38 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PAH1 ~wire 0 38 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PAL0 ~wire 0 38 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PAL1 ~wire 0 38 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PBH0 ~wire 0 38 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PBH1 ~wire 0 38 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PBL0 ~wire 0 38 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PBL1 ~wire 0 38 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal TP10 ~wire 0 38 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal TP11 ~wire 0 38 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal TP12 ~wire 0 39 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal SCL ~wire 0 39 (_architecture (_inout ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_type (_internal ~[7:0]wire~ 0 39 (_array ~wire ((_downto (i 7) (i 0))))))
		(_port (_internal AD ~[7:0]wire~ 0 39 (_architecture (_inout ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET1635 ~wire 0 190 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET1643 ~wire 0 191 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET1651 ~wire 0 192 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET1659 ~wire 0 193 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET1667 ~wire 0 194 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET1675 ~wire 0 195 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET1683 ~wire 0 196 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET1691 ~wire 0 197 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET1699 ~wire 0 198 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET1707 ~wire 0 199 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET1970 ~wire 0 200 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET1978 ~wire 0 201 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET1989 ~wire 0 202 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET2017 ~wire 0 203 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET2025 ~wire 0 204 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET2036 ~wire 0 205 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET2047 ~wire 0 206 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET2064 ~wire 0 207 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET2078 ~wire 0 208 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET2311 ~wire 0 209 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET2482 ~wire 0 210 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET2493 ~wire 0 211 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET2501 ~wire 0 212 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET2512 ~wire 0 213 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET2528 ~wire 0 214 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET2539 ~wire 0 215 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET2575 ~wire 0 216 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET3248 ~wire 0 217 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET3253 ~wire 0 218 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET3919 ~wire 0 219 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal NET3926 ~wire 0 220 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal NET615 ~wire 0 221 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal NET621 ~wire 0 222 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal NET629 ~wire 0 223 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal BUS1564 ~[7:0]wire~ 0 224 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal inDATA ~[7:0]wire~ 0 225 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal outDATA ~[7:0]wire~ 0 226 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_subprogram
			

		)
		(_type (_external ~wire (vl verilog_logic wire)))
		(_type (_external ~reg (vl verilog_logic reg)))
		(_type (_external ~event (vl verilog_logic event)))
		(_type (_external ~wand (vl verilog_logic wand)))
		(_type (_external ~wor (vl verilog_logic wor)))
		(_type (_external ~tri1 (vl verilog_logic tri1)))
		(_type (_external ~tri0 (vl verilog_logic tri0)))
		(_type (_external ~trireg (vl verilog_logic trireg)))
		(_type (_external ~supply0 (vl verilog_logic supply0)))
		(_type (_external ~supply1 (vl verilog_logic supply1)))
		(_type (_external ~real (vl verilog_logic real)))
		(_type (_external ~realtime (vl verilog_logic realtime)))
		(_type (_external ~tri (vl verilog_logic tri)))
		(_type (_external ~triand (vl verilog_logic triand)))
		(_type (_external ~trior (vl verilog_logic trior)))
		(_type (_external ~bit (vl verilog_logic bit)))
		(_type (_external ~extstd.standard.integer (std standard integer)))
		(_type (_external ~extstd.standard.bit (std standard bit)))
		(_process
			(#ASSIGN#456_0 (_architecture 0 0 456 (_process (_alias ((NET3919)(SCLreset)))(_simple)
				(_target(102))
				(_sensitivity(35))
			)))
			(#ASSIGN#457_1 (_architecture 1 0 457 (_process (_alias ((NET3926)(SCLinc)))(_simple)
				(_target(103))
				(_sensitivity(34))
			)))
			(#ASSIGN#458_2 (_architecture 2 0 458 (_process (_alias ((NET615)(MHSO)))(_simple)
				(_target(104))
				(_sensitivity(22))
			)))
			(#ASSIGN#459_3 (_architecture 3 0 459 (_process (_alias ((NET621)(HSI)))(_simple)
				(_target(105))
				(_sensitivity(13))
			)))
			(#ASSIGN#460_4 (_architecture 4 0 460 (_process (_alias ((NET629)(TXI)))(_simple)
				(_target(106))
				(_sensitivity(36))
			)))
			(#ASSIGN#463_5 (_architecture 5 0 463 (_process (_alias ((HSO)(NET615)))(_simple)
				(_target(45))
				(_sensitivity(104))
			)))
			(#ASSIGN#464_6 (_architecture 6 0 464 (_process (_alias ((MHSI)(NET621)))(_simple)
				(_target(56))
				(_sensitivity(105))
			)))
			(#ASSIGN#465_7 (_architecture 7 0 465 (_process (_alias ((MTXI)(NET629)))(_simple)
				(_target(59))
				(_sensitivity(106))
			)))
			(#ASSIGN#466_8 (_architecture 8 0 466 (_process (_alias ((TP10)(NET3919)))(_simple)
				(_target(68))
				(_sensitivity(102))
			)))
			(#ASSIGN#467_9 (_architecture 9 0 467 (_process (_alias ((TP11)(NET3926)))(_simple)
				(_target(69))
				(_sensitivity(103))
			)))
			(#ASSIGN#468_10 (_architecture 10 0 468 (_process (_alias ((TP12)(SCL)))(_simple)
				(_target(70))
				(_sensitivity(71))
			)))
		)
	)
	
	
	(_defparam
	)
	(_scope
	)
	(_instantiation U1 0 230 (_entity .  Servos)
		(_port
			((DCOR0CNTHIGHr) (NET1667))
			((DCOR0CNTLOWr) (NET1651))
			((DCOR0CNTMIDr) (NET1659))
			((DCOR0THRESLOWr) (NET1635))
			((DCOR0THRESMIDr) (NET1643))
			((DCOR1CNTHIGHr) (NET1675))
			((DCOR1CNTLOWr) (NET1683))
			((DCOR1CNTMIDr) (NET1691))
			((DCOR1THRESLOWr) (NET1707))
			((DCOR1THRESMIDr) (NET1699))
			((DCORENCCTLw) (NET1970))
			((DCORIFGr) (NET1978))
			((DCORIFGw) (NET1989))
			((Hfound0) (NET2482))
			((Hfound1) (NET2493))
			((Home_Encoder0) (Home0))
			((Home_Encoder1) (Home1))
			((Mclk) (Mclk))
			((MotorIn0) (GP_Motor0_0))
			((Motorin1) (GP_Motor1_0))
			((PhaseA_Encoder0) (PhaseA_Encoder0))
			((PhaseA_Encoder1) (PhaseA_Encoder1))
			((PhaseB_Encoder0) (PhaseB_Encoder0))
			((PhaseB_Encoder1) (PhaseB_Encoder1))
			((Reset) (Reset))
			((Tfound0) (NET2501))
			((Tfound1) (NET2512))
			((inDATA) (inDATA))
			((outDATA) (outDATA))
		)
		(_strength strong0 strong1)
	)
	(_instantiation U11 0 265 (_entity .  I2Cfix)
		(_port
			((DCORI2CCNTr) (NET2311))
			((Inc) (NET3926))
			((Mclk) (Mclk))
			((SCL) (SCL))
			((SCLint) (NET2539))
			((SCLreset) (NET3919))
			((outDATA) (outDATA))
			((SCLenable) (_open))
		)
		(_strength strong0 strong1)
	)
	(_instantiation U12 0 278 (_entity .  U21AddDecode)
		(_port
			((ADDR) (BUS1564))
			((AS) (AS))
			((DCOR0CNTHIGHr) (NET1667))
			((DCOR0CNTLOWr) (NET1651))
			((DCOR0CNTMIDr) (NET1659))
			((DCOR0THRESLOWr) (NET1635))
			((DCOR0THRESMIDr) (NET1643))
			((DCOR1CNTHIGHr) (NET1675))
			((DCOR1CNTLOWr) (NET1683))
			((DCOR1CNTMIDr) (NET1691))
			((DCOR1THRESLOWr) (NET1707))
			((DCOR1THRESMIDr) (NET1699))
			((DCORCONFIGr) (NET2064))
			((DCORENCCTLw) (NET1970))
			((DCORENCPWRr) (NET2036))
			((DCORENCPWRw) (NET2025))
			((DCORI2CCNTr) (NET2311))
			((DCORIEw) (NET2078))
			((DCORIFGr) (NET1978))
			((DCORIFGw) (NET1989))
			((DCORLIMITSr) (NET2047))
			((DCOROUTw) (NET2017))
			((RD) (RD))
			((WR) (WR))
		)
		(_strength strong0 strong1)
	)
	(_instantiation U2 0 308 (_entity .  Interface)
		(_port
			((AD) (AD))
			((ADDR) (BUS1564))
			((AS) (AS))
			((Mclk) (Mclk))
			((RD) (RD))
			((Reset) (Reset))
			((WR) (WR))
			((inDATA) (inDATA))
			((outDATA) (outDATA))
		)
		(_strength strong0 strong1)
	)
	(_instantiation U3 0 323 (_entity .  Interrupt)
		(_port
			((BusInt) (INTbus))
			((DCORIEw) (NET2078))
			((Homed0) (NET2482))
			((Homed1) (NET2493))
			((I2Cint) (NET2539))
			((INT) (INT))
			((LSwitchInt) (NET2575))
			((Mclk) (Mclk))
			((PWRint) (NET2528))
			((Reset) (Reset))
			((Thres0) (NET2501))
			((Thres1) (NET2512))
			((inDATA) (inDATA))
		)
		(_strength strong0 strong1)
	)
	(_instantiation U4 0 342 (_entity .  PWRreg)
		(_port
			((DCORENCPWRr) (NET2036))
			((DCORENCPWRw) (NET2025))
			((DCORIFGr) (NET1978))
			((DCORIFGw) (NET1989))
			((Enc033ctl) (Home15ctrl))
			((Enc033flg) (Enc033FLG))
			((Enc05ctl) (Home133ctrl))
			((Enc05flg) (Enc05FLG))
			((Enc133ctl) (Home05ctrl))
			((Enc133flg) (Enc133FLG))
			((Enc15ctl) (Home033ctrl))
			((Enc15flg) (Enc15FLG))
			((Hme033ctl) (Enc15ctrl))
			((Hme033flg) (Home033FLG))
			((Hme05ctl) (Enc133ctrl))
			((Hme05flg) (Home05FLG))
			((Hme133ctl) (Enc05ctrl))
			((Hme133flg) (Home133FLG))
			((Hme15ctl) (Enc033ctrl))
			((Hme15flg) (Home15FLG))
			((Mclk) (Mclk))
			((PWRint) (NET2528))
			((Reset) (Reset))
			((inDATA) (inDATA))
			((outDATA) (outDATA))
		)
		(_strength strong0 strong1)
	)
	(_instantiation U5 0 373 (_entity .  Lswitch)
		(_port
			((Brake0) (Brake0))
			((Brake1) (Brake1))
			((DCORIFGr) (NET1978))
			((DCORIFGw) (NET1989))
			((DCORLIMITSr) (NET2047))
			((DIR0) (DIR0))
			((DIR1) (DIR1))
			((FLS0) (FLS0))
			((FLS1) (FLS1))
			((Home0) (Home0))
			((Home1) (Home1))
			((LSwitchInt) (NET2575))
			((Mclk) (Mclk))
			((RLS0) (RLS0))
			((RLS1) (RLS1))
			((Reset) (Reset))
			((fBRK0) (NET3248))
			((fBRK1) (NET3253))
			((inDATA) (inDATA))
			((outDATA) (outDATA))
		)
		(_strength strong0 strong1)
	)
	(_instantiation U6 0 399 (_entity .  I2CAddress)
		(_port
			((DCORCONFIGr) (NET2064))
			((I2CS) (I2CS))
			((MotorIn0) (GP_Motor0_0))
			((MotorIn1) (GP_Motor1_0))
			((outDATA) (outDATA))
		)
		(_strength strong0 strong1)
	)
	(_instantiation U7 0 410 (_entity .  PWMcontrol)
		(_port
			((Brake1) (Brake0))
			((Brake2) (Brake1))
			((DIR1) (DIR0))
			((DIR2) (DIR1))
			((HBRK1) (NET3248))
			((HBRK2) (NET3253))
			((PAH1) (PAH0))
			((PAH2) (PBL1))
			((PAL1) (PAL0))
			((PAL2) (PBH1))
			((PBH1) (PBH0))
			((PBH2) (PAL1))
			((PBL1) (PBL0))
			((PBL2) (PAH1))
			((PWM1) (PWM1))
			((PWM2) (PWM2))
			((fBRK1) (NET3248))
			((fBRK2) (NET3253))
		)
		(_strength strong0 strong1)
	)
	(_instantiation U9 0 434 (_entity .  MISCouts)
		(_port
			((DCOROUTw) (NET2017))
			((GP_Motor0_1) (GP_Motor0_1))
			((GP_Motor1_1) (GP_Motor1_1))
			((LED1) (LED1))
			((LED2) (LED2))
			((LED3) (LED3))
			((LED4) (LED4))
			((LED5) (LED5))
			((LightSense) (LightSense))
			((MTRpwr) (MTRpwr))
			((MTRpwrn) (MTRpwrn))
			((Mclk) (Mclk))
			((Reset) (Reset))
			((inDATA) (inDATA))
		)
		(_strength strong0 strong1)
	)
	(_model . U21 12 -1)

)
I 000051 55 3596          1078871472248 BitCounter
(_unit VERILOG 6.349C.6.256 (BitCounter 0 25 (BitCounter 0 25 ))
	(_version v32)
	(_time 1078871472123 2004.03.09 14:31:12)
	(_source (\./src/bitcounter.v\ VERILOG (\./src/bitcounter.v\ VERILOG)))
	(_use (std(standard))(vl(verilog_logic)))
	(_base (E 6))
	(_entity
		(_time 1078871472123)
		(_use )
	)
	(_timescale 1ps 1ps)
	(_parameters    dbg   accs  )
	(_attribute nb_assign )
	(_object
		(_type (_internal ~[7:0]wire~ 0 25 (_array ~wire ((_downto (i 7) (i 0))))))
		(_port (_internal outDATA ~[7:0]wire~ 0 25 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal NegInc ~wire 0 25 (_architecture (_in ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal SCLreset ~wire 0 25 (_architecture (_in ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal Mclk ~wire 0 25 (_architecture (_in ))) (_net  ) (_nonbaction) (_noforceassign))
		(_port (_internal SCLenable ~wire 0 25 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal DriveSCL ~wire 0 25 (_architecture (_inout ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal NegSCL ~wire 0 25 (_architecture (_in ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal DCORI2CCNTr ~wire 0 25 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal SCLint ~wire 0 25 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_type (_internal ~[5:0]reg~ 0 52 (_array ~reg ((_downto (i 5) (i 0))))))
		(_signal (_internal counterr ~[5:0]reg~ 0 52 (_architecture (_uni ))) (_reg ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_subprogram
			

		)
		(_type (_external ~wire (vl verilog_logic wire)))
		(_type (_external ~reg (vl verilog_logic reg)))
		(_type (_external ~event (vl verilog_logic event)))
		(_type (_external ~wand (vl verilog_logic wand)))
		(_type (_external ~wor (vl verilog_logic wor)))
		(_type (_external ~tri1 (vl verilog_logic tri1)))
		(_type (_external ~tri0 (vl verilog_logic tri0)))
		(_type (_external ~trireg (vl verilog_logic trireg)))
		(_type (_external ~supply0 (vl verilog_logic supply0)))
		(_type (_external ~supply1 (vl verilog_logic supply1)))
		(_type (_external ~real (vl verilog_logic real)))
		(_type (_external ~realtime (vl verilog_logic realtime)))
		(_type (_external ~tri (vl verilog_logic tri)))
		(_type (_external ~triand (vl verilog_logic triand)))
		(_type (_external ~trior (vl verilog_logic trior)))
		(_type (_external ~bit (vl verilog_logic bit)))
		(_type (_external ~extstd.standard.integer (std standard integer)))
		(_type (_external ~extstd.standard.bit (std standard bit)))
		(_process
			(#ASSIGN#54_0 (_architecture 0 0 54 (_process (_simple)
				(_target(8))
				(_sensitivity(9))
			)))
			(#ASSIGN#56_1 (_architecture 1 0 56 (_process (_simple)
				(_target(4))
				(_sensitivity(9))
			)))
			(#ASSIGN#58_2 (_architecture 2 0 58 (_process (_simple)
				(_target(5))
				(_sensitivity(4))
			)))
			(#ASSIGN#60_3 (_architecture 3 0 60 (_process (_simple)
				(_target(0))
				(_sensitivity(7)(9))
			)))
			(#ALWAYS#62_4 (_architecture 4 0 62 (_process 
				(_target(9))
				(_read(3)(2)(1)(6)(9))
			)))
		)
	)
	
	
	(_defparam
	)
	(_model . BitCounter 6 -1)

)
I 000050 55 4040          1079015845795 Interrupt
(_unit VERILOG 6.349C.6.256 (Interrupt 0 25 (Interrupt 0 25 ))
	(_version v32)
	(_time 1079015845498 2004.03.11 06:37:25)
	(_source (\./src/interrupt.v\ VERILOG (\./src/interrupt.v\ VERILOG)))
	(_use (std(standard))(vl(verilog_logic)))
	(_base (E 3))
	(_entity
		(_time 1079015845498)
		(_use )
	)
	(_timescale 1ps 1ps)
	(_parameters    dbg   accs  )
	(_attribute nb_assign )
	(_object
		(_type (_internal ~[7:0]wire~ 0 25 (_array ~wire ((_downto (i 7) (i 0))))))
		(_port (_internal inDATA ~[7:0]wire~ 0 25 (_architecture (_in ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal Reset ~wire 0 25 (_architecture (_in ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal PWRint ~wire 0 25 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal BusInt ~wire 0 25 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal Thres0 ~wire 0 25 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal Mclk ~wire 0 25 (_architecture (_in ))) (_net  ) (_nonbaction) (_noforceassign))
		(_port (_internal Thres1 ~wire 0 25 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal I2Cint ~wire 0 25 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal LSwitchInt ~wire 0 25 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal INT ~wire 0 25 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal DCORIEw ~wire 0 25 (_architecture (_in ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal Homed0 ~wire 0 25 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal Homed1 ~wire 0 25 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_type (_internal ~[7:0]reg~ 0 59 (_array ~reg ((_downto (i 7) (i 0))))))
		(_signal (_internal DCORIE ~[7:0]reg~ 0 59 (_architecture (_uni ))) (_reg ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_subprogram
			

		)
		(_type (_external ~wire (vl verilog_logic wire)))
		(_type (_external ~reg (vl verilog_logic reg)))
		(_type (_external ~event (vl verilog_logic event)))
		(_type (_external ~wand (vl verilog_logic wand)))
		(_type (_external ~wor (vl verilog_logic wor)))
		(_type (_external ~tri1 (vl verilog_logic tri1)))
		(_type (_external ~tri0 (vl verilog_logic tri0)))
		(_type (_external ~trireg (vl verilog_logic trireg)))
		(_type (_external ~supply0 (vl verilog_logic supply0)))
		(_type (_external ~supply1 (vl verilog_logic supply1)))
		(_type (_external ~real (vl verilog_logic real)))
		(_type (_external ~realtime (vl verilog_logic realtime)))
		(_type (_external ~tri (vl verilog_logic tri)))
		(_type (_external ~triand (vl verilog_logic triand)))
		(_type (_external ~trior (vl verilog_logic trior)))
		(_type (_external ~bit (vl verilog_logic bit)))
		(_type (_external ~extstd.standard.integer (std standard integer)))
		(_type (_external ~extstd.standard.bit (std standard bit)))
		(_process
			(#ASSIGN#68_0 (_architecture 0 0 68 (_process (_alias ((INT)(DCORIE(7))(I2Cint)(DCORIE(6))(Thres1)(DCORIE(5))(Thres0)(DCORIE(4))(LSwitchInt)(DCORIE(3))(Homed1)(DCORIE(2))(Homed0)(DCORIE(1))(PWRint)(DCORIE(0))(BusInt)))(_simple)
				(_target(9))
				(_sensitivity(13(7))(7)(13(6))(6)(13(5))(4)(13(4))(8)(13(3))(12)(13(2))(11)(13(1))(2)(13(0))(3))
			)))
			(#ALWAYS#70_1 (_architecture 1 0 70 (_process 
				(_target(13))
				(_read(5)(1)(10)(0))
			)))
		)
	)
	
	
	(_defparam
	)
	(_model . Interrupt 3 -1)

)
I 000051 55 3750          1079016924686 BitCounter
(_unit VERILOG 6.349C.6.256 (BitCounter 0 25 (BitCounter 0 25 ))
	(_version v32)
	(_time 1079016924623 2004.03.11 06:55:24)
	(_source (\./src/bitcounter.v\ VERILOG (\./src/bitcounter.v\ VERILOG)))
	(_use (std(standard))(vl(verilog_logic)))
	(_base (E 6))
	(_entity
		(_time 1079016924623)
		(_use )
	)
	(_timescale 1ps 1ps)
	(_parameters    dbg   accs  )
	(_attribute nb_assign )
	(_object
		(_type (_internal ~[7:0]wire~ 0 25 (_array ~wire ((_downto (i 7) (i 0))))))
		(_port (_internal outDATA ~[7:0]wire~ 0 25 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal NegInc ~wire 0 25 (_architecture (_in ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal SCLreset ~wire 0 25 (_architecture (_in ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal Mclk ~wire 0 25 (_architecture (_in ))) (_net  ) (_nonbaction) (_noforceassign))
		(_port (_internal SCLenable ~wire 0 25 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal Inc ~wire 0 25 (_architecture (_in ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal DriveSCL ~wire 0 25 (_architecture (_inout ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal NegSCL ~wire 0 25 (_architecture (_in ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal DCORI2CCNTr ~wire 0 25 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal SCLint ~wire 0 25 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_type (_internal ~[5:0]reg~ 0 54 (_array ~reg ((_downto (i 5) (i 0))))))
		(_signal (_internal counterr ~[5:0]reg~ 0 54 (_architecture (_uni ))) (_reg ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_subprogram
			

		)
		(_type (_external ~wire (vl verilog_logic wire)))
		(_type (_external ~reg (vl verilog_logic reg)))
		(_type (_external ~event (vl verilog_logic event)))
		(_type (_external ~wand (vl verilog_logic wand)))
		(_type (_external ~wor (vl verilog_logic wor)))
		(_type (_external ~tri1 (vl verilog_logic tri1)))
		(_type (_external ~tri0 (vl verilog_logic tri0)))
		(_type (_external ~trireg (vl verilog_logic trireg)))
		(_type (_external ~supply0 (vl verilog_logic supply0)))
		(_type (_external ~supply1 (vl verilog_logic supply1)))
		(_type (_external ~real (vl verilog_logic real)))
		(_type (_external ~realtime (vl verilog_logic realtime)))
		(_type (_external ~tri (vl verilog_logic tri)))
		(_type (_external ~triand (vl verilog_logic triand)))
		(_type (_external ~trior (vl verilog_logic trior)))
		(_type (_external ~bit (vl verilog_logic bit)))
		(_type (_external ~extstd.standard.integer (std standard integer)))
		(_type (_external ~extstd.standard.bit (std standard bit)))
		(_process
			(#ASSIGN#56_0 (_architecture 0 0 56 (_process (_simple)
				(_target(9))
				(_sensitivity(10))
			)))
			(#ASSIGN#58_1 (_architecture 1 0 58 (_process (_simple)
				(_target(4))
				(_sensitivity(10))
			)))
			(#ASSIGN#60_2 (_architecture 2 0 60 (_process (_simple)
				(_target(6))
				(_sensitivity(4))
			)))
			(#ASSIGN#62_3 (_architecture 3 0 62 (_process (_simple)
				(_target(0))
				(_sensitivity(8)(10))
			)))
			(#ALWAYS#64_4 (_architecture 4 0 64 (_process 
				(_target(10))
				(_read(3)(2)(5)(1)(7)(10))
			)))
		)
	)
	
	
	(_defparam
	)
	(_model . BitCounter 6 -1)

)
V 000047 55 3739          1079016939279 I2Cfix
(_unit VERILOG 6.349C.6.256 (I2Cfix 0 32 (I2Cfix 0 32 ))
	(_version v32)
	(_time 1079016939201 2004.03.11 06:55:39)
	(_source (\./compile/i2cfix.v\ VERILOG (\./compile/i2cfix.v\ VERILOG)))
	(_use (std(standard))(vl(verilog_logic)))
	(_base (E 1))
	(_entity
		(_time 1079016939201)
		(_use )
	)
	(_timescale 1ns 1ns)
	(_parameters    dbg   accs  )
	(_attribute )
	(_object
		(_port (_internal DCORI2CCNTr ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Inc ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Mclk ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal SCLreset ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal SCLenable ~wire 0 32 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal SCLint ~wire 0 32 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_type (_internal ~[7:0]wire~ 0 32 (_array ~wire ((_downto (i 7) (i 0))))))
		(_port (_internal outDATA ~[7:0]wire~ 0 32 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal SCL ~wire 0 32 (_architecture (_inout ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal Incdetect ~wire 0 53 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal SCLdetect ~wire 0 54 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_subprogram
			

		)
		(_type (_external ~wire (vl verilog_logic wire)))
		(_type (_external ~reg (vl verilog_logic reg)))
		(_type (_external ~event (vl verilog_logic event)))
		(_type (_external ~wand (vl verilog_logic wand)))
		(_type (_external ~wor (vl verilog_logic wor)))
		(_type (_external ~tri1 (vl verilog_logic tri1)))
		(_type (_external ~tri0 (vl verilog_logic tri0)))
		(_type (_external ~trireg (vl verilog_logic trireg)))
		(_type (_external ~supply0 (vl verilog_logic supply0)))
		(_type (_external ~supply1 (vl verilog_logic supply1)))
		(_type (_external ~real (vl verilog_logic real)))
		(_type (_external ~realtime (vl verilog_logic realtime)))
		(_type (_external ~tri (vl verilog_logic tri)))
		(_type (_external ~triand (vl verilog_logic triand)))
		(_type (_external ~trior (vl verilog_logic trior)))
		(_type (_external ~bit (vl verilog_logic bit)))
		(_type (_external ~extstd.standard.integer (std standard integer)))
		(_type (_external ~extstd.standard.bit (std standard bit)))
	)
	
	
	(_defparam
	)
	(_scope
	)
	(_instantiation U1 0 58 (_entity .  NegDetect)
		(_port
			((Line) (Inc))
			((Mclk) (Mclk))
			((Ndetect) (Incdetect))
		)
		(_strength strong0 strong1)
	)
	(_instantiation U2 0 67 (_entity .  NegDetect)
		(_port
			((Line) (SCL))
			((Mclk) (Mclk))
			((Ndetect) (SCLdetect))
		)
		(_strength strong0 strong1)
	)
	(_instantiation U3 0 76 (_entity .  BitCounter)
		(_port
			((DCORI2CCNTr) (DCORI2CCNTr))
			((DriveSCL) (SCL))
			((Inc) (Inc))
			((Mclk) (Mclk))
			((NegInc) (Incdetect))
			((NegSCL) (SCLdetect))
			((SCLenable) (SCLenable))
			((SCLint) (SCLint))
			((SCLreset) (SCLreset))
			((outDATA) (outDATA))
		)
		(_strength strong0 strong1)
	)
	(_model . I2Cfix 1 -1)

)
I 000051 55 3750          1079017602483 BitCounter
(_unit VERILOG 6.349C.6.256 (BitCounter 0 25 (BitCounter 0 25 ))
	(_version v32)
	(_time 1079017602420 2004.03.11 07:06:42)
	(_source (\./src/bitcounter.v\ VERILOG (\./src/bitcounter.v\ VERILOG)))
	(_use (std(standard))(vl(verilog_logic)))
	(_base (E 6))
	(_entity
		(_time 1079017602420)
		(_use )
	)
	(_timescale 1ps 1ps)
	(_parameters    dbg   accs  )
	(_attribute nb_assign )
	(_object
		(_type (_internal ~[7:0]wire~ 0 25 (_array ~wire ((_downto (i 7) (i 0))))))
		(_port (_internal outDATA ~[7:0]wire~ 0 25 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal NegInc ~wire 0 25 (_architecture (_in ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal SCLreset ~wire 0 25 (_architecture (_in ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal Mclk ~wire 0 25 (_architecture (_in ))) (_net  ) (_nonbaction) (_noforceassign))
		(_port (_internal SCLenable ~wire 0 25 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal Inc ~wire 0 25 (_architecture (_in ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal DriveSCL ~wire 0 25 (_architecture (_inout ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal NegSCL ~wire 0 25 (_architecture (_in ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal DCORI2CCNTr ~wire 0 25 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal SCLint ~wire 0 25 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_type (_internal ~[5:0]reg~ 0 54 (_array ~reg ((_downto (i 5) (i 0))))))
		(_signal (_internal counterr ~[5:0]reg~ 0 54 (_architecture (_uni ))) (_reg ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_subprogram
			

		)
		(_type (_external ~wire (vl verilog_logic wire)))
		(_type (_external ~reg (vl verilog_logic reg)))
		(_type (_external ~event (vl verilog_logic event)))
		(_type (_external ~wand (vl verilog_logic wand)))
		(_type (_external ~wor (vl verilog_logic wor)))
		(_type (_external ~tri1 (vl verilog_logic tri1)))
		(_type (_external ~tri0 (vl verilog_logic tri0)))
		(_type (_external ~trireg (vl verilog_logic trireg)))
		(_type (_external ~supply0 (vl verilog_logic supply0)))
		(_type (_external ~supply1 (vl verilog_logic supply1)))
		(_type (_external ~real (vl verilog_logic real)))
		(_type (_external ~realtime (vl verilog_logic realtime)))
		(_type (_external ~tri (vl verilog_logic tri)))
		(_type (_external ~triand (vl verilog_logic triand)))
		(_type (_external ~trior (vl verilog_logic trior)))
		(_type (_external ~bit (vl verilog_logic bit)))
		(_type (_external ~extstd.standard.integer (std standard integer)))
		(_type (_external ~extstd.standard.bit (std standard bit)))
		(_process
			(#ASSIGN#56_0 (_architecture 0 0 56 (_process (_simple)
				(_target(9))
				(_sensitivity(10))
			)))
			(#ASSIGN#58_1 (_architecture 1 0 58 (_process (_simple)
				(_target(4))
				(_sensitivity(10))
			)))
			(#ASSIGN#60_2 (_architecture 2 0 60 (_process (_simple)
				(_target(6))
				(_sensitivity(4))
			)))
			(#ASSIGN#62_3 (_architecture 3 0 62 (_process (_simple)
				(_target(0))
				(_sensitivity(8)(10))
			)))
			(#ALWAYS#64_4 (_architecture 4 0 64 (_process 
				(_target(10))
				(_read(3)(2)(5)(1)(7)(10))
			)))
		)
	)
	
	
	(_defparam
	)
	(_model . BitCounter 6 -1)

)
I 000050 55 4827          1079725285583 Interface
(_unit VERILOG 6.349C.6.256 (Interface 0 25 (Interface 0 25 ))
	(_version v32)
	(_time 1079725285489 2004.03.19 11:41:25)
	(_source (\./src/interface.v\ VERILOG (\./src/interface.v\ VERILOG)))
	(_use (std(standard))(vl(verilog_logic)))
	(_base (E 8))
	(_entity
		(_time 1079725285489)
		(_use )
	)
	(_timescale 1ps 1ps)
	(_parameters    dbg   accs  )
	(_attribute nb_assign )
	(_object
		(_type (_internal ~[7:0]wire~ 0 25 (_array ~wire ((_downto (i 7) (i 0))))))
		(_port (_internal inDATA ~[7:0]wire~ 0 25 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal outDATA ~[7:0]wire~ 0 25 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal Reset ~wire 0 25 (_architecture (_in ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal AS ~wire 0 25 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal AD ~[7:0]wire~ 0 25 (_architecture (_inout ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal RD ~wire 0 25 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal Mclk ~wire 0 25 (_architecture (_in ))) (_net  ) (_nonbaction) (_noforceassign))
		(_port (_internal ASleading ~wire 0 25 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal WR ~wire 0 25 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal ADDR ~[7:0]wire~ 0 25 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_type (_internal ~[7:0]reg~ 0 58 (_array ~reg ((_downto (i 7) (i 0))))))
		(_signal (_internal ADDR_reg ~[7:0]reg~ 0 58 (_architecture (_uni ))) (_reg ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal AutoInc ~reg 0 66 (_architecture (_uni ))) (_reg ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal ASedge ~reg 0 68 (_architecture (_uni ))) (_reg ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal WRRDedge ~reg 0 70 (_architecture (_uni ))) (_reg ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal Enable_AD ~wire 0 74 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal ADDR_in_Range ~wire 0 75 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_subprogram
			

		)
		(_type (_external ~wire (vl verilog_logic wire)))
		(_type (_external ~reg (vl verilog_logic reg)))
		(_type (_external ~event (vl verilog_logic event)))
		(_type (_external ~wand (vl verilog_logic wand)))
		(_type (_external ~wor (vl verilog_logic wor)))
		(_type (_external ~tri1 (vl verilog_logic tri1)))
		(_type (_external ~tri0 (vl verilog_logic tri0)))
		(_type (_external ~trireg (vl verilog_logic trireg)))
		(_type (_external ~supply0 (vl verilog_logic supply0)))
		(_type (_external ~supply1 (vl verilog_logic supply1)))
		(_type (_external ~real (vl verilog_logic real)))
		(_type (_external ~realtime (vl verilog_logic realtime)))
		(_type (_external ~tri (vl verilog_logic tri)))
		(_type (_external ~triand (vl verilog_logic triand)))
		(_type (_external ~trior (vl verilog_logic trior)))
		(_type (_external ~bit (vl verilog_logic bit)))
		(_type (_external ~extstd.standard.integer (std standard integer)))
		(_type (_external ~extstd.standard.bit (std standard bit)))
		(_process
			(#ASSIGN#79_0 (_architecture 0 0 79 (_process (_alias ((ADDR)(ADDR_reg)))(_simple)
				(_target(9))
				(_sensitivity(10))
			)))
			(#ASSIGN#82_1 (_architecture 1 0 82 (_process (_alias ((Enable_AD)(WR)(RD)(ADDR_in_Range)))(_simple)
				(_target(14))
				(_sensitivity(8)(5)(15))
			)))
			(#ASSIGN#83_2 (_architecture 2 0 83 (_process (_simple)
				(_target(15))
				(_sensitivity(10))
			)))
			(#ASSIGN#84_3 (_architecture 3 0 84 (_process (_alias ((ASleading)(AS)(ASedge)))(_simple)
				(_target(7))
				(_sensitivity(3)(12))
			)))
			(#ASSIGN#91_4 (_architecture 4 0 91 (_process (_alias ((inDATA)(AD)))(_simple)
				(_target(0))
				(_sensitivity(4))
			)))
			(#ASSIGN#92_5 (_architecture 5 0 92 (_process (_simple)
				(_target(4))
				(_sensitivity(14)(1))
			)))
			(#ALWAYS#94_6 (_architecture 6 0 94 (_process 
				(_target(12)(13)(10)(11))
				(_read(6)(3)(8)(5)(2)(7)(4)(13)(11)(15)(10))
			)))
		)
	)
	
	
	(_defparam
	)
	(_model . Interface 8 -1)

)
I 000048 55 4486          1079725724083 Holdreg
(_unit VERILOG 6.349C.6.256 (Holdreg 0 25 (Holdreg 0 25 ))
	(_version v32)
	(_time 1079725723864 2004.03.19 11:48:43)
	(_source (\./src/holdreg.v\ VERILOG (\./src/holdreg.v\ VERILOG)))
	(_use (std(standard))(vl(verilog_logic)))
	(_base (E 4))
	(_entity
		(_time 1079725723864)
		(_use )
	)
	(_timescale 1ps 1ps)
	(_parameters    dbg   accs  )
	(_attribute nb_assign )
	(_object
		(_port (_internal DCOR1CNTHIGHr ~wire 0 25 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal DCOR0CNTLOWr ~wire 0 25 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_type (_internal ~[7:0]wire~ 0 25 (_array ~wire ((_downto (i 7) (i 0))))))
		(_port (_internal outDATA ~[7:0]wire~ 0 25 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal DCOR1CNTLOWr ~wire 0 25 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_type (_internal ~[23:0]wire~ 0 25 (_array ~wire ((_downto (i 23) (i 0))))))
		(_port (_internal ch0in ~[23:0]wire~ 0 25 (_architecture (_in ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal ch1in ~[23:0]wire~ 0 25 (_architecture (_in ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal Reset ~wire 0 25 (_architecture (_in ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal ASleading ~wire 0 25 (_architecture (_in ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal DCOR0CNTMIDr ~wire 0 25 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal DCOR1CNTMIDr ~wire 0 25 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal Sclk ~wire 0 25 (_architecture (_in ))) (_net  ) (_nonbaction) (_noforceassign))
		(_port (_internal DCOR0CNTHIGHr ~wire 0 25 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal RDedge ~reg 0 73 (_architecture (_uni ))) (_reg ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_type (_internal ~[23:0]reg~ 0 75 (_array ~reg ((_downto (i 23) (i 0))))))
		(_signal (_internal holdingreg0 ~[23:0]reg~ 0 75 (_architecture (_uni ))) (_reg ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal holdingreg1 ~[23:0]reg~ 0 75 (_architecture (_uni ))) (_reg ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal interDATA ~[7:0]wire~ 0 76 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_subprogram
			

		)
		(_type (_external ~wire (vl verilog_logic wire)))
		(_type (_external ~reg (vl verilog_logic reg)))
		(_type (_external ~event (vl verilog_logic event)))
		(_type (_external ~wand (vl verilog_logic wand)))
		(_type (_external ~wor (vl verilog_logic wor)))
		(_type (_external ~tri1 (vl verilog_logic tri1)))
		(_type (_external ~tri0 (vl verilog_logic tri0)))
		(_type (_external ~trireg (vl verilog_logic trireg)))
		(_type (_external ~supply0 (vl verilog_logic supply0)))
		(_type (_external ~supply1 (vl verilog_logic supply1)))
		(_type (_external ~real (vl verilog_logic real)))
		(_type (_external ~realtime (vl verilog_logic realtime)))
		(_type (_external ~tri (vl verilog_logic tri)))
		(_type (_external ~triand (vl verilog_logic triand)))
		(_type (_external ~trior (vl verilog_logic trior)))
		(_type (_external ~bit (vl verilog_logic bit)))
		(_type (_external ~extstd.standard.integer (std standard integer)))
		(_type (_external ~extstd.standard.bit (std standard bit)))
		(_process
			(#ASSIGN#91_0 (_architecture 0 0 91 (_process (_simple)
				(_target(15))
				(_sensitivity(1)(13(d_7_0))(3)(14(d_7_0))(8)(13(d_15_8))(9)(14(d_15_8))(11)(13(d_23_16))(0)(14(d_23_16)))
			)))
			(#ASSIGN#93_1 (_architecture 1 0 93 (_process (_alias ((outDATA)(interDATA)))(_simple)
				(_target(2))
				(_sensitivity(15))
			)))
			(#ALWAYS#95_2 (_architecture 2 0 95 (_process 
				(_target(12)(13)(14))
				(_read(10)(1)(3)(6)(7)(4)(5))
			)))
		)
	)
	
	
	(_defparam
	)
	(_model . Holdreg 4 -1)

)
V 000047 55 10424         1079725739927 Servos
(_unit VERILOG 6.349C.6.256 (Servos 0 32 (Servos 0 32 ))
	(_version v32)
	(_time 1079725739864 2004.03.19 11:48:59)
	(_source (\./compile/servos.v\ VERILOG (\./compile/servos.v\ VERILOG)))
	(_use (std(standard))(vl(verilog_logic)))
	(_base (E 2))
	(_entity
		(_time 1079725739864)
		(_use )
	)
	(_timescale 1ns 1ns)
	(_parameters    dbg   accs  )
	(_attribute )
	(_object
		(_port (_internal ASleading ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal DCOR0CNTHIGHr ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal DCOR0CNTLOWr ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal DCOR0CNTMIDr ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal DCOR0THRESLOWr ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal DCOR0THRESMIDr ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal DCOR1CNTHIGHr ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal DCOR1CNTLOWr ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal DCOR1CNTMIDr ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal DCOR1THRESLOWr ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal DCOR1THRESMIDr ~wire 0 33 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal DCORENCCTLw ~wire 0 33 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal DCORIFGr ~wire 0 33 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal DCORIFGw ~wire 0 33 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Home_Encoder0 ~wire 0 33 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Home_Encoder1 ~wire 0 33 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Mclk ~wire 0 33 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal MotorIn0 ~wire 0 33 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Motorin1 ~wire 0 33 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PhaseA_Encoder0 ~wire 0 33 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PhaseA_Encoder1 ~wire 0 34 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PhaseB_Encoder0 ~wire 0 34 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PhaseB_Encoder1 ~wire 0 34 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Reset ~wire 0 34 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_type (_internal ~[7:0]wire~ 0 34 (_array ~wire ((_downto (i 7) (i 0))))))
		(_port (_internal inDATA ~[7:0]wire~ 0 34 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Hfound0 ~wire 0 34 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Hfound1 ~wire 0 34 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Tfound0 ~wire 0 34 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Tfound1 ~wire 0 34 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal outDATA ~[7:0]wire~ 0 34 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal ce0 ~wire 0 99 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal ce1 ~wire 0 100 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET3720 ~wire 0 101 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET3721 ~wire 0 102 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal Sclk ~wire 0 103 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal updown0 ~wire 0 104 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal updown1 ~wire 0 105 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal Zero0 ~wire 0 106 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal Zero1 ~wire 0 107 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_type (_internal ~[23:0]wire~ 0 108 (_array ~wire ((_downto (i 23) (i 0))))))
		(_signal (_internal Channel0 ~[23:0]wire~ 0 108 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal Channel1 ~[23:0]wire~ 0 109 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_subprogram
			

		)
		(_type (_external ~wire (vl verilog_logic wire)))
		(_type (_external ~reg (vl verilog_logic reg)))
		(_type (_external ~event (vl verilog_logic event)))
		(_type (_external ~wand (vl verilog_logic wand)))
		(_type (_external ~wor (vl verilog_logic wor)))
		(_type (_external ~tri1 (vl verilog_logic tri1)))
		(_type (_external ~tri0 (vl verilog_logic tri0)))
		(_type (_external ~trireg (vl verilog_logic trireg)))
		(_type (_external ~supply0 (vl verilog_logic supply0)))
		(_type (_external ~supply1 (vl verilog_logic supply1)))
		(_type (_external ~real (vl verilog_logic real)))
		(_type (_external ~realtime (vl verilog_logic realtime)))
		(_type (_external ~tri (vl verilog_logic tri)))
		(_type (_external ~triand (vl verilog_logic triand)))
		(_type (_external ~trior (vl verilog_logic trior)))
		(_type (_external ~bit (vl verilog_logic bit)))
		(_type (_external ~extstd.standard.integer (std standard integer)))
		(_type (_external ~extstd.standard.bit (std standard bit)))
		(_process
			(#ASSIGN#214_0 (_architecture 0 0 214 (_process (_alias ((Sclk)(Mclk)))(_simple)
				(_target(34))
				(_sensitivity(16))
			)))
		)
	)
	
	
	(_defparam
	)
	(_scope
	)
	(_instantiation U1 0 113 (_entity .  Decode)
		(_port
			((Reset) (Reset))
			((Sclk) (Sclk))
			((ce) (ce0))
			((phaseA) (PhaseA_Encoder0))
			((phaseB) (PhaseB_Encoder0))
			((updown) (updown0))
		)
		(_strength strong0 strong1)
	)
	(_instantiation U2 0 125 (_entity .  Counter)
		(_port
			((Reset) (Reset))
			((Sclk) (Sclk))
			((Zero) (Zero0))
			((ce) (ce0))
			((count) (Channel0))
			((sense) (NET3721))
			((updown) (updown0))
		)
		(_strength strong0 strong1)
	)
	(_instantiation U3 0 138 (_entity .  Holdreg)
		(_port
			((ASleading) (ASleading))
			((DCOR0CNTHIGHr) (DCOR0CNTHIGHr))
			((DCOR0CNTLOWr) (DCOR0CNTLOWr))
			((DCOR0CNTMIDr) (DCOR0CNTMIDr))
			((DCOR1CNTHIGHr) (DCOR1CNTHIGHr))
			((DCOR1CNTLOWr) (DCOR1CNTLOWr))
			((DCOR1CNTMIDr) (DCOR1CNTMIDr))
			((Reset) (Reset))
			((Sclk) (Sclk))
			((ch0in) (Channel0))
			((ch1in) (Channel1))
			((outDATA) (outDATA))
		)
		(_strength strong0 strong1)
	)
	(_instantiation U4 0 156 (_entity .  HomeConfig)
		(_port
			((Channel0) (Channel0(d_15_0)))
			((Channel1) (Channel1(d_15_0)))
			((DCOR0THRESLOWr) (DCOR0THRESLOWr))
			((DCOR0THRESMIDr) (DCOR0THRESMIDr))
			((DCOR1THRESLOWr) (DCOR1THRESLOWr))
			((DCOR1THRESMIDr) (DCOR1THRESMIDr))
			((DCORENCCTLw) (DCORENCCTLw))
			((DCORIFGr) (DCORIFGr))
			((DCORIFGw) (DCORIFGw))
			((Hfound0) (Hfound0))
			((Hfound1) (Hfound1))
			((Home_Encoder0) (Home_Encoder0))
			((Home_Encoder1) (Home_Encoder1))
			((MotorIn0) (MotorIn0))
			((MotorIn1) (Motorin1))
			((Reset) (Reset))
			((Sclk) (Sclk))
			((Tfound0) (Tfound0))
			((Tfound1) (Tfound1))
			((Zero0) (Zero0))
			((Zero1) (Zero1))
			((inDATA) (inDATA))
			((outDATA) (outDATA))
			((sense0) (NET3721))
			((sense1) (NET3720))
		)
		(_strength strong0 strong1)
	)
	(_instantiation U5 0 187 (_entity .  Counter)
		(_port
			((Reset) (Reset))
			((Sclk) (Sclk))
			((Zero) (Zero1))
			((ce) (ce1))
			((count) (Channel1))
			((sense) (NET3720))
			((updown) (updown1))
		)
		(_strength strong0 strong1)
	)
	(_instantiation U6 0 200 (_entity .  Decode)
		(_port
			((Reset) (Reset))
			((Sclk) (Sclk))
			((ce) (ce1))
			((phaseA) (PhaseA_Encoder1))
			((phaseB) (PhaseB_Encoder1))
			((updown) (updown1))
		)
		(_strength strong0 strong1)
	)
	(_model . Servos 2 -1)

)
V 000044 55 25310         1079725758427 U21
(_unit VERILOG 6.349C.6.256 (U21 0 32 (U21 0 32 ))
	(_version v32)
	(_time 1079725758364 2004.03.19 11:49:18)
	(_source (\./compile/u21.v\ VERILOG (\./compile/u21.v\ VERILOG)))
	(_use (std(standard))(vl(verilog_logic)))
	(_base (E 12))
	(_entity
		(_time 1079725758364)
		(_use )
	)
	(_timescale 1ns 1ns)
	(_parameters    dbg   accs  )
	(_attribute )
	(_object
		(_port (_internal AS ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Brake0 ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Brake1 ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal DIR0 ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal DIR1 ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Enc033FLG ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Enc05FLG ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Enc133FLG ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Enc15FLG ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal FLS0 ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal FLS1 ~wire 0 33 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal GP_Motor0_0 ~wire 0 33 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal GP_Motor1_0 ~wire 0 33 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal HSI ~wire 0 33 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal Home0 ~wire 0 33 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Home033FLG ~wire 0 33 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Home05FLG ~wire 0 33 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Home1 ~wire 0 33 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Home133FLG ~wire 0 33 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Home15FLG ~wire 0 33 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal INTbus ~wire 0 34 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal LightSense ~wire 0 34 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal MHSO ~wire 0 34 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal Mclk ~wire 0 34 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PWM1 ~wire 0 34 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PWM2 ~wire 0 34 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PhaseA_Encoder0 ~wire 0 34 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PhaseA_Encoder1 ~wire 0 34 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PhaseB_Encoder0 ~wire 0 34 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PhaseB_Encoder1 ~wire 0 34 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal RD ~wire 0 35 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal RLS0 ~wire 0 35 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal RLS1 ~wire 0 35 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Reset ~wire 0 35 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal SCLinc ~wire 0 35 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal SCLreset ~wire 0 35 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal TXI ~wire 0 35 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal WR ~wire 0 35 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_type (_internal ~[5:0]wire~ 0 35 (_array ~wire ((_downto (i 5) (i 0))))))
		(_port (_internal I2CS ~[5:0]wire~ 0 35 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Enc033ctrl ~wire 0 35 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Enc05ctrl ~wire 0 36 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Enc133ctrl ~wire 0 36 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Enc15ctrl ~wire 0 36 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal GP_Motor0_1 ~wire 0 36 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal GP_Motor1_1 ~wire 0 36 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal HSO ~wire 0 36 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal Home033ctrl ~wire 0 36 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Home05ctrl ~wire 0 36 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Home133ctrl ~wire 0 36 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Home15ctrl ~wire 0 36 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal INT ~wire 0 37 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal LED1 ~wire 0 37 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal LED2 ~wire 0 37 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal LED3 ~wire 0 37 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal LED4 ~wire 0 37 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal LED5 ~wire 0 37 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal MHSI ~wire 0 37 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal MTRpwr ~wire 0 37 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal MTRpwrn ~wire 0 37 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal MTXI ~wire 0 37 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal PAH0 ~wire 0 38 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PAH1 ~wire 0 38 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PAL0 ~wire 0 38 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PAL1 ~wire 0 38 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PBH0 ~wire 0 38 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PBH1 ~wire 0 38 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PBL0 ~wire 0 38 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PBL1 ~wire 0 38 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal TP10 ~wire 0 38 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal TP11 ~wire 0 38 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal TP12 ~wire 0 39 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal SCL ~wire 0 39 (_architecture (_inout ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_type (_internal ~[7:0]wire~ 0 39 (_array ~wire ((_downto (i 7) (i 0))))))
		(_port (_internal AD ~[7:0]wire~ 0 39 (_architecture (_inout ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET1635 ~wire 0 190 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET1643 ~wire 0 191 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET1651 ~wire 0 192 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET1659 ~wire 0 193 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET1667 ~wire 0 194 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET1675 ~wire 0 195 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET1683 ~wire 0 196 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET1691 ~wire 0 197 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET1699 ~wire 0 198 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET1707 ~wire 0 199 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET1970 ~wire 0 200 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET1978 ~wire 0 201 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET1989 ~wire 0 202 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET2017 ~wire 0 203 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET2025 ~wire 0 204 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET2036 ~wire 0 205 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET2047 ~wire 0 206 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET2064 ~wire 0 207 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET2078 ~wire 0 208 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET2311 ~wire 0 209 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET2482 ~wire 0 210 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET2493 ~wire 0 211 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET2501 ~wire 0 212 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET2512 ~wire 0 213 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET2528 ~wire 0 214 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET2539 ~wire 0 215 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET2575 ~wire 0 216 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET3248 ~wire 0 217 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET3253 ~wire 0 218 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET3919 ~wire 0 219 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal NET3926 ~wire 0 220 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal NET4826 ~wire 0 221 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET615 ~wire 0 222 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal NET621 ~wire 0 223 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal NET629 ~wire 0 224 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal BUS1564 ~[7:0]wire~ 0 225 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal inDATA ~[7:0]wire~ 0 226 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal outDATA ~[7:0]wire~ 0 227 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_subprogram
			

		)
		(_type (_external ~wire (vl verilog_logic wire)))
		(_type (_external ~reg (vl verilog_logic reg)))
		(_type (_external ~event (vl verilog_logic event)))
		(_type (_external ~wand (vl verilog_logic wand)))
		(_type (_external ~wor (vl verilog_logic wor)))
		(_type (_external ~tri1 (vl verilog_logic tri1)))
		(_type (_external ~tri0 (vl verilog_logic tri0)))
		(_type (_external ~trireg (vl verilog_logic trireg)))
		(_type (_external ~supply0 (vl verilog_logic supply0)))
		(_type (_external ~supply1 (vl verilog_logic supply1)))
		(_type (_external ~real (vl verilog_logic real)))
		(_type (_external ~realtime (vl verilog_logic realtime)))
		(_type (_external ~tri (vl verilog_logic tri)))
		(_type (_external ~triand (vl verilog_logic triand)))
		(_type (_external ~trior (vl verilog_logic trior)))
		(_type (_external ~bit (vl verilog_logic bit)))
		(_type (_external ~extstd.standard.integer (std standard integer)))
		(_type (_external ~extstd.standard.bit (std standard bit)))
		(_process
			(#ASSIGN#459_0 (_architecture 0 0 459 (_process (_alias ((NET3919)(SCLreset)))(_simple)
				(_target(102))
				(_sensitivity(35))
			)))
			(#ASSIGN#460_1 (_architecture 1 0 460 (_process (_alias ((NET3926)(SCLinc)))(_simple)
				(_target(103))
				(_sensitivity(34))
			)))
			(#ASSIGN#461_2 (_architecture 2 0 461 (_process (_alias ((NET615)(MHSO)))(_simple)
				(_target(105))
				(_sensitivity(22))
			)))
			(#ASSIGN#462_3 (_architecture 3 0 462 (_process (_alias ((NET621)(HSI)))(_simple)
				(_target(106))
				(_sensitivity(13))
			)))
			(#ASSIGN#463_4 (_architecture 4 0 463 (_process (_alias ((NET629)(TXI)))(_simple)
				(_target(107))
				(_sensitivity(36))
			)))
			(#ASSIGN#466_5 (_architecture 5 0 466 (_process (_alias ((HSO)(NET615)))(_simple)
				(_target(45))
				(_sensitivity(105))
			)))
			(#ASSIGN#467_6 (_architecture 6 0 467 (_process (_alias ((MHSI)(NET621)))(_simple)
				(_target(56))
				(_sensitivity(106))
			)))
			(#ASSIGN#468_7 (_architecture 7 0 468 (_process (_alias ((MTXI)(NET629)))(_simple)
				(_target(59))
				(_sensitivity(107))
			)))
			(#ASSIGN#469_8 (_architecture 8 0 469 (_process (_alias ((TP10)(NET3919)))(_simple)
				(_target(68))
				(_sensitivity(102))
			)))
			(#ASSIGN#470_9 (_architecture 9 0 470 (_process (_alias ((TP11)(NET3926)))(_simple)
				(_target(69))
				(_sensitivity(103))
			)))
			(#ASSIGN#471_10 (_architecture 10 0 471 (_process (_alias ((TP12)(SCL)))(_simple)
				(_target(70))
				(_sensitivity(71))
			)))
		)
	)
	
	
	(_defparam
	)
	(_scope
	)
	(_instantiation U1 0 231 (_entity .  Servos)
		(_port
			((ASleading) (NET4826))
			((DCOR0CNTHIGHr) (NET1667))
			((DCOR0CNTLOWr) (NET1651))
			((DCOR0CNTMIDr) (NET1659))
			((DCOR0THRESLOWr) (NET1635))
			((DCOR0THRESMIDr) (NET1643))
			((DCOR1CNTHIGHr) (NET1675))
			((DCOR1CNTLOWr) (NET1683))
			((DCOR1CNTMIDr) (NET1691))
			((DCOR1THRESLOWr) (NET1707))
			((DCOR1THRESMIDr) (NET1699))
			((DCORENCCTLw) (NET1970))
			((DCORIFGr) (NET1978))
			((DCORIFGw) (NET1989))
			((Hfound0) (NET2482))
			((Hfound1) (NET2493))
			((Home_Encoder0) (Home0))
			((Home_Encoder1) (Home1))
			((Mclk) (Mclk))
			((MotorIn0) (GP_Motor0_0))
			((Motorin1) (GP_Motor1_0))
			((PhaseA_Encoder0) (PhaseA_Encoder0))
			((PhaseA_Encoder1) (PhaseA_Encoder1))
			((PhaseB_Encoder0) (PhaseB_Encoder0))
			((PhaseB_Encoder1) (PhaseB_Encoder1))
			((Reset) (Reset))
			((Tfound0) (NET2501))
			((Tfound1) (NET2512))
			((inDATA) (inDATA))
			((outDATA) (outDATA))
		)
		(_strength strong0 strong1)
	)
	(_instantiation U11 0 267 (_entity .  I2Cfix)
		(_port
			((DCORI2CCNTr) (NET2311))
			((Inc) (NET3926))
			((Mclk) (Mclk))
			((SCL) (SCL))
			((SCLint) (NET2539))
			((SCLreset) (NET3919))
			((outDATA) (outDATA))
			((SCLenable) (_open))
		)
		(_strength strong0 strong1)
	)
	(_instantiation U12 0 280 (_entity .  U21AddDecode)
		(_port
			((ADDR) (BUS1564))
			((AS) (AS))
			((DCOR0CNTHIGHr) (NET1667))
			((DCOR0CNTLOWr) (NET1651))
			((DCOR0CNTMIDr) (NET1659))
			((DCOR0THRESLOWr) (NET1635))
			((DCOR0THRESMIDr) (NET1643))
			((DCOR1CNTHIGHr) (NET1675))
			((DCOR1CNTLOWr) (NET1683))
			((DCOR1CNTMIDr) (NET1691))
			((DCOR1THRESLOWr) (NET1707))
			((DCOR1THRESMIDr) (NET1699))
			((DCORCONFIGr) (NET2064))
			((DCORENCCTLw) (NET1970))
			((DCORENCPWRr) (NET2036))
			((DCORENCPWRw) (NET2025))
			((DCORI2CCNTr) (NET2311))
			((DCORIEw) (NET2078))
			((DCORIFGr) (NET1978))
			((DCORIFGw) (NET1989))
			((DCORLIMITSr) (NET2047))
			((DCOROUTw) (NET2017))
			((RD) (RD))
			((WR) (WR))
		)
		(_strength strong0 strong1)
	)
	(_instantiation U2 0 310 (_entity .  Interface)
		(_port
			((AD) (AD))
			((ADDR) (BUS1564))
			((AS) (AS))
			((ASleading) (NET4826))
			((Mclk) (Mclk))
			((RD) (RD))
			((Reset) (Reset))
			((WR) (WR))
			((inDATA) (inDATA))
			((outDATA) (outDATA))
		)
		(_strength strong0 strong1)
	)
	(_instantiation U3 0 326 (_entity .  Interrupt)
		(_port
			((BusInt) (INTbus))
			((DCORIEw) (NET2078))
			((Homed0) (NET2482))
			((Homed1) (NET2493))
			((I2Cint) (NET2539))
			((INT) (INT))
			((LSwitchInt) (NET2575))
			((Mclk) (Mclk))
			((PWRint) (NET2528))
			((Reset) (Reset))
			((Thres0) (NET2501))
			((Thres1) (NET2512))
			((inDATA) (inDATA))
		)
		(_strength strong0 strong1)
	)
	(_instantiation U4 0 345 (_entity .  PWRreg)
		(_port
			((DCORENCPWRr) (NET2036))
			((DCORENCPWRw) (NET2025))
			((DCORIFGr) (NET1978))
			((DCORIFGw) (NET1989))
			((Enc033ctl) (Home15ctrl))
			((Enc033flg) (Enc033FLG))
			((Enc05ctl) (Home133ctrl))
			((Enc05flg) (Enc05FLG))
			((Enc133ctl) (Home05ctrl))
			((Enc133flg) (Enc133FLG))
			((Enc15ctl) (Home033ctrl))
			((Enc15flg) (Enc15FLG))
			((Hme033ctl) (Enc15ctrl))
			((Hme033flg) (Home033FLG))
			((Hme05ctl) (Enc133ctrl))
			((Hme05flg) (Home05FLG))
			((Hme133ctl) (Enc05ctrl))
			((Hme133flg) (Home133FLG))
			((Hme15ctl) (Enc033ctrl))
			((Hme15flg) (Home15FLG))
			((Mclk) (Mclk))
			((PWRint) (NET2528))
			((Reset) (Reset))
			((inDATA) (inDATA))
			((outDATA) (outDATA))
		)
		(_strength strong0 strong1)
	)
	(_instantiation U5 0 376 (_entity .  Lswitch)
		(_port
			((Brake0) (Brake0))
			((Brake1) (Brake1))
			((DCORIFGr) (NET1978))
			((DCORIFGw) (NET1989))
			((DCORLIMITSr) (NET2047))
			((DIR0) (DIR0))
			((DIR1) (DIR1))
			((FLS0) (FLS0))
			((FLS1) (FLS1))
			((Home0) (Home0))
			((Home1) (Home1))
			((LSwitchInt) (NET2575))
			((Mclk) (Mclk))
			((RLS0) (RLS0))
			((RLS1) (RLS1))
			((Reset) (Reset))
			((fBRK0) (NET3248))
			((fBRK1) (NET3253))
			((inDATA) (inDATA))
			((outDATA) (outDATA))
		)
		(_strength strong0 strong1)
	)
	(_instantiation U6 0 402 (_entity .  I2CAddress)
		(_port
			((DCORCONFIGr) (NET2064))
			((I2CS) (I2CS))
			((MotorIn0) (GP_Motor0_0))
			((MotorIn1) (GP_Motor1_0))
			((outDATA) (outDATA))
		)
		(_strength strong0 strong1)
	)
	(_instantiation U7 0 413 (_entity .  PWMcontrol)
		(_port
			((Brake1) (Brake0))
			((Brake2) (Brake1))
			((DIR1) (DIR0))
			((DIR2) (DIR1))
			((HBRK1) (NET3248))
			((HBRK2) (NET3253))
			((PAH1) (PAH0))
			((PAH2) (PBL1))
			((PAL1) (PAL0))
			((PAL2) (PBH1))
			((PBH1) (PBH0))
			((PBH2) (PAL1))
			((PBL1) (PBL0))
			((PBL2) (PAH1))
			((PWM1) (PWM1))
			((PWM2) (PWM2))
			((fBRK1) (NET3248))
			((fBRK2) (NET3253))
		)
		(_strength strong0 strong1)
	)
	(_instantiation U9 0 437 (_entity .  MISCouts)
		(_port
			((DCOROUTw) (NET2017))
			((GP_Motor0_1) (GP_Motor0_1))
			((GP_Motor1_1) (GP_Motor1_1))
			((LED1) (LED1))
			((LED2) (LED2))
			((LED3) (LED3))
			((LED4) (LED4))
			((LED5) (LED5))
			((LightSense) (LightSense))
			((MTRpwr) (MTRpwr))
			((MTRpwrn) (MTRpwrn))
			((Mclk) (Mclk))
			((Reset) (Reset))
			((inDATA) (inDATA))
		)
		(_strength strong0 strong1)
	)
	(_model . U21 12 -1)

)
V 000047 55 4287          1079990823918 reader
(_unit VERILOG 6.349C.6.256 (reader 0 32 (reader 0 32 ))
	(_version v32)
	(_time 1079990823558 2004.03.22 13:27:03)
	(_source (\./compile/reader.v\ VERILOG (\./compile/reader.v\ VERILOG)))
	(_use (std(standard))(vl(verilog_logic)))
	(_base (E 2))
	(_entity
		(_time 1079990823558)
		(_use )
	)
	(_timescale 1ns 1ns)
	(_parameters    dbg   accs  )
	(_attribute )
	(_object
		(_port (_internal RVALVECTLw ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal RVALVEHIGHr ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal RVALVELOWr ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal RVALVESTATr ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal data ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal SSclk ~wire 0 32 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal clk ~wire 0 32 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal reset ~wire 0 32 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_type (_internal ~[7:0]wire~ 0 32 (_array ~wire ((_downto (i 7) (i 0))))))
		(_port (_internal outDATA ~[7:0]wire~ 0 32 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET1330 ~wire 0 55 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET843 ~wire 0 56 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_type (_internal ~[5:0]wire~ 0 57 (_array ~wire ((_downto (i 5) (i 0))))))
		(_signal (_internal SSclkb ~[5:0]wire~ 0 57 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_subprogram
			

		)
		(_type (_external ~wire (vl verilog_logic wire)))
		(_type (_external ~reg (vl verilog_logic reg)))
		(_type (_external ~event (vl verilog_logic event)))
		(_type (_external ~wand (vl verilog_logic wand)))
		(_type (_external ~wor (vl verilog_logic wor)))
		(_type (_external ~tri1 (vl verilog_logic tri1)))
		(_type (_external ~tri0 (vl verilog_logic tri0)))
		(_type (_external ~trireg (vl verilog_logic trireg)))
		(_type (_external ~supply0 (vl verilog_logic supply0)))
		(_type (_external ~supply1 (vl verilog_logic supply1)))
		(_type (_external ~real (vl verilog_logic real)))
		(_type (_external ~realtime (vl verilog_logic realtime)))
		(_type (_external ~tri (vl verilog_logic tri)))
		(_type (_external ~triand (vl verilog_logic triand)))
		(_type (_external ~trior (vl verilog_logic trior)))
		(_type (_external ~bit (vl verilog_logic bit)))
		(_type (_external ~extstd.standard.integer (std standard integer)))
		(_type (_external ~extstd.standard.bit (std standard bit)))
		(_process
			(#ASSIGN#98_0 (_architecture 0 0 98 (_process (_alias ((SSclk)(SSclkb(1))))(_simple)
				(_target(5))
				(_sensitivity(11(1)))
			)))
		)
	)
	
	
	(_defparam
	)
	(_scope
	)
	(_instantiation U3 0 61 (_entity .  EncoderEngine)
		(_port
			((DAV) (NET1330))
			((SSclkb) (SSclkb))
			((clk) (clk))
			((data) (data))
			((reset) (reset))
			((shift) (NET843))
			((start) (RVALVECTLw))
		)
		(_strength strong0 strong1)
	)
	(_instantiation U4 0 74 (_entity .  Shifter)
		(_port
			((Pdata) (outDATA))
			((RVALVEHIGHr) (RVALVEHIGHr))
			((RVALVELOWr) (RVALVELOWr))
			((clk) (clk))
			((data) (data))
			((reset) (reset))
			((shift) (NET843))
		)
		(_strength strong0 strong1)
	)
	(_instantiation U5 0 87 (_entity .  DAVctl)
		(_port
			((DAVin) (NET1330))
			((Pdata) (outDATA))
			((RVALVESTATr) (RVALVESTATr))
		)
		(_strength strong0 strong1)
	)
	(_model . reader 2 -1)

)
V 000047 55 4287          1079992000075 reader
(_unit VERILOG 6.349C.6.256 (reader 0 32 (reader 0 32 ))
	(_version v32)
	(_time 1079991999980 2004.03.22 13:46:39)
	(_source (\./compile/reader.v\ VERILOG (\./compile/reader.v\ VERILOG)))
	(_use (std(standard))(vl(verilog_logic)))
	(_base (E 2))
	(_entity
		(_time 1079991999980)
		(_use )
	)
	(_timescale 1ns 1ns)
	(_parameters    dbg   accs  )
	(_attribute )
	(_object
		(_port (_internal RVALVECTLw ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal RVALVEHIGHr ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal RVALVELOWr ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal RVALVESTATr ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal data ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal SSclk ~wire 0 32 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal clk ~wire 0 32 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal reset ~wire 0 32 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_type (_internal ~[7:0]wire~ 0 32 (_array ~wire ((_downto (i 7) (i 0))))))
		(_port (_internal outDATA ~[7:0]wire~ 0 32 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET1330 ~wire 0 55 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET843 ~wire 0 56 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_type (_internal ~[5:0]wire~ 0 57 (_array ~wire ((_downto (i 5) (i 0))))))
		(_signal (_internal SSclkb ~[5:0]wire~ 0 57 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_subprogram
			

		)
		(_type (_external ~wire (vl verilog_logic wire)))
		(_type (_external ~reg (vl verilog_logic reg)))
		(_type (_external ~event (vl verilog_logic event)))
		(_type (_external ~wand (vl verilog_logic wand)))
		(_type (_external ~wor (vl verilog_logic wor)))
		(_type (_external ~tri1 (vl verilog_logic tri1)))
		(_type (_external ~tri0 (vl verilog_logic tri0)))
		(_type (_external ~trireg (vl verilog_logic trireg)))
		(_type (_external ~supply0 (vl verilog_logic supply0)))
		(_type (_external ~supply1 (vl verilog_logic supply1)))
		(_type (_external ~real (vl verilog_logic real)))
		(_type (_external ~realtime (vl verilog_logic realtime)))
		(_type (_external ~tri (vl verilog_logic tri)))
		(_type (_external ~triand (vl verilog_logic triand)))
		(_type (_external ~trior (vl verilog_logic trior)))
		(_type (_external ~bit (vl verilog_logic bit)))
		(_type (_external ~extstd.standard.integer (std standard integer)))
		(_type (_external ~extstd.standard.bit (std standard bit)))
		(_process
			(#ASSIGN#98_0 (_architecture 0 0 98 (_process (_alias ((SSclk)(SSclkb(1))))(_simple)
				(_target(5))
				(_sensitivity(11(1)))
			)))
		)
	)
	
	
	(_defparam
	)
	(_scope
	)
	(_instantiation U3 0 61 (_entity .  EncoderEngine)
		(_port
			((DAV) (NET1330))
			((SSclkb) (SSclkb))
			((clk) (clk))
			((data) (data))
			((reset) (reset))
			((shift) (NET843))
			((start) (RVALVECTLw))
		)
		(_strength strong0 strong1)
	)
	(_instantiation U4 0 74 (_entity .  Shifter)
		(_port
			((Pdata) (outDATA))
			((RVALVEHIGHr) (RVALVEHIGHr))
			((RVALVELOWr) (RVALVELOWr))
			((clk) (clk))
			((data) (data))
			((reset) (reset))
			((shift) (NET843))
		)
		(_strength strong0 strong1)
	)
	(_instantiation U5 0 87 (_entity .  DAVctl)
		(_port
			((DAVin) (NET1330))
			((Pdata) (outDATA))
			((RVALVESTATr) (RVALVESTATr))
		)
		(_strength strong0 strong1)
	)
	(_model . reader 2 -1)

)
V 000044 55 23481         1079992059058 U21
(_unit VERILOG 6.349C.6.256 (U21 0 32 (U21 0 32 ))
	(_version v32)
	(_time 1079992058965 2004.03.22 13:47:38)
	(_source (\./compile/u21.v\ VERILOG (\./compile/u21.v\ VERILOG)))
	(_use (std(standard))(vl(verilog_logic)))
	(_base (E 13))
	(_entity
		(_time 1079992058965)
		(_use )
	)
	(_timescale 1ns 1ns)
	(_parameters    dbg   accs  )
	(_attribute )
	(_object
		(_type (_internal ~vector~0 0 190 (_array ~bit ((_uto (i 0) (i 0))))))
		(_generic (_internal DANGLING_INPUT_CONSTANT ~vector~0 0 190 \1'bZ\ (_entity -1 (_constant \1'bZ\))))
		(_port (_internal AS ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Brake0 ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Brake1 ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal DIR0 ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal DIR1 ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Enc033FLG ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Enc05FLG ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Enc133FLG ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Enc15FLG ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal FLS0 ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal FLS1 ~wire 0 33 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal GP_Motor0_0 ~wire 0 33 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal GP_Motor1_0 ~wire 0 33 (_architecture (_in ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal HSI ~wire 0 33 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal Home0 ~wire 0 33 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Home033FLG ~wire 0 33 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Home05FLG ~wire 0 33 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Home1 ~wire 0 33 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Home133FLG ~wire 0 33 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Home15FLG ~wire 0 33 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal INTbus ~wire 0 34 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal LightSense ~wire 0 34 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal MHSO ~wire 0 34 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal Mclk ~wire 0 34 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PWM1 ~wire 0 34 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PWM2 ~wire 0 34 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PhaseA_Encoder0 ~wire 0 34 (_architecture (_in ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PhaseA_Encoder1 ~wire 0 34 (_architecture (_in ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PhaseB_Encoder0 ~wire 0 34 (_architecture (_in ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PhaseB_Encoder1 ~wire 0 34 (_architecture (_in ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal RD ~wire 0 35 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal RLS0 ~wire 0 35 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal RLS1 ~wire 0 35 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Reset ~wire 0 35 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal SCLinc ~wire 0 35 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal SCLreset ~wire 0 35 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal TXI ~wire 0 35 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal WR ~wire 0 35 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_type (_internal ~[5:0]wire~ 0 35 (_array ~wire ((_downto (i 5) (i 0))))))
		(_port (_internal I2CS ~[5:0]wire~ 0 35 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Enc033ctrl ~wire 0 35 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Enc05ctrl ~wire 0 36 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Enc133ctrl ~wire 0 36 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Enc15ctrl ~wire 0 36 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal GP_Motor0_1 ~wire 0 36 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal GP_Motor1_1 ~wire 0 36 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal HSO ~wire 0 36 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal Home033ctrl ~wire 0 36 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Home05ctrl ~wire 0 36 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Home133ctrl ~wire 0 36 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Home15ctrl ~wire 0 36 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal INT ~wire 0 37 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal LED1 ~wire 0 37 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal LED2 ~wire 0 37 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal LED3 ~wire 0 37 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal LED4 ~wire 0 37 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal LED5 ~wire 0 37 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal MHSI ~wire 0 37 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal MTRpwr ~wire 0 37 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal MTRpwrn ~wire 0 37 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal MTXI ~wire 0 37 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal PAH0 ~wire 0 38 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PAH1 ~wire 0 38 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PAL0 ~wire 0 38 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PAL1 ~wire 0 38 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PBH0 ~wire 0 38 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PBH1 ~wire 0 38 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PBL0 ~wire 0 38 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PBL1 ~wire 0 38 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal TP10 ~wire 0 38 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal TP11 ~wire 0 38 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal TP12 ~wire 0 39 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal SCL ~wire 0 39 (_architecture (_inout ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_type (_internal ~[7:0]wire~ 0 39 (_array ~wire ((_downto (i 7) (i 0))))))
		(_port (_internal AD ~[7:0]wire~ 0 39 (_architecture (_inout ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET1635 ~wire 0 193 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET1643 ~wire 0 194 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET1651 ~wire 0 195 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET1667 ~wire 0 196 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET1978 ~wire 0 197 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET1989 ~wire 0 198 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET2017 ~wire 0 199 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET2025 ~wire 0 200 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET2036 ~wire 0 201 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET2047 ~wire 0 202 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET2064 ~wire 0 203 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET2078 ~wire 0 204 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET2311 ~wire 0 205 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET2528 ~wire 0 206 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET2539 ~wire 0 207 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET2575 ~wire 0 208 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET3248 ~wire 0 209 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET3253 ~wire 0 210 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET3919 ~wire 0 211 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal NET3926 ~wire 0 212 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal NET5008 ~wire 0 213 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET615 ~wire 0 214 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal NET621 ~wire 0 215 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal NET629 ~wire 0 216 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal BUS1564 ~[7:0]wire~ 0 217 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal BUS5075 ~[7:0]wire~ 0 218 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal outDATA ~[7:0]wire~ 0 219 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal Dangling_Input_Signal ~wire 0 222 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_subprogram
			

		)
		(_type (_external ~wire (vl verilog_logic wire)))
		(_type (_external ~reg (vl verilog_logic reg)))
		(_type (_external ~event (vl verilog_logic event)))
		(_type (_external ~wand (vl verilog_logic wand)))
		(_type (_external ~wor (vl verilog_logic wor)))
		(_type (_external ~tri1 (vl verilog_logic tri1)))
		(_type (_external ~tri0 (vl verilog_logic tri0)))
		(_type (_external ~trireg (vl verilog_logic trireg)))
		(_type (_external ~supply0 (vl verilog_logic supply0)))
		(_type (_external ~supply1 (vl verilog_logic supply1)))
		(_type (_external ~real (vl verilog_logic real)))
		(_type (_external ~realtime (vl verilog_logic realtime)))
		(_type (_external ~tri (vl verilog_logic tri)))
		(_type (_external ~triand (vl verilog_logic triand)))
		(_type (_external ~trior (vl verilog_logic trior)))
		(_type (_external ~bit (vl verilog_logic bit)))
		(_type (_external ~extstd.standard.integer (std standard integer)))
		(_type (_external ~extstd.standard.bit (std standard bit)))
		(_process
			(#ASSIGN#222_0 (_architecture 0 0 222 (_process (_simple)
				(_target(100))
			)))
			(#ASSIGN#421_1 (_architecture 1 0 421 (_process (_alias ((NET3919)(SCLreset)))(_simple)
				(_target(91))
				(_sensitivity(35))
			)))
			(#ASSIGN#422_2 (_architecture 2 0 422 (_process (_alias ((NET3926)(SCLinc)))(_simple)
				(_target(92))
				(_sensitivity(34))
			)))
			(#ASSIGN#423_3 (_architecture 3 0 423 (_process (_alias ((NET615)(MHSO)))(_simple)
				(_target(94))
				(_sensitivity(22))
			)))
			(#ASSIGN#424_4 (_architecture 4 0 424 (_process (_alias ((NET621)(HSI)))(_simple)
				(_target(95))
				(_sensitivity(13))
			)))
			(#ASSIGN#425_5 (_architecture 5 0 425 (_process (_alias ((NET629)(TXI)))(_simple)
				(_target(96))
				(_sensitivity(36))
			)))
			(#ASSIGN#428_6 (_architecture 6 0 428 (_process (_alias ((HSO)(NET615)))(_simple)
				(_target(45))
				(_sensitivity(94))
			)))
			(#ASSIGN#429_7 (_architecture 7 0 429 (_process (_alias ((MHSI)(NET621)))(_simple)
				(_target(56))
				(_sensitivity(95))
			)))
			(#ASSIGN#430_8 (_architecture 8 0 430 (_process (_alias ((MTXI)(NET629)))(_simple)
				(_target(59))
				(_sensitivity(96))
			)))
			(#ASSIGN#431_9 (_architecture 9 0 431 (_process (_alias ((TP10)(NET3919)))(_simple)
				(_target(68))
				(_sensitivity(91))
			)))
			(#ASSIGN#432_10 (_architecture 10 0 432 (_process (_alias ((TP11)(NET3926)))(_simple)
				(_target(69))
				(_sensitivity(92))
			)))
			(#ASSIGN#433_11 (_architecture 11 0 433 (_process (_alias ((TP12)(SCL)))(_simple)
				(_target(70))
				(_sensitivity(71))
			)))
			(#INTERNAL#0_12 (_internal 12 0 0 (_process (_virtual))))
		)
	)
	
	
	(_defparam
	)
	(_scope
	)
	(_instantiation U1 0 226 (_entity .  reader)
		(_port
			((RVALVECTLw) (NET1635))
			((RVALVEHIGHr) (NET1643))
			((RVALVELOWr) (NET1651))
			((RVALVESTATr) (NET1667))
			((SSclk) (GP_Motor0_1))
			((data) (GP_Motor0_0))
			((outDATA) (outDATA))
			((clk) (_open))
			((reset) (_open))
		)
		(_strength strong0 strong1)
	)
	(_instantiation U11 0 239 (_entity .  I2Cfix)
		(_port
			((DCORI2CCNTr) (NET2311))
			((Inc) (NET3926))
			((Mclk) (Mclk))
			((SCL) (SCL))
			((SCLint) (NET2539))
			((SCLreset) (NET3919))
			((outDATA) (outDATA))
			((SCLenable) (_open))
		)
		(_strength strong0 strong1)
	)
	(_instantiation U12 0 252 (_entity .  U21AddDecode)
		(_port
			((ADDR) (BUS1564))
			((AS) (AS))
			((DCOR0CNTHIGHr) (NET1667))
			((DCOR0CNTLOWr) (NET1651))
			((DCOR0CNTMIDr) (NET1643))
			((DCORCONFIGr) (NET2064))
			((DCORENCCTLw) (NET1635))
			((DCORENCPWRr) (NET2036))
			((DCORENCPWRw) (NET2025))
			((DCORI2CCNTr) (NET2311))
			((DCORIEw) (NET2078))
			((DCORIFGr) (NET1978))
			((DCORIFGw) (NET1989))
			((DCORLIMITSr) (NET2047))
			((DCOROUTw) (NET2017))
			((RD) (RD))
			((WR) (WR))
			((DCOR0THRESLOWr) (_open))
			((DCOR1CNTLOWr) (_open))
			((DCOR1THRESLOWr) (_open))
			((DCOR0THRESMIDr) (_open))
			((DCOR1CNTMIDr) (_open))
			((DCOR1THRESMIDr) (_open))
			((DCOR1CNTHIGHr) (_open))
		)
		(_strength strong0 strong1)
	)
	(_instantiation U2 0 275 (_entity .  Interface)
		(_port
			((AD) (AD))
			((ADDR) (BUS1564))
			((AS) (AS))
			((Mclk) (Mclk))
			((RD) (RD))
			((Reset) (Reset))
			((WR) (WR))
			((inDATA) (BUS5075))
			((outDATA) (outDATA))
			((ASleading) (_open))
		)
		(_strength strong0 strong1)
	)
	(_instantiation U3 0 290 (_entity .  Interrupt)
		(_port
			((BusInt) (INTbus))
			((DCORIEw) (NET2078))
			((Homed0) (Dangling_Input_Signal))
			((Homed1) (Dangling_Input_Signal))
			((I2Cint) (NET2539))
			((INT) (INT))
			((LSwitchInt) (NET2575))
			((Mclk) (Mclk))
			((PWRint) (NET2528))
			((Reset) (Reset))
			((Thres0) (Dangling_Input_Signal))
			((Thres1) (Dangling_Input_Signal))
			((inDATA) (BUS5075))
		)
		(_strength strong0 strong1)
	)
	(_instantiation U4 0 309 (_entity .  PWRreg)
		(_port
			((DCORENCPWRr) (NET2036))
			((DCORENCPWRw) (NET2025))
			((DCORIFGr) (NET1978))
			((DCORIFGw) (NET1989))
			((Enc033ctl) (Home15ctrl))
			((Enc033flg) (Enc033FLG))
			((Enc05ctl) (Home133ctrl))
			((Enc05flg) (Enc05FLG))
			((Enc133ctl) (Home05ctrl))
			((Enc133flg) (Enc133FLG))
			((Enc15ctl) (Home033ctrl))
			((Enc15flg) (Enc15FLG))
			((Hme033ctl) (Enc15ctrl))
			((Hme033flg) (Home033FLG))
			((Hme05ctl) (Enc133ctrl))
			((Hme05flg) (Home05FLG))
			((Hme133ctl) (Enc05ctrl))
			((Hme133flg) (Home133FLG))
			((Hme15ctl) (Enc033ctrl))
			((Hme15flg) (Home15FLG))
			((Mclk) (Mclk))
			((PWRint) (NET2528))
			((Reset) (Reset))
			((inDATA) (BUS5075))
			((outDATA) (outDATA))
		)
		(_strength strong0 strong1)
	)
	(_instantiation U5 0 340 (_entity .  Lswitch)
		(_port
			((Brake0) (Brake0))
			((Brake1) (Brake1))
			((DCORIFGr) (NET1978))
			((DCORIFGw) (NET1989))
			((DCORLIMITSr) (NET2047))
			((DIR0) (DIR0))
			((DIR1) (DIR1))
			((FLS0) (FLS0))
			((FLS1) (FLS1))
			((Home0) (Home0))
			((Home1) (Home1))
			((LSwitchInt) (NET2575))
			((Mclk) (Mclk))
			((RLS0) (RLS0))
			((RLS1) (RLS1))
			((Reset) (Reset))
			((fBRK0) (NET3248))
			((fBRK1) (NET3253))
			((inDATA) (BUS5075))
			((outDATA) (outDATA))
		)
		(_strength strong0 strong1)
	)
	(_instantiation U6 0 366 (_entity .  I2CAddress)
		(_port
			((DCORCONFIGr) (NET2064))
			((I2CS) (I2CS))
			((MotorIn0) (GP_Motor0_0))
			((MotorIn1) (NET5008))
			((outDATA) (outDATA))
		)
		(_strength strong0 strong1)
	)
	(_instantiation U7 0 377 (_entity .  PWMcontrol)
		(_port
			((Brake1) (Brake0))
			((Brake2) (Brake1))
			((DIR1) (DIR0))
			((DIR2) (DIR1))
			((HBRK1) (NET3248))
			((HBRK2) (NET3253))
			((PAH1) (PAH0))
			((PAH2) (PBL1))
			((PAL1) (PAL0))
			((PAL2) (PBH1))
			((PBH1) (PBH0))
			((PBH2) (PAL1))
			((PBL1) (PBL0))
			((PBL2) (PAH1))
			((PWM1) (PWM1))
			((PWM2) (PWM2))
			((fBRK1) (NET3248))
			((fBRK2) (NET3253))
		)
		(_strength strong0 strong1)
	)
	(_instantiation U9 0 401 (_entity .  MISCouts)
		(_port
			((DCOROUTw) (NET2017))
			((LED1) (LED1))
			((LED2) (LED2))
			((LED3) (LED3))
			((LED4) (LED4))
			((LED5) (LED5))
			((LightSense) (LightSense))
			((MTRpwr) (MTRpwr))
			((MTRpwrn) (MTRpwrn))
			((Mclk) (Mclk))
			((Reset) (Reset))
			((inDATA) (BUS5075))
			((GP_Motor0_1) (_open))
			((GP_Motor1_1) (_open))
		)
		(_strength strong0 strong1)
	)
	(_model . U21 13 -1)

)
V 000054 55 3721          1079992157981 EncoderEngine
(_unit VERILOG 6.349C.6.256 (EncoderEngine 0 23 (EncoderEngine 0 23 ))
	(_version v32)
	(_time 1079992157902 2004.03.22 13:49:17)
	(_source (\./compile/encoderengine.v\ VERILOG (\./compile/encoderengine.v\ VERILOG)))
	(_use (std(standard))(vl(verilog_logic)))
	(_base (E 5))
	(_entity
		(_time 1079992157902)
		(_use )
	)
	(_timescale 1ns 1ps)
	(_parameters    dbg   accs  )
	(_attribute nb_assign )
	(_object
		(_port (_internal DAV ~reg 0 23 (_architecture (_out ))) (_reg ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_type (_internal ~[5:0]reg~ 0 23 (_array ~reg ((_downto (i 5) (i 0))))))
		(_port (_internal SSclkb ~[5:0]reg~ 0 23 (_architecture (_out ))) (_reg ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal clk ~wire 0 23 (_architecture (_in ))) (_net  ) (_nonbaction) (_noforceassign))
		(_port (_internal data ~wire 0 23 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal reset ~wire 0 23 (_architecture (_in ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal shift ~reg 0 23 (_architecture (_out ))) (_reg ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal start ~wire 0 23 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal next_DAV ~reg 0 32 (_architecture (_uni ))) (_reg ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal next_shift ~reg 0 37 (_architecture (_uni ))) (_reg ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal CurrState_Sreg0 ~[5:0]reg~ 0 83 (_architecture (_uni ))) (_reg ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal NextState_Sreg0 ~[5:0]reg~ 0 85 (_architecture (_uni ))) (_reg ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_subprogram
			

		)
		(_type (_external ~wire (vl verilog_logic wire)))
		(_type (_external ~reg (vl verilog_logic reg)))
		(_type (_external ~event (vl verilog_logic event)))
		(_type (_external ~wand (vl verilog_logic wand)))
		(_type (_external ~wor (vl verilog_logic wor)))
		(_type (_external ~tri1 (vl verilog_logic tri1)))
		(_type (_external ~tri0 (vl verilog_logic tri0)))
		(_type (_external ~trireg (vl verilog_logic trireg)))
		(_type (_external ~supply0 (vl verilog_logic supply0)))
		(_type (_external ~supply1 (vl verilog_logic supply1)))
		(_type (_external ~real (vl verilog_logic real)))
		(_type (_external ~realtime (vl verilog_logic realtime)))
		(_type (_external ~tri (vl verilog_logic tri)))
		(_type (_external ~triand (vl verilog_logic triand)))
		(_type (_external ~trior (vl verilog_logic trior)))
		(_type (_external ~bit (vl verilog_logic bit)))
		(_type (_external ~extstd.standard.integer (std standard integer)))
		(_type (_external ~extstd.standard.bit (std standard bit)))
		(_process
			(#ALWAYS#97_0 (_architecture 0 0 97 (_process 
				(_target(10)(7)(8))
				(_read)
				(_sensitivity(0)(6)(3)(5)(9))
			)))
			(#ALWAYS#354_1 (_architecture 1 0 354 (_process 
				(_target(9))
				(_read(2)(4)(10))
			)))
			(#ALWAYS#365_2 (_architecture 2 0 365 (_process 
				(_target(0)(5))
				(_read(2)(4)(7)(8))
			)))
			(#ALWAYS#380_3 (_architecture 3 0 380 (_process 
				(_target(1))
				(_read)
				(_sensitivity(9))
			)))
		)
	)
	
	
	(_defparam
	)
	(_scope
		(_unit Sreg0_NextState begin 0 98
		)
		(_unit Sreg0_CurrentState begin 0 355
		)
		(_unit Sreg0_RegOutput begin 0 366
		)
	)
	(_model . EncoderEngine 5 -1)

)
I 000048 55 2955          1079992190761 Shifter
(_unit VERILOG 6.349C.6.256 (Shifter 0 25 (Shifter 0 25 ))
	(_version v32)
	(_time 1079992190699 2004.03.22 13:49:50)
	(_source (\./src/shifter.v\ VERILOG (\./src/shifter.v\ VERILOG)))
	(_use (std(standard))(vl(verilog_logic)))
	(_base (E 3))
	(_entity
		(_time 1079992190699)
		(_use )
	)
	(_parameters    dbg   accs  )
	(_attribute nb_assign )
	(_object
		(_type (_internal ~[7:0]wire~ 0 25 (_array ~wire ((_downto (i 7) (i 0))))))
		(_port (_internal Pdata ~[7:0]wire~ 0 25 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal RVALVEHIGHr ~wire 0 25 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal data ~wire 0 25 (_architecture (_in ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal clk ~wire 0 25 (_architecture (_in ))) (_net  ) (_nonbaction) (_noforceassign))
		(_port (_internal reset ~wire 0 25 (_architecture (_in ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal RVALVELOWr ~wire 0 25 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal shift ~wire 0 25 (_architecture (_in ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_type (_internal ~[8:0]reg~ 0 47 (_array ~reg ((_downto (i 8) (i 0))))))
		(_signal (_internal Pdatar ~[8:0]reg~ 0 47 (_architecture (_uni ))) (_reg ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_subprogram
			

		)
		(_type (_external ~wire (vl verilog_logic wire)))
		(_type (_external ~reg (vl verilog_logic reg)))
		(_type (_external ~event (vl verilog_logic event)))
		(_type (_external ~wand (vl verilog_logic wand)))
		(_type (_external ~wor (vl verilog_logic wor)))
		(_type (_external ~tri1 (vl verilog_logic tri1)))
		(_type (_external ~tri0 (vl verilog_logic tri0)))
		(_type (_external ~trireg (vl verilog_logic trireg)))
		(_type (_external ~supply0 (vl verilog_logic supply0)))
		(_type (_external ~supply1 (vl verilog_logic supply1)))
		(_type (_external ~real (vl verilog_logic real)))
		(_type (_external ~realtime (vl verilog_logic realtime)))
		(_type (_external ~tri (vl verilog_logic tri)))
		(_type (_external ~triand (vl verilog_logic triand)))
		(_type (_external ~trior (vl verilog_logic trior)))
		(_type (_external ~bit (vl verilog_logic bit)))
		(_type (_external ~extstd.standard.integer (std standard integer)))
		(_type (_external ~extstd.standard.bit (std standard bit)))
		(_process
			(#ASSIGN#50_0 (_architecture 0 0 50 (_process (_simple)
				(_target(0))
				(_sensitivity(1)(7(8))(5)(7(d_7_0)))
			)))
			(#ALWAYS#52_1 (_architecture 1 0 52 (_process 
				(_target(7))
				(_read(3)(4)(6)(7(d_7_0))(2)(7))
			)))
		)
	)
	
	
	(_defparam
	)
	(_model . Shifter 3 -1)

)
I 000047 55 2043          1079992217403 DAVctl
(_unit VERILOG 6.349C.6.256 (DAVctl 0 25 (DAVctl 0 25 ))
	(_version v32)
	(_time 1079992217355 2004.03.22 13:50:17)
	(_source (\./src/davctl.v\ VERILOG (\./src/davctl.v\ VERILOG)))
	(_use (std(standard))(vl(verilog_logic)))
	(_base (E 2))
	(_entity
		(_time 1079992217355)
		(_use )
	)
	(_parameters    dbg   accs  )
	(_attribute )
	(_object
		(_type (_internal ~[7:0]wire~ 0 25 (_array ~wire ((_downto (i 7) (i 0))))))
		(_port (_internal Pdata ~[7:0]wire~ 0 25 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal DAVin ~wire 0 25 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal RVALVESTATr ~wire 0 25 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_subprogram
			

		)
		(_type (_external ~wire (vl verilog_logic wire)))
		(_type (_external ~reg (vl verilog_logic reg)))
		(_type (_external ~event (vl verilog_logic event)))
		(_type (_external ~wand (vl verilog_logic wand)))
		(_type (_external ~wor (vl verilog_logic wor)))
		(_type (_external ~tri1 (vl verilog_logic tri1)))
		(_type (_external ~tri0 (vl verilog_logic tri0)))
		(_type (_external ~trireg (vl verilog_logic trireg)))
		(_type (_external ~supply0 (vl verilog_logic supply0)))
		(_type (_external ~supply1 (vl verilog_logic supply1)))
		(_type (_external ~real (vl verilog_logic real)))
		(_type (_external ~realtime (vl verilog_logic realtime)))
		(_type (_external ~tri (vl verilog_logic tri)))
		(_type (_external ~triand (vl verilog_logic triand)))
		(_type (_external ~trior (vl verilog_logic trior)))
		(_type (_external ~bit (vl verilog_logic bit)))
		(_type (_external ~extstd.standard.integer (std standard integer)))
		(_type (_external ~extstd.standard.bit (std standard bit)))
		(_process
			(#ASSIGN#39_0 (_architecture 0 0 39 (_process (_simple)
				(_target(0))
				(_sensitivity(2)(1))
			)))
		)
	)
	
	
	(_defparam
	)
	(_model . DAVctl 2 -1)

)
V 000047 55 4287          1079992229058 reader
(_unit VERILOG 6.349C.6.256 (reader 0 32 (reader 0 32 ))
	(_version v32)
	(_time 1079992228996 2004.03.22 13:50:28)
	(_source (\./compile/reader.v\ VERILOG (\./compile/reader.v\ VERILOG)))
	(_use (std(standard))(vl(verilog_logic)))
	(_base (E 2))
	(_entity
		(_time 1079992228996)
		(_use )
	)
	(_timescale 1ns 1ns)
	(_parameters    dbg   accs  )
	(_attribute )
	(_object
		(_port (_internal RVALVECTLw ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal RVALVEHIGHr ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal RVALVELOWr ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal RVALVESTATr ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal data ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal SSclk ~wire 0 32 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal clk ~wire 0 32 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal reset ~wire 0 32 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_type (_internal ~[7:0]wire~ 0 32 (_array ~wire ((_downto (i 7) (i 0))))))
		(_port (_internal outDATA ~[7:0]wire~ 0 32 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET1330 ~wire 0 55 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET843 ~wire 0 56 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_type (_internal ~[5:0]wire~ 0 57 (_array ~wire ((_downto (i 5) (i 0))))))
		(_signal (_internal SSclkb ~[5:0]wire~ 0 57 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_subprogram
			

		)
		(_type (_external ~wire (vl verilog_logic wire)))
		(_type (_external ~reg (vl verilog_logic reg)))
		(_type (_external ~event (vl verilog_logic event)))
		(_type (_external ~wand (vl verilog_logic wand)))
		(_type (_external ~wor (vl verilog_logic wor)))
		(_type (_external ~tri1 (vl verilog_logic tri1)))
		(_type (_external ~tri0 (vl verilog_logic tri0)))
		(_type (_external ~trireg (vl verilog_logic trireg)))
		(_type (_external ~supply0 (vl verilog_logic supply0)))
		(_type (_external ~supply1 (vl verilog_logic supply1)))
		(_type (_external ~real (vl verilog_logic real)))
		(_type (_external ~realtime (vl verilog_logic realtime)))
		(_type (_external ~tri (vl verilog_logic tri)))
		(_type (_external ~triand (vl verilog_logic triand)))
		(_type (_external ~trior (vl verilog_logic trior)))
		(_type (_external ~bit (vl verilog_logic bit)))
		(_type (_external ~extstd.standard.integer (std standard integer)))
		(_type (_external ~extstd.standard.bit (std standard bit)))
		(_process
			(#ASSIGN#98_0 (_architecture 0 0 98 (_process (_alias ((SSclk)(SSclkb(1))))(_simple)
				(_target(5))
				(_sensitivity(11(1)))
			)))
		)
	)
	
	
	(_defparam
	)
	(_scope
	)
	(_instantiation U3 0 61 (_entity .  EncoderEngine)
		(_port
			((DAV) (NET1330))
			((SSclkb) (SSclkb))
			((clk) (clk))
			((data) (data))
			((reset) (reset))
			((shift) (NET843))
			((start) (RVALVECTLw))
		)
		(_strength strong0 strong1)
	)
	(_instantiation U4 0 74 (_entity .  Shifter)
		(_port
			((Pdata) (outDATA))
			((RVALVEHIGHr) (RVALVEHIGHr))
			((RVALVELOWr) (RVALVELOWr))
			((clk) (clk))
			((data) (data))
			((reset) (reset))
			((shift) (NET843))
		)
		(_strength strong0 strong1)
	)
	(_instantiation U5 0 87 (_entity .  DAVctl)
		(_port
			((DAVin) (NET1330))
			((Pdata) (outDATA))
			((RVALVESTATr) (RVALVESTATr))
		)
		(_strength strong0 strong1)
	)
	(_model . reader 2 -1)

)
V 000044 55 23481         1079992261512 U21
(_unit VERILOG 6.349C.6.256 (U21 0 32 (U21 0 32 ))
	(_version v32)
	(_time 1079992261433 2004.03.22 13:51:01)
	(_source (\./compile/u21.v\ VERILOG (\./compile/u21.v\ VERILOG)))
	(_use (std(standard))(vl(verilog_logic)))
	(_base (E 13))
	(_entity
		(_time 1079992261433)
		(_use )
	)
	(_timescale 1ns 1ns)
	(_parameters    dbg   accs  )
	(_attribute )
	(_object
		(_type (_internal ~vector~0 0 190 (_array ~bit ((_uto (i 0) (i 0))))))
		(_generic (_internal DANGLING_INPUT_CONSTANT ~vector~0 0 190 \1'bZ\ (_entity -1 (_constant \1'bZ\))))
		(_port (_internal AS ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Brake0 ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Brake1 ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal DIR0 ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal DIR1 ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Enc033FLG ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Enc05FLG ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Enc133FLG ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Enc15FLG ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal FLS0 ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal FLS1 ~wire 0 33 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal GP_Motor0_0 ~wire 0 33 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal GP_Motor1_0 ~wire 0 33 (_architecture (_in ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal HSI ~wire 0 33 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal Home0 ~wire 0 33 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Home033FLG ~wire 0 33 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Home05FLG ~wire 0 33 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Home1 ~wire 0 33 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Home133FLG ~wire 0 33 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Home15FLG ~wire 0 33 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal INTbus ~wire 0 34 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal LightSense ~wire 0 34 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal MHSO ~wire 0 34 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal Mclk ~wire 0 34 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PWM1 ~wire 0 34 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PWM2 ~wire 0 34 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PhaseA_Encoder0 ~wire 0 34 (_architecture (_in ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PhaseA_Encoder1 ~wire 0 34 (_architecture (_in ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PhaseB_Encoder0 ~wire 0 34 (_architecture (_in ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PhaseB_Encoder1 ~wire 0 34 (_architecture (_in ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal RD ~wire 0 35 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal RLS0 ~wire 0 35 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal RLS1 ~wire 0 35 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Reset ~wire 0 35 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal SCLinc ~wire 0 35 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal SCLreset ~wire 0 35 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal TXI ~wire 0 35 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal WR ~wire 0 35 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_type (_internal ~[5:0]wire~ 0 35 (_array ~wire ((_downto (i 5) (i 0))))))
		(_port (_internal I2CS ~[5:0]wire~ 0 35 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Enc033ctrl ~wire 0 35 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Enc05ctrl ~wire 0 36 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Enc133ctrl ~wire 0 36 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Enc15ctrl ~wire 0 36 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal GP_Motor0_1 ~wire 0 36 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal GP_Motor1_1 ~wire 0 36 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal HSO ~wire 0 36 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal Home033ctrl ~wire 0 36 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Home05ctrl ~wire 0 36 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Home133ctrl ~wire 0 36 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Home15ctrl ~wire 0 36 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal INT ~wire 0 37 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal LED1 ~wire 0 37 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal LED2 ~wire 0 37 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal LED3 ~wire 0 37 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal LED4 ~wire 0 37 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal LED5 ~wire 0 37 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal MHSI ~wire 0 37 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal MTRpwr ~wire 0 37 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal MTRpwrn ~wire 0 37 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal MTXI ~wire 0 37 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal PAH0 ~wire 0 38 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PAH1 ~wire 0 38 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PAL0 ~wire 0 38 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PAL1 ~wire 0 38 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PBH0 ~wire 0 38 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PBH1 ~wire 0 38 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PBL0 ~wire 0 38 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PBL1 ~wire 0 38 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal TP10 ~wire 0 38 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal TP11 ~wire 0 38 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal TP12 ~wire 0 39 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal SCL ~wire 0 39 (_architecture (_inout ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_type (_internal ~[7:0]wire~ 0 39 (_array ~wire ((_downto (i 7) (i 0))))))
		(_port (_internal AD ~[7:0]wire~ 0 39 (_architecture (_inout ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET1635 ~wire 0 193 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET1643 ~wire 0 194 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET1651 ~wire 0 195 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET1667 ~wire 0 196 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET1978 ~wire 0 197 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET1989 ~wire 0 198 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET2017 ~wire 0 199 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET2025 ~wire 0 200 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET2036 ~wire 0 201 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET2047 ~wire 0 202 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET2064 ~wire 0 203 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET2078 ~wire 0 204 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET2311 ~wire 0 205 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET2528 ~wire 0 206 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET2539 ~wire 0 207 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET2575 ~wire 0 208 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET3248 ~wire 0 209 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET3253 ~wire 0 210 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET3919 ~wire 0 211 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal NET3926 ~wire 0 212 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal NET5008 ~wire 0 213 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET615 ~wire 0 214 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal NET621 ~wire 0 215 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal NET629 ~wire 0 216 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal BUS1564 ~[7:0]wire~ 0 217 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal BUS5075 ~[7:0]wire~ 0 218 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal outDATA ~[7:0]wire~ 0 219 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal Dangling_Input_Signal ~wire 0 222 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_subprogram
			

		)
		(_type (_external ~wire (vl verilog_logic wire)))
		(_type (_external ~reg (vl verilog_logic reg)))
		(_type (_external ~event (vl verilog_logic event)))
		(_type (_external ~wand (vl verilog_logic wand)))
		(_type (_external ~wor (vl verilog_logic wor)))
		(_type (_external ~tri1 (vl verilog_logic tri1)))
		(_type (_external ~tri0 (vl verilog_logic tri0)))
		(_type (_external ~trireg (vl verilog_logic trireg)))
		(_type (_external ~supply0 (vl verilog_logic supply0)))
		(_type (_external ~supply1 (vl verilog_logic supply1)))
		(_type (_external ~real (vl verilog_logic real)))
		(_type (_external ~realtime (vl verilog_logic realtime)))
		(_type (_external ~tri (vl verilog_logic tri)))
		(_type (_external ~triand (vl verilog_logic triand)))
		(_type (_external ~trior (vl verilog_logic trior)))
		(_type (_external ~bit (vl verilog_logic bit)))
		(_type (_external ~extstd.standard.integer (std standard integer)))
		(_type (_external ~extstd.standard.bit (std standard bit)))
		(_process
			(#ASSIGN#222_0 (_architecture 0 0 222 (_process (_simple)
				(_target(100))
			)))
			(#ASSIGN#421_1 (_architecture 1 0 421 (_process (_alias ((NET3919)(SCLreset)))(_simple)
				(_target(91))
				(_sensitivity(35))
			)))
			(#ASSIGN#422_2 (_architecture 2 0 422 (_process (_alias ((NET3926)(SCLinc)))(_simple)
				(_target(92))
				(_sensitivity(34))
			)))
			(#ASSIGN#423_3 (_architecture 3 0 423 (_process (_alias ((NET615)(MHSO)))(_simple)
				(_target(94))
				(_sensitivity(22))
			)))
			(#ASSIGN#424_4 (_architecture 4 0 424 (_process (_alias ((NET621)(HSI)))(_simple)
				(_target(95))
				(_sensitivity(13))
			)))
			(#ASSIGN#425_5 (_architecture 5 0 425 (_process (_alias ((NET629)(TXI)))(_simple)
				(_target(96))
				(_sensitivity(36))
			)))
			(#ASSIGN#428_6 (_architecture 6 0 428 (_process (_alias ((HSO)(NET615)))(_simple)
				(_target(45))
				(_sensitivity(94))
			)))
			(#ASSIGN#429_7 (_architecture 7 0 429 (_process (_alias ((MHSI)(NET621)))(_simple)
				(_target(56))
				(_sensitivity(95))
			)))
			(#ASSIGN#430_8 (_architecture 8 0 430 (_process (_alias ((MTXI)(NET629)))(_simple)
				(_target(59))
				(_sensitivity(96))
			)))
			(#ASSIGN#431_9 (_architecture 9 0 431 (_process (_alias ((TP10)(NET3919)))(_simple)
				(_target(68))
				(_sensitivity(91))
			)))
			(#ASSIGN#432_10 (_architecture 10 0 432 (_process (_alias ((TP11)(NET3926)))(_simple)
				(_target(69))
				(_sensitivity(92))
			)))
			(#ASSIGN#433_11 (_architecture 11 0 433 (_process (_alias ((TP12)(SCL)))(_simple)
				(_target(70))
				(_sensitivity(71))
			)))
			(#INTERNAL#0_12 (_internal 12 0 0 (_process (_virtual))))
		)
	)
	
	
	(_defparam
	)
	(_scope
	)
	(_instantiation U1 0 226 (_entity .  reader)
		(_port
			((RVALVECTLw) (NET1635))
			((RVALVEHIGHr) (NET1643))
			((RVALVELOWr) (NET1651))
			((RVALVESTATr) (NET1667))
			((SSclk) (GP_Motor0_1))
			((data) (GP_Motor0_0))
			((outDATA) (outDATA))
			((clk) (_open))
			((reset) (_open))
		)
		(_strength strong0 strong1)
	)
	(_instantiation U11 0 239 (_entity .  I2Cfix)
		(_port
			((DCORI2CCNTr) (NET2311))
			((Inc) (NET3926))
			((Mclk) (Mclk))
			((SCL) (SCL))
			((SCLint) (NET2539))
			((SCLreset) (NET3919))
			((outDATA) (outDATA))
			((SCLenable) (_open))
		)
		(_strength strong0 strong1)
	)
	(_instantiation U12 0 252 (_entity .  U21AddDecode)
		(_port
			((ADDR) (BUS1564))
			((AS) (AS))
			((DCOR0CNTHIGHr) (NET1667))
			((DCOR0CNTLOWr) (NET1651))
			((DCOR0CNTMIDr) (NET1643))
			((DCORCONFIGr) (NET2064))
			((DCORENCCTLw) (NET1635))
			((DCORENCPWRr) (NET2036))
			((DCORENCPWRw) (NET2025))
			((DCORI2CCNTr) (NET2311))
			((DCORIEw) (NET2078))
			((DCORIFGr) (NET1978))
			((DCORIFGw) (NET1989))
			((DCORLIMITSr) (NET2047))
			((DCOROUTw) (NET2017))
			((RD) (RD))
			((WR) (WR))
			((DCOR0THRESLOWr) (_open))
			((DCOR1CNTLOWr) (_open))
			((DCOR1THRESLOWr) (_open))
			((DCOR0THRESMIDr) (_open))
			((DCOR1CNTMIDr) (_open))
			((DCOR1THRESMIDr) (_open))
			((DCOR1CNTHIGHr) (_open))
		)
		(_strength strong0 strong1)
	)
	(_instantiation U2 0 275 (_entity .  Interface)
		(_port
			((AD) (AD))
			((ADDR) (BUS1564))
			((AS) (AS))
			((Mclk) (Mclk))
			((RD) (RD))
			((Reset) (Reset))
			((WR) (WR))
			((inDATA) (BUS5075))
			((outDATA) (outDATA))
			((ASleading) (_open))
		)
		(_strength strong0 strong1)
	)
	(_instantiation U3 0 290 (_entity .  Interrupt)
		(_port
			((BusInt) (INTbus))
			((DCORIEw) (NET2078))
			((Homed0) (Dangling_Input_Signal))
			((Homed1) (Dangling_Input_Signal))
			((I2Cint) (NET2539))
			((INT) (INT))
			((LSwitchInt) (NET2575))
			((Mclk) (Mclk))
			((PWRint) (NET2528))
			((Reset) (Reset))
			((Thres0) (Dangling_Input_Signal))
			((Thres1) (Dangling_Input_Signal))
			((inDATA) (BUS5075))
		)
		(_strength strong0 strong1)
	)
	(_instantiation U4 0 309 (_entity .  PWRreg)
		(_port
			((DCORENCPWRr) (NET2036))
			((DCORENCPWRw) (NET2025))
			((DCORIFGr) (NET1978))
			((DCORIFGw) (NET1989))
			((Enc033ctl) (Home15ctrl))
			((Enc033flg) (Enc033FLG))
			((Enc05ctl) (Home133ctrl))
			((Enc05flg) (Enc05FLG))
			((Enc133ctl) (Home05ctrl))
			((Enc133flg) (Enc133FLG))
			((Enc15ctl) (Home033ctrl))
			((Enc15flg) (Enc15FLG))
			((Hme033ctl) (Enc15ctrl))
			((Hme033flg) (Home033FLG))
			((Hme05ctl) (Enc133ctrl))
			((Hme05flg) (Home05FLG))
			((Hme133ctl) (Enc05ctrl))
			((Hme133flg) (Home133FLG))
			((Hme15ctl) (Enc033ctrl))
			((Hme15flg) (Home15FLG))
			((Mclk) (Mclk))
			((PWRint) (NET2528))
			((Reset) (Reset))
			((inDATA) (BUS5075))
			((outDATA) (outDATA))
		)
		(_strength strong0 strong1)
	)
	(_instantiation U5 0 340 (_entity .  Lswitch)
		(_port
			((Brake0) (Brake0))
			((Brake1) (Brake1))
			((DCORIFGr) (NET1978))
			((DCORIFGw) (NET1989))
			((DCORLIMITSr) (NET2047))
			((DIR0) (DIR0))
			((DIR1) (DIR1))
			((FLS0) (FLS0))
			((FLS1) (FLS1))
			((Home0) (Home0))
			((Home1) (Home1))
			((LSwitchInt) (NET2575))
			((Mclk) (Mclk))
			((RLS0) (RLS0))
			((RLS1) (RLS1))
			((Reset) (Reset))
			((fBRK0) (NET3248))
			((fBRK1) (NET3253))
			((inDATA) (BUS5075))
			((outDATA) (outDATA))
		)
		(_strength strong0 strong1)
	)
	(_instantiation U6 0 366 (_entity .  I2CAddress)
		(_port
			((DCORCONFIGr) (NET2064))
			((I2CS) (I2CS))
			((MotorIn0) (GP_Motor0_0))
			((MotorIn1) (NET5008))
			((outDATA) (outDATA))
		)
		(_strength strong0 strong1)
	)
	(_instantiation U7 0 377 (_entity .  PWMcontrol)
		(_port
			((Brake1) (Brake0))
			((Brake2) (Brake1))
			((DIR1) (DIR0))
			((DIR2) (DIR1))
			((HBRK1) (NET3248))
			((HBRK2) (NET3253))
			((PAH1) (PAH0))
			((PAH2) (PBL1))
			((PAL1) (PAL0))
			((PAL2) (PBH1))
			((PBH1) (PBH0))
			((PBH2) (PAL1))
			((PBL1) (PBL0))
			((PBL2) (PAH1))
			((PWM1) (PWM1))
			((PWM2) (PWM2))
			((fBRK1) (NET3248))
			((fBRK2) (NET3253))
		)
		(_strength strong0 strong1)
	)
	(_instantiation U9 0 401 (_entity .  MISCouts)
		(_port
			((DCOROUTw) (NET2017))
			((LED1) (LED1))
			((LED2) (LED2))
			((LED3) (LED3))
			((LED4) (LED4))
			((LED5) (LED5))
			((LightSense) (LightSense))
			((MTRpwr) (MTRpwr))
			((MTRpwrn) (MTRpwrn))
			((Mclk) (Mclk))
			((Reset) (Reset))
			((inDATA) (BUS5075))
			((GP_Motor0_1) (_open))
			((GP_Motor1_1) (_open))
		)
		(_strength strong0 strong1)
	)
	(_model . U21 13 -1)

)
V 000046 55 8545          1079992316855 U4_TB
(_unit VERILOG 6.349C.6.256 (U4_TB 0 32 (U4_TB 0 32 ))
	(_version v32)
	(_time 1079992316793 2004.03.22 13:51:56)
	(_source (\./compile/u21_tb.v\ VERILOG (\./compile/u21_tb.v\ VERILOG)))
	(_use (std(standard))(vl(verilog_logic)))
	(_base (E 3))
	(_entity
		(_time 1079992316793)
		(_use )
	)
	(_timescale 1ns 1ns)
	(_parameters    dbg   accs  )
	(_attribute )
	(_object
		(_type (_internal ~vector~0 0 78 (_array ~bit ((_uto (i 0) (i 0))))))
		(_generic (_internal DANGLING_INPUT_CONSTANT ~vector~0 0 78 \1'bZ\ (_entity -1 (_constant \1'bZ\))))
		(_port (_internal Enc133FLG ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Enc15FLG ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal FLS1 ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal FLS2 ~wire 0 32 (_architecture (_in ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Home1 ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Home133FLG ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Home15FLG ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Home2 ~wire 0 32 (_architecture (_in ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PhaseA_Encoder1 ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PhaseB_Encoder1 ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal RLS1 ~wire 0 33 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal RLS2 ~wire 0 33 (_architecture (_in ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Reset ~wire 0 33 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal SCL ~wire 0 33 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal SCLinc ~wire 0 33 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal SCLreset ~wire 0 33 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Enc133ctrl ~wire 0 33 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Enc15ctrl ~wire 0 33 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Home133ctrl ~wire 0 33 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Home15ctrl ~wire 0 33 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal AS ~wire 0 81 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal Mclk ~wire 0 82 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal RD ~wire 0 83 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal WR ~wire 0 84 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_type (_internal ~[7:0]wire~ 0 85 (_array ~wire ((_downto (i 7) (i 0))))))
		(_signal (_internal AD ~[7:0]wire~ 0 85 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal Dangling_Input_Signal ~wire 0 88 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_type (_internal ~[5:0]wire~ 0 119 (_array ~wire ((_downto (i 5) (i 0))))))
		(_signal (_internal \1 \ ~[5:0]wire~ -1 119 (_internal (_uni ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_subprogram
			

		)
		(_type (_external ~wire (vl verilog_logic wire)))
		(_type (_external ~reg (vl verilog_logic reg)))
		(_type (_external ~event (vl verilog_logic event)))
		(_type (_external ~wand (vl verilog_logic wand)))
		(_type (_external ~wor (vl verilog_logic wor)))
		(_type (_external ~tri1 (vl verilog_logic tri1)))
		(_type (_external ~tri0 (vl verilog_logic tri0)))
		(_type (_external ~trireg (vl verilog_logic trireg)))
		(_type (_external ~supply0 (vl verilog_logic supply0)))
		(_type (_external ~supply1 (vl verilog_logic supply1)))
		(_type (_external ~real (vl verilog_logic real)))
		(_type (_external ~realtime (vl verilog_logic realtime)))
		(_type (_external ~tri (vl verilog_logic tri)))
		(_type (_external ~triand (vl verilog_logic triand)))
		(_type (_external ~trior (vl verilog_logic trior)))
		(_type (_external ~bit (vl verilog_logic bit)))
		(_type (_external ~extstd.standard.integer (std standard integer)))
		(_type (_external ~extstd.standard.bit (std standard bit)))
		(_process
			(#INTERNAL#119_0 (_internal 0 0 119 (_process (_simple)
				(_target(26))
				(_sensitivity(25))
			)))
			(#ASSIGN#88_1 (_architecture 1 0 88 (_process (_simple)
				(_target(25))
			)))
			(#INTERNAL#0_2 (_internal 2 0 0 (_process (_virtual))))
		)
	)
	
	
	(_defparam
	)
	(_scope
	)
	(_instantiation U1 0 92 (_entity .  U21)
		(_port
			((AD) (AD))
			((AS) (AS))
			((Brake0) (Dangling_Input_Signal))
			((Brake1) (Dangling_Input_Signal))
			((DIR0) (Dangling_Input_Signal))
			((DIR1) (Dangling_Input_Signal))
			((Enc033FLG) (Dangling_Input_Signal))
			((Enc05FLG) (Dangling_Input_Signal))
			((Enc133FLG) (Enc133FLG))
			((Enc133ctrl) (Enc133ctrl))
			((Enc15FLG) (Enc15FLG))
			((Enc15ctrl) (Enc15ctrl))
			((FLS0) (Dangling_Input_Signal))
			((FLS1) (FLS1))
			((GP_Motor0_0) (Dangling_Input_Signal))
			((GP_Motor1_0) (Dangling_Input_Signal))
			((HSI) (Dangling_Input_Signal))
			((Home0) (Dangling_Input_Signal))
			((Home033FLG) (Dangling_Input_Signal))
			((Home05FLG) (Dangling_Input_Signal))
			((Home1) (Home1))
			((Home133FLG) (Home133FLG))
			((Home133ctrl) (Home133ctrl))
			((Home15FLG) (Home15FLG))
			((Home15ctrl) (Home15ctrl))
			((I2CS) (\1 \))
			((INTbus) (Dangling_Input_Signal))
			((LightSense) (Dangling_Input_Signal))
			((MHSO) (Dangling_Input_Signal))
			((Mclk) (Mclk))
			((PWM1) (Dangling_Input_Signal))
			((PWM2) (Dangling_Input_Signal))
			((PhaseA_Encoder0) (Dangling_Input_Signal))
			((PhaseA_Encoder1) (PhaseA_Encoder1))
			((PhaseB_Encoder0) (Dangling_Input_Signal))
			((PhaseB_Encoder1) (PhaseB_Encoder1))
			((RD) (RD))
			((RLS0) (Dangling_Input_Signal))
			((RLS1) (RLS1))
			((Reset) (Reset))
			((SCL) (SCL))
			((SCLinc) (SCLinc))
			((SCLreset) (SCLreset))
			((TXI) (Dangling_Input_Signal))
			((WR) (WR))
			((Enc033ctrl) (_open))
			((Enc05ctrl) (_open))
			((GP_Motor0_1) (_open))
			((GP_Motor1_1) (_open))
			((HSO) (_open))
			((Home033ctrl) (_open))
			((Home05ctrl) (_open))
			((INT) (_open))
			((LED1) (_open))
			((LED2) (_open))
			((LED3) (_open))
			((LED4) (_open))
			((LED5) (_open))
			((MHSI) (_open))
			((MTRpwr) (_open))
			((MTRpwrn) (_open))
			((MTXI) (_open))
			((PAH0) (_open))
			((PAH1) (_open))
			((PAL0) (_open))
			((PAL1) (_open))
			((PBH0) (_open))
			((PBH1) (_open))
			((PBL0) (_open))
			((PBL1) (_open))
			((TP10) (_open))
			((TP11) (_open))
			((TP12) (_open))
		)
		(_strength strong0 strong1)
	)
	(_instantiation U2 0 143 (_entity .  MSP)
		(_port
			((AD) (AD))
			((AS) (AS))
			((Mclk) (Mclk))
			((RD) (RD))
			((WR) (WR))
		)
		(_strength strong0 strong1)
	)
	(_model . U4_TB 3 -1)

)
I 000053 55 9137          1079994173778 U21AddDecode
(_unit VERILOG 6.349C.6.256 (U21AddDecode 0 27 (U21AddDecode 0 27 ))
	(_version v32)
	(_time 1079994173699 2004.03.22 14:22:53)
	(_source (\./src/u21adddecode.v\ VERILOG (\./src/u21adddecode.v\ VERILOG)))
	(_use (std(standard))(vl(verilog_logic)))
	(_base (E 22))
	(_entity
		(_time 1079994173699)
		(_use )
	)
	(_timescale 1ps 1ps)
	(_parameters    dbg   accs  )
	(_attribute )
	(_object
		(_port (_internal DCOR0CNTLOWr ~wire 0 27 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal DCOR0THRESLOWr ~wire 0 27 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal DCOR1CNTLOWr ~wire 0 27 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal DCOR1THRESLOWr ~wire 0 27 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal DCORENCPWRr ~wire 0 27 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal WR ~wire 0 27 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal DCOR0CNTMIDr ~wire 0 27 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal DCOR0THRESMIDr ~wire 0 27 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal DCOR1CNTMIDr ~wire 0 27 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal DCOR1THRESMIDr ~wire 0 27 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal DCORLIMITSr ~wire 0 27 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal DCORIEw ~wire 0 27 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal DCORENCPWRw ~wire 0 27 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal DCOR0CNTHIGHr ~wire 0 27 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal DCORCONFIGr ~wire 0 27 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal DCORIFGr ~wire 0 27 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal DCOR1CNTHIGHr ~wire 0 27 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal AS ~wire 0 27 (_architecture (_in ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal DCORIFGw ~wire 0 27 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal RD ~wire 0 27 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal DCOROUTw ~wire 0 27 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal DCORENCCTLw ~wire 0 27 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_type (_internal ~[7:0]wire~ 0 27 (_array ~wire ((_downto (i 7) (i 0))))))
		(_port (_internal ADDR ~[7:0]wire~ 0 27 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal DCORI2CCNTr ~wire 0 27 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_type (_internal ~[7:0]reg~ 0 91 (_array ~reg ((_downto (i 7) (i 0))))))
		(_signal (_internal Select.Address ~[7:0]reg~ 0 91 (_subprogram Select (_in ))) (_reg ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal Select.Location ~[7:0]reg~ 0 92 (_subprogram Select (_in ))) (_reg ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal Select.RD ~reg 0 93 (_subprogram Select (_in ))) (_reg ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal Select.WR ~reg 0 93 (_subprogram Select (_in ))) (_reg ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal Select.RorW ~reg 0 94 (_subprogram Select (_in ))) (_reg ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal Select.Select ~reg 0 0 (_subprogram Select (_out ))) (_reg ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_subprogram
			
			(_internal Select 20 0 90 (_architecture (_function)(_target(29))
				(_read(28)(26)(27)(22)(25))
			))

		)
		(_type (_external ~wire (vl verilog_logic wire)))
		(_type (_external ~reg (vl verilog_logic reg)))
		(_type (_external ~event (vl verilog_logic event)))
		(_type (_external ~wand (vl verilog_logic wand)))
		(_type (_external ~wor (vl verilog_logic wor)))
		(_type (_external ~tri1 (vl verilog_logic tri1)))
		(_type (_external ~tri0 (vl verilog_logic tri0)))
		(_type (_external ~trireg (vl verilog_logic trireg)))
		(_type (_external ~supply0 (vl verilog_logic supply0)))
		(_type (_external ~supply1 (vl verilog_logic supply1)))
		(_type (_external ~real (vl verilog_logic real)))
		(_type (_external ~realtime (vl verilog_logic realtime)))
		(_type (_external ~tri (vl verilog_logic tri)))
		(_type (_external ~triand (vl verilog_logic triand)))
		(_type (_external ~trior (vl verilog_logic trior)))
		(_type (_external ~bit (vl verilog_logic bit)))
		(_type (_external ~extstd.standard.integer (std standard integer)))
		(_type (_external ~extstd.standard.bit (std standard bit)))
		(_process
			(#ASSIGN#102_0 (_architecture 0 0 102 (_process (_simple)
				(_target(11))
				(_sensitivity(22)(19)(5))
				(_call(0))
			)))
			(#ASSIGN#105_1 (_architecture 1 0 105 (_process (_simple)
				(_target(18))
				(_sensitivity(22)(19)(5))
				(_call(0))
			)))
			(#ASSIGN#108_2 (_architecture 2 0 108 (_process (_simple)
				(_target(15))
				(_sensitivity(22)(19)(5))
				(_call(0))
			)))
			(#ASSIGN#111_3 (_architecture 3 0 111 (_process (_simple)
				(_target(10))
				(_sensitivity(22)(19)(5))
				(_call(0))
			)))
			(#ASSIGN#114_4 (_architecture 4 0 114 (_process (_simple)
				(_target(21))
				(_sensitivity(22)(19)(5))
				(_call(0))
			)))
			(#ASSIGN#117_5 (_architecture 5 0 117 (_process (_simple)
				(_target(0))
				(_sensitivity(22)(19)(5))
				(_call(0))
			)))
			(#ASSIGN#120_6 (_architecture 6 0 120 (_process (_simple)
				(_target(6))
				(_sensitivity(22)(19)(5))
				(_call(0))
			)))
			(#ASSIGN#123_7 (_architecture 7 0 123 (_process (_simple)
				(_target(13))
				(_sensitivity(22)(19)(5))
				(_call(0))
			)))
			(#ASSIGN#126_8 (_architecture 8 0 126 (_process (_simple)
				(_target(2))
				(_sensitivity(22)(19)(5))
				(_call(0))
			)))
			(#ASSIGN#129_9 (_architecture 9 0 129 (_process (_simple)
				(_target(8))
				(_sensitivity(22)(19)(5))
				(_call(0))
			)))
			(#ASSIGN#132_10 (_architecture 10 0 132 (_process (_simple)
				(_target(16))
				(_sensitivity(22)(19)(5))
				(_call(0))
			)))
			(#ASSIGN#135_11 (_architecture 11 0 135 (_process (_simple)
				(_target(1))
				(_sensitivity(22)(19)(5))
				(_call(0))
			)))
			(#ASSIGN#138_12 (_architecture 12 0 138 (_process (_simple)
				(_target(7))
				(_sensitivity(22)(19)(5))
				(_call(0))
			)))
			(#ASSIGN#141_13 (_architecture 13 0 141 (_process (_simple)
				(_target(3))
				(_sensitivity(22)(19)(5))
				(_call(0))
			)))
			(#ASSIGN#144_14 (_architecture 14 0 144 (_process (_simple)
				(_target(9))
				(_sensitivity(22)(19)(5))
				(_call(0))
			)))
			(#ASSIGN#147_15 (_architecture 15 0 147 (_process (_simple)
				(_target(4))
				(_sensitivity(22)(19)(5))
				(_call(0))
			)))
			(#ASSIGN#150_16 (_architecture 16 0 150 (_process (_simple)
				(_target(12))
				(_sensitivity(22)(19)(5))
				(_call(0))
			)))
			(#ASSIGN#153_17 (_architecture 17 0 153 (_process (_simple)
				(_target(14))
				(_sensitivity(22)(19)(5))
				(_call(0))
			)))
			(#ASSIGN#156_18 (_architecture 18 0 156 (_process (_simple)
				(_target(20))
				(_sensitivity(22)(19)(5))
				(_call(0))
			)))
			(#ASSIGN#159_19 (_architecture 19 0 159 (_process (_simple)
				(_target(23))
				(_sensitivity(22)(19)(5))
				(_call(0))
			)))
			(#INTERNAL#0_21 (_internal 21 0 0 (_process (_virtual))))
		)
	)
	
	
	(_defparam
	)
	(_scope
		(_unit Select function 0 90
		)
	)
	(_model . U21AddDecode 22 -1)

)
V 000044 55 24024         1079994347528 U21
(_unit VERILOG 6.349C.6.256 (U21 0 32 (U21 0 32 ))
	(_version v32)
	(_time 1079994347465 2004.03.22 14:25:47)
	(_source (\./compile/u21.v\ VERILOG (\./compile/u21.v\ VERILOG)))
	(_use (std(standard))(vl(verilog_logic)))
	(_base (E 15))
	(_entity
		(_time 1079994347465)
		(_use )
	)
	(_timescale 1ns 1ns)
	(_parameters    dbg   accs  )
	(_attribute )
	(_object
		(_type (_internal ~vector~0 0 190 (_array ~bit ((_uto (i 0) (i 0))))))
		(_generic (_internal DANGLING_INPUT_CONSTANT ~vector~0 0 190 \1'bZ\ (_entity -1 (_constant \1'bZ\))))
		(_port (_internal AS ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Brake0 ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Brake1 ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal DIR0 ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal DIR1 ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Enc033FLG ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Enc05FLG ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Enc133FLG ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Enc15FLG ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal FLS0 ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal FLS1 ~wire 0 33 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal GP_Motor0_0 ~wire 0 33 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal GP_Motor1_0 ~wire 0 33 (_architecture (_in ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal HSI ~wire 0 33 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal Home0 ~wire 0 33 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Home033FLG ~wire 0 33 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Home05FLG ~wire 0 33 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Home1 ~wire 0 33 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Home133FLG ~wire 0 33 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Home15FLG ~wire 0 33 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal INTbus ~wire 0 34 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal LightSense ~wire 0 34 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal MHSO ~wire 0 34 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal Mclk ~wire 0 34 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal PWM1 ~wire 0 34 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PWM2 ~wire 0 34 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PhaseA_Encoder0 ~wire 0 34 (_architecture (_in ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PhaseA_Encoder1 ~wire 0 34 (_architecture (_in ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PhaseB_Encoder0 ~wire 0 34 (_architecture (_in ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PhaseB_Encoder1 ~wire 0 34 (_architecture (_in ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal RD ~wire 0 35 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal RLS0 ~wire 0 35 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal RLS1 ~wire 0 35 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Reset ~wire 0 35 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal SCLinc ~wire 0 35 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal SCLreset ~wire 0 35 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal TXI ~wire 0 35 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal WR ~wire 0 35 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_type (_internal ~[5:0]wire~ 0 35 (_array ~wire ((_downto (i 5) (i 0))))))
		(_port (_internal I2CS ~[5:0]wire~ 0 35 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Enc033ctrl ~wire 0 35 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Enc05ctrl ~wire 0 36 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Enc133ctrl ~wire 0 36 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Enc15ctrl ~wire 0 36 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal GP_Motor0_1 ~wire 0 36 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal GP_Motor1_1 ~wire 0 36 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal HSO ~wire 0 36 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal Home033ctrl ~wire 0 36 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Home05ctrl ~wire 0 36 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Home133ctrl ~wire 0 36 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Home15ctrl ~wire 0 36 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal INT ~wire 0 37 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal LED1 ~wire 0 37 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal LED2 ~wire 0 37 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal LED3 ~wire 0 37 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal LED4 ~wire 0 37 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal LED5 ~wire 0 37 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal MHSI ~wire 0 37 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal MTRpwr ~wire 0 37 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal MTRpwrn ~wire 0 37 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal MTXI ~wire 0 37 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal PAH0 ~wire 0 38 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PAH1 ~wire 0 38 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PAL0 ~wire 0 38 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PAL1 ~wire 0 38 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PBH0 ~wire 0 38 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PBH1 ~wire 0 38 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PBL0 ~wire 0 38 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PBL1 ~wire 0 38 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal TP10 ~wire 0 38 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal TP11 ~wire 0 38 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal TP12 ~wire 0 39 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal SCL ~wire 0 39 (_architecture (_inout ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_type (_internal ~[7:0]wire~ 0 39 (_array ~wire ((_downto (i 7) (i 0))))))
		(_port (_internal AD ~[7:0]wire~ 0 39 (_architecture (_inout ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal clk ~wire 0 193 (_architecture (_uni ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal NET1635 ~wire 0 194 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET1643 ~wire 0 195 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET1651 ~wire 0 196 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET1667 ~wire 0 197 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET1978 ~wire 0 198 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET1989 ~wire 0 199 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET2017 ~wire 0 200 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET2025 ~wire 0 201 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET2036 ~wire 0 202 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET2047 ~wire 0 203 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET2064 ~wire 0 204 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET2078 ~wire 0 205 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET2311 ~wire 0 206 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET2528 ~wire 0 207 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET2539 ~wire 0 208 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET2575 ~wire 0 209 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET3248 ~wire 0 210 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET3253 ~wire 0 211 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET3919 ~wire 0 212 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal NET3926 ~wire 0 213 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal NET5008 ~wire 0 214 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET615 ~wire 0 215 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal NET621 ~wire 0 216 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal NET629 ~wire 0 217 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal reset ~wire 0 218 (_architecture (_uni ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal BUS1564 ~[7:0]wire~ 0 219 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal BUS5075 ~[7:0]wire~ 0 220 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal outDATA ~[7:0]wire~ 0 221 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal Dangling_Input_Signal ~wire 0 224 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_subprogram
			

		)
		(_type (_external ~wire (vl verilog_logic wire)))
		(_type (_external ~reg (vl verilog_logic reg)))
		(_type (_external ~event (vl verilog_logic event)))
		(_type (_external ~wand (vl verilog_logic wand)))
		(_type (_external ~wor (vl verilog_logic wor)))
		(_type (_external ~tri1 (vl verilog_logic tri1)))
		(_type (_external ~tri0 (vl verilog_logic tri0)))
		(_type (_external ~trireg (vl verilog_logic trireg)))
		(_type (_external ~supply0 (vl verilog_logic supply0)))
		(_type (_external ~supply1 (vl verilog_logic supply1)))
		(_type (_external ~real (vl verilog_logic real)))
		(_type (_external ~realtime (vl verilog_logic realtime)))
		(_type (_external ~tri (vl verilog_logic tri)))
		(_type (_external ~triand (vl verilog_logic triand)))
		(_type (_external ~trior (vl verilog_logic trior)))
		(_type (_external ~bit (vl verilog_logic bit)))
		(_type (_external ~extstd.standard.integer (std standard integer)))
		(_type (_external ~extstd.standard.bit (std standard bit)))
		(_process
			(#ASSIGN#224_0 (_architecture 0 0 224 (_process (_simple)
				(_target(102))
			)))
			(#ASSIGN#423_1 (_architecture 1 0 423 (_process (_alias ((clk)(Mclk)))(_simple)
				(_target(73))
				(_sensitivity(23))
			)))
			(#ASSIGN#424_2 (_architecture 2 0 424 (_process (_alias ((NET3919)(SCLreset)))(_simple)
				(_target(92))
				(_sensitivity(35))
			)))
			(#ASSIGN#425_3 (_architecture 3 0 425 (_process (_alias ((NET3926)(SCLinc)))(_simple)
				(_target(93))
				(_sensitivity(34))
			)))
			(#ASSIGN#426_4 (_architecture 4 0 426 (_process (_alias ((NET615)(MHSO)))(_simple)
				(_target(95))
				(_sensitivity(22))
			)))
			(#ASSIGN#427_5 (_architecture 5 0 427 (_process (_alias ((NET621)(HSI)))(_simple)
				(_target(96))
				(_sensitivity(13))
			)))
			(#ASSIGN#428_6 (_architecture 6 0 428 (_process (_alias ((NET629)(TXI)))(_simple)
				(_target(97))
				(_sensitivity(36))
			)))
			(#ASSIGN#429_7 (_architecture 7 0 429 (_process (_alias ((reset)(Reset)))(_simple)
				(_target(98))
				(_sensitivity(33))
			)))
			(#ASSIGN#432_8 (_architecture 8 0 432 (_process (_alias ((HSO)(NET615)))(_simple)
				(_target(45))
				(_sensitivity(95))
			)))
			(#ASSIGN#433_9 (_architecture 9 0 433 (_process (_alias ((MHSI)(NET621)))(_simple)
				(_target(56))
				(_sensitivity(96))
			)))
			(#ASSIGN#434_10 (_architecture 10 0 434 (_process (_alias ((MTXI)(NET629)))(_simple)
				(_target(59))
				(_sensitivity(97))
			)))
			(#ASSIGN#435_11 (_architecture 11 0 435 (_process (_alias ((TP10)(NET3919)))(_simple)
				(_target(68))
				(_sensitivity(92))
			)))
			(#ASSIGN#436_12 (_architecture 12 0 436 (_process (_alias ((TP11)(NET3926)))(_simple)
				(_target(69))
				(_sensitivity(93))
			)))
			(#ASSIGN#437_13 (_architecture 13 0 437 (_process (_alias ((TP12)(SCL)))(_simple)
				(_target(70))
				(_sensitivity(71))
			)))
			(#INTERNAL#0_14 (_internal 14 0 0 (_process (_virtual))))
		)
	)
	
	
	(_defparam
	)
	(_scope
	)
	(_instantiation U1 0 228 (_entity .  reader)
		(_port
			((RVALVECTLw) (NET1635))
			((RVALVEHIGHr) (NET1643))
			((RVALVELOWr) (NET1651))
			((RVALVESTATr) (NET1667))
			((SSclk) (GP_Motor0_1))
			((data) (GP_Motor0_0))
			((outDATA) (outDATA))
			((clk) (_open))
			((reset) (_open))
		)
		(_strength strong0 strong1)
	)
	(_instantiation U11 0 241 (_entity .  I2Cfix)
		(_port
			((DCORI2CCNTr) (NET2311))
			((Inc) (NET3926))
			((Mclk) (Mclk))
			((SCL) (SCL))
			((SCLint) (NET2539))
			((SCLreset) (NET3919))
			((outDATA) (outDATA))
			((SCLenable) (_open))
		)
		(_strength strong0 strong1)
	)
	(_instantiation U12 0 254 (_entity .  U21AddDecode)
		(_port
			((ADDR) (BUS1564))
			((AS) (AS))
			((DCOR0CNTHIGHr) (NET1667))
			((DCOR0CNTLOWr) (NET1651))
			((DCOR0CNTMIDr) (NET1643))
			((DCORCONFIGr) (NET2064))
			((DCORENCCTLw) (NET1635))
			((DCORENCPWRr) (NET2036))
			((DCORENCPWRw) (NET2025))
			((DCORI2CCNTr) (NET2311))
			((DCORIEw) (NET2078))
			((DCORIFGr) (NET1978))
			((DCORIFGw) (NET1989))
			((DCORLIMITSr) (NET2047))
			((DCOROUTw) (NET2017))
			((RD) (RD))
			((WR) (WR))
			((DCOR0THRESLOWr) (_open))
			((DCOR1CNTLOWr) (_open))
			((DCOR1THRESLOWr) (_open))
			((DCOR0THRESMIDr) (_open))
			((DCOR1CNTMIDr) (_open))
			((DCOR1THRESMIDr) (_open))
			((DCOR1CNTHIGHr) (_open))
		)
		(_strength strong0 strong1)
	)
	(_instantiation U2 0 277 (_entity .  Interface)
		(_port
			((AD) (AD))
			((ADDR) (BUS1564))
			((AS) (AS))
			((Mclk) (Mclk))
			((RD) (RD))
			((Reset) (Reset))
			((WR) (WR))
			((inDATA) (BUS5075))
			((outDATA) (outDATA))
			((ASleading) (_open))
		)
		(_strength strong0 strong1)
	)
	(_instantiation U3 0 292 (_entity .  Interrupt)
		(_port
			((BusInt) (INTbus))
			((DCORIEw) (NET2078))
			((Homed0) (Dangling_Input_Signal))
			((Homed1) (Dangling_Input_Signal))
			((I2Cint) (NET2539))
			((INT) (INT))
			((LSwitchInt) (NET2575))
			((Mclk) (Mclk))
			((PWRint) (NET2528))
			((Reset) (Reset))
			((Thres0) (Dangling_Input_Signal))
			((Thres1) (Dangling_Input_Signal))
			((inDATA) (BUS5075))
		)
		(_strength strong0 strong1)
	)
	(_instantiation U4 0 311 (_entity .  PWRreg)
		(_port
			((DCORENCPWRr) (NET2036))
			((DCORENCPWRw) (NET2025))
			((DCORIFGr) (NET1978))
			((DCORIFGw) (NET1989))
			((Enc033ctl) (Home15ctrl))
			((Enc033flg) (Enc033FLG))
			((Enc05ctl) (Home133ctrl))
			((Enc05flg) (Enc05FLG))
			((Enc133ctl) (Home05ctrl))
			((Enc133flg) (Enc133FLG))
			((Enc15ctl) (Home033ctrl))
			((Enc15flg) (Enc15FLG))
			((Hme033ctl) (Enc15ctrl))
			((Hme033flg) (Home033FLG))
			((Hme05ctl) (Enc133ctrl))
			((Hme05flg) (Home05FLG))
			((Hme133ctl) (Enc05ctrl))
			((Hme133flg) (Home133FLG))
			((Hme15ctl) (Enc033ctrl))
			((Hme15flg) (Home15FLG))
			((Mclk) (Mclk))
			((PWRint) (NET2528))
			((Reset) (Reset))
			((inDATA) (BUS5075))
			((outDATA) (outDATA))
		)
		(_strength strong0 strong1)
	)
	(_instantiation U5 0 342 (_entity .  Lswitch)
		(_port
			((Brake0) (Brake0))
			((Brake1) (Brake1))
			((DCORIFGr) (NET1978))
			((DCORIFGw) (NET1989))
			((DCORLIMITSr) (NET2047))
			((DIR0) (DIR0))
			((DIR1) (DIR1))
			((FLS0) (FLS0))
			((FLS1) (FLS1))
			((Home0) (Home0))
			((Home1) (Home1))
			((LSwitchInt) (NET2575))
			((Mclk) (Mclk))
			((RLS0) (RLS0))
			((RLS1) (RLS1))
			((Reset) (Reset))
			((fBRK0) (NET3248))
			((fBRK1) (NET3253))
			((inDATA) (BUS5075))
			((outDATA) (outDATA))
		)
		(_strength strong0 strong1)
	)
	(_instantiation U6 0 368 (_entity .  I2CAddress)
		(_port
			((DCORCONFIGr) (NET2064))
			((I2CS) (I2CS))
			((MotorIn0) (GP_Motor0_0))
			((MotorIn1) (NET5008))
			((outDATA) (outDATA))
		)
		(_strength strong0 strong1)
	)
	(_instantiation U7 0 379 (_entity .  PWMcontrol)
		(_port
			((Brake1) (Brake0))
			((Brake2) (Brake1))
			((DIR1) (DIR0))
			((DIR2) (DIR1))
			((HBRK1) (NET3248))
			((HBRK2) (NET3253))
			((PAH1) (PAH0))
			((PAH2) (PBL1))
			((PAL1) (PAL0))
			((PAL2) (PBH1))
			((PBH1) (PBH0))
			((PBH2) (PAL1))
			((PBL1) (PBL0))
			((PBL2) (PAH1))
			((PWM1) (PWM1))
			((PWM2) (PWM2))
			((fBRK1) (NET3248))
			((fBRK2) (NET3253))
		)
		(_strength strong0 strong1)
	)
	(_instantiation U9 0 403 (_entity .  MISCouts)
		(_port
			((DCOROUTw) (NET2017))
			((LED1) (LED1))
			((LED2) (LED2))
			((LED3) (LED3))
			((LED4) (LED4))
			((LED5) (LED5))
			((LightSense) (LightSense))
			((MTRpwr) (MTRpwr))
			((MTRpwrn) (MTRpwrn))
			((Mclk) (Mclk))
			((Reset) (Reset))
			((inDATA) (BUS5075))
			((GP_Motor0_1) (_open))
			((GP_Motor1_1) (_open))
		)
		(_strength strong0 strong1)
	)
	(_model . U21 15 -1)

)
V 000044 55 24002         1079994464372 U21
(_unit VERILOG 6.349C.6.256 (U21 0 32 (U21 0 32 ))
	(_version v32)
	(_time 1079994464293 2004.03.22 14:27:44)
	(_source (\./compile/u21.v\ VERILOG (\./compile/u21.v\ VERILOG)))
	(_use (std(standard))(vl(verilog_logic)))
	(_base (E 15))
	(_entity
		(_time 1079994464293)
		(_use )
	)
	(_timescale 1ns 1ns)
	(_parameters    dbg   accs  )
	(_attribute )
	(_object
		(_type (_internal ~vector~0 0 190 (_array ~bit ((_uto (i 0) (i 0))))))
		(_generic (_internal DANGLING_INPUT_CONSTANT ~vector~0 0 190 \1'bZ\ (_entity -1 (_constant \1'bZ\))))
		(_port (_internal AS ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Brake0 ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Brake1 ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal DIR0 ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal DIR1 ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Enc033FLG ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Enc05FLG ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Enc133FLG ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Enc15FLG ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal FLS0 ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal FLS1 ~wire 0 33 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal GP_Motor0_0 ~wire 0 33 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal GP_Motor1_0 ~wire 0 33 (_architecture (_in ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal HSI ~wire 0 33 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal Home0 ~wire 0 33 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Home033FLG ~wire 0 33 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Home05FLG ~wire 0 33 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Home1 ~wire 0 33 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Home133FLG ~wire 0 33 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Home15FLG ~wire 0 33 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal INTbus ~wire 0 34 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal LightSense ~wire 0 34 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal MHSO ~wire 0 34 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal Mclk ~wire 0 34 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal PWM1 ~wire 0 34 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PWM2 ~wire 0 34 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PhaseA_Encoder0 ~wire 0 34 (_architecture (_in ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PhaseA_Encoder1 ~wire 0 34 (_architecture (_in ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PhaseB_Encoder0 ~wire 0 34 (_architecture (_in ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PhaseB_Encoder1 ~wire 0 34 (_architecture (_in ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal RD ~wire 0 35 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal RLS0 ~wire 0 35 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal RLS1 ~wire 0 35 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Reset ~wire 0 35 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal SCLinc ~wire 0 35 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal SCLreset ~wire 0 35 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal TXI ~wire 0 35 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal WR ~wire 0 35 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_type (_internal ~[5:0]wire~ 0 35 (_array ~wire ((_downto (i 5) (i 0))))))
		(_port (_internal I2CS ~[5:0]wire~ 0 35 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Enc033ctrl ~wire 0 35 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Enc05ctrl ~wire 0 36 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Enc133ctrl ~wire 0 36 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Enc15ctrl ~wire 0 36 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal GP_Motor0_1 ~wire 0 36 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal GP_Motor1_1 ~wire 0 36 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal HSO ~wire 0 36 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal Home033ctrl ~wire 0 36 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Home05ctrl ~wire 0 36 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Home133ctrl ~wire 0 36 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Home15ctrl ~wire 0 36 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal INT ~wire 0 37 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal LED1 ~wire 0 37 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal LED2 ~wire 0 37 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal LED3 ~wire 0 37 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal LED4 ~wire 0 37 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal LED5 ~wire 0 37 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal MHSI ~wire 0 37 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal MTRpwr ~wire 0 37 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal MTRpwrn ~wire 0 37 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal MTXI ~wire 0 37 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal PAH0 ~wire 0 38 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PAH1 ~wire 0 38 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PAL0 ~wire 0 38 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PAL1 ~wire 0 38 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PBH0 ~wire 0 38 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PBH1 ~wire 0 38 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PBL0 ~wire 0 38 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PBL1 ~wire 0 38 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal TP10 ~wire 0 38 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal TP11 ~wire 0 38 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal TP12 ~wire 0 39 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal SCL ~wire 0 39 (_architecture (_inout ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_type (_internal ~[7:0]wire~ 0 39 (_array ~wire ((_downto (i 7) (i 0))))))
		(_port (_internal AD ~[7:0]wire~ 0 39 (_architecture (_inout ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal clk ~wire 0 193 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal NET1635 ~wire 0 194 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET1643 ~wire 0 195 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET1651 ~wire 0 196 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET1667 ~wire 0 197 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET1978 ~wire 0 198 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET1989 ~wire 0 199 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET2017 ~wire 0 200 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET2025 ~wire 0 201 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET2036 ~wire 0 202 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET2047 ~wire 0 203 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET2064 ~wire 0 204 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET2078 ~wire 0 205 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET2311 ~wire 0 206 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET2528 ~wire 0 207 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET2539 ~wire 0 208 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET2575 ~wire 0 209 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET3248 ~wire 0 210 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET3253 ~wire 0 211 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET3919 ~wire 0 212 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal NET3926 ~wire 0 213 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal NET5008 ~wire 0 214 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET615 ~wire 0 215 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal NET621 ~wire 0 216 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal NET629 ~wire 0 217 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal reset ~wire 0 218 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal BUS1564 ~[7:0]wire~ 0 219 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal BUS5075 ~[7:0]wire~ 0 220 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal outDATA ~[7:0]wire~ 0 221 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal Dangling_Input_Signal ~wire 0 224 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_subprogram
			

		)
		(_type (_external ~wire (vl verilog_logic wire)))
		(_type (_external ~reg (vl verilog_logic reg)))
		(_type (_external ~event (vl verilog_logic event)))
		(_type (_external ~wand (vl verilog_logic wand)))
		(_type (_external ~wor (vl verilog_logic wor)))
		(_type (_external ~tri1 (vl verilog_logic tri1)))
		(_type (_external ~tri0 (vl verilog_logic tri0)))
		(_type (_external ~trireg (vl verilog_logic trireg)))
		(_type (_external ~supply0 (vl verilog_logic supply0)))
		(_type (_external ~supply1 (vl verilog_logic supply1)))
		(_type (_external ~real (vl verilog_logic real)))
		(_type (_external ~realtime (vl verilog_logic realtime)))
		(_type (_external ~tri (vl verilog_logic tri)))
		(_type (_external ~triand (vl verilog_logic triand)))
		(_type (_external ~trior (vl verilog_logic trior)))
		(_type (_external ~bit (vl verilog_logic bit)))
		(_type (_external ~extstd.standard.integer (std standard integer)))
		(_type (_external ~extstd.standard.bit (std standard bit)))
		(_process
			(#ASSIGN#224_0 (_architecture 0 0 224 (_process (_simple)
				(_target(102))
			)))
			(#ASSIGN#425_1 (_architecture 1 0 425 (_process (_alias ((clk)(Mclk)))(_simple)
				(_target(73))
				(_sensitivity(23))
			)))
			(#ASSIGN#426_2 (_architecture 2 0 426 (_process (_alias ((NET3919)(SCLreset)))(_simple)
				(_target(92))
				(_sensitivity(35))
			)))
			(#ASSIGN#427_3 (_architecture 3 0 427 (_process (_alias ((NET3926)(SCLinc)))(_simple)
				(_target(93))
				(_sensitivity(34))
			)))
			(#ASSIGN#428_4 (_architecture 4 0 428 (_process (_alias ((NET615)(MHSO)))(_simple)
				(_target(95))
				(_sensitivity(22))
			)))
			(#ASSIGN#429_5 (_architecture 5 0 429 (_process (_alias ((NET621)(HSI)))(_simple)
				(_target(96))
				(_sensitivity(13))
			)))
			(#ASSIGN#430_6 (_architecture 6 0 430 (_process (_alias ((NET629)(TXI)))(_simple)
				(_target(97))
				(_sensitivity(36))
			)))
			(#ASSIGN#431_7 (_architecture 7 0 431 (_process (_alias ((reset)(Reset)))(_simple)
				(_target(98))
				(_sensitivity(33))
			)))
			(#ASSIGN#434_8 (_architecture 8 0 434 (_process (_alias ((HSO)(NET615)))(_simple)
				(_target(45))
				(_sensitivity(95))
			)))
			(#ASSIGN#435_9 (_architecture 9 0 435 (_process (_alias ((MHSI)(NET621)))(_simple)
				(_target(56))
				(_sensitivity(96))
			)))
			(#ASSIGN#436_10 (_architecture 10 0 436 (_process (_alias ((MTXI)(NET629)))(_simple)
				(_target(59))
				(_sensitivity(97))
			)))
			(#ASSIGN#437_11 (_architecture 11 0 437 (_process (_alias ((TP10)(NET3919)))(_simple)
				(_target(68))
				(_sensitivity(92))
			)))
			(#ASSIGN#438_12 (_architecture 12 0 438 (_process (_alias ((TP11)(NET3926)))(_simple)
				(_target(69))
				(_sensitivity(93))
			)))
			(#ASSIGN#439_13 (_architecture 13 0 439 (_process (_alias ((TP12)(SCL)))(_simple)
				(_target(70))
				(_sensitivity(71))
			)))
			(#INTERNAL#0_14 (_internal 14 0 0 (_process (_virtual))))
		)
	)
	
	
	(_defparam
	)
	(_scope
	)
	(_instantiation U1 0 228 (_entity .  reader)
		(_port
			((RVALVECTLw) (NET1635))
			((RVALVEHIGHr) (NET1643))
			((RVALVELOWr) (NET1651))
			((RVALVESTATr) (NET1667))
			((SSclk) (GP_Motor0_1))
			((clk) (clk))
			((data) (GP_Motor0_0))
			((outDATA) (outDATA))
			((reset) (reset))
		)
		(_strength strong0 strong1)
	)
	(_instantiation U11 0 243 (_entity .  I2Cfix)
		(_port
			((DCORI2CCNTr) (NET2311))
			((Inc) (NET3926))
			((Mclk) (Mclk))
			((SCL) (SCL))
			((SCLint) (NET2539))
			((SCLreset) (NET3919))
			((outDATA) (outDATA))
			((SCLenable) (_open))
		)
		(_strength strong0 strong1)
	)
	(_instantiation U12 0 256 (_entity .  U21AddDecode)
		(_port
			((ADDR) (BUS1564))
			((AS) (AS))
			((DCOR0CNTHIGHr) (NET1667))
			((DCOR0CNTLOWr) (NET1651))
			((DCOR0CNTMIDr) (NET1643))
			((DCORCONFIGr) (NET2064))
			((DCORENCCTLw) (NET1635))
			((DCORENCPWRr) (NET2036))
			((DCORENCPWRw) (NET2025))
			((DCORI2CCNTr) (NET2311))
			((DCORIEw) (NET2078))
			((DCORIFGr) (NET1978))
			((DCORIFGw) (NET1989))
			((DCORLIMITSr) (NET2047))
			((DCOROUTw) (NET2017))
			((RD) (RD))
			((WR) (WR))
			((DCOR0THRESLOWr) (_open))
			((DCOR1CNTLOWr) (_open))
			((DCOR1THRESLOWr) (_open))
			((DCOR0THRESMIDr) (_open))
			((DCOR1CNTMIDr) (_open))
			((DCOR1THRESMIDr) (_open))
			((DCOR1CNTHIGHr) (_open))
		)
		(_strength strong0 strong1)
	)
	(_instantiation U2 0 279 (_entity .  Interface)
		(_port
			((AD) (AD))
			((ADDR) (BUS1564))
			((AS) (AS))
			((Mclk) (Mclk))
			((RD) (RD))
			((Reset) (Reset))
			((WR) (WR))
			((inDATA) (BUS5075))
			((outDATA) (outDATA))
			((ASleading) (_open))
		)
		(_strength strong0 strong1)
	)
	(_instantiation U3 0 294 (_entity .  Interrupt)
		(_port
			((BusInt) (INTbus))
			((DCORIEw) (NET2078))
			((Homed0) (Dangling_Input_Signal))
			((Homed1) (Dangling_Input_Signal))
			((I2Cint) (NET2539))
			((INT) (INT))
			((LSwitchInt) (NET2575))
			((Mclk) (Mclk))
			((PWRint) (NET2528))
			((Reset) (Reset))
			((Thres0) (Dangling_Input_Signal))
			((Thres1) (Dangling_Input_Signal))
			((inDATA) (BUS5075))
		)
		(_strength strong0 strong1)
	)
	(_instantiation U4 0 313 (_entity .  PWRreg)
		(_port
			((DCORENCPWRr) (NET2036))
			((DCORENCPWRw) (NET2025))
			((DCORIFGr) (NET1978))
			((DCORIFGw) (NET1989))
			((Enc033ctl) (Home15ctrl))
			((Enc033flg) (Enc033FLG))
			((Enc05ctl) (Home133ctrl))
			((Enc05flg) (Enc05FLG))
			((Enc133ctl) (Home05ctrl))
			((Enc133flg) (Enc133FLG))
			((Enc15ctl) (Home033ctrl))
			((Enc15flg) (Enc15FLG))
			((Hme033ctl) (Enc15ctrl))
			((Hme033flg) (Home033FLG))
			((Hme05ctl) (Enc133ctrl))
			((Hme05flg) (Home05FLG))
			((Hme133ctl) (Enc05ctrl))
			((Hme133flg) (Home133FLG))
			((Hme15ctl) (Enc033ctrl))
			((Hme15flg) (Home15FLG))
			((Mclk) (Mclk))
			((PWRint) (NET2528))
			((Reset) (Reset))
			((inDATA) (BUS5075))
			((outDATA) (outDATA))
		)
		(_strength strong0 strong1)
	)
	(_instantiation U5 0 344 (_entity .  Lswitch)
		(_port
			((Brake0) (Brake0))
			((Brake1) (Brake1))
			((DCORIFGr) (NET1978))
			((DCORIFGw) (NET1989))
			((DCORLIMITSr) (NET2047))
			((DIR0) (DIR0))
			((DIR1) (DIR1))
			((FLS0) (FLS0))
			((FLS1) (FLS1))
			((Home0) (Home0))
			((Home1) (Home1))
			((LSwitchInt) (NET2575))
			((Mclk) (Mclk))
			((RLS0) (RLS0))
			((RLS1) (RLS1))
			((Reset) (Reset))
			((fBRK0) (NET3248))
			((fBRK1) (NET3253))
			((inDATA) (BUS5075))
			((outDATA) (outDATA))
		)
		(_strength strong0 strong1)
	)
	(_instantiation U6 0 370 (_entity .  I2CAddress)
		(_port
			((DCORCONFIGr) (NET2064))
			((I2CS) (I2CS))
			((MotorIn0) (GP_Motor0_0))
			((MotorIn1) (NET5008))
			((outDATA) (outDATA))
		)
		(_strength strong0 strong1)
	)
	(_instantiation U7 0 381 (_entity .  PWMcontrol)
		(_port
			((Brake1) (Brake0))
			((Brake2) (Brake1))
			((DIR1) (DIR0))
			((DIR2) (DIR1))
			((HBRK1) (NET3248))
			((HBRK2) (NET3253))
			((PAH1) (PAH0))
			((PAH2) (PBL1))
			((PAL1) (PAL0))
			((PAL2) (PBH1))
			((PBH1) (PBH0))
			((PBH2) (PAL1))
			((PBL1) (PBL0))
			((PBL2) (PAH1))
			((PWM1) (PWM1))
			((PWM2) (PWM2))
			((fBRK1) (NET3248))
			((fBRK2) (NET3253))
		)
		(_strength strong0 strong1)
	)
	(_instantiation U9 0 405 (_entity .  MISCouts)
		(_port
			((DCOROUTw) (NET2017))
			((LED1) (LED1))
			((LED2) (LED2))
			((LED3) (LED3))
			((LED4) (LED4))
			((LED5) (LED5))
			((LightSense) (LightSense))
			((MTRpwr) (MTRpwr))
			((MTRpwrn) (MTRpwrn))
			((Mclk) (Mclk))
			((Reset) (Reset))
			((inDATA) (BUS5075))
			((GP_Motor0_1) (_open))
			((GP_Motor1_1) (_open))
		)
		(_strength strong0 strong1)
	)
	(_model . U21 15 -1)

)
V 000044 55 24002         1079994472997 U21
(_unit VERILOG 6.349C.6.256 (U21 0 32 (U21 0 32 ))
	(_version v32)
	(_time 1079994472933 2004.03.22 14:27:52)
	(_source (\./compile/u21.v\ VERILOG (\./compile/u21.v\ VERILOG)))
	(_use (std(standard))(vl(verilog_logic)))
	(_base (E 15))
	(_entity
		(_time 1079994472933)
		(_use )
	)
	(_timescale 1ns 1ns)
	(_parameters    dbg   accs  )
	(_attribute )
	(_object
		(_type (_internal ~vector~0 0 190 (_array ~bit ((_uto (i 0) (i 0))))))
		(_generic (_internal DANGLING_INPUT_CONSTANT ~vector~0 0 190 \1'bZ\ (_entity -1 (_constant \1'bZ\))))
		(_port (_internal AS ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Brake0 ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Brake1 ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal DIR0 ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal DIR1 ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Enc033FLG ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Enc05FLG ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Enc133FLG ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Enc15FLG ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal FLS0 ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal FLS1 ~wire 0 33 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal GP_Motor0_0 ~wire 0 33 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal GP_Motor1_0 ~wire 0 33 (_architecture (_in ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal HSI ~wire 0 33 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal Home0 ~wire 0 33 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Home033FLG ~wire 0 33 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Home05FLG ~wire 0 33 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Home1 ~wire 0 33 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Home133FLG ~wire 0 33 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Home15FLG ~wire 0 33 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal INTbus ~wire 0 34 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal LightSense ~wire 0 34 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal MHSO ~wire 0 34 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal Mclk ~wire 0 34 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal PWM1 ~wire 0 34 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PWM2 ~wire 0 34 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PhaseA_Encoder0 ~wire 0 34 (_architecture (_in ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PhaseA_Encoder1 ~wire 0 34 (_architecture (_in ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PhaseB_Encoder0 ~wire 0 34 (_architecture (_in ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PhaseB_Encoder1 ~wire 0 34 (_architecture (_in ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal RD ~wire 0 35 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal RLS0 ~wire 0 35 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal RLS1 ~wire 0 35 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Reset ~wire 0 35 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal SCLinc ~wire 0 35 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal SCLreset ~wire 0 35 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal TXI ~wire 0 35 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal WR ~wire 0 35 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_type (_internal ~[5:0]wire~ 0 35 (_array ~wire ((_downto (i 5) (i 0))))))
		(_port (_internal I2CS ~[5:0]wire~ 0 35 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Enc033ctrl ~wire 0 35 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Enc05ctrl ~wire 0 36 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Enc133ctrl ~wire 0 36 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Enc15ctrl ~wire 0 36 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal GP_Motor0_1 ~wire 0 36 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal GP_Motor1_1 ~wire 0 36 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal HSO ~wire 0 36 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal Home033ctrl ~wire 0 36 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Home05ctrl ~wire 0 36 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Home133ctrl ~wire 0 36 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Home15ctrl ~wire 0 36 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal INT ~wire 0 37 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal LED1 ~wire 0 37 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal LED2 ~wire 0 37 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal LED3 ~wire 0 37 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal LED4 ~wire 0 37 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal LED5 ~wire 0 37 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal MHSI ~wire 0 37 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal MTRpwr ~wire 0 37 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal MTRpwrn ~wire 0 37 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal MTXI ~wire 0 37 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal PAH0 ~wire 0 38 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PAH1 ~wire 0 38 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PAL0 ~wire 0 38 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PAL1 ~wire 0 38 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PBH0 ~wire 0 38 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PBH1 ~wire 0 38 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PBL0 ~wire 0 38 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PBL1 ~wire 0 38 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal TP10 ~wire 0 38 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal TP11 ~wire 0 38 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal TP12 ~wire 0 39 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal SCL ~wire 0 39 (_architecture (_inout ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_type (_internal ~[7:0]wire~ 0 39 (_array ~wire ((_downto (i 7) (i 0))))))
		(_port (_internal AD ~[7:0]wire~ 0 39 (_architecture (_inout ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal clk ~wire 0 193 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal NET1635 ~wire 0 194 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET1643 ~wire 0 195 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET1651 ~wire 0 196 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET1667 ~wire 0 197 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET1978 ~wire 0 198 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET1989 ~wire 0 199 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET2017 ~wire 0 200 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET2025 ~wire 0 201 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET2036 ~wire 0 202 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET2047 ~wire 0 203 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET2064 ~wire 0 204 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET2078 ~wire 0 205 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET2311 ~wire 0 206 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET2528 ~wire 0 207 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET2539 ~wire 0 208 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET2575 ~wire 0 209 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET3248 ~wire 0 210 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET3253 ~wire 0 211 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET3919 ~wire 0 212 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal NET3926 ~wire 0 213 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal NET5008 ~wire 0 214 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET615 ~wire 0 215 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal NET621 ~wire 0 216 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal NET629 ~wire 0 217 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal reset ~wire 0 218 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal BUS1564 ~[7:0]wire~ 0 219 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal BUS5075 ~[7:0]wire~ 0 220 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal outDATA ~[7:0]wire~ 0 221 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal Dangling_Input_Signal ~wire 0 224 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_subprogram
			

		)
		(_type (_external ~wire (vl verilog_logic wire)))
		(_type (_external ~reg (vl verilog_logic reg)))
		(_type (_external ~event (vl verilog_logic event)))
		(_type (_external ~wand (vl verilog_logic wand)))
		(_type (_external ~wor (vl verilog_logic wor)))
		(_type (_external ~tri1 (vl verilog_logic tri1)))
		(_type (_external ~tri0 (vl verilog_logic tri0)))
		(_type (_external ~trireg (vl verilog_logic trireg)))
		(_type (_external ~supply0 (vl verilog_logic supply0)))
		(_type (_external ~supply1 (vl verilog_logic supply1)))
		(_type (_external ~real (vl verilog_logic real)))
		(_type (_external ~realtime (vl verilog_logic realtime)))
		(_type (_external ~tri (vl verilog_logic tri)))
		(_type (_external ~triand (vl verilog_logic triand)))
		(_type (_external ~trior (vl verilog_logic trior)))
		(_type (_external ~bit (vl verilog_logic bit)))
		(_type (_external ~extstd.standard.integer (std standard integer)))
		(_type (_external ~extstd.standard.bit (std standard bit)))
		(_process
			(#ASSIGN#224_0 (_architecture 0 0 224 (_process (_simple)
				(_target(102))
			)))
			(#ASSIGN#425_1 (_architecture 1 0 425 (_process (_alias ((clk)(Mclk)))(_simple)
				(_target(73))
				(_sensitivity(23))
			)))
			(#ASSIGN#426_2 (_architecture 2 0 426 (_process (_alias ((NET3919)(SCLreset)))(_simple)
				(_target(92))
				(_sensitivity(35))
			)))
			(#ASSIGN#427_3 (_architecture 3 0 427 (_process (_alias ((NET3926)(SCLinc)))(_simple)
				(_target(93))
				(_sensitivity(34))
			)))
			(#ASSIGN#428_4 (_architecture 4 0 428 (_process (_alias ((NET615)(MHSO)))(_simple)
				(_target(95))
				(_sensitivity(22))
			)))
			(#ASSIGN#429_5 (_architecture 5 0 429 (_process (_alias ((NET621)(HSI)))(_simple)
				(_target(96))
				(_sensitivity(13))
			)))
			(#ASSIGN#430_6 (_architecture 6 0 430 (_process (_alias ((NET629)(TXI)))(_simple)
				(_target(97))
				(_sensitivity(36))
			)))
			(#ASSIGN#431_7 (_architecture 7 0 431 (_process (_alias ((reset)(Reset)))(_simple)
				(_target(98))
				(_sensitivity(33))
			)))
			(#ASSIGN#434_8 (_architecture 8 0 434 (_process (_alias ((HSO)(NET615)))(_simple)
				(_target(45))
				(_sensitivity(95))
			)))
			(#ASSIGN#435_9 (_architecture 9 0 435 (_process (_alias ((MHSI)(NET621)))(_simple)
				(_target(56))
				(_sensitivity(96))
			)))
			(#ASSIGN#436_10 (_architecture 10 0 436 (_process (_alias ((MTXI)(NET629)))(_simple)
				(_target(59))
				(_sensitivity(97))
			)))
			(#ASSIGN#437_11 (_architecture 11 0 437 (_process (_alias ((TP10)(NET3919)))(_simple)
				(_target(68))
				(_sensitivity(92))
			)))
			(#ASSIGN#438_12 (_architecture 12 0 438 (_process (_alias ((TP11)(NET3926)))(_simple)
				(_target(69))
				(_sensitivity(93))
			)))
			(#ASSIGN#439_13 (_architecture 13 0 439 (_process (_alias ((TP12)(SCL)))(_simple)
				(_target(70))
				(_sensitivity(71))
			)))
			(#INTERNAL#0_14 (_internal 14 0 0 (_process (_virtual))))
		)
	)
	
	
	(_defparam
	)
	(_scope
	)
	(_instantiation U1 0 228 (_entity .  reader)
		(_port
			((RVALVECTLw) (NET1635))
			((RVALVEHIGHr) (NET1643))
			((RVALVELOWr) (NET1651))
			((RVALVESTATr) (NET1667))
			((SSclk) (GP_Motor0_1))
			((clk) (clk))
			((data) (GP_Motor0_0))
			((outDATA) (outDATA))
			((reset) (reset))
		)
		(_strength strong0 strong1)
	)
	(_instantiation U11 0 243 (_entity .  I2Cfix)
		(_port
			((DCORI2CCNTr) (NET2311))
			((Inc) (NET3926))
			((Mclk) (Mclk))
			((SCL) (SCL))
			((SCLint) (NET2539))
			((SCLreset) (NET3919))
			((outDATA) (outDATA))
			((SCLenable) (_open))
		)
		(_strength strong0 strong1)
	)
	(_instantiation U12 0 256 (_entity .  U21AddDecode)
		(_port
			((ADDR) (BUS1564))
			((AS) (AS))
			((DCOR0CNTHIGHr) (NET1667))
			((DCOR0CNTLOWr) (NET1651))
			((DCOR0CNTMIDr) (NET1643))
			((DCORCONFIGr) (NET2064))
			((DCORENCCTLw) (NET1635))
			((DCORENCPWRr) (NET2036))
			((DCORENCPWRw) (NET2025))
			((DCORI2CCNTr) (NET2311))
			((DCORIEw) (NET2078))
			((DCORIFGr) (NET1978))
			((DCORIFGw) (NET1989))
			((DCORLIMITSr) (NET2047))
			((DCOROUTw) (NET2017))
			((RD) (RD))
			((WR) (WR))
			((DCOR0THRESLOWr) (_open))
			((DCOR1CNTLOWr) (_open))
			((DCOR1THRESLOWr) (_open))
			((DCOR0THRESMIDr) (_open))
			((DCOR1CNTMIDr) (_open))
			((DCOR1THRESMIDr) (_open))
			((DCOR1CNTHIGHr) (_open))
		)
		(_strength strong0 strong1)
	)
	(_instantiation U2 0 279 (_entity .  Interface)
		(_port
			((AD) (AD))
			((ADDR) (BUS1564))
			((AS) (AS))
			((Mclk) (Mclk))
			((RD) (RD))
			((Reset) (Reset))
			((WR) (WR))
			((inDATA) (BUS5075))
			((outDATA) (outDATA))
			((ASleading) (_open))
		)
		(_strength strong0 strong1)
	)
	(_instantiation U3 0 294 (_entity .  Interrupt)
		(_port
			((BusInt) (INTbus))
			((DCORIEw) (NET2078))
			((Homed0) (Dangling_Input_Signal))
			((Homed1) (Dangling_Input_Signal))
			((I2Cint) (NET2539))
			((INT) (INT))
			((LSwitchInt) (NET2575))
			((Mclk) (Mclk))
			((PWRint) (NET2528))
			((Reset) (Reset))
			((Thres0) (Dangling_Input_Signal))
			((Thres1) (Dangling_Input_Signal))
			((inDATA) (BUS5075))
		)
		(_strength strong0 strong1)
	)
	(_instantiation U4 0 313 (_entity .  PWRreg)
		(_port
			((DCORENCPWRr) (NET2036))
			((DCORENCPWRw) (NET2025))
			((DCORIFGr) (NET1978))
			((DCORIFGw) (NET1989))
			((Enc033ctl) (Home15ctrl))
			((Enc033flg) (Enc033FLG))
			((Enc05ctl) (Home133ctrl))
			((Enc05flg) (Enc05FLG))
			((Enc133ctl) (Home05ctrl))
			((Enc133flg) (Enc133FLG))
			((Enc15ctl) (Home033ctrl))
			((Enc15flg) (Enc15FLG))
			((Hme033ctl) (Enc15ctrl))
			((Hme033flg) (Home033FLG))
			((Hme05ctl) (Enc133ctrl))
			((Hme05flg) (Home05FLG))
			((Hme133ctl) (Enc05ctrl))
			((Hme133flg) (Home133FLG))
			((Hme15ctl) (Enc033ctrl))
			((Hme15flg) (Home15FLG))
			((Mclk) (Mclk))
			((PWRint) (NET2528))
			((Reset) (Reset))
			((inDATA) (BUS5075))
			((outDATA) (outDATA))
		)
		(_strength strong0 strong1)
	)
	(_instantiation U5 0 344 (_entity .  Lswitch)
		(_port
			((Brake0) (Brake0))
			((Brake1) (Brake1))
			((DCORIFGr) (NET1978))
			((DCORIFGw) (NET1989))
			((DCORLIMITSr) (NET2047))
			((DIR0) (DIR0))
			((DIR1) (DIR1))
			((FLS0) (FLS0))
			((FLS1) (FLS1))
			((Home0) (Home0))
			((Home1) (Home1))
			((LSwitchInt) (NET2575))
			((Mclk) (Mclk))
			((RLS0) (RLS0))
			((RLS1) (RLS1))
			((Reset) (Reset))
			((fBRK0) (NET3248))
			((fBRK1) (NET3253))
			((inDATA) (BUS5075))
			((outDATA) (outDATA))
		)
		(_strength strong0 strong1)
	)
	(_instantiation U6 0 370 (_entity .  I2CAddress)
		(_port
			((DCORCONFIGr) (NET2064))
			((I2CS) (I2CS))
			((MotorIn0) (GP_Motor0_0))
			((MotorIn1) (NET5008))
			((outDATA) (outDATA))
		)
		(_strength strong0 strong1)
	)
	(_instantiation U7 0 381 (_entity .  PWMcontrol)
		(_port
			((Brake1) (Brake0))
			((Brake2) (Brake1))
			((DIR1) (DIR0))
			((DIR2) (DIR1))
			((HBRK1) (NET3248))
			((HBRK2) (NET3253))
			((PAH1) (PAH0))
			((PAH2) (PBL1))
			((PAL1) (PAL0))
			((PAL2) (PBH1))
			((PBH1) (PBH0))
			((PBH2) (PAL1))
			((PBL1) (PBL0))
			((PBL2) (PAH1))
			((PWM1) (PWM1))
			((PWM2) (PWM2))
			((fBRK1) (NET3248))
			((fBRK2) (NET3253))
		)
		(_strength strong0 strong1)
	)
	(_instantiation U9 0 405 (_entity .  MISCouts)
		(_port
			((DCOROUTw) (NET2017))
			((LED1) (LED1))
			((LED2) (LED2))
			((LED3) (LED3))
			((LED4) (LED4))
			((LED5) (LED5))
			((LightSense) (LightSense))
			((MTRpwr) (MTRpwr))
			((MTRpwrn) (MTRpwrn))
			((Mclk) (Mclk))
			((Reset) (Reset))
			((inDATA) (BUS5075))
			((GP_Motor0_1) (_open))
			((GP_Motor1_1) (_open))
		)
		(_strength strong0 strong1)
	)
	(_model . U21 15 -1)

)
V 000044 55 24156         1079994771075 U21
(_unit VERILOG 6.349C.6.256 (U21 0 32 (U21 0 32 ))
	(_version v32)
	(_time 1079994770996 2004.03.22 14:32:50)
	(_source (\./compile/u21.v\ VERILOG (\./compile/u21.v\ VERILOG)))
	(_use (std(standard))(vl(verilog_logic)))
	(_base (E 15))
	(_entity
		(_time 1079994770996)
		(_use )
	)
	(_timescale 1ns 1ns)
	(_parameters    dbg   accs  )
	(_attribute )
	(_object
		(_type (_internal ~vector~0 0 190 (_array ~bit ((_uto (i 0) (i 0))))))
		(_generic (_internal DANGLING_INPUT_CONSTANT ~vector~0 0 190 \1'bZ\ (_entity -1 (_constant \1'bZ\))))
		(_port (_internal AS ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Brake0 ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Brake1 ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal DIR0 ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal DIR1 ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Enc033FLG ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Enc05FLG ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Enc133FLG ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Enc15FLG ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal FLS0 ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal FLS1 ~wire 0 33 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal GP_Motor0_0 ~wire 0 33 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal GP_Motor1_0 ~wire 0 33 (_architecture (_in ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal HSI ~wire 0 33 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal Home0 ~wire 0 33 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Home033FLG ~wire 0 33 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Home05FLG ~wire 0 33 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Home1 ~wire 0 33 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Home133FLG ~wire 0 33 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Home15FLG ~wire 0 33 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal INTbus ~wire 0 34 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal LightSense ~wire 0 34 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal MHSO ~wire 0 34 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal Mclk ~wire 0 34 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal PWM1 ~wire 0 34 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PWM2 ~wire 0 34 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PhaseA_Encoder0 ~wire 0 34 (_architecture (_in ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PhaseA_Encoder1 ~wire 0 34 (_architecture (_in ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PhaseB_Encoder0 ~wire 0 34 (_architecture (_in ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PhaseB_Encoder1 ~wire 0 34 (_architecture (_in ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal RD ~wire 0 35 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal RLS0 ~wire 0 35 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal RLS1 ~wire 0 35 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Reset ~wire 0 35 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal SCLinc ~wire 0 35 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal SCLreset ~wire 0 35 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal TXI ~wire 0 35 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal WR ~wire 0 35 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_type (_internal ~[5:0]wire~ 0 35 (_array ~wire ((_downto (i 5) (i 0))))))
		(_port (_internal I2CS ~[5:0]wire~ 0 35 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Enc033ctrl ~wire 0 35 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Enc05ctrl ~wire 0 36 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Enc133ctrl ~wire 0 36 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Enc15ctrl ~wire 0 36 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal GP_Motor0_1 ~wire 0 36 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal GP_Motor1_1 ~wire 0 36 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal HSO ~wire 0 36 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal Home033ctrl ~wire 0 36 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Home05ctrl ~wire 0 36 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Home133ctrl ~wire 0 36 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Home15ctrl ~wire 0 36 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal INT ~wire 0 37 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal LED1 ~wire 0 37 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal LED2 ~wire 0 37 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal LED3 ~wire 0 37 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal LED4 ~wire 0 37 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal LED5 ~wire 0 37 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal MHSI ~wire 0 37 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal MTRpwr ~wire 0 37 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal MTRpwrn ~wire 0 37 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal MTXI ~wire 0 37 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal PAH0 ~wire 0 38 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PAH1 ~wire 0 38 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PAL0 ~wire 0 38 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PAL1 ~wire 0 38 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PBH0 ~wire 0 38 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PBH1 ~wire 0 38 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PBL0 ~wire 0 38 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PBL1 ~wire 0 38 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal TP10 ~wire 0 38 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal TP11 ~wire 0 38 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal TP12 ~wire 0 39 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal SCL ~wire 0 39 (_architecture (_inout ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_type (_internal ~[7:0]wire~ 0 39 (_array ~wire ((_downto (i 7) (i 0))))))
		(_port (_internal AD ~[7:0]wire~ 0 39 (_architecture (_inout ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal clk ~wire 0 193 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal NET1635 ~wire 0 194 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET1643 ~wire 0 195 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET1651 ~wire 0 196 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET1667 ~wire 0 197 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET1978 ~wire 0 198 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET1989 ~wire 0 199 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET2017 ~wire 0 200 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET2025 ~wire 0 201 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET2036 ~wire 0 202 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET2047 ~wire 0 203 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET2064 ~wire 0 204 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET2078 ~wire 0 205 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET2311 ~wire 0 206 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET2528 ~wire 0 207 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET2539 ~wire 0 208 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET2575 ~wire 0 209 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET3248 ~wire 0 210 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET3253 ~wire 0 211 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET3919 ~wire 0 212 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal NET3926 ~wire 0 213 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal NET5008 ~wire 0 214 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET5863 ~wire 0 215 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET615 ~wire 0 216 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal NET621 ~wire 0 217 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal NET629 ~wire 0 218 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal reset ~wire 0 219 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal BUS1564 ~[7:0]wire~ 0 220 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal BUS5075 ~[7:0]wire~ 0 221 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal outDATA ~[7:0]wire~ 0 222 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal Dangling_Input_Signal ~wire 0 225 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_subprogram
			

		)
		(_type (_external ~wire (vl verilog_logic wire)))
		(_type (_external ~reg (vl verilog_logic reg)))
		(_type (_external ~event (vl verilog_logic event)))
		(_type (_external ~wand (vl verilog_logic wand)))
		(_type (_external ~wor (vl verilog_logic wor)))
		(_type (_external ~tri1 (vl verilog_logic tri1)))
		(_type (_external ~tri0 (vl verilog_logic tri0)))
		(_type (_external ~trireg (vl verilog_logic trireg)))
		(_type (_external ~supply0 (vl verilog_logic supply0)))
		(_type (_external ~supply1 (vl verilog_logic supply1)))
		(_type (_external ~real (vl verilog_logic real)))
		(_type (_external ~realtime (vl verilog_logic realtime)))
		(_type (_external ~tri (vl verilog_logic tri)))
		(_type (_external ~triand (vl verilog_logic triand)))
		(_type (_external ~trior (vl verilog_logic trior)))
		(_type (_external ~bit (vl verilog_logic bit)))
		(_type (_external ~extstd.standard.integer (std standard integer)))
		(_type (_external ~extstd.standard.bit (std standard bit)))
		(_process
			(#ASSIGN#225_0 (_architecture 0 0 225 (_process (_simple)
				(_target(103))
			)))
			(#ASSIGN#426_1 (_architecture 1 0 426 (_process (_alias ((clk)(Mclk)))(_simple)
				(_target(73))
				(_sensitivity(23))
			)))
			(#ASSIGN#427_2 (_architecture 2 0 427 (_process (_alias ((NET3919)(SCLreset)))(_simple)
				(_target(92))
				(_sensitivity(35))
			)))
			(#ASSIGN#428_3 (_architecture 3 0 428 (_process (_alias ((NET3926)(SCLinc)))(_simple)
				(_target(93))
				(_sensitivity(34))
			)))
			(#ASSIGN#429_4 (_architecture 4 0 429 (_process (_alias ((NET615)(MHSO)))(_simple)
				(_target(96))
				(_sensitivity(22))
			)))
			(#ASSIGN#430_5 (_architecture 5 0 430 (_process (_alias ((NET621)(HSI)))(_simple)
				(_target(97))
				(_sensitivity(13))
			)))
			(#ASSIGN#431_6 (_architecture 6 0 431 (_process (_alias ((NET629)(TXI)))(_simple)
				(_target(98))
				(_sensitivity(36))
			)))
			(#ASSIGN#432_7 (_architecture 7 0 432 (_process (_alias ((reset)(Reset)))(_simple)
				(_target(99))
				(_sensitivity(33))
			)))
			(#ASSIGN#435_8 (_architecture 8 0 435 (_process (_alias ((HSO)(NET615)))(_simple)
				(_target(45))
				(_sensitivity(96))
			)))
			(#ASSIGN#436_9 (_architecture 9 0 436 (_process (_alias ((MHSI)(NET621)))(_simple)
				(_target(56))
				(_sensitivity(97))
			)))
			(#ASSIGN#437_10 (_architecture 10 0 437 (_process (_alias ((MTXI)(NET629)))(_simple)
				(_target(59))
				(_sensitivity(98))
			)))
			(#ASSIGN#438_11 (_architecture 11 0 438 (_process (_alias ((TP10)(NET3919)))(_simple)
				(_target(68))
				(_sensitivity(92))
			)))
			(#ASSIGN#439_12 (_architecture 12 0 439 (_process (_alias ((TP11)(NET3926)))(_simple)
				(_target(69))
				(_sensitivity(93))
			)))
			(#ASSIGN#440_13 (_architecture 13 0 440 (_process (_alias ((TP12)(SCL)))(_simple)
				(_target(70))
				(_sensitivity(71))
			)))
			(#INTERNAL#0_14 (_internal 14 0 0 (_process (_virtual))))
		)
	)
	
	
	(_defparam
	)
	(_scope
	)
	(_instantiation U1 0 229 (_entity .  reader)
		(_port
			((RVALVECTLw) (NET1635))
			((RVALVEHIGHr) (NET1643))
			((RVALVELOWr) (NET1651))
			((RVALVESTATr) (NET1667))
			((SSclk) (GP_Motor0_1))
			((clk) (clk))
			((data) (GP_Motor0_0))
			((outDATA) (outDATA))
			((reset) (reset))
		)
		(_strength strong0 strong1)
	)
	(_instantiation U11 0 244 (_entity .  I2Cfix)
		(_port
			((DCORI2CCNTr) (NET2311))
			((Inc) (NET3926))
			((Mclk) (Mclk))
			((SCL) (SCL))
			((SCLint) (NET2539))
			((SCLreset) (NET3919))
			((outDATA) (outDATA))
			((SCLenable) (_open))
		)
		(_strength strong0 strong1)
	)
	(_instantiation U12 0 257 (_entity .  U21AddDecode)
		(_port
			((ADDR) (BUS1564))
			((AS) (AS))
			((DCOR0CNTHIGHr) (NET1667))
			((DCOR0CNTLOWr) (NET1651))
			((DCOR0CNTMIDr) (NET1643))
			((DCORCONFIGr) (NET2064))
			((DCORENCCTLw) (NET1635))
			((DCORENCPWRr) (NET2036))
			((DCORENCPWRw) (NET2025))
			((DCORI2CCNTr) (NET2311))
			((DCORIEw) (NET2078))
			((DCORIFGr) (NET1978))
			((DCORIFGw) (NET1989))
			((DCORLIMITSr) (NET2047))
			((DCOROUTw) (NET2017))
			((RD) (RD))
			((WR) (WR))
			((DCOR0THRESLOWr) (_open))
			((DCOR1CNTLOWr) (_open))
			((DCOR1THRESLOWr) (_open))
			((DCOR0THRESMIDr) (_open))
			((DCOR1CNTMIDr) (_open))
			((DCOR1THRESMIDr) (_open))
			((DCOR1CNTHIGHr) (_open))
		)
		(_strength strong0 strong1)
	)
	(_instantiation U2 0 280 (_entity .  Interface)
		(_port
			((AD) (AD))
			((ADDR) (BUS1564))
			((AS) (AS))
			((Mclk) (Mclk))
			((RD) (RD))
			((Reset) (Reset))
			((WR) (WR))
			((inDATA) (BUS5075))
			((outDATA) (outDATA))
			((ASleading) (_open))
		)
		(_strength strong0 strong1)
	)
	(_instantiation U3 0 295 (_entity .  Interrupt)
		(_port
			((BusInt) (INTbus))
			((DCORIEw) (NET2078))
			((Homed0) (Dangling_Input_Signal))
			((Homed1) (Dangling_Input_Signal))
			((I2Cint) (NET2539))
			((INT) (INT))
			((LSwitchInt) (NET2575))
			((Mclk) (Mclk))
			((PWRint) (NET2528))
			((Reset) (Reset))
			((Thres0) (Dangling_Input_Signal))
			((Thres1) (Dangling_Input_Signal))
			((inDATA) (BUS5075))
		)
		(_strength strong0 strong1)
	)
	(_instantiation U4 0 314 (_entity .  PWRreg)
		(_port
			((DCORENCPWRr) (NET2036))
			((DCORENCPWRw) (NET2025))
			((DCORIFGr) (NET1978))
			((DCORIFGw) (NET1989))
			((Enc033ctl) (Home15ctrl))
			((Enc033flg) (Enc033FLG))
			((Enc05ctl) (Home133ctrl))
			((Enc05flg) (Enc05FLG))
			((Enc133ctl) (Home05ctrl))
			((Enc133flg) (Enc133FLG))
			((Enc15ctl) (Home033ctrl))
			((Enc15flg) (Enc15FLG))
			((Hme033ctl) (Enc15ctrl))
			((Hme033flg) (Home033FLG))
			((Hme05ctl) (Enc133ctrl))
			((Hme05flg) (Home05FLG))
			((Hme133ctl) (Enc05ctrl))
			((Hme133flg) (Home133FLG))
			((Hme15ctl) (Enc033ctrl))
			((Hme15flg) (Home15FLG))
			((Mclk) (Mclk))
			((PWRint) (NET2528))
			((Reset) (Reset))
			((inDATA) (BUS5075))
			((outDATA) (outDATA))
		)
		(_strength strong0 strong1)
	)
	(_instantiation U5 0 345 (_entity .  Lswitch)
		(_port
			((Brake0) (Brake0))
			((Brake1) (Brake1))
			((DCORIFGr) (NET1978))
			((DCORIFGw) (NET1989))
			((DCORLIMITSr) (NET2047))
			((DIR0) (DIR0))
			((DIR1) (DIR1))
			((FLS0) (FLS0))
			((FLS1) (FLS1))
			((Home0) (Home0))
			((Home1) (Home1))
			((LSwitchInt) (NET2575))
			((Mclk) (Mclk))
			((RLS0) (RLS0))
			((RLS1) (RLS1))
			((Reset) (Reset))
			((fBRK0) (NET3248))
			((fBRK1) (NET3253))
			((inDATA) (BUS5075))
			((outDATA) (outDATA))
		)
		(_strength strong0 strong1)
	)
	(_instantiation U6 0 371 (_entity .  I2CAddress)
		(_port
			((DCORCONFIGr) (NET2064))
			((I2CS) (I2CS))
			((MotorIn0) (NET5863))
			((MotorIn1) (NET5008))
			((outDATA) (outDATA))
		)
		(_strength strong0 strong1)
	)
	(_instantiation U7 0 382 (_entity .  PWMcontrol)
		(_port
			((Brake1) (Brake0))
			((Brake2) (Brake1))
			((DIR1) (DIR0))
			((DIR2) (DIR1))
			((HBRK1) (NET3248))
			((HBRK2) (NET3253))
			((PAH1) (PAH0))
			((PAH2) (PBL1))
			((PAL1) (PAL0))
			((PAL2) (PBH1))
			((PBH1) (PBH0))
			((PBH2) (PAL1))
			((PBL1) (PBL0))
			((PBL2) (PAH1))
			((PWM1) (PWM1))
			((PWM2) (PWM2))
			((fBRK1) (NET3248))
			((fBRK2) (NET3253))
		)
		(_strength strong0 strong1)
	)
	(_instantiation U9 0 406 (_entity .  MISCouts)
		(_port
			((DCOROUTw) (NET2017))
			((LED1) (LED1))
			((LED2) (LED2))
			((LED3) (LED3))
			((LED4) (LED4))
			((LED5) (LED5))
			((LightSense) (LightSense))
			((MTRpwr) (MTRpwr))
			((MTRpwrn) (MTRpwrn))
			((Mclk) (Mclk))
			((Reset) (Reset))
			((inDATA) (BUS5075))
			((GP_Motor0_1) (_open))
			((GP_Motor1_1) (_open))
		)
		(_strength strong0 strong1)
	)
	(_model . U21 15 -1)

)
I 000053 55 9137          1080050760032 U21AddDecode
(_unit VERILOG 6.349C.6.256 (U21AddDecode 0 27 (U21AddDecode 0 27 ))
	(_version v32)
	(_time 1080050759610 2004.03.23 06:05:59)
	(_source (\./src/u21adddecode.v\ VERILOG (\./src/u21adddecode.v\ VERILOG)))
	(_use (std(standard))(vl(verilog_logic)))
	(_base (E 22))
	(_entity
		(_time 1080050759610)
		(_use )
	)
	(_timescale 1ps 1ps)
	(_parameters    dbg   accs  )
	(_attribute )
	(_object
		(_port (_internal DCOR0CNTLOWr ~wire 0 27 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal DCOR0THRESLOWr ~wire 0 27 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal DCOR1CNTLOWr ~wire 0 27 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal DCOR1THRESLOWr ~wire 0 27 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal DCORENCPWRr ~wire 0 27 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal WR ~wire 0 27 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal DCOR0CNTMIDr ~wire 0 27 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal DCOR0THRESMIDr ~wire 0 27 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal DCOR1CNTMIDr ~wire 0 27 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal DCOR1THRESMIDr ~wire 0 27 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal DCORLIMITSr ~wire 0 27 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal DCORIEw ~wire 0 27 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal DCORENCPWRw ~wire 0 27 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal DCOR0CNTHIGHr ~wire 0 27 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal DCORCONFIGr ~wire 0 27 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal DCORIFGr ~wire 0 27 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal DCOR1CNTHIGHr ~wire 0 27 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal AS ~wire 0 27 (_architecture (_in ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal DCORIFGw ~wire 0 27 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal RD ~wire 0 27 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal DCOROUTw ~wire 0 27 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal DCORENCCTLw ~wire 0 27 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_type (_internal ~[7:0]wire~ 0 27 (_array ~wire ((_downto (i 7) (i 0))))))
		(_port (_internal ADDR ~[7:0]wire~ 0 27 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal DCORI2CCNTr ~wire 0 27 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_type (_internal ~[7:0]reg~ 0 91 (_array ~reg ((_downto (i 7) (i 0))))))
		(_signal (_internal Select.Address ~[7:0]reg~ 0 91 (_subprogram Select (_in ))) (_reg ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal Select.Location ~[7:0]reg~ 0 92 (_subprogram Select (_in ))) (_reg ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal Select.RD ~reg 0 93 (_subprogram Select (_in ))) (_reg ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal Select.WR ~reg 0 93 (_subprogram Select (_in ))) (_reg ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal Select.RorW ~reg 0 94 (_subprogram Select (_in ))) (_reg ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal Select.Select ~reg 0 0 (_subprogram Select (_out ))) (_reg ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_subprogram
			
			(_internal Select 20 0 90 (_architecture (_function)(_target(29))
				(_read(28)(26)(27)(22)(25))
			))

		)
		(_type (_external ~wire (vl verilog_logic wire)))
		(_type (_external ~reg (vl verilog_logic reg)))
		(_type (_external ~event (vl verilog_logic event)))
		(_type (_external ~wand (vl verilog_logic wand)))
		(_type (_external ~wor (vl verilog_logic wor)))
		(_type (_external ~tri1 (vl verilog_logic tri1)))
		(_type (_external ~tri0 (vl verilog_logic tri0)))
		(_type (_external ~trireg (vl verilog_logic trireg)))
		(_type (_external ~supply0 (vl verilog_logic supply0)))
		(_type (_external ~supply1 (vl verilog_logic supply1)))
		(_type (_external ~real (vl verilog_logic real)))
		(_type (_external ~realtime (vl verilog_logic realtime)))
		(_type (_external ~tri (vl verilog_logic tri)))
		(_type (_external ~triand (vl verilog_logic triand)))
		(_type (_external ~trior (vl verilog_logic trior)))
		(_type (_external ~bit (vl verilog_logic bit)))
		(_type (_external ~extstd.standard.integer (std standard integer)))
		(_type (_external ~extstd.standard.bit (std standard bit)))
		(_process
			(#ASSIGN#102_0 (_architecture 0 0 102 (_process (_simple)
				(_target(11))
				(_sensitivity(22)(19)(5))
				(_call(0))
			)))
			(#ASSIGN#105_1 (_architecture 1 0 105 (_process (_simple)
				(_target(18))
				(_sensitivity(22)(19)(5))
				(_call(0))
			)))
			(#ASSIGN#108_2 (_architecture 2 0 108 (_process (_simple)
				(_target(15))
				(_sensitivity(22)(19)(5))
				(_call(0))
			)))
			(#ASSIGN#111_3 (_architecture 3 0 111 (_process (_simple)
				(_target(10))
				(_sensitivity(22)(19)(5))
				(_call(0))
			)))
			(#ASSIGN#114_4 (_architecture 4 0 114 (_process (_simple)
				(_target(21))
				(_sensitivity(22)(19)(5))
				(_call(0))
			)))
			(#ASSIGN#117_5 (_architecture 5 0 117 (_process (_simple)
				(_target(0))
				(_sensitivity(22)(19)(5))
				(_call(0))
			)))
			(#ASSIGN#120_6 (_architecture 6 0 120 (_process (_simple)
				(_target(6))
				(_sensitivity(22)(19)(5))
				(_call(0))
			)))
			(#ASSIGN#123_7 (_architecture 7 0 123 (_process (_simple)
				(_target(13))
				(_sensitivity(22)(19)(5))
				(_call(0))
			)))
			(#ASSIGN#126_8 (_architecture 8 0 126 (_process (_simple)
				(_target(2))
				(_sensitivity(22)(19)(5))
				(_call(0))
			)))
			(#ASSIGN#129_9 (_architecture 9 0 129 (_process (_simple)
				(_target(8))
				(_sensitivity(22)(19)(5))
				(_call(0))
			)))
			(#ASSIGN#132_10 (_architecture 10 0 132 (_process (_simple)
				(_target(16))
				(_sensitivity(22)(19)(5))
				(_call(0))
			)))
			(#ASSIGN#135_11 (_architecture 11 0 135 (_process (_simple)
				(_target(1))
				(_sensitivity(22)(19)(5))
				(_call(0))
			)))
			(#ASSIGN#138_12 (_architecture 12 0 138 (_process (_simple)
				(_target(7))
				(_sensitivity(22)(19)(5))
				(_call(0))
			)))
			(#ASSIGN#141_13 (_architecture 13 0 141 (_process (_simple)
				(_target(3))
				(_sensitivity(22)(19)(5))
				(_call(0))
			)))
			(#ASSIGN#144_14 (_architecture 14 0 144 (_process (_simple)
				(_target(9))
				(_sensitivity(22)(19)(5))
				(_call(0))
			)))
			(#ASSIGN#147_15 (_architecture 15 0 147 (_process (_simple)
				(_target(4))
				(_sensitivity(22)(19)(5))
				(_call(0))
			)))
			(#ASSIGN#150_16 (_architecture 16 0 150 (_process (_simple)
				(_target(12))
				(_sensitivity(22)(19)(5))
				(_call(0))
			)))
			(#ASSIGN#153_17 (_architecture 17 0 153 (_process (_simple)
				(_target(14))
				(_sensitivity(22)(19)(5))
				(_call(0))
			)))
			(#ASSIGN#156_18 (_architecture 18 0 156 (_process (_simple)
				(_target(20))
				(_sensitivity(22)(19)(5))
				(_call(0))
			)))
			(#ASSIGN#159_19 (_architecture 19 0 159 (_process (_simple)
				(_target(23))
				(_sensitivity(22)(19)(5))
				(_call(0))
			)))
			(#INTERNAL#0_21 (_internal 21 0 0 (_process (_virtual))))
		)
	)
	
	
	(_defparam
	)
	(_scope
		(_unit Select function 0 90
		)
	)
	(_model . U21AddDecode 22 -1)

)
V 000044 55 23996         1080051936485 U21
(_unit VERILOG 6.349C.6.256 (U21 0 32 (U21 0 32 ))
	(_version v32)
	(_time 1080051935828 2004.03.23 06:25:35)
	(_source (\./compile/u21.v\ VERILOG (\./compile/u21.v\ VERILOG)))
	(_use (std(standard))(vl(verilog_logic)))
	(_base (E 15))
	(_entity
		(_time 1080051935828)
		(_use )
	)
	(_timescale 1ns 1ns)
	(_parameters    dbg   accs  )
	(_attribute )
	(_object
		(_type (_internal ~vector~0 0 190 (_array ~bit ((_uto (i 0) (i 0))))))
		(_generic (_internal DANGLING_INPUT_CONSTANT ~vector~0 0 190 \1'bZ\ (_entity -1 (_constant \1'bZ\))))
		(_port (_internal AS ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Brake0 ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Brake1 ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal DIR0 ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal DIR1 ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Enc033FLG ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Enc05FLG ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Enc133FLG ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Enc15FLG ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal FLS0 ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal FLS1 ~wire 0 33 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal GP_Motor0_0 ~wire 0 33 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal GP_Motor1_0 ~wire 0 33 (_architecture (_in ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal HSI ~wire 0 33 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal Home0 ~wire 0 33 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Home033FLG ~wire 0 33 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Home05FLG ~wire 0 33 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Home1 ~wire 0 33 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Home133FLG ~wire 0 33 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Home15FLG ~wire 0 33 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal INTbus ~wire 0 34 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal LightSense ~wire 0 34 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal MHSO ~wire 0 34 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal Mclk ~wire 0 34 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal PWM1 ~wire 0 34 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PWM2 ~wire 0 34 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PhaseA_Encoder0 ~wire 0 34 (_architecture (_in ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PhaseA_Encoder1 ~wire 0 34 (_architecture (_in ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PhaseB_Encoder0 ~wire 0 34 (_architecture (_in ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PhaseB_Encoder1 ~wire 0 34 (_architecture (_in ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal RD ~wire 0 35 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal RLS0 ~wire 0 35 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal RLS1 ~wire 0 35 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Reset ~wire 0 35 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal SCLinc ~wire 0 35 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal SCLreset ~wire 0 35 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal TXI ~wire 0 35 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal WR ~wire 0 35 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_type (_internal ~[5:0]wire~ 0 35 (_array ~wire ((_downto (i 5) (i 0))))))
		(_port (_internal I2CS ~[5:0]wire~ 0 35 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Enc033ctrl ~wire 0 35 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Enc05ctrl ~wire 0 36 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Enc133ctrl ~wire 0 36 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Enc15ctrl ~wire 0 36 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal GP_Motor0_1 ~wire 0 36 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal GP_Motor1_1 ~wire 0 36 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal HSO ~wire 0 36 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal Home033ctrl ~wire 0 36 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Home05ctrl ~wire 0 36 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Home133ctrl ~wire 0 36 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Home15ctrl ~wire 0 36 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal INT ~wire 0 37 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal LED1 ~wire 0 37 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal LED2 ~wire 0 37 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal LED3 ~wire 0 37 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal LED4 ~wire 0 37 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal LED5 ~wire 0 37 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal MHSI ~wire 0 37 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal MTRpwr ~wire 0 37 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal MTRpwrn ~wire 0 37 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal MTXI ~wire 0 37 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal PAH0 ~wire 0 38 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PAH1 ~wire 0 38 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PAL0 ~wire 0 38 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PAL1 ~wire 0 38 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PBH0 ~wire 0 38 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PBH1 ~wire 0 38 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PBL0 ~wire 0 38 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PBL1 ~wire 0 38 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal TP10 ~wire 0 38 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal TP11 ~wire 0 38 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal TP12 ~wire 0 39 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal SCL ~wire 0 39 (_architecture (_inout ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_type (_internal ~[7:0]wire~ 0 39 (_array ~wire ((_downto (i 7) (i 0))))))
		(_port (_internal AD ~[7:0]wire~ 0 39 (_architecture (_inout ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal clk ~wire 0 193 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal NET1635 ~wire 0 194 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET1643 ~wire 0 195 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET1651 ~wire 0 196 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET1667 ~wire 0 197 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET1978 ~wire 0 198 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET1989 ~wire 0 199 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET2017 ~wire 0 200 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET2025 ~wire 0 201 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET2036 ~wire 0 202 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET2047 ~wire 0 203 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET2064 ~wire 0 204 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET2078 ~wire 0 205 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET2311 ~wire 0 206 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET2528 ~wire 0 207 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET2539 ~wire 0 208 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET2575 ~wire 0 209 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET3248 ~wire 0 210 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET3253 ~wire 0 211 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET3919 ~wire 0 212 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal NET3926 ~wire 0 213 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal NET5008 ~wire 0 214 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET5863 ~wire 0 215 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET615 ~wire 0 216 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal NET621 ~wire 0 217 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal NET629 ~wire 0 218 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal reset ~wire 0 219 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal BUS1564 ~[7:0]wire~ 0 220 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal BUS5075 ~[7:0]wire~ 0 221 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal outDATA ~[7:0]wire~ 0 222 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal Dangling_Input_Signal ~wire 0 225 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_subprogram
			

		)
		(_type (_external ~wire (vl verilog_logic wire)))
		(_type (_external ~reg (vl verilog_logic reg)))
		(_type (_external ~event (vl verilog_logic event)))
		(_type (_external ~wand (vl verilog_logic wand)))
		(_type (_external ~wor (vl verilog_logic wor)))
		(_type (_external ~tri1 (vl verilog_logic tri1)))
		(_type (_external ~tri0 (vl verilog_logic tri0)))
		(_type (_external ~trireg (vl verilog_logic trireg)))
		(_type (_external ~supply0 (vl verilog_logic supply0)))
		(_type (_external ~supply1 (vl verilog_logic supply1)))
		(_type (_external ~real (vl verilog_logic real)))
		(_type (_external ~realtime (vl verilog_logic realtime)))
		(_type (_external ~tri (vl verilog_logic tri)))
		(_type (_external ~triand (vl verilog_logic triand)))
		(_type (_external ~trior (vl verilog_logic trior)))
		(_type (_external ~bit (vl verilog_logic bit)))
		(_type (_external ~extstd.standard.integer (std standard integer)))
		(_type (_external ~extstd.standard.bit (std standard bit)))
		(_process
			(#ASSIGN#225_0 (_architecture 0 0 225 (_process (_simple)
				(_target(103))
			)))
			(#ASSIGN#426_1 (_architecture 1 0 426 (_process (_alias ((clk)(Mclk)))(_simple)
				(_target(73))
				(_sensitivity(23))
			)))
			(#ASSIGN#427_2 (_architecture 2 0 427 (_process (_alias ((NET3919)(SCLreset)))(_simple)
				(_target(92))
				(_sensitivity(35))
			)))
			(#ASSIGN#428_3 (_architecture 3 0 428 (_process (_alias ((NET3926)(SCLinc)))(_simple)
				(_target(93))
				(_sensitivity(34))
			)))
			(#ASSIGN#429_4 (_architecture 4 0 429 (_process (_alias ((NET615)(MHSO)))(_simple)
				(_target(96))
				(_sensitivity(22))
			)))
			(#ASSIGN#430_5 (_architecture 5 0 430 (_process (_alias ((NET621)(HSI)))(_simple)
				(_target(97))
				(_sensitivity(13))
			)))
			(#ASSIGN#431_6 (_architecture 6 0 431 (_process (_alias ((NET629)(TXI)))(_simple)
				(_target(98))
				(_sensitivity(36))
			)))
			(#ASSIGN#432_7 (_architecture 7 0 432 (_process (_alias ((reset)(Reset)))(_simple)
				(_target(99))
				(_sensitivity(33))
			)))
			(#ASSIGN#435_8 (_architecture 8 0 435 (_process (_alias ((HSO)(NET615)))(_simple)
				(_target(45))
				(_sensitivity(96))
			)))
			(#ASSIGN#436_9 (_architecture 9 0 436 (_process (_alias ((MHSI)(NET621)))(_simple)
				(_target(56))
				(_sensitivity(97))
			)))
			(#ASSIGN#437_10 (_architecture 10 0 437 (_process (_alias ((MTXI)(NET629)))(_simple)
				(_target(59))
				(_sensitivity(98))
			)))
			(#ASSIGN#438_11 (_architecture 11 0 438 (_process (_alias ((TP10)(NET3919)))(_simple)
				(_target(68))
				(_sensitivity(92))
			)))
			(#ASSIGN#439_12 (_architecture 12 0 439 (_process (_alias ((TP11)(NET3926)))(_simple)
				(_target(69))
				(_sensitivity(93))
			)))
			(#ASSIGN#440_13 (_architecture 13 0 440 (_process (_alias ((TP12)(SCL)))(_simple)
				(_target(70))
				(_sensitivity(71))
			)))
			(#INTERNAL#0_14 (_internal 14 0 0 (_process (_virtual))))
		)
	)
	
	
	(_defparam
	)
	(_scope
	)
	(_instantiation U1 0 229 (_entity .  reader)
		(_port
			((RVALVECTLw) (NET1635))
			((RVALVEHIGHr) (NET1643))
			((RVALVELOWr) (NET1651))
			((RVALVESTATr) (NET1667))
			((SSclk) (GP_Motor0_1))
			((clk) (clk))
			((data) (GP_Motor0_0))
			((outDATA) (outDATA))
			((reset) (reset))
		)
		(_strength)
	)
	(_instantiation U11 0 244 (_entity .  I2Cfix)
		(_port
			((DCORI2CCNTr) (NET2311))
			((Inc) (NET3926))
			((Mclk) (Mclk))
			((SCL) (SCL))
			((SCLint) (NET2539))
			((SCLreset) (NET3919))
			((outDATA) (outDATA))
			((SCLenable) (_open))
		)
		(_strength)
	)
	(_instantiation U12 0 257 (_entity .  U21AddDecode)
		(_port
			((ADDR) (BUS1564))
			((AS) (AS))
			((DCOR0CNTHIGHr) (NET1667))
			((DCOR0CNTLOWr) (NET1651))
			((DCOR0CNTMIDr) (NET1643))
			((DCORCONFIGr) (NET2064))
			((DCORENCCTLw) (NET1635))
			((DCORENCPWRr) (NET2036))
			((DCORENCPWRw) (NET2025))
			((DCORI2CCNTr) (NET2311))
			((DCORIEw) (NET2078))
			((DCORIFGr) (NET1978))
			((DCORIFGw) (NET1989))
			((DCORLIMITSr) (NET2047))
			((DCOROUTw) (NET2017))
			((RD) (RD))
			((WR) (WR))
			((DCOR0THRESLOWr) (_open))
			((DCOR1CNTLOWr) (_open))
			((DCOR1THRESLOWr) (_open))
			((DCOR0THRESMIDr) (_open))
			((DCOR1CNTMIDr) (_open))
			((DCOR1THRESMIDr) (_open))
			((DCOR1CNTHIGHr) (_open))
		)
		(_strength)
	)
	(_instantiation U2 0 280 (_entity .  Interface)
		(_port
			((AD) (AD))
			((ADDR) (BUS1564))
			((AS) (AS))
			((Mclk) (Mclk))
			((RD) (RD))
			((Reset) (Reset))
			((WR) (WR))
			((inDATA) (BUS5075))
			((outDATA) (outDATA))
			((ASleading) (_open))
		)
		(_strength)
	)
	(_instantiation U3 0 295 (_entity .  Interrupt)
		(_port
			((BusInt) (INTbus))
			((DCORIEw) (NET2078))
			((Homed0) (Dangling_Input_Signal))
			((Homed1) (Dangling_Input_Signal))
			((I2Cint) (NET2539))
			((INT) (INT))
			((LSwitchInt) (NET2575))
			((Mclk) (Mclk))
			((PWRint) (NET2528))
			((Reset) (Reset))
			((Thres0) (Dangling_Input_Signal))
			((Thres1) (Dangling_Input_Signal))
			((inDATA) (BUS5075))
		)
		(_strength)
	)
	(_instantiation U4 0 314 (_entity .  PWRreg)
		(_port
			((DCORENCPWRr) (NET2036))
			((DCORENCPWRw) (NET2025))
			((DCORIFGr) (NET1978))
			((DCORIFGw) (NET1989))
			((Enc033ctl) (Home15ctrl))
			((Enc033flg) (Enc033FLG))
			((Enc05ctl) (Home133ctrl))
			((Enc05flg) (Enc05FLG))
			((Enc133ctl) (Home05ctrl))
			((Enc133flg) (Enc133FLG))
			((Enc15ctl) (Home033ctrl))
			((Enc15flg) (Enc15FLG))
			((Hme033ctl) (Enc15ctrl))
			((Hme033flg) (Home033FLG))
			((Hme05ctl) (Enc133ctrl))
			((Hme05flg) (Home05FLG))
			((Hme133ctl) (Enc05ctrl))
			((Hme133flg) (Home133FLG))
			((Hme15ctl) (Enc033ctrl))
			((Hme15flg) (Home15FLG))
			((Mclk) (Mclk))
			((PWRint) (NET2528))
			((Reset) (Reset))
			((inDATA) (BUS5075))
			((outDATA) (outDATA))
		)
		(_strength)
	)
	(_instantiation U5 0 345 (_entity .  Lswitch)
		(_port
			((Brake0) (Brake0))
			((Brake1) (Brake1))
			((DCORIFGr) (NET1978))
			((DCORIFGw) (NET1989))
			((DCORLIMITSr) (NET2047))
			((DIR0) (DIR0))
			((DIR1) (DIR1))
			((FLS0) (FLS0))
			((FLS1) (FLS1))
			((Home0) (Home0))
			((Home1) (Home1))
			((LSwitchInt) (NET2575))
			((Mclk) (Mclk))
			((RLS0) (RLS0))
			((RLS1) (RLS1))
			((Reset) (Reset))
			((fBRK0) (NET3248))
			((fBRK1) (NET3253))
			((inDATA) (BUS5075))
			((outDATA) (outDATA))
		)
		(_strength)
	)
	(_instantiation U6 0 371 (_entity .  I2CAddress)
		(_port
			((DCORCONFIGr) (NET2064))
			((I2CS) (I2CS))
			((MotorIn0) (NET5863))
			((MotorIn1) (NET5008))
			((outDATA) (outDATA))
		)
		(_strength)
	)
	(_instantiation U7 0 382 (_entity .  PWMcontrol)
		(_port
			((Brake1) (Brake0))
			((Brake2) (Brake1))
			((DIR1) (DIR0))
			((DIR2) (DIR1))
			((HBRK1) (NET3248))
			((HBRK2) (NET3253))
			((PAH1) (PAH0))
			((PAH2) (PBL1))
			((PAL1) (PAL0))
			((PAL2) (PBH1))
			((PBH1) (PBH0))
			((PBH2) (PAL1))
			((PBL1) (PBL0))
			((PBL2) (PAH1))
			((PWM1) (PWM1))
			((PWM2) (PWM2))
			((fBRK1) (NET3248))
			((fBRK2) (NET3253))
		)
		(_strength)
	)
	(_instantiation U9 0 406 (_entity .  MISCouts)
		(_port
			((DCOROUTw) (NET2017))
			((LED1) (LED1))
			((LED2) (LED2))
			((LED3) (LED3))
			((LED4) (LED4))
			((LED5) (LED5))
			((LightSense) (LightSense))
			((MTRpwr) (MTRpwr))
			((MTRpwrn) (MTRpwrn))
			((Mclk) (Mclk))
			((Reset) (Reset))
			((inDATA) (BUS5075))
			((GP_Motor0_1) (_open))
			((GP_Motor1_1) (_open))
		)
		(_strength)
	)
	(_model . U21 15 -1)

)
V 000047 55 4239          1080051936516 reader
(_unit VERILOG 6.349C.6.256 (reader 0 32 (reader 0 32 ))
	(_version v32)
	(_time 1080051935828 2004.03.23 06:25:35)
	(_source (\./compile/reader.v\ VERILOG (\./compile/reader.v\ VERILOG)))
	(_use (std(standard))(vl(verilog_logic)))
	(_base (E 2))
	(_entity
		(_time 1080051935828)
		(_use )
	)
	(_timescale 1ns 1ns)
	(_parameters    dbg   accs  )
	(_attribute )
	(_object
		(_port (_internal RVALVECTLw ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal RVALVEHIGHr ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal RVALVELOWr ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal RVALVESTATr ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal data ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal SSclk ~wire 0 32 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal clk ~wire 0 32 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal reset ~wire 0 32 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_type (_internal ~[7:0]wire~ 0 32 (_array ~wire ((_downto (i 7) (i 0))))))
		(_port (_internal outDATA ~[7:0]wire~ 0 32 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET1330 ~wire 0 55 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET843 ~wire 0 56 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_type (_internal ~[5:0]wire~ 0 57 (_array ~wire ((_downto (i 5) (i 0))))))
		(_signal (_internal SSclkb ~[5:0]wire~ 0 57 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_subprogram
			

		)
		(_type (_external ~wire (vl verilog_logic wire)))
		(_type (_external ~reg (vl verilog_logic reg)))
		(_type (_external ~event (vl verilog_logic event)))
		(_type (_external ~wand (vl verilog_logic wand)))
		(_type (_external ~wor (vl verilog_logic wor)))
		(_type (_external ~tri1 (vl verilog_logic tri1)))
		(_type (_external ~tri0 (vl verilog_logic tri0)))
		(_type (_external ~trireg (vl verilog_logic trireg)))
		(_type (_external ~supply0 (vl verilog_logic supply0)))
		(_type (_external ~supply1 (vl verilog_logic supply1)))
		(_type (_external ~real (vl verilog_logic real)))
		(_type (_external ~realtime (vl verilog_logic realtime)))
		(_type (_external ~tri (vl verilog_logic tri)))
		(_type (_external ~triand (vl verilog_logic triand)))
		(_type (_external ~trior (vl verilog_logic trior)))
		(_type (_external ~bit (vl verilog_logic bit)))
		(_type (_external ~extstd.standard.integer (std standard integer)))
		(_type (_external ~extstd.standard.bit (std standard bit)))
		(_process
			(#ASSIGN#98_0 (_architecture 0 0 98 (_process (_alias ((SSclk)(SSclkb(1))))(_simple)
				(_target(5))
				(_sensitivity(11(1)))
			)))
		)
	)
	
	
	(_defparam
	)
	(_scope
	)
	(_instantiation U3 0 61 (_entity .  EncoderEngine)
		(_port
			((DAV) (NET1330))
			((SSclkb) (SSclkb))
			((clk) (clk))
			((data) (data))
			((reset) (reset))
			((shift) (NET843))
			((start) (RVALVECTLw))
		)
		(_strength)
	)
	(_instantiation U4 0 74 (_entity .  Shifter)
		(_port
			((Pdata) (outDATA))
			((RVALVEHIGHr) (RVALVEHIGHr))
			((RVALVELOWr) (RVALVELOWr))
			((clk) (clk))
			((data) (data))
			((reset) (reset))
			((shift) (NET843))
		)
		(_strength)
	)
	(_instantiation U5 0 87 (_entity .  DAVctl)
		(_port
			((DAVin) (NET1330))
			((Pdata) (outDATA))
			((RVALVESTATr) (RVALVESTATr))
		)
		(_strength)
	)
	(_model . reader 2 -1)

)
V 000047 55 3691          1080051936531 I2Cfix
(_unit VERILOG 6.349C.6.256 (I2Cfix 0 32 (I2Cfix 0 32 ))
	(_version v32)
	(_time 1080051935828 2004.03.23 06:25:35)
	(_source (\./compile/I2Cfix.v\ VERILOG (\./compile/i2cfix.v\ VERILOG)))
	(_use (std(standard))(vl(verilog_logic)))
	(_base (E 1))
	(_entity
		(_time 1080051935828)
		(_use )
	)
	(_timescale 1ns 1ns)
	(_parameters    dbg   accs  )
	(_attribute )
	(_object
		(_port (_internal DCORI2CCNTr ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Inc ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Mclk ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal SCLreset ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal SCLenable ~wire 0 32 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal SCLint ~wire 0 32 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_type (_internal ~[7:0]wire~ 0 32 (_array ~wire ((_downto (i 7) (i 0))))))
		(_port (_internal outDATA ~[7:0]wire~ 0 32 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal SCL ~wire 0 32 (_architecture (_inout ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal Incdetect ~wire 0 53 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal SCLdetect ~wire 0 54 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_subprogram
			

		)
		(_type (_external ~wire (vl verilog_logic wire)))
		(_type (_external ~reg (vl verilog_logic reg)))
		(_type (_external ~event (vl verilog_logic event)))
		(_type (_external ~wand (vl verilog_logic wand)))
		(_type (_external ~wor (vl verilog_logic wor)))
		(_type (_external ~tri1 (vl verilog_logic tri1)))
		(_type (_external ~tri0 (vl verilog_logic tri0)))
		(_type (_external ~trireg (vl verilog_logic trireg)))
		(_type (_external ~supply0 (vl verilog_logic supply0)))
		(_type (_external ~supply1 (vl verilog_logic supply1)))
		(_type (_external ~real (vl verilog_logic real)))
		(_type (_external ~realtime (vl verilog_logic realtime)))
		(_type (_external ~tri (vl verilog_logic tri)))
		(_type (_external ~triand (vl verilog_logic triand)))
		(_type (_external ~trior (vl verilog_logic trior)))
		(_type (_external ~bit (vl verilog_logic bit)))
		(_type (_external ~extstd.standard.integer (std standard integer)))
		(_type (_external ~extstd.standard.bit (std standard bit)))
	)
	
	
	(_defparam
	)
	(_scope
	)
	(_instantiation U1 0 58 (_entity .  NegDetect)
		(_port
			((Line) (Inc))
			((Mclk) (Mclk))
			((Ndetect) (Incdetect))
		)
		(_strength)
	)
	(_instantiation U2 0 67 (_entity .  NegDetect)
		(_port
			((Line) (SCL))
			((Mclk) (Mclk))
			((Ndetect) (SCLdetect))
		)
		(_strength)
	)
	(_instantiation U3 0 76 (_entity .  BitCounter)
		(_port
			((DCORI2CCNTr) (DCORI2CCNTr))
			((DriveSCL) (SCL))
			((Inc) (Inc))
			((Mclk) (Mclk))
			((NegInc) (Incdetect))
			((NegSCL) (SCLdetect))
			((SCLenable) (SCLenable))
			((SCLint) (SCLint))
			((SCLreset) (SCLreset))
			((outDATA) (outDATA))
		)
		(_strength)
	)
	(_model . I2Cfix 1 -1)

)
I 000053 55 9137          1080051936547 U21AddDecode
(_unit VERILOG 6.349C.6.256 (U21AddDecode 0 27 (U21AddDecode 0 27 ))
	(_version v32)
	(_time 1080051935828 2004.03.23 06:25:35)
	(_source (\./src/u21adddecode.v\ VERILOG (\./src/u21adddecode.v\ VERILOG)))
	(_use (std(standard))(vl(verilog_logic)))
	(_base (E 22))
	(_entity
		(_time 1080051935828)
		(_use )
	)
	(_timescale 1ps 1ps)
	(_parameters    dbg   accs  )
	(_attribute )
	(_object
		(_port (_internal DCOR0CNTLOWr ~wire 0 27 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal DCOR0THRESLOWr ~wire 0 27 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal DCOR1CNTLOWr ~wire 0 27 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal DCOR1THRESLOWr ~wire 0 27 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal DCORENCPWRr ~wire 0 27 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal WR ~wire 0 27 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal DCOR0CNTMIDr ~wire 0 27 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal DCOR0THRESMIDr ~wire 0 27 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal DCOR1CNTMIDr ~wire 0 27 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal DCOR1THRESMIDr ~wire 0 27 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal DCORLIMITSr ~wire 0 27 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal DCORIEw ~wire 0 27 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal DCORENCPWRw ~wire 0 27 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal DCOR0CNTHIGHr ~wire 0 27 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal DCORCONFIGr ~wire 0 27 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal DCORIFGr ~wire 0 27 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal DCOR1CNTHIGHr ~wire 0 27 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal AS ~wire 0 27 (_architecture (_in ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal DCORIFGw ~wire 0 27 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal RD ~wire 0 27 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal DCOROUTw ~wire 0 27 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal DCORENCCTLw ~wire 0 27 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_type (_internal ~[7:0]wire~ 0 27 (_array ~wire ((_downto (i 7) (i 0))))))
		(_port (_internal ADDR ~[7:0]wire~ 0 27 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal DCORI2CCNTr ~wire 0 27 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_type (_internal ~[7:0]reg~ 0 91 (_array ~reg ((_downto (i 7) (i 0))))))
		(_signal (_internal Select.Address ~[7:0]reg~ 0 91 (_subprogram Select (_in ))) (_reg ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal Select.Location ~[7:0]reg~ 0 92 (_subprogram Select (_in ))) (_reg ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal Select.RD ~reg 0 93 (_subprogram Select (_in ))) (_reg ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal Select.WR ~reg 0 93 (_subprogram Select (_in ))) (_reg ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal Select.RorW ~reg 0 94 (_subprogram Select (_in ))) (_reg ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal Select.Select ~reg 0 0 (_subprogram Select (_out ))) (_reg ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_subprogram
			
			(_internal Select 20 0 90 (_architecture (_function)(_target(29))
				(_read(28)(26)(27)(22)(25))
			))

		)
		(_type (_external ~wire (vl verilog_logic wire)))
		(_type (_external ~reg (vl verilog_logic reg)))
		(_type (_external ~event (vl verilog_logic event)))
		(_type (_external ~wand (vl verilog_logic wand)))
		(_type (_external ~wor (vl verilog_logic wor)))
		(_type (_external ~tri1 (vl verilog_logic tri1)))
		(_type (_external ~tri0 (vl verilog_logic tri0)))
		(_type (_external ~trireg (vl verilog_logic trireg)))
		(_type (_external ~supply0 (vl verilog_logic supply0)))
		(_type (_external ~supply1 (vl verilog_logic supply1)))
		(_type (_external ~real (vl verilog_logic real)))
		(_type (_external ~realtime (vl verilog_logic realtime)))
		(_type (_external ~tri (vl verilog_logic tri)))
		(_type (_external ~triand (vl verilog_logic triand)))
		(_type (_external ~trior (vl verilog_logic trior)))
		(_type (_external ~bit (vl verilog_logic bit)))
		(_type (_external ~extstd.standard.integer (std standard integer)))
		(_type (_external ~extstd.standard.bit (std standard bit)))
		(_process
			(#ASSIGN#102_0 (_architecture 0 0 102 (_process (_simple)
				(_target(11))
				(_sensitivity(22)(19)(5))
				(_call(0))
			)))
			(#ASSIGN#105_1 (_architecture 1 0 105 (_process (_simple)
				(_target(18))
				(_sensitivity(22)(19)(5))
				(_call(0))
			)))
			(#ASSIGN#108_2 (_architecture 2 0 108 (_process (_simple)
				(_target(15))
				(_sensitivity(22)(19)(5))
				(_call(0))
			)))
			(#ASSIGN#111_3 (_architecture 3 0 111 (_process (_simple)
				(_target(10))
				(_sensitivity(22)(19)(5))
				(_call(0))
			)))
			(#ASSIGN#114_4 (_architecture 4 0 114 (_process (_simple)
				(_target(21))
				(_sensitivity(22)(19)(5))
				(_call(0))
			)))
			(#ASSIGN#117_5 (_architecture 5 0 117 (_process (_simple)
				(_target(0))
				(_sensitivity(22)(19)(5))
				(_call(0))
			)))
			(#ASSIGN#120_6 (_architecture 6 0 120 (_process (_simple)
				(_target(6))
				(_sensitivity(22)(19)(5))
				(_call(0))
			)))
			(#ASSIGN#123_7 (_architecture 7 0 123 (_process (_simple)
				(_target(13))
				(_sensitivity(22)(19)(5))
				(_call(0))
			)))
			(#ASSIGN#126_8 (_architecture 8 0 126 (_process (_simple)
				(_target(2))
				(_sensitivity(22)(19)(5))
				(_call(0))
			)))
			(#ASSIGN#129_9 (_architecture 9 0 129 (_process (_simple)
				(_target(8))
				(_sensitivity(22)(19)(5))
				(_call(0))
			)))
			(#ASSIGN#132_10 (_architecture 10 0 132 (_process (_simple)
				(_target(16))
				(_sensitivity(22)(19)(5))
				(_call(0))
			)))
			(#ASSIGN#135_11 (_architecture 11 0 135 (_process (_simple)
				(_target(1))
				(_sensitivity(22)(19)(5))
				(_call(0))
			)))
			(#ASSIGN#138_12 (_architecture 12 0 138 (_process (_simple)
				(_target(7))
				(_sensitivity(22)(19)(5))
				(_call(0))
			)))
			(#ASSIGN#141_13 (_architecture 13 0 141 (_process (_simple)
				(_target(3))
				(_sensitivity(22)(19)(5))
				(_call(0))
			)))
			(#ASSIGN#144_14 (_architecture 14 0 144 (_process (_simple)
				(_target(9))
				(_sensitivity(22)(19)(5))
				(_call(0))
			)))
			(#ASSIGN#147_15 (_architecture 15 0 147 (_process (_simple)
				(_target(4))
				(_sensitivity(22)(19)(5))
				(_call(0))
			)))
			(#ASSIGN#150_16 (_architecture 16 0 150 (_process (_simple)
				(_target(12))
				(_sensitivity(22)(19)(5))
				(_call(0))
			)))
			(#ASSIGN#153_17 (_architecture 17 0 153 (_process (_simple)
				(_target(14))
				(_sensitivity(22)(19)(5))
				(_call(0))
			)))
			(#ASSIGN#156_18 (_architecture 18 0 156 (_process (_simple)
				(_target(20))
				(_sensitivity(22)(19)(5))
				(_call(0))
			)))
			(#ASSIGN#159_19 (_architecture 19 0 159 (_process (_simple)
				(_target(23))
				(_sensitivity(22)(19)(5))
				(_call(0))
			)))
			(#INTERNAL#0_21 (_internal 21 0 0 (_process (_virtual))))
		)
	)
	
	
	(_defparam
	)
	(_scope
		(_unit Select function 0 90
		)
	)
	(_model . U21AddDecode 22 -1)

)
I 000050 55 4827          1080051936563 Interface
(_unit VERILOG 6.349C.6.256 (Interface 0 25 (Interface 0 25 ))
	(_version v32)
	(_time 1080051935828 2004.03.23 06:25:35)
	(_source (\./src/interface.v\ VERILOG (\./src/interface.v\ VERILOG)))
	(_use (std(standard))(vl(verilog_logic)))
	(_base (E 8))
	(_entity
		(_time 1080051935828)
		(_use )
	)
	(_timescale 1ps 1ps)
	(_parameters    dbg   accs  )
	(_attribute nb_assign )
	(_object
		(_type (_internal ~[7:0]wire~ 0 25 (_array ~wire ((_downto (i 7) (i 0))))))
		(_port (_internal inDATA ~[7:0]wire~ 0 25 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal outDATA ~[7:0]wire~ 0 25 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal Reset ~wire 0 25 (_architecture (_in ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal AS ~wire 0 25 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal AD ~[7:0]wire~ 0 25 (_architecture (_inout ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal RD ~wire 0 25 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal Mclk ~wire 0 25 (_architecture (_in ))) (_net  ) (_nonbaction) (_noforceassign))
		(_port (_internal ASleading ~wire 0 25 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal WR ~wire 0 25 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal ADDR ~[7:0]wire~ 0 25 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_type (_internal ~[7:0]reg~ 0 58 (_array ~reg ((_downto (i 7) (i 0))))))
		(_signal (_internal ADDR_reg ~[7:0]reg~ 0 58 (_architecture (_uni ))) (_reg ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal AutoInc ~reg 0 66 (_architecture (_uni ))) (_reg ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal ASedge ~reg 0 68 (_architecture (_uni ))) (_reg ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal WRRDedge ~reg 0 70 (_architecture (_uni ))) (_reg ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal Enable_AD ~wire 0 74 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal ADDR_in_Range ~wire 0 75 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_subprogram
			

		)
		(_type (_external ~wire (vl verilog_logic wire)))
		(_type (_external ~reg (vl verilog_logic reg)))
		(_type (_external ~event (vl verilog_logic event)))
		(_type (_external ~wand (vl verilog_logic wand)))
		(_type (_external ~wor (vl verilog_logic wor)))
		(_type (_external ~tri1 (vl verilog_logic tri1)))
		(_type (_external ~tri0 (vl verilog_logic tri0)))
		(_type (_external ~trireg (vl verilog_logic trireg)))
		(_type (_external ~supply0 (vl verilog_logic supply0)))
		(_type (_external ~supply1 (vl verilog_logic supply1)))
		(_type (_external ~real (vl verilog_logic real)))
		(_type (_external ~realtime (vl verilog_logic realtime)))
		(_type (_external ~tri (vl verilog_logic tri)))
		(_type (_external ~triand (vl verilog_logic triand)))
		(_type (_external ~trior (vl verilog_logic trior)))
		(_type (_external ~bit (vl verilog_logic bit)))
		(_type (_external ~extstd.standard.integer (std standard integer)))
		(_type (_external ~extstd.standard.bit (std standard bit)))
		(_process
			(#ASSIGN#79_0 (_architecture 0 0 79 (_process (_alias ((ADDR)(ADDR_reg)))(_simple)
				(_target(9))
				(_sensitivity(10))
			)))
			(#ASSIGN#82_1 (_architecture 1 0 82 (_process (_alias ((Enable_AD)(WR)(RD)(ADDR_in_Range)))(_simple)
				(_target(14))
				(_sensitivity(8)(5)(15))
			)))
			(#ASSIGN#83_2 (_architecture 2 0 83 (_process (_simple)
				(_target(15))
				(_sensitivity(10))
			)))
			(#ASSIGN#84_3 (_architecture 3 0 84 (_process (_alias ((ASleading)(AS)(ASedge)))(_simple)
				(_target(7))
				(_sensitivity(3)(12))
			)))
			(#ASSIGN#91_4 (_architecture 4 0 91 (_process (_alias ((inDATA)(AD)))(_simple)
				(_target(0))
				(_sensitivity(4))
			)))
			(#ASSIGN#92_5 (_architecture 5 0 92 (_process (_simple)
				(_target(4))
				(_sensitivity(14)(1))
			)))
			(#ALWAYS#94_6 (_architecture 6 0 94 (_process 
				(_target(12)(13)(10)(11))
				(_read(6)(3)(8)(5)(2)(7)(4)(13)(11)(15)(10))
			)))
		)
	)
	
	
	(_defparam
	)
	(_model . Interface 8 -1)

)
I 000050 55 4040          1080051936578 Interrupt
(_unit VERILOG 6.349C.6.256 (Interrupt 0 25 (Interrupt 0 25 ))
	(_version v32)
	(_time 1080051935828 2004.03.23 06:25:35)
	(_source (\./src/interrupt.v\ VERILOG (\./src/interrupt.v\ VERILOG)))
	(_use (std(standard))(vl(verilog_logic)))
	(_base (E 3))
	(_entity
		(_time 1080051935828)
		(_use )
	)
	(_timescale 1ps 1ps)
	(_parameters    dbg   accs  )
	(_attribute nb_assign )
	(_object
		(_type (_internal ~[7:0]wire~ 0 25 (_array ~wire ((_downto (i 7) (i 0))))))
		(_port (_internal inDATA ~[7:0]wire~ 0 25 (_architecture (_in ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal Reset ~wire 0 25 (_architecture (_in ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal PWRint ~wire 0 25 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal BusInt ~wire 0 25 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal Thres0 ~wire 0 25 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal Mclk ~wire 0 25 (_architecture (_in ))) (_net  ) (_nonbaction) (_noforceassign))
		(_port (_internal Thres1 ~wire 0 25 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal I2Cint ~wire 0 25 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal LSwitchInt ~wire 0 25 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal INT ~wire 0 25 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal DCORIEw ~wire 0 25 (_architecture (_in ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal Homed0 ~wire 0 25 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal Homed1 ~wire 0 25 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_type (_internal ~[7:0]reg~ 0 59 (_array ~reg ((_downto (i 7) (i 0))))))
		(_signal (_internal DCORIE ~[7:0]reg~ 0 59 (_architecture (_uni ))) (_reg ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_subprogram
			

		)
		(_type (_external ~wire (vl verilog_logic wire)))
		(_type (_external ~reg (vl verilog_logic reg)))
		(_type (_external ~event (vl verilog_logic event)))
		(_type (_external ~wand (vl verilog_logic wand)))
		(_type (_external ~wor (vl verilog_logic wor)))
		(_type (_external ~tri1 (vl verilog_logic tri1)))
		(_type (_external ~tri0 (vl verilog_logic tri0)))
		(_type (_external ~trireg (vl verilog_logic trireg)))
		(_type (_external ~supply0 (vl verilog_logic supply0)))
		(_type (_external ~supply1 (vl verilog_logic supply1)))
		(_type (_external ~real (vl verilog_logic real)))
		(_type (_external ~realtime (vl verilog_logic realtime)))
		(_type (_external ~tri (vl verilog_logic tri)))
		(_type (_external ~triand (vl verilog_logic triand)))
		(_type (_external ~trior (vl verilog_logic trior)))
		(_type (_external ~bit (vl verilog_logic bit)))
		(_type (_external ~extstd.standard.integer (std standard integer)))
		(_type (_external ~extstd.standard.bit (std standard bit)))
		(_process
			(#ASSIGN#68_0 (_architecture 0 0 68 (_process (_alias ((INT)(DCORIE(7))(I2Cint)(DCORIE(6))(Thres1)(DCORIE(5))(Thres0)(DCORIE(4))(LSwitchInt)(DCORIE(3))(Homed1)(DCORIE(2))(Homed0)(DCORIE(1))(PWRint)(DCORIE(0))(BusInt)))(_simple)
				(_target(9))
				(_sensitivity(13(7))(7)(13(6))(6)(13(5))(4)(13(4))(8)(13(3))(12)(13(2))(11)(13(1))(2)(13(0))(3))
			)))
			(#ALWAYS#70_1 (_architecture 1 0 70 (_process 
				(_target(13))
				(_read(5)(1)(10)(0))
			)))
		)
	)
	
	
	(_defparam
	)
	(_model . Interrupt 3 -1)

)
I 000047 55 7698          1080051936582 PWRreg
(_unit VERILOG 6.349C.6.256 (PWRreg 0 25 (PWRreg 0 25 ))
	(_version v32)
	(_time 1080051935828 2004.03.23 06:25:35)
	(_source (\./src/PWRreg.v\ VERILOG (\./src/pwrreg.v\ VERILOG)))
	(_use (std(standard))(vl(verilog_logic)))
	(_base (E 14))
	(_entity
		(_time 1080051935828)
		(_use )
	)
	(_timescale 1ps 1ps)
	(_parameters    dbg   accs  )
	(_attribute nb_assign )
	(_object
		(_port (_internal Hme05ctl ~wire 0 25 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal Hme15ctl ~wire 0 25 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal Reset ~wire 0 25 (_architecture (_in ))) (_net  ) (_nonbaction) (_noforceassign))
		(_port (_internal PWRint ~wire 0 25 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal Enc033flg ~wire 0 25 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal Enc133flg ~wire 0 25 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal Mclk ~wire 0 25 (_architecture (_in ))) (_net  ) (_nonbaction) (_noforceassign))
		(_port (_internal Hme033flg ~wire 0 25 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal DCORENCPWRr ~wire 0 25 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal Hme133flg ~wire 0 25 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal DCORENCPWRw ~wire 0 25 (_architecture (_in ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal Enc033ctl ~wire 0 25 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal Enc133ctl ~wire 0 25 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal DCORIFGr ~wire 0 25 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_type (_internal ~[7:0]wire~ 0 25 (_array ~wire ((_downto (i 7) (i 0))))))
		(_port (_internal inDATA ~[7:0]wire~ 0 25 (_architecture (_in ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal outDATA ~[7:0]wire~ 0 25 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal Hme033ctl ~wire 0 25 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal Hme133ctl ~wire 0 25 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal Enc05flg ~wire 0 25 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal Enc15flg ~wire 0 25 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal DCORIFGw ~wire 0 25 (_architecture (_in ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal Hme05flg ~wire 0 25 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal Hme15flg ~wire 0 25 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal Enc05ctl ~wire 0 25 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal Enc15ctl ~wire 0 25 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_type (_internal ~[7:0]reg~ 0 82 (_array ~reg ((_downto (i 7) (i 0))))))
		(_signal (_internal ctrlr ~[7:0]reg~ 0 82 (_architecture (_uni ))) (_reg ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal Flgreg ~[7:0]reg~ 0 83 (_architecture (_uni ))) (_reg ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal DCORIFG ~reg 0 84 (_architecture (_uni ))) (_reg ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal orFLGs ~wire 0 85 (_architecture (_uni ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_subprogram
			

		)
		(_type (_external ~wire (vl verilog_logic wire)))
		(_type (_external ~reg (vl verilog_logic reg)))
		(_type (_external ~event (vl verilog_logic event)))
		(_type (_external ~wand (vl verilog_logic wand)))
		(_type (_external ~wor (vl verilog_logic wor)))
		(_type (_external ~tri1 (vl verilog_logic tri1)))
		(_type (_external ~tri0 (vl verilog_logic tri0)))
		(_type (_external ~trireg (vl verilog_logic trireg)))
		(_type (_external ~supply0 (vl verilog_logic supply0)))
		(_type (_external ~supply1 (vl verilog_logic supply1)))
		(_type (_external ~real (vl verilog_logic real)))
		(_type (_external ~realtime (vl verilog_logic realtime)))
		(_type (_external ~tri (vl verilog_logic tri)))
		(_type (_external ~triand (vl verilog_logic triand)))
		(_type (_external ~trior (vl verilog_logic trior)))
		(_type (_external ~bit (vl verilog_logic bit)))
		(_type (_external ~extstd.standard.integer (std standard integer)))
		(_type (_external ~extstd.standard.bit (std standard bit)))
		(_process
			(#ASSIGN#88_0 (_architecture 0 0 88 (_process (_simple)
				(_target(15))
				(_sensitivity(8)(27)(26)(19)(5)(22)(9)(18)(4)(21)(7)(13))
			)))
			(#ASSIGN#89_1 (_architecture 1 0 89 (_process (_alias ((PWRint)(DCORIFG)))(_simple)
				(_target(3))
				(_sensitivity(27))
			)))
			(#ASSIGN#90_2 (_architecture 2 0 90 (_process (_alias ((orFLGs)(Enc15flg)(Enc133flg)(Hme15flg)(Hme133flg)(Enc05flg)(Enc033flg)(Hme05flg)(Hme033flg)))(_simple)
				(_target(28))
				(_sensitivity(19)(5)(22)(9)(18)(4)(21)(7))
			)))
			(#ASSIGN#92_3 (_architecture 3 0 92 (_process (_alias ((Enc15ctl)(ctrlr(7))))(_simple)
				(_target(24))
				(_sensitivity(25(7)))
			)))
			(#ASSIGN#93_4 (_architecture 4 0 93 (_process (_alias ((Enc133ctl)(ctrlr(6))))(_simple)
				(_target(12))
				(_sensitivity(25(6)))
			)))
			(#ASSIGN#94_5 (_architecture 5 0 94 (_process (_alias ((Hme15ctl)(ctrlr(5))))(_simple)
				(_target(1))
				(_sensitivity(25(5)))
			)))
			(#ASSIGN#95_6 (_architecture 6 0 95 (_process (_alias ((Hme133ctl)(ctrlr(4))))(_simple)
				(_target(17))
				(_sensitivity(25(4)))
			)))
			(#ASSIGN#96_7 (_architecture 7 0 96 (_process (_alias ((Enc05ctl)(ctrlr(3))))(_simple)
				(_target(23))
				(_sensitivity(25(3)))
			)))
			(#ASSIGN#97_8 (_architecture 8 0 97 (_process (_alias ((Enc033ctl)(ctrlr(2))))(_simple)
				(_target(11))
				(_sensitivity(25(2)))
			)))
			(#ASSIGN#98_9 (_architecture 9 0 98 (_process (_alias ((Hme05ctl)(ctrlr(1))))(_simple)
				(_target(0))
				(_sensitivity(25(1)))
			)))
			(#ASSIGN#99_10 (_architecture 10 0 99 (_process (_alias ((Hme033ctl)(ctrlr(0))))(_simple)
				(_target(16))
				(_sensitivity(25(0)))
			)))
			(#ALWAYS#101_11 (_architecture 11 0 101 (_process 
				(_target(27)(26))
				(_read(6)(2)(20)(14(1))(28)(27)(19)(5)(22)(9)(18)(4)(21)(7))
			)))
			(#ALWAYS#112_12 (_architecture 12 0 112 (_process 
				(_target(25))
				(_read(6)(2)(10)(14))
			)))
		)
	)
	
	
	(_defparam
	)
	(_model . PWRreg 14 -1)

)
I 000048 55 6214          1080051936594 Lswitch
(_unit VERILOG 6.349C.6.256 (Lswitch 0 25 (Lswitch 0 25 ))
	(_version v32)
	(_time 1080051935828 2004.03.23 06:25:35)
	(_source (\./src/lswitch.v\ VERILOG (\./src/lswitch.v\ VERILOG)))
	(_use (std(standard))(vl(verilog_logic)))
	(_base (E 9))
	(_entity
		(_time 1080051935828)
		(_use )
	)
	(_timescale 1ps 1ps)
	(_parameters    dbg   accs  )
	(_attribute nb_assign )
	(_object
		(_port (_internal DCORIFGr ~wire 0 25 (_architecture (_in ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal DIR1 ~wire 0 25 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_type (_internal ~[7:0]wire~ 0 25 (_array ~wire ((_downto (i 7) (i 0))))))
		(_port (_internal inDATA ~[7:0]wire~ 0 25 (_architecture (_in ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal RLS0 ~wire 0 25 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal outDATA ~[7:0]wire~ 0 25 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal RLS1 ~wire 0 25 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal Reset ~wire 0 25 (_architecture (_in ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal fBRK0 ~wire 0 25 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal DCORIFGw ~wire 0 25 (_architecture (_in ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal Brake0 ~wire 0 25 (_architecture (_in ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal FLS0 ~wire 0 25 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal fBRK1 ~wire 0 25 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal Brake1 ~wire 0 25 (_architecture (_in ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal FLS1 ~wire 0 25 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal Mclk ~wire 0 25 (_architecture (_in ))) (_net  ) (_nonbaction) (_noforceassign))
		(_port (_internal LSwitchInt ~wire 0 25 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal Home0 ~wire 0 25 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal Home1 ~wire 0 25 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal DCORLIMITSr ~wire 0 25 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal DIR0 ~wire 0 25 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal DCORIFG ~reg 0 73 (_architecture (_uni ))) (_reg ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal fBRK0r ~reg 0 74 (_architecture (_uni ))) (_reg ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal fBRK1r ~reg 0 74 (_architecture (_uni ))) (_reg ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal trip0 ~wire 0 75 (_architecture (_uni ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal trip1 ~wire 0 75 (_architecture (_uni ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_subprogram
			

		)
		(_type (_external ~wire (vl verilog_logic wire)))
		(_type (_external ~reg (vl verilog_logic reg)))
		(_type (_external ~event (vl verilog_logic event)))
		(_type (_external ~wand (vl verilog_logic wand)))
		(_type (_external ~wor (vl verilog_logic wor)))
		(_type (_external ~tri1 (vl verilog_logic tri1)))
		(_type (_external ~tri0 (vl verilog_logic tri0)))
		(_type (_external ~trireg (vl verilog_logic trireg)))
		(_type (_external ~supply0 (vl verilog_logic supply0)))
		(_type (_external ~supply1 (vl verilog_logic supply1)))
		(_type (_external ~real (vl verilog_logic real)))
		(_type (_external ~realtime (vl verilog_logic realtime)))
		(_type (_external ~tri (vl verilog_logic tri)))
		(_type (_external ~triand (vl verilog_logic triand)))
		(_type (_external ~trior (vl verilog_logic trior)))
		(_type (_external ~bit (vl verilog_logic bit)))
		(_type (_external ~extstd.standard.integer (std standard integer)))
		(_type (_external ~extstd.standard.bit (std standard bit)))
		(_process
			(#ASSIGN#77_0 (_architecture 0 0 77 (_process (_simple)
				(_target(4))
				(_sensitivity(18)(22)(17)(13)(5)(21)(16)(10)(3))
			)))
			(#ASSIGN#79_1 (_architecture 1 0 79 (_process (_alias ((trip1)(DIR1)(FLS1)(DIR1)(RLS1)))(_simple)
				(_target(24))
				(_sensitivity(1)(13)(5))
			)))
			(#ASSIGN#80_2 (_architecture 2 0 80 (_process (_alias ((trip0)(DIR0)(FLS0)(DIR0)(RLS0)))(_simple)
				(_target(23))
				(_sensitivity(19)(10)(3))
			)))
			(#ASSIGN#82_3 (_architecture 3 0 82 (_process (_alias ((fBRK1)(fBRK1r)))(_simple)
				(_target(11))
				(_sensitivity(22))
			)))
			(#ASSIGN#83_4 (_architecture 4 0 83 (_process (_alias ((fBRK0)(fBRK0r)))(_simple)
				(_target(7))
				(_sensitivity(21))
			)))
			(#ASSIGN#85_5 (_architecture 5 0 85 (_process (_alias ((LSwitchInt)(DCORIFG)))(_simple)
				(_target(15))
				(_sensitivity(20))
			)))
			(#ALWAYS#87_6 (_architecture 6 0 87 (_process 
				(_target(20))
				(_read(14)(6)(24)(23)(8)(2(4))(20))
			)))
			(#ALWAYS#98_7 (_architecture 7 0 98 (_process 
				(_target(22)(21))
				(_read(14)(6)(24)(12)(22)(23)(9)(21))
			)))
		)
	)
	
	
	(_defparam
	)
	(_model . Lswitch 9 -1)

)
I 000051 55 3250          1080051936610 I2CAddress
(_unit VERILOG 6.349C.6.256 (I2CAddress 0 25 (I2CAddress 0 25 ))
	(_version v32)
	(_time 1080051935828 2004.03.23 06:25:35)
	(_source (\./src/i2caddress.v\ VERILOG (\./src/i2caddress.v\ VERILOG)))
	(_use (std(standard))(vl(verilog_logic)))
	(_base (E 9))
	(_entity
		(_time 1080051935828)
		(_use )
	)
	(_timescale 1ps 1ps)
	(_parameters    dbg   accs  )
	(_attribute )
	(_object
		(_port (_internal MotorIn0 ~wire 0 25 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal DCORCONFIGr ~wire 0 25 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal MotorIn1 ~wire 0 25 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_type (_internal ~[5:0]wire~ 0 25 (_array ~wire ((_downto (i 5) (i 0))))))
		(_port (_internal I2CS ~[5:0]wire~ 0 25 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_type (_internal ~[7:0]wire~ 0 25 (_array ~wire ((_downto (i 7) (i 0))))))
		(_port (_internal outDATA ~[7:0]wire~ 0 25 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_subprogram
			

		)
		(_type (_external ~wire (vl verilog_logic wire)))
		(_type (_external ~reg (vl verilog_logic reg)))
		(_type (_external ~event (vl verilog_logic event)))
		(_type (_external ~wand (vl verilog_logic wand)))
		(_type (_external ~wor (vl verilog_logic wor)))
		(_type (_external ~tri1 (vl verilog_logic tri1)))
		(_type (_external ~tri0 (vl verilog_logic tri0)))
		(_type (_external ~trireg (vl verilog_logic trireg)))
		(_type (_external ~supply0 (vl verilog_logic supply0)))
		(_type (_external ~supply1 (vl verilog_logic supply1)))
		(_type (_external ~real (vl verilog_logic real)))
		(_type (_external ~realtime (vl verilog_logic realtime)))
		(_type (_external ~tri (vl verilog_logic tri)))
		(_type (_external ~triand (vl verilog_logic triand)))
		(_type (_external ~trior (vl verilog_logic trior)))
		(_type (_external ~bit (vl verilog_logic bit)))
		(_type (_external ~extstd.standard.integer (std standard integer)))
		(_type (_external ~extstd.standard.bit (std standard bit)))
		(_process
			(#ASSIGN#43_0 (_architecture 0 0 43 (_process (_simple)
				(_target(4(0)))
				(_sensitivity(1)(3(0)))
			)))
			(#ASSIGN#44_1 (_architecture 1 0 44 (_process (_simple)
				(_target(4(1)))
				(_sensitivity(1)(3(1)))
			)))
			(#ASSIGN#45_2 (_architecture 2 0 45 (_process (_simple)
				(_target(4(2)))
				(_sensitivity(1)(3(2)))
			)))
			(#ASSIGN#46_3 (_architecture 3 0 46 (_process (_simple)
				(_target(4(3)))
				(_sensitivity(1)(3(3)))
			)))
			(#ASSIGN#47_4 (_architecture 4 0 47 (_process (_simple)
				(_target(4(4)))
				(_sensitivity(1)(3(4)))
			)))
			(#ASSIGN#48_5 (_architecture 5 0 48 (_process (_simple)
				(_target(4(5)))
				(_sensitivity(1)(3(5)))
			)))
			(#ASSIGN#49_6 (_architecture 6 0 49 (_process (_simple)
				(_target(4(6)))
				(_sensitivity(1)(0))
			)))
			(#ASSIGN#50_7 (_architecture 7 0 50 (_process (_simple)
				(_target(4(7)))
				(_sensitivity(1)(2))
			)))
		)
	)
	
	
	(_defparam
	)
	(_model . I2CAddress 9 -1)

)
V 000051 55 4704          1080051936625 PWMcontrol
(_unit VERILOG 6.349C.6.256 (PWMcontrol 0 32 (PWMcontrol 0 32 ))
	(_version v32)
	(_time 1080051935828 2004.03.23 06:25:35)
	(_source (\./compile/PWMcontrol.v\ VERILOG (\./compile/pwmcontrol.v\ VERILOG)))
	(_use (std(standard))(vl(verilog_logic)))
	(_base (E 1))
	(_entity
		(_time 1080051935828)
		(_use )
	)
	(_timescale 1ns 1ns)
	(_parameters    dbg   accs  )
	(_attribute )
	(_object
		(_port (_internal Brake1 ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Brake2 ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal DIR1 ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal DIR2 ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal HBRK1 ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal HBRK2 ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PWM1 ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PWM2 ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal fBRK1 ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal fBRK2 ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PAH1 ~wire 0 33 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PAH2 ~wire 0 33 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PAL1 ~wire 0 33 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PAL2 ~wire 0 33 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PBH1 ~wire 0 33 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PBH2 ~wire 0 33 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PBL1 ~wire 0 33 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PBL2 ~wire 0 33 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_subprogram
			

		)
		(_type (_external ~wire (vl verilog_logic wire)))
		(_type (_external ~reg (vl verilog_logic reg)))
		(_type (_external ~event (vl verilog_logic event)))
		(_type (_external ~wand (vl verilog_logic wand)))
		(_type (_external ~wor (vl verilog_logic wor)))
		(_type (_external ~tri1 (vl verilog_logic tri1)))
		(_type (_external ~tri0 (vl verilog_logic tri0)))
		(_type (_external ~trireg (vl verilog_logic trireg)))
		(_type (_external ~supply0 (vl verilog_logic supply0)))
		(_type (_external ~supply1 (vl verilog_logic supply1)))
		(_type (_external ~real (vl verilog_logic real)))
		(_type (_external ~realtime (vl verilog_logic realtime)))
		(_type (_external ~tri (vl verilog_logic tri)))
		(_type (_external ~triand (vl verilog_logic triand)))
		(_type (_external ~trior (vl verilog_logic trior)))
		(_type (_external ~bit (vl verilog_logic bit)))
		(_type (_external ~extstd.standard.integer (std standard integer)))
		(_type (_external ~extstd.standard.bit (std standard bit)))
	)
	
	
	(_defparam
	)
	(_scope
	)
	(_instantiation U1 0 75 (_entity .  PWMtranslator)
		(_port
			((Brake) (Brake1))
			((DIR) (DIR1))
			((HBRK) (HBRK1))
			((PAH) (PAH1))
			((PAL) (PAL1))
			((PBH) (PBH1))
			((PBL) (PBL1))
			((PWM) (PWM1))
			((fBRK) (fBRK1))
		)
		(_strength)
	)
	(_instantiation U2 0 90 (_entity .  PWMtranslator)
		(_port
			((Brake) (Brake2))
			((DIR) (DIR2))
			((HBRK) (HBRK2))
			((PAH) (PAH2))
			((PAL) (PAL2))
			((PBH) (PBH2))
			((PBL) (PBL2))
			((PWM) (PWM2))
			((fBRK) (fBRK2))
		)
		(_strength)
	)
	(_model . PWMcontrol 1 -1)

)
I 000049 55 5191          1080051936629 MISCouts
(_unit VERILOG 6.349C.6.256 (MISCouts 0 25 (MISCouts 0 25 ))
	(_version v32)
	(_time 1080051935828 2004.03.23 06:25:35)
	(_source (\./src/miscouts.v\ VERILOG (\./src/miscouts.v\ VERILOG)))
	(_use (std(standard))(vl(verilog_logic)))
	(_base (E 11))
	(_entity
		(_time 1080051935828)
		(_use )
	)
	(_timescale 1ps 1ps)
	(_parameters    dbg   accs  )
	(_attribute nb_assign )
	(_object
		(_type (_internal ~[7:0]wire~ 0 25 (_array ~wire ((_downto (i 7) (i 0))))))
		(_port (_internal inDATA ~[7:0]wire~ 0 25 (_architecture (_in ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal Reset ~wire 0 25 (_architecture (_in ))) (_net  ) (_nonbaction) (_noforceassign))
		(_port (_internal LED1 ~wire 0 25 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal LightSense ~wire 0 25 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal GP_Motor0_1 ~wire 0 25 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal LED2 ~wire 0 25 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal DCOROUTw ~wire 0 25 (_architecture (_in ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal Mclk ~wire 0 25 (_architecture (_in ))) (_net  ) (_nonbaction) (_noforceassign))
		(_port (_internal GP_Motor1_1 ~wire 0 25 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal LED3 ~wire 0 25 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal LED4 ~wire 0 25 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal MTRpwrn ~wire 0 25 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal LED5 ~wire 0 25 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal MTRpwr ~wire 0 25 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_type (_internal ~[7:0]reg~ 0 63 (_array ~reg ((_downto (i 7) (i 0))))))
		(_signal (_internal MISCr ~[7:0]reg~ 0 63 (_architecture (_uni ))) (_reg ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_subprogram
			

		)
		(_type (_external ~wire (vl verilog_logic wire)))
		(_type (_external ~reg (vl verilog_logic reg)))
		(_type (_external ~event (vl verilog_logic event)))
		(_type (_external ~wand (vl verilog_logic wand)))
		(_type (_external ~wor (vl verilog_logic wor)))
		(_type (_external ~tri1 (vl verilog_logic tri1)))
		(_type (_external ~tri0 (vl verilog_logic tri0)))
		(_type (_external ~trireg (vl verilog_logic trireg)))
		(_type (_external ~supply0 (vl verilog_logic supply0)))
		(_type (_external ~supply1 (vl verilog_logic supply1)))
		(_type (_external ~real (vl verilog_logic real)))
		(_type (_external ~realtime (vl verilog_logic realtime)))
		(_type (_external ~tri (vl verilog_logic tri)))
		(_type (_external ~triand (vl verilog_logic triand)))
		(_type (_external ~trior (vl verilog_logic trior)))
		(_type (_external ~bit (vl verilog_logic bit)))
		(_type (_external ~extstd.standard.integer (std standard integer)))
		(_type (_external ~extstd.standard.bit (std standard bit)))
		(_process
			(#ASSIGN#65_0 (_architecture 0 0 65 (_process (_alias ((LED1)(MISCr(0))(LightSense)))(_simple)
				(_target(2))
				(_sensitivity(14(0))(3))
			)))
			(#ASSIGN#66_1 (_architecture 1 0 66 (_process (_alias ((LED2)(MISCr(1))(LightSense)))(_simple)
				(_target(5))
				(_sensitivity(14(1))(3))
			)))
			(#ASSIGN#67_2 (_architecture 2 0 67 (_process (_alias ((LED3)(MISCr(2))(LightSense)))(_simple)
				(_target(9))
				(_sensitivity(14(2))(3))
			)))
			(#ASSIGN#68_3 (_architecture 3 0 68 (_process (_alias ((LED4)(MISCr(3))(LightSense)))(_simple)
				(_target(10))
				(_sensitivity(14(3))(3))
			)))
			(#ASSIGN#69_4 (_architecture 4 0 69 (_process (_alias ((LED5)(MISCr(4))(LightSense)))(_simple)
				(_target(12))
				(_sensitivity(14(4))(3))
			)))
			(#ASSIGN#70_5 (_architecture 5 0 70 (_process (_alias ((GP_Motor0_1)(MISCr(6))))(_simple)
				(_target(4))
				(_sensitivity(14(6)))
			)))
			(#ASSIGN#71_6 (_architecture 6 0 71 (_process (_alias ((GP_Motor1_1)(MISCr(7))))(_simple)
				(_target(8))
				(_sensitivity(14(7)))
			)))
			(#ASSIGN#72_7 (_architecture 7 0 72 (_process (_alias ((MTRpwr)(MISCr(5))))(_simple)
				(_target(13))
				(_sensitivity(14(5)))
			)))
			(#ASSIGN#73_8 (_architecture 8 0 73 (_process (_alias ((MTRpwrn)(MISCr(5))))(_simple)
				(_target(11))
				(_sensitivity(14(5)))
			)))
			(#ALWAYS#75_9 (_architecture 9 0 75 (_process 
				(_target(14))
				(_read(7)(1)(6)(0)(14))
			)))
		)
	)
	
	
	(_defparam
	)
	(_model . MISCouts 11 -1)

)
V 000047 55 10328         1080051936641 Servos
(_unit VERILOG 6.349C.6.256 (Servos 0 32 (Servos 0 32 ))
	(_version v32)
	(_time 1080051935828 2004.03.23 06:25:35)
	(_source (\./compile/Servos.v\ VERILOG (\./compile/servos.v\ VERILOG)))
	(_use (std(standard))(vl(verilog_logic)))
	(_base (E 2))
	(_entity
		(_time 1080051935828)
		(_use )
	)
	(_timescale 1ns 1ns)
	(_parameters    dbg   accs  )
	(_attribute )
	(_object
		(_port (_internal ASleading ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal DCOR0CNTHIGHr ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal DCOR0CNTLOWr ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal DCOR0CNTMIDr ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal DCOR0THRESLOWr ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal DCOR0THRESMIDr ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal DCOR1CNTHIGHr ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal DCOR1CNTLOWr ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal DCOR1CNTMIDr ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal DCOR1THRESLOWr ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal DCOR1THRESMIDr ~wire 0 33 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal DCORENCCTLw ~wire 0 33 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal DCORIFGr ~wire 0 33 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal DCORIFGw ~wire 0 33 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Home_Encoder0 ~wire 0 33 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Home_Encoder1 ~wire 0 33 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Mclk ~wire 0 33 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal MotorIn0 ~wire 0 33 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Motorin1 ~wire 0 33 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PhaseA_Encoder0 ~wire 0 33 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PhaseA_Encoder1 ~wire 0 34 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PhaseB_Encoder0 ~wire 0 34 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PhaseB_Encoder1 ~wire 0 34 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Reset ~wire 0 34 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_type (_internal ~[7:0]wire~ 0 34 (_array ~wire ((_downto (i 7) (i 0))))))
		(_port (_internal inDATA ~[7:0]wire~ 0 34 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Hfound0 ~wire 0 34 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Hfound1 ~wire 0 34 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Tfound0 ~wire 0 34 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Tfound1 ~wire 0 34 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal outDATA ~[7:0]wire~ 0 34 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal ce0 ~wire 0 99 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal ce1 ~wire 0 100 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET3720 ~wire 0 101 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET3721 ~wire 0 102 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal Sclk ~wire 0 103 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal updown0 ~wire 0 104 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal updown1 ~wire 0 105 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal Zero0 ~wire 0 106 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal Zero1 ~wire 0 107 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_type (_internal ~[23:0]wire~ 0 108 (_array ~wire ((_downto (i 23) (i 0))))))
		(_signal (_internal Channel0 ~[23:0]wire~ 0 108 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal Channel1 ~[23:0]wire~ 0 109 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_subprogram
			

		)
		(_type (_external ~wire (vl verilog_logic wire)))
		(_type (_external ~reg (vl verilog_logic reg)))
		(_type (_external ~event (vl verilog_logic event)))
		(_type (_external ~wand (vl verilog_logic wand)))
		(_type (_external ~wor (vl verilog_logic wor)))
		(_type (_external ~tri1 (vl verilog_logic tri1)))
		(_type (_external ~tri0 (vl verilog_logic tri0)))
		(_type (_external ~trireg (vl verilog_logic trireg)))
		(_type (_external ~supply0 (vl verilog_logic supply0)))
		(_type (_external ~supply1 (vl verilog_logic supply1)))
		(_type (_external ~real (vl verilog_logic real)))
		(_type (_external ~realtime (vl verilog_logic realtime)))
		(_type (_external ~tri (vl verilog_logic tri)))
		(_type (_external ~triand (vl verilog_logic triand)))
		(_type (_external ~trior (vl verilog_logic trior)))
		(_type (_external ~bit (vl verilog_logic bit)))
		(_type (_external ~extstd.standard.integer (std standard integer)))
		(_type (_external ~extstd.standard.bit (std standard bit)))
		(_process
			(#ASSIGN#214_0 (_architecture 0 0 214 (_process (_alias ((Sclk)(Mclk)))(_simple)
				(_target(34))
				(_sensitivity(16))
			)))
		)
	)
	
	
	(_defparam
	)
	(_scope
	)
	(_instantiation U1 0 113 (_entity .  Decode)
		(_port
			((Reset) (Reset))
			((Sclk) (Sclk))
			((ce) (ce0))
			((phaseA) (PhaseA_Encoder0))
			((phaseB) (PhaseB_Encoder0))
			((updown) (updown0))
		)
		(_strength)
	)
	(_instantiation U2 0 125 (_entity .  Counter)
		(_port
			((Reset) (Reset))
			((Sclk) (Sclk))
			((Zero) (Zero0))
			((ce) (ce0))
			((count) (Channel0))
			((sense) (NET3721))
			((updown) (updown0))
		)
		(_strength)
	)
	(_instantiation U3 0 138 (_entity .  Holdreg)
		(_port
			((ASleading) (ASleading))
			((DCOR0CNTHIGHr) (DCOR0CNTHIGHr))
			((DCOR0CNTLOWr) (DCOR0CNTLOWr))
			((DCOR0CNTMIDr) (DCOR0CNTMIDr))
			((DCOR1CNTHIGHr) (DCOR1CNTHIGHr))
			((DCOR1CNTLOWr) (DCOR1CNTLOWr))
			((DCOR1CNTMIDr) (DCOR1CNTMIDr))
			((Reset) (Reset))
			((Sclk) (Sclk))
			((ch0in) (Channel0))
			((ch1in) (Channel1))
			((outDATA) (outDATA))
		)
		(_strength)
	)
	(_instantiation U4 0 156 (_entity .  HomeConfig)
		(_port
			((Channel0) (Channel0(d_15_0)))
			((Channel1) (Channel1(d_15_0)))
			((DCOR0THRESLOWr) (DCOR0THRESLOWr))
			((DCOR0THRESMIDr) (DCOR0THRESMIDr))
			((DCOR1THRESLOWr) (DCOR1THRESLOWr))
			((DCOR1THRESMIDr) (DCOR1THRESMIDr))
			((DCORENCCTLw) (DCORENCCTLw))
			((DCORIFGr) (DCORIFGr))
			((DCORIFGw) (DCORIFGw))
			((Hfound0) (Hfound0))
			((Hfound1) (Hfound1))
			((Home_Encoder0) (Home_Encoder0))
			((Home_Encoder1) (Home_Encoder1))
			((MotorIn0) (MotorIn0))
			((MotorIn1) (Motorin1))
			((Reset) (Reset))
			((Sclk) (Sclk))
			((Tfound0) (Tfound0))
			((Tfound1) (Tfound1))
			((Zero0) (Zero0))
			((Zero1) (Zero1))
			((inDATA) (inDATA))
			((outDATA) (outDATA))
			((sense0) (NET3721))
			((sense1) (NET3720))
		)
		(_strength)
	)
	(_instantiation U5 0 187 (_entity .  Counter)
		(_port
			((Reset) (Reset))
			((Sclk) (Sclk))
			((Zero) (Zero1))
			((ce) (ce1))
			((count) (Channel1))
			((sense) (NET3720))
			((updown) (updown1))
		)
		(_strength)
	)
	(_instantiation U6 0 200 (_entity .  Decode)
		(_port
			((Reset) (Reset))
			((Sclk) (Sclk))
			((ce) (ce1))
			((phaseA) (PhaseA_Encoder1))
			((phaseB) (PhaseB_Encoder1))
			((updown) (updown1))
		)
		(_strength)
	)
	(_model . Servos 2 -1)

)
I 000047 55 3614          1080051936645 Decode
(_unit VERILOG 6.349C.6.256 (Decode 0 23 (Decode 0 23 ))
	(_version v32)
	(_time 1080051935828 2004.03.23 06:25:35)
	(_source (\./compile/Qdecode.v\ VERILOG (\./compile/qdecode.v\ VERILOG)))
	(_use (std(standard))(vl(verilog_logic)))
	(_base (E 5))
	(_entity
		(_time 1080051935828)
		(_use )
	)
	(_timescale 1ns 1ps)
	(_parameters    dbg   accs  )
	(_attribute nb_assign )
	(_object
		(_port (_internal Reset ~wire 0 23 (_architecture (_in ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal Sclk ~wire 0 23 (_architecture (_in ))) (_net  ) (_nonbaction) (_noforceassign))
		(_port (_internal ce ~wire 0 23 (_architecture (_inout ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal phaseA ~wire 0 23 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal phaseB ~wire 0 23 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal updown ~wire 0 23 (_architecture (_inout ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal ino_ce ~reg 0 34 (_architecture (_uni ))) (_reg ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal ino_updown ~reg 0 38 (_architecture (_uni ))) (_reg ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_type (_internal ~[3:0]reg~ 0 52 (_array ~reg ((_downto (i 3) (i 0))))))
		(_signal (_internal CurrState_Sreg0 ~[3:0]reg~ 0 52 (_architecture (_uni ))) (_reg ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal NextState_Sreg0 ~[3:0]reg~ 0 54 (_architecture (_uni ))) (_reg ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_subprogram
			

		)
		(_type (_external ~wire (vl verilog_logic wire)))
		(_type (_external ~reg (vl verilog_logic reg)))
		(_type (_external ~event (vl verilog_logic event)))
		(_type (_external ~wand (vl verilog_logic wand)))
		(_type (_external ~wor (vl verilog_logic wor)))
		(_type (_external ~tri1 (vl verilog_logic tri1)))
		(_type (_external ~tri0 (vl verilog_logic tri0)))
		(_type (_external ~trireg (vl verilog_logic trireg)))
		(_type (_external ~supply0 (vl verilog_logic supply0)))
		(_type (_external ~supply1 (vl verilog_logic supply1)))
		(_type (_external ~real (vl verilog_logic real)))
		(_type (_external ~realtime (vl verilog_logic realtime)))
		(_type (_external ~tri (vl verilog_logic tri)))
		(_type (_external ~triand (vl verilog_logic triand)))
		(_type (_external ~trior (vl verilog_logic trior)))
		(_type (_external ~bit (vl verilog_logic bit)))
		(_type (_external ~extstd.standard.integer (std standard integer)))
		(_type (_external ~extstd.standard.bit (std standard bit)))
		(_process
			(#ASSIGN#57_0 (_architecture 0 0 57 (_process (_alias ((updown)(CurrState_Sreg0(3))))(_simple)
				(_target(5))
				(_sensitivity(8(3)))
			)))
			(#ASSIGN#58_1 (_architecture 1 0 58 (_process (_alias ((ce)(CurrState_Sreg0(2))))(_simple)
				(_target(2))
				(_sensitivity(8(2)))
			)))
			(#ALWAYS#67_2 (_architecture 2 0 67 (_process 
				(_target(9))
				(_read)
				(_sensitivity(3)(4)(8))
			)))
			(#ALWAYS#150_3 (_architecture 3 0 150 (_process 
				(_target(8))
				(_read(1)(0)(9))
			)))
		)
	)
	
	
	(_defparam
	)
	(_scope
		(_unit Sreg0_NextState begin 0 68
		)
		(_unit Sreg0_CurrentState begin 0 151
		)
	)
	(_model . Decode 5 -1)

)
I 000048 55 2998          1080051936649 Counter
(_unit VERILOG 6.349C.6.256 (Counter 0 25 (Counter 0 25 ))
	(_version v32)
	(_time 1080051935828 2004.03.23 06:25:35)
	(_source (\./src/counter.v\ VERILOG (\./src/counter.v\ VERILOG)))
	(_use (std(standard))(vl(verilog_logic)))
	(_base (E 3))
	(_entity
		(_time 1080051935828)
		(_use )
	)
	(_timescale 1ps 1ps)
	(_parameters    dbg   accs  )
	(_attribute nb_assign )
	(_object
		(_port (_internal Zero ~wire 0 25 (_architecture (_in ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal ce ~wire 0 25 (_architecture (_in ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_type (_internal ~[23:0]wire~ 0 25 (_array ~wire ((_downto (i 23) (i 0))))))
		(_port (_internal count ~[23:0]wire~ 0 25 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal Reset ~wire 0 25 (_architecture (_in ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal updown ~wire 0 25 (_architecture (_in ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal Sclk ~wire 0 25 (_architecture (_in ))) (_net  ) (_nonbaction) (_noforceassign))
		(_port (_internal sense ~wire 0 25 (_architecture (_in ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_type (_internal ~[23:0]reg~ 0 48 (_array ~reg ((_downto (i 23) (i 0))))))
		(_signal (_internal location ~[23:0]reg~ 0 48 (_architecture (_uni ))) (_reg ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_subprogram
			

		)
		(_type (_external ~wire (vl verilog_logic wire)))
		(_type (_external ~reg (vl verilog_logic reg)))
		(_type (_external ~event (vl verilog_logic event)))
		(_type (_external ~wand (vl verilog_logic wand)))
		(_type (_external ~wor (vl verilog_logic wor)))
		(_type (_external ~tri1 (vl verilog_logic tri1)))
		(_type (_external ~tri0 (vl verilog_logic tri0)))
		(_type (_external ~trireg (vl verilog_logic trireg)))
		(_type (_external ~supply0 (vl verilog_logic supply0)))
		(_type (_external ~supply1 (vl verilog_logic supply1)))
		(_type (_external ~real (vl verilog_logic real)))
		(_type (_external ~realtime (vl verilog_logic realtime)))
		(_type (_external ~tri (vl verilog_logic tri)))
		(_type (_external ~triand (vl verilog_logic triand)))
		(_type (_external ~trior (vl verilog_logic trior)))
		(_type (_external ~bit (vl verilog_logic bit)))
		(_type (_external ~extstd.standard.integer (std standard integer)))
		(_type (_external ~extstd.standard.bit (std standard bit)))
		(_process
			(#ASSIGN#49_0 (_architecture 0 0 49 (_process (_alias ((count)(location)))(_simple)
				(_target(2))
				(_sensitivity(7))
			)))
			(#ALWAYS#51_1 (_architecture 1 0 51 (_process 
				(_target(7))
				(_read(5)(3)(0)(1)(4)(6)(7))
			)))
		)
	)
	
	
	(_defparam
	)
	(_model . Counter 3 -1)

)
I 000048 55 4486          1080051936656 Holdreg
(_unit VERILOG 6.349C.6.256 (Holdreg 0 25 (Holdreg 0 25 ))
	(_version v32)
	(_time 1080051935828 2004.03.23 06:25:35)
	(_source (\./src/holdreg.v\ VERILOG (\./src/holdreg.v\ VERILOG)))
	(_use (std(standard))(vl(verilog_logic)))
	(_base (E 4))
	(_entity
		(_time 1080051935828)
		(_use )
	)
	(_timescale 1ps 1ps)
	(_parameters    dbg   accs  )
	(_attribute nb_assign )
	(_object
		(_port (_internal DCOR1CNTHIGHr ~wire 0 25 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal DCOR0CNTLOWr ~wire 0 25 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_type (_internal ~[7:0]wire~ 0 25 (_array ~wire ((_downto (i 7) (i 0))))))
		(_port (_internal outDATA ~[7:0]wire~ 0 25 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal DCOR1CNTLOWr ~wire 0 25 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_type (_internal ~[23:0]wire~ 0 25 (_array ~wire ((_downto (i 23) (i 0))))))
		(_port (_internal ch0in ~[23:0]wire~ 0 25 (_architecture (_in ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal ch1in ~[23:0]wire~ 0 25 (_architecture (_in ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal Reset ~wire 0 25 (_architecture (_in ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal ASleading ~wire 0 25 (_architecture (_in ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal DCOR0CNTMIDr ~wire 0 25 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal DCOR1CNTMIDr ~wire 0 25 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal Sclk ~wire 0 25 (_architecture (_in ))) (_net  ) (_nonbaction) (_noforceassign))
		(_port (_internal DCOR0CNTHIGHr ~wire 0 25 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal RDedge ~reg 0 73 (_architecture (_uni ))) (_reg ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_type (_internal ~[23:0]reg~ 0 75 (_array ~reg ((_downto (i 23) (i 0))))))
		(_signal (_internal holdingreg0 ~[23:0]reg~ 0 75 (_architecture (_uni ))) (_reg ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal holdingreg1 ~[23:0]reg~ 0 75 (_architecture (_uni ))) (_reg ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal interDATA ~[7:0]wire~ 0 76 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_subprogram
			

		)
		(_type (_external ~wire (vl verilog_logic wire)))
		(_type (_external ~reg (vl verilog_logic reg)))
		(_type (_external ~event (vl verilog_logic event)))
		(_type (_external ~wand (vl verilog_logic wand)))
		(_type (_external ~wor (vl verilog_logic wor)))
		(_type (_external ~tri1 (vl verilog_logic tri1)))
		(_type (_external ~tri0 (vl verilog_logic tri0)))
		(_type (_external ~trireg (vl verilog_logic trireg)))
		(_type (_external ~supply0 (vl verilog_logic supply0)))
		(_type (_external ~supply1 (vl verilog_logic supply1)))
		(_type (_external ~real (vl verilog_logic real)))
		(_type (_external ~realtime (vl verilog_logic realtime)))
		(_type (_external ~tri (vl verilog_logic tri)))
		(_type (_external ~triand (vl verilog_logic triand)))
		(_type (_external ~trior (vl verilog_logic trior)))
		(_type (_external ~bit (vl verilog_logic bit)))
		(_type (_external ~extstd.standard.integer (std standard integer)))
		(_type (_external ~extstd.standard.bit (std standard bit)))
		(_process
			(#ASSIGN#91_0 (_architecture 0 0 91 (_process (_simple)
				(_target(15))
				(_sensitivity(1)(13(d_7_0))(3)(14(d_7_0))(8)(13(d_15_8))(9)(14(d_15_8))(11)(13(d_23_16))(0)(14(d_23_16)))
			)))
			(#ASSIGN#93_1 (_architecture 1 0 93 (_process (_alias ((outDATA)(interDATA)))(_simple)
				(_target(2))
				(_sensitivity(15))
			)))
			(#ALWAYS#95_2 (_architecture 2 0 95 (_process 
				(_target(12)(13)(14))
				(_read(10)(1)(3)(6)(7)(4)(5))
			)))
		)
	)
	
	
	(_defparam
	)
	(_model . Holdreg 4 -1)

)
I 000051 55 10303         1080051936672 HomeConfig
(_unit VERILOG 6.349C.6.256 (HomeConfig 0 25 (HomeConfig 0 25 ))
	(_version v32)
	(_time 1080051935828 2004.03.23 06:25:35)
	(_source (\./src/homeconfig.v\ VERILOG (\./src/homeconfig.v\ VERILOG)))
	(_use (std(standard))(vl(verilog_logic)))
	(_base (E 11))
	(_entity
		(_time 1080051935828)
		(_use )
	)
	(_timescale 1ps 1ps)
	(_parameters    dbg   accs  )
	(_attribute nb_assign )
	(_object
		(_port (_internal Tfound0 ~wire 0 25 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal Tfound1 ~wire 0 25 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal DCOR0THRESLOWr ~wire 0 25 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal DCOR1THRESLOWr ~wire 0 25 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal Reset ~wire 0 25 (_architecture (_in ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_type (_internal ~[15:0]wire~ 0 25 (_array ~wire ((_downto (i 15) (i 0))))))
		(_port (_internal Channel0 ~[15:0]wire~ 0 25 (_architecture (_in ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal Channel1 ~[15:0]wire~ 0 25 (_architecture (_in ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal DCOR0THRESMIDr ~wire 0 25 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal DCOR1THRESMIDr ~wire 0 25 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal Sclk ~wire 0 25 (_architecture (_in ))) (_net  ) (_nonbaction) (_noforceassign))
		(_port (_internal sense0 ~wire 0 25 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal sense1 ~wire 0 25 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal DCORIFGr ~wire 0 25 (_architecture (_in ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Zero0 ~wire 0 25 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_type (_internal ~[7:0]wire~ 0 25 (_array ~wire ((_downto (i 7) (i 0))))))
		(_port (_internal inDATA ~[7:0]wire~ 0 25 (_architecture (_in ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal Zero1 ~wire 0 25 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal outDATA ~[7:0]wire~ 0 25 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal Hfound0 ~wire 0 25 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal Hfound1 ~wire 0 25 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal DCORIFGw ~wire 0 25 (_architecture (_in ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal MotorIn0 ~wire 0 25 (_architecture (_in ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal Home_Encoder0 ~wire 0 25 (_architecture (_in ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal DCORENCCTLw ~wire 0 25 (_architecture (_in ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal MotorIn1 ~wire 0 25 (_architecture (_in ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal Home_Encoder1 ~wire 0 25 (_architecture (_in ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal RF1r ~reg 0 84 (_architecture (_uni ))) (_reg ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal E1r ~reg 0 86 (_architecture (_uni ))) (_reg ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal RF0r ~reg 0 88 (_architecture (_uni ))) (_reg ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal E0r ~reg 0 90 (_architecture (_uni ))) (_reg ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal LatchEdge0r ~reg 0 92 (_architecture (_uni ))) (_reg ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal LatchEdge1r ~reg 0 93 (_architecture (_uni ))) (_reg ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal sense0r ~reg 0 95 (_architecture (_uni ))) (_reg ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal sense1r ~reg 0 96 (_architecture (_uni ))) (_reg ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal HE0stater ~reg 0 99 (_architecture (_uni ))) (_reg ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal HE0statelastr ~reg 0 100 (_architecture (_uni ))) (_reg ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal HE1stater ~reg 0 101 (_architecture (_uni ))) (_reg ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal HE1statelastr ~reg 0 102 (_architecture (_uni ))) (_reg ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal Hfound0r ~reg 0 105 (_architecture (_uni ))) (_reg ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal Hfound1r ~reg 0 106 (_architecture (_uni ))) (_reg ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal Zero0r ~reg 0 108 (_architecture (_uni ))) (_reg ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal Zero1r ~reg 0 109 (_architecture (_uni ))) (_reg ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal Tfound0r ~reg 0 112 (_architecture (_uni ))) (_reg ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal Tfound1r ~reg 0 113 (_architecture (_uni ))) (_reg ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_type (_internal ~[15:0]reg~ 0 116 (_array ~reg ((_downto (i 15) (i 0))))))
		(_signal (_internal Latch0r ~[15:0]reg~ 0 116 (_architecture (_uni ))) (_reg ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal Latch1r ~[15:0]reg~ 0 117 (_architecture (_uni ))) (_reg ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal InEdge0r ~reg 0 120 (_architecture (_uni ))) (_reg ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal InEdge1r ~reg 0 121 (_architecture (_uni ))) (_reg ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_subprogram
			

		)
		(_type (_external ~wire (vl verilog_logic wire)))
		(_type (_external ~reg (vl verilog_logic reg)))
		(_type (_external ~event (vl verilog_logic event)))
		(_type (_external ~wand (vl verilog_logic wand)))
		(_type (_external ~wor (vl verilog_logic wor)))
		(_type (_external ~tri1 (vl verilog_logic tri1)))
		(_type (_external ~tri0 (vl verilog_logic tri0)))
		(_type (_external ~trireg (vl verilog_logic trireg)))
		(_type (_external ~supply0 (vl verilog_logic supply0)))
		(_type (_external ~supply1 (vl verilog_logic supply1)))
		(_type (_external ~real (vl verilog_logic real)))
		(_type (_external ~realtime (vl verilog_logic realtime)))
		(_type (_external ~tri (vl verilog_logic tri)))
		(_type (_external ~triand (vl verilog_logic triand)))
		(_type (_external ~trior (vl verilog_logic trior)))
		(_type (_external ~bit (vl verilog_logic bit)))
		(_type (_external ~extstd.standard.integer (std standard integer)))
		(_type (_external ~extstd.standard.bit (std standard bit)))
		(_process
			(#ASSIGN#127_0 (_architecture 0 0 127 (_process (_alias ((Zero0)(Zero0r)))(_simple)
				(_target(13))
				(_sensitivity(39))
			)))
			(#ASSIGN#128_1 (_architecture 1 0 128 (_process (_alias ((Zero1)(Zero1r)))(_simple)
				(_target(15))
				(_sensitivity(40))
			)))
			(#ASSIGN#132_2 (_architecture 2 0 132 (_process (_alias ((sense0)(sense0r)))(_simple)
				(_target(10))
				(_sensitivity(31))
			)))
			(#ASSIGN#133_3 (_architecture 3 0 133 (_process (_alias ((sense1)(sense1r)))(_simple)
				(_target(11))
				(_sensitivity(32))
			)))
			(#ASSIGN#135_4 (_architecture 4 0 135 (_process (_alias ((Hfound1)(Hfound1r)))(_simple)
				(_target(18))
				(_sensitivity(38))
			)))
			(#ASSIGN#136_5 (_architecture 5 0 136 (_process (_alias ((Hfound0)(Hfound0r)))(_simple)
				(_target(17))
				(_sensitivity(37))
			)))
			(#ASSIGN#137_6 (_architecture 6 0 137 (_process (_alias ((Tfound0)(Tfound0r)))(_simple)
				(_target(0))
				(_sensitivity(41))
			)))
			(#ASSIGN#138_7 (_architecture 7 0 138 (_process (_alias ((Tfound1)(Tfound1r)))(_simple)
				(_target(1))
				(_sensitivity(42))
			)))
			(#ASSIGN#145_8 (_architecture 8 0 145 (_process (_simple)
				(_target(16))
				(_sensitivity(2)(43(d_7_0))(7)(43(d_15_8))(3)(44(d_7_0))(8)(44(d_15_8)))
			)))
			(#ALWAYS#147_9 (_architecture 9 0 147 (_process 
				(_target(33)(34)(35)(36)(45)(46)(32)(30)(26)(25)(31)(29)(28)(27)(43)(44)(42)(41)(38)(37)(39)(40))
				(_read(9)(21)(33)(24)(35)(20)(23)(4)(22)(14)(19)(14(d_6_5))(14(d_3_2))(27)(34)(17)(28)(37)(26)(25)(36)(18)(38)(0)(45)(29)(5)(41)(43)(1)(46)(30)(6)(42))
			)))
		)
	)
	
	
	(_defparam
	)
	(_model . HomeConfig 11 -1)

)
I 000054 55 3632          1080051936688 PWMtranslator
(_unit VERILOG 6.349C.6.256 (PWMtranslator 0 27 (PWMtranslator 0 27 ))
	(_version v32)
	(_time 1080051935828 2004.03.23 06:25:35)
	(_source (\./src/PWMtranslator.v\ VERILOG (\./src/pwmtranslator.v\ VERILOG)))
	(_use (std(standard))(vl(verilog_logic)))
	(_base (E 6))
	(_entity
		(_time 1080051935828)
		(_use )
	)
	(_timescale 1ps 1ps)
	(_parameters    dbg   accs  )
	(_attribute )
	(_object
		(_port (_internal PWM ~wire 0 27 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal fBRK ~wire 0 27 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal Brake ~wire 0 27 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal HBRK ~wire 0 27 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal PAH ~wire 0 27 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal PBH ~wire 0 27 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal PAL ~wire 0 27 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal PBL ~wire 0 27 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal DIR ~wire 0 27 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal BRK ~wire 0 55 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_subprogram
			

		)
		(_type (_external ~wire (vl verilog_logic wire)))
		(_type (_external ~reg (vl verilog_logic reg)))
		(_type (_external ~event (vl verilog_logic event)))
		(_type (_external ~wand (vl verilog_logic wand)))
		(_type (_external ~wor (vl verilog_logic wor)))
		(_type (_external ~tri1 (vl verilog_logic tri1)))
		(_type (_external ~tri0 (vl verilog_logic tri0)))
		(_type (_external ~trireg (vl verilog_logic trireg)))
		(_type (_external ~supply0 (vl verilog_logic supply0)))
		(_type (_external ~supply1 (vl verilog_logic supply1)))
		(_type (_external ~real (vl verilog_logic real)))
		(_type (_external ~realtime (vl verilog_logic realtime)))
		(_type (_external ~tri (vl verilog_logic tri)))
		(_type (_external ~triand (vl verilog_logic triand)))
		(_type (_external ~trior (vl verilog_logic trior)))
		(_type (_external ~bit (vl verilog_logic bit)))
		(_type (_external ~extstd.standard.integer (std standard integer)))
		(_type (_external ~extstd.standard.bit (std standard bit)))
		(_process
			(#ASSIGN#57_0 (_architecture 0 0 57 (_process (_alias ((BRK)(fBRK)(Brake)(HBRK)))(_simple)
				(_target(9))
				(_sensitivity(1)(2)(3))
			)))
			(#ASSIGN#64_1 (_architecture 1 0 64 (_process (_alias ((PAH)(PWM)(DIR)(BRK)))(_simple)
				(_target(4))
				(_sensitivity(0)(8)(9))
			)))
			(#ASSIGN#65_2 (_architecture 2 0 65 (_process (_alias ((PAL)(PWM)(DIR)(BRK)(PWM)(DIR)(BRK)))(_simple)
				(_target(6))
				(_sensitivity(0)(8)(9))
			)))
			(#ASSIGN#66_3 (_architecture 3 0 66 (_process (_alias ((PBH)(PWM)(DIR)(BRK)))(_simple)
				(_target(5))
				(_sensitivity(0)(8)(9))
			)))
			(#ASSIGN#67_4 (_architecture 4 0 67 (_process (_alias ((PBL)(PWM)(DIR)(BRK)(PWM)(DIR)(BRK)))(_simple)
				(_target(7))
				(_sensitivity(0)(8)(9))
			)))
		)
	)
	
	
	(_defparam
	)
	(_model . PWMtranslator 6 -1)

)
I 000050 55 2394          1080051936692 NegDetect
(_unit VERILOG 6.349C.6.256 (NegDetect 0 25 (NegDetect 0 25 ))
	(_version v32)
	(_time 1080051935828 2004.03.23 06:25:35)
	(_source (\./src/negdetect.v\ VERILOG (\./src/negdetect.v\ VERILOG)))
	(_use (std(standard))(vl(verilog_logic)))
	(_base (E 3))
	(_entity
		(_time 1080051935828)
		(_use )
	)
	(_timescale 1ps 1ps)
	(_parameters    dbg   accs  )
	(_attribute nb_assign )
	(_object
		(_port (_internal Line ~wire 0 25 (_architecture (_in ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal Ndetect ~wire 0 25 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal Mclk ~wire 0 25 (_architecture (_in ))) (_net  ) (_nonbaction) (_noforceassign))
		(_signal (_internal Line_last ~reg 0 39 (_architecture (_uni ))) (_reg ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal Ndetectr ~reg 0 40 (_architecture (_uni ))) (_reg ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_subprogram
			

		)
		(_type (_external ~wire (vl verilog_logic wire)))
		(_type (_external ~reg (vl verilog_logic reg)))
		(_type (_external ~event (vl verilog_logic event)))
		(_type (_external ~wand (vl verilog_logic wand)))
		(_type (_external ~wor (vl verilog_logic wor)))
		(_type (_external ~tri1 (vl verilog_logic tri1)))
		(_type (_external ~tri0 (vl verilog_logic tri0)))
		(_type (_external ~trireg (vl verilog_logic trireg)))
		(_type (_external ~supply0 (vl verilog_logic supply0)))
		(_type (_external ~supply1 (vl verilog_logic supply1)))
		(_type (_external ~real (vl verilog_logic real)))
		(_type (_external ~realtime (vl verilog_logic realtime)))
		(_type (_external ~tri (vl verilog_logic tri)))
		(_type (_external ~triand (vl verilog_logic triand)))
		(_type (_external ~trior (vl verilog_logic trior)))
		(_type (_external ~bit (vl verilog_logic bit)))
		(_type (_external ~extstd.standard.integer (std standard integer)))
		(_type (_external ~extstd.standard.bit (std standard bit)))
		(_process
			(#ASSIGN#42_0 (_architecture 0 0 42 (_process (_alias ((Ndetect)(Ndetectr)))(_simple)
				(_target(1))
				(_sensitivity(4))
			)))
			(#ALWAYS#44_1 (_architecture 1 0 44 (_process 
				(_target(3)(4))
				(_read(2)(0)(3))
			)))
		)
	)
	
	
	(_defparam
	)
	(_model . NegDetect 3 -1)

)
I 000051 55 3750          1080051936696 BitCounter
(_unit VERILOG 6.349C.6.256 (BitCounter 0 25 (BitCounter 0 25 ))
	(_version v32)
	(_time 1080051935828 2004.03.23 06:25:35)
	(_source (\./src/bitcounter.v\ VERILOG (\./src/bitcounter.v\ VERILOG)))
	(_use (std(standard))(vl(verilog_logic)))
	(_base (E 6))
	(_entity
		(_time 1080051935828)
		(_use )
	)
	(_timescale 1ps 1ps)
	(_parameters    dbg   accs  )
	(_attribute nb_assign )
	(_object
		(_type (_internal ~[7:0]wire~ 0 25 (_array ~wire ((_downto (i 7) (i 0))))))
		(_port (_internal outDATA ~[7:0]wire~ 0 25 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal NegInc ~wire 0 25 (_architecture (_in ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal SCLreset ~wire 0 25 (_architecture (_in ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal Mclk ~wire 0 25 (_architecture (_in ))) (_net  ) (_nonbaction) (_noforceassign))
		(_port (_internal SCLenable ~wire 0 25 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal Inc ~wire 0 25 (_architecture (_in ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal DriveSCL ~wire 0 25 (_architecture (_inout ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal NegSCL ~wire 0 25 (_architecture (_in ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal DCORI2CCNTr ~wire 0 25 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal SCLint ~wire 0 25 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_type (_internal ~[5:0]reg~ 0 54 (_array ~reg ((_downto (i 5) (i 0))))))
		(_signal (_internal counterr ~[5:0]reg~ 0 54 (_architecture (_uni ))) (_reg ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_subprogram
			

		)
		(_type (_external ~wire (vl verilog_logic wire)))
		(_type (_external ~reg (vl verilog_logic reg)))
		(_type (_external ~event (vl verilog_logic event)))
		(_type (_external ~wand (vl verilog_logic wand)))
		(_type (_external ~wor (vl verilog_logic wor)))
		(_type (_external ~tri1 (vl verilog_logic tri1)))
		(_type (_external ~tri0 (vl verilog_logic tri0)))
		(_type (_external ~trireg (vl verilog_logic trireg)))
		(_type (_external ~supply0 (vl verilog_logic supply0)))
		(_type (_external ~supply1 (vl verilog_logic supply1)))
		(_type (_external ~real (vl verilog_logic real)))
		(_type (_external ~realtime (vl verilog_logic realtime)))
		(_type (_external ~tri (vl verilog_logic tri)))
		(_type (_external ~triand (vl verilog_logic triand)))
		(_type (_external ~trior (vl verilog_logic trior)))
		(_type (_external ~bit (vl verilog_logic bit)))
		(_type (_external ~extstd.standard.integer (std standard integer)))
		(_type (_external ~extstd.standard.bit (std standard bit)))
		(_process
			(#ASSIGN#56_0 (_architecture 0 0 56 (_process (_simple)
				(_target(9))
				(_sensitivity(10))
			)))
			(#ASSIGN#58_1 (_architecture 1 0 58 (_process (_simple)
				(_target(4))
				(_sensitivity(10))
			)))
			(#ASSIGN#60_2 (_architecture 2 0 60 (_process (_simple)
				(_target(6))
				(_sensitivity(4))
			)))
			(#ASSIGN#62_3 (_architecture 3 0 62 (_process (_simple)
				(_target(0))
				(_sensitivity(8)(10))
			)))
			(#ALWAYS#64_4 (_architecture 4 0 64 (_process 
				(_target(10))
				(_read(3)(2)(5)(1)(7)(10))
			)))
		)
	)
	
	
	(_defparam
	)
	(_model . BitCounter 6 -1)

)
I 000044 55 5014          1080051936703 MSP
(_unit VERILOG 6.349C.6.256 (MSP 0 25 (MSP 0 25 ))
	(_version v32)
	(_time 1080051935828 2004.03.23 06:25:35)
	(_source (\./src/msp.v\ VERILOG (\./src/msp.v\ VERILOG)))
	(_use (std(standard))(vl(verilog_logic)))
	(_base (E 7))
	(_entity
		(_time 1080051935828)
		(_use )
	)
	(_timescale 1ps 1ps)
	(_parameters    dbg   accs  )
	(_attribute )
	(_object
		(_type (_internal ~vector~0 0 52 (_array ~bit ((_uto (i 0) (i 0))))(_attribute signed)))
		(_generic (_internal Half_period ~vector~0 0 52 \500000\ (_entity -1 (_constant \500000\))))
		(_type (_internal ~vector~1 0 53 (_array ~bit ((_uto (i 0) (i 0))))(_attribute signed)))
		(_generic (_internal BITS ~vector~1 0 53 \12\ (_entity -1 (_constant \12\))))
		(_type (_internal ~vector~2 0 53 (_array ~bit ((_uto (i 0) (i 0))))(_attribute signed)))
		(_generic (_internal WORDS ~vector~2 0 53 \159\ (_entity -1 (_constant \159\))))
		(_port (_internal WR ~wire 0 25 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal AS ~wire 0 25 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_type (_internal ~[7:0]wire~ 0 25 (_array ~wire ((_downto (i 7) (i 0))))))
		(_port (_internal AD ~[7:0]wire~ 0 25 (_architecture (_inout ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal RD ~wire 0 25 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal Mclk ~wire 0 25 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal ASr ~reg 0 43 (_architecture (_uni ))) (_reg ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal WRr ~reg 0 44 (_architecture (_uni ))) (_reg ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal RDr ~reg 0 45 (_architecture (_uni ))) (_reg ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal Mclkr ~reg 0 46 (_architecture (_uni ))) (_reg ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_type (_internal ~[7:0]reg~ 0 47 (_array ~reg ((_downto (i 7) (i 0))))))
		(_signal (_internal ADr ~[7:0]reg~ 0 47 (_architecture (_uni ))) (_reg ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal busDrive ~reg 0 48 (_architecture (_uni ))) (_reg ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_type (_internal ~integer 0 50 (_array ~reg ((_downto (i 31) (i 0))))(_attribute signed)))
		(_signal (_internal J ~integer 0 50 (_architecture (_uni ))) (_reg integer) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_type (_internal ~[1:BITS]reg~[1:WORDS]~ 0 54 (_array ~reg ((_range  7)(_range  8)))))
		(_signal (_internal Vmem ~[1:BITS]reg~[1:WORDS]~ 0 54 (_architecture (_uni ))) (_reg memory) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_subprogram
			
			(_function \$readmemb\)

		)
		(_type (_external ~wire (vl verilog_logic wire)))
		(_type (_external ~reg (vl verilog_logic reg)))
		(_type (_external ~event (vl verilog_logic event)))
		(_type (_external ~wand (vl verilog_logic wand)))
		(_type (_external ~wor (vl verilog_logic wor)))
		(_type (_external ~tri1 (vl verilog_logic tri1)))
		(_type (_external ~tri0 (vl verilog_logic tri0)))
		(_type (_external ~trireg (vl verilog_logic trireg)))
		(_type (_external ~supply0 (vl verilog_logic supply0)))
		(_type (_external ~supply1 (vl verilog_logic supply1)))
		(_type (_external ~real (vl verilog_logic real)))
		(_type (_external ~realtime (vl verilog_logic realtime)))
		(_type (_external ~tri (vl verilog_logic tri)))
		(_type (_external ~triand (vl verilog_logic triand)))
		(_type (_external ~trior (vl verilog_logic trior)))
		(_type (_external ~bit (vl verilog_logic bit)))
		(_type (_external ~extstd.standard.integer (std standard integer)))
		(_type (_external ~extstd.standard.bit (std standard bit)))
		(_process
			(#ASSIGN#57_0 (_architecture 0 0 57 (_process (_alias ((AS)(ASr)))(_simple)
				(_target(1))
				(_sensitivity(5))
			)))
			(#ASSIGN#58_1 (_architecture 1 0 58 (_process (_alias ((RD)(RDr)))(_simple)
				(_target(3))
				(_sensitivity(7))
			)))
			(#ASSIGN#59_2 (_architecture 2 0 59 (_process (_alias ((WR)(WRr)))(_simple)
				(_target(0))
				(_sensitivity(6))
			)))
			(#ASSIGN#60_3 (_architecture 3 0 60 (_process (_simple)
				(_target(2))
				(_sensitivity(10)(9))
			)))
			(#ASSIGN#61_4 (_architecture 4 0 61 (_process (_alias ((Mclk)(Mclkr)))(_simple)
				(_target(4))
				(_sensitivity(8))
			)))
			(#INITIAL#63_5 (_architecture 5 0 63 (_process 
				(_target(11)(8)(5)(7)(6)(10)(9))
				(_read(12)(11))
			)))
			(#INTERNAL#0_6 (_internal 6 0 0 (_process (_virtual))))
		)
	)
	
	
	(_defparam
	)
	(_model . MSP 9 -1)

)
V 000046 55 8513          1080051936719 U4_TB
(_unit VERILOG 6.349C.6.256 (U4_TB 0 32 (U4_TB 0 32 ))
	(_version v32)
	(_time 1080051935828 2004.03.23 06:25:35)
	(_source (\./compile/U21_TB.v\ VERILOG (\./compile/u21_tb.v\ VERILOG)))
	(_use (std(standard))(vl(verilog_logic)))
	(_base (E 3))
	(_entity
		(_time 1080051935828)
		(_use )
	)
	(_timescale 1ns 1ns)
	(_parameters    dbg   accs  )
	(_attribute )
	(_object
		(_type (_internal ~vector~0 0 78 (_array ~bit ((_uto (i 0) (i 0))))))
		(_generic (_internal DANGLING_INPUT_CONSTANT ~vector~0 0 78 \1'bZ\ (_entity -1 (_constant \1'bZ\))))
		(_port (_internal Enc133FLG ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Enc15FLG ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal FLS1 ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal FLS2 ~wire 0 32 (_architecture (_in ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Home1 ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Home133FLG ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Home15FLG ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Home2 ~wire 0 32 (_architecture (_in ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PhaseA_Encoder1 ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PhaseB_Encoder1 ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal RLS1 ~wire 0 33 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal RLS2 ~wire 0 33 (_architecture (_in ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Reset ~wire 0 33 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal SCL ~wire 0 33 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal SCLinc ~wire 0 33 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal SCLreset ~wire 0 33 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Enc133ctrl ~wire 0 33 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Enc15ctrl ~wire 0 33 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Home133ctrl ~wire 0 33 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Home15ctrl ~wire 0 33 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal AS ~wire 0 81 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal Mclk ~wire 0 82 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal RD ~wire 0 83 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal WR ~wire 0 84 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_type (_internal ~[7:0]wire~ 0 85 (_array ~wire ((_downto (i 7) (i 0))))))
		(_signal (_internal AD ~[7:0]wire~ 0 85 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal Dangling_Input_Signal ~wire 0 88 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_type (_internal ~[5:0]wire~ 0 119 (_array ~wire ((_downto (i 5) (i 0))))))
		(_signal (_internal \1 \ ~[5:0]wire~ -1 119 (_internal (_uni ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_subprogram
			

		)
		(_type (_external ~wire (vl verilog_logic wire)))
		(_type (_external ~reg (vl verilog_logic reg)))
		(_type (_external ~event (vl verilog_logic event)))
		(_type (_external ~wand (vl verilog_logic wand)))
		(_type (_external ~wor (vl verilog_logic wor)))
		(_type (_external ~tri1 (vl verilog_logic tri1)))
		(_type (_external ~tri0 (vl verilog_logic tri0)))
		(_type (_external ~trireg (vl verilog_logic trireg)))
		(_type (_external ~supply0 (vl verilog_logic supply0)))
		(_type (_external ~supply1 (vl verilog_logic supply1)))
		(_type (_external ~real (vl verilog_logic real)))
		(_type (_external ~realtime (vl verilog_logic realtime)))
		(_type (_external ~tri (vl verilog_logic tri)))
		(_type (_external ~triand (vl verilog_logic triand)))
		(_type (_external ~trior (vl verilog_logic trior)))
		(_type (_external ~bit (vl verilog_logic bit)))
		(_type (_external ~extstd.standard.integer (std standard integer)))
		(_type (_external ~extstd.standard.bit (std standard bit)))
		(_process
			(#INTERNAL#119_0 (_internal 0 0 119 (_process (_simple)
				(_target(26))
				(_sensitivity(25))
			)))
			(#ASSIGN#88_1 (_architecture 1 0 88 (_process (_simple)
				(_target(25))
			)))
			(#INTERNAL#0_2 (_internal 2 0 0 (_process (_virtual))))
		)
	)
	
	
	(_defparam
	)
	(_scope
	)
	(_instantiation U1 0 92 (_entity .  U21)
		(_port
			((AD) (AD))
			((AS) (AS))
			((Brake0) (Dangling_Input_Signal))
			((Brake1) (Dangling_Input_Signal))
			((DIR0) (Dangling_Input_Signal))
			((DIR1) (Dangling_Input_Signal))
			((Enc033FLG) (Dangling_Input_Signal))
			((Enc05FLG) (Dangling_Input_Signal))
			((Enc133FLG) (Enc133FLG))
			((Enc133ctrl) (Enc133ctrl))
			((Enc15FLG) (Enc15FLG))
			((Enc15ctrl) (Enc15ctrl))
			((FLS0) (Dangling_Input_Signal))
			((FLS1) (FLS1))
			((GP_Motor0_0) (Dangling_Input_Signal))
			((GP_Motor1_0) (Dangling_Input_Signal))
			((HSI) (Dangling_Input_Signal))
			((Home0) (Dangling_Input_Signal))
			((Home033FLG) (Dangling_Input_Signal))
			((Home05FLG) (Dangling_Input_Signal))
			((Home1) (Home1))
			((Home133FLG) (Home133FLG))
			((Home133ctrl) (Home133ctrl))
			((Home15FLG) (Home15FLG))
			((Home15ctrl) (Home15ctrl))
			((I2CS) (\1 \))
			((INTbus) (Dangling_Input_Signal))
			((LightSense) (Dangling_Input_Signal))
			((MHSO) (Dangling_Input_Signal))
			((Mclk) (Mclk))
			((PWM1) (Dangling_Input_Signal))
			((PWM2) (Dangling_Input_Signal))
			((PhaseA_Encoder0) (Dangling_Input_Signal))
			((PhaseA_Encoder1) (PhaseA_Encoder1))
			((PhaseB_Encoder0) (Dangling_Input_Signal))
			((PhaseB_Encoder1) (PhaseB_Encoder1))
			((RD) (RD))
			((RLS0) (Dangling_Input_Signal))
			((RLS1) (RLS1))
			((Reset) (Reset))
			((SCL) (SCL))
			((SCLinc) (SCLinc))
			((SCLreset) (SCLreset))
			((TXI) (Dangling_Input_Signal))
			((WR) (WR))
			((Enc033ctrl) (_open))
			((Enc05ctrl) (_open))
			((GP_Motor0_1) (_open))
			((GP_Motor1_1) (_open))
			((HSO) (_open))
			((Home033ctrl) (_open))
			((Home05ctrl) (_open))
			((INT) (_open))
			((LED1) (_open))
			((LED2) (_open))
			((LED3) (_open))
			((LED4) (_open))
			((LED5) (_open))
			((MHSI) (_open))
			((MTRpwr) (_open))
			((MTRpwrn) (_open))
			((MTXI) (_open))
			((PAH0) (_open))
			((PAH1) (_open))
			((PAL0) (_open))
			((PAL1) (_open))
			((PBH0) (_open))
			((PBH1) (_open))
			((PBL0) (_open))
			((PBL1) (_open))
			((TP10) (_open))
			((TP11) (_open))
			((TP12) (_open))
		)
		(_strength)
	)
	(_instantiation U2 0 143 (_entity .  MSP)
		(_port
			((AD) (AD))
			((AS) (AS))
			((Mclk) (Mclk))
			((RD) (RD))
			((WR) (WR))
		)
		(_strength)
	)
	(_model . U4_TB 3 -1)

)
V 000052 55 12821         1080051936735 U21_TB_tsim
(_unit VERILOG 6.349C.6.256 (U21_TB_tsim 0 32 (U21_TB_tsim 0 32 ))
	(_version v32)
	(_time 1080051935828 2004.03.23 06:25:35)
	(_source (\./compile/U21_TB_tsim.v\ VERILOG (\./compile/u21_tb_tsim.v\ VERILOG)))
	(_use (std(standard))(vl(verilog_logic)))
	(_base (E 3))
	(_entity
		(_time 1080051935828)
		(_use )
	)
	(_timescale 1ns 1ns)
	(_parameters    dbg   accs  )
	(_attribute )
	(_object
		(_type (_internal ~vector~0 0 139 (_array ~bit ((_uto (i 0) (i 0))))))
		(_generic (_internal DANGLING_INPUT_CONSTANT ~vector~0 0 139 \1'bZ\ (_entity -1 (_constant \1'bZ\))))
		(_port (_internal Brake1 ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Brake2 ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal DIR1 ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal DIR2 ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Enc133FLG ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Enc15FLG ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Enc233FLG ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Enc25FLG ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal FLS1 ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal FLS2 ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Home1 ~wire 0 33 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Home133FLG ~wire 0 33 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Home15FLG ~wire 0 33 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Home2 ~wire 0 33 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Home233FLG ~wire 0 33 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Home25FLG ~wire 0 33 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PWM1 ~wire 0 33 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PWM2 ~wire 0 33 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PhaseA_Encoder1 ~wire 0 33 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PhaseA_Encoder2 ~wire 0 33 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PhaseB_Encoder1 ~wire 0 34 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PhaseB_Encoder2 ~wire 0 34 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal RLS1 ~wire 0 34 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal RLS2 ~wire 0 34 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Reset ~wire 0 34 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Enc133ctrl ~wire 0 34 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Enc15ctrl ~wire 0 34 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Enc233ctrl ~wire 0 34 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Enc25ctrl ~wire 0 34 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Home133ctrl ~wire 0 34 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Home15ctrl ~wire 0 35 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Home233ctrl ~wire 0 35 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Home25ctrl ~wire 0 35 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal INT ~wire 0 35 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal LED1 ~wire 0 35 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal LED2 ~wire 0 35 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal LED3 ~wire 0 35 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal LED4 ~wire 0 35 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal LED5 ~wire 0 35 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal MTRpwr ~wire 0 35 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal MTRpwrn ~wire 0 36 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PAH1 ~wire 0 36 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PAH2 ~wire 0 36 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PAL1 ~wire 0 36 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PAL2 ~wire 0 36 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PBH1 ~wire 0 36 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PBH2 ~wire 0 36 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PBL1 ~wire 0 36 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PBL2 ~wire 0 36 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal AS ~wire 0 142 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal Mclk ~wire 0 143 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal RD ~wire 0 144 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal WR ~wire 0 145 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_type (_internal ~[7:0]wire~ 0 146 (_array ~wire ((_downto (i 7) (i 0))))))
		(_signal (_internal AD ~[7:0]wire~ 0 146 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal Dangling_Input_Signal ~wire 0 149 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_type (_internal ~[5:0]wire~ 0 184 (_array ~wire ((_downto (i 5) (i 0))))))
		(_signal (_internal \1 \ ~[5:0]wire~ -1 184 (_internal (_uni ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_subprogram
			

		)
		(_type (_external ~wire (vl verilog_logic wire)))
		(_type (_external ~reg (vl verilog_logic reg)))
		(_type (_external ~event (vl verilog_logic event)))
		(_type (_external ~wand (vl verilog_logic wand)))
		(_type (_external ~wor (vl verilog_logic wor)))
		(_type (_external ~tri1 (vl verilog_logic tri1)))
		(_type (_external ~tri0 (vl verilog_logic tri0)))
		(_type (_external ~trireg (vl verilog_logic trireg)))
		(_type (_external ~supply0 (vl verilog_logic supply0)))
		(_type (_external ~supply1 (vl verilog_logic supply1)))
		(_type (_external ~real (vl verilog_logic real)))
		(_type (_external ~realtime (vl verilog_logic realtime)))
		(_type (_external ~tri (vl verilog_logic tri)))
		(_type (_external ~triand (vl verilog_logic triand)))
		(_type (_external ~trior (vl verilog_logic trior)))
		(_type (_external ~bit (vl verilog_logic bit)))
		(_type (_external ~extstd.standard.integer (std standard integer)))
		(_type (_external ~extstd.standard.bit (std standard bit)))
		(_process
			(#INTERNAL#184_0 (_internal 0 0 184 (_process (_simple)
				(_target(55))
				(_sensitivity(54))
			)))
			(#ASSIGN#149_1 (_architecture 1 0 149 (_process (_simple)
				(_target(54))
			)))
			(#INTERNAL#0_2 (_internal 2 0 0 (_process (_virtual))))
		)
	)
	
	
	(_defparam
	)
	(_scope
	)
	(_instantiation U1 0 153 (_entity .  U21)
		(_port
			((AD) (AD))
			((AS) (AS))
			((Brake0) (Brake1))
			((Brake1) (Brake2))
			((DIR0) (DIR1))
			((DIR1) (DIR2))
			((Enc033FLG) (Enc133FLG))
			((Enc033ctrl) (Enc133ctrl))
			((Enc05FLG) (Enc15FLG))
			((Enc05ctrl) (Enc15ctrl))
			((Enc133FLG) (Enc233FLG))
			((Enc133ctrl) (Enc233ctrl))
			((Enc15FLG) (Enc25FLG))
			((Enc15ctrl) (Enc25ctrl))
			((FLS0) (FLS1))
			((FLS1) (FLS2))
			((GP_Motor0_0) (Dangling_Input_Signal))
			((GP_Motor1_0) (Dangling_Input_Signal))
			((HSI) (Dangling_Input_Signal))
			((Home0) (Home1))
			((Home033FLG) (Home133FLG))
			((Home033ctrl) (Home133ctrl))
			((Home05FLG) (Home15FLG))
			((Home05ctrl) (Home15ctrl))
			((Home1) (Home2))
			((Home133FLG) (Home233FLG))
			((Home133ctrl) (Home233ctrl))
			((Home15FLG) (Home25FLG))
			((Home15ctrl) (Home25ctrl))
			((I2CS) (\1 \))
			((INT) (INT))
			((INTbus) (Dangling_Input_Signal))
			((LED1) (LED1))
			((LED2) (LED2))
			((LED3) (LED3))
			((LED4) (LED4))
			((LED5) (LED5))
			((LightSense) (Dangling_Input_Signal))
			((MHSO) (Dangling_Input_Signal))
			((MTRpwr) (MTRpwr))
			((MTRpwrn) (MTRpwrn))
			((Mclk) (Mclk))
			((PAH0) (PAH1))
			((PAH1) (PAH2))
			((PAL0) (PAL1))
			((PAL1) (PAL2))
			((PBH0) (PBH1))
			((PBH1) (PBH2))
			((PBL0) (PBL1))
			((PBL1) (PBL2))
			((PWM1) (PWM1))
			((PWM2) (PWM2))
			((PhaseA_Encoder0) (PhaseA_Encoder1))
			((PhaseA_Encoder1) (PhaseA_Encoder2))
			((PhaseB_Encoder0) (PhaseB_Encoder1))
			((PhaseB_Encoder1) (PhaseB_Encoder2))
			((RD) (RD))
			((RLS0) (RLS1))
			((RLS1) (RLS2))
			((Reset) (Reset))
			((SCLinc) (Dangling_Input_Signal))
			((SCLreset) (Dangling_Input_Signal))
			((TXI) (Dangling_Input_Signal))
			((WR) (WR))
			((GP_Motor0_1) (_open))
			((GP_Motor1_1) (_open))
			((HSO) (_open))
			((MHSI) (_open))
			((MTXI) (_open))
			((TP10) (_open))
			((TP11) (_open))
			((TP12) (_open))
			((SCL) (_open))
		)
		(_strength)
	)
	(_instantiation U2 0 223 (_entity .  MSP)
		(_port
			((AD) (AD))
			((AS) (AS))
			((Mclk) (Mclk))
			((RD) (RD))
			((WR) (WR))
		)
		(_strength)
	)
	(_model . U21_TB_tsim 3 -1)

)
V 000054 55 3721          1080051936739 EncoderEngine
(_unit VERILOG 6.349C.6.256 (EncoderEngine 0 23 (EncoderEngine 0 23 ))
	(_version v32)
	(_time 1080051935828 2004.03.23 06:25:35)
	(_source (\./compile/EncoderEngine.v\ VERILOG (\./compile/encoderengine.v\ VERILOG)))
	(_use (std(standard))(vl(verilog_logic)))
	(_base (E 5))
	(_entity
		(_time 1080051935828)
		(_use )
	)
	(_timescale 1ns 1ps)
	(_parameters    dbg   accs  )
	(_attribute nb_assign )
	(_object
		(_port (_internal DAV ~reg 0 23 (_architecture (_out ))) (_reg ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_type (_internal ~[5:0]reg~ 0 23 (_array ~reg ((_downto (i 5) (i 0))))))
		(_port (_internal SSclkb ~[5:0]reg~ 0 23 (_architecture (_out ))) (_reg ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal clk ~wire 0 23 (_architecture (_in ))) (_net  ) (_nonbaction) (_noforceassign))
		(_port (_internal data ~wire 0 23 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal reset ~wire 0 23 (_architecture (_in ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal shift ~reg 0 23 (_architecture (_out ))) (_reg ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal start ~wire 0 23 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal next_DAV ~reg 0 32 (_architecture (_uni ))) (_reg ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal next_shift ~reg 0 37 (_architecture (_uni ))) (_reg ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal CurrState_Sreg0 ~[5:0]reg~ 0 83 (_architecture (_uni ))) (_reg ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal NextState_Sreg0 ~[5:0]reg~ 0 85 (_architecture (_uni ))) (_reg ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_subprogram
			

		)
		(_type (_external ~wire (vl verilog_logic wire)))
		(_type (_external ~reg (vl verilog_logic reg)))
		(_type (_external ~event (vl verilog_logic event)))
		(_type (_external ~wand (vl verilog_logic wand)))
		(_type (_external ~wor (vl verilog_logic wor)))
		(_type (_external ~tri1 (vl verilog_logic tri1)))
		(_type (_external ~tri0 (vl verilog_logic tri0)))
		(_type (_external ~trireg (vl verilog_logic trireg)))
		(_type (_external ~supply0 (vl verilog_logic supply0)))
		(_type (_external ~supply1 (vl verilog_logic supply1)))
		(_type (_external ~real (vl verilog_logic real)))
		(_type (_external ~realtime (vl verilog_logic realtime)))
		(_type (_external ~tri (vl verilog_logic tri)))
		(_type (_external ~triand (vl verilog_logic triand)))
		(_type (_external ~trior (vl verilog_logic trior)))
		(_type (_external ~bit (vl verilog_logic bit)))
		(_type (_external ~extstd.standard.integer (std standard integer)))
		(_type (_external ~extstd.standard.bit (std standard bit)))
		(_process
			(#ALWAYS#97_0 (_architecture 0 0 97 (_process 
				(_target(10)(7)(8))
				(_read)
				(_sensitivity(0)(6)(3)(5)(9))
			)))
			(#ALWAYS#354_1 (_architecture 1 0 354 (_process 
				(_target(9))
				(_read(2)(4)(10))
			)))
			(#ALWAYS#365_2 (_architecture 2 0 365 (_process 
				(_target(0)(5))
				(_read(2)(4)(7)(8))
			)))
			(#ALWAYS#380_3 (_architecture 3 0 380 (_process 
				(_target(1))
				(_read)
				(_sensitivity(9))
			)))
		)
	)
	
	
	(_defparam
	)
	(_scope
		(_unit Sreg0_NextState begin 0 98
		)
		(_unit Sreg0_CurrentState begin 0 355
		)
		(_unit Sreg0_RegOutput begin 0 366
		)
	)
	(_model . EncoderEngine 5 -1)

)
I 000048 55 2977          1080051936750 Shifter
(_unit VERILOG 6.349C.6.256 (Shifter 0 25 (Shifter 0 25 ))
	(_version v32)
	(_time 1080051935828 2004.03.23 06:25:35)
	(_source (\./src/shifter.v\ VERILOG (\./src/shifter.v\ VERILOG)))
	(_use (std(standard))(vl(verilog_logic)))
	(_base (E 3))
	(_entity
		(_time 1080051935828)
		(_use )
	)
	(_timescale 1ns 1ps)
	(_parameters    dbg   accs  )
	(_attribute nb_assign )
	(_object
		(_type (_internal ~[7:0]wire~ 0 25 (_array ~wire ((_downto (i 7) (i 0))))))
		(_port (_internal Pdata ~[7:0]wire~ 0 25 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal RVALVEHIGHr ~wire 0 25 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal data ~wire 0 25 (_architecture (_in ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal clk ~wire 0 25 (_architecture (_in ))) (_net  ) (_nonbaction) (_noforceassign))
		(_port (_internal reset ~wire 0 25 (_architecture (_in ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal RVALVELOWr ~wire 0 25 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal shift ~wire 0 25 (_architecture (_in ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_type (_internal ~[8:0]reg~ 0 47 (_array ~reg ((_downto (i 8) (i 0))))))
		(_signal (_internal Pdatar ~[8:0]reg~ 0 47 (_architecture (_uni ))) (_reg ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_subprogram
			

		)
		(_type (_external ~wire (vl verilog_logic wire)))
		(_type (_external ~reg (vl verilog_logic reg)))
		(_type (_external ~event (vl verilog_logic event)))
		(_type (_external ~wand (vl verilog_logic wand)))
		(_type (_external ~wor (vl verilog_logic wor)))
		(_type (_external ~tri1 (vl verilog_logic tri1)))
		(_type (_external ~tri0 (vl verilog_logic tri0)))
		(_type (_external ~trireg (vl verilog_logic trireg)))
		(_type (_external ~supply0 (vl verilog_logic supply0)))
		(_type (_external ~supply1 (vl verilog_logic supply1)))
		(_type (_external ~real (vl verilog_logic real)))
		(_type (_external ~realtime (vl verilog_logic realtime)))
		(_type (_external ~tri (vl verilog_logic tri)))
		(_type (_external ~triand (vl verilog_logic triand)))
		(_type (_external ~trior (vl verilog_logic trior)))
		(_type (_external ~bit (vl verilog_logic bit)))
		(_type (_external ~extstd.standard.integer (std standard integer)))
		(_type (_external ~extstd.standard.bit (std standard bit)))
		(_process
			(#ASSIGN#50_0 (_architecture 0 0 50 (_process (_simple)
				(_target(0))
				(_sensitivity(1)(7(8))(5)(7(d_7_0)))
			)))
			(#ALWAYS#52_1 (_architecture 1 0 52 (_process 
				(_target(7))
				(_read(3)(4)(6)(7(d_7_0))(2)(7))
			)))
		)
	)
	
	
	(_defparam
	)
	(_model . Shifter 3 -1)

)
I 000047 55 2065          1080051936754 DAVctl
(_unit VERILOG 6.349C.6.256 (DAVctl 0 25 (DAVctl 0 25 ))
	(_version v32)
	(_time 1080051935828 2004.03.23 06:25:35)
	(_source (\./src/DAVctl.v\ VERILOG (\./src/davctl.v\ VERILOG)))
	(_use (std(standard))(vl(verilog_logic)))
	(_base (E 2))
	(_entity
		(_time 1080051935828)
		(_use )
	)
	(_timescale 1ns 1ps)
	(_parameters    dbg   accs  )
	(_attribute )
	(_object
		(_type (_internal ~[7:0]wire~ 0 25 (_array ~wire ((_downto (i 7) (i 0))))))
		(_port (_internal Pdata ~[7:0]wire~ 0 25 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal DAVin ~wire 0 25 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal RVALVESTATr ~wire 0 25 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_subprogram
			

		)
		(_type (_external ~wire (vl verilog_logic wire)))
		(_type (_external ~reg (vl verilog_logic reg)))
		(_type (_external ~event (vl verilog_logic event)))
		(_type (_external ~wand (vl verilog_logic wand)))
		(_type (_external ~wor (vl verilog_logic wor)))
		(_type (_external ~tri1 (vl verilog_logic tri1)))
		(_type (_external ~tri0 (vl verilog_logic tri0)))
		(_type (_external ~trireg (vl verilog_logic trireg)))
		(_type (_external ~supply0 (vl verilog_logic supply0)))
		(_type (_external ~supply1 (vl verilog_logic supply1)))
		(_type (_external ~real (vl verilog_logic real)))
		(_type (_external ~realtime (vl verilog_logic realtime)))
		(_type (_external ~tri (vl verilog_logic tri)))
		(_type (_external ~triand (vl verilog_logic triand)))
		(_type (_external ~trior (vl verilog_logic trior)))
		(_type (_external ~bit (vl verilog_logic bit)))
		(_type (_external ~extstd.standard.integer (std standard integer)))
		(_type (_external ~extstd.standard.bit (std standard bit)))
		(_process
			(#ASSIGN#39_0 (_architecture 0 0 39 (_process (_simple)
				(_target(0))
				(_sensitivity(2)(1))
			)))
		)
	)
	
	
	(_defparam
	)
	(_model . DAVctl 2 -1)

)
V 000044 55 23996         1080052027375 U21
(_unit VERILOG 6.349C.6.256 (U21 0 32 (U21 0 32 ))
	(_version v32)
	(_time 1080052027078 2004.03.23 06:27:07)
	(_source (\./compile/u21.v\ VERILOG (\./compile/u21.v\ VERILOG)))
	(_use (std(standard))(vl(verilog_logic)))
	(_base (E 15))
	(_entity
		(_time 1080052027078)
		(_use )
	)
	(_timescale 1ns 1ns)
	(_parameters    dbg   accs  )
	(_attribute )
	(_object
		(_type (_internal ~vector~0 0 190 (_array ~bit ((_uto (i 0) (i 0))))))
		(_generic (_internal DANGLING_INPUT_CONSTANT ~vector~0 0 190 \1'bZ\ (_entity -1 (_constant \1'bZ\))))
		(_port (_internal AS ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Brake0 ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Brake1 ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal DIR0 ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal DIR1 ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Enc033FLG ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Enc05FLG ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Enc133FLG ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Enc15FLG ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal FLS0 ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal FLS1 ~wire 0 33 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal GP_Motor0_0 ~wire 0 33 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal GP_Motor1_0 ~wire 0 33 (_architecture (_in ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal HSI ~wire 0 33 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal Home0 ~wire 0 33 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Home033FLG ~wire 0 33 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Home05FLG ~wire 0 33 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Home1 ~wire 0 33 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Home133FLG ~wire 0 33 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Home15FLG ~wire 0 33 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal INTbus ~wire 0 34 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal LightSense ~wire 0 34 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal MHSO ~wire 0 34 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal Mclk ~wire 0 34 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal PWM1 ~wire 0 34 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PWM2 ~wire 0 34 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PhaseA_Encoder0 ~wire 0 34 (_architecture (_in ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PhaseA_Encoder1 ~wire 0 34 (_architecture (_in ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PhaseB_Encoder0 ~wire 0 34 (_architecture (_in ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PhaseB_Encoder1 ~wire 0 34 (_architecture (_in ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal RD ~wire 0 35 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal RLS0 ~wire 0 35 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal RLS1 ~wire 0 35 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Reset ~wire 0 35 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal SCLinc ~wire 0 35 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal SCLreset ~wire 0 35 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal TXI ~wire 0 35 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal WR ~wire 0 35 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_type (_internal ~[5:0]wire~ 0 35 (_array ~wire ((_downto (i 5) (i 0))))))
		(_port (_internal I2CS ~[5:0]wire~ 0 35 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Enc033ctrl ~wire 0 35 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Enc05ctrl ~wire 0 36 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Enc133ctrl ~wire 0 36 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Enc15ctrl ~wire 0 36 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal GP_Motor0_1 ~wire 0 36 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal GP_Motor1_1 ~wire 0 36 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal HSO ~wire 0 36 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal Home033ctrl ~wire 0 36 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Home05ctrl ~wire 0 36 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Home133ctrl ~wire 0 36 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Home15ctrl ~wire 0 36 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal INT ~wire 0 37 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal LED1 ~wire 0 37 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal LED2 ~wire 0 37 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal LED3 ~wire 0 37 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal LED4 ~wire 0 37 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal LED5 ~wire 0 37 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal MHSI ~wire 0 37 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal MTRpwr ~wire 0 37 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal MTRpwrn ~wire 0 37 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal MTXI ~wire 0 37 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal PAH0 ~wire 0 38 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PAH1 ~wire 0 38 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PAL0 ~wire 0 38 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PAL1 ~wire 0 38 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PBH0 ~wire 0 38 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PBH1 ~wire 0 38 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PBL0 ~wire 0 38 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PBL1 ~wire 0 38 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal TP10 ~wire 0 38 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal TP11 ~wire 0 38 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal TP12 ~wire 0 39 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal SCL ~wire 0 39 (_architecture (_inout ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_type (_internal ~[7:0]wire~ 0 39 (_array ~wire ((_downto (i 7) (i 0))))))
		(_port (_internal AD ~[7:0]wire~ 0 39 (_architecture (_inout ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal clk ~wire 0 193 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal NET1635 ~wire 0 194 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET1643 ~wire 0 195 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET1651 ~wire 0 196 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET1667 ~wire 0 197 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET1978 ~wire 0 198 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET1989 ~wire 0 199 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET2017 ~wire 0 200 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET2025 ~wire 0 201 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET2036 ~wire 0 202 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET2047 ~wire 0 203 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET2064 ~wire 0 204 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET2078 ~wire 0 205 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET2311 ~wire 0 206 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET2528 ~wire 0 207 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET2539 ~wire 0 208 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET2575 ~wire 0 209 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET3248 ~wire 0 210 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET3253 ~wire 0 211 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET3919 ~wire 0 212 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal NET3926 ~wire 0 213 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal NET5008 ~wire 0 214 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET5863 ~wire 0 215 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET615 ~wire 0 216 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal NET621 ~wire 0 217 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal NET629 ~wire 0 218 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal reset ~wire 0 219 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal BUS1564 ~[7:0]wire~ 0 220 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal BUS5075 ~[7:0]wire~ 0 221 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal outDATA ~[7:0]wire~ 0 222 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal Dangling_Input_Signal ~wire 0 225 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_subprogram
			

		)
		(_type (_external ~wire (vl verilog_logic wire)))
		(_type (_external ~reg (vl verilog_logic reg)))
		(_type (_external ~event (vl verilog_logic event)))
		(_type (_external ~wand (vl verilog_logic wand)))
		(_type (_external ~wor (vl verilog_logic wor)))
		(_type (_external ~tri1 (vl verilog_logic tri1)))
		(_type (_external ~tri0 (vl verilog_logic tri0)))
		(_type (_external ~trireg (vl verilog_logic trireg)))
		(_type (_external ~supply0 (vl verilog_logic supply0)))
		(_type (_external ~supply1 (vl verilog_logic supply1)))
		(_type (_external ~real (vl verilog_logic real)))
		(_type (_external ~realtime (vl verilog_logic realtime)))
		(_type (_external ~tri (vl verilog_logic tri)))
		(_type (_external ~triand (vl verilog_logic triand)))
		(_type (_external ~trior (vl verilog_logic trior)))
		(_type (_external ~bit (vl verilog_logic bit)))
		(_type (_external ~extstd.standard.integer (std standard integer)))
		(_type (_external ~extstd.standard.bit (std standard bit)))
		(_process
			(#ASSIGN#225_0 (_architecture 0 0 225 (_process (_simple)
				(_target(103))
			)))
			(#ASSIGN#426_1 (_architecture 1 0 426 (_process (_alias ((clk)(Mclk)))(_simple)
				(_target(73))
				(_sensitivity(23))
			)))
			(#ASSIGN#427_2 (_architecture 2 0 427 (_process (_alias ((NET3919)(SCLreset)))(_simple)
				(_target(92))
				(_sensitivity(35))
			)))
			(#ASSIGN#428_3 (_architecture 3 0 428 (_process (_alias ((NET3926)(SCLinc)))(_simple)
				(_target(93))
				(_sensitivity(34))
			)))
			(#ASSIGN#429_4 (_architecture 4 0 429 (_process (_alias ((NET615)(MHSO)))(_simple)
				(_target(96))
				(_sensitivity(22))
			)))
			(#ASSIGN#430_5 (_architecture 5 0 430 (_process (_alias ((NET621)(HSI)))(_simple)
				(_target(97))
				(_sensitivity(13))
			)))
			(#ASSIGN#431_6 (_architecture 6 0 431 (_process (_alias ((NET629)(TXI)))(_simple)
				(_target(98))
				(_sensitivity(36))
			)))
			(#ASSIGN#432_7 (_architecture 7 0 432 (_process (_alias ((reset)(Reset)))(_simple)
				(_target(99))
				(_sensitivity(33))
			)))
			(#ASSIGN#435_8 (_architecture 8 0 435 (_process (_alias ((HSO)(NET615)))(_simple)
				(_target(45))
				(_sensitivity(96))
			)))
			(#ASSIGN#436_9 (_architecture 9 0 436 (_process (_alias ((MHSI)(NET621)))(_simple)
				(_target(56))
				(_sensitivity(97))
			)))
			(#ASSIGN#437_10 (_architecture 10 0 437 (_process (_alias ((MTXI)(NET629)))(_simple)
				(_target(59))
				(_sensitivity(98))
			)))
			(#ASSIGN#438_11 (_architecture 11 0 438 (_process (_alias ((TP10)(NET3919)))(_simple)
				(_target(68))
				(_sensitivity(92))
			)))
			(#ASSIGN#439_12 (_architecture 12 0 439 (_process (_alias ((TP11)(NET3926)))(_simple)
				(_target(69))
				(_sensitivity(93))
			)))
			(#ASSIGN#440_13 (_architecture 13 0 440 (_process (_alias ((TP12)(SCL)))(_simple)
				(_target(70))
				(_sensitivity(71))
			)))
			(#INTERNAL#0_14 (_internal 14 0 0 (_process (_virtual))))
		)
	)
	
	
	(_defparam
	)
	(_scope
	)
	(_instantiation U1 0 229 (_entity .  reader)
		(_port
			((RVALVECTLw) (NET1635))
			((RVALVEHIGHr) (NET1643))
			((RVALVELOWr) (NET1651))
			((RVALVESTATr) (NET1667))
			((SSclk) (GP_Motor0_1))
			((clk) (clk))
			((data) (GP_Motor0_0))
			((outDATA) (outDATA))
			((reset) (reset))
		)
		(_strength)
	)
	(_instantiation U11 0 244 (_entity .  I2Cfix)
		(_port
			((DCORI2CCNTr) (NET2311))
			((Inc) (NET3926))
			((Mclk) (Mclk))
			((SCL) (SCL))
			((SCLint) (NET2539))
			((SCLreset) (NET3919))
			((outDATA) (outDATA))
			((SCLenable) (_open))
		)
		(_strength)
	)
	(_instantiation U12 0 257 (_entity .  U21AddDecode)
		(_port
			((ADDR) (BUS1564))
			((AS) (AS))
			((DCOR0CNTHIGHr) (NET1667))
			((DCOR0CNTLOWr) (NET1651))
			((DCOR0CNTMIDr) (NET1643))
			((DCORCONFIGr) (NET2064))
			((DCORENCCTLw) (NET1635))
			((DCORENCPWRr) (NET2036))
			((DCORENCPWRw) (NET2025))
			((DCORI2CCNTr) (NET2311))
			((DCORIEw) (NET2078))
			((DCORIFGr) (NET1978))
			((DCORIFGw) (NET1989))
			((DCORLIMITSr) (NET2047))
			((DCOROUTw) (NET2017))
			((RD) (RD))
			((WR) (WR))
			((DCOR0THRESLOWr) (_open))
			((DCOR1CNTLOWr) (_open))
			((DCOR1THRESLOWr) (_open))
			((DCOR0THRESMIDr) (_open))
			((DCOR1CNTMIDr) (_open))
			((DCOR1THRESMIDr) (_open))
			((DCOR1CNTHIGHr) (_open))
		)
		(_strength)
	)
	(_instantiation U2 0 280 (_entity .  Interface)
		(_port
			((AD) (AD))
			((ADDR) (BUS1564))
			((AS) (AS))
			((Mclk) (Mclk))
			((RD) (RD))
			((Reset) (Reset))
			((WR) (WR))
			((inDATA) (BUS5075))
			((outDATA) (outDATA))
			((ASleading) (_open))
		)
		(_strength)
	)
	(_instantiation U3 0 295 (_entity .  Interrupt)
		(_port
			((BusInt) (INTbus))
			((DCORIEw) (NET2078))
			((Homed0) (Dangling_Input_Signal))
			((Homed1) (Dangling_Input_Signal))
			((I2Cint) (NET2539))
			((INT) (INT))
			((LSwitchInt) (NET2575))
			((Mclk) (Mclk))
			((PWRint) (NET2528))
			((Reset) (Reset))
			((Thres0) (Dangling_Input_Signal))
			((Thres1) (Dangling_Input_Signal))
			((inDATA) (BUS5075))
		)
		(_strength)
	)
	(_instantiation U4 0 314 (_entity .  PWRreg)
		(_port
			((DCORENCPWRr) (NET2036))
			((DCORENCPWRw) (NET2025))
			((DCORIFGr) (NET1978))
			((DCORIFGw) (NET1989))
			((Enc033ctl) (Home15ctrl))
			((Enc033flg) (Enc033FLG))
			((Enc05ctl) (Home133ctrl))
			((Enc05flg) (Enc05FLG))
			((Enc133ctl) (Home05ctrl))
			((Enc133flg) (Enc133FLG))
			((Enc15ctl) (Home033ctrl))
			((Enc15flg) (Enc15FLG))
			((Hme033ctl) (Enc15ctrl))
			((Hme033flg) (Home033FLG))
			((Hme05ctl) (Enc133ctrl))
			((Hme05flg) (Home05FLG))
			((Hme133ctl) (Enc05ctrl))
			((Hme133flg) (Home133FLG))
			((Hme15ctl) (Enc033ctrl))
			((Hme15flg) (Home15FLG))
			((Mclk) (Mclk))
			((PWRint) (NET2528))
			((Reset) (Reset))
			((inDATA) (BUS5075))
			((outDATA) (outDATA))
		)
		(_strength)
	)
	(_instantiation U5 0 345 (_entity .  Lswitch)
		(_port
			((Brake0) (Brake0))
			((Brake1) (Brake1))
			((DCORIFGr) (NET1978))
			((DCORIFGw) (NET1989))
			((DCORLIMITSr) (NET2047))
			((DIR0) (DIR0))
			((DIR1) (DIR1))
			((FLS0) (FLS0))
			((FLS1) (FLS1))
			((Home0) (Home0))
			((Home1) (Home1))
			((LSwitchInt) (NET2575))
			((Mclk) (Mclk))
			((RLS0) (RLS0))
			((RLS1) (RLS1))
			((Reset) (Reset))
			((fBRK0) (NET3248))
			((fBRK1) (NET3253))
			((inDATA) (BUS5075))
			((outDATA) (outDATA))
		)
		(_strength)
	)
	(_instantiation U6 0 371 (_entity .  I2CAddress)
		(_port
			((DCORCONFIGr) (NET2064))
			((I2CS) (I2CS))
			((MotorIn0) (NET5863))
			((MotorIn1) (NET5008))
			((outDATA) (outDATA))
		)
		(_strength)
	)
	(_instantiation U7 0 382 (_entity .  PWMcontrol)
		(_port
			((Brake1) (Brake0))
			((Brake2) (Brake1))
			((DIR1) (DIR0))
			((DIR2) (DIR1))
			((HBRK1) (NET3248))
			((HBRK2) (NET3253))
			((PAH1) (PAH0))
			((PAH2) (PBL1))
			((PAL1) (PAL0))
			((PAL2) (PBH1))
			((PBH1) (PBH0))
			((PBH2) (PAL1))
			((PBL1) (PBL0))
			((PBL2) (PAH1))
			((PWM1) (PWM1))
			((PWM2) (PWM2))
			((fBRK1) (NET3248))
			((fBRK2) (NET3253))
		)
		(_strength)
	)
	(_instantiation U9 0 406 (_entity .  MISCouts)
		(_port
			((DCOROUTw) (NET2017))
			((LED1) (LED1))
			((LED2) (LED2))
			((LED3) (LED3))
			((LED4) (LED4))
			((LED5) (LED5))
			((LightSense) (LightSense))
			((MTRpwr) (MTRpwr))
			((MTRpwrn) (MTRpwrn))
			((Mclk) (Mclk))
			((Reset) (Reset))
			((inDATA) (BUS5075))
			((GP_Motor0_1) (_open))
			((GP_Motor1_1) (_open))
		)
		(_strength)
	)
	(_model . U21 15 -1)

)
V 000047 55 4239          1080052027379 reader
(_unit VERILOG 6.349C.6.256 (reader 0 32 (reader 0 32 ))
	(_version v32)
	(_time 1080052027078 2004.03.23 06:27:07)
	(_source (\./compile/reader.v\ VERILOG (\./compile/reader.v\ VERILOG)))
	(_use (std(standard))(vl(verilog_logic)))
	(_base (E 2))
	(_entity
		(_time 1080052027078)
		(_use )
	)
	(_timescale 1ns 1ns)
	(_parameters    dbg   accs  )
	(_attribute )
	(_object
		(_port (_internal RVALVECTLw ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal RVALVEHIGHr ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal RVALVELOWr ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal RVALVESTATr ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal data ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal SSclk ~wire 0 32 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal clk ~wire 0 32 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal reset ~wire 0 32 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_type (_internal ~[7:0]wire~ 0 32 (_array ~wire ((_downto (i 7) (i 0))))))
		(_port (_internal outDATA ~[7:0]wire~ 0 32 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET1330 ~wire 0 55 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET843 ~wire 0 56 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_type (_internal ~[5:0]wire~ 0 57 (_array ~wire ((_downto (i 5) (i 0))))))
		(_signal (_internal SSclkb ~[5:0]wire~ 0 57 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_subprogram
			

		)
		(_type (_external ~wire (vl verilog_logic wire)))
		(_type (_external ~reg (vl verilog_logic reg)))
		(_type (_external ~event (vl verilog_logic event)))
		(_type (_external ~wand (vl verilog_logic wand)))
		(_type (_external ~wor (vl verilog_logic wor)))
		(_type (_external ~tri1 (vl verilog_logic tri1)))
		(_type (_external ~tri0 (vl verilog_logic tri0)))
		(_type (_external ~trireg (vl verilog_logic trireg)))
		(_type (_external ~supply0 (vl verilog_logic supply0)))
		(_type (_external ~supply1 (vl verilog_logic supply1)))
		(_type (_external ~real (vl verilog_logic real)))
		(_type (_external ~realtime (vl verilog_logic realtime)))
		(_type (_external ~tri (vl verilog_logic tri)))
		(_type (_external ~triand (vl verilog_logic triand)))
		(_type (_external ~trior (vl verilog_logic trior)))
		(_type (_external ~bit (vl verilog_logic bit)))
		(_type (_external ~extstd.standard.integer (std standard integer)))
		(_type (_external ~extstd.standard.bit (std standard bit)))
		(_process
			(#ASSIGN#98_0 (_architecture 0 0 98 (_process (_alias ((SSclk)(SSclkb(1))))(_simple)
				(_target(5))
				(_sensitivity(11(1)))
			)))
		)
	)
	
	
	(_defparam
	)
	(_scope
	)
	(_instantiation U3 0 61 (_entity .  EncoderEngine)
		(_port
			((DAV) (NET1330))
			((SSclkb) (SSclkb))
			((clk) (clk))
			((data) (data))
			((reset) (reset))
			((shift) (NET843))
			((start) (RVALVECTLw))
		)
		(_strength)
	)
	(_instantiation U4 0 74 (_entity .  Shifter)
		(_port
			((Pdata) (outDATA))
			((RVALVEHIGHr) (RVALVEHIGHr))
			((RVALVELOWr) (RVALVELOWr))
			((clk) (clk))
			((data) (data))
			((reset) (reset))
			((shift) (NET843))
		)
		(_strength)
	)
	(_instantiation U5 0 87 (_entity .  DAVctl)
		(_port
			((DAVin) (NET1330))
			((Pdata) (outDATA))
			((RVALVESTATr) (RVALVESTATr))
		)
		(_strength)
	)
	(_model . reader 2 -1)

)
V 000047 55 3691          1080052027394 I2Cfix
(_unit VERILOG 6.349C.6.256 (I2Cfix 0 32 (I2Cfix 0 32 ))
	(_version v32)
	(_time 1080052027078 2004.03.23 06:27:07)
	(_source (\./compile/I2Cfix.v\ VERILOG (\./compile/i2cfix.v\ VERILOG)))
	(_use (std(standard))(vl(verilog_logic)))
	(_base (E 1))
	(_entity
		(_time 1080052027078)
		(_use )
	)
	(_timescale 1ns 1ns)
	(_parameters    dbg   accs  )
	(_attribute )
	(_object
		(_port (_internal DCORI2CCNTr ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Inc ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Mclk ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal SCLreset ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal SCLenable ~wire 0 32 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal SCLint ~wire 0 32 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_type (_internal ~[7:0]wire~ 0 32 (_array ~wire ((_downto (i 7) (i 0))))))
		(_port (_internal outDATA ~[7:0]wire~ 0 32 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal SCL ~wire 0 32 (_architecture (_inout ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal Incdetect ~wire 0 53 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal SCLdetect ~wire 0 54 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_subprogram
			

		)
		(_type (_external ~wire (vl verilog_logic wire)))
		(_type (_external ~reg (vl verilog_logic reg)))
		(_type (_external ~event (vl verilog_logic event)))
		(_type (_external ~wand (vl verilog_logic wand)))
		(_type (_external ~wor (vl verilog_logic wor)))
		(_type (_external ~tri1 (vl verilog_logic tri1)))
		(_type (_external ~tri0 (vl verilog_logic tri0)))
		(_type (_external ~trireg (vl verilog_logic trireg)))
		(_type (_external ~supply0 (vl verilog_logic supply0)))
		(_type (_external ~supply1 (vl verilog_logic supply1)))
		(_type (_external ~real (vl verilog_logic real)))
		(_type (_external ~realtime (vl verilog_logic realtime)))
		(_type (_external ~tri (vl verilog_logic tri)))
		(_type (_external ~triand (vl verilog_logic triand)))
		(_type (_external ~trior (vl verilog_logic trior)))
		(_type (_external ~bit (vl verilog_logic bit)))
		(_type (_external ~extstd.standard.integer (std standard integer)))
		(_type (_external ~extstd.standard.bit (std standard bit)))
	)
	
	
	(_defparam
	)
	(_scope
	)
	(_instantiation U1 0 58 (_entity .  NegDetect)
		(_port
			((Line) (Inc))
			((Mclk) (Mclk))
			((Ndetect) (Incdetect))
		)
		(_strength)
	)
	(_instantiation U2 0 67 (_entity .  NegDetect)
		(_port
			((Line) (SCL))
			((Mclk) (Mclk))
			((Ndetect) (SCLdetect))
		)
		(_strength)
	)
	(_instantiation U3 0 76 (_entity .  BitCounter)
		(_port
			((DCORI2CCNTr) (DCORI2CCNTr))
			((DriveSCL) (SCL))
			((Inc) (Inc))
			((Mclk) (Mclk))
			((NegInc) (Incdetect))
			((NegSCL) (SCLdetect))
			((SCLenable) (SCLenable))
			((SCLint) (SCLint))
			((SCLreset) (SCLreset))
			((outDATA) (outDATA))
		)
		(_strength)
	)
	(_model . I2Cfix 1 -1)

)
V 000053 55 9137          1080052027398 U21AddDecode
(_unit VERILOG 6.349C.6.256 (U21AddDecode 0 27 (U21AddDecode 0 27 ))
	(_version v32)
	(_time 1080052027078 2004.03.23 06:27:07)
	(_source (\./src/u21adddecode.v\ VERILOG (\./src/u21adddecode.v\ VERILOG)))
	(_use (std(standard))(vl(verilog_logic)))
	(_base (E 22))
	(_entity
		(_time 1080052027078)
		(_use )
	)
	(_timescale 1ps 1ps)
	(_parameters    dbg   accs  )
	(_attribute )
	(_object
		(_port (_internal DCOR0CNTLOWr ~wire 0 27 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal DCOR0THRESLOWr ~wire 0 27 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal DCOR1CNTLOWr ~wire 0 27 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal DCOR1THRESLOWr ~wire 0 27 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal DCORENCPWRr ~wire 0 27 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal WR ~wire 0 27 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal DCOR0CNTMIDr ~wire 0 27 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal DCOR0THRESMIDr ~wire 0 27 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal DCOR1CNTMIDr ~wire 0 27 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal DCOR1THRESMIDr ~wire 0 27 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal DCORLIMITSr ~wire 0 27 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal DCORIEw ~wire 0 27 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal DCORENCPWRw ~wire 0 27 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal DCOR0CNTHIGHr ~wire 0 27 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal DCORCONFIGr ~wire 0 27 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal DCORIFGr ~wire 0 27 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal DCOR1CNTHIGHr ~wire 0 27 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal AS ~wire 0 27 (_architecture (_in ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal DCORIFGw ~wire 0 27 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal RD ~wire 0 27 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal DCOROUTw ~wire 0 27 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal DCORENCCTLw ~wire 0 27 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_type (_internal ~[7:0]wire~ 0 27 (_array ~wire ((_downto (i 7) (i 0))))))
		(_port (_internal ADDR ~[7:0]wire~ 0 27 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal DCORI2CCNTr ~wire 0 27 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_type (_internal ~[7:0]reg~ 0 91 (_array ~reg ((_downto (i 7) (i 0))))))
		(_signal (_internal Select.Address ~[7:0]reg~ 0 91 (_subprogram Select (_in ))) (_reg ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal Select.Location ~[7:0]reg~ 0 92 (_subprogram Select (_in ))) (_reg ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal Select.RD ~reg 0 93 (_subprogram Select (_in ))) (_reg ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal Select.WR ~reg 0 93 (_subprogram Select (_in ))) (_reg ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal Select.RorW ~reg 0 94 (_subprogram Select (_in ))) (_reg ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal Select.Select ~reg 0 0 (_subprogram Select (_out ))) (_reg ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_subprogram
			
			(_internal Select 20 0 90 (_architecture (_function)(_target(29))
				(_read(28)(26)(27)(22)(25))
			))

		)
		(_type (_external ~wire (vl verilog_logic wire)))
		(_type (_external ~reg (vl verilog_logic reg)))
		(_type (_external ~event (vl verilog_logic event)))
		(_type (_external ~wand (vl verilog_logic wand)))
		(_type (_external ~wor (vl verilog_logic wor)))
		(_type (_external ~tri1 (vl verilog_logic tri1)))
		(_type (_external ~tri0 (vl verilog_logic tri0)))
		(_type (_external ~trireg (vl verilog_logic trireg)))
		(_type (_external ~supply0 (vl verilog_logic supply0)))
		(_type (_external ~supply1 (vl verilog_logic supply1)))
		(_type (_external ~real (vl verilog_logic real)))
		(_type (_external ~realtime (vl verilog_logic realtime)))
		(_type (_external ~tri (vl verilog_logic tri)))
		(_type (_external ~triand (vl verilog_logic triand)))
		(_type (_external ~trior (vl verilog_logic trior)))
		(_type (_external ~bit (vl verilog_logic bit)))
		(_type (_external ~extstd.standard.integer (std standard integer)))
		(_type (_external ~extstd.standard.bit (std standard bit)))
		(_process
			(#ASSIGN#102_0 (_architecture 0 0 102 (_process (_simple)
				(_target(11))
				(_sensitivity(22)(19)(5))
				(_call(0))
			)))
			(#ASSIGN#105_1 (_architecture 1 0 105 (_process (_simple)
				(_target(18))
				(_sensitivity(22)(19)(5))
				(_call(0))
			)))
			(#ASSIGN#108_2 (_architecture 2 0 108 (_process (_simple)
				(_target(15))
				(_sensitivity(22)(19)(5))
				(_call(0))
			)))
			(#ASSIGN#111_3 (_architecture 3 0 111 (_process (_simple)
				(_target(10))
				(_sensitivity(22)(19)(5))
				(_call(0))
			)))
			(#ASSIGN#114_4 (_architecture 4 0 114 (_process (_simple)
				(_target(21))
				(_sensitivity(22)(19)(5))
				(_call(0))
			)))
			(#ASSIGN#117_5 (_architecture 5 0 117 (_process (_simple)
				(_target(0))
				(_sensitivity(22)(19)(5))
				(_call(0))
			)))
			(#ASSIGN#120_6 (_architecture 6 0 120 (_process (_simple)
				(_target(6))
				(_sensitivity(22)(19)(5))
				(_call(0))
			)))
			(#ASSIGN#123_7 (_architecture 7 0 123 (_process (_simple)
				(_target(13))
				(_sensitivity(22)(19)(5))
				(_call(0))
			)))
			(#ASSIGN#126_8 (_architecture 8 0 126 (_process (_simple)
				(_target(2))
				(_sensitivity(22)(19)(5))
				(_call(0))
			)))
			(#ASSIGN#129_9 (_architecture 9 0 129 (_process (_simple)
				(_target(8))
				(_sensitivity(22)(19)(5))
				(_call(0))
			)))
			(#ASSIGN#132_10 (_architecture 10 0 132 (_process (_simple)
				(_target(16))
				(_sensitivity(22)(19)(5))
				(_call(0))
			)))
			(#ASSIGN#135_11 (_architecture 11 0 135 (_process (_simple)
				(_target(1))
				(_sensitivity(22)(19)(5))
				(_call(0))
			)))
			(#ASSIGN#138_12 (_architecture 12 0 138 (_process (_simple)
				(_target(7))
				(_sensitivity(22)(19)(5))
				(_call(0))
			)))
			(#ASSIGN#141_13 (_architecture 13 0 141 (_process (_simple)
				(_target(3))
				(_sensitivity(22)(19)(5))
				(_call(0))
			)))
			(#ASSIGN#144_14 (_architecture 14 0 144 (_process (_simple)
				(_target(9))
				(_sensitivity(22)(19)(5))
				(_call(0))
			)))
			(#ASSIGN#147_15 (_architecture 15 0 147 (_process (_simple)
				(_target(4))
				(_sensitivity(22)(19)(5))
				(_call(0))
			)))
			(#ASSIGN#150_16 (_architecture 16 0 150 (_process (_simple)
				(_target(12))
				(_sensitivity(22)(19)(5))
				(_call(0))
			)))
			(#ASSIGN#153_17 (_architecture 17 0 153 (_process (_simple)
				(_target(14))
				(_sensitivity(22)(19)(5))
				(_call(0))
			)))
			(#ASSIGN#156_18 (_architecture 18 0 156 (_process (_simple)
				(_target(20))
				(_sensitivity(22)(19)(5))
				(_call(0))
			)))
			(#ASSIGN#159_19 (_architecture 19 0 159 (_process (_simple)
				(_target(23))
				(_sensitivity(22)(19)(5))
				(_call(0))
			)))
			(#INTERNAL#0_21 (_internal 21 0 0 (_process (_virtual))))
		)
	)
	
	
	(_defparam
	)
	(_scope
		(_unit Select function 0 90
		)
	)
	(_model . U21AddDecode 22 -1)

)
V 000050 55 4827          1080052027402 Interface
(_unit VERILOG 6.349C.6.256 (Interface 0 25 (Interface 0 25 ))
	(_version v32)
	(_time 1080052027078 2004.03.23 06:27:07)
	(_source (\./src/interface.v\ VERILOG (\./src/interface.v\ VERILOG)))
	(_use (std(standard))(vl(verilog_logic)))
	(_base (E 8))
	(_entity
		(_time 1080052027078)
		(_use )
	)
	(_timescale 1ps 1ps)
	(_parameters    dbg   accs  )
	(_attribute nb_assign )
	(_object
		(_type (_internal ~[7:0]wire~ 0 25 (_array ~wire ((_downto (i 7) (i 0))))))
		(_port (_internal inDATA ~[7:0]wire~ 0 25 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal outDATA ~[7:0]wire~ 0 25 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal Reset ~wire 0 25 (_architecture (_in ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal AS ~wire 0 25 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal AD ~[7:0]wire~ 0 25 (_architecture (_inout ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal RD ~wire 0 25 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal Mclk ~wire 0 25 (_architecture (_in ))) (_net  ) (_nonbaction) (_noforceassign))
		(_port (_internal ASleading ~wire 0 25 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal WR ~wire 0 25 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal ADDR ~[7:0]wire~ 0 25 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_type (_internal ~[7:0]reg~ 0 58 (_array ~reg ((_downto (i 7) (i 0))))))
		(_signal (_internal ADDR_reg ~[7:0]reg~ 0 58 (_architecture (_uni ))) (_reg ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal AutoInc ~reg 0 66 (_architecture (_uni ))) (_reg ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal ASedge ~reg 0 68 (_architecture (_uni ))) (_reg ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal WRRDedge ~reg 0 70 (_architecture (_uni ))) (_reg ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal Enable_AD ~wire 0 74 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal ADDR_in_Range ~wire 0 75 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_subprogram
			

		)
		(_type (_external ~wire (vl verilog_logic wire)))
		(_type (_external ~reg (vl verilog_logic reg)))
		(_type (_external ~event (vl verilog_logic event)))
		(_type (_external ~wand (vl verilog_logic wand)))
		(_type (_external ~wor (vl verilog_logic wor)))
		(_type (_external ~tri1 (vl verilog_logic tri1)))
		(_type (_external ~tri0 (vl verilog_logic tri0)))
		(_type (_external ~trireg (vl verilog_logic trireg)))
		(_type (_external ~supply0 (vl verilog_logic supply0)))
		(_type (_external ~supply1 (vl verilog_logic supply1)))
		(_type (_external ~real (vl verilog_logic real)))
		(_type (_external ~realtime (vl verilog_logic realtime)))
		(_type (_external ~tri (vl verilog_logic tri)))
		(_type (_external ~triand (vl verilog_logic triand)))
		(_type (_external ~trior (vl verilog_logic trior)))
		(_type (_external ~bit (vl verilog_logic bit)))
		(_type (_external ~extstd.standard.integer (std standard integer)))
		(_type (_external ~extstd.standard.bit (std standard bit)))
		(_process
			(#ASSIGN#79_0 (_architecture 0 0 79 (_process (_alias ((ADDR)(ADDR_reg)))(_simple)
				(_target(9))
				(_sensitivity(10))
			)))
			(#ASSIGN#82_1 (_architecture 1 0 82 (_process (_alias ((Enable_AD)(WR)(RD)(ADDR_in_Range)))(_simple)
				(_target(14))
				(_sensitivity(8)(5)(15))
			)))
			(#ASSIGN#83_2 (_architecture 2 0 83 (_process (_simple)
				(_target(15))
				(_sensitivity(10))
			)))
			(#ASSIGN#84_3 (_architecture 3 0 84 (_process (_alias ((ASleading)(AS)(ASedge)))(_simple)
				(_target(7))
				(_sensitivity(3)(12))
			)))
			(#ASSIGN#91_4 (_architecture 4 0 91 (_process (_alias ((inDATA)(AD)))(_simple)
				(_target(0))
				(_sensitivity(4))
			)))
			(#ASSIGN#92_5 (_architecture 5 0 92 (_process (_simple)
				(_target(4))
				(_sensitivity(14)(1))
			)))
			(#ALWAYS#94_6 (_architecture 6 0 94 (_process 
				(_target(12)(13)(10)(11))
				(_read(6)(3)(8)(5)(2)(7)(4)(13)(11)(15)(10))
			)))
		)
	)
	
	
	(_defparam
	)
	(_model . Interface 8 -1)

)
V 000050 55 4040          1080052027406 Interrupt
(_unit VERILOG 6.349C.6.256 (Interrupt 0 25 (Interrupt 0 25 ))
	(_version v32)
	(_time 1080052027078 2004.03.23 06:27:07)
	(_source (\./src/interrupt.v\ VERILOG (\./src/interrupt.v\ VERILOG)))
	(_use (std(standard))(vl(verilog_logic)))
	(_base (E 3))
	(_entity
		(_time 1080052027078)
		(_use )
	)
	(_timescale 1ps 1ps)
	(_parameters    dbg   accs  )
	(_attribute nb_assign )
	(_object
		(_type (_internal ~[7:0]wire~ 0 25 (_array ~wire ((_downto (i 7) (i 0))))))
		(_port (_internal inDATA ~[7:0]wire~ 0 25 (_architecture (_in ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal Reset ~wire 0 25 (_architecture (_in ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal PWRint ~wire 0 25 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal BusInt ~wire 0 25 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal Thres0 ~wire 0 25 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal Mclk ~wire 0 25 (_architecture (_in ))) (_net  ) (_nonbaction) (_noforceassign))
		(_port (_internal Thres1 ~wire 0 25 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal I2Cint ~wire 0 25 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal LSwitchInt ~wire 0 25 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal INT ~wire 0 25 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal DCORIEw ~wire 0 25 (_architecture (_in ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal Homed0 ~wire 0 25 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal Homed1 ~wire 0 25 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_type (_internal ~[7:0]reg~ 0 59 (_array ~reg ((_downto (i 7) (i 0))))))
		(_signal (_internal DCORIE ~[7:0]reg~ 0 59 (_architecture (_uni ))) (_reg ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_subprogram
			

		)
		(_type (_external ~wire (vl verilog_logic wire)))
		(_type (_external ~reg (vl verilog_logic reg)))
		(_type (_external ~event (vl verilog_logic event)))
		(_type (_external ~wand (vl verilog_logic wand)))
		(_type (_external ~wor (vl verilog_logic wor)))
		(_type (_external ~tri1 (vl verilog_logic tri1)))
		(_type (_external ~tri0 (vl verilog_logic tri0)))
		(_type (_external ~trireg (vl verilog_logic trireg)))
		(_type (_external ~supply0 (vl verilog_logic supply0)))
		(_type (_external ~supply1 (vl verilog_logic supply1)))
		(_type (_external ~real (vl verilog_logic real)))
		(_type (_external ~realtime (vl verilog_logic realtime)))
		(_type (_external ~tri (vl verilog_logic tri)))
		(_type (_external ~triand (vl verilog_logic triand)))
		(_type (_external ~trior (vl verilog_logic trior)))
		(_type (_external ~bit (vl verilog_logic bit)))
		(_type (_external ~extstd.standard.integer (std standard integer)))
		(_type (_external ~extstd.standard.bit (std standard bit)))
		(_process
			(#ASSIGN#68_0 (_architecture 0 0 68 (_process (_alias ((INT)(DCORIE(7))(I2Cint)(DCORIE(6))(Thres1)(DCORIE(5))(Thres0)(DCORIE(4))(LSwitchInt)(DCORIE(3))(Homed1)(DCORIE(2))(Homed0)(DCORIE(1))(PWRint)(DCORIE(0))(BusInt)))(_simple)
				(_target(9))
				(_sensitivity(13(7))(7)(13(6))(6)(13(5))(4)(13(4))(8)(13(3))(12)(13(2))(11)(13(1))(2)(13(0))(3))
			)))
			(#ALWAYS#70_1 (_architecture 1 0 70 (_process 
				(_target(13))
				(_read(5)(1)(10)(0))
			)))
		)
	)
	
	
	(_defparam
	)
	(_model . Interrupt 3 -1)

)
V 000047 55 7698          1080052027410 PWRreg
(_unit VERILOG 6.349C.6.256 (PWRreg 0 25 (PWRreg 0 25 ))
	(_version v32)
	(_time 1080052027078 2004.03.23 06:27:07)
	(_source (\./src/PWRreg.v\ VERILOG (\./src/pwrreg.v\ VERILOG)))
	(_use (std(standard))(vl(verilog_logic)))
	(_base (E 14))
	(_entity
		(_time 1080052027078)
		(_use )
	)
	(_timescale 1ps 1ps)
	(_parameters    dbg   accs  )
	(_attribute nb_assign )
	(_object
		(_port (_internal Hme05ctl ~wire 0 25 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal Hme15ctl ~wire 0 25 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal Reset ~wire 0 25 (_architecture (_in ))) (_net  ) (_nonbaction) (_noforceassign))
		(_port (_internal PWRint ~wire 0 25 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal Enc033flg ~wire 0 25 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal Enc133flg ~wire 0 25 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal Mclk ~wire 0 25 (_architecture (_in ))) (_net  ) (_nonbaction) (_noforceassign))
		(_port (_internal Hme033flg ~wire 0 25 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal DCORENCPWRr ~wire 0 25 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal Hme133flg ~wire 0 25 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal DCORENCPWRw ~wire 0 25 (_architecture (_in ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal Enc033ctl ~wire 0 25 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal Enc133ctl ~wire 0 25 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal DCORIFGr ~wire 0 25 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_type (_internal ~[7:0]wire~ 0 25 (_array ~wire ((_downto (i 7) (i 0))))))
		(_port (_internal inDATA ~[7:0]wire~ 0 25 (_architecture (_in ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal outDATA ~[7:0]wire~ 0 25 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal Hme033ctl ~wire 0 25 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal Hme133ctl ~wire 0 25 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal Enc05flg ~wire 0 25 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal Enc15flg ~wire 0 25 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal DCORIFGw ~wire 0 25 (_architecture (_in ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal Hme05flg ~wire 0 25 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal Hme15flg ~wire 0 25 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal Enc05ctl ~wire 0 25 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal Enc15ctl ~wire 0 25 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_type (_internal ~[7:0]reg~ 0 82 (_array ~reg ((_downto (i 7) (i 0))))))
		(_signal (_internal ctrlr ~[7:0]reg~ 0 82 (_architecture (_uni ))) (_reg ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal Flgreg ~[7:0]reg~ 0 83 (_architecture (_uni ))) (_reg ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal DCORIFG ~reg 0 84 (_architecture (_uni ))) (_reg ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal orFLGs ~wire 0 85 (_architecture (_uni ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_subprogram
			

		)
		(_type (_external ~wire (vl verilog_logic wire)))
		(_type (_external ~reg (vl verilog_logic reg)))
		(_type (_external ~event (vl verilog_logic event)))
		(_type (_external ~wand (vl verilog_logic wand)))
		(_type (_external ~wor (vl verilog_logic wor)))
		(_type (_external ~tri1 (vl verilog_logic tri1)))
		(_type (_external ~tri0 (vl verilog_logic tri0)))
		(_type (_external ~trireg (vl verilog_logic trireg)))
		(_type (_external ~supply0 (vl verilog_logic supply0)))
		(_type (_external ~supply1 (vl verilog_logic supply1)))
		(_type (_external ~real (vl verilog_logic real)))
		(_type (_external ~realtime (vl verilog_logic realtime)))
		(_type (_external ~tri (vl verilog_logic tri)))
		(_type (_external ~triand (vl verilog_logic triand)))
		(_type (_external ~trior (vl verilog_logic trior)))
		(_type (_external ~bit (vl verilog_logic bit)))
		(_type (_external ~extstd.standard.integer (std standard integer)))
		(_type (_external ~extstd.standard.bit (std standard bit)))
		(_process
			(#ASSIGN#88_0 (_architecture 0 0 88 (_process (_simple)
				(_target(15))
				(_sensitivity(8)(27)(26)(19)(5)(22)(9)(18)(4)(21)(7)(13))
			)))
			(#ASSIGN#89_1 (_architecture 1 0 89 (_process (_alias ((PWRint)(DCORIFG)))(_simple)
				(_target(3))
				(_sensitivity(27))
			)))
			(#ASSIGN#90_2 (_architecture 2 0 90 (_process (_alias ((orFLGs)(Enc15flg)(Enc133flg)(Hme15flg)(Hme133flg)(Enc05flg)(Enc033flg)(Hme05flg)(Hme033flg)))(_simple)
				(_target(28))
				(_sensitivity(19)(5)(22)(9)(18)(4)(21)(7))
			)))
			(#ASSIGN#92_3 (_architecture 3 0 92 (_process (_alias ((Enc15ctl)(ctrlr(7))))(_simple)
				(_target(24))
				(_sensitivity(25(7)))
			)))
			(#ASSIGN#93_4 (_architecture 4 0 93 (_process (_alias ((Enc133ctl)(ctrlr(6))))(_simple)
				(_target(12))
				(_sensitivity(25(6)))
			)))
			(#ASSIGN#94_5 (_architecture 5 0 94 (_process (_alias ((Hme15ctl)(ctrlr(5))))(_simple)
				(_target(1))
				(_sensitivity(25(5)))
			)))
			(#ASSIGN#95_6 (_architecture 6 0 95 (_process (_alias ((Hme133ctl)(ctrlr(4))))(_simple)
				(_target(17))
				(_sensitivity(25(4)))
			)))
			(#ASSIGN#96_7 (_architecture 7 0 96 (_process (_alias ((Enc05ctl)(ctrlr(3))))(_simple)
				(_target(23))
				(_sensitivity(25(3)))
			)))
			(#ASSIGN#97_8 (_architecture 8 0 97 (_process (_alias ((Enc033ctl)(ctrlr(2))))(_simple)
				(_target(11))
				(_sensitivity(25(2)))
			)))
			(#ASSIGN#98_9 (_architecture 9 0 98 (_process (_alias ((Hme05ctl)(ctrlr(1))))(_simple)
				(_target(0))
				(_sensitivity(25(1)))
			)))
			(#ASSIGN#99_10 (_architecture 10 0 99 (_process (_alias ((Hme033ctl)(ctrlr(0))))(_simple)
				(_target(16))
				(_sensitivity(25(0)))
			)))
			(#ALWAYS#101_11 (_architecture 11 0 101 (_process 
				(_target(27)(26))
				(_read(6)(2)(20)(14(1))(28)(27)(19)(5)(22)(9)(18)(4)(21)(7))
			)))
			(#ALWAYS#112_12 (_architecture 12 0 112 (_process 
				(_target(25))
				(_read(6)(2)(10)(14))
			)))
		)
	)
	
	
	(_defparam
	)
	(_model . PWRreg 14 -1)

)
V 000048 55 6214          1080052027414 Lswitch
(_unit VERILOG 6.349C.6.256 (Lswitch 0 25 (Lswitch 0 25 ))
	(_version v32)
	(_time 1080052027078 2004.03.23 06:27:07)
	(_source (\./src/lswitch.v\ VERILOG (\./src/lswitch.v\ VERILOG)))
	(_use (std(standard))(vl(verilog_logic)))
	(_base (E 9))
	(_entity
		(_time 1080052027078)
		(_use )
	)
	(_timescale 1ps 1ps)
	(_parameters    dbg   accs  )
	(_attribute nb_assign )
	(_object
		(_port (_internal DCORIFGr ~wire 0 25 (_architecture (_in ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal DIR1 ~wire 0 25 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_type (_internal ~[7:0]wire~ 0 25 (_array ~wire ((_downto (i 7) (i 0))))))
		(_port (_internal inDATA ~[7:0]wire~ 0 25 (_architecture (_in ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal RLS0 ~wire 0 25 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal outDATA ~[7:0]wire~ 0 25 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal RLS1 ~wire 0 25 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal Reset ~wire 0 25 (_architecture (_in ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal fBRK0 ~wire 0 25 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal DCORIFGw ~wire 0 25 (_architecture (_in ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal Brake0 ~wire 0 25 (_architecture (_in ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal FLS0 ~wire 0 25 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal fBRK1 ~wire 0 25 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal Brake1 ~wire 0 25 (_architecture (_in ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal FLS1 ~wire 0 25 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal Mclk ~wire 0 25 (_architecture (_in ))) (_net  ) (_nonbaction) (_noforceassign))
		(_port (_internal LSwitchInt ~wire 0 25 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal Home0 ~wire 0 25 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal Home1 ~wire 0 25 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal DCORLIMITSr ~wire 0 25 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal DIR0 ~wire 0 25 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal DCORIFG ~reg 0 73 (_architecture (_uni ))) (_reg ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal fBRK0r ~reg 0 74 (_architecture (_uni ))) (_reg ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal fBRK1r ~reg 0 74 (_architecture (_uni ))) (_reg ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal trip0 ~wire 0 75 (_architecture (_uni ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal trip1 ~wire 0 75 (_architecture (_uni ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_subprogram
			

		)
		(_type (_external ~wire (vl verilog_logic wire)))
		(_type (_external ~reg (vl verilog_logic reg)))
		(_type (_external ~event (vl verilog_logic event)))
		(_type (_external ~wand (vl verilog_logic wand)))
		(_type (_external ~wor (vl verilog_logic wor)))
		(_type (_external ~tri1 (vl verilog_logic tri1)))
		(_type (_external ~tri0 (vl verilog_logic tri0)))
		(_type (_external ~trireg (vl verilog_logic trireg)))
		(_type (_external ~supply0 (vl verilog_logic supply0)))
		(_type (_external ~supply1 (vl verilog_logic supply1)))
		(_type (_external ~real (vl verilog_logic real)))
		(_type (_external ~realtime (vl verilog_logic realtime)))
		(_type (_external ~tri (vl verilog_logic tri)))
		(_type (_external ~triand (vl verilog_logic triand)))
		(_type (_external ~trior (vl verilog_logic trior)))
		(_type (_external ~bit (vl verilog_logic bit)))
		(_type (_external ~extstd.standard.integer (std standard integer)))
		(_type (_external ~extstd.standard.bit (std standard bit)))
		(_process
			(#ASSIGN#77_0 (_architecture 0 0 77 (_process (_simple)
				(_target(4))
				(_sensitivity(18)(22)(17)(13)(5)(21)(16)(10)(3))
			)))
			(#ASSIGN#79_1 (_architecture 1 0 79 (_process (_alias ((trip1)(DIR1)(FLS1)(DIR1)(RLS1)))(_simple)
				(_target(24))
				(_sensitivity(1)(13)(5))
			)))
			(#ASSIGN#80_2 (_architecture 2 0 80 (_process (_alias ((trip0)(DIR0)(FLS0)(DIR0)(RLS0)))(_simple)
				(_target(23))
				(_sensitivity(19)(10)(3))
			)))
			(#ASSIGN#82_3 (_architecture 3 0 82 (_process (_alias ((fBRK1)(fBRK1r)))(_simple)
				(_target(11))
				(_sensitivity(22))
			)))
			(#ASSIGN#83_4 (_architecture 4 0 83 (_process (_alias ((fBRK0)(fBRK0r)))(_simple)
				(_target(7))
				(_sensitivity(21))
			)))
			(#ASSIGN#85_5 (_architecture 5 0 85 (_process (_alias ((LSwitchInt)(DCORIFG)))(_simple)
				(_target(15))
				(_sensitivity(20))
			)))
			(#ALWAYS#87_6 (_architecture 6 0 87 (_process 
				(_target(20))
				(_read(14)(6)(24)(23)(8)(2(4))(20))
			)))
			(#ALWAYS#98_7 (_architecture 7 0 98 (_process 
				(_target(22)(21))
				(_read(14)(6)(24)(12)(22)(23)(9)(21))
			)))
		)
	)
	
	
	(_defparam
	)
	(_model . Lswitch 9 -1)

)
V 000051 55 3250          1080052027424 I2CAddress
(_unit VERILOG 6.349C.6.256 (I2CAddress 0 25 (I2CAddress 0 25 ))
	(_version v32)
	(_time 1080052027078 2004.03.23 06:27:07)
	(_source (\./src/i2caddress.v\ VERILOG (\./src/i2caddress.v\ VERILOG)))
	(_use (std(standard))(vl(verilog_logic)))
	(_base (E 9))
	(_entity
		(_time 1080052027078)
		(_use )
	)
	(_timescale 1ps 1ps)
	(_parameters    dbg   accs  )
	(_attribute )
	(_object
		(_port (_internal MotorIn0 ~wire 0 25 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal DCORCONFIGr ~wire 0 25 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal MotorIn1 ~wire 0 25 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_type (_internal ~[5:0]wire~ 0 25 (_array ~wire ((_downto (i 5) (i 0))))))
		(_port (_internal I2CS ~[5:0]wire~ 0 25 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_type (_internal ~[7:0]wire~ 0 25 (_array ~wire ((_downto (i 7) (i 0))))))
		(_port (_internal outDATA ~[7:0]wire~ 0 25 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_subprogram
			

		)
		(_type (_external ~wire (vl verilog_logic wire)))
		(_type (_external ~reg (vl verilog_logic reg)))
		(_type (_external ~event (vl verilog_logic event)))
		(_type (_external ~wand (vl verilog_logic wand)))
		(_type (_external ~wor (vl verilog_logic wor)))
		(_type (_external ~tri1 (vl verilog_logic tri1)))
		(_type (_external ~tri0 (vl verilog_logic tri0)))
		(_type (_external ~trireg (vl verilog_logic trireg)))
		(_type (_external ~supply0 (vl verilog_logic supply0)))
		(_type (_external ~supply1 (vl verilog_logic supply1)))
		(_type (_external ~real (vl verilog_logic real)))
		(_type (_external ~realtime (vl verilog_logic realtime)))
		(_type (_external ~tri (vl verilog_logic tri)))
		(_type (_external ~triand (vl verilog_logic triand)))
		(_type (_external ~trior (vl verilog_logic trior)))
		(_type (_external ~bit (vl verilog_logic bit)))
		(_type (_external ~extstd.standard.integer (std standard integer)))
		(_type (_external ~extstd.standard.bit (std standard bit)))
		(_process
			(#ASSIGN#43_0 (_architecture 0 0 43 (_process (_simple)
				(_target(4(0)))
				(_sensitivity(1)(3(0)))
			)))
			(#ASSIGN#44_1 (_architecture 1 0 44 (_process (_simple)
				(_target(4(1)))
				(_sensitivity(1)(3(1)))
			)))
			(#ASSIGN#45_2 (_architecture 2 0 45 (_process (_simple)
				(_target(4(2)))
				(_sensitivity(1)(3(2)))
			)))
			(#ASSIGN#46_3 (_architecture 3 0 46 (_process (_simple)
				(_target(4(3)))
				(_sensitivity(1)(3(3)))
			)))
			(#ASSIGN#47_4 (_architecture 4 0 47 (_process (_simple)
				(_target(4(4)))
				(_sensitivity(1)(3(4)))
			)))
			(#ASSIGN#48_5 (_architecture 5 0 48 (_process (_simple)
				(_target(4(5)))
				(_sensitivity(1)(3(5)))
			)))
			(#ASSIGN#49_6 (_architecture 6 0 49 (_process (_simple)
				(_target(4(6)))
				(_sensitivity(1)(0))
			)))
			(#ASSIGN#50_7 (_architecture 7 0 50 (_process (_simple)
				(_target(4(7)))
				(_sensitivity(1)(2))
			)))
		)
	)
	
	
	(_defparam
	)
	(_model . I2CAddress 9 -1)

)
V 000051 55 4704          1080052027438 PWMcontrol
(_unit VERILOG 6.349C.6.256 (PWMcontrol 0 32 (PWMcontrol 0 32 ))
	(_version v32)
	(_time 1080052027078 2004.03.23 06:27:07)
	(_source (\./compile/PWMcontrol.v\ VERILOG (\./compile/pwmcontrol.v\ VERILOG)))
	(_use (std(standard))(vl(verilog_logic)))
	(_base (E 1))
	(_entity
		(_time 1080052027078)
		(_use )
	)
	(_timescale 1ns 1ns)
	(_parameters    dbg   accs  )
	(_attribute )
	(_object
		(_port (_internal Brake1 ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Brake2 ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal DIR1 ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal DIR2 ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal HBRK1 ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal HBRK2 ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PWM1 ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PWM2 ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal fBRK1 ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal fBRK2 ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PAH1 ~wire 0 33 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PAH2 ~wire 0 33 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PAL1 ~wire 0 33 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PAL2 ~wire 0 33 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PBH1 ~wire 0 33 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PBH2 ~wire 0 33 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PBL1 ~wire 0 33 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PBL2 ~wire 0 33 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_subprogram
			

		)
		(_type (_external ~wire (vl verilog_logic wire)))
		(_type (_external ~reg (vl verilog_logic reg)))
		(_type (_external ~event (vl verilog_logic event)))
		(_type (_external ~wand (vl verilog_logic wand)))
		(_type (_external ~wor (vl verilog_logic wor)))
		(_type (_external ~tri1 (vl verilog_logic tri1)))
		(_type (_external ~tri0 (vl verilog_logic tri0)))
		(_type (_external ~trireg (vl verilog_logic trireg)))
		(_type (_external ~supply0 (vl verilog_logic supply0)))
		(_type (_external ~supply1 (vl verilog_logic supply1)))
		(_type (_external ~real (vl verilog_logic real)))
		(_type (_external ~realtime (vl verilog_logic realtime)))
		(_type (_external ~tri (vl verilog_logic tri)))
		(_type (_external ~triand (vl verilog_logic triand)))
		(_type (_external ~trior (vl verilog_logic trior)))
		(_type (_external ~bit (vl verilog_logic bit)))
		(_type (_external ~extstd.standard.integer (std standard integer)))
		(_type (_external ~extstd.standard.bit (std standard bit)))
	)
	
	
	(_defparam
	)
	(_scope
	)
	(_instantiation U1 0 75 (_entity .  PWMtranslator)
		(_port
			((Brake) (Brake1))
			((DIR) (DIR1))
			((HBRK) (HBRK1))
			((PAH) (PAH1))
			((PAL) (PAL1))
			((PBH) (PBH1))
			((PBL) (PBL1))
			((PWM) (PWM1))
			((fBRK) (fBRK1))
		)
		(_strength)
	)
	(_instantiation U2 0 90 (_entity .  PWMtranslator)
		(_port
			((Brake) (Brake2))
			((DIR) (DIR2))
			((HBRK) (HBRK2))
			((PAH) (PAH2))
			((PAL) (PAL2))
			((PBH) (PBH2))
			((PBL) (PBL2))
			((PWM) (PWM2))
			((fBRK) (fBRK2))
		)
		(_strength)
	)
	(_model . PWMcontrol 1 -1)

)
V 000049 55 5191          1080052027442 MISCouts
(_unit VERILOG 6.349C.6.256 (MISCouts 0 25 (MISCouts 0 25 ))
	(_version v32)
	(_time 1080052027078 2004.03.23 06:27:07)
	(_source (\./src/miscouts.v\ VERILOG (\./src/miscouts.v\ VERILOG)))
	(_use (std(standard))(vl(verilog_logic)))
	(_base (E 11))
	(_entity
		(_time 1080052027078)
		(_use )
	)
	(_timescale 1ps 1ps)
	(_parameters    dbg   accs  )
	(_attribute nb_assign )
	(_object
		(_type (_internal ~[7:0]wire~ 0 25 (_array ~wire ((_downto (i 7) (i 0))))))
		(_port (_internal inDATA ~[7:0]wire~ 0 25 (_architecture (_in ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal Reset ~wire 0 25 (_architecture (_in ))) (_net  ) (_nonbaction) (_noforceassign))
		(_port (_internal LED1 ~wire 0 25 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal LightSense ~wire 0 25 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal GP_Motor0_1 ~wire 0 25 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal LED2 ~wire 0 25 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal DCOROUTw ~wire 0 25 (_architecture (_in ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal Mclk ~wire 0 25 (_architecture (_in ))) (_net  ) (_nonbaction) (_noforceassign))
		(_port (_internal GP_Motor1_1 ~wire 0 25 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal LED3 ~wire 0 25 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal LED4 ~wire 0 25 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal MTRpwrn ~wire 0 25 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal LED5 ~wire 0 25 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal MTRpwr ~wire 0 25 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_type (_internal ~[7:0]reg~ 0 63 (_array ~reg ((_downto (i 7) (i 0))))))
		(_signal (_internal MISCr ~[7:0]reg~ 0 63 (_architecture (_uni ))) (_reg ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_subprogram
			

		)
		(_type (_external ~wire (vl verilog_logic wire)))
		(_type (_external ~reg (vl verilog_logic reg)))
		(_type (_external ~event (vl verilog_logic event)))
		(_type (_external ~wand (vl verilog_logic wand)))
		(_type (_external ~wor (vl verilog_logic wor)))
		(_type (_external ~tri1 (vl verilog_logic tri1)))
		(_type (_external ~tri0 (vl verilog_logic tri0)))
		(_type (_external ~trireg (vl verilog_logic trireg)))
		(_type (_external ~supply0 (vl verilog_logic supply0)))
		(_type (_external ~supply1 (vl verilog_logic supply1)))
		(_type (_external ~real (vl verilog_logic real)))
		(_type (_external ~realtime (vl verilog_logic realtime)))
		(_type (_external ~tri (vl verilog_logic tri)))
		(_type (_external ~triand (vl verilog_logic triand)))
		(_type (_external ~trior (vl verilog_logic trior)))
		(_type (_external ~bit (vl verilog_logic bit)))
		(_type (_external ~extstd.standard.integer (std standard integer)))
		(_type (_external ~extstd.standard.bit (std standard bit)))
		(_process
			(#ASSIGN#65_0 (_architecture 0 0 65 (_process (_alias ((LED1)(MISCr(0))(LightSense)))(_simple)
				(_target(2))
				(_sensitivity(14(0))(3))
			)))
			(#ASSIGN#66_1 (_architecture 1 0 66 (_process (_alias ((LED2)(MISCr(1))(LightSense)))(_simple)
				(_target(5))
				(_sensitivity(14(1))(3))
			)))
			(#ASSIGN#67_2 (_architecture 2 0 67 (_process (_alias ((LED3)(MISCr(2))(LightSense)))(_simple)
				(_target(9))
				(_sensitivity(14(2))(3))
			)))
			(#ASSIGN#68_3 (_architecture 3 0 68 (_process (_alias ((LED4)(MISCr(3))(LightSense)))(_simple)
				(_target(10))
				(_sensitivity(14(3))(3))
			)))
			(#ASSIGN#69_4 (_architecture 4 0 69 (_process (_alias ((LED5)(MISCr(4))(LightSense)))(_simple)
				(_target(12))
				(_sensitivity(14(4))(3))
			)))
			(#ASSIGN#70_5 (_architecture 5 0 70 (_process (_alias ((GP_Motor0_1)(MISCr(6))))(_simple)
				(_target(4))
				(_sensitivity(14(6)))
			)))
			(#ASSIGN#71_6 (_architecture 6 0 71 (_process (_alias ((GP_Motor1_1)(MISCr(7))))(_simple)
				(_target(8))
				(_sensitivity(14(7)))
			)))
			(#ASSIGN#72_7 (_architecture 7 0 72 (_process (_alias ((MTRpwr)(MISCr(5))))(_simple)
				(_target(13))
				(_sensitivity(14(5)))
			)))
			(#ASSIGN#73_8 (_architecture 8 0 73 (_process (_alias ((MTRpwrn)(MISCr(5))))(_simple)
				(_target(11))
				(_sensitivity(14(5)))
			)))
			(#ALWAYS#75_9 (_architecture 9 0 75 (_process 
				(_target(14))
				(_read(7)(1)(6)(0)(14))
			)))
		)
	)
	
	
	(_defparam
	)
	(_model . MISCouts 11 -1)

)
V 000047 55 10328         1080052027446 Servos
(_unit VERILOG 6.349C.6.256 (Servos 0 32 (Servos 0 32 ))
	(_version v32)
	(_time 1080052027078 2004.03.23 06:27:07)
	(_source (\./compile/Servos.v\ VERILOG (\./compile/servos.v\ VERILOG)))
	(_use (std(standard))(vl(verilog_logic)))
	(_base (E 2))
	(_entity
		(_time 1080052027078)
		(_use )
	)
	(_timescale 1ns 1ns)
	(_parameters    dbg   accs  )
	(_attribute )
	(_object
		(_port (_internal ASleading ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal DCOR0CNTHIGHr ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal DCOR0CNTLOWr ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal DCOR0CNTMIDr ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal DCOR0THRESLOWr ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal DCOR0THRESMIDr ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal DCOR1CNTHIGHr ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal DCOR1CNTLOWr ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal DCOR1CNTMIDr ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal DCOR1THRESLOWr ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal DCOR1THRESMIDr ~wire 0 33 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal DCORENCCTLw ~wire 0 33 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal DCORIFGr ~wire 0 33 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal DCORIFGw ~wire 0 33 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Home_Encoder0 ~wire 0 33 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Home_Encoder1 ~wire 0 33 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Mclk ~wire 0 33 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal MotorIn0 ~wire 0 33 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Motorin1 ~wire 0 33 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PhaseA_Encoder0 ~wire 0 33 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PhaseA_Encoder1 ~wire 0 34 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PhaseB_Encoder0 ~wire 0 34 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PhaseB_Encoder1 ~wire 0 34 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Reset ~wire 0 34 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_type (_internal ~[7:0]wire~ 0 34 (_array ~wire ((_downto (i 7) (i 0))))))
		(_port (_internal inDATA ~[7:0]wire~ 0 34 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Hfound0 ~wire 0 34 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Hfound1 ~wire 0 34 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Tfound0 ~wire 0 34 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Tfound1 ~wire 0 34 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal outDATA ~[7:0]wire~ 0 34 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal ce0 ~wire 0 99 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal ce1 ~wire 0 100 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET3720 ~wire 0 101 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal NET3721 ~wire 0 102 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal Sclk ~wire 0 103 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal updown0 ~wire 0 104 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal updown1 ~wire 0 105 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal Zero0 ~wire 0 106 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal Zero1 ~wire 0 107 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_type (_internal ~[23:0]wire~ 0 108 (_array ~wire ((_downto (i 23) (i 0))))))
		(_signal (_internal Channel0 ~[23:0]wire~ 0 108 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal Channel1 ~[23:0]wire~ 0 109 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_subprogram
			

		)
		(_type (_external ~wire (vl verilog_logic wire)))
		(_type (_external ~reg (vl verilog_logic reg)))
		(_type (_external ~event (vl verilog_logic event)))
		(_type (_external ~wand (vl verilog_logic wand)))
		(_type (_external ~wor (vl verilog_logic wor)))
		(_type (_external ~tri1 (vl verilog_logic tri1)))
		(_type (_external ~tri0 (vl verilog_logic tri0)))
		(_type (_external ~trireg (vl verilog_logic trireg)))
		(_type (_external ~supply0 (vl verilog_logic supply0)))
		(_type (_external ~supply1 (vl verilog_logic supply1)))
		(_type (_external ~real (vl verilog_logic real)))
		(_type (_external ~realtime (vl verilog_logic realtime)))
		(_type (_external ~tri (vl verilog_logic tri)))
		(_type (_external ~triand (vl verilog_logic triand)))
		(_type (_external ~trior (vl verilog_logic trior)))
		(_type (_external ~bit (vl verilog_logic bit)))
		(_type (_external ~extstd.standard.integer (std standard integer)))
		(_type (_external ~extstd.standard.bit (std standard bit)))
		(_process
			(#ASSIGN#214_0 (_architecture 0 0 214 (_process (_alias ((Sclk)(Mclk)))(_simple)
				(_target(34))
				(_sensitivity(16))
			)))
		)
	)
	
	
	(_defparam
	)
	(_scope
	)
	(_instantiation U1 0 113 (_entity .  Decode)
		(_port
			((Reset) (Reset))
			((Sclk) (Sclk))
			((ce) (ce0))
			((phaseA) (PhaseA_Encoder0))
			((phaseB) (PhaseB_Encoder0))
			((updown) (updown0))
		)
		(_strength)
	)
	(_instantiation U2 0 125 (_entity .  Counter)
		(_port
			((Reset) (Reset))
			((Sclk) (Sclk))
			((Zero) (Zero0))
			((ce) (ce0))
			((count) (Channel0))
			((sense) (NET3721))
			((updown) (updown0))
		)
		(_strength)
	)
	(_instantiation U3 0 138 (_entity .  Holdreg)
		(_port
			((ASleading) (ASleading))
			((DCOR0CNTHIGHr) (DCOR0CNTHIGHr))
			((DCOR0CNTLOWr) (DCOR0CNTLOWr))
			((DCOR0CNTMIDr) (DCOR0CNTMIDr))
			((DCOR1CNTHIGHr) (DCOR1CNTHIGHr))
			((DCOR1CNTLOWr) (DCOR1CNTLOWr))
			((DCOR1CNTMIDr) (DCOR1CNTMIDr))
			((Reset) (Reset))
			((Sclk) (Sclk))
			((ch0in) (Channel0))
			((ch1in) (Channel1))
			((outDATA) (outDATA))
		)
		(_strength)
	)
	(_instantiation U4 0 156 (_entity .  HomeConfig)
		(_port
			((Channel0) (Channel0(d_15_0)))
			((Channel1) (Channel1(d_15_0)))
			((DCOR0THRESLOWr) (DCOR0THRESLOWr))
			((DCOR0THRESMIDr) (DCOR0THRESMIDr))
			((DCOR1THRESLOWr) (DCOR1THRESLOWr))
			((DCOR1THRESMIDr) (DCOR1THRESMIDr))
			((DCORENCCTLw) (DCORENCCTLw))
			((DCORIFGr) (DCORIFGr))
			((DCORIFGw) (DCORIFGw))
			((Hfound0) (Hfound0))
			((Hfound1) (Hfound1))
			((Home_Encoder0) (Home_Encoder0))
			((Home_Encoder1) (Home_Encoder1))
			((MotorIn0) (MotorIn0))
			((MotorIn1) (Motorin1))
			((Reset) (Reset))
			((Sclk) (Sclk))
			((Tfound0) (Tfound0))
			((Tfound1) (Tfound1))
			((Zero0) (Zero0))
			((Zero1) (Zero1))
			((inDATA) (inDATA))
			((outDATA) (outDATA))
			((sense0) (NET3721))
			((sense1) (NET3720))
		)
		(_strength)
	)
	(_instantiation U5 0 187 (_entity .  Counter)
		(_port
			((Reset) (Reset))
			((Sclk) (Sclk))
			((Zero) (Zero1))
			((ce) (ce1))
			((count) (Channel1))
			((sense) (NET3720))
			((updown) (updown1))
		)
		(_strength)
	)
	(_instantiation U6 0 200 (_entity .  Decode)
		(_port
			((Reset) (Reset))
			((Sclk) (Sclk))
			((ce) (ce1))
			((phaseA) (PhaseA_Encoder1))
			((phaseB) (PhaseB_Encoder1))
			((updown) (updown1))
		)
		(_strength)
	)
	(_model . Servos 2 -1)

)
V 000047 55 3614          1080052027453 Decode
(_unit VERILOG 6.349C.6.256 (Decode 0 23 (Decode 0 23 ))
	(_version v32)
	(_time 1080052027078 2004.03.23 06:27:07)
	(_source (\./compile/Qdecode.v\ VERILOG (\./compile/qdecode.v\ VERILOG)))
	(_use (std(standard))(vl(verilog_logic)))
	(_base (E 5))
	(_entity
		(_time 1080052027078)
		(_use )
	)
	(_timescale 1ns 1ps)
	(_parameters    dbg   accs  )
	(_attribute nb_assign )
	(_object
		(_port (_internal Reset ~wire 0 23 (_architecture (_in ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal Sclk ~wire 0 23 (_architecture (_in ))) (_net  ) (_nonbaction) (_noforceassign))
		(_port (_internal ce ~wire 0 23 (_architecture (_inout ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal phaseA ~wire 0 23 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal phaseB ~wire 0 23 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal updown ~wire 0 23 (_architecture (_inout ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal ino_ce ~reg 0 34 (_architecture (_uni ))) (_reg ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal ino_updown ~reg 0 38 (_architecture (_uni ))) (_reg ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_type (_internal ~[3:0]reg~ 0 52 (_array ~reg ((_downto (i 3) (i 0))))))
		(_signal (_internal CurrState_Sreg0 ~[3:0]reg~ 0 52 (_architecture (_uni ))) (_reg ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal NextState_Sreg0 ~[3:0]reg~ 0 54 (_architecture (_uni ))) (_reg ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_subprogram
			

		)
		(_type (_external ~wire (vl verilog_logic wire)))
		(_type (_external ~reg (vl verilog_logic reg)))
		(_type (_external ~event (vl verilog_logic event)))
		(_type (_external ~wand (vl verilog_logic wand)))
		(_type (_external ~wor (vl verilog_logic wor)))
		(_type (_external ~tri1 (vl verilog_logic tri1)))
		(_type (_external ~tri0 (vl verilog_logic tri0)))
		(_type (_external ~trireg (vl verilog_logic trireg)))
		(_type (_external ~supply0 (vl verilog_logic supply0)))
		(_type (_external ~supply1 (vl verilog_logic supply1)))
		(_type (_external ~real (vl verilog_logic real)))
		(_type (_external ~realtime (vl verilog_logic realtime)))
		(_type (_external ~tri (vl verilog_logic tri)))
		(_type (_external ~triand (vl verilog_logic triand)))
		(_type (_external ~trior (vl verilog_logic trior)))
		(_type (_external ~bit (vl verilog_logic bit)))
		(_type (_external ~extstd.standard.integer (std standard integer)))
		(_type (_external ~extstd.standard.bit (std standard bit)))
		(_process
			(#ASSIGN#57_0 (_architecture 0 0 57 (_process (_alias ((updown)(CurrState_Sreg0(3))))(_simple)
				(_target(5))
				(_sensitivity(8(3)))
			)))
			(#ASSIGN#58_1 (_architecture 1 0 58 (_process (_alias ((ce)(CurrState_Sreg0(2))))(_simple)
				(_target(2))
				(_sensitivity(8(2)))
			)))
			(#ALWAYS#67_2 (_architecture 2 0 67 (_process 
				(_target(9))
				(_read)
				(_sensitivity(3)(4)(8))
			)))
			(#ALWAYS#150_3 (_architecture 3 0 150 (_process 
				(_target(8))
				(_read(1)(0)(9))
			)))
		)
	)
	
	
	(_defparam
	)
	(_scope
		(_unit Sreg0_NextState begin 0 68
		)
		(_unit Sreg0_CurrentState begin 0 151
		)
	)
	(_model . Decode 5 -1)

)
V 000048 55 2998          1080052027457 Counter
(_unit VERILOG 6.349C.6.256 (Counter 0 25 (Counter 0 25 ))
	(_version v32)
	(_time 1080052027078 2004.03.23 06:27:07)
	(_source (\./src/counter.v\ VERILOG (\./src/counter.v\ VERILOG)))
	(_use (std(standard))(vl(verilog_logic)))
	(_base (E 3))
	(_entity
		(_time 1080052027078)
		(_use )
	)
	(_timescale 1ps 1ps)
	(_parameters    dbg   accs  )
	(_attribute nb_assign )
	(_object
		(_port (_internal Zero ~wire 0 25 (_architecture (_in ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal ce ~wire 0 25 (_architecture (_in ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_type (_internal ~[23:0]wire~ 0 25 (_array ~wire ((_downto (i 23) (i 0))))))
		(_port (_internal count ~[23:0]wire~ 0 25 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal Reset ~wire 0 25 (_architecture (_in ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal updown ~wire 0 25 (_architecture (_in ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal Sclk ~wire 0 25 (_architecture (_in ))) (_net  ) (_nonbaction) (_noforceassign))
		(_port (_internal sense ~wire 0 25 (_architecture (_in ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_type (_internal ~[23:0]reg~ 0 48 (_array ~reg ((_downto (i 23) (i 0))))))
		(_signal (_internal location ~[23:0]reg~ 0 48 (_architecture (_uni ))) (_reg ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_subprogram
			

		)
		(_type (_external ~wire (vl verilog_logic wire)))
		(_type (_external ~reg (vl verilog_logic reg)))
		(_type (_external ~event (vl verilog_logic event)))
		(_type (_external ~wand (vl verilog_logic wand)))
		(_type (_external ~wor (vl verilog_logic wor)))
		(_type (_external ~tri1 (vl verilog_logic tri1)))
		(_type (_external ~tri0 (vl verilog_logic tri0)))
		(_type (_external ~trireg (vl verilog_logic trireg)))
		(_type (_external ~supply0 (vl verilog_logic supply0)))
		(_type (_external ~supply1 (vl verilog_logic supply1)))
		(_type (_external ~real (vl verilog_logic real)))
		(_type (_external ~realtime (vl verilog_logic realtime)))
		(_type (_external ~tri (vl verilog_logic tri)))
		(_type (_external ~triand (vl verilog_logic triand)))
		(_type (_external ~trior (vl verilog_logic trior)))
		(_type (_external ~bit (vl verilog_logic bit)))
		(_type (_external ~extstd.standard.integer (std standard integer)))
		(_type (_external ~extstd.standard.bit (std standard bit)))
		(_process
			(#ASSIGN#49_0 (_architecture 0 0 49 (_process (_alias ((count)(location)))(_simple)
				(_target(2))
				(_sensitivity(7))
			)))
			(#ALWAYS#51_1 (_architecture 1 0 51 (_process 
				(_target(7))
				(_read(5)(3)(0)(1)(4)(6)(7))
			)))
		)
	)
	
	
	(_defparam
	)
	(_model . Counter 3 -1)

)
V 000048 55 4486          1080052027469 Holdreg
(_unit VERILOG 6.349C.6.256 (Holdreg 0 25 (Holdreg 0 25 ))
	(_version v32)
	(_time 1080052027078 2004.03.23 06:27:07)
	(_source (\./src/holdreg.v\ VERILOG (\./src/holdreg.v\ VERILOG)))
	(_use (std(standard))(vl(verilog_logic)))
	(_base (E 4))
	(_entity
		(_time 1080052027078)
		(_use )
	)
	(_timescale 1ps 1ps)
	(_parameters    dbg   accs  )
	(_attribute nb_assign )
	(_object
		(_port (_internal DCOR1CNTHIGHr ~wire 0 25 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal DCOR0CNTLOWr ~wire 0 25 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_type (_internal ~[7:0]wire~ 0 25 (_array ~wire ((_downto (i 7) (i 0))))))
		(_port (_internal outDATA ~[7:0]wire~ 0 25 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal DCOR1CNTLOWr ~wire 0 25 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_type (_internal ~[23:0]wire~ 0 25 (_array ~wire ((_downto (i 23) (i 0))))))
		(_port (_internal ch0in ~[23:0]wire~ 0 25 (_architecture (_in ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal ch1in ~[23:0]wire~ 0 25 (_architecture (_in ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal Reset ~wire 0 25 (_architecture (_in ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal ASleading ~wire 0 25 (_architecture (_in ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal DCOR0CNTMIDr ~wire 0 25 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal DCOR1CNTMIDr ~wire 0 25 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal Sclk ~wire 0 25 (_architecture (_in ))) (_net  ) (_nonbaction) (_noforceassign))
		(_port (_internal DCOR0CNTHIGHr ~wire 0 25 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal RDedge ~reg 0 73 (_architecture (_uni ))) (_reg ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_type (_internal ~[23:0]reg~ 0 75 (_array ~reg ((_downto (i 23) (i 0))))))
		(_signal (_internal holdingreg0 ~[23:0]reg~ 0 75 (_architecture (_uni ))) (_reg ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal holdingreg1 ~[23:0]reg~ 0 75 (_architecture (_uni ))) (_reg ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal interDATA ~[7:0]wire~ 0 76 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_subprogram
			

		)
		(_type (_external ~wire (vl verilog_logic wire)))
		(_type (_external ~reg (vl verilog_logic reg)))
		(_type (_external ~event (vl verilog_logic event)))
		(_type (_external ~wand (vl verilog_logic wand)))
		(_type (_external ~wor (vl verilog_logic wor)))
		(_type (_external ~tri1 (vl verilog_logic tri1)))
		(_type (_external ~tri0 (vl verilog_logic tri0)))
		(_type (_external ~trireg (vl verilog_logic trireg)))
		(_type (_external ~supply0 (vl verilog_logic supply0)))
		(_type (_external ~supply1 (vl verilog_logic supply1)))
		(_type (_external ~real (vl verilog_logic real)))
		(_type (_external ~realtime (vl verilog_logic realtime)))
		(_type (_external ~tri (vl verilog_logic tri)))
		(_type (_external ~triand (vl verilog_logic triand)))
		(_type (_external ~trior (vl verilog_logic trior)))
		(_type (_external ~bit (vl verilog_logic bit)))
		(_type (_external ~extstd.standard.integer (std standard integer)))
		(_type (_external ~extstd.standard.bit (std standard bit)))
		(_process
			(#ASSIGN#91_0 (_architecture 0 0 91 (_process (_simple)
				(_target(15))
				(_sensitivity(1)(13(d_7_0))(3)(14(d_7_0))(8)(13(d_15_8))(9)(14(d_15_8))(11)(13(d_23_16))(0)(14(d_23_16)))
			)))
			(#ASSIGN#93_1 (_architecture 1 0 93 (_process (_alias ((outDATA)(interDATA)))(_simple)
				(_target(2))
				(_sensitivity(15))
			)))
			(#ALWAYS#95_2 (_architecture 2 0 95 (_process 
				(_target(12)(13)(14))
				(_read(10)(1)(3)(6)(7)(4)(5))
			)))
		)
	)
	
	
	(_defparam
	)
	(_model . Holdreg 4 -1)

)
V 000051 55 10303         1080052027473 HomeConfig
(_unit VERILOG 6.349C.6.256 (HomeConfig 0 25 (HomeConfig 0 25 ))
	(_version v32)
	(_time 1080052027078 2004.03.23 06:27:07)
	(_source (\./src/homeconfig.v\ VERILOG (\./src/homeconfig.v\ VERILOG)))
	(_use (std(standard))(vl(verilog_logic)))
	(_base (E 11))
	(_entity
		(_time 1080052027078)
		(_use )
	)
	(_timescale 1ps 1ps)
	(_parameters    dbg   accs  )
	(_attribute nb_assign )
	(_object
		(_port (_internal Tfound0 ~wire 0 25 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal Tfound1 ~wire 0 25 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal DCOR0THRESLOWr ~wire 0 25 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal DCOR1THRESLOWr ~wire 0 25 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal Reset ~wire 0 25 (_architecture (_in ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_type (_internal ~[15:0]wire~ 0 25 (_array ~wire ((_downto (i 15) (i 0))))))
		(_port (_internal Channel0 ~[15:0]wire~ 0 25 (_architecture (_in ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal Channel1 ~[15:0]wire~ 0 25 (_architecture (_in ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal DCOR0THRESMIDr ~wire 0 25 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal DCOR1THRESMIDr ~wire 0 25 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal Sclk ~wire 0 25 (_architecture (_in ))) (_net  ) (_nonbaction) (_noforceassign))
		(_port (_internal sense0 ~wire 0 25 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal sense1 ~wire 0 25 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal DCORIFGr ~wire 0 25 (_architecture (_in ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Zero0 ~wire 0 25 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_type (_internal ~[7:0]wire~ 0 25 (_array ~wire ((_downto (i 7) (i 0))))))
		(_port (_internal inDATA ~[7:0]wire~ 0 25 (_architecture (_in ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal Zero1 ~wire 0 25 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal outDATA ~[7:0]wire~ 0 25 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal Hfound0 ~wire 0 25 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal Hfound1 ~wire 0 25 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal DCORIFGw ~wire 0 25 (_architecture (_in ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal MotorIn0 ~wire 0 25 (_architecture (_in ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal Home_Encoder0 ~wire 0 25 (_architecture (_in ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal DCORENCCTLw ~wire 0 25 (_architecture (_in ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal MotorIn1 ~wire 0 25 (_architecture (_in ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal Home_Encoder1 ~wire 0 25 (_architecture (_in ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal RF1r ~reg 0 84 (_architecture (_uni ))) (_reg ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal E1r ~reg 0 86 (_architecture (_uni ))) (_reg ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal RF0r ~reg 0 88 (_architecture (_uni ))) (_reg ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal E0r ~reg 0 90 (_architecture (_uni ))) (_reg ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal LatchEdge0r ~reg 0 92 (_architecture (_uni ))) (_reg ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal LatchEdge1r ~reg 0 93 (_architecture (_uni ))) (_reg ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal sense0r ~reg 0 95 (_architecture (_uni ))) (_reg ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal sense1r ~reg 0 96 (_architecture (_uni ))) (_reg ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal HE0stater ~reg 0 99 (_architecture (_uni ))) (_reg ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal HE0statelastr ~reg 0 100 (_architecture (_uni ))) (_reg ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal HE1stater ~reg 0 101 (_architecture (_uni ))) (_reg ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal HE1statelastr ~reg 0 102 (_architecture (_uni ))) (_reg ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal Hfound0r ~reg 0 105 (_architecture (_uni ))) (_reg ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal Hfound1r ~reg 0 106 (_architecture (_uni ))) (_reg ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal Zero0r ~reg 0 108 (_architecture (_uni ))) (_reg ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal Zero1r ~reg 0 109 (_architecture (_uni ))) (_reg ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal Tfound0r ~reg 0 112 (_architecture (_uni ))) (_reg ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal Tfound1r ~reg 0 113 (_architecture (_uni ))) (_reg ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_type (_internal ~[15:0]reg~ 0 116 (_array ~reg ((_downto (i 15) (i 0))))))
		(_signal (_internal Latch0r ~[15:0]reg~ 0 116 (_architecture (_uni ))) (_reg ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal Latch1r ~[15:0]reg~ 0 117 (_architecture (_uni ))) (_reg ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal InEdge0r ~reg 0 120 (_architecture (_uni ))) (_reg ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal InEdge1r ~reg 0 121 (_architecture (_uni ))) (_reg ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_subprogram
			

		)
		(_type (_external ~wire (vl verilog_logic wire)))
		(_type (_external ~reg (vl verilog_logic reg)))
		(_type (_external ~event (vl verilog_logic event)))
		(_type (_external ~wand (vl verilog_logic wand)))
		(_type (_external ~wor (vl verilog_logic wor)))
		(_type (_external ~tri1 (vl verilog_logic tri1)))
		(_type (_external ~tri0 (vl verilog_logic tri0)))
		(_type (_external ~trireg (vl verilog_logic trireg)))
		(_type (_external ~supply0 (vl verilog_logic supply0)))
		(_type (_external ~supply1 (vl verilog_logic supply1)))
		(_type (_external ~real (vl verilog_logic real)))
		(_type (_external ~realtime (vl verilog_logic realtime)))
		(_type (_external ~tri (vl verilog_logic tri)))
		(_type (_external ~triand (vl verilog_logic triand)))
		(_type (_external ~trior (vl verilog_logic trior)))
		(_type (_external ~bit (vl verilog_logic bit)))
		(_type (_external ~extstd.standard.integer (std standard integer)))
		(_type (_external ~extstd.standard.bit (std standard bit)))
		(_process
			(#ASSIGN#127_0 (_architecture 0 0 127 (_process (_alias ((Zero0)(Zero0r)))(_simple)
				(_target(13))
				(_sensitivity(39))
			)))
			(#ASSIGN#128_1 (_architecture 1 0 128 (_process (_alias ((Zero1)(Zero1r)))(_simple)
				(_target(15))
				(_sensitivity(40))
			)))
			(#ASSIGN#132_2 (_architecture 2 0 132 (_process (_alias ((sense0)(sense0r)))(_simple)
				(_target(10))
				(_sensitivity(31))
			)))
			(#ASSIGN#133_3 (_architecture 3 0 133 (_process (_alias ((sense1)(sense1r)))(_simple)
				(_target(11))
				(_sensitivity(32))
			)))
			(#ASSIGN#135_4 (_architecture 4 0 135 (_process (_alias ((Hfound1)(Hfound1r)))(_simple)
				(_target(18))
				(_sensitivity(38))
			)))
			(#ASSIGN#136_5 (_architecture 5 0 136 (_process (_alias ((Hfound0)(Hfound0r)))(_simple)
				(_target(17))
				(_sensitivity(37))
			)))
			(#ASSIGN#137_6 (_architecture 6 0 137 (_process (_alias ((Tfound0)(Tfound0r)))(_simple)
				(_target(0))
				(_sensitivity(41))
			)))
			(#ASSIGN#138_7 (_architecture 7 0 138 (_process (_alias ((Tfound1)(Tfound1r)))(_simple)
				(_target(1))
				(_sensitivity(42))
			)))
			(#ASSIGN#145_8 (_architecture 8 0 145 (_process (_simple)
				(_target(16))
				(_sensitivity(2)(43(d_7_0))(7)(43(d_15_8))(3)(44(d_7_0))(8)(44(d_15_8)))
			)))
			(#ALWAYS#147_9 (_architecture 9 0 147 (_process 
				(_target(33)(34)(35)(36)(45)(46)(32)(30)(26)(25)(31)(29)(28)(27)(43)(44)(42)(41)(38)(37)(39)(40))
				(_read(9)(21)(33)(24)(35)(20)(23)(4)(22)(14)(19)(14(d_6_5))(14(d_3_2))(27)(34)(17)(28)(37)(26)(25)(36)(18)(38)(0)(45)(29)(5)(41)(43)(1)(46)(30)(6)(42))
			)))
		)
	)
	
	
	(_defparam
	)
	(_model . HomeConfig 11 -1)

)
V 000054 55 3632          1080052027477 PWMtranslator
(_unit VERILOG 6.349C.6.256 (PWMtranslator 0 27 (PWMtranslator 0 27 ))
	(_version v32)
	(_time 1080052027078 2004.03.23 06:27:07)
	(_source (\./src/PWMtranslator.v\ VERILOG (\./src/pwmtranslator.v\ VERILOG)))
	(_use (std(standard))(vl(verilog_logic)))
	(_base (E 6))
	(_entity
		(_time 1080052027078)
		(_use )
	)
	(_timescale 1ps 1ps)
	(_parameters    dbg   accs  )
	(_attribute )
	(_object
		(_port (_internal PWM ~wire 0 27 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal fBRK ~wire 0 27 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal Brake ~wire 0 27 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal HBRK ~wire 0 27 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal PAH ~wire 0 27 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal PBH ~wire 0 27 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal PAL ~wire 0 27 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal PBL ~wire 0 27 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal DIR ~wire 0 27 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal BRK ~wire 0 55 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_subprogram
			

		)
		(_type (_external ~wire (vl verilog_logic wire)))
		(_type (_external ~reg (vl verilog_logic reg)))
		(_type (_external ~event (vl verilog_logic event)))
		(_type (_external ~wand (vl verilog_logic wand)))
		(_type (_external ~wor (vl verilog_logic wor)))
		(_type (_external ~tri1 (vl verilog_logic tri1)))
		(_type (_external ~tri0 (vl verilog_logic tri0)))
		(_type (_external ~trireg (vl verilog_logic trireg)))
		(_type (_external ~supply0 (vl verilog_logic supply0)))
		(_type (_external ~supply1 (vl verilog_logic supply1)))
		(_type (_external ~real (vl verilog_logic real)))
		(_type (_external ~realtime (vl verilog_logic realtime)))
		(_type (_external ~tri (vl verilog_logic tri)))
		(_type (_external ~triand (vl verilog_logic triand)))
		(_type (_external ~trior (vl verilog_logic trior)))
		(_type (_external ~bit (vl verilog_logic bit)))
		(_type (_external ~extstd.standard.integer (std standard integer)))
		(_type (_external ~extstd.standard.bit (std standard bit)))
		(_process
			(#ASSIGN#57_0 (_architecture 0 0 57 (_process (_alias ((BRK)(fBRK)(Brake)(HBRK)))(_simple)
				(_target(9))
				(_sensitivity(1)(2)(3))
			)))
			(#ASSIGN#64_1 (_architecture 1 0 64 (_process (_alias ((PAH)(PWM)(DIR)(BRK)))(_simple)
				(_target(4))
				(_sensitivity(0)(8)(9))
			)))
			(#ASSIGN#65_2 (_architecture 2 0 65 (_process (_alias ((PAL)(PWM)(DIR)(BRK)(PWM)(DIR)(BRK)))(_simple)
				(_target(6))
				(_sensitivity(0)(8)(9))
			)))
			(#ASSIGN#66_3 (_architecture 3 0 66 (_process (_alias ((PBH)(PWM)(DIR)(BRK)))(_simple)
				(_target(5))
				(_sensitivity(0)(8)(9))
			)))
			(#ASSIGN#67_4 (_architecture 4 0 67 (_process (_alias ((PBL)(PWM)(DIR)(BRK)(PWM)(DIR)(BRK)))(_simple)
				(_target(7))
				(_sensitivity(0)(8)(9))
			)))
		)
	)
	
	
	(_defparam
	)
	(_model . PWMtranslator 6 -1)

)
V 000050 55 2394          1080052027485 NegDetect
(_unit VERILOG 6.349C.6.256 (NegDetect 0 25 (NegDetect 0 25 ))
	(_version v32)
	(_time 1080052027078 2004.03.23 06:27:07)
	(_source (\./src/negdetect.v\ VERILOG (\./src/negdetect.v\ VERILOG)))
	(_use (std(standard))(vl(verilog_logic)))
	(_base (E 3))
	(_entity
		(_time 1080052027078)
		(_use )
	)
	(_timescale 1ps 1ps)
	(_parameters    dbg   accs  )
	(_attribute nb_assign )
	(_object
		(_port (_internal Line ~wire 0 25 (_architecture (_in ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal Ndetect ~wire 0 25 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal Mclk ~wire 0 25 (_architecture (_in ))) (_net  ) (_nonbaction) (_noforceassign))
		(_signal (_internal Line_last ~reg 0 39 (_architecture (_uni ))) (_reg ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal Ndetectr ~reg 0 40 (_architecture (_uni ))) (_reg ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_subprogram
			

		)
		(_type (_external ~wire (vl verilog_logic wire)))
		(_type (_external ~reg (vl verilog_logic reg)))
		(_type (_external ~event (vl verilog_logic event)))
		(_type (_external ~wand (vl verilog_logic wand)))
		(_type (_external ~wor (vl verilog_logic wor)))
		(_type (_external ~tri1 (vl verilog_logic tri1)))
		(_type (_external ~tri0 (vl verilog_logic tri0)))
		(_type (_external ~trireg (vl verilog_logic trireg)))
		(_type (_external ~supply0 (vl verilog_logic supply0)))
		(_type (_external ~supply1 (vl verilog_logic supply1)))
		(_type (_external ~real (vl verilog_logic real)))
		(_type (_external ~realtime (vl verilog_logic realtime)))
		(_type (_external ~tri (vl verilog_logic tri)))
		(_type (_external ~triand (vl verilog_logic triand)))
		(_type (_external ~trior (vl verilog_logic trior)))
		(_type (_external ~bit (vl verilog_logic bit)))
		(_type (_external ~extstd.standard.integer (std standard integer)))
		(_type (_external ~extstd.standard.bit (std standard bit)))
		(_process
			(#ASSIGN#42_0 (_architecture 0 0 42 (_process (_alias ((Ndetect)(Ndetectr)))(_simple)
				(_target(1))
				(_sensitivity(4))
			)))
			(#ALWAYS#44_1 (_architecture 1 0 44 (_process 
				(_target(3)(4))
				(_read(2)(0)(3))
			)))
		)
	)
	
	
	(_defparam
	)
	(_model . NegDetect 3 -1)

)
V 000051 55 3750          1080052027489 BitCounter
(_unit VERILOG 6.349C.6.256 (BitCounter 0 25 (BitCounter 0 25 ))
	(_version v32)
	(_time 1080052027078 2004.03.23 06:27:07)
	(_source (\./src/bitcounter.v\ VERILOG (\./src/bitcounter.v\ VERILOG)))
	(_use (std(standard))(vl(verilog_logic)))
	(_base (E 6))
	(_entity
		(_time 1080052027078)
		(_use )
	)
	(_timescale 1ps 1ps)
	(_parameters    dbg   accs  )
	(_attribute nb_assign )
	(_object
		(_type (_internal ~[7:0]wire~ 0 25 (_array ~wire ((_downto (i 7) (i 0))))))
		(_port (_internal outDATA ~[7:0]wire~ 0 25 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal NegInc ~wire 0 25 (_architecture (_in ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal SCLreset ~wire 0 25 (_architecture (_in ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal Mclk ~wire 0 25 (_architecture (_in ))) (_net  ) (_nonbaction) (_noforceassign))
		(_port (_internal SCLenable ~wire 0 25 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal Inc ~wire 0 25 (_architecture (_in ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal DriveSCL ~wire 0 25 (_architecture (_inout ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal NegSCL ~wire 0 25 (_architecture (_in ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal DCORI2CCNTr ~wire 0 25 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal SCLint ~wire 0 25 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_type (_internal ~[5:0]reg~ 0 54 (_array ~reg ((_downto (i 5) (i 0))))))
		(_signal (_internal counterr ~[5:0]reg~ 0 54 (_architecture (_uni ))) (_reg ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_subprogram
			

		)
		(_type (_external ~wire (vl verilog_logic wire)))
		(_type (_external ~reg (vl verilog_logic reg)))
		(_type (_external ~event (vl verilog_logic event)))
		(_type (_external ~wand (vl verilog_logic wand)))
		(_type (_external ~wor (vl verilog_logic wor)))
		(_type (_external ~tri1 (vl verilog_logic tri1)))
		(_type (_external ~tri0 (vl verilog_logic tri0)))
		(_type (_external ~trireg (vl verilog_logic trireg)))
		(_type (_external ~supply0 (vl verilog_logic supply0)))
		(_type (_external ~supply1 (vl verilog_logic supply1)))
		(_type (_external ~real (vl verilog_logic real)))
		(_type (_external ~realtime (vl verilog_logic realtime)))
		(_type (_external ~tri (vl verilog_logic tri)))
		(_type (_external ~triand (vl verilog_logic triand)))
		(_type (_external ~trior (vl verilog_logic trior)))
		(_type (_external ~bit (vl verilog_logic bit)))
		(_type (_external ~extstd.standard.integer (std standard integer)))
		(_type (_external ~extstd.standard.bit (std standard bit)))
		(_process
			(#ASSIGN#56_0 (_architecture 0 0 56 (_process (_simple)
				(_target(9))
				(_sensitivity(10))
			)))
			(#ASSIGN#58_1 (_architecture 1 0 58 (_process (_simple)
				(_target(4))
				(_sensitivity(10))
			)))
			(#ASSIGN#60_2 (_architecture 2 0 60 (_process (_simple)
				(_target(6))
				(_sensitivity(4))
			)))
			(#ASSIGN#62_3 (_architecture 3 0 62 (_process (_simple)
				(_target(0))
				(_sensitivity(8)(10))
			)))
			(#ALWAYS#64_4 (_architecture 4 0 64 (_process 
				(_target(10))
				(_read(3)(2)(5)(1)(7)(10))
			)))
		)
	)
	
	
	(_defparam
	)
	(_model . BitCounter 6 -1)

)
V 000044 55 5014          1080052027500 MSP
(_unit VERILOG 6.349C.6.256 (MSP 0 25 (MSP 0 25 ))
	(_version v32)
	(_time 1080052027078 2004.03.23 06:27:07)
	(_source (\./src/msp.v\ VERILOG (\./src/msp.v\ VERILOG)))
	(_use (std(standard))(vl(verilog_logic)))
	(_base (E 7))
	(_entity
		(_time 1080052027078)
		(_use )
	)
	(_timescale 1ps 1ps)
	(_parameters    dbg   accs  )
	(_attribute )
	(_object
		(_type (_internal ~vector~0 0 52 (_array ~bit ((_uto (i 0) (i 0))))(_attribute signed)))
		(_generic (_internal Half_period ~vector~0 0 52 \500000\ (_entity -1 (_constant \500000\))))
		(_type (_internal ~vector~1 0 53 (_array ~bit ((_uto (i 0) (i 0))))(_attribute signed)))
		(_generic (_internal BITS ~vector~1 0 53 \12\ (_entity -1 (_constant \12\))))
		(_type (_internal ~vector~2 0 53 (_array ~bit ((_uto (i 0) (i 0))))(_attribute signed)))
		(_generic (_internal WORDS ~vector~2 0 53 \159\ (_entity -1 (_constant \159\))))
		(_port (_internal WR ~wire 0 25 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal AS ~wire 0 25 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_type (_internal ~[7:0]wire~ 0 25 (_array ~wire ((_downto (i 7) (i 0))))))
		(_port (_internal AD ~[7:0]wire~ 0 25 (_architecture (_inout ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal RD ~wire 0 25 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal Mclk ~wire 0 25 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal ASr ~reg 0 43 (_architecture (_uni ))) (_reg ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal WRr ~reg 0 44 (_architecture (_uni ))) (_reg ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal RDr ~reg 0 45 (_architecture (_uni ))) (_reg ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal Mclkr ~reg 0 46 (_architecture (_uni ))) (_reg ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_type (_internal ~[7:0]reg~ 0 47 (_array ~reg ((_downto (i 7) (i 0))))))
		(_signal (_internal ADr ~[7:0]reg~ 0 47 (_architecture (_uni ))) (_reg ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal busDrive ~reg 0 48 (_architecture (_uni ))) (_reg ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_type (_internal ~integer 0 50 (_array ~reg ((_downto (i 31) (i 0))))(_attribute signed)))
		(_signal (_internal J ~integer 0 50 (_architecture (_uni ))) (_reg integer) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_type (_internal ~[1:BITS]reg~[1:WORDS]~ 0 54 (_array ~reg ((_range  7)(_range  8)))))
		(_signal (_internal Vmem ~[1:BITS]reg~[1:WORDS]~ 0 54 (_architecture (_uni ))) (_reg memory) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_subprogram
			
			(_function \$readmemb\)

		)
		(_type (_external ~wire (vl verilog_logic wire)))
		(_type (_external ~reg (vl verilog_logic reg)))
		(_type (_external ~event (vl verilog_logic event)))
		(_type (_external ~wand (vl verilog_logic wand)))
		(_type (_external ~wor (vl verilog_logic wor)))
		(_type (_external ~tri1 (vl verilog_logic tri1)))
		(_type (_external ~tri0 (vl verilog_logic tri0)))
		(_type (_external ~trireg (vl verilog_logic trireg)))
		(_type (_external ~supply0 (vl verilog_logic supply0)))
		(_type (_external ~supply1 (vl verilog_logic supply1)))
		(_type (_external ~real (vl verilog_logic real)))
		(_type (_external ~realtime (vl verilog_logic realtime)))
		(_type (_external ~tri (vl verilog_logic tri)))
		(_type (_external ~triand (vl verilog_logic triand)))
		(_type (_external ~trior (vl verilog_logic trior)))
		(_type (_external ~bit (vl verilog_logic bit)))
		(_type (_external ~extstd.standard.integer (std standard integer)))
		(_type (_external ~extstd.standard.bit (std standard bit)))
		(_process
			(#ASSIGN#57_0 (_architecture 0 0 57 (_process (_alias ((AS)(ASr)))(_simple)
				(_target(1))
				(_sensitivity(5))
			)))
			(#ASSIGN#58_1 (_architecture 1 0 58 (_process (_alias ((RD)(RDr)))(_simple)
				(_target(3))
				(_sensitivity(7))
			)))
			(#ASSIGN#59_2 (_architecture 2 0 59 (_process (_alias ((WR)(WRr)))(_simple)
				(_target(0))
				(_sensitivity(6))
			)))
			(#ASSIGN#60_3 (_architecture 3 0 60 (_process (_simple)
				(_target(2))
				(_sensitivity(10)(9))
			)))
			(#ASSIGN#61_4 (_architecture 4 0 61 (_process (_alias ((Mclk)(Mclkr)))(_simple)
				(_target(4))
				(_sensitivity(8))
			)))
			(#INITIAL#63_5 (_architecture 5 0 63 (_process 
				(_target(11)(8)(5)(7)(6)(10)(9))
				(_read(12)(11))
			)))
			(#INTERNAL#0_6 (_internal 6 0 0 (_process (_virtual))))
		)
	)
	
	
	(_defparam
	)
	(_model . MSP 9 -1)

)
V 000046 55 8513          1080052027504 U4_TB
(_unit VERILOG 6.349C.6.256 (U4_TB 0 32 (U4_TB 0 32 ))
	(_version v32)
	(_time 1080052027078 2004.03.23 06:27:07)
	(_source (\./compile/U21_TB.v\ VERILOG (\./compile/u21_tb.v\ VERILOG)))
	(_use (std(standard))(vl(verilog_logic)))
	(_base (E 3))
	(_entity
		(_time 1080052027078)
		(_use )
	)
	(_timescale 1ns 1ns)
	(_parameters    dbg   accs  )
	(_attribute )
	(_object
		(_type (_internal ~vector~0 0 78 (_array ~bit ((_uto (i 0) (i 0))))))
		(_generic (_internal DANGLING_INPUT_CONSTANT ~vector~0 0 78 \1'bZ\ (_entity -1 (_constant \1'bZ\))))
		(_port (_internal Enc133FLG ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Enc15FLG ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal FLS1 ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal FLS2 ~wire 0 32 (_architecture (_in ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Home1 ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Home133FLG ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Home15FLG ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Home2 ~wire 0 32 (_architecture (_in ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PhaseA_Encoder1 ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PhaseB_Encoder1 ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal RLS1 ~wire 0 33 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal RLS2 ~wire 0 33 (_architecture (_in ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Reset ~wire 0 33 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal SCL ~wire 0 33 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal SCLinc ~wire 0 33 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal SCLreset ~wire 0 33 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Enc133ctrl ~wire 0 33 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Enc15ctrl ~wire 0 33 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Home133ctrl ~wire 0 33 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Home15ctrl ~wire 0 33 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal AS ~wire 0 81 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal Mclk ~wire 0 82 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal RD ~wire 0 83 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal WR ~wire 0 84 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_type (_internal ~[7:0]wire~ 0 85 (_array ~wire ((_downto (i 7) (i 0))))))
		(_signal (_internal AD ~[7:0]wire~ 0 85 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal Dangling_Input_Signal ~wire 0 88 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_type (_internal ~[5:0]wire~ 0 119 (_array ~wire ((_downto (i 5) (i 0))))))
		(_signal (_internal \1 \ ~[5:0]wire~ -1 119 (_internal (_uni ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_subprogram
			

		)
		(_type (_external ~wire (vl verilog_logic wire)))
		(_type (_external ~reg (vl verilog_logic reg)))
		(_type (_external ~event (vl verilog_logic event)))
		(_type (_external ~wand (vl verilog_logic wand)))
		(_type (_external ~wor (vl verilog_logic wor)))
		(_type (_external ~tri1 (vl verilog_logic tri1)))
		(_type (_external ~tri0 (vl verilog_logic tri0)))
		(_type (_external ~trireg (vl verilog_logic trireg)))
		(_type (_external ~supply0 (vl verilog_logic supply0)))
		(_type (_external ~supply1 (vl verilog_logic supply1)))
		(_type (_external ~real (vl verilog_logic real)))
		(_type (_external ~realtime (vl verilog_logic realtime)))
		(_type (_external ~tri (vl verilog_logic tri)))
		(_type (_external ~triand (vl verilog_logic triand)))
		(_type (_external ~trior (vl verilog_logic trior)))
		(_type (_external ~bit (vl verilog_logic bit)))
		(_type (_external ~extstd.standard.integer (std standard integer)))
		(_type (_external ~extstd.standard.bit (std standard bit)))
		(_process
			(#INTERNAL#119_0 (_internal 0 0 119 (_process (_simple)
				(_target(26))
				(_sensitivity(25))
			)))
			(#ASSIGN#88_1 (_architecture 1 0 88 (_process (_simple)
				(_target(25))
			)))
			(#INTERNAL#0_2 (_internal 2 0 0 (_process (_virtual))))
		)
	)
	
	
	(_defparam
	)
	(_scope
	)
	(_instantiation U1 0 92 (_entity .  U21)
		(_port
			((AD) (AD))
			((AS) (AS))
			((Brake0) (Dangling_Input_Signal))
			((Brake1) (Dangling_Input_Signal))
			((DIR0) (Dangling_Input_Signal))
			((DIR1) (Dangling_Input_Signal))
			((Enc033FLG) (Dangling_Input_Signal))
			((Enc05FLG) (Dangling_Input_Signal))
			((Enc133FLG) (Enc133FLG))
			((Enc133ctrl) (Enc133ctrl))
			((Enc15FLG) (Enc15FLG))
			((Enc15ctrl) (Enc15ctrl))
			((FLS0) (Dangling_Input_Signal))
			((FLS1) (FLS1))
			((GP_Motor0_0) (Dangling_Input_Signal))
			((GP_Motor1_0) (Dangling_Input_Signal))
			((HSI) (Dangling_Input_Signal))
			((Home0) (Dangling_Input_Signal))
			((Home033FLG) (Dangling_Input_Signal))
			((Home05FLG) (Dangling_Input_Signal))
			((Home1) (Home1))
			((Home133FLG) (Home133FLG))
			((Home133ctrl) (Home133ctrl))
			((Home15FLG) (Home15FLG))
			((Home15ctrl) (Home15ctrl))
			((I2CS) (\1 \))
			((INTbus) (Dangling_Input_Signal))
			((LightSense) (Dangling_Input_Signal))
			((MHSO) (Dangling_Input_Signal))
			((Mclk) (Mclk))
			((PWM1) (Dangling_Input_Signal))
			((PWM2) (Dangling_Input_Signal))
			((PhaseA_Encoder0) (Dangling_Input_Signal))
			((PhaseA_Encoder1) (PhaseA_Encoder1))
			((PhaseB_Encoder0) (Dangling_Input_Signal))
			((PhaseB_Encoder1) (PhaseB_Encoder1))
			((RD) (RD))
			((RLS0) (Dangling_Input_Signal))
			((RLS1) (RLS1))
			((Reset) (Reset))
			((SCL) (SCL))
			((SCLinc) (SCLinc))
			((SCLreset) (SCLreset))
			((TXI) (Dangling_Input_Signal))
			((WR) (WR))
			((Enc033ctrl) (_open))
			((Enc05ctrl) (_open))
			((GP_Motor0_1) (_open))
			((GP_Motor1_1) (_open))
			((HSO) (_open))
			((Home033ctrl) (_open))
			((Home05ctrl) (_open))
			((INT) (_open))
			((LED1) (_open))
			((LED2) (_open))
			((LED3) (_open))
			((LED4) (_open))
			((LED5) (_open))
			((MHSI) (_open))
			((MTRpwr) (_open))
			((MTRpwrn) (_open))
			((MTXI) (_open))
			((PAH0) (_open))
			((PAH1) (_open))
			((PAL0) (_open))
			((PAL1) (_open))
			((PBH0) (_open))
			((PBH1) (_open))
			((PBL0) (_open))
			((PBL1) (_open))
			((TP10) (_open))
			((TP11) (_open))
			((TP12) (_open))
		)
		(_strength)
	)
	(_instantiation U2 0 143 (_entity .  MSP)
		(_port
			((AD) (AD))
			((AS) (AS))
			((Mclk) (Mclk))
			((RD) (RD))
			((WR) (WR))
		)
		(_strength)
	)
	(_model . U4_TB 3 -1)

)
V 000052 55 12821         1080052027508 U21_TB_tsim
(_unit VERILOG 6.349C.6.256 (U21_TB_tsim 0 32 (U21_TB_tsim 0 32 ))
	(_version v32)
	(_time 1080052027078 2004.03.23 06:27:07)
	(_source (\./compile/U21_TB_tsim.v\ VERILOG (\./compile/u21_tb_tsim.v\ VERILOG)))
	(_use (std(standard))(vl(verilog_logic)))
	(_base (E 3))
	(_entity
		(_time 1080052027078)
		(_use )
	)
	(_timescale 1ns 1ns)
	(_parameters    dbg   accs  )
	(_attribute )
	(_object
		(_type (_internal ~vector~0 0 139 (_array ~bit ((_uto (i 0) (i 0))))))
		(_generic (_internal DANGLING_INPUT_CONSTANT ~vector~0 0 139 \1'bZ\ (_entity -1 (_constant \1'bZ\))))
		(_port (_internal Brake1 ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Brake2 ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal DIR1 ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal DIR2 ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Enc133FLG ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Enc15FLG ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Enc233FLG ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Enc25FLG ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal FLS1 ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal FLS2 ~wire 0 32 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Home1 ~wire 0 33 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Home133FLG ~wire 0 33 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Home15FLG ~wire 0 33 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Home2 ~wire 0 33 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Home233FLG ~wire 0 33 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Home25FLG ~wire 0 33 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PWM1 ~wire 0 33 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PWM2 ~wire 0 33 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PhaseA_Encoder1 ~wire 0 33 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PhaseA_Encoder2 ~wire 0 33 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PhaseB_Encoder1 ~wire 0 34 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PhaseB_Encoder2 ~wire 0 34 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal RLS1 ~wire 0 34 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal RLS2 ~wire 0 34 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Reset ~wire 0 34 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Enc133ctrl ~wire 0 34 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Enc15ctrl ~wire 0 34 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Enc233ctrl ~wire 0 34 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Enc25ctrl ~wire 0 34 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Home133ctrl ~wire 0 34 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Home15ctrl ~wire 0 35 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Home233ctrl ~wire 0 35 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal Home25ctrl ~wire 0 35 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal INT ~wire 0 35 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal LED1 ~wire 0 35 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal LED2 ~wire 0 35 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal LED3 ~wire 0 35 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal LED4 ~wire 0 35 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal LED5 ~wire 0 35 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal MTRpwr ~wire 0 35 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal MTRpwrn ~wire 0 36 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PAH1 ~wire 0 36 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PAH2 ~wire 0 36 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PAL1 ~wire 0 36 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PAL2 ~wire 0 36 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PBH1 ~wire 0 36 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PBH2 ~wire 0 36 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PBL1 ~wire 0 36 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_port (_internal PBL2 ~wire 0 36 (_architecture (_out ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal AS ~wire 0 142 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal Mclk ~wire 0 143 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal RD ~wire 0 144 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal WR ~wire 0 145 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_type (_internal ~[7:0]wire~ 0 146 (_array ~wire ((_downto (i 7) (i 0))))))
		(_signal (_internal AD ~[7:0]wire~ 0 146 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_signal (_internal Dangling_Input_Signal ~wire 0 149 (_architecture (_uni ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_type (_internal ~[5:0]wire~ 0 184 (_array ~wire ((_downto (i 5) (i 0))))))
		(_signal (_internal \1 \ ~[5:0]wire~ -1 184 (_internal (_uni ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign))
		(_subprogram
			

		)
		(_type (_external ~wire (vl verilog_logic wire)))
		(_type (_external ~reg (vl verilog_logic reg)))
		(_type (_external ~event (vl verilog_logic event)))
		(_type (_external ~wand (vl verilog_logic wand)))
		(_type (_external ~wor (vl verilog_logic wor)))
		(_type (_external ~tri1 (vl verilog_logic tri1)))
		(_type (_external ~tri0 (vl verilog_logic tri0)))
		(_type (_external ~trireg (vl verilog_logic trireg)))
		(_type (_external ~supply0 (vl verilog_logic supply0)))
		(_type (_external ~supply1 (vl verilog_logic supply1)))
		(_type (_external ~real (vl verilog_logic real)))
		(_type (_external ~realtime (vl verilog_logic realtime)))
		(_type (_external ~tri (vl verilog_logic tri)))
		(_type (_external ~triand (vl verilog_logic triand)))
		(_type (_external ~trior (vl verilog_logic trior)))
		(_type (_external ~bit (vl verilog_logic bit)))
		(_type (_external ~extstd.standard.integer (std standard integer)))
		(_type (_external ~extstd.standard.bit (std standard bit)))
		(_process
			(#INTERNAL#184_0 (_internal 0 0 184 (_process (_simple)
				(_target(55))
				(_sensitivity(54))
			)))
			(#ASSIGN#149_1 (_architecture 1 0 149 (_process (_simple)
				(_target(54))
			)))
			(#INTERNAL#0_2 (_internal 2 0 0 (_process (_virtual))))
		)
	)
	
	
	(_defparam
	)
	(_scope
	)
	(_instantiation U1 0 153 (_entity .  U21)
		(_port
			((AD) (AD))
			((AS) (AS))
			((Brake0) (Brake1))
			((Brake1) (Brake2))
			((DIR0) (DIR1))
			((DIR1) (DIR2))
			((Enc033FLG) (Enc133FLG))
			((Enc033ctrl) (Enc133ctrl))
			((Enc05FLG) (Enc15FLG))
			((Enc05ctrl) (Enc15ctrl))
			((Enc133FLG) (Enc233FLG))
			((Enc133ctrl) (Enc233ctrl))
			((Enc15FLG) (Enc25FLG))
			((Enc15ctrl) (Enc25ctrl))
			((FLS0) (FLS1))
			((FLS1) (FLS2))
			((GP_Motor0_0) (Dangling_Input_Signal))
			((GP_Motor1_0) (Dangling_Input_Signal))
			((HSI) (Dangling_Input_Signal))
			((Home0) (Home1))
			((Home033FLG) (Home133FLG))
			((Home033ctrl) (Home133ctrl))
			((Home05FLG) (Home15FLG))
			((Home05ctrl) (Home15ctrl))
			((Home1) (Home2))
			((Home133FLG) (Home233FLG))
			((Home133ctrl) (Home233ctrl))
			((Home15FLG) (Home25FLG))
			((Home15ctrl) (Home25ctrl))
			((I2CS) (\1 \))
			((INT) (INT))
			((INTbus) (Dangling_Input_Signal))
			((LED1) (LED1))
			((LED2) (LED2))
			((LED3) (LED3))
			((LED4) (LED4))
			((LED5) (LED5))
			((LightSense) (Dangling_Input_Signal))
			((MHSO) (Dangling_Input_Signal))
			((MTRpwr) (MTRpwr))
			((MTRpwrn) (MTRpwrn))
			((Mclk) (Mclk))
			((PAH0) (PAH1))
			((PAH1) (PAH2))
			((PAL0) (PAL1))
			((PAL1) (PAL2))
			((PBH0) (PBH1))
			((PBH1) (PBH2))
			((PBL0) (PBL1))
			((PBL1) (PBL2))
			((PWM1) (PWM1))
			((PWM2) (PWM2))
			((PhaseA_Encoder0) (PhaseA_Encoder1))
			((PhaseA_Encoder1) (PhaseA_Encoder2))
			((PhaseB_Encoder0) (PhaseB_Encoder1))
			((PhaseB_Encoder1) (PhaseB_Encoder2))
			((RD) (RD))
			((RLS0) (RLS1))
			((RLS1) (RLS2))
			((Reset) (Reset))
			((SCLinc) (Dangling_Input_Signal))
			((SCLreset) (Dangling_Input_Signal))
			((TXI) (Dangling_Input_Signal))
			((WR) (WR))
			((GP_Motor0_1) (_open))
			((GP_Motor1_1) (_open))
			((HSO) (_open))
			((MHSI) (_open))
			((MTXI) (_open))
			((TP10) (_open))
			((TP11) (_open))
			((TP12) (_open))
			((SCL) (_open))
		)
		(_strength)
	)
	(_instantiation U2 0 223 (_entity .  MSP)
		(_port
			((AD) (AD))
			((AS) (AS))
			((Mclk) (Mclk))
			((RD) (RD))
			((WR) (WR))
		)
		(_strength)
	)
	(_model . U21_TB_tsim 3 -1)

)
V 000054 55 3721          1080052027519 EncoderEngine
(_unit VERILOG 6.349C.6.256 (EncoderEngine 0 23 (EncoderEngine 0 23 ))
	(_version v32)
	(_time 1080052027078 2004.03.23 06:27:07)
	(_source (\./compile/EncoderEngine.v\ VERILOG (\./compile/encoderengine.v\ VERILOG)))
	(_use (std(standard))(vl(verilog_logic)))
	(_base (E 5))
	(_entity
		(_time 1080052027078)
		(_use )
	)
	(_timescale 1ns 1ps)
	(_parameters    dbg   accs  )
	(_attribute nb_assign )
	(_object
		(_port (_internal DAV ~reg 0 23 (_architecture (_out ))) (_reg ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_type (_internal ~[5:0]reg~ 0 23 (_array ~reg ((_downto (i 5) (i 0))))))
		(_port (_internal SSclkb ~[5:0]reg~ 0 23 (_architecture (_out ))) (_reg ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal clk ~wire 0 23 (_architecture (_in ))) (_net  ) (_nonbaction) (_noforceassign))
		(_port (_internal data ~wire 0 23 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal reset ~wire 0 23 (_architecture (_in ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal shift ~reg 0 23 (_architecture (_out ))) (_reg ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal start ~wire 0 23 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal next_DAV ~reg 0 32 (_architecture (_uni ))) (_reg ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal next_shift ~reg 0 37 (_architecture (_uni ))) (_reg ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal CurrState_Sreg0 ~[5:0]reg~ 0 83 (_architecture (_uni ))) (_reg ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_signal (_internal NextState_Sreg0 ~[5:0]reg~ 0 85 (_architecture (_uni ))) (_reg ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_subprogram
			

		)
		(_type (_external ~wire (vl verilog_logic wire)))
		(_type (_external ~reg (vl verilog_logic reg)))
		(_type (_external ~event (vl verilog_logic event)))
		(_type (_external ~wand (vl verilog_logic wand)))
		(_type (_external ~wor (vl verilog_logic wor)))
		(_type (_external ~tri1 (vl verilog_logic tri1)))
		(_type (_external ~tri0 (vl verilog_logic tri0)))
		(_type (_external ~trireg (vl verilog_logic trireg)))
		(_type (_external ~supply0 (vl verilog_logic supply0)))
		(_type (_external ~supply1 (vl verilog_logic supply1)))
		(_type (_external ~real (vl verilog_logic real)))
		(_type (_external ~realtime (vl verilog_logic realtime)))
		(_type (_external ~tri (vl verilog_logic tri)))
		(_type (_external ~triand (vl verilog_logic triand)))
		(_type (_external ~trior (vl verilog_logic trior)))
		(_type (_external ~bit (vl verilog_logic bit)))
		(_type (_external ~extstd.standard.integer (std standard integer)))
		(_type (_external ~extstd.standard.bit (std standard bit)))
		(_process
			(#ALWAYS#97_0 (_architecture 0 0 97 (_process 
				(_target(10)(7)(8))
				(_read)
				(_sensitivity(0)(6)(3)(5)(9))
			)))
			(#ALWAYS#354_1 (_architecture 1 0 354 (_process 
				(_target(9))
				(_read(2)(4)(10))
			)))
			(#ALWAYS#365_2 (_architecture 2 0 365 (_process 
				(_target(0)(5))
				(_read(2)(4)(7)(8))
			)))
			(#ALWAYS#380_3 (_architecture 3 0 380 (_process 
				(_target(1))
				(_read)
				(_sensitivity(9))
			)))
		)
	)
	
	
	(_defparam
	)
	(_scope
		(_unit Sreg0_NextState begin 0 98
		)
		(_unit Sreg0_CurrentState begin 0 355
		)
		(_unit Sreg0_RegOutput begin 0 366
		)
	)
	(_model . EncoderEngine 5 -1)

)
V 000048 55 2977          1080052027523 Shifter
(_unit VERILOG 6.349C.6.256 (Shifter 0 25 (Shifter 0 25 ))
	(_version v32)
	(_time 1080052027078 2004.03.23 06:27:07)
	(_source (\./src/shifter.v\ VERILOG (\./src/shifter.v\ VERILOG)))
	(_use (std(standard))(vl(verilog_logic)))
	(_base (E 3))
	(_entity
		(_time 1080052027078)
		(_use )
	)
	(_timescale 1ns 1ps)
	(_parameters    dbg   accs  )
	(_attribute nb_assign )
	(_object
		(_type (_internal ~[7:0]wire~ 0 25 (_array ~wire ((_downto (i 7) (i 0))))))
		(_port (_internal Pdata ~[7:0]wire~ 0 25 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal RVALVEHIGHr ~wire 0 25 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal data ~wire 0 25 (_architecture (_in ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal clk ~wire 0 25 (_architecture (_in ))) (_net  ) (_nonbaction) (_noforceassign))
		(_port (_internal reset ~wire 0 25 (_architecture (_in ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal RVALVELOWr ~wire 0 25 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal shift ~wire 0 25 (_architecture (_in ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_type (_internal ~[8:0]reg~ 0 47 (_array ~reg ((_downto (i 8) (i 0))))))
		(_signal (_internal Pdatar ~[8:0]reg~ 0 47 (_architecture (_uni ))) (_reg ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_subprogram
			

		)
		(_type (_external ~wire (vl verilog_logic wire)))
		(_type (_external ~reg (vl verilog_logic reg)))
		(_type (_external ~event (vl verilog_logic event)))
		(_type (_external ~wand (vl verilog_logic wand)))
		(_type (_external ~wor (vl verilog_logic wor)))
		(_type (_external ~tri1 (vl verilog_logic tri1)))
		(_type (_external ~tri0 (vl verilog_logic tri0)))
		(_type (_external ~trireg (vl verilog_logic trireg)))
		(_type (_external ~supply0 (vl verilog_logic supply0)))
		(_type (_external ~supply1 (vl verilog_logic supply1)))
		(_type (_external ~real (vl verilog_logic real)))
		(_type (_external ~realtime (vl verilog_logic realtime)))
		(_type (_external ~tri (vl verilog_logic tri)))
		(_type (_external ~triand (vl verilog_logic triand)))
		(_type (_external ~trior (vl verilog_logic trior)))
		(_type (_external ~bit (vl verilog_logic bit)))
		(_type (_external ~extstd.standard.integer (std standard integer)))
		(_type (_external ~extstd.standard.bit (std standard bit)))
		(_process
			(#ASSIGN#50_0 (_architecture 0 0 50 (_process (_simple)
				(_target(0))
				(_sensitivity(1)(7(8))(5)(7(d_7_0)))
			)))
			(#ALWAYS#52_1 (_architecture 1 0 52 (_process 
				(_target(7))
				(_read(3)(4)(6)(7(d_7_0))(2)(7))
			)))
		)
	)
	
	
	(_defparam
	)
	(_model . Shifter 3 -1)

)
V 000047 55 2065          1080052027527 DAVctl
(_unit VERILOG 6.349C.6.256 (DAVctl 0 25 (DAVctl 0 25 ))
	(_version v32)
	(_time 1080052027078 2004.03.23 06:27:07)
	(_source (\./src/DAVctl.v\ VERILOG (\./src/davctl.v\ VERILOG)))
	(_use (std(standard))(vl(verilog_logic)))
	(_base (E 2))
	(_entity
		(_time 1080052027078)
		(_use )
	)
	(_timescale 1ns 1ps)
	(_parameters    dbg   accs  )
	(_attribute )
	(_object
		(_type (_internal ~[7:0]wire~ 0 25 (_array ~wire ((_downto (i 7) (i 0))))))
		(_port (_internal Pdata ~[7:0]wire~ 0 25 (_architecture (_out ))) (_net  ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal DAVin ~wire 0 25 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_port (_internal RVALVESTATr ~wire 0 25 (_architecture (_in ))) (_net  ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign))
		(_subprogram
			

		)
		(_type (_external ~wire (vl verilog_logic wire)))
		(_type (_external ~reg (vl verilog_logic reg)))
		(_type (_external ~event (vl verilog_logic event)))
		(_type (_external ~wand (vl verilog_logic wand)))
		(_type (_external ~wor (vl verilog_logic wor)))
		(_type (_external ~tri1 (vl verilog_logic tri1)))
		(_type (_external ~tri0 (vl verilog_logic tri0)))
		(_type (_external ~trireg (vl verilog_logic trireg)))
		(_type (_external ~supply0 (vl verilog_logic supply0)))
		(_type (_external ~supply1 (vl verilog_logic supply1)))
		(_type (_external ~real (vl verilog_logic real)))
		(_type (_external ~realtime (vl verilog_logic realtime)))
		(_type (_external ~tri (vl verilog_logic tri)))
		(_type (_external ~triand (vl verilog_logic triand)))
		(_type (_external ~trior (vl verilog_logic trior)))
		(_type (_external ~bit (vl verilog_logic bit)))
		(_type (_external ~extstd.standard.integer (std standard integer)))
		(_type (_external ~extstd.standard.bit (std standard bit)))
		(_process
			(#ASSIGN#39_0 (_architecture 0 0 39 (_process (_simple)
				(_target(0))
				(_sensitivity(2)(1))
			)))
		)
	)
	
	
	(_defparam
	)
	(_model . DAVctl 2 -1)

)