//--------------------------------------------------------------------------------------------------
//
// Title       : No Title
// Design      : encoder
// Author      : 
// Company     : 
//
//-------------------------------------------------------------------------------------------------
//
// File        : C:\Projects\genosensor\2g\CPLDs\Encoder check\encoder\compile\EncoderEngine.v
// Generated   : 03/22/04 13:49:14
// From        : C:\Projects\genosensor\2g\CPLDs\Encoder check\encoder\src\EncoderEngine.asf
// By          : FSM2VHDL ver. 4.0.3.8
//
//-------------------------------------------------------------------------------------------------
//
// Description : 
//
//-------------------------------------------------------------------------------------------------

`timescale 1ns / 1ps

module EncoderEngine (DAV, SSclkb, clk, data, reset, shift, start);
input   clk;
input   data;
input   reset;
input   start;
output  DAV;
output  [5:0] SSclkb;
output  shift;

reg     DAV, next_DAV;
reg     [5:0] SSclkb;
wire    clk;
wire    data;
wire    reset;
reg     shift, next_shift;
wire    start;

// USER DEFINED ENCODED state machine: Sreg0
// State codes definitions:
`define S1 6'b100011
`define S2 6'b100110
`define S3 6'b100001
`define S4 6'b100000
`define S5 6'b011111
`define S6 6'b011110
`define S7 6'b011101
`define S8 6'b011100
`define S9 6'b011011
`define S10 6'b011010
`define S11 6'b011001
`define S12 6'b011000
`define S14 6'b010110
`define S16 6'b010100
`define S17 6'b010011
`define S18 6'b010010
`define S19 6'b010001
`define S20 6'b010000
`define S21 6'b001111
`define S22 6'b001110
`define S23 6'b001101
`define S24 6'b001100
`define S25 6'b001011
`define S26 6'b001010
`define S27 6'b001001
`define S28 6'b001000
`define S29 6'b000111
`define S30 6'b000110
`define S31 6'b000101
`define S32 6'b000100
`define S33 6'b000011
`define S34 6'b000010
`define S35 6'b000001
`define S36 6'b000000
`define S15 6'b010101
`define S13 6'b010111
`define S37 6'b100010
`define S38 6'b100101
`define S39 6'b100100
`define S40 6'b100111

reg [5:0] CurrState_Sreg0; // synthesis attribute fsm_extract of CurrState_Sreg0 is "yes";
 // synthesis attribute fsm_fftype of CurrState_Sreg0 is "d";
reg [5:0] NextState_Sreg0;

// Diagram actions (continuous assignments allowed only: assign ...)
// diagram ACTION


//--------------------------------------------------------------------
// Machine: Sreg0
//--------------------------------------------------------------------
//----------------------------------
// NextState logic (combinatorial)
//----------------------------------
always @ (DAV or start or data or shift or CurrState_Sreg0)
begin : Sreg0_NextState
	NextState_Sreg0 <= CurrState_Sreg0;
	// Set default values for outputs and signals
	next_DAV <= DAV;
	next_shift <= shift;
	case (CurrState_Sreg0)
		`S1:
		begin
			next_DAV <= 1'b0;
			next_shift <= 1'b1;
			NextState_Sreg0 <= `S37;
		end
		`S2:
		begin
			next_DAV <= DAV;
			next_shift <= 1'b0;
			if ((start))	
			begin
				NextState_Sreg0 <= `S3;
				next_DAV <= 1'b0;
			end
		end
		`S3:
		begin
			next_shift <= 1'b0;
			NextState_Sreg0 <= `S4;
		end
		`S4:
		begin
			next_DAV <= 1'b0;
			next_shift <= 1'b0;
			NextState_Sreg0 <= `S5;
		end
		`S5:
		begin
			next_DAV <= 1'b0;
			next_shift <= 1'b1;
			NextState_Sreg0 <= `S6;
		end
		`S6:
		begin
			next_DAV <= 1'b0;
			next_shift <= 1'b0;
			NextState_Sreg0 <= `S7;
		end
		`S7:
		begin
			next_DAV <= 1'b0;
			next_shift <= 1'b0;
			NextState_Sreg0 <= `S8;
		end
		`S8:
		begin
			next_DAV <= 1'b0;
			next_shift <= 1'b0;
			NextState_Sreg0 <= `S9;
		end
		`S9:
		begin
			next_DAV <= 1'b0;
			next_shift <= 1'b1;
			NextState_Sreg0 <= `S10;
		end
		`S10:
		begin
			next_DAV <= 1'b0;
			next_shift <= 1'b0;
			NextState_Sreg0 <= `S11;
		end
		`S11:
		begin
			next_DAV <= 1'b0;
			next_shift <= 1'b0;
			NextState_Sreg0 <= `S12;
		end
		`S12:
		begin
			next_DAV <= 1'b0;
			next_shift <= 1'b0;
			NextState_Sreg0 <= `S13;
		end
		`S14:
		begin
			next_DAV <= 1'b0;
			next_shift <= 1'b0;
			NextState_Sreg0 <= `S15;
		end
		`S16:
		begin
			next_DAV <= 1'b0;
			next_shift <= 1'b0;
			NextState_Sreg0 <= `S17;
		end
		`S17:
		begin
			next_DAV <= 1'b0;
			next_shift <= 1'b1;
			NextState_Sreg0 <= `S18;
		end
		`S18:
		begin
			next_DAV <= 1'b0;
			next_shift <= 1'b0;
			NextState_Sreg0 <= `S19;
		end
		`S19:
		begin
			next_DAV <= 1'b0;
			next_shift <= 1'b0;
			NextState_Sreg0 <= `S20;
		end
		`S20:
		begin
			next_DAV <= 1'b0;
			next_shift <= 1'b0;
			NextState_Sreg0 <= `S21;
		end
		`S21:
		begin
			next_DAV <= 1'b0;
			next_shift <= 1'b1;
			NextState_Sreg0 <= `S22;
		end
		`S22:
		begin
			next_DAV <= 1'b0;
			next_shift <= 1'b0;
			NextState_Sreg0 <= `S23;
		end
		`S23:
		begin
			next_DAV <= 1'b0;
			next_shift <= 1'b0;
			NextState_Sreg0 <= `S24;
		end
		`S24:
		begin
			next_DAV <= 1'b0;
			next_shift <= 1'b0;
			NextState_Sreg0 <= `S25;
		end
		`S25:
		begin
			next_DAV <= 1'b0;
			next_shift <= 1'b1;
			NextState_Sreg0 <= `S26;
		end
		`S26:
		begin
			next_DAV <= 1'b0;
			next_shift <= 1'b0;
			NextState_Sreg0 <= `S27;
		end
		`S27:
		begin
			next_DAV <= 1'b0;
			next_shift <= 1'b0;
			NextState_Sreg0 <= `S28;
		end
		`S28:
		begin
			next_DAV <= 1'b0;
			next_shift <= 1'b0;
			NextState_Sreg0 <= `S29;
		end
		`S29:
		begin
			next_DAV <= 1'b0;
			next_shift <= 1'b1;
			NextState_Sreg0 <= `S30;
		end
		`S30:
		begin
			next_DAV <= 1'b0;
			next_shift <= 1'b0;
			NextState_Sreg0 <= `S31;
		end
		`S31:
		begin
			next_DAV <= 1'b0;
			next_shift <= 1'b0;
			NextState_Sreg0 <= `S32;
		end
		`S32:
		begin
			next_DAV <= 1'b0;
			next_shift <= 1'b0;
			NextState_Sreg0 <= `S33;
		end
		`S33:
		begin
			next_DAV <= 1'b0;
			next_shift <= 1'b1;
			NextState_Sreg0 <= `S34;
		end
		`S34:
		begin
			next_DAV <= 1'b0;
			next_shift <= 1'b0;
			NextState_Sreg0 <= `S35;
		end
		`S35:
		begin
			next_DAV <= 1'b0;
			next_shift <= 1'b0;
			NextState_Sreg0 <= `S36;
		end
		`S36:
		begin
			next_DAV <= 1'b0;
			next_shift <= 1'b0;
			NextState_Sreg0 <= `S1;
		end
		`S15:
		begin
			next_DAV <= 1'b0;
			next_shift <= 1'b0;
			NextState_Sreg0 <= `S16;
		end
		`S13:
		begin
			next_DAV <= 1'b0;
			next_shift <= 1'b1;
			NextState_Sreg0 <= `S14;
		end
		`S37:
		begin
			next_DAV <= 1'b0;
			next_shift <= 1'b0;
			NextState_Sreg0 <= `S38;
		end
		`S38:
		begin
			next_DAV <= 1'b0;
			next_shift <= 1'b0;
			NextState_Sreg0 <= `S39;
		end
		`S39:
		begin
			next_DAV <= 1'b0;
			next_shift <= 1'b0;
			NextState_Sreg0 <= `S40;
		end
		`S40:
		begin
			next_DAV <= 1'b1;
			next_shift <= 1'b0;
			if (data)	
				NextState_Sreg0 <= `S2;
		end
	endcase
end

//----------------------------------
// Current State Logic (sequential)
//----------------------------------
always @ (posedge clk)
begin : Sreg0_CurrentState
	if ((reset))	
		CurrState_Sreg0 <= `S2;
	else
		CurrState_Sreg0 <= NextState_Sreg0;
end

//----------------------------------
// Registered outputs logic
//----------------------------------
always @ (posedge clk)
begin : Sreg0_RegOutput
	if ((reset))	
	begin
		DAV <= 1'b0;
		shift <= 1'b0;
	end
	else 
	begin
		DAV <= next_DAV;
		shift <= next_shift;
	end
end

// Copy state register(s) to output port(s)
always @ (CurrState_Sreg0)
	SSclkb = CurrState_Sreg0;

endmodule