//--------------------------------------------------------------------------------------------------
//
// Title       : No Title
// Design      : U4
// Author      : 
// Company     : 
//
//-------------------------------------------------------------------------------------------------
//
// File        : c:\Projects\genosensor\2g\CPLDs\Core\U4\compile\PWMtranslator.v
// Generated   : 12/19/03 17:34:32
// From        : c:\Projects\genosensor\2g\CPLDs\Core\U4\src\PWMtranslator.asf
// By          : FSM2VHDL ver. 4.0.3.8
//
//-------------------------------------------------------------------------------------------------
//
// Description : 
//
//-------------------------------------------------------------------------------------------------

`timescale 1ns / 1ps

module PWMtranslator (Brake, DIR, Hcontrol, Mclk, PWM, Reset, fBRK);
input   Brake;
input   DIR;
input   Mclk;
input   PWM;
input   Reset;
input   fBRK;
output  [3:0] Hcontrol;

wire    Brake;
wire    DIR;
reg     [3:0] Hcontrol;
wire    Mclk;
wire    PWM;
wire    Reset;
wire    fBRK;

// USER DEFINED ENCODED state machine: Sreg0
// State codes definitions:
`define Off 4'b0000
`define DriveFWD 4'b1011
`define ChrgFWD 4'b0010
`define Brake 4'b1010
`define DriveRVS 4'b1110
`define ChrgRVS 4'b1000

reg [3:0] CurrState_Sreg0; // synthesis attribute fsm_extract of CurrState_Sreg0 is "yes";
 // synthesis attribute fsm_fftype of CurrState_Sreg0 is "d";
reg [3:0] NextState_Sreg0;

// Diagram actions (continuous assignments allowed only: assign ...)
// diagram ACTION


//--------------------------------------------------------------------
// Machine: Sreg0
//--------------------------------------------------------------------
//----------------------------------
// NextState logic (combinatorial)
//----------------------------------
always @ (fBRK or Brake or DIR or PWM or CurrState_Sreg0)
begin : Sreg0_NextState
	NextState_Sreg0 <= CurrState_Sreg0;
	// Set default values for outputs and signals
	// ... 
	case (CurrState_Sreg0)
		`Off:
			if ((!fBRK & !Brake & !DIR & PWM))	
				NextState_Sreg0 <= `DriveFWD;
			else if ((!fBRK & !Brake & DIR & PWM))	
				NextState_Sreg0 <= `DriveRVS;
			else if ((!fBRK & !Brake & !DIR & !PWM))	
				NextState_Sreg0 <= `ChrgFWD;
			else if ((fBRK | Brake))	
				NextState_Sreg0 <= `Brake;
		`DriveFWD:
			if ((fBRK | Brake))	
				NextState_Sreg0 <= `Brake;
			else if ((!fBRK & !Brake & !DIR & !PWM))	
				NextState_Sreg0 <= `ChrgFWD;
		`ChrgFWD:
			if ((fBRK | Brake))	
				NextState_Sreg0 <= `Brake;
			else if ((!fBRK & !Brake & !DIR & PWM))	
				NextState_Sreg0 <= `DriveFWD;
		`Brake:
			if ((!(!fBRK | ! Brake)))	
				NextState_Sreg0 <= `Off;
		`DriveRVS:
			if ((!fBRK & !Brake & DIR & !PWM))	
				NextState_Sreg0 <= `ChrgRVS;
			else if ((fBRK | Brake))	
				NextState_Sreg0 <= `Brake;
		`ChrgRVS:
			if ((!fBRK & !Brake & DIR & PWM))	
				NextState_Sreg0 <= `DriveRVS;
			else if ((fBRK | Brake))	
				NextState_Sreg0 <= `Brake;
	endcase
end

//----------------------------------
// Current State Logic (sequential)
//----------------------------------
always @ (posedge Mclk)
begin : Sreg0_CurrentState
	if (Reset)	
		CurrState_Sreg0 <= `Off;
	else
		CurrState_Sreg0 <= NextState_Sreg0;
end

// Copy state register(s) to output port(s)
always @ (CurrState_Sreg0)
	Hcontrol = CurrState_Sreg0;

endmodule