//--------------------------------------------------------------------------------------------------
//
// Title       : reader
// Design      : encoder
// Author      : mbari###
// Company     : MBARI
//
//-------------------------------------------------------------------------------------------------
//
// File        : C:\Projects\genosensor\2g\CPLDs\Encoder check\encoder\compile\reader.v
// Generated   : Mon Mar 22 13:50:28 2004
// From        : C:\Projects\genosensor\2g\CPLDs\Encoder check\encoder\src\reader.bde
// By          : Bde2Verilog ver. 2.01
//
//-------------------------------------------------------------------------------------------------
//
// Description : 
//
//-------------------------------------------------------------------------------------------------

// synopsys translate_off
`ifdef _VCP
`else
`define library(a,b)
`endif
// synopsys translate_on


// ---------- Design Unit Header ---------- //
`timescale 1ns / 1ns

module reader (RVALVECTLw,RVALVEHIGHr,RVALVELOWr,RVALVESTATr,data,SSclk,clk,reset,outDATA) ;

// ------------ Port declarations --------- //
input RVALVECTLw;
wire RVALVECTLw;
input RVALVEHIGHr;
wire RVALVEHIGHr;
input RVALVELOWr;
wire RVALVELOWr;
input RVALVESTATr;
wire RVALVESTATr;
input data;
wire data;
output SSclk;
wire SSclk;
output clk;
wire clk;
output reset;
wire reset;
output [7:0] outDATA;
wire [7:0] outDATA;

// ----------- Signal declarations -------- //
wire NET1330;
wire NET843;
wire [5:0] SSclkb;

// -------- Component instantiations -------//

EncoderEngine U3
(
	.DAV(NET1330),
	.SSclkb(SSclkb),
	.clk(clk),
	.data(data),
	.reset(reset),
	.shift(NET843),
	.start(RVALVECTLw)
);



Shifter U4
(
	.Pdata(outDATA),
	.RVALVEHIGHr(RVALVEHIGHr),
	.RVALVELOWr(RVALVELOWr),
	.clk(clk),
	.data(data),
	.reset(reset),
	.shift(NET843)
);



DAVctl U5
(
	.DAVin(NET1330),
	.Pdata(outDATA),
	.RVALVESTATr(RVALVESTATr)
);



// ----------- Terminals assignment --------//
//		   ---- Output terminals ---        //
assign SSclk = SSclkb[1];

endmodule 
