[Project]
Current Flow=Multivendor
VCS=0
version=1
Current Config=compile

[Configurations]
compile=encoder

[$LibMap$]
U4=.
Active_lib=XC9500
xilinxun=XC9500
UnlinkedDesignLibrary=XC9500
DESIGNS=XC9500
U21=.
encoder=.

[Settings]
FLOW_TYPE=HDL
LANGUAGE=VERILOG
SYNTH_TOOL=MV_XST6
IMPL_TOOL=MV_ISE61
FAMILY=Xilinx6x COOLRUNNER
FLOWTOOLS=IMPL_WITH_SYNTH
SYNTH_STATUS=errors
FUNC_LIB=encoder
POST_LIB=U4_post_synthesis
IMPL_STATUS=warnings
CSYNTH_TOOL=<none>
Celoxica=0
UseCeloxica=0
C_SERVER_SIM=
ON_SERVERFARM_SIM=0
C_SERVER_SYNTH=
ON_SERVERFARM_SYNTH=0
C_SERVER_IMPL=
ON_SERVERFARM_IMPL=0
RUN_MODE_IMPL=0
REFRESH_FLOW=1
TIM_LIB=encoder_timing

[IMPLEMENTATION]
UCF=C:\Projects\genosensor\2g\CPLDs\Core\U21\src\U21.ucf
FAMILY=Xilinx6x COOLRUNNER
DEVICE=r3384xlTQ144
SPEED=-7
NETLIST=c:\Projects\genosensor\2g\CPLDs\Encoder check\encoder\synthesis\U21.ngc
LAST_RUN=1079725814
OUTPUT_NETLIST=IMPLEMENT\TIME_SIM.V
OUTPUT_SDF=
DEF_UCF=0
VER=ver0
REV=rev1
PADS=0
SIMOUTFORM=2
EFFORT_LEVEL=2
USE_PAR_CMD_FILE=0
PAR_CMD_FILE=
GENERATE_BIT_FILE=0
USE_BIT_CMD_FILE=0
BIT_CMD_FILE=
XON=1
CORELATE=1
AUTO_CLOSE=0
JOB_DESCRIPTION=ImplementationJob1
SERVERFARM_INCLUDE_INPUT_FILES=*.*
SERVERFARM_EXCLUDE_INPUT_FILES=log\*.*
IS_BAT_MODE=0
BAT_FILE=
OVERRIDE_EXISTING_PROJECT=1
CLB_PACKING_STRATEGY=100
PACK_CLB_REGISTERS_FOR=Structure
PACK_IO_REGISTERS_INTO_IOB_FOR=Inputs and Outputs
USE_GENERIC_CLOCK_BUFFERS=0
IGNORE_RLOC_CONSTRAINTS=1
CREATE_DETAILED_MAP_REPORT=0
IMPL_TEMPL=2
LOC_CONSTR=0
SLEW_RATE=1
POWERUP=0
GLOB_CLKS=1
GLOB_OUT_EN=1
GLOB_SETRESET=1
UNUSED=0
TRI_STATE_TERM=0
VOLT_STD=LVCMOS18
UNSED_IO_PAD_MODE_1=Pullup
PROG_GND_PINS=1
MCRCELL_PWR=1
FIT_MODE=0
LOG_OPT=1
FAST_INPUT=1
INP_LIMIT=32
PTERM_LIMIT=40
FOLDBACK=0
ISP_PINS=1
LOCAL_FBK=0
PIN_FBK=0
UIM_OPT=1
use_ngdbuild_file=0
use_par_file=0
use_map_file=0
use_trace_file=0
use_netgen_file=0
use_cpld_ndg2vhdl_file=0
use_cgsm_ndg2vhdl_file=0
use_bitgen_file=0
use_use_cpldfit_file=0
use_hprep6_file=0
use_tsim_file=0
ngdbuild_file_str=
trace_file_str=
par_file_str=
map_file_str=
netgen_file_str=
bitgen_file_str=
cpldfit_file_str=
hprep6_file_str=
tsim_file_str=
XIL_SEL_BAT_FILES=0
impl_opt(edif_str)=c:\Projects\genosensor\2g\CPLDs\Core\U21\synthesis\U21.ngc
impl_opt(netlist_format)=2
impl_opt(auto_close)=0
impl_opt(override_existing_project)=1
impl_opt(is_bat_mode)=0
impl_opt(def_ucf)=0
impl_opt(ucf_str)=C:\Projects\genosensor\2g\CPLDs\Core\U21\src\U21.ucf
impl_opt(version_sel)=ver0
impl_opt(revision_sel)=rev1
impl_opt(insert_pads)=0
impl_opt(impl_templ)=2
impl_opt(loc_constr)=0
impl_opt(slew_rate)=1
impl_opt(powerup)=0
impl_opt(prog_gnd_pins)=1
impl_opt(mcrcell_pwr)=1
impl_opt(fit_mode)=0
impl_opt(log_opt)=1
impl_opt(fast_input)=1
impl_opt(inp_limit)=32
impl_opt(pterm_limit)=40
impl_opt(local_fbk)=0
impl_opt(uim_opt)=1
impl_opt(ngdbuild_file_str)=
impl_opt(use_ngdbuild_file)=0
impl_opt(cpldfit_file_str)=
impl_opt(use_cpldfit_file)=0
impl_opt(hprep6_file_str)=
impl_opt(use_hprep6_file)=0
impl_opt(tsim_file_str)=
impl_opt(use_tsim_file)=0
impl_opt(Allow_Unmatched_LOC_Constraint)=0
impl_opt(Show_Trim_Unconnected_Signals)=1
impl_opt(Show_Use_Timing_Constraint)=1
impl_opt(Show_Function_Block_Input_Limit)=36
Disable_Register_Ordering=0
impl_opt(tri_state_term)=Pullup
impl_opt(unsed_io_pad_mode_1)=Pullup

[SYNTHESIS]
OBSOLETE_ALIASES=1
TOPLEVEL=U21
FAMILY=Xilinx6x COOLRUNNER
DEVICE=r3384xlTQ144
SPEED=-7
FSM_ENCODE=
PACK_IO_REGISTERS=
SIMOUTFORM=2
AUTO_CLOSE_GUI=0
USE_DEF_UCF_FILE=1
UCF_FILENAME=C:\Projects\genosensor\2g\CPLDs\Encoder check\encoder\src\U21.xcf
XST_INCLUDE_PATH=C:/Projects/genosensor/ESP 2003/design/Baby/CPLD/Core/U4/U4/src
Show_Optimization_Goal=1
Show_Optimization_Effort=0
Show_Keep_Hierarchy=1
Show_FSM_Encoding_Algorithm=Auto
Show_Mux_Extraction=0
Show_Resource_Sharing=1
Show_Add_IO_Buffer=1
Show_Equivalent_Register_Removal=1
Show_Clock_Enable=1
Show_Macro_Generator=Auto
Show_Macro_Preserve=1
Show_Xor_Preserve=1
Show_Wysiwyg=0
Show_JobDescription=JobDesc1
Show_IncludeInputFiles=*.*
Show_ExcludeInputFiles=log*.*:implement*.*
Show_IgnoreUserConstraints=1
Show_HierarchySeparator=_
Show_BusDelimiter=<>
Show_GenerateRtlSchematic=Yes
Show_CaseVhdl=Maintain
Show_RomStyle=Auto
JOB_DESCRIPTION=JobDesc1
SERVERFARM_INCLUDE_INPUT_FILES=*.*
SERVERFARM_EXCLUDE_INPUT_FILES=log*.*:implement*.*
LAST_RUN=1080052043
OUTPUT_NETLIST=c:\Projects\genosensor\2g\CPLDs\Encoder check\encoder\synthesis\U21.ngc

[SIM.TIME]
SDF_PATH=
TOPLEVEL=glbl U21_TB_tsim
FJD=TimingSimJob1
FST=-all
SERVERFARM_INCLUDE_INPUT_FILES=*.*
SERVERFARM_EXCLUDE_INPUT_FILES=log\*.*
OPTION=0
SDF_TYPE=1
SDF_REGION=
SDF_REGIONAUTO=1
WAVEFORMS={src\rev1 test.awf}
DEFWAVE=1

[HierarchyViewer]
SortInfo=u
HierarchyInformation=
ShowHide=ShowTopLevel
Selected=

[sdf.vm.U4_TB]
SdfNoWarn=0
IVG=0
0=IMPLEMENT\TIME_SIM.SDF| /U1, Average, No

[sdf.vmm.U4 glbl]
0=IMPLEMENT\TIME_SIM.SDF| /U4, Average, Yes
SdfNoWarn=0
IVG=0

[sdf.vm.U4]
0=IMPLEMENT\TIME_SIM.SDF| /, Average, No
SdfNoWarn=0
IVG=0

[sdf.vm.glbl]
SdfNoWarn=0
IVG=0

[sdf.vmm.U4_TB glbl]
0=IMPLEMENT\TIME_SIM.SDF| /U4_TB/U1, Average, No
SdfNoWarn=0
IVG=0

[SIM.FUNC]
FJD=FunctionalSimJob1
FST=-all
OPTION=0
SERVERFARM_INCLUDE_INPUT_FILES=*.*
SERVERFARM_EXCLUDE_INPUT_FILES=log\*.*:synthesis\*.*:implement\*.*
TOPLEVEL=U4_TB
WAVEFORMS={src\rev1 test.awf}
DEFWAVE=0

[sdf.vmm.U4_TB_tsim glbl]
0=IMPLEMENT\TIME_SIM.SDF| /U4_TB_tsim/U1, Average, No
SdfNoWarn=0
IVG=0

[sdf.vma.All-Verilog]
0=IMPLEMENT\TIME_SIM.SDF| /U4, Average, No
1=IMPLEMENT\TIME_SIM.SDF| /U4_TB/U1, Average, No
2=IMPLEMENT\TIME_SIM.SDF| /U4_TB_tsim/U1, Average, No
SdfNoWarn=0
IVG=0

[sdf.vm.U4_TB_tsim]
0=IMPLEMENT\TIME_SIM.SDF| /U1, Average, No
SdfNoWarn=0
IVG=0

[sdf.vm.MSP]
SdfNoWarn=0
IVG=0

[sdf.vmm.U4]
0=IMPLEMENT\TIME_SIM.SDF| /, Average, No
SdfNoWarn=0
IVG=0

[sdf.vm.U21]
SdfNoWarn=0
IVG=0
0=IMPLEMENT\TIME_SIM.SDF| /, Average, No

[sdf.vmm.glbl U21_TB_tsim]
0=IMPLEMENT\TIME_SIM.SDF| /U21_TB_tsim/U1, Average, No
SdfNoWarn=0
IVG=0

[sdf.vmm.U21 glbl]
0=IMPLEMENT\TIME_SIM.SDF| /U21, Average, No
SdfNoWarn=0
IVG=0

[Groups]
timing=1

[Library]
encoder=.\encoder.LIB
encoder_timing=.\encoder_timing\encoder_timing.LIB

[Files]
/Design Notes.txt=-1
/MSP_vectors.txt=-1
/U21.xcf=-1
/U21.ucf=-1
/U21.bde=-1
/U21AddressMap.v=-1
/U21AddDecode.v=-1
/Servos.bde=-1
/MISCouts.v=-1
/PWRreg.v=-1
/Lswitch.v=-1
/PWMcontrol.bde=-1
/PWMtranslator.v=-1
/I2Cfix.bde=-1
/I2CAddress.v=-1
/Qdecode.asf=-1
/counter.v=-1
/holdreg.v=-1
/Interface.v=-1
/HomeConfig.v=-1
/MSP.v=-1
/negdetect.v=-1
/BitCounter.v=-1
/Interrupt.v=-1
/interface test.awf=-1
/Waveform Editor 3.awf=-1
/Time sim start 1.awf=-1
/time_sim.awf=-1
/tim_sim2.awf=-1
/U21_TB.bde=-1
/U21_TB_tsim.bde=-1
/dwarfcore.h=-1
/u21_tb_tsim.awf=-1
/Waveform Editor 1.awf=-1
/Waveform Editor 5.awf=-1
/MSP_vectors old.txt=-1
/rev1 test.awf=-1
/reader.bde=-1
/EncoderEngine.asf=-1
/shifter.v=-1
/DAVctl.v=-1
timing/\IMPLEMENT\TIME_SIM.V=-1
timing/\IMPLEMENT\TIME_SIM.SDF=-1
timing/\implement\glbl.v=-1

[Files.Data]
.\src\Design Notes.txt=Text File
.\src\MSP_vectors.txt=Text File
.\src\U21.xcf=External File
.\src\U21.ucf=External File
.\src\U21.bde=Block Diagram
.\src\U21AddressMap.v=Verilog Source Code
.\src\U21AddDecode.v=Verilog Source Code
.\src\Servos.bde=Block Diagram
.\src\MISCouts.v=Verilog Source Code
.\src\PWRreg.v=Verilog Source Code
.\src\Lswitch.v=Verilog Source Code
.\src\PWMcontrol.bde=Block Diagram
.\src\PWMtranslator.v=Verilog Source Code
.\src\I2Cfix.bde=Block Diagram
.\src\I2CAddress.v=Verilog Source Code
.\src\Qdecode.asf=State Diagram
.\src\counter.v=Verilog Source Code
.\src\holdreg.v=Verilog Source Code
.\src\Interface.v=Verilog Source Code
.\src\HomeConfig.v=Verilog Source Code
.\src\MSP.v=Verilog Source Code
.\src\negdetect.v=Verilog Source Code
.\src\BitCounter.v=Verilog Source Code
.\src\Interrupt.v=Verilog Source Code
.\src\interface test.awf=Waveform File
.\src\Waveform Editor 3.awf=Waveform File
.\src\Time sim start 1.awf=Waveform File
.\src\time_sim.awf=Waveform File
.\src\tim_sim2.awf=Waveform File
.\src\U21_TB.bde=Block Diagram
.\src\U21_TB_tsim.bde=Block Diagram
.\src\dwarfcore.h=C++ File
.\src\u21_tb_tsim.awf=Waveform File
.\src\Waveform Editor 1.awf=Waveform File
.\src\Waveform Editor 5.awf=Waveform File
.\src\MSP_vectors old.txt=Text File
.\src\rev1 test.awf=Waveform File
.\src\reader.bde=Block Diagram
.\src\EncoderEngine.asf=State Diagram
.\src\shifter.v=Verilog Source Code
.\src\DAVctl.v=Verilog Source Code
.\IMPLEMENT\TIME_SIM.V=VERILOG SOURCE CODE
.\IMPLEMENT\TIME_SIM.SDF=SDF FILE
.\implement\glbl.v=VERILOG SOURCE CODE


[file_out:/Servos.bde]
/\compile\Servos.v=-1

[file_out:/PWMcontrol.bde]
/\compile\PWMcontrol.v=-1

[file_out:/I2Cfix.bde]
/\compile\I2Cfix.v=-1

[file_out:/Qdecode.asf]
/\compile\Qdecode.v=-1

[file_out:/U21_TB.bde]
/\compile\U21_TB.v=-1

[file_out:/U21_TB_tsim.bde]
/\compile\U21_TB_tsim.v=-1

[file_out:/reader.bde]
/\compile\reader.v=-1

[file_out:/EncoderEngine.asf]
/\compile\EncoderEngine.v=-1

[file_out:/U21.bde]
/\compile\U21.v=-1