//--------------------------------------------------------------------------------------------------
//
// Title       : BitCounter
// Design      : U4
// Author      : mbari###
// Company     : MBARI
//
//-------------------------------------------------------------------------------------------------
//
// File        : c:\projects\genosensor\2g\cplds\core\u4\src\BitCounter.v
// Generated   : Fri Feb 20 16:17:40 2004
// From        : interface description file
// By          : Itf2Vhdl ver. 1.20
//
//-------------------------------------------------------------------------------------------------
//
// Description : 
//
//-------------------------------------------------------------------------------------------------
`timescale 1ps / 1ps

//{{ Section below this comment is automatically maintained
//   and may be overwritten
//{module {BitCounter}}
module BitCounter ( outDATA ,NegInc ,SCLreset ,Mclk ,SCLenable ,Inc ,DriveSCL ,NegSCL ,DCORI2CCNTr ,SCLint );

input Inc ;
wire Inc ;
input NegSCL ;
wire NegSCL ;
input NegInc ;
wire NegInc ;
input DCORI2CCNTr ;
wire DCORI2CCNTr ;
input SCLreset ;
wire SCLreset ;
input Mclk ;
wire Mclk ;

output SCLenable ;
wire SCLenable ;
output [7:0] outDATA ;
wire [7:0] outDATA ;
output SCLint ;
wire SCLint ;

inout DriveSCL ;
wire DriveSCL ;

//}} End of automatically maintained section

// -- Enter your statements here -- //

reg [5:0] counterr;

assign SCLint = (counterr == 6'b0) ? 1'b1 : 1'b0;

assign SCLenable = (counterr == 6'b0) ? 1'b1 : 1'b0; 

assign DriveSCL = (SCLenable) ? 1'b0 : 1'bz;

assign outDATA = (DCORI2CCNTr) ? {2'b0,counterr} : 8'bz;

always @ (posedge Mclk)
	begin  
//		if (SCLreset) counterr <= 6'd9;  //reset to 10 which releases SCL and prepares for counting
//		else
		case ({SCLreset,Inc,NegInc,NegSCL})
			4'b1000,
			4'b1001,
			4'b1010,
			4'b1011 : counterr <= 6'd10;   //reset when Reset high
			4'b1100,
			4'b1101,
			4'b1110,
			4'b1111 : counterr <= 6'd9;   //reset when Reset high
			4'b0000,
			4'b0100 : counterr <= counterr; //do nothing condition
			4'b0001,
			4'b0101 : counterr <= ((counterr == 6'b0) ? 6'b0 : (counterr - 6'd1));  //subtract one	if not 0
			4'b0010,
			4'b0110 : counterr <= counterr + 6'd9; //add 9 more
			4'b0011,
			4'b0111: counterr <= counterr + 6'd8; //add 9 , subtract 1
	 	endcase
	end

endmodule