//--------------------------------------------------------------------------------------------------
//
// Title       : Lswitch
// Design      : U4
// Author      : mbari###
// Company     : MBARI
//
//-------------------------------------------------------------------------------------------------
//
// File        : c:\Projects\genosensor\2g\CPLDs\Core\U4\src\Lswitch.v
// Generated   : Wed Dec 17 14:13:49 2003
// From        : interface description file
// By          : Itf2Vhdl ver. 1.20
//
//-------------------------------------------------------------------------------------------------
//
// Description : 
//
//-------------------------------------------------------------------------------------------------
`timescale 1ps / 1ps

//{{ Section below this comment is automatically maintained
//   and may be overwritten
//{module {Lswitch}}
module Lswitch ( DCORIFGr ,DIR1 ,inDATA ,RLS0 ,outDATA ,RLS1 ,Reset ,fBRK0 ,DCORIFGw ,Brake0 ,FLS0 ,fBRK1 ,Brake1 ,FLS1 ,Mclk ,LSwitchInt ,Home0 ,Home1 ,DCORLIMITSr ,DIR0 );

input DCORIFGr ;
wire DCORIFGr ;
input DIR1 ;
wire DIR1 ;
input [7:0] inDATA ;
wire [7:0] inDATA ;
input RLS0 ;
wire RLS0 ;
input RLS1 ;
wire RLS1 ;
input Reset ;
wire Reset ;
input DCORIFGw ;
wire DCORIFGw ;
input Brake0 ;
wire Brake0 ;
input FLS0 ;
wire FLS0 ;
input Brake1 ;
wire Brake1 ;
input FLS1 ;
wire FLS1 ;
input Mclk ;
wire Mclk ;
input Home0 ;
wire Home0 ;
input Home1 ;
wire Home1 ;
input DCORLIMITSr ;
wire DCORLIMITSr ;
input DIR0 ;
wire DIR0 ;

output LSwitchInt ;
wire LSwitchInt ;
output [7:0] outDATA ;
wire [7:0] outDATA ;
output fBRK0 ;
wire fBRK0 ;
output fBRK1 ;
wire fBRK1 ;

//}} End of automatically maintained section

// -- Enter your statements here -- //						 

reg DCORIFG;
reg fBRK0r,fBRK1r;
wire trip0, trip1;

assign outDATA = (DCORLIMITSr) ?  {fBRK1r, Home1, FLS1, RLS1, fBRK0r, Home0, FLS0, RLS0} : 8'bz;

assign trip1 =  ((DIR1 & !FLS1) | (!DIR1 & !RLS1));
assign trip0 =  ((DIR0 & !FLS0) | (!DIR0 & !RLS0));

assign fBRK1 = fBRK1r;
assign fBRK0 = fBRK0r;

assign LSwitchInt = DCORIFG;

always @ (posedge Mclk)
	begin
		if (Reset) DCORIFG <= 1'b0;
		else 
			begin
				if 	(trip1 | trip0) DCORIFG <= 1'b1; //This first so that flag cannot begin reset uptil problem cleared
				else if (DCORIFGw) DCORIFG <= inDATA[4];
				else DCORIFG <= DCORIFG;
			end
	end							
	
always @ (posedge Mclk)
	begin
		if (Reset) {fBRK1r, fBRK0r} <= 2'b0;
		else
			begin
				if (trip1) fBRK1r <= 1'b1;  //apply brake
				else 
					if (Brake1) fBRK1r <= 1'b0;   //release if manual brake applied 
					else fBRK1r <= fBRK1r;    ///leave as is.

				if (trip0) fBRK0r <= 1'b1;  //apply brake
				else 
					if (Brake0) fBRK0r <= 1'b0;   //release if manual brake applied 
					else fBRK0r <= fBRK0r;    ///leave as is.
			end
	end
endmodule