//--------------------------------------------------------------------------------------------------
//
// Title       : reader
// Design      : encoder
// Author      : SJensen
// Company     : MBARI
//
//-------------------------------------------------------------------------------------------------
//
// File        : c:\Projects\genosensor\2g\CPLDs\Encoder_check\encoder\compile\reader.v
// Generated   : Wed Mar 24 12:36:02 2004
// From        : c:\Projects\genosensor\2g\CPLDs\Encoder_check\encoder\src\reader.bde
// By          : Bde2Verilog ver. 2.01
//
//-------------------------------------------------------------------------------------------------
//
// Description : 
//
//-------------------------------------------------------------------------------------------------

// synopsys translate_off
`ifdef _VCP
`else
`define library(a,b)
`endif
// synopsys translate_on


// ---------- Design Unit Header ---------- //
`timescale 1ns / 1ns


module reader (Mclk,RVALVECTLw,RVALVEHIGHr,RVALVELOWr,RVALVESTATr,Reset,data,SSclk,outDATA) ;

// ------------ Port declarations --------- //
input Mclk;
wire Mclk;
input RVALVECTLw;
wire RVALVECTLw;
input RVALVEHIGHr;
wire RVALVEHIGHr;
input RVALVELOWr;
wire RVALVELOWr;
input RVALVESTATr;
wire RVALVESTATr;
input Reset;
wire Reset;
input data;
wire data;
output SSclk;
wire SSclk;
output [7:0] outDATA;
wire [7:0] outDATA;

// ----------- Signal declarations -------- //
wire NET1330;
wire NET843;
wire [5:0] SSclkb;

// -------- Component instantiations -------//

EncoderEngine U3
(
	.DAV(NET1330),
	.Mclk(Mclk),
	.Reset(Reset),
	.SSclkb(SSclkb),
	.data(data),
	.shift(NET843),
	.start(RVALVECTLw)
);



Shifter U4
(
	.Mclk(Mclk),
	.Pdata(outDATA),
	.RVALVEHIGHr(RVALVEHIGHr),
	.RVALVELOWr(RVALVELOWr),
	.Reset(Reset),
	.data(data),
	.shift(NET843)
);



DAVctl U5
(
	.DAVin(NET1330),
	.Pdata(outDATA),
	.RVALVESTATr(RVALVESTATr)
);



// ----------- Terminals assignment --------//
//		   ---- Output terminals ---        //
assign SSclk = SSclkb[1];

endmodule 
