I 000051 55 4788 1083358828894 ClkDivider (_unit VERILOG 6.349C.6.256 (ClkDivider 0 25 (ClkDivider 0 25 )) (_version v32) (_time 1083358828831 2004.04.30 14:00:28) (_source (\./src/clkdivider.v\ VERILOG (\./src/clkdivider.v\ VERILOG))) (_use (std(standard))(vl(verilog_logic))) (_base (E 8)) (_entity (_time 1083358828831) (_use ) ) (_timescale 1ps 1ps) (_parameters dbg accs ) (_attribute nb_assign ) (_object (_type (_internal ~vector~0 0 47 (_array ~bit ((_uto (i 0) (i 0)))))) (_generic (_internal divisor ~vector~0 0 47 \4'd3\ (_entity -1 (_constant \4'd3\)))) (_type (_internal ~vector~1 0 48 (_array ~bit ((_uto (i 0) (i 0)))))) (_generic (_internal bits ~vector~1 0 48 \4'd9\ (_entity -1 (_constant \4'd9\)))) (_port (_internal CE ~wire 0 25 (_architecture (_out ))) (_net ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign)) (_port (_internal DAV ~wire 0 25 (_architecture (_out ))) (_net ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign)) (_port (_internal Reset ~wire 0 25 (_architecture (_in ))) (_net ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign)) (_port (_internal Shift ~wire 0 25 (_architecture (_out ))) (_net ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign)) (_port (_internal Start ~wire 0 25 (_architecture (_in ))) (_net ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign)) (_port (_internal Eclk ~wire 0 25 (_architecture (_out ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign)) (_port (_internal Mclk ~wire 0 25 (_architecture (_in ))) (_net ) (_nonbaction) (_noforceassign)) (_signal (_internal SS ~reg 0 50 (_architecture (_uni ))) (_reg ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign)) (_type (_internal ~[3:0]reg~ 0 51 (_array ~reg ((_downto (i 3) (i 0)))))) (_signal (_internal divider ~[3:0]reg~ 0 51 (_architecture (_uni ))) (_reg ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign)) (_signal (_internal CEr ~reg 0 52 (_architecture (_uni ))) (_reg ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign)) (_signal (_internal BitCounter ~[3:0]reg~ 0 53 (_architecture (_uni ))) (_reg ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign)) (_signal (_internal Eclkr ~reg 0 54 (_architecture (_uni ))) (_reg ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign)) (_signal (_internal Stop ~wire 0 55 (_architecture (_uni ))) (_net ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign)) (_signal (_internal DAVr ~reg 0 56 (_architecture (_uni ))) (_reg ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign)) (_subprogram ) (_type (_external ~wire (vl verilog_logic wire))) (_type (_external ~reg (vl verilog_logic reg))) (_type (_external ~event (vl verilog_logic event))) (_type (_external ~wand (vl verilog_logic wand))) (_type (_external ~wor (vl verilog_logic wor))) (_type (_external ~tri1 (vl verilog_logic tri1))) (_type (_external ~tri0 (vl verilog_logic tri0))) (_type (_external ~trireg (vl verilog_logic trireg))) (_type (_external ~supply0 (vl verilog_logic supply0))) (_type (_external ~supply1 (vl verilog_logic supply1))) (_type (_external ~real (vl verilog_logic real))) (_type (_external ~realtime (vl verilog_logic realtime))) (_type (_external ~tri (vl verilog_logic tri))) (_type (_external ~triand (vl verilog_logic triand))) (_type (_external ~trior (vl verilog_logic trior))) (_type (_external ~bit (vl verilog_logic bit))) (_type (_external ~extstd.standard.integer (std standard integer))) (_type (_external ~extstd.standard.bit (std standard bit))) (_process (#ASSIGN#58_0 (_architecture 0 0 58 (_process (_simple) (_target(12)) (_sensitivity(5)(10)) ))) (#ASSIGN#59_1 (_architecture 1 0 59 (_process (_alias ((CE)(CEr)))(_simple) (_target(0)) (_sensitivity(9)) ))) (#ASSIGN#60_2 (_architecture 2 0 60 (_process (_alias ((Eclk)(Eclkr)))(_simple) (_target(5)) (_sensitivity(11)) ))) (#ASSIGN#61_3 (_architecture 3 0 61 (_process (_alias ((Shift)(Eclkr)(CEr)))(_simple) (_target(3)) (_sensitivity(11)(9)) ))) (#ASSIGN#62_4 (_architecture 4 0 62 (_process (_alias ((DAV)(DAVr)))(_simple) (_target(1)) (_sensitivity(13)) ))) (#ALWAYS#64_5 (_architecture 5 0 64 (_process (_target(7)(9)(13)) (_read(6)(2)(12)(4)(7)(8)(10)(5)(13)) ))) (#ALWAYS#79_6 (_architecture 6 0 79 (_process (_target(8)(11)(10)) (_read(6)(2)(7)(8)(11)(0)(10)) ))) (#INTERNAL#0_7 (_internal 7 0 0 (_process (_virtual)))) ) ) (_defparam ) (_model . ClkDivider 8 -1) ) V 000044 55 2704 1083358916691 top (_unit VERILOG 6.349C.6.256 (top 0 32 (top 0 32 )) (_version v32) (_time 1083358916628 2004.04.30 14:01:56) (_source (\./compile/top.v\ VERILOG (\./compile/top.v\ VERILOG))) (_use (std(standard))(vl(verilog_logic))) (_base (E 1)) (_entity (_time 1083358916628) (_use ) ) (_timescale 1ps 1ps) (_parameters dbg accs ) (_attribute ) (_object (_port (_internal Mclk ~wire 0 32 (_architecture (_in ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign)) (_port (_internal Reset ~wire 0 32 (_architecture (_in ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign)) (_port (_internal Start ~wire 0 32 (_architecture (_in ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign)) (_port (_internal CE ~wire 0 32 (_architecture (_out ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign)) (_port (_internal DAV ~wire 0 32 (_architecture (_out ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign)) (_port (_internal Eclk ~wire 0 32 (_architecture (_out ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign)) (_port (_internal Shift ~wire 0 32 (_architecture (_out ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign)) (_subprogram ) (_type (_external ~wire (vl verilog_logic wire))) (_type (_external ~reg (vl verilog_logic reg))) (_type (_external ~event (vl verilog_logic event))) (_type (_external ~wand (vl verilog_logic wand))) (_type (_external ~wor (vl verilog_logic wor))) (_type (_external ~tri1 (vl verilog_logic tri1))) (_type (_external ~tri0 (vl verilog_logic tri0))) (_type (_external ~trireg (vl verilog_logic trireg))) (_type (_external ~supply0 (vl verilog_logic supply0))) (_type (_external ~supply1 (vl verilog_logic supply1))) (_type (_external ~real (vl verilog_logic real))) (_type (_external ~realtime (vl verilog_logic realtime))) (_type (_external ~tri (vl verilog_logic tri))) (_type (_external ~triand (vl verilog_logic triand))) (_type (_external ~trior (vl verilog_logic trior))) (_type (_external ~bit (vl verilog_logic bit))) (_type (_external ~extstd.standard.integer (std standard integer))) (_type (_external ~extstd.standard.bit (std standard bit))) ) (_defparam ) (_scope ) (_instantiation U1 0 52 (_entity . ClkDivider) (_port ((CE) (CE)) ((DAV) (DAV)) ((Eclk) (Eclk)) ((Mclk) (Mclk)) ((Reset) (Reset)) ((Shift) (Shift)) ((Start) (Start)) ) (_strength) ) (_model . top 1 -1) ) V 000051 55 4934 1083360146316 ClkDivider (_unit VERILOG 6.349C.6.256 (ClkDivider 0 25 (ClkDivider 0 25 )) (_version v32) (_time 1083360146253 2004.04.30 14:22:26) (_source (\./src/clkdivider.v\ VERILOG (\./src/clkdivider.v\ VERILOG))) (_use (std(standard))(vl(verilog_logic))) (_base (E 8)) (_entity (_time 1083360146253) (_use ) ) (_timescale 1ps 1ps) (_parameters dbg accs ) (_attribute nb_assign ) (_object (_type (_internal ~vector~0 0 47 (_array ~bit ((_uto (i 0) (i 0)))))) (_generic (_internal divisor ~vector~0 0 47 \4'd3\ (_entity -1 (_constant \4'd3\)))) (_type (_internal ~vector~1 0 48 (_array ~bit ((_uto (i 0) (i 0)))))) (_generic (_internal bits ~vector~1 0 48 \4'd10\ (_entity -1 (_constant \4'd10\)))) (_port (_internal CE ~wire 0 25 (_architecture (_out ))) (_net ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign)) (_port (_internal DAV ~wire 0 25 (_architecture (_out ))) (_net ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign)) (_port (_internal Reset ~wire 0 25 (_architecture (_in ))) (_net ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign)) (_port (_internal Shift ~wire 0 25 (_architecture (_out ))) (_net ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign)) (_port (_internal Start ~wire 0 25 (_architecture (_in ))) (_net ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign)) (_port (_internal Eclk ~wire 0 25 (_architecture (_out ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign)) (_port (_internal Mclk ~wire 0 25 (_architecture (_in ))) (_net ) (_nonbaction) (_noforceassign)) (_signal (_internal SS ~reg 0 50 (_architecture (_uni ))) (_reg ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign)) (_type (_internal ~[3:0]reg~ 0 51 (_array ~reg ((_downto (i 3) (i 0)))))) (_signal (_internal divider ~[3:0]reg~ 0 51 (_architecture (_uni ))) (_reg ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign)) (_signal (_internal CEr ~reg 0 52 (_architecture (_uni ))) (_reg ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign)) (_signal (_internal BitCounter ~[3:0]reg~ 0 53 (_architecture (_uni ))) (_reg ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign)) (_signal (_internal Eclkr ~reg 0 54 (_architecture (_uni ))) (_reg ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign)) (_signal (_internal Stop ~wire 0 55 (_architecture (_uni ))) (_net ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign)) (_signal (_internal DAVr ~reg 0 56 (_architecture (_uni ))) (_reg ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign)) (_signal (_internal Shiftr ~reg 0 57 (_architecture (_uni ))) (_reg ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign)) (_subprogram ) (_type (_external ~wire (vl verilog_logic wire))) (_type (_external ~reg (vl verilog_logic reg))) (_type (_external ~event (vl verilog_logic event))) (_type (_external ~wand (vl verilog_logic wand))) (_type (_external ~wor (vl verilog_logic wor))) (_type (_external ~tri1 (vl verilog_logic tri1))) (_type (_external ~tri0 (vl verilog_logic tri0))) (_type (_external ~trireg (vl verilog_logic trireg))) (_type (_external ~supply0 (vl verilog_logic supply0))) (_type (_external ~supply1 (vl verilog_logic supply1))) (_type (_external ~real (vl verilog_logic real))) (_type (_external ~realtime (vl verilog_logic realtime))) (_type (_external ~tri (vl verilog_logic tri))) (_type (_external ~triand (vl verilog_logic triand))) (_type (_external ~trior (vl verilog_logic trior))) (_type (_external ~bit (vl verilog_logic bit))) (_type (_external ~extstd.standard.integer (std standard integer))) (_type (_external ~extstd.standard.bit (std standard bit))) (_process (#ASSIGN#59_0 (_architecture 0 0 59 (_process (_simple) (_target(12)) (_sensitivity(5)(10)) ))) (#ASSIGN#60_1 (_architecture 1 0 60 (_process (_alias ((CE)(CEr)))(_simple) (_target(0)) (_sensitivity(9)) ))) (#ASSIGN#61_2 (_architecture 2 0 61 (_process (_alias ((Eclk)(Eclkr)))(_simple) (_target(5)) (_sensitivity(11)) ))) (#ASSIGN#62_3 (_architecture 3 0 62 (_process (_alias ((Shift)(Shiftr)))(_simple) (_target(3)) (_sensitivity(14)) ))) (#ASSIGN#63_4 (_architecture 4 0 63 (_process (_alias ((DAV)(DAVr)))(_simple) (_target(1)) (_sensitivity(13)) ))) (#ALWAYS#65_5 (_architecture 5 0 65 (_process (_target(7)(9)(14)(13)) (_read(6)(2)(12)(4)(7)(8)(11)(10)(5)(13)) ))) (#ALWAYS#92_6 (_architecture 6 0 92 (_process (_target(8)(11)(10)) (_read(6)(2)(7)(8)(9)(11)(0)(10)) ))) (#INTERNAL#0_7 (_internal 7 0 0 (_process (_virtual)))) ) ) (_defparam ) (_model . ClkDivider 8 -1) )