[ClkDivider]
A/ClkDivider=22|./src/clkdivider.v|25|1*7587
B/ClkDivider=3*7491
P/~emb=330,618,942,1002
R=./src/clkdivider.v|25
S/clkdivider=S/ClkDivider 40|0|2*0

[top]
A/top=24|.\src\top.bde|10000|1*4839
B/top=3*7370
P/~emb=268,461,663,839
R=./compile/top.v|32

[~A]
./../../../../Encodertest/EncControl/compile/top.v_clkdivider.v=0*5400*6381
./../../../../Encodertest/EncControl/src/clkdivider.v=0*25925*26755
./src/clkdivider.v=0*20015*20781
LastVerilogToplevel=ClkDivider
ModifyID=121
Version=73

[~MFT]
0=39|0EncControl.mgf|26755|7777
1=17|1EncControl.mgf|7587|4839
2=0|2EncControl.mgf|0|0
3=17|3EncControl.mgf|7491|7370

[~U]
ClkDivider=12|0*24251||151
top=12|0*2845||144