[Project]
Current Flow=Multivendor
VCS=0
version=1
Current Config=compile

[Configurations]
compile=EncControl

[Library]
EncControl=.\EncControl.lib

[$LibMap$]
EncControl=.
Active_lib=

[Settings]
FLOW_TYPE=HDL
LANGUAGE=VERILOG
REFRESH_FLOW=1
SYNTH_TOOL=<none>
IMPL_TOOL=<none>
FAMILY=
FLOWTOOLS=ONLY_IMPL
FUNC_LIB=EncControl

[IMPLEMENTATION]
UCF=

[SIM.FUNC]
FJD=FunctionalSimJob1
FST=-all
OPTION=0
SERVERFARM_INCLUDE_INPUT_FILES=*.*
SERVERFARM_EXCLUDE_INPUT_FILES=log\*.*:synthesis\*.*:implement\*.*
TOPLEVEL=top
WAVEFORMS=
DEFWAVE=0

[Files]
/top.bde=-1
/clkdivider.v=-1
/EncoderControl.v=-1
/Waveform Editor 2.awf=-1

[Files.Data]
.\src\top.bde=Block Diagram
.\src\clkdivider.v=Verilog Source Code
.\src\EncoderControl.v=Verilog Source Code
.\src\Waveform Editor 2.awf=Waveform File

[file_out:/top.bde]
/\compile\top.v=-1

[HierarchyViewer]
SortInfo=u
HierarchyInformation=
ShowHide=ShowTopLevel
Selected=