I 000050 55 5810 1093622254894 AddDecode (_unit VERILOG 6.349C.6.256 (AddDecode 0 25 (AddDecode 0 25 )) (_version v32) (_time 1093622254596 2004.08.27 08:57:34) (_source (\./src/adddecode.v\ VERILOG (\./src/adddecode.v\ VERILOG))) (_use (std(standard))(vl(verilog_logic))) (_base (E 15)) (_entity (_time 1093622254596) (_use ) ) (_timescale 1ps 1ps) (_parameters dbg accs ) (_attribute ) (_object (_port (_internal Wslctc ~wire 0 25 (_architecture (_out ))) (_net ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign)) (_port (_internal Wslct5 ~wire 0 25 (_architecture (_out ))) (_net ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign)) (_port (_internal Wslct7 ~wire 0 25 (_architecture (_out ))) (_net ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign)) (_port (_internal AS ~wire 0 25 (_architecture (_in ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign)) (_port (_internal Wslct9 ~wire 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AddDecode 15 -1) ) I 000050 55 4827 1093622353769 Interface (_unit VERILOG 6.349C.6.256 (Interface 0 25 (Interface 0 25 )) (_version v32) (_time 1093622353659 2004.08.27 08:59:13) (_source (\./src/interface.v\ VERILOG (\./src/interface.v\ VERILOG))) (_use (std(standard))(vl(verilog_logic))) (_base (E 8)) (_entity (_time 1093622353659) (_use ) ) (_timescale 1ps 1ps) (_parameters dbg accs ) (_attribute nb_assign ) (_object (_type (_internal ~[7:0]wire~ 0 25 (_array ~wire ((_downto (i 7) (i 0)))))) (_port (_internal inDATA ~[7:0]wire~ 0 25 (_architecture (_out ))) (_net ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign)) (_port (_internal outDATA ~[7:0]wire~ 0 25 (_architecture (_in ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign)) (_port (_internal Reset ~wire 0 25 (_architecture (_in ))) (_net ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign)) (_port (_internal AS ~wire 0 25 (_architecture (_in ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign)) (_port (_internal AD ~[7:0]wire~ 0 25 (_architecture (_inout ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign)) (_port (_internal RD ~wire 0 25 (_architecture (_in ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign)) (_port (_internal Mclk ~wire 0 25 (_architecture (_in ))) (_net ) (_nonbaction) (_noforceassign)) (_port (_internal ASleading ~wire 0 25 (_architecture (_out ))) (_net ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign)) (_port (_internal WR ~wire 0 25 (_architecture (_in ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign)) (_port (_internal ADDR ~[7:0]wire~ 0 25 (_architecture (_out ))) (_net ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign)) (_type (_internal ~[7:0]reg~ 0 58 (_array ~reg ((_downto (i 7) (i 0)))))) (_signal (_internal ADDR_reg ~[7:0]reg~ 0 58 (_architecture (_uni ))) (_reg ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign)) (_signal (_internal AutoInc ~reg 0 66 (_architecture (_uni ))) (_reg ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign)) (_signal (_internal ASedge ~reg 0 68 (_architecture (_uni ))) (_reg ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign)) (_signal (_internal WRRDedge ~reg 0 70 (_architecture (_uni ))) (_reg ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign)) (_signal (_internal Enable_AD ~wire 0 74 (_architecture (_uni ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign)) (_signal (_internal ADDR_in_Range ~wire 0 75 (_architecture (_uni ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign)) (_subprogram ) (_type (_external ~wire (vl verilog_logic wire))) (_type (_external ~reg (vl verilog_logic reg))) (_type (_external ~event (vl verilog_logic event))) (_type (_external ~wand (vl verilog_logic wand))) (_type (_external ~wor (vl verilog_logic wor))) (_type (_external ~tri1 (vl verilog_logic tri1))) (_type (_external ~tri0 (vl verilog_logic tri0))) (_type (_external ~trireg (vl verilog_logic trireg))) (_type (_external ~supply0 (vl verilog_logic supply0))) (_type (_external ~supply1 (vl verilog_logic supply1))) (_type (_external ~real (vl verilog_logic real))) (_type (_external ~realtime (vl verilog_logic realtime))) (_type (_external ~tri (vl verilog_logic tri))) (_type (_external ~triand (vl verilog_logic triand))) (_type (_external ~trior (vl verilog_logic trior))) (_type (_external ~bit (vl verilog_logic bit))) (_type (_external ~extstd.standard.integer (std standard integer))) (_type (_external ~extstd.standard.bit (std standard bit))) (_process (#ASSIGN#79_0 (_architecture 0 0 79 (_process (_alias ((ADDR)(ADDR_reg)))(_simple) (_target(9)) (_sensitivity(10)) ))) (#ASSIGN#82_1 (_architecture 1 0 82 (_process (_alias ((Enable_AD)(WR)(RD)(ADDR_in_Range)))(_simple) (_target(14)) (_sensitivity(8)(5)(15)) ))) (#ASSIGN#83_2 (_architecture 2 0 83 (_process (_simple) (_target(15)) (_sensitivity(10)) ))) (#ASSIGN#84_3 (_architecture 3 0 84 (_process (_alias ((ASleading)(AS)(ASedge)))(_simple) (_target(7)) (_sensitivity(3)(12)) ))) (#ASSIGN#91_4 (_architecture 4 0 91 (_process (_alias ((inDATA)(AD)))(_simple) (_target(0)) (_sensitivity(4)) ))) (#ASSIGN#92_5 (_architecture 5 0 92 (_process (_simple) (_target(4)) (_sensitivity(14)(1)) ))) (#ALWAYS#94_6 (_architecture 6 0 94 (_process (_target(12)(13)(10)(11)) (_read(6)(3)(8)(5)(2)(7)(4)(13)(11)(15)(10)) ))) ) ) (_defparam ) (_model . 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GalvRelay 4 -1) ) V 000059 55 3324 1093637910862 TransceiverControl (_unit VERILOG 6.349C.6.256 (TransceiverControl 0 25 (TransceiverControl 0 25 )) (_version v32) (_time 1093637910800 2004.08.27 13:18:30) (_source (\./src/transceivercontrol.v\ VERILOG (\./src/transceivercontrol.v\ VERILOG))) (_use (std(standard))(vl(verilog_logic))) (_base (E 4)) (_entity (_time 1093637910800) (_use ) ) (_timescale 1ps 1ps) (_parameters dbg accs ) (_attribute nb_assign ) (_object (_type (_internal ~[7:0]wire~ 0 25 (_array ~wire ((_downto (i 7) (i 0)))))) (_port (_internal inDATA ~[7:0]wire~ 0 25 (_architecture (_in ))) (_net ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign)) (_port (_internal PwrDwn ~[7:0]wire~ 0 25 (_architecture (_out ))) (_net ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign)) (_port (_internal Reset ~wire 0 25 (_architecture (_in ))) (_net ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign)) (_port (_internal SLPYEN ~wire 0 25 (_architecture (_in ))) (_net ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign)) (_port (_internal SLPYPD ~wire 0 25 (_architecture (_in ))) (_net ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign)) (_port (_internal Enable ~[7:0]wire~ 0 25 (_architecture (_out ))) (_net ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign)) (_port (_internal MCLK ~wire 0 25 (_architecture (_in ))) (_net ) (_nonbaction) (_noforceassign)) (_type (_internal ~[7:0]reg~ 0 47 (_array ~reg ((_downto (i 7) (i 0)))))) (_signal (_internal en ~[7:0]reg~ 0 47 (_architecture (_uni ))) (_reg ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign)) (_signal (_internal pd ~[7:0]reg~ 0 48 (_architecture (_uni ))) (_reg ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign)) (_subprogram ) (_type (_external ~wire (vl verilog_logic wire))) (_type (_external ~reg (vl verilog_logic reg))) (_type (_external ~event (vl verilog_logic event))) (_type (_external ~wand (vl verilog_logic wand))) (_type (_external ~wor (vl verilog_logic wor))) (_type (_external ~tri1 (vl verilog_logic tri1))) (_type (_external ~tri0 (vl verilog_logic tri0))) (_type (_external ~trireg (vl verilog_logic trireg))) (_type (_external ~supply0 (vl verilog_logic supply0))) (_type (_external ~supply1 (vl verilog_logic supply1))) (_type (_external ~real (vl verilog_logic real))) (_type (_external ~realtime (vl verilog_logic realtime))) (_type (_external ~tri (vl verilog_logic tri))) (_type (_external ~triand (vl verilog_logic triand))) (_type (_external ~trior (vl verilog_logic trior))) (_type (_external ~bit (vl verilog_logic bit))) (_type (_external ~extstd.standard.integer (std standard integer))) (_type (_external ~extstd.standard.bit (std standard bit))) (_process (#ASSIGN#50_0 (_architecture 0 0 50 (_process (_alias ((PwrDwn)(pd)))(_simple) (_target(1)) (_sensitivity(8)) ))) (#ASSIGN#51_1 (_architecture 1 0 51 (_process (_alias ((Enable)(en)))(_simple) (_target(5)) (_sensitivity(7)) ))) (#ALWAYS#53_2 (_architecture 2 0 53 (_process (_target(8)(7)) (_read(6)(2)(4)(0)(3)) ))) ) ) (_defparam ) (_model . TransceiverControl 4 -1) ) V 000050 55 4496 1093874200505 GalvRelay (_unit VERILOG 6.349C.6.256 (GalvRelay 0 25 (GalvRelay 0 25 )) (_version v32) (_time 1093874200442 2004.08.30 06:56:40) (_source (\./src/galvrelay.v\ VERILOG (\./src/galvrelay.v\ VERILOG))) (_use (std(standard))(vl(verilog_logic))) (_base (E 4)) (_entity (_time 1093874200442) (_use ) ) (_timescale 1ps 1ps) (_parameters dbg accs ) (_attribute nb_assign ) (_object (_port (_internal CONcon0 ~wire 0 25 (_architecture (_out ))) (_net ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign)) (_port (_internal CONcon1 ~wire 0 25 (_architecture (_out ))) (_net ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign)) (_type (_internal ~[7:0]wire~ 0 25 (_array ~wire ((_downto (i 7) (i 0)))))) (_port (_internal inDATA ~[7:0]wire~ 0 25 (_architecture (_in ))) (_net ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign)) (_port (_internal CONmodem ~wire 0 25 (_architecture (_out ))) (_net ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign)) (_port (_internal CONcon2 ~wire 0 25 (_architecture (_out ))) (_net ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign)) (_port (_internal CONextr ~wire 0 25 (_architecture (_out ))) (_net ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign)) (_port (_internal Reset ~wire 0 25 (_architecture (_in ))) (_net ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign)) (_port (_internal SLPYLP ~wire 0 25 (_architecture (_in ))) (_net ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign)) (_port (_internal MCLK ~wire 0 25 (_architecture (_in ))) (_net ) (_nonbaction) (_noforceassign)) (_port (_internal SLPYCON ~wire 0 25 (_architecture (_in ))) (_net ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign)) (_port (_internal LOOPcon0 ~wire 0 25 (_architecture (_out ))) (_net ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign)) (_port (_internal LOOPcon1 ~wire 0 25 (_architecture (_out ))) (_net ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign)) (_port (_internal LOOPmodem ~wire 0 25 (_architecture (_out ))) (_net ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign)) (_port (_internal LOOPcon2 ~wire 0 25 (_architecture (_out ))) (_net ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign)) (_port (_internal LOOPextr ~wire 0 25 (_architecture (_out ))) (_net ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign)) (_type (_internal ~[4:0]reg~ 0 63 (_array ~reg ((_downto (i 4) (i 0)))))) (_signal (_internal connect ~[4:0]reg~ 0 63 (_architecture (_uni ))) (_reg ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign)) (_signal (_internal loop ~[4:0]reg~ 0 64 (_architecture (_uni ))) (_reg ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign)) (_subprogram ) (_type (_external ~wire (vl verilog_logic wire))) (_type (_external ~reg (vl verilog_logic reg))) (_type (_external ~event (vl verilog_logic event))) (_type (_external ~wand (vl verilog_logic wand))) (_type (_external ~wor (vl verilog_logic wor))) (_type (_external ~tri1 (vl verilog_logic tri1))) (_type (_external ~tri0 (vl verilog_logic tri0))) (_type (_external ~trireg (vl verilog_logic trireg))) (_type (_external ~supply0 (vl verilog_logic supply0))) (_type (_external ~supply1 (vl verilog_logic supply1))) (_type (_external ~real (vl verilog_logic real))) (_type (_external ~realtime (vl verilog_logic realtime))) (_type (_external ~tri (vl verilog_logic tri))) (_type (_external ~triand (vl verilog_logic triand))) (_type (_external ~trior (vl verilog_logic trior))) (_type (_external ~bit (vl verilog_logic bit))) (_type (_external ~extstd.standard.integer (std standard integer))) (_type (_external ~extstd.standard.bit (std standard bit))) (_process (#ASSIGN#66_0 (_architecture 0 0 66 (_process (_simple) (_target(3)(5)(4)(1)(0)) (_sensitivity(15)) ))) (#ASSIGN#67_1 (_architecture 1 0 67 (_process (_simple) (_target(12)(14)(13)(11)(10)) (_sensitivity(16)) ))) (#ALWAYS#69_2 (_architecture 2 0 69 (_process (_target(15)(16)) (_read(8)(6)(9)(2(d_7_6))(2(d_2_0))(7)) ))) ) ) (_defparam ) (_model . GalvRelay 4 -1) ) V 000051 55 5203 1093875872630 PwrControl (_unit VERILOG 6.349C.6.256 (PwrControl 0 25 (PwrControl 0 25 )) (_version v32) (_time 1093875872551 2004.08.30 07:24:32) (_source (\./src/pwrcontrol.v\ VERILOG (\./src/pwrcontrol.v\ VERILOG))) (_use (std(standard))(vl(verilog_logic))) (_base (E 4)) (_entity (_time 1093875872551) (_use ) ) (_timescale 1ps 1ps) (_parameters dbg accs ) (_attribute nb_assign ) (_object (_port (_internal SLPYPWR ~wire 0 25 (_architecture (_in ))) (_net ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign)) (_port (_internal AM0Status ~wire 0 25 (_architecture (_in ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign)) (_port (_internal AM1Status ~wire 0 25 (_architecture (_in ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign)) (_port (_internal Reset ~wire 0 25 (_architecture (_in ))) (_net ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign)) (_port (_internal AM2Status ~wire 0 25 (_architecture (_in ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign)) (_port (_internal ModemEN ~wire 0 25 (_architecture (_out ))) (_net ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign)) (_port (_internal DwarfEN ~wire 0 25 (_architecture (_out ))) (_net ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign)) (_port (_internal ExternalStatus ~wire 0 25 (_architecture (_in ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign)) (_port (_internal MCLK ~wire 0 25 (_architecture (_in ))) (_net ) (_nonbaction) (_noforceassign)) (_port (_internal SystemStatus ~wire 0 25 (_architecture (_in ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign)) (_port (_internal SLPYSTATUS ~wire 0 25 (_architecture (_in ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign)) (_port (_internal CameraStatus ~wire 0 25 (_architecture (_in ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign)) (_type (_internal ~[7:0]wire~ 0 25 (_array ~wire ((_downto (i 7) (i 0)))))) (_port (_internal inDATA ~[7:0]wire~ 0 25 (_architecture (_in ))) (_net ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign)) (_port (_internal AM0EN ~wire 0 25 (_architecture (_out ))) (_net ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign)) (_port (_internal outDATA ~[7:0]wire~ 0 25 (_architecture (_out ))) (_net ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign)) (_port (_internal AM1EN ~wire 0 25 (_architecture (_out ))) (_net ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign)) (_port (_internal AM2EN ~wire 0 25 (_architecture (_out ))) (_net ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign)) (_port (_internal ModemStatus ~wire 0 25 (_architecture (_in ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign)) (_port (_internal ExternalEN ~wire 0 25 (_architecture (_out ))) (_net ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign)) (_port (_internal SystemEN ~wire 0 25 (_architecture (_out ))) (_net ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign)) (_port (_internal CameraEN ~wire 0 25 (_architecture (_out ))) (_net ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign)) (_type (_internal ~[7:0]reg~ 0 75 (_array ~reg ((_downto (i 7) (i 0)))))) (_signal (_internal Enable ~[7:0]reg~ 0 75 (_architecture (_uni ))) (_reg ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign)) (_subprogram ) (_type (_external ~wire (vl verilog_logic wire))) (_type (_external ~reg (vl verilog_logic reg))) (_type (_external ~event (vl verilog_logic event))) (_type (_external ~wand (vl verilog_logic wand))) (_type (_external ~wor (vl verilog_logic wor))) (_type (_external ~tri1 (vl verilog_logic tri1))) (_type (_external ~tri0 (vl verilog_logic tri0))) (_type (_external ~trireg (vl verilog_logic trireg))) (_type (_external ~supply0 (vl verilog_logic supply0))) (_type (_external ~supply1 (vl verilog_logic supply1))) (_type (_external ~real (vl verilog_logic real))) (_type (_external ~realtime (vl verilog_logic realtime))) (_type (_external ~tri (vl verilog_logic tri))) (_type (_external ~triand (vl verilog_logic triand))) (_type (_external ~trior (vl verilog_logic trior))) (_type (_external ~bit (vl verilog_logic bit))) (_type (_external ~extstd.standard.integer (std standard integer))) (_type (_external ~extstd.standard.bit (std standard bit))) (_process (#ASSIGN#77_0 (_architecture 0 0 77 (_process (_simple) (_target(5)(18)(16)(15)(13)(20)(6)(19)) (_sensitivity(21)) ))) (#ASSIGN#78_1 (_architecture 1 0 78 (_process (_simple) (_target(14)) (_sensitivity(10)(17)(7)(4)(2)(1)(11)(9)) ))) (#ALWAYS#80_2 (_architecture 2 0 80 (_process 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PwrControl 4 -1) ) I 000049 55 3856 1093876808739 UARTaddr (_unit VERILOG 6.349C.6.256 (UARTaddr 0 25 (UARTaddr 0 25 )) (_version v32) (_time 1093876808676 2004.08.30 07:40:08) (_source (\./src/uartaddr.v\ VERILOG (\./src/uartaddr.v\ VERILOG))) (_use (std(standard))(vl(verilog_logic))) (_base (E 8)) (_entity (_time 1093876808676) (_use ) ) (_timescale 1ps 1ps) (_parameters dbg accs ) (_attribute ) (_object (_type (_internal ~[7:0]wire~ 0 25 (_array ~wire ((_downto (i 7) (i 0)))))) (_port (_internal inDATA ~[7:0]wire~ 0 25 (_architecture (_in ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign)) (_port (_internal WR ~wire 0 25 (_architecture (_in ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign)) (_port (_internal outDATA ~[7:0]wire~ 0 25 (_architecture (_out ))) (_net ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign)) (_port (_internal UARTcs ~wire 0 25 (_architecture (_out ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign)) (_port (_internal ADDR ~[7:0]wire~ 0 25 (_architecture (_in ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign)) (_port (_internal UIOW ~wire 0 25 (_architecture (_out ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign)) (_port (_internal RD ~wire 0 25 (_architecture (_in ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign)) (_port (_internal UDATA ~[7:0]wire~ 0 25 (_architecture (_inout ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign)) (_port (_internal UIOR ~wire 0 25 (_architecture (_out ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign)) (_port (_internal UARTaddr ~[7:0]wire~ 0 25 (_architecture (_out ))) (_net ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign)) (_subprogram ) (_type (_external ~wire (vl verilog_logic wire))) (_type (_external ~reg (vl verilog_logic reg))) (_type (_external ~event (vl verilog_logic event))) (_type (_external ~wand (vl verilog_logic wand))) (_type (_external ~wor (vl verilog_logic wor))) (_type (_external ~tri1 (vl verilog_logic tri1))) (_type (_external ~tri0 (vl verilog_logic tri0))) (_type (_external ~trireg (vl verilog_logic trireg))) (_type (_external ~supply0 (vl verilog_logic supply0))) (_type (_external ~supply1 (vl verilog_logic supply1))) (_type (_external ~real (vl verilog_logic real))) (_type (_external ~realtime (vl verilog_logic realtime))) (_type (_external ~tri (vl verilog_logic tri))) (_type (_external ~triand (vl verilog_logic triand))) (_type (_external ~trior (vl verilog_logic trior))) (_type (_external ~bit (vl verilog_logic bit))) (_type (_external ~extstd.standard.integer (std standard integer))) (_type (_external ~extstd.standard.bit (std standard bit))) (_process (#ASSIGN#55_0 (_architecture 0 0 55 (_process (_simple) (_target(9(d_7_4))) (_sensitivity(4(d_7_4))) ))) (#ASSIGN#56_1 (_architecture 1 0 56 (_process (_alias ((UARTaddr(d_3_0))(ADDR(d_3_0))))(_simple) (_target(9(d_3_0))) (_sensitivity(4(d_3_0))) ))) (#ASSIGN#59_2 (_architecture 2 0 59 (_process (_simple) (_target(3)) (_sensitivity(4(d_7_4))) ))) (#ASSIGN#62_3 (_architecture 3 0 62 (_process (_alias ((UIOR)(RD)(UARTcs)))(_simple) (_target(8)) (_sensitivity(6)(3)) ))) (#ASSIGN#63_4 (_architecture 4 0 63 (_process (_alias ((UIOW)(WR)(UARTcs)))(_simple) (_target(5)) (_sensitivity(1)(3)) ))) (#ASSIGN#67_5 (_architecture 5 0 67 (_process (_simple) (_target(7)) (_sensitivity(3)(5)(0)(8)) ))) (#ASSIGN#68_6 (_architecture 6 0 68 (_process (_simple) (_target(2)) (_sensitivity(3)(8)(7)) ))) ) ) (_defparam ) (_model . UARTaddr 8 -1) ) I 000050 55 2394 1093877049551 NegDetect (_unit VERILOG 6.349C.6.256 (NegDetect 0 25 (NegDetect 0 25 )) (_version v32) (_time 1093877049489 2004.08.30 07:44:09) (_source (\./src/negdetect.v\ VERILOG (\./src/negdetect.v\ VERILOG))) (_use (std(standard))(vl(verilog_logic))) (_base (E 3)) (_entity (_time 1093877049489) (_use ) ) (_timescale 1ps 1ps) (_parameters dbg accs ) (_attribute nb_assign ) (_object (_port (_internal Line ~wire 0 25 (_architecture (_in ))) (_net ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign)) (_port (_internal Ndetect ~wire 0 25 (_architecture (_out ))) (_net ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign)) (_port (_internal Mclk ~wire 0 25 (_architecture (_in ))) (_net ) (_nonbaction) (_noforceassign)) (_signal (_internal Line_last ~reg 0 39 (_architecture (_uni ))) (_reg ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign)) (_signal (_internal Ndetectr ~reg 0 40 (_architecture (_uni ))) (_reg ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign)) (_subprogram ) (_type (_external ~wire (vl verilog_logic wire))) (_type (_external ~reg (vl verilog_logic reg))) (_type (_external ~event (vl verilog_logic event))) (_type (_external ~wand (vl verilog_logic wand))) (_type (_external ~wor (vl verilog_logic wor))) (_type (_external ~tri1 (vl verilog_logic tri1))) (_type (_external ~tri0 (vl verilog_logic tri0))) (_type (_external ~trireg (vl verilog_logic trireg))) (_type (_external ~supply0 (vl verilog_logic supply0))) (_type (_external ~supply1 (vl verilog_logic supply1))) (_type (_external ~real (vl verilog_logic real))) (_type (_external ~realtime (vl verilog_logic realtime))) (_type (_external ~tri (vl verilog_logic tri))) (_type (_external ~triand (vl verilog_logic triand))) (_type (_external ~trior (vl verilog_logic trior))) (_type (_external ~bit (vl verilog_logic bit))) (_type (_external ~extstd.standard.integer (std standard integer))) (_type (_external ~extstd.standard.bit (std standard bit))) (_process (#ASSIGN#42_0 (_architecture 0 0 42 (_process (_alias ((Ndetect)(Ndetectr)))(_simple) (_target(1)) (_sensitivity(4)) ))) (#ALWAYS#44_1 (_architecture 1 0 44 (_process (_target(3)(4)) (_read(2)(0)(3)) ))) ) ) (_defparam ) (_model . NegDetect 3 -1) ) I 000051 55 3908 1093877394834 BitCounter (_unit VERILOG 6.349C.6.256 (BitCounter 0 25 (BitCounter 0 25 )) (_version v32) (_time 1093877394770 2004.08.30 07:49:54) (_source (\./src/bitcounter.v\ VERILOG (\./src/bitcounter.v\ VERILOG))) (_use (std(standard))(vl(verilog_logic))) (_base (E 6)) (_entity (_time 1093877394770) (_use ) ) (_timescale 1ps 1ps) (_parameters dbg accs ) (_attribute nb_assign ) (_object (_type (_internal ~[7:0]wire~ 0 25 (_array ~wire ((_downto (i 7) (i 0)))))) (_port (_internal outDATA ~[7:0]wire~ 0 25 (_architecture (_out ))) (_net ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign)) (_port (_internal NegInc ~wire 0 25 (_architecture (_in ))) (_net ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign)) (_port (_internal SCLreset ~wire 0 25 (_architecture (_in ))) (_net ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign)) (_port (_internal Mclk ~wire 0 25 (_architecture (_in ))) (_net ) (_nonbaction) (_noforceassign)) (_port (_internal SCLenable ~wire 0 25 (_architecture (_out ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign)) (_port (_internal Inc ~wire 0 25 (_architecture (_in ))) (_net ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign)) (_port (_internal DriveSCL ~wire 0 25 (_architecture (_inout ))) (_net ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign)) (_port (_internal NegSCL ~wire 0 25 (_architecture (_in ))) (_net ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign)) (_port (_internal ResetDetect ~wire 0 25 (_architecture (_in ))) (_net ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign)) (_port (_internal SLPYI2CCNTr ~wire 0 25 (_architecture (_in ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign)) (_port (_internal SCLint ~wire 0 25 (_architecture (_out ))) (_net ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign)) (_type (_internal ~[5:0]reg~ 0 56 (_array ~reg ((_downto (i 5) (i 0)))))) (_signal (_internal counterr ~[5:0]reg~ 0 56 (_architecture (_uni ))) (_reg ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign)) (_subprogram ) (_type (_external ~wire (vl verilog_logic wire))) (_type (_external ~reg (vl verilog_logic reg))) (_type (_external ~event (vl verilog_logic event))) (_type (_external ~wand (vl verilog_logic wand))) (_type (_external ~wor (vl verilog_logic wor))) (_type (_external ~tri1 (vl verilog_logic tri1))) (_type (_external ~tri0 (vl verilog_logic tri0))) (_type (_external ~trireg (vl verilog_logic trireg))) (_type (_external ~supply0 (vl verilog_logic supply0))) (_type (_external ~supply1 (vl verilog_logic supply1))) (_type (_external ~real (vl verilog_logic real))) (_type (_external ~realtime (vl verilog_logic realtime))) (_type (_external ~tri (vl verilog_logic tri))) (_type (_external ~triand (vl verilog_logic triand))) (_type (_external ~trior (vl verilog_logic trior))) (_type (_external ~bit (vl verilog_logic bit))) (_type (_external ~extstd.standard.integer (std standard integer))) (_type (_external ~extstd.standard.bit (std standard bit))) (_process (#ASSIGN#58_0 (_architecture 0 0 58 (_process (_simple) (_target(10)) (_sensitivity(11)) ))) (#ASSIGN#60_1 (_architecture 1 0 60 (_process (_simple) (_target(4)) (_sensitivity(11)) ))) (#ASSIGN#62_2 (_architecture 2 0 62 (_process (_simple) (_target(6)) (_sensitivity(4)) ))) (#ASSIGN#64_3 (_architecture 3 0 64 (_process (_simple) (_target(0)) (_sensitivity(9)(11)) ))) (#ALWAYS#66_4 (_architecture 4 0 66 (_process (_target(11)) (_read(3)(2)(8)(5)(1)(7)(11)) ))) ) ) (_defparam ) (_model . BitCounter 6 -1) ) V 000047 55 4098 1093877411145 I2Cfix (_unit VERILOG 6.349C.6.256 (I2Cfix 0 32 (I2Cfix 0 32 )) (_version v32) (_time 1093877411067 2004.08.30 07:50:11) (_source (\./compile/i2cfix.v\ VERILOG (\./compile/i2cfix.v\ VERILOG))) (_use (std(standard))(vl(verilog_logic))) (_base (E 1)) (_entity (_time 1093877411067) (_use ) ) (_timescale 1ps 1ps) (_parameters dbg accs ) (_attribute ) (_object (_port (_internal Inc ~wire 0 32 (_architecture (_in ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign)) (_port (_internal Mclk ~wire 0 32 (_architecture (_in ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign)) (_port (_internal SCLreset ~wire 0 32 (_architecture (_in ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign)) (_port (_internal SLPYI2CCNTr ~wire 0 32 (_architecture (_in ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign)) (_port (_internal SCLenable ~wire 0 32 (_architecture (_out ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign)) (_port (_internal SCLint ~wire 0 32 (_architecture (_out ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign)) (_type (_internal ~[7:0]wire~ 0 32 (_array ~wire ((_downto (i 7) (i 0)))))) (_port (_internal outDATA ~[7:0]wire~ 0 32 (_architecture (_out ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign)) (_port (_internal SCL ~wire 0 32 (_architecture (_inout ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign)) (_signal (_internal Incdetect ~wire 0 53 (_architecture (_uni ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign)) (_signal (_internal ResetDetect ~wire 0 54 (_architecture (_uni ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign)) (_signal (_internal SCLdetect ~wire 0 55 (_architecture (_uni ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign)) (_subprogram ) (_type (_external ~wire (vl verilog_logic wire))) (_type (_external ~reg (vl verilog_logic reg))) (_type (_external ~event (vl verilog_logic event))) (_type (_external ~wand (vl verilog_logic wand))) (_type (_external ~wor (vl verilog_logic wor))) (_type (_external ~tri1 (vl verilog_logic tri1))) (_type (_external ~tri0 (vl verilog_logic tri0))) (_type (_external ~trireg (vl verilog_logic trireg))) (_type (_external ~supply0 (vl verilog_logic supply0))) (_type (_external ~supply1 (vl verilog_logic supply1))) (_type (_external ~real (vl verilog_logic real))) (_type (_external ~realtime (vl verilog_logic realtime))) (_type (_external ~tri (vl verilog_logic tri))) (_type (_external ~triand (vl verilog_logic triand))) (_type (_external ~trior (vl verilog_logic trior))) (_type (_external ~bit (vl verilog_logic bit))) (_type (_external ~extstd.standard.integer (std standard integer))) (_type (_external ~extstd.standard.bit (std standard bit))) ) (_defparam ) (_scope ) (_instantiation U1 0 59 (_entity . NegDetect) (_port ((Line) (Inc)) ((Mclk) (Mclk)) ((Ndetect) (Incdetect)) ) (_strength strong0 strong1) ) (_instantiation U2 0 68 (_entity . NegDetect) (_port ((Line) (SCL)) ((Mclk) (Mclk)) ((Ndetect) (SCLdetect)) ) (_strength strong0 strong1) ) (_instantiation U3 0 77 (_entity . BitCounter) (_port ((DriveSCL) (SCL)) ((Inc) (Inc)) ((Mclk) (Mclk)) ((NegInc) (Incdetect)) ((NegSCL) (SCLdetect)) ((ResetDetect) (ResetDetect)) ((SCLenable) (SCLenable)) ((SCLint) (SCLint)) ((SCLreset) (SCLreset)) ((SLPYI2CCNTr) (SLPYI2CCNTr)) ((outDATA) (outDATA)) ) (_strength strong0 strong1) ) (_instantiation U4 0 94 (_entity . NegDetect) (_port ((Line) (SCLreset)) ((Mclk) (Mclk)) ((Ndetect) (ResetDetect)) ) (_strength strong0 strong1) ) (_model . I2Cfix 1 -1) ) I 000049 55 5072 1093892966755 UARTaddr (_unit VERILOG 6.349C.6.256 (UARTaddr 0 25 (UARTaddr 0 25 )) (_version v32) (_time 1093892966676 2004.08.30 12:09:26) (_source (\./src/uartaddr.v\ VERILOG (\./src/uartaddr.v\ VERILOG))) (_use (std(standard))(vl(verilog_logic))) (_base (E 9)) (_entity (_time 1093892966676) (_use ) ) (_timescale 1ps 1ps) (_parameters dbg accs ) (_attribute ) (_object (_type (_internal ~vector~0 0 64 (_array ~bit ((_uto (i 0) (i 0)))))) (_generic (_internal HIGHUART ~vector~0 0 64 \6'b0\ (_entity -1 (_constant \6'b0\)))) (_port (_internal IOWR ~wire 0 25 (_architecture (_in ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign)) (_type (_internal ~[7:0]wire~ 0 25 (_array ~wire ((_downto (i 7) (i 0)))))) (_port (_internal inDATA ~[7:0]wire~ 0 25 (_architecture (_in ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign)) (_port (_internal outDATA ~[7:0]wire~ 0 25 (_architecture (_out ))) (_net ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign)) (_port (_internal UARTcs ~wire 0 25 (_architecture (_out ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign)) (_port (_internal UIOW ~wire 0 25 (_architecture (_out ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign)) (_type (_internal ~[13:0]wire~ 0 25 (_array ~wire ((_downto (i 13) (i 0)))))) (_port (_internal SA ~[13:0]wire~ 0 25 (_architecture (_in ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign)) (_port (_internal RD ~wire 0 25 (_architecture (_in ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign)) (_port (_internal SD ~[7:0]wire~ 0 25 (_architecture (_inout ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign)) (_port (_internal UARTaddr ~[7:0]wire~ 0 25 (_architecture (_out ))) (_net ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign)) (_port (_internal SystemEN ~wire 0 25 (_architecture (_in ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign)) (_port (_internal WR ~wire 0 25 (_architecture (_in ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign)) (_port (_internal ADDR ~[7:0]wire~ 0 25 (_architecture (_in ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign)) (_port (_internal IORD ~wire 0 25 (_architecture (_in ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign)) (_port (_internal UDATA ~[7:0]wire~ 0 25 (_architecture (_inout ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign)) (_port (_internal UIOR ~wire 0 25 (_architecture (_out ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign)) (_subprogram ) (_type (_external ~wire (vl verilog_logic wire))) (_type (_external ~reg (vl verilog_logic reg))) (_type (_external ~event (vl verilog_logic event))) (_type (_external ~wand (vl verilog_logic wand))) (_type (_external ~wor (vl verilog_logic wor))) (_type (_external ~tri1 (vl verilog_logic tri1))) (_type (_external ~tri0 (vl verilog_logic tri0))) (_type (_external ~trireg (vl verilog_logic trireg))) (_type (_external ~supply0 (vl verilog_logic supply0))) (_type (_external ~supply1 (vl verilog_logic supply1))) (_type (_external ~real (vl verilog_logic real))) (_type (_external ~realtime (vl verilog_logic realtime))) (_type (_external ~tri (vl verilog_logic tri))) (_type (_external ~triand (vl verilog_logic triand))) (_type (_external ~trior (vl verilog_logic trior))) (_type (_external ~bit (vl verilog_logic bit))) (_type (_external ~extstd.standard.integer (std standard integer))) (_type (_external ~extstd.standard.bit (std standard bit))) (_process (#ASSIGN#68_0 (_architecture 0 0 68 (_process (_simple) (_target(8(d_7_4))) (_sensitivity(9)(5(d_13_8))(5(d_7_4))(11(d_7_4))) ))) (#ASSIGN#69_1 (_architecture 1 0 69 (_process (_simple) (_target(8(d_3_0))) (_sensitivity(9)(5(d_13_8))(5(d_3_0))(11(d_3_0))) ))) (#ASSIGN#72_2 (_architecture 2 0 72 (_process (_simple) (_target(3)) (_sensitivity(9)(5(d_13_8))(11(d_7_4))) ))) (#ASSIGN#75_3 (_architecture 3 0 75 (_process (_alias ((UIOR)(SystemEN)(UARTcs)(IORD)(RD)(UARTcs)))(_simple) (_target(14)) (_sensitivity(9)(3)(12)(6)) ))) (#ASSIGN#76_4 (_architecture 4 0 76 (_process (_alias ((UIOW)(SystemEN)(UARTcs)(IOWR)(WR)(UARTcs)))(_simple) (_target(4)) (_sensitivity(9)(3)(0)(10)) ))) (#ASSIGN#80_5 (_architecture 5 0 80 (_process (_simple) (_target(13)) (_sensitivity(3)(4)(9)(7)(1)(14)) ))) (#ASSIGN#81_6 (_architecture 6 0 81 (_process (_simple) (_target(2)) (_sensitivity(3)(14)(9)(13)) ))) (#ASSIGN#82_7 (_architecture 7 0 82 (_process (_simple) (_target(7)) (_sensitivity(3)(14)(9)(13)) ))) (#INTERNAL#0_8 (_internal 8 0 0 (_process (_virtual)))) ) ) (_defparam ) (_model . UARTaddr 9 -1) ) I 000050 55 5177 1093966674403 Interrupt (_unit VERILOG 6.349C.6.256 (Interrupt 0 25 (Interrupt 0 25 )) (_version v32) (_time 1093966674325 2004.08.31 08:37:54) (_source (\./src/interrupt.v\ VERILOG (\./src/interrupt.v\ VERILOG))) (_use (std(standard))(vl(verilog_logic))) (_base (E 5)) (_entity (_time 1093966674325) (_use ) ) (_timescale 1ps 1ps) (_parameters dbg accs ) (_attribute nb_assign ) (_object (_port (_internal AM0Status ~wire 0 25 (_architecture (_in ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign)) (_port (_internal AM1Status ~wire 0 25 (_architecture (_in ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign)) (_port (_internal Reset ~wire 0 25 (_architecture (_in ))) (_net ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign)) (_port (_internal AM2Status ~wire 0 25 (_architecture (_in ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign)) (_port (_internal ExternalStatus ~wire 0 25 (_architecture (_in ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign)) (_port (_internal Mclk ~wire 0 25 (_architecture (_in ))) (_net ) (_nonbaction) (_noforceassign)) (_port (_internal UARTint ~wire 0 25 (_architecture (_in ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign)) (_port (_internal SystemStatus ~wire 0 25 (_architecture (_in ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign)) (_port (_internal INT ~wire 0 25 (_architecture (_out ))) (_net ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign)) (_port (_internal SCLint ~wire 0 25 (_architecture (_in ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign)) (_port (_internal SLPYIEw ~wire 0 25 (_architecture (_in ))) (_net ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign)) (_port (_internal CameraStatus ~wire 0 25 (_architecture (_in ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign)) (_port (_internal SLPYIFGr ~wire 0 25 (_architecture (_in ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign)) (_type (_internal ~[7:0]wire~ 0 25 (_array ~wire ((_downto (i 7) (i 0)))))) (_port (_internal inDATA ~[7:0]wire~ 0 25 (_architecture (_in ))) (_net ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign)) (_port (_internal outDATA ~[7:0]wire~ 0 25 (_architecture (_out ))) (_net ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign)) (_port (_internal SLPYIFGw ~wire 0 25 (_architecture (_in ))) (_net ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign)) (_port (_internal ModemStatus ~wire 0 25 (_architecture (_in ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign)) (_port (_internal SystemEN ~wire 0 25 (_architecture (_in ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign)) (_signal (_internal PWRFlgs ~wire 0 69 (_architecture (_uni ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign)) (_type (_internal ~[7:0]reg~ 0 71 (_array ~reg ((_downto (i 7) (i 0)))))) (_signal (_internal SLPYIE ~[7:0]reg~ 0 71 (_architecture (_uni ))) (_reg ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign)) (_subprogram ) (_type (_external ~wire (vl verilog_logic wire))) (_type (_external ~reg (vl verilog_logic reg))) (_type (_external ~event (vl verilog_logic event))) (_type (_external ~wand (vl verilog_logic wand))) (_type (_external ~wor (vl verilog_logic wor))) (_type (_external ~tri1 (vl verilog_logic tri1))) (_type (_external ~tri0 (vl verilog_logic tri0))) (_type (_external ~trireg (vl verilog_logic trireg))) (_type (_external ~supply0 (vl verilog_logic supply0))) (_type (_external ~supply1 (vl verilog_logic supply1))) (_type (_external ~real (vl verilog_logic real))) (_type (_external ~realtime (vl verilog_logic realtime))) (_type (_external ~tri (vl verilog_logic tri))) (_type (_external ~triand (vl verilog_logic triand))) (_type (_external ~trior (vl verilog_logic trior))) (_type (_external ~bit (vl verilog_logic bit))) (_type (_external ~extstd.standard.integer (std standard integer))) (_type (_external ~extstd.standard.bit (std standard bit))) (_process (#ASSIGN#73_0 (_architecture 0 0 73 (_process (_alias ((PWRFlgs)(SystemStatus)(CameraStatus)(ExternalStatus)(AM2Status)(AM1Status)(AM0Status)(ModemStatus)))(_simple) (_target(18)) (_sensitivity(7)(11)(4)(3)(1)(0)(16)) ))) (#ASSIGN#74_1 (_architecture 1 0 74 (_process (_simple) (_target(14)) (_sensitivity(12)(9)(18)(6)) ))) (#ASSIGN#78_2 (_architecture 2 0 78 (_process (_alias ((INT)(SLPYIE(7))(SCLint)(SLPYIE(1))(PWRFlgs)(SLPYIE(0))(UARTint)(SystemEN)))(_simple) (_target(8)) (_sensitivity(19(7))(9)(19(1))(18)(19(0))(6)(17)) ))) (#ALWAYS#80_3 (_architecture 3 0 80 (_process (_target(19)) (_read(5)(2)(10)(13)) ))) ) ) (_defparam ) (_model . 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(_architecture (_out ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign)) (_subprogram ) (_type (_external ~wire (vl verilog_logic wire))) (_type (_external ~reg (vl verilog_logic reg))) (_type (_external ~event (vl verilog_logic event))) (_type (_external ~wand (vl verilog_logic wand))) (_type (_external ~wor (vl verilog_logic wor))) (_type (_external ~tri1 (vl verilog_logic tri1))) (_type (_external ~tri0 (vl verilog_logic tri0))) (_type (_external ~trireg (vl verilog_logic trireg))) (_type (_external ~supply0 (vl verilog_logic supply0))) (_type (_external ~supply1 (vl verilog_logic supply1))) (_type (_external ~real (vl verilog_logic real))) (_type (_external ~realtime (vl verilog_logic realtime))) (_type (_external ~tri (vl verilog_logic tri))) (_type (_external ~triand (vl verilog_logic triand))) (_type (_external ~trior (vl verilog_logic trior))) (_type (_external ~bit (vl verilog_logic bit))) (_type (_external ~extstd.standard.integer (std standard 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Interface 8 -1) ) V 000050 55 2394 1093969561419 NegDetect (_unit VERILOG 6.349C.6.256 (NegDetect 0 25 (NegDetect 0 25 )) (_version v32) (_time 1093969561341 2004.08.31 09:26:01) (_source (\./src/negdetect.v\ VERILOG (\./src/negdetect.v\ VERILOG))) (_use (std(standard))(vl(verilog_logic))) (_base (E 3)) (_entity (_time 1093969561341) (_use ) ) (_timescale 1ps 1ps) (_parameters dbg accs ) (_attribute nb_assign ) (_object (_port (_internal Line ~wire 0 25 (_architecture (_in ))) (_net ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign)) (_port (_internal Ndetect ~wire 0 25 (_architecture (_out ))) (_net ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign)) (_port (_internal MCLK ~wire 0 25 (_architecture (_in ))) (_net ) (_nonbaction) (_noforceassign)) (_signal (_internal Line_last ~reg 0 39 (_architecture (_uni ))) (_reg ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign)) (_signal (_internal Ndetectr ~reg 0 40 (_architecture (_uni ))) (_reg ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign)) (_subprogram ) (_type (_external ~wire (vl verilog_logic wire))) (_type (_external ~reg (vl verilog_logic reg))) (_type (_external ~event (vl verilog_logic event))) (_type (_external ~wand (vl verilog_logic wand))) (_type (_external ~wor (vl verilog_logic wor))) (_type (_external ~tri1 (vl verilog_logic tri1))) (_type (_external ~tri0 (vl verilog_logic tri0))) (_type (_external ~trireg (vl verilog_logic trireg))) (_type (_external ~supply0 (vl verilog_logic supply0))) (_type (_external ~supply1 (vl verilog_logic supply1))) (_type (_external ~real (vl verilog_logic real))) (_type (_external ~realtime (vl verilog_logic realtime))) (_type (_external ~tri (vl verilog_logic tri))) (_type (_external ~triand (vl verilog_logic triand))) (_type (_external ~trior (vl verilog_logic trior))) (_type (_external ~bit (vl verilog_logic bit))) (_type (_external ~extstd.standard.integer (std standard integer))) (_type (_external ~extstd.standard.bit (std standard bit))) (_process (#ASSIGN#42_0 (_architecture 0 0 42 (_process (_alias ((Ndetect)(Ndetectr)))(_simple) (_target(1)) (_sensitivity(4)) ))) (#ALWAYS#44_1 (_architecture 1 0 44 (_process (_target(3)(4)) (_read(2)(0)(3)) ))) ) ) (_defparam ) (_model . NegDetect 3 -1) ) V 000051 55 3908 1093969587403 BitCounter (_unit VERILOG 6.349C.6.256 (BitCounter 0 25 (BitCounter 0 25 )) (_version v32) (_time 1093969587325 2004.08.31 09:26:27) (_source (\./src/bitcounter.v\ VERILOG (\./src/bitcounter.v\ VERILOG))) (_use (std(standard))(vl(verilog_logic))) (_base (E 6)) (_entity (_time 1093969587325) (_use ) ) (_timescale 1ps 1ps) (_parameters dbg accs ) (_attribute nb_assign ) (_object (_type (_internal ~[7:0]wire~ 0 25 (_array ~wire ((_downto (i 7) (i 0)))))) (_port (_internal outDATA ~[7:0]wire~ 0 25 (_architecture (_out ))) (_net ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign)) (_port (_internal NegInc ~wire 0 25 (_architecture (_in ))) (_net ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign)) (_port (_internal SCLreset ~wire 0 25 (_architecture (_in ))) (_net ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign)) (_port (_internal MCLK ~wire 0 25 (_architecture (_in ))) (_net ) (_nonbaction) (_noforceassign)) (_port (_internal SCLenable ~wire 0 25 (_architecture (_out ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign)) (_port (_internal Inc ~wire 0 25 (_architecture (_in ))) (_net ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign)) (_port (_internal DriveSCL ~wire 0 25 (_architecture (_inout ))) (_net ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign)) (_port (_internal NegSCL ~wire 0 25 (_architecture (_in ))) (_net ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign)) (_port (_internal ResetDetect ~wire 0 25 (_architecture (_in ))) (_net ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign)) (_port (_internal SLPYI2CCNTr ~wire 0 25 (_architecture (_in ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign)) (_port (_internal SCLint ~wire 0 25 (_architecture (_out ))) (_net ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign)) (_type (_internal ~[5:0]reg~ 0 56 (_array ~reg ((_downto (i 5) (i 0)))))) (_signal (_internal counterr ~[5:0]reg~ 0 56 (_architecture (_uni ))) (_reg ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign)) (_subprogram ) (_type (_external ~wire (vl verilog_logic wire))) (_type (_external ~reg (vl verilog_logic reg))) (_type (_external ~event (vl verilog_logic event))) (_type (_external ~wand (vl verilog_logic wand))) (_type (_external ~wor (vl verilog_logic wor))) (_type (_external ~tri1 (vl verilog_logic tri1))) (_type (_external ~tri0 (vl verilog_logic tri0))) (_type (_external ~trireg (vl verilog_logic trireg))) (_type (_external ~supply0 (vl verilog_logic supply0))) (_type (_external ~supply1 (vl verilog_logic supply1))) (_type (_external ~real (vl verilog_logic real))) (_type (_external ~realtime (vl verilog_logic realtime))) (_type (_external ~tri (vl verilog_logic tri))) (_type (_external ~triand (vl verilog_logic triand))) (_type (_external ~trior (vl verilog_logic trior))) (_type (_external ~bit (vl verilog_logic bit))) (_type (_external ~extstd.standard.integer (std standard integer))) (_type (_external ~extstd.standard.bit (std standard bit))) (_process (#ASSIGN#58_0 (_architecture 0 0 58 (_process (_simple) (_target(10)) (_sensitivity(11)) ))) (#ASSIGN#60_1 (_architecture 1 0 60 (_process (_simple) (_target(4)) (_sensitivity(11)) ))) (#ASSIGN#62_2 (_architecture 2 0 62 (_process (_simple) (_target(6)) (_sensitivity(4)) ))) (#ASSIGN#64_3 (_architecture 3 0 64 (_process (_simple) (_target(0)) (_sensitivity(9)(11)) ))) (#ALWAYS#66_4 (_architecture 4 0 66 (_process (_target(11)) (_read(3)(2)(8)(5)(1)(7)(11)) ))) ) ) (_defparam ) (_model . BitCounter 6 -1) ) V 000047 55 4098 1093969622903 I2Cfix (_unit VERILOG 6.349C.6.256 (I2Cfix 0 32 (I2Cfix 0 32 )) (_version v32) (_time 1093969622841 2004.08.31 09:27:02) (_source (\./compile/i2cfix.v\ VERILOG (\./compile/i2cfix.v\ VERILOG))) (_use (std(standard))(vl(verilog_logic))) (_base (E 1)) (_entity (_time 1093969622841) (_use ) ) (_timescale 1ps 1ps) (_parameters dbg accs ) (_attribute ) (_object (_port (_internal Inc ~wire 0 32 (_architecture (_in ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign)) (_port (_internal MCLK ~wire 0 32 (_architecture (_in ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign)) (_port (_internal SCLreset ~wire 0 32 (_architecture (_in ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign)) (_port (_internal SLPYI2CCNTr ~wire 0 32 (_architecture (_in ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign)) (_port (_internal SCLenable ~wire 0 32 (_architecture (_out ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign)) (_port (_internal SCLint ~wire 0 32 (_architecture (_out ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign)) (_type (_internal ~[7:0]wire~ 0 32 (_array ~wire ((_downto (i 7) (i 0)))))) (_port (_internal outDATA ~[7:0]wire~ 0 32 (_architecture (_out ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign)) (_port (_internal SCL ~wire 0 32 (_architecture (_inout ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign)) (_signal (_internal Incdetect ~wire 0 53 (_architecture (_uni ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign)) (_signal (_internal ResetDetect ~wire 0 54 (_architecture (_uni ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign)) (_signal (_internal SCLdetect ~wire 0 55 (_architecture (_uni ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign)) (_subprogram ) (_type (_external ~wire (vl verilog_logic wire))) (_type (_external ~reg (vl verilog_logic reg))) (_type (_external ~event (vl verilog_logic event))) (_type (_external ~wand (vl verilog_logic wand))) (_type (_external ~wor (vl verilog_logic wor))) (_type (_external ~tri1 (vl verilog_logic tri1))) (_type (_external ~tri0 (vl verilog_logic tri0))) (_type (_external ~trireg (vl verilog_logic trireg))) (_type (_external ~supply0 (vl verilog_logic supply0))) (_type (_external ~supply1 (vl verilog_logic supply1))) (_type (_external ~real (vl verilog_logic real))) (_type (_external ~realtime (vl verilog_logic realtime))) (_type (_external ~tri (vl verilog_logic tri))) (_type (_external ~triand (vl verilog_logic triand))) (_type (_external ~trior (vl verilog_logic trior))) (_type (_external ~bit (vl verilog_logic bit))) (_type (_external ~extstd.standard.integer (std standard integer))) (_type (_external ~extstd.standard.bit (std standard bit))) ) (_defparam ) (_scope ) (_instantiation U1 0 59 (_entity . NegDetect) (_port ((Line) (Inc)) ((MCLK) (MCLK)) ((Ndetect) (Incdetect)) ) (_strength strong0 strong1) ) (_instantiation U2 0 68 (_entity . NegDetect) (_port ((Line) (SCL)) ((MCLK) (MCLK)) ((Ndetect) (SCLdetect)) ) (_strength strong0 strong1) ) (_instantiation U3 0 77 (_entity . BitCounter) (_port ((DriveSCL) (SCL)) ((Inc) (Inc)) ((MCLK) (MCLK)) ((NegInc) (Incdetect)) ((NegSCL) (SCLdetect)) ((ResetDetect) (ResetDetect)) ((SCLenable) (SCLenable)) ((SCLint) (SCLint)) ((SCLreset) (SCLreset)) ((SLPYI2CCNTr) (SLPYI2CCNTr)) ((outDATA) (outDATA)) ) (_strength strong0 strong1) ) (_instantiation U4 0 94 (_entity . NegDetect) (_port ((Line) (SCLreset)) ((MCLK) (MCLK)) ((Ndetect) (ResetDetect)) ) (_strength strong0 strong1) ) (_model . I2Cfix 1 -1) ) I 000050 55 5177 1093969654857 Interrupt (_unit VERILOG 6.349C.6.256 (Interrupt 0 25 (Interrupt 0 25 )) (_version v32) (_time 1093969654794 2004.08.31 09:27:34) (_source (\./src/interrupt.v\ VERILOG (\./src/interrupt.v\ VERILOG))) (_use (std(standard))(vl(verilog_logic))) (_base (E 5)) (_entity (_time 1093969654794) (_use ) ) (_timescale 1ps 1ps) (_parameters dbg accs ) (_attribute nb_assign ) (_object (_port (_internal AM0Status ~wire 0 25 (_architecture (_in ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign)) (_port (_internal AM1Status ~wire 0 25 (_architecture (_in ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign)) (_port (_internal Reset ~wire 0 25 (_architecture (_in ))) (_net ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign)) (_port (_internal AM2Status ~wire 0 25 (_architecture (_in ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign)) (_port (_internal ExternalStatus ~wire 0 25 (_architecture (_in ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign)) (_port (_internal MCLK ~wire 0 25 (_architecture (_in ))) (_net ) (_nonbaction) (_noforceassign)) (_port (_internal UARTint ~wire 0 25 (_architecture (_in ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign)) (_port (_internal SystemStatus ~wire 0 25 (_architecture (_in ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign)) (_port (_internal INT ~wire 0 25 (_architecture (_out ))) (_net ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign)) (_port (_internal SCLint ~wire 0 25 (_architecture (_in ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign)) (_port (_internal SLPYIEw ~wire 0 25 (_architecture (_in ))) (_net ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign)) (_port (_internal CameraStatus ~wire 0 25 (_architecture (_in ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign)) (_port (_internal SLPYIFGr ~wire 0 25 (_architecture (_in ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign)) (_type (_internal ~[7:0]wire~ 0 25 (_array ~wire ((_downto (i 7) (i 0)))))) (_port (_internal inDATA ~[7:0]wire~ 0 25 (_architecture (_in ))) (_net ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign)) (_port (_internal outDATA ~[7:0]wire~ 0 25 (_architecture (_out ))) (_net ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign)) (_port (_internal SLPYIFGw ~wire 0 25 (_architecture (_in ))) (_net ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign)) (_port (_internal ModemStatus ~wire 0 25 (_architecture (_in ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign)) (_port (_internal SystemEN ~wire 0 25 (_architecture (_in ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign)) (_signal (_internal PWRFlgs ~wire 0 69 (_architecture (_uni ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign)) (_type (_internal ~[7:0]reg~ 0 71 (_array ~reg ((_downto (i 7) (i 0)))))) (_signal (_internal SLPYIE ~[7:0]reg~ 0 71 (_architecture (_uni ))) (_reg ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign)) (_subprogram ) (_type (_external ~wire (vl verilog_logic wire))) (_type (_external ~reg (vl verilog_logic reg))) (_type (_external ~event (vl verilog_logic event))) (_type (_external ~wand (vl verilog_logic wand))) (_type (_external ~wor (vl verilog_logic wor))) (_type (_external ~tri1 (vl verilog_logic tri1))) (_type (_external ~tri0 (vl verilog_logic tri0))) (_type (_external ~trireg (vl verilog_logic trireg))) (_type (_external ~supply0 (vl verilog_logic supply0))) (_type (_external ~supply1 (vl verilog_logic supply1))) (_type (_external ~real (vl verilog_logic real))) (_type (_external ~realtime (vl verilog_logic realtime))) (_type (_external ~tri (vl verilog_logic tri))) (_type (_external ~triand (vl verilog_logic triand))) (_type (_external ~trior (vl verilog_logic trior))) (_type (_external ~bit (vl verilog_logic bit))) (_type (_external ~extstd.standard.integer (std standard integer))) (_type (_external ~extstd.standard.bit (std standard bit))) (_process (#ASSIGN#73_0 (_architecture 0 0 73 (_process (_alias ((PWRFlgs)(SystemStatus)(CameraStatus)(ExternalStatus)(AM2Status)(AM1Status)(AM0Status)(ModemStatus)))(_simple) (_target(18)) (_sensitivity(7)(11)(4)(3)(1)(0)(16)) ))) (#ASSIGN#74_1 (_architecture 1 0 74 (_process (_simple) (_target(14)) (_sensitivity(12)(9)(18)(6)) ))) (#ASSIGN#78_2 (_architecture 2 0 78 (_process (_alias ((INT)(SLPYIE(7))(SCLint)(SLPYIE(1))(PWRFlgs)(SLPYIE(0))(UARTint)(SystemEN)))(_simple) (_target(8)) (_sensitivity(19(7))(9)(19(1))(18)(19(0))(6)(17)) ))) (#ALWAYS#80_3 (_architecture 3 0 80 (_process (_target(19)) (_read(5)(2)(10)(13)) ))) ) ) (_defparam ) (_model . Interrupt 5 -1) ) V 000044 55 5014 1093976033372 MSP (_unit VERILOG 6.349C.6.256 (MSP 0 25 (MSP 0 25 )) (_version v32) (_time 1093976033294 2004.08.31 11:13:53) (_source (\./src/msp.v\ VERILOG (\./src/msp.v\ VERILOG))) (_use (std(standard))(vl(verilog_logic))) (_base (E 7)) (_entity (_time 1093976033294) (_use ) ) (_timescale 1ps 1ps) (_parameters dbg accs ) (_attribute ) (_object (_type (_internal ~vector~0 0 52 (_array ~bit ((_uto (i 0) (i 0))))(_attribute signed))) (_generic (_internal Half_period ~vector~0 0 52 \500000\ (_entity -1 (_constant \500000\)))) (_type (_internal ~vector~1 0 53 (_array ~bit ((_uto (i 0) (i 0))))(_attribute signed))) (_generic (_internal BITS ~vector~1 0 53 \12\ (_entity -1 (_constant \12\)))) (_type (_internal ~vector~2 0 53 (_array ~bit ((_uto (i 0) (i 0))))(_attribute signed))) (_generic (_internal WORDS ~vector~2 0 53 \159\ (_entity -1 (_constant \159\)))) (_port (_internal WR ~wire 0 25 (_architecture (_out ))) (_net ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign)) (_port (_internal AS ~wire 0 25 (_architecture (_out ))) (_net ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign)) (_type (_internal ~[7:0]wire~ 0 25 (_array ~wire ((_downto (i 7) (i 0)))))) (_port (_internal AD ~[7:0]wire~ 0 25 (_architecture (_inout ))) (_net ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign)) (_port (_internal RD ~wire 0 25 (_architecture (_out ))) (_net ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign)) (_port (_internal Mclk ~wire 0 25 (_architecture (_out ))) (_net ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign)) (_signal (_internal ASr ~reg 0 43 (_architecture (_uni ))) (_reg ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign)) (_signal (_internal WRr ~reg 0 44 (_architecture (_uni ))) (_reg ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign)) (_signal (_internal RDr ~reg 0 45 (_architecture (_uni ))) (_reg ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign)) (_signal (_internal Mclkr ~reg 0 46 (_architecture (_uni ))) (_reg ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign)) (_type (_internal ~[7:0]reg~ 0 47 (_array ~reg ((_downto (i 7) (i 0)))))) (_signal (_internal ADr ~[7:0]reg~ 0 47 (_architecture (_uni ))) (_reg ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign)) (_signal (_internal busDrive ~reg 0 48 (_architecture (_uni ))) (_reg ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign)) (_type (_internal ~integer 0 50 (_array ~reg ((_downto (i 31) (i 0))))(_attribute signed))) (_signal (_internal J ~integer 0 50 (_architecture (_uni ))) (_reg integer) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign)) (_type (_internal ~[1:BITS]reg~[1:WORDS]~ 0 54 (_array ~reg ((_range 7)(_range 8))))) (_signal (_internal Vmem ~[1:BITS]reg~[1:WORDS]~ 0 54 (_architecture (_uni ))) (_reg memory) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign)) (_subprogram (_function \$readmemb\) ) (_type (_external ~wire (vl verilog_logic wire))) (_type (_external ~reg (vl verilog_logic reg))) (_type (_external ~event (vl verilog_logic event))) (_type (_external ~wand (vl verilog_logic wand))) (_type (_external ~wor (vl verilog_logic wor))) (_type (_external ~tri1 (vl verilog_logic tri1))) (_type (_external ~tri0 (vl verilog_logic tri0))) (_type (_external ~trireg (vl verilog_logic trireg))) (_type (_external ~supply0 (vl verilog_logic supply0))) (_type (_external ~supply1 (vl verilog_logic supply1))) (_type (_external ~real (vl verilog_logic real))) (_type (_external ~realtime (vl verilog_logic realtime))) (_type (_external ~tri (vl verilog_logic tri))) (_type (_external ~triand (vl verilog_logic triand))) (_type (_external ~trior (vl verilog_logic trior))) (_type (_external ~bit (vl verilog_logic bit))) (_type (_external ~extstd.standard.integer (std standard integer))) (_type (_external ~extstd.standard.bit (std standard bit))) (_process (#ASSIGN#57_0 (_architecture 0 0 57 (_process (_alias ((AS)(ASr)))(_simple) (_target(1)) (_sensitivity(5)) ))) (#ASSIGN#58_1 (_architecture 1 0 58 (_process (_alias ((RD)(RDr)))(_simple) (_target(3)) (_sensitivity(7)) ))) (#ASSIGN#59_2 (_architecture 2 0 59 (_process (_alias ((WR)(WRr)))(_simple) (_target(0)) (_sensitivity(6)) ))) (#ASSIGN#60_3 (_architecture 3 0 60 (_process (_simple) (_target(2)) (_sensitivity(10)(9)) ))) (#ASSIGN#61_4 (_architecture 4 0 61 (_process (_alias ((Mclk)(Mclkr)))(_simple) (_target(4)) (_sensitivity(8)) ))) (#INITIAL#63_5 (_architecture 5 0 63 (_process (_target(11)(8)(5)(7)(6)(10)(9)) (_read(12)(11)) ))) (#INTERNAL#0_6 (_internal 6 0 0 (_process (_virtual)))) ) ) (_defparam ) (_model . MSP 9 -1) ) V 000049 55 11113 1094579381583 SleepyTB (_unit VERILOG 6.349C.6.256 (SleepyTB 0 32 (SleepyTB 0 32 )) (_version v32) (_time 1094579381301 2004.09.07 10:49:41) (_source (\./compile/sleepytb.v\ VERILOG (\./compile/sleepytb.v\ VERILOG))) (_use (std(standard))(vl(verilog_logic))) (_base (E 3)) (_entity (_time 1094579381301) (_use ) ) (_timescale 1ps 1ps) (_parameters dbg accs ) (_attribute ) (_object (_type (_internal ~vector~0 0 125 (_array ~bit ((_uto (i 0) (i 0)))))) (_generic (_internal DANGLING_INPUT_CONSTANT ~vector~0 0 125 \1'bZ\ (_entity -1 (_constant \1'bZ\)))) (_port (_internal AM0status ~wire 0 32 (_architecture (_in ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign)) (_port (_internal AM1status ~wire 0 32 (_architecture (_in ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign)) (_port (_internal AM2status ~wire 0 32 (_architecture (_in ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign)) (_port (_internal CameraStatus ~wire 0 32 (_architecture (_in ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign)) (_port (_internal ExternalStatus ~wire 0 32 (_architecture (_in ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign)) (_port (_internal IORD ~wire 0 32 (_architecture (_in ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign)) (_port (_internal IOWR ~wire 0 32 (_architecture (_in ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign)) (_port (_internal ModemStatus ~wire 0 32 (_architecture (_in ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign)) (_port (_internal Reset ~wire 0 32 (_architecture (_in ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign)) (_port (_internal SCLinc ~wire 0 32 (_architecture (_in ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign)) (_port (_internal SCLreset ~wire 0 33 (_architecture (_in ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign)) (_port (_internal SystemStatus ~wire 0 33 (_architecture (_in ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign)) (_port (_internal UINT ~wire 0 33 (_architecture (_in ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign)) (_type (_internal ~[7:0]wire~ 0 33 (_array ~wire ((_downto (i 7) (i 0)))))) (_port (_internal SA ~[7:0]wire~ 0 33 (_architecture (_in ))) (_net ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign)) (_port (_internal AM0EN ~wire 0 33 (_architecture (_out ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign)) (_port (_internal AM1EN ~wire 0 33 (_architecture (_out ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign)) (_port (_internal AM2EN ~wire 0 33 (_architecture (_out ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign)) (_port (_internal CONcon0 ~wire 0 33 (_architecture (_out ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign)) (_port (_internal CONcon1 ~wire 0 33 (_architecture (_out ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign)) (_port (_internal CONcon2 ~wire 0 33 (_architecture (_out ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign)) (_port (_internal CONextr ~wire 0 34 (_architecture (_out ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign)) (_port (_internal CONmodem ~wire 0 34 (_architecture (_out ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign)) (_port (_internal CameraEN ~wire 0 34 (_architecture (_out ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign)) (_port (_internal DwarfEN ~wire 0 34 (_architecture (_out ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign)) (_port (_internal ExternalEN ~wire 0 34 (_architecture (_out ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign)) (_port (_internal INT ~wire 0 34 (_architecture (_out ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign)) (_port (_internal IRQ ~wire 0 34 (_architecture (_out ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign)) (_port (_internal LOOPcon0 ~wire 0 34 (_architecture (_out ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign)) (_port (_internal LOOPcon1 ~wire 0 34 (_architecture (_out ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign)) (_port (_internal LOOPcon2 ~wire 0 34 (_architecture (_out ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign)) (_port (_internal LOOPextr ~wire 0 35 (_architecture (_out ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign)) (_port (_internal LOOPmodem ~wire 0 35 (_architecture (_out ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign)) (_port (_internal ModemEN ~wire 0 35 (_architecture (_out ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign)) (_port (_internal SystemEN ~wire 0 35 (_architecture (_out ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign)) (_port (_internal UCS ~wire 0 35 (_architecture (_out ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign)) (_port (_internal UIOR ~wire 0 35 (_architecture (_out ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign)) (_port (_internal UIOW ~wire 0 35 (_architecture (_out ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign)) (_port (_internal EN ~[7:0]wire~ 0 35 (_architecture (_out ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign)) (_port (_internal PD ~[7:0]wire~ 0 35 (_architecture (_out ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign)) (_port (_internal UAD ~[7:0]wire~ 0 35 (_architecture (_out ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign)) (_port (_internal SD ~[7:0]wire~ 0 36 (_architecture (_inout ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign)) (_port (_internal UD ~[7:0]wire~ 0 36 (_architecture (_inout ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign)) (_signal (_internal NET21 ~wire 0 128 (_architecture (_uni ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign)) (_signal (_internal NET25 ~wire 0 129 (_architecture (_uni ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign)) (_signal (_internal NET29 ~wire 0 130 (_architecture (_uni ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign)) (_signal (_internal NET33 ~wire 0 131 (_architecture (_uni ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign)) (_signal (_internal BUS37 ~[7:0]wire~ 0 132 (_architecture (_uni ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign)) (_signal (_internal Dangling_Input_Signal ~wire 0 135 (_architecture (_uni ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign)) (_type (_internal ~[5:0]wire~ 0 186 (_array ~wire ((_downto (i 5) (i 0)))))) (_signal (_internal \2 \ ~[5:0]wire~ -1 186 (_internal (_uni ))) (_net ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign)) (_signal (_virtual \1 \ 0 186 (_uni ((13)(48))))) (_subprogram ) (_type (_external ~wire (vl verilog_logic wire))) (_type (_external ~reg (vl verilog_logic reg))) (_type (_external ~event (vl verilog_logic event))) (_type (_external ~wand (vl verilog_logic wand))) (_type (_external ~wor (vl verilog_logic wor))) (_type (_external ~tri1 (vl verilog_logic tri1))) (_type (_external ~tri0 (vl verilog_logic tri0))) (_type (_external ~trireg (vl verilog_logic trireg))) (_type (_external ~supply0 (vl verilog_logic supply0))) (_type (_external ~supply1 (vl verilog_logic supply1))) (_type (_external ~real (vl verilog_logic real))) (_type (_external ~realtime (vl verilog_logic realtime))) (_type (_external ~tri (vl verilog_logic tri))) (_type (_external ~triand (vl verilog_logic triand))) (_type (_external ~trior (vl verilog_logic trior))) (_type (_external ~bit (vl verilog_logic bit))) (_type (_external ~extstd.standard.integer (std standard integer))) (_type (_external ~extstd.standard.bit (std standard bit))) (_process (#INTERNAL#186_0 (_internal 0 0 186 (_process (_simple) (_target(48)) (_sensitivity(47)) ))) (#ASSIGN#135_1 (_architecture 1 0 135 (_process (_simple) (_target(47)) ))) (#INTERNAL#0_2 (_internal 2 0 0 (_process (_virtual)))) ) ) (_defparam ) (_scope ) (_instantiation U1 0 139 (_entity . MSP) (_port ((AD) (BUS37)) ((AS) (NET25)) ((Mclk) (NET33)) ((RD) (NET29)) ((WR) (NET21)) ) (_strength strong0 strong1) ) (_instantiation U2 0 150 (_entity . SleepyPLD) (_port ((AD) (BUS37)) ((AM0EN) (AM0EN)) ((AM0Status) (AM0status)) ((AM1EN) (AM1EN)) ((AM1Status) (AM1status)) ((AM2EN) (AM2EN)) ((AM2Status) (AM2status)) ((AS) (NET25)) ((CONcon0) (CONcon0)) ((CONcon1) (CONcon1)) ((CONcon2) (CONcon2)) ((CONextr) (CONextr)) ((CONmodem) (CONmodem)) ((CameraEN) (CameraEN)) ((CameraStatus) (CameraStatus)) ((DwarfEN) (DwarfEN)) ((EN) (EN)) ((ExternalEN) (ExternalEN)) ((ExternalStatus) (ExternalStatus)) ((INT) (INT)) ((IORD) (IORD)) ((IOWR) (IOWR)) ((IRQ) (IRQ)) ((LOOPcon0) (LOOPcon0)) ((LOOPcon1) (LOOPcon1)) ((LOOPcon2) (LOOPcon2)) ((LOOPextr) (LOOPextr)) ((LOOPmodem) (LOOPmodem)) ((MCLK) (NET33)) ((ModemEN) (ModemEN)) ((ModemStatus) (ModemStatus)) ((PD) (PD)) ((RD) (NET29)) ((Reset) (Reset)) ((SA) (\1 \)) ((SCLinc) (SCLinc)) ((SCLreset) (SCLreset)) ((SD) (SD)) ((SystemEN) (SystemEN)) ((SystemStatus) (SystemStatus)) ((UAD) (UAD)) ((UCS) (UCS)) ((UD) (UD)) ((UINT) (UINT)) ((UIOR) (UIOR)) ((UIOW) (UIOW)) ((WR) (NET21)) ) (_strength strong0 strong1) ) (_model . SleepyTB 3 -1) ) V 000050 55 14521 1094579423021 SleepyPLD (_unit VERILOG 6.349C.6.256 (SleepyPLD 0 32 (SleepyPLD 0 32 )) (_version v32) (_time 1094579422957 2004.09.07 10:50:22) (_source (\./compile/sleepypld.v\ VERILOG (\./compile/sleepypld.v\ VERILOG))) (_use (std(standard))(vl(verilog_logic))) (_base (E 1)) (_entity (_time 1094579422957) (_use ) ) (_timescale 1ps 1ps) (_parameters dbg accs ) (_attribute ) (_object (_port (_internal AM0Status ~wire 0 32 (_architecture (_in ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign)) (_port (_internal AM1Status ~wire 0 32 (_architecture (_in ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign)) (_port (_internal AM2Status ~wire 0 32 (_architecture (_in ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign)) (_port (_internal AS ~wire 0 32 (_architecture (_in ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign)) (_port (_internal CameraStatus ~wire 0 32 (_architecture (_in ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign)) (_port (_internal ExternalStatus ~wire 0 32 (_architecture (_in ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign)) (_port (_internal IORD ~wire 0 32 (_architecture (_in ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign)) (_port (_internal IOWR ~wire 0 32 (_architecture (_in ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign)) (_port (_internal MCLK ~wire 0 32 (_architecture (_in ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign)) (_port (_internal ModemStatus ~wire 0 32 (_architecture (_in ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign)) (_port (_internal RD ~wire 0 33 (_architecture (_in ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign)) (_port (_internal Reset ~wire 0 33 (_architecture (_in ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign)) (_port (_internal SCLinc ~wire 0 33 (_architecture (_in ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign)) (_port (_internal SCLreset ~wire 0 33 (_architecture (_in ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign)) (_port (_internal SystemStatus ~wire 0 33 (_architecture (_in ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign)) (_port (_internal UINT ~wire 0 33 (_architecture (_in ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign)) (_port (_internal WR ~wire 0 33 (_architecture (_in ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign)) (_type (_internal ~[13:0]wire~ 0 33 (_array ~wire ((_downto (i 13) (i 0)))))) (_port (_internal SA ~[13:0]wire~ 0 33 (_architecture (_in ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign)) (_port (_internal AM0EN ~wire 0 33 (_architecture (_out ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign)) (_port (_internal AM1EN ~wire 0 33 (_architecture (_out ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign)) (_port (_internal AM2EN ~wire 0 34 (_architecture (_out ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign)) (_port (_internal CONcon0 ~wire 0 34 (_architecture (_out ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign)) (_port (_internal CONcon1 ~wire 0 34 (_architecture (_out ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign)) (_port (_internal CONcon2 ~wire 0 34 (_architecture (_out ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign)) (_port (_internal CONextr ~wire 0 34 (_architecture (_out ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign)) (_port (_internal CONmodem ~wire 0 34 (_architecture (_out ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign)) (_port (_internal CameraEN ~wire 0 34 (_architecture (_out ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign)) (_port (_internal DwarfEN ~wire 0 34 (_architecture (_out ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign)) (_port (_internal ExternalEN ~wire 0 34 (_architecture (_out ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign)) (_port (_internal INT ~wire 0 34 (_architecture (_out ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign)) (_port (_internal IRQ ~wire 0 35 (_architecture (_out ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign)) (_port (_internal LOOPcon0 ~wire 0 35 (_architecture (_out ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign)) (_port (_internal LOOPcon1 ~wire 0 35 (_architecture (_out ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign)) (_port (_internal LOOPcon2 ~wire 0 35 (_architecture (_out ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign)) (_port (_internal LOOPextr ~wire 0 35 (_architecture (_out ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign)) (_port (_internal LOOPmodem ~wire 0 35 (_architecture (_out ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign)) (_port (_internal ModemEN ~wire 0 35 (_architecture (_out ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign)) (_port (_internal SystemEN ~wire 0 35 (_architecture (_out ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign)) (_port (_internal UCS ~wire 0 35 (_architecture (_out ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign)) (_port (_internal UIOR ~wire 0 35 (_architecture (_out ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign)) (_port (_internal UIOW ~wire 0 36 (_architecture (_out ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign)) (_type (_internal ~[7:0]wire~ 0 36 (_array ~wire ((_downto (i 7) (i 0)))))) (_port (_internal EN ~[7:0]wire~ 0 36 (_architecture (_out ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign)) (_port (_internal PD ~[7:0]wire~ 0 36 (_architecture (_out ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign)) (_port (_internal UAD ~[7:0]wire~ 0 36 (_architecture (_out ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign)) (_port (_internal SCL ~wire 0 36 (_architecture (_inout ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign)) (_port (_internal AD ~[7:0]wire~ 0 36 (_architecture (_inout ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign)) (_port (_internal SD ~[7:0]wire~ 0 36 (_architecture (_inout ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign)) (_port (_internal UD ~[7:0]wire~ 0 36 (_architecture (_inout ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign)) (_signal (_internal NET1432 ~wire 0 137 (_architecture (_uni ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign)) (_signal (_internal NET1440 ~wire 0 138 (_architecture (_uni ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign)) (_signal (_internal NET1448 ~wire 0 139 (_architecture (_uni ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign)) (_signal (_internal NET1456 ~wire 0 140 (_architecture (_uni ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign)) (_signal (_internal NET1474 ~wire 0 141 (_architecture (_uni ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign)) (_signal (_internal NET1523 ~wire 0 142 (_architecture (_uni ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign)) (_signal (_internal NET1535 ~wire 0 143 (_architecture (_uni ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign)) (_signal (_internal NET1764 ~wire 0 144 (_architecture (_uni ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign)) (_signal (_internal NET2480 ~wire 0 145 (_architecture (_uni ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign)) (_signal (_internal NET2519 ~wire 0 146 (_architecture (_uni ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign)) (_signal (_internal NET2533 ~wire 0 147 (_architecture (_uni ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign)) (_signal (_internal ADDR ~[7:0]wire~ 0 148 (_architecture (_uni ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign)) (_signal (_internal inDATA ~[7:0]wire~ 0 149 (_architecture (_uni ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign)) (_signal (_internal outDATA ~[7:0]wire~ 0 150 (_architecture (_uni ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign)) (_subprogram ) (_type (_external ~wire (vl verilog_logic wire))) (_type (_external ~reg (vl verilog_logic reg))) (_type (_external ~event (vl verilog_logic event))) (_type (_external ~wand (vl verilog_logic wand))) (_type (_external ~wor (vl verilog_logic wor))) (_type (_external ~tri1 (vl verilog_logic tri1))) (_type (_external ~tri0 (vl verilog_logic tri0))) (_type (_external ~trireg (vl verilog_logic trireg))) (_type (_external ~supply0 (vl verilog_logic supply0))) (_type (_external ~supply1 (vl verilog_logic supply1))) (_type (_external ~real (vl verilog_logic real))) (_type (_external ~realtime (vl verilog_logic realtime))) (_type (_external ~tri (vl verilog_logic tri))) (_type (_external ~triand (vl verilog_logic triand))) (_type (_external ~trior (vl verilog_logic trior))) (_type (_external ~bit (vl verilog_logic bit))) (_type (_external ~extstd.standard.integer (std standard integer))) (_type (_external ~extstd.standard.bit (std standard bit))) ) (_defparam ) (_scope ) (_instantiation U1 0 154 (_entity . Fub2) (_port ((ADDR) (ADDR)) ((AS) (AS)) ((RD) (RD)) ((Rslct0) (NET1535)) ((Rslct1) (NET2533)) ((Rslct6) (NET1523)) ((WR) (WR)) ((Wslct0) (NET2480)) ((Wslct1) (NET2519)) ((Wslct2) (NET1432)) ((Wslct3) (NET1440)) ((Wslct4) (NET1456)) ((Wslct5) (NET1474)) ((Wslct6) (NET1448)) ) (_strength strong0 strong1) ) (_instantiation U2 0 174 (_entity . Fub5) (_port ((AD) (AD)) ((ADDR) (ADDR)) ((AS) (AS)) ((MCLK) (MCLK)) ((RD) (RD)) ((Reset) (Reset)) ((WR) (WR)) ((inDATA) (inDATA)) ((outDATA) (outDATA)) ) (_strength strong0 strong1) ) (_instantiation U3 0 189 (_entity . Fub9) (_port ((ADDR) (ADDR)) ((IORD) (IORD)) ((IOWR) (IOWR)) ((IRQ) (IRQ)) ((RD) (RD)) ((SA) (SA)) ((SD) (SD)) ((SystemEN) (SystemEN)) ((UARTaddr) (UAD)) ((UARTcs) (UCS)) ((UDATA) (UD)) ((UINT) (UINT)) ((UIOR) (UIOR)) ((UIOW) (UIOW)) ((WR) (WR)) ((inDATA) (inDATA)) ((outDATA) (outDATA)) ) (_strength strong0 strong1) ) (_instantiation U4 0 212 (_entity . Fub3) (_port ((CONcon0) (CONcon0)) ((CONcon1) (CONcon1)) ((CONcon2) (CONcon2)) ((CONextr) (CONextr)) ((CONmodem) (CONmodem)) ((LOOPcon0) (LOOPcon0)) ((LOOPcon1) (LOOPcon1)) ((LOOPcon2) (LOOPcon2)) ((LOOPextr) (LOOPextr)) ((LOOPmodem) (LOOPmodem)) ((MCLK) (MCLK)) ((Reset) (Reset)) ((SLPYCON) (NET1432)) ((SLPYLP) (NET1440)) ((inDATA) (inDATA)) ) (_strength strong0 strong1) ) (_instantiation U5 0 233 (_entity . Fub8) (_port ((Enable) (EN)) ((MCLK) (MCLK)) ((PwrDwn) (PD)) ((Reset) (Reset)) ((SLPYEN) (NET1456)) ((SLPYPD) (NET1474)) ((inDATA) (inDATA)) ) (_strength strong0 strong1) ) (_instantiation U6 0 246 (_entity . Fub7) (_port ((AM0EN) (AM0EN)) ((AM0Status) (AM0Status)) ((AM1EN) (AM1EN)) ((AM1Status) (AM1Status)) ((AM2EN) (AM2EN)) ((AM2Status) (AM2Status)) ((CameraEN) (CameraEN)) ((CameraStatus) (CameraStatus)) ((DwarfEN) (DwarfEN)) ((ExternalEN) (ExternalEN)) ((ExternalStatus) (ExternalStatus)) ((MCLK) (MCLK)) ((ModemEN) (ModemEN)) ((ModemStatus) (ModemStatus)) ((Reset) (Reset)) ((SLPYPWR) (NET1448)) ((SLPYSTATUS) (NET1523)) ((SystemEN) (SystemEN)) ((SystemStatus) (SystemStatus)) ((inDATA) (inDATA)) ((outDATA) (outDATA)) ) (_strength strong0 strong1) ) (_instantiation U7 0 273 (_entity . Fub4) (_port ((Inc) (SCLinc)) ((MCLK) (MCLK)) ((SCL) (SCL)) ((SCLint) (NET1764)) ((SCLreset) (SCLreset)) ((SLPYI2CCNTr) (NET1535)) ((outDATA) (outDATA)) ) (_strength strong0 strong1) ) (_instantiation U8 0 286 (_entity . Fub6) (_port ((AM0Status) (AM0Status)) ((AM1Status) (AM1Status)) ((AM2Status) (AM2Status)) ((CameraStatus) (CameraStatus)) ((ExternalStatus) (ExternalStatus)) ((INT) (INT)) ((MCLK) (MCLK)) ((ModemStatus) (ModemStatus)) ((Reset) (Reset)) ((SCLint) (NET1764)) ((SLPYIEw) (NET2480)) ((SLPYIFGr) (NET2533)) ((SLPYIFGw) (NET2519)) ((SystemEN) (SystemEN)) ((SystemStatus) (SystemStatus)) ((UARTint) (UINT)) ((inDATA) (inDATA)) ((outDATA) (outDATA)) ) (_strength strong0 strong1) ) (_model . SleepyPLD 1 -1) ) V 000049 55 10290 1094580429442 SleepyTB (_unit VERILOG 6.349C.6.256 (SleepyTB 0 32 (SleepyTB 0 32 )) (_version v32) (_time 1094580429395 2004.09.07 11:07:09) (_source (\./compile/sleepytb.v\ VERILOG (\./compile/sleepytb.v\ VERILOG))) (_use (std(standard))(vl(verilog_logic))) (_base (E 1)) (_entity (_time 1094580429395) (_use ) ) (_timescale 1ps 1ps) (_parameters dbg accs ) (_attribute ) (_object (_port (_internal AM0status ~wire 0 32 (_architecture (_in ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign)) (_port (_internal AM1status ~wire 0 32 (_architecture (_in ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign)) (_port (_internal AM2status ~wire 0 32 (_architecture (_in ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign)) (_port (_internal CameraStatus ~wire 0 32 (_architecture (_in ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign)) (_port (_internal ExternalStatus ~wire 0 32 (_architecture (_in ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign)) (_port (_internal IORD ~wire 0 32 (_architecture (_in ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign)) (_port (_internal IOWR ~wire 0 32 (_architecture (_in ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign)) (_port (_internal ModemStatus ~wire 0 32 (_architecture (_in ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign)) (_port (_internal Reset ~wire 0 32 (_architecture (_in ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign)) (_port (_internal SCLinc ~wire 0 32 (_architecture (_in ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign)) (_port (_internal SCLreset ~wire 0 33 (_architecture (_in ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign)) (_port (_internal SystemStatus ~wire 0 33 (_architecture (_in ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign)) (_port (_internal UINT ~wire 0 33 (_architecture (_in ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign)) (_type (_internal ~[13:0]wire~ 0 33 (_array ~wire ((_downto (i 13) (i 0)))))) (_port (_internal SA ~[13:0]wire~ 0 33 (_architecture (_in ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign)) (_port (_internal AM0EN ~wire 0 33 (_architecture (_out ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign)) (_port (_internal AM1EN ~wire 0 33 (_architecture (_out ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign)) (_port (_internal AM2EN ~wire 0 33 (_architecture (_out ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign)) (_port (_internal CONcon0 ~wire 0 33 (_architecture (_out ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign)) (_port (_internal CONcon1 ~wire 0 33 (_architecture (_out ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign)) (_port (_internal CONcon2 ~wire 0 33 (_architecture (_out ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign)) (_port (_internal CONextr ~wire 0 34 (_architecture (_out ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign)) (_port (_internal CONmodem ~wire 0 34 (_architecture (_out ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign)) (_port (_internal CameraEN ~wire 0 34 (_architecture (_out ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign)) (_port (_internal DwarfEN ~wire 0 34 (_architecture (_out ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign)) (_port (_internal ExternalEN ~wire 0 34 (_architecture (_out ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign)) (_port (_internal INT ~wire 0 34 (_architecture (_out ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign)) (_port (_internal IRQ ~wire 0 34 (_architecture (_out ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign)) (_port (_internal LOOPcon0 ~wire 0 34 (_architecture (_out ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign)) (_port (_internal LOOPcon1 ~wire 0 34 (_architecture (_out ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign)) (_port (_internal LOOPcon2 ~wire 0 34 (_architecture (_out ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign)) (_port (_internal LOOPextr ~wire 0 35 (_architecture (_out ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign)) (_port (_internal LOOPmodem ~wire 0 35 (_architecture (_out ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign)) (_port (_internal ModemEN ~wire 0 35 (_architecture (_out ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign)) (_port (_internal SystemEN ~wire 0 35 (_architecture (_out ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign)) (_port (_internal UCS ~wire 0 35 (_architecture (_out ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign)) (_port (_internal UIOR ~wire 0 35 (_architecture (_out ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign)) (_port (_internal UIOW ~wire 0 35 (_architecture (_out ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign)) (_type (_internal ~[7:0]wire~ 0 35 (_array ~wire ((_downto (i 7) (i 0)))))) (_port (_internal EN ~[7:0]wire~ 0 35 (_architecture (_out ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign)) (_port (_internal PD ~[7:0]wire~ 0 35 (_architecture (_out ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign)) (_port (_internal UAD ~[7:0]wire~ 0 35 (_architecture (_out ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign)) (_port (_internal SD ~[7:0]wire~ 0 36 (_architecture (_inout ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign)) (_port (_internal UD ~[7:0]wire~ 0 36 (_architecture (_inout ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign)) (_signal (_internal NET21 ~wire 0 125 (_architecture (_uni ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign)) (_signal (_internal NET25 ~wire 0 126 (_architecture (_uni ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign)) (_signal (_internal NET29 ~wire 0 127 (_architecture (_uni ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign)) (_signal (_internal NET33 ~wire 0 128 (_architecture (_uni ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign)) (_signal (_internal AD ~[7:0]wire~ 0 129 (_architecture (_uni ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign)) (_subprogram ) (_type (_external ~wire (vl verilog_logic wire))) (_type (_external ~reg (vl verilog_logic reg))) (_type (_external ~event (vl verilog_logic event))) (_type (_external ~wand (vl verilog_logic wand))) (_type (_external ~wor (vl verilog_logic wor))) (_type (_external ~tri1 (vl verilog_logic tri1))) (_type (_external ~tri0 (vl verilog_logic tri0))) (_type (_external ~trireg (vl verilog_logic trireg))) (_type (_external ~supply0 (vl verilog_logic supply0))) (_type (_external ~supply1 (vl verilog_logic supply1))) (_type (_external ~real (vl verilog_logic real))) (_type (_external ~realtime (vl verilog_logic realtime))) (_type (_external ~tri (vl verilog_logic tri))) (_type (_external ~triand (vl verilog_logic triand))) (_type (_external ~trior (vl verilog_logic trior))) (_type (_external ~bit (vl verilog_logic bit))) (_type (_external ~extstd.standard.integer (std standard integer))) (_type (_external ~extstd.standard.bit (std standard bit))) ) (_defparam ) (_scope ) (_instantiation U1 0 133 (_entity . MSP) (_port ((AD) (AD)) ((AS) (NET25)) ((Mclk) (NET33)) ((RD) (NET29)) ((WR) (NET21)) ) (_strength strong0 strong1) ) (_instantiation U2 0 144 (_entity . SleepyPLD) (_port ((AD) (AD)) ((AM0EN) (AM0EN)) ((AM0Status) (AM0status)) ((AM1EN) (AM1EN)) ((AM1Status) (AM1status)) ((AM2EN) (AM2EN)) ((AM2Status) (AM2status)) ((AS) (NET25)) ((CONcon0) (CONcon0)) ((CONcon1) (CONcon1)) ((CONcon2) (CONcon2)) ((CONextr) (CONextr)) ((CONmodem) (CONmodem)) ((CameraEN) (CameraEN)) ((CameraStatus) (CameraStatus)) ((DwarfEN) (DwarfEN)) ((EN) (EN)) ((ExternalEN) (ExternalEN)) ((ExternalStatus) (ExternalStatus)) ((INT) (INT)) ((IORD) (IORD)) ((IOWR) (IOWR)) ((IRQ) (IRQ)) ((LOOPcon0) (LOOPcon0)) ((LOOPcon1) (LOOPcon1)) ((LOOPcon2) (LOOPcon2)) ((LOOPextr) (LOOPextr)) ((LOOPmodem) (LOOPmodem)) ((MCLK) (NET33)) ((ModemEN) (ModemEN)) ((ModemStatus) (ModemStatus)) ((PD) (PD)) ((RD) (NET29)) ((Reset) (Reset)) ((SA) (SA)) ((SCLinc) (SCLinc)) ((SCLreset) (SCLreset)) ((SD) (SD)) ((SystemEN) (SystemEN)) ((SystemStatus) (SystemStatus)) ((UAD) (UAD)) ((UCS) (UCS)) ((UD) (UD)) ((UINT) (UINT)) ((UIOR) (UIOR)) ((UIOW) (UIOW)) ((WR) (NET21)) ((SCL) (_open)) ) (_strength strong0 strong1) ) (_model . SleepyTB 1 -1) ) V 000050 55 14617 1094580932098 SleepyPLD (_unit VERILOG 6.349C.6.256 (SleepyPLD 0 32 (SleepyPLD 0 32 )) (_version v32) (_time 1094580932004 2004.09.07 11:15:32) (_source (\./compile/sleepypld.v\ VERILOG (\./compile/sleepypld.v\ VERILOG))) (_use (std(standard))(vl(verilog_logic))) (_base (E 1)) (_entity (_time 1094580932004) (_use ) ) (_timescale 1ps 1ps) (_parameters dbg accs ) (_attribute ) (_object (_port (_internal AM0Status ~wire 0 32 (_architecture (_in ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign)) (_port (_internal AM1Status ~wire 0 32 (_architecture (_in ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign)) (_port (_internal AM2Status ~wire 0 32 (_architecture (_in ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign)) (_port (_internal AS ~wire 0 32 (_architecture (_in ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign)) (_port (_internal CameraStatus ~wire 0 32 (_architecture (_in ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign)) (_port (_internal ExternalStatus ~wire 0 32 (_architecture (_in ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign)) (_port (_internal IORD ~wire 0 32 (_architecture (_in ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign)) (_port (_internal IOWR ~wire 0 32 (_architecture (_in ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign)) (_port (_internal MCLK ~wire 0 32 (_architecture (_in ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign)) (_port (_internal ModemStatus ~wire 0 32 (_architecture (_in ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign)) (_port (_internal RD ~wire 0 33 (_architecture (_in ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign)) (_port (_internal Reset ~wire 0 33 (_architecture (_in ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign)) (_port (_internal SCLinc ~wire 0 33 (_architecture (_in ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign)) (_port (_internal SCLreset ~wire 0 33 (_architecture (_in ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign)) (_port (_internal SystemStatus ~wire 0 33 (_architecture (_in ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign)) (_port (_internal UINT ~wire 0 33 (_architecture (_in ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign)) (_port (_internal WR ~wire 0 33 (_architecture (_in ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign)) (_type (_internal ~[13:0]wire~ 0 33 (_array ~wire ((_downto (i 13) (i 0)))))) (_port (_internal SA ~[13:0]wire~ 0 33 (_architecture (_in ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign)) (_port (_internal AM0EN ~wire 0 33 (_architecture (_out ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign)) (_port (_internal AM1EN ~wire 0 33 (_architecture (_out ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign)) (_port (_internal AM2EN ~wire 0 34 (_architecture (_out ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign)) (_port (_internal CONcon0 ~wire 0 34 (_architecture (_out ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign)) (_port (_internal CONcon1 ~wire 0 34 (_architecture (_out ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign)) (_port (_internal CONcon2 ~wire 0 34 (_architecture (_out ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign)) (_port (_internal CONextr ~wire 0 34 (_architecture (_out ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign)) (_port (_internal CONmodem ~wire 0 34 (_architecture (_out ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign)) (_port (_internal CameraEN ~wire 0 34 (_architecture (_out ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign)) (_port (_internal DwarfEN ~wire 0 34 (_architecture (_out ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign)) (_port (_internal ExternalEN ~wire 0 34 (_architecture (_out ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign)) (_port (_internal INT ~wire 0 34 (_architecture (_out ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign)) (_port (_internal IRQ ~wire 0 35 (_architecture (_out ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign)) (_port (_internal LOOPcon0 ~wire 0 35 (_architecture (_out ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign)) (_port (_internal LOOPcon1 ~wire 0 35 (_architecture (_out ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign)) (_port (_internal LOOPcon2 ~wire 0 35 (_architecture (_out ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign)) (_port (_internal LOOPextr ~wire 0 35 (_architecture (_out ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign)) (_port (_internal LOOPmodem ~wire 0 35 (_architecture (_out ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign)) (_port (_internal ModemEN ~wire 0 35 (_architecture (_out ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign)) (_port (_internal SystemEN ~wire 0 35 (_architecture (_out ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign)) (_port (_internal UCS ~wire 0 35 (_architecture (_out ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign)) (_port (_internal UIOR ~wire 0 35 (_architecture (_out ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign)) (_port (_internal UIOW ~wire 0 36 (_architecture (_out ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign)) (_type (_internal ~[7:0]wire~ 0 36 (_array ~wire ((_downto (i 7) (i 0)))))) (_port (_internal EN ~[7:0]wire~ 0 36 (_architecture (_out ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign)) (_port (_internal PD ~[7:0]wire~ 0 36 (_architecture (_out ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign)) (_port (_internal UAD ~[7:0]wire~ 0 36 (_architecture (_out ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign)) (_port (_internal SCL ~wire 0 36 (_architecture (_inout ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign)) (_port (_internal AD ~[7:0]wire~ 0 36 (_architecture (_inout ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign)) (_port (_internal SD ~[7:0]wire~ 0 36 (_architecture (_inout ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign)) (_port (_internal UD ~[7:0]wire~ 0 36 (_architecture (_inout ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign)) (_signal (_internal NET1432 ~wire 0 137 (_architecture (_uni ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign)) (_signal (_internal NET1440 ~wire 0 138 (_architecture (_uni ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign)) (_signal (_internal NET1448 ~wire 0 139 (_architecture (_uni ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign)) (_signal (_internal NET1456 ~wire 0 140 (_architecture (_uni ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign)) (_signal (_internal NET1474 ~wire 0 141 (_architecture (_uni ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign)) (_signal (_internal NET1523 ~wire 0 142 (_architecture (_uni ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign)) (_signal (_internal NET1535 ~wire 0 143 (_architecture (_uni ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign)) (_signal (_internal NET1764 ~wire 0 144 (_architecture (_uni ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign)) (_signal (_internal NET2480 ~wire 0 145 (_architecture (_uni ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign)) (_signal (_internal NET2519 ~wire 0 146 (_architecture (_uni ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign)) (_signal (_internal NET2533 ~wire 0 147 (_architecture (_uni ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign)) (_signal (_internal ADDR ~[7:0]wire~ 0 148 (_architecture (_uni ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign)) (_signal (_internal inDATA ~[7:0]wire~ 0 149 (_architecture (_uni ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign)) (_signal (_internal outDATA ~[7:0]wire~ 0 150 (_architecture (_uni ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign)) (_subprogram ) (_type (_external ~wire (vl verilog_logic wire))) (_type (_external ~reg (vl verilog_logic reg))) (_type (_external ~event (vl verilog_logic event))) (_type (_external ~wand (vl verilog_logic wand))) (_type (_external ~wor (vl verilog_logic wor))) (_type (_external ~tri1 (vl verilog_logic tri1))) (_type (_external ~tri0 (vl verilog_logic tri0))) (_type (_external ~trireg (vl verilog_logic trireg))) (_type (_external ~supply0 (vl verilog_logic supply0))) (_type (_external ~supply1 (vl verilog_logic supply1))) (_type (_external ~real (vl verilog_logic real))) (_type (_external ~realtime (vl verilog_logic realtime))) (_type (_external ~tri (vl verilog_logic tri))) (_type (_external ~triand (vl verilog_logic triand))) (_type (_external ~trior (vl verilog_logic trior))) (_type (_external ~bit (vl verilog_logic bit))) (_type (_external ~extstd.standard.integer (std standard integer))) (_type (_external ~extstd.standard.bit (std standard bit))) ) (_defparam ) (_scope ) (_instantiation U1 0 154 (_entity . AddDecode) (_port ((ADDR) (ADDR)) ((AS) (AS)) ((RD) (RD)) ((Rslct0) (NET1535)) ((Rslct1) (NET2533)) ((Rslct6) (NET1523)) ((WR) (WR)) ((Wslct0) (NET2480)) ((Wslct1) (NET2519)) ((Wslct2) (NET1432)) ((Wslct3) (NET1440)) ((Wslct4) (NET1456)) ((Wslct5) (NET1474)) ((Wslct6) (NET1448)) ) (_strength strong0 strong1) ) (_instantiation U2 0 174 (_entity . Interface) (_port ((AD) (AD)) ((ADDR) (ADDR)) ((AS) (AS)) ((MCLK) (MCLK)) ((RD) (RD)) ((Reset) (Reset)) ((WR) (WR)) ((inDATA) (inDATA)) ((outDATA) (outDATA)) ((ASleading) (_open)) ) (_strength strong0 strong1) ) (_instantiation U3 0 189 (_entity . UARTaddr) (_port ((ADDR) (ADDR)) ((IORD) (IORD)) ((IOWR) (IOWR)) ((IRQ) (IRQ)) ((RD) (RD)) ((SA) (SA)) ((SD) (SD)) ((SystemEN) (SystemEN)) ((UARTaddr) (UAD)) ((UARTcs) (UCS)) ((UDATA) (UD)) ((UINT) (UINT)) ((UIOR) (UIOR)) ((UIOW) (UIOW)) ((WR) (WR)) ((inDATA) (inDATA)) ((outDATA) (outDATA)) ) (_strength strong0 strong1) ) (_instantiation U4 0 212 (_entity . GalvRelay) (_port ((CONcon0) (CONcon0)) ((CONcon1) (CONcon1)) ((CONcon2) (CONcon2)) ((CONextr) (CONextr)) ((CONmodem) (CONmodem)) ((LOOPcon0) (LOOPcon0)) ((LOOPcon1) (LOOPcon1)) ((LOOPcon2) (LOOPcon2)) ((LOOPextr) (LOOPextr)) ((LOOPmodem) (LOOPmodem)) ((MCLK) (MCLK)) ((Reset) (Reset)) ((SLPYCON) (NET1432)) ((SLPYLP) (NET1440)) ((inDATA) (inDATA)) ) (_strength strong0 strong1) ) (_instantiation U5 0 233 (_entity . TransceiverControl) (_port ((Enable) (EN)) ((MCLK) (MCLK)) ((PwrDwn) (PD)) ((Reset) (Reset)) ((SLPYEN) (NET1456)) ((SLPYPD) (NET1474)) ((inDATA) (inDATA)) ) (_strength strong0 strong1) ) (_instantiation U6 0 246 (_entity . PwrControl) (_port ((AM0EN) (AM0EN)) ((AM0Status) (AM0Status)) ((AM1EN) (AM1EN)) ((AM1Status) (AM1Status)) ((AM2EN) (AM2EN)) ((AM2Status) (AM2Status)) ((CameraEN) (CameraEN)) ((CameraStatus) (CameraStatus)) ((DwarfEN) (DwarfEN)) ((ExternalEN) (ExternalEN)) ((ExternalStatus) (ExternalStatus)) ((MCLK) (MCLK)) ((ModemEN) (ModemEN)) ((ModemStatus) (ModemStatus)) ((Reset) (Reset)) ((SLPYPWR) (NET1448)) ((SLPYSTATUS) (NET1523)) ((SystemEN) (SystemEN)) ((SystemStatus) (SystemStatus)) ((inDATA) (inDATA)) ((outDATA) (outDATA)) ) (_strength strong0 strong1) ) (_instantiation U7 0 273 (_entity . I2Cfix) (_port ((Inc) (SCLinc)) ((MCLK) (MCLK)) ((SCL) (SCL)) ((SCLint) (NET1764)) ((SCLreset) (SCLreset)) ((SLPYI2CCNTr) (NET1535)) ((outDATA) (outDATA)) ((SCLenable) (_open)) ) (_strength strong0 strong1) ) (_instantiation U8 0 286 (_entity . Interrupt) (_port ((AM0Status) (AM0Status)) ((AM1Status) (AM1Status)) ((AM2Status) (AM2Status)) ((CameraStatus) (CameraStatus)) ((ExternalStatus) (ExternalStatus)) ((INT) (INT)) ((MCLK) (MCLK)) ((ModemStatus) (ModemStatus)) ((Reset) (Reset)) ((SCLint) (NET1764)) ((SLPYIEw) (NET2480)) ((SLPYIFGr) (NET2533)) ((SLPYIFGw) (NET2519)) ((SystemEN) (SystemEN)) ((SystemStatus) (SystemStatus)) ((UARTint) (UINT)) ((inDATA) (inDATA)) ((outDATA) (outDATA)) ) (_strength strong0 strong1) ) (_model . SleepyPLD 1 -1) ) V 000049 55 10290 1094580955380 SleepyTB (_unit VERILOG 6.349C.6.256 (SleepyTB 0 32 (SleepyTB 0 32 )) (_version v32) (_time 1094580955332 2004.09.07 11:15:55) (_source (\./compile/sleepytb.v\ VERILOG (\./compile/sleepytb.v\ VERILOG))) (_use (std(standard))(vl(verilog_logic))) (_base (E 1)) (_entity (_time 1094580955332) (_use ) ) (_timescale 1ps 1ps) (_parameters dbg accs ) (_attribute ) (_object (_port (_internal AM0status ~wire 0 32 (_architecture (_in ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign)) (_port (_internal AM1status ~wire 0 32 (_architecture (_in ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign)) (_port (_internal AM2status ~wire 0 32 (_architecture (_in ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign)) (_port (_internal CameraStatus ~wire 0 32 (_architecture (_in ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign)) (_port (_internal ExternalStatus ~wire 0 32 (_architecture (_in ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign)) (_port (_internal IORD ~wire 0 32 (_architecture (_in ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign)) (_port (_internal IOWR ~wire 0 32 (_architecture (_in ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign)) (_port (_internal ModemStatus ~wire 0 32 (_architecture (_in ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign)) (_port (_internal Reset ~wire 0 32 (_architecture (_in ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign)) (_port (_internal SCLinc ~wire 0 32 (_architecture (_in ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign)) (_port (_internal SCLreset ~wire 0 33 (_architecture (_in ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign)) (_port (_internal SystemStatus ~wire 0 33 (_architecture (_in ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign)) (_port (_internal UINT ~wire 0 33 (_architecture (_in ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign)) (_type (_internal ~[13:0]wire~ 0 33 (_array ~wire ((_downto (i 13) (i 0)))))) (_port (_internal SA ~[13:0]wire~ 0 33 (_architecture (_in ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign)) (_port (_internal AM0EN ~wire 0 33 (_architecture (_out ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign)) (_port (_internal AM1EN ~wire 0 33 (_architecture (_out ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign)) (_port (_internal AM2EN ~wire 0 33 (_architecture (_out ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign)) (_port (_internal CONcon0 ~wire 0 33 (_architecture (_out ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign)) (_port (_internal CONcon1 ~wire 0 33 (_architecture (_out ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign)) (_port (_internal CONcon2 ~wire 0 33 (_architecture (_out ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign)) (_port (_internal CONextr ~wire 0 34 (_architecture (_out ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign)) (_port (_internal CONmodem ~wire 0 34 (_architecture (_out ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign)) (_port (_internal CameraEN ~wire 0 34 (_architecture (_out ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign)) (_port (_internal DwarfEN ~wire 0 34 (_architecture (_out ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign)) (_port (_internal ExternalEN ~wire 0 34 (_architecture (_out ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign)) (_port (_internal INT ~wire 0 34 (_architecture (_out ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign)) (_port (_internal IRQ ~wire 0 34 (_architecture (_out ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign)) (_port (_internal LOOPcon0 ~wire 0 34 (_architecture (_out ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign)) (_port (_internal LOOPcon1 ~wire 0 34 (_architecture (_out ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign)) (_port (_internal LOOPcon2 ~wire 0 34 (_architecture (_out ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign)) (_port (_internal LOOPextr ~wire 0 35 (_architecture (_out ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign)) (_port (_internal LOOPmodem ~wire 0 35 (_architecture (_out ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign)) (_port (_internal ModemEN ~wire 0 35 (_architecture (_out ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign)) (_port (_internal SystemEN ~wire 0 35 (_architecture (_out ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign)) (_port (_internal UCS ~wire 0 35 (_architecture (_out ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign)) (_port (_internal UIOR ~wire 0 35 (_architecture (_out ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign)) (_port (_internal UIOW ~wire 0 35 (_architecture (_out ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign)) (_type (_internal ~[7:0]wire~ 0 35 (_array ~wire ((_downto (i 7) (i 0)))))) (_port (_internal EN ~[7:0]wire~ 0 35 (_architecture (_out ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign)) (_port (_internal PD ~[7:0]wire~ 0 35 (_architecture (_out ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign)) (_port (_internal UAD ~[7:0]wire~ 0 35 (_architecture (_out ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign)) (_port (_internal SD ~[7:0]wire~ 0 36 (_architecture (_inout ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign)) (_port (_internal UD ~[7:0]wire~ 0 36 (_architecture (_inout ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign)) (_signal (_internal NET21 ~wire 0 125 (_architecture (_uni ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign)) (_signal (_internal NET25 ~wire 0 126 (_architecture (_uni ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign)) (_signal (_internal NET29 ~wire 0 127 (_architecture (_uni ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign)) (_signal (_internal NET33 ~wire 0 128 (_architecture (_uni ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign)) (_signal (_internal AD ~[7:0]wire~ 0 129 (_architecture (_uni ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign)) (_subprogram ) (_type (_external ~wire (vl verilog_logic wire))) (_type (_external ~reg (vl verilog_logic reg))) (_type (_external ~event (vl verilog_logic event))) (_type (_external ~wand (vl verilog_logic wand))) (_type (_external ~wor (vl verilog_logic wor))) (_type (_external ~tri1 (vl verilog_logic tri1))) (_type (_external ~tri0 (vl verilog_logic tri0))) (_type (_external ~trireg (vl verilog_logic trireg))) (_type (_external ~supply0 (vl verilog_logic supply0))) (_type (_external ~supply1 (vl verilog_logic supply1))) (_type (_external ~real (vl verilog_logic real))) (_type (_external ~realtime (vl verilog_logic realtime))) (_type (_external ~tri (vl verilog_logic tri))) (_type (_external ~triand (vl verilog_logic triand))) (_type (_external ~trior (vl verilog_logic trior))) (_type (_external ~bit (vl verilog_logic bit))) (_type (_external ~extstd.standard.integer (std standard integer))) (_type (_external ~extstd.standard.bit (std standard bit))) ) (_defparam ) (_scope ) (_instantiation U1 0 133 (_entity . MSP) (_port ((AD) (AD)) ((AS) (NET25)) ((Mclk) (NET33)) ((RD) (NET29)) ((WR) (NET21)) ) (_strength strong0 strong1) ) (_instantiation U2 0 144 (_entity . SleepyPLD) (_port ((AD) (AD)) ((AM0EN) (AM0EN)) ((AM0Status) (AM0status)) ((AM1EN) (AM1EN)) ((AM1Status) (AM1status)) ((AM2EN) (AM2EN)) ((AM2Status) (AM2status)) ((AS) (NET25)) ((CONcon0) (CONcon0)) ((CONcon1) (CONcon1)) ((CONcon2) (CONcon2)) ((CONextr) (CONextr)) ((CONmodem) (CONmodem)) ((CameraEN) (CameraEN)) ((CameraStatus) (CameraStatus)) ((DwarfEN) (DwarfEN)) ((EN) (EN)) ((ExternalEN) (ExternalEN)) ((ExternalStatus) (ExternalStatus)) ((INT) (INT)) ((IORD) (IORD)) ((IOWR) (IOWR)) ((IRQ) (IRQ)) ((LOOPcon0) (LOOPcon0)) ((LOOPcon1) (LOOPcon1)) ((LOOPcon2) (LOOPcon2)) ((LOOPextr) (LOOPextr)) ((LOOPmodem) (LOOPmodem)) ((MCLK) (NET33)) ((ModemEN) (ModemEN)) ((ModemStatus) (ModemStatus)) ((PD) (PD)) ((RD) (NET29)) ((Reset) (Reset)) ((SA) (SA)) ((SCLinc) (SCLinc)) ((SCLreset) (SCLreset)) ((SD) (SD)) ((SystemEN) (SystemEN)) ((SystemStatus) (SystemStatus)) ((UAD) (UAD)) ((UCS) (UCS)) ((UD) (UD)) ((UINT) (UINT)) ((UIOR) (UIOR)) ((UIOW) (UIOW)) ((WR) (NET21)) ((SCL) (_open)) ) (_strength strong0 strong1) ) (_model . SleepyTB 1 -1) ) I 000050 55 6147 1094590799333 AddDecode (_unit VERILOG 6.349C.6.256 (AddDecode 0 25 (AddDecode 0 25 )) (_version v32) (_time 1094590799238 2004.09.07 13:59:59) (_source (\./src/adddecode.v\ VERILOG (\./src/adddecode.v\ VERILOG))) (_use (std(standard))(vl(verilog_logic))) (_base (E 12)) (_entity (_time 1094590799238) (_use ) ) (_timescale 1ps 1ps) (_parameters dbg accs ) (_attribute ) (_object (_port (_internal Wslct3 ~wire 0 25 (_architecture (_out ))) (_net ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign)) (_port (_internal Wslct4 ~wire 0 25 (_architecture (_out ))) (_net ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign)) (_port (_internal Wslct5 ~wire 0 25 (_architecture (_out ))) (_net ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign)) (_port (_internal Wslct6 ~wire 0 25 (_architecture (_out ))) (_net ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign)) (_port (_internal AS ~wire 0 25 (_architecture (_in ))) (_net ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign)) (_port (_internal RD ~wire 0 25 (_architecture (_in ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign)) (_port (_internal Rslct0 ~wire 0 25 (_architecture (_out ))) (_net ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign)) (_port (_internal Rslct1 ~wire 0 25 (_architecture (_out ))) (_net ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign)) (_port (_internal WR ~wire 0 25 (_architecture (_in ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign)) (_type (_internal ~[7:0]wire~ 0 25 (_array ~wire ((_downto (i 7) (i 0)))))) (_port (_internal ADDR ~[7:0]wire~ 0 25 (_architecture (_in ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign)) (_port (_internal Wslct0 ~wire 0 25 (_architecture (_out ))) (_net ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign)) (_port (_internal Rslct6 ~wire 0 25 (_architecture (_out ))) (_net ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign)) (_port (_internal Wslct1 ~wire 0 25 (_architecture (_out ))) (_net ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign)) (_port (_internal Wslct2 ~wire 0 25 (_architecture (_out ))) (_net ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign)) (_type (_internal ~[7:0]reg~ 0 67 (_array ~reg ((_downto (i 7) (i 0)))))) (_signal (_internal Select.Address ~[7:0]reg~ 0 67 (_subprogram Select (_in ))) (_reg ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign)) (_signal (_internal Select.Location ~[7:0]reg~ 0 68 (_subprogram Select (_in ))) (_reg ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign)) (_signal (_internal Select.RD ~reg 0 69 (_subprogram Select (_in ))) (_reg ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign)) (_signal (_internal Select.WR ~reg 0 69 (_subprogram Select (_in ))) (_reg ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign)) (_signal (_internal Select.RorW ~reg 0 70 (_subprogram Select (_in ))) (_reg ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign)) (_signal (_internal Select.Select ~reg 0 0 (_subprogram Select (_out ))) (_reg ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign)) (_subprogram (_internal Select 10 0 66 (_architecture (_function)(_target(19)) (_read(18)(16)(17)(9)(15)) )) ) (_type (_external ~wire (vl verilog_logic wire))) (_type (_external ~reg (vl verilog_logic reg))) (_type (_external ~event (vl verilog_logic event))) (_type (_external ~wand (vl verilog_logic wand))) (_type (_external ~wor (vl verilog_logic wor))) (_type (_external ~tri1 (vl verilog_logic tri1))) (_type (_external ~tri0 (vl verilog_logic tri0))) (_type (_external ~trireg (vl verilog_logic trireg))) (_type (_external ~supply0 (vl verilog_logic supply0))) (_type (_external ~supply1 (vl verilog_logic supply1))) (_type (_external ~real (vl verilog_logic real))) (_type (_external ~realtime (vl verilog_logic realtime))) (_type (_external ~tri (vl verilog_logic tri))) (_type (_external ~triand (vl verilog_logic triand))) (_type (_external ~trior (vl verilog_logic trior))) (_type (_external ~bit (vl verilog_logic bit))) (_type (_external ~extstd.standard.integer (std standard integer))) (_type (_external ~extstd.standard.bit (std standard bit))) (_process (#ASSIGN#78_0 (_architecture 0 0 78 (_process (_simple) (_target(10)) (_sensitivity(9)(5)(8)) (_call(0)) ))) (#ASSIGN#80_1 (_architecture 1 0 80 (_process (_simple) (_target(12)) (_sensitivity(9)(5)(8)) (_call(0)) ))) (#ASSIGN#82_2 (_architecture 2 0 82 (_process (_simple) (_target(13)) (_sensitivity(9)(5)(8)) (_call(0)) ))) (#ASSIGN#84_3 (_architecture 3 0 84 (_process (_simple) (_target(0)) (_sensitivity(9)(5)(8)) (_call(0)) ))) (#ASSIGN#86_4 (_architecture 4 0 86 (_process (_simple) (_target(1)) (_sensitivity(9)(5)(8)) (_call(0)) ))) (#ASSIGN#88_5 (_architecture 5 0 88 (_process (_simple) (_target(2)) (_sensitivity(9)(5)(8)) (_call(0)) ))) (#ASSIGN#90_6 (_architecture 6 0 90 (_process (_simple) (_target(3)) (_sensitivity(9)(5)(8)) (_call(0)) ))) (#ASSIGN#93_7 (_architecture 7 0 93 (_process (_simple) (_target(6)) (_sensitivity(9)(5)(8)) (_call(0)) ))) (#ASSIGN#95_8 (_architecture 8 0 95 (_process (_simple) (_target(7)) (_sensitivity(9)(5)(8)) (_call(0)) ))) (#ASSIGN#97_9 (_architecture 9 0 97 (_process (_simple) (_target(11)) (_sensitivity(9)(5)(8)) (_call(0)) ))) (#INTERNAL#0_11 (_internal 11 0 0 (_process (_virtual)))) ) ) (_defparam ) (_scope (_unit Select function 0 66 ) ) (_model . AddDecode 12 -1) ) V 000049 55 13094 1094591988816 SleepyTB (_unit VERILOG 6.349C.6.256 (SleepyTB 0 32 (SleepyTB 0 32 )) (_version v32) (_time 1094591988738 2004.09.07 14:19:48) (_source (\./compile/sleepytb.v\ VERILOG (\./compile/sleepytb.v\ VERILOG))) (_use (std(standard))(vl(verilog_logic))) (_base (E 15)) (_entity (_time 1094591988738) (_use ) ) (_timescale 1ps 1ps) (_parameters dbg accs ) (_attribute ) (_object (_port (_internal AM0status ~wire 0 32 (_architecture (_in ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign)) (_port (_internal AM1status ~wire 0 32 (_architecture (_in ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign)) (_port (_internal AM2status ~wire 0 32 (_architecture (_in ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign)) (_port (_internal CameraStatus ~wire 0 32 (_architecture (_in ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign)) (_port (_internal ExternalStatus ~wire 0 32 (_architecture (_in ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign)) (_port (_internal IORD ~wire 0 32 (_architecture (_in ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign)) (_port (_internal IOWR ~wire 0 32 (_architecture (_in ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign)) (_port (_internal ModemStatus ~wire 0 32 (_architecture (_in ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign)) (_port (_internal Reset ~wire 0 32 (_architecture (_in ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign)) (_port (_internal SCLinc ~wire 0 32 (_architecture (_in ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign)) (_port (_internal SCLreset ~wire 0 33 (_architecture (_in ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign)) (_port (_internal SystemStatus ~wire 0 33 (_architecture (_in ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign)) (_port (_internal UINT ~wire 0 33 (_architecture (_in ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign)) (_type (_internal ~[13:0]wire~ 0 33 (_array ~wire ((_downto (i 13) (i 0)))))) (_port (_internal SA ~[13:0]wire~ 0 33 (_architecture (_in ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign)) (_port (_internal AM0EN ~wire 0 33 (_architecture (_out ))) (_net ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign)) (_port (_internal AM1EN ~wire 0 33 (_architecture (_out ))) (_net ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign)) (_port (_internal AM2EN ~wire 0 33 (_architecture (_out ))) (_net ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign)) (_port (_internal CONcon0 ~wire 0 33 (_architecture (_out ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign)) (_port (_internal CONcon1 ~wire 0 33 (_architecture (_out ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign)) (_port (_internal CONcon2 ~wire 0 33 (_architecture (_out ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign)) (_port (_internal CONextr ~wire 0 34 (_architecture (_out ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign)) (_port (_internal CONmodem ~wire 0 34 (_architecture (_out ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign)) (_port (_internal CameraEN ~wire 0 34 (_architecture (_out ))) (_net ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign)) (_port (_internal DwarfEN ~wire 0 34 (_architecture (_out ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign)) (_port (_internal ExternalEN ~wire 0 34 (_architecture (_out ))) (_net ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign)) (_port (_internal INT ~wire 0 34 (_architecture (_out ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign)) (_port (_internal IRQ ~wire 0 34 (_architecture (_out ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign)) (_port (_internal LOOPcon0 ~wire 0 34 (_architecture (_out ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign)) (_port (_internal LOOPcon1 ~wire 0 34 (_architecture (_out ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign)) (_port (_internal LOOPcon2 ~wire 0 34 (_architecture (_out ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign)) (_port (_internal LOOPextr ~wire 0 35 (_architecture (_out ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign)) (_port (_internal LOOPmodem ~wire 0 35 (_architecture (_out ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign)) (_port (_internal ModemEN ~wire 0 35 (_architecture (_out ))) (_net ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign)) (_port (_internal SystemEN ~wire 0 35 (_architecture (_out ))) (_net ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign)) (_port (_internal UCS ~wire 0 35 (_architecture (_out ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign)) (_port (_internal UIOR ~wire 0 35 (_architecture (_out ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign)) (_port (_internal UIOW ~wire 0 35 (_architecture (_out ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign)) (_type (_internal ~[7:0]wire~ 0 35 (_array ~wire ((_downto (i 7) (i 0)))))) (_port (_internal EN ~[7:0]wire~ 0 35 (_architecture (_out ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign)) (_port (_internal PD ~[7:0]wire~ 0 35 (_architecture (_out ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign)) (_port (_internal UAD ~[7:0]wire~ 0 35 (_architecture (_out ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign)) (_port (_internal SD ~[7:0]wire~ 0 36 (_architecture (_inout ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign)) (_port (_internal UD ~[7:0]wire~ 0 36 (_architecture (_inout ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign)) (_signal (_internal NET1005 ~wire 0 125 (_architecture (_uni ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign)) (_signal (_internal NET21 ~wire 0 126 (_architecture (_uni ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign)) (_signal (_internal NET25 ~wire 0 127 (_architecture (_uni ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign)) (_signal (_internal NET29 ~wire 0 128 (_architecture (_uni ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign)) (_signal (_internal NET33 ~wire 0 129 (_architecture (_uni ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign)) (_signal (_internal NET951 ~wire 0 130 (_architecture (_uni ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign)) (_signal (_internal NET960 ~wire 0 131 (_architecture (_uni ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign)) (_signal (_internal NET969 ~wire 0 132 (_architecture (_uni ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign)) (_signal (_internal NET978 ~wire 0 133 (_architecture (_uni ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign)) (_signal (_internal NET987 ~wire 0 134 (_architecture (_uni ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign)) (_signal (_internal NET996 ~wire 0 135 (_architecture (_uni ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign)) (_signal (_internal AD ~[7:0]wire~ 0 136 (_architecture (_uni ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign)) (_subprogram ) (_type (_external ~wire (vl verilog_logic wire))) (_type (_external ~reg (vl verilog_logic reg))) (_type (_external ~event (vl verilog_logic event))) (_type (_external ~wand (vl verilog_logic wand))) (_type (_external ~wor (vl verilog_logic wor))) (_type (_external ~tri1 (vl verilog_logic tri1))) (_type (_external ~tri0 (vl verilog_logic tri0))) (_type (_external ~trireg (vl verilog_logic trireg))) (_type (_external ~supply0 (vl verilog_logic supply0))) (_type (_external ~supply1 (vl verilog_logic supply1))) (_type (_external ~real (vl verilog_logic real))) (_type (_external ~realtime (vl verilog_logic realtime))) (_type (_external ~tri (vl verilog_logic tri))) (_type (_external ~triand (vl verilog_logic triand))) (_type (_external ~trior (vl verilog_logic trior))) (_type (_external ~bit (vl verilog_logic bit))) (_type (_external ~extstd.standard.integer (std standard integer))) (_type (_external ~extstd.standard.bit (std standard bit))) (_process (#ASSIGN#206_0 (_architecture 0 0 206 (_process (_alias ((NET1005)(CameraStatus)))(_simple) (_target(42)) (_sensitivity(3)) ))) (#ASSIGN#207_1 (_architecture 1 0 207 (_process (_alias ((NET951)(AM0status)))(_simple) (_target(47)) (_sensitivity(0)) ))) (#ASSIGN#208_2 (_architecture 2 0 208 (_process (_alias ((NET960)(AM1status)))(_simple) (_target(48)) (_sensitivity(1)) ))) (#ASSIGN#209_3 (_architecture 3 0 209 (_process (_alias ((NET969)(AM2status)))(_simple) (_target(49)) (_sensitivity(2)) ))) (#ASSIGN#210_4 (_architecture 4 0 210 (_process (_alias ((NET978)(SystemStatus)))(_simple) (_target(50)) (_sensitivity(11)) ))) (#ASSIGN#211_5 (_architecture 5 0 211 (_process (_alias ((NET987)(ModemStatus)))(_simple) (_target(51)) (_sensitivity(7)) ))) (#ASSIGN#212_6 (_architecture 6 0 212 (_process (_alias ((NET996)(ExternalStatus)))(_simple) (_target(52)) (_sensitivity(4)) ))) (#ASSIGN#215_7 (_architecture 7 0 215 (_process (_alias ((AM0EN)(NET951)))(_simple) (_target(14)) (_sensitivity(47)) ))) (#ASSIGN#216_8 (_architecture 8 0 216 (_process (_alias ((AM1EN)(NET960)))(_simple) (_target(15)) (_sensitivity(48)) ))) (#ASSIGN#217_9 (_architecture 9 0 217 (_process (_alias ((AM2EN)(NET969)))(_simple) (_target(16)) (_sensitivity(49)) ))) (#ASSIGN#218_10 (_architecture 10 0 218 (_process (_alias ((CameraEN)(NET1005)))(_simple) (_target(22)) (_sensitivity(42)) ))) (#ASSIGN#219_11 (_architecture 11 0 219 (_process (_alias ((ExternalEN)(NET996)))(_simple) (_target(24)) (_sensitivity(52)) ))) (#ASSIGN#220_12 (_architecture 12 0 220 (_process (_alias ((ModemEN)(NET987)))(_simple) (_target(32)) (_sensitivity(51)) ))) (#ASSIGN#221_13 (_architecture 13 0 221 (_process (_alias ((SystemEN)(NET978)))(_simple) (_target(33)) (_sensitivity(50)) ))) ) ) (_defparam ) (_scope ) (_instantiation U1 0 140 (_entity . MSP) (_port ((AD) (AD)) ((AS) (NET25)) ((Mclk) (NET33)) ((RD) (NET29)) ((WR) (NET21)) ) (_strength strong0 strong1) ) (_instantiation U2 0 151 (_entity . SleepyPLD) (_port ((AD) (AD)) ((AM0EN) (NET951)) ((AM0Status) (NET951)) ((AM1EN) (NET960)) ((AM1Status) (NET960)) ((AM2EN) (NET969)) ((AM2Status) (NET969)) ((AS) (NET25)) ((CONcon0) (CONcon0)) ((CONcon1) (CONcon1)) ((CONcon2) (CONcon2)) ((CONextr) (CONextr)) ((CONmodem) (CONmodem)) ((CameraEN) (NET1005)) ((CameraStatus) (NET1005)) ((DwarfEN) (DwarfEN)) ((EN) (EN)) ((ExternalEN) (NET996)) ((ExternalStatus) (NET996)) ((INT) (INT)) ((IORD) (IORD)) ((IOWR) (IOWR)) ((IRQ) (IRQ)) ((LOOPcon0) (LOOPcon0)) ((LOOPcon1) (LOOPcon1)) ((LOOPcon2) (LOOPcon2)) ((LOOPextr) (LOOPextr)) ((LOOPmodem) (LOOPmodem)) ((MCLK) (NET33)) ((ModemEN) (NET987)) ((ModemStatus) (NET987)) ((PD) (PD)) ((RD) (NET29)) ((Reset) (Reset)) ((SA) (SA)) ((SCLinc) (SCLinc)) ((SCLreset) (SCLreset)) ((SD) (SD)) ((SystemEN) (NET978)) ((SystemStatus) (NET978)) ((UAD) (UAD)) ((UCS) (UCS)) ((UD) (UD)) ((UINT) (UINT)) ((UIOR) (UIOR)) ((UIOW) (UIOW)) ((WR) (NET21)) ((SCL) (_open)) ) (_strength strong0 strong1) ) (_model . SleepyTB 15 -1) ) V 000050 55 14904 1094657137876 SleepyPLD (_unit VERILOG 6.349C.6.256 (SleepyPLD 0 32 (SleepyPLD 0 32 )) (_version v32) (_time 1094657137641 2004.09.08 08:25:37) (_source (\./compile/sleepypld.v\ VERILOG (\./compile/sleepypld.v\ VERILOG))) (_use (std(standard))(vl(verilog_logic))) (_base (E 2)) (_entity (_time 1094657137641) (_use ) ) (_timescale 1ps 1ps) (_parameters dbg accs ) (_attribute ) (_object (_port (_internal AM0Status ~wire 0 32 (_architecture (_in ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign)) (_port (_internal AM1Status ~wire 0 32 (_architecture (_in ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign)) (_port (_internal AM2Status ~wire 0 32 (_architecture (_in ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign)) (_port (_internal AS ~wire 0 32 (_architecture (_in ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign)) (_port (_internal CPLD_Reset ~wire 0 32 (_architecture (_in ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign)) (_port (_internal CameraStatus ~wire 0 32 (_architecture (_in ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign)) (_port (_internal ExternalStatus ~wire 0 32 (_architecture (_in ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign)) (_port (_internal IORD ~wire 0 32 (_architecture (_in ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign)) (_port (_internal IOWR ~wire 0 32 (_architecture (_in ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign)) (_port (_internal MCLK ~wire 0 32 (_architecture (_in ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign)) (_port (_internal ModemStatus ~wire 0 33 (_architecture (_in ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign)) (_port (_internal RD ~wire 0 33 (_architecture (_in ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign)) (_port (_internal SCLinc ~wire 0 33 (_architecture (_in ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign)) (_port (_internal SCLreset ~wire 0 33 (_architecture (_in ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign)) (_port (_internal SystemStatus ~wire 0 33 (_architecture (_in ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign)) (_port (_internal UINT ~wire 0 33 (_architecture (_in ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign)) (_port (_internal WR ~wire 0 33 (_architecture (_in ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign)) (_type (_internal ~[13:0]wire~ 0 33 (_array ~wire ((_downto (i 13) (i 0)))))) (_port (_internal SA ~[13:0]wire~ 0 33 (_architecture (_in ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign)) (_port (_internal AM0EN ~wire 0 33 (_architecture (_out ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign)) (_port (_internal AM1EN ~wire 0 33 (_architecture (_out ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign)) (_port (_internal AM2EN ~wire 0 34 (_architecture (_out ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign)) (_port (_internal CONcon0 ~wire 0 34 (_architecture (_out ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign)) (_port (_internal CONcon1 ~wire 0 34 (_architecture (_out ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign)) (_port (_internal CONcon2 ~wire 0 34 (_architecture (_out ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign)) (_port (_internal CONextr ~wire 0 34 (_architecture (_out ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign)) (_port (_internal CONmodem ~wire 0 34 (_architecture (_out ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign)) (_port (_internal CameraEN ~wire 0 34 (_architecture (_out ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign)) (_port (_internal DwarfEN ~wire 0 34 (_architecture (_out ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign)) (_port (_internal ExternalEN ~wire 0 34 (_architecture (_out ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign)) (_port (_internal INT ~wire 0 34 (_architecture (_out ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign)) (_port (_internal IRQ ~wire 0 35 (_architecture (_out ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign)) (_port (_internal LOOPcon0 ~wire 0 35 (_architecture (_out ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign)) (_port (_internal LOOPcon1 ~wire 0 35 (_architecture (_out ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign)) (_port (_internal LOOPcon2 ~wire 0 35 (_architecture (_out ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign)) (_port (_internal LOOPextr ~wire 0 35 (_architecture (_out ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign)) (_port (_internal LOOPmodem ~wire 0 35 (_architecture (_out ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign)) (_port (_internal ModemEN ~wire 0 35 (_architecture (_out ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign)) (_port (_internal SystemEN ~wire 0 35 (_architecture (_out ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign)) (_port (_internal UCS ~wire 0 35 (_architecture (_out ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign)) (_port (_internal UIOR ~wire 0 35 (_architecture (_out ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign)) (_port (_internal UIOW ~wire 0 36 (_architecture (_out ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign)) (_type (_internal ~[7:0]wire~ 0 36 (_array ~wire ((_downto (i 7) (i 0)))))) (_port (_internal EN ~[7:0]wire~ 0 36 (_architecture (_out ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign)) (_port (_internal PD ~[7:0]wire~ 0 36 (_architecture (_out ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign)) (_port (_internal UAD ~[7:0]wire~ 0 36 (_architecture (_out ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign)) (_port (_internal SCL ~wire 0 36 (_architecture (_inout ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign)) (_port (_internal AD ~[7:0]wire~ 0 36 (_architecture (_inout ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign)) (_port (_internal SD ~[7:0]wire~ 0 36 (_architecture (_inout ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign)) (_port (_internal UD ~[7:0]wire~ 0 36 (_architecture (_inout ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign)) (_signal (_internal NET1432 ~wire 0 137 (_architecture (_uni ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign)) (_signal (_internal NET1440 ~wire 0 138 (_architecture (_uni ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign)) (_signal (_internal NET1448 ~wire 0 139 (_architecture (_uni ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign)) (_signal (_internal NET1456 ~wire 0 140 (_architecture (_uni ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign)) (_signal (_internal NET1474 ~wire 0 141 (_architecture (_uni ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign)) (_signal (_internal NET1523 ~wire 0 142 (_architecture (_uni ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign)) (_signal (_internal NET1535 ~wire 0 143 (_architecture (_uni ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign)) (_signal (_internal NET1764 ~wire 0 144 (_architecture (_uni ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign)) (_signal (_internal NET2480 ~wire 0 145 (_architecture (_uni ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign)) (_signal (_internal NET2519 ~wire 0 146 (_architecture (_uni ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign)) (_signal (_internal NET2533 ~wire 0 147 (_architecture (_uni ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign)) (_signal (_internal Reset ~wire 0 148 (_architecture (_uni ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign)) (_signal (_internal ADDR ~[7:0]wire~ 0 149 (_architecture (_uni ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign)) (_signal (_internal inDATA ~[7:0]wire~ 0 150 (_architecture (_uni ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign)) (_signal (_internal outDATA ~[7:0]wire~ 0 151 (_architecture (_uni ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign)) (_subprogram ) (_type (_external ~wire (vl verilog_logic wire))) (_type (_external ~reg (vl verilog_logic reg))) (_type (_external ~event (vl verilog_logic event))) (_type (_external ~wand (vl verilog_logic wand))) (_type (_external ~wor (vl verilog_logic wor))) (_type (_external ~tri1 (vl verilog_logic tri1))) (_type (_external ~tri0 (vl verilog_logic tri0))) (_type (_external ~trireg (vl verilog_logic trireg))) (_type (_external ~supply0 (vl verilog_logic supply0))) (_type (_external ~supply1 (vl verilog_logic supply1))) (_type (_external ~real (vl verilog_logic real))) (_type (_external ~realtime (vl verilog_logic realtime))) (_type (_external ~tri (vl verilog_logic tri))) (_type (_external ~triand (vl verilog_logic triand))) (_type (_external ~trior (vl verilog_logic trior))) (_type (_external ~bit (vl verilog_logic bit))) (_type (_external ~extstd.standard.integer (std standard integer))) (_type (_external ~extstd.standard.bit (std standard bit))) (_process (#ASSIGN#313_0 (_architecture 0 0 313 (_process (_alias ((Reset)(CPLD_Reset)))(_simple) (_target(59)) (_sensitivity(4)) ))) ) ) (_defparam ) (_scope ) (_instantiation U1 0 155 (_entity . AddDecode) (_port ((ADDR) (ADDR)) ((AS) (AS)) ((RD) (RD)) ((Rslct0) (NET1535)) ((Rslct1) (NET2533)) ((Rslct6) (NET1523)) ((WR) (WR)) ((Wslct0) (NET2480)) ((Wslct1) (NET2519)) ((Wslct2) (NET1432)) ((Wslct3) (NET1440)) ((Wslct4) (NET1456)) ((Wslct5) (NET1474)) ((Wslct6) (NET1448)) ) (_strength strong0 strong1) ) (_instantiation U2 0 175 (_entity . Interface) (_port ((AD) (AD)) ((ADDR) (ADDR)) ((AS) (AS)) ((MCLK) (MCLK)) ((RD) (RD)) ((Reset) (Reset)) ((WR) (WR)) ((inDATA) (inDATA)) ((outDATA) (outDATA)) ((ASleading) (_open)) ) (_strength strong0 strong1) ) (_instantiation U3 0 190 (_entity . UARTaddr) (_port ((ADDR) (ADDR)) ((IORD) (IORD)) ((IOWR) (IOWR)) ((IRQ) (IRQ)) ((RD) (RD)) ((SA) (SA)) ((SD) (SD)) ((SystemEN) (SystemEN)) ((UARTaddr) (UAD)) ((UARTcs) (UCS)) ((UDATA) (UD)) ((UINT) (UINT)) ((UIOR) (UIOR)) ((UIOW) (UIOW)) ((WR) (WR)) ((inDATA) (inDATA)) ((outDATA) (outDATA)) ) (_strength strong0 strong1) ) (_instantiation U4 0 213 (_entity . GalvRelay) (_port ((CONcon0) (CONcon0)) ((CONcon1) (CONcon1)) ((CONcon2) (CONcon2)) ((CONextr) (CONextr)) ((CONmodem) (CONmodem)) ((LOOPcon0) (LOOPcon0)) ((LOOPcon1) (LOOPcon1)) ((LOOPcon2) (LOOPcon2)) ((LOOPextr) (LOOPextr)) ((LOOPmodem) (LOOPmodem)) ((MCLK) (MCLK)) ((Reset) (Reset)) ((SLPYCON) (NET1432)) ((SLPYLP) (NET1440)) ((inDATA) (inDATA)) ) (_strength strong0 strong1) ) (_instantiation U5 0 234 (_entity . TransceiverControl) (_port ((Enable) (EN)) ((MCLK) (MCLK)) ((PwrDwn) (PD)) ((Reset) (Reset)) ((SLPYEN) (NET1456)) ((SLPYPD) (NET1474)) ((inDATA) (inDATA)) ) (_strength strong0 strong1) ) (_instantiation U6 0 247 (_entity . PwrControl) (_port ((AM0EN) (AM0EN)) ((AM0Status) (AM0Status)) ((AM1EN) (AM1EN)) ((AM1Status) (AM1Status)) ((AM2EN) (AM2EN)) ((AM2Status) (AM2Status)) ((CameraEN) (CameraEN)) ((CameraStatus) (CameraStatus)) ((DwarfEN) (DwarfEN)) ((ExternalEN) (ExternalEN)) ((ExternalStatus) (ExternalStatus)) ((MCLK) (MCLK)) ((ModemEN) (ModemEN)) ((ModemStatus) (ModemStatus)) ((Reset) (Reset)) ((SLPYPWR) (NET1448)) ((SLPYSTATUS) (NET1523)) ((SystemEN) (SystemEN)) ((SystemStatus) (SystemStatus)) ((inDATA) (inDATA)) ((outDATA) (outDATA)) ) (_strength strong0 strong1) ) (_instantiation U7 0 274 (_entity . I2Cfix) (_port ((Inc) (SCLinc)) ((MCLK) (MCLK)) ((SCL) (SCL)) ((SCLint) (NET1764)) ((SCLreset) (SCLreset)) ((SLPYI2CCNTr) (NET1535)) ((outDATA) (outDATA)) ((SCLenable) (_open)) ) (_strength strong0 strong1) ) (_instantiation U8 0 287 (_entity . Interrupt) (_port ((AM0Status) (AM0Status)) ((AM1Status) (AM1Status)) ((AM2Status) (AM2Status)) ((CameraStatus) (CameraStatus)) ((ExternalStatus) (ExternalStatus)) ((INT) (INT)) ((MCLK) (MCLK)) ((ModemStatus) (ModemStatus)) ((Reset) (Reset)) ((SCLint) (NET1764)) ((SLPYIEw) (NET2480)) ((SLPYIFGr) (NET2533)) ((SLPYIFGw) (NET2519)) ((SystemEN) (SystemEN)) ((SystemStatus) (SystemStatus)) ((UARTint) (UINT)) ((inDATA) (inDATA)) ((outDATA) (outDATA)) ) (_strength strong0 strong1) ) (_model . SleepyPLD 2 -1) ) V 000050 55 5869 1094738774808 AddDecode (_unit VERILOG 6.349C.6.256 (AddDecode 0 25 (AddDecode 0 25 )) (_version v32) (_time 1094738774558 2004.09.09 07:06:14) (_source (\./src/adddecode.v\ VERILOG (\./src/adddecode.v\ VERILOG))) (_use (std(standard))(vl(verilog_logic))) (_base (E 11)) (_entity (_time 1094738774558) (_use ) ) (_timescale 1ps 1ps) (_parameters dbg accs ) (_attribute ) (_object (_port (_internal Wslct3 ~wire 0 25 (_architecture (_out ))) (_net ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign)) (_port (_internal Wslct4 ~wire 0 25 (_architecture (_out ))) (_net ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign)) (_port (_internal Wslct5 ~wire 0 25 (_architecture (_out ))) (_net ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign)) (_port (_internal Wslct6 ~wire 0 25 (_architecture (_out ))) (_net ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign)) (_port (_internal AS ~wire 0 25 (_architecture (_in ))) (_net ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign)) (_port (_internal RD ~wire 0 25 (_architecture (_in ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign)) (_port (_internal Rslct0 ~wire 0 25 (_architecture (_out ))) (_net ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign)) (_port (_internal WR ~wire 0 25 (_architecture (_in ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign)) (_port (_internal Rslct1 ~wire 0 25 (_architecture (_out ))) (_net ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign)) (_type (_internal ~[7:0]wire~ 0 25 (_array ~wire ((_downto (i 7) (i 0)))))) (_port (_internal ADDR ~[7:0]wire~ 0 25 (_architecture (_in ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign)) (_port (_internal Wslct0 ~wire 0 25 (_architecture (_out ))) (_net ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign)) (_port (_internal Rslct6 ~wire 0 25 (_architecture (_out ))) (_net ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign)) (_port (_internal Wslct2 ~wire 0 25 (_architecture (_out ))) (_net ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign)) (_type (_internal ~[7:0]reg~ 0 65 (_array ~reg ((_downto (i 7) (i 0)))))) (_signal (_internal Select.Address ~[7:0]reg~ 0 65 (_subprogram Select (_in ))) (_reg ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign)) (_signal (_internal Select.Location ~[7:0]reg~ 0 66 (_subprogram Select (_in ))) (_reg ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign)) (_signal (_internal Select.RD ~reg 0 67 (_subprogram Select (_in ))) (_reg ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign)) (_signal (_internal Select.WR ~reg 0 67 (_subprogram Select (_in ))) (_reg ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign)) (_signal (_internal Select.RorW ~reg 0 68 (_subprogram Select (_in ))) (_reg ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign)) (_signal (_internal Select.Select ~reg 0 0 (_subprogram Select (_out ))) (_reg ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign)) (_subprogram (_internal Select 9 0 64 (_architecture (_function)(_target(18)) (_read(17)(15)(16)(9)(14)) )) ) (_type (_external ~wire (vl verilog_logic wire))) (_type (_external ~reg (vl verilog_logic reg))) (_type (_external ~event (vl verilog_logic event))) (_type (_external ~wand (vl verilog_logic wand))) (_type (_external ~wor (vl verilog_logic wor))) (_type (_external ~tri1 (vl verilog_logic tri1))) (_type (_external ~tri0 (vl verilog_logic tri0))) (_type (_external ~trireg (vl verilog_logic trireg))) (_type (_external ~supply0 (vl verilog_logic supply0))) (_type (_external ~supply1 (vl verilog_logic supply1))) (_type (_external ~real (vl verilog_logic real))) (_type (_external ~realtime (vl verilog_logic realtime))) (_type (_external ~tri (vl verilog_logic tri))) (_type (_external ~triand (vl verilog_logic triand))) (_type (_external ~trior (vl verilog_logic trior))) (_type (_external ~bit (vl verilog_logic bit))) (_type (_external ~extstd.standard.integer (std standard integer))) (_type (_external ~extstd.standard.bit (std standard bit))) (_process (#ASSIGN#76_0 (_architecture 0 0 76 (_process (_simple) (_target(10)) (_sensitivity(9)(5)(7)) (_call(0)) ))) (#ASSIGN#80_1 (_architecture 1 0 80 (_process (_simple) (_target(12)) (_sensitivity(9)(5)(7)) (_call(0)) ))) (#ASSIGN#82_2 (_architecture 2 0 82 (_process (_simple) (_target(0)) (_sensitivity(9)(5)(7)) (_call(0)) ))) (#ASSIGN#84_3 (_architecture 3 0 84 (_process (_simple) (_target(1)) (_sensitivity(9)(5)(7)) (_call(0)) ))) (#ASSIGN#86_4 (_architecture 4 0 86 (_process (_simple) (_target(2)) (_sensitivity(9)(5)(7)) (_call(0)) ))) (#ASSIGN#88_5 (_architecture 5 0 88 (_process (_simple) (_target(3)) (_sensitivity(9)(5)(7)) (_call(0)) ))) (#ASSIGN#91_6 (_architecture 6 0 91 (_process (_simple) (_target(6)) (_sensitivity(9)(5)(7)) (_call(0)) ))) (#ASSIGN#93_7 (_architecture 7 0 93 (_process (_simple) (_target(8)) (_sensitivity(9)(5)(7)) (_call(0)) ))) (#ASSIGN#95_8 (_architecture 8 0 95 (_process (_simple) (_target(11)) (_sensitivity(9)(5)(7)) (_call(0)) ))) (#INTERNAL#0_10 (_internal 10 0 0 (_process (_virtual)))) ) ) (_defparam ) (_scope (_unit Select function 0 64 ) ) (_model . AddDecode 11 -1) ) V 000050 55 5012 1094738811011 Interrupt (_unit VERILOG 6.349C.6.256 (Interrupt 0 25 (Interrupt 0 25 )) (_version v32) (_time 1094738810933 2004.09.09 07:06:50) (_source (\./src/interrupt.v\ VERILOG (\./src/interrupt.v\ VERILOG))) (_use (std(standard))(vl(verilog_logic))) (_base (E 5)) (_entity (_time 1094738810933) (_use ) ) (_timescale 1ps 1ps) (_parameters dbg accs ) (_attribute nb_assign ) (_object (_port (_internal AM0Status ~wire 0 25 (_architecture (_in ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign)) (_port (_internal AM1Status ~wire 0 25 (_architecture (_in ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign)) (_port (_internal Reset ~wire 0 25 (_architecture (_in ))) (_net ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign)) (_port (_internal AM2Status ~wire 0 25 (_architecture (_in ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign)) (_port (_internal ExternalStatus ~wire 0 25 (_architecture (_in ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign)) (_port (_internal MCLK ~wire 0 25 (_architecture (_in ))) (_net ) (_nonbaction) (_noforceassign)) (_port (_internal UARTint ~wire 0 25 (_architecture (_in ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign)) (_port (_internal SystemStatus ~wire 0 25 (_architecture (_in ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign)) (_port (_internal INT ~wire 0 25 (_architecture (_out ))) (_net ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign)) (_port (_internal SCLint ~wire 0 25 (_architecture (_in ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign)) (_port (_internal SLPYIEw ~wire 0 25 (_architecture (_in ))) (_net ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign)) (_port (_internal CameraStatus ~wire 0 25 (_architecture (_in ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign)) (_port (_internal SLPYIFGr ~wire 0 25 (_architecture (_in ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign)) (_type (_internal ~[7:0]wire~ 0 25 (_array ~wire ((_downto (i 7) (i 0)))))) (_port (_internal inDATA ~[7:0]wire~ 0 25 (_architecture (_in ))) (_net ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign)) (_port (_internal outDATA ~[7:0]wire~ 0 25 (_architecture (_out ))) (_net ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign)) (_port (_internal ModemStatus ~wire 0 25 (_architecture (_in ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign)) (_port (_internal SystemEN ~wire 0 25 (_architecture (_in ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign)) (_signal (_internal PWRFlgs ~wire 0 67 (_architecture (_uni ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign)) (_type (_internal ~[7:0]reg~ 0 69 (_array ~reg ((_downto (i 7) (i 0)))))) (_signal (_internal SLPYIE ~[7:0]reg~ 0 69 (_architecture (_uni ))) (_reg ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign)) (_subprogram ) (_type (_external ~wire (vl verilog_logic wire))) (_type (_external ~reg (vl verilog_logic reg))) (_type (_external ~event (vl verilog_logic event))) (_type (_external ~wand (vl verilog_logic wand))) (_type (_external ~wor (vl verilog_logic wor))) (_type (_external ~tri1 (vl verilog_logic tri1))) (_type (_external ~tri0 (vl verilog_logic tri0))) (_type (_external ~trireg (vl verilog_logic trireg))) (_type (_external ~supply0 (vl verilog_logic supply0))) (_type (_external ~supply1 (vl verilog_logic supply1))) (_type (_external ~real (vl verilog_logic real))) (_type (_external ~realtime (vl verilog_logic realtime))) (_type (_external ~tri (vl verilog_logic tri))) (_type (_external ~triand (vl verilog_logic triand))) (_type (_external ~trior (vl verilog_logic trior))) (_type (_external ~bit (vl verilog_logic bit))) (_type (_external ~extstd.standard.integer (std standard integer))) (_type (_external ~extstd.standard.bit (std standard bit))) (_process (#ASSIGN#71_0 (_architecture 0 0 71 (_process (_alias ((PWRFlgs)(SystemStatus)(CameraStatus)(ExternalStatus)(AM2Status)(AM1Status)(AM0Status)(ModemStatus)))(_simple) (_target(17)) (_sensitivity(7)(11)(4)(3)(1)(0)(15)) ))) (#ASSIGN#72_1 (_architecture 1 0 72 (_process (_simple) (_target(14)) (_sensitivity(12)(9)(17)(6)) ))) (#ASSIGN#76_2 (_architecture 2 0 76 (_process (_alias ((INT)(SLPYIE(7))(SCLint)(SLPYIE(1))(PWRFlgs)(SLPYIE(0))(UARTint)(SystemEN)))(_simple) (_target(8)) (_sensitivity(18(7))(9)(18(1))(17)(18(0))(6)(16)) ))) (#ALWAYS#78_3 (_architecture 3 0 78 (_process (_target(18)) (_read(5)(2)(10)(13)) ))) ) ) (_defparam ) (_model . Interrupt 5 -1) ) V 000050 55 14696 1094738827887 SleepyPLD (_unit VERILOG 6.349C.6.256 (SleepyPLD 0 32 (SleepyPLD 0 32 )) (_version v32) (_time 1094738827839 2004.09.09 07:07:07) (_source (\./compile/sleepypld.v\ VERILOG (\./compile/sleepypld.v\ VERILOG))) (_use (std(standard))(vl(verilog_logic))) (_base (E 2)) (_entity (_time 1094738827839) (_use ) ) (_timescale 1ps 1ps) (_parameters dbg accs ) (_attribute ) (_object (_port (_internal AM0Status ~wire 0 32 (_architecture (_in ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign)) (_port (_internal AM1Status ~wire 0 32 (_architecture (_in ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign)) (_port (_internal AM2Status ~wire 0 32 (_architecture (_in ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign)) (_port (_internal AS ~wire 0 32 (_architecture (_in ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign)) (_port (_internal CPLD_Reset ~wire 0 32 (_architecture (_in ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign)) (_port (_internal CameraStatus ~wire 0 32 (_architecture (_in ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign)) (_port (_internal ExternalStatus ~wire 0 32 (_architecture (_in ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign)) (_port (_internal IORD ~wire 0 32 (_architecture (_in ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign)) (_port (_internal IOWR ~wire 0 32 (_architecture (_in ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign)) (_port (_internal MCLK ~wire 0 32 (_architecture (_in ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign)) (_port (_internal ModemStatus ~wire 0 33 (_architecture (_in ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign)) (_port (_internal RD ~wire 0 33 (_architecture (_in ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign)) (_port (_internal SCLinc ~wire 0 33 (_architecture (_in ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign)) (_port (_internal SCLreset ~wire 0 33 (_architecture (_in ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign)) (_port (_internal SystemStatus ~wire 0 33 (_architecture (_in ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign)) (_port (_internal UINT ~wire 0 33 (_architecture (_in ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign)) (_port (_internal WR ~wire 0 33 (_architecture (_in ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign)) (_type (_internal ~[13:0]wire~ 0 33 (_array ~wire ((_downto (i 13) (i 0)))))) (_port (_internal SA ~[13:0]wire~ 0 33 (_architecture (_in ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign)) (_port (_internal AM0EN ~wire 0 33 (_architecture (_out ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign)) (_port (_internal AM1EN ~wire 0 33 (_architecture (_out ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign)) (_port (_internal AM2EN ~wire 0 34 (_architecture (_out ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign)) (_port (_internal CONcon0 ~wire 0 34 (_architecture (_out ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign)) (_port (_internal CONcon1 ~wire 0 34 (_architecture (_out ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign)) (_port (_internal CONcon2 ~wire 0 34 (_architecture (_out ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign)) (_port (_internal CONextr ~wire 0 34 (_architecture (_out ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign)) (_port (_internal CONmodem ~wire 0 34 (_architecture (_out ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign)) (_port (_internal CameraEN ~wire 0 34 (_architecture (_out ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign)) (_port (_internal DwarfEN ~wire 0 34 (_architecture (_out ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign)) (_port (_internal ExternalEN ~wire 0 34 (_architecture (_out ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign)) (_port (_internal INT ~wire 0 34 (_architecture (_out ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign)) (_port (_internal IRQ ~wire 0 35 (_architecture (_out ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign)) (_port (_internal LOOPcon0 ~wire 0 35 (_architecture (_out ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign)) (_port (_internal LOOPcon1 ~wire 0 35 (_architecture (_out ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign)) (_port (_internal LOOPcon2 ~wire 0 35 (_architecture (_out ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign)) (_port (_internal LOOPextr ~wire 0 35 (_architecture (_out ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign)) (_port (_internal LOOPmodem ~wire 0 35 (_architecture (_out ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign)) (_port (_internal ModemEN ~wire 0 35 (_architecture (_out ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign)) (_port (_internal SystemEN ~wire 0 35 (_architecture (_out ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign)) (_port (_internal UCS ~wire 0 35 (_architecture (_out ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign)) (_port (_internal UIOR ~wire 0 35 (_architecture (_out ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign)) (_port (_internal UIOW ~wire 0 36 (_architecture (_out ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign)) (_type (_internal ~[7:0]wire~ 0 36 (_array ~wire ((_downto (i 7) (i 0)))))) (_port (_internal EN ~[7:0]wire~ 0 36 (_architecture (_out ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign)) (_port (_internal PD ~[7:0]wire~ 0 36 (_architecture (_out ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign)) (_port (_internal UAD ~[7:0]wire~ 0 36 (_architecture (_out ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign)) (_port (_internal SCL ~wire 0 36 (_architecture (_inout ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign)) (_port (_internal AD ~[7:0]wire~ 0 36 (_architecture (_inout ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign)) (_port (_internal SD ~[7:0]wire~ 0 36 (_architecture (_inout ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign)) (_port (_internal UD ~[7:0]wire~ 0 36 (_architecture (_inout ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign)) (_signal (_internal NET1432 ~wire 0 137 (_architecture (_uni ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign)) (_signal (_internal NET1440 ~wire 0 138 (_architecture (_uni ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign)) (_signal (_internal NET1448 ~wire 0 139 (_architecture (_uni ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign)) (_signal (_internal NET1456 ~wire 0 140 (_architecture (_uni ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign)) (_signal (_internal NET1474 ~wire 0 141 (_architecture (_uni ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign)) (_signal (_internal NET1523 ~wire 0 142 (_architecture (_uni ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign)) (_signal (_internal NET1535 ~wire 0 143 (_architecture (_uni ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign)) (_signal (_internal NET1764 ~wire 0 144 (_architecture (_uni ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign)) (_signal (_internal NET2480 ~wire 0 145 (_architecture (_uni ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign)) (_signal (_internal NET2533 ~wire 0 146 (_architecture (_uni ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign)) (_signal (_internal Reset ~wire 0 147 (_architecture (_uni ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign)) (_signal (_internal ADDR ~[7:0]wire~ 0 148 (_architecture (_uni ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign)) (_signal (_internal inDATA ~[7:0]wire~ 0 149 (_architecture (_uni ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign)) (_signal (_internal outDATA ~[7:0]wire~ 0 150 (_architecture (_uni ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_onlyingate) (_noforceassign)) (_subprogram ) (_type (_external ~wire (vl verilog_logic wire))) (_type (_external ~reg (vl verilog_logic reg))) (_type (_external ~event (vl verilog_logic event))) (_type (_external ~wand (vl verilog_logic wand))) (_type (_external ~wor (vl verilog_logic wor))) (_type (_external ~tri1 (vl verilog_logic tri1))) (_type (_external ~tri0 (vl verilog_logic tri0))) (_type (_external ~trireg (vl verilog_logic trireg))) (_type (_external ~supply0 (vl verilog_logic supply0))) (_type (_external ~supply1 (vl verilog_logic supply1))) (_type (_external ~real (vl verilog_logic real))) (_type (_external ~realtime (vl verilog_logic realtime))) (_type (_external ~tri (vl verilog_logic tri))) (_type (_external ~triand (vl verilog_logic triand))) (_type (_external ~trior (vl verilog_logic trior))) (_type (_external ~bit (vl verilog_logic bit))) (_type (_external ~extstd.standard.integer (std standard integer))) (_type (_external ~extstd.standard.bit (std standard bit))) (_process (#ASSIGN#310_0 (_architecture 0 0 310 (_process (_alias ((Reset)(CPLD_Reset)))(_simple) (_target(58)) (_sensitivity(4)) ))) ) ) (_defparam ) (_scope ) (_instantiation U1 0 154 (_entity . AddDecode) (_port ((ADDR) (ADDR)) ((AS) (AS)) ((RD) (RD)) ((Rslct0) (NET1535)) ((Rslct1) (NET2533)) ((Rslct6) (NET1523)) ((WR) (WR)) ((Wslct0) (NET2480)) ((Wslct2) (NET1432)) ((Wslct3) (NET1440)) ((Wslct4) (NET1456)) ((Wslct5) (NET1474)) ((Wslct6) (NET1448)) ) (_strength strong0 strong1) ) (_instantiation U2 0 173 (_entity . Interface) (_port ((AD) (AD)) ((ADDR) (ADDR)) ((AS) (AS)) ((MCLK) (MCLK)) ((RD) (RD)) ((Reset) (Reset)) ((WR) (WR)) ((inDATA) (inDATA)) ((outDATA) (outDATA)) ((ASleading) (_open)) ) (_strength strong0 strong1) ) (_instantiation U3 0 188 (_entity . UARTaddr) (_port ((ADDR) (ADDR)) ((IORD) (IORD)) ((IOWR) (IOWR)) ((IRQ) (IRQ)) ((RD) (RD)) ((SA) (SA)) ((SD) (SD)) ((SystemEN) (SystemEN)) ((UARTaddr) (UAD)) ((UARTcs) (UCS)) ((UDATA) (UD)) ((UINT) (UINT)) ((UIOR) (UIOR)) ((UIOW) (UIOW)) ((WR) (WR)) ((inDATA) (inDATA)) ((outDATA) (outDATA)) ) (_strength strong0 strong1) ) (_instantiation U4 0 211 (_entity . GalvRelay) (_port ((CONcon0) (CONcon0)) ((CONcon1) (CONcon1)) ((CONcon2) (CONcon2)) ((CONextr) (CONextr)) ((CONmodem) (CONmodem)) ((LOOPcon0) (LOOPcon0)) ((LOOPcon1) (LOOPcon1)) ((LOOPcon2) (LOOPcon2)) ((LOOPextr) (LOOPextr)) ((LOOPmodem) (LOOPmodem)) ((MCLK) (MCLK)) ((Reset) (Reset)) ((SLPYCON) (NET1432)) ((SLPYLP) (NET1440)) ((inDATA) (inDATA)) ) (_strength strong0 strong1) ) (_instantiation U5 0 232 (_entity . TransceiverControl) (_port ((Enable) (EN)) ((MCLK) (MCLK)) ((PwrDwn) (PD)) ((Reset) (Reset)) ((SLPYEN) (NET1456)) ((SLPYPD) (NET1474)) ((inDATA) (inDATA)) ) (_strength strong0 strong1) ) (_instantiation U6 0 245 (_entity . PwrControl) (_port ((AM0EN) (AM0EN)) ((AM0Status) (AM0Status)) ((AM1EN) (AM1EN)) ((AM1Status) (AM1Status)) ((AM2EN) (AM2EN)) ((AM2Status) (AM2Status)) ((CameraEN) (CameraEN)) ((CameraStatus) (CameraStatus)) ((DwarfEN) (DwarfEN)) ((ExternalEN) (ExternalEN)) ((ExternalStatus) (ExternalStatus)) ((MCLK) (MCLK)) ((ModemEN) (ModemEN)) ((ModemStatus) (ModemStatus)) ((Reset) (Reset)) ((SLPYPWR) (NET1448)) ((SLPYSTATUS) (NET1523)) ((SystemEN) (SystemEN)) ((SystemStatus) (SystemStatus)) ((inDATA) (inDATA)) ((outDATA) (outDATA)) ) (_strength strong0 strong1) ) (_instantiation U7 0 272 (_entity . I2Cfix) (_port ((Inc) (SCLinc)) ((MCLK) (MCLK)) ((SCL) (SCL)) ((SCLint) (NET1764)) ((SCLreset) (SCLreset)) ((SLPYI2CCNTr) (NET1535)) ((outDATA) (outDATA)) ((SCLenable) (_open)) ) (_strength strong0 strong1) ) (_instantiation U8 0 285 (_entity . Interrupt) (_port ((AM0Status) (AM0Status)) ((AM1Status) (AM1Status)) ((AM2Status) (AM2Status)) ((CameraStatus) (CameraStatus)) ((ExternalStatus) (ExternalStatus)) ((INT) (INT)) ((MCLK) (MCLK)) ((ModemStatus) (ModemStatus)) ((Reset) (Reset)) ((SCLint) (NET1764)) ((SLPYIEw) (NET2480)) ((SLPYIFGr) (NET2533)) ((SystemEN) (SystemEN)) ((SystemStatus) (SystemStatus)) ((UARTint) (UINT)) ((inDATA) (inDATA)) ((outDATA) (outDATA)) ) (_strength strong0 strong1) ) (_model . SleepyPLD 2 -1) ) V 000049 55 5620 1094829523216 UARTaddr (_unit VERILOG 6.349C.6.256 (UARTaddr 0 25 (UARTaddr 0 25 )) (_version v32) (_time 1094829523137 2004.09.10 08:18:43) (_source (\./src/uartaddr.v\ VERILOG (\./src/uartaddr.v\ VERILOG))) (_use (std(standard))(vl(verilog_logic))) (_base (E 10)) (_entity (_time 1094829523137) (_use ) ) (_timescale 1ps 1ps) (_parameters dbg accs ) (_attribute ) (_object (_type (_internal ~vector~0 0 27 (_array ~bit ((_uto (i 0) (i 0)))))) (_generic (_internal HIGHUART ~vector~0 0 27 \8'b0\ (_entity -1 (_constant \8'b0\)))) (_port (_internal UINT ~wire 0 25 (_architecture (_in ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign)) (_port (_internal IOWR ~wire 0 25 (_architecture (_in ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign)) (_port (_internal UIOW ~wire 0 25 (_architecture (_out ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign)) (_port (_internal WR ~wire 0 25 (_architecture (_in ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign)) (_port (_internal IRQ ~wire 0 25 (_architecture (_out ))) (_net ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign)) (_port (_internal IORD ~wire 0 25 (_architecture (_in ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign)) (_type (_internal ~[7:0]wire~ 0 25 (_array ~wire ((_downto (i 7) (i 0)))))) (_port (_internal UDATA ~[7:0]wire~ 0 25 (_architecture (_inout ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign)) (_port (_internal inDATA ~[7:0]wire~ 0 25 (_architecture (_in ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign)) (_port (_internal UARTcs ~wire 0 25 (_architecture (_out ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign)) (_port (_internal outDATA ~[7:0]wire~ 0 25 (_architecture (_out ))) (_net ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign)) (_type (_internal ~[15:0]wire~ 0 25 (_array ~wire ((_downto (i 15) (i 0)))))) (_port (_internal SA ~[15:0]wire~ 0 25 (_architecture (_in ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign)) (_port (_internal AEN ~wire 0 25 (_architecture (_in ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign)) (_port (_internal RD ~wire 0 25 (_architecture (_in ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign)) (_port (_internal SD ~[7:0]wire~ 0 25 (_architecture (_inout ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign)) (_port (_internal UARTaddr ~[7:0]wire~ 0 25 (_architecture (_out ))) (_net ) (_simple) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign)) (_port (_internal SystemEN ~wire 0 25 (_architecture (_in ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign)) (_port (_internal ADDR ~[7:0]wire~ 0 25 (_architecture (_in ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign)) (_port (_internal UIOR ~wire 0 25 (_architecture (_out ))) (_net ) (_nonbaction) (_noedge) (_nodynamic) (_nodynauto) (_noforceassign)) (_subprogram ) (_type (_external ~wire (vl verilog_logic wire))) (_type (_external ~reg (vl verilog_logic reg))) (_type (_external ~event (vl verilog_logic event))) (_type (_external ~wand (vl verilog_logic wand))) (_type (_external ~wor (vl verilog_logic wor))) (_type (_external ~tri1 (vl verilog_logic tri1))) (_type (_external ~tri0 (vl verilog_logic tri0))) (_type (_external ~trireg (vl verilog_logic trireg))) (_type (_external ~supply0 (vl verilog_logic supply0))) (_type (_external ~supply1 (vl verilog_logic supply1))) (_type (_external ~real (vl verilog_logic real))) (_type (_external ~realtime (vl verilog_logic realtime))) (_type (_external ~tri (vl verilog_logic tri))) (_type (_external ~triand (vl verilog_logic triand))) (_type (_external ~trior (vl verilog_logic trior))) (_type (_external ~bit (vl verilog_logic bit))) (_type (_external ~extstd.standard.integer (std standard integer))) (_type (_external ~extstd.standard.bit (std standard bit))) (_process (#ASSIGN#74_0 (_architecture 0 0 74 (_process (_simple) (_target(14(d_7_4))) (_sensitivity(15)(10(d_15_8))(10(d_7_4))(16(d_7_4))) ))) (#ASSIGN#75_1 (_architecture 1 0 75 (_process (_simple) (_target(14(d_3_0))) (_sensitivity(15)(10(d_15_8))(10(d_3_0))(16(d_3_0))) ))) (#ASSIGN#78_2 (_architecture 2 0 78 (_process (_simple) (_target(8)) (_sensitivity(15)(10(d_15_8))(11)(16(d_7_4))) ))) (#ASSIGN#81_3 (_architecture 3 0 81 (_process (_alias ((UIOR)(SystemEN)(UARTcs)(IORD)(RD)(UARTcs)))(_simple) (_target(17)) (_sensitivity(15)(8)(5)(12)) ))) (#ASSIGN#82_4 (_architecture 4 0 82 (_process (_alias ((UIOW)(SystemEN)(UARTcs)(IOWR)(WR)(UARTcs)))(_simple) (_target(2)) (_sensitivity(15)(8)(1)(3)) ))) (#ASSIGN#86_5 (_architecture 5 0 86 (_process (_simple) (_target(6)) (_sensitivity(8)(2)(15)(13)(7)(17)) ))) (#ASSIGN#87_6 (_architecture 6 0 87 (_process (_simple) (_target(9)) (_sensitivity(8)(17)(15)(6)) ))) (#ASSIGN#88_7 (_architecture 7 0 88 (_process (_simple) (_target(13)) (_sensitivity(8)(17)(15)(6)) ))) (#ASSIGN#90_8 (_architecture 8 0 90 (_process (_simple) (_target(4)) (_sensitivity(15)(0)) ))) (#INTERNAL#0_9 (_internal 9 0 0 (_process (_virtual)))) ) ) (_defparam ) (_model . UARTaddr 10 -1) )