//--------------------------------------------------------------------------------------------------
//
// Title       : PwrControl
// Design      : SleepyPLD
// Author      : SJensen
// Company     : MBARI
//
//-------------------------------------------------------------------------------------------------
//
// File        : c:\Projects\genosensor\2g\CPLDs\Sleepy\SleepyPLD\src\PwrControl.v
// Generated   : Mon Aug 30 07:14:19 2004
// From        : interface description file
// By          : Itf2Vhdl ver. 1.20
//
//-------------------------------------------------------------------------------------------------
//
// Description : 
//
//-------------------------------------------------------------------------------------------------
`timescale 1ps / 1ps

//{{ Section below this comment is automatically maintained
//   and may be overwritten
//{module {PwrControl}}
module PwrControl ( SLPYPWR ,AM0Status ,AM1Status ,Reset ,AM2Status ,ModemEN ,DwarfEN ,ExternalStatus ,MCLK ,SystemStatus ,SLPYSTATUS ,CameraStatus ,inDATA ,AM0EN ,outDATA ,AM1EN ,AM2EN ,ModemStatus ,ExternalEN ,SystemEN ,CameraEN );

input SLPYPWR ;
wire SLPYPWR ;
input [7:0] inDATA ;
wire [7:0] inDATA ;
input AM0Status ;
wire AM0Status ;
input AM1Status ;
wire AM1Status ;
input Reset ;
wire Reset ;
input AM2Status ;
wire AM2Status ;
input ModemStatus ;
wire ModemStatus ;
input ExternalStatus ;
wire ExternalStatus ;
input MCLK ;
wire MCLK ;
input SystemStatus ;
wire SystemStatus ;
input SLPYSTATUS ;
wire SLPYSTATUS ;
input CameraStatus ;
wire CameraStatus ;

output AM0EN ;
wire AM0EN ;
output [7:0] outDATA ;
wire [7:0] outDATA ;
output AM1EN ;
wire AM1EN ;
output AM2EN ;
wire AM2EN ;
output ModemEN ;
wire ModemEN ;
output ExternalEN ;
wire ExternalEN ;
output DwarfEN ;
wire DwarfEN ;
output SystemEN ;
wire SystemEN ;
output CameraEN ;
wire CameraEN ;

//}} End of automatically maintained section

// -- Enter your statements here -- //
  
reg [7:0]  Enable;

assign {ModemEN,ExternalEN,AM2EN,AM1EN,AM0EN,CameraEN,DwarfEN,SystemEN} = Enable;
assign outDATA[7:0] = (SLPYSTATUS) ? {ModemStatus,ExternalStatus,AM2Status,AM1Status,AM0Status,CameraStatus,1'b1,SystemStatus} : 8'bz;

always @ (negedge MCLK)
	begin
		if (Reset) 
			begin
				Enable <= 8'b0;
			end					
		else
			begin
				if (SLPYPWR) Enable <= inDATA[7:0];
			end
	end
endmodule