//--------------------------------------------------------------------------------------------------
//
// Title       : UARTaddr
// Design      : SleepyPLD
// Author      : SJensen
// Company     : MBARI
//
//-------------------------------------------------------------------------------------------------
//
// File        : c:\Projects\genosensor\2g\CPLDs\Sleepy\SleepyPLD\src\UARTaddr.v
// Generated   : Fri Aug 27 10:59:11 2004
// From        : interface description file
// By          : Itf2Vhdl ver. 1.20
//
//-------------------------------------------------------------------------------------------------
//
// Description : 
//
//-------------------------------------------------------------------------------------------------
`timescale 1ps / 1ps

//{{ Section below this comment is automatically maintained
//   and may be overwritten
//{module {UARTaddr}}
module UARTaddr ( UINT ,IOWR ,UIOW ,WR ,IRQ ,IORD ,UDATA ,inDATA ,UARTcs ,outDATA ,SA ,AEN ,RD ,SD ,UARTaddr ,SystemEN ,ADDR ,UIOR );

parameter HIGHUART =  8'b0 ;

input UINT ;
wire UINT ;
input SystemEN ;
wire SystemEN ;
input IOWR ;
wire IOWR ;
input [7:0] inDATA ;
wire [7:0] inDATA ;
input WR ;
wire WR ;
input [7:0] ADDR ;
wire [7:0] ADDR ;
input AEN ;
wire AEN ;
input [15:0] SA ;
wire [15:0] SA ;
input IORD ;
wire IORD ;
input RD ;
wire RD ;

output [7:0] outDATA ;
wire [7:0] outDATA ;
output UARTcs ;
wire UARTcs ;
output IRQ ;
wire IRQ ;
output UIOW ;
wire UIOW ;
output UIOR ;
wire UIOR ;
output [7:0] UARTaddr ;
wire [7:0] UARTaddr ;

inout [7:0] SD ;
wire [7:0] SD ;
inout [7:0] UDATA ;
wire [7:0] UDATA ;

//}} End of automatically maintained section

// -- Enter your statements here -- //		 	 

//The purpose of this module is to traslate the sleepy bus address space of the UART down to the address
//space that the UART uses.  This translate the UART to sleepy address 70 - ff.
assign UARTaddr[7:4] = (SystemEN) ?  ((SA[15:8] == HIGHUART) ? SA[7:4] : 4'b0) : ADDR[7:4] + 4'h9;
assign UARTaddr[3:0] = (SystemEN) ?  ((SA[15:8] == HIGHUART) ? SA[3:0] : 4'b0) : ADDR[3:0];

//CS should only begin active while initial the region of the UART
assign UARTcs = (SystemEN) ?  (((SA[15:8] == HIGHUART) & !AEN) ? 1'b0 : 1'b1) : ((ADDR[7:4] >= 4'H7) ? 1'b0 : 1'b1);

//Lock output based on UARTcs.  Pass through the read and write signals
assign UIOR = (SystemEN) ? UARTcs | IORD : RD | UARTcs;
assign UIOW = (SystemEN) ? UARTcs | IOWR : WR | UARTcs;

//define the the UARTs data bus, driven while writing, floating while reading and 0 when nothing
assign UDATA = (!UARTcs & !UIOW) ? ((SystemEN) ? SD : inDATA) : 
			   (!UARTcs & !UIOR) ? 8'bz : 8'b0;
assign outDATA = (!UARTcs & !UIOR & !SystemEN) ? UDATA : 8'bz;
assign SD =  (!UARTcs & !UIOR & SystemEN) ? UDATA : 8'bz;	  

assign IRQ = (SystemEN & !UINT) ? 1'b0 : 1'bz;

endmodule