// Xilinx Verilog produced by program ngc2hdl G.26
// Command: -ofmt verilog -intstyle silent -w SleepyPLD.ngc SleepyPLD.v 
// Input file: SleepyPLD.ngc
// Output file: SleepyPLD.v
// Design name: SleepyPLD
// Xilinx: C:/Xilinx

// The output of ngc2hdl is a simulation model. This file cannot be synthesized,
// or used in any other manner other than simulation. This netlist uses simulation
// primitives which may not represent the true implementation of the device, however
// the netlist is functionally correct. Do not modify this file.

`timescale 1 ns/10 ps

module LPM_XOR2_1 (
  Data_0_, Data_1_, Result
);
  input Data_0_;
  input Data_1_;
  output Result;
  XOR2 Xo_0_1 (
    .I0(Data_0_),
    .I1(Data_1_),
    .O(Result)
  );
endmodule

module NegDetect (
  Line, MCLK, Ndetect
);
  input Line;
  input MCLK;
  output Ndetect;
  wire Line_last;
  wire _n0001;
  wire Ndetectr__n0002;
  wire _n00011;
  FD Ndetectr (
    .D(_n0001),
    .C(Ndetectr__n0002),
    .Q(Ndetect)
  );
  INV _n00011_2 (
    .I(Line),
    .O(_n00011)
  );
  INV Ndetectr__n00021 (
    .I(MCLK),
    .O(Ndetectr__n0002)
  );
  AND2 _n00012 (
    .I0(Line_last),
    .I1(_n00011),
    .O(_n0001)
  );
  FD Line_last_3 (
    .D(Line),
    .C(Ndetectr__n0002),
    .Q(Line_last)
  );
endmodule

module PwrControl (
  AM2Status, AM1Status, Reset, AM0Status, SystemStatus, ExternalStatus, ModemStatus, SLPYSTATUS, CameraStatus, SLPYPWR, MCLK, ModemEN, AM2EN, CameraEN
, ExternalEN, DwarfEN, AM0EN, SystemEN, AM1EN, inDATA, outDATA
);
  input AM2Status;
  input AM1Status;
  input Reset;
  input AM0Status;
  input SystemStatus;
  input ExternalStatus;
  input ModemStatus;
  input SLPYSTATUS;
  input CameraStatus;
  input SLPYPWR;
  input MCLK;
  output ModemEN;
  output AM2EN;
  output CameraEN;
  output ExternalEN;
  output DwarfEN;
  output AM0EN;
  output SystemEN;
  output AM1EN;
  input [7 : 0] inDATA;
  output [7 : 0] outDATA;
  wire N562;
  wire Enable_4__n0000;
  wire Enable_6__n0000;
  wire Enable_7__n0003;
  wire N4920;
  wire Enable_0__n0000;
  wire Enable_5__n0000;
  wire Enable_7__n0002;
  wire Enable_3__n0000;
  wire Enable_7__n0000;
  wire Enable_1__n0000;
  wire Enable_2__n0000;
  wire Enable_0__n00001;
  wire Enable_7__n00021;
  wire Enable_7__n00022;
  wire Enable_7__n00023;
  wire Enable_7__n00001;
  wire Enable_1__n00001;
  wire Enable_4__n00001;
  wire Enable_6__n00001;
  wire Enable_3__n00001;
  wire Enable_2__n00001;
  wire Enable_5__n00001;
  BUFE I1_7 (
    .E(SLPYSTATUS),
    .I(ModemStatus),
    .O(outDATA[7])
  );
  VCC XST_VCC (
    .P(N562)
  );
  AND2 Enable_0__n00002 (
    .I0(inDATA[0]),
    .I1(Enable_0__n00001),
    .O(Enable_0__n0000)
  );
  BUFE I1_0 (
    .E(SLPYSTATUS),
    .I(SystemStatus),
    .O(outDATA[0])
  );
  BUFE I1_1 (
    .E(SLPYSTATUS),
    .I(N562),
    .O(outDATA[1])
  );
  BUFE I1_2 (
    .E(SLPYSTATUS),
    .I(CameraStatus),
    .O(outDATA[2])
  );
  BUFE I1_3 (
    .E(SLPYSTATUS),
    .I(AM0Status),
    .O(outDATA[3])
  );
  BUFE I1_4 (
    .E(SLPYSTATUS),
    .I(AM1Status),
    .O(outDATA[4])
  );
  BUFE I1_5 (
    .E(SLPYSTATUS),
    .I(AM2Status),
    .O(outDATA[5])
  );
  BUFE I1_6 (
    .E(SLPYSTATUS),
    .I(ExternalStatus),
    .O(outDATA[6])
  );
  FDCE Enable_7 (
    .D(Enable_7__n0000),
    .CE(Enable_7__n0002),
    .CLR(N4920),
    .C(Enable_7__n0003),
    .Q(ModemEN)
  );
  FDCE Enable_6 (
    .D(Enable_6__n0000),
    .CE(Enable_7__n0002),
    .CLR(N4920),
    .C(Enable_7__n0003),
    .Q(ExternalEN)
  );
  FDCE Enable_0 (
    .D(Enable_0__n0000),
    .CE(Enable_7__n0002),
    .CLR(N4920),
    .C(Enable_7__n0003),
    .Q(SystemEN)
  );
  FDCE Enable_1 (
    .D(Enable_1__n0000),
    .CE(Enable_7__n0002),
    .CLR(N4920),
    .C(Enable_7__n0003),
    .Q(DwarfEN)
  );
  FDCE Enable_2 (
    .D(Enable_2__n0000),
    .CE(Enable_7__n0002),
    .CLR(N4920),
    .C(Enable_7__n0003),
    .Q(CameraEN)
  );
  FDCE Enable_3 (
    .D(Enable_3__n0000),
    .CE(Enable_7__n0002),
    .CLR(N4920),
    .C(Enable_7__n0003),
    .Q(AM0EN)
  );
  FDCE Enable_4 (
    .D(Enable_4__n0000),
    .CE(Enable_7__n0002),
    .CLR(N4920),
    .C(Enable_7__n0003),
    .Q(AM1EN)
  );
  FDCE Enable_5 (
    .D(Enable_5__n0000),
    .CE(Enable_7__n0002),
    .CLR(N4920),
    .C(Enable_7__n0003),
    .Q(AM2EN)
  );
  INV Enable_7__n00031 (
    .I(MCLK),
    .O(Enable_7__n0003)
  );
  INV Enable_7__n00024 (
    .I(Enable_7__n00023),
    .O(Enable_7__n0002)
  );
  AND2 Enable_7__n00002 (
    .I0(inDATA[7]),
    .I1(Enable_7__n00001),
    .O(Enable_7__n0000)
  );
  GND XST_GND (
    .G(N4920)
  );
  AND2 Enable_1__n00002 (
    .I0(inDATA[1]),
    .I1(Enable_1__n00001),
    .O(Enable_1__n0000)
  );
  AND2 Enable_4__n00002 (
    .I0(inDATA[4]),
    .I1(Enable_4__n00001),
    .O(Enable_4__n0000)
  );
  AND2 Enable_6__n00002 (
    .I0(inDATA[6]),
    .I1(Enable_6__n00001),
    .O(Enable_6__n0000)
  );
  AND2 Enable_3__n00002 (
    .I0(inDATA[3]),
    .I1(Enable_3__n00001),
    .O(Enable_3__n0000)
  );
  AND2 Enable_2__n00002 (
    .I0(inDATA[2]),
    .I1(Enable_2__n00001),
    .O(Enable_2__n0000)
  );
  AND2 Enable_5__n00002 (
    .I0(inDATA[5]),
    .I1(Enable_5__n00001),
    .O(Enable_5__n0000)
  );
  INV Enable_0__n00001_45 (
    .I(Reset),
    .O(Enable_0__n00001)
  );
  INV Enable_7__n00021_46 (
    .I(SLPYPWR),
    .O(Enable_7__n00021)
  );
  INV Enable_7__n00022_47 (
    .I(Reset),
    .O(Enable_7__n00022)
  );
  AND2 Enable_7__n00023_48 (
    .I0(Enable_7__n00021),
    .I1(Enable_7__n00022),
    .O(Enable_7__n00023)
  );
  INV Enable_7__n00001_49 (
    .I(Reset),
    .O(Enable_7__n00001)
  );
  INV Enable_1__n00001_50 (
    .I(Reset),
    .O(Enable_1__n00001)
  );
  INV Enable_4__n00001_51 (
    .I(Reset),
    .O(Enable_4__n00001)
  );
  INV Enable_6__n00001_52 (
    .I(Reset),
    .O(Enable_6__n00001)
  );
  INV Enable_3__n00001_53 (
    .I(Reset),
    .O(Enable_3__n00001)
  );
  INV Enable_2__n00001_54 (
    .I(Reset),
    .O(Enable_2__n00001)
  );
  INV Enable_5__n00001_55 (
    .I(Reset),
    .O(Enable_5__n00001)
  );
endmodule

module TransceiverControl (
  Reset, SLPYEN, SLPYPD, MCLK, inDATA, PwrDwn, Enable
);
  input Reset;
  input SLPYEN;
  input SLPYPD;
  input MCLK;
  input [7 : 0] inDATA;
  output [7 : 0] PwrDwn;
  output [7 : 0] Enable;
  wire en_3__n0000;
  wire en_1__n0000;
  wire en_7__n0003;
  wire en_2__n0000;
  wire en_0__n0000;
  wire en_5__n0000;
  wire en_4__n0000;
  wire en_6__n0000;
  wire en_7__n0002;
  wire pd_0__n0002;
  wire N4989;
  wire en_7__n0000;
  wire en_0__n00001;
  wire pd_0__n00021;
  wire pd_0__n00022;
  wire pd_0__n00023;
  wire en_7__n00021;
  wire en_7__n00022;
  wire en_7__n00023;
  wire en_7__n00001;
  wire en_6__n00001;
  wire en_5__n00001;
  wire en_1__n00001;
  wire en_4__n00001;
  wire en_2__n00001;
  wire en_3__n00001;
  AND2 en_0__n00002 (
    .I0(inDATA[0]),
    .I1(en_0__n00001),
    .O(en_0__n0000)
  );
  INV pd_0__n00024 (
    .I(pd_0__n00023),
    .O(pd_0__n0002)
  );
  FDCE en_7 (
    .D(en_7__n0000),
    .CE(en_7__n0002),
    .CLR(N4989),
    .C(en_7__n0003),
    .Q(Enable[7])
  );
  FDCE en_6 (
    .D(en_6__n0000),
    .CE(en_7__n0002),
    .CLR(N4989),
    .C(en_7__n0003),
    .Q(Enable[6])
  );
  FDCE en_0 (
    .D(en_0__n0000),
    .CE(en_7__n0002),
    .CLR(N4989),
    .C(en_7__n0003),
    .Q(Enable[0])
  );
  FDCE en_1 (
    .D(en_1__n0000),
    .CE(en_7__n0002),
    .CLR(N4989),
    .C(en_7__n0003),
    .Q(Enable[1])
  );
  FDCE en_2 (
    .D(en_2__n0000),
    .CE(en_7__n0002),
    .CLR(N4989),
    .C(en_7__n0003),
    .Q(Enable[2])
  );
  FDCE en_3 (
    .D(en_3__n0000),
    .CE(en_7__n0002),
    .CLR(N4989),
    .C(en_7__n0003),
    .Q(Enable[3])
  );
  FDCE en_4 (
    .D(en_4__n0000),
    .CE(en_7__n0002),
    .CLR(N4989),
    .C(en_7__n0003),
    .Q(Enable[4])
  );
  FDCE en_5 (
    .D(en_5__n0000),
    .CE(en_7__n0002),
    .CLR(N4989),
    .C(en_7__n0003),
    .Q(Enable[5])
  );
  INV en_7__n00031 (
    .I(MCLK),
    .O(en_7__n0003)
  );
  INV en_7__n00024 (
    .I(en_7__n00023),
    .O(en_7__n0002)
  );
  AND2 en_7__n00002 (
    .I0(inDATA[7]),
    .I1(en_7__n00001),
    .O(en_7__n0000)
  );
  GND XST_GND (
    .G(N4989)
  );
  FDCE pd_5 (
    .D(en_5__n0000),
    .CE(pd_0__n0002),
    .CLR(N4989),
    .C(en_7__n0003),
    .Q(PwrDwn[5])
  );
  FDCE pd_3 (
    .D(en_3__n0000),
    .CE(pd_0__n0002),
    .CLR(N4989),
    .C(en_7__n0003),
    .Q(PwrDwn[3])
  );
  AND2 en_6__n00002 (
    .I0(inDATA[6]),
    .I1(en_6__n00001),
    .O(en_6__n0000)
  );
  FDCE pd_7 (
    .D(en_7__n0000),
    .CE(pd_0__n0002),
    .CLR(N4989),
    .C(en_7__n0003),
    .Q(PwrDwn[7])
  );
  FDCE pd_2 (
    .D(en_2__n0000),
    .CE(pd_0__n0002),
    .CLR(N4989),
    .C(en_7__n0003),
    .Q(PwrDwn[2])
  );
  AND2 en_5__n00002 (
    .I0(inDATA[5]),
    .I1(en_5__n00001),
    .O(en_5__n0000)
  );
  AND2 en_1__n00002 (
    .I0(inDATA[1]),
    .I1(en_1__n00001),
    .O(en_1__n0000)
  );
  FDCE pd_1 (
    .D(en_1__n0000),
    .CE(pd_0__n0002),
    .CLR(N4989),
    .C(en_7__n0003),
    .Q(PwrDwn[1])
  );
  AND2 en_4__n00002 (
    .I0(inDATA[4]),
    .I1(en_4__n00001),
    .O(en_4__n0000)
  );
  AND2 en_2__n00002 (
    .I0(inDATA[2]),
    .I1(en_2__n00001),
    .O(en_2__n0000)
  );
  FDCE pd_0 (
    .D(en_0__n0000),
    .CE(pd_0__n0002),
    .CLR(N4989),
    .C(en_7__n0003),
    .Q(PwrDwn[0])
  );
  AND2 en_3__n00002 (
    .I0(inDATA[3]),
    .I1(en_3__n00001),
    .O(en_3__n0000)
  );
  FDCE pd_4 (
    .D(en_4__n0000),
    .CE(pd_0__n0002),
    .CLR(N4989),
    .C(en_7__n0003),
    .Q(PwrDwn[4])
  );
  FDCE pd_6 (
    .D(en_6__n0000),
    .CE(pd_0__n0002),
    .CLR(N4989),
    .C(en_7__n0003),
    .Q(PwrDwn[6])
  );
  INV en_0__n00001_94 (
    .I(Reset),
    .O(en_0__n00001)
  );
  INV pd_0__n00021_95 (
    .I(SLPYPD),
    .O(pd_0__n00021)
  );
  INV pd_0__n00022_96 (
    .I(Reset),
    .O(pd_0__n00022)
  );
  AND2 pd_0__n00023_97 (
    .I0(pd_0__n00021),
    .I1(pd_0__n00022),
    .O(pd_0__n00023)
  );
  INV en_7__n00021_98 (
    .I(SLPYEN),
    .O(en_7__n00021)
  );
  INV en_7__n00022_99 (
    .I(Reset),
    .O(en_7__n00022)
  );
  AND2 en_7__n00023_100 (
    .I0(en_7__n00021),
    .I1(en_7__n00022),
    .O(en_7__n00023)
  );
  INV en_7__n00001_101 (
    .I(Reset),
    .O(en_7__n00001)
  );
  INV en_6__n00001_102 (
    .I(Reset),
    .O(en_6__n00001)
  );
  INV en_5__n00001_103 (
    .I(Reset),
    .O(en_5__n00001)
  );
  INV en_1__n00001_104 (
    .I(Reset),
    .O(en_1__n00001)
  );
  INV en_4__n00001_105 (
    .I(Reset),
    .O(en_4__n00001)
  );
  INV en_2__n00001_106 (
    .I(Reset),
    .O(en_2__n00001)
  );
  INV en_3__n00001_107 (
    .I(Reset),
    .O(en_3__n00001)
  );
endmodule

module GalvRelay (
  Reset, SLPYLP, MCLK, SLPYCON, LOOPcon0, LOOPcon1, LOOPcon2, CONmodem, LOOPmodem, CONextr, CONcon0, CONcon1, CONcon2, LOOPextr, inDATA
);
  input Reset;
  input SLPYLP;
  input MCLK;
  input SLPYCON;
  output LOOPcon0;
  output LOOPcon1;
  output LOOPcon2;
  output CONmodem;
  output LOOPmodem;
  output CONextr;
  output CONcon0;
  output CONcon1;
  output CONcon2;
  output LOOPextr;
  input [7 : 0] inDATA;
  wire loop_4__n0002;
  wire loop_2__n0000;
  wire N4741;
  wire loop_4__n0003;
  wire loop_0__n0000;
  wire loop_3__n0000;
  wire connect_0__n0002;
  wire loop_4__n0000;
  wire loop_1__n0000;
  wire loop_0__n00001;
  wire connect_0__n00021;
  wire connect_0__n00022;
  wire connect_0__n00023;
  wire loop_4__n00021;
  wire loop_4__n00022;
  wire loop_4__n00023;
  wire loop_4__n00001;
  wire loop_1__n00001;
  wire loop_3__n00001;
  wire loop_2__n00001;
  AND2 loop_0__n00002 (
    .I0(inDATA[0]),
    .I1(loop_0__n00001),
    .O(loop_0__n0000)
  );
  INV connect_0__n00024 (
    .I(connect_0__n00023),
    .O(connect_0__n0002)
  );
  FDCE loop_4 (
    .D(loop_4__n0000),
    .CE(loop_4__n0002),
    .CLR(N4741),
    .C(loop_4__n0003),
    .Q(LOOPmodem)
  );
  FDCE loop_3 (
    .D(loop_3__n0000),
    .CE(loop_4__n0002),
    .CLR(N4741),
    .C(loop_4__n0003),
    .Q(LOOPextr)
  );
  FDCE loop_0 (
    .D(loop_0__n0000),
    .CE(loop_4__n0002),
    .CLR(N4741),
    .C(loop_4__n0003),
    .Q(LOOPcon0)
  );
  FDCE loop_1 (
    .D(loop_1__n0000),
    .CE(loop_4__n0002),
    .CLR(N4741),
    .C(loop_4__n0003),
    .Q(LOOPcon1)
  );
  FDCE loop_2 (
    .D(loop_2__n0000),
    .CE(loop_4__n0002),
    .CLR(N4741),
    .C(loop_4__n0003),
    .Q(LOOPcon2)
  );
  INV loop_4__n00031 (
    .I(MCLK),
    .O(loop_4__n0003)
  );
  INV loop_4__n00024 (
    .I(loop_4__n00023),
    .O(loop_4__n0002)
  );
  AND2 loop_4__n00002 (
    .I0(inDATA[7]),
    .I1(loop_4__n00001),
    .O(loop_4__n0000)
  );
  GND XST_GND (
    .G(N4741)
  );
  AND2 loop_1__n00002 (
    .I0(inDATA[1]),
    .I1(loop_1__n00001),
    .O(loop_1__n0000)
  );
  FDCE connect_0 (
    .D(loop_0__n0000),
    .CE(connect_0__n0002),
    .CLR(N4741),
    .C(loop_4__n0003),
    .Q(CONcon0)
  );
  AND2 loop_3__n00002 (
    .I0(inDATA[6]),
    .I1(loop_3__n00001),
    .O(loop_3__n0000)
  );
  FDCE connect_1 (
    .D(loop_1__n0000),
    .CE(connect_0__n0002),
    .CLR(N4741),
    .C(loop_4__n0003),
    .Q(CONcon1)
  );
  FDCE connect_3 (
    .D(loop_3__n0000),
    .CE(connect_0__n0002),
    .CLR(N4741),
    .C(loop_4__n0003),
    .Q(CONextr)
  );
  AND2 loop_2__n00002 (
    .I0(inDATA[2]),
    .I1(loop_2__n00001),
    .O(loop_2__n0000)
  );
  FDCE connect_4 (
    .D(loop_4__n0000),
    .CE(connect_0__n0002),
    .CLR(N4741),
    .C(loop_4__n0003),
    .Q(CONmodem)
  );
  FDCE connect_2 (
    .D(loop_2__n0000),
    .CE(connect_0__n0002),
    .CLR(N4741),
    .C(loop_4__n0003),
    .Q(CONcon2)
  );
  INV loop_0__n00001_134 (
    .I(Reset),
    .O(loop_0__n00001)
  );
  INV connect_0__n00021_135 (
    .I(SLPYCON),
    .O(connect_0__n00021)
  );
  INV connect_0__n00022_136 (
    .I(Reset),
    .O(connect_0__n00022)
  );
  AND2 connect_0__n00023_137 (
    .I0(connect_0__n00021),
    .I1(connect_0__n00022),
    .O(connect_0__n00023)
  );
  INV loop_4__n00021_138 (
    .I(SLPYLP),
    .O(loop_4__n00021)
  );
  INV loop_4__n00022_139 (
    .I(Reset),
    .O(loop_4__n00022)
  );
  AND2 loop_4__n00023_140 (
    .I0(loop_4__n00021),
    .I1(loop_4__n00022),
    .O(loop_4__n00023)
  );
  INV loop_4__n00001_141 (
    .I(Reset),
    .O(loop_4__n00001)
  );
  INV loop_1__n00001_142 (
    .I(Reset),
    .O(loop_1__n00001)
  );
  INV loop_3__n00001_143 (
    .I(Reset),
    .O(loop_3__n00001)
  );
  INV loop_2__n00001_144 (
    .I(Reset),
    .O(loop_2__n00001)
  );
endmodule

module AddDecode (
  AS, RD, WR, Wslct0, Wslct2, Wslct3, Wslct4, Wslct5, Wslct6, Rslct0, Rslct1, Rslct6, ADDR
);
  input AS;
  input RD;
  input WR;
  output Wslct0;
  output Wslct2;
  output Wslct3;
  output Wslct4;
  output Wslct5;
  output Wslct6;
  output Rslct0;
  output Rslct1;
  output Rslct6;
  input [7 : 0] ADDR;
  wire SF7355;
  wire SF7349;
  wire SF7342;
  wire SF7338;
  wire SF73421;
  wire SF73422;
  wire Select_1_Select;
  wire Select_1_Select1;
  wire Select_2_Select;
  wire Select_2_Select1;
  wire Select_2_Select2;
  wire Select_2_Select3;
  wire Select_5_Select;
  wire Select_5_Select1;
  wire Select_5_Select2;
  wire Select_5_Select3;
  wire Select_8_Select;
  wire Select_8_Select1;
  wire Select_8_Select2;
  wire Select_8_Select3;
  wire SF73491;
  wire SF73492;
  wire SF73493;
  wire SF73494;
  wire SF73495;
  wire Select_3_Select;
  wire Select_3_Select1;
  wire Select_7_Select;
  wire Select_7_Select1;
  wire Select_6_Select;
  wire Select_6_Select1;
  wire Select_6_Select2;
  wire Select_6_Select3;
  wire Select_6_Select4;
  wire Select_9_Select;
  wire Select_9_Select1;
  wire SF73551;
  wire SF73552;
  wire SF73381;
  wire SF73382;
  wire SF73383;
  wire SF73384;
  wire SF73385;
  wire SF73386;
  wire Select_4_Select;
  wire Select_4_Select1;
  AND3 SF73423 (
    .I0(SF73421),
    .I1(SF7338),
    .I2(SF73422),
    .O(SF7342)
  );
  AND2 Select_1_Select3 (
    .I0(Select_1_Select),
    .I1(Select_1_Select1),
    .O(Rslct6)
  );
  AND3 Select_2_Select5 (
    .I0(Select_2_Select3),
    .I1(Select_2_Select),
    .I2(Select_2_Select2),
    .O(Rslct1)
  );
  AND3 Select_5_Select5 (
    .I0(Select_5_Select3),
    .I1(Select_5_Select),
    .I2(Select_5_Select2),
    .O(Wslct5)
  );
  AND3 Select_8_Select5 (
    .I0(Select_8_Select3),
    .I1(Select_8_Select),
    .I2(Select_8_Select2),
    .O(Wslct2)
  );
  AND6 SF73496 (
    .I0(SF73491),
    .I1(ADDR[2]),
    .I2(SF73492),
    .I3(SF73494),
    .I4(SF73493),
    .I5(SF73495),
    .O(SF7349)
  );
  AND2 Select_3_Select3 (
    .I0(Select_3_Select),
    .I1(Select_3_Select1),
    .O(Rslct0)
  );
  AND2 Select_7_Select3 (
    .I0(Select_7_Select),
    .I1(Select_7_Select1),
    .O(Wslct3)
  );
  AND3 Select_6_Select6 (
    .I0(Select_6_Select4),
    .I1(Select_6_Select),
    .I2(Select_6_Select3),
    .O(Wslct4)
  );
  AND2 Select_9_Select3 (
    .I0(Select_9_Select),
    .I1(Select_9_Select1),
    .O(Wslct0)
  );
  AND2 SF73553 (
    .I0(SF73551),
    .I1(SF73552),
    .O(SF7355)
  );
  AND6 SF73387 (
    .I0(SF73382),
    .I1(SF73381),
    .I2(SF73383),
    .I3(SF73385),
    .I4(SF73384),
    .I5(SF73386),
    .O(SF7338)
  );
  AND2 Select_4_Select3 (
    .I0(Select_4_Select),
    .I1(Select_4_Select1),
    .O(Wslct6)
  );
  INV SF73421_195 (
    .I(ADDR[1]),
    .O(SF73421)
  );
  INV SF73422_196 (
    .I(ADDR[0]),
    .O(SF73422)
  );
  AND2 Select_1_Select1_197 (
    .I0(WR),
    .I1(SF7355),
    .O(Select_1_Select)
  );
  INV Select_1_Select2 (
    .I(RD),
    .O(Select_1_Select1)
  );
  AND2 Select_2_Select1_198 (
    .I0(WR),
    .I1(ADDR[0]),
    .O(Select_2_Select)
  );
  INV Select_2_Select2_199 (
    .I(RD),
    .O(Select_2_Select1)
  );
  INV Select_2_Select3_200 (
    .I(ADDR[1]),
    .O(Select_2_Select2)
  );
  AND2 Select_2_Select4 (
    .I0(SF7338),
    .I1(Select_2_Select1),
    .O(Select_2_Select3)
  );
  AND2 Select_5_Select1_201 (
    .I0(ADDR[0]),
    .I1(RD),
    .O(Select_5_Select)
  );
  INV Select_5_Select2_202 (
    .I(WR),
    .O(Select_5_Select1)
  );
  INV Select_5_Select3_203 (
    .I(ADDR[1]),
    .O(Select_5_Select2)
  );
  AND2 Select_5_Select4 (
    .I0(SF7349),
    .I1(Select_5_Select1),
    .O(Select_5_Select3)
  );
  AND2 Select_8_Select1_204 (
    .I0(RD),
    .I1(ADDR[1]),
    .O(Select_8_Select)
  );
  INV Select_8_Select2_205 (
    .I(WR),
    .O(Select_8_Select1)
  );
  INV Select_8_Select3_206 (
    .I(ADDR[0]),
    .O(Select_8_Select2)
  );
  AND2 Select_8_Select4 (
    .I0(SF7338),
    .I1(Select_8_Select1),
    .O(Select_8_Select3)
  );
  INV SF73491_207 (
    .I(ADDR[4]),
    .O(SF73491)
  );
  INV SF73492_208 (
    .I(ADDR[6]),
    .O(SF73492)
  );
  INV SF73493_209 (
    .I(ADDR[5]),
    .O(SF73493)
  );
  INV SF73494_210 (
    .I(ADDR[7]),
    .O(SF73494)
  );
  INV SF73495_211 (
    .I(ADDR[3]),
    .O(SF73495)
  );
  AND2 Select_3_Select1_212 (
    .I0(WR),
    .I1(SF7342),
    .O(Select_3_Select)
  );
  INV Select_3_Select2 (
    .I(RD),
    .O(Select_3_Select1)
  );
  AND4 Select_7_Select1_213 (
    .I0(ADDR[0]),
    .I1(RD),
    .I2(ADDR[1]),
    .I3(SF7338),
    .O(Select_7_Select)
  );
  INV Select_7_Select2 (
    .I(WR),
    .O(Select_7_Select1)
  );
  AND2 Select_6_Select1_214 (
    .I0(RD),
    .I1(SF7349),
    .O(Select_6_Select)
  );
  INV Select_6_Select2_215 (
    .I(WR),
    .O(Select_6_Select1)
  );
  INV Select_6_Select3_216 (
    .I(ADDR[0]),
    .O(Select_6_Select2)
  );
  INV Select_6_Select4_217 (
    .I(ADDR[1]),
    .O(Select_6_Select3)
  );
  AND2 Select_6_Select5 (
    .I0(Select_6_Select1),
    .I1(Select_6_Select2),
    .O(Select_6_Select4)
  );
  AND2 Select_9_Select1_218 (
    .I0(SF7342),
    .I1(RD),
    .O(Select_9_Select)
  );
  INV Select_9_Select2 (
    .I(WR),
    .O(Select_9_Select1)
  );
  AND2 SF73551_219 (
    .I0(ADDR[1]),
    .I1(SF7349),
    .O(SF73551)
  );
  INV SF73552_220 (
    .I(ADDR[0]),
    .O(SF73552)
  );
  INV SF73381_221 (
    .I(ADDR[4]),
    .O(SF73381)
  );
  INV SF73382_222 (
    .I(ADDR[6]),
    .O(SF73382)
  );
  INV SF73383_223 (
    .I(ADDR[5]),
    .O(SF73383)
  );
  INV SF73384_224 (
    .I(ADDR[7]),
    .O(SF73384)
  );
  INV SF73385_225 (
    .I(ADDR[3]),
    .O(SF73385)
  );
  INV SF73386_226 (
    .I(ADDR[2]),
    .O(SF73386)
  );
  AND2 Select_4_Select1_227 (
    .I0(SF7355),
    .I1(RD),
    .O(Select_4_Select)
  );
  INV Select_4_Select2 (
    .I(WR),
    .O(Select_4_Select1)
  );
endmodule

module Interrupt (
  SCLint, AM2Status, AM1Status, Reset, AM0Status, SystemStatus, ExternalStatus, ModemStatus, SLPYIEw, CameraStatus, UARTint, SLPYIFGr, SystemEN, MCLK
, INT, inDATA, outDATA
);
  input SCLint;
  input AM2Status;
  input AM1Status;
  input Reset;
  input AM0Status;
  input SystemStatus;
  input ExternalStatus;
  input ModemStatus;
  input SLPYIEw;
  input CameraStatus;
  input UARTint;
  input SLPYIFGr;
  input SystemEN;
  input MCLK;
  output INT;
  input [7 : 0] inDATA;
  output [7 : 0] outDATA;
  wire SLPYIE_0_;
  wire SLPYIE_1_;
  wire _n0001;
  wire _n0002;
  wire _n0003;
  wire SLPYIE_0__n0002;
  wire SLPYIE_7_;
  wire N564;
  wire SLPYIE_0__n0003;
  wire PWRFlgs;
  wire SLPYIE_7__n0000;
  wire SLPYIE_1__n0000;
  wire SLPYIE_0__n0000;
  wire PWRFlgs1;
  wire INT1;
  wire INT2;
  wire INT3;
  wire INT4;
  wire SLPYIE_0__n00021;
  wire SLPYIE_0__n00022;
  wire SLPYIE_0__n00023;
  wire _n00031;
  wire _n00032;
  wire SLPYIE_1__n00001;
  wire SLPYIE_7__n00001;
  wire SLPYIE_0__n00001;
  wire [0 : 0] _n0004;
  INV _n00091 (
    .I(UARTint),
    .O(_n0004[0])
  );
  GND XST_GND (
    .G(N564)
  );
  INV PWRFlgs2 (
    .I(PWRFlgs1),
    .O(PWRFlgs)
  );
  INV INT5 (
    .I(INT4),
    .O(INT)
  );
  BUFE I1_7 (
    .E(SLPYIFGr),
    .I(SCLint),
    .O(outDATA[7])
  );
  INV SLPYIE_0__n00024 (
    .I(SLPYIE_0__n00023),
    .O(SLPYIE_0__n0002)
  );
  AND3 _n00033 (
    .I0(_n00031),
    .I1(SLPYIE_0_),
    .I2(_n00032),
    .O(_n0003)
  );
  AND2 _n00021 (
    .I0(SLPYIE_1_),
    .I1(PWRFlgs),
    .O(_n0002)
  );
  AND2 _n00011 (
    .I0(SLPYIE_7_),
    .I1(SCLint),
    .O(_n0001)
  );
  BUFE I1_0 (
    .E(SLPYIFGr),
    .I(_n0004[0]),
    .O(outDATA[0])
  );
  BUFE I1_1 (
    .E(SLPYIFGr),
    .I(PWRFlgs),
    .O(outDATA[1])
  );
  BUFE I1_2 (
    .E(SLPYIFGr),
    .I(N564),
    .O(outDATA[2])
  );
  BUFE I1_3 (
    .E(SLPYIFGr),
    .I(N564),
    .O(outDATA[3])
  );
  BUFE I1_4 (
    .E(SLPYIFGr),
    .I(N564),
    .O(outDATA[4])
  );
  BUFE I1_5 (
    .E(SLPYIFGr),
    .I(N564),
    .O(outDATA[5])
  );
  BUFE I1_6 (
    .E(SLPYIFGr),
    .I(N564),
    .O(outDATA[6])
  );
  FDCE SLPYIE_7 (
    .D(SLPYIE_7__n0000),
    .CE(SLPYIE_0__n0002),
    .CLR(N564),
    .C(SLPYIE_0__n0003),
    .Q(SLPYIE_7_)
  );
  INV SLPYIE_0__n00031 (
    .I(MCLK),
    .O(SLPYIE_0__n0003)
  );
  FDCE SLPYIE_0 (
    .D(SLPYIE_0__n0000),
    .CE(SLPYIE_0__n0002),
    .CLR(N564),
    .C(SLPYIE_0__n0003),
    .Q(SLPYIE_0_)
  );
  FDCE SLPYIE_1 (
    .D(SLPYIE_1__n0000),
    .CE(SLPYIE_0__n0002),
    .CLR(N564),
    .C(SLPYIE_0__n0003),
    .Q(SLPYIE_1_)
  );
  AND2 SLPYIE_1__n00002 (
    .I0(inDATA[1]),
    .I1(SLPYIE_1__n00001),
    .O(SLPYIE_1__n0000)
  );
  AND2 SLPYIE_7__n00002 (
    .I0(inDATA[7]),
    .I1(SLPYIE_7__n00001),
    .O(SLPYIE_7__n0000)
  );
  AND2 SLPYIE_0__n00002 (
    .I0(inDATA[0]),
    .I1(SLPYIE_0__n00001),
    .O(SLPYIE_0__n0000)
  );
  AND7 PWRFlgs1_257 (
    .I0(CameraStatus),
    .I1(ExternalStatus),
    .I2(AM2Status),
    .I3(AM1Status),
    .I4(AM0Status),
    .I5(ModemStatus),
    .I6(SystemStatus),
    .O(PWRFlgs1)
  );
  INV INT1_258 (
    .I(_n0003),
    .O(INT1)
  );
  INV INT2_259 (
    .I(_n0002),
    .O(INT2)
  );
  INV INT3_260 (
    .I(_n0001),
    .O(INT3)
  );
  AND3 INT4_261 (
    .I0(INT2),
    .I1(INT1),
    .I2(INT3),
    .O(INT4)
  );
  INV SLPYIE_0__n00021_262 (
    .I(SLPYIEw),
    .O(SLPYIE_0__n00021)
  );
  INV SLPYIE_0__n00022_263 (
    .I(Reset),
    .O(SLPYIE_0__n00022)
  );
  AND2 SLPYIE_0__n00023_264 (
    .I0(SLPYIE_0__n00021),
    .I1(SLPYIE_0__n00022),
    .O(SLPYIE_0__n00023)
  );
  INV _n00031_265 (
    .I(UARTint),
    .O(_n00031)
  );
  INV _n00032_266 (
    .I(SystemEN),
    .O(_n00032)
  );
  INV SLPYIE_1__n00001_267 (
    .I(Reset),
    .O(SLPYIE_1__n00001)
  );
  INV SLPYIE_7__n00001_268 (
    .I(Reset),
    .O(SLPYIE_7__n00001)
  );
  INV SLPYIE_0__n00001_269 (
    .I(Reset),
    .O(SLPYIE_0__n00001)
  );
endmodule

module SleepyPLD (
  AS, AM2Status, IOWR, AM1Status, AM0Status, SystemStatus, ExternalStatus, ModemStatus, RD, AEN, WR, CameraStatus, SCLreset, CPLD_Reset, MCLK, SCLinc
, UINT, IORD, SCL, IRQ, UIOW, ModemEN, AM2EN, LOOPcon0, LOOPcon1, LOOPcon2, UCS, CONmodem, CameraEN, LOOPmodem, ExternalEN, CONextr, DwarfEN, AM0EN, 
CONcon0, CONcon1, CONcon2, LOOPextr, SystemEN, AM1EN, INT, UIOR, SA, AD, SD, UD, UAD, EN, PD
);
  input AS;
  input AM2Status;
  input IOWR;
  input AM1Status;
  input AM0Status;
  input SystemStatus;
  input ExternalStatus;
  input ModemStatus;
  input RD;
  input AEN;
  input WR;
  input CameraStatus;
  input SCLreset;
  input CPLD_Reset;
  input MCLK;
  input SCLinc;
  input UINT;
  input IORD;
  inout SCL;
  output IRQ;
  output UIOW;
  output ModemEN;
  output AM2EN;
  output LOOPcon0;
  output LOOPcon1;
  output LOOPcon2;
  output UCS;
  output CONmodem;
  output CameraEN;
  output LOOPmodem;
  output ExternalEN;
  output CONextr;
  output DwarfEN;
  output AM0EN;
  output CONcon0;
  output CONcon1;
  output CONcon2;
  output LOOPextr;
  output SystemEN;
  output AM1EN;
  output INT;
  output UIOR;
  input [15 : 0] SA;
  inout [7 : 0] AD;
  inout [7 : 0] SD;
  inout [7 : 0] UD;
  output [7 : 0] UAD;
  output [7 : 0] EN;
  output [7 : 0] PD;
  wire UIOW_OBUF;
  wire ModemEN_OBUF;
  wire AM2EN_OBUF;
  wire LOOPcon0_OBUF;
  wire LOOPcon1_OBUF;
  wire LOOPcon2_OBUF;
  wire AS_IBUF;
  wire AM2Status_IBUF;
  wire UCS_OBUF;
  wire IOWR_IBUF;
  wire AM1Status_IBUF;
  wire AM0Status_IBUF;
  wire CONmodem_OBUF;
  wire CameraEN_OBUF;
  wire SystemStatus_IBUF;
  wire ExternalStatus_IBUF;
  wire ModemStatus_IBUF;
  wire LOOPmodem_OBUF;
  wire ExternalEN_OBUF;
  wire RD_IBUF;
  wire AEN_IBUF;
  wire CONextr_OBUF;
  wire WR_IBUF;
  wire CameraStatus_IBUF;
  wire DwarfEN_OBUF;
  wire AM0EN_OBUF;
  wire SCLreset_IBUF;
  wire CPLD_Reset_IBUF;
  wire CONcon0_OBUF;
  wire CONcon1_OBUF;
  wire CONcon2_OBUF;
  wire LOOPextr_OBUF;
  wire SystemEN_OBUF;
  wire AM1EN_OBUF;
  wire MCLK_IBUF;
  wire INT_OBUF;
  wire SCLinc_IBUF;
  wire UINT_IBUF;
  wire UIOR_OBUF;
  wire IORD_IBUF;
  wire NET2480;
  wire NET1432;
  wire NET1440;
  wire NET1448;
  wire NET1456;
  wire NET1523;
  wire NET1474;
  wire NET2533;
  wire NET1535;
  wire NET1764;
  wire UAD_7_OBUF;
  wire UAD_6_OBUF;
  wire UAD_5_OBUF;
  wire UAD_4_OBUF;
  wire UAD_3_OBUF;
  wire UAD_2_OBUF;
  wire UAD_1_OBUF;
  wire UAD_0_OBUF;
  wire EN_7_OBUF;
  wire EN_6_OBUF;
  wire EN_5_OBUF;
  wire EN_4_OBUF;
  wire EN_3_OBUF;
  wire EN_2_OBUF;
  wire EN_1_OBUF;
  wire EN_0_OBUF;
  wire PD_7_OBUF;
  wire PD_6_OBUF;
  wire PD_5_OBUF;
  wire PD_4_OBUF;
  wire PD_3_OBUF;
  wire PD_2_OBUF;
  wire PD_1_OBUF;
  wire PD_0_OBUF;
  wire SA_15_IBUF;
  wire SA_14_IBUF;
  wire SA_13_IBUF;
  wire SA_12_IBUF;
  wire SA_11_IBUF;
  wire SA_10_IBUF;
  wire SA_9_IBUF;
  wire SA_8_IBUF;
  wire SA_7_IBUF;
  wire SA_6_IBUF;
  wire SA_5_IBUF;
  wire SA_4_IBUF;
  wire SA_3_IBUF;
  wire SA_2_IBUF;
  wire SA_1_IBUF;
  wire SA_0_IBUF;
  wire U2_ADDR_reg_0__n0002;
  wire U2_ADDR_reg_0__n0000;
  wire U7_U3__n0006;
  wire U2_ADDR_reg_6__n0000;
  wire U2_ADDR_reg_7__n0000;
  wire U2_WRRDedge;
  wire U2__n0000;
  wire U2__n0003;
  wire U2__n0005;
  wire U2__n0006;
  wire U7_U3_Maddsub__n0002__n0018;
  wire U3__n0001;
  wire U7_U3_Maddsub__n0002__n0019;
  wire U2__n0018;
  wire U2_Enable_AD;
  wire U2_ASedge;
  wire U2_AutoInc;
  wire U2_ADDR_in_Range;
  wire SCL_IOBUFE;
  wire UD_4_IOBUFE;
  wire U2_ADDR_reg_3__n0000;
  wire U2_ADDR_reg_5__n0000;
  wire U2_ADDR_reg_0__n0003;
  wire U2_ADDR_reg_2__n0000;
  wire U2_ADDR_reg_1__n0000;
  wire U2_ADDR_reg_4__n0000;
  wire UD_2_IOBUFE;
  wire UD_0_IOBUFE;
  wire UD_3_IOBUFE;
  wire U7_Incdetect;
  wire UD_1_IOBUFE;
  wire U7_U3_Maddsub__n0002__n0020;
  wire U7_SCLdetect;
  wire U7_ResetDetect;
  wire UD_6_IOBUFE;
  wire N5975;
  wire U3__n0028;
  wire U3__n0033;
  wire U7_U3__n0041;
  wire UD_5_IOBUFE;
  wire U7_U3__n0042;
  wire U3__n0002;
  wire U3__n0015;
  wire UD_7_IOBUFE;
  wire U3__n0003;
  wire U7_U3_Maddsub__n0002__n0017;
  wire U2_ADDR_reg_1__n00001;
  wire U2_ADDR_reg_1__n00002;
  wire U2_ADDR_reg_1__n00003;
  wire U2_ADDR_reg_1__n00004;
  wire U2_ADDR_reg_1__n00005;
  wire U2_ADDR_reg_1__n00006;
  wire U2_ADDR_reg_2__n00001;
  wire U2_ADDR_reg_2__n00002;
  wire U2_ADDR_reg_2__n00003;
  wire U2_ADDR_reg_2__n00004;
  wire U2_ADDR_reg_2__n00005;
  wire U2_ADDR_reg_2__n00006;
  wire U2_ADDR_reg_3__n00001;
  wire U2_ADDR_reg_3__n00002;
  wire U2_ADDR_reg_3__n00003;
  wire U2_ADDR_reg_3__n00004;
  wire U2_ADDR_reg_3__n00005;
  wire U2_ADDR_reg_3__n00006;
  wire U2_ADDR_reg_4__n00001;
  wire U2_ADDR_reg_4__n00002;
  wire U2_ADDR_reg_4__n00003;
  wire U2_ADDR_reg_4__n00004;
  wire U2_ADDR_reg_4__n00005;
  wire U2_ADDR_reg_4__n00006;
  wire U2_ADDR_reg_5__n00001;
  wire U2_ADDR_reg_5__n00002;
  wire U2_ADDR_reg_5__n00003;
  wire U2_ADDR_reg_5__n00004;
  wire U2_ADDR_reg_5__n00005;
  wire U2_ADDR_reg_5__n00006;
  wire U2_ADDR_reg_6__n00001;
  wire U2_ADDR_reg_6__n00002;
  wire U2_ADDR_reg_6__n00003;
  wire U2_ADDR_reg_6__n00004;
  wire U2_ADDR_reg_6__n00005;
  wire U2_ADDR_reg_6__n00006;
  wire U2_ADDR_reg_7__n00001;
  wire U2_ADDR_reg_7__n00002;
  wire U2_ADDR_reg_7__n00003;
  wire U2_ADDR_reg_7__n00004;
  wire U2_ADDR_reg_7__n00005;
  wire U2_ADDR_reg_7__n00006;
  wire U3__n00151;
  wire U3__n00152;
  wire U3__n00153;
  wire U3__n00154;
  wire U3__n00155;
  wire U3__n00156;
  wire U3__n00157;
  wire U3__n00158;
  wire U3__n00159;
  wire U3__n001510;
  wire U3__n001511;
  wire U3__n001512;
  wire U3__n001513;
  wire U3__n001514;
  wire U3__n001515;
  wire U3__n001516;
  wire U2_ADDR_reg_0__n00021;
  wire U2_ADDR_reg_0__n00022;
  wire U2_ADDR_reg_0__n00023;
  wire U2_ADDR_reg_0__n00024;
  wire U2_ADDR_reg_0__n00025;
  wire U2_ADDR_reg_0__n00026;
  wire U2_ADDR_reg_0__n00027;
  wire U2_ADDR_reg_0__n00028;
  wire U2_ADDR_reg_0__n00001;
  wire U2_ADDR_reg_0__n00002;
  wire U2_ADDR_reg_0__n00003;
  wire U2_ADDR_reg_0__n00004;
  wire U2_ADDR_reg_0__n00005;
  wire U2_ADDR_reg_0__n00006;
  wire U2_ADDR_reg_0__n00007;
  wire U2_ADDR_reg_0__n00008;
  wire U2_ADDR_reg_0__n00009;
  wire U2_ADDR_reg_0__n000010;
  wire U2__n00031;
  wire U2_Mcompar_ADDR_in_Range_ALEB;
  wire U2_Mcompar_ADDR_in_Range_ALEB1;
  wire U2_Mcompar_ADDR_in_Range_ALEB2;
  wire U2_Mcompar_ADDR_in_Range_ALEB3;
  wire U2__n00051;
  wire U2__n00052;
  wire U2__n00053;
  wire U2_Enable_AD1;
  wire U2_Enable_AD2;
  wire U2_Mcompar__n0006_ALB;
  wire U2_Mcompar__n0006_ALB1;
  wire U2_Mcompar__n0006_ALB2;
  wire U2_Mcompar__n0006_ALB3;
  wire U2_Mcompar__n0006_ALB4;
  wire U2_Mcompar__n0006_ALB5;
  wire U2_Mcompar__n0006_ALB6;
  wire U7_U3_Maddsub__n0002__n0003;
  wire U7_U3_Maddsub__n0002__n00031;
  wire U7_U3_Maddsub__n0002__n00032;
  wire U7_U3_Maddsub__n0002__n00033;
  wire U7_U3_Maddsub__n0002__n00034;
  wire U7_U3_Maddsub__n0002__n00035;
  wire U7_U3__n00411;
  wire U7_U3__n00412;
  wire U7_U3__n00413;
  wire U7_U3__n00414;
  wire U7_U3__n00415;
  wire U7_U3__n00416;
  wire U7_U3_Maddsub__n0002__n0001;
  wire U7_U3_Maddsub__n0002__n00011;
  wire U7_U3_Maddsub__n0002__n00012;
  wire U7_U3_Maddsub__n0002__n00013;
  wire U7_U3_Maddsub__n0002__n00014;
  wire U7_U3_Maddsub__n0002__n00015;
  wire U7_U3_Maddsub__n0002__n0004;
  wire U7_U3_Maddsub__n0002__n00041;
  wire U7_U3_Maddsub__n0002__n00042;
  wire U7_U3_Maddsub__n0002__n00043;
  wire U7_U3_Maddsub__n0002__n0002;
  wire U7_U3_Maddsub__n0002__n00021;
  wire U7_U3_Maddsub__n0002__n00022;
  wire U7_U3_Maddsub__n0002__n00023;
  wire U7_U3_Maddsub__n0002__n00024;
  wire U7_U3_Maddsub__n0002__n00025;
  wire U7_U3__n0005;
  wire U7_U3__n00051;
  wire U7_U3__n00052;
  wire U7_U3__n00053;
  wire U7_U3__n00054;
  wire U7_U3__n00055;
  wire U7_U3__n00421;
  wire U7_U3__n00422;
  wire U7_U3__n00423;
  wire U7_U3__n00424;
  wire U7_U3__n00425;
  wire U7_U3__n00426;
  wire U7_U3__n00427;
  wire U7_U3_Maddsub__n0002__n0000;
  wire U7_U3_Maddsub__n0002__n00001;
  wire U7_U3_Maddsub__n0002__n00002;
  wire U7_U3_Maddsub__n0002__n00003;
  wire U7_U3_Maddsub__n0002__n00004;
  wire U7_U3_Maddsub__n0002__n00005;
  wire U7_U3__n0000_2_1;
  wire U7_U3__n0000_2_2;
  wire U7_U3__n0000_2_3;
  wire U7_U3__n0000_2_4;
  wire U7_U3__n0000_2_5;
  wire U7_U3__n0000_2_6;
  wire U7_U3__n0000_2_7;
  wire U7_U3__n0000_2_8;
  wire U7_U3__n0000_2_9;
  wire U7_U3__n0000_2_10;
  wire U7_U3__n00061;
  wire U7_U3__n00062;
  wire U3__n0061;
  wire U3__n00611;
  wire U3__n00612;
  wire U3__n00613;
  wire U3__n00614;
  wire U3__n00615;
  wire U3__n00616;
  wire U3__n00617;
  wire U3__n00618;
  wire U3__n00619;
  wire U3__n006110;
  wire U3__n006111;
  wire U3__n006112;
  wire U3__n006113;
  wire U3__n006114;
  wire U3__n006115;
  wire U3__n006116;
  wire U3__n0058;
  wire U3__n00581;
  wire U3__n00582;
  wire U3__n00583;
  wire U3__n00584;
  wire U3__n00585;
  wire U3__n00586;
  wire U3__n00587;
  wire U3__n00588;
  wire U3__n00589;
  wire U3__n005810;
  wire U3__n005811;
  wire U3__n005812;
  wire U3__n005813;
  wire U3__n005814;
  wire U3__n005815;
  wire U3__n0055;
  wire U3__n00551;
  wire U3__n00552;
  wire U3__n00553;
  wire U3__n00554;
  wire U3__n00555;
  wire U3__n00556;
  wire U3__n00557;
  wire U3__n00558;
  wire U3__n00559;
  wire U3__n005510;
  wire U3__n005511;
  wire U3__n005512;
  wire U3__n005513;
  wire U3__n005514;
  wire U3__n005515;
  wire U3__n0052;
  wire U3__n00521;
  wire U3__n00522;
  wire U3__n00523;
  wire U3__n00524;
  wire U3__n00525;
  wire U3__n00526;
  wire U3__n00527;
  wire U3__n00528;
  wire U3__n00529;
  wire U3__n005210;
  wire U3__n005211;
  wire U3__n005212;
  wire U3__n005213;
  wire U3__n005214;
  wire U3__n005215;
  wire U3__n0049;
  wire U3__n00491;
  wire U3__n00492;
  wire U3__n00493;
  wire U3__n00494;
  wire U3__n00495;
  wire U3__n00496;
  wire U3__n00497;
  wire U3__n00498;
  wire U3__n00499;
  wire U3__n004910;
  wire U3__n004911;
  wire U3__n004912;
  wire U3__n004913;
  wire U3__n004914;
  wire U3__n004915;
  wire U3__n0046;
  wire U3__n00461;
  wire U3__n00462;
  wire U3__n00463;
  wire U3__n00464;
  wire U3__n00465;
  wire U3__n00466;
  wire U3__n00467;
  wire U3__n00468;
  wire U3__n00469;
  wire U3__n004610;
  wire U3__n004611;
  wire U3__n004612;
  wire U3__n004613;
  wire U3__n004614;
  wire U3__n004615;
  wire U3__n0043;
  wire U3__n00431;
  wire U3__n00432;
  wire U3__n00433;
  wire U3__n00434;
  wire U3__n00435;
  wire U3__n00436;
  wire U3__n00437;
  wire U3__n00438;
  wire U3__n00439;
  wire U3__n004310;
  wire U3__n004311;
  wire U3__n004312;
  wire U3__n004313;
  wire U3__n004314;
  wire U3__n004315;
  wire U7_U3__n0000_3_1;
  wire U7_U3__n0000_3_2;
  wire U7_U3__n0000_3_3;
  wire U7_U3__n0000_3_4;
  wire U7_U3__n0000_3_5;
  wire U7_U3__n0000_3_6;
  wire U7_U3__n0000_3_7;
  wire U7_U3__n0000_3_8;
  wire U7_U3__n0000_3_9;
  wire U7_U3__n0000_3_10;
  wire U3__n00281;
  wire U3__n00282;
  wire U7_U3__n0000_0_1;
  wire U7_U3__n0000_0_2;
  wire U7_U3__n0000_0_3;
  wire U7_U3__n0000_0_4;
  wire U7_U3__n0000_0_5;
  wire U7_U3__n0000_0_6;
  wire U7_U3__n0000_0_7;
  wire U7_U3__n0000_0_8;
  wire U7_U3__n0000_0_9;
  wire U7_U3__n0000_0_10;
  wire U7_U3__n0000_0_11;
  wire U7_U3__n0000_0_12;
  wire U7_U3__n0000_0_13;
  wire U7_U3__n0000_0_14;
  wire U7_U3__n0000_0_15;
  wire U7_U3__n0000_0_16;
  wire U7_U3__n0000_5_1;
  wire U7_U3__n0000_5_2;
  wire U7_U3__n0000_5_3;
  wire U7_U3__n0000_5_4;
  wire U7_U3__n0000_5_5;
  wire U7_U3__n0000_5_6;
  wire U7_U3__n0000_5_7;
  wire U7_U3__n0000_5_8;
  wire U7_U3__n0000_5_9;
  wire U3__n0040;
  wire U3__n00401;
  wire U3__n00402;
  wire U3__n00403;
  wire U3__n00404;
  wire U3__n00405;
  wire U3__n00406;
  wire U3__n00407;
  wire U3__n00408;
  wire U3__n00409;
  wire U3__n004010;
  wire U3__n004011;
  wire U3__n004012;
  wire U3__n004013;
  wire U3__n004014;
  wire U3__n004015;
  wire U3__n0004_6_1;
  wire U3__n0004_6_2;
  wire U3__n0004_6_3;
  wire U3__n0004_6_4;
  wire U3__n0004_6_5;
  wire U3__n00021;
  wire U3__n00022;
  wire U3__n00023;
  wire U3__n00024;
  wire U3__n00025;
  wire U3__n00026;
  wire U3__n00027;
  wire U3__n00028;
  wire U3__n00029;
  wire U3__n000210;
  wire U3__n000211;
  wire U3__n000212;
  wire U3_Mmux_UIOR_Result;
  wire U3_Mmux_UIOR_Result1;
  wire U3_Mmux_UIOR_Result2;
  wire U3_Mmux_UIOR_Result3;
  wire U3_Mmux_UIOW_Result;
  wire U3_Mmux_UIOW_Result1;
  wire U3_Mmux_UIOW_Result2;
  wire U3_Mmux_UIOW_Result3;
  wire U7_U3__n0000_1_1;
  wire U7_U3__n0000_1_2;
  wire U7_U3__n0000_1_3;
  wire U7_U3__n0000_1_4;
  wire U7_U3__n0000_1_5;
  wire U7_U3__n0000_1_6;
  wire U7_U3__n0000_1_7;
  wire U7_U3__n0000_1_8;
  wire U7_U3__n0000_1_9;
  wire U7_U3__n0000_1_10;
  wire U7_U3__n0000_1_11;
  wire U7_U3__n0000_1_12;
  wire U3__n0004_0_1;
  wire U3__n0004_0_2;
  wire U3__n0004_0_3;
  wire U3__n0004_0_4;
  wire U3__n0004_0_5;
  wire U3__n0004_1_1;
  wire U3__n0004_1_2;
  wire U3__n0004_1_3;
  wire U3__n0004_1_4;
  wire U3__n0004_1_5;
  wire U3__n0004_2_1;
  wire U3__n0004_2_2;
  wire U3__n0004_2_3;
  wire U3__n0004_2_4;
  wire U3__n0004_2_5;
  wire U3__n0004_3_1;
  wire U3__n0004_3_2;
  wire U3__n0004_3_3;
  wire U3__n0004_3_4;
  wire U3__n0004_3_5;
  wire U3__n0004_4_1;
  wire U3__n0004_4_2;
  wire U3__n0004_4_3;
  wire U3__n0004_4_4;
  wire U3__n0004_4_5;
  wire U3__n0004_5_1;
  wire U3__n0004_5_2;
  wire U3__n0004_5_3;
  wire U3__n0004_5_4;
  wire U3__n0004_5_5;
  wire U7_U3__n0000_4_1;
  wire U7_U3__n0000_4_2;
  wire U7_U3__n0000_4_3;
  wire U7_U3__n0000_4_4;
  wire U7_U3__n0000_4_5;
  wire U7_U3__n0000_4_6;
  wire U7_U3__n0000_4_7;
  wire U7_U3__n0000_4_8;
  wire U7_U3__n0000_4_9;
  wire U3__n0004_7_1;
  wire U3__n0004_7_2;
  wire U3__n0004_7_3;
  wire U3__n0004_7_4;
  wire U3__n0004_7_5;
  wire U3__n00031;
  wire U3__n00032;
  wire U3__n00011;
  wire N8543;
  wire N8545;
  wire N8547;
  wire N8549;
  wire N8551;
  wire N8553;
  wire N8555;
  wire N8557;
  wire N8559;
  wire N8561;
  wire N8563;
  wire SD_0_IOBUFE;
  wire SD_1_IOBUFE;
  wire SD_2_IOBUFE;
  wire SD_3_IOBUFE;
  wire SD_4_IOBUFE;
  wire SD_5_IOBUFE;
  wire SD_6_IOBUFE;
  wire SD_7_IOBUFE;
  wire N8581;
  wire N8583;
  wire N8585;
  wire N8587;
  wire N8589;
  wire N8591;
  wire [7 : 0] U2_ADDR_reg;
  wire [5 : 0] U7_U3_counterr;
  wire [5 : 0] U7_U3__n0000;
  wire [0 : 0] U2_Madd__n0011__n0016;
  wire [0 : 0] U2_Madd__n0011__n0014;
  wire [7 : 0] outDATA;
  wire [7 : 1] U2__n0011;
  wire [0 : 0] U7_U3_Maddsub__n0002_Mxor_Result_1___n0002;
  wire [5 : 0] U7_U3__n0002;
  wire [0 : 0] U7_U3_Madd__n0001__n0003;
  wire [0 : 0] U7_U3_Maddsub__n0002_Mxor_Result_2___n0002;
  wire [1 : 0] U7_U3_Maddsub__n0002__n0026;
  wire [1 : 0] U7_U3_Maddsub__n0002__n0028;
  wire [0 : 0] U7_U3_Maddsub__n0002_Mxor_Result_3___n0002;
  wire [0 : 0] U7_U3_Maddsub__n0002__n0032;
  wire [0 : 0] U2_Madd__n0011__n0008;
  wire [3 : 3] U7_U3__n0003;
  wire [5 : 4] U7_U3__n0049;
  wire [1 : 0] U7_U3_Maddsub__n0002__n0030;
  wire [0 : 0] U2_Madd__n0011__n0018;
  wire [0 : 0] U2_Madd__n0011__n0010;
  wire [0 : 0] U2_Madd__n0011__n0012;
  wire [3 : 1] U3__n0000;
  wire [0 : 0] U7_U3_Maddsub__n0002__n0034;
  wire [0 : 0] U7_U3_Maddsub__n0002_Mxor_Result_5___n0002;
  wire [0 : 0] U3_Madd__n0000__n0005;
  wire [1 : 0] U3_Madd__n0000__n0007;
  wire [0 : 0] U7_U3_Maddsub__n0002_Mxor_Result_4___n0002;
  Interrupt U8 (
    .SCLint(NET1764),
    .AM2Status(AM2Status_IBUF),
    .AM1Status(AM1Status_IBUF),
    .Reset(CPLD_Reset_IBUF),
    .AM0Status(AM0Status_IBUF),
    .SystemStatus(SystemStatus_IBUF),
    .ExternalStatus(ExternalStatus_IBUF),
    .ModemStatus(ModemStatus_IBUF),
    .SLPYIEw(NET2480),
    .CameraStatus(CameraStatus_IBUF),
    .UARTint(UINT_IBUF),
    .SLPYIFGr(NET2533),
    .SystemEN(SystemEN_OBUF),
    .MCLK(MCLK_IBUF),
    .INT(INT_OBUF),
    .inDATA({N8547, N8545, N8543, N8591, N8589, N8587, N8585, N8581}),
    .outDATA({outDATA[7], outDATA[6], outDATA[5], outDATA[4], outDATA[3], outDATA[2], outDATA[1], outDATA[0]})
  );
  AddDecode U1 (
    .AS(AS_IBUF),
    .RD(RD_IBUF),
    .WR(WR_IBUF),
    .Wslct0(NET2480),
    .Wslct2(NET1432),
    .Wslct3(NET1440),
    .Wslct4(NET1456),
    .Wslct5(NET1474),
    .Wslct6(NET1448),
    .Rslct0(NET1535),
    .Rslct1(NET2533),
    .Rslct6(NET1523),
    .ADDR({U2_ADDR_reg[7], U2_ADDR_reg[6], U2_ADDR_reg[5], U2_ADDR_reg[4], U2_ADDR_reg[3], U2_ADDR_reg[2], U2_ADDR_reg[1], U2_ADDR_reg[0]})
  );
  INV U2_ADDR_reg_0__n00031 (
    .I(MCLK_IBUF),
    .O(U2_ADDR_reg_0__n0003)
  );
  LPM_XOR2_1 U3_Madd__n0000_Mxor_Result_3_ (
    .Data_0_(U3_Madd__n0000__n0007[0]),
    .Data_1_(U3_Madd__n0000__n0007[1]),
    .Result(U3__n0000[3])
  );
  GalvRelay U4 (
    .Reset(CPLD_Reset_IBUF),
    .SLPYLP(NET1440),
    .MCLK(MCLK_IBUF),
    .SLPYCON(NET1432),
    .LOOPcon0(LOOPcon0_OBUF),
    .LOOPcon1(LOOPcon1_OBUF),
    .LOOPcon2(LOOPcon2_OBUF),
    .CONmodem(CONmodem_OBUF),
    .LOOPmodem(LOOPmodem_OBUF),
    .CONextr(CONextr_OBUF),
    .CONcon0(CONcon0_OBUF),
    .CONcon1(CONcon1_OBUF),
    .CONcon2(CONcon2_OBUF),
    .LOOPextr(LOOPextr_OBUF),
    .inDATA({N8547, N8545, N8543, N8591, N8589, N8587, N8585, N8581})
  );
  TransceiverControl U5 (
    .Reset(CPLD_Reset_IBUF),
    .SLPYEN(NET1456),
    .SLPYPD(NET1474),
    .MCLK(MCLK_IBUF),
    .inDATA({N8547, N8545, N8543, N8591, N8589, N8587, N8585, N8581}),
    .PwrDwn({PD_7_OBUF, PD_6_OBUF, PD_5_OBUF, PD_4_OBUF, PD_3_OBUF, PD_2_OBUF, PD_1_OBUF, PD_0_OBUF}),
    .Enable({EN_7_OBUF, EN_6_OBUF, EN_5_OBUF, EN_4_OBUF, EN_3_OBUF, EN_2_OBUF, EN_1_OBUF, EN_0_OBUF})
  );
  PwrControl U6 (
    .AM2Status(AM2Status_IBUF),
    .AM1Status(AM1Status_IBUF),
    .Reset(CPLD_Reset_IBUF),
    .AM0Status(AM0Status_IBUF),
    .SystemStatus(SystemStatus_IBUF),
    .ExternalStatus(ExternalStatus_IBUF),
    .ModemStatus(ModemStatus_IBUF),
    .SLPYSTATUS(NET1523),
    .CameraStatus(CameraStatus_IBUF),
    .SLPYPWR(NET1448),
    .MCLK(MCLK_IBUF),
    .ModemEN(ModemEN_OBUF),
    .AM2EN(AM2EN_OBUF),
    .CameraEN(CameraEN_OBUF),
    .ExternalEN(ExternalEN_OBUF),
    .DwarfEN(DwarfEN_OBUF),
    .AM0EN(AM0EN_OBUF),
    .SystemEN(SystemEN_OBUF),
    .AM1EN(AM1EN_OBUF),
    .inDATA({N8547, N8545, N8543, N8591, N8589, N8587, N8585, N8581}),
    .outDATA({outDATA[7], outDATA[6], outDATA[5], outDATA[4], outDATA[3], outDATA[2], outDATA[1], outDATA[0]})
  );
  LPM_XOR2_1 U7_U3_Maddsub__n0002_Mxor_Result_4__Mxor_Result (
    .Data_0_(U7_U3_Maddsub__n0002_Mxor_Result_4___n0002[0]),
    .Data_1_(U7_U3_Maddsub__n0002__n0032[0]),
    .Result(U7_U3__n0002[4])
  );
  AND2 U2_ADDR_reg_1__n00007 (
    .I0(U2_ADDR_reg_1__n00006),
    .I1(U2_ADDR_reg_1__n00004),
    .O(U2_ADDR_reg_1__n0000)
  );
  AND2 U2_ADDR_reg_2__n00007 (
    .I0(U2_ADDR_reg_2__n00006),
    .I1(U2_ADDR_reg_2__n00004),
    .O(U2_ADDR_reg_2__n0000)
  );
  AND2 U2_ADDR_reg_3__n00007 (
    .I0(U2_ADDR_reg_3__n00006),
    .I1(U2_ADDR_reg_3__n00004),
    .O(U2_ADDR_reg_3__n0000)
  );
  LPM_XOR2_1 U2_Madd__n0011_Mxor_Result_1_ (
    .Data_0_(U2_ADDR_reg[0]),
    .Data_1_(U2_ADDR_reg[1]),
    .Result(U2__n0011[1])
  );
  AND2 U2_ADDR_reg_4__n00007 (
    .I0(U2_ADDR_reg_4__n00006),
    .I1(U2_ADDR_reg_4__n00004),
    .O(U2_ADDR_reg_4__n0000)
  );
  AND2 U2_ADDR_reg_5__n00007 (
    .I0(U2_ADDR_reg_5__n00006),
    .I1(U2_ADDR_reg_5__n00004),
    .O(U2_ADDR_reg_5__n0000)
  );
  AND2 U2_ADDR_reg_6__n00007 (
    .I0(U2_ADDR_reg_6__n00006),
    .I1(U2_ADDR_reg_6__n00004),
    .O(U2_ADDR_reg_6__n0000)
  );
  AND2 U2_ADDR_reg_7__n00007 (
    .I0(U2_ADDR_reg_7__n00006),
    .I1(U2_ADDR_reg_7__n00004),
    .O(U2_ADDR_reg_7__n0000)
  );
  INV U2__n00181 (
    .I(AS_IBUF),
    .O(U2__n0018)
  );
  OR2 U3__n001517 (
    .I0(U3__n001515),
    .I1(U3__n001516),
    .O(U3__n0015)
  );
  BUFE U7_U3_I1_1 (
    .E(NET1535),
    .I(U7_U3_counterr[1]),
    .O(outDATA[1])
  );
  LPM_XOR2_1 U7_U3_Maddsub__n0002_Mxor_Result_3__Mxor_Result (
    .Data_0_(U7_U3_Maddsub__n0002_Mxor_Result_3___n0002[0]),
    .Data_1_(U7_U3_Maddsub__n0002__n0030[0]),
    .Result(U7_U3__n0002[3])
  );
  OR2 U2_ADDR_reg_0__n00029 (
    .I0(CPLD_Reset_IBUF),
    .I1(U2_ADDR_reg_0__n00028),
    .O(U2_ADDR_reg_0__n0002)
  );
  LPM_XOR2_1 U7_U3_Maddsub__n0002_Mxor_Result_0_ (
    .Data_0_(U7_U3_counterr[0]),
    .Data_1_(N5975),
    .Result(U7_U3__n0002[0])
  );
  AND2 U2_ADDR_reg_0__n000011 (
    .I0(U2_ADDR_reg_0__n000010),
    .I1(U2_ADDR_reg_0__n00008),
    .O(U2_ADDR_reg_0__n0000)
  );
  BUFE U7_U3_I1_5 (
    .E(NET1535),
    .I(U7_U3_counterr[5]),
    .O(outDATA[5])
  );
  IOBUFE SCL_IOBUFE_895 (
    .I(SCL_IOBUFE),
    .E(NET1764),
    .O(N8583),
    .IO(SCL)
  );
  FD U7_U3_counterr_1 (
    .D(U7_U3__n0000[1]),
    .C(U2_ADDR_reg_0__n0003),
    .Q(U7_U3_counterr[1])
  );
  AND2 U2__n00032 (
    .I0(U2_WRRDedge),
    .I1(U2__n00031),
    .O(U2__n0003)
  );
  BUFE U7_U3_I1_4 (
    .E(NET1535),
    .I(U7_U3_counterr[4]),
    .O(outDATA[4])
  );
  FD U2_ASedge_896 (
    .D(AS_IBUF),
    .C(U2_ADDR_reg_0__n0003),
    .Q(U2_ASedge)
  );
  FD U2_WRRDedge_897 (
    .D(U2__n0000),
    .C(U2_ADDR_reg_0__n0003),
    .Q(U2_WRRDedge)
  );
  BUFE U7_U3_I1_0 (
    .E(NET1535),
    .I(U7_U3_counterr[0]),
    .O(outDATA[0])
  );
  GND XST_GND (
    .G(SCL_IOBUFE)
  );
  IOBUFE AD_7_IOBUFE (
    .I(outDATA[7]),
    .E(U2_Enable_AD),
    .O(N8547),
    .IO(AD[7])
  );
  AND4 U2_Mcompar_ADDR_in_Range_ALEB5 (
    .I0(U2_Mcompar_ADDR_in_Range_ALEB),
    .I1(U2_Mcompar_ADDR_in_Range_ALEB1),
    .I2(U2_Mcompar_ADDR_in_Range_ALEB2),
    .I3(U2_Mcompar_ADDR_in_Range_ALEB3),
    .O(U2_ADDR_in_Range)
  );
  FD U7_U3_counterr_5 (
    .D(U7_U3__n0000[5]),
    .C(U2_ADDR_reg_0__n0003),
    .Q(U7_U3_counterr[5])
  );
  BUFE U7_U3_I1_6 (
    .E(NET1535),
    .I(SCL_IOBUFE),
    .O(outDATA[6])
  );
  AND2 U2__n00054 (
    .I0(U2__n00051),
    .I1(U2__n00053),
    .O(U2__n0005)
  );
  AND2 U2_Enable_AD3 (
    .I0(U2_Enable_AD1),
    .I1(U2_Enable_AD2),
    .O(U2_Enable_AD)
  );
  AND2 U2__n00001 (
    .I0(WR_IBUF),
    .I1(RD_IBUF),
    .O(U2__n0000)
  );
  LPM_XOR2_1 U7_U3_Maddsub__n0002_Mxor_Result_2__Mxor__n0000 (
    .Data_0_(U7_U3_counterr[2]),
    .Data_1_(U7_U3_Maddsub__n0002__n0028[1]),
    .Result(U7_U3_Maddsub__n0002_Mxor_Result_2___n0002[0])
  );
  IOBUFE AD_6_IOBUFE (
    .I(outDATA[6]),
    .E(U2_Enable_AD),
    .O(N8545),
    .IO(AD[6])
  );
  IOBUFE AD_5_IOBUFE (
    .I(outDATA[5]),
    .E(U2_Enable_AD),
    .O(N8543),
    .IO(AD[5])
  );
  FDCE U2_AutoInc_898 (
    .D(U2__n0018),
    .CE(U2__n0003),
    .CLR(SCL_IOBUFE),
    .C(U2_ADDR_reg_0__n0003),
    .Q(U2_AutoInc)
  );
  IOBUFE AD_0_IOBUFE (
    .I(outDATA[0]),
    .E(U2_Enable_AD),
    .O(N8581),
    .IO(AD[0])
  );
  IOBUFE AD_1_IOBUFE (
    .I(outDATA[1]),
    .E(U2_Enable_AD),
    .O(N8585),
    .IO(AD[1])
  );
  IOBUFE AD_2_IOBUFE (
    .I(outDATA[2]),
    .E(U2_Enable_AD),
    .O(N8587),
    .IO(AD[2])
  );
  IOBUFE AD_3_IOBUFE (
    .I(outDATA[3]),
    .E(U2_Enable_AD),
    .O(N8589),
    .IO(AD[3])
  );
  IOBUFE AD_4_IOBUFE (
    .I(outDATA[4]),
    .E(U2_Enable_AD),
    .O(N8591),
    .IO(AD[4])
  );
  AND2 U2_Mcompar__n0006_ALB8 (
    .I0(U2_Mcompar__n0006_ALB5),
    .I1(U2_Mcompar__n0006_ALB6),
    .O(U2__n0006)
  );
  AND2 U2_Madd__n0011__n00051 (
    .I0(U2_ADDR_reg[6]),
    .I1(U2_Madd__n0011__n0016[0]),
    .O(U2_Madd__n0011__n0018[0])
  );
  AND2 U2_Madd__n0011__n00041 (
    .I0(U2_ADDR_reg[5]),
    .I1(U2_Madd__n0011__n0014[0]),
    .O(U2_Madd__n0011__n0016[0])
  );
  AND2 U2_Madd__n0011__n00031 (
    .I0(U2_ADDR_reg[4]),
    .I1(U2_Madd__n0011__n0012[0]),
    .O(U2_Madd__n0011__n0014[0])
  );
  AND2 U2_Madd__n0011__n00021 (
    .I0(U2_ADDR_reg[3]),
    .I1(U2_Madd__n0011__n0010[0]),
    .O(U2_Madd__n0011__n0012[0])
  );
  AND2 U2_Madd__n0011__n00011 (
    .I0(U2_ADDR_reg[2]),
    .I1(U2_Madd__n0011__n0008[0]),
    .O(U2_Madd__n0011__n0010[0])
  );
  AND2 U2_Madd__n0011__n00001 (
    .I0(U2_ADDR_reg[1]),
    .I1(U2_ADDR_reg[0]),
    .O(U2_Madd__n0011__n0008[0])
  );
  LPM_XOR2_1 U2_Madd__n0011_Mxor_Result_7_ (
    .Data_0_(U2_Madd__n0011__n0018[0]),
    .Data_1_(U2_ADDR_reg[7]),
    .Result(U2__n0011[7])
  );
  LPM_XOR2_1 U2_Madd__n0011_Mxor_Result_6_ (
    .Data_0_(U2_Madd__n0011__n0016[0]),
    .Data_1_(U2_ADDR_reg[6]),
    .Result(U2__n0011[6])
  );
  LPM_XOR2_1 U2_Madd__n0011_Mxor_Result_5_ (
    .Data_0_(U2_Madd__n0011__n0014[0]),
    .Data_1_(U2_ADDR_reg[5]),
    .Result(U2__n0011[5])
  );
  LPM_XOR2_1 U2_Madd__n0011_Mxor_Result_4_ (
    .Data_0_(U2_Madd__n0011__n0012[0]),
    .Data_1_(U2_ADDR_reg[4]),
    .Result(U2__n0011[4])
  );
  LPM_XOR2_1 U2_Madd__n0011_Mxor_Result_3_ (
    .Data_0_(U2_Madd__n0011__n0010[0]),
    .Data_1_(U2_ADDR_reg[3]),
    .Result(U2__n0011[3])
  );
  LPM_XOR2_1 U2_Madd__n0011_Mxor_Result_2_ (
    .Data_0_(U2_Madd__n0011__n0008[0]),
    .Data_1_(U2_ADDR_reg[2]),
    .Result(U2__n0011[2])
  );
  FDCE U2_ADDR_reg_7 (
    .D(U2_ADDR_reg_7__n0000),
    .CE(U2_ADDR_reg_0__n0002),
    .CLR(SCL_IOBUFE),
    .C(U2_ADDR_reg_0__n0003),
    .Q(U2_ADDR_reg[7])
  );
  FDCE U2_ADDR_reg_6 (
    .D(U2_ADDR_reg_6__n0000),
    .CE(U2_ADDR_reg_0__n0002),
    .CLR(SCL_IOBUFE),
    .C(U2_ADDR_reg_0__n0003),
    .Q(U2_ADDR_reg[6])
  );
  FDCE U2_ADDR_reg_0 (
    .D(U2_ADDR_reg_0__n0000),
    .CE(U2_ADDR_reg_0__n0002),
    .CLR(SCL_IOBUFE),
    .C(U2_ADDR_reg_0__n0003),
    .Q(U2_ADDR_reg[0])
  );
  FDCE U2_ADDR_reg_1 (
    .D(U2_ADDR_reg_1__n0000),
    .CE(U2_ADDR_reg_0__n0002),
    .CLR(SCL_IOBUFE),
    .C(U2_ADDR_reg_0__n0003),
    .Q(U2_ADDR_reg[1])
  );
  FDCE U2_ADDR_reg_2 (
    .D(U2_ADDR_reg_2__n0000),
    .CE(U2_ADDR_reg_0__n0002),
    .CLR(SCL_IOBUFE),
    .C(U2_ADDR_reg_0__n0003),
    .Q(U2_ADDR_reg[2])
  );
  FDCE U2_ADDR_reg_3 (
    .D(U2_ADDR_reg_3__n0000),
    .CE(U2_ADDR_reg_0__n0002),
    .CLR(SCL_IOBUFE),
    .C(U2_ADDR_reg_0__n0003),
    .Q(U2_ADDR_reg[3])
  );
  FDCE U2_ADDR_reg_4 (
    .D(U2_ADDR_reg_4__n0000),
    .CE(U2_ADDR_reg_0__n0002),
    .CLR(SCL_IOBUFE),
    .C(U2_ADDR_reg_0__n0003),
    .Q(U2_ADDR_reg[4])
  );
  FDCE U2_ADDR_reg_5 (
    .D(U2_ADDR_reg_5__n0000),
    .CE(U2_ADDR_reg_0__n0002),
    .CLR(SCL_IOBUFE),
    .C(U2_ADDR_reg_0__n0003),
    .Q(U2_ADDR_reg[5])
  );
  LPM_XOR2_1 U7_U3_Maddsub__n0002_Mxor__n0022 (
    .Data_0_(U7_U3__n0006),
    .Data_1_(SCL_IOBUFE),
    .Result(U7_U3_Maddsub__n0002__n0028[0])
  );
  BUFE U7_U3_I1_2 (
    .E(NET1535),
    .I(U7_U3_counterr[2]),
    .O(outDATA[2])
  );
  OR2 U7_U3_Maddsub__n0002__n00037 (
    .I0(U7_U3_Maddsub__n0002__n0003),
    .I1(U7_U3_Maddsub__n0002__n00035),
    .O(U7_U3_Maddsub__n0002__n0032[0])
  );
  AND2 U7_U3__n00417 (
    .I0(U7_U3__n00411),
    .I1(U7_U3__n00416),
    .O(U7_U3__n0041)
  );
  LPM_XOR2_1 U7_U3_Maddsub__n0002_Mxor__n0021 (
    .Data_0_(U7_U3__n0006),
    .Data_1_(SCL_IOBUFE),
    .Result(U7_U3_Maddsub__n0002__n0026[0])
  );
  OR2 U7_U3_Maddsub__n0002__n00017 (
    .I0(U7_U3_Maddsub__n0002__n0001),
    .I1(U7_U3_Maddsub__n0002__n00015),
    .O(U7_U3_Maddsub__n0002__n0028[1])
  );
  FD U7_U3_counterr_3 (
    .D(U7_U3__n0000[3]),
    .C(U2_ADDR_reg_0__n0003),
    .Q(U7_U3_counterr[3])
  );
  LPM_XOR2_1 U7_U3_Maddsub__n0002_Mxor__n0020 (
    .Data_0_(U7_U3__n0006),
    .Data_1_(N5975),
    .Result(U7_U3_Maddsub__n0002__n0020)
  );
  INV U7_U3_Maddsub__n0002__n00045 (
    .I(U7_U3_Maddsub__n0002__n00043),
    .O(U7_U3_Maddsub__n0002__n0034[0])
  );
  OR2 U7_U3_Maddsub__n0002__n00027 (
    .I0(U7_U3_Maddsub__n0002__n0002),
    .I1(U7_U3_Maddsub__n0002__n00025),
    .O(U7_U3_Maddsub__n0002__n0030[1])
  );
  LPM_XOR2_1 U7_U3_Maddsub__n0002_Mxor_Result_5__Mxor__n0000 (
    .Data_0_(U7_U3_counterr[5]),
    .Data_1_(U7_U3__n0006),
    .Result(U7_U3_Maddsub__n0002_Mxor_Result_5___n0002[0])
  );
  AND6 U7_U3__n00057 (
    .I0(U7_U3__n00051),
    .I1(U7_U3__n0005),
    .I2(U7_U3__n00052),
    .I3(U7_U3__n00054),
    .I4(U7_U3__n00053),
    .I5(U7_U3__n00055),
    .O(NET1764)
  );
  AND2 U7_U3__n00428 (
    .I0(U7_U3__n00424),
    .I1(U7_U3__n00427),
    .O(U7_U3__n0042)
  );
  LPM_XOR2_1 U7_U3_Maddsub__n0002_Mxor_Result_4__Mxor__n0000 (
    .Data_0_(U7_U3_counterr[4]),
    .Data_1_(U7_U3__n0006),
    .Result(U7_U3_Maddsub__n0002_Mxor_Result_4___n0002[0])
  );
  OR2 U7_U3_Maddsub__n0002__n00007 (
    .I0(U7_U3_Maddsub__n0002__n0000),
    .I1(U7_U3_Maddsub__n0002__n00005),
    .O(U7_U3_Maddsub__n0002__n0026[1])
  );
  FD U7_U3_counterr_4 (
    .D(U7_U3__n0000[4]),
    .C(U2_ADDR_reg_0__n0003),
    .Q(U7_U3_counterr[4])
  );
  LPM_XOR2_1 U7_U3_Maddsub__n0002_Mxor_Result_3__Mxor__n0000 (
    .Data_0_(U7_U3_counterr[3]),
    .Data_1_(U7_U3_Maddsub__n0002__n0030[1]),
    .Result(U7_U3_Maddsub__n0002_Mxor_Result_3___n0002[0])
  );
  OR2 U7_U3__n0000_2_11 (
    .I0(U7_U3__n0000_2_9),
    .I1(U7_U3__n0000_2_10),
    .O(U7_U3__n0000[2])
  );
  FD U7_U3_counterr_2 (
    .D(U7_U3__n0000[2]),
    .C(U2_ADDR_reg_0__n0003),
    .Q(U7_U3_counterr[2])
  );
  LPM_XOR2_1 U7_U3_Maddsub__n0002_Mxor_Result_1__Mxor__n0000 (
    .Data_0_(U7_U3_counterr[1]),
    .Data_1_(U7_U3_Maddsub__n0002__n0026[1]),
    .Result(U7_U3_Maddsub__n0002_Mxor_Result_1___n0002[0])
  );
  AND2 U7_U3_Maddsub__n0002__n00191 (
    .I0(U7_U3__n0006),
    .I1(U7_U3_Maddsub__n0002__n0032[0]),
    .O(U7_U3_Maddsub__n0002__n0019)
  );
  AND3 U7_U3__n00063 (
    .I0(U7_U3__n00061),
    .I1(U7_SCLdetect),
    .I2(U7_U3__n00062),
    .O(U7_U3__n0006)
  );
  OR2 U3__n006118 (
    .I0(U3__n006116),
    .I1(U3__n006114),
    .O(UAD_4_OBUF)
  );
  OR2 U3__n005817 (
    .I0(U3__n005810),
    .I1(U3__n005815),
    .O(UAD_5_OBUF)
  );
  OR2 U3__n005517 (
    .I0(U3__n005510),
    .I1(U3__n005515),
    .O(UAD_6_OBUF)
  );
  OR2 U3__n005217 (
    .I0(U3__n005210),
    .I1(U3__n005215),
    .O(UAD_7_OBUF)
  );
  OR2 U3__n004917 (
    .I0(U3__n004910),
    .I1(U3__n004915),
    .O(UAD_0_OBUF)
  );
  OR2 U3__n004617 (
    .I0(U3__n004610),
    .I1(U3__n004615),
    .O(UAD_1_OBUF)
  );
  OR2 U3__n004317 (
    .I0(U3__n004310),
    .I1(U3__n004315),
    .O(UAD_2_OBUF)
  );
  OR3 U7_U3__n0000_3_11 (
    .I0(U7_U3__n0000_3_10),
    .I1(SCLreset_IBUF),
    .I2(U7_U3__n0000_3_9),
    .O(U7_U3__n0000[3])
  );
  INV U3__n00331 (
    .I(U3__n0028),
    .O(U3__n0033)
  );
  LPM_XOR2_1 U3_Madd__n0000_Mxor_Result_2_ (
    .Data_0_(U3_Madd__n0000__n0005[0]),
    .Data_1_(U2_ADDR_reg[6]),
    .Result(U3__n0000[2])
  );
  AND2 U3__n00283 (
    .I0(U3__n00281),
    .I1(U3__n00282),
    .O(U3__n0028)
  );
  AND2 U7_U3_Maddsub__n0002__n00171 (
    .I0(U7_U3_counterr[4]),
    .I1(U7_U3__n0006),
    .O(U7_U3_Maddsub__n0002__n0017)
  );
  LPM_XOR2_1 U7_U3_Maddsub__n0002_Mxor_Result_1__Mxor_Result (
    .Data_0_(U7_U3_Maddsub__n0002_Mxor_Result_1___n0002[0]),
    .Data_1_(U7_U3_Maddsub__n0002__n0026[0]),
    .Result(U7_U3__n0002[1])
  );
  BUFE U7_U3_I1_7 (
    .E(NET1535),
    .I(SCL_IOBUFE),
    .O(outDATA[7])
  );
  LPM_XOR2_1 U7_U3_Madd__n0001_Mxor_Result_2_ (
    .Data_0_(U7_U3_Madd__n0001__n0003[0]),
    .Data_1_(U7_U3_counterr[5]),
    .Result(U7_U3__n0049[5])
  );
  IOBUFE UD_7_IOBUFE_899 (
    .I(UD_7_IOBUFE),
    .E(U3__n0033),
    .O(SD_7_IOBUFE),
    .IO(UD[7])
  );
  BUFE U3_I2_7 (
    .E(U3__n0003),
    .I(SD_7_IOBUFE),
    .O(outDATA[7])
  );
  OR4 U7_U3__n0000_0_17 (
    .I3(U7_U3__n0000_0_14),
    .I0(U7_U3__n0000_0_1),
    .I1(U7_U3__n0000_0_15),
    .I2(U7_U3__n0000_0_16),
    .O(U7_U3__n0000[0])
  );
  OR3 U7_U3__n0000_5_10 (
    .I0(U7_U3__n0000_5_9),
    .I1(U7_U3__n0000_5_1),
    .I2(U7_U3__n0000_5_7),
    .O(U7_U3__n0000[5])
  );
  OR2 U3__n004017 (
    .I0(U3__n004010),
    .I1(U3__n004015),
    .O(UAD_3_OBUF)
  );
  INV U7_U3__n0003_3_1 (
    .I(U7_U3__n0006),
    .O(U7_U3__n0003[3])
  );
  IOBUFE SD_7_IOBUFE_900 (
    .I(SD_7_IOBUFE),
    .E(U3__n0002),
    .O(N8563),
    .IO(SD[7])
  );
  BUFE U7_U3_I1_3 (
    .E(NET1535),
    .I(U7_U3_counterr[3]),
    .O(outDATA[3])
  );
  AND2 U7_U3_Madd__n0001__n00001 (
    .I0(U7_U3_counterr[4]),
    .I1(U7_U3_counterr[3]),
    .O(U7_U3_Madd__n0001__n0003[0])
  );
  LPM_XOR2_1 U7_U3_Maddsub__n0002_Mxor__n0023 (
    .Data_0_(U7_U3__n0006),
    .Data_1_(U7_U3__n0003[3]),
    .Result(U7_U3_Maddsub__n0002__n0030[0])
  );
  AND3 U3__n0004_6_6 (
    .I0(U3__n0004_6_5),
    .I1(U3__n0015),
    .I2(U3__n0004_6_3),
    .O(UD_6_IOBUFE)
  );
  AND2 U3__n000213 (
    .I0(U3__n000211),
    .I1(U3__n000212),
    .O(U3__n0002)
  );
  INV U3_UARTcs1 (
    .I(U3__n0015),
    .O(UCS_OBUF)
  );
  OR3 U3_Mmux_UIOR_Result5 (
    .I0(U3_Mmux_UIOR_Result3),
    .I1(U3_Mmux_UIOR_Result),
    .I2(U3_Mmux_UIOR_Result2),
    .O(UIOR_OBUF)
  );
  AND2 U7_U3_Maddsub__n0002__n00181 (
    .I0(U7_U3_counterr[4]),
    .I1(U7_U3_Maddsub__n0002__n0032[0]),
    .O(U7_U3_Maddsub__n0002__n0018)
  );
  OR3 U3_Mmux_UIOW_Result5 (
    .I0(U3_Mmux_UIOW_Result3),
    .I1(U3_Mmux_UIOW_Result),
    .I2(U3_Mmux_UIOW_Result2),
    .O(UIOW_OBUF)
  );
  OR3 U7_U3__n0000_1_13 (
    .I0(U7_U3__n0000_1_12),
    .I1(U7_U3__n0000_1_11),
    .I2(U7_U3__n0000_1_8),
    .O(U7_U3__n0000[1])
  );
  AND3 U3__n0004_0_6 (
    .I0(U3__n0004_0_5),
    .I1(U3__n0015),
    .I2(U3__n0004_0_3),
    .O(UD_0_IOBUFE)
  );
  AND3 U3__n0004_1_6 (
    .I0(U3__n0004_1_5),
    .I1(U3__n0015),
    .I2(U3__n0004_1_3),
    .O(UD_1_IOBUFE)
  );
  AND3 U3__n0004_2_6 (
    .I0(U3__n0004_2_5),
    .I1(U3__n0015),
    .I2(U3__n0004_2_3),
    .O(UD_2_IOBUFE)
  );
  AND3 U3__n0004_3_6 (
    .I0(U3__n0004_3_5),
    .I1(U3__n0015),
    .I2(U3__n0004_3_3),
    .O(UD_3_IOBUFE)
  );
  AND3 U3__n0004_4_6 (
    .I0(U3__n0004_4_5),
    .I1(U3__n0015),
    .I2(U3__n0004_4_3),
    .O(UD_4_IOBUFE)
  );
  AND3 U3__n0004_5_6 (
    .I0(U3__n0004_5_5),
    .I1(U3__n0015),
    .I2(U3__n0004_5_3),
    .O(UD_5_IOBUFE)
  );
  OR3 U7_U3__n0000_4_10 (
    .I0(U7_U3__n0000_4_9),
    .I1(U7_U3__n0000_4_1),
    .I2(U7_U3__n0000_4_7),
    .O(U7_U3__n0000[4])
  );
  AND3 U3__n0004_7_6 (
    .I0(U3__n0004_7_5),
    .I1(U3__n0015),
    .I2(U3__n0004_7_3),
    .O(UD_7_IOBUFE)
  );
  AND3 U3__n00033 (
    .I0(U3__n00031),
    .I1(U3__n0015),
    .I2(U3__n00032),
    .O(U3__n0003)
  );
  NegDetect U7_U4 (
    .Line(SCLreset_IBUF),
    .MCLK(MCLK_IBUF),
    .Ndetect(U7_ResetDetect)
  );
  AND2 U3__n00012 (
    .I0(SystemEN_OBUF),
    .I1(U3__n00011),
    .O(U3__n0001)
  );
  VCC XST_VCC (
    .P(N5975)
  );
  LPM_XOR2_1 U3_Madd__n0000_Mxor_Result_1_ (
    .Data_0_(U2_ADDR_reg[4]),
    .Data_1_(U2_ADDR_reg[5]),
    .Result(U3__n0000[1])
  );
  LPM_XOR2_1 U7_U3_Madd__n0001_Mxor_Result_1_ (
    .Data_0_(U7_U3_counterr[3]),
    .Data_1_(U7_U3_counterr[4]),
    .Result(U7_U3__n0049[4])
  );
  FD U7_U3_counterr_0 (
    .D(U7_U3__n0000[0]),
    .C(U2_ADDR_reg_0__n0003),
    .Q(U7_U3_counterr[0])
  );
  OBUFE IRQ_OBUFE (
    .E(U3__n0001),
    .I(SCL_IOBUFE),
    .O(IRQ)
  );
  IOBUFE UD_0_IOBUFE_901 (
    .I(UD_0_IOBUFE),
    .E(U3__n0033),
    .O(SD_0_IOBUFE),
    .IO(UD[0])
  );
  IOBUFE UD_1_IOBUFE_902 (
    .I(UD_1_IOBUFE),
    .E(U3__n0033),
    .O(SD_1_IOBUFE),
    .IO(UD[1])
  );
  IOBUFE UD_2_IOBUFE_903 (
    .I(UD_2_IOBUFE),
    .E(U3__n0033),
    .O(SD_2_IOBUFE),
    .IO(UD[2])
  );
  IOBUFE UD_3_IOBUFE_904 (
    .I(UD_3_IOBUFE),
    .E(U3__n0033),
    .O(SD_3_IOBUFE),
    .IO(UD[3])
  );
  IOBUFE UD_4_IOBUFE_905 (
    .I(UD_4_IOBUFE),
    .E(U3__n0033),
    .O(SD_4_IOBUFE),
    .IO(UD[4])
  );
  IOBUFE UD_5_IOBUFE_906 (
    .I(UD_5_IOBUFE),
    .E(U3__n0033),
    .O(SD_5_IOBUFE),
    .IO(UD[5])
  );
  IOBUFE UD_6_IOBUFE_907 (
    .I(UD_6_IOBUFE),
    .E(U3__n0033),
    .O(SD_6_IOBUFE),
    .IO(UD[6])
  );
  BUFE U3_I2_0 (
    .E(U3__n0003),
    .I(SD_0_IOBUFE),
    .O(outDATA[0])
  );
  BUFE U3_I2_1 (
    .E(U3__n0003),
    .I(SD_1_IOBUFE),
    .O(outDATA[1])
  );
  BUFE U3_I2_2 (
    .E(U3__n0003),
    .I(SD_2_IOBUFE),
    .O(outDATA[2])
  );
  BUFE U3_I2_3 (
    .E(U3__n0003),
    .I(SD_3_IOBUFE),
    .O(outDATA[3])
  );
  BUFE U3_I2_4 (
    .E(U3__n0003),
    .I(SD_4_IOBUFE),
    .O(outDATA[4])
  );
  BUFE U3_I2_5 (
    .E(U3__n0003),
    .I(SD_5_IOBUFE),
    .O(outDATA[5])
  );
  BUFE U3_I2_6 (
    .E(U3__n0003),
    .I(SD_6_IOBUFE),
    .O(outDATA[6])
  );
  IOBUFE SD_0_IOBUFE_908 (
    .I(SD_0_IOBUFE),
    .E(U3__n0002),
    .O(N8549),
    .IO(SD[0])
  );
  IOBUFE SD_1_IOBUFE_909 (
    .I(SD_1_IOBUFE),
    .E(U3__n0002),
    .O(N8551),
    .IO(SD[1])
  );
  IOBUFE SD_2_IOBUFE_910 (
    .I(SD_2_IOBUFE),
    .E(U3__n0002),
    .O(N8553),
    .IO(SD[2])
  );
  IOBUFE SD_3_IOBUFE_911 (
    .I(SD_3_IOBUFE),
    .E(U3__n0002),
    .O(N8555),
    .IO(SD[3])
  );
  IOBUFE SD_4_IOBUFE_912 (
    .I(SD_4_IOBUFE),
    .E(U3__n0002),
    .O(N8557),
    .IO(SD[4])
  );
  IOBUFE SD_5_IOBUFE_913 (
    .I(SD_5_IOBUFE),
    .E(U3__n0002),
    .O(N8559),
    .IO(SD[5])
  );
  IOBUFE SD_6_IOBUFE_914 (
    .I(SD_6_IOBUFE),
    .E(U3__n0002),
    .O(N8561),
    .IO(SD[6])
  );
  INV U3_Madd__n0000__n00141 (
    .I(U2_ADDR_reg[7]),
    .O(U3_Madd__n0000__n0007[1])
  );
  LPM_XOR2_1 U7_U3_Maddsub__n0002_Mxor_Result_5__Mxor_Result (
    .Data_0_(U7_U3_Maddsub__n0002_Mxor_Result_5___n0002[0]),
    .Data_1_(U7_U3_Maddsub__n0002__n0034[0]),
    .Result(U7_U3__n0002[5])
  );
  AND2 U3_Madd__n0000__n00011 (
    .I0(U2_ADDR_reg[6]),
    .I1(U3_Madd__n0000__n0005[0]),
    .O(U3_Madd__n0000__n0007[0])
  );
  AND2 U3_Madd__n0000__n00001 (
    .I0(U2_ADDR_reg[5]),
    .I1(U2_ADDR_reg[4]),
    .O(U3_Madd__n0000__n0005[0])
  );
  NegDetect U7_U1 (
    .Line(SCLinc_IBUF),
    .MCLK(MCLK_IBUF),
    .Ndetect(U7_Incdetect)
  );
  NegDetect U7_U2 (
    .Line(N8583),
    .MCLK(MCLK_IBUF),
    .Ndetect(U7_SCLdetect)
  );
  LPM_XOR2_1 U7_U3_Maddsub__n0002_Mxor_Result_2__Mxor_Result (
    .Data_0_(U7_U3_Maddsub__n0002_Mxor_Result_2___n0002[0]),
    .Data_1_(U7_U3_Maddsub__n0002__n0028[0]),
    .Result(U7_U3__n0002[2])
  );
  AND2 U2_ADDR_reg_1__n00001_915 (
    .I0(U2__n0005),
    .I1(N8585),
    .O(U2_ADDR_reg_1__n00001)
  );
  AND2 U2_ADDR_reg_1__n00002_916 (
    .I0(U2__n0011[1]),
    .I1(U2__n0006),
    .O(U2_ADDR_reg_1__n00002)
  );
  INV U2_ADDR_reg_1__n00003_917 (
    .I(U2__n0005),
    .O(U2_ADDR_reg_1__n00003)
  );
  INV U2_ADDR_reg_1__n00004_918 (
    .I(CPLD_Reset_IBUF),
    .O(U2_ADDR_reg_1__n00004)
  );
  AND2 U2_ADDR_reg_1__n00005_919 (
    .I0(U2_ADDR_reg_1__n00002),
    .I1(U2_ADDR_reg_1__n00003),
    .O(U2_ADDR_reg_1__n00005)
  );
  OR2 U2_ADDR_reg_1__n00006_920 (
    .I0(U2_ADDR_reg_1__n00001),
    .I1(U2_ADDR_reg_1__n00005),
    .O(U2_ADDR_reg_1__n00006)
  );
  AND2 U2_ADDR_reg_2__n00001_921 (
    .I0(U2__n0005),
    .I1(N8587),
    .O(U2_ADDR_reg_2__n00001)
  );
  AND2 U2_ADDR_reg_2__n00002_922 (
    .I0(U2__n0011[2]),
    .I1(U2__n0006),
    .O(U2_ADDR_reg_2__n00002)
  );
  INV U2_ADDR_reg_2__n00003_923 (
    .I(U2__n0005),
    .O(U2_ADDR_reg_2__n00003)
  );
  INV U2_ADDR_reg_2__n00004_924 (
    .I(CPLD_Reset_IBUF),
    .O(U2_ADDR_reg_2__n00004)
  );
  AND2 U2_ADDR_reg_2__n00005_925 (
    .I0(U2_ADDR_reg_2__n00002),
    .I1(U2_ADDR_reg_2__n00003),
    .O(U2_ADDR_reg_2__n00005)
  );
  OR2 U2_ADDR_reg_2__n00006_926 (
    .I0(U2_ADDR_reg_2__n00001),
    .I1(U2_ADDR_reg_2__n00005),
    .O(U2_ADDR_reg_2__n00006)
  );
  AND2 U2_ADDR_reg_3__n00001_927 (
    .I0(U2__n0005),
    .I1(N8589),
    .O(U2_ADDR_reg_3__n00001)
  );
  AND2 U2_ADDR_reg_3__n00002_928 (
    .I0(U2__n0011[3]),
    .I1(U2__n0006),
    .O(U2_ADDR_reg_3__n00002)
  );
  INV U2_ADDR_reg_3__n00003_929 (
    .I(U2__n0005),
    .O(U2_ADDR_reg_3__n00003)
  );
  INV U2_ADDR_reg_3__n00004_930 (
    .I(CPLD_Reset_IBUF),
    .O(U2_ADDR_reg_3__n00004)
  );
  AND2 U2_ADDR_reg_3__n00005_931 (
    .I0(U2_ADDR_reg_3__n00002),
    .I1(U2_ADDR_reg_3__n00003),
    .O(U2_ADDR_reg_3__n00005)
  );
  OR2 U2_ADDR_reg_3__n00006_932 (
    .I0(U2_ADDR_reg_3__n00001),
    .I1(U2_ADDR_reg_3__n00005),
    .O(U2_ADDR_reg_3__n00006)
  );
  AND2 U2_ADDR_reg_4__n00001_933 (
    .I0(U2__n0005),
    .I1(N8591),
    .O(U2_ADDR_reg_4__n00001)
  );
  AND2 U2_ADDR_reg_4__n00002_934 (
    .I0(U2__n0011[4]),
    .I1(U2__n0006),
    .O(U2_ADDR_reg_4__n00002)
  );
  INV U2_ADDR_reg_4__n00003_935 (
    .I(U2__n0005),
    .O(U2_ADDR_reg_4__n00003)
  );
  INV U2_ADDR_reg_4__n00004_936 (
    .I(CPLD_Reset_IBUF),
    .O(U2_ADDR_reg_4__n00004)
  );
  AND2 U2_ADDR_reg_4__n00005_937 (
    .I0(U2_ADDR_reg_4__n00002),
    .I1(U2_ADDR_reg_4__n00003),
    .O(U2_ADDR_reg_4__n00005)
  );
  OR2 U2_ADDR_reg_4__n00006_938 (
    .I0(U2_ADDR_reg_4__n00001),
    .I1(U2_ADDR_reg_4__n00005),
    .O(U2_ADDR_reg_4__n00006)
  );
  AND2 U2_ADDR_reg_5__n00001_939 (
    .I0(U2__n0005),
    .I1(N8543),
    .O(U2_ADDR_reg_5__n00001)
  );
  AND2 U2_ADDR_reg_5__n00002_940 (
    .I0(U2__n0011[5]),
    .I1(U2__n0006),
    .O(U2_ADDR_reg_5__n00002)
  );
  INV U2_ADDR_reg_5__n00003_941 (
    .I(U2__n0005),
    .O(U2_ADDR_reg_5__n00003)
  );
  INV U2_ADDR_reg_5__n00004_942 (
    .I(CPLD_Reset_IBUF),
    .O(U2_ADDR_reg_5__n00004)
  );
  AND2 U2_ADDR_reg_5__n00005_943 (
    .I0(U2_ADDR_reg_5__n00002),
    .I1(U2_ADDR_reg_5__n00003),
    .O(U2_ADDR_reg_5__n00005)
  );
  OR2 U2_ADDR_reg_5__n00006_944 (
    .I0(U2_ADDR_reg_5__n00001),
    .I1(U2_ADDR_reg_5__n00005),
    .O(U2_ADDR_reg_5__n00006)
  );
  AND2 U2_ADDR_reg_6__n00001_945 (
    .I0(U2__n0005),
    .I1(N8545),
    .O(U2_ADDR_reg_6__n00001)
  );
  AND2 U2_ADDR_reg_6__n00002_946 (
    .I0(U2__n0011[6]),
    .I1(U2__n0006),
    .O(U2_ADDR_reg_6__n00002)
  );
  INV U2_ADDR_reg_6__n00003_947 (
    .I(U2__n0005),
    .O(U2_ADDR_reg_6__n00003)
  );
  INV U2_ADDR_reg_6__n00004_948 (
    .I(CPLD_Reset_IBUF),
    .O(U2_ADDR_reg_6__n00004)
  );
  AND2 U2_ADDR_reg_6__n00005_949 (
    .I0(U2_ADDR_reg_6__n00002),
    .I1(U2_ADDR_reg_6__n00003),
    .O(U2_ADDR_reg_6__n00005)
  );
  OR2 U2_ADDR_reg_6__n00006_950 (
    .I0(U2_ADDR_reg_6__n00001),
    .I1(U2_ADDR_reg_6__n00005),
    .O(U2_ADDR_reg_6__n00006)
  );
  AND2 U2_ADDR_reg_7__n00001_951 (
    .I0(U2__n0005),
    .I1(N8547),
    .O(U2_ADDR_reg_7__n00001)
  );
  AND2 U2_ADDR_reg_7__n00002_952 (
    .I0(U2__n0011[7]),
    .I1(U2__n0006),
    .O(U2_ADDR_reg_7__n00002)
  );
  INV U2_ADDR_reg_7__n00003_953 (
    .I(U2__n0005),
    .O(U2_ADDR_reg_7__n00003)
  );
  INV U2_ADDR_reg_7__n00004_954 (
    .I(CPLD_Reset_IBUF),
    .O(U2_ADDR_reg_7__n00004)
  );
  AND2 U2_ADDR_reg_7__n00005_955 (
    .I0(U2_ADDR_reg_7__n00002),
    .I1(U2_ADDR_reg_7__n00003),
    .O(U2_ADDR_reg_7__n00005)
  );
  OR2 U2_ADDR_reg_7__n00006_956 (
    .I0(U2_ADDR_reg_7__n00001),
    .I1(U2_ADDR_reg_7__n00005),
    .O(U2_ADDR_reg_7__n00006)
  );
  AND3 U3__n00151_957 (
    .I0(U2_ADDR_reg[4]),
    .I1(U2_ADDR_reg[5]),
    .I2(U2_ADDR_reg[6]),
    .O(U3__n00151)
  );
  INV U3__n00152_958 (
    .I(SystemEN_OBUF),
    .O(U3__n00152)
  );
  INV U3__n00153_959 (
    .I(AEN_IBUF),
    .O(U3__n00153)
  );
  INV U3__n00154_960 (
    .I(SA_8_IBUF),
    .O(U3__n00154)
  );
  INV U3__n00155_961 (
    .I(SA_9_IBUF),
    .O(U3__n00155)
  );
  INV U3__n00156_962 (
    .I(SA_10_IBUF),
    .O(U3__n00156)
  );
  INV U3__n00157_963 (
    .I(SA_12_IBUF),
    .O(U3__n00157)
  );
  INV U3__n00158_964 (
    .I(SA_11_IBUF),
    .O(U3__n00158)
  );
  INV U3__n00159_965 (
    .I(SA_13_IBUF),
    .O(U3__n00159)
  );
  INV U3__n001510_966 (
    .I(SA_14_IBUF),
    .O(U3__n001510)
  );
  INV U3__n001511_967 (
    .I(SA_15_IBUF),
    .O(U3__n001511)
  );
  OR2 U3__n001512_968 (
    .I0(U2_ADDR_reg[7]),
    .I1(U3__n00151),
    .O(U3__n001512)
  );
  AND8 U3__n001513_969 (
    .I0(SystemEN_OBUF),
    .I1(U3__n00153),
    .I2(U3__n00154),
    .I3(U3__n00155),
    .I4(U3__n00156),
    .I5(U3__n00157),
    .I6(U3__n00158),
    .I7(U3__n00159),
    .O(U3__n001513)
  );
  AND2 U3__n001514_970 (
    .I0(U3__n001510),
    .I1(U3__n001511),
    .O(U3__n001514)
  );
  AND2 U3__n001515_971 (
    .I0(U3__n001512),
    .I1(U3__n00152),
    .O(U3__n001515)
  );
  AND2 U3__n001516_972 (
    .I0(U3__n001513),
    .I1(U3__n001514),
    .O(U3__n001516)
  );
  AND2 U2_ADDR_reg_0__n00021_973 (
    .I0(RD_IBUF),
    .I1(WR_IBUF),
    .O(U2_ADDR_reg_0__n00021)
  );
  INV U2_ADDR_reg_0__n00022_974 (
    .I(AS_IBUF),
    .O(U2_ADDR_reg_0__n00022)
  );
  AND2 U2_ADDR_reg_0__n00023_975 (
    .I0(U2_AutoInc),
    .I1(U2_ADDR_in_Range),
    .O(U2_ADDR_reg_0__n00023)
  );
  INV U2_ADDR_reg_0__n00024_976 (
    .I(U2_WRRDedge),
    .O(U2_ADDR_reg_0__n00024)
  );
  AND2 U2_ADDR_reg_0__n00025_977 (
    .I0(U2_ASedge),
    .I1(U2_ADDR_reg_0__n00022),
    .O(U2_ADDR_reg_0__n00025)
  );
  AND2 U2_ADDR_reg_0__n00026_978 (
    .I0(U2_ADDR_reg_0__n00023),
    .I1(U2_ADDR_reg_0__n00024),
    .O(U2_ADDR_reg_0__n00026)
  );
  OR2 U2_ADDR_reg_0__n00027_979 (
    .I0(U2_ADDR_reg_0__n00025),
    .I1(U2_ADDR_reg_0__n00026),
    .O(U2_ADDR_reg_0__n00027)
  );
  AND2 U2_ADDR_reg_0__n00028_980 (
    .I0(U2_ADDR_reg_0__n00021),
    .I1(U2_ADDR_reg_0__n00027),
    .O(U2_ADDR_reg_0__n00028)
  );
  AND2 U2_ADDR_reg_0__n00001_981 (
    .I0(U2__n0005),
    .I1(N8581),
    .O(U2_ADDR_reg_0__n00001)
  );
  INV U2_ADDR_reg_0__n00002_982 (
    .I(U2_ADDR_reg[0]),
    .O(U2_ADDR_reg_0__n00002)
  );
  INV U2_ADDR_reg_0__n00003_983 (
    .I(U2__n0005),
    .O(U2_ADDR_reg_0__n00003)
  );
  INV U2_ADDR_reg_0__n00004_984 (
    .I(U2_ADDR_reg[4]),
    .O(U2_ADDR_reg_0__n00004)
  );
  INV U2_ADDR_reg_0__n00005_985 (
    .I(U2_ADDR_reg[6]),
    .O(U2_ADDR_reg_0__n00005)
  );
  INV U2_ADDR_reg_0__n00006_986 (
    .I(U2_ADDR_reg[5]),
    .O(U2_ADDR_reg_0__n00006)
  );
  INV U2_ADDR_reg_0__n00007_987 (
    .I(U2_ADDR_reg[7]),
    .O(U2_ADDR_reg_0__n00007)
  );
  INV U2_ADDR_reg_0__n00008_988 (
    .I(CPLD_Reset_IBUF),
    .O(U2_ADDR_reg_0__n00008)
  );
  AND6 U2_ADDR_reg_0__n00009_989 (
    .I0(U2_ADDR_reg_0__n00003),
    .I1(U2_ADDR_reg_0__n00002),
    .I2(U2_ADDR_reg_0__n00004),
    .I3(U2_ADDR_reg_0__n00006),
    .I4(U2_ADDR_reg_0__n00005),
    .I5(U2_ADDR_reg_0__n00007),
    .O(U2_ADDR_reg_0__n00009)
  );
  OR2 U2_ADDR_reg_0__n000010_990 (
    .I0(U2_ADDR_reg_0__n00001),
    .I1(U2_ADDR_reg_0__n00009),
    .O(U2_ADDR_reg_0__n000010)
  );
  INV U2__n00031_991 (
    .I(U2__n0000),
    .O(U2__n00031)
  );
  INV U2_Mcompar_ADDR_in_Range_ALEB1_992 (
    .I(U2_ADDR_reg[4]),
    .O(U2_Mcompar_ADDR_in_Range_ALEB)
  );
  INV U2_Mcompar_ADDR_in_Range_ALEB2_993 (
    .I(U2_ADDR_reg[5]),
    .O(U2_Mcompar_ADDR_in_Range_ALEB1)
  );
  INV U2_Mcompar_ADDR_in_Range_ALEB3_994 (
    .I(U2_ADDR_reg[6]),
    .O(U2_Mcompar_ADDR_in_Range_ALEB2)
  );
  INV U2_Mcompar_ADDR_in_Range_ALEB4 (
    .I(U2_ADDR_reg[7]),
    .O(U2_Mcompar_ADDR_in_Range_ALEB3)
  );
  AND2 U2__n00051_995 (
    .I0(RD_IBUF),
    .I1(WR_IBUF),
    .O(U2__n00051)
  );
  INV U2__n00052_996 (
    .I(AS_IBUF),
    .O(U2__n00052)
  );
  AND2 U2__n00053_997 (
    .I0(U2_ASedge),
    .I1(U2__n00052),
    .O(U2__n00053)
  );
  AND2 U2_Enable_AD1_998 (
    .I0(U2_ADDR_in_Range),
    .I1(WR_IBUF),
    .O(U2_Enable_AD1)
  );
  INV U2_Enable_AD2_999 (
    .I(RD_IBUF),
    .O(U2_Enable_AD2)
  );
  INV U2_Mcompar__n0006_ALB1_1000 (
    .I(U2_ADDR_reg[4]),
    .O(U2_Mcompar__n0006_ALB)
  );
  INV U2_Mcompar__n0006_ALB2_1001 (
    .I(U2_ADDR_reg[5]),
    .O(U2_Mcompar__n0006_ALB1)
  );
  INV U2_Mcompar__n0006_ALB3_1002 (
    .I(U2_ADDR_reg[6]),
    .O(U2_Mcompar__n0006_ALB2)
  );
  INV U2_Mcompar__n0006_ALB4_1003 (
    .I(U2_ADDR_reg[7]),
    .O(U2_Mcompar__n0006_ALB3)
  );
  AND4 U2_Mcompar__n0006_ALB5_1004 (
    .I0(U2_ADDR_reg[2]),
    .I1(U2_ADDR_reg[3]),
    .I2(U2_ADDR_reg[0]),
    .I3(U2_ADDR_reg[1]),
    .O(U2_Mcompar__n0006_ALB4)
  );
  AND4 U2_Mcompar__n0006_ALB6_1005 (
    .I0(U2_Mcompar__n0006_ALB),
    .I1(U2_Mcompar__n0006_ALB1),
    .I2(U2_Mcompar__n0006_ALB2),
    .I3(U2_Mcompar__n0006_ALB3),
    .O(U2_Mcompar__n0006_ALB5)
  );
  INV U2_Mcompar__n0006_ALB7 (
    .I(U2_Mcompar__n0006_ALB4),
    .O(U2_Mcompar__n0006_ALB6)
  );
  AND2 U7_U3_Maddsub__n0002__n00031_1006 (
    .I0(U7_U3_Maddsub__n0002__n0030[1]),
    .I1(U7_U3_counterr[3]),
    .O(U7_U3_Maddsub__n0002__n0003)
  );
  INV U7_U3_Maddsub__n0002__n00032_1007 (
    .I(U7_U3_Maddsub__n0002__n0030[1]),
    .O(U7_U3_Maddsub__n0002__n00031)
  );
  INV U7_U3_Maddsub__n0002__n00033_1008 (
    .I(U7_U3_counterr[3]),
    .O(U7_U3_Maddsub__n0002__n00032)
  );
  AND2 U7_U3_Maddsub__n0002__n00034_1009 (
    .I0(U7_U3_Maddsub__n0002__n00031),
    .I1(U7_U3_Maddsub__n0002__n00032),
    .O(U7_U3_Maddsub__n0002__n00033)
  );
  INV U7_U3_Maddsub__n0002__n00035_1010 (
    .I(U7_U3_Maddsub__n0002__n00033),
    .O(U7_U3_Maddsub__n0002__n00034)
  );
  AND2 U7_U3_Maddsub__n0002__n00036 (
    .I0(U7_U3_Maddsub__n0002__n0030[0]),
    .I1(U7_U3_Maddsub__n0002__n00034),
    .O(U7_U3_Maddsub__n0002__n00035)
  );
  AND2 U7_U3__n00411_1011 (
    .I0(U7_SCLdetect),
    .I1(U7_Incdetect),
    .O(U7_U3__n00411)
  );
  INV U7_U3__n00412_1012 (
    .I(SCLreset_IBUF),
    .O(U7_U3__n00412)
  );
  INV U7_U3__n00413_1013 (
    .I(SCLinc_IBUF),
    .O(U7_U3__n00413)
  );
  AND2 U7_U3__n00414_1014 (
    .I0(U7_ResetDetect),
    .I1(U7_U3__n00413),
    .O(U7_U3__n00414)
  );
  INV U7_U3__n00415_1015 (
    .I(U7_U3__n00414),
    .O(U7_U3__n00415)
  );
  AND2 U7_U3__n00416_1016 (
    .I0(U7_U3__n00412),
    .I1(U7_U3__n00415),
    .O(U7_U3__n00416)
  );
  AND2 U7_U3_Maddsub__n0002__n00011_1017 (
    .I0(U7_U3_Maddsub__n0002__n0026[1]),
    .I1(U7_U3_counterr[1]),
    .O(U7_U3_Maddsub__n0002__n0001)
  );
  INV U7_U3_Maddsub__n0002__n00012_1018 (
    .I(U7_U3_Maddsub__n0002__n0026[1]),
    .O(U7_U3_Maddsub__n0002__n00011)
  );
  INV U7_U3_Maddsub__n0002__n00013_1019 (
    .I(U7_U3_counterr[1]),
    .O(U7_U3_Maddsub__n0002__n00012)
  );
  AND2 U7_U3_Maddsub__n0002__n00014_1020 (
    .I0(U7_U3_Maddsub__n0002__n00011),
    .I1(U7_U3_Maddsub__n0002__n00012),
    .O(U7_U3_Maddsub__n0002__n00013)
  );
  INV U7_U3_Maddsub__n0002__n00015_1021 (
    .I(U7_U3_Maddsub__n0002__n00013),
    .O(U7_U3_Maddsub__n0002__n00014)
  );
  AND2 U7_U3_Maddsub__n0002__n00016 (
    .I0(U7_U3_Maddsub__n0002__n0026[0]),
    .I1(U7_U3_Maddsub__n0002__n00014),
    .O(U7_U3_Maddsub__n0002__n00015)
  );
  INV U7_U3_Maddsub__n0002__n00041_1022 (
    .I(U7_U3_Maddsub__n0002__n0019),
    .O(U7_U3_Maddsub__n0002__n0004)
  );
  INV U7_U3_Maddsub__n0002__n00042_1023 (
    .I(U7_U3_Maddsub__n0002__n0018),
    .O(U7_U3_Maddsub__n0002__n00041)
  );
  INV U7_U3_Maddsub__n0002__n00043_1024 (
    .I(U7_U3_Maddsub__n0002__n0017),
    .O(U7_U3_Maddsub__n0002__n00042)
  );
  AND3 U7_U3_Maddsub__n0002__n00044 (
    .I0(U7_U3_Maddsub__n0002__n00041),
    .I1(U7_U3_Maddsub__n0002__n0004),
    .I2(U7_U3_Maddsub__n0002__n00042),
    .O(U7_U3_Maddsub__n0002__n00043)
  );
  AND2 U7_U3_Maddsub__n0002__n00021_1025 (
    .I0(U7_U3_Maddsub__n0002__n0028[1]),
    .I1(U7_U3_counterr[2]),
    .O(U7_U3_Maddsub__n0002__n0002)
  );
  INV U7_U3_Maddsub__n0002__n00022_1026 (
    .I(U7_U3_Maddsub__n0002__n0028[1]),
    .O(U7_U3_Maddsub__n0002__n00021)
  );
  INV U7_U3_Maddsub__n0002__n00023_1027 (
    .I(U7_U3_counterr[2]),
    .O(U7_U3_Maddsub__n0002__n00022)
  );
  AND2 U7_U3_Maddsub__n0002__n00024_1028 (
    .I0(U7_U3_Maddsub__n0002__n00021),
    .I1(U7_U3_Maddsub__n0002__n00022),
    .O(U7_U3_Maddsub__n0002__n00023)
  );
  INV U7_U3_Maddsub__n0002__n00025_1029 (
    .I(U7_U3_Maddsub__n0002__n00023),
    .O(U7_U3_Maddsub__n0002__n00024)
  );
  AND2 U7_U3_Maddsub__n0002__n00026 (
    .I0(U7_U3_Maddsub__n0002__n0028[0]),
    .I1(U7_U3_Maddsub__n0002__n00024),
    .O(U7_U3_Maddsub__n0002__n00025)
  );
  INV U7_U3__n00051_1030 (
    .I(U7_U3_counterr[1]),
    .O(U7_U3__n0005)
  );
  INV U7_U3__n00052_1031 (
    .I(U7_U3_counterr[0]),
    .O(U7_U3__n00051)
  );
  INV U7_U3__n00053_1032 (
    .I(U7_U3_counterr[2]),
    .O(U7_U3__n00052)
  );
  INV U7_U3__n00054_1033 (
    .I(U7_U3_counterr[4]),
    .O(U7_U3__n00053)
  );
  INV U7_U3__n00055_1034 (
    .I(U7_U3_counterr[3]),
    .O(U7_U3__n00054)
  );
  INV U7_U3__n00056 (
    .I(U7_U3_counterr[5]),
    .O(U7_U3__n00055)
  );
  INV U7_U3__n00421_1035 (
    .I(U7_SCLdetect),
    .O(U7_U3__n00421)
  );
  INV U7_U3__n00422_1036 (
    .I(SCLreset_IBUF),
    .O(U7_U3__n00422)
  );
  INV U7_U3__n00423_1037 (
    .I(SCLinc_IBUF),
    .O(U7_U3__n00423)
  );
  AND2 U7_U3__n00424_1038 (
    .I0(U7_Incdetect),
    .I1(U7_U3__n00421),
    .O(U7_U3__n00424)
  );
  AND2 U7_U3__n00425_1039 (
    .I0(U7_ResetDetect),
    .I1(U7_U3__n00423),
    .O(U7_U3__n00425)
  );
  INV U7_U3__n00426_1040 (
    .I(U7_U3__n00425),
    .O(U7_U3__n00426)
  );
  AND2 U7_U3__n00427_1041 (
    .I0(U7_U3__n00422),
    .I1(U7_U3__n00426),
    .O(U7_U3__n00427)
  );
  AND2 U7_U3_Maddsub__n0002__n00001_1042 (
    .I0(U7_U3__n0006),
    .I1(U7_U3_counterr[0]),
    .O(U7_U3_Maddsub__n0002__n0000)
  );
  INV U7_U3_Maddsub__n0002__n00002_1043 (
    .I(U7_U3__n0006),
    .O(U7_U3_Maddsub__n0002__n00001)
  );
  INV U7_U3_Maddsub__n0002__n00003_1044 (
    .I(U7_U3_counterr[0]),
    .O(U7_U3_Maddsub__n0002__n00002)
  );
  AND2 U7_U3_Maddsub__n0002__n00004_1045 (
    .I0(U7_U3_Maddsub__n0002__n00001),
    .I1(U7_U3_Maddsub__n0002__n00002),
    .O(U7_U3_Maddsub__n0002__n00003)
  );
  INV U7_U3_Maddsub__n0002__n00005_1046 (
    .I(U7_U3_Maddsub__n0002__n00003),
    .O(U7_U3_Maddsub__n0002__n00004)
  );
  AND2 U7_U3_Maddsub__n0002__n00006 (
    .I0(U7_U3_Maddsub__n0002__n0020),
    .I1(U7_U3_Maddsub__n0002__n00004),
    .O(U7_U3_Maddsub__n0002__n00005)
  );
  INV U7_U3__n0000_2_1_1047 (
    .I(NET1764),
    .O(U7_U3__n0000_2_1)
  );
  INV U7_U3__n0000_2_2_1048 (
    .I(U7_Incdetect),
    .O(U7_U3__n0000_2_2)
  );
  INV U7_U3__n0000_2_3_1049 (
    .I(U7_SCLdetect),
    .O(U7_U3__n0000_2_3)
  );
  INV U7_U3__n0000_2_4_1050 (
    .I(SCLreset_IBUF),
    .O(U7_U3__n0000_2_4)
  );
  AND2 U7_U3__n0000_2_5_1051 (
    .I0(U7_U3__n0006),
    .I1(U7_U3__n0000_2_1),
    .O(U7_U3__n0000_2_5)
  );
  AND3 U7_U3__n0000_2_6_1052 (
    .I0(U7_U3__n0000_2_3),
    .I1(U7_U3__n0000_2_2),
    .I2(U7_U3__n0000_2_4),
    .O(U7_U3__n0000_2_6)
  );
  OR2 U7_U3__n0000_2_7_1053 (
    .I0(U7_U3__n0042),
    .I1(U7_U3__n0000_2_5),
    .O(U7_U3__n0000_2_7)
  );
  OR2 U7_U3__n0000_2_8_1054 (
    .I0(U7_U3__n0041),
    .I1(U7_U3__n0000_2_6),
    .O(U7_U3__n0000_2_8)
  );
  AND2 U7_U3__n0000_2_9_1055 (
    .I0(U7_U3__n0002[2]),
    .I1(U7_U3__n0000_2_7),
    .O(U7_U3__n0000_2_9)
  );
  AND2 U7_U3__n0000_2_10_1056 (
    .I0(U7_U3_counterr[2]),
    .I1(U7_U3__n0000_2_8),
    .O(U7_U3__n0000_2_10)
  );
  INV U7_U3__n00061_1057 (
    .I(U7_Incdetect),
    .O(U7_U3__n00061)
  );
  INV U7_U3__n00062_1058 (
    .I(SCLreset_IBUF),
    .O(U7_U3__n00062)
  );
  AND2 U3__n00611_1059 (
    .I0(SA_4_IBUF),
    .I1(SystemEN_OBUF),
    .O(U3__n0061)
  );
  INV U3__n00612_1060 (
    .I(SA_8_IBUF),
    .O(U3__n00611)
  );
  INV U3__n00613_1061 (
    .I(SA_9_IBUF),
    .O(U3__n00612)
  );
  INV U3__n00614_1062 (
    .I(SA_10_IBUF),
    .O(U3__n00613)
  );
  INV U3__n00615_1063 (
    .I(SA_12_IBUF),
    .O(U3__n00614)
  );
  INV U3__n00616_1064 (
    .I(SA_11_IBUF),
    .O(U3__n00615)
  );
  INV U3__n00617_1065 (
    .I(SA_13_IBUF),
    .O(U3__n00616)
  );
  INV U3__n00618_1066 (
    .I(SA_14_IBUF),
    .O(U3__n00617)
  );
  INV U3__n00619_1067 (
    .I(SA_15_IBUF),
    .O(U3__n00618)
  );
  INV U3__n006110_1068 (
    .I(SystemEN_OBUF),
    .O(U3__n00619)
  );
  INV U3__n006111_1069 (
    .I(U2_ADDR_reg[4]),
    .O(U3__n006110)
  );
  AND2 U3__n006112_1070 (
    .I0(U3__n00611),
    .I1(U3__n00612),
    .O(U3__n006111)
  );
  AND4 U3__n006113_1071 (
    .I0(U3__n00613),
    .I1(U3__n00614),
    .I2(U3__n00615),
    .I3(U3__n00616),
    .O(U3__n006112)
  );
  AND2 U3__n006114_1072 (
    .I0(U3__n00617),
    .I1(U3__n00618),
    .O(U3__n006113)
  );
  AND2 U3__n006115_1073 (
    .I0(U3__n00619),
    .I1(U3__n006110),
    .O(U3__n006114)
  );
  AND3 U3__n006116_1074 (
    .I0(U3__n006111),
    .I1(U3__n0061),
    .I2(U3__n006112),
    .O(U3__n006115)
  );
  AND2 U3__n006117 (
    .I0(U3__n006115),
    .I1(U3__n006113),
    .O(U3__n006116)
  );
  INV U3__n00581_1075 (
    .I(SystemEN_OBUF),
    .O(U3__n0058)
  );
  AND2 U3__n00582_1076 (
    .I0(SA_5_IBUF),
    .I1(SystemEN_OBUF),
    .O(U3__n00581)
  );
  INV U3__n00583_1077 (
    .I(SA_8_IBUF),
    .O(U3__n00582)
  );
  INV U3__n00584_1078 (
    .I(SA_9_IBUF),
    .O(U3__n00583)
  );
  INV U3__n00585_1079 (
    .I(SA_10_IBUF),
    .O(U3__n00584)
  );
  INV U3__n00586_1080 (
    .I(SA_12_IBUF),
    .O(U3__n00585)
  );
  INV U3__n00587_1081 (
    .I(SA_11_IBUF),
    .O(U3__n00586)
  );
  INV U3__n00588_1082 (
    .I(SA_13_IBUF),
    .O(U3__n00587)
  );
  INV U3__n00589_1083 (
    .I(SA_14_IBUF),
    .O(U3__n00588)
  );
  INV U3__n005810_1084 (
    .I(SA_15_IBUF),
    .O(U3__n00589)
  );
  AND2 U3__n005811_1085 (
    .I0(U3__n0000[1]),
    .I1(U3__n0058),
    .O(U3__n005810)
  );
  AND2 U3__n005812_1086 (
    .I0(U3__n00582),
    .I1(U3__n00583),
    .O(U3__n005811)
  );
  AND4 U3__n005813_1087 (
    .I0(U3__n00584),
    .I1(U3__n00585),
    .I2(U3__n00586),
    .I3(U3__n00587),
    .O(U3__n005812)
  );
  AND2 U3__n005814_1088 (
    .I0(U3__n00588),
    .I1(U3__n00589),
    .O(U3__n005813)
  );
  AND3 U3__n005815_1089 (
    .I0(U3__n005811),
    .I1(U3__n00581),
    .I2(U3__n005812),
    .O(U3__n005814)
  );
  AND2 U3__n005816 (
    .I0(U3__n005814),
    .I1(U3__n005813),
    .O(U3__n005815)
  );
  INV U3__n00551_1090 (
    .I(SystemEN_OBUF),
    .O(U3__n0055)
  );
  AND2 U3__n00552_1091 (
    .I0(SA_6_IBUF),
    .I1(SystemEN_OBUF),
    .O(U3__n00551)
  );
  INV U3__n00553_1092 (
    .I(SA_8_IBUF),
    .O(U3__n00552)
  );
  INV U3__n00554_1093 (
    .I(SA_9_IBUF),
    .O(U3__n00553)
  );
  INV U3__n00555_1094 (
    .I(SA_10_IBUF),
    .O(U3__n00554)
  );
  INV U3__n00556_1095 (
    .I(SA_12_IBUF),
    .O(U3__n00555)
  );
  INV U3__n00557_1096 (
    .I(SA_11_IBUF),
    .O(U3__n00556)
  );
  INV U3__n00558_1097 (
    .I(SA_13_IBUF),
    .O(U3__n00557)
  );
  INV U3__n00559_1098 (
    .I(SA_14_IBUF),
    .O(U3__n00558)
  );
  INV U3__n005510_1099 (
    .I(SA_15_IBUF),
    .O(U3__n00559)
  );
  AND2 U3__n005511_1100 (
    .I0(U3__n0000[2]),
    .I1(U3__n0055),
    .O(U3__n005510)
  );
  AND2 U3__n005512_1101 (
    .I0(U3__n00552),
    .I1(U3__n00553),
    .O(U3__n005511)
  );
  AND4 U3__n005513_1102 (
    .I0(U3__n00554),
    .I1(U3__n00555),
    .I2(U3__n00556),
    .I3(U3__n00557),
    .O(U3__n005512)
  );
  AND2 U3__n005514_1103 (
    .I0(U3__n00558),
    .I1(U3__n00559),
    .O(U3__n005513)
  );
  AND3 U3__n005515_1104 (
    .I0(U3__n005511),
    .I1(U3__n00551),
    .I2(U3__n005512),
    .O(U3__n005514)
  );
  AND2 U3__n005516 (
    .I0(U3__n005514),
    .I1(U3__n005513),
    .O(U3__n005515)
  );
  INV U3__n00521_1105 (
    .I(SystemEN_OBUF),
    .O(U3__n0052)
  );
  AND2 U3__n00522_1106 (
    .I0(SA_7_IBUF),
    .I1(SystemEN_OBUF),
    .O(U3__n00521)
  );
  INV U3__n00523_1107 (
    .I(SA_8_IBUF),
    .O(U3__n00522)
  );
  INV U3__n00524_1108 (
    .I(SA_9_IBUF),
    .O(U3__n00523)
  );
  INV U3__n00525_1109 (
    .I(SA_10_IBUF),
    .O(U3__n00524)
  );
  INV U3__n00526_1110 (
    .I(SA_12_IBUF),
    .O(U3__n00525)
  );
  INV U3__n00527_1111 (
    .I(SA_11_IBUF),
    .O(U3__n00526)
  );
  INV U3__n00528_1112 (
    .I(SA_13_IBUF),
    .O(U3__n00527)
  );
  INV U3__n00529_1113 (
    .I(SA_14_IBUF),
    .O(U3__n00528)
  );
  INV U3__n005210_1114 (
    .I(SA_15_IBUF),
    .O(U3__n00529)
  );
  AND2 U3__n005211_1115 (
    .I0(U3__n0000[3]),
    .I1(U3__n0052),
    .O(U3__n005210)
  );
  AND2 U3__n005212_1116 (
    .I0(U3__n00522),
    .I1(U3__n00523),
    .O(U3__n005211)
  );
  AND4 U3__n005213_1117 (
    .I0(U3__n00524),
    .I1(U3__n00525),
    .I2(U3__n00526),
    .I3(U3__n00527),
    .O(U3__n005212)
  );
  AND2 U3__n005214_1118 (
    .I0(U3__n00528),
    .I1(U3__n00529),
    .O(U3__n005213)
  );
  AND3 U3__n005215_1119 (
    .I0(U3__n005211),
    .I1(U3__n00521),
    .I2(U3__n005212),
    .O(U3__n005214)
  );
  AND2 U3__n005216 (
    .I0(U3__n005214),
    .I1(U3__n005213),
    .O(U3__n005215)
  );
  INV U3__n00491_1120 (
    .I(SystemEN_OBUF),
    .O(U3__n0049)
  );
  AND2 U3__n00492_1121 (
    .I0(SA_0_IBUF),
    .I1(SystemEN_OBUF),
    .O(U3__n00491)
  );
  INV U3__n00493_1122 (
    .I(SA_8_IBUF),
    .O(U3__n00492)
  );
  INV U3__n00494_1123 (
    .I(SA_9_IBUF),
    .O(U3__n00493)
  );
  INV U3__n00495_1124 (
    .I(SA_10_IBUF),
    .O(U3__n00494)
  );
  INV U3__n00496_1125 (
    .I(SA_12_IBUF),
    .O(U3__n00495)
  );
  INV U3__n00497_1126 (
    .I(SA_11_IBUF),
    .O(U3__n00496)
  );
  INV U3__n00498_1127 (
    .I(SA_13_IBUF),
    .O(U3__n00497)
  );
  INV U3__n00499_1128 (
    .I(SA_14_IBUF),
    .O(U3__n00498)
  );
  INV U3__n004910_1129 (
    .I(SA_15_IBUF),
    .O(U3__n00499)
  );
  AND2 U3__n004911_1130 (
    .I0(U2_ADDR_reg[0]),
    .I1(U3__n0049),
    .O(U3__n004910)
  );
  AND2 U3__n004912_1131 (
    .I0(U3__n00492),
    .I1(U3__n00493),
    .O(U3__n004911)
  );
  AND4 U3__n004913_1132 (
    .I0(U3__n00494),
    .I1(U3__n00495),
    .I2(U3__n00496),
    .I3(U3__n00497),
    .O(U3__n004912)
  );
  AND2 U3__n004914_1133 (
    .I0(U3__n00498),
    .I1(U3__n00499),
    .O(U3__n004913)
  );
  AND3 U3__n004915_1134 (
    .I0(U3__n004911),
    .I1(U3__n00491),
    .I2(U3__n004912),
    .O(U3__n004914)
  );
  AND2 U3__n004916 (
    .I0(U3__n004914),
    .I1(U3__n004913),
    .O(U3__n004915)
  );
  INV U3__n00461_1135 (
    .I(SystemEN_OBUF),
    .O(U3__n0046)
  );
  AND2 U3__n00462_1136 (
    .I0(SA_1_IBUF),
    .I1(SystemEN_OBUF),
    .O(U3__n00461)
  );
  INV U3__n00463_1137 (
    .I(SA_8_IBUF),
    .O(U3__n00462)
  );
  INV U3__n00464_1138 (
    .I(SA_9_IBUF),
    .O(U3__n00463)
  );
  INV U3__n00465_1139 (
    .I(SA_10_IBUF),
    .O(U3__n00464)
  );
  INV U3__n00466_1140 (
    .I(SA_12_IBUF),
    .O(U3__n00465)
  );
  INV U3__n00467_1141 (
    .I(SA_11_IBUF),
    .O(U3__n00466)
  );
  INV U3__n00468_1142 (
    .I(SA_13_IBUF),
    .O(U3__n00467)
  );
  INV U3__n00469_1143 (
    .I(SA_14_IBUF),
    .O(U3__n00468)
  );
  INV U3__n004610_1144 (
    .I(SA_15_IBUF),
    .O(U3__n00469)
  );
  AND2 U3__n004611_1145 (
    .I0(U2_ADDR_reg[1]),
    .I1(U3__n0046),
    .O(U3__n004610)
  );
  AND2 U3__n004612_1146 (
    .I0(U3__n00462),
    .I1(U3__n00463),
    .O(U3__n004611)
  );
  AND4 U3__n004613_1147 (
    .I0(U3__n00464),
    .I1(U3__n00465),
    .I2(U3__n00466),
    .I3(U3__n00467),
    .O(U3__n004612)
  );
  AND2 U3__n004614_1148 (
    .I0(U3__n00468),
    .I1(U3__n00469),
    .O(U3__n004613)
  );
  AND3 U3__n004615_1149 (
    .I0(U3__n004611),
    .I1(U3__n00461),
    .I2(U3__n004612),
    .O(U3__n004614)
  );
  AND2 U3__n004616 (
    .I0(U3__n004614),
    .I1(U3__n004613),
    .O(U3__n004615)
  );
  INV U3__n00431_1150 (
    .I(SystemEN_OBUF),
    .O(U3__n0043)
  );
  AND2 U3__n00432_1151 (
    .I0(SA_2_IBUF),
    .I1(SystemEN_OBUF),
    .O(U3__n00431)
  );
  INV U3__n00433_1152 (
    .I(SA_8_IBUF),
    .O(U3__n00432)
  );
  INV U3__n00434_1153 (
    .I(SA_9_IBUF),
    .O(U3__n00433)
  );
  INV U3__n00435_1154 (
    .I(SA_10_IBUF),
    .O(U3__n00434)
  );
  INV U3__n00436_1155 (
    .I(SA_12_IBUF),
    .O(U3__n00435)
  );
  INV U3__n00437_1156 (
    .I(SA_11_IBUF),
    .O(U3__n00436)
  );
  INV U3__n00438_1157 (
    .I(SA_13_IBUF),
    .O(U3__n00437)
  );
  INV U3__n00439_1158 (
    .I(SA_14_IBUF),
    .O(U3__n00438)
  );
  INV U3__n004310_1159 (
    .I(SA_15_IBUF),
    .O(U3__n00439)
  );
  AND2 U3__n004311_1160 (
    .I0(U2_ADDR_reg[2]),
    .I1(U3__n0043),
    .O(U3__n004310)
  );
  AND2 U3__n004312_1161 (
    .I0(U3__n00432),
    .I1(U3__n00433),
    .O(U3__n004311)
  );
  AND4 U3__n004313_1162 (
    .I0(U3__n00434),
    .I1(U3__n00435),
    .I2(U3__n00436),
    .I3(U3__n00437),
    .O(U3__n004312)
  );
  AND2 U3__n004314_1163 (
    .I0(U3__n00438),
    .I1(U3__n00439),
    .O(U3__n004313)
  );
  AND3 U3__n004315_1164 (
    .I0(U3__n004311),
    .I1(U3__n00431),
    .I2(U3__n004312),
    .O(U3__n004314)
  );
  AND2 U3__n004316 (
    .I0(U3__n004314),
    .I1(U3__n004313),
    .O(U3__n004315)
  );
  INV U7_U3__n0000_3_1_1165 (
    .I(NET1764),
    .O(U7_U3__n0000_3_1)
  );
  INV U7_U3__n0000_3_2_1166 (
    .I(U7_U3_counterr[3]),
    .O(U7_U3__n0000_3_2)
  );
  INV U7_U3__n0000_3_3_1167 (
    .I(U7_SCLdetect),
    .O(U7_U3__n0000_3_3)
  );
  INV U7_U3__n0000_3_4_1168 (
    .I(U7_Incdetect),
    .O(U7_U3__n0000_3_4)
  );
  AND2 U7_U3__n0000_3_5_1169 (
    .I0(U7_U3__n0006),
    .I1(U7_U3__n0000_3_1),
    .O(U7_U3__n0000_3_5)
  );
  AND2 U7_U3__n0000_3_6_1170 (
    .I0(U7_U3__n0041),
    .I1(U7_U3__n0000_3_2),
    .O(U7_U3__n0000_3_6)
  );
  AND3 U7_U3__n0000_3_7_1171 (
    .I0(U7_U3__n0000_3_3),
    .I1(U7_U3_counterr[3]),
    .I2(U7_U3__n0000_3_4),
    .O(U7_U3__n0000_3_7)
  );
  OR2 U7_U3__n0000_3_8_1172 (
    .I0(U7_U3__n0042),
    .I1(U7_U3__n0000_3_5),
    .O(U7_U3__n0000_3_8)
  );
  OR2 U7_U3__n0000_3_9_1173 (
    .I0(U7_U3__n0000_3_6),
    .I1(U7_U3__n0000_3_7),
    .O(U7_U3__n0000_3_9)
  );
  AND2 U7_U3__n0000_3_10_1174 (
    .I0(U7_U3__n0002[3]),
    .I1(U7_U3__n0000_3_8),
    .O(U7_U3__n0000_3_10)
  );
  AND2 U3__n00281_1175 (
    .I0(UIOW_OBUF),
    .I1(U3__n0015),
    .O(U3__n00281)
  );
  INV U3__n00282_1176 (
    .I(UIOR_OBUF),
    .O(U3__n00282)
  );
  AND2 U7_U3__n0000_0_1_1177 (
    .I0(SCLreset_IBUF),
    .I1(SCLinc_IBUF),
    .O(U7_U3__n0000_0_1)
  );
  INV U7_U3__n0000_0_2_1178 (
    .I(NET1764),
    .O(U7_U3__n0000_0_2)
  );
  INV U7_U3__n0000_0_3_1179 (
    .I(U7_Incdetect),
    .O(U7_U3__n0000_0_3)
  );
  INV U7_U3__n0000_0_4_1180 (
    .I(U7_SCLdetect),
    .O(U7_U3__n0000_0_4)
  );
  INV U7_U3__n0000_0_5_1181 (
    .I(SCLreset_IBUF),
    .O(U7_U3__n0000_0_5)
  );
  AND2 U7_U3__n0000_0_6_1182 (
    .I0(U7_Incdetect),
    .I1(U7_ResetDetect),
    .O(U7_U3__n0000_0_6)
  );
  INV U7_U3__n0000_0_7_1183 (
    .I(SCLreset_IBUF),
    .O(U7_U3__n0000_0_7)
  );
  INV U7_U3__n0000_0_8_1184 (
    .I(SCLinc_IBUF),
    .O(U7_U3__n0000_0_8)
  );
  AND2 U7_U3__n0000_0_9_1185 (
    .I0(U7_U3__n0006),
    .I1(U7_U3__n0000_0_2),
    .O(U7_U3__n0000_0_9)
  );
  AND3 U7_U3__n0000_0_10_1186 (
    .I0(U7_U3__n0000_0_4),
    .I1(U7_U3__n0000_0_3),
    .I2(U7_U3__n0000_0_5),
    .O(U7_U3__n0000_0_10)
  );
  AND2 U7_U3__n0000_0_11_1187 (
    .I0(U7_U3__n0000_0_7),
    .I1(U7_U3__n0000_0_8),
    .O(U7_U3__n0000_0_11)
  );
  OR2 U7_U3__n0000_0_12_1188 (
    .I0(U7_U3__n0042),
    .I1(U7_U3__n0000_0_9),
    .O(U7_U3__n0000_0_12)
  );
  OR2 U7_U3__n0000_0_13_1189 (
    .I0(U7_U3__n0041),
    .I1(U7_U3__n0000_0_10),
    .O(U7_U3__n0000_0_13)
  );
  AND2 U7_U3__n0000_0_14_1190 (
    .I0(U7_U3__n0000_0_6),
    .I1(U7_U3__n0000_0_11),
    .O(U7_U3__n0000_0_14)
  );
  AND2 U7_U3__n0000_0_15_1191 (
    .I0(U7_U3__n0002[0]),
    .I1(U7_U3__n0000_0_12),
    .O(U7_U3__n0000_0_15)
  );
  AND2 U7_U3__n0000_0_16_1192 (
    .I0(U7_U3_counterr[0]),
    .I1(U7_U3__n0000_0_13),
    .O(U7_U3__n0000_0_16)
  );
  AND2 U7_U3__n0000_5_1_1193 (
    .I0(U7_U3__n0041),
    .I1(U7_U3__n0049[5]),
    .O(U7_U3__n0000_5_1)
  );
  INV U7_U3__n0000_5_2_1194 (
    .I(NET1764),
    .O(U7_U3__n0000_5_2)
  );
  INV U7_U3__n0000_5_3_1195 (
    .I(U7_SCLdetect),
    .O(U7_U3__n0000_5_3)
  );
  INV U7_U3__n0000_5_4_1196 (
    .I(U7_Incdetect),
    .O(U7_U3__n0000_5_4)
  );
  INV U7_U3__n0000_5_5_1197 (
    .I(SCLreset_IBUF),
    .O(U7_U3__n0000_5_5)
  );
  AND2 U7_U3__n0000_5_6_1198 (
    .I0(U7_U3__n0006),
    .I1(U7_U3__n0000_5_2),
    .O(U7_U3__n0000_5_6)
  );
  AND4 U7_U3__n0000_5_7_1199 (
    .I0(U7_U3_counterr[5]),
    .I1(U7_U3__n0000_5_3),
    .I2(U7_U3__n0000_5_4),
    .I3(U7_U3__n0000_5_5),
    .O(U7_U3__n0000_5_7)
  );
  OR2 U7_U3__n0000_5_8_1200 (
    .I0(U7_U3__n0042),
    .I1(U7_U3__n0000_5_6),
    .O(U7_U3__n0000_5_8)
  );
  AND2 U7_U3__n0000_5_9_1201 (
    .I0(U7_U3__n0002[5]),
    .I1(U7_U3__n0000_5_8),
    .O(U7_U3__n0000_5_9)
  );
  INV U3__n00401_1202 (
    .I(SystemEN_OBUF),
    .O(U3__n0040)
  );
  AND2 U3__n00402_1203 (
    .I0(SA_3_IBUF),
    .I1(SystemEN_OBUF),
    .O(U3__n00401)
  );
  INV U3__n00403_1204 (
    .I(SA_8_IBUF),
    .O(U3__n00402)
  );
  INV U3__n00404_1205 (
    .I(SA_9_IBUF),
    .O(U3__n00403)
  );
  INV U3__n00405_1206 (
    .I(SA_10_IBUF),
    .O(U3__n00404)
  );
  INV U3__n00406_1207 (
    .I(SA_12_IBUF),
    .O(U3__n00405)
  );
  INV U3__n00407_1208 (
    .I(SA_11_IBUF),
    .O(U3__n00406)
  );
  INV U3__n00408_1209 (
    .I(SA_13_IBUF),
    .O(U3__n00407)
  );
  INV U3__n00409_1210 (
    .I(SA_14_IBUF),
    .O(U3__n00408)
  );
  INV U3__n004010_1211 (
    .I(SA_15_IBUF),
    .O(U3__n00409)
  );
  AND2 U3__n004011_1212 (
    .I0(U2_ADDR_reg[3]),
    .I1(U3__n0040),
    .O(U3__n004010)
  );
  AND2 U3__n004012_1213 (
    .I0(U3__n00402),
    .I1(U3__n00403),
    .O(U3__n004011)
  );
  AND4 U3__n004013_1214 (
    .I0(U3__n00404),
    .I1(U3__n00405),
    .I2(U3__n00406),
    .I3(U3__n00407),
    .O(U3__n004012)
  );
  AND2 U3__n004014_1215 (
    .I0(U3__n00408),
    .I1(U3__n00409),
    .O(U3__n004013)
  );
  AND3 U3__n004015_1216 (
    .I0(U3__n004011),
    .I1(U3__n00401),
    .I2(U3__n004012),
    .O(U3__n004014)
  );
  AND2 U3__n004016 (
    .I0(U3__n004014),
    .I1(U3__n004013),
    .O(U3__n004015)
  );
  AND2 U3__n0004_6_1_1217 (
    .I0(SystemEN_OBUF),
    .I1(N8561),
    .O(U3__n0004_6_1)
  );
  INV U3__n0004_6_2_1218 (
    .I(SystemEN_OBUF),
    .O(U3__n0004_6_2)
  );
  INV U3__n0004_6_3_1219 (
    .I(UIOW_OBUF),
    .O(U3__n0004_6_3)
  );
  AND2 U3__n0004_6_4_1220 (
    .I0(N8545),
    .I1(U3__n0004_6_2),
    .O(U3__n0004_6_4)
  );
  OR2 U3__n0004_6_5_1221 (
    .I0(U3__n0004_6_1),
    .I1(U3__n0004_6_4),
    .O(U3__n0004_6_5)
  );
  INV U3__n00021_1222 (
    .I(AEN_IBUF),
    .O(U3__n00021)
  );
  INV U3__n00022_1223 (
    .I(IORD_IBUF),
    .O(U3__n00022)
  );
  INV U3__n00023_1224 (
    .I(SA_9_IBUF),
    .O(U3__n00023)
  );
  INV U3__n00024_1225 (
    .I(SA_8_IBUF),
    .O(U3__n00024)
  );
  INV U3__n00025_1226 (
    .I(SA_10_IBUF),
    .O(U3__n00025)
  );
  INV U3__n00026_1227 (
    .I(SA_12_IBUF),
    .O(U3__n00026)
  );
  INV U3__n00027_1228 (
    .I(SA_11_IBUF),
    .O(U3__n00027)
  );
  INV U3__n00028_1229 (
    .I(SA_13_IBUF),
    .O(U3__n00028)
  );
  INV U3__n00029_1230 (
    .I(SA_14_IBUF),
    .O(U3__n00029)
  );
  INV U3__n000210_1231 (
    .I(SA_15_IBUF),
    .O(U3__n000210)
  );
  AND8 U3__n000211_1232 (
    .I0(SystemEN_OBUF),
    .I1(U3__n00021),
    .I2(U3__n00022),
    .I3(U3__n00023),
    .I4(U3__n00024),
    .I5(U3__n00025),
    .I6(U3__n00026),
    .I7(U3__n00027),
    .O(U3__n000211)
  );
  AND3 U3__n000212_1233 (
    .I0(U3__n00029),
    .I1(U3__n00028),
    .I2(U3__n000210),
    .O(U3__n000212)
  );
  AND2 U3_Mmux_UIOR_Result1_1234 (
    .I0(SystemEN_OBUF),
    .I1(IORD_IBUF),
    .O(U3_Mmux_UIOR_Result)
  );
  INV U3_Mmux_UIOR_Result2_1235 (
    .I(SystemEN_OBUF),
    .O(U3_Mmux_UIOR_Result1)
  );
  INV U3_Mmux_UIOR_Result3_1236 (
    .I(U3__n0015),
    .O(U3_Mmux_UIOR_Result2)
  );
  AND2 U3_Mmux_UIOR_Result4 (
    .I0(RD_IBUF),
    .I1(U3_Mmux_UIOR_Result1),
    .O(U3_Mmux_UIOR_Result3)
  );
  AND2 U3_Mmux_UIOW_Result1_1237 (
    .I0(SystemEN_OBUF),
    .I1(IOWR_IBUF),
    .O(U3_Mmux_UIOW_Result)
  );
  INV U3_Mmux_UIOW_Result2_1238 (
    .I(SystemEN_OBUF),
    .O(U3_Mmux_UIOW_Result1)
  );
  INV U3_Mmux_UIOW_Result3_1239 (
    .I(U3__n0015),
    .O(U3_Mmux_UIOW_Result2)
  );
  AND2 U3_Mmux_UIOW_Result4 (
    .I0(WR_IBUF),
    .I1(U3_Mmux_UIOW_Result1),
    .O(U3_Mmux_UIOW_Result3)
  );
  INV U7_U3__n0000_1_1_1240 (
    .I(NET1764),
    .O(U7_U3__n0000_1_1)
  );
  INV U7_U3__n0000_1_2_1241 (
    .I(U7_Incdetect),
    .O(U7_U3__n0000_1_2)
  );
  INV U7_U3__n0000_1_3_1242 (
    .I(U7_SCLdetect),
    .O(U7_U3__n0000_1_3)
  );
  INV U7_U3__n0000_1_4_1243 (
    .I(SCLreset_IBUF),
    .O(U7_U3__n0000_1_4)
  );
  INV U7_U3__n0000_1_5_1244 (
    .I(SCLinc_IBUF),
    .O(U7_U3__n0000_1_5)
  );
  AND2 U7_U3__n0000_1_6_1245 (
    .I0(U7_U3__n0006),
    .I1(U7_U3__n0000_1_1),
    .O(U7_U3__n0000_1_6)
  );
  AND3 U7_U3__n0000_1_7_1246 (
    .I0(U7_U3__n0000_1_3),
    .I1(U7_U3__n0000_1_2),
    .I2(U7_U3__n0000_1_4),
    .O(U7_U3__n0000_1_7)
  );
  AND2 U7_U3__n0000_1_8_1247 (
    .I0(SCLreset_IBUF),
    .I1(U7_U3__n0000_1_5),
    .O(U7_U3__n0000_1_8)
  );
  OR2 U7_U3__n0000_1_9_1248 (
    .I0(U7_U3__n0042),
    .I1(U7_U3__n0000_1_6),
    .O(U7_U3__n0000_1_9)
  );
  OR2 U7_U3__n0000_1_10_1249 (
    .I0(U7_U3__n0041),
    .I1(U7_U3__n0000_1_7),
    .O(U7_U3__n0000_1_10)
  );
  AND2 U7_U3__n0000_1_11_1250 (
    .I0(U7_U3__n0002[1]),
    .I1(U7_U3__n0000_1_9),
    .O(U7_U3__n0000_1_11)
  );
  AND2 U7_U3__n0000_1_12_1251 (
    .I0(U7_U3_counterr[1]),
    .I1(U7_U3__n0000_1_10),
    .O(U7_U3__n0000_1_12)
  );
  AND2 U3__n0004_0_1_1252 (
    .I0(SystemEN_OBUF),
    .I1(N8549),
    .O(U3__n0004_0_1)
  );
  INV U3__n0004_0_2_1253 (
    .I(SystemEN_OBUF),
    .O(U3__n0004_0_2)
  );
  INV U3__n0004_0_3_1254 (
    .I(UIOW_OBUF),
    .O(U3__n0004_0_3)
  );
  AND2 U3__n0004_0_4_1255 (
    .I0(N8581),
    .I1(U3__n0004_0_2),
    .O(U3__n0004_0_4)
  );
  OR2 U3__n0004_0_5_1256 (
    .I0(U3__n0004_0_1),
    .I1(U3__n0004_0_4),
    .O(U3__n0004_0_5)
  );
  AND2 U3__n0004_1_1_1257 (
    .I0(SystemEN_OBUF),
    .I1(N8551),
    .O(U3__n0004_1_1)
  );
  INV U3__n0004_1_2_1258 (
    .I(SystemEN_OBUF),
    .O(U3__n0004_1_2)
  );
  INV U3__n0004_1_3_1259 (
    .I(UIOW_OBUF),
    .O(U3__n0004_1_3)
  );
  AND2 U3__n0004_1_4_1260 (
    .I0(N8585),
    .I1(U3__n0004_1_2),
    .O(U3__n0004_1_4)
  );
  OR2 U3__n0004_1_5_1261 (
    .I0(U3__n0004_1_1),
    .I1(U3__n0004_1_4),
    .O(U3__n0004_1_5)
  );
  AND2 U3__n0004_2_1_1262 (
    .I0(SystemEN_OBUF),
    .I1(N8553),
    .O(U3__n0004_2_1)
  );
  INV U3__n0004_2_2_1263 (
    .I(SystemEN_OBUF),
    .O(U3__n0004_2_2)
  );
  INV U3__n0004_2_3_1264 (
    .I(UIOW_OBUF),
    .O(U3__n0004_2_3)
  );
  AND2 U3__n0004_2_4_1265 (
    .I0(N8587),
    .I1(U3__n0004_2_2),
    .O(U3__n0004_2_4)
  );
  OR2 U3__n0004_2_5_1266 (
    .I0(U3__n0004_2_1),
    .I1(U3__n0004_2_4),
    .O(U3__n0004_2_5)
  );
  AND2 U3__n0004_3_1_1267 (
    .I0(SystemEN_OBUF),
    .I1(N8555),
    .O(U3__n0004_3_1)
  );
  INV U3__n0004_3_2_1268 (
    .I(SystemEN_OBUF),
    .O(U3__n0004_3_2)
  );
  INV U3__n0004_3_3_1269 (
    .I(UIOW_OBUF),
    .O(U3__n0004_3_3)
  );
  AND2 U3__n0004_3_4_1270 (
    .I0(N8589),
    .I1(U3__n0004_3_2),
    .O(U3__n0004_3_4)
  );
  OR2 U3__n0004_3_5_1271 (
    .I0(U3__n0004_3_1),
    .I1(U3__n0004_3_4),
    .O(U3__n0004_3_5)
  );
  AND2 U3__n0004_4_1_1272 (
    .I0(SystemEN_OBUF),
    .I1(N8557),
    .O(U3__n0004_4_1)
  );
  INV U3__n0004_4_2_1273 (
    .I(SystemEN_OBUF),
    .O(U3__n0004_4_2)
  );
  INV U3__n0004_4_3_1274 (
    .I(UIOW_OBUF),
    .O(U3__n0004_4_3)
  );
  AND2 U3__n0004_4_4_1275 (
    .I0(N8591),
    .I1(U3__n0004_4_2),
    .O(U3__n0004_4_4)
  );
  OR2 U3__n0004_4_5_1276 (
    .I0(U3__n0004_4_1),
    .I1(U3__n0004_4_4),
    .O(U3__n0004_4_5)
  );
  AND2 U3__n0004_5_1_1277 (
    .I0(SystemEN_OBUF),
    .I1(N8559),
    .O(U3__n0004_5_1)
  );
  INV U3__n0004_5_2_1278 (
    .I(SystemEN_OBUF),
    .O(U3__n0004_5_2)
  );
  INV U3__n0004_5_3_1279 (
    .I(UIOW_OBUF),
    .O(U3__n0004_5_3)
  );
  AND2 U3__n0004_5_4_1280 (
    .I0(N8543),
    .I1(U3__n0004_5_2),
    .O(U3__n0004_5_4)
  );
  OR2 U3__n0004_5_5_1281 (
    .I0(U3__n0004_5_1),
    .I1(U3__n0004_5_4),
    .O(U3__n0004_5_5)
  );
  AND2 U7_U3__n0000_4_1_1282 (
    .I0(U7_U3__n0041),
    .I1(U7_U3__n0049[4]),
    .O(U7_U3__n0000_4_1)
  );
  INV U7_U3__n0000_4_2_1283 (
    .I(NET1764),
    .O(U7_U3__n0000_4_2)
  );
  INV U7_U3__n0000_4_3_1284 (
    .I(U7_SCLdetect),
    .O(U7_U3__n0000_4_3)
  );
  INV U7_U3__n0000_4_4_1285 (
    .I(U7_Incdetect),
    .O(U7_U3__n0000_4_4)
  );
  INV U7_U3__n0000_4_5_1286 (
    .I(SCLreset_IBUF),
    .O(U7_U3__n0000_4_5)
  );
  AND2 U7_U3__n0000_4_6_1287 (
    .I0(U7_U3__n0006),
    .I1(U7_U3__n0000_4_2),
    .O(U7_U3__n0000_4_6)
  );
  AND4 U7_U3__n0000_4_7_1288 (
    .I0(U7_U3_counterr[4]),
    .I1(U7_U3__n0000_4_3),
    .I2(U7_U3__n0000_4_4),
    .I3(U7_U3__n0000_4_5),
    .O(U7_U3__n0000_4_7)
  );
  OR2 U7_U3__n0000_4_8_1289 (
    .I0(U7_U3__n0042),
    .I1(U7_U3__n0000_4_6),
    .O(U7_U3__n0000_4_8)
  );
  AND2 U7_U3__n0000_4_9_1290 (
    .I0(U7_U3__n0002[4]),
    .I1(U7_U3__n0000_4_8),
    .O(U7_U3__n0000_4_9)
  );
  AND2 U3__n0004_7_1_1291 (
    .I0(SystemEN_OBUF),
    .I1(N8563),
    .O(U3__n0004_7_1)
  );
  INV U3__n0004_7_2_1292 (
    .I(SystemEN_OBUF),
    .O(U3__n0004_7_2)
  );
  INV U3__n0004_7_3_1293 (
    .I(UIOW_OBUF),
    .O(U3__n0004_7_3)
  );
  AND2 U3__n0004_7_4_1294 (
    .I0(N8547),
    .I1(U3__n0004_7_2),
    .O(U3__n0004_7_4)
  );
  OR2 U3__n0004_7_5_1295 (
    .I0(U3__n0004_7_1),
    .I1(U3__n0004_7_4),
    .O(U3__n0004_7_5)
  );
  INV U3__n00031_1296 (
    .I(UIOR_OBUF),
    .O(U3__n00031)
  );
  INV U3__n00032_1297 (
    .I(SystemEN_OBUF),
    .O(U3__n00032)
  );
  INV U3__n00011_1298 (
    .I(UINT_IBUF),
    .O(U3__n00011)
  );
  IBUF MCLK_IBUF_1299 (
    .I(MCLK),
    .O(MCLK_IBUF)
  );
  IBUF AS_IBUF_1300 (
    .I(AS),
    .O(AS_IBUF)
  );
  IBUF AM2Status_IBUF_1301 (
    .I(AM2Status),
    .O(AM2Status_IBUF)
  );
  IBUF IOWR_IBUF_1302 (
    .I(IOWR),
    .O(IOWR_IBUF)
  );
  IBUF AM1Status_IBUF_1303 (
    .I(AM1Status),
    .O(AM1Status_IBUF)
  );
  IBUF AM0Status_IBUF_1304 (
    .I(AM0Status),
    .O(AM0Status_IBUF)
  );
  IBUF SystemStatus_IBUF_1305 (
    .I(SystemStatus),
    .O(SystemStatus_IBUF)
  );
  IBUF ExternalStatus_IBUF_1306 (
    .I(ExternalStatus),
    .O(ExternalStatus_IBUF)
  );
  IBUF ModemStatus_IBUF_1307 (
    .I(ModemStatus),
    .O(ModemStatus_IBUF)
  );
  IBUF RD_IBUF_1308 (
    .I(RD),
    .O(RD_IBUF)
  );
  IBUF AEN_IBUF_1309 (
    .I(AEN),
    .O(AEN_IBUF)
  );
  IBUF WR_IBUF_1310 (
    .I(WR),
    .O(WR_IBUF)
  );
  IBUF CameraStatus_IBUF_1311 (
    .I(CameraStatus),
    .O(CameraStatus_IBUF)
  );
  IBUF SCLreset_IBUF_1312 (
    .I(SCLreset),
    .O(SCLreset_IBUF)
  );
  IBUF CPLD_Reset_IBUF_1313 (
    .I(CPLD_Reset),
    .O(CPLD_Reset_IBUF)
  );
  IBUF SCLinc_IBUF_1314 (
    .I(SCLinc),
    .O(SCLinc_IBUF)
  );
  IBUF UINT_IBUF_1315 (
    .I(UINT),
    .O(UINT_IBUF)
  );
  IBUF IORD_IBUF_1316 (
    .I(IORD),
    .O(IORD_IBUF)
  );
  IBUF SA_15_IBUF_1317 (
    .I(SA[15]),
    .O(SA_15_IBUF)
  );
  IBUF SA_14_IBUF_1318 (
    .I(SA[14]),
    .O(SA_14_IBUF)
  );
  IBUF SA_13_IBUF_1319 (
    .I(SA[13]),
    .O(SA_13_IBUF)
  );
  IBUF SA_12_IBUF_1320 (
    .I(SA[12]),
    .O(SA_12_IBUF)
  );
  IBUF SA_11_IBUF_1321 (
    .I(SA[11]),
    .O(SA_11_IBUF)
  );
  IBUF SA_10_IBUF_1322 (
    .I(SA[10]),
    .O(SA_10_IBUF)
  );
  IBUF SA_9_IBUF_1323 (
    .I(SA[9]),
    .O(SA_9_IBUF)
  );
  IBUF SA_8_IBUF_1324 (
    .I(SA[8]),
    .O(SA_8_IBUF)
  );
  IBUF SA_7_IBUF_1325 (
    .I(SA[7]),
    .O(SA_7_IBUF)
  );
  IBUF SA_6_IBUF_1326 (
    .I(SA[6]),
    .O(SA_6_IBUF)
  );
  IBUF SA_5_IBUF_1327 (
    .I(SA[5]),
    .O(SA_5_IBUF)
  );
  IBUF SA_4_IBUF_1328 (
    .I(SA[4]),
    .O(SA_4_IBUF)
  );
  IBUF SA_3_IBUF_1329 (
    .I(SA[3]),
    .O(SA_3_IBUF)
  );
  IBUF SA_2_IBUF_1330 (
    .I(SA[2]),
    .O(SA_2_IBUF)
  );
  IBUF SA_1_IBUF_1331 (
    .I(SA[1]),
    .O(SA_1_IBUF)
  );
  IBUF SA_0_IBUF_1332 (
    .I(SA[0]),
    .O(SA_0_IBUF)
  );
  OBUF UIOW_OBUF_1333 (
    .I(UIOW_OBUF),
    .O(UIOW)
  );
  OBUF ModemEN_OBUF_1334 (
    .I(ModemEN_OBUF),
    .O(ModemEN)
  );
  OBUF AM2EN_OBUF_1335 (
    .I(AM2EN_OBUF),
    .O(AM2EN)
  );
  OBUF LOOPcon0_OBUF_1336 (
    .I(LOOPcon0_OBUF),
    .O(LOOPcon0)
  );
  OBUF LOOPcon1_OBUF_1337 (
    .I(LOOPcon1_OBUF),
    .O(LOOPcon1)
  );
  OBUF LOOPcon2_OBUF_1338 (
    .I(LOOPcon2_OBUF),
    .O(LOOPcon2)
  );
  OBUF UCS_OBUF_1339 (
    .I(UCS_OBUF),
    .O(UCS)
  );
  OBUF CONmodem_OBUF_1340 (
    .I(CONmodem_OBUF),
    .O(CONmodem)
  );
  OBUF CameraEN_OBUF_1341 (
    .I(CameraEN_OBUF),
    .O(CameraEN)
  );
  OBUF LOOPmodem_OBUF_1342 (
    .I(LOOPmodem_OBUF),
    .O(LOOPmodem)
  );
  OBUF ExternalEN_OBUF_1343 (
    .I(ExternalEN_OBUF),
    .O(ExternalEN)
  );
  OBUF CONextr_OBUF_1344 (
    .I(CONextr_OBUF),
    .O(CONextr)
  );
  OBUF DwarfEN_OBUF_1345 (
    .I(DwarfEN_OBUF),
    .O(DwarfEN)
  );
  OBUF AM0EN_OBUF_1346 (
    .I(AM0EN_OBUF),
    .O(AM0EN)
  );
  OBUF CONcon0_OBUF_1347 (
    .I(CONcon0_OBUF),
    .O(CONcon0)
  );
  OBUF CONcon1_OBUF_1348 (
    .I(CONcon1_OBUF),
    .O(CONcon1)
  );
  OBUF CONcon2_OBUF_1349 (
    .I(CONcon2_OBUF),
    .O(CONcon2)
  );
  OBUF LOOPextr_OBUF_1350 (
    .I(LOOPextr_OBUF),
    .O(LOOPextr)
  );
  OBUF SystemEN_OBUF_1351 (
    .I(SystemEN_OBUF),
    .O(SystemEN)
  );
  OBUF AM1EN_OBUF_1352 (
    .I(AM1EN_OBUF),
    .O(AM1EN)
  );
  OBUF INT_OBUF_1353 (
    .I(INT_OBUF),
    .O(INT)
  );
  OBUF UIOR_OBUF_1354 (
    .I(UIOR_OBUF),
    .O(UIOR)
  );
  OBUF UAD_7_OBUF_1355 (
    .I(UAD_7_OBUF),
    .O(UAD[7])
  );
  OBUF UAD_6_OBUF_1356 (
    .I(UAD_6_OBUF),
    .O(UAD[6])
  );
  OBUF UAD_5_OBUF_1357 (
    .I(UAD_5_OBUF),
    .O(UAD[5])
  );
  OBUF UAD_4_OBUF_1358 (
    .I(UAD_4_OBUF),
    .O(UAD[4])
  );
  OBUF UAD_3_OBUF_1359 (
    .I(UAD_3_OBUF),
    .O(UAD[3])
  );
  OBUF UAD_2_OBUF_1360 (
    .I(UAD_2_OBUF),
    .O(UAD[2])
  );
  OBUF UAD_1_OBUF_1361 (
    .I(UAD_1_OBUF),
    .O(UAD[1])
  );
  OBUF UAD_0_OBUF_1362 (
    .I(UAD_0_OBUF),
    .O(UAD[0])
  );
  OBUF EN_7_OBUF_1363 (
    .I(EN_7_OBUF),
    .O(EN[7])
  );
  OBUF EN_6_OBUF_1364 (
    .I(EN_6_OBUF),
    .O(EN[6])
  );
  OBUF EN_5_OBUF_1365 (
    .I(EN_5_OBUF),
    .O(EN[5])
  );
  OBUF EN_4_OBUF_1366 (
    .I(EN_4_OBUF),
    .O(EN[4])
  );
  OBUF EN_3_OBUF_1367 (
    .I(EN_3_OBUF),
    .O(EN[3])
  );
  OBUF EN_2_OBUF_1368 (
    .I(EN_2_OBUF),
    .O(EN[2])
  );
  OBUF EN_1_OBUF_1369 (
    .I(EN_1_OBUF),
    .O(EN[1])
  );
  OBUF EN_0_OBUF_1370 (
    .I(EN_0_OBUF),
    .O(EN[0])
  );
  OBUF PD_7_OBUF_1371 (
    .I(PD_7_OBUF),
    .O(PD[7])
  );
  OBUF PD_6_OBUF_1372 (
    .I(PD_6_OBUF),
    .O(PD[6])
  );
  OBUF PD_5_OBUF_1373 (
    .I(PD_5_OBUF),
    .O(PD[5])
  );
  OBUF PD_4_OBUF_1374 (
    .I(PD_4_OBUF),
    .O(PD[4])
  );
  OBUF PD_3_OBUF_1375 (
    .I(PD_3_OBUF),
    .O(PD[3])
  );
  OBUF PD_2_OBUF_1376 (
    .I(PD_2_OBUF),
    .O(PD[2])
  );
  OBUF PD_1_OBUF_1377 (
    .I(PD_1_OBUF),
    .O(PD[1])
  );
  OBUF PD_0_OBUF_1378 (
    .I(PD_0_OBUF),
    .O(PD[0])
  );
endmodule