(---------------------------------------------------------------------)
(                                                                     )
(    Allegro Netrev Import Logic                                      )
(                                                                     )
(    Drawing          : 3g_powerSupplyProto.brd                       )
(    Software Version : 16.6S040                                      )
(    Date/Time        : Tue Dec 30 07:29:59 2014                      )
(                                                                     )
(---------------------------------------------------------------------)


------ Directives ------------

Ripup etch:                  No
Ripup delete first segment:  No
Ripup retain bondwire:       No
Ripup symbols:               Always
Missing symbol has error:    No
DRC update:                  Yes
Schematic directory:         '.'
Design Directory:            '.'
Old design name:             'X:/ESP/G3-ESP/Project.Drawings/EE.Drawings/power supply/layout/allegro/3g_powerSupplyProto.brd'
New design name:             'X:/ESP/G3-ESP/Project.Drawings/EE.Drawings/power supply/layout/allegro/3g_powerSupplyProto.brd'

CmdLine: netrev -$ -i . -y 1 -q netrev_constraint_report.xml X:/ESP/G3-ESP/Project.Drawings/EE.Drawings/power supply/layout/allegro/#Taaaaac08152.tmp

------ Preparing to read pst files ------

Starting to read ./pstchip.dat 
   Finished reading ./pstchip.dat (00:00:00.06)
Starting to read ./pstxprt.dat 
   Finished reading ./pstxprt.dat (00:00:00.00)
Starting to read ./pstxnet.dat 
   Finished reading ./pstxnet.dat (00:00:00.00)

------ Oversights/Warnings/Errors ------


#1   WARNING(SPMHNI-192): Device/Symbol check warning detected. [help]

WARNING(SPMHNI-194): Symbol 'SOP50P490X100-13_17L30T175X294N' used by RefDes U2 for device 'LTC3630AXMSE_SOP50P490X100-13_1' not found in PSMPATH or must be "dbdoctor"ed.

------ Library Paths ------
MODULEPATH =  . 
           C:/Cadence/SPB_16.6/share/local/pcb/modules 

PSMPATH =  . 
           //WATER/Allegro_Library/Symbols 
           //WATER/Allegro_Library/FORMAT 
           //WATER/Allegro_Library/Pads 
           J:/PCB_Layout/Layout_Libraries/LIBRARIES/SYMBOLS_2009 

PADPATH =  . 
           //WATER/Allegro_Library/Pads 
           J:/PCB_Layout/Layout_Libraries/LIBRARIES/CNC_PAD-LIBRARY/ 
           J:/PCB_Layout/Layout_Libraries/LIBRARIES/PADSTACKS_2009 


------ Summary Statistics ------


netrev run on Dec 30 7:29:59 2014
   DESIGN NAME : 'G3LOGICPOWER'
   PACKAGING ON Oct 15 2014 05:53:32

   COMPILE 'logic'
   CHECK_PIN_NAMES OFF
   CROSS_REFERENCE OFF
   FEEDBACK OFF
   INCREMENTAL OFF
   INTERFACE_TYPE PHYSICAL
   MAX_ERRORS 500
   MERGE_MINIMUM 5
   NET_NAME_CHARS '#%&()*+-./:=>?@[]^_`|'
   NET_NAME_LENGTH 24
   OVERSIGHTS ON
   REPLACE_CHECK OFF
   SINGLE_NODE_NETS ON
   SPLIT_MINIMUM 0
   SUPPRESS   20
   WARNINGS ON

 No error detected
 No oversight detected
  1 warnings detected

cpu time      0:02:54
elapsed time  0:00:02