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ADSP-BF537 EZ-KIT Lite Cache example

Analog Devices, Inc.
DSP Division
Three Technology Way
Norwood, MA 02062

Date Created:	11/21/05

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This directory contains an example of the ADSP-BF537 cache capability.

This project allows the L1 memory to be configured as instruction and/or data cache based 
on the #defines in cache_init.h

The project will configure the L1 memory and then do a performance analysis (cycle count) on the my_program 
subroutine in myprogram.asm.

In this example myprogram.asm contains a 2D-convolution routine.


Files contained in this directory:


Cache_Example.dpj		VisualDSP++ project file

main.asm			assembly file for calling all setup subroutines
cacheinit.asm			assembly file for configuring L1 memory as cache 
myprogram.asm			assembly file for performance analysis -contain 2d conv routine.

cache_init.h			header to define cache initialization - data and/or instruction

heaptab.c			Generated startup code
basiccrt.s			Generated runtime code, with Cache disabled

Cache_Example.ldf		linker description file customized for 4x1MB SDRAM pages

readme.txt			this project description file
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CONTENTS

I.	FUNCTIONAL DESCRIPTION
II.	IMPLEMENTATION DESCRIPTION
III.	OPERATION DESCRIPTION


I.    FUNCTIONAL DESCRIPTION

This project demonstrates how to configure the L1 memory for instruction and/or data cache.  
After doing the cache initialization, the cycle counters are enabled and cleared to zero in order to perform
a performance analysis on my_program.  my_program is a routine that runs out of SDRAM and accesses data that 
is also located in SDRAM.


II.   IMPLEMENTATION DESCRIPTION

The main file calls:

1. An init function that configures L1 Memory as cache.
2. A function that will run out of SDRAM.



III.  OPERATION DESCRIPTION

- Open the project "Cache_example.dpj" in the VisualDSP Integrated Development Environment (IDDE).
- Under the "Project" tab, select "Build Project" (program is then loaded automatically into DSP).

- Place a breakpoint at the following location: 	

"end:idle;" in main.asm


- Select "Run" from the "Debug" tab on the menu bar of VisualDSP++.
- When the processor hits the breakpoint, 

Select  Register->Core->Data Register File from the VisualDSP++ menus.
The number of cycles it took to run my_program will be reflected in r0 (low word) and r1 (high word).

This project has instruction and data cache enabled (see cache_init.h), so the expected cycle counts
are approximately r1=0x0 and r0=0x2818.  Cycle counts may vary slightly due to core clock and system clock
synchronization.

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Note: This project contains code and data that is located in SDRAM.  When using the USB debugger or an Emulator, SDRAM 
will automatically be initialized if the option "Use XML reset values" is checked in Settings -> Target Options.  
If you're booting in this application you must include an INIT.dxe file in the Loader property page to pre-initialize the 
SDRAM before dowonloading your code/data to SDRAM memory.