/* MANAGED-BY-SYSTEM-BUILDER                                    */

/*
** CPLB table definitions generated on Mar 30, 2006 at 11:13:19.
**
** Copyright (C) 2000-2006 Analog Devices Inc., All Rights Reserved.
**
** This file is generated automatically based upon the options selected
** in the LDF Wizard. Changes to the LDF configuration should be made by 
** changing the appropriate options rather than editing this file. 
**
** Configuration:-
**     crt_doj:                                .\Debug\TalkThrough_3_2_basiccrt.doj
**     processor:                              ADSP-BF537
**     si_revision:                            automatic
**     cplb_init_cplb_ctrl:                    127
**     cplb_init_dcache_ctrl:                  dcache_wb
**     cplb_init_cplb_src_file:                C:\CVS\Stage\VisualDSP_4.5\Stage\Blackfin\Examples\ADSP-BF537 EZ-KIT Lite\Getting Started Examples\Part_3_2\TalkThrough_3_2_cplbtab.c
**     cplb_init_cplb_obj_file:                .\Debug\TalkThrough_3_2_cplbtab.doj
**     using_cplusplus:                        true
**     mem_init:                               false
**     use_vdk:                                true
**     use_eh:                                 true
**     use_argv:                               false
**     user_heap_src_file:                     C:\CVS\Stage\VisualDSP_4.5\Stage\Blackfin\Examples\ADSP-BF537 EZ-KIT Lite\Getting Started Examples\Part_3_2\TalkThrough_3_2_heaptab.c
**     libraries_use_stdlib:                   true
**     libraries_use_fileio_libs:              false
**     libraries_use_ieeefp_emulation_libs:    false
**     libraries_use_eh_enabled_libs:          false
**     system_heap:                            L3
**     system_heap_min_size:                   2M
**     system_stack:                           SCRATCHPAD
**     system_stack_min_size:                  1K
**     use_sdram:                              true
**     use_sdram_size:                         64M
**     use_sdram_partitioned:                  default
**
*/

/////////////////////////////////////////////////////////////////
// cplbs_in_write_back

#define CACHE_MEM_MODE CPLB_DDOCACHE_WB


/////////////////////////////////////////////////////////////////
// cplb_header

#include <sys/platform.h>
#include <cplbtab.h>

#pragma section("cplb_data")

cplb_entry dcplbs_table[] = {



/*$VDSG<customisable-data-cplb-table>                           */
/* This code is preserved if the CPLB tables are re-generated.  */


   // L1 Data B
   {0xFF900000, (PAGE_SIZE_1MB | CPLB_D_PAGE_MGMT | CPLB_WT)}, 

   // L1 Data A
   {0xFF800000, (PAGE_SIZE_1MB | CPLB_D_PAGE_MGMT | CPLB_WT)}, 

   // Async Memory Bank 2 (Second)
   // Async Memory Bank 1 (Prim B)
   // Async Memory Bank 0 (Prim A)
   {0x20200000, (PAGE_SIZE_1MB | CACHE_MEM_MODE)}, 
   {0x20100000, (PAGE_SIZE_1MB | CACHE_MEM_MODE)}, 
   {0x20000000, (PAGE_SIZE_1MB | CACHE_MEM_MODE)}, 
   
   // CPLBs covering 64MB
   {0x00000000, (PAGE_SIZE_4MB | CACHE_MEM_MODE)},
   {0x00400000, (PAGE_SIZE_4MB | CACHE_MEM_MODE)},
   {0x00800000, (PAGE_SIZE_4MB | CACHE_MEM_MODE)},
   {0x00c00000, (PAGE_SIZE_4MB | CACHE_MEM_MODE)},
   {0x01000000, (PAGE_SIZE_4MB | CACHE_MEM_MODE)},
   {0x01400000, (PAGE_SIZE_4MB | CACHE_MEM_MODE)},
   {0x01800000, (PAGE_SIZE_4MB | CACHE_MEM_MODE)},
   {0x01c00000, (PAGE_SIZE_4MB | CACHE_MEM_MODE)},
   {0x02000000, (PAGE_SIZE_4MB | CACHE_MEM_MODE)},
   {0x02400000, (PAGE_SIZE_4MB | CACHE_MEM_MODE)},
   {0x02800000, (PAGE_SIZE_4MB | CACHE_MEM_MODE)},
   {0x02c00000, (PAGE_SIZE_4MB | CACHE_MEM_MODE)},
   {0x03000000, (PAGE_SIZE_4MB | CACHE_MEM_MODE)},
   {0x03400000, (PAGE_SIZE_4MB | CACHE_MEM_MODE)},
   {0x03800000, (PAGE_SIZE_4MB | CACHE_MEM_MODE)},
   {0x03c00000, (PAGE_SIZE_4MB | CACHE_MEM_MODE)},

   // Async Memory Bank 3
   {0x20300000, (PAGE_SIZE_1MB | CACHE_MEM_MODE)}, 

   // end of section - termination
   {0xffffffff, 0}, 
/*$VDSG<customisable-data-cplb-table>                           */

/////////////////////////////////////////////////////////////////
// cplb_body

}; /* dcplbs_table */

cplb_entry icplbs_table[] = {



/*$VDSG<customisable-instr-cplb-table>                          */
/* This code is preserved if the CPLB tables are re-generated.  */


   // L1 Code
   {0xFFA00000, (PAGE_SIZE_1MB | CPLB_I_PAGE_MGMT)}, 

   // Async Memory Bank 2 (Secnd)
   // Async Memory Bank 1 (Prim B)
   // Async Memory Bank 0 (Prim A)
   {0x20200000, (PAGE_SIZE_1MB | CPLB_INOCACHE)}, 
   {0x20100000, (PAGE_SIZE_1MB | CPLB_IDOCACHE)}, 
   {0x20000000, (PAGE_SIZE_1MB | CPLB_IDOCACHE)}, 
   
   // CPLBs covering 64MB
   {0x00000000, (PAGE_SIZE_4MB | CPLB_IDOCACHE)},
   {0x00400000, (PAGE_SIZE_4MB | CPLB_IDOCACHE)},
   {0x00800000, (PAGE_SIZE_4MB | CPLB_IDOCACHE)},
   {0x00c00000, (PAGE_SIZE_4MB | CPLB_IDOCACHE)},
   {0x01000000, (PAGE_SIZE_4MB | CPLB_IDOCACHE)},
   {0x01400000, (PAGE_SIZE_4MB | CPLB_IDOCACHE)},
   {0x01800000, (PAGE_SIZE_4MB | CPLB_IDOCACHE)},
   {0x01c00000, (PAGE_SIZE_4MB | CPLB_IDOCACHE)},
   {0x02000000, (PAGE_SIZE_4MB | CPLB_IDOCACHE)},
   {0x02400000, (PAGE_SIZE_4MB | CPLB_IDOCACHE)},
   {0x02800000, (PAGE_SIZE_4MB | CPLB_IDOCACHE)},
   {0x02c00000, (PAGE_SIZE_4MB | CPLB_IDOCACHE)},
   {0x03000000, (PAGE_SIZE_4MB | CPLB_IDOCACHE)},
   {0x03400000, (PAGE_SIZE_4MB | CPLB_IDOCACHE)},
   {0x03800000, (PAGE_SIZE_4MB | CPLB_IDOCACHE)},
   {0x03c00000, (PAGE_SIZE_4MB | CPLB_IDOCACHE)},

   // Async Memory Bank 3 
   {0x20300000, (PAGE_SIZE_1MB | CPLB_IDOCACHE)}, 

   // end of section - termination
   {0xffffffff, 0}, 
/*$VDSG<customisable-instr-cplb-table>                          */

/////////////////////////////////////////////////////////////////
// cplb_footer

}; /* icplbs_table */