/*****************************************************************************
Copyright(c) 2005 Analog Devices, Inc.  All Rights Reserved. This software is 
proprietary and confidential to Analog Devices, Inc. and its licensors.
******************************************************************************

$RCSfile: JPEGImageEdgeDetection_cplb_tables.c,v $
$Revision: 1.1 $
$Date: 2007/05/22 18:37:56 $

Project:	BlackfinSDK (Edge Detection on JPEG Image)
Title:		cplb_tables
Author(s):	dwu
Revised by: bmk

Description:
			User defined CPLB tables for BF533 & BF561 (caching purpose)

References:
			None

******************************************************************************
Tab Setting:			4

Target Processor:		ADSP-BF5xx
Target Tools Revision:	ADSP VisualDSP++ v4.5
******************************************************************************

Modification History:
====================
$Log: JPEGImageEdgeDetection_cplb_tables.c,v $
Revision 1.1  2007/05/22 18:37:56  gstephan
Creating VDSP 5.00 release folder.  Created from the head copy of
VDSP 4.50 release folder.

Revision 1.2  2006/11/20 05:56:50  bmk
Merged BF533 & BF561
Fixed BF561 cache issue

Revision 1.1  2006/11/03 07:11:20  bmk
SDK 2.0  files - Initial Entry

*****************************************************************************/

#include <JPEGImageEdgeDetection_cplb_tables.h>
#include <cplb.h>

/***********************
CPLB Tables for BF533
***********************/
#if defined(__ADSPBF533__)

// CPLB Data Table
int codec_dcplbs_table[16][2] =	{
	// L1 DATA
	{ 0xFF800000,	(PAGE_SIZE_1MB | CPLB_D_PAGE_MGMT | CPLB_WT) },	// L1 Data A
	{ 0xFF900000,	(PAGE_SIZE_1MB | CPLB_D_PAGE_MGMT | CPLB_WT) },	// L1 Data B
	
	// SDRAM bank 0
	{ 0x00000000,	(PAGE_SIZE_4MB | CPLB_DNOCACHE) },	// Standard Heap (index 0) NON Cached
	{ 0x00400000,	(PAGE_SIZE_4MB | CPLB_DNOCACHE) },	// Slow Heap (index 1) NON Cached

	// SDRAM bank 1
	{ 0x00800000,	(PAGE_SIZE_4MB | CPLB_DDOCACHE) },	// Cached Data Memory (YUV Buffers)
	{ 0x00C00000,	(PAGE_SIZE_4MB | CPLB_DNOCACHE) },	// NON Cached Data Memory
	
	// SDRAM bank 2
	{ 0x01000000,	(PAGE_SIZE_4MB | CPLB_DDOCACHE) },	// JPEG Image buffer
	{ 0x01400000,	(PAGE_SIZE_4MB | CPLB_DNOCACHE) },	// NON Cached Data Memory

	// SDRAM bank 3
	{ 0x01800000,	(PAGE_SIZE_4MB | CPLB_DDOCACHE) },	// Cached Data Memory (Edge detected buffer)
	{ 0x01C00000,	(PAGE_SIZE_4MB | CPLB_DNOCACHE) },	// NON Cached Data Memory

	// ASYNC MEMORY
	{ 0x20000000,	(PAGE_SIZE_1MB | CPLB_DNOCACHE) },	// Async Memory Bank 0 (Prim A)
	{ 0x20100000,	(PAGE_SIZE_1MB | CPLB_DNOCACHE) },	// Async Memory Bank 1 (Prim B)
	{ 0x20200000,	(PAGE_SIZE_1MB | CPLB_DNOCACHE) },	// Async Memory Bank 2 (Secnd)
	{ 0x20300000,	(PAGE_SIZE_1MB | CPLB_DNOCACHE) },	// Async Memory Bank 3

	// other SDRAM .... not populated on EZ-kit ... dummy entries
	{ 0x02000000,	(PAGE_SIZE_4MB | CPLB_DNOCACHE) },	// 
	{ 0x02400000,	(PAGE_SIZE_4MB | CPLB_DNOCACHE) }	//
};

// CPLB Instruction Table
int codec_icplbs_table[16][2] =	{
	// L1 CODE
	{ 0xFFA00000,	(PAGE_SIZE_1MB | CPLB_I_PAGE_MGMT)	 },	// L1 Code
	
	// SDRAM bank 0
	{ 0x00000000,	(PAGE_SIZE_4MB | CPLB_INOCACHE) },	// dummy non cached instruction memory (keep free for data heap)
	{ 0x00400000,	(PAGE_SIZE_4MB | CPLB_INOCACHE) },	// dummy non cached instruction memory (keep free for data heap)

	// SDRAM bank 1
	{ 0x00800000,	(PAGE_SIZE_4MB | CPLB_IDOCACHE) },	// Cached Instruction Memory
	{ 0x00C00000,	(PAGE_SIZE_4MB | CPLB_INOCACHE) },	// NON Cached Instruction Memory
	
	// SDRAM bank 2
	{ 0x01000000,	(PAGE_SIZE_4MB | CPLB_IDOCACHE) },	// Cached Instruction Memory
	{ 0x01400000,	(PAGE_SIZE_4MB | CPLB_IDOCACHE) },	// Cached Instruction Memory

	// SDRAM bank 3
	{ 0x01800000,	(PAGE_SIZE_4MB | CPLB_INOCACHE) },	// Cached Instruction Memory
	{ 0x01C00000,	(PAGE_SIZE_4MB | CPLB_INOCACHE) },	// Cached Instruction Memory

	// ASYNC MEMORY
	{ 0x20000000,	(PAGE_SIZE_1MB | CPLB_INOCACHE) },	// Async Memory Bank 0 (Prim A)
	{ 0x20100000,	(PAGE_SIZE_1MB | CPLB_INOCACHE) },	// Async Memory Bank 1 (Prim B)
	{ 0x20200000,	(PAGE_SIZE_1MB | CPLB_INOCACHE) },	// Async Memory Bank 2 (Second)
	{ 0x20300000,	(PAGE_SIZE_1MB | CPLB_INOCACHE) },	// Async Memory Bank 3

	// other SDRAM .... not populated on EZ-kit ... dummy entries
	{ 0x02000000,	(PAGE_SIZE_4MB | CPLB_INOCACHE) },	// 
	{ 0x02400000,	(PAGE_SIZE_4MB | CPLB_INOCACHE) },	// 
	{ 0x02800000,	(PAGE_SIZE_4MB | CPLB_INOCACHE) }	//
};

/***************************
CPLB data Tables for BF561
****************************/
#elif defined(__ADSPBF561__)

// CPLB Data Table
#define BIT9 (0x0200)			// workaround for anomaly 05000159/161
int codec_dcplbs_table[16][2] =	{
	// L1 DATA
	{ 0xFF800000,	(PAGE_SIZE_1MB | CPLB_D_PAGE_MGMT | CPLB_WT | BIT9) },	// L1 Data A
	{ 0xFF900000,	(PAGE_SIZE_1MB | CPLB_D_PAGE_MGMT | CPLB_WT | BIT9) },	// L1 Data B

	// L2 memory
	{ 0xFEB00000,	(PAGE_SIZE_1MB | CPLB_DDOCACHE | BIT9) },	// 
			
	// SDRAM bank 0
	{ 0x00000000,	(PAGE_SIZE_4MB | CPLB_DNOCACHE | BIT9) },	// Standard Heap (index 0) NON Cached
	{ 0x00400000,	(PAGE_SIZE_4MB | CPLB_DNOCACHE | BIT9) },	// Slow Heap (index 1) NON Cached

	// SDRAM bank 1
	{ 0x01000000,	(PAGE_SIZE_4MB | CPLB_DDOCACHE | BIT9) },	// Cached Data Memory (YUV buffers)
	{ 0x01400000,	(PAGE_SIZE_4MB | CPLB_DNOCACHE | BIT9) },	// NON cached data memory
	
	// SDRAM bank 2
	{ 0x02000000,	(PAGE_SIZE_4MB | CPLB_DDOCACHE | BIT9) },	// Edge Detection Buffer
	{ 0x02400000,	(PAGE_SIZE_4MB | CPLB_DDOCACHE | BIT9) },	// Cached Data Memory

	// SDRAM bank 3
	{ 0x03000000,	(PAGE_SIZE_4MB | CPLB_DDOCACHE | BIT9) },	// JPEG Image Buffer
	{ 0x03400000,	(PAGE_SIZE_4MB | CPLB_DDOCACHE | BIT9) },	// Cached Data Memory

	// ASYNC MEMORY
	{ 0x20000000,	(PAGE_SIZE_1MB | CPLB_DNOCACHE | BIT9) },	// Async Memory Bank 0 (Prim A)
	{ 0x24000000,	(PAGE_SIZE_1MB | CPLB_DNOCACHE | BIT9) },	// Async Memory Bank 1 (Prim B)
	{ 0x28000000,	(PAGE_SIZE_1MB | CPLB_DNOCACHE | BIT9) },	// Async Memory Bank 2 (Secnd)
	{ 0x2C000000,	(PAGE_SIZE_1MB | CPLB_DNOCACHE | BIT9) },	// Async Memory Bank 3

	// other SDRAM .... . dummy entries
	{ 0x02400000,	(PAGE_SIZE_4MB | CPLB_DNOCACHE | BIT9) }	//
};

// CPLB Instruction Table
int codec_icplbs_table[16][2] =	{
	// L1 CODE
	{ 0xFFA00000,	(PAGE_SIZE_1MB | CPLB_I_PAGE_MGMT)	 },	// L1 Code

	// L2 memory
	{ 0xFEB00000,	(PAGE_SIZE_1MB | CPLB_IDOCACHE) },	// 
			
	// SDRAM bank 0
	{ 0x00000000,	(PAGE_SIZE_4MB | CPLB_INOCACHE) },	// dummy non cached instruction memory (keep free for data heap)
	{ 0x00400000,	(PAGE_SIZE_4MB | CPLB_INOCACHE) },	// dummy non cached instruction memory (keep free for data heap)

	// SDRAM bank 1
	{ 0x01000000,	(PAGE_SIZE_4MB | CPLB_IDOCACHE) },	// Cached Instruction Memory
	{ 0x01400000,	(PAGE_SIZE_4MB | CPLB_INOCACHE) },	// NON Cached Instruction Memory
	
	// SDRAM bank 2
	{ 0x02000000,	(PAGE_SIZE_4MB | CPLB_IDOCACHE) },	// Cached Instruction Memory
	{ 0x02400000,	(PAGE_SIZE_4MB | CPLB_IDOCACHE) },	// Cached Instruction Memory

	// SDRAM bank 3
	{ 0x03000000,	(PAGE_SIZE_4MB | CPLB_IDOCACHE) },	// Cached Instruction Memory
	{ 0x03400000,	(PAGE_SIZE_4MB | CPLB_IDOCACHE) },	// Cached Instruction Memory

	// ASYNC MEMORY
	{ 0x20000000,	(PAGE_SIZE_1MB | CPLB_INOCACHE) },	// Async Memory Bank 0 (Prim A)
	{ 0x24000000,	(PAGE_SIZE_1MB | CPLB_INOCACHE) },	// Async Memory Bank 1 (Prim B)
	{ 0x28000000,	(PAGE_SIZE_1MB | CPLB_INOCACHE) },	// Async Memory Bank 2 (Second)
	{ 0x2C000000,	(PAGE_SIZE_1MB | CPLB_INOCACHE) },	// Async Memory Bank 3
	
	// other SDRAM .... . dummy entries
	{ 0x02400000,	(PAGE_SIZE_4MB | CPLB_INOCACHE) },	// 
	{ 0x02800000,	(PAGE_SIZE_4MB | CPLB_INOCACHE) }	//
};

#endif

/*****/