Implement Log
Created on 6:52:18 PM 4/17/2009
InputFile = c:/dwarf_fpgas/core/implement/xie1.ini
Executing "C:\Xilinx\10.1\ISE\bin\nt\ngdbuild.exe" -p R3384XLTQ144-7 -sd "c:\dwarf_fpgas\core\synthesis" -sd "c:\dwarf_fpgas\core\compile" -sd "c:\dwarf_fpgas\core\src" -sd "C:\Program Files\Aldec\Active-HDL 8.1\vlib\XC9500\compile" -uc "U21.ucf" "U21.ngc" "U21.ngd"
Release 10.1.03 - ngdbuild K.39 (nt)
Copyright (c) 1995-2008 Xilinx, Inc. All rights reserved.
Command Line: C:\Xilinx\10.1\ISE\bin\nt\unwrapped\ngdbuild.exe -p R3384XLTQ144-7
-sd c:\dwarf_fpgas\core\synthesis -sd c:\dwarf_fpgas\core\compile -sd
c:\dwarf_fpgas\core\src -sd C:\Program Files\Aldec\Active-HDL
8.1\vlib\XC9500\compile -uc U21.ucf U21.ngc U21.ngd
Reading NGO file "C:/dwarf_fpgas/core/implement/ver1/rev1/U21.ngc" ...
Gathering constraint information from source properties...
Done.
Applying constraints in "U21.ucf" to the design...
Resolving constraint associations...
Checking Constraint Associations...
Done...
Checking Partitions ...
Checking expanded design ...
Partition Implementation Status
-------------------------------
No Partitions were found in this design.
-------------------------------
NGDBUILD Design Results Summary:
Number of errors: 0
Number of warnings: 0
Writing NGD file "U21.ngd" ...
Writing NGDBUILD log file "U21.bld"...
NGDBUILD done.
Executing "C:\Xilinx\10.1\ISE\bin\nt\cpldfit.exe" -p XCR3384XL-7-TQ144 -loc on -slew fast -init low -unused pullup -terminate float -optimize density -inputs 32 -pterms 28 -inreg on -blkfanin 38 "U21.ngd"
Release 10.1.03 - CPLD Optimizer/Partitioner K.39 (nt)
Copyright (c) 1995-2008 Xilinx, Inc. All rights reserved.
INFO:Cpld - Inferring BUFG constraint for signal 'Mclk' based upon the LOC
constraint 'P127'. It is recommended that you declare this BUFG explicitedly
in your design. Note that for certain device families the output of a BUFG
constraint can not drive a gated clock, and the BUFG constraint will be
ignored.
Cpld:987 - An internal tristate buffer 'outDATA<0>\$WA4' is detected.
The logic is being translated to a mux implementation.
Cpld:987 - An internal tristate buffer 'outDATA<5>\$WA3' is detected.
The logic is being translated to a mux implementation.
Cpld:987 - An internal tristate buffer 'outDATA<4>\$WA3' is detected.
The logic is being translated to a mux implementation.
Cpld:987 - An internal tristate buffer 'outDATA<3>\$WA3' is detected.
The logic is being translated to a mux implementation.
Cpld:987 - An internal tristate buffer 'outDATA<2>\$WA3' is detected.
The logic is being translated to a mux implementation.
Cpld:987 - An internal tristate buffer 'outDATA<1>\$WA3' is detected.
The logic is being translated to a mux implementation.
Cpld:987 - An internal tristate buffer 'outDATA<0>\$WA3' is detected.
The logic is being translated to a mux implementation.
Cpld:987 - An internal tristate buffer 'outDATA<7>\$WA3' is detected.
The logic is being translated to a mux implementation.
Cpld:987 - An internal tristate buffer 'outDATA<6>\$WA3' is detected.
The logic is being translated to a mux implementation.
Cpld:987 - An internal tristate buffer 'outDATA<6>\$WA2' is detected.
The logic is being translated to a mux implementation.
Cpld:987 - An internal tristate buffer 'outDATA<2>\$WA2' is detected.
The logic is being translated to a mux implementation.
Cpld:987 - An internal tristate buffer 'outDATA<0>\$WA5' is detected.
The logic is being translated to a mux implementation.
Cpld:987 - An internal tristate buffer 'outDATA<2>\$WA5' is detected.
The logic is being translated to a mux implementation.
Cpld:987 - An internal tristate buffer 'outDATA<3>\$WA5' is detected.
The logic is being translated to a mux implementation.
Cpld:987 - An internal tristate buffer 'outDATA<4>\$WA5' is detected.
The logic is being translated to a mux implementation.
Cpld:987 - An internal tristate buffer 'outDATA<5>\$WA5' is detected.
The logic is being translated to a mux implementation.
Cpld:987 - An internal tristate buffer 'outDATA<6>\$WA5' is detected.
The logic is being translated to a mux implementation.
Cpld:987 - An internal tristate buffer 'outDATA<7>\$WA5' is detected.
The logic is being translated to a mux implementation.
Cpld:987 - An internal tristate buffer 'outDATA<0>\$WA1' is detected.
The logic is being translated to a mux implementation.
Cpld:987 - An internal tristate buffer 'outDATA<1>\$WA1' is detected.
The logic is being translated to a mux implementation.
Cpld:987 - An internal tristate buffer 'outDATA<2>\$WA1' is detected.
The logic is being translated to a mux implementation.
Cpld:987 - An internal tristate buffer 'outDATA<3>\$WA1' is detected.
The logic is being translated to a mux implementation.
Cpld:987 - An internal tristate buffer 'outDATA<4>\$WA1' is detected.
The logic is being translated to a mux implementation.
Cpld:987 - An internal tristate buffer 'outDATA<5>\$WA1' is detected.
The logic is being translated to a mux implementation.
Cpld:987 - An internal tristate buffer 'outDATA<6>\$WA1' is detected.
The logic is being translated to a mux implementation.
Cpld:987 - An internal tristate buffer 'outDATA<7>\$WA1' is detected.
The logic is being translated to a mux implementation.
Cpld:987 - An internal tristate buffer 'outDATA<4>\$WA4' is detected.
The logic is being translated to a mux implementation.
Cpld:987 - An internal tristate buffer 'outDATA<7>\$WA4' is detected.
The logic is being translated to a mux implementation.
Cpld:987 - An internal tristate buffer 'outDATA<3>\$WA2' is detected.
The logic is being translated to a mux implementation.
Cpld:987 - An internal tristate buffer 'outDATA<7>\$WA2' is detected.
The logic is being translated to a mux implementation.
Cpld:987 - An internal tristate buffer 'outDATA<0>\$WA6' is detected.
The logic is being translated to a mux implementation.
Cpld:987 - An internal tristate buffer 'outDATA<1>\$WA6' is detected.
The logic is being translated to a mux implementation.
Cpld:987 - An internal tristate buffer 'outDATA<2>\$WA6' is detected.
The logic is being translated to a mux implementation.
Cpld:987 - An internal tristate buffer 'outDATA<3>\$WA6' is detected.
The logic is being translated to a mux implementation.
Cpld:987 - An internal tristate buffer 'outDATA<4>\$WA6' is detected.
The logic is being translated to a mux implementation.
Cpld:987 - An internal tristate buffer 'outDATA<5>\$WA6' is detected.
The logic is being translated to a mux implementation.
Cpld:987 - An internal tristate buffer 'outDATA<6>\$WA6' is detected.
The logic is being translated to a mux implementation.
Cpld:987 - An internal tristate buffer 'outDATA<7>\$WA6' is detected.
The logic is being translated to a mux implementation.
Cpld:987 - An internal tristate buffer 'outDATA<2>\$WA0' is detected.
The logic is being translated to a mux implementation.
Cpld:987 - An internal tristate buffer 'outDATA<3>\$WA0' is detected.
The logic is being translated to a mux implementation.
Cpld:987 - An internal tristate buffer 'outDATA<5>\$WA0' is detected.
The logic is being translated to a mux implementation.
Cpld:987 - An internal tristate buffer 'outDATA<6>\$WA0' is detected.
The logic is being translated to a mux implementation.
Cpld:987 - An internal tristate buffer 'outDATA<0>\$WA0' is detected.
The logic is being translated to a mux implementation.
Cpld:987 - An internal tristate buffer 'outDATA<1>\$WA0' is detected.
The logic is being translated to a mux implementation.
Cpld:987 - An internal tristate buffer 'outDATA<4>\$WA0' is detected.
The logic is being translated to a mux implementation.
Cpld:987 - An internal tristate buffer 'outDATA<7>\$WA0' is detected.
The logic is being translated to a mux implementation.
Cpld:987 - An internal tristate buffer 'outDATA<1>\$WA5' is detected.
The logic is being translated to a mux implementation.
Cpld:987 - An internal tristate buffer 'outDATA<0>\$WA2' is detected.
The logic is being translated to a mux implementation.
Cpld:987 - An internal tristate buffer 'outDATA<1>\$WA2' is detected.
The logic is being translated to a mux implementation.
Cpld:987 - An internal tristate buffer 'outDATA<4>\$WA2' is detected.
The logic is being translated to a mux implementation.
Cpld:987 - An internal tristate buffer 'outDATA<5>\$WA2' is detected.
The logic is being translated to a mux implementation.
Cpld:987 - An internal tristate buffer 'outDATA<3>\$WA4' is detected.
The logic is being translated to a mux implementation.
Cpld:987 - An internal tristate buffer 'outDATA<5>\$WA4' is detected.
The logic is being translated to a mux implementation.
Cpld:987 - An internal tristate buffer 'outDATA<1>\$WA4' is detected.
The logic is being translated to a mux implementation.
Cpld:987 - An internal tristate buffer 'outDATA<6>\$WA4' is detected.
The logic is being translated to a mux implementation.
Cpld:987 - An internal tristate buffer 'outDATA<2>\$WA4' is detected.
The logic is being translated to a mux implementation.
Considering device XCR3384XL-7-TQ144.
Re-checking device resources ...
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Synthesizing and Optimizing...
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Fitting...
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Design U21 has been optimized and fit into device XCR3384XL-7-TQ144.
Executing "C:\Xilinx\10.1\ISE\bin\nt\tsim.exe" "U21.vm6" "U21.nga"
Release 10.1.03 - CPLD Timing Simulation Interface K.39 (nt)
Copyright (c) 1995-2008 Xilinx, Inc. All rights reserved.
Creating NGA for simulation.
Speed File: Version 6.0
Executing "C:\Xilinx\10.1\ISE\bin\nt\netgen.exe" -w -sim -ofmt verilog -sdf_anno true -sdf_path c:\esp\electrical\Dwarf\Core\CPLD\implement -insert_glbl true "U21.nga" "time_sim.v"
Release 10.1.03 - netgen K.39 (nt)
Copyright (c) 1995-2008 Xilinx, Inc. All rights reserved.
Command Line: netgen -w -sim -ofmt verilog -sdf_anno true -sdf_path
c:\esp\electrical\Dwarf\Core\CPLD\implement -insert_glbl true U21.nga time_sim.v
NetListWriters:76 - c:\esp\electrical\Dwarf\Core\CPLD\implement is not
pointed to any full path of a direcory, current work directory is used for
the sdf file in $sdf_annotate (if any).
Reading design 'U21.nga' ...
Flattening design ...
Processing design ...
Preping design's networks ...
Preping design's macros ...
Writing Verilog SDF file 'c:\dwarf_fpgas\core\implement\ver1\rev1\time_sim.sdf'
...
Writing Verilog netlist file 'time_sim.v' ...
INFO:NetListWriters:633 - The generated Verilog netlist contains Xilinx SIMPRIM
simulation primitives and has to be used with SIMPRIM simulation library for
correct compilation and simulation.
INFO:NetListWriters - Setup Simulation - To perform a setup simulation, specify
values in the Maximum (MAX) field with the following command line modifier:
-SDFMAX
INFO:NetListWriters - Hold Simulation - To perform the most accurate hold
simulation, specify values in the Minimum (MIN) field with the following
command line modifier: -SDFMIN
INFO:NetListWriters:665 - For more information on how to pass the SDF switches
to the simulator, see your Simulator tool documentation.
Number of warnings: 1
Number of info messages: 4
Total memory usage is 68152 kilobytes
Created netgen log file 'time_sim.nlf'.
Executing "C:\Xilinx\10.1\ISE\bin\nt\hprep6.exe" -i "U21"
Release 10.1.03 - Programming File Generator K.39 (nt)
Copyright (c) 1995-2008 Xilinx, Inc. All rights reserved.
Implementation ver1->rev1: 0 error(s), 57 warning(s)
Implementation ended with warning(s).