[SETTINGS] UUT_module%U21% TB_module%U21_tb% DSN_PATH%$DSN\src\TestBench% OUTPUT_DIRECTORY%C:\esp\electrical\Dwarf\Core\CPLD\src\TestBench% STIMULUS%NO% VECTORS_FILE%% AWF_FILE%% TB_FILE%U21_TB.v% MACRO_FILE%U21_TB_runtest.do% UUT_module_FILE%% LIBRARY_NAME%Core% LIBRARY_TYPE%work% TestBench_TYPE%simple% ENABLE_FILE%none% RESULT_FILE%none% [GENERICS] DANGLING_INPUT_CONSTANT%1'bZ% [PORTS] AS%in%wire%NO%NOCLK% Brake0%in%wire%NO%NOCLK% Brake1%in%wire%NO%NOCLK% DIR0%in%wire%NO%NOCLK% DIR1%in%wire%NO%NOCLK% Enc05FLG%in%wire%NO%NOCLK% Enc15FLG%in%wire%NO%NOCLK% FLS0%in%wire%NO%NOCLK% FLS1%in%wire%NO%NOCLK% GP_Motor0_0%in%wire%NO%NOCLK% GP_Motor1_0%in%wire%NO%NOCLK% Home0%in%wire%NO%NOCLK% Home05FLG%in%wire%NO%NOCLK% Home1%in%wire%NO%NOCLK% Home15FLG%in%wire%NO%NOCLK% INTbus%in%wire%NO%NOCLK% Latch033FLG%in%wire%NO%NOCLK% Latch133FLG%in%wire%NO%NOCLK% LightSense%in%wire%NO%NOCLK% MReset%in%wire%NO%NOCLK% MSPReset%in%wire%NO%NOCLK% Mclk%in%wire%NO%NOCLK% PWM1%in%wire%NO%NOCLK% PWM2%in%wire%NO%NOCLK% PWM3%in%wire%NO%NOCLK% PWM4%in%wire%NO%NOCLK% PWM5%in%wire%NO%NOCLK% PhaseA_Encoder0%in%wire%NO%NOCLK% PhaseA_Encoder1%in%wire%NO%NOCLK% PhaseB_Encoder0%in%wire%NO%NOCLK% PhaseB_Encoder1%in%wire%NO%NOCLK% RD%in%wire%NO%NOCLK% RLS0%in%wire%NO%NOCLK% RLS1%in%wire%NO%NOCLK% SCLinc%in%wire%NO%NOCLK% SCLreset%in%wire%NO%NOCLK% WR%in%wire%NO%NOCLK% I2CS%in%[5:0]wire%NO%NOCLK% Enc05ctrl%out%wire%NO%NOCLK% Enc15ctrl%out%wire%NO%NOCLK% GPIO10%out%wire%NO%NOCLK% GPIO8%out%wire%NO%NOCLK% GPIO9%out%wire%NO%NOCLK% GP_Motor0_1%out%wire%NO%NOCLK% GP_Motor1_1%out%wire%NO%NOCLK% Home05ctrl%out%wire%NO%NOCLK% Home15ctrl%out%wire%NO%NOCLK% INT%out%wire%NO%NOCLK% LED1%out%wire%NO%NOCLK% LED2%out%wire%NO%NOCLK% LED3%out%wire%NO%NOCLK% LED4%out%wire%NO%NOCLK% LED5%out%wire%NO%NOCLK% Latch033ctrl%out%wire%NO%NOCLK% Latch133ctrl%out%wire%NO%NOCLK% MTRpwr%out%wire%NO%NOCLK% MTRpwrn%out%wire%NO%NOCLK% PAH0%out%wire%NO%NOCLK% PAH1%out%wire%NO%NOCLK% PAL0%out%wire%NO%NOCLK% PAL1%out%wire%NO%NOCLK% PBH0%out%wire%NO%NOCLK% PBH1%out%wire%NO%NOCLK% PBL0%out%wire%NO%NOCLK% PBL1%out%wire%NO%NOCLK% PresEn%out%wire%NO%NOCLK% PresSlct%out%wire%NO%NOCLK% TP12%out%wire%NO%NOCLK% TP21%out%wire%NO%NOCLK% TP26%out%wire%NO%NOCLK% TmpEn%out%wire%NO%NOCLK% TmpSlct%out%wire%NO%NOCLK% SCL%inout%wire%NO%NOCLK% AD%inout%[7:0]wire%NO%NOCLK% [SDF] [INCLUDE] [Verilog_FILES]