////////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995-2008 Xilinx, Inc.  All rights reserved.
////////////////////////////////////////////////////////////////////////////////
//   ____  ____
//  /   /\/   /
// /___/  \  /    Vendor: Xilinx
// \   \   \/     Version: K.39
//  \   \         Application: netgen
//  /   /         Filename: U21.v
// /___/   /\     Timestamp: Fri Apr 17 18:46:26 2009
// \   \  /  \ 
//  \___\/\___\
//             
// Command	: -ofmt verilog -intstyle silent -w U21.ngc U21.v 
// Device	: xcr3384xlTQ144-7
// Input file	: U21.ngc
// Output file	: U21.v
// # of Modules	: 25
// Design Name	: U21
// Xilinx        : C:\Xilinx\10.1\ISE
//             
// Purpose:    
//     This verilog netlist is a verification model and uses simulation 
//     primitives which may not represent the true implementation of the 
//     device, however the netlist is functionally correct and should not 
//     be modified. This file cannot be synthesized and should only be used 
//     with supported simulation tools.
//             
// Reference:  
//     Development System Reference Guide, Chapter 23 and Synthesis and Simulation Design Guide, Chapter 6
//             
////////////////////////////////////////////////////////////////////////////////

`timescale 1 ns/1 ps

module low_pass_filter_INST_3 (
  reset_i, phase_i, clock_i, filtered_phase_o
);
  input reset_i;
  input phase_i;
  input clock_i;
  output filtered_phase_o;
  wire delayed_0__and0000;
  wire delayed_0__and00001_1968;
  wire delayed_1__and0000;
  wire delayed_1__and00001_1971;
  wire delayed_2__and0000;
  wire delayed_2__and00001_1974;
  wire delayed_3__and0000;
  wire delayed_3__and00001_1977;
  wire delayed_4__and0000;
  wire delayed_4__and00001_1980;
  wire q__and0000;
  wire q__and00001;
  wire q__and000011_1985;
  wire q__and000012_1986;
  wire [4 : 0] delayed;
  FD   q (
    .C(clock_i),
    .D(q__and0000),
    .Q(filtered_phase_o)
  );
  FD   delayed_0 (
    .C(clock_i),
    .D(delayed_0__and0000),
    .Q(delayed[0])
  );
  FD   delayed_1 (
    .C(clock_i),
    .D(delayed_1__and0000),
    .Q(delayed[1])
  );
  FD   delayed_2 (
    .C(clock_i),
    .D(delayed_2__and0000),
    .Q(delayed[2])
  );
  FD   delayed_3 (
    .C(clock_i),
    .D(delayed_3__and0000),
    .Q(delayed[3])
  );
  FD   delayed_4 (
    .C(clock_i),
    .D(delayed_4__and0000),
    .Q(delayed[4])
  );
  INV   delayed_0__and00001 (
    .I(reset_i),
    .O(delayed_0__and00001_1968)
  );
  AND2   delayed_0__and00002 (
    .I0(phase_i),
    .I1(delayed_0__and00001_1968),
    .O(delayed_0__and0000)
  );
  INV   delayed_1__and00001 (
    .I(reset_i),
    .O(delayed_1__and00001_1971)
  );
  AND2   delayed_1__and00002 (
    .I0(delayed[0]),
    .I1(delayed_1__and00001_1971),
    .O(delayed_1__and0000)
  );
  INV   delayed_2__and00001 (
    .I(reset_i),
    .O(delayed_2__and00001_1974)
  );
  AND2   delayed_2__and00002 (
    .I0(delayed[1]),
    .I1(delayed_2__and00001_1974),
    .O(delayed_2__and0000)
  );
  INV   delayed_3__and00001 (
    .I(reset_i),
    .O(delayed_3__and00001_1977)
  );
  AND2   delayed_3__and00002 (
    .I0(delayed[2]),
    .I1(delayed_3__and00001_1977),
    .O(delayed_3__and0000)
  );
  INV   delayed_4__and00001 (
    .I(reset_i),
    .O(delayed_4__and00001_1980)
  );
  AND2   delayed_4__and00002 (
    .I0(delayed[3]),
    .I1(delayed_4__and00001_1980),
    .O(delayed_4__and0000)
  );
  AND2   q__and000011 (
    .I0(delayed[2]),
    .I1(delayed[3]),
    .O(q__and00001)
  );
  INV   q__and000012 (
    .I(reset_i),
    .O(q__and000011_1985)
  );
  AND2   q__and000013 (
    .I0(delayed[4]),
    .I1(q__and000011_1985),
    .O(q__and000012_1986)
  );
  AND2   q__and000014 (
    .I0(q__and00001),
    .I1(q__and000012_1986),
    .O(q__and0000)
  );
endmodule

module low_pass_filter_INST_2 (
  reset_i, phase_i, clock_i, filtered_phase_o
);
  input reset_i;
  input phase_i;
  input clock_i;
  output filtered_phase_o;
  wire delayed_0__and0000;
  wire delayed_0__and00001_1945;
  wire delayed_1__and0000;
  wire delayed_1__and00001_1948;
  wire delayed_2__and0000;
  wire delayed_2__and00001_1951;
  wire delayed_3__and0000;
  wire delayed_3__and00001_1954;
  wire delayed_4__and0000;
  wire delayed_4__and00001_1957;
  wire q__and0000;
  wire q__and00001;
  wire q__and000011_1962;
  wire q__and000012_1963;
  wire [4 : 0] delayed;
  FD   q (
    .C(clock_i),
    .D(q__and0000),
    .Q(filtered_phase_o)
  );
  FD   delayed_0 (
    .C(clock_i),
    .D(delayed_0__and0000),
    .Q(delayed[0])
  );
  FD   delayed_1 (
    .C(clock_i),
    .D(delayed_1__and0000),
    .Q(delayed[1])
  );
  FD   delayed_2 (
    .C(clock_i),
    .D(delayed_2__and0000),
    .Q(delayed[2])
  );
  FD   delayed_3 (
    .C(clock_i),
    .D(delayed_3__and0000),
    .Q(delayed[3])
  );
  FD   delayed_4 (
    .C(clock_i),
    .D(delayed_4__and0000),
    .Q(delayed[4])
  );
  INV   delayed_0__and00001 (
    .I(reset_i),
    .O(delayed_0__and00001_1945)
  );
  AND2   delayed_0__and00002 (
    .I0(phase_i),
    .I1(delayed_0__and00001_1945),
    .O(delayed_0__and0000)
  );
  INV   delayed_1__and00001 (
    .I(reset_i),
    .O(delayed_1__and00001_1948)
  );
  AND2   delayed_1__and00002 (
    .I0(delayed[0]),
    .I1(delayed_1__and00001_1948),
    .O(delayed_1__and0000)
  );
  INV   delayed_2__and00001 (
    .I(reset_i),
    .O(delayed_2__and00001_1951)
  );
  AND2   delayed_2__and00002 (
    .I0(delayed[1]),
    .I1(delayed_2__and00001_1951),
    .O(delayed_2__and0000)
  );
  INV   delayed_3__and00001 (
    .I(reset_i),
    .O(delayed_3__and00001_1954)
  );
  AND2   delayed_3__and00002 (
    .I0(delayed[2]),
    .I1(delayed_3__and00001_1954),
    .O(delayed_3__and0000)
  );
  INV   delayed_4__and00001 (
    .I(reset_i),
    .O(delayed_4__and00001_1957)
  );
  AND2   delayed_4__and00002 (
    .I0(delayed[3]),
    .I1(delayed_4__and00001_1957),
    .O(delayed_4__and0000)
  );
  AND2   q__and000011 (
    .I0(delayed[2]),
    .I1(delayed[3]),
    .O(q__and00001)
  );
  INV   q__and000012 (
    .I(reset_i),
    .O(q__and000011_1962)
  );
  AND2   q__and000013 (
    .I0(delayed[4]),
    .I1(q__and000011_1962),
    .O(q__and000012_1963)
  );
  AND2   q__and000014 (
    .I0(q__and00001),
    .I1(q__and000012_1963),
    .O(q__and0000)
  );
endmodule

module Decode_INST_1 (
  ce, Reset, updown, phaseA, phaseB, Sclk
);
  output ce;
  input Reset;
  output updown;
  input phaseA;
  input phaseB;
  input Sclk;
  wire SFDecomp_82;
  wire SFDecomp_83;
  wire SFDecomp_831_1991;
  wire SFDecomp_832_1992;
  wire SFDecomp_833_1993;
  wire SFDecomp_85;
  wire SFDecomp_851_1995;
  wire SFDecomp_852_1996;
  wire SFDecomp_853_1997;
  wire SFDecomp_86;
  wire SFDecomp_87;
  wire SFDecomp_871_2000;
  wire SFDecomp_872_2001;
  wire SFDecomp_873_2002;
  wire SFDecomp_874_2003;
  wire SFDecomp_875_2004;
  wire SFDecomp_876_2005;
  wire SFDecomp_89;
  wire SFDecomp_891_2007;
  wire SFDecomp_892_2008;
  wire SFDecomp_893_2009;
  wire SFDecomp_90;
  wire SFDecomp_901_2011;
  wire SFDecomp_902_2012;
  wire SFDecomp_92;
  wire SFDecomp_921_2014;
  wire SFDecomp_922_2015;
  wire SFDecomp_923_2016;
  wire SFDecomp_94;
  wire SFDecomp_941_2018;
  wire SFDecomp_942_2019;
  wire SFDecomp_943_2020;
  wire SFDecomp_95;
  wire SFDecomp_96;
  wire SFDecomp_961_2023;
  wire SFDecomp_962_2024;
  wire SFDecomp_963_2025;
  wire SFDecomp_97;
  wire ce__and0000;
  wire ce__and00001;
  wire ce__and000011_2031;
  wire ce__and000012_2032;
  wire ce__and000013_2033;
  wire ce__and00002;
  wire ce__and000021_2035;
  wire ce__and000022_2036;
  wire ce__and000023_2037;
  wire ce__and000024_2038;
  wire ce__and000025_2039;
  wire ce__and000026_2040;
  wire ce__and0000_bdd0;
  wire phase_b_filtered;
  wire state_FSM_FFd1_2045;
  wire state_FSM_FFd1_N2;
  wire state_FSM_FFd1_N21_2047;
  wire state_FSM_FFd1_N211_2048;
  wire state_FSM_FFd1_N2110_2049;
  wire state_FSM_FFd1_N2111_2050;
  wire state_FSM_FFd1_N2112_2051;
  wire state_FSM_FFd1_N2113_2052;
  wire state_FSM_FFd1_N2114_2053;
  wire state_FSM_FFd1_N2115_2054;
  wire state_FSM_FFd1_N2116_2055;
  wire state_FSM_FFd1_N2117_2056;
  wire state_FSM_FFd1_N2118_2057;
  wire state_FSM_FFd1_N2119_2058;
  wire state_FSM_FFd1_N212_2059;
  wire state_FSM_FFd1_N213_2060;
  wire state_FSM_FFd1_N214_2061;
  wire state_FSM_FFd1_N215_2062;
  wire state_FSM_FFd1_N216_2063;
  wire state_FSM_FFd1_N217_2064;
  wire state_FSM_FFd1_N218_2065;
  wire state_FSM_FFd1_N219_2066;
  wire state_FSM_FFd1_N22_2067;
  wire state_FSM_FFd1_N23_2068;
  wire state_FSM_FFd1_N24_2069;
  wire state_FSM_FFd1_N2_bdd0;
  wire state_FSM_FFd2_2071;
  wire state_FSM_FFd2_N2;
  wire state_FSM_FFd2_N21_2073;
  wire state_FSM_FFd2_N211_2074;
  wire state_FSM_FFd2_N212_2075;
  wire state_FSM_FFd2_N213_2076;
  wire state_FSM_FFd2_N214_2077;
  wire state_FSM_FFd2_N215_2078;
  wire state_FSM_FFd2_N22_2079;
  wire state_FSM_FFd2_N23_2080;
  wire state_FSM_FFd2_N231_2081;
  wire state_FSM_FFd2_N232_2082;
  wire state_FSM_FFd2_N233_2083;
  wire state_FSM_FFd2_N24_2084;
  wire state_FSM_FFd2_N25_2085;
  wire state_FSM_FFd2_N251_2086;
  wire state_FSM_FFd2_N252_2087;
  wire state_FSM_FFd2_N253_2088;
  wire state_FSM_FFd2_N254_2089;
  wire state_FSM_FFd2_N26;
  wire state_FSM_FFd2_N261_2091;
  wire state_FSM_FFd2_N262_2092;
  wire state_FSM_FFd2_N263_2093;
  wire state_FSM_FFd2_N264_2094;
  wire state_FSM_FFd2_N265_2095;
  wire state_FSM_FFd2_N27;
  wire state_FSM_FFd2_N28;
  wire state_FSM_FFd2_N2_bdd0;
  wire state_FSM_FFd2_N2_bdd1;
  wire state_FSM_FFd2_N2_bdd2;
  wire state_FSM_FFd2_N2_bdd3;
  wire state_FSM_FFd3_2102;
  wire state_FSM_FFd3_N2;
  wire state_FSM_FFd3_N21_2104;
  wire state_FSM_FFd3_N211_2105;
  wire state_FSM_FFd3_N212_2106;
  wire state_FSM_FFd3_N213_2107;
  wire state_FSM_FFd3_N214_2108;
  wire state_FSM_FFd3_N22_2109;
  wire state_FSM_FFd3_N23_2110;
  wire state_FSM_FFd3_N2_bdd0;
  wire NlwRenamedSig_OI_updown;
  wire updown__and0000;
  wire updown__and00001;
  wire updown__and000011_2115;
  wire updown__and000012_2116;
  wire updown__and000013_2117;
  wire updown__and00002;
  wire updown__and000021_2119;
  wire updown__and0000210_2120;
  wire updown__and0000211_2121;
  wire updown__and000022_2122;
  wire updown__and000023_2123;
  wire updown__and000024_2124;
  wire updown__and000025_2125;
  wire updown__and000026_2126;
  wire updown__and000027_2127;
  wire updown__and000028_2128;
  wire updown__and000029_2129;
  wire updown__and00003;
  wire updown__and000031_2131;
  wire updown__and000032_2132;
  wire updown__and000033_2133;
  wire updown__and000034_2134;
  wire updown__and000035_2135;
  wire updown__and0000_bdd0;
  wire updown__and0000_bdd1;
  assign
    updown = NlwRenamedSig_OI_updown;
  FD   state_FSM_FFd3 (
    .C(Sclk),
    .D(state_FSM_FFd3_N2),
    .Q(state_FSM_FFd3_2102)
  );
  FD   state_FSM_FFd2 (
    .C(Sclk),
    .D(state_FSM_FFd2_N2),
    .Q(state_FSM_FFd2_2071)
  );
  FD   state_FSM_FFd1 (
    .C(Sclk),
    .D(state_FSM_FFd1_N2),
    .Q(state_FSM_FFd1_2045)
  );
  FD   ce_1719 (
    .C(Sclk),
    .D(ce__and0000),
    .Q(ce)
  );
  FD   updown_1720 (
    .C(Sclk),
    .D(updown__and0000),
    .Q(NlwRenamedSig_OI_updown)
  );
  low_pass_filter_INST_2   phase_b_filter (
    .reset_i(Reset),
    .phase_i(phaseB),
    .clock_i(Sclk),
    .filtered_phase_o(phase_b_filtered)
  );
  low_pass_filter_INST_3   phase_a_filter (
    .reset_i(Reset),
    .phase_i(phaseA),
    .clock_i(Sclk),
    .filtered_phase_o(SFDecomp_82)
  );
  AND2   updown__and000031 (
    .I0(state_FSM_FFd1_2045),
    .I1(NlwRenamedSig_OI_updown),
    .O(updown__and00003)
  );
  INV   updown__and000032 (
    .I(state_FSM_FFd1_2045),
    .O(updown__and000031_2131)
  );
  INV   updown__and000033 (
    .I(state_FSM_FFd3_2102),
    .O(updown__and000032_2132)
  );
  OR2   updown__and000034 (
    .I0(state_FSM_FFd2_2071),
    .I1(updown__and000032_2132),
    .O(updown__and000033_2133)
  );
  INV   updown__and000035 (
    .I(updown__and000033_2133),
    .O(updown__and000034_2134)
  );
  AND2   updown__and000036 (
    .I0(updown__and000031_2131),
    .I1(updown__and000034_2134),
    .O(updown__and000035_2135)
  );
  OR2   updown__and000037 (
    .I0(updown__and00003),
    .I1(updown__and000035_2135),
    .O(updown__and0000_bdd1)
  );
  INV   updown__and000021 (
    .I(state_FSM_FFd3_2102),
    .O(updown__and00002)
  );
  INV   updown__and000022 (
    .I(state_FSM_FFd2_2071),
    .O(updown__and000021_2119)
  );
  AND2   updown__and000023 (
    .I0(state_FSM_FFd3_2102),
    .I1(NlwRenamedSig_OI_updown),
    .O(updown__and000022_2122)
  );
  INV   updown__and000024 (
    .I(state_FSM_FFd2_2071),
    .O(updown__and000023_2123)
  );
  INV   updown__and000025 (
    .I(state_FSM_FFd1_2045),
    .O(updown__and000024_2124)
  );
  OR2   updown__and000026 (
    .I0(NlwRenamedSig_OI_updown),
    .I1(updown__and00002),
    .O(updown__and000025_2125)
  );
  AND2   updown__and000027 (
    .I0(NlwRenamedSig_OI_updown),
    .I1(updown__and000021_2119),
    .O(updown__and000026_2126)
  );
  OR2   updown__and000028 (
    .I0(updown__and000022_2122),
    .I1(updown__and000023_2123),
    .O(updown__and000027_2127)
  );
  AND2   updown__and000029 (
    .I0(state_FSM_FFd2_2071),
    .I1(updown__and000025_2125),
    .O(updown__and000028_2128)
  );
  AND2   updown__and0000210 (
    .I0(updown__and000027_2127),
    .I1(updown__and000024_2124),
    .O(updown__and000029_2129)
  );
  OR2   updown__and0000211 (
    .I0(updown__and000028_2128),
    .I1(updown__and000026_2126),
    .O(updown__and0000210_2120)
  );
  AND2   updown__and0000212 (
    .I0(state_FSM_FFd1_2045),
    .I1(updown__and0000210_2120),
    .O(updown__and0000211_2121)
  );
  OR2   updown__and0000213 (
    .I0(updown__and0000211_2121),
    .I1(updown__and000029_2129),
    .O(updown__and0000_bdd0)
  );
  INV   updown__and000011 (
    .I(SFDecomp_82),
    .O(updown__and00001)
  );
  INV   updown__and000012 (
    .I(Reset),
    .O(updown__and000011_2115)
  );
  AND2   updown__and000013 (
    .I0(SFDecomp_85),
    .I1(updown__and00001),
    .O(updown__and000012_2116)
  );
  OR2   updown__and000014 (
    .I0(SFDecomp_86),
    .I1(updown__and000012_2116),
    .O(updown__and000013_2117)
  );
  AND2   updown__and000015 (
    .I0(updown__and000013_2117),
    .I1(updown__and000011_2115),
    .O(updown__and0000)
  );
  OR2   state_FSM_FFd3_N211 (
    .I0(state_FSM_FFd2_2071),
    .I1(state_FSM_FFd3_2102),
    .O(state_FSM_FFd3_N21_2104)
  );
  INV   state_FSM_FFd3_N212 (
    .I(state_FSM_FFd1_2045),
    .O(state_FSM_FFd3_N211_2105)
  );
  INV   state_FSM_FFd3_N213 (
    .I(state_FSM_FFd2_2071),
    .O(state_FSM_FFd3_N212_2106)
  );
  AND2   state_FSM_FFd3_N214 (
    .I0(state_FSM_FFd1_2045),
    .I1(state_FSM_FFd3_N21_2104),
    .O(state_FSM_FFd3_N213_2107)
  );
  AND2   state_FSM_FFd3_N215 (
    .I0(state_FSM_FFd3_N211_2105),
    .I1(state_FSM_FFd3_N212_2106),
    .O(state_FSM_FFd3_N214_2108)
  );
  OR2   state_FSM_FFd3_N216 (
    .I0(state_FSM_FFd3_N213_2107),
    .I1(state_FSM_FFd3_N214_2108),
    .O(state_FSM_FFd3_N2_bdd0)
  );
  INV   state_FSM_FFd3_N21 (
    .I(SFDecomp_82),
    .O(state_FSM_FFd3_N22_2109)
  );
  OR2   state_FSM_FFd3_N22 (
    .I0(SFDecomp_89),
    .I1(state_FSM_FFd3_N22_2109),
    .O(state_FSM_FFd3_N23_2110)
  );
  AND2   state_FSM_FFd3_N23 (
    .I0(SFDecomp_90),
    .I1(state_FSM_FFd3_N23_2110),
    .O(state_FSM_FFd3_N2)
  );
  AND2   state_FSM_FFd2_N261 (
    .I0(state_FSM_FFd2_2071),
    .I1(state_FSM_FFd3_2102),
    .O(state_FSM_FFd2_N26)
  );
  INV   state_FSM_FFd2_N262 (
    .I(state_FSM_FFd3_2102),
    .O(state_FSM_FFd2_N261_2091)
  );
  INV   state_FSM_FFd2_N263 (
    .I(state_FSM_FFd1_2045),
    .O(state_FSM_FFd2_N262_2092)
  );
  OR2   state_FSM_FFd2_N264 (
    .I0(state_FSM_FFd1_2045),
    .I1(state_FSM_FFd2_N26),
    .O(state_FSM_FFd2_N263_2093)
  );
  AND2   state_FSM_FFd2_N265 (
    .I0(state_FSM_FFd2_2071),
    .I1(state_FSM_FFd2_N261_2091),
    .O(state_FSM_FFd2_N264_2094)
  );
  OR2   state_FSM_FFd2_N266 (
    .I0(state_FSM_FFd2_N264_2094),
    .I1(state_FSM_FFd2_N262_2092),
    .O(state_FSM_FFd2_N265_2095)
  );
  AND2   state_FSM_FFd2_N267 (
    .I0(state_FSM_FFd2_N263_2093),
    .I1(state_FSM_FFd2_N265_2095),
    .O(state_FSM_FFd2_N2_bdd3)
  );
  AND2   state_FSM_FFd2_N251 (
    .I0(state_FSM_FFd1_2045),
    .I1(state_FSM_FFd2_2071),
    .O(state_FSM_FFd2_N25_2085)
  );
  INV   state_FSM_FFd2_N252 (
    .I(state_FSM_FFd3_2102),
    .O(state_FSM_FFd2_N251_2086)
  );
  INV   state_FSM_FFd2_N253 (
    .I(state_FSM_FFd1_2045),
    .O(state_FSM_FFd2_N252_2087)
  );
  OR2   state_FSM_FFd2_N254 (
    .I0(state_FSM_FFd2_2071),
    .I1(state_FSM_FFd2_N251_2086),
    .O(state_FSM_FFd2_N253_2088)
  );
  AND2   state_FSM_FFd2_N255 (
    .I0(state_FSM_FFd2_N253_2088),
    .I1(state_FSM_FFd2_N252_2087),
    .O(state_FSM_FFd2_N254_2089)
  );
  OR2   state_FSM_FFd2_N256 (
    .I0(state_FSM_FFd2_N25_2085),
    .I1(state_FSM_FFd2_N254_2089),
    .O(state_FSM_FFd2_N2_bdd2)
  );
  AND3   state_FSM_FFd2_N231 (
    .I0(state_FSM_FFd1_2045),
    .I1(state_FSM_FFd2_2071),
    .I2(state_FSM_FFd3_2102),
    .O(state_FSM_FFd2_N23_2080)
  );
  INV   state_FSM_FFd2_N232 (
    .I(state_FSM_FFd1_2045),
    .O(state_FSM_FFd2_N231_2081)
  );
  INV   state_FSM_FFd2_N233 (
    .I(state_FSM_FFd3_2102),
    .O(state_FSM_FFd2_N232_2082)
  );
  AND3   state_FSM_FFd2_N234 (
    .I0(state_FSM_FFd2_N231_2081),
    .I1(state_FSM_FFd2_2071),
    .I2(state_FSM_FFd2_N232_2082),
    .O(state_FSM_FFd2_N233_2083)
  );
  OR2   state_FSM_FFd2_N235 (
    .I0(state_FSM_FFd2_N23_2080),
    .I1(state_FSM_FFd2_N233_2083),
    .O(state_FSM_FFd2_N2_bdd1)
  );
  INV   state_FSM_FFd2_N211 (
    .I(state_FSM_FFd3_2102),
    .O(state_FSM_FFd2_N21_2073)
  );
  OR2   state_FSM_FFd2_N212 (
    .I0(state_FSM_FFd2_2071),
    .I1(state_FSM_FFd3_2102),
    .O(state_FSM_FFd2_N211_2074)
  );
  INV   state_FSM_FFd2_N213 (
    .I(state_FSM_FFd1_2045),
    .O(state_FSM_FFd2_N212_2075)
  );
  OR2   state_FSM_FFd2_N214 (
    .I0(state_FSM_FFd2_2071),
    .I1(state_FSM_FFd2_N21_2073),
    .O(state_FSM_FFd2_N213_2076)
  );
  AND2   state_FSM_FFd2_N215 (
    .I0(state_FSM_FFd2_N211_2074),
    .I1(state_FSM_FFd2_N212_2075),
    .O(state_FSM_FFd2_N214_2077)
  );
  AND2   state_FSM_FFd2_N216 (
    .I0(state_FSM_FFd1_2045),
    .I1(state_FSM_FFd2_N213_2076),
    .O(state_FSM_FFd2_N215_2078)
  );
  OR2   state_FSM_FFd2_N217 (
    .I0(state_FSM_FFd2_N215_2078),
    .I1(state_FSM_FFd2_N214_2077),
    .O(state_FSM_FFd2_N2_bdd0)
  );
  INV   state_FSM_FFd2_N21 (
    .I(SFDecomp_82),
    .O(state_FSM_FFd2_N22_2079)
  );
  INV   state_FSM_FFd2_N22 (
    .I(Reset),
    .O(state_FSM_FFd2_N24_2084)
  );
  AND2   state_FSM_FFd2_N23 (
    .I0(SFDecomp_94),
    .I1(state_FSM_FFd2_N22_2079),
    .O(state_FSM_FFd2_N27)
  );
  OR2   state_FSM_FFd2_N24 (
    .I0(SFDecomp_95),
    .I1(state_FSM_FFd2_N27),
    .O(state_FSM_FFd2_N28)
  );
  AND2   state_FSM_FFd2_N25 (
    .I0(state_FSM_FFd2_N28),
    .I1(state_FSM_FFd2_N24_2084),
    .O(state_FSM_FFd2_N2)
  );
  AND2   state_FSM_FFd1_N211 (
    .I0(state_FSM_FFd1_2045),
    .I1(state_FSM_FFd2_2071),
    .O(state_FSM_FFd1_N21_2047)
  );
  INV   state_FSM_FFd1_N212 (
    .I(state_FSM_FFd1_2045),
    .O(state_FSM_FFd1_N211_2048)
  );
  INV   state_FSM_FFd1_N213 (
    .I(state_FSM_FFd3_2102),
    .O(state_FSM_FFd1_N212_2059)
  );
  AND2   state_FSM_FFd1_N214 (
    .I0(state_FSM_FFd3_2102),
    .I1(state_FSM_FFd2_2071),
    .O(state_FSM_FFd1_N213_2060)
  );
  INV   state_FSM_FFd1_N215 (
    .I(state_FSM_FFd2_2071),
    .O(state_FSM_FFd1_N214_2061)
  );
  INV   state_FSM_FFd1_N216 (
    .I(state_FSM_FFd3_2102),
    .O(state_FSM_FFd1_N215_2062)
  );
  AND2   state_FSM_FFd1_N217 (
    .I0(state_FSM_FFd2_2071),
    .I1(state_FSM_FFd3_2102),
    .O(state_FSM_FFd1_N216_2063)
  );
  INV   state_FSM_FFd1_N218 (
    .I(state_FSM_FFd1_2045),
    .O(state_FSM_FFd1_N217_2064)
  );
  INV   state_FSM_FFd1_N219 (
    .I(phase_b_filtered),
    .O(state_FSM_FFd1_N218_2065)
  );
  OR2   state_FSM_FFd1_N2110 (
    .I0(state_FSM_FFd2_2071),
    .I1(state_FSM_FFd1_N212_2059),
    .O(state_FSM_FFd1_N219_2066)
  );
  AND2   state_FSM_FFd1_N2111 (
    .I0(state_FSM_FFd1_N214_2061),
    .I1(state_FSM_FFd1_N215_2062),
    .O(state_FSM_FFd1_N2110_2049)
  );
  AND2   state_FSM_FFd1_N2112 (
    .I0(state_FSM_FFd1_N216_2063),
    .I1(state_FSM_FFd1_N217_2064),
    .O(state_FSM_FFd1_N2111_2050)
  );
  INV   state_FSM_FFd1_N2113 (
    .I(state_FSM_FFd1_N219_2066),
    .O(state_FSM_FFd1_N2112_2051)
  );
  OR2   state_FSM_FFd1_N2114 (
    .I0(state_FSM_FFd1_N213_2060),
    .I1(state_FSM_FFd1_N2110_2049),
    .O(state_FSM_FFd1_N2113_2052)
  );
  AND2   state_FSM_FFd1_N2115 (
    .I0(state_FSM_FFd1_N211_2048),
    .I1(state_FSM_FFd1_N2112_2051),
    .O(state_FSM_FFd1_N2114_2053)
  );
  AND2   state_FSM_FFd1_N2116 (
    .I0(state_FSM_FFd1_2045),
    .I1(state_FSM_FFd1_N2113_2052),
    .O(state_FSM_FFd1_N2115_2054)
  );
  OR2   state_FSM_FFd1_N2117 (
    .I0(state_FSM_FFd1_N21_2047),
    .I1(state_FSM_FFd1_N2114_2053),
    .O(state_FSM_FFd1_N2116_2055)
  );
  OR2   state_FSM_FFd1_N2118 (
    .I0(state_FSM_FFd1_N2115_2054),
    .I1(state_FSM_FFd1_N2111_2050),
    .O(state_FSM_FFd1_N2117_2056)
  );
  AND2   state_FSM_FFd1_N2119 (
    .I0(phase_b_filtered),
    .I1(state_FSM_FFd1_N2116_2055),
    .O(state_FSM_FFd1_N2118_2057)
  );
  AND2   state_FSM_FFd1_N2120 (
    .I0(state_FSM_FFd1_N2117_2056),
    .I1(state_FSM_FFd1_N218_2065),
    .O(state_FSM_FFd1_N2119_2058)
  );
  OR2   state_FSM_FFd1_N2121 (
    .I0(state_FSM_FFd1_N2118_2057),
    .I1(state_FSM_FFd1_N2119_2058),
    .O(state_FSM_FFd1_N2_bdd0)
  );
  AND2   state_FSM_FFd1_N21 (
    .I0(SFDecomp_96),
    .I1(state_FSM_FFd1_2045),
    .O(state_FSM_FFd1_N22_2067)
  );
  INV   state_FSM_FFd1_N22 (
    .I(Reset),
    .O(state_FSM_FFd1_N23_2068)
  );
  OR2   state_FSM_FFd1_N23 (
    .I0(SFDecomp_97),
    .I1(state_FSM_FFd1_N22_2067),
    .O(state_FSM_FFd1_N24_2069)
  );
  AND2   state_FSM_FFd1_N24 (
    .I0(state_FSM_FFd1_N24_2069),
    .I1(state_FSM_FFd1_N23_2068),
    .O(state_FSM_FFd1_N2)
  );
  INV   ce__and000021 (
    .I(state_FSM_FFd1_2045),
    .O(ce__and00002)
  );
  AND2   ce__and000022 (
    .I0(state_FSM_FFd3_2102),
    .I1(state_FSM_FFd2_2071),
    .O(ce__and000021_2035)
  );
  INV   ce__and000023 (
    .I(state_FSM_FFd2_2071),
    .O(ce__and000022_2036)
  );
  INV   ce__and000024 (
    .I(state_FSM_FFd3_2102),
    .O(ce__and000023_2037)
  );
  AND2   ce__and000025 (
    .I0(ce__and000022_2036),
    .I1(ce__and000023_2037),
    .O(ce__and000024_2038)
  );
  OR2   ce__and000026 (
    .I0(ce__and000021_2035),
    .I1(ce__and000024_2038),
    .O(ce__and000025_2039)
  );
  INV   ce__and000027 (
    .I(ce__and000025_2039),
    .O(ce__and000026_2040)
  );
  OR2   ce__and000028 (
    .I0(ce__and00002),
    .I1(ce__and000026_2040),
    .O(ce__and0000_bdd0)
  );
  INV   ce__and000011 (
    .I(Reset),
    .O(ce__and00001)
  );
  INV   ce__and000012 (
    .I(SFDecomp_82),
    .O(ce__and000011_2031)
  );
  INV   ce__and000013 (
    .I(phase_b_filtered),
    .O(ce__and000012_2032)
  );
  INV   ce__and000014 (
    .I(ce__and0000_bdd0),
    .O(ce__and000013_2033)
  );
  AND4   ce__and000015 (
    .I0(ce__and00001),
    .I1(ce__and000011_2031),
    .I2(ce__and000012_2032),
    .I3(ce__and000013_2033),
    .O(ce__and0000)
  );
  AND2   SFDecomp_831 (
    .I0(phase_b_filtered),
    .I1(NlwRenamedSig_OI_updown),
    .O(SFDecomp_831_1991)
  );
  INV   SFDecomp_832 (
    .I(phase_b_filtered),
    .O(SFDecomp_832_1992)
  );
  AND2   SFDecomp_833 (
    .I0(updown__and0000_bdd0),
    .I1(SFDecomp_832_1992),
    .O(SFDecomp_833_1993)
  );
  OR2   SFDecomp_834 (
    .I0(SFDecomp_831_1991),
    .I1(SFDecomp_833_1993),
    .O(SFDecomp_83)
  );
  AND2   SFDecomp_851 (
    .I0(phase_b_filtered),
    .I1(updown__and0000_bdd1),
    .O(SFDecomp_851_1995)
  );
  INV   SFDecomp_852 (
    .I(phase_b_filtered),
    .O(SFDecomp_852_1996)
  );
  AND2   SFDecomp_853 (
    .I0(NlwRenamedSig_OI_updown),
    .I1(SFDecomp_852_1996),
    .O(SFDecomp_853_1997)
  );
  OR2   SFDecomp_854 (
    .I0(SFDecomp_851_1995),
    .I1(SFDecomp_853_1997),
    .O(SFDecomp_85)
  );
  AND2   SFDecomp_861 (
    .I0(SFDecomp_83),
    .I1(SFDecomp_82),
    .O(SFDecomp_86)
  );
  OR2   SFDecomp_871 (
    .I0(state_FSM_FFd1_2045),
    .I1(state_FSM_FFd2_2071),
    .O(SFDecomp_871_2000)
  );
  INV   SFDecomp_872 (
    .I(state_FSM_FFd2_2071),
    .O(SFDecomp_872_2001)
  );
  INV   SFDecomp_873 (
    .I(state_FSM_FFd1_2045),
    .O(SFDecomp_873_2002)
  );
  OR2   SFDecomp_874 (
    .I0(SFDecomp_872_2001),
    .I1(SFDecomp_873_2002),
    .O(SFDecomp_874_2003)
  );
  AND2   SFDecomp_875 (
    .I0(SFDecomp_871_2000),
    .I1(SFDecomp_874_2003),
    .O(SFDecomp_875_2004)
  );
  INV   SFDecomp_876 (
    .I(SFDecomp_875_2004),
    .O(SFDecomp_876_2005)
  );
  OR2   SFDecomp_877 (
    .I0(phase_b_filtered),
    .I1(SFDecomp_876_2005),
    .O(SFDecomp_87)
  );
  INV   SFDecomp_891 (
    .I(phase_b_filtered),
    .O(SFDecomp_891_2007)
  );
  INV   SFDecomp_892 (
    .I(state_FSM_FFd3_N2_bdd0),
    .O(SFDecomp_892_2008)
  );
  OR2   SFDecomp_893 (
    .I0(SFDecomp_891_2007),
    .I1(SFDecomp_892_2008),
    .O(SFDecomp_893_2009)
  );
  AND2   SFDecomp_894 (
    .I0(SFDecomp_87),
    .I1(SFDecomp_893_2009),
    .O(SFDecomp_89)
  );
  OR2   SFDecomp_901 (
    .I0(SFDecomp_82),
    .I1(state_FSM_FFd1_N2_bdd0),
    .O(SFDecomp_901_2011)
  );
  INV   SFDecomp_902 (
    .I(Reset),
    .O(SFDecomp_902_2012)
  );
  AND2   SFDecomp_903 (
    .I0(SFDecomp_901_2011),
    .I1(SFDecomp_902_2012),
    .O(SFDecomp_90)
  );
  AND2   SFDecomp_921 (
    .I0(phase_b_filtered),
    .I1(state_FSM_FFd2_N2_bdd0),
    .O(SFDecomp_921_2014)
  );
  INV   SFDecomp_922 (
    .I(phase_b_filtered),
    .O(SFDecomp_922_2015)
  );
  AND2   SFDecomp_923 (
    .I0(state_FSM_FFd2_N2_bdd1),
    .I1(SFDecomp_922_2015),
    .O(SFDecomp_923_2016)
  );
  OR2   SFDecomp_924 (
    .I0(SFDecomp_921_2014),
    .I1(SFDecomp_923_2016),
    .O(SFDecomp_92)
  );
  AND2   SFDecomp_941 (
    .I0(phase_b_filtered),
    .I1(state_FSM_FFd2_N2_bdd2),
    .O(SFDecomp_941_2018)
  );
  INV   SFDecomp_942 (
    .I(phase_b_filtered),
    .O(SFDecomp_942_2019)
  );
  AND2   SFDecomp_943 (
    .I0(state_FSM_FFd2_N2_bdd3),
    .I1(SFDecomp_942_2019),
    .O(SFDecomp_943_2020)
  );
  OR2   SFDecomp_944 (
    .I0(SFDecomp_941_2018),
    .I1(SFDecomp_943_2020),
    .O(SFDecomp_94)
  );
  AND2   SFDecomp_951 (
    .I0(SFDecomp_92),
    .I1(SFDecomp_82),
    .O(SFDecomp_95)
  );
  INV   SFDecomp_961 (
    .I(state_FSM_FFd3_2102),
    .O(SFDecomp_961_2023)
  );
  INV   SFDecomp_962 (
    .I(SFDecomp_82),
    .O(SFDecomp_962_2024)
  );
  OR2   SFDecomp_963 (
    .I0(state_FSM_FFd2_2071),
    .I1(SFDecomp_961_2023),
    .O(SFDecomp_963_2025)
  );
  AND2   SFDecomp_964 (
    .I0(SFDecomp_963_2025),
    .I1(SFDecomp_962_2024),
    .O(SFDecomp_96)
  );
  AND2   SFDecomp_971 (
    .I0(SFDecomp_82),
    .I1(state_FSM_FFd1_N2_bdd0),
    .O(SFDecomp_97)
  );
endmodule

module low_pass_filter_INST_1 (
  reset_i, phase_i, clock_i, filtered_phase_o
);
  input reset_i;
  input phase_i;
  input clock_i;
  output filtered_phase_o;
  wire delayed_0__and0000;
  wire delayed_0__and00001_1772;
  wire delayed_1__and0000;
  wire delayed_1__and00001_1775;
  wire delayed_2__and0000;
  wire delayed_2__and00001_1778;
  wire delayed_3__and0000;
  wire delayed_3__and00001_1781;
  wire delayed_4__and0000;
  wire delayed_4__and00001_1784;
  wire q__and0000;
  wire q__and00001;
  wire q__and000011_1789;
  wire q__and000012_1790;
  wire [4 : 0] delayed;
  FD   q (
    .C(clock_i),
    .D(q__and0000),
    .Q(filtered_phase_o)
  );
  FD   delayed_0 (
    .C(clock_i),
    .D(delayed_0__and0000),
    .Q(delayed[0])
  );
  FD   delayed_1 (
    .C(clock_i),
    .D(delayed_1__and0000),
    .Q(delayed[1])
  );
  FD   delayed_2 (
    .C(clock_i),
    .D(delayed_2__and0000),
    .Q(delayed[2])
  );
  FD   delayed_3 (
    .C(clock_i),
    .D(delayed_3__and0000),
    .Q(delayed[3])
  );
  FD   delayed_4 (
    .C(clock_i),
    .D(delayed_4__and0000),
    .Q(delayed[4])
  );
  INV   delayed_0__and00001 (
    .I(reset_i),
    .O(delayed_0__and00001_1772)
  );
  AND2   delayed_0__and00002 (
    .I0(phase_i),
    .I1(delayed_0__and00001_1772),
    .O(delayed_0__and0000)
  );
  INV   delayed_1__and00001 (
    .I(reset_i),
    .O(delayed_1__and00001_1775)
  );
  AND2   delayed_1__and00002 (
    .I0(delayed[0]),
    .I1(delayed_1__and00001_1775),
    .O(delayed_1__and0000)
  );
  INV   delayed_2__and00001 (
    .I(reset_i),
    .O(delayed_2__and00001_1778)
  );
  AND2   delayed_2__and00002 (
    .I0(delayed[1]),
    .I1(delayed_2__and00001_1778),
    .O(delayed_2__and0000)
  );
  INV   delayed_3__and00001 (
    .I(reset_i),
    .O(delayed_3__and00001_1781)
  );
  AND2   delayed_3__and00002 (
    .I0(delayed[2]),
    .I1(delayed_3__and00001_1781),
    .O(delayed_3__and0000)
  );
  INV   delayed_4__and00001 (
    .I(reset_i),
    .O(delayed_4__and00001_1784)
  );
  AND2   delayed_4__and00002 (
    .I0(delayed[3]),
    .I1(delayed_4__and00001_1784),
    .O(delayed_4__and0000)
  );
  AND2   q__and000011 (
    .I0(delayed[2]),
    .I1(delayed[3]),
    .O(q__and00001)
  );
  INV   q__and000012 (
    .I(reset_i),
    .O(q__and000011_1789)
  );
  AND2   q__and000013 (
    .I0(delayed[4]),
    .I1(q__and000011_1789),
    .O(q__and000012_1790)
  );
  AND2   q__and000014 (
    .I0(q__and00001),
    .I1(q__and000012_1790),
    .O(q__and0000)
  );
endmodule

module low_pass_filter (
  reset_i, phase_i, clock_i, filtered_phase_o
);
  input reset_i;
  input phase_i;
  input clock_i;
  output filtered_phase_o;
  wire delayed_0__and0000;
  wire delayed_0__and00001_1749;
  wire delayed_1__and0000;
  wire delayed_1__and00001_1752;
  wire delayed_2__and0000;
  wire delayed_2__and00001_1755;
  wire delayed_3__and0000;
  wire delayed_3__and00001_1758;
  wire delayed_4__and0000;
  wire delayed_4__and00001_1761;
  wire q__and0000;
  wire q__and00001;
  wire q__and000011_1766;
  wire q__and000012_1767;
  wire [4 : 0] delayed;
  FD   q (
    .C(clock_i),
    .D(q__and0000),
    .Q(filtered_phase_o)
  );
  FD   delayed_0 (
    .C(clock_i),
    .D(delayed_0__and0000),
    .Q(delayed[0])
  );
  FD   delayed_1 (
    .C(clock_i),
    .D(delayed_1__and0000),
    .Q(delayed[1])
  );
  FD   delayed_2 (
    .C(clock_i),
    .D(delayed_2__and0000),
    .Q(delayed[2])
  );
  FD   delayed_3 (
    .C(clock_i),
    .D(delayed_3__and0000),
    .Q(delayed[3])
  );
  FD   delayed_4 (
    .C(clock_i),
    .D(delayed_4__and0000),
    .Q(delayed[4])
  );
  INV   delayed_0__and00001 (
    .I(reset_i),
    .O(delayed_0__and00001_1749)
  );
  AND2   delayed_0__and00002 (
    .I0(phase_i),
    .I1(delayed_0__and00001_1749),
    .O(delayed_0__and0000)
  );
  INV   delayed_1__and00001 (
    .I(reset_i),
    .O(delayed_1__and00001_1752)
  );
  AND2   delayed_1__and00002 (
    .I0(delayed[0]),
    .I1(delayed_1__and00001_1752),
    .O(delayed_1__and0000)
  );
  INV   delayed_2__and00001 (
    .I(reset_i),
    .O(delayed_2__and00001_1755)
  );
  AND2   delayed_2__and00002 (
    .I0(delayed[1]),
    .I1(delayed_2__and00001_1755),
    .O(delayed_2__and0000)
  );
  INV   delayed_3__and00001 (
    .I(reset_i),
    .O(delayed_3__and00001_1758)
  );
  AND2   delayed_3__and00002 (
    .I0(delayed[2]),
    .I1(delayed_3__and00001_1758),
    .O(delayed_3__and0000)
  );
  INV   delayed_4__and00001 (
    .I(reset_i),
    .O(delayed_4__and00001_1761)
  );
  AND2   delayed_4__and00002 (
    .I0(delayed[3]),
    .I1(delayed_4__and00001_1761),
    .O(delayed_4__and0000)
  );
  AND2   q__and000011 (
    .I0(delayed[2]),
    .I1(delayed[3]),
    .O(q__and00001)
  );
  INV   q__and000012 (
    .I(reset_i),
    .O(q__and000011_1766)
  );
  AND2   q__and000013 (
    .I0(delayed[4]),
    .I1(q__and000011_1766),
    .O(q__and000012_1767)
  );
  AND2   q__and000014 (
    .I0(q__and00001),
    .I1(q__and000012_1767),
    .O(q__and0000)
  );
endmodule

module Decode (
  ce, Reset, updown, phaseA, phaseB, Sclk
);
  output ce;
  input Reset;
  output updown;
  input phaseA;
  input phaseB;
  input Sclk;
  wire SFDecomp_82;
  wire SFDecomp_83;
  wire SFDecomp_831_1795;
  wire SFDecomp_832_1796;
  wire SFDecomp_833_1797;
  wire SFDecomp_85;
  wire SFDecomp_851_1799;
  wire SFDecomp_852_1800;
  wire SFDecomp_853_1801;
  wire SFDecomp_86;
  wire SFDecomp_87;
  wire SFDecomp_871_1804;
  wire SFDecomp_872_1805;
  wire SFDecomp_873_1806;
  wire SFDecomp_874_1807;
  wire SFDecomp_875_1808;
  wire SFDecomp_876_1809;
  wire SFDecomp_89;
  wire SFDecomp_891_1811;
  wire SFDecomp_892_1812;
  wire SFDecomp_893_1813;
  wire SFDecomp_90;
  wire SFDecomp_901_1815;
  wire SFDecomp_902_1816;
  wire SFDecomp_92;
  wire SFDecomp_921_1818;
  wire SFDecomp_922_1819;
  wire SFDecomp_923_1820;
  wire SFDecomp_94;
  wire SFDecomp_941_1822;
  wire SFDecomp_942_1823;
  wire SFDecomp_943_1824;
  wire SFDecomp_95;
  wire SFDecomp_96;
  wire SFDecomp_961_1827;
  wire SFDecomp_962_1828;
  wire SFDecomp_963_1829;
  wire SFDecomp_97;
  wire ce__and0000;
  wire ce__and00001;
  wire ce__and000011_1835;
  wire ce__and000012_1836;
  wire ce__and000013_1837;
  wire ce__and00002;
  wire ce__and000021_1839;
  wire ce__and000022_1840;
  wire ce__and000023_1841;
  wire ce__and000024_1842;
  wire ce__and000025_1843;
  wire ce__and000026_1844;
  wire ce__and0000_bdd0;
  wire phase_b_filtered;
  wire state_FSM_FFd1_1849;
  wire state_FSM_FFd1_N2;
  wire state_FSM_FFd1_N21_1851;
  wire state_FSM_FFd1_N211_1852;
  wire state_FSM_FFd1_N2110_1853;
  wire state_FSM_FFd1_N2111_1854;
  wire state_FSM_FFd1_N2112_1855;
  wire state_FSM_FFd1_N2113_1856;
  wire state_FSM_FFd1_N2114_1857;
  wire state_FSM_FFd1_N2115_1858;
  wire state_FSM_FFd1_N2116_1859;
  wire state_FSM_FFd1_N2117_1860;
  wire state_FSM_FFd1_N2118_1861;
  wire state_FSM_FFd1_N2119_1862;
  wire state_FSM_FFd1_N212_1863;
  wire state_FSM_FFd1_N213_1864;
  wire state_FSM_FFd1_N214_1865;
  wire state_FSM_FFd1_N215_1866;
  wire state_FSM_FFd1_N216_1867;
  wire state_FSM_FFd1_N217_1868;
  wire state_FSM_FFd1_N218_1869;
  wire state_FSM_FFd1_N219_1870;
  wire state_FSM_FFd1_N22_1871;
  wire state_FSM_FFd1_N23_1872;
  wire state_FSM_FFd1_N24_1873;
  wire state_FSM_FFd1_N2_bdd0;
  wire state_FSM_FFd2_1875;
  wire state_FSM_FFd2_N2;
  wire state_FSM_FFd2_N21_1877;
  wire state_FSM_FFd2_N211_1878;
  wire state_FSM_FFd2_N212_1879;
  wire state_FSM_FFd2_N213_1880;
  wire state_FSM_FFd2_N214_1881;
  wire state_FSM_FFd2_N215_1882;
  wire state_FSM_FFd2_N22_1883;
  wire state_FSM_FFd2_N23_1884;
  wire state_FSM_FFd2_N231_1885;
  wire state_FSM_FFd2_N232_1886;
  wire state_FSM_FFd2_N233_1887;
  wire state_FSM_FFd2_N24_1888;
  wire state_FSM_FFd2_N25_1889;
  wire state_FSM_FFd2_N251_1890;
  wire state_FSM_FFd2_N252_1891;
  wire state_FSM_FFd2_N253_1892;
  wire state_FSM_FFd2_N254_1893;
  wire state_FSM_FFd2_N26;
  wire state_FSM_FFd2_N261_1895;
  wire state_FSM_FFd2_N262_1896;
  wire state_FSM_FFd2_N263_1897;
  wire state_FSM_FFd2_N264_1898;
  wire state_FSM_FFd2_N265_1899;
  wire state_FSM_FFd2_N27;
  wire state_FSM_FFd2_N28;
  wire state_FSM_FFd2_N2_bdd0;
  wire state_FSM_FFd2_N2_bdd1;
  wire state_FSM_FFd2_N2_bdd2;
  wire state_FSM_FFd2_N2_bdd3;
  wire state_FSM_FFd3_1906;
  wire state_FSM_FFd3_N2;
  wire state_FSM_FFd3_N21_1908;
  wire state_FSM_FFd3_N211_1909;
  wire state_FSM_FFd3_N212_1910;
  wire state_FSM_FFd3_N213_1911;
  wire state_FSM_FFd3_N214_1912;
  wire state_FSM_FFd3_N22_1913;
  wire state_FSM_FFd3_N23_1914;
  wire state_FSM_FFd3_N2_bdd0;
  wire NlwRenamedSig_OI_updown;
  wire updown__and0000;
  wire updown__and00001;
  wire updown__and000011_1919;
  wire updown__and000012_1920;
  wire updown__and000013_1921;
  wire updown__and00002;
  wire updown__and000021_1923;
  wire updown__and0000210_1924;
  wire updown__and0000211_1925;
  wire updown__and000022_1926;
  wire updown__and000023_1927;
  wire updown__and000024_1928;
  wire updown__and000025_1929;
  wire updown__and000026_1930;
  wire updown__and000027_1931;
  wire updown__and000028_1932;
  wire updown__and000029_1933;
  wire updown__and00003;
  wire updown__and000031_1935;
  wire updown__and000032_1936;
  wire updown__and000033_1937;
  wire updown__and000034_1938;
  wire updown__and000035_1939;
  wire updown__and0000_bdd0;
  wire updown__and0000_bdd1;
  assign
    updown = NlwRenamedSig_OI_updown;
  FD   state_FSM_FFd3 (
    .C(Sclk),
    .D(state_FSM_FFd3_N2),
    .Q(state_FSM_FFd3_1906)
  );
  FD   state_FSM_FFd2 (
    .C(Sclk),
    .D(state_FSM_FFd2_N2),
    .Q(state_FSM_FFd2_1875)
  );
  FD   state_FSM_FFd1 (
    .C(Sclk),
    .D(state_FSM_FFd1_N2),
    .Q(state_FSM_FFd1_1849)
  );
  FD   ce_1532 (
    .C(Sclk),
    .D(ce__and0000),
    .Q(ce)
  );
  FD   updown_1533 (
    .C(Sclk),
    .D(updown__and0000),
    .Q(NlwRenamedSig_OI_updown)
  );
  low_pass_filter   phase_b_filter (
    .reset_i(Reset),
    .phase_i(phaseB),
    .clock_i(Sclk),
    .filtered_phase_o(phase_b_filtered)
  );
  low_pass_filter_INST_1   phase_a_filter (
    .reset_i(Reset),
    .phase_i(phaseA),
    .clock_i(Sclk),
    .filtered_phase_o(SFDecomp_82)
  );
  AND2   updown__and000031 (
    .I0(state_FSM_FFd1_1849),
    .I1(NlwRenamedSig_OI_updown),
    .O(updown__and00003)
  );
  INV   updown__and000032 (
    .I(state_FSM_FFd1_1849),
    .O(updown__and000031_1935)
  );
  INV   updown__and000033 (
    .I(state_FSM_FFd3_1906),
    .O(updown__and000032_1936)
  );
  OR2   updown__and000034 (
    .I0(state_FSM_FFd2_1875),
    .I1(updown__and000032_1936),
    .O(updown__and000033_1937)
  );
  INV   updown__and000035 (
    .I(updown__and000033_1937),
    .O(updown__and000034_1938)
  );
  AND2   updown__and000036 (
    .I0(updown__and000031_1935),
    .I1(updown__and000034_1938),
    .O(updown__and000035_1939)
  );
  OR2   updown__and000037 (
    .I0(updown__and00003),
    .I1(updown__and000035_1939),
    .O(updown__and0000_bdd1)
  );
  INV   updown__and000021 (
    .I(state_FSM_FFd3_1906),
    .O(updown__and00002)
  );
  INV   updown__and000022 (
    .I(state_FSM_FFd2_1875),
    .O(updown__and000021_1923)
  );
  AND2   updown__and000023 (
    .I0(state_FSM_FFd3_1906),
    .I1(NlwRenamedSig_OI_updown),
    .O(updown__and000022_1926)
  );
  INV   updown__and000024 (
    .I(state_FSM_FFd2_1875),
    .O(updown__and000023_1927)
  );
  INV   updown__and000025 (
    .I(state_FSM_FFd1_1849),
    .O(updown__and000024_1928)
  );
  OR2   updown__and000026 (
    .I0(NlwRenamedSig_OI_updown),
    .I1(updown__and00002),
    .O(updown__and000025_1929)
  );
  AND2   updown__and000027 (
    .I0(NlwRenamedSig_OI_updown),
    .I1(updown__and000021_1923),
    .O(updown__and000026_1930)
  );
  OR2   updown__and000028 (
    .I0(updown__and000022_1926),
    .I1(updown__and000023_1927),
    .O(updown__and000027_1931)
  );
  AND2   updown__and000029 (
    .I0(state_FSM_FFd2_1875),
    .I1(updown__and000025_1929),
    .O(updown__and000028_1932)
  );
  AND2   updown__and0000210 (
    .I0(updown__and000027_1931),
    .I1(updown__and000024_1928),
    .O(updown__and000029_1933)
  );
  OR2   updown__and0000211 (
    .I0(updown__and000028_1932),
    .I1(updown__and000026_1930),
    .O(updown__and0000210_1924)
  );
  AND2   updown__and0000212 (
    .I0(state_FSM_FFd1_1849),
    .I1(updown__and0000210_1924),
    .O(updown__and0000211_1925)
  );
  OR2   updown__and0000213 (
    .I0(updown__and0000211_1925),
    .I1(updown__and000029_1933),
    .O(updown__and0000_bdd0)
  );
  INV   updown__and000011 (
    .I(SFDecomp_82),
    .O(updown__and00001)
  );
  INV   updown__and000012 (
    .I(Reset),
    .O(updown__and000011_1919)
  );
  AND2   updown__and000013 (
    .I0(SFDecomp_85),
    .I1(updown__and00001),
    .O(updown__and000012_1920)
  );
  OR2   updown__and000014 (
    .I0(SFDecomp_86),
    .I1(updown__and000012_1920),
    .O(updown__and000013_1921)
  );
  AND2   updown__and000015 (
    .I0(updown__and000013_1921),
    .I1(updown__and000011_1919),
    .O(updown__and0000)
  );
  OR2   state_FSM_FFd3_N211 (
    .I0(state_FSM_FFd2_1875),
    .I1(state_FSM_FFd3_1906),
    .O(state_FSM_FFd3_N21_1908)
  );
  INV   state_FSM_FFd3_N212 (
    .I(state_FSM_FFd1_1849),
    .O(state_FSM_FFd3_N211_1909)
  );
  INV   state_FSM_FFd3_N213 (
    .I(state_FSM_FFd2_1875),
    .O(state_FSM_FFd3_N212_1910)
  );
  AND2   state_FSM_FFd3_N214 (
    .I0(state_FSM_FFd1_1849),
    .I1(state_FSM_FFd3_N21_1908),
    .O(state_FSM_FFd3_N213_1911)
  );
  AND2   state_FSM_FFd3_N215 (
    .I0(state_FSM_FFd3_N211_1909),
    .I1(state_FSM_FFd3_N212_1910),
    .O(state_FSM_FFd3_N214_1912)
  );
  OR2   state_FSM_FFd3_N216 (
    .I0(state_FSM_FFd3_N213_1911),
    .I1(state_FSM_FFd3_N214_1912),
    .O(state_FSM_FFd3_N2_bdd0)
  );
  INV   state_FSM_FFd3_N21 (
    .I(SFDecomp_82),
    .O(state_FSM_FFd3_N22_1913)
  );
  OR2   state_FSM_FFd3_N22 (
    .I0(SFDecomp_89),
    .I1(state_FSM_FFd3_N22_1913),
    .O(state_FSM_FFd3_N23_1914)
  );
  AND2   state_FSM_FFd3_N23 (
    .I0(SFDecomp_90),
    .I1(state_FSM_FFd3_N23_1914),
    .O(state_FSM_FFd3_N2)
  );
  AND2   state_FSM_FFd2_N261 (
    .I0(state_FSM_FFd2_1875),
    .I1(state_FSM_FFd3_1906),
    .O(state_FSM_FFd2_N26)
  );
  INV   state_FSM_FFd2_N262 (
    .I(state_FSM_FFd3_1906),
    .O(state_FSM_FFd2_N261_1895)
  );
  INV   state_FSM_FFd2_N263 (
    .I(state_FSM_FFd1_1849),
    .O(state_FSM_FFd2_N262_1896)
  );
  OR2   state_FSM_FFd2_N264 (
    .I0(state_FSM_FFd1_1849),
    .I1(state_FSM_FFd2_N26),
    .O(state_FSM_FFd2_N263_1897)
  );
  AND2   state_FSM_FFd2_N265 (
    .I0(state_FSM_FFd2_1875),
    .I1(state_FSM_FFd2_N261_1895),
    .O(state_FSM_FFd2_N264_1898)
  );
  OR2   state_FSM_FFd2_N266 (
    .I0(state_FSM_FFd2_N264_1898),
    .I1(state_FSM_FFd2_N262_1896),
    .O(state_FSM_FFd2_N265_1899)
  );
  AND2   state_FSM_FFd2_N267 (
    .I0(state_FSM_FFd2_N263_1897),
    .I1(state_FSM_FFd2_N265_1899),
    .O(state_FSM_FFd2_N2_bdd3)
  );
  AND2   state_FSM_FFd2_N251 (
    .I0(state_FSM_FFd1_1849),
    .I1(state_FSM_FFd2_1875),
    .O(state_FSM_FFd2_N25_1889)
  );
  INV   state_FSM_FFd2_N252 (
    .I(state_FSM_FFd3_1906),
    .O(state_FSM_FFd2_N251_1890)
  );
  INV   state_FSM_FFd2_N253 (
    .I(state_FSM_FFd1_1849),
    .O(state_FSM_FFd2_N252_1891)
  );
  OR2   state_FSM_FFd2_N254 (
    .I0(state_FSM_FFd2_1875),
    .I1(state_FSM_FFd2_N251_1890),
    .O(state_FSM_FFd2_N253_1892)
  );
  AND2   state_FSM_FFd2_N255 (
    .I0(state_FSM_FFd2_N253_1892),
    .I1(state_FSM_FFd2_N252_1891),
    .O(state_FSM_FFd2_N254_1893)
  );
  OR2   state_FSM_FFd2_N256 (
    .I0(state_FSM_FFd2_N25_1889),
    .I1(state_FSM_FFd2_N254_1893),
    .O(state_FSM_FFd2_N2_bdd2)
  );
  AND3   state_FSM_FFd2_N231 (
    .I0(state_FSM_FFd1_1849),
    .I1(state_FSM_FFd2_1875),
    .I2(state_FSM_FFd3_1906),
    .O(state_FSM_FFd2_N23_1884)
  );
  INV   state_FSM_FFd2_N232 (
    .I(state_FSM_FFd1_1849),
    .O(state_FSM_FFd2_N231_1885)
  );
  INV   state_FSM_FFd2_N233 (
    .I(state_FSM_FFd3_1906),
    .O(state_FSM_FFd2_N232_1886)
  );
  AND3   state_FSM_FFd2_N234 (
    .I0(state_FSM_FFd2_N231_1885),
    .I1(state_FSM_FFd2_1875),
    .I2(state_FSM_FFd2_N232_1886),
    .O(state_FSM_FFd2_N233_1887)
  );
  OR2   state_FSM_FFd2_N235 (
    .I0(state_FSM_FFd2_N23_1884),
    .I1(state_FSM_FFd2_N233_1887),
    .O(state_FSM_FFd2_N2_bdd1)
  );
  INV   state_FSM_FFd2_N211 (
    .I(state_FSM_FFd3_1906),
    .O(state_FSM_FFd2_N21_1877)
  );
  OR2   state_FSM_FFd2_N212 (
    .I0(state_FSM_FFd2_1875),
    .I1(state_FSM_FFd3_1906),
    .O(state_FSM_FFd2_N211_1878)
  );
  INV   state_FSM_FFd2_N213 (
    .I(state_FSM_FFd1_1849),
    .O(state_FSM_FFd2_N212_1879)
  );
  OR2   state_FSM_FFd2_N214 (
    .I0(state_FSM_FFd2_1875),
    .I1(state_FSM_FFd2_N21_1877),
    .O(state_FSM_FFd2_N213_1880)
  );
  AND2   state_FSM_FFd2_N215 (
    .I0(state_FSM_FFd2_N211_1878),
    .I1(state_FSM_FFd2_N212_1879),
    .O(state_FSM_FFd2_N214_1881)
  );
  AND2   state_FSM_FFd2_N216 (
    .I0(state_FSM_FFd1_1849),
    .I1(state_FSM_FFd2_N213_1880),
    .O(state_FSM_FFd2_N215_1882)
  );
  OR2   state_FSM_FFd2_N217 (
    .I0(state_FSM_FFd2_N215_1882),
    .I1(state_FSM_FFd2_N214_1881),
    .O(state_FSM_FFd2_N2_bdd0)
  );
  INV   state_FSM_FFd2_N21 (
    .I(SFDecomp_82),
    .O(state_FSM_FFd2_N22_1883)
  );
  INV   state_FSM_FFd2_N22 (
    .I(Reset),
    .O(state_FSM_FFd2_N24_1888)
  );
  AND2   state_FSM_FFd2_N23 (
    .I0(SFDecomp_94),
    .I1(state_FSM_FFd2_N22_1883),
    .O(state_FSM_FFd2_N27)
  );
  OR2   state_FSM_FFd2_N24 (
    .I0(SFDecomp_95),
    .I1(state_FSM_FFd2_N27),
    .O(state_FSM_FFd2_N28)
  );
  AND2   state_FSM_FFd2_N25 (
    .I0(state_FSM_FFd2_N28),
    .I1(state_FSM_FFd2_N24_1888),
    .O(state_FSM_FFd2_N2)
  );
  AND2   state_FSM_FFd1_N211 (
    .I0(state_FSM_FFd1_1849),
    .I1(state_FSM_FFd2_1875),
    .O(state_FSM_FFd1_N21_1851)
  );
  INV   state_FSM_FFd1_N212 (
    .I(state_FSM_FFd1_1849),
    .O(state_FSM_FFd1_N211_1852)
  );
  INV   state_FSM_FFd1_N213 (
    .I(state_FSM_FFd3_1906),
    .O(state_FSM_FFd1_N212_1863)
  );
  AND2   state_FSM_FFd1_N214 (
    .I0(state_FSM_FFd3_1906),
    .I1(state_FSM_FFd2_1875),
    .O(state_FSM_FFd1_N213_1864)
  );
  INV   state_FSM_FFd1_N215 (
    .I(state_FSM_FFd2_1875),
    .O(state_FSM_FFd1_N214_1865)
  );
  INV   state_FSM_FFd1_N216 (
    .I(state_FSM_FFd3_1906),
    .O(state_FSM_FFd1_N215_1866)
  );
  AND2   state_FSM_FFd1_N217 (
    .I0(state_FSM_FFd2_1875),
    .I1(state_FSM_FFd3_1906),
    .O(state_FSM_FFd1_N216_1867)
  );
  INV   state_FSM_FFd1_N218 (
    .I(state_FSM_FFd1_1849),
    .O(state_FSM_FFd1_N217_1868)
  );
  INV   state_FSM_FFd1_N219 (
    .I(phase_b_filtered),
    .O(state_FSM_FFd1_N218_1869)
  );
  OR2   state_FSM_FFd1_N2110 (
    .I0(state_FSM_FFd2_1875),
    .I1(state_FSM_FFd1_N212_1863),
    .O(state_FSM_FFd1_N219_1870)
  );
  AND2   state_FSM_FFd1_N2111 (
    .I0(state_FSM_FFd1_N214_1865),
    .I1(state_FSM_FFd1_N215_1866),
    .O(state_FSM_FFd1_N2110_1853)
  );
  AND2   state_FSM_FFd1_N2112 (
    .I0(state_FSM_FFd1_N216_1867),
    .I1(state_FSM_FFd1_N217_1868),
    .O(state_FSM_FFd1_N2111_1854)
  );
  INV   state_FSM_FFd1_N2113 (
    .I(state_FSM_FFd1_N219_1870),
    .O(state_FSM_FFd1_N2112_1855)
  );
  OR2   state_FSM_FFd1_N2114 (
    .I0(state_FSM_FFd1_N213_1864),
    .I1(state_FSM_FFd1_N2110_1853),
    .O(state_FSM_FFd1_N2113_1856)
  );
  AND2   state_FSM_FFd1_N2115 (
    .I0(state_FSM_FFd1_N211_1852),
    .I1(state_FSM_FFd1_N2112_1855),
    .O(state_FSM_FFd1_N2114_1857)
  );
  AND2   state_FSM_FFd1_N2116 (
    .I0(state_FSM_FFd1_1849),
    .I1(state_FSM_FFd1_N2113_1856),
    .O(state_FSM_FFd1_N2115_1858)
  );
  OR2   state_FSM_FFd1_N2117 (
    .I0(state_FSM_FFd1_N21_1851),
    .I1(state_FSM_FFd1_N2114_1857),
    .O(state_FSM_FFd1_N2116_1859)
  );
  OR2   state_FSM_FFd1_N2118 (
    .I0(state_FSM_FFd1_N2115_1858),
    .I1(state_FSM_FFd1_N2111_1854),
    .O(state_FSM_FFd1_N2117_1860)
  );
  AND2   state_FSM_FFd1_N2119 (
    .I0(phase_b_filtered),
    .I1(state_FSM_FFd1_N2116_1859),
    .O(state_FSM_FFd1_N2118_1861)
  );
  AND2   state_FSM_FFd1_N2120 (
    .I0(state_FSM_FFd1_N2117_1860),
    .I1(state_FSM_FFd1_N218_1869),
    .O(state_FSM_FFd1_N2119_1862)
  );
  OR2   state_FSM_FFd1_N2121 (
    .I0(state_FSM_FFd1_N2118_1861),
    .I1(state_FSM_FFd1_N2119_1862),
    .O(state_FSM_FFd1_N2_bdd0)
  );
  AND2   state_FSM_FFd1_N21 (
    .I0(SFDecomp_96),
    .I1(state_FSM_FFd1_1849),
    .O(state_FSM_FFd1_N22_1871)
  );
  INV   state_FSM_FFd1_N22 (
    .I(Reset),
    .O(state_FSM_FFd1_N23_1872)
  );
  OR2   state_FSM_FFd1_N23 (
    .I0(SFDecomp_97),
    .I1(state_FSM_FFd1_N22_1871),
    .O(state_FSM_FFd1_N24_1873)
  );
  AND2   state_FSM_FFd1_N24 (
    .I0(state_FSM_FFd1_N24_1873),
    .I1(state_FSM_FFd1_N23_1872),
    .O(state_FSM_FFd1_N2)
  );
  INV   ce__and000021 (
    .I(state_FSM_FFd1_1849),
    .O(ce__and00002)
  );
  AND2   ce__and000022 (
    .I0(state_FSM_FFd3_1906),
    .I1(state_FSM_FFd2_1875),
    .O(ce__and000021_1839)
  );
  INV   ce__and000023 (
    .I(state_FSM_FFd2_1875),
    .O(ce__and000022_1840)
  );
  INV   ce__and000024 (
    .I(state_FSM_FFd3_1906),
    .O(ce__and000023_1841)
  );
  AND2   ce__and000025 (
    .I0(ce__and000022_1840),
    .I1(ce__and000023_1841),
    .O(ce__and000024_1842)
  );
  OR2   ce__and000026 (
    .I0(ce__and000021_1839),
    .I1(ce__and000024_1842),
    .O(ce__and000025_1843)
  );
  INV   ce__and000027 (
    .I(ce__and000025_1843),
    .O(ce__and000026_1844)
  );
  OR2   ce__and000028 (
    .I0(ce__and00002),
    .I1(ce__and000026_1844),
    .O(ce__and0000_bdd0)
  );
  INV   ce__and000011 (
    .I(Reset),
    .O(ce__and00001)
  );
  INV   ce__and000012 (
    .I(SFDecomp_82),
    .O(ce__and000011_1835)
  );
  INV   ce__and000013 (
    .I(phase_b_filtered),
    .O(ce__and000012_1836)
  );
  INV   ce__and000014 (
    .I(ce__and0000_bdd0),
    .O(ce__and000013_1837)
  );
  AND4   ce__and000015 (
    .I0(ce__and00001),
    .I1(ce__and000011_1835),
    .I2(ce__and000012_1836),
    .I3(ce__and000013_1837),
    .O(ce__and0000)
  );
  AND2   SFDecomp_831 (
    .I0(phase_b_filtered),
    .I1(NlwRenamedSig_OI_updown),
    .O(SFDecomp_831_1795)
  );
  INV   SFDecomp_832 (
    .I(phase_b_filtered),
    .O(SFDecomp_832_1796)
  );
  AND2   SFDecomp_833 (
    .I0(updown__and0000_bdd0),
    .I1(SFDecomp_832_1796),
    .O(SFDecomp_833_1797)
  );
  OR2   SFDecomp_834 (
    .I0(SFDecomp_831_1795),
    .I1(SFDecomp_833_1797),
    .O(SFDecomp_83)
  );
  AND2   SFDecomp_851 (
    .I0(phase_b_filtered),
    .I1(updown__and0000_bdd1),
    .O(SFDecomp_851_1799)
  );
  INV   SFDecomp_852 (
    .I(phase_b_filtered),
    .O(SFDecomp_852_1800)
  );
  AND2   SFDecomp_853 (
    .I0(NlwRenamedSig_OI_updown),
    .I1(SFDecomp_852_1800),
    .O(SFDecomp_853_1801)
  );
  OR2   SFDecomp_854 (
    .I0(SFDecomp_851_1799),
    .I1(SFDecomp_853_1801),
    .O(SFDecomp_85)
  );
  AND2   SFDecomp_861 (
    .I0(SFDecomp_83),
    .I1(SFDecomp_82),
    .O(SFDecomp_86)
  );
  OR2   SFDecomp_871 (
    .I0(state_FSM_FFd1_1849),
    .I1(state_FSM_FFd2_1875),
    .O(SFDecomp_871_1804)
  );
  INV   SFDecomp_872 (
    .I(state_FSM_FFd2_1875),
    .O(SFDecomp_872_1805)
  );
  INV   SFDecomp_873 (
    .I(state_FSM_FFd1_1849),
    .O(SFDecomp_873_1806)
  );
  OR2   SFDecomp_874 (
    .I0(SFDecomp_872_1805),
    .I1(SFDecomp_873_1806),
    .O(SFDecomp_874_1807)
  );
  AND2   SFDecomp_875 (
    .I0(SFDecomp_871_1804),
    .I1(SFDecomp_874_1807),
    .O(SFDecomp_875_1808)
  );
  INV   SFDecomp_876 (
    .I(SFDecomp_875_1808),
    .O(SFDecomp_876_1809)
  );
  OR2   SFDecomp_877 (
    .I0(phase_b_filtered),
    .I1(SFDecomp_876_1809),
    .O(SFDecomp_87)
  );
  INV   SFDecomp_891 (
    .I(phase_b_filtered),
    .O(SFDecomp_891_1811)
  );
  INV   SFDecomp_892 (
    .I(state_FSM_FFd3_N2_bdd0),
    .O(SFDecomp_892_1812)
  );
  OR2   SFDecomp_893 (
    .I0(SFDecomp_891_1811),
    .I1(SFDecomp_892_1812),
    .O(SFDecomp_893_1813)
  );
  AND2   SFDecomp_894 (
    .I0(SFDecomp_87),
    .I1(SFDecomp_893_1813),
    .O(SFDecomp_89)
  );
  OR2   SFDecomp_901 (
    .I0(SFDecomp_82),
    .I1(state_FSM_FFd1_N2_bdd0),
    .O(SFDecomp_901_1815)
  );
  INV   SFDecomp_902 (
    .I(Reset),
    .O(SFDecomp_902_1816)
  );
  AND2   SFDecomp_903 (
    .I0(SFDecomp_901_1815),
    .I1(SFDecomp_902_1816),
    .O(SFDecomp_90)
  );
  AND2   SFDecomp_921 (
    .I0(phase_b_filtered),
    .I1(state_FSM_FFd2_N2_bdd0),
    .O(SFDecomp_921_1818)
  );
  INV   SFDecomp_922 (
    .I(phase_b_filtered),
    .O(SFDecomp_922_1819)
  );
  AND2   SFDecomp_923 (
    .I0(state_FSM_FFd2_N2_bdd1),
    .I1(SFDecomp_922_1819),
    .O(SFDecomp_923_1820)
  );
  OR2   SFDecomp_924 (
    .I0(SFDecomp_921_1818),
    .I1(SFDecomp_923_1820),
    .O(SFDecomp_92)
  );
  AND2   SFDecomp_941 (
    .I0(phase_b_filtered),
    .I1(state_FSM_FFd2_N2_bdd2),
    .O(SFDecomp_941_1822)
  );
  INV   SFDecomp_942 (
    .I(phase_b_filtered),
    .O(SFDecomp_942_1823)
  );
  AND2   SFDecomp_943 (
    .I0(state_FSM_FFd2_N2_bdd3),
    .I1(SFDecomp_942_1823),
    .O(SFDecomp_943_1824)
  );
  OR2   SFDecomp_944 (
    .I0(SFDecomp_941_1822),
    .I1(SFDecomp_943_1824),
    .O(SFDecomp_94)
  );
  AND2   SFDecomp_951 (
    .I0(SFDecomp_92),
    .I1(SFDecomp_82),
    .O(SFDecomp_95)
  );
  INV   SFDecomp_961 (
    .I(state_FSM_FFd3_1906),
    .O(SFDecomp_961_1827)
  );
  INV   SFDecomp_962 (
    .I(SFDecomp_82),
    .O(SFDecomp_962_1828)
  );
  OR2   SFDecomp_963 (
    .I0(state_FSM_FFd2_1875),
    .I1(SFDecomp_961_1827),
    .O(SFDecomp_963_1829)
  );
  AND2   SFDecomp_964 (
    .I0(SFDecomp_963_1829),
    .I1(SFDecomp_962_1828),
    .O(SFDecomp_96)
  );
  AND2   SFDecomp_971 (
    .I0(SFDecomp_82),
    .I1(state_FSM_FFd1_N2_bdd0),
    .O(SFDecomp_97)
  );
endmodule

module Counter_INST_1 (
  sense, ce, Reset, updown, Zero, Sclk, count
);
  input sense;
  input ce;
  input Reset;
  input updown;
  input Zero;
  input Sclk;
  output [15 : 0] count;
  wire N0;
  wire N1;
  wire N10;
  wire N11;
  wire N12;
  wire N13;
  wire N14;
  wire N15;
  wire N16;
  wire N17;
  wire N18;
  wire N19;
  wire N2;
  wire N20;
  wire N21;
  wire N211;
  wire N22;
  wire N23;
  wire N24;
  wire N25;
  wire N26;
  wire N27;
  wire N28;
  wire N31;
  wire N4;
  wire N5;
  wire N6;
  wire N7;
  wire N8;
  wire N9;
  wire SFDecomp_78;
  wire SFDecomp_79;
  wire SFDecomp_80;
  wire SFDecomp_81;
  wire location_0__and0000;
  wire location_0__and00001_1574;
  wire location_0__and00002_1575;
  wire location_0__or0000;
  wire location_10__and0000;
  wire location_10__and00001_1578;
  wire location_11__and0000;
  wire location_11__and00001_1580;
  wire location_12__and0000;
  wire location_12__and00001_1582;
  wire location_13__and0000;
  wire location_13__and00001_1584;
  wire location_14__and0000;
  wire location_14__and00001_1586;
  wire location_15__and0000;
  wire location_15__and00001_1588;
  wire location_1__and0000;
  wire location_1__and00001_1590;
  wire location_2__and0000;
  wire location_2__and00001_1592;
  wire location_3__and0000;
  wire location_3__and00001_1594;
  wire location_4__and0000;
  wire location_4__and00001_1596;
  wire location_5__and0000;
  wire location_5__and00001_1598;
  wire location_6__and0000;
  wire location_6__and00001_1600;
  wire location_7__and0000;
  wire location_7__and00001_1602;
  wire location_8__and0000;
  wire location_8__and00001_1604;
  wire location_9__and0000;
  wire location_9__and00001_1606;
  wire \location_Madd__add0000_CARRY_IN[10] ;
  wire \location_Madd__add0000_CARRY_IN<10>1_1608 ;
  wire \location_Madd__add0000_CARRY_IN<10>2_1609 ;
  wire \location_Madd__add0000_CARRY_IN<10>3_1610 ;
  wire \location_Madd__add0000_CARRY_IN[13] ;
  wire \location_Madd__add0000_CARRY_IN<13>1_1612 ;
  wire \location_Madd__add0000_CARRY_IN<13>2_1613 ;
  wire \location_Madd__add0000_CARRY_IN<13>3_1614 ;
  wire \location_Madd__add0000_CARRY_IN[4] ;
  wire \location_Madd__add0000_CARRY_IN<4>1_1616 ;
  wire \location_Madd__add0000_CARRY_IN<4>2_1617 ;
  wire \location_Madd__add0000_CARRY_IN<4>3_1618 ;
  wire \location_Madd__add0000_CARRY_IN[7] ;
  wire \location_Madd__add0000_CARRY_IN<7>1_1620 ;
  wire \location_Madd__add0000_CARRY_IN<7>2_1621 ;
  wire \location_Madd__add0000_CARRY_IN<7>3_1622 ;
  wire \location_Madd__add0000_Result<10>1_1624 ;
  wire \location_Madd__add0000_Result<10>2_1625 ;
  wire \location_Madd__add0000_Result<10>3_1626 ;
  wire \location_Madd__add0000_Result<11>1 ;
  wire \location_Madd__add0000_Result<11>11_1629 ;
  wire \location_Madd__add0000_Result<11>111_1630 ;
  wire \location_Madd__add0000_Result<11>12_1631 ;
  wire \location_Madd__add0000_Result<11>13_1632 ;
  wire \location_Madd__add0000_Result<11>14_1633 ;
  wire \location_Madd__add0000_Result<11>2_1634 ;
  wire \location_Madd__add0000_Result<11>3_1635 ;
  wire \location_Madd__add0000_Result<12>1 ;
  wire \location_Madd__add0000_Result<12>11_1638 ;
  wire \location_Madd__add0000_Result<12>12_1639 ;
  wire \location_Madd__add0000_Result<12>13_1640 ;
  wire \location_Madd__add0000_Result<12>14_1641 ;
  wire \location_Madd__add0000_Result<12>2_1642 ;
  wire \location_Madd__add0000_Result<12>3_1643 ;
  wire \location_Madd__add0000_Result<13>1_1645 ;
  wire \location_Madd__add0000_Result<13>2_1646 ;
  wire \location_Madd__add0000_Result<13>3_1647 ;
  wire \location_Madd__add0000_Result<14>1 ;
  wire \location_Madd__add0000_Result<14>11_1650 ;
  wire \location_Madd__add0000_Result<14>111_1651 ;
  wire \location_Madd__add0000_Result<14>12_1652 ;
  wire \location_Madd__add0000_Result<14>13_1653 ;
  wire \location_Madd__add0000_Result<14>14_1654 ;
  wire \location_Madd__add0000_Result<14>2_1655 ;
  wire \location_Madd__add0000_Result<14>3_1656 ;
  wire \location_Madd__add0000_Result<15>1 ;
  wire \location_Madd__add0000_Result<15>11_1659 ;
  wire \location_Madd__add0000_Result<15>12_1660 ;
  wire \location_Madd__add0000_Result<15>13_1661 ;
  wire \location_Madd__add0000_Result<15>14_1662 ;
  wire \location_Madd__add0000_Result<15>2_1663 ;
  wire \location_Madd__add0000_Result<15>3_1664 ;
  wire \location_Madd__add0000_Result<1>1_1666 ;
  wire \location_Madd__add0000_Result<1>2_1667 ;
  wire \location_Madd__add0000_Result<1>3_1668 ;
  wire \location_Madd__add0000_Result<2>1 ;
  wire \location_Madd__add0000_Result<2>11_1671 ;
  wire \location_Madd__add0000_Result<2>111_1672 ;
  wire \location_Madd__add0000_Result<2>12_1673 ;
  wire \location_Madd__add0000_Result<2>13_1674 ;
  wire \location_Madd__add0000_Result<2>14_1675 ;
  wire \location_Madd__add0000_Result<2>2_1676 ;
  wire \location_Madd__add0000_Result<2>3_1677 ;
  wire \location_Madd__add0000_Result<3>1 ;
  wire \location_Madd__add0000_Result<3>11_1680 ;
  wire \location_Madd__add0000_Result<3>12_1681 ;
  wire \location_Madd__add0000_Result<3>13_1682 ;
  wire \location_Madd__add0000_Result<3>14_1683 ;
  wire \location_Madd__add0000_Result<3>2_1684 ;
  wire \location_Madd__add0000_Result<3>3_1685 ;
  wire \location_Madd__add0000_Result<4>1_1687 ;
  wire \location_Madd__add0000_Result<4>2_1688 ;
  wire \location_Madd__add0000_Result<4>3_1689 ;
  wire \location_Madd__add0000_Result<5>1 ;
  wire \location_Madd__add0000_Result<5>11_1692 ;
  wire \location_Madd__add0000_Result<5>111_1693 ;
  wire \location_Madd__add0000_Result<5>12_1694 ;
  wire \location_Madd__add0000_Result<5>13_1695 ;
  wire \location_Madd__add0000_Result<5>14_1696 ;
  wire \location_Madd__add0000_Result<5>2_1697 ;
  wire \location_Madd__add0000_Result<5>3_1698 ;
  wire \location_Madd__add0000_Result<6>1 ;
  wire \location_Madd__add0000_Result<6>11_1701 ;
  wire \location_Madd__add0000_Result<6>12_1702 ;
  wire \location_Madd__add0000_Result<6>13_1703 ;
  wire \location_Madd__add0000_Result<6>14_1704 ;
  wire \location_Madd__add0000_Result<6>2_1705 ;
  wire \location_Madd__add0000_Result<6>3_1706 ;
  wire \location_Madd__add0000_Result<7>1_1708 ;
  wire \location_Madd__add0000_Result<7>2_1709 ;
  wire \location_Madd__add0000_Result<7>3_1710 ;
  wire \location_Madd__add0000_Result<8>1 ;
  wire \location_Madd__add0000_Result<8>11_1713 ;
  wire \location_Madd__add0000_Result<8>111_1714 ;
  wire \location_Madd__add0000_Result<8>12_1715 ;
  wire \location_Madd__add0000_Result<8>13_1716 ;
  wire \location_Madd__add0000_Result<8>14_1717 ;
  wire \location_Madd__add0000_Result<8>2_1718 ;
  wire \location_Madd__add0000_Result<8>3_1719 ;
  wire \location_Madd__add0000_Result<9>1 ;
  wire \location_Madd__add0000_Result<9>11_1722 ;
  wire \location_Madd__add0000_Result<9>12_1723 ;
  wire \location_Madd__add0000_Result<9>13_1724 ;
  wire \location_Madd__add0000_Result<9>14_1725 ;
  wire \location_Madd__add0000_Result<9>2_1726 ;
  wire \location_Madd__add0000_Result<9>3_1727 ;
  wire location_or0001;
  wire [15 : 0] NlwRenamedSig_OI_count;
  wire [15 : 1] location_Madd__add0000_Result;
  wire [15 : 1] location__add0000;
  assign
    count[15] = NlwRenamedSig_OI_count[15],
    count[14] = NlwRenamedSig_OI_count[14],
    count[13] = NlwRenamedSig_OI_count[13],
    count[12] = NlwRenamedSig_OI_count[12],
    count[11] = NlwRenamedSig_OI_count[11],
    count[10] = NlwRenamedSig_OI_count[10],
    count[9] = NlwRenamedSig_OI_count[9],
    count[8] = NlwRenamedSig_OI_count[8],
    count[7] = NlwRenamedSig_OI_count[7],
    count[6] = NlwRenamedSig_OI_count[6],
    count[5] = NlwRenamedSig_OI_count[5],
    count[4] = NlwRenamedSig_OI_count[4],
    count[3] = NlwRenamedSig_OI_count[3],
    count[2] = NlwRenamedSig_OI_count[2],
    count[1] = NlwRenamedSig_OI_count[1],
    count[0] = NlwRenamedSig_OI_count[0];
  FDCE   location_15 (
    .CE(location_0__or0000),
    .CLR(N2),
    .C(Sclk),
    .D(location_15__and0000),
    .Q(NlwRenamedSig_OI_count[15])
  );
  FDCE   location_14 (
    .CE(location_0__or0000),
    .CLR(N2),
    .C(Sclk),
    .D(location_14__and0000),
    .Q(NlwRenamedSig_OI_count[14])
  );
  FDCE   location_13 (
    .CE(location_0__or0000),
    .CLR(N2),
    .C(Sclk),
    .D(location_13__and0000),
    .Q(NlwRenamedSig_OI_count[13])
  );
  FDCE   location_12 (
    .CE(location_0__or0000),
    .CLR(N2),
    .C(Sclk),
    .D(location_12__and0000),
    .Q(NlwRenamedSig_OI_count[12])
  );
  FDCE   location_11 (
    .CE(location_0__or0000),
    .CLR(N2),
    .C(Sclk),
    .D(location_11__and0000),
    .Q(NlwRenamedSig_OI_count[11])
  );
  FDCE   location_10 (
    .CE(location_0__or0000),
    .CLR(N2),
    .C(Sclk),
    .D(location_10__and0000),
    .Q(NlwRenamedSig_OI_count[10])
  );
  FDCE   location_9 (
    .CE(location_0__or0000),
    .CLR(N2),
    .C(Sclk),
    .D(location_9__and0000),
    .Q(NlwRenamedSig_OI_count[9])
  );
  FDCE   location_8 (
    .CE(location_0__or0000),
    .CLR(N2),
    .C(Sclk),
    .D(location_8__and0000),
    .Q(NlwRenamedSig_OI_count[8])
  );
  FDCE   location_7 (
    .CE(location_0__or0000),
    .CLR(N2),
    .C(Sclk),
    .D(location_7__and0000),
    .Q(NlwRenamedSig_OI_count[7])
  );
  FDCE   location_6 (
    .CE(location_0__or0000),
    .CLR(N2),
    .C(Sclk),
    .D(location_6__and0000),
    .Q(NlwRenamedSig_OI_count[6])
  );
  FDCE   location_5 (
    .CE(location_0__or0000),
    .CLR(N2),
    .C(Sclk),
    .D(location_5__and0000),
    .Q(NlwRenamedSig_OI_count[5])
  );
  FDCE   location_4 (
    .CE(location_0__or0000),
    .CLR(N2),
    .C(Sclk),
    .D(location_4__and0000),
    .Q(NlwRenamedSig_OI_count[4])
  );
  FDCE   location_3 (
    .CE(location_0__or0000),
    .CLR(N2),
    .C(Sclk),
    .D(location_3__and0000),
    .Q(NlwRenamedSig_OI_count[3])
  );
  FDCE   location_2 (
    .CE(location_0__or0000),
    .CLR(N2),
    .C(Sclk),
    .D(location_2__and0000),
    .Q(NlwRenamedSig_OI_count[2])
  );
  FDCE   location_1 (
    .CE(location_0__or0000),
    .CLR(N2),
    .C(Sclk),
    .D(location_1__and0000),
    .Q(NlwRenamedSig_OI_count[1])
  );
  FDCE   location_0 (
    .CE(location_0__or0000),
    .CLR(N2),
    .C(Sclk),
    .D(location_0__and0000),
    .Q(NlwRenamedSig_OI_count[0])
  );
  GND   XST_GND (
    .G(N2)
  );
  INV   location_15__and00001 (
    .I(Reset),
    .O(location_15__and00001_1588)
  );
  AND2   location_15__and00002 (
    .I0(location__add0000[15]),
    .I1(location_15__and00001_1588),
    .O(location_15__and0000)
  );
  INV   location_14__and00001 (
    .I(Reset),
    .O(location_14__and00001_1586)
  );
  AND2   location_14__and00002 (
    .I0(location__add0000[14]),
    .I1(location_14__and00001_1586),
    .O(location_14__and0000)
  );
  INV   location_13__and00001 (
    .I(Reset),
    .O(location_13__and00001_1584)
  );
  AND2   location_13__and00002 (
    .I0(location__add0000[13]),
    .I1(location_13__and00001_1584),
    .O(location_13__and0000)
  );
  INV   location_12__and00001 (
    .I(Reset),
    .O(location_12__and00001_1582)
  );
  AND2   location_12__and00002 (
    .I0(location__add0000[12]),
    .I1(location_12__and00001_1582),
    .O(location_12__and0000)
  );
  INV   location_11__and00001 (
    .I(Reset),
    .O(location_11__and00001_1580)
  );
  AND2   location_11__and00002 (
    .I0(location__add0000[11]),
    .I1(location_11__and00001_1580),
    .O(location_11__and0000)
  );
  INV   location_10__and00001 (
    .I(Reset),
    .O(location_10__and00001_1578)
  );
  AND2   location_10__and00002 (
    .I0(location__add0000[10]),
    .I1(location_10__and00001_1578),
    .O(location_10__and0000)
  );
  INV   location_9__and00001 (
    .I(Reset),
    .O(location_9__and00001_1606)
  );
  AND2   location_9__and00002 (
    .I0(location__add0000[9]),
    .I1(location_9__and00001_1606),
    .O(location_9__and0000)
  );
  INV   location_8__and00001 (
    .I(Reset),
    .O(location_8__and00001_1604)
  );
  AND2   location_8__and00002 (
    .I0(location__add0000[8]),
    .I1(location_8__and00001_1604),
    .O(location_8__and0000)
  );
  INV   location_7__and00001 (
    .I(Reset),
    .O(location_7__and00001_1602)
  );
  AND2   location_7__and00002 (
    .I0(location__add0000[7]),
    .I1(location_7__and00001_1602),
    .O(location_7__and0000)
  );
  INV   location_6__and00001 (
    .I(Reset),
    .O(location_6__and00001_1600)
  );
  AND2   location_6__and00002 (
    .I0(location__add0000[6]),
    .I1(location_6__and00001_1600),
    .O(location_6__and0000)
  );
  INV   location_5__and00001 (
    .I(Reset),
    .O(location_5__and00001_1598)
  );
  AND2   location_5__and00002 (
    .I0(location__add0000[5]),
    .I1(location_5__and00001_1598),
    .O(location_5__and0000)
  );
  INV   location_4__and00001 (
    .I(Reset),
    .O(location_4__and00001_1596)
  );
  AND2   location_4__and00002 (
    .I0(location__add0000[4]),
    .I1(location_4__and00001_1596),
    .O(location_4__and0000)
  );
  INV   location_3__and00001 (
    .I(Reset),
    .O(location_3__and00001_1594)
  );
  AND2   location_3__and00002 (
    .I0(location__add0000[3]),
    .I1(location_3__and00001_1594),
    .O(location_3__and0000)
  );
  INV   location_2__and00001 (
    .I(Reset),
    .O(location_2__and00001_1592)
  );
  AND2   location_2__and00002 (
    .I0(location__add0000[2]),
    .I1(location_2__and00001_1592),
    .O(location_2__and0000)
  );
  INV   location_1__and00001 (
    .I(Reset),
    .O(location_1__and00001_1590)
  );
  AND2   location_1__and00002 (
    .I0(location__add0000[1]),
    .I1(location_1__and00001_1590),
    .O(location_1__and0000)
  );
  OR2   location_0__or00001 (
    .I0(ce),
    .I1(Reset),
    .O(location_0__or0000)
  );
  INV   location_0__and00001 (
    .I(Reset),
    .O(location_0__and00001_1574)
  );
  INV   location_0__and00002 (
    .I(NlwRenamedSig_OI_count[0]),
    .O(location_0__and00002_1575)
  );
  AND2   location_0__and00003 (
    .I0(location_0__and00001_1574),
    .I1(location_0__and00002_1575),
    .O(location_0__and0000)
  );
  XOR2   location_or00011 (
    .I0(sense),
    .I1(updown),
    .O(location_or0001)
  );
  AND2   \location_Madd__add0000_Result<3>2  (
    .I0(NlwRenamedSig_OI_count[3]),
    .I1(N0),
    .O(location_Madd__add0000_Result[3])
  );
  INV   \location_Madd__add0000_Result<3>3  (
    .I(NlwRenamedSig_OI_count[3]),
    .O(\location_Madd__add0000_Result<3>1 )
  );
  INV   \location_Madd__add0000_Result<3>4  (
    .I(N0),
    .O(\location_Madd__add0000_Result<3>2_1684 )
  );
  AND2   \location_Madd__add0000_Result<3>5  (
    .I0(\location_Madd__add0000_Result<3>1 ),
    .I1(\location_Madd__add0000_Result<3>2_1684 ),
    .O(\location_Madd__add0000_Result<3>3_1685 )
  );
  OR2   \location_Madd__add0000_Result<3>6  (
    .I0(location_Madd__add0000_Result[3]),
    .I1(\location_Madd__add0000_Result<3>3_1685 ),
    .O(location__add0000[3])
  );
  AND2   \location_Madd__add0000_Result<6>2  (
    .I0(NlwRenamedSig_OI_count[6]),
    .I1(N1),
    .O(location_Madd__add0000_Result[6])
  );
  INV   \location_Madd__add0000_Result<6>3  (
    .I(NlwRenamedSig_OI_count[6]),
    .O(\location_Madd__add0000_Result<6>1 )
  );
  INV   \location_Madd__add0000_Result<6>4  (
    .I(N1),
    .O(\location_Madd__add0000_Result<6>2_1705 )
  );
  AND2   \location_Madd__add0000_Result<6>5  (
    .I0(\location_Madd__add0000_Result<6>1 ),
    .I1(\location_Madd__add0000_Result<6>2_1705 ),
    .O(\location_Madd__add0000_Result<6>3_1706 )
  );
  OR2   \location_Madd__add0000_Result<6>6  (
    .I0(location_Madd__add0000_Result[6]),
    .I1(\location_Madd__add0000_Result<6>3_1706 ),
    .O(location__add0000[6])
  );
  AND2   \location_Madd__add0000_Result<9>2  (
    .I0(NlwRenamedSig_OI_count[9]),
    .I1(N21),
    .O(location_Madd__add0000_Result[9])
  );
  INV   \location_Madd__add0000_Result<9>3  (
    .I(NlwRenamedSig_OI_count[9]),
    .O(\location_Madd__add0000_Result<9>1 )
  );
  INV   \location_Madd__add0000_Result<9>4  (
    .I(N21),
    .O(\location_Madd__add0000_Result<9>2_1726 )
  );
  AND2   \location_Madd__add0000_Result<9>5  (
    .I0(\location_Madd__add0000_Result<9>1 ),
    .I1(\location_Madd__add0000_Result<9>2_1726 ),
    .O(\location_Madd__add0000_Result<9>3_1727 )
  );
  OR2   \location_Madd__add0000_Result<9>6  (
    .I0(location_Madd__add0000_Result[9]),
    .I1(\location_Madd__add0000_Result<9>3_1727 ),
    .O(location__add0000[9])
  );
  AND2   \location_Madd__add0000_Result<12>2  (
    .I0(NlwRenamedSig_OI_count[12]),
    .I1(N31),
    .O(location_Madd__add0000_Result[12])
  );
  INV   \location_Madd__add0000_Result<12>3  (
    .I(NlwRenamedSig_OI_count[12]),
    .O(\location_Madd__add0000_Result<12>1 )
  );
  INV   \location_Madd__add0000_Result<12>4  (
    .I(N31),
    .O(\location_Madd__add0000_Result<12>2_1642 )
  );
  AND2   \location_Madd__add0000_Result<12>5  (
    .I0(\location_Madd__add0000_Result<12>1 ),
    .I1(\location_Madd__add0000_Result<12>2_1642 ),
    .O(\location_Madd__add0000_Result<12>3_1643 )
  );
  OR2   \location_Madd__add0000_Result<12>6  (
    .I0(location_Madd__add0000_Result[12]),
    .I1(\location_Madd__add0000_Result<12>3_1643 ),
    .O(location__add0000[12])
  );
  AND2   \location_Madd__add0000_Result<15>2  (
    .I0(NlwRenamedSig_OI_count[15]),
    .I1(N4),
    .O(location_Madd__add0000_Result[15])
  );
  INV   \location_Madd__add0000_Result<15>3  (
    .I(NlwRenamedSig_OI_count[15]),
    .O(\location_Madd__add0000_Result<15>1 )
  );
  INV   \location_Madd__add0000_Result<15>4  (
    .I(N4),
    .O(\location_Madd__add0000_Result<15>2_1663 )
  );
  AND2   \location_Madd__add0000_Result<15>5  (
    .I0(\location_Madd__add0000_Result<15>1 ),
    .I1(\location_Madd__add0000_Result<15>2_1663 ),
    .O(\location_Madd__add0000_Result<15>3_1664 )
  );
  OR2   \location_Madd__add0000_Result<15>6  (
    .I0(location_Madd__add0000_Result[15]),
    .I1(\location_Madd__add0000_Result<15>3_1664 ),
    .O(location__add0000[15])
  );
  AND2   \location_Madd__add0000_Result<2>2  (
    .I0(NlwRenamedSig_OI_count[2]),
    .I1(N5),
    .O(location_Madd__add0000_Result[2])
  );
  INV   \location_Madd__add0000_Result<2>3  (
    .I(NlwRenamedSig_OI_count[2]),
    .O(\location_Madd__add0000_Result<2>1 )
  );
  INV   \location_Madd__add0000_Result<2>4  (
    .I(N5),
    .O(\location_Madd__add0000_Result<2>2_1676 )
  );
  AND2   \location_Madd__add0000_Result<2>5  (
    .I0(\location_Madd__add0000_Result<2>1 ),
    .I1(\location_Madd__add0000_Result<2>2_1676 ),
    .O(\location_Madd__add0000_Result<2>3_1677 )
  );
  OR2   \location_Madd__add0000_Result<2>6  (
    .I0(location_Madd__add0000_Result[2]),
    .I1(\location_Madd__add0000_Result<2>3_1677 ),
    .O(location__add0000[2])
  );
  AND2   \location_Madd__add0000_Result<5>2  (
    .I0(NlwRenamedSig_OI_count[5]),
    .I1(N6),
    .O(location_Madd__add0000_Result[5])
  );
  INV   \location_Madd__add0000_Result<5>3  (
    .I(NlwRenamedSig_OI_count[5]),
    .O(\location_Madd__add0000_Result<5>1 )
  );
  INV   \location_Madd__add0000_Result<5>4  (
    .I(N6),
    .O(\location_Madd__add0000_Result<5>2_1697 )
  );
  AND2   \location_Madd__add0000_Result<5>5  (
    .I0(\location_Madd__add0000_Result<5>1 ),
    .I1(\location_Madd__add0000_Result<5>2_1697 ),
    .O(\location_Madd__add0000_Result<5>3_1698 )
  );
  OR2   \location_Madd__add0000_Result<5>6  (
    .I0(location_Madd__add0000_Result[5]),
    .I1(\location_Madd__add0000_Result<5>3_1698 ),
    .O(location__add0000[5])
  );
  AND2   \location_Madd__add0000_Result<8>2  (
    .I0(NlwRenamedSig_OI_count[8]),
    .I1(N7),
    .O(location_Madd__add0000_Result[8])
  );
  INV   \location_Madd__add0000_Result<8>3  (
    .I(NlwRenamedSig_OI_count[8]),
    .O(\location_Madd__add0000_Result<8>1 )
  );
  INV   \location_Madd__add0000_Result<8>4  (
    .I(N7),
    .O(\location_Madd__add0000_Result<8>2_1718 )
  );
  AND2   \location_Madd__add0000_Result<8>5  (
    .I0(\location_Madd__add0000_Result<8>1 ),
    .I1(\location_Madd__add0000_Result<8>2_1718 ),
    .O(\location_Madd__add0000_Result<8>3_1719 )
  );
  OR2   \location_Madd__add0000_Result<8>6  (
    .I0(location_Madd__add0000_Result[8]),
    .I1(\location_Madd__add0000_Result<8>3_1719 ),
    .O(location__add0000[8])
  );
  AND2   \location_Madd__add0000_Result<11>2  (
    .I0(NlwRenamedSig_OI_count[11]),
    .I1(N8),
    .O(location_Madd__add0000_Result[11])
  );
  INV   \location_Madd__add0000_Result<11>3  (
    .I(NlwRenamedSig_OI_count[11]),
    .O(\location_Madd__add0000_Result<11>1 )
  );
  INV   \location_Madd__add0000_Result<11>4  (
    .I(N8),
    .O(\location_Madd__add0000_Result<11>2_1634 )
  );
  AND2   \location_Madd__add0000_Result<11>5  (
    .I0(\location_Madd__add0000_Result<11>1 ),
    .I1(\location_Madd__add0000_Result<11>2_1634 ),
    .O(\location_Madd__add0000_Result<11>3_1635 )
  );
  OR2   \location_Madd__add0000_Result<11>6  (
    .I0(location_Madd__add0000_Result[11]),
    .I1(\location_Madd__add0000_Result<11>3_1635 ),
    .O(location__add0000[11])
  );
  AND2   \location_Madd__add0000_Result<14>2  (
    .I0(NlwRenamedSig_OI_count[14]),
    .I1(N9),
    .O(location_Madd__add0000_Result[14])
  );
  INV   \location_Madd__add0000_Result<14>3  (
    .I(NlwRenamedSig_OI_count[14]),
    .O(\location_Madd__add0000_Result<14>1 )
  );
  INV   \location_Madd__add0000_Result<14>4  (
    .I(N9),
    .O(\location_Madd__add0000_Result<14>2_1655 )
  );
  AND2   \location_Madd__add0000_Result<14>5  (
    .I0(\location_Madd__add0000_Result<14>1 ),
    .I1(\location_Madd__add0000_Result<14>2_1655 ),
    .O(\location_Madd__add0000_Result<14>3_1656 )
  );
  OR2   \location_Madd__add0000_Result<14>6  (
    .I0(location_Madd__add0000_Result[14]),
    .I1(\location_Madd__add0000_Result<14>3_1656 ),
    .O(location__add0000[14])
  );
  XOR2   \location_Madd__add0000_Result<13>11  (
    .I0(location_or0001),
    .I1(\location_Madd__add0000_CARRY_IN[13] ),
    .O(N10)
  );
  AND2   \location_Madd__add0000_Result<13>1  (
    .I0(NlwRenamedSig_OI_count[13]),
    .I1(N10),
    .O(location_Madd__add0000_Result[13])
  );
  INV   \location_Madd__add0000_Result<13>2  (
    .I(NlwRenamedSig_OI_count[13]),
    .O(\location_Madd__add0000_Result<13>1_1645 )
  );
  INV   \location_Madd__add0000_Result<13>3  (
    .I(N10),
    .O(\location_Madd__add0000_Result<13>2_1646 )
  );
  AND2   \location_Madd__add0000_Result<13>4  (
    .I0(\location_Madd__add0000_Result<13>1_1645 ),
    .I1(\location_Madd__add0000_Result<13>2_1646 ),
    .O(\location_Madd__add0000_Result<13>3_1647 )
  );
  OR2   \location_Madd__add0000_Result<13>5  (
    .I0(location_Madd__add0000_Result[13]),
    .I1(\location_Madd__add0000_Result<13>3_1647 ),
    .O(location__add0000[13])
  );
  XOR2   \location_Madd__add0000_Result<10>11  (
    .I0(location_or0001),
    .I1(\location_Madd__add0000_CARRY_IN[10] ),
    .O(N11)
  );
  AND2   \location_Madd__add0000_Result<10>1  (
    .I0(NlwRenamedSig_OI_count[10]),
    .I1(N11),
    .O(location_Madd__add0000_Result[10])
  );
  INV   \location_Madd__add0000_Result<10>2  (
    .I(NlwRenamedSig_OI_count[10]),
    .O(\location_Madd__add0000_Result<10>1_1624 )
  );
  INV   \location_Madd__add0000_Result<10>3  (
    .I(N11),
    .O(\location_Madd__add0000_Result<10>2_1625 )
  );
  AND2   \location_Madd__add0000_Result<10>4  (
    .I0(\location_Madd__add0000_Result<10>1_1624 ),
    .I1(\location_Madd__add0000_Result<10>2_1625 ),
    .O(\location_Madd__add0000_Result<10>3_1626 )
  );
  OR2   \location_Madd__add0000_Result<10>5  (
    .I0(location_Madd__add0000_Result[10]),
    .I1(\location_Madd__add0000_Result<10>3_1626 ),
    .O(location__add0000[10])
  );
  XOR2   \location_Madd__add0000_Result<7>11  (
    .I0(location_or0001),
    .I1(\location_Madd__add0000_CARRY_IN[7] ),
    .O(N12)
  );
  AND2   \location_Madd__add0000_Result<7>1  (
    .I0(NlwRenamedSig_OI_count[7]),
    .I1(N12),
    .O(location_Madd__add0000_Result[7])
  );
  INV   \location_Madd__add0000_Result<7>2  (
    .I(NlwRenamedSig_OI_count[7]),
    .O(\location_Madd__add0000_Result<7>1_1708 )
  );
  INV   \location_Madd__add0000_Result<7>3  (
    .I(N12),
    .O(\location_Madd__add0000_Result<7>2_1709 )
  );
  AND2   \location_Madd__add0000_Result<7>4  (
    .I0(\location_Madd__add0000_Result<7>1_1708 ),
    .I1(\location_Madd__add0000_Result<7>2_1709 ),
    .O(\location_Madd__add0000_Result<7>3_1710 )
  );
  OR2   \location_Madd__add0000_Result<7>5  (
    .I0(location_Madd__add0000_Result[7]),
    .I1(\location_Madd__add0000_Result<7>3_1710 ),
    .O(location__add0000[7])
  );
  XOR2   \location_Madd__add0000_Result<4>11  (
    .I0(location_or0001),
    .I1(\location_Madd__add0000_CARRY_IN[4] ),
    .O(N13)
  );
  AND2   \location_Madd__add0000_Result<4>1  (
    .I0(NlwRenamedSig_OI_count[4]),
    .I1(N13),
    .O(location_Madd__add0000_Result[4])
  );
  INV   \location_Madd__add0000_Result<4>2  (
    .I(NlwRenamedSig_OI_count[4]),
    .O(\location_Madd__add0000_Result<4>1_1687 )
  );
  INV   \location_Madd__add0000_Result<4>3  (
    .I(N13),
    .O(\location_Madd__add0000_Result<4>2_1688 )
  );
  AND2   \location_Madd__add0000_Result<4>4  (
    .I0(\location_Madd__add0000_Result<4>1_1687 ),
    .I1(\location_Madd__add0000_Result<4>2_1688 ),
    .O(\location_Madd__add0000_Result<4>3_1689 )
  );
  OR2   \location_Madd__add0000_Result<4>5  (
    .I0(location_Madd__add0000_Result[4]),
    .I1(\location_Madd__add0000_Result<4>3_1689 ),
    .O(location__add0000[4])
  );
  XOR2   \location_Madd__add0000_Result<1>11  (
    .I0(location_or0001),
    .I1(NlwRenamedSig_OI_count[1]),
    .O(N14)
  );
  AND2   \location_Madd__add0000_Result<1>1  (
    .I0(NlwRenamedSig_OI_count[0]),
    .I1(N14),
    .O(location_Madd__add0000_Result[1])
  );
  INV   \location_Madd__add0000_Result<1>2  (
    .I(NlwRenamedSig_OI_count[0]),
    .O(\location_Madd__add0000_Result<1>1_1666 )
  );
  INV   \location_Madd__add0000_Result<1>3  (
    .I(N14),
    .O(\location_Madd__add0000_Result<1>2_1667 )
  );
  AND2   \location_Madd__add0000_Result<1>4  (
    .I0(\location_Madd__add0000_Result<1>1_1666 ),
    .I1(\location_Madd__add0000_Result<1>2_1667 ),
    .O(\location_Madd__add0000_Result<1>3_1668 )
  );
  OR2   \location_Madd__add0000_Result<1>5  (
    .I0(location_Madd__add0000_Result[1]),
    .I1(\location_Madd__add0000_Result<1>3_1668 ),
    .O(location__add0000[1])
  );
  OR4   \location_Madd__add0000_CARRY_IN<4>11  (
    .I0(NlwRenamedSig_OI_count[0]),
    .I1(NlwRenamedSig_OI_count[1]),
    .I2(NlwRenamedSig_OI_count[2]),
    .I3(NlwRenamedSig_OI_count[3]),
    .O(N15)
  );
  AND2   \location_Madd__add0000_CARRY_IN<4>1  (
    .I0(SFDecomp_78),
    .I1(NlwRenamedSig_OI_count[3]),
    .O(\location_Madd__add0000_CARRY_IN<4>1_1616 )
  );
  INV   \location_Madd__add0000_CARRY_IN<4>2  (
    .I(location_or0001),
    .O(\location_Madd__add0000_CARRY_IN<4>2_1617 )
  );
  AND2   \location_Madd__add0000_CARRY_IN<4>3  (
    .I0(N15),
    .I1(\location_Madd__add0000_CARRY_IN<4>2_1617 ),
    .O(\location_Madd__add0000_CARRY_IN<4>3_1618 )
  );
  OR2   \location_Madd__add0000_CARRY_IN<4>4  (
    .I0(\location_Madd__add0000_CARRY_IN<4>1_1616 ),
    .I1(\location_Madd__add0000_CARRY_IN<4>3_1618 ),
    .O(\location_Madd__add0000_CARRY_IN[4] )
  );
  OR4   \location_Madd__add0000_CARRY_IN<7>11  (
    .I0(NlwRenamedSig_OI_count[4]),
    .I1(NlwRenamedSig_OI_count[5]),
    .I2(NlwRenamedSig_OI_count[6]),
    .I3(\location_Madd__add0000_CARRY_IN[4] ),
    .O(N16)
  );
  AND2   \location_Madd__add0000_CARRY_IN<7>1  (
    .I0(SFDecomp_79),
    .I1(\location_Madd__add0000_CARRY_IN[4] ),
    .O(\location_Madd__add0000_CARRY_IN<7>1_1620 )
  );
  INV   \location_Madd__add0000_CARRY_IN<7>2  (
    .I(location_or0001),
    .O(\location_Madd__add0000_CARRY_IN<7>2_1621 )
  );
  AND2   \location_Madd__add0000_CARRY_IN<7>3  (
    .I0(N16),
    .I1(\location_Madd__add0000_CARRY_IN<7>2_1621 ),
    .O(\location_Madd__add0000_CARRY_IN<7>3_1622 )
  );
  OR2   \location_Madd__add0000_CARRY_IN<7>4  (
    .I0(\location_Madd__add0000_CARRY_IN<7>1_1620 ),
    .I1(\location_Madd__add0000_CARRY_IN<7>3_1622 ),
    .O(\location_Madd__add0000_CARRY_IN[7] )
  );
  OR4   \location_Madd__add0000_CARRY_IN<10>11  (
    .I0(NlwRenamedSig_OI_count[7]),
    .I1(NlwRenamedSig_OI_count[8]),
    .I2(NlwRenamedSig_OI_count[9]),
    .I3(\location_Madd__add0000_CARRY_IN[7] ),
    .O(N17)
  );
  AND2   \location_Madd__add0000_CARRY_IN<10>1  (
    .I0(SFDecomp_80),
    .I1(\location_Madd__add0000_CARRY_IN[7] ),
    .O(\location_Madd__add0000_CARRY_IN<10>1_1608 )
  );
  INV   \location_Madd__add0000_CARRY_IN<10>2  (
    .I(location_or0001),
    .O(\location_Madd__add0000_CARRY_IN<10>2_1609 )
  );
  AND2   \location_Madd__add0000_CARRY_IN<10>3  (
    .I0(N17),
    .I1(\location_Madd__add0000_CARRY_IN<10>2_1609 ),
    .O(\location_Madd__add0000_CARRY_IN<10>3_1610 )
  );
  OR2   \location_Madd__add0000_CARRY_IN<10>4  (
    .I0(\location_Madd__add0000_CARRY_IN<10>1_1608 ),
    .I1(\location_Madd__add0000_CARRY_IN<10>3_1610 ),
    .O(\location_Madd__add0000_CARRY_IN[10] )
  );
  OR4   \location_Madd__add0000_CARRY_IN<13>11  (
    .I0(NlwRenamedSig_OI_count[10]),
    .I1(NlwRenamedSig_OI_count[11]),
    .I2(NlwRenamedSig_OI_count[12]),
    .I3(\location_Madd__add0000_CARRY_IN[10] ),
    .O(N18)
  );
  AND2   \location_Madd__add0000_CARRY_IN<13>1  (
    .I0(SFDecomp_81),
    .I1(\location_Madd__add0000_CARRY_IN[10] ),
    .O(\location_Madd__add0000_CARRY_IN<13>1_1612 )
  );
  INV   \location_Madd__add0000_CARRY_IN<13>2  (
    .I(location_or0001),
    .O(\location_Madd__add0000_CARRY_IN<13>2_1613 )
  );
  AND2   \location_Madd__add0000_CARRY_IN<13>3  (
    .I0(N18),
    .I1(\location_Madd__add0000_CARRY_IN<13>2_1613 ),
    .O(\location_Madd__add0000_CARRY_IN<13>3_1614 )
  );
  OR2   \location_Madd__add0000_CARRY_IN<13>4  (
    .I0(\location_Madd__add0000_CARRY_IN<13>1_1612 ),
    .I1(\location_Madd__add0000_CARRY_IN<13>3_1614 ),
    .O(\location_Madd__add0000_CARRY_IN[13] )
  );
  INV   \location_Madd__add0000_Result<12>11  (
    .I(location_or0001),
    .O(\location_Madd__add0000_Result<12>11_1638 )
  );
  INV   \location_Madd__add0000_Result<12>12  (
    .I(NlwRenamedSig_OI_count[11]),
    .O(\location_Madd__add0000_Result<12>12_1639 )
  );
  AND2   \location_Madd__add0000_Result<12>13  (
    .I0(NlwRenamedSig_OI_count[11]),
    .I1(\location_Madd__add0000_Result<12>11_1638 ),
    .O(\location_Madd__add0000_Result<12>13_1640 )
  );
  AND2   \location_Madd__add0000_Result<12>14  (
    .I0(location_or0001),
    .I1(\location_Madd__add0000_Result<12>12_1639 ),
    .O(\location_Madd__add0000_Result<12>14_1641 )
  );
  OR3   \location_Madd__add0000_Result<12>15  (
    .I0(\location_Madd__add0000_Result<12>13_1640 ),
    .I1(N8),
    .I2(\location_Madd__add0000_Result<12>14_1641 ),
    .O(N31)
  );
  INV   \location_Madd__add0000_Result<15>11  (
    .I(location_or0001),
    .O(\location_Madd__add0000_Result<15>11_1659 )
  );
  INV   \location_Madd__add0000_Result<15>12  (
    .I(NlwRenamedSig_OI_count[14]),
    .O(\location_Madd__add0000_Result<15>12_1660 )
  );
  AND2   \location_Madd__add0000_Result<15>13  (
    .I0(NlwRenamedSig_OI_count[14]),
    .I1(\location_Madd__add0000_Result<15>11_1659 ),
    .O(\location_Madd__add0000_Result<15>13_1661 )
  );
  AND2   \location_Madd__add0000_Result<15>14  (
    .I0(location_or0001),
    .I1(\location_Madd__add0000_Result<15>12_1660 ),
    .O(\location_Madd__add0000_Result<15>14_1662 )
  );
  OR3   \location_Madd__add0000_Result<15>15  (
    .I0(\location_Madd__add0000_Result<15>13_1661 ),
    .I1(N9),
    .I2(\location_Madd__add0000_Result<15>14_1662 ),
    .O(N4)
  );
  INV   \location_Madd__add0000_Result<3>11  (
    .I(location_or0001),
    .O(\location_Madd__add0000_Result<3>11_1680 )
  );
  INV   \location_Madd__add0000_Result<3>12  (
    .I(NlwRenamedSig_OI_count[2]),
    .O(\location_Madd__add0000_Result<3>12_1681 )
  );
  AND2   \location_Madd__add0000_Result<3>13  (
    .I0(NlwRenamedSig_OI_count[2]),
    .I1(\location_Madd__add0000_Result<3>11_1680 ),
    .O(\location_Madd__add0000_Result<3>13_1682 )
  );
  AND2   \location_Madd__add0000_Result<3>14  (
    .I0(location_or0001),
    .I1(\location_Madd__add0000_Result<3>12_1681 ),
    .O(\location_Madd__add0000_Result<3>14_1683 )
  );
  OR3   \location_Madd__add0000_Result<3>15  (
    .I0(\location_Madd__add0000_Result<3>13_1682 ),
    .I1(N5),
    .I2(\location_Madd__add0000_Result<3>14_1683 ),
    .O(N0)
  );
  INV   \location_Madd__add0000_Result<6>11  (
    .I(location_or0001),
    .O(\location_Madd__add0000_Result<6>11_1701 )
  );
  INV   \location_Madd__add0000_Result<6>12  (
    .I(NlwRenamedSig_OI_count[5]),
    .O(\location_Madd__add0000_Result<6>12_1702 )
  );
  AND2   \location_Madd__add0000_Result<6>13  (
    .I0(NlwRenamedSig_OI_count[5]),
    .I1(\location_Madd__add0000_Result<6>11_1701 ),
    .O(\location_Madd__add0000_Result<6>13_1703 )
  );
  AND2   \location_Madd__add0000_Result<6>14  (
    .I0(location_or0001),
    .I1(\location_Madd__add0000_Result<6>12_1702 ),
    .O(\location_Madd__add0000_Result<6>14_1704 )
  );
  OR3   \location_Madd__add0000_Result<6>15  (
    .I0(\location_Madd__add0000_Result<6>13_1703 ),
    .I1(N6),
    .I2(\location_Madd__add0000_Result<6>14_1704 ),
    .O(N1)
  );
  INV   \location_Madd__add0000_Result<9>11  (
    .I(location_or0001),
    .O(\location_Madd__add0000_Result<9>11_1722 )
  );
  INV   \location_Madd__add0000_Result<9>12  (
    .I(NlwRenamedSig_OI_count[8]),
    .O(\location_Madd__add0000_Result<9>12_1723 )
  );
  AND2   \location_Madd__add0000_Result<9>13  (
    .I0(NlwRenamedSig_OI_count[8]),
    .I1(\location_Madd__add0000_Result<9>11_1722 ),
    .O(\location_Madd__add0000_Result<9>13_1724 )
  );
  AND2   \location_Madd__add0000_Result<9>14  (
    .I0(location_or0001),
    .I1(\location_Madd__add0000_Result<9>12_1723 ),
    .O(\location_Madd__add0000_Result<9>14_1725 )
  );
  OR3   \location_Madd__add0000_Result<9>15  (
    .I0(\location_Madd__add0000_Result<9>13_1724 ),
    .I1(N7),
    .I2(\location_Madd__add0000_Result<9>14_1725 ),
    .O(N21)
  );
  INV   \location_Madd__add0000_Result<11>111  (
    .I(NlwRenamedSig_OI_count[10]),
    .O(\location_Madd__add0000_Result<11>11_1629 )
  );
  INV   \location_Madd__add0000_Result<11>112  (
    .I(\location_Madd__add0000_CARRY_IN[10] ),
    .O(\location_Madd__add0000_Result<11>111_1630 )
  );
  OR2   \location_Madd__add0000_Result<11>113  (
    .I0(\location_Madd__add0000_Result<11>11_1629 ),
    .I1(\location_Madd__add0000_Result<11>111_1630 ),
    .O(N19)
  );
  INV   \location_Madd__add0000_Result<14>111  (
    .I(NlwRenamedSig_OI_count[13]),
    .O(\location_Madd__add0000_Result<14>11_1650 )
  );
  INV   \location_Madd__add0000_Result<14>112  (
    .I(\location_Madd__add0000_CARRY_IN[13] ),
    .O(\location_Madd__add0000_Result<14>111_1651 )
  );
  OR2   \location_Madd__add0000_Result<14>113  (
    .I0(\location_Madd__add0000_Result<14>11_1650 ),
    .I1(\location_Madd__add0000_Result<14>111_1651 ),
    .O(N20)
  );
  INV   \location_Madd__add0000_Result<2>111  (
    .I(NlwRenamedSig_OI_count[0]),
    .O(\location_Madd__add0000_Result<2>11_1671 )
  );
  INV   \location_Madd__add0000_Result<2>112  (
    .I(NlwRenamedSig_OI_count[1]),
    .O(\location_Madd__add0000_Result<2>111_1672 )
  );
  OR2   \location_Madd__add0000_Result<2>113  (
    .I0(\location_Madd__add0000_Result<2>11_1671 ),
    .I1(\location_Madd__add0000_Result<2>111_1672 ),
    .O(N211)
  );
  INV   \location_Madd__add0000_Result<5>111  (
    .I(NlwRenamedSig_OI_count[4]),
    .O(\location_Madd__add0000_Result<5>11_1692 )
  );
  INV   \location_Madd__add0000_Result<5>112  (
    .I(\location_Madd__add0000_CARRY_IN[4] ),
    .O(\location_Madd__add0000_Result<5>111_1693 )
  );
  OR2   \location_Madd__add0000_Result<5>113  (
    .I0(\location_Madd__add0000_Result<5>11_1692 ),
    .I1(\location_Madd__add0000_Result<5>111_1693 ),
    .O(N22)
  );
  INV   \location_Madd__add0000_Result<8>111  (
    .I(NlwRenamedSig_OI_count[7]),
    .O(\location_Madd__add0000_Result<8>11_1713 )
  );
  INV   \location_Madd__add0000_Result<8>112  (
    .I(\location_Madd__add0000_CARRY_IN[7] ),
    .O(\location_Madd__add0000_Result<8>111_1714 )
  );
  OR2   \location_Madd__add0000_Result<8>113  (
    .I0(\location_Madd__add0000_Result<8>11_1713 ),
    .I1(\location_Madd__add0000_Result<8>111_1714 ),
    .O(N23)
  );
  OR2   \location_Madd__add0000_Result<11>121  (
    .I0(NlwRenamedSig_OI_count[10]),
    .I1(\location_Madd__add0000_CARRY_IN[10] ),
    .O(N24)
  );
  AND2   \location_Madd__add0000_Result<11>11  (
    .I0(location_or0001),
    .I1(N19),
    .O(\location_Madd__add0000_Result<11>12_1631 )
  );
  INV   \location_Madd__add0000_Result<11>12  (
    .I(location_or0001),
    .O(\location_Madd__add0000_Result<11>13_1632 )
  );
  AND2   \location_Madd__add0000_Result<11>13  (
    .I0(N24),
    .I1(\location_Madd__add0000_Result<11>13_1632 ),
    .O(\location_Madd__add0000_Result<11>14_1633 )
  );
  OR2   \location_Madd__add0000_Result<11>14  (
    .I0(\location_Madd__add0000_Result<11>12_1631 ),
    .I1(\location_Madd__add0000_Result<11>14_1633 ),
    .O(N8)
  );
  OR2   \location_Madd__add0000_Result<14>121  (
    .I0(NlwRenamedSig_OI_count[13]),
    .I1(\location_Madd__add0000_CARRY_IN[13] ),
    .O(N25)
  );
  AND2   \location_Madd__add0000_Result<14>11  (
    .I0(location_or0001),
    .I1(N20),
    .O(\location_Madd__add0000_Result<14>12_1652 )
  );
  INV   \location_Madd__add0000_Result<14>12  (
    .I(location_or0001),
    .O(\location_Madd__add0000_Result<14>13_1653 )
  );
  AND2   \location_Madd__add0000_Result<14>13  (
    .I0(N25),
    .I1(\location_Madd__add0000_Result<14>13_1653 ),
    .O(\location_Madd__add0000_Result<14>14_1654 )
  );
  OR2   \location_Madd__add0000_Result<14>14  (
    .I0(\location_Madd__add0000_Result<14>12_1652 ),
    .I1(\location_Madd__add0000_Result<14>14_1654 ),
    .O(N9)
  );
  OR2   \location_Madd__add0000_Result<2>121  (
    .I0(NlwRenamedSig_OI_count[0]),
    .I1(NlwRenamedSig_OI_count[1]),
    .O(N26)
  );
  AND2   \location_Madd__add0000_Result<2>11  (
    .I0(location_or0001),
    .I1(N211),
    .O(\location_Madd__add0000_Result<2>12_1673 )
  );
  INV   \location_Madd__add0000_Result<2>12  (
    .I(location_or0001),
    .O(\location_Madd__add0000_Result<2>13_1674 )
  );
  AND2   \location_Madd__add0000_Result<2>13  (
    .I0(N26),
    .I1(\location_Madd__add0000_Result<2>13_1674 ),
    .O(\location_Madd__add0000_Result<2>14_1675 )
  );
  OR2   \location_Madd__add0000_Result<2>14  (
    .I0(\location_Madd__add0000_Result<2>12_1673 ),
    .I1(\location_Madd__add0000_Result<2>14_1675 ),
    .O(N5)
  );
  OR2   \location_Madd__add0000_Result<5>121  (
    .I0(NlwRenamedSig_OI_count[4]),
    .I1(\location_Madd__add0000_CARRY_IN[4] ),
    .O(N27)
  );
  AND2   \location_Madd__add0000_Result<5>11  (
    .I0(location_or0001),
    .I1(N22),
    .O(\location_Madd__add0000_Result<5>12_1694 )
  );
  INV   \location_Madd__add0000_Result<5>12  (
    .I(location_or0001),
    .O(\location_Madd__add0000_Result<5>13_1695 )
  );
  AND2   \location_Madd__add0000_Result<5>13  (
    .I0(N27),
    .I1(\location_Madd__add0000_Result<5>13_1695 ),
    .O(\location_Madd__add0000_Result<5>14_1696 )
  );
  OR2   \location_Madd__add0000_Result<5>14  (
    .I0(\location_Madd__add0000_Result<5>12_1694 ),
    .I1(\location_Madd__add0000_Result<5>14_1696 ),
    .O(N6)
  );
  OR2   \location_Madd__add0000_Result<8>121  (
    .I0(NlwRenamedSig_OI_count[7]),
    .I1(\location_Madd__add0000_CARRY_IN[7] ),
    .O(N28)
  );
  AND2   \location_Madd__add0000_Result<8>11  (
    .I0(location_or0001),
    .I1(N23),
    .O(\location_Madd__add0000_Result<8>12_1715 )
  );
  INV   \location_Madd__add0000_Result<8>12  (
    .I(location_or0001),
    .O(\location_Madd__add0000_Result<8>13_1716 )
  );
  AND2   \location_Madd__add0000_Result<8>13  (
    .I0(N28),
    .I1(\location_Madd__add0000_Result<8>13_1716 ),
    .O(\location_Madd__add0000_Result<8>14_1717 )
  );
  OR2   \location_Madd__add0000_Result<8>14  (
    .I0(\location_Madd__add0000_Result<8>12_1715 ),
    .I1(\location_Madd__add0000_Result<8>14_1717 ),
    .O(N7)
  );
  AND3   SFDecomp_781 (
    .I0(NlwRenamedSig_OI_count[0]),
    .I1(NlwRenamedSig_OI_count[1]),
    .I2(NlwRenamedSig_OI_count[2]),
    .O(SFDecomp_78)
  );
  AND3   SFDecomp_791 (
    .I0(NlwRenamedSig_OI_count[4]),
    .I1(NlwRenamedSig_OI_count[5]),
    .I2(NlwRenamedSig_OI_count[6]),
    .O(SFDecomp_79)
  );
  AND3   SFDecomp_801 (
    .I0(NlwRenamedSig_OI_count[7]),
    .I1(NlwRenamedSig_OI_count[8]),
    .I2(NlwRenamedSig_OI_count[9]),
    .O(SFDecomp_80)
  );
  AND3   SFDecomp_811 (
    .I0(NlwRenamedSig_OI_count[10]),
    .I1(NlwRenamedSig_OI_count[11]),
    .I2(NlwRenamedSig_OI_count[12]),
    .O(SFDecomp_81)
  );
endmodule

module Counter (
  sense, ce, Reset, updown, Zero, Sclk, count
);
  input sense;
  input ce;
  input Reset;
  input updown;
  input Zero;
  input Sclk;
  output [15 : 0] count;
  wire N0;
  wire N1;
  wire N10;
  wire N11;
  wire N12;
  wire N13;
  wire N14;
  wire N15;
  wire N16;
  wire N17;
  wire N18;
  wire N19;
  wire N2;
  wire N20;
  wire N21;
  wire N211;
  wire N22;
  wire N23;
  wire N24;
  wire N25;
  wire N26;
  wire N27;
  wire N28;
  wire N31;
  wire N4;
  wire N5;
  wire N6;
  wire N7;
  wire N8;
  wire N9;
  wire SFDecomp_78;
  wire SFDecomp_79;
  wire SFDecomp_80;
  wire SFDecomp_81;
  wire location_0__and0000;
  wire location_0__and00001_1348;
  wire location_0__and00002_1349;
  wire location_0__or0000;
  wire location_10__and0000;
  wire location_10__and00001_1352;
  wire location_11__and0000;
  wire location_11__and00001_1354;
  wire location_12__and0000;
  wire location_12__and00001_1356;
  wire location_13__and0000;
  wire location_13__and00001_1358;
  wire location_14__and0000;
  wire location_14__and00001_1360;
  wire location_15__and0000;
  wire location_15__and00001_1362;
  wire location_1__and0000;
  wire location_1__and00001_1364;
  wire location_2__and0000;
  wire location_2__and00001_1366;
  wire location_3__and0000;
  wire location_3__and00001_1368;
  wire location_4__and0000;
  wire location_4__and00001_1370;
  wire location_5__and0000;
  wire location_5__and00001_1372;
  wire location_6__and0000;
  wire location_6__and00001_1374;
  wire location_7__and0000;
  wire location_7__and00001_1376;
  wire location_8__and0000;
  wire location_8__and00001_1378;
  wire location_9__and0000;
  wire location_9__and00001_1380;
  wire \location_Madd__add0000_CARRY_IN[10] ;
  wire \location_Madd__add0000_CARRY_IN<10>1_1382 ;
  wire \location_Madd__add0000_CARRY_IN<10>2_1383 ;
  wire \location_Madd__add0000_CARRY_IN<10>3_1384 ;
  wire \location_Madd__add0000_CARRY_IN[13] ;
  wire \location_Madd__add0000_CARRY_IN<13>1_1386 ;
  wire \location_Madd__add0000_CARRY_IN<13>2_1387 ;
  wire \location_Madd__add0000_CARRY_IN<13>3_1388 ;
  wire \location_Madd__add0000_CARRY_IN[4] ;
  wire \location_Madd__add0000_CARRY_IN<4>1_1390 ;
  wire \location_Madd__add0000_CARRY_IN<4>2_1391 ;
  wire \location_Madd__add0000_CARRY_IN<4>3_1392 ;
  wire \location_Madd__add0000_CARRY_IN[7] ;
  wire \location_Madd__add0000_CARRY_IN<7>1_1394 ;
  wire \location_Madd__add0000_CARRY_IN<7>2_1395 ;
  wire \location_Madd__add0000_CARRY_IN<7>3_1396 ;
  wire \location_Madd__add0000_Result<10>1_1398 ;
  wire \location_Madd__add0000_Result<10>2_1399 ;
  wire \location_Madd__add0000_Result<10>3_1400 ;
  wire \location_Madd__add0000_Result<11>1 ;
  wire \location_Madd__add0000_Result<11>11_1403 ;
  wire \location_Madd__add0000_Result<11>111_1404 ;
  wire \location_Madd__add0000_Result<11>12_1405 ;
  wire \location_Madd__add0000_Result<11>13_1406 ;
  wire \location_Madd__add0000_Result<11>14_1407 ;
  wire \location_Madd__add0000_Result<11>2_1408 ;
  wire \location_Madd__add0000_Result<11>3_1409 ;
  wire \location_Madd__add0000_Result<12>1 ;
  wire \location_Madd__add0000_Result<12>11_1412 ;
  wire \location_Madd__add0000_Result<12>12_1413 ;
  wire \location_Madd__add0000_Result<12>13_1414 ;
  wire \location_Madd__add0000_Result<12>14_1415 ;
  wire \location_Madd__add0000_Result<12>2_1416 ;
  wire \location_Madd__add0000_Result<12>3_1417 ;
  wire \location_Madd__add0000_Result<13>1_1419 ;
  wire \location_Madd__add0000_Result<13>2_1420 ;
  wire \location_Madd__add0000_Result<13>3_1421 ;
  wire \location_Madd__add0000_Result<14>1 ;
  wire \location_Madd__add0000_Result<14>11_1424 ;
  wire \location_Madd__add0000_Result<14>111_1425 ;
  wire \location_Madd__add0000_Result<14>12_1426 ;
  wire \location_Madd__add0000_Result<14>13_1427 ;
  wire \location_Madd__add0000_Result<14>14_1428 ;
  wire \location_Madd__add0000_Result<14>2_1429 ;
  wire \location_Madd__add0000_Result<14>3_1430 ;
  wire \location_Madd__add0000_Result<15>1 ;
  wire \location_Madd__add0000_Result<15>11_1433 ;
  wire \location_Madd__add0000_Result<15>12_1434 ;
  wire \location_Madd__add0000_Result<15>13_1435 ;
  wire \location_Madd__add0000_Result<15>14_1436 ;
  wire \location_Madd__add0000_Result<15>2_1437 ;
  wire \location_Madd__add0000_Result<15>3_1438 ;
  wire \location_Madd__add0000_Result<1>1_1440 ;
  wire \location_Madd__add0000_Result<1>2_1441 ;
  wire \location_Madd__add0000_Result<1>3_1442 ;
  wire \location_Madd__add0000_Result<2>1 ;
  wire \location_Madd__add0000_Result<2>11_1445 ;
  wire \location_Madd__add0000_Result<2>111_1446 ;
  wire \location_Madd__add0000_Result<2>12_1447 ;
  wire \location_Madd__add0000_Result<2>13_1448 ;
  wire \location_Madd__add0000_Result<2>14_1449 ;
  wire \location_Madd__add0000_Result<2>2_1450 ;
  wire \location_Madd__add0000_Result<2>3_1451 ;
  wire \location_Madd__add0000_Result<3>1 ;
  wire \location_Madd__add0000_Result<3>11_1454 ;
  wire \location_Madd__add0000_Result<3>12_1455 ;
  wire \location_Madd__add0000_Result<3>13_1456 ;
  wire \location_Madd__add0000_Result<3>14_1457 ;
  wire \location_Madd__add0000_Result<3>2_1458 ;
  wire \location_Madd__add0000_Result<3>3_1459 ;
  wire \location_Madd__add0000_Result<4>1_1461 ;
  wire \location_Madd__add0000_Result<4>2_1462 ;
  wire \location_Madd__add0000_Result<4>3_1463 ;
  wire \location_Madd__add0000_Result<5>1 ;
  wire \location_Madd__add0000_Result<5>11_1466 ;
  wire \location_Madd__add0000_Result<5>111_1467 ;
  wire \location_Madd__add0000_Result<5>12_1468 ;
  wire \location_Madd__add0000_Result<5>13_1469 ;
  wire \location_Madd__add0000_Result<5>14_1470 ;
  wire \location_Madd__add0000_Result<5>2_1471 ;
  wire \location_Madd__add0000_Result<5>3_1472 ;
  wire \location_Madd__add0000_Result<6>1 ;
  wire \location_Madd__add0000_Result<6>11_1475 ;
  wire \location_Madd__add0000_Result<6>12_1476 ;
  wire \location_Madd__add0000_Result<6>13_1477 ;
  wire \location_Madd__add0000_Result<6>14_1478 ;
  wire \location_Madd__add0000_Result<6>2_1479 ;
  wire \location_Madd__add0000_Result<6>3_1480 ;
  wire \location_Madd__add0000_Result<7>1_1482 ;
  wire \location_Madd__add0000_Result<7>2_1483 ;
  wire \location_Madd__add0000_Result<7>3_1484 ;
  wire \location_Madd__add0000_Result<8>1 ;
  wire \location_Madd__add0000_Result<8>11_1487 ;
  wire \location_Madd__add0000_Result<8>111_1488 ;
  wire \location_Madd__add0000_Result<8>12_1489 ;
  wire \location_Madd__add0000_Result<8>13_1490 ;
  wire \location_Madd__add0000_Result<8>14_1491 ;
  wire \location_Madd__add0000_Result<8>2_1492 ;
  wire \location_Madd__add0000_Result<8>3_1493 ;
  wire \location_Madd__add0000_Result<9>1 ;
  wire \location_Madd__add0000_Result<9>11_1496 ;
  wire \location_Madd__add0000_Result<9>12_1497 ;
  wire \location_Madd__add0000_Result<9>13_1498 ;
  wire \location_Madd__add0000_Result<9>14_1499 ;
  wire \location_Madd__add0000_Result<9>2_1500 ;
  wire \location_Madd__add0000_Result<9>3_1501 ;
  wire location_or0001;
  wire [15 : 0] NlwRenamedSig_OI_count;
  wire [15 : 1] location_Madd__add0000_Result;
  wire [15 : 1] location__add0000;
  assign
    count[15] = NlwRenamedSig_OI_count[15],
    count[14] = NlwRenamedSig_OI_count[14],
    count[13] = NlwRenamedSig_OI_count[13],
    count[12] = NlwRenamedSig_OI_count[12],
    count[11] = NlwRenamedSig_OI_count[11],
    count[10] = NlwRenamedSig_OI_count[10],
    count[9] = NlwRenamedSig_OI_count[9],
    count[8] = NlwRenamedSig_OI_count[8],
    count[7] = NlwRenamedSig_OI_count[7],
    count[6] = NlwRenamedSig_OI_count[6],
    count[5] = NlwRenamedSig_OI_count[5],
    count[4] = NlwRenamedSig_OI_count[4],
    count[3] = NlwRenamedSig_OI_count[3],
    count[2] = NlwRenamedSig_OI_count[2],
    count[1] = NlwRenamedSig_OI_count[1],
    count[0] = NlwRenamedSig_OI_count[0];
  FDCE   location_15 (
    .CE(location_0__or0000),
    .CLR(N2),
    .C(Sclk),
    .D(location_15__and0000),
    .Q(NlwRenamedSig_OI_count[15])
  );
  FDCE   location_14 (
    .CE(location_0__or0000),
    .CLR(N2),
    .C(Sclk),
    .D(location_14__and0000),
    .Q(NlwRenamedSig_OI_count[14])
  );
  FDCE   location_13 (
    .CE(location_0__or0000),
    .CLR(N2),
    .C(Sclk),
    .D(location_13__and0000),
    .Q(NlwRenamedSig_OI_count[13])
  );
  FDCE   location_12 (
    .CE(location_0__or0000),
    .CLR(N2),
    .C(Sclk),
    .D(location_12__and0000),
    .Q(NlwRenamedSig_OI_count[12])
  );
  FDCE   location_11 (
    .CE(location_0__or0000),
    .CLR(N2),
    .C(Sclk),
    .D(location_11__and0000),
    .Q(NlwRenamedSig_OI_count[11])
  );
  FDCE   location_10 (
    .CE(location_0__or0000),
    .CLR(N2),
    .C(Sclk),
    .D(location_10__and0000),
    .Q(NlwRenamedSig_OI_count[10])
  );
  FDCE   location_9 (
    .CE(location_0__or0000),
    .CLR(N2),
    .C(Sclk),
    .D(location_9__and0000),
    .Q(NlwRenamedSig_OI_count[9])
  );
  FDCE   location_8 (
    .CE(location_0__or0000),
    .CLR(N2),
    .C(Sclk),
    .D(location_8__and0000),
    .Q(NlwRenamedSig_OI_count[8])
  );
  FDCE   location_7 (
    .CE(location_0__or0000),
    .CLR(N2),
    .C(Sclk),
    .D(location_7__and0000),
    .Q(NlwRenamedSig_OI_count[7])
  );
  FDCE   location_6 (
    .CE(location_0__or0000),
    .CLR(N2),
    .C(Sclk),
    .D(location_6__and0000),
    .Q(NlwRenamedSig_OI_count[6])
  );
  FDCE   location_5 (
    .CE(location_0__or0000),
    .CLR(N2),
    .C(Sclk),
    .D(location_5__and0000),
    .Q(NlwRenamedSig_OI_count[5])
  );
  FDCE   location_4 (
    .CE(location_0__or0000),
    .CLR(N2),
    .C(Sclk),
    .D(location_4__and0000),
    .Q(NlwRenamedSig_OI_count[4])
  );
  FDCE   location_3 (
    .CE(location_0__or0000),
    .CLR(N2),
    .C(Sclk),
    .D(location_3__and0000),
    .Q(NlwRenamedSig_OI_count[3])
  );
  FDCE   location_2 (
    .CE(location_0__or0000),
    .CLR(N2),
    .C(Sclk),
    .D(location_2__and0000),
    .Q(NlwRenamedSig_OI_count[2])
  );
  FDCE   location_1 (
    .CE(location_0__or0000),
    .CLR(N2),
    .C(Sclk),
    .D(location_1__and0000),
    .Q(NlwRenamedSig_OI_count[1])
  );
  FDCE   location_0 (
    .CE(location_0__or0000),
    .CLR(N2),
    .C(Sclk),
    .D(location_0__and0000),
    .Q(NlwRenamedSig_OI_count[0])
  );
  GND   XST_GND (
    .G(N2)
  );
  INV   location_15__and00001 (
    .I(Reset),
    .O(location_15__and00001_1362)
  );
  AND2   location_15__and00002 (
    .I0(location__add0000[15]),
    .I1(location_15__and00001_1362),
    .O(location_15__and0000)
  );
  INV   location_14__and00001 (
    .I(Reset),
    .O(location_14__and00001_1360)
  );
  AND2   location_14__and00002 (
    .I0(location__add0000[14]),
    .I1(location_14__and00001_1360),
    .O(location_14__and0000)
  );
  INV   location_13__and00001 (
    .I(Reset),
    .O(location_13__and00001_1358)
  );
  AND2   location_13__and00002 (
    .I0(location__add0000[13]),
    .I1(location_13__and00001_1358),
    .O(location_13__and0000)
  );
  INV   location_12__and00001 (
    .I(Reset),
    .O(location_12__and00001_1356)
  );
  AND2   location_12__and00002 (
    .I0(location__add0000[12]),
    .I1(location_12__and00001_1356),
    .O(location_12__and0000)
  );
  INV   location_11__and00001 (
    .I(Reset),
    .O(location_11__and00001_1354)
  );
  AND2   location_11__and00002 (
    .I0(location__add0000[11]),
    .I1(location_11__and00001_1354),
    .O(location_11__and0000)
  );
  INV   location_10__and00001 (
    .I(Reset),
    .O(location_10__and00001_1352)
  );
  AND2   location_10__and00002 (
    .I0(location__add0000[10]),
    .I1(location_10__and00001_1352),
    .O(location_10__and0000)
  );
  INV   location_9__and00001 (
    .I(Reset),
    .O(location_9__and00001_1380)
  );
  AND2   location_9__and00002 (
    .I0(location__add0000[9]),
    .I1(location_9__and00001_1380),
    .O(location_9__and0000)
  );
  INV   location_8__and00001 (
    .I(Reset),
    .O(location_8__and00001_1378)
  );
  AND2   location_8__and00002 (
    .I0(location__add0000[8]),
    .I1(location_8__and00001_1378),
    .O(location_8__and0000)
  );
  INV   location_7__and00001 (
    .I(Reset),
    .O(location_7__and00001_1376)
  );
  AND2   location_7__and00002 (
    .I0(location__add0000[7]),
    .I1(location_7__and00001_1376),
    .O(location_7__and0000)
  );
  INV   location_6__and00001 (
    .I(Reset),
    .O(location_6__and00001_1374)
  );
  AND2   location_6__and00002 (
    .I0(location__add0000[6]),
    .I1(location_6__and00001_1374),
    .O(location_6__and0000)
  );
  INV   location_5__and00001 (
    .I(Reset),
    .O(location_5__and00001_1372)
  );
  AND2   location_5__and00002 (
    .I0(location__add0000[5]),
    .I1(location_5__and00001_1372),
    .O(location_5__and0000)
  );
  INV   location_4__and00001 (
    .I(Reset),
    .O(location_4__and00001_1370)
  );
  AND2   location_4__and00002 (
    .I0(location__add0000[4]),
    .I1(location_4__and00001_1370),
    .O(location_4__and0000)
  );
  INV   location_3__and00001 (
    .I(Reset),
    .O(location_3__and00001_1368)
  );
  AND2   location_3__and00002 (
    .I0(location__add0000[3]),
    .I1(location_3__and00001_1368),
    .O(location_3__and0000)
  );
  INV   location_2__and00001 (
    .I(Reset),
    .O(location_2__and00001_1366)
  );
  AND2   location_2__and00002 (
    .I0(location__add0000[2]),
    .I1(location_2__and00001_1366),
    .O(location_2__and0000)
  );
  INV   location_1__and00001 (
    .I(Reset),
    .O(location_1__and00001_1364)
  );
  AND2   location_1__and00002 (
    .I0(location__add0000[1]),
    .I1(location_1__and00001_1364),
    .O(location_1__and0000)
  );
  OR2   location_0__or00001 (
    .I0(ce),
    .I1(Reset),
    .O(location_0__or0000)
  );
  INV   location_0__and00001 (
    .I(Reset),
    .O(location_0__and00001_1348)
  );
  INV   location_0__and00002 (
    .I(NlwRenamedSig_OI_count[0]),
    .O(location_0__and00002_1349)
  );
  AND2   location_0__and00003 (
    .I0(location_0__and00001_1348),
    .I1(location_0__and00002_1349),
    .O(location_0__and0000)
  );
  XOR2   location_or00011 (
    .I0(sense),
    .I1(updown),
    .O(location_or0001)
  );
  AND2   \location_Madd__add0000_Result<3>2  (
    .I0(NlwRenamedSig_OI_count[3]),
    .I1(N0),
    .O(location_Madd__add0000_Result[3])
  );
  INV   \location_Madd__add0000_Result<3>3  (
    .I(NlwRenamedSig_OI_count[3]),
    .O(\location_Madd__add0000_Result<3>1 )
  );
  INV   \location_Madd__add0000_Result<3>4  (
    .I(N0),
    .O(\location_Madd__add0000_Result<3>2_1458 )
  );
  AND2   \location_Madd__add0000_Result<3>5  (
    .I0(\location_Madd__add0000_Result<3>1 ),
    .I1(\location_Madd__add0000_Result<3>2_1458 ),
    .O(\location_Madd__add0000_Result<3>3_1459 )
  );
  OR2   \location_Madd__add0000_Result<3>6  (
    .I0(location_Madd__add0000_Result[3]),
    .I1(\location_Madd__add0000_Result<3>3_1459 ),
    .O(location__add0000[3])
  );
  AND2   \location_Madd__add0000_Result<6>2  (
    .I0(NlwRenamedSig_OI_count[6]),
    .I1(N1),
    .O(location_Madd__add0000_Result[6])
  );
  INV   \location_Madd__add0000_Result<6>3  (
    .I(NlwRenamedSig_OI_count[6]),
    .O(\location_Madd__add0000_Result<6>1 )
  );
  INV   \location_Madd__add0000_Result<6>4  (
    .I(N1),
    .O(\location_Madd__add0000_Result<6>2_1479 )
  );
  AND2   \location_Madd__add0000_Result<6>5  (
    .I0(\location_Madd__add0000_Result<6>1 ),
    .I1(\location_Madd__add0000_Result<6>2_1479 ),
    .O(\location_Madd__add0000_Result<6>3_1480 )
  );
  OR2   \location_Madd__add0000_Result<6>6  (
    .I0(location_Madd__add0000_Result[6]),
    .I1(\location_Madd__add0000_Result<6>3_1480 ),
    .O(location__add0000[6])
  );
  AND2   \location_Madd__add0000_Result<9>2  (
    .I0(NlwRenamedSig_OI_count[9]),
    .I1(N21),
    .O(location_Madd__add0000_Result[9])
  );
  INV   \location_Madd__add0000_Result<9>3  (
    .I(NlwRenamedSig_OI_count[9]),
    .O(\location_Madd__add0000_Result<9>1 )
  );
  INV   \location_Madd__add0000_Result<9>4  (
    .I(N21),
    .O(\location_Madd__add0000_Result<9>2_1500 )
  );
  AND2   \location_Madd__add0000_Result<9>5  (
    .I0(\location_Madd__add0000_Result<9>1 ),
    .I1(\location_Madd__add0000_Result<9>2_1500 ),
    .O(\location_Madd__add0000_Result<9>3_1501 )
  );
  OR2   \location_Madd__add0000_Result<9>6  (
    .I0(location_Madd__add0000_Result[9]),
    .I1(\location_Madd__add0000_Result<9>3_1501 ),
    .O(location__add0000[9])
  );
  AND2   \location_Madd__add0000_Result<12>2  (
    .I0(NlwRenamedSig_OI_count[12]),
    .I1(N31),
    .O(location_Madd__add0000_Result[12])
  );
  INV   \location_Madd__add0000_Result<12>3  (
    .I(NlwRenamedSig_OI_count[12]),
    .O(\location_Madd__add0000_Result<12>1 )
  );
  INV   \location_Madd__add0000_Result<12>4  (
    .I(N31),
    .O(\location_Madd__add0000_Result<12>2_1416 )
  );
  AND2   \location_Madd__add0000_Result<12>5  (
    .I0(\location_Madd__add0000_Result<12>1 ),
    .I1(\location_Madd__add0000_Result<12>2_1416 ),
    .O(\location_Madd__add0000_Result<12>3_1417 )
  );
  OR2   \location_Madd__add0000_Result<12>6  (
    .I0(location_Madd__add0000_Result[12]),
    .I1(\location_Madd__add0000_Result<12>3_1417 ),
    .O(location__add0000[12])
  );
  AND2   \location_Madd__add0000_Result<15>2  (
    .I0(NlwRenamedSig_OI_count[15]),
    .I1(N4),
    .O(location_Madd__add0000_Result[15])
  );
  INV   \location_Madd__add0000_Result<15>3  (
    .I(NlwRenamedSig_OI_count[15]),
    .O(\location_Madd__add0000_Result<15>1 )
  );
  INV   \location_Madd__add0000_Result<15>4  (
    .I(N4),
    .O(\location_Madd__add0000_Result<15>2_1437 )
  );
  AND2   \location_Madd__add0000_Result<15>5  (
    .I0(\location_Madd__add0000_Result<15>1 ),
    .I1(\location_Madd__add0000_Result<15>2_1437 ),
    .O(\location_Madd__add0000_Result<15>3_1438 )
  );
  OR2   \location_Madd__add0000_Result<15>6  (
    .I0(location_Madd__add0000_Result[15]),
    .I1(\location_Madd__add0000_Result<15>3_1438 ),
    .O(location__add0000[15])
  );
  AND2   \location_Madd__add0000_Result<2>2  (
    .I0(NlwRenamedSig_OI_count[2]),
    .I1(N5),
    .O(location_Madd__add0000_Result[2])
  );
  INV   \location_Madd__add0000_Result<2>3  (
    .I(NlwRenamedSig_OI_count[2]),
    .O(\location_Madd__add0000_Result<2>1 )
  );
  INV   \location_Madd__add0000_Result<2>4  (
    .I(N5),
    .O(\location_Madd__add0000_Result<2>2_1450 )
  );
  AND2   \location_Madd__add0000_Result<2>5  (
    .I0(\location_Madd__add0000_Result<2>1 ),
    .I1(\location_Madd__add0000_Result<2>2_1450 ),
    .O(\location_Madd__add0000_Result<2>3_1451 )
  );
  OR2   \location_Madd__add0000_Result<2>6  (
    .I0(location_Madd__add0000_Result[2]),
    .I1(\location_Madd__add0000_Result<2>3_1451 ),
    .O(location__add0000[2])
  );
  AND2   \location_Madd__add0000_Result<5>2  (
    .I0(NlwRenamedSig_OI_count[5]),
    .I1(N6),
    .O(location_Madd__add0000_Result[5])
  );
  INV   \location_Madd__add0000_Result<5>3  (
    .I(NlwRenamedSig_OI_count[5]),
    .O(\location_Madd__add0000_Result<5>1 )
  );
  INV   \location_Madd__add0000_Result<5>4  (
    .I(N6),
    .O(\location_Madd__add0000_Result<5>2_1471 )
  );
  AND2   \location_Madd__add0000_Result<5>5  (
    .I0(\location_Madd__add0000_Result<5>1 ),
    .I1(\location_Madd__add0000_Result<5>2_1471 ),
    .O(\location_Madd__add0000_Result<5>3_1472 )
  );
  OR2   \location_Madd__add0000_Result<5>6  (
    .I0(location_Madd__add0000_Result[5]),
    .I1(\location_Madd__add0000_Result<5>3_1472 ),
    .O(location__add0000[5])
  );
  AND2   \location_Madd__add0000_Result<8>2  (
    .I0(NlwRenamedSig_OI_count[8]),
    .I1(N7),
    .O(location_Madd__add0000_Result[8])
  );
  INV   \location_Madd__add0000_Result<8>3  (
    .I(NlwRenamedSig_OI_count[8]),
    .O(\location_Madd__add0000_Result<8>1 )
  );
  INV   \location_Madd__add0000_Result<8>4  (
    .I(N7),
    .O(\location_Madd__add0000_Result<8>2_1492 )
  );
  AND2   \location_Madd__add0000_Result<8>5  (
    .I0(\location_Madd__add0000_Result<8>1 ),
    .I1(\location_Madd__add0000_Result<8>2_1492 ),
    .O(\location_Madd__add0000_Result<8>3_1493 )
  );
  OR2   \location_Madd__add0000_Result<8>6  (
    .I0(location_Madd__add0000_Result[8]),
    .I1(\location_Madd__add0000_Result<8>3_1493 ),
    .O(location__add0000[8])
  );
  AND2   \location_Madd__add0000_Result<11>2  (
    .I0(NlwRenamedSig_OI_count[11]),
    .I1(N8),
    .O(location_Madd__add0000_Result[11])
  );
  INV   \location_Madd__add0000_Result<11>3  (
    .I(NlwRenamedSig_OI_count[11]),
    .O(\location_Madd__add0000_Result<11>1 )
  );
  INV   \location_Madd__add0000_Result<11>4  (
    .I(N8),
    .O(\location_Madd__add0000_Result<11>2_1408 )
  );
  AND2   \location_Madd__add0000_Result<11>5  (
    .I0(\location_Madd__add0000_Result<11>1 ),
    .I1(\location_Madd__add0000_Result<11>2_1408 ),
    .O(\location_Madd__add0000_Result<11>3_1409 )
  );
  OR2   \location_Madd__add0000_Result<11>6  (
    .I0(location_Madd__add0000_Result[11]),
    .I1(\location_Madd__add0000_Result<11>3_1409 ),
    .O(location__add0000[11])
  );
  AND2   \location_Madd__add0000_Result<14>2  (
    .I0(NlwRenamedSig_OI_count[14]),
    .I1(N9),
    .O(location_Madd__add0000_Result[14])
  );
  INV   \location_Madd__add0000_Result<14>3  (
    .I(NlwRenamedSig_OI_count[14]),
    .O(\location_Madd__add0000_Result<14>1 )
  );
  INV   \location_Madd__add0000_Result<14>4  (
    .I(N9),
    .O(\location_Madd__add0000_Result<14>2_1429 )
  );
  AND2   \location_Madd__add0000_Result<14>5  (
    .I0(\location_Madd__add0000_Result<14>1 ),
    .I1(\location_Madd__add0000_Result<14>2_1429 ),
    .O(\location_Madd__add0000_Result<14>3_1430 )
  );
  OR2   \location_Madd__add0000_Result<14>6  (
    .I0(location_Madd__add0000_Result[14]),
    .I1(\location_Madd__add0000_Result<14>3_1430 ),
    .O(location__add0000[14])
  );
  XOR2   \location_Madd__add0000_Result<13>11  (
    .I0(location_or0001),
    .I1(\location_Madd__add0000_CARRY_IN[13] ),
    .O(N10)
  );
  AND2   \location_Madd__add0000_Result<13>1  (
    .I0(NlwRenamedSig_OI_count[13]),
    .I1(N10),
    .O(location_Madd__add0000_Result[13])
  );
  INV   \location_Madd__add0000_Result<13>2  (
    .I(NlwRenamedSig_OI_count[13]),
    .O(\location_Madd__add0000_Result<13>1_1419 )
  );
  INV   \location_Madd__add0000_Result<13>3  (
    .I(N10),
    .O(\location_Madd__add0000_Result<13>2_1420 )
  );
  AND2   \location_Madd__add0000_Result<13>4  (
    .I0(\location_Madd__add0000_Result<13>1_1419 ),
    .I1(\location_Madd__add0000_Result<13>2_1420 ),
    .O(\location_Madd__add0000_Result<13>3_1421 )
  );
  OR2   \location_Madd__add0000_Result<13>5  (
    .I0(location_Madd__add0000_Result[13]),
    .I1(\location_Madd__add0000_Result<13>3_1421 ),
    .O(location__add0000[13])
  );
  XOR2   \location_Madd__add0000_Result<10>11  (
    .I0(location_or0001),
    .I1(\location_Madd__add0000_CARRY_IN[10] ),
    .O(N11)
  );
  AND2   \location_Madd__add0000_Result<10>1  (
    .I0(NlwRenamedSig_OI_count[10]),
    .I1(N11),
    .O(location_Madd__add0000_Result[10])
  );
  INV   \location_Madd__add0000_Result<10>2  (
    .I(NlwRenamedSig_OI_count[10]),
    .O(\location_Madd__add0000_Result<10>1_1398 )
  );
  INV   \location_Madd__add0000_Result<10>3  (
    .I(N11),
    .O(\location_Madd__add0000_Result<10>2_1399 )
  );
  AND2   \location_Madd__add0000_Result<10>4  (
    .I0(\location_Madd__add0000_Result<10>1_1398 ),
    .I1(\location_Madd__add0000_Result<10>2_1399 ),
    .O(\location_Madd__add0000_Result<10>3_1400 )
  );
  OR2   \location_Madd__add0000_Result<10>5  (
    .I0(location_Madd__add0000_Result[10]),
    .I1(\location_Madd__add0000_Result<10>3_1400 ),
    .O(location__add0000[10])
  );
  XOR2   \location_Madd__add0000_Result<7>11  (
    .I0(location_or0001),
    .I1(\location_Madd__add0000_CARRY_IN[7] ),
    .O(N12)
  );
  AND2   \location_Madd__add0000_Result<7>1  (
    .I0(NlwRenamedSig_OI_count[7]),
    .I1(N12),
    .O(location_Madd__add0000_Result[7])
  );
  INV   \location_Madd__add0000_Result<7>2  (
    .I(NlwRenamedSig_OI_count[7]),
    .O(\location_Madd__add0000_Result<7>1_1482 )
  );
  INV   \location_Madd__add0000_Result<7>3  (
    .I(N12),
    .O(\location_Madd__add0000_Result<7>2_1483 )
  );
  AND2   \location_Madd__add0000_Result<7>4  (
    .I0(\location_Madd__add0000_Result<7>1_1482 ),
    .I1(\location_Madd__add0000_Result<7>2_1483 ),
    .O(\location_Madd__add0000_Result<7>3_1484 )
  );
  OR2   \location_Madd__add0000_Result<7>5  (
    .I0(location_Madd__add0000_Result[7]),
    .I1(\location_Madd__add0000_Result<7>3_1484 ),
    .O(location__add0000[7])
  );
  XOR2   \location_Madd__add0000_Result<4>11  (
    .I0(location_or0001),
    .I1(\location_Madd__add0000_CARRY_IN[4] ),
    .O(N13)
  );
  AND2   \location_Madd__add0000_Result<4>1  (
    .I0(NlwRenamedSig_OI_count[4]),
    .I1(N13),
    .O(location_Madd__add0000_Result[4])
  );
  INV   \location_Madd__add0000_Result<4>2  (
    .I(NlwRenamedSig_OI_count[4]),
    .O(\location_Madd__add0000_Result<4>1_1461 )
  );
  INV   \location_Madd__add0000_Result<4>3  (
    .I(N13),
    .O(\location_Madd__add0000_Result<4>2_1462 )
  );
  AND2   \location_Madd__add0000_Result<4>4  (
    .I0(\location_Madd__add0000_Result<4>1_1461 ),
    .I1(\location_Madd__add0000_Result<4>2_1462 ),
    .O(\location_Madd__add0000_Result<4>3_1463 )
  );
  OR2   \location_Madd__add0000_Result<4>5  (
    .I0(location_Madd__add0000_Result[4]),
    .I1(\location_Madd__add0000_Result<4>3_1463 ),
    .O(location__add0000[4])
  );
  XOR2   \location_Madd__add0000_Result<1>11  (
    .I0(location_or0001),
    .I1(NlwRenamedSig_OI_count[1]),
    .O(N14)
  );
  AND2   \location_Madd__add0000_Result<1>1  (
    .I0(NlwRenamedSig_OI_count[0]),
    .I1(N14),
    .O(location_Madd__add0000_Result[1])
  );
  INV   \location_Madd__add0000_Result<1>2  (
    .I(NlwRenamedSig_OI_count[0]),
    .O(\location_Madd__add0000_Result<1>1_1440 )
  );
  INV   \location_Madd__add0000_Result<1>3  (
    .I(N14),
    .O(\location_Madd__add0000_Result<1>2_1441 )
  );
  AND2   \location_Madd__add0000_Result<1>4  (
    .I0(\location_Madd__add0000_Result<1>1_1440 ),
    .I1(\location_Madd__add0000_Result<1>2_1441 ),
    .O(\location_Madd__add0000_Result<1>3_1442 )
  );
  OR2   \location_Madd__add0000_Result<1>5  (
    .I0(location_Madd__add0000_Result[1]),
    .I1(\location_Madd__add0000_Result<1>3_1442 ),
    .O(location__add0000[1])
  );
  OR4   \location_Madd__add0000_CARRY_IN<4>11  (
    .I0(NlwRenamedSig_OI_count[0]),
    .I1(NlwRenamedSig_OI_count[1]),
    .I2(NlwRenamedSig_OI_count[2]),
    .I3(NlwRenamedSig_OI_count[3]),
    .O(N15)
  );
  AND2   \location_Madd__add0000_CARRY_IN<4>1  (
    .I0(SFDecomp_78),
    .I1(NlwRenamedSig_OI_count[3]),
    .O(\location_Madd__add0000_CARRY_IN<4>1_1390 )
  );
  INV   \location_Madd__add0000_CARRY_IN<4>2  (
    .I(location_or0001),
    .O(\location_Madd__add0000_CARRY_IN<4>2_1391 )
  );
  AND2   \location_Madd__add0000_CARRY_IN<4>3  (
    .I0(N15),
    .I1(\location_Madd__add0000_CARRY_IN<4>2_1391 ),
    .O(\location_Madd__add0000_CARRY_IN<4>3_1392 )
  );
  OR2   \location_Madd__add0000_CARRY_IN<4>4  (
    .I0(\location_Madd__add0000_CARRY_IN<4>1_1390 ),
    .I1(\location_Madd__add0000_CARRY_IN<4>3_1392 ),
    .O(\location_Madd__add0000_CARRY_IN[4] )
  );
  OR4   \location_Madd__add0000_CARRY_IN<7>11  (
    .I0(NlwRenamedSig_OI_count[4]),
    .I1(NlwRenamedSig_OI_count[5]),
    .I2(NlwRenamedSig_OI_count[6]),
    .I3(\location_Madd__add0000_CARRY_IN[4] ),
    .O(N16)
  );
  AND2   \location_Madd__add0000_CARRY_IN<7>1  (
    .I0(SFDecomp_79),
    .I1(\location_Madd__add0000_CARRY_IN[4] ),
    .O(\location_Madd__add0000_CARRY_IN<7>1_1394 )
  );
  INV   \location_Madd__add0000_CARRY_IN<7>2  (
    .I(location_or0001),
    .O(\location_Madd__add0000_CARRY_IN<7>2_1395 )
  );
  AND2   \location_Madd__add0000_CARRY_IN<7>3  (
    .I0(N16),
    .I1(\location_Madd__add0000_CARRY_IN<7>2_1395 ),
    .O(\location_Madd__add0000_CARRY_IN<7>3_1396 )
  );
  OR2   \location_Madd__add0000_CARRY_IN<7>4  (
    .I0(\location_Madd__add0000_CARRY_IN<7>1_1394 ),
    .I1(\location_Madd__add0000_CARRY_IN<7>3_1396 ),
    .O(\location_Madd__add0000_CARRY_IN[7] )
  );
  OR4   \location_Madd__add0000_CARRY_IN<10>11  (
    .I0(NlwRenamedSig_OI_count[7]),
    .I1(NlwRenamedSig_OI_count[8]),
    .I2(NlwRenamedSig_OI_count[9]),
    .I3(\location_Madd__add0000_CARRY_IN[7] ),
    .O(N17)
  );
  AND2   \location_Madd__add0000_CARRY_IN<10>1  (
    .I0(SFDecomp_80),
    .I1(\location_Madd__add0000_CARRY_IN[7] ),
    .O(\location_Madd__add0000_CARRY_IN<10>1_1382 )
  );
  INV   \location_Madd__add0000_CARRY_IN<10>2  (
    .I(location_or0001),
    .O(\location_Madd__add0000_CARRY_IN<10>2_1383 )
  );
  AND2   \location_Madd__add0000_CARRY_IN<10>3  (
    .I0(N17),
    .I1(\location_Madd__add0000_CARRY_IN<10>2_1383 ),
    .O(\location_Madd__add0000_CARRY_IN<10>3_1384 )
  );
  OR2   \location_Madd__add0000_CARRY_IN<10>4  (
    .I0(\location_Madd__add0000_CARRY_IN<10>1_1382 ),
    .I1(\location_Madd__add0000_CARRY_IN<10>3_1384 ),
    .O(\location_Madd__add0000_CARRY_IN[10] )
  );
  OR4   \location_Madd__add0000_CARRY_IN<13>11  (
    .I0(NlwRenamedSig_OI_count[10]),
    .I1(NlwRenamedSig_OI_count[11]),
    .I2(NlwRenamedSig_OI_count[12]),
    .I3(\location_Madd__add0000_CARRY_IN[10] ),
    .O(N18)
  );
  AND2   \location_Madd__add0000_CARRY_IN<13>1  (
    .I0(SFDecomp_81),
    .I1(\location_Madd__add0000_CARRY_IN[10] ),
    .O(\location_Madd__add0000_CARRY_IN<13>1_1386 )
  );
  INV   \location_Madd__add0000_CARRY_IN<13>2  (
    .I(location_or0001),
    .O(\location_Madd__add0000_CARRY_IN<13>2_1387 )
  );
  AND2   \location_Madd__add0000_CARRY_IN<13>3  (
    .I0(N18),
    .I1(\location_Madd__add0000_CARRY_IN<13>2_1387 ),
    .O(\location_Madd__add0000_CARRY_IN<13>3_1388 )
  );
  OR2   \location_Madd__add0000_CARRY_IN<13>4  (
    .I0(\location_Madd__add0000_CARRY_IN<13>1_1386 ),
    .I1(\location_Madd__add0000_CARRY_IN<13>3_1388 ),
    .O(\location_Madd__add0000_CARRY_IN[13] )
  );
  INV   \location_Madd__add0000_Result<12>11  (
    .I(location_or0001),
    .O(\location_Madd__add0000_Result<12>11_1412 )
  );
  INV   \location_Madd__add0000_Result<12>12  (
    .I(NlwRenamedSig_OI_count[11]),
    .O(\location_Madd__add0000_Result<12>12_1413 )
  );
  AND2   \location_Madd__add0000_Result<12>13  (
    .I0(NlwRenamedSig_OI_count[11]),
    .I1(\location_Madd__add0000_Result<12>11_1412 ),
    .O(\location_Madd__add0000_Result<12>13_1414 )
  );
  AND2   \location_Madd__add0000_Result<12>14  (
    .I0(location_or0001),
    .I1(\location_Madd__add0000_Result<12>12_1413 ),
    .O(\location_Madd__add0000_Result<12>14_1415 )
  );
  OR3   \location_Madd__add0000_Result<12>15  (
    .I0(\location_Madd__add0000_Result<12>13_1414 ),
    .I1(N8),
    .I2(\location_Madd__add0000_Result<12>14_1415 ),
    .O(N31)
  );
  INV   \location_Madd__add0000_Result<15>11  (
    .I(location_or0001),
    .O(\location_Madd__add0000_Result<15>11_1433 )
  );
  INV   \location_Madd__add0000_Result<15>12  (
    .I(NlwRenamedSig_OI_count[14]),
    .O(\location_Madd__add0000_Result<15>12_1434 )
  );
  AND2   \location_Madd__add0000_Result<15>13  (
    .I0(NlwRenamedSig_OI_count[14]),
    .I1(\location_Madd__add0000_Result<15>11_1433 ),
    .O(\location_Madd__add0000_Result<15>13_1435 )
  );
  AND2   \location_Madd__add0000_Result<15>14  (
    .I0(location_or0001),
    .I1(\location_Madd__add0000_Result<15>12_1434 ),
    .O(\location_Madd__add0000_Result<15>14_1436 )
  );
  OR3   \location_Madd__add0000_Result<15>15  (
    .I0(\location_Madd__add0000_Result<15>13_1435 ),
    .I1(N9),
    .I2(\location_Madd__add0000_Result<15>14_1436 ),
    .O(N4)
  );
  INV   \location_Madd__add0000_Result<3>11  (
    .I(location_or0001),
    .O(\location_Madd__add0000_Result<3>11_1454 )
  );
  INV   \location_Madd__add0000_Result<3>12  (
    .I(NlwRenamedSig_OI_count[2]),
    .O(\location_Madd__add0000_Result<3>12_1455 )
  );
  AND2   \location_Madd__add0000_Result<3>13  (
    .I0(NlwRenamedSig_OI_count[2]),
    .I1(\location_Madd__add0000_Result<3>11_1454 ),
    .O(\location_Madd__add0000_Result<3>13_1456 )
  );
  AND2   \location_Madd__add0000_Result<3>14  (
    .I0(location_or0001),
    .I1(\location_Madd__add0000_Result<3>12_1455 ),
    .O(\location_Madd__add0000_Result<3>14_1457 )
  );
  OR3   \location_Madd__add0000_Result<3>15  (
    .I0(\location_Madd__add0000_Result<3>13_1456 ),
    .I1(N5),
    .I2(\location_Madd__add0000_Result<3>14_1457 ),
    .O(N0)
  );
  INV   \location_Madd__add0000_Result<6>11  (
    .I(location_or0001),
    .O(\location_Madd__add0000_Result<6>11_1475 )
  );
  INV   \location_Madd__add0000_Result<6>12  (
    .I(NlwRenamedSig_OI_count[5]),
    .O(\location_Madd__add0000_Result<6>12_1476 )
  );
  AND2   \location_Madd__add0000_Result<6>13  (
    .I0(NlwRenamedSig_OI_count[5]),
    .I1(\location_Madd__add0000_Result<6>11_1475 ),
    .O(\location_Madd__add0000_Result<6>13_1477 )
  );
  AND2   \location_Madd__add0000_Result<6>14  (
    .I0(location_or0001),
    .I1(\location_Madd__add0000_Result<6>12_1476 ),
    .O(\location_Madd__add0000_Result<6>14_1478 )
  );
  OR3   \location_Madd__add0000_Result<6>15  (
    .I0(\location_Madd__add0000_Result<6>13_1477 ),
    .I1(N6),
    .I2(\location_Madd__add0000_Result<6>14_1478 ),
    .O(N1)
  );
  INV   \location_Madd__add0000_Result<9>11  (
    .I(location_or0001),
    .O(\location_Madd__add0000_Result<9>11_1496 )
  );
  INV   \location_Madd__add0000_Result<9>12  (
    .I(NlwRenamedSig_OI_count[8]),
    .O(\location_Madd__add0000_Result<9>12_1497 )
  );
  AND2   \location_Madd__add0000_Result<9>13  (
    .I0(NlwRenamedSig_OI_count[8]),
    .I1(\location_Madd__add0000_Result<9>11_1496 ),
    .O(\location_Madd__add0000_Result<9>13_1498 )
  );
  AND2   \location_Madd__add0000_Result<9>14  (
    .I0(location_or0001),
    .I1(\location_Madd__add0000_Result<9>12_1497 ),
    .O(\location_Madd__add0000_Result<9>14_1499 )
  );
  OR3   \location_Madd__add0000_Result<9>15  (
    .I0(\location_Madd__add0000_Result<9>13_1498 ),
    .I1(N7),
    .I2(\location_Madd__add0000_Result<9>14_1499 ),
    .O(N21)
  );
  INV   \location_Madd__add0000_Result<11>111  (
    .I(NlwRenamedSig_OI_count[10]),
    .O(\location_Madd__add0000_Result<11>11_1403 )
  );
  INV   \location_Madd__add0000_Result<11>112  (
    .I(\location_Madd__add0000_CARRY_IN[10] ),
    .O(\location_Madd__add0000_Result<11>111_1404 )
  );
  OR2   \location_Madd__add0000_Result<11>113  (
    .I0(\location_Madd__add0000_Result<11>11_1403 ),
    .I1(\location_Madd__add0000_Result<11>111_1404 ),
    .O(N19)
  );
  INV   \location_Madd__add0000_Result<14>111  (
    .I(NlwRenamedSig_OI_count[13]),
    .O(\location_Madd__add0000_Result<14>11_1424 )
  );
  INV   \location_Madd__add0000_Result<14>112  (
    .I(\location_Madd__add0000_CARRY_IN[13] ),
    .O(\location_Madd__add0000_Result<14>111_1425 )
  );
  OR2   \location_Madd__add0000_Result<14>113  (
    .I0(\location_Madd__add0000_Result<14>11_1424 ),
    .I1(\location_Madd__add0000_Result<14>111_1425 ),
    .O(N20)
  );
  INV   \location_Madd__add0000_Result<2>111  (
    .I(NlwRenamedSig_OI_count[0]),
    .O(\location_Madd__add0000_Result<2>11_1445 )
  );
  INV   \location_Madd__add0000_Result<2>112  (
    .I(NlwRenamedSig_OI_count[1]),
    .O(\location_Madd__add0000_Result<2>111_1446 )
  );
  OR2   \location_Madd__add0000_Result<2>113  (
    .I0(\location_Madd__add0000_Result<2>11_1445 ),
    .I1(\location_Madd__add0000_Result<2>111_1446 ),
    .O(N211)
  );
  INV   \location_Madd__add0000_Result<5>111  (
    .I(NlwRenamedSig_OI_count[4]),
    .O(\location_Madd__add0000_Result<5>11_1466 )
  );
  INV   \location_Madd__add0000_Result<5>112  (
    .I(\location_Madd__add0000_CARRY_IN[4] ),
    .O(\location_Madd__add0000_Result<5>111_1467 )
  );
  OR2   \location_Madd__add0000_Result<5>113  (
    .I0(\location_Madd__add0000_Result<5>11_1466 ),
    .I1(\location_Madd__add0000_Result<5>111_1467 ),
    .O(N22)
  );
  INV   \location_Madd__add0000_Result<8>111  (
    .I(NlwRenamedSig_OI_count[7]),
    .O(\location_Madd__add0000_Result<8>11_1487 )
  );
  INV   \location_Madd__add0000_Result<8>112  (
    .I(\location_Madd__add0000_CARRY_IN[7] ),
    .O(\location_Madd__add0000_Result<8>111_1488 )
  );
  OR2   \location_Madd__add0000_Result<8>113  (
    .I0(\location_Madd__add0000_Result<8>11_1487 ),
    .I1(\location_Madd__add0000_Result<8>111_1488 ),
    .O(N23)
  );
  OR2   \location_Madd__add0000_Result<11>121  (
    .I0(NlwRenamedSig_OI_count[10]),
    .I1(\location_Madd__add0000_CARRY_IN[10] ),
    .O(N24)
  );
  AND2   \location_Madd__add0000_Result<11>11  (
    .I0(location_or0001),
    .I1(N19),
    .O(\location_Madd__add0000_Result<11>12_1405 )
  );
  INV   \location_Madd__add0000_Result<11>12  (
    .I(location_or0001),
    .O(\location_Madd__add0000_Result<11>13_1406 )
  );
  AND2   \location_Madd__add0000_Result<11>13  (
    .I0(N24),
    .I1(\location_Madd__add0000_Result<11>13_1406 ),
    .O(\location_Madd__add0000_Result<11>14_1407 )
  );
  OR2   \location_Madd__add0000_Result<11>14  (
    .I0(\location_Madd__add0000_Result<11>12_1405 ),
    .I1(\location_Madd__add0000_Result<11>14_1407 ),
    .O(N8)
  );
  OR2   \location_Madd__add0000_Result<14>121  (
    .I0(NlwRenamedSig_OI_count[13]),
    .I1(\location_Madd__add0000_CARRY_IN[13] ),
    .O(N25)
  );
  AND2   \location_Madd__add0000_Result<14>11  (
    .I0(location_or0001),
    .I1(N20),
    .O(\location_Madd__add0000_Result<14>12_1426 )
  );
  INV   \location_Madd__add0000_Result<14>12  (
    .I(location_or0001),
    .O(\location_Madd__add0000_Result<14>13_1427 )
  );
  AND2   \location_Madd__add0000_Result<14>13  (
    .I0(N25),
    .I1(\location_Madd__add0000_Result<14>13_1427 ),
    .O(\location_Madd__add0000_Result<14>14_1428 )
  );
  OR2   \location_Madd__add0000_Result<14>14  (
    .I0(\location_Madd__add0000_Result<14>12_1426 ),
    .I1(\location_Madd__add0000_Result<14>14_1428 ),
    .O(N9)
  );
  OR2   \location_Madd__add0000_Result<2>121  (
    .I0(NlwRenamedSig_OI_count[0]),
    .I1(NlwRenamedSig_OI_count[1]),
    .O(N26)
  );
  AND2   \location_Madd__add0000_Result<2>11  (
    .I0(location_or0001),
    .I1(N211),
    .O(\location_Madd__add0000_Result<2>12_1447 )
  );
  INV   \location_Madd__add0000_Result<2>12  (
    .I(location_or0001),
    .O(\location_Madd__add0000_Result<2>13_1448 )
  );
  AND2   \location_Madd__add0000_Result<2>13  (
    .I0(N26),
    .I1(\location_Madd__add0000_Result<2>13_1448 ),
    .O(\location_Madd__add0000_Result<2>14_1449 )
  );
  OR2   \location_Madd__add0000_Result<2>14  (
    .I0(\location_Madd__add0000_Result<2>12_1447 ),
    .I1(\location_Madd__add0000_Result<2>14_1449 ),
    .O(N5)
  );
  OR2   \location_Madd__add0000_Result<5>121  (
    .I0(NlwRenamedSig_OI_count[4]),
    .I1(\location_Madd__add0000_CARRY_IN[4] ),
    .O(N27)
  );
  AND2   \location_Madd__add0000_Result<5>11  (
    .I0(location_or0001),
    .I1(N22),
    .O(\location_Madd__add0000_Result<5>12_1468 )
  );
  INV   \location_Madd__add0000_Result<5>12  (
    .I(location_or0001),
    .O(\location_Madd__add0000_Result<5>13_1469 )
  );
  AND2   \location_Madd__add0000_Result<5>13  (
    .I0(N27),
    .I1(\location_Madd__add0000_Result<5>13_1469 ),
    .O(\location_Madd__add0000_Result<5>14_1470 )
  );
  OR2   \location_Madd__add0000_Result<5>14  (
    .I0(\location_Madd__add0000_Result<5>12_1468 ),
    .I1(\location_Madd__add0000_Result<5>14_1470 ),
    .O(N6)
  );
  OR2   \location_Madd__add0000_Result<8>121  (
    .I0(NlwRenamedSig_OI_count[7]),
    .I1(\location_Madd__add0000_CARRY_IN[7] ),
    .O(N28)
  );
  AND2   \location_Madd__add0000_Result<8>11  (
    .I0(location_or0001),
    .I1(N23),
    .O(\location_Madd__add0000_Result<8>12_1489 )
  );
  INV   \location_Madd__add0000_Result<8>12  (
    .I(location_or0001),
    .O(\location_Madd__add0000_Result<8>13_1490 )
  );
  AND2   \location_Madd__add0000_Result<8>13  (
    .I0(N28),
    .I1(\location_Madd__add0000_Result<8>13_1490 ),
    .O(\location_Madd__add0000_Result<8>14_1491 )
  );
  OR2   \location_Madd__add0000_Result<8>14  (
    .I0(\location_Madd__add0000_Result<8>12_1489 ),
    .I1(\location_Madd__add0000_Result<8>14_1491 ),
    .O(N7)
  );
  AND3   SFDecomp_781 (
    .I0(NlwRenamedSig_OI_count[0]),
    .I1(NlwRenamedSig_OI_count[1]),
    .I2(NlwRenamedSig_OI_count[2]),
    .O(SFDecomp_78)
  );
  AND3   SFDecomp_791 (
    .I0(NlwRenamedSig_OI_count[4]),
    .I1(NlwRenamedSig_OI_count[5]),
    .I2(NlwRenamedSig_OI_count[6]),
    .O(SFDecomp_79)
  );
  AND3   SFDecomp_801 (
    .I0(NlwRenamedSig_OI_count[7]),
    .I1(NlwRenamedSig_OI_count[8]),
    .I2(NlwRenamedSig_OI_count[9]),
    .O(SFDecomp_80)
  );
  AND3   SFDecomp_811 (
    .I0(NlwRenamedSig_OI_count[10]),
    .I1(NlwRenamedSig_OI_count[11]),
    .I2(NlwRenamedSig_OI_count[12]),
    .O(SFDecomp_81)
  );
endmodule

module HomeConfig (
  Zero0, Zero1, DCORENCCTLw, DCOR0THRESLOWr, DCOR0THRESHIGHr, Reset, DCOR1THRESHIGHr, DCORIFGr, Hfound0, Hfound1, DCORIFGw, MotorIn0, MotorIn1, 
Home_Encoder0, Home_Encoder1, sense0, sense1, Sclk, DCOR1THRESLOWr, Tfound0, Tfound1, outDATA, inDATA, Channel0, Channel1
);
  output Zero0;
  output Zero1;
  input DCORENCCTLw;
  input DCOR0THRESLOWr;
  input DCOR0THRESHIGHr;
  input Reset;
  input DCOR1THRESHIGHr;
  input DCORIFGr;
  output Hfound0;
  output Hfound1;
  input DCORIFGw;
  input MotorIn0;
  input MotorIn1;
  input Home_Encoder0;
  input Home_Encoder1;
  output sense0;
  output sense1;
  input Sclk;
  input DCOR1THRESLOWr;
  output Tfound0;
  output Tfound1;
  output [7 : 0] outDATA;
  input [7 : 0] inDATA;
  input [15 : 0] Channel0;
  input [15 : 0] Channel1;
  wire E0r_902;
  wire E0r_0_not0000;
  wire E0r__and0000;
  wire E0r__and00001_905;
  wire E0r__or0000;
  wire E1r_907;
  wire E1r__and0000;
  wire E1r__and00001_909;
  wire HE0statelastr_910;
  wire HE0stater_911;
  wire HE1statelastr_912;
  wire HE1stater_913;
  wire NlwRenamedSig_OI_Hfound0;
  wire Hfound0r__and0000;
  wire Hfound0r__and00001;
  wire Hfound0r__and000011_917;
  wire Hfound0r__and000012_918;
  wire Hfound0r__and000013_919;
  wire Hfound0r__and000014_920;
  wire Hfound0r__or0000;
  wire Hfound0r__or00001;
  wire Hfound0r__or000011_923;
  wire Hfound0r__or00002;
  wire Hfound0r__or000021_925;
  wire Hfound0r__or000022_926;
  wire Hfound0r__or000023_927;
  wire Hfound0r__or000024_928;
  wire Hfound0r__or00003;
  wire Hfound0r__or000031_930;
  wire Hfound0r__or00004;
  wire Hfound0r__or000041_932;
  wire Hfound0r__or0000_bdd0;
  wire Hfound0r__or0000_bdd2;
  wire Hfound0r__or0000_bdd3;
  wire NlwRenamedSig_OI_Hfound1;
  wire Hfound1r__and0000;
  wire Hfound1r__and00001;
  wire Hfound1r__and000011_939;
  wire Hfound1r__and000012_940;
  wire Hfound1r__and000013_941;
  wire Hfound1r__and000014_942;
  wire Hfound1r__or0000;
  wire Hfound1r__or00001;
  wire Hfound1r__or000011_945;
  wire Hfound1r__or00002;
  wire Hfound1r__or000021_947;
  wire Hfound1r__or000022_948;
  wire Hfound1r__or000023_949;
  wire Hfound1r__or000024_950;
  wire Hfound1r__or00003;
  wire Hfound1r__or000031_952;
  wire Hfound1r__or00004;
  wire Hfound1r__or000041_954;
  wire Hfound1r__or0000_bdd0;
  wire Hfound1r__or0000_bdd2;
  wire Hfound1r__or0000_bdd3;
  wire InEdge0r_960;
  wire InEdge1r_961;
  wire LastEdge0r_962;
  wire LastEdge1r_963;
  wire Latch0r_0__and0000;
  wire Latch0r_0__and00001_966;
  wire Latch0r_0__or0000;
  wire Latch0r_10__and0000;
  wire Latch0r_10__and00001_971;
  wire Latch0r_11__and0000;
  wire Latch0r_11__and00001_974;
  wire Latch0r_12__and0000;
  wire Latch0r_12__and00001_977;
  wire Latch0r_13__and0000;
  wire Latch0r_13__and00001_980;
  wire Latch0r_14__and0000;
  wire Latch0r_14__and00001_983;
  wire Latch0r_15__and0000;
  wire Latch0r_15__and00001_986;
  wire Latch0r_1__and0000;
  wire Latch0r_1__and00001_988;
  wire Latch0r_2__and0000;
  wire Latch0r_2__and00001_991;
  wire Latch0r_3__and0000;
  wire Latch0r_3__and00001_994;
  wire Latch0r_4__and0000;
  wire Latch0r_4__and00001_997;
  wire Latch0r_5__and0000;
  wire Latch0r_5__and00001_1000;
  wire Latch0r_6__and0000;
  wire Latch0r_6__and00001_1003;
  wire Latch0r_7__and0000;
  wire Latch0r_7__and00001_1006;
  wire Latch0r_8__and0000;
  wire Latch0r_8__and00001_1009;
  wire Latch0r_9__and0000;
  wire Latch0r_9__and00001_1012;
  wire Latch1r_0__and0000;
  wire Latch1r_0__and00001_1015;
  wire Latch1r_0__or0000;
  wire Latch1r_10__and0000;
  wire Latch1r_10__and00001_1020;
  wire Latch1r_11__and0000;
  wire Latch1r_11__and00001_1023;
  wire Latch1r_12__and0000;
  wire Latch1r_12__and00001_1026;
  wire Latch1r_13__and0000;
  wire Latch1r_13__and00001_1029;
  wire Latch1r_14__and0000;
  wire Latch1r_14__and00001_1032;
  wire Latch1r_15__and0000;
  wire Latch1r_15__and00001_1035;
  wire Latch1r_1__and0000;
  wire Latch1r_1__and00001_1037;
  wire Latch1r_2__and0000;
  wire Latch1r_2__and00001_1040;
  wire Latch1r_3__and0000;
  wire Latch1r_3__and00001_1043;
  wire Latch1r_4__and0000;
  wire Latch1r_4__and00001_1046;
  wire Latch1r_5__and0000;
  wire Latch1r_5__and00001_1049;
  wire Latch1r_6__and0000;
  wire Latch1r_6__and00001_1052;
  wire Latch1r_7__and0000;
  wire Latch1r_7__and00001_1055;
  wire Latch1r_8__and0000;
  wire Latch1r_8__and00001_1058;
  wire Latch1r_9__and0000;
  wire Latch1r_9__and00001_1061;
  wire LatchEdge0r_1062;
  wire LatchEdge0r__and0000;
  wire LatchEdge0r__and00001_1064;
  wire LatchEdge1r_1065;
  wire LatchEdge1r__and0000;
  wire LatchEdge1r__and00001_1067;
  wire RF0r_1070;
  wire RF0r__and0000;
  wire RF0r__and00001_1072;
  wire RF1r_1073;
  wire RF1r__and0000;
  wire RF1r__and00001_1075;
  wire SFDecomp_34;
  wire SFDecomp_341_1078;
  wire SFDecomp_342_1079;
  wire SFDecomp_343_1080;
  wire SFDecomp_36;
  wire SFDecomp_361_1082;
  wire SFDecomp_362_1083;
  wire SFDecomp_363_1084;
  wire SFDecomp_37;
  wire SFDecomp_371_1086;
  wire SFDecomp_372_1087;
  wire SFDecomp_373_1088;
  wire SFDecomp_39;
  wire SFDecomp_391_1090;
  wire SFDecomp_392_1091;
  wire SFDecomp_393_1092;
  wire SFDecomp_40;
  wire SFDecomp_401_1094;
  wire SFDecomp_402_1095;
  wire SFDecomp_403_1096;
  wire SFDecomp_42;
  wire SFDecomp_421_1098;
  wire SFDecomp_422_1099;
  wire SFDecomp_423_1100;
  wire SFDecomp_43;
  wire SFDecomp_431_1102;
  wire SFDecomp_432_1103;
  wire SFDecomp_433_1104;
  wire SFDecomp_45;
  wire SFDecomp_451_1106;
  wire SFDecomp_452_1107;
  wire SFDecomp_453_1108;
  wire SFDecomp_47;
  wire SFDecomp_471_1110;
  wire SFDecomp_472_1111;
  wire SFDecomp_473_1112;
  wire SFDecomp_48;
  wire SFDecomp_51;
  wire SFDecomp_511_1115;
  wire SFDecomp_512_1116;
  wire SFDecomp_53;
  wire SFDecomp_531_1118;
  wire SFDecomp_532_1119;
  wire SFDecomp_533_1120;
  wire SFDecomp_54;
  wire SFDecomp_57;
  wire SFDecomp_571_1123;
  wire SFDecomp_572_1124;
  wire SFDecomp_59;
  wire SFDecomp_591_1126;
  wire SFDecomp_592_1127;
  wire SFDecomp_593_1128;
  wire SFDecomp_60;
  wire SFDecomp_63;
  wire SFDecomp_631_1131;
  wire SFDecomp_632_1132;
  wire SFDecomp_65;
  wire SFDecomp_651_1134;
  wire SFDecomp_652_1135;
  wire SFDecomp_653_1136;
  wire SFDecomp_66;
  wire SFDecomp_69;
  wire SFDecomp_691_1139;
  wire SFDecomp_692_1140;
  wire SFDecomp_70;
  wire SFDecomp_701_1142;
  wire SFDecomp_71;
  wire SFDecomp_711_1144;
  wire SFDecomp_74;
  wire SFDecomp_741_1146;
  wire SFDecomp_742_1147;
  wire SFDecomp_743_1148;
  wire SFDecomp_77;
  wire SFDecomp_771_1150;
  wire SFDecomp_772_1151;
  wire SFDecomp_773_1152;
  wire NlwRenamedSig_OI_Tfound0;
  wire Tfound0r_and0000;
  wire Tfound0r_and00001_1156;
  wire Tfound0r_and00002_1157;
  wire Tfound0r_and00003_1158;
  wire Tfound0r_mux0000;
  wire Tfound0r_mux00001;
  wire Tfound0r_mux000011_1161;
  wire Tfound0r_mux000012_1162;
  wire Tfound0r_not0001;
  wire Tfound0r_or0000;
  wire NlwRenamedSig_OI_Tfound1;
  wire Tfound1r_and0000;
  wire Tfound1r_and00001_1167;
  wire Tfound1r_and00002_1168;
  wire Tfound1r_and00003_1169;
  wire Tfound1r_mux0000;
  wire Tfound1r_mux00001;
  wire Tfound1r_mux000011_1172;
  wire Tfound1r_mux000012_1173;
  wire Tfound1r_not0001;
  wire Tfound1r_or0000;
  wire NlwRenamedSig_OI_Zero1;
  wire latchitH0_1185;
  wire latchitH0__and0000;
  wire latchitH0__and00001;
  wire latchitH0__and000011_1188;
  wire latchitH0__and000012_1189;
  wire latchitH0__and000013_1190;
  wire latchitH0__or0000;
  wire latchitH0__or00001;
  wire latchitH0__or000011_1193;
  wire latchitH0__or000012_1194;
  wire latchitH1_1195;
  wire latchitH1__and0000;
  wire latchitH1__and00001;
  wire latchitH1__and000011_1198;
  wire latchitH1__and000012_1199;
  wire latchitH1__and000013_1200;
  wire latchitL0_1201;
  wire latchitL0__and0000;
  wire latchitL0__and00001_1203;
  wire latchitL0__and00002_1204;
  wire latchitL0_cmp_eq0000;
  wire latchitL0_cmp_eq00001_1206;
  wire latchitL0_cmp_eq00002_1207;
  wire latchitL0_cmp_eq00003_1208;
  wire latchitL0_cmp_eq00004_1209;
  wire latchitL0_cmp_eq0001;
  wire latchitL0_cmp_eq00011_1211;
  wire latchitL0_cmp_eq00012_1212;
  wire latchitL0_cmp_eq00013_1213;
  wire latchitL1_1214;
  wire latchitL1__and0000;
  wire latchitL1__and00001_1216;
  wire latchitL1__and00002_1217;
  wire latchitL1_cmp_eq0000;
  wire latchitL1_cmp_eq00001_1219;
  wire latchitL1_cmp_eq00002_1220;
  wire latchitL1_cmp_eq00003_1221;
  wire latchitL1_cmp_eq00004_1222;
  wire latchitL1_cmp_eq0001;
  wire latchitL1_cmp_eq00011_1224;
  wire latchitL1_cmp_eq00012_1225;
  wire latchitL1_cmp_eq00013_1226;
  wire \outDATA<6>_not0000 ;
  wire \outDATA<6>_not0000_bdd0 ;
  wire \outDATA<7>_not0000 ;
  wire \outDATA<7>_not00001 ;
  wire \outDATA<7>_not000011_1239 ;
  wire outDATA_0_mux0000;
  wire outDATA_0_mux00001;
  wire outDATA_0_mux000011_1242;
  wire outDATA_0_mux000012_1243;
  wire outDATA_1_mux0000;
  wire outDATA_1_mux00001;
  wire outDATA_1_mux000011_1246;
  wire outDATA_1_mux000012_1247;
  wire outDATA_2_mux0000;
  wire outDATA_2_mux00001;
  wire outDATA_2_mux000011_1250;
  wire outDATA_2_mux000012_1251;
  wire outDATA_2_mux00002;
  wire outDATA_2_mux000021_1253;
  wire outDATA_2_mux000022_1254;
  wire outDATA_2_mux0000_bdd0;
  wire outDATA_3_mux0000;
  wire outDATA_3_mux00001;
  wire outDATA_3_mux000011_1258;
  wire outDATA_3_mux000012_1259;
  wire outDATA_3_mux00002;
  wire outDATA_3_mux000021_1261;
  wire outDATA_3_mux000022_1262;
  wire outDATA_3_mux0000_bdd0;
  wire outDATA_4_mux0000;
  wire outDATA_4_mux00001;
  wire outDATA_4_mux000011_1266;
  wire outDATA_4_mux000012_1267;
  wire outDATA_5_mux0000;
  wire outDATA_5_mux00001;
  wire outDATA_5_mux000011_1270;
  wire outDATA_5_mux000012_1271;
  wire outDATA_5_mux00002;
  wire outDATA_5_mux000021_1273;
  wire outDATA_5_mux000022_1274;
  wire outDATA_5_mux0000_bdd0;
  wire outDATA_6_mux0000;
  wire outDATA_6_mux00001;
  wire outDATA_6_mux000011_1278;
  wire outDATA_6_mux000012_1279;
  wire outDATA_6_mux00002;
  wire outDATA_6_mux000021_1281;
  wire outDATA_6_mux000022_1282;
  wire outDATA_6_mux0000_bdd0;
  wire outDATA_7_mux0000;
  wire outDATA_7_mux00001;
  wire outDATA_7_mux000011_1286;
  wire outDATA_7_mux000012_1287;
  wire sense0r__and0000;
  wire sense0r__and00001_1290;
  wire sense1r__and0000;
  wire sense1r__and00001_1293;
  wire [15 : 0] Latch0r;
  wire [15 : 0] Latch1r;
  assign
    Zero0 = NlwRenamedSig_OI_Zero1,
    Zero1 = NlwRenamedSig_OI_Zero1,
    Hfound0 = NlwRenamedSig_OI_Hfound0,
    Hfound1 = NlwRenamedSig_OI_Hfound1,
    Tfound0 = NlwRenamedSig_OI_Tfound0,
    Tfound1 = NlwRenamedSig_OI_Tfound1;
  GND   XST_GND (
    .G(NlwRenamedSig_OI_Zero1)
  );
  BUFE   \outDATA<0>_0  (
    .I(outDATA_0_mux0000),
    .E(\outDATA<7>_not0000 ),
    .O(outDATA[0])
  );
  BUFE   \outDATA<1>_0  (
    .I(outDATA_1_mux0000),
    .E(\outDATA<7>_not0000 ),
    .O(outDATA[1])
  );
  BUFE   \outDATA<2>_0  (
    .I(outDATA_2_mux0000),
    .E(\outDATA<6>_not0000 ),
    .O(outDATA[2])
  );
  BUFE   \outDATA<3>_0  (
    .I(outDATA_3_mux0000),
    .E(\outDATA<6>_not0000 ),
    .O(outDATA[3])
  );
  BUFE   \outDATA<4>_0  (
    .I(outDATA_4_mux0000),
    .E(\outDATA<7>_not0000 ),
    .O(outDATA[4])
  );
  BUFE   \outDATA<5>_0  (
    .I(outDATA_5_mux0000),
    .E(\outDATA<6>_not0000 ),
    .O(outDATA[5])
  );
  BUFE   \outDATA<6>_0  (
    .I(outDATA_6_mux0000),
    .E(\outDATA<6>_not0000 ),
    .O(outDATA[6])
  );
  BUFE   \outDATA<7>_0  (
    .I(outDATA_7_mux0000),
    .E(\outDATA<7>_not0000 ),
    .O(outDATA[7])
  );
  FD   LastEdge1r (
    .C(E0r_0_not0000),
    .D(InEdge1r_961),
    .Q(LastEdge1r_963)
  );
  FD   LastEdge0r (
    .C(E0r_0_not0000),
    .D(InEdge0r_960),
    .Q(LastEdge0r_962)
  );
  FD   InEdge1r (
    .C(E0r_0_not0000),
    .D(MotorIn1),
    .Q(InEdge1r_961)
  );
  FD   InEdge0r (
    .C(E0r_0_not0000),
    .D(MotorIn0),
    .Q(InEdge0r_960)
  );
  FD   HE1statelastr (
    .C(E0r_0_not0000),
    .D(HE1stater_913),
    .Q(HE1statelastr_912)
  );
  FD   HE1stater (
    .C(E0r_0_not0000),
    .D(Home_Encoder1),
    .Q(HE1stater_913)
  );
  FD   HE0statelastr (
    .C(E0r_0_not0000),
    .D(HE0stater_911),
    .Q(HE0statelastr_910)
  );
  FD   HE0stater (
    .C(E0r_0_not0000),
    .D(Home_Encoder0),
    .Q(HE0stater_911)
  );
  FDCE   Tfound1r (
    .CE(Tfound1r_not0001),
    .CLR(NlwRenamedSig_OI_Zero1),
    .C(E0r_0_not0000),
    .D(Tfound1r_mux0000),
    .Q(NlwRenamedSig_OI_Tfound1)
  );
  FDCE   Tfound0r (
    .CE(Tfound0r_not0001),
    .CLR(NlwRenamedSig_OI_Zero1),
    .C(E0r_0_not0000),
    .D(Tfound0r_mux0000),
    .Q(NlwRenamedSig_OI_Tfound0)
  );
  FDCE   latchitL1 (
    .CE(latchitH0__or0000),
    .CLR(NlwRenamedSig_OI_Zero1),
    .C(E0r_0_not0000),
    .D(latchitL1__and0000),
    .Q(latchitL1_1214)
  );
  FDCE   latchitL0 (
    .CE(latchitH0__or0000),
    .CLR(NlwRenamedSig_OI_Zero1),
    .C(E0r_0_not0000),
    .D(latchitL0__and0000),
    .Q(latchitL0_1201)
  );
  FDCE   latchitH1 (
    .CE(latchitH0__or0000),
    .CLR(NlwRenamedSig_OI_Zero1),
    .C(E0r_0_not0000),
    .D(latchitH1__and0000),
    .Q(latchitH1_1195)
  );
  FDCE   latchitH0 (
    .CE(latchitH0__or0000),
    .CLR(NlwRenamedSig_OI_Zero1),
    .C(E0r_0_not0000),
    .D(latchitH0__and0000),
    .Q(latchitH0_1185)
  );
  FDCE   Hfound1r (
    .CE(Hfound1r__or0000),
    .CLR(NlwRenamedSig_OI_Zero1),
    .C(E0r_0_not0000),
    .D(Hfound1r__and0000),
    .Q(NlwRenamedSig_OI_Hfound1)
  );
  FDCE   Hfound0r (
    .CE(Hfound0r__or0000),
    .CLR(NlwRenamedSig_OI_Zero1),
    .C(E0r_0_not0000),
    .D(Hfound0r__and0000),
    .Q(NlwRenamedSig_OI_Hfound0)
  );
  FDCE   sense1r (
    .CE(E0r__or0000),
    .CLR(NlwRenamedSig_OI_Zero1),
    .C(E0r_0_not0000),
    .D(sense1r__and0000),
    .Q(sense1)
  );
  FDCE   LatchEdge1r (
    .CE(E0r__or0000),
    .CLR(NlwRenamedSig_OI_Zero1),
    .C(E0r_0_not0000),
    .D(LatchEdge1r__and0000),
    .Q(LatchEdge1r_1065)
  );
  FDCE   E1r (
    .CE(E0r__or0000),
    .CLR(NlwRenamedSig_OI_Zero1),
    .C(E0r_0_not0000),
    .D(E1r__and0000),
    .Q(E1r_907)
  );
  FDCE   RF1r (
    .CE(E0r__or0000),
    .CLR(NlwRenamedSig_OI_Zero1),
    .C(E0r_0_not0000),
    .D(RF1r__and0000),
    .Q(RF1r_1073)
  );
  FDCE   sense0r (
    .CE(E0r__or0000),
    .CLR(NlwRenamedSig_OI_Zero1),
    .C(E0r_0_not0000),
    .D(sense0r__and0000),
    .Q(sense0)
  );
  FDCE   LatchEdge0r (
    .CE(E0r__or0000),
    .CLR(NlwRenamedSig_OI_Zero1),
    .C(E0r_0_not0000),
    .D(LatchEdge0r__and0000),
    .Q(LatchEdge0r_1062)
  );
  FDCE   E0r (
    .CE(E0r__or0000),
    .CLR(NlwRenamedSig_OI_Zero1),
    .C(E0r_0_not0000),
    .D(E0r__and0000),
    .Q(E0r_902)
  );
  FDCE   RF0r (
    .CE(E0r__or0000),
    .CLR(NlwRenamedSig_OI_Zero1),
    .C(E0r_0_not0000),
    .D(RF0r__and0000),
    .Q(RF0r_1070)
  );
  FDCE   Latch1r_0 (
    .CE(Latch1r_0__or0000),
    .CLR(NlwRenamedSig_OI_Zero1),
    .C(E0r_0_not0000),
    .D(Latch1r_0__and0000),
    .Q(Latch1r[0])
  );
  FDCE   Latch1r_1 (
    .CE(Latch1r_0__or0000),
    .CLR(NlwRenamedSig_OI_Zero1),
    .C(E0r_0_not0000),
    .D(Latch1r_1__and0000),
    .Q(Latch1r[1])
  );
  FDCE   Latch1r_2 (
    .CE(Latch1r_0__or0000),
    .CLR(NlwRenamedSig_OI_Zero1),
    .C(E0r_0_not0000),
    .D(Latch1r_2__and0000),
    .Q(Latch1r[2])
  );
  FDCE   Latch1r_3 (
    .CE(Latch1r_0__or0000),
    .CLR(NlwRenamedSig_OI_Zero1),
    .C(E0r_0_not0000),
    .D(Latch1r_3__and0000),
    .Q(Latch1r[3])
  );
  FDCE   Latch1r_4 (
    .CE(Latch1r_0__or0000),
    .CLR(NlwRenamedSig_OI_Zero1),
    .C(E0r_0_not0000),
    .D(Latch1r_4__and0000),
    .Q(Latch1r[4])
  );
  FDCE   Latch1r_5 (
    .CE(Latch1r_0__or0000),
    .CLR(NlwRenamedSig_OI_Zero1),
    .C(E0r_0_not0000),
    .D(Latch1r_5__and0000),
    .Q(Latch1r[5])
  );
  FDCE   Latch1r_6 (
    .CE(Latch1r_0__or0000),
    .CLR(NlwRenamedSig_OI_Zero1),
    .C(E0r_0_not0000),
    .D(Latch1r_6__and0000),
    .Q(Latch1r[6])
  );
  FDCE   Latch1r_7 (
    .CE(Latch1r_0__or0000),
    .CLR(NlwRenamedSig_OI_Zero1),
    .C(E0r_0_not0000),
    .D(Latch1r_7__and0000),
    .Q(Latch1r[7])
  );
  FDCE   Latch1r_8 (
    .CE(Latch1r_0__or0000),
    .CLR(NlwRenamedSig_OI_Zero1),
    .C(E0r_0_not0000),
    .D(Latch1r_8__and0000),
    .Q(Latch1r[8])
  );
  FDCE   Latch1r_9 (
    .CE(Latch1r_0__or0000),
    .CLR(NlwRenamedSig_OI_Zero1),
    .C(E0r_0_not0000),
    .D(Latch1r_9__and0000),
    .Q(Latch1r[9])
  );
  FDCE   Latch1r_10 (
    .CE(Latch1r_0__or0000),
    .CLR(NlwRenamedSig_OI_Zero1),
    .C(E0r_0_not0000),
    .D(Latch1r_10__and0000),
    .Q(Latch1r[10])
  );
  FDCE   Latch1r_11 (
    .CE(Latch1r_0__or0000),
    .CLR(NlwRenamedSig_OI_Zero1),
    .C(E0r_0_not0000),
    .D(Latch1r_11__and0000),
    .Q(Latch1r[11])
  );
  FDCE   Latch1r_12 (
    .CE(Latch1r_0__or0000),
    .CLR(NlwRenamedSig_OI_Zero1),
    .C(E0r_0_not0000),
    .D(Latch1r_12__and0000),
    .Q(Latch1r[12])
  );
  FDCE   Latch1r_13 (
    .CE(Latch1r_0__or0000),
    .CLR(NlwRenamedSig_OI_Zero1),
    .C(E0r_0_not0000),
    .D(Latch1r_13__and0000),
    .Q(Latch1r[13])
  );
  FDCE   Latch1r_14 (
    .CE(Latch1r_0__or0000),
    .CLR(NlwRenamedSig_OI_Zero1),
    .C(E0r_0_not0000),
    .D(Latch1r_14__and0000),
    .Q(Latch1r[14])
  );
  FDCE   Latch1r_15 (
    .CE(Latch1r_0__or0000),
    .CLR(NlwRenamedSig_OI_Zero1),
    .C(E0r_0_not0000),
    .D(Latch1r_15__and0000),
    .Q(Latch1r[15])
  );
  FDCE   Latch0r_0 (
    .CE(Latch0r_0__or0000),
    .CLR(NlwRenamedSig_OI_Zero1),
    .C(E0r_0_not0000),
    .D(Latch0r_0__and0000),
    .Q(Latch0r[0])
  );
  FDCE   Latch0r_1 (
    .CE(Latch0r_0__or0000),
    .CLR(NlwRenamedSig_OI_Zero1),
    .C(E0r_0_not0000),
    .D(Latch0r_1__and0000),
    .Q(Latch0r[1])
  );
  FDCE   Latch0r_2 (
    .CE(Latch0r_0__or0000),
    .CLR(NlwRenamedSig_OI_Zero1),
    .C(E0r_0_not0000),
    .D(Latch0r_2__and0000),
    .Q(Latch0r[2])
  );
  FDCE   Latch0r_3 (
    .CE(Latch0r_0__or0000),
    .CLR(NlwRenamedSig_OI_Zero1),
    .C(E0r_0_not0000),
    .D(Latch0r_3__and0000),
    .Q(Latch0r[3])
  );
  FDCE   Latch0r_4 (
    .CE(Latch0r_0__or0000),
    .CLR(NlwRenamedSig_OI_Zero1),
    .C(E0r_0_not0000),
    .D(Latch0r_4__and0000),
    .Q(Latch0r[4])
  );
  FDCE   Latch0r_5 (
    .CE(Latch0r_0__or0000),
    .CLR(NlwRenamedSig_OI_Zero1),
    .C(E0r_0_not0000),
    .D(Latch0r_5__and0000),
    .Q(Latch0r[5])
  );
  FDCE   Latch0r_6 (
    .CE(Latch0r_0__or0000),
    .CLR(NlwRenamedSig_OI_Zero1),
    .C(E0r_0_not0000),
    .D(Latch0r_6__and0000),
    .Q(Latch0r[6])
  );
  FDCE   Latch0r_7 (
    .CE(Latch0r_0__or0000),
    .CLR(NlwRenamedSig_OI_Zero1),
    .C(E0r_0_not0000),
    .D(Latch0r_7__and0000),
    .Q(Latch0r[7])
  );
  FDCE   Latch0r_8 (
    .CE(Latch0r_0__or0000),
    .CLR(NlwRenamedSig_OI_Zero1),
    .C(E0r_0_not0000),
    .D(Latch0r_8__and0000),
    .Q(Latch0r[8])
  );
  FDCE   Latch0r_9 (
    .CE(Latch0r_0__or0000),
    .CLR(NlwRenamedSig_OI_Zero1),
    .C(E0r_0_not0000),
    .D(Latch0r_9__and0000),
    .Q(Latch0r[9])
  );
  FDCE   Latch0r_10 (
    .CE(Latch0r_0__or0000),
    .CLR(NlwRenamedSig_OI_Zero1),
    .C(E0r_0_not0000),
    .D(Latch0r_10__and0000),
    .Q(Latch0r[10])
  );
  FDCE   Latch0r_11 (
    .CE(Latch0r_0__or0000),
    .CLR(NlwRenamedSig_OI_Zero1),
    .C(E0r_0_not0000),
    .D(Latch0r_11__and0000),
    .Q(Latch0r[11])
  );
  FDCE   Latch0r_12 (
    .CE(Latch0r_0__or0000),
    .CLR(NlwRenamedSig_OI_Zero1),
    .C(E0r_0_not0000),
    .D(Latch0r_12__and0000),
    .Q(Latch0r[12])
  );
  FDCE   Latch0r_13 (
    .CE(Latch0r_0__or0000),
    .CLR(NlwRenamedSig_OI_Zero1),
    .C(E0r_0_not0000),
    .D(Latch0r_13__and0000),
    .Q(Latch0r[13])
  );
  FDCE   Latch0r_14 (
    .CE(Latch0r_0__or0000),
    .CLR(NlwRenamedSig_OI_Zero1),
    .C(E0r_0_not0000),
    .D(Latch0r_14__and0000),
    .Q(Latch0r[14])
  );
  FDCE   Latch0r_15 (
    .CE(Latch0r_0__or0000),
    .CLR(NlwRenamedSig_OI_Zero1),
    .C(E0r_0_not0000),
    .D(Latch0r_15__and0000),
    .Q(Latch0r[15])
  );
  INV   sense1r__and00001 (
    .I(Reset),
    .O(sense1r__and00001_1293)
  );
  AND2   sense1r__and00002 (
    .I0(inDATA[7]),
    .I1(sense1r__and00001_1293),
    .O(sense1r__and0000)
  );
  INV   LatchEdge1r__and00001 (
    .I(Reset),
    .O(LatchEdge1r__and00001_1067)
  );
  AND2   LatchEdge1r__and00002 (
    .I0(inDATA[6]),
    .I1(LatchEdge1r__and00001_1067),
    .O(LatchEdge1r__and0000)
  );
  INV   E1r__and00001 (
    .I(Reset),
    .O(E1r__and00001_909)
  );
  AND2   E1r__and00002 (
    .I0(inDATA[5]),
    .I1(E1r__and00001_909),
    .O(E1r__and0000)
  );
  INV   RF1r__and00001 (
    .I(Reset),
    .O(RF1r__and00001_1075)
  );
  AND2   RF1r__and00002 (
    .I0(inDATA[4]),
    .I1(RF1r__and00001_1075),
    .O(RF1r__and0000)
  );
  INV   sense0r__and00001 (
    .I(Reset),
    .O(sense0r__and00001_1290)
  );
  AND2   sense0r__and00002 (
    .I0(inDATA[3]),
    .I1(sense0r__and00001_1290),
    .O(sense0r__and0000)
  );
  INV   LatchEdge0r__and00001 (
    .I(Reset),
    .O(LatchEdge0r__and00001_1064)
  );
  AND2   LatchEdge0r__and00002 (
    .I0(inDATA[2]),
    .I1(LatchEdge0r__and00001_1064),
    .O(LatchEdge0r__and0000)
  );
  INV   E0r_0_not00001 (
    .I(Sclk),
    .O(E0r_0_not0000)
  );
  OR2   E0r__or00001 (
    .I0(DCORENCCTLw),
    .I1(Reset),
    .O(E0r__or0000)
  );
  INV   E0r__and00001 (
    .I(Reset),
    .O(E0r__and00001_905)
  );
  AND2   E0r__and00002 (
    .I0(inDATA[1]),
    .I1(E0r__and00001_905),
    .O(E0r__and0000)
  );
  INV   RF0r__and00001 (
    .I(Reset),
    .O(RF0r__and00001_1072)
  );
  AND2   RF0r__and00002 (
    .I0(inDATA[0]),
    .I1(RF0r__and00001_1072),
    .O(RF0r__and0000)
  );
  INV   Latch1r_0__and00001 (
    .I(Reset),
    .O(Latch1r_0__and00001_1015)
  );
  AND2   Latch1r_0__and00002 (
    .I0(Channel1[0]),
    .I1(Latch1r_0__and00001_1015),
    .O(Latch1r_0__and0000)
  );
  INV   Latch1r_1__and00001 (
    .I(Reset),
    .O(Latch1r_1__and00001_1037)
  );
  AND2   Latch1r_1__and00002 (
    .I0(Channel1[1]),
    .I1(Latch1r_1__and00001_1037),
    .O(Latch1r_1__and0000)
  );
  INV   Latch1r_2__and00001 (
    .I(Reset),
    .O(Latch1r_2__and00001_1040)
  );
  AND2   Latch1r_2__and00002 (
    .I0(Channel1[2]),
    .I1(Latch1r_2__and00001_1040),
    .O(Latch1r_2__and0000)
  );
  INV   Latch1r_3__and00001 (
    .I(Reset),
    .O(Latch1r_3__and00001_1043)
  );
  AND2   Latch1r_3__and00002 (
    .I0(Channel1[3]),
    .I1(Latch1r_3__and00001_1043),
    .O(Latch1r_3__and0000)
  );
  INV   Latch1r_4__and00001 (
    .I(Reset),
    .O(Latch1r_4__and00001_1046)
  );
  AND2   Latch1r_4__and00002 (
    .I0(Channel1[4]),
    .I1(Latch1r_4__and00001_1046),
    .O(Latch1r_4__and0000)
  );
  INV   Latch1r_5__and00001 (
    .I(Reset),
    .O(Latch1r_5__and00001_1049)
  );
  AND2   Latch1r_5__and00002 (
    .I0(Channel1[5]),
    .I1(Latch1r_5__and00001_1049),
    .O(Latch1r_5__and0000)
  );
  INV   Latch1r_6__and00001 (
    .I(Reset),
    .O(Latch1r_6__and00001_1052)
  );
  AND2   Latch1r_6__and00002 (
    .I0(Channel1[6]),
    .I1(Latch1r_6__and00001_1052),
    .O(Latch1r_6__and0000)
  );
  INV   Latch1r_7__and00001 (
    .I(Reset),
    .O(Latch1r_7__and00001_1055)
  );
  AND2   Latch1r_7__and00002 (
    .I0(Channel1[7]),
    .I1(Latch1r_7__and00001_1055),
    .O(Latch1r_7__and0000)
  );
  INV   Latch1r_8__and00001 (
    .I(Reset),
    .O(Latch1r_8__and00001_1058)
  );
  AND2   Latch1r_8__and00002 (
    .I0(Channel1[8]),
    .I1(Latch1r_8__and00001_1058),
    .O(Latch1r_8__and0000)
  );
  INV   Latch1r_9__and00001 (
    .I(Reset),
    .O(Latch1r_9__and00001_1061)
  );
  AND2   Latch1r_9__and00002 (
    .I0(Channel1[9]),
    .I1(Latch1r_9__and00001_1061),
    .O(Latch1r_9__and0000)
  );
  INV   Latch1r_10__and00001 (
    .I(Reset),
    .O(Latch1r_10__and00001_1020)
  );
  AND2   Latch1r_10__and00002 (
    .I0(Channel1[10]),
    .I1(Latch1r_10__and00001_1020),
    .O(Latch1r_10__and0000)
  );
  INV   Latch1r_11__and00001 (
    .I(Reset),
    .O(Latch1r_11__and00001_1023)
  );
  AND2   Latch1r_11__and00002 (
    .I0(Channel1[11]),
    .I1(Latch1r_11__and00001_1023),
    .O(Latch1r_11__and0000)
  );
  INV   Latch1r_12__and00001 (
    .I(Reset),
    .O(Latch1r_12__and00001_1026)
  );
  AND2   Latch1r_12__and00002 (
    .I0(Channel1[12]),
    .I1(Latch1r_12__and00001_1026),
    .O(Latch1r_12__and0000)
  );
  INV   Latch1r_13__and00001 (
    .I(Reset),
    .O(Latch1r_13__and00001_1029)
  );
  AND2   Latch1r_13__and00002 (
    .I0(Channel1[13]),
    .I1(Latch1r_13__and00001_1029),
    .O(Latch1r_13__and0000)
  );
  INV   Latch1r_14__and00001 (
    .I(Reset),
    .O(Latch1r_14__and00001_1032)
  );
  AND2   Latch1r_14__and00002 (
    .I0(Channel1[14]),
    .I1(Latch1r_14__and00001_1032),
    .O(Latch1r_14__and0000)
  );
  INV   Latch1r_15__and00001 (
    .I(Reset),
    .O(Latch1r_15__and00001_1035)
  );
  AND2   Latch1r_15__and00002 (
    .I0(Channel1[15]),
    .I1(Latch1r_15__and00001_1035),
    .O(Latch1r_15__and0000)
  );
  INV   Latch0r_0__and00001 (
    .I(Reset),
    .O(Latch0r_0__and00001_966)
  );
  AND2   Latch0r_0__and00002 (
    .I0(Channel0[0]),
    .I1(Latch0r_0__and00001_966),
    .O(Latch0r_0__and0000)
  );
  INV   Latch0r_1__and00001 (
    .I(Reset),
    .O(Latch0r_1__and00001_988)
  );
  AND2   Latch0r_1__and00002 (
    .I0(Channel0[1]),
    .I1(Latch0r_1__and00001_988),
    .O(Latch0r_1__and0000)
  );
  INV   Latch0r_2__and00001 (
    .I(Reset),
    .O(Latch0r_2__and00001_991)
  );
  AND2   Latch0r_2__and00002 (
    .I0(Channel0[2]),
    .I1(Latch0r_2__and00001_991),
    .O(Latch0r_2__and0000)
  );
  INV   Latch0r_3__and00001 (
    .I(Reset),
    .O(Latch0r_3__and00001_994)
  );
  AND2   Latch0r_3__and00002 (
    .I0(Channel0[3]),
    .I1(Latch0r_3__and00001_994),
    .O(Latch0r_3__and0000)
  );
  INV   Latch0r_4__and00001 (
    .I(Reset),
    .O(Latch0r_4__and00001_997)
  );
  AND2   Latch0r_4__and00002 (
    .I0(Channel0[4]),
    .I1(Latch0r_4__and00001_997),
    .O(Latch0r_4__and0000)
  );
  INV   Latch0r_5__and00001 (
    .I(Reset),
    .O(Latch0r_5__and00001_1000)
  );
  AND2   Latch0r_5__and00002 (
    .I0(Channel0[5]),
    .I1(Latch0r_5__and00001_1000),
    .O(Latch0r_5__and0000)
  );
  INV   Latch0r_6__and00001 (
    .I(Reset),
    .O(Latch0r_6__and00001_1003)
  );
  AND2   Latch0r_6__and00002 (
    .I0(Channel0[6]),
    .I1(Latch0r_6__and00001_1003),
    .O(Latch0r_6__and0000)
  );
  INV   Latch0r_7__and00001 (
    .I(Reset),
    .O(Latch0r_7__and00001_1006)
  );
  AND2   Latch0r_7__and00002 (
    .I0(Channel0[7]),
    .I1(Latch0r_7__and00001_1006),
    .O(Latch0r_7__and0000)
  );
  INV   Latch0r_8__and00001 (
    .I(Reset),
    .O(Latch0r_8__and00001_1009)
  );
  AND2   Latch0r_8__and00002 (
    .I0(Channel0[8]),
    .I1(Latch0r_8__and00001_1009),
    .O(Latch0r_8__and0000)
  );
  INV   Latch0r_9__and00001 (
    .I(Reset),
    .O(Latch0r_9__and00001_1012)
  );
  AND2   Latch0r_9__and00002 (
    .I0(Channel0[9]),
    .I1(Latch0r_9__and00001_1012),
    .O(Latch0r_9__and0000)
  );
  INV   Latch0r_10__and00001 (
    .I(Reset),
    .O(Latch0r_10__and00001_971)
  );
  AND2   Latch0r_10__and00002 (
    .I0(Channel0[10]),
    .I1(Latch0r_10__and00001_971),
    .O(Latch0r_10__and0000)
  );
  INV   Latch0r_11__and00001 (
    .I(Reset),
    .O(Latch0r_11__and00001_974)
  );
  AND2   Latch0r_11__and00002 (
    .I0(Channel0[11]),
    .I1(Latch0r_11__and00001_974),
    .O(Latch0r_11__and0000)
  );
  INV   Latch0r_12__and00001 (
    .I(Reset),
    .O(Latch0r_12__and00001_977)
  );
  AND2   Latch0r_12__and00002 (
    .I0(Channel0[12]),
    .I1(Latch0r_12__and00001_977),
    .O(Latch0r_12__and0000)
  );
  INV   Latch0r_13__and00001 (
    .I(Reset),
    .O(Latch0r_13__and00001_980)
  );
  AND2   Latch0r_13__and00002 (
    .I0(Channel0[13]),
    .I1(Latch0r_13__and00001_980),
    .O(Latch0r_13__and0000)
  );
  INV   Latch0r_14__and00001 (
    .I(Reset),
    .O(Latch0r_14__and00001_983)
  );
  AND2   Latch0r_14__and00002 (
    .I0(Channel0[14]),
    .I1(Latch0r_14__and00001_983),
    .O(Latch0r_14__and0000)
  );
  INV   Latch0r_15__and00001 (
    .I(Reset),
    .O(Latch0r_15__and00001_986)
  );
  AND2   Latch0r_15__and00002 (
    .I0(Channel0[15]),
    .I1(Latch0r_15__and00001_986),
    .O(Latch0r_15__and0000)
  );
  INV   Tfound1r_mux000011 (
    .I(inDATA[6]),
    .O(Tfound1r_mux00001)
  );
  INV   Tfound1r_mux000012 (
    .I(DCORIFGw),
    .O(Tfound1r_mux000011_1172)
  );
  AND2   Tfound1r_mux000013 (
    .I0(NlwRenamedSig_OI_Tfound1),
    .I1(Tfound1r_mux00001),
    .O(Tfound1r_mux000012_1173)
  );
  OR2   Tfound1r_mux000014 (
    .I0(Tfound1r_mux000012_1173),
    .I1(Tfound1r_mux000011_1172),
    .O(Tfound1r_mux0000)
  );
  INV   Tfound0r_mux000011 (
    .I(inDATA[5]),
    .O(Tfound0r_mux00001)
  );
  INV   Tfound0r_mux000012 (
    .I(DCORIFGw),
    .O(Tfound0r_mux000011_1161)
  );
  AND2   Tfound0r_mux000013 (
    .I0(NlwRenamedSig_OI_Tfound0),
    .I1(Tfound0r_mux00001),
    .O(Tfound0r_mux000012_1162)
  );
  OR2   Tfound0r_mux000014 (
    .I0(Tfound0r_mux000012_1162),
    .I1(Tfound0r_mux000011_1161),
    .O(Tfound0r_mux0000)
  );
  INV   Hfound1r__and000011 (
    .I(inDATA[3]),
    .O(Hfound1r__and00001)
  );
  INV   Hfound1r__and000012 (
    .I(DCORIFGw),
    .O(Hfound1r__and000011_939)
  );
  INV   Hfound1r__and000013 (
    .I(Reset),
    .O(Hfound1r__and000012_940)
  );
  AND2   Hfound1r__and000014 (
    .I0(NlwRenamedSig_OI_Hfound1),
    .I1(Hfound1r__and00001),
    .O(Hfound1r__and000013_941)
  );
  OR2   Hfound1r__and000015 (
    .I0(Hfound1r__and000013_941),
    .I1(Hfound1r__and000011_939),
    .O(Hfound1r__and000014_942)
  );
  AND2   Hfound1r__and000016 (
    .I0(Hfound1r__and000014_942),
    .I1(Hfound1r__and000012_940),
    .O(Hfound1r__and0000)
  );
  INV   Hfound0r__and000011 (
    .I(inDATA[2]),
    .O(Hfound0r__and00001)
  );
  INV   Hfound0r__and000012 (
    .I(DCORIFGw),
    .O(Hfound0r__and000011_917)
  );
  INV   Hfound0r__and000013 (
    .I(Reset),
    .O(Hfound0r__and000012_918)
  );
  AND2   Hfound0r__and000014 (
    .I0(NlwRenamedSig_OI_Hfound0),
    .I1(Hfound0r__and00001),
    .O(Hfound0r__and000013_919)
  );
  OR2   Hfound0r__and000015 (
    .I0(Hfound0r__and000013_919),
    .I1(Hfound0r__and000011_917),
    .O(Hfound0r__and000014_920)
  );
  AND2   Hfound0r__and000016 (
    .I0(Hfound0r__and000014_920),
    .I1(Hfound0r__and000012_918),
    .O(Hfound0r__and0000)
  );
  OR3   Latch0r_0__or000011 (
    .I0(Reset),
    .I1(latchitH0_1185),
    .I2(latchitL0_1201),
    .O(Latch0r_0__or0000)
  );
  OR3   Latch1r_0__or000011 (
    .I0(Reset),
    .I1(latchitH1_1195),
    .I2(latchitL1_1214),
    .O(Latch1r_0__or0000)
  );
  INV   latchitH0__or000011 (
    .I(DCORIFGw),
    .O(latchitH0__or00001)
  );
  INV   latchitH0__or000012 (
    .I(DCORENCCTLw),
    .O(latchitH0__or000011_1193)
  );
  AND2   latchitH0__or000013 (
    .I0(latchitH0__or00001),
    .I1(latchitH0__or000011_1193),
    .O(latchitH0__or000012_1194)
  );
  OR2   latchitH0__or000014 (
    .I0(Reset),
    .I1(latchitH0__or000012_1194),
    .O(latchitH0__or0000)
  );
  AND2   outDATA_7_mux000011 (
    .I0(DCOR0THRESLOWr),
    .I1(Latch0r[7]),
    .O(outDATA_7_mux00001)
  );
  INV   outDATA_7_mux000012 (
    .I(DCOR0THRESLOWr),
    .O(outDATA_7_mux000011_1286)
  );
  AND2   outDATA_7_mux000013 (
    .I0(SFDecomp_36),
    .I1(outDATA_7_mux000011_1286),
    .O(outDATA_7_mux000012_1287)
  );
  OR2   outDATA_7_mux000014 (
    .I0(outDATA_7_mux00001),
    .I1(outDATA_7_mux000012_1287),
    .O(outDATA_7_mux0000)
  );
  AND2   outDATA_6_mux000021 (
    .I0(DCOR1THRESLOWr),
    .I1(Latch1r[6]),
    .O(outDATA_6_mux00002)
  );
  INV   outDATA_6_mux000022 (
    .I(DCOR1THRESLOWr),
    .O(outDATA_6_mux000021_1281)
  );
  AND2   outDATA_6_mux000023 (
    .I0(Latch1r[14]),
    .I1(outDATA_6_mux000021_1281),
    .O(outDATA_6_mux000022_1282)
  );
  OR2   outDATA_6_mux000024 (
    .I0(outDATA_6_mux00002),
    .I1(outDATA_6_mux000022_1282),
    .O(outDATA_6_mux0000_bdd0)
  );
  AND2   outDATA_6_mux000011 (
    .I0(DCOR0THRESLOWr),
    .I1(Latch0r[6]),
    .O(outDATA_6_mux00001)
  );
  INV   outDATA_6_mux000012 (
    .I(DCOR0THRESLOWr),
    .O(outDATA_6_mux000011_1278)
  );
  AND2   outDATA_6_mux000013 (
    .I0(SFDecomp_51),
    .I1(outDATA_6_mux000011_1278),
    .O(outDATA_6_mux000012_1279)
  );
  OR2   outDATA_6_mux000014 (
    .I0(outDATA_6_mux00001),
    .I1(outDATA_6_mux000012_1279),
    .O(outDATA_6_mux0000)
  );
  AND2   outDATA_5_mux000021 (
    .I0(DCOR1THRESLOWr),
    .I1(Latch1r[5]),
    .O(outDATA_5_mux00002)
  );
  INV   outDATA_5_mux000022 (
    .I(DCOR1THRESLOWr),
    .O(outDATA_5_mux000021_1273)
  );
  AND2   outDATA_5_mux000023 (
    .I0(Latch1r[13]),
    .I1(outDATA_5_mux000021_1273),
    .O(outDATA_5_mux000022_1274)
  );
  OR2   outDATA_5_mux000024 (
    .I0(outDATA_5_mux00002),
    .I1(outDATA_5_mux000022_1274),
    .O(outDATA_5_mux0000_bdd0)
  );
  AND2   outDATA_5_mux000011 (
    .I0(DCOR0THRESLOWr),
    .I1(Latch0r[5]),
    .O(outDATA_5_mux00001)
  );
  INV   outDATA_5_mux000012 (
    .I(DCOR0THRESLOWr),
    .O(outDATA_5_mux000011_1270)
  );
  AND2   outDATA_5_mux000013 (
    .I0(SFDecomp_57),
    .I1(outDATA_5_mux000011_1270),
    .O(outDATA_5_mux000012_1271)
  );
  OR2   outDATA_5_mux000014 (
    .I0(outDATA_5_mux00001),
    .I1(outDATA_5_mux000012_1271),
    .O(outDATA_5_mux0000)
  );
  AND2   outDATA_4_mux000011 (
    .I0(DCOR0THRESLOWr),
    .I1(Latch0r[4]),
    .O(outDATA_4_mux00001)
  );
  INV   outDATA_4_mux000012 (
    .I(DCOR0THRESLOWr),
    .O(outDATA_4_mux000011_1266)
  );
  AND2   outDATA_4_mux000013 (
    .I0(SFDecomp_39),
    .I1(outDATA_4_mux000011_1266),
    .O(outDATA_4_mux000012_1267)
  );
  OR2   outDATA_4_mux000014 (
    .I0(outDATA_4_mux00001),
    .I1(outDATA_4_mux000012_1267),
    .O(outDATA_4_mux0000)
  );
  AND2   outDATA_3_mux000021 (
    .I0(DCOR1THRESLOWr),
    .I1(Latch1r[3]),
    .O(outDATA_3_mux00002)
  );
  INV   outDATA_3_mux000022 (
    .I(DCOR1THRESLOWr),
    .O(outDATA_3_mux000021_1261)
  );
  AND2   outDATA_3_mux000023 (
    .I0(Latch1r[11]),
    .I1(outDATA_3_mux000021_1261),
    .O(outDATA_3_mux000022_1262)
  );
  OR2   outDATA_3_mux000024 (
    .I0(outDATA_3_mux00002),
    .I1(outDATA_3_mux000022_1262),
    .O(outDATA_3_mux0000_bdd0)
  );
  AND2   outDATA_3_mux000011 (
    .I0(DCOR0THRESLOWr),
    .I1(Latch0r[3]),
    .O(outDATA_3_mux00001)
  );
  INV   outDATA_3_mux000012 (
    .I(DCOR0THRESLOWr),
    .O(outDATA_3_mux000011_1258)
  );
  AND2   outDATA_3_mux000013 (
    .I0(SFDecomp_63),
    .I1(outDATA_3_mux000011_1258),
    .O(outDATA_3_mux000012_1259)
  );
  OR2   outDATA_3_mux000014 (
    .I0(outDATA_3_mux00001),
    .I1(outDATA_3_mux000012_1259),
    .O(outDATA_3_mux0000)
  );
  AND2   outDATA_2_mux000021 (
    .I0(DCOR1THRESLOWr),
    .I1(Latch1r[2]),
    .O(outDATA_2_mux00002)
  );
  INV   outDATA_2_mux000022 (
    .I(DCOR1THRESLOWr),
    .O(outDATA_2_mux000021_1253)
  );
  AND2   outDATA_2_mux000023 (
    .I0(Latch1r[10]),
    .I1(outDATA_2_mux000021_1253),
    .O(outDATA_2_mux000022_1254)
  );
  OR2   outDATA_2_mux000024 (
    .I0(outDATA_2_mux00002),
    .I1(outDATA_2_mux000022_1254),
    .O(outDATA_2_mux0000_bdd0)
  );
  AND2   outDATA_2_mux000011 (
    .I0(DCOR0THRESLOWr),
    .I1(Latch0r[2]),
    .O(outDATA_2_mux00001)
  );
  INV   outDATA_2_mux000012 (
    .I(DCOR0THRESLOWr),
    .O(outDATA_2_mux000011_1250)
  );
  AND2   outDATA_2_mux000013 (
    .I0(SFDecomp_69),
    .I1(outDATA_2_mux000011_1250),
    .O(outDATA_2_mux000012_1251)
  );
  OR2   outDATA_2_mux000014 (
    .I0(outDATA_2_mux00001),
    .I1(outDATA_2_mux000012_1251),
    .O(outDATA_2_mux0000)
  );
  AND2   outDATA_1_mux000011 (
    .I0(DCOR0THRESLOWr),
    .I1(Latch0r[1]),
    .O(outDATA_1_mux00001)
  );
  INV   outDATA_1_mux000012 (
    .I(DCOR0THRESLOWr),
    .O(outDATA_1_mux000011_1246)
  );
  AND2   outDATA_1_mux000013 (
    .I0(SFDecomp_42),
    .I1(outDATA_1_mux000011_1246),
    .O(outDATA_1_mux000012_1247)
  );
  OR2   outDATA_1_mux000014 (
    .I0(outDATA_1_mux00001),
    .I1(outDATA_1_mux000012_1247),
    .O(outDATA_1_mux0000)
  );
  AND2   outDATA_0_mux000011 (
    .I0(DCOR0THRESLOWr),
    .I1(Latch0r[0]),
    .O(outDATA_0_mux00001)
  );
  INV   outDATA_0_mux000012 (
    .I(DCOR0THRESLOWr),
    .O(outDATA_0_mux000011_1242)
  );
  AND2   outDATA_0_mux000013 (
    .I0(SFDecomp_45),
    .I1(outDATA_0_mux000011_1242),
    .O(outDATA_0_mux000012_1243)
  );
  OR2   outDATA_0_mux000014 (
    .I0(outDATA_0_mux00001),
    .I1(outDATA_0_mux000012_1243),
    .O(outDATA_0_mux0000)
  );
  OR2   latchitH0__and000011 (
    .I0(RF0r_1070),
    .I1(Hfound0r__or0000_bdd3),
    .O(latchitH0__and00001)
  );
  INV   latchitH0__and000012 (
    .I(RF0r_1070),
    .O(latchitH0__and000011_1188)
  );
  AND2   latchitH0__and000013 (
    .I0(SFDecomp_70),
    .I1(latchitH0__and00001),
    .O(latchitH0__and000012_1189)
  );
  OR2   latchitH0__and000014 (
    .I0(Hfound0r__or0000_bdd2),
    .I1(latchitH0__and000011_1188),
    .O(latchitH0__and000013_1190)
  );
  AND2   latchitH0__and000015 (
    .I0(latchitH0__and000012_1189),
    .I1(latchitH0__and000013_1190),
    .O(latchitH0__and0000)
  );
  INV   Hfound0r__or000041 (
    .I(HE0stater_911),
    .O(Hfound0r__or00004)
  );
  INV   Hfound0r__or000042 (
    .I(NlwRenamedSig_OI_Hfound0),
    .O(Hfound0r__or000041_932)
  );
  AND3   Hfound0r__or000043 (
    .I0(Hfound0r__or00004),
    .I1(HE0statelastr_910),
    .I2(Hfound0r__or000041_932),
    .O(Hfound0r__or0000_bdd3)
  );
  INV   Hfound0r__or000031 (
    .I(NlwRenamedSig_OI_Hfound0),
    .O(Hfound0r__or00003)
  );
  INV   Hfound0r__or000032 (
    .I(HE0statelastr_910),
    .O(Hfound0r__or000031_930)
  );
  AND3   Hfound0r__or000033 (
    .I0(Hfound0r__or00003),
    .I1(HE0stater_911),
    .I2(Hfound0r__or000031_930),
    .O(Hfound0r__or0000_bdd2)
  );
  OR2   Hfound0r__or000021 (
    .I0(DCORIFGw),
    .I1(Hfound0r__or0000_bdd2),
    .O(Hfound0r__or00002)
  );
  OR2   Hfound0r__or000022 (
    .I0(DCORIFGw),
    .I1(Hfound0r__or0000_bdd3),
    .O(Hfound0r__or000021_925)
  );
  INV   Hfound0r__or000023 (
    .I(RF0r_1070),
    .O(Hfound0r__or000022_926)
  );
  AND2   Hfound0r__or000024 (
    .I0(RF0r_1070),
    .I1(Hfound0r__or00002),
    .O(Hfound0r__or000023_927)
  );
  AND2   Hfound0r__or000025 (
    .I0(Hfound0r__or000021_925),
    .I1(Hfound0r__or000022_926),
    .O(Hfound0r__or000024_928)
  );
  OR2   Hfound0r__or000026 (
    .I0(Hfound0r__or000023_927),
    .I1(Hfound0r__or000024_928),
    .O(Hfound0r__or0000_bdd0)
  );
  INV   Hfound0r__or000011 (
    .I(DCORENCCTLw),
    .O(Hfound0r__or00001)
  );
  AND2   Hfound0r__or000012 (
    .I0(SFDecomp_74),
    .I1(Hfound0r__or00001),
    .O(Hfound0r__or000011_923)
  );
  OR2   Hfound0r__or000013 (
    .I0(Reset),
    .I1(Hfound0r__or000011_923),
    .O(Hfound0r__or0000)
  );
  OR2   latchitH1__and000011 (
    .I0(RF1r_1073),
    .I1(Hfound1r__or0000_bdd3),
    .O(latchitH1__and00001)
  );
  INV   latchitH1__and000012 (
    .I(RF1r_1073),
    .O(latchitH1__and000011_1198)
  );
  AND2   latchitH1__and000013 (
    .I0(SFDecomp_71),
    .I1(latchitH1__and00001),
    .O(latchitH1__and000012_1199)
  );
  OR2   latchitH1__and000014 (
    .I0(Hfound1r__or0000_bdd2),
    .I1(latchitH1__and000011_1198),
    .O(latchitH1__and000013_1200)
  );
  AND2   latchitH1__and000015 (
    .I0(latchitH1__and000012_1199),
    .I1(latchitH1__and000013_1200),
    .O(latchitH1__and0000)
  );
  INV   Hfound1r__or000041 (
    .I(HE1stater_913),
    .O(Hfound1r__or00004)
  );
  INV   Hfound1r__or000042 (
    .I(NlwRenamedSig_OI_Hfound1),
    .O(Hfound1r__or000041_954)
  );
  AND3   Hfound1r__or000043 (
    .I0(Hfound1r__or00004),
    .I1(HE1statelastr_912),
    .I2(Hfound1r__or000041_954),
    .O(Hfound1r__or0000_bdd3)
  );
  INV   Hfound1r__or000031 (
    .I(NlwRenamedSig_OI_Hfound1),
    .O(Hfound1r__or00003)
  );
  INV   Hfound1r__or000032 (
    .I(HE1statelastr_912),
    .O(Hfound1r__or000031_952)
  );
  AND3   Hfound1r__or000033 (
    .I0(Hfound1r__or00003),
    .I1(HE1stater_913),
    .I2(Hfound1r__or000031_952),
    .O(Hfound1r__or0000_bdd2)
  );
  OR2   Hfound1r__or000021 (
    .I0(DCORIFGw),
    .I1(Hfound1r__or0000_bdd2),
    .O(Hfound1r__or00002)
  );
  OR2   Hfound1r__or000022 (
    .I0(DCORIFGw),
    .I1(Hfound1r__or0000_bdd3),
    .O(Hfound1r__or000021_947)
  );
  INV   Hfound1r__or000023 (
    .I(RF1r_1073),
    .O(Hfound1r__or000022_948)
  );
  AND2   Hfound1r__or000024 (
    .I0(RF1r_1073),
    .I1(Hfound1r__or00002),
    .O(Hfound1r__or000023_949)
  );
  AND2   Hfound1r__or000025 (
    .I0(Hfound1r__or000021_947),
    .I1(Hfound1r__or000022_948),
    .O(Hfound1r__or000024_950)
  );
  OR2   Hfound1r__or000026 (
    .I0(Hfound1r__or000023_949),
    .I1(Hfound1r__or000024_950),
    .O(Hfound1r__or0000_bdd0)
  );
  INV   Hfound1r__or000011 (
    .I(DCORENCCTLw),
    .O(Hfound1r__or00001)
  );
  AND2   Hfound1r__or000012 (
    .I0(SFDecomp_77),
    .I1(Hfound1r__or00001),
    .O(Hfound1r__or000011_945)
  );
  OR2   Hfound1r__or000013 (
    .I0(Reset),
    .I1(Hfound1r__or000011_945),
    .O(Hfound1r__or0000)
  );
  INV   Tfound0r_not00011 (
    .I(Tfound0r_or0000),
    .O(Tfound0r_not0001)
  );
  OR3   Tfound0r_or00001 (
    .I0(DCORENCCTLw),
    .I1(Tfound0r_and0000),
    .I2(Reset),
    .O(Tfound0r_or0000)
  );
  INV   Tfound0r_and00001 (
    .I(latchitL0_cmp_eq0001),
    .O(Tfound0r_and00001_1156)
  );
  INV   Tfound0r_and00002 (
    .I(latchitL0_cmp_eq0000),
    .O(Tfound0r_and00002_1157)
  );
  INV   Tfound0r_and00003 (
    .I(DCORIFGw),
    .O(Tfound0r_and00003_1158)
  );
  AND3   Tfound0r_and00004 (
    .I0(Tfound0r_and00002_1157),
    .I1(Tfound0r_and00001_1156),
    .I2(Tfound0r_and00003_1158),
    .O(Tfound0r_and0000)
  );
  INV   latchitL0_cmp_eq00011 (
    .I(LatchEdge0r_1062),
    .O(latchitL0_cmp_eq00011_1211)
  );
  INV   latchitL0_cmp_eq00012 (
    .I(InEdge0r_960),
    .O(latchitL0_cmp_eq00012_1212)
  );
  INV   latchitL0_cmp_eq00013 (
    .I(NlwRenamedSig_OI_Tfound0),
    .O(latchitL0_cmp_eq00013_1213)
  );
  AND4   latchitL0_cmp_eq00014 (
    .I0(LastEdge0r_962),
    .I1(latchitL0_cmp_eq00011_1211),
    .I2(latchitL0_cmp_eq00012_1212),
    .I3(latchitL0_cmp_eq00013_1213),
    .O(latchitL0_cmp_eq0001)
  );
  OR2   latchitL0__and00001 (
    .I0(latchitL0_cmp_eq0001),
    .I1(latchitL0_cmp_eq0000),
    .O(latchitL0__and00001_1203)
  );
  INV   latchitL0__and00002 (
    .I(Reset),
    .O(latchitL0__and00002_1204)
  );
  AND2   latchitL0__and00003 (
    .I0(latchitL0__and00001_1203),
    .I1(latchitL0__and00002_1204),
    .O(latchitL0__and0000)
  );
  AND2   latchitL0_cmp_eq00001 (
    .I0(LatchEdge0r_1062),
    .I1(InEdge0r_960),
    .O(latchitL0_cmp_eq00001_1206)
  );
  INV   latchitL0_cmp_eq00002 (
    .I(LastEdge0r_962),
    .O(latchitL0_cmp_eq00002_1207)
  );
  INV   latchitL0_cmp_eq00003 (
    .I(NlwRenamedSig_OI_Tfound0),
    .O(latchitL0_cmp_eq00003_1208)
  );
  AND2   latchitL0_cmp_eq00004 (
    .I0(latchitL0_cmp_eq00002_1207),
    .I1(latchitL0_cmp_eq00003_1208),
    .O(latchitL0_cmp_eq00004_1209)
  );
  AND2   latchitL0_cmp_eq00005 (
    .I0(latchitL0_cmp_eq00001_1206),
    .I1(latchitL0_cmp_eq00004_1209),
    .O(latchitL0_cmp_eq0000)
  );
  INV   Tfound1r_not00011 (
    .I(Tfound1r_or0000),
    .O(Tfound1r_not0001)
  );
  OR3   Tfound1r_or00001 (
    .I0(DCORENCCTLw),
    .I1(Tfound1r_and0000),
    .I2(Reset),
    .O(Tfound1r_or0000)
  );
  INV   Tfound1r_and00001 (
    .I(latchitL1_cmp_eq0001),
    .O(Tfound1r_and00001_1167)
  );
  INV   Tfound1r_and00002 (
    .I(latchitL1_cmp_eq0000),
    .O(Tfound1r_and00002_1168)
  );
  INV   Tfound1r_and00003 (
    .I(DCORIFGw),
    .O(Tfound1r_and00003_1169)
  );
  AND3   Tfound1r_and00004 (
    .I0(Tfound1r_and00002_1168),
    .I1(Tfound1r_and00001_1167),
    .I2(Tfound1r_and00003_1169),
    .O(Tfound1r_and0000)
  );
  INV   latchitL1_cmp_eq00011 (
    .I(LatchEdge1r_1065),
    .O(latchitL1_cmp_eq00011_1224)
  );
  INV   latchitL1_cmp_eq00012 (
    .I(InEdge1r_961),
    .O(latchitL1_cmp_eq00012_1225)
  );
  INV   latchitL1_cmp_eq00013 (
    .I(NlwRenamedSig_OI_Tfound1),
    .O(latchitL1_cmp_eq00013_1226)
  );
  AND4   latchitL1_cmp_eq00014 (
    .I0(LastEdge1r_963),
    .I1(latchitL1_cmp_eq00011_1224),
    .I2(latchitL1_cmp_eq00012_1225),
    .I3(latchitL1_cmp_eq00013_1226),
    .O(latchitL1_cmp_eq0001)
  );
  OR2   latchitL1__and00001 (
    .I0(latchitL1_cmp_eq0001),
    .I1(latchitL1_cmp_eq0000),
    .O(latchitL1__and00001_1216)
  );
  INV   latchitL1__and00002 (
    .I(Reset),
    .O(latchitL1__and00002_1217)
  );
  AND2   latchitL1__and00003 (
    .I0(latchitL1__and00001_1216),
    .I1(latchitL1__and00002_1217),
    .O(latchitL1__and0000)
  );
  AND2   latchitL1_cmp_eq00001 (
    .I0(LatchEdge1r_1065),
    .I1(InEdge1r_961),
    .O(latchitL1_cmp_eq00001_1219)
  );
  INV   latchitL1_cmp_eq00002 (
    .I(LastEdge1r_963),
    .O(latchitL1_cmp_eq00002_1220)
  );
  INV   latchitL1_cmp_eq00003 (
    .I(NlwRenamedSig_OI_Tfound1),
    .O(latchitL1_cmp_eq00003_1221)
  );
  AND2   latchitL1_cmp_eq00004 (
    .I0(latchitL1_cmp_eq00002_1220),
    .I1(latchitL1_cmp_eq00003_1221),
    .O(latchitL1_cmp_eq00004_1222)
  );
  AND2   latchitL1_cmp_eq00005 (
    .I0(latchitL1_cmp_eq00001_1219),
    .I1(latchitL1_cmp_eq00004_1222),
    .O(latchitL1_cmp_eq0000)
  );
  INV   \outDATA<7>_not000011  (
    .I(DCORIFGr),
    .O(\outDATA<7>_not00001 )
  );
  AND2   \outDATA<7>_not000012  (
    .I0(\outDATA<6>_not0000_bdd0 ),
    .I1(\outDATA<7>_not00001 ),
    .O(\outDATA<7>_not000011_1239 )
  );
  OR2   \outDATA<7>_not000013  (
    .I0(DCOR0THRESLOWr),
    .I1(\outDATA<7>_not000011_1239 ),
    .O(\outDATA<7>_not0000 )
  );
  OR3   \outDATA<6>_not000021  (
    .I0(DCOR0THRESHIGHr),
    .I1(DCOR1THRESHIGHr),
    .I2(DCOR1THRESLOWr),
    .O(\outDATA<6>_not0000_bdd0 )
  );
  OR3   \outDATA<6>_not000011  (
    .I0(DCOR0THRESLOWr),
    .I1(DCORIFGr),
    .I2(\outDATA<6>_not0000_bdd0 ),
    .O(\outDATA<6>_not0000 )
  );
  AND2   SFDecomp_341 (
    .I0(DCOR1THRESLOWr),
    .I1(Latch1r[7]),
    .O(SFDecomp_341_1078)
  );
  INV   SFDecomp_342 (
    .I(DCOR1THRESLOWr),
    .O(SFDecomp_342_1079)
  );
  AND2   SFDecomp_343 (
    .I0(Latch1r[15]),
    .I1(SFDecomp_342_1079),
    .O(SFDecomp_343_1080)
  );
  OR2   SFDecomp_344 (
    .I0(SFDecomp_341_1078),
    .I1(SFDecomp_343_1080),
    .O(SFDecomp_34)
  );
  AND2   SFDecomp_361 (
    .I0(DCOR0THRESHIGHr),
    .I1(Latch0r[15]),
    .O(SFDecomp_361_1082)
  );
  INV   SFDecomp_362 (
    .I(DCOR0THRESHIGHr),
    .O(SFDecomp_362_1083)
  );
  AND2   SFDecomp_363 (
    .I0(SFDecomp_34),
    .I1(SFDecomp_362_1083),
    .O(SFDecomp_363_1084)
  );
  OR2   SFDecomp_364 (
    .I0(SFDecomp_361_1082),
    .I1(SFDecomp_363_1084),
    .O(SFDecomp_36)
  );
  AND2   SFDecomp_371 (
    .I0(DCOR1THRESLOWr),
    .I1(Latch1r[4]),
    .O(SFDecomp_371_1086)
  );
  INV   SFDecomp_372 (
    .I(DCOR1THRESLOWr),
    .O(SFDecomp_372_1087)
  );
  AND2   SFDecomp_373 (
    .I0(Latch1r[12]),
    .I1(SFDecomp_372_1087),
    .O(SFDecomp_373_1088)
  );
  OR2   SFDecomp_374 (
    .I0(SFDecomp_371_1086),
    .I1(SFDecomp_373_1088),
    .O(SFDecomp_37)
  );
  AND2   SFDecomp_391 (
    .I0(DCOR0THRESHIGHr),
    .I1(Latch0r[12]),
    .O(SFDecomp_391_1090)
  );
  INV   SFDecomp_392 (
    .I(DCOR0THRESHIGHr),
    .O(SFDecomp_392_1091)
  );
  AND2   SFDecomp_393 (
    .I0(SFDecomp_37),
    .I1(SFDecomp_392_1091),
    .O(SFDecomp_393_1092)
  );
  OR2   SFDecomp_394 (
    .I0(SFDecomp_391_1090),
    .I1(SFDecomp_393_1092),
    .O(SFDecomp_39)
  );
  AND2   SFDecomp_401 (
    .I0(DCOR1THRESLOWr),
    .I1(Latch1r[1]),
    .O(SFDecomp_401_1094)
  );
  INV   SFDecomp_402 (
    .I(DCOR1THRESLOWr),
    .O(SFDecomp_402_1095)
  );
  AND2   SFDecomp_403 (
    .I0(Latch1r[9]),
    .I1(SFDecomp_402_1095),
    .O(SFDecomp_403_1096)
  );
  OR2   SFDecomp_404 (
    .I0(SFDecomp_401_1094),
    .I1(SFDecomp_403_1096),
    .O(SFDecomp_40)
  );
  AND2   SFDecomp_421 (
    .I0(DCOR0THRESHIGHr),
    .I1(Latch0r[9]),
    .O(SFDecomp_421_1098)
  );
  INV   SFDecomp_422 (
    .I(DCOR0THRESHIGHr),
    .O(SFDecomp_422_1099)
  );
  AND2   SFDecomp_423 (
    .I0(SFDecomp_40),
    .I1(SFDecomp_422_1099),
    .O(SFDecomp_423_1100)
  );
  OR2   SFDecomp_424 (
    .I0(SFDecomp_421_1098),
    .I1(SFDecomp_423_1100),
    .O(SFDecomp_42)
  );
  AND2   SFDecomp_431 (
    .I0(DCOR1THRESLOWr),
    .I1(Latch1r[0]),
    .O(SFDecomp_431_1102)
  );
  INV   SFDecomp_432 (
    .I(DCOR1THRESLOWr),
    .O(SFDecomp_432_1103)
  );
  AND2   SFDecomp_433 (
    .I0(Latch1r[8]),
    .I1(SFDecomp_432_1103),
    .O(SFDecomp_433_1104)
  );
  OR2   SFDecomp_434 (
    .I0(SFDecomp_431_1102),
    .I1(SFDecomp_433_1104),
    .O(SFDecomp_43)
  );
  AND2   SFDecomp_451 (
    .I0(DCOR0THRESHIGHr),
    .I1(Latch0r[8]),
    .O(SFDecomp_451_1106)
  );
  INV   SFDecomp_452 (
    .I(DCOR0THRESHIGHr),
    .O(SFDecomp_452_1107)
  );
  AND2   SFDecomp_453 (
    .I0(SFDecomp_43),
    .I1(SFDecomp_452_1107),
    .O(SFDecomp_453_1108)
  );
  OR2   SFDecomp_454 (
    .I0(SFDecomp_451_1106),
    .I1(SFDecomp_453_1108),
    .O(SFDecomp_45)
  );
  AND2   SFDecomp_471 (
    .I0(DCOR0THRESHIGHr),
    .I1(Latch0r[14]),
    .O(SFDecomp_471_1110)
  );
  INV   SFDecomp_472 (
    .I(DCOR0THRESHIGHr),
    .O(SFDecomp_472_1111)
  );
  AND2   SFDecomp_473 (
    .I0(outDATA_6_mux0000_bdd0),
    .I1(SFDecomp_472_1111),
    .O(SFDecomp_473_1112)
  );
  OR2   SFDecomp_474 (
    .I0(SFDecomp_471_1110),
    .I1(SFDecomp_473_1112),
    .O(SFDecomp_47)
  );
  AND2   SFDecomp_481 (
    .I0(DCORIFGr),
    .I1(NlwRenamedSig_OI_Tfound1),
    .O(SFDecomp_48)
  );
  INV   SFDecomp_511 (
    .I(DCORIFGr),
    .O(SFDecomp_511_1115)
  );
  AND2   SFDecomp_512 (
    .I0(SFDecomp_47),
    .I1(SFDecomp_511_1115),
    .O(SFDecomp_512_1116)
  );
  OR2   SFDecomp_513 (
    .I0(SFDecomp_48),
    .I1(SFDecomp_512_1116),
    .O(SFDecomp_51)
  );
  AND2   SFDecomp_531 (
    .I0(DCOR0THRESHIGHr),
    .I1(Latch0r[13]),
    .O(SFDecomp_531_1118)
  );
  INV   SFDecomp_532 (
    .I(DCOR0THRESHIGHr),
    .O(SFDecomp_532_1119)
  );
  AND2   SFDecomp_533 (
    .I0(outDATA_5_mux0000_bdd0),
    .I1(SFDecomp_532_1119),
    .O(SFDecomp_533_1120)
  );
  OR2   SFDecomp_534 (
    .I0(SFDecomp_531_1118),
    .I1(SFDecomp_533_1120),
    .O(SFDecomp_53)
  );
  AND2   SFDecomp_541 (
    .I0(DCORIFGr),
    .I1(NlwRenamedSig_OI_Tfound0),
    .O(SFDecomp_54)
  );
  INV   SFDecomp_571 (
    .I(DCORIFGr),
    .O(SFDecomp_571_1123)
  );
  AND2   SFDecomp_572 (
    .I0(SFDecomp_53),
    .I1(SFDecomp_571_1123),
    .O(SFDecomp_572_1124)
  );
  OR2   SFDecomp_573 (
    .I0(SFDecomp_54),
    .I1(SFDecomp_572_1124),
    .O(SFDecomp_57)
  );
  AND2   SFDecomp_591 (
    .I0(DCOR0THRESHIGHr),
    .I1(Latch0r[11]),
    .O(SFDecomp_591_1126)
  );
  INV   SFDecomp_592 (
    .I(DCOR0THRESHIGHr),
    .O(SFDecomp_592_1127)
  );
  AND2   SFDecomp_593 (
    .I0(outDATA_3_mux0000_bdd0),
    .I1(SFDecomp_592_1127),
    .O(SFDecomp_593_1128)
  );
  OR2   SFDecomp_594 (
    .I0(SFDecomp_591_1126),
    .I1(SFDecomp_593_1128),
    .O(SFDecomp_59)
  );
  AND2   SFDecomp_601 (
    .I0(DCORIFGr),
    .I1(NlwRenamedSig_OI_Hfound1),
    .O(SFDecomp_60)
  );
  INV   SFDecomp_631 (
    .I(DCORIFGr),
    .O(SFDecomp_631_1131)
  );
  AND2   SFDecomp_632 (
    .I0(SFDecomp_59),
    .I1(SFDecomp_631_1131),
    .O(SFDecomp_632_1132)
  );
  OR2   SFDecomp_633 (
    .I0(SFDecomp_60),
    .I1(SFDecomp_632_1132),
    .O(SFDecomp_63)
  );
  AND2   SFDecomp_651 (
    .I0(DCOR0THRESHIGHr),
    .I1(Latch0r[10]),
    .O(SFDecomp_651_1134)
  );
  INV   SFDecomp_652 (
    .I(DCOR0THRESHIGHr),
    .O(SFDecomp_652_1135)
  );
  AND2   SFDecomp_653 (
    .I0(outDATA_2_mux0000_bdd0),
    .I1(SFDecomp_652_1135),
    .O(SFDecomp_653_1136)
  );
  OR2   SFDecomp_654 (
    .I0(SFDecomp_651_1134),
    .I1(SFDecomp_653_1136),
    .O(SFDecomp_65)
  );
  AND2   SFDecomp_661 (
    .I0(DCORIFGr),
    .I1(NlwRenamedSig_OI_Hfound0),
    .O(SFDecomp_66)
  );
  INV   SFDecomp_691 (
    .I(DCORIFGr),
    .O(SFDecomp_691_1139)
  );
  AND2   SFDecomp_692 (
    .I0(SFDecomp_65),
    .I1(SFDecomp_691_1139),
    .O(SFDecomp_692_1140)
  );
  OR2   SFDecomp_693 (
    .I0(SFDecomp_66),
    .I1(SFDecomp_692_1140),
    .O(SFDecomp_69)
  );
  INV   SFDecomp_701 (
    .I(Reset),
    .O(SFDecomp_701_1142)
  );
  AND2   SFDecomp_702 (
    .I0(E0r_902),
    .I1(SFDecomp_701_1142),
    .O(SFDecomp_70)
  );
  INV   SFDecomp_711 (
    .I(Reset),
    .O(SFDecomp_711_1144)
  );
  AND2   SFDecomp_712 (
    .I0(E1r_907),
    .I1(SFDecomp_711_1144),
    .O(SFDecomp_71)
  );
  AND2   SFDecomp_741 (
    .I0(E0r_902),
    .I1(Hfound0r__or0000_bdd0),
    .O(SFDecomp_741_1146)
  );
  INV   SFDecomp_742 (
    .I(E0r_902),
    .O(SFDecomp_742_1147)
  );
  AND2   SFDecomp_743 (
    .I0(DCORIFGw),
    .I1(SFDecomp_742_1147),
    .O(SFDecomp_743_1148)
  );
  OR2   SFDecomp_744 (
    .I0(SFDecomp_741_1146),
    .I1(SFDecomp_743_1148),
    .O(SFDecomp_74)
  );
  AND2   SFDecomp_771 (
    .I0(E1r_907),
    .I1(Hfound1r__or0000_bdd0),
    .O(SFDecomp_771_1150)
  );
  INV   SFDecomp_772 (
    .I(E1r_907),
    .O(SFDecomp_772_1151)
  );
  AND2   SFDecomp_773 (
    .I0(DCORIFGw),
    .I1(SFDecomp_772_1151),
    .O(SFDecomp_773_1152)
  );
  OR2   SFDecomp_774 (
    .I0(SFDecomp_771_1150),
    .I1(SFDecomp_773_1152),
    .O(SFDecomp_77)
  );
endmodule

module Holdreg (
  DCOR0CNTLOWr, DCOR1CNTHIGHr, Reset, DCOR0CNTHIGHr, Sclk, DCOR1CNTLOWr, ASleading, outDATA, ch0in, ch1in
);
  input DCOR0CNTLOWr;
  input DCOR1CNTHIGHr;
  input Reset;
  input DCOR0CNTHIGHr;
  input Sclk;
  input DCOR1CNTLOWr;
  input ASleading;
  output [7 : 0] outDATA;
  input [15 : 0] ch0in;
  input [15 : 0] ch1in;
  wire N2;
  wire SFDecomp_10;
  wire SFDecomp_101_628;
  wire SFDecomp_102_629;
  wire SFDecomp_103_630;
  wire SFDecomp_12;
  wire SFDecomp_121_632;
  wire SFDecomp_122_633;
  wire SFDecomp_123_634;
  wire SFDecomp_13;
  wire SFDecomp_131_636;
  wire SFDecomp_132_637;
  wire SFDecomp_133_638;
  wire SFDecomp_15;
  wire SFDecomp_151_640;
  wire SFDecomp_152_641;
  wire SFDecomp_153_642;
  wire SFDecomp_16;
  wire SFDecomp_161_644;
  wire SFDecomp_162_645;
  wire SFDecomp_163_646;
  wire SFDecomp_18;
  wire SFDecomp_181_648;
  wire SFDecomp_182_649;
  wire SFDecomp_183_650;
  wire SFDecomp_19;
  wire SFDecomp_191_652;
  wire SFDecomp_192_653;
  wire SFDecomp_193_654;
  wire SFDecomp_21;
  wire SFDecomp_211_656;
  wire SFDecomp_212_657;
  wire SFDecomp_213_658;
  wire SFDecomp_22;
  wire SFDecomp_221_660;
  wire SFDecomp_222_661;
  wire SFDecomp_223_662;
  wire SFDecomp_24;
  wire SFDecomp_241_664;
  wire SFDecomp_242_665;
  wire SFDecomp_243_666;
  wire SFDecomp_25;
  wire SFDecomp_251_668;
  wire SFDecomp_252_669;
  wire SFDecomp_253_670;
  wire SFDecomp_27;
  wire SFDecomp_271_672;
  wire SFDecomp_272_673;
  wire SFDecomp_273_674;
  wire SFDecomp_28;
  wire SFDecomp_281_676;
  wire SFDecomp_282_677;
  wire SFDecomp_283_678;
  wire SFDecomp_30;
  wire SFDecomp_301_680;
  wire SFDecomp_302_681;
  wire SFDecomp_303_682;
  wire SFDecomp_31;
  wire SFDecomp_311_684;
  wire SFDecomp_312_685;
  wire SFDecomp_313_686;
  wire SFDecomp_33;
  wire SFDecomp_331_688;
  wire SFDecomp_332_689;
  wire SFDecomp_333_690;
  wire holdingreg0_0_0_not0000;
  wire holdingreg0_0__and0000;
  wire holdingreg0_0__and00001_727;
  wire holdingreg0_0__or0000;
  wire holdingreg0_10__and0000;
  wire holdingreg0_10__and00001_732;
  wire holdingreg0_11__and0000;
  wire holdingreg0_11__and00001_735;
  wire holdingreg0_12__and0000;
  wire holdingreg0_12__and00001_738;
  wire holdingreg0_13__and0000;
  wire holdingreg0_13__and00001_741;
  wire holdingreg0_14__and0000;
  wire holdingreg0_14__and00001_744;
  wire holdingreg0_15__and0000;
  wire holdingreg0_15__and00001_747;
  wire holdingreg0_1__and0000;
  wire holdingreg0_1__and00001_749;
  wire holdingreg0_2__and0000;
  wire holdingreg0_2__and00001_752;
  wire holdingreg0_3__and0000;
  wire holdingreg0_3__and00001_755;
  wire holdingreg0_4__and0000;
  wire holdingreg0_4__and00001_758;
  wire holdingreg0_5__and0000;
  wire holdingreg0_5__and00001_761;
  wire holdingreg0_6__and0000;
  wire holdingreg0_6__and00001_764;
  wire holdingreg0_7__and0000;
  wire holdingreg0_7__and00001_767;
  wire holdingreg0_8__and0000;
  wire holdingreg0_8__and00001_770;
  wire holdingreg0_9__and0000;
  wire holdingreg0_9__and00001_773;
  wire holdingreg1_0__and0000;
  wire holdingreg1_0__and00001_776;
  wire holdingreg1_10__and0000;
  wire holdingreg1_10__and00001_780;
  wire holdingreg1_11__and0000;
  wire holdingreg1_11__and00001_783;
  wire holdingreg1_12__and0000;
  wire holdingreg1_12__and00001_786;
  wire holdingreg1_13__and0000;
  wire holdingreg1_13__and00001_789;
  wire holdingreg1_14__and0000;
  wire holdingreg1_14__and00001_792;
  wire holdingreg1_15__and0000;
  wire holdingreg1_15__and00001_795;
  wire holdingreg1_1__and0000;
  wire holdingreg1_1__and00001_797;
  wire holdingreg1_2__and0000;
  wire holdingreg1_2__and00001_800;
  wire holdingreg1_3__and0000;
  wire holdingreg1_3__and00001_803;
  wire holdingreg1_4__and0000;
  wire holdingreg1_4__and00001_806;
  wire holdingreg1_5__and0000;
  wire holdingreg1_5__and00001_809;
  wire holdingreg1_6__and0000;
  wire holdingreg1_6__and00001_812;
  wire holdingreg1_7__and0000;
  wire holdingreg1_7__and00001_815;
  wire holdingreg1_8__and0000;
  wire holdingreg1_8__and00001_818;
  wire holdingreg1_9__and0000;
  wire holdingreg1_9__and00001_821;
  wire \interDATA_mux0000<0>1 ;
  wire \interDATA_mux0000<0>11_832 ;
  wire \interDATA_mux0000<0>12_833 ;
  wire \interDATA_mux0000<1>1 ;
  wire \interDATA_mux0000<1>11_836 ;
  wire \interDATA_mux0000<1>12_837 ;
  wire \interDATA_mux0000<2>1 ;
  wire \interDATA_mux0000<2>11_840 ;
  wire \interDATA_mux0000<2>12_841 ;
  wire \interDATA_mux0000<3>1 ;
  wire \interDATA_mux0000<3>11_844 ;
  wire \interDATA_mux0000<3>12_845 ;
  wire \interDATA_mux0000<4>1 ;
  wire \interDATA_mux0000<4>11_848 ;
  wire \interDATA_mux0000<4>12_849 ;
  wire \interDATA_mux0000<5>1 ;
  wire \interDATA_mux0000<5>11_852 ;
  wire \interDATA_mux0000<5>12_853 ;
  wire \interDATA_mux0000<6>1 ;
  wire \interDATA_mux0000<6>11_856 ;
  wire \interDATA_mux0000<6>12_857 ;
  wire \interDATA_mux0000<7>1 ;
  wire \interDATA_mux0000<7>11_860 ;
  wire \interDATA_mux0000<7>12_861 ;
  wire interDATA_not0001;
  wire [15 : 0] holdingreg0;
  wire [15 : 0] holdingreg1;
  wire [7 : 0] interDATA;
  wire [7 : 0] interDATA_mux0000;
  assign
    outDATA[7] = interDATA[7],
    outDATA[6] = interDATA[6],
    outDATA[5] = interDATA[5],
    outDATA[4] = interDATA[4],
    outDATA[3] = interDATA[3],
    outDATA[2] = interDATA[2],
    outDATA[1] = interDATA[1],
    outDATA[0] = interDATA[0];
  BUFE   interDATA_7 (
    .I(interDATA_mux0000[7]),
    .E(interDATA_not0001),
    .O(interDATA[7])
  );
  BUFE   interDATA_6 (
    .I(interDATA_mux0000[6]),
    .E(interDATA_not0001),
    .O(interDATA[6])
  );
  BUFE   interDATA_5 (
    .I(interDATA_mux0000[5]),
    .E(interDATA_not0001),
    .O(interDATA[5])
  );
  BUFE   interDATA_4 (
    .I(interDATA_mux0000[4]),
    .E(interDATA_not0001),
    .O(interDATA[4])
  );
  BUFE   interDATA_3 (
    .I(interDATA_mux0000[3]),
    .E(interDATA_not0001),
    .O(interDATA[3])
  );
  BUFE   interDATA_2 (
    .I(interDATA_mux0000[2]),
    .E(interDATA_not0001),
    .O(interDATA[2])
  );
  BUFE   interDATA_1 (
    .I(interDATA_mux0000[1]),
    .E(interDATA_not0001),
    .O(interDATA[1])
  );
  BUFE   interDATA_0 (
    .I(interDATA_mux0000[0]),
    .E(interDATA_not0001),
    .O(interDATA[0])
  );
  FDCE   holdingreg1_0 (
    .CE(holdingreg0_0__or0000),
    .CLR(N2),
    .C(holdingreg0_0_0_not0000),
    .D(holdingreg1_0__and0000),
    .Q(holdingreg1[0])
  );
  FDCE   holdingreg1_1 (
    .CE(holdingreg0_0__or0000),
    .CLR(N2),
    .C(holdingreg0_0_0_not0000),
    .D(holdingreg1_1__and0000),
    .Q(holdingreg1[1])
  );
  FDCE   holdingreg1_2 (
    .CE(holdingreg0_0__or0000),
    .CLR(N2),
    .C(holdingreg0_0_0_not0000),
    .D(holdingreg1_2__and0000),
    .Q(holdingreg1[2])
  );
  FDCE   holdingreg1_3 (
    .CE(holdingreg0_0__or0000),
    .CLR(N2),
    .C(holdingreg0_0_0_not0000),
    .D(holdingreg1_3__and0000),
    .Q(holdingreg1[3])
  );
  FDCE   holdingreg1_4 (
    .CE(holdingreg0_0__or0000),
    .CLR(N2),
    .C(holdingreg0_0_0_not0000),
    .D(holdingreg1_4__and0000),
    .Q(holdingreg1[4])
  );
  FDCE   holdingreg1_5 (
    .CE(holdingreg0_0__or0000),
    .CLR(N2),
    .C(holdingreg0_0_0_not0000),
    .D(holdingreg1_5__and0000),
    .Q(holdingreg1[5])
  );
  FDCE   holdingreg1_6 (
    .CE(holdingreg0_0__or0000),
    .CLR(N2),
    .C(holdingreg0_0_0_not0000),
    .D(holdingreg1_6__and0000),
    .Q(holdingreg1[6])
  );
  FDCE   holdingreg1_7 (
    .CE(holdingreg0_0__or0000),
    .CLR(N2),
    .C(holdingreg0_0_0_not0000),
    .D(holdingreg1_7__and0000),
    .Q(holdingreg1[7])
  );
  FDCE   holdingreg1_8 (
    .CE(holdingreg0_0__or0000),
    .CLR(N2),
    .C(holdingreg0_0_0_not0000),
    .D(holdingreg1_8__and0000),
    .Q(holdingreg1[8])
  );
  FDCE   holdingreg1_9 (
    .CE(holdingreg0_0__or0000),
    .CLR(N2),
    .C(holdingreg0_0_0_not0000),
    .D(holdingreg1_9__and0000),
    .Q(holdingreg1[9])
  );
  FDCE   holdingreg1_10 (
    .CE(holdingreg0_0__or0000),
    .CLR(N2),
    .C(holdingreg0_0_0_not0000),
    .D(holdingreg1_10__and0000),
    .Q(holdingreg1[10])
  );
  FDCE   holdingreg1_11 (
    .CE(holdingreg0_0__or0000),
    .CLR(N2),
    .C(holdingreg0_0_0_not0000),
    .D(holdingreg1_11__and0000),
    .Q(holdingreg1[11])
  );
  FDCE   holdingreg1_12 (
    .CE(holdingreg0_0__or0000),
    .CLR(N2),
    .C(holdingreg0_0_0_not0000),
    .D(holdingreg1_12__and0000),
    .Q(holdingreg1[12])
  );
  FDCE   holdingreg1_13 (
    .CE(holdingreg0_0__or0000),
    .CLR(N2),
    .C(holdingreg0_0_0_not0000),
    .D(holdingreg1_13__and0000),
    .Q(holdingreg1[13])
  );
  FDCE   holdingreg1_14 (
    .CE(holdingreg0_0__or0000),
    .CLR(N2),
    .C(holdingreg0_0_0_not0000),
    .D(holdingreg1_14__and0000),
    .Q(holdingreg1[14])
  );
  FDCE   holdingreg1_15 (
    .CE(holdingreg0_0__or0000),
    .CLR(N2),
    .C(holdingreg0_0_0_not0000),
    .D(holdingreg1_15__and0000),
    .Q(holdingreg1[15])
  );
  GND   XST_GND (
    .G(N2)
  );
  FDCE   holdingreg0_0 (
    .CE(holdingreg0_0__or0000),
    .CLR(N2),
    .C(holdingreg0_0_0_not0000),
    .D(holdingreg0_0__and0000),
    .Q(holdingreg0[0])
  );
  FDCE   holdingreg0_1 (
    .CE(holdingreg0_0__or0000),
    .CLR(N2),
    .C(holdingreg0_0_0_not0000),
    .D(holdingreg0_1__and0000),
    .Q(holdingreg0[1])
  );
  FDCE   holdingreg0_2 (
    .CE(holdingreg0_0__or0000),
    .CLR(N2),
    .C(holdingreg0_0_0_not0000),
    .D(holdingreg0_2__and0000),
    .Q(holdingreg0[2])
  );
  FDCE   holdingreg0_3 (
    .CE(holdingreg0_0__or0000),
    .CLR(N2),
    .C(holdingreg0_0_0_not0000),
    .D(holdingreg0_3__and0000),
    .Q(holdingreg0[3])
  );
  FDCE   holdingreg0_4 (
    .CE(holdingreg0_0__or0000),
    .CLR(N2),
    .C(holdingreg0_0_0_not0000),
    .D(holdingreg0_4__and0000),
    .Q(holdingreg0[4])
  );
  FDCE   holdingreg0_5 (
    .CE(holdingreg0_0__or0000),
    .CLR(N2),
    .C(holdingreg0_0_0_not0000),
    .D(holdingreg0_5__and0000),
    .Q(holdingreg0[5])
  );
  FDCE   holdingreg0_6 (
    .CE(holdingreg0_0__or0000),
    .CLR(N2),
    .C(holdingreg0_0_0_not0000),
    .D(holdingreg0_6__and0000),
    .Q(holdingreg0[6])
  );
  FDCE   holdingreg0_7 (
    .CE(holdingreg0_0__or0000),
    .CLR(N2),
    .C(holdingreg0_0_0_not0000),
    .D(holdingreg0_7__and0000),
    .Q(holdingreg0[7])
  );
  FDCE   holdingreg0_8 (
    .CE(holdingreg0_0__or0000),
    .CLR(N2),
    .C(holdingreg0_0_0_not0000),
    .D(holdingreg0_8__and0000),
    .Q(holdingreg0[8])
  );
  FDCE   holdingreg0_9 (
    .CE(holdingreg0_0__or0000),
    .CLR(N2),
    .C(holdingreg0_0_0_not0000),
    .D(holdingreg0_9__and0000),
    .Q(holdingreg0[9])
  );
  FDCE   holdingreg0_10 (
    .CE(holdingreg0_0__or0000),
    .CLR(N2),
    .C(holdingreg0_0_0_not0000),
    .D(holdingreg0_10__and0000),
    .Q(holdingreg0[10])
  );
  FDCE   holdingreg0_11 (
    .CE(holdingreg0_0__or0000),
    .CLR(N2),
    .C(holdingreg0_0_0_not0000),
    .D(holdingreg0_11__and0000),
    .Q(holdingreg0[11])
  );
  FDCE   holdingreg0_12 (
    .CE(holdingreg0_0__or0000),
    .CLR(N2),
    .C(holdingreg0_0_0_not0000),
    .D(holdingreg0_12__and0000),
    .Q(holdingreg0[12])
  );
  FDCE   holdingreg0_13 (
    .CE(holdingreg0_0__or0000),
    .CLR(N2),
    .C(holdingreg0_0_0_not0000),
    .D(holdingreg0_13__and0000),
    .Q(holdingreg0[13])
  );
  FDCE   holdingreg0_14 (
    .CE(holdingreg0_0__or0000),
    .CLR(N2),
    .C(holdingreg0_0_0_not0000),
    .D(holdingreg0_14__and0000),
    .Q(holdingreg0[14])
  );
  FDCE   holdingreg0_15 (
    .CE(holdingreg0_0__or0000),
    .CLR(N2),
    .C(holdingreg0_0_0_not0000),
    .D(holdingreg0_15__and0000),
    .Q(holdingreg0[15])
  );
  INV   holdingreg1_0__and00001 (
    .I(Reset),
    .O(holdingreg1_0__and00001_776)
  );
  AND2   holdingreg1_0__and00002 (
    .I0(ch1in[0]),
    .I1(holdingreg1_0__and00001_776),
    .O(holdingreg1_0__and0000)
  );
  INV   holdingreg1_1__and00001 (
    .I(Reset),
    .O(holdingreg1_1__and00001_797)
  );
  AND2   holdingreg1_1__and00002 (
    .I0(ch1in[1]),
    .I1(holdingreg1_1__and00001_797),
    .O(holdingreg1_1__and0000)
  );
  INV   holdingreg1_2__and00001 (
    .I(Reset),
    .O(holdingreg1_2__and00001_800)
  );
  AND2   holdingreg1_2__and00002 (
    .I0(ch1in[2]),
    .I1(holdingreg1_2__and00001_800),
    .O(holdingreg1_2__and0000)
  );
  INV   holdingreg1_3__and00001 (
    .I(Reset),
    .O(holdingreg1_3__and00001_803)
  );
  AND2   holdingreg1_3__and00002 (
    .I0(ch1in[3]),
    .I1(holdingreg1_3__and00001_803),
    .O(holdingreg1_3__and0000)
  );
  INV   holdingreg1_4__and00001 (
    .I(Reset),
    .O(holdingreg1_4__and00001_806)
  );
  AND2   holdingreg1_4__and00002 (
    .I0(ch1in[4]),
    .I1(holdingreg1_4__and00001_806),
    .O(holdingreg1_4__and0000)
  );
  INV   holdingreg1_5__and00001 (
    .I(Reset),
    .O(holdingreg1_5__and00001_809)
  );
  AND2   holdingreg1_5__and00002 (
    .I0(ch1in[5]),
    .I1(holdingreg1_5__and00001_809),
    .O(holdingreg1_5__and0000)
  );
  INV   holdingreg1_6__and00001 (
    .I(Reset),
    .O(holdingreg1_6__and00001_812)
  );
  AND2   holdingreg1_6__and00002 (
    .I0(ch1in[6]),
    .I1(holdingreg1_6__and00001_812),
    .O(holdingreg1_6__and0000)
  );
  INV   holdingreg1_7__and00001 (
    .I(Reset),
    .O(holdingreg1_7__and00001_815)
  );
  AND2   holdingreg1_7__and00002 (
    .I0(ch1in[7]),
    .I1(holdingreg1_7__and00001_815),
    .O(holdingreg1_7__and0000)
  );
  INV   holdingreg1_8__and00001 (
    .I(Reset),
    .O(holdingreg1_8__and00001_818)
  );
  AND2   holdingreg1_8__and00002 (
    .I0(ch1in[8]),
    .I1(holdingreg1_8__and00001_818),
    .O(holdingreg1_8__and0000)
  );
  INV   holdingreg1_9__and00001 (
    .I(Reset),
    .O(holdingreg1_9__and00001_821)
  );
  AND2   holdingreg1_9__and00002 (
    .I0(ch1in[9]),
    .I1(holdingreg1_9__and00001_821),
    .O(holdingreg1_9__and0000)
  );
  INV   holdingreg1_10__and00001 (
    .I(Reset),
    .O(holdingreg1_10__and00001_780)
  );
  AND2   holdingreg1_10__and00002 (
    .I0(ch1in[10]),
    .I1(holdingreg1_10__and00001_780),
    .O(holdingreg1_10__and0000)
  );
  INV   holdingreg1_11__and00001 (
    .I(Reset),
    .O(holdingreg1_11__and00001_783)
  );
  AND2   holdingreg1_11__and00002 (
    .I0(ch1in[11]),
    .I1(holdingreg1_11__and00001_783),
    .O(holdingreg1_11__and0000)
  );
  INV   holdingreg1_12__and00001 (
    .I(Reset),
    .O(holdingreg1_12__and00001_786)
  );
  AND2   holdingreg1_12__and00002 (
    .I0(ch1in[12]),
    .I1(holdingreg1_12__and00001_786),
    .O(holdingreg1_12__and0000)
  );
  INV   holdingreg1_13__and00001 (
    .I(Reset),
    .O(holdingreg1_13__and00001_789)
  );
  AND2   holdingreg1_13__and00002 (
    .I0(ch1in[13]),
    .I1(holdingreg1_13__and00001_789),
    .O(holdingreg1_13__and0000)
  );
  INV   holdingreg1_14__and00001 (
    .I(Reset),
    .O(holdingreg1_14__and00001_792)
  );
  AND2   holdingreg1_14__and00002 (
    .I0(ch1in[14]),
    .I1(holdingreg1_14__and00001_792),
    .O(holdingreg1_14__and0000)
  );
  INV   holdingreg1_15__and00001 (
    .I(Reset),
    .O(holdingreg1_15__and00001_795)
  );
  AND2   holdingreg1_15__and00002 (
    .I0(ch1in[15]),
    .I1(holdingreg1_15__and00001_795),
    .O(holdingreg1_15__and0000)
  );
  INV   holdingreg0_0__and00001 (
    .I(Reset),
    .O(holdingreg0_0__and00001_727)
  );
  AND2   holdingreg0_0__and00002 (
    .I0(ch0in[0]),
    .I1(holdingreg0_0__and00001_727),
    .O(holdingreg0_0__and0000)
  );
  OR2   holdingreg0_0__or00001 (
    .I0(ASleading),
    .I1(Reset),
    .O(holdingreg0_0__or0000)
  );
  INV   holdingreg0_0_0_not00001 (
    .I(Sclk),
    .O(holdingreg0_0_0_not0000)
  );
  INV   holdingreg0_1__and00001 (
    .I(Reset),
    .O(holdingreg0_1__and00001_749)
  );
  AND2   holdingreg0_1__and00002 (
    .I0(ch0in[1]),
    .I1(holdingreg0_1__and00001_749),
    .O(holdingreg0_1__and0000)
  );
  INV   holdingreg0_2__and00001 (
    .I(Reset),
    .O(holdingreg0_2__and00001_752)
  );
  AND2   holdingreg0_2__and00002 (
    .I0(ch0in[2]),
    .I1(holdingreg0_2__and00001_752),
    .O(holdingreg0_2__and0000)
  );
  INV   holdingreg0_3__and00001 (
    .I(Reset),
    .O(holdingreg0_3__and00001_755)
  );
  AND2   holdingreg0_3__and00002 (
    .I0(ch0in[3]),
    .I1(holdingreg0_3__and00001_755),
    .O(holdingreg0_3__and0000)
  );
  INV   holdingreg0_4__and00001 (
    .I(Reset),
    .O(holdingreg0_4__and00001_758)
  );
  AND2   holdingreg0_4__and00002 (
    .I0(ch0in[4]),
    .I1(holdingreg0_4__and00001_758),
    .O(holdingreg0_4__and0000)
  );
  INV   holdingreg0_5__and00001 (
    .I(Reset),
    .O(holdingreg0_5__and00001_761)
  );
  AND2   holdingreg0_5__and00002 (
    .I0(ch0in[5]),
    .I1(holdingreg0_5__and00001_761),
    .O(holdingreg0_5__and0000)
  );
  INV   holdingreg0_6__and00001 (
    .I(Reset),
    .O(holdingreg0_6__and00001_764)
  );
  AND2   holdingreg0_6__and00002 (
    .I0(ch0in[6]),
    .I1(holdingreg0_6__and00001_764),
    .O(holdingreg0_6__and0000)
  );
  INV   holdingreg0_7__and00001 (
    .I(Reset),
    .O(holdingreg0_7__and00001_767)
  );
  AND2   holdingreg0_7__and00002 (
    .I0(ch0in[7]),
    .I1(holdingreg0_7__and00001_767),
    .O(holdingreg0_7__and0000)
  );
  INV   holdingreg0_8__and00001 (
    .I(Reset),
    .O(holdingreg0_8__and00001_770)
  );
  AND2   holdingreg0_8__and00002 (
    .I0(ch0in[8]),
    .I1(holdingreg0_8__and00001_770),
    .O(holdingreg0_8__and0000)
  );
  INV   holdingreg0_9__and00001 (
    .I(Reset),
    .O(holdingreg0_9__and00001_773)
  );
  AND2   holdingreg0_9__and00002 (
    .I0(ch0in[9]),
    .I1(holdingreg0_9__and00001_773),
    .O(holdingreg0_9__and0000)
  );
  INV   holdingreg0_10__and00001 (
    .I(Reset),
    .O(holdingreg0_10__and00001_732)
  );
  AND2   holdingreg0_10__and00002 (
    .I0(ch0in[10]),
    .I1(holdingreg0_10__and00001_732),
    .O(holdingreg0_10__and0000)
  );
  INV   holdingreg0_11__and00001 (
    .I(Reset),
    .O(holdingreg0_11__and00001_735)
  );
  AND2   holdingreg0_11__and00002 (
    .I0(ch0in[11]),
    .I1(holdingreg0_11__and00001_735),
    .O(holdingreg0_11__and0000)
  );
  INV   holdingreg0_12__and00001 (
    .I(Reset),
    .O(holdingreg0_12__and00001_738)
  );
  AND2   holdingreg0_12__and00002 (
    .I0(ch0in[12]),
    .I1(holdingreg0_12__and00001_738),
    .O(holdingreg0_12__and0000)
  );
  INV   holdingreg0_13__and00001 (
    .I(Reset),
    .O(holdingreg0_13__and00001_741)
  );
  AND2   holdingreg0_13__and00002 (
    .I0(ch0in[13]),
    .I1(holdingreg0_13__and00001_741),
    .O(holdingreg0_13__and0000)
  );
  INV   holdingreg0_14__and00001 (
    .I(Reset),
    .O(holdingreg0_14__and00001_744)
  );
  AND2   holdingreg0_14__and00002 (
    .I0(ch0in[14]),
    .I1(holdingreg0_14__and00001_744),
    .O(holdingreg0_14__and0000)
  );
  INV   holdingreg0_15__and00001 (
    .I(Reset),
    .O(holdingreg0_15__and00001_747)
  );
  AND2   holdingreg0_15__and00002 (
    .I0(ch0in[15]),
    .I1(holdingreg0_15__and00001_747),
    .O(holdingreg0_15__and0000)
  );
  AND2   \interDATA_mux0000<7>11  (
    .I0(DCOR0CNTLOWr),
    .I1(holdingreg0[7]),
    .O(\interDATA_mux0000<7>1 )
  );
  INV   \interDATA_mux0000<7>12  (
    .I(DCOR0CNTLOWr),
    .O(\interDATA_mux0000<7>11_860 )
  );
  AND2   \interDATA_mux0000<7>13  (
    .I0(SFDecomp_15),
    .I1(\interDATA_mux0000<7>11_860 ),
    .O(\interDATA_mux0000<7>12_861 )
  );
  OR2   \interDATA_mux0000<7>14  (
    .I0(\interDATA_mux0000<7>1 ),
    .I1(\interDATA_mux0000<7>12_861 ),
    .O(interDATA_mux0000[7])
  );
  AND2   \interDATA_mux0000<6>11  (
    .I0(DCOR0CNTLOWr),
    .I1(holdingreg0[6]),
    .O(\interDATA_mux0000<6>1 )
  );
  INV   \interDATA_mux0000<6>12  (
    .I(DCOR0CNTLOWr),
    .O(\interDATA_mux0000<6>11_856 )
  );
  AND2   \interDATA_mux0000<6>13  (
    .I0(SFDecomp_12),
    .I1(\interDATA_mux0000<6>11_856 ),
    .O(\interDATA_mux0000<6>12_857 )
  );
  OR2   \interDATA_mux0000<6>14  (
    .I0(\interDATA_mux0000<6>1 ),
    .I1(\interDATA_mux0000<6>12_857 ),
    .O(interDATA_mux0000[6])
  );
  AND2   \interDATA_mux0000<5>11  (
    .I0(DCOR0CNTLOWr),
    .I1(holdingreg0[5]),
    .O(\interDATA_mux0000<5>1 )
  );
  INV   \interDATA_mux0000<5>12  (
    .I(DCOR0CNTLOWr),
    .O(\interDATA_mux0000<5>11_852 )
  );
  AND2   \interDATA_mux0000<5>13  (
    .I0(SFDecomp_18),
    .I1(\interDATA_mux0000<5>11_852 ),
    .O(\interDATA_mux0000<5>12_853 )
  );
  OR2   \interDATA_mux0000<5>14  (
    .I0(\interDATA_mux0000<5>1 ),
    .I1(\interDATA_mux0000<5>12_853 ),
    .O(interDATA_mux0000[5])
  );
  AND2   \interDATA_mux0000<4>11  (
    .I0(DCOR0CNTLOWr),
    .I1(holdingreg0[4]),
    .O(\interDATA_mux0000<4>1 )
  );
  INV   \interDATA_mux0000<4>12  (
    .I(DCOR0CNTLOWr),
    .O(\interDATA_mux0000<4>11_848 )
  );
  AND2   \interDATA_mux0000<4>13  (
    .I0(SFDecomp_21),
    .I1(\interDATA_mux0000<4>11_848 ),
    .O(\interDATA_mux0000<4>12_849 )
  );
  OR2   \interDATA_mux0000<4>14  (
    .I0(\interDATA_mux0000<4>1 ),
    .I1(\interDATA_mux0000<4>12_849 ),
    .O(interDATA_mux0000[4])
  );
  AND2   \interDATA_mux0000<3>11  (
    .I0(DCOR0CNTLOWr),
    .I1(holdingreg0[3]),
    .O(\interDATA_mux0000<3>1 )
  );
  INV   \interDATA_mux0000<3>12  (
    .I(DCOR0CNTLOWr),
    .O(\interDATA_mux0000<3>11_844 )
  );
  AND2   \interDATA_mux0000<3>13  (
    .I0(SFDecomp_27),
    .I1(\interDATA_mux0000<3>11_844 ),
    .O(\interDATA_mux0000<3>12_845 )
  );
  OR2   \interDATA_mux0000<3>14  (
    .I0(\interDATA_mux0000<3>1 ),
    .I1(\interDATA_mux0000<3>12_845 ),
    .O(interDATA_mux0000[3])
  );
  AND2   \interDATA_mux0000<2>11  (
    .I0(DCOR0CNTLOWr),
    .I1(holdingreg0[2]),
    .O(\interDATA_mux0000<2>1 )
  );
  INV   \interDATA_mux0000<2>12  (
    .I(DCOR0CNTLOWr),
    .O(\interDATA_mux0000<2>11_840 )
  );
  AND2   \interDATA_mux0000<2>13  (
    .I0(SFDecomp_30),
    .I1(\interDATA_mux0000<2>11_840 ),
    .O(\interDATA_mux0000<2>12_841 )
  );
  OR2   \interDATA_mux0000<2>14  (
    .I0(\interDATA_mux0000<2>1 ),
    .I1(\interDATA_mux0000<2>12_841 ),
    .O(interDATA_mux0000[2])
  );
  AND2   \interDATA_mux0000<1>11  (
    .I0(DCOR0CNTLOWr),
    .I1(holdingreg0[1]),
    .O(\interDATA_mux0000<1>1 )
  );
  INV   \interDATA_mux0000<1>12  (
    .I(DCOR0CNTLOWr),
    .O(\interDATA_mux0000<1>11_836 )
  );
  AND2   \interDATA_mux0000<1>13  (
    .I0(SFDecomp_24),
    .I1(\interDATA_mux0000<1>11_836 ),
    .O(\interDATA_mux0000<1>12_837 )
  );
  OR2   \interDATA_mux0000<1>14  (
    .I0(\interDATA_mux0000<1>1 ),
    .I1(\interDATA_mux0000<1>12_837 ),
    .O(interDATA_mux0000[1])
  );
  AND2   \interDATA_mux0000<0>11  (
    .I0(DCOR0CNTLOWr),
    .I1(holdingreg0[0]),
    .O(\interDATA_mux0000<0>1 )
  );
  INV   \interDATA_mux0000<0>12  (
    .I(DCOR0CNTLOWr),
    .O(\interDATA_mux0000<0>11_832 )
  );
  AND2   \interDATA_mux0000<0>13  (
    .I0(SFDecomp_33),
    .I1(\interDATA_mux0000<0>11_832 ),
    .O(\interDATA_mux0000<0>12_833 )
  );
  OR2   \interDATA_mux0000<0>14  (
    .I0(\interDATA_mux0000<0>1 ),
    .I1(\interDATA_mux0000<0>12_833 ),
    .O(interDATA_mux0000[0])
  );
  OR4   interDATA_not000111 (
    .I0(DCOR0CNTHIGHr),
    .I1(DCOR1CNTHIGHr),
    .I2(DCOR0CNTLOWr),
    .I3(DCOR1CNTLOWr),
    .O(interDATA_not0001)
  );
  AND2   SFDecomp_101 (
    .I0(DCOR0CNTHIGHr),
    .I1(holdingreg0[14]),
    .O(SFDecomp_101_628)
  );
  INV   SFDecomp_102 (
    .I(DCOR0CNTHIGHr),
    .O(SFDecomp_102_629)
  );
  AND2   SFDecomp_103 (
    .I0(holdingreg1[14]),
    .I1(SFDecomp_102_629),
    .O(SFDecomp_103_630)
  );
  OR2   SFDecomp_104 (
    .I0(SFDecomp_101_628),
    .I1(SFDecomp_103_630),
    .O(SFDecomp_10)
  );
  AND2   SFDecomp_121 (
    .I0(DCOR1CNTLOWr),
    .I1(holdingreg1[6]),
    .O(SFDecomp_121_632)
  );
  INV   SFDecomp_122 (
    .I(DCOR1CNTLOWr),
    .O(SFDecomp_122_633)
  );
  AND2   SFDecomp_123 (
    .I0(SFDecomp_10),
    .I1(SFDecomp_122_633),
    .O(SFDecomp_123_634)
  );
  OR2   SFDecomp_124 (
    .I0(SFDecomp_121_632),
    .I1(SFDecomp_123_634),
    .O(SFDecomp_12)
  );
  AND2   SFDecomp_131 (
    .I0(DCOR0CNTHIGHr),
    .I1(holdingreg0[15]),
    .O(SFDecomp_131_636)
  );
  INV   SFDecomp_132 (
    .I(DCOR0CNTHIGHr),
    .O(SFDecomp_132_637)
  );
  AND2   SFDecomp_133 (
    .I0(holdingreg1[15]),
    .I1(SFDecomp_132_637),
    .O(SFDecomp_133_638)
  );
  OR2   SFDecomp_134 (
    .I0(SFDecomp_131_636),
    .I1(SFDecomp_133_638),
    .O(SFDecomp_13)
  );
  AND2   SFDecomp_151 (
    .I0(DCOR1CNTLOWr),
    .I1(holdingreg1[7]),
    .O(SFDecomp_151_640)
  );
  INV   SFDecomp_152 (
    .I(DCOR1CNTLOWr),
    .O(SFDecomp_152_641)
  );
  AND2   SFDecomp_153 (
    .I0(SFDecomp_13),
    .I1(SFDecomp_152_641),
    .O(SFDecomp_153_642)
  );
  OR2   SFDecomp_154 (
    .I0(SFDecomp_151_640),
    .I1(SFDecomp_153_642),
    .O(SFDecomp_15)
  );
  AND2   SFDecomp_161 (
    .I0(DCOR0CNTHIGHr),
    .I1(holdingreg0[13]),
    .O(SFDecomp_161_644)
  );
  INV   SFDecomp_162 (
    .I(DCOR0CNTHIGHr),
    .O(SFDecomp_162_645)
  );
  AND2   SFDecomp_163 (
    .I0(holdingreg1[13]),
    .I1(SFDecomp_162_645),
    .O(SFDecomp_163_646)
  );
  OR2   SFDecomp_164 (
    .I0(SFDecomp_161_644),
    .I1(SFDecomp_163_646),
    .O(SFDecomp_16)
  );
  AND2   SFDecomp_181 (
    .I0(DCOR1CNTLOWr),
    .I1(holdingreg1[5]),
    .O(SFDecomp_181_648)
  );
  INV   SFDecomp_182 (
    .I(DCOR1CNTLOWr),
    .O(SFDecomp_182_649)
  );
  AND2   SFDecomp_183 (
    .I0(SFDecomp_16),
    .I1(SFDecomp_182_649),
    .O(SFDecomp_183_650)
  );
  OR2   SFDecomp_184 (
    .I0(SFDecomp_181_648),
    .I1(SFDecomp_183_650),
    .O(SFDecomp_18)
  );
  AND2   SFDecomp_191 (
    .I0(DCOR0CNTHIGHr),
    .I1(holdingreg0[12]),
    .O(SFDecomp_191_652)
  );
  INV   SFDecomp_192 (
    .I(DCOR0CNTHIGHr),
    .O(SFDecomp_192_653)
  );
  AND2   SFDecomp_193 (
    .I0(holdingreg1[12]),
    .I1(SFDecomp_192_653),
    .O(SFDecomp_193_654)
  );
  OR2   SFDecomp_194 (
    .I0(SFDecomp_191_652),
    .I1(SFDecomp_193_654),
    .O(SFDecomp_19)
  );
  AND2   SFDecomp_211 (
    .I0(DCOR1CNTLOWr),
    .I1(holdingreg1[4]),
    .O(SFDecomp_211_656)
  );
  INV   SFDecomp_212 (
    .I(DCOR1CNTLOWr),
    .O(SFDecomp_212_657)
  );
  AND2   SFDecomp_213 (
    .I0(SFDecomp_19),
    .I1(SFDecomp_212_657),
    .O(SFDecomp_213_658)
  );
  OR2   SFDecomp_214 (
    .I0(SFDecomp_211_656),
    .I1(SFDecomp_213_658),
    .O(SFDecomp_21)
  );
  AND2   SFDecomp_221 (
    .I0(DCOR0CNTHIGHr),
    .I1(holdingreg0[9]),
    .O(SFDecomp_221_660)
  );
  INV   SFDecomp_222 (
    .I(DCOR0CNTHIGHr),
    .O(SFDecomp_222_661)
  );
  AND2   SFDecomp_223 (
    .I0(holdingreg1[9]),
    .I1(SFDecomp_222_661),
    .O(SFDecomp_223_662)
  );
  OR2   SFDecomp_224 (
    .I0(SFDecomp_221_660),
    .I1(SFDecomp_223_662),
    .O(SFDecomp_22)
  );
  AND2   SFDecomp_241 (
    .I0(DCOR1CNTLOWr),
    .I1(holdingreg1[1]),
    .O(SFDecomp_241_664)
  );
  INV   SFDecomp_242 (
    .I(DCOR1CNTLOWr),
    .O(SFDecomp_242_665)
  );
  AND2   SFDecomp_243 (
    .I0(SFDecomp_22),
    .I1(SFDecomp_242_665),
    .O(SFDecomp_243_666)
  );
  OR2   SFDecomp_244 (
    .I0(SFDecomp_241_664),
    .I1(SFDecomp_243_666),
    .O(SFDecomp_24)
  );
  AND2   SFDecomp_251 (
    .I0(DCOR0CNTHIGHr),
    .I1(holdingreg0[11]),
    .O(SFDecomp_251_668)
  );
  INV   SFDecomp_252 (
    .I(DCOR0CNTHIGHr),
    .O(SFDecomp_252_669)
  );
  AND2   SFDecomp_253 (
    .I0(holdingreg1[11]),
    .I1(SFDecomp_252_669),
    .O(SFDecomp_253_670)
  );
  OR2   SFDecomp_254 (
    .I0(SFDecomp_251_668),
    .I1(SFDecomp_253_670),
    .O(SFDecomp_25)
  );
  AND2   SFDecomp_271 (
    .I0(DCOR1CNTLOWr),
    .I1(holdingreg1[3]),
    .O(SFDecomp_271_672)
  );
  INV   SFDecomp_272 (
    .I(DCOR1CNTLOWr),
    .O(SFDecomp_272_673)
  );
  AND2   SFDecomp_273 (
    .I0(SFDecomp_25),
    .I1(SFDecomp_272_673),
    .O(SFDecomp_273_674)
  );
  OR2   SFDecomp_274 (
    .I0(SFDecomp_271_672),
    .I1(SFDecomp_273_674),
    .O(SFDecomp_27)
  );
  AND2   SFDecomp_281 (
    .I0(DCOR0CNTHIGHr),
    .I1(holdingreg0[10]),
    .O(SFDecomp_281_676)
  );
  INV   SFDecomp_282 (
    .I(DCOR0CNTHIGHr),
    .O(SFDecomp_282_677)
  );
  AND2   SFDecomp_283 (
    .I0(holdingreg1[10]),
    .I1(SFDecomp_282_677),
    .O(SFDecomp_283_678)
  );
  OR2   SFDecomp_284 (
    .I0(SFDecomp_281_676),
    .I1(SFDecomp_283_678),
    .O(SFDecomp_28)
  );
  AND2   SFDecomp_301 (
    .I0(DCOR1CNTLOWr),
    .I1(holdingreg1[2]),
    .O(SFDecomp_301_680)
  );
  INV   SFDecomp_302 (
    .I(DCOR1CNTLOWr),
    .O(SFDecomp_302_681)
  );
  AND2   SFDecomp_303 (
    .I0(SFDecomp_28),
    .I1(SFDecomp_302_681),
    .O(SFDecomp_303_682)
  );
  OR2   SFDecomp_304 (
    .I0(SFDecomp_301_680),
    .I1(SFDecomp_303_682),
    .O(SFDecomp_30)
  );
  AND2   SFDecomp_311 (
    .I0(DCOR0CNTHIGHr),
    .I1(holdingreg0[8]),
    .O(SFDecomp_311_684)
  );
  INV   SFDecomp_312 (
    .I(DCOR0CNTHIGHr),
    .O(SFDecomp_312_685)
  );
  AND2   SFDecomp_313 (
    .I0(holdingreg1[8]),
    .I1(SFDecomp_312_685),
    .O(SFDecomp_313_686)
  );
  OR2   SFDecomp_314 (
    .I0(SFDecomp_311_684),
    .I1(SFDecomp_313_686),
    .O(SFDecomp_31)
  );
  AND2   SFDecomp_331 (
    .I0(DCOR1CNTLOWr),
    .I1(holdingreg1[0]),
    .O(SFDecomp_331_688)
  );
  INV   SFDecomp_332 (
    .I(DCOR1CNTLOWr),
    .O(SFDecomp_332_689)
  );
  AND2   SFDecomp_333 (
    .I0(SFDecomp_31),
    .I1(SFDecomp_332_689),
    .O(SFDecomp_333_690)
  );
  OR2   SFDecomp_334 (
    .I0(SFDecomp_331_688),
    .I1(SFDecomp_333_690),
    .O(SFDecomp_33)
  );
endmodule

module Servos (
  DCOR0CNTLOWr, DCORENCCTLw, DCOR0THRESLOWr, PhaseB_Encoder0, PhaseB_Encoder1, DCOR0THRESHIGHr, DCOR1CNTHIGHr, Reset, DCOR0CNTHIGHr, DCOR1THRESHIGHr, 
PhaseA_Encoder0, PhaseA_Encoder1, DCORIFGr, Hfound0, Hfound1, DCORIFGw, MotorIn0, Motorin1, TP, Home_Encoder0, Home_Encoder1, DCOR1CNTLOWr, ASleading
, Mclk, DCOR1THRESLOWr, Tfound0, Tfound1, outDATA, inDATA
);
  input DCOR0CNTLOWr;
  input DCORENCCTLw;
  input DCOR0THRESLOWr;
  input PhaseB_Encoder0;
  input PhaseB_Encoder1;
  input DCOR0THRESHIGHr;
  input DCOR1CNTHIGHr;
  input Reset;
  input DCOR0CNTHIGHr;
  input DCOR1THRESHIGHr;
  input PhaseA_Encoder0;
  input PhaseA_Encoder1;
  input DCORIFGr;
  output Hfound0;
  output Hfound1;
  input DCORIFGw;
  input MotorIn0;
  input Motorin1;
  output TP;
  input Home_Encoder0;
  input Home_Encoder1;
  input DCOR1CNTLOWr;
  input ASleading;
  input Mclk;
  input DCOR1THRESLOWr;
  output Tfound0;
  output Tfound1;
  output [7 : 0] outDATA;
  input [7 : 0] inDATA;
  wire NET3720;
  wire NlwRenamedSig_OI_TP;
  wire Zero0;
  wire Zero1;
  wire ce0;
  wire ce1;
  wire updown0;
  wire updown1;
  wire [15 : 0] Channel0;
  wire [15 : 0] Channel1;
  assign
    TP = NlwRenamedSig_OI_TP;
  Holdreg   U3 (
    .DCOR0CNTLOWr(DCOR0CNTLOWr),
    .DCOR1CNTHIGHr(DCOR1CNTHIGHr),
    .Reset(Reset),
    .DCOR0CNTHIGHr(DCOR0CNTHIGHr),
    .Sclk(Mclk),
    .DCOR1CNTLOWr(DCOR1CNTLOWr),
    .ASleading(ASleading),
    .outDATA({outDATA[7], outDATA[6], outDATA[5], outDATA[4], outDATA[3], outDATA[2], outDATA[1], outDATA[0]}),
    .ch0in({Channel0[15], Channel0[14], Channel0[13], Channel0[12], Channel0[11], Channel0[10], Channel0[9], Channel0[8], Channel0[7], Channel0[6], 
Channel0[5], Channel0[4], Channel0[3], Channel0[2], Channel0[1], Channel0[0]}),
    .ch1in({Channel1[15], Channel1[14], Channel1[13], Channel1[12], Channel1[11], Channel1[10], Channel1[9], Channel1[8], Channel1[7], Channel1[6], 
Channel1[5], Channel1[4], Channel1[3], Channel1[2], Channel1[1], Channel1[0]})
  );
  HomeConfig   U4 (
    .Zero0(Zero0),
    .Zero1(Zero1),
    .DCORENCCTLw(DCORENCCTLw),
    .DCOR0THRESLOWr(DCOR0THRESLOWr),
    .DCOR0THRESHIGHr(DCOR0THRESHIGHr),
    .Reset(Reset),
    .DCOR1THRESHIGHr(DCOR1THRESHIGHr),
    .DCORIFGr(DCORIFGr),
    .Hfound0(Hfound0),
    .Hfound1(Hfound1),
    .DCORIFGw(DCORIFGw),
    .MotorIn0(MotorIn0),
    .MotorIn1(Motorin1),
    .Home_Encoder0(Home_Encoder0),
    .Home_Encoder1(Home_Encoder1),
    .sense0(NlwRenamedSig_OI_TP),
    .sense1(NET3720),
    .Sclk(Mclk),
    .DCOR1THRESLOWr(DCOR1THRESLOWr),
    .Tfound0(Tfound0),
    .Tfound1(Tfound1),
    .outDATA({outDATA[7], outDATA[6], outDATA[5], outDATA[4], outDATA[3], outDATA[2], outDATA[1], outDATA[0]}),
    .inDATA({inDATA[7], inDATA[6], inDATA[5], inDATA[4], inDATA[3], inDATA[2], inDATA[1], inDATA[0]}),
    .Channel0({Channel0[15], Channel0[14], Channel0[13], Channel0[12], Channel0[11], Channel0[10], Channel0[9], Channel0[8], Channel0[7], Channel0[6]
, Channel0[5], Channel0[4], Channel0[3], Channel0[2], Channel0[1], Channel0[0]}),
    .Channel1({Channel1[15], Channel1[14], Channel1[13], Channel1[12], Channel1[11], Channel1[10], Channel1[9], Channel1[8], Channel1[7], Channel1[6]
, Channel1[5], Channel1[4], Channel1[3], Channel1[2], Channel1[1], Channel1[0]})
  );
  Counter   U5 (
    .sense(NET3720),
    .ce(ce1),
    .Reset(Reset),
    .updown(updown1),
    .Zero(Zero1),
    .Sclk(Mclk),
    .count({Channel1[15], Channel1[14], Channel1[13], Channel1[12], Channel1[11], Channel1[10], Channel1[9], Channel1[8], Channel1[7], Channel1[6], 
Channel1[5], Channel1[4], Channel1[3], Channel1[2], Channel1[1], Channel1[0]})
  );
  Counter_INST_1   U2 (
    .sense(NlwRenamedSig_OI_TP),
    .ce(ce0),
    .Reset(Reset),
    .updown(updown0),
    .Zero(Zero0),
    .Sclk(Mclk),
    .count({Channel0[15], Channel0[14], Channel0[13], Channel0[12], Channel0[11], Channel0[10], Channel0[9], Channel0[8], Channel0[7], Channel0[6], 
Channel0[5], Channel0[4], Channel0[3], Channel0[2], Channel0[1], Channel0[0]})
  );
  Decode   U6 (
    .ce(ce1),
    .Reset(Reset),
    .updown(updown1),
    .phaseA(PhaseA_Encoder1),
    .phaseB(PhaseB_Encoder1),
    .Sclk(Mclk)
  );
  Decode_INST_1   U1 (
    .ce(ce0),
    .Reset(Reset),
    .updown(updown0),
    .phaseA(PhaseA_Encoder0),
    .phaseB(PhaseB_Encoder0),
    .Sclk(Mclk)
  );
endmodule

module MISCouts (
  LightSense, MTRpwrn, LED1, LED2, LED3, LED4, LED5, Reset, GP_Motor0_1, GP_Motor1_1, DCOROUTw, Mclk, MTRpwr, MReset, inDATA
);
  input LightSense;
  output MTRpwrn;
  output LED1;
  output LED2;
  output LED3;
  output LED4;
  output LED5;
  input Reset;
  output GP_Motor0_1;
  output GP_Motor1_1;
  input DCOROUTw;
  input Mclk;
  output MTRpwr;
  input MReset;
  input [7 : 0] inDATA;
  wire LED11_574;
  wire LED21_576;
  wire LED31_578;
  wire LED41_580;
  wire LED51_582;
  wire MISCr_0_N0;
  wire \MISCr_mux0000<0>1_591 ;
  wire \MISCr_mux0000<1>1_593 ;
  wire \MISCr_mux0000<2>1_595 ;
  wire \MISCr_mux0000<3>1_597 ;
  wire \MISCr_mux0000<4>1_599 ;
  wire \MISCr_mux0000<5>1_601 ;
  wire \MISCr_mux0000<6>1_603 ;
  wire \MISCr_mux0000<7>1_605 ;
  wire MISCr_not0001;
  wire NlwRenamedSig_OI_MTRpwr;
  wire [4 : 0] MISCr;
  wire [7 : 0] MISCr_mux0000;
  assign
    MTRpwr = NlwRenamedSig_OI_MTRpwr;
  FDCE   MISCr_0 (
    .CE(MISCr_not0001),
    .CLR(MReset),
    .C(MISCr_0_N0),
    .D(MISCr_mux0000[7]),
    .Q(MISCr[0])
  );
  FDCE   MISCr_1 (
    .CE(MISCr_not0001),
    .CLR(MReset),
    .C(MISCr_0_N0),
    .D(MISCr_mux0000[6]),
    .Q(MISCr[1])
  );
  FDCE   MISCr_2 (
    .CE(MISCr_not0001),
    .CLR(MReset),
    .C(MISCr_0_N0),
    .D(MISCr_mux0000[5]),
    .Q(MISCr[2])
  );
  FDCE   MISCr_3 (
    .CE(MISCr_not0001),
    .CLR(MReset),
    .C(MISCr_0_N0),
    .D(MISCr_mux0000[4]),
    .Q(MISCr[3])
  );
  FDCE   MISCr_4 (
    .CE(MISCr_not0001),
    .CLR(MReset),
    .C(MISCr_0_N0),
    .D(MISCr_mux0000[3]),
    .Q(MISCr[4])
  );
  FDCE   MISCr_5 (
    .CE(MISCr_not0001),
    .CLR(MReset),
    .C(MISCr_0_N0),
    .D(MISCr_mux0000[2]),
    .Q(NlwRenamedSig_OI_MTRpwr)
  );
  FDCE   MISCr_6 (
    .CE(MISCr_not0001),
    .CLR(MReset),
    .C(MISCr_0_N0),
    .D(MISCr_mux0000[1]),
    .Q(GP_Motor0_1)
  );
  FDCE   MISCr_7 (
    .CE(MISCr_not0001),
    .CLR(MReset),
    .C(MISCr_0_N0),
    .D(MISCr_mux0000[0]),
    .Q(GP_Motor1_1)
  );
  INV   LED11 (
    .I(LightSense),
    .O(LED11_574)
  );
  OR2   LED12 (
    .I0(MISCr[0]),
    .I1(LED11_574),
    .O(LED1)
  );
  INV   LED21 (
    .I(LightSense),
    .O(LED21_576)
  );
  OR2   LED22 (
    .I0(MISCr[1]),
    .I1(LED21_576),
    .O(LED2)
  );
  INV   LED31 (
    .I(LightSense),
    .O(LED31_578)
  );
  OR2   LED32 (
    .I0(MISCr[2]),
    .I1(LED31_578),
    .O(LED3)
  );
  INV   LED41 (
    .I(LightSense),
    .O(LED41_580)
  );
  OR2   LED42 (
    .I0(MISCr[3]),
    .I1(LED41_580),
    .O(LED4)
  );
  INV   LED51 (
    .I(LightSense),
    .O(LED51_582)
  );
  OR2   LED52 (
    .I0(MISCr[4]),
    .I1(LED51_582),
    .O(LED5)
  );
  INV   MTRpwrn1 (
    .I(NlwRenamedSig_OI_MTRpwr),
    .O(MTRpwrn)
  );
  INV   \MISCr_mux0000<0>1  (
    .I(Reset),
    .O(\MISCr_mux0000<0>1_591 )
  );
  AND2   \MISCr_mux0000<0>2  (
    .I0(inDATA[7]),
    .I1(\MISCr_mux0000<0>1_591 ),
    .O(MISCr_mux0000[0])
  );
  INV   \MISCr_mux0000<1>1  (
    .I(Reset),
    .O(\MISCr_mux0000<1>1_593 )
  );
  AND2   \MISCr_mux0000<1>2  (
    .I0(inDATA[6]),
    .I1(\MISCr_mux0000<1>1_593 ),
    .O(MISCr_mux0000[1])
  );
  INV   \MISCr_mux0000<2>1  (
    .I(Reset),
    .O(\MISCr_mux0000<2>1_595 )
  );
  AND2   \MISCr_mux0000<2>2  (
    .I0(inDATA[5]),
    .I1(\MISCr_mux0000<2>1_595 ),
    .O(MISCr_mux0000[2])
  );
  INV   \MISCr_mux0000<3>1  (
    .I(Reset),
    .O(\MISCr_mux0000<3>1_597 )
  );
  AND2   \MISCr_mux0000<3>2  (
    .I0(inDATA[4]),
    .I1(\MISCr_mux0000<3>1_597 ),
    .O(MISCr_mux0000[3])
  );
  INV   \MISCr_mux0000<4>1  (
    .I(Reset),
    .O(\MISCr_mux0000<4>1_599 )
  );
  AND2   \MISCr_mux0000<4>2  (
    .I0(inDATA[3]),
    .I1(\MISCr_mux0000<4>1_599 ),
    .O(MISCr_mux0000[4])
  );
  INV   \MISCr_mux0000<5>1  (
    .I(Reset),
    .O(\MISCr_mux0000<5>1_601 )
  );
  AND2   \MISCr_mux0000<5>2  (
    .I0(inDATA[2]),
    .I1(\MISCr_mux0000<5>1_601 ),
    .O(MISCr_mux0000[5])
  );
  INV   \MISCr_mux0000<6>1  (
    .I(Reset),
    .O(\MISCr_mux0000<6>1_603 )
  );
  AND2   \MISCr_mux0000<6>2  (
    .I0(inDATA[1]),
    .I1(\MISCr_mux0000<6>1_603 ),
    .O(MISCr_mux0000[6])
  );
  INV   \MISCr_mux0000<7>1  (
    .I(Reset),
    .O(\MISCr_mux0000<7>1_605 )
  );
  AND2   \MISCr_mux0000<7>2  (
    .I0(inDATA[0]),
    .I1(\MISCr_mux0000<7>1_605 ),
    .O(MISCr_mux0000[7])
  );
  INV   MISCr_0_N01 (
    .I(Mclk),
    .O(MISCr_0_N0)
  );
  OR2   MISCr_not000111 (
    .I0(Reset),
    .I1(DCOROUTw),
    .O(MISCr_not0001)
  );
endmodule

module Sensor (
  TmpSlct, Reset, DCORSENSORw, TmpEn, PresEn, PresSlct, Mclk, MReset, inDATA
);
  output TmpSlct;
  input Reset;
  input DCORSENSORw;
  output TmpEn;
  output PresEn;
  output PresSlct;
  input Mclk;
  input MReset;
  input [3 : 0] inDATA;
  wire \sensorr[0] ;
  wire sensorr_0_N0;
  wire \sensorr[2] ;
  wire \sensorr_mux0000<0>1_562 ;
  wire \sensorr_mux0000<1>1_564 ;
  wire \sensorr_mux0000<2>1_566 ;
  wire \sensorr_mux0000<3>1_568 ;
  wire sensorr_not0001;
  wire [3 : 0] sensorr_mux0000;
  FDCE   sensorr_0 (
    .CE(sensorr_not0001),
    .CLR(MReset),
    .C(sensorr_0_N0),
    .D(sensorr_mux0000[3]),
    .Q(\sensorr[0] )
  );
  FDCE   sensorr_1 (
    .CE(sensorr_not0001),
    .CLR(MReset),
    .C(sensorr_0_N0),
    .D(sensorr_mux0000[2]),
    .Q(PresSlct)
  );
  FDCE   sensorr_2 (
    .CE(sensorr_not0001),
    .CLR(MReset),
    .C(sensorr_0_N0),
    .D(sensorr_mux0000[1]),
    .Q(\sensorr[2] )
  );
  FDCE   sensorr_3 (
    .CE(sensorr_not0001),
    .CLR(MReset),
    .C(sensorr_0_N0),
    .D(sensorr_mux0000[0]),
    .Q(TmpSlct)
  );
  INV   PresEn1 (
    .I(\sensorr[0] ),
    .O(PresEn)
  );
  INV   TmpEn1 (
    .I(\sensorr[2] ),
    .O(TmpEn)
  );
  INV   \sensorr_mux0000<0>1  (
    .I(Reset),
    .O(\sensorr_mux0000<0>1_562 )
  );
  AND2   \sensorr_mux0000<0>2  (
    .I0(inDATA[3]),
    .I1(\sensorr_mux0000<0>1_562 ),
    .O(sensorr_mux0000[0])
  );
  INV   \sensorr_mux0000<1>1  (
    .I(Reset),
    .O(\sensorr_mux0000<1>1_564 )
  );
  AND2   \sensorr_mux0000<1>2  (
    .I0(inDATA[2]),
    .I1(\sensorr_mux0000<1>1_564 ),
    .O(sensorr_mux0000[1])
  );
  INV   \sensorr_mux0000<2>1  (
    .I(Reset),
    .O(\sensorr_mux0000<2>1_566 )
  );
  AND2   \sensorr_mux0000<2>2  (
    .I0(inDATA[1]),
    .I1(\sensorr_mux0000<2>1_566 ),
    .O(sensorr_mux0000[2])
  );
  INV   \sensorr_mux0000<3>1  (
    .I(Reset),
    .O(\sensorr_mux0000<3>1_568 )
  );
  AND2   \sensorr_mux0000<3>2  (
    .I0(inDATA[0]),
    .I1(\sensorr_mux0000<3>1_568 ),
    .O(sensorr_mux0000[3])
  );
  INV   sensorr_0_N01 (
    .I(Mclk),
    .O(sensorr_0_N0)
  );
  OR2   sensorr_not000111 (
    .I0(Reset),
    .I1(DCORSENSORw),
    .O(sensorr_not0001)
  );
endmodule

module PWRreg (
  DCORENCPWRr, DCORENCPWRw, PWRint, Hme05ctl, Enc033ctl, Hme033ctl, Reset, Hme05flg, Enc05ctl, Enc033flg, Hme033flg, Hme15ctl, Enc133ctl, Hme133ctl, 
DCORIFGr, DCORIFGw, Enc05flg, Hme15flg, Enc133flg, Hme133flg, Enc15ctl, Enc15flg, Mclk, outDATA, inDATA
);
  input DCORENCPWRr;
  input DCORENCPWRw;
  output PWRint;
  output Hme05ctl;
  output Enc033ctl;
  output Hme033ctl;
  input Reset;
  input Hme05flg;
  output Enc05ctl;
  input Enc033flg;
  input Hme033flg;
  output Hme15ctl;
  output Enc133ctl;
  output Hme133ctl;
  input DCORIFGr;
  input DCORIFGw;
  input Enc05flg;
  input Hme15flg;
  input Enc133flg;
  input Hme133flg;
  output Enc15ctl;
  input Enc15flg;
  input Mclk;
  output [7 : 0] outDATA;
  input [7 : 0] inDATA;
  wire DCORIFG_0_not0000;
  wire DCORIFG__and0000;
  wire DCORIFG__and00001;
  wire DCORIFG__and000011_457;
  wire DCORIFG__and000012_458;
  wire DCORIFG__and000013_459;
  wire DCORIFG__and000014_460;
  wire DCORIFG__or0000;
  wire DCORIFG__or00002;
  wire DCORIFG__or000021_463;
  wire DCORIFG__or000022_464;
  wire DCORIFG__or000023_465;
  wire DCORIFG__or0000_bdd0;
  wire DCORIFG__or0000_bdd2;
  wire NlwRenamedSig_OI_Enc133ctl;
  wire \Flgreg[0] ;
  wire \Flgreg[1] ;
  wire \Flgreg[2] ;
  wire \Flgreg[3] ;
  wire \Flgreg[4] ;
  wire \Flgreg[5] ;
  wire \Flgreg[7] ;
  wire Flgreg_and0000;
  wire Flgreg_and00001;
  wire N1;
  wire NlwRenamedSig_OI_PWRint;
  wire \ctrlr[0] ;
  wire \ctrlr[1] ;
  wire \ctrlr[3] ;
  wire \ctrlr[4] ;
  wire \ctrlr[5] ;
  wire \ctrlr[7] ;
  wire \outDATA<1>_not0000 ;
  wire outDATA_0_mux0000;
  wire outDATA_0_mux00001_518;
  wire outDATA_0_mux00002_519;
  wire outDATA_0_mux00003_520;
  wire outDATA_1_mux0000;
  wire outDATA_1_mux00001_522;
  wire outDATA_1_mux00002_523;
  wire outDATA_1_mux00003_524;
  wire outDATA_1_mux00004_525;
  wire outDATA_1_mux00005_526;
  wire outDATA_1_mux00006_527;
  wire outDATA_2_mux0000;
  wire outDATA_2_mux00001_529;
  wire outDATA_3_mux0000;
  wire outDATA_3_mux00001_531;
  wire outDATA_3_mux00002_532;
  wire outDATA_3_mux00003_533;
  wire outDATA_4_mux0000;
  wire outDATA_4_mux00001_535;
  wire outDATA_4_mux00002_536;
  wire outDATA_4_mux00003_537;
  wire outDATA_5_mux0000;
  wire outDATA_5_mux00001_539;
  wire outDATA_5_mux00002_540;
  wire outDATA_5_mux00003_541;
  wire outDATA_7_mux0000;
  wire outDATA_7_mux00001_543;
  wire outDATA_7_mux00002_544;
  wire outDATA_7_mux00003_545;
  assign
    PWRint = NlwRenamedSig_OI_PWRint,
    Enc033ctl = NlwRenamedSig_OI_Enc133ctl,
    Enc133ctl = NlwRenamedSig_OI_Enc133ctl;
  GND   XST_GND (
    .G(NlwRenamedSig_OI_Enc133ctl)
  );
  VCC   XST_VCC (
    .P(N1)
  );
  BUFE   \outDATA<0>_0  (
    .I(outDATA_0_mux0000),
    .E(DCORENCPWRr),
    .O(outDATA[0])
  );
  BUFE   \outDATA<1>_0  (
    .I(outDATA_1_mux0000),
    .E(\outDATA<1>_not0000 ),
    .O(outDATA[1])
  );
  BUFE   \outDATA<2>_0  (
    .I(outDATA_2_mux0000),
    .E(DCORENCPWRr),
    .O(outDATA[2])
  );
  BUFE   \outDATA<3>_0  (
    .I(outDATA_3_mux0000),
    .E(DCORENCPWRr),
    .O(outDATA[3])
  );
  BUFE   \outDATA<4>_0  (
    .I(outDATA_4_mux0000),
    .E(DCORENCPWRr),
    .O(outDATA[4])
  );
  BUFE   \outDATA<5>_0  (
    .I(outDATA_5_mux0000),
    .E(DCORENCPWRr),
    .O(outDATA[5])
  );
  BUFE   \outDATA<6>_0  (
    .I(outDATA_2_mux0000),
    .E(DCORENCPWRr),
    .O(outDATA[6])
  );
  BUFE   \outDATA<7>_0  (
    .I(outDATA_7_mux0000),
    .E(DCORENCPWRr),
    .O(outDATA[7])
  );
  FDCE   DCORIFG (
    .CE(DCORIFG__or0000),
    .CLR(NlwRenamedSig_OI_Enc133ctl),
    .C(DCORIFG_0_not0000),
    .D(DCORIFG__and0000),
    .Q(NlwRenamedSig_OI_PWRint)
  );
  FDCE   ctrlr_0 (
    .CE(DCORENCPWRw),
    .CLR(Reset),
    .C(DCORIFG_0_not0000),
    .D(inDATA[0]),
    .Q(\ctrlr[0] )
  );
  FDCE   ctrlr_1 (
    .CE(DCORENCPWRw),
    .CLR(Reset),
    .C(DCORIFG_0_not0000),
    .D(inDATA[1]),
    .Q(\ctrlr[1] )
  );
  FDCE   ctrlr_3 (
    .CE(DCORENCPWRw),
    .CLR(Reset),
    .C(DCORIFG_0_not0000),
    .D(inDATA[3]),
    .Q(\ctrlr[3] )
  );
  FDCE   ctrlr_4 (
    .CE(DCORENCPWRw),
    .CLR(Reset),
    .C(DCORIFG_0_not0000),
    .D(inDATA[4]),
    .Q(\ctrlr[4] )
  );
  FDCE   ctrlr_5 (
    .CE(DCORENCPWRw),
    .CLR(Reset),
    .C(DCORIFG_0_not0000),
    .D(inDATA[5]),
    .Q(\ctrlr[5] )
  );
  FDCE   ctrlr_7 (
    .CE(DCORENCPWRw),
    .CLR(Reset),
    .C(DCORIFG_0_not0000),
    .D(inDATA[7]),
    .Q(\ctrlr[7] )
  );
  FDCE   Flgreg_0 (
    .CE(Flgreg_and0000),
    .CLR(NlwRenamedSig_OI_Enc133ctl),
    .C(DCORIFG_0_not0000),
    .D(Hme033flg),
    .Q(\Flgreg[0] )
  );
  FDCE   Flgreg_1 (
    .CE(Flgreg_and0000),
    .CLR(NlwRenamedSig_OI_Enc133ctl),
    .C(DCORIFG_0_not0000),
    .D(Hme05flg),
    .Q(\Flgreg[1] )
  );
  FDCE   Flgreg_2 (
    .CE(Flgreg_and0000),
    .CLR(NlwRenamedSig_OI_Enc133ctl),
    .C(DCORIFG_0_not0000),
    .D(N1),
    .Q(\Flgreg[2] )
  );
  FDCE   Flgreg_3 (
    .CE(Flgreg_and0000),
    .CLR(NlwRenamedSig_OI_Enc133ctl),
    .C(DCORIFG_0_not0000),
    .D(Enc05flg),
    .Q(\Flgreg[3] )
  );
  FDCE   Flgreg_4 (
    .CE(Flgreg_and0000),
    .CLR(NlwRenamedSig_OI_Enc133ctl),
    .C(DCORIFG_0_not0000),
    .D(Hme133flg),
    .Q(\Flgreg[4] )
  );
  FDCE   Flgreg_5 (
    .CE(Flgreg_and0000),
    .CLR(NlwRenamedSig_OI_Enc133ctl),
    .C(DCORIFG_0_not0000),
    .D(Hme15flg),
    .Q(\Flgreg[5] )
  );
  FDCE   Flgreg_7 (
    .CE(Flgreg_and0000),
    .CLR(NlwRenamedSig_OI_Enc133ctl),
    .C(DCORIFG_0_not0000),
    .D(Enc15flg),
    .Q(\Flgreg[7] )
  );
  INV   Enc15ctl1 (
    .I(\ctrlr[7] ),
    .O(Enc15ctl)
  );
  INV   Hme15ctl1 (
    .I(\ctrlr[5] ),
    .O(Hme15ctl)
  );
  INV   Hme133ctl1 (
    .I(\ctrlr[4] ),
    .O(Hme133ctl)
  );
  INV   Enc05ctl1 (
    .I(\ctrlr[3] ),
    .O(Enc05ctl)
  );
  INV   Hme05ctl1 (
    .I(\ctrlr[1] ),
    .O(Hme05ctl)
  );
  INV   Hme033ctl1 (
    .I(\ctrlr[0] ),
    .O(Hme033ctl)
  );
  AND2   outDATA_7_mux00001 (
    .I0(NlwRenamedSig_OI_PWRint),
    .I1(\Flgreg[7] ),
    .O(outDATA_7_mux00001_543)
  );
  INV   outDATA_7_mux00002 (
    .I(NlwRenamedSig_OI_PWRint),
    .O(outDATA_7_mux00002_544)
  );
  AND2   outDATA_7_mux00003 (
    .I0(Enc15flg),
    .I1(outDATA_7_mux00002_544),
    .O(outDATA_7_mux00003_545)
  );
  OR2   outDATA_7_mux00004 (
    .I0(outDATA_7_mux00001_543),
    .I1(outDATA_7_mux00003_545),
    .O(outDATA_7_mux0000)
  );
  AND2   outDATA_5_mux00001 (
    .I0(NlwRenamedSig_OI_PWRint),
    .I1(\Flgreg[5] ),
    .O(outDATA_5_mux00001_539)
  );
  INV   outDATA_5_mux00002 (
    .I(NlwRenamedSig_OI_PWRint),
    .O(outDATA_5_mux00002_540)
  );
  AND2   outDATA_5_mux00003 (
    .I0(Hme15flg),
    .I1(outDATA_5_mux00002_540),
    .O(outDATA_5_mux00003_541)
  );
  OR2   outDATA_5_mux00004 (
    .I0(outDATA_5_mux00001_539),
    .I1(outDATA_5_mux00003_541),
    .O(outDATA_5_mux0000)
  );
  AND2   outDATA_4_mux00001 (
    .I0(NlwRenamedSig_OI_PWRint),
    .I1(\Flgreg[4] ),
    .O(outDATA_4_mux00001_535)
  );
  INV   outDATA_4_mux00002 (
    .I(NlwRenamedSig_OI_PWRint),
    .O(outDATA_4_mux00002_536)
  );
  AND2   outDATA_4_mux00003 (
    .I0(Hme133flg),
    .I1(outDATA_4_mux00002_536),
    .O(outDATA_4_mux00003_537)
  );
  OR2   outDATA_4_mux00004 (
    .I0(outDATA_4_mux00001_535),
    .I1(outDATA_4_mux00003_537),
    .O(outDATA_4_mux0000)
  );
  AND2   outDATA_3_mux00001 (
    .I0(NlwRenamedSig_OI_PWRint),
    .I1(\Flgreg[3] ),
    .O(outDATA_3_mux00001_531)
  );
  INV   outDATA_3_mux00002 (
    .I(NlwRenamedSig_OI_PWRint),
    .O(outDATA_3_mux00002_532)
  );
  AND2   outDATA_3_mux00003 (
    .I0(Enc05flg),
    .I1(outDATA_3_mux00002_532),
    .O(outDATA_3_mux00003_533)
  );
  OR2   outDATA_3_mux00004 (
    .I0(outDATA_3_mux00001_531),
    .I1(outDATA_3_mux00003_533),
    .O(outDATA_3_mux0000)
  );
  INV   outDATA_2_mux00001 (
    .I(NlwRenamedSig_OI_PWRint),
    .O(outDATA_2_mux00001_529)
  );
  OR2   outDATA_2_mux00002 (
    .I0(\Flgreg[2] ),
    .I1(outDATA_2_mux00001_529),
    .O(outDATA_2_mux0000)
  );
  AND2   outDATA_1_mux00001 (
    .I0(NlwRenamedSig_OI_PWRint),
    .I1(\Flgreg[1] ),
    .O(outDATA_1_mux00001_522)
  );
  INV   outDATA_1_mux00002 (
    .I(DCORENCPWRr),
    .O(outDATA_1_mux00002_523)
  );
  AND2   outDATA_1_mux00003 (
    .I0(Hme05flg),
    .I1(DCORENCPWRr),
    .O(outDATA_1_mux00003_524)
  );
  INV   outDATA_1_mux00004 (
    .I(NlwRenamedSig_OI_PWRint),
    .O(outDATA_1_mux00004_525)
  );
  AND2   outDATA_1_mux00005 (
    .I0(NlwRenamedSig_OI_PWRint),
    .I1(outDATA_1_mux00002_523),
    .O(outDATA_1_mux00005_526)
  );
  AND2   outDATA_1_mux00006 (
    .I0(outDATA_1_mux00003_524),
    .I1(outDATA_1_mux00004_525),
    .O(outDATA_1_mux00006_527)
  );
  OR3   outDATA_1_mux00007 (
    .I0(outDATA_1_mux00005_526),
    .I1(outDATA_1_mux00001_522),
    .I2(outDATA_1_mux00006_527),
    .O(outDATA_1_mux0000)
  );
  AND2   outDATA_0_mux00001 (
    .I0(NlwRenamedSig_OI_PWRint),
    .I1(\Flgreg[0] ),
    .O(outDATA_0_mux00001_518)
  );
  INV   outDATA_0_mux00002 (
    .I(NlwRenamedSig_OI_PWRint),
    .O(outDATA_0_mux00002_519)
  );
  AND2   outDATA_0_mux00003 (
    .I0(Hme033flg),
    .I1(outDATA_0_mux00002_519),
    .O(outDATA_0_mux00003_520)
  );
  OR2   outDATA_0_mux00004 (
    .I0(outDATA_0_mux00001_518),
    .I1(outDATA_0_mux00003_520),
    .O(outDATA_0_mux0000)
  );
  INV   DCORIFG_0_not00001 (
    .I(Mclk),
    .O(DCORIFG_0_not0000)
  );
  INV   Flgreg_and000011 (
    .I(NlwRenamedSig_OI_PWRint),
    .O(Flgreg_and00001)
  );
  AND2   Flgreg_and000012 (
    .I0(DCORIFG__or0000_bdd0),
    .I1(Flgreg_and00001),
    .O(Flgreg_and0000)
  );
  AND3   DCORIFG__or000031 (
    .I0(Hme133flg),
    .I1(Enc15flg),
    .I2(Hme15flg),
    .O(DCORIFG__or0000_bdd2)
  );
  INV   DCORIFG__or000021 (
    .I(Hme033flg),
    .O(DCORIFG__or00002)
  );
  INV   DCORIFG__or000022 (
    .I(Enc05flg),
    .O(DCORIFG__or000021_463)
  );
  INV   DCORIFG__or000023 (
    .I(Hme05flg),
    .O(DCORIFG__or000022_464)
  );
  INV   DCORIFG__or000024 (
    .I(DCORIFG__or0000_bdd2),
    .O(DCORIFG__or000023_465)
  );
  OR4   DCORIFG__or000025 (
    .I0(DCORIFG__or00002),
    .I1(DCORIFG__or000021_463),
    .I2(DCORIFG__or000022_464),
    .I3(DCORIFG__or000023_465),
    .O(DCORIFG__or0000_bdd0)
  );
  OR3   DCORIFG__or000011 (
    .I0(Reset),
    .I1(DCORIFGw),
    .I2(DCORIFG__or0000_bdd0),
    .O(DCORIFG__or0000)
  );
  INV   DCORIFG__and000011 (
    .I(inDATA[1]),
    .O(DCORIFG__and00001)
  );
  INV   DCORIFG__and000012 (
    .I(DCORIFGw),
    .O(DCORIFG__and000011_457)
  );
  INV   DCORIFG__and000013 (
    .I(Reset),
    .O(DCORIFG__and000012_458)
  );
  AND2   DCORIFG__and000014 (
    .I0(NlwRenamedSig_OI_PWRint),
    .I1(DCORIFG__and00001),
    .O(DCORIFG__and000013_459)
  );
  OR2   DCORIFG__and000015 (
    .I0(DCORIFG__and000013_459),
    .I1(DCORIFG__and000011_457),
    .O(DCORIFG__and000014_460)
  );
  AND2   DCORIFG__and000016 (
    .I0(DCORIFG__and000014_460),
    .I1(DCORIFG__and000012_458),
    .O(DCORIFG__and0000)
  );
  OR2   \outDATA<1>_not000011  (
    .I0(DCORIFGr),
    .I1(DCORENCPWRr),
    .O(\outDATA<1>_not0000 )
  );
endmodule

module Interrupt (
  PWRint, Reset, I2Cint, DCORIFGr, Homed0, Homed1, BusInt, TP, DCORIEw, Thres0, Thres1, LSwitchInt, Mclk, INT, outDATA, inDATA
);
  input PWRint;
  input Reset;
  input I2Cint;
  input DCORIFGr;
  input Homed0;
  input Homed1;
  input BusInt;
  output TP;
  input DCORIEw;
  input Thres0;
  input Thres1;
  input LSwitchInt;
  input Mclk;
  output INT;
  output [7 : 0] outDATA;
  input [7 : 0] inDATA;
  wire \DCORIE[0] ;
  wire DCORIE_0_0_not0000;
  wire DCORIE_0__and0000;
  wire DCORIE_0__and00001_385;
  wire DCORIE_0__or0000;
  wire \DCORIE[1] ;
  wire DCORIE_1__and0000;
  wire DCORIE_1__and00001_389;
  wire \DCORIE[2] ;
  wire DCORIE_2__and0000;
  wire DCORIE_2__and00001_392;
  wire \DCORIE[3] ;
  wire DCORIE_3__and0000;
  wire DCORIE_3__and00001_395;
  wire \DCORIE[4] ;
  wire DCORIE_4__and0000;
  wire DCORIE_4__and00001_398;
  wire DCORIE_5__and0000;
  wire DCORIE_5__and00001_400;
  wire \DCORIE[6] ;
  wire DCORIE_6__and0000;
  wire DCORIE_6__and00001_403;
  wire \DCORIE[7] ;
  wire DCORIE_7__and0000;
  wire DCORIE_7__and00001_406;
  wire INT1_413;
  wire INT2_414;
  wire N0;
  wire SFDecomp_1;
  wire SFDecomp_11_421;
  wire SFDecomp_2;
  wire SFDecomp_21_423;
  wire SFDecomp_22_424;
  wire SFDecomp_5;
  wire SFDecomp_6;
  wire SFDecomp_61_427;
  wire SFDecomp_7;
  wire SFDecomp_8;
  wire SFDecomp_81_430;
  wire SFDecomp_9;
  wire SFDecomp_91_432;
  wire NlwRenamedSig_OI_TP;
  assign
    TP = NlwRenamedSig_OI_TP;
  GND   XST_GND (
    .G(N0)
  );
  BUFE   \outDATA<0>_BusInt_0  (
    .I(BusInt),
    .E(DCORIFGr),
    .O(outDATA[0])
  );
  BUFE   \outDATA<1>_0  (
    .I(N0),
    .E(N0),
    .O(outDATA[1])
  );
  BUFE   \outDATA<2>_0  (
    .I(N0),
    .E(N0),
    .O(outDATA[2])
  );
  BUFE   \outDATA<3>_0  (
    .I(N0),
    .E(N0),
    .O(outDATA[3])
  );
  BUFE   \outDATA<4>_LSwitchInt_0  (
    .I(LSwitchInt),
    .E(DCORIFGr),
    .O(outDATA[4])
  );
  BUFE   \outDATA<5>_0  (
    .I(N0),
    .E(N0),
    .O(outDATA[5])
  );
  BUFE   \outDATA<6>_0  (
    .I(N0),
    .E(N0),
    .O(outDATA[6])
  );
  BUFE   \outDATA<7>_I2Cint_0  (
    .I(I2Cint),
    .E(DCORIFGr),
    .O(outDATA[7])
  );
  FDCE   DCORIE_0 (
    .CE(DCORIE_0__or0000),
    .CLR(N0),
    .C(DCORIE_0_0_not0000),
    .D(DCORIE_0__and0000),
    .Q(\DCORIE[0] )
  );
  FDCE   DCORIE_1 (
    .CE(DCORIE_0__or0000),
    .CLR(N0),
    .C(DCORIE_0_0_not0000),
    .D(DCORIE_1__and0000),
    .Q(\DCORIE[1] )
  );
  FDCE   DCORIE_2 (
    .CE(DCORIE_0__or0000),
    .CLR(N0),
    .C(DCORIE_0_0_not0000),
    .D(DCORIE_2__and0000),
    .Q(\DCORIE[2] )
  );
  FDCE   DCORIE_3 (
    .CE(DCORIE_0__or0000),
    .CLR(N0),
    .C(DCORIE_0_0_not0000),
    .D(DCORIE_3__and0000),
    .Q(\DCORIE[3] )
  );
  FDCE   DCORIE_4 (
    .CE(DCORIE_0__or0000),
    .CLR(N0),
    .C(DCORIE_0_0_not0000),
    .D(DCORIE_4__and0000),
    .Q(\DCORIE[4] )
  );
  FDCE   DCORIE_5 (
    .CE(DCORIE_0__or0000),
    .CLR(N0),
    .C(DCORIE_0_0_not0000),
    .D(DCORIE_5__and0000),
    .Q(NlwRenamedSig_OI_TP)
  );
  FDCE   DCORIE_6 (
    .CE(DCORIE_0__or0000),
    .CLR(N0),
    .C(DCORIE_0_0_not0000),
    .D(DCORIE_6__and0000),
    .Q(\DCORIE[6] )
  );
  FDCE   DCORIE_7 (
    .CE(DCORIE_0__or0000),
    .CLR(N0),
    .C(DCORIE_0_0_not0000),
    .D(DCORIE_7__and0000),
    .Q(\DCORIE[7] )
  );
  INV   DCORIE_0__and00001 (
    .I(Reset),
    .O(DCORIE_0__and00001_385)
  );
  AND2   DCORIE_0__and00002 (
    .I0(inDATA[0]),
    .I1(DCORIE_0__and00001_385),
    .O(DCORIE_0__and0000)
  );
  OR2   DCORIE_0__or00001 (
    .I0(DCORIEw),
    .I1(Reset),
    .O(DCORIE_0__or0000)
  );
  INV   DCORIE_0_0_not00001 (
    .I(Mclk),
    .O(DCORIE_0_0_not0000)
  );
  INV   DCORIE_1__and00001 (
    .I(Reset),
    .O(DCORIE_1__and00001_389)
  );
  AND2   DCORIE_1__and00002 (
    .I0(inDATA[1]),
    .I1(DCORIE_1__and00001_389),
    .O(DCORIE_1__and0000)
  );
  INV   DCORIE_2__and00001 (
    .I(Reset),
    .O(DCORIE_2__and00001_392)
  );
  AND2   DCORIE_2__and00002 (
    .I0(inDATA[2]),
    .I1(DCORIE_2__and00001_392),
    .O(DCORIE_2__and0000)
  );
  INV   DCORIE_3__and00001 (
    .I(Reset),
    .O(DCORIE_3__and00001_395)
  );
  AND2   DCORIE_3__and00002 (
    .I0(inDATA[3]),
    .I1(DCORIE_3__and00001_395),
    .O(DCORIE_3__and0000)
  );
  INV   DCORIE_4__and00001 (
    .I(Reset),
    .O(DCORIE_4__and00001_398)
  );
  AND2   DCORIE_4__and00002 (
    .I0(inDATA[4]),
    .I1(DCORIE_4__and00001_398),
    .O(DCORIE_4__and0000)
  );
  INV   DCORIE_5__and00001 (
    .I(Reset),
    .O(DCORIE_5__and00001_400)
  );
  AND2   DCORIE_5__and00002 (
    .I0(inDATA[5]),
    .I1(DCORIE_5__and00001_400),
    .O(DCORIE_5__and0000)
  );
  INV   DCORIE_6__and00001 (
    .I(Reset),
    .O(DCORIE_6__and00001_403)
  );
  AND2   DCORIE_6__and00002 (
    .I0(inDATA[6]),
    .I1(DCORIE_6__and00001_403),
    .O(DCORIE_6__and0000)
  );
  INV   DCORIE_7__and00001 (
    .I(Reset),
    .O(DCORIE_7__and00001_406)
  );
  AND2   DCORIE_7__and00002 (
    .I0(inDATA[7]),
    .I1(DCORIE_7__and00001_406),
    .O(DCORIE_7__and0000)
  );
  INV   SFDecomp_21 (
    .I(BusInt),
    .O(SFDecomp_21_423)
  );
  AND2   SFDecomp_22 (
    .I0(\DCORIE[0] ),
    .I1(SFDecomp_21_423),
    .O(SFDecomp_22_424)
  );
  OR2   SFDecomp_23 (
    .I0(SFDecomp_6),
    .I1(SFDecomp_22_424),
    .O(SFDecomp_2)
  );
  AND2   SFDecomp_11 (
    .I0(\DCORIE[6] ),
    .I1(Thres1),
    .O(SFDecomp_11_421)
  );
  OR2   SFDecomp_12 (
    .I0(SFDecomp_8),
    .I1(SFDecomp_11_421),
    .O(SFDecomp_1)
  );
  OR2   INT1 (
    .I0(SFDecomp_2),
    .I1(SFDecomp_9),
    .O(INT1_413)
  );
  AND2   INT2 (
    .I0(\DCORIE[4] ),
    .I1(LSwitchInt),
    .O(INT2_414)
  );
  OR2   INT3 (
    .I0(INT1_413),
    .I1(INT2_414),
    .O(INT)
  );
  AND2   SFDecomp_51 (
    .I0(\DCORIE[1] ),
    .I1(PWRint),
    .O(SFDecomp_5)
  );
  AND2   SFDecomp_61 (
    .I0(\DCORIE[2] ),
    .I1(Homed0),
    .O(SFDecomp_61_427)
  );
  OR2   SFDecomp_62 (
    .I0(SFDecomp_5),
    .I1(SFDecomp_61_427),
    .O(SFDecomp_6)
  );
  AND2   SFDecomp_71 (
    .I0(\DCORIE[7] ),
    .I1(I2Cint),
    .O(SFDecomp_7)
  );
  AND2   SFDecomp_81 (
    .I0(NlwRenamedSig_OI_TP),
    .I1(Thres0),
    .O(SFDecomp_81_430)
  );
  OR2   SFDecomp_82 (
    .I0(SFDecomp_7),
    .I1(SFDecomp_81_430),
    .O(SFDecomp_8)
  );
  AND2   SFDecomp_91 (
    .I0(\DCORIE[3] ),
    .I1(Homed1),
    .O(SFDecomp_91_432)
  );
  OR2   SFDecomp_92 (
    .I0(SFDecomp_1),
    .I1(SFDecomp_91_432),
    .O(SFDecomp_9)
  );
endmodule

module PWMtranslator_INST_1 (
  PWM, RLS, DIR, external_pwm_o, fBRK, PAH, PAL, PBH, FLS, PBL, Brake, HBRK, MTRpwr
);
  input PWM;
  input RLS;
  input DIR;
  output external_pwm_o;
  input fBRK;
  output PAH;
  output PAL;
  output PBH;
  input FLS;
  output PBL;
  input Brake;
  input HBRK;
  input MTRpwr;
  wire BRK;
  wire N0;
  wire PAH1_333;
  wire PAH2_334;
  wire PAL_or0000;
  wire PAL_or00001_337;
  wire PBH1_339;
  wire PBH2_340;
  wire PBL_or0000;
  wire PBL_or00001_343;
  wire PBL_or00002_344;
  wire SFDecomp_1;
  wire SFDecomp_11_348;
  wire SFDecomp_12_349;
  wire SFDecomp_2;
  wire external_pwm_o1_352;
  wire external_pwm_o2_353;
  wire external_pwm_o3_354;
  OR3   BRK1 (
    .I0(Brake),
    .I1(HBRK),
    .I2(fBRK),
    .O(BRK)
  );
  AND2   PAH1 (
    .I0(MTRpwr),
    .I1(SFDecomp_1),
    .O(PAH1_333)
  );
  INV   PAH2 (
    .I(BRK),
    .O(PAH2_334)
  );
  AND2   PAH3 (
    .I0(PAH1_333),
    .I1(PAH2_334),
    .O(PAH)
  );
  AND2   PAL1 (
    .I0(PAL_or0000),
    .I1(MTRpwr),
    .O(PAL)
  );
  AND2   PBH1 (
    .I0(MTRpwr),
    .I1(SFDecomp_2),
    .O(PBH1_339)
  );
  INV   PBH2 (
    .I(BRK),
    .O(PBH2_340)
  );
  AND2   PBH3 (
    .I0(PBH1_339),
    .I1(PBH2_340),
    .O(PBH)
  );
  AND2   PBL1 (
    .I0(PBL_or0000),
    .I1(MTRpwr),
    .O(PBL)
  );
  AND2   external_pwm_o1 (
    .I0(FLS),
    .I1(RLS),
    .O(external_pwm_o1_352)
  );
  INV   external_pwm_o2 (
    .I(BRK),
    .O(external_pwm_o2_353)
  );
  AND2   external_pwm_o3 (
    .I0(PWM),
    .I1(external_pwm_o2_353),
    .O(external_pwm_o3_354)
  );
  AND2   external_pwm_o4 (
    .I0(external_pwm_o1_352),
    .I1(external_pwm_o3_354),
    .O(external_pwm_o)
  );
  AND2   SFDecomp_11 (
    .I0(RLS),
    .I1(PWM),
    .O(SFDecomp_11_348)
  );
  INV   SFDecomp_12 (
    .I(DIR),
    .O(SFDecomp_12_349)
  );
  AND2   SFDecomp_13 (
    .I0(SFDecomp_11_348),
    .I1(SFDecomp_12_349),
    .O(SFDecomp_1)
  );
  AND3   SFDecomp_21 (
    .I0(PWM),
    .I1(DIR),
    .I2(FLS),
    .O(SFDecomp_2)
  );
  XOR2   PAL_or000011 (
    .I0(PWM),
    .I1(DIR),
    .O(N0)
  );
  INV   PAL_or00001 (
    .I(BRK),
    .O(PAL_or00001_337)
  );
  AND2   PAL_or00002 (
    .I0(N0),
    .I1(PAL_or00001_337),
    .O(PAL_or0000)
  );
  INV   PBL_or00001 (
    .I(BRK),
    .O(PBL_or00001_343)
  );
  INV   PBL_or00002 (
    .I(N0),
    .O(PBL_or00002_344)
  );
  AND2   PBL_or00003 (
    .I0(PBL_or00001_343),
    .I1(PBL_or00002_344),
    .O(PBL_or0000)
  );
endmodule

module PWMtranslator (
  PWM, RLS, DIR, external_pwm_o, fBRK, PAH, PAL, PBH, FLS, PBL, Brake, HBRK, MTRpwr
);
  input PWM;
  input RLS;
  input DIR;
  output external_pwm_o;
  input fBRK;
  output PAH;
  output PAL;
  output PBH;
  input FLS;
  output PBL;
  input Brake;
  input HBRK;
  input MTRpwr;
  wire BRK;
  wire N0;
  wire PAH1_302;
  wire PAH2_303;
  wire PAL_or0000;
  wire PAL_or00001_306;
  wire PBH1_308;
  wire PBH2_309;
  wire PBL_or0000;
  wire PBL_or00001_312;
  wire PBL_or00002_313;
  wire SFDecomp_1;
  wire SFDecomp_11_317;
  wire SFDecomp_12_318;
  wire SFDecomp_2;
  wire external_pwm_o1_321;
  wire external_pwm_o2_322;
  wire external_pwm_o3_323;
  OR3   BRK1 (
    .I0(Brake),
    .I1(HBRK),
    .I2(fBRK),
    .O(BRK)
  );
  AND2   PAH1 (
    .I0(MTRpwr),
    .I1(SFDecomp_1),
    .O(PAH1_302)
  );
  INV   PAH2 (
    .I(BRK),
    .O(PAH2_303)
  );
  AND2   PAH3 (
    .I0(PAH1_302),
    .I1(PAH2_303),
    .O(PAH)
  );
  AND2   PAL1 (
    .I0(PAL_or0000),
    .I1(MTRpwr),
    .O(PAL)
  );
  AND2   PBH1 (
    .I0(MTRpwr),
    .I1(SFDecomp_2),
    .O(PBH1_308)
  );
  INV   PBH2 (
    .I(BRK),
    .O(PBH2_309)
  );
  AND2   PBH3 (
    .I0(PBH1_308),
    .I1(PBH2_309),
    .O(PBH)
  );
  AND2   PBL1 (
    .I0(PBL_or0000),
    .I1(MTRpwr),
    .O(PBL)
  );
  AND2   external_pwm_o1 (
    .I0(FLS),
    .I1(RLS),
    .O(external_pwm_o1_321)
  );
  INV   external_pwm_o2 (
    .I(BRK),
    .O(external_pwm_o2_322)
  );
  AND2   external_pwm_o3 (
    .I0(PWM),
    .I1(external_pwm_o2_322),
    .O(external_pwm_o3_323)
  );
  AND2   external_pwm_o4 (
    .I0(external_pwm_o1_321),
    .I1(external_pwm_o3_323),
    .O(external_pwm_o)
  );
  AND2   SFDecomp_11 (
    .I0(RLS),
    .I1(PWM),
    .O(SFDecomp_11_317)
  );
  INV   SFDecomp_12 (
    .I(DIR),
    .O(SFDecomp_12_318)
  );
  AND2   SFDecomp_13 (
    .I0(SFDecomp_11_317),
    .I1(SFDecomp_12_318),
    .O(SFDecomp_1)
  );
  AND3   SFDecomp_21 (
    .I0(PWM),
    .I1(DIR),
    .I2(FLS),
    .O(SFDecomp_2)
  );
  XOR2   PAL_or000011 (
    .I0(PWM),
    .I1(DIR),
    .O(N0)
  );
  INV   PAL_or00001 (
    .I(BRK),
    .O(PAL_or00001_306)
  );
  AND2   PAL_or00002 (
    .I0(N0),
    .I1(PAL_or00001_306),
    .O(PAL_or0000)
  );
  INV   PBL_or00001 (
    .I(BRK),
    .O(PBL_or00001_312)
  );
  INV   PBL_or00002 (
    .I(N0),
    .O(PBL_or00002_313)
  );
  AND2   PBL_or00003 (
    .I0(PBL_or00001_312),
    .I1(PBL_or00002_313),
    .O(PBL_or0000)
  );
endmodule

module PWMcontrol (
  Brake1, Brake2, fBRK1, fBRK2, PWM1, PWM2, PAH1, RLS0, PAH2, RLS1, PWM0_out, PAL1, PAL2, PBH1, PBH2, FLS0, FLS1, PBL1, PBL2, PWM1_out, HBRK1, HBRK2, 
DIR1, DIR2, MTRpwr
);
  input Brake1;
  input Brake2;
  input fBRK1;
  input fBRK2;
  input PWM1;
  input PWM2;
  output PAH1;
  input RLS0;
  output PAH2;
  input RLS1;
  output PWM0_out;
  output PAL1;
  output PAL2;
  output PBH1;
  output PBH2;
  input FLS0;
  input FLS1;
  output PBL1;
  output PBL2;
  output PWM1_out;
  input HBRK1;
  input HBRK2;
  input DIR1;
  input DIR2;
  input MTRpwr;
  PWMtranslator   U2 (
    .PWM(PWM2),
    .RLS(RLS1),
    .DIR(DIR2),
    .external_pwm_o(PWM1_out),
    .fBRK(fBRK2),
    .PAH(PAH2),
    .PAL(PAL2),
    .PBH(PBH2),
    .FLS(FLS1),
    .PBL(PBL2),
    .Brake(Brake2),
    .HBRK(HBRK2),
    .MTRpwr(MTRpwr)
  );
  PWMtranslator_INST_1   U1 (
    .PWM(PWM1),
    .RLS(RLS0),
    .DIR(DIR1),
    .external_pwm_o(PWM0_out),
    .fBRK(fBRK1),
    .PAH(PAH1),
    .PAL(PAL1),
    .PBH(PBH1),
    .FLS(FLS0),
    .PBL(PBL1),
    .Brake(Brake1),
    .HBRK(HBRK1),
    .MTRpwr(MTRpwr)
  );
endmodule

module NegDetect_INST_2 (
  Line, Ndetect, Mclk
);
  input Line;
  output Ndetect;
  input Mclk;
  wire Line_last_288;
  wire Ndetectr_0_not0000;
  wire Ndetectr__and0000;
  wire Ndetectr_and0000;
  FD   Line_last (
    .C(Ndetectr_0_not0000),
    .D(Line),
    .Q(Line_last_288)
  );
  FD   Ndetectr (
    .C(Ndetectr_0_not0000),
    .D(Ndetectr__and0000),
    .Q(Ndetect)
  );
  INV   Ndetectr_and00001 (
    .I(Line),
    .O(Ndetectr_and0000)
  );
  AND2   Ndetectr_and00002 (
    .I0(Line_last_288),
    .I1(Ndetectr_and0000),
    .O(Ndetectr__and0000)
  );
  INV   Ndetectr_0_not00001 (
    .I(Mclk),
    .O(Ndetectr_0_not0000)
  );
endmodule

module NegDetect_INST_1 (
  Line, Ndetect, Mclk
);
  input Line;
  output Ndetect;
  input Mclk;
  wire Line_last_281;
  wire Ndetectr_0_not0000;
  wire Ndetectr__and0000;
  wire Ndetectr_and0000;
  FD   Line_last (
    .C(Ndetectr_0_not0000),
    .D(Line),
    .Q(Line_last_281)
  );
  FD   Ndetectr (
    .C(Ndetectr_0_not0000),
    .D(Ndetectr__and0000),
    .Q(Ndetect)
  );
  INV   Ndetectr_and00001 (
    .I(Line),
    .O(Ndetectr_and0000)
  );
  AND2   Ndetectr_and00002 (
    .I0(Line_last_281),
    .I1(Ndetectr_and0000),
    .O(Ndetectr__and0000)
  );
  INV   Ndetectr_0_not00001 (
    .I(Mclk),
    .O(Ndetectr_0_not0000)
  );
endmodule

module NegDetect (
  Line, Ndetect, Mclk
);
  input Line;
  output Ndetect;
  input Mclk;
  wire Line_last_274;
  wire Ndetectr_0_not0000;
  wire Ndetectr__and0000;
  wire Ndetectr_and0000;
  FD   Line_last (
    .C(Ndetectr_0_not0000),
    .D(Line),
    .Q(Line_last_274)
  );
  FD   Ndetectr (
    .C(Ndetectr_0_not0000),
    .D(Ndetectr__and0000),
    .Q(Ndetect)
  );
  INV   Ndetectr_and00001 (
    .I(Line),
    .O(Ndetectr_and0000)
  );
  AND2   Ndetectr_and00002 (
    .I0(Line_last_274),
    .I1(Ndetectr_and0000),
    .O(Ndetectr__and0000)
  );
  INV   Ndetectr_0_not00001 (
    .I(Mclk),
    .O(Ndetectr_0_not0000)
  );
endmodule

module I2CAddress (
  DCORCONFIGr, MotorIn0, MotorIn1, outDATA, I2CS
);
  input DCORCONFIGr;
  input MotorIn0;
  input MotorIn1;
  output [7 : 0] outDATA;
  input [5 : 0] I2CS;
  BUFE   \outDATA<7>_MotorIn1_0  (
    .I(MotorIn1),
    .E(DCORCONFIGr),
    .O(outDATA[7])
  );
  BUFE   \outDATA<6>_MotorIn0_0  (
    .I(MotorIn0),
    .E(DCORCONFIGr),
    .O(outDATA[6])
  );
  BUFE   \outDATA<5>_I2CS<5>_0  (
    .I(I2CS[5]),
    .E(DCORCONFIGr),
    .O(outDATA[5])
  );
  BUFE   \outDATA<4>_I2CS<4>_0  (
    .I(I2CS[4]),
    .E(DCORCONFIGr),
    .O(outDATA[4])
  );
  BUFE   \outDATA<3>_I2CS<3>_0  (
    .I(I2CS[3]),
    .E(DCORCONFIGr),
    .O(outDATA[3])
  );
  BUFE   \outDATA<2>_I2CS<2>_0  (
    .I(I2CS[2]),
    .E(DCORCONFIGr),
    .O(outDATA[2])
  );
  BUFE   \outDATA<1>_I2CS<1>_0  (
    .I(I2CS[1]),
    .E(DCORCONFIGr),
    .O(outDATA[1])
  );
  BUFE   \outDATA<0>_I2CS<0>_0  (
    .I(I2CS[0]),
    .E(DCORCONFIGr),
    .O(outDATA[0])
  );
endmodule

module Lswitch (
  Brake0, Brake1, DCORLINTr, Reset, fBRK0, fBRK1, DCORLIMITSr, Home0, Home1, RLS0, RLS1, DCORIFGw, FLS0, FLS1, LSwitchInt, LIFG, DIR0, DIR1, Mclk, 
outDATA
);
  input Brake0;
  input Brake1;
  input DCORLINTr;
  input Reset;
  output fBRK0;
  output fBRK1;
  input DCORLIMITSr;
  input Home0;
  input Home1;
  input RLS0;
  input RLS1;
  input DCORIFGw;
  input FLS0;
  input FLS1;
  output LSwitchInt;
  input LIFG;
  input DIR0;
  input DIR1;
  input Mclk;
  output [7 : 0] outDATA;
  wire DCORIFG_0_not0000;
  wire DCORIFG__and0000;
  wire DCORIFG__and00001;
  wire DCORIFG__and000011_149;
  wire DCORIFG__and000012_150;
  wire DCORIFG__and000013_151;
  wire DCORIFG__and000014_152;
  wire DCORIFG__or0000;
  wire DCORIFG__or0000_bdd0;
  wire FLS0fr_161;
  wire FLS0fr__and0000;
  wire FLS0fr__and00001_163;
  wire FLS0fr__or0000;
  wire FLS0r_165;
  wire FLS0r__and0000;
  wire FLS0r__and00001_167;
  wire FLS1fr_169;
  wire FLS1fr__or0000;
  wire FLS1r_171;
  wire FLS1r__and0000;
  wire FLS1r__and00001_173;
  wire Ftrip0;
  wire Ftrip01_175;
  wire Ftrip02_176;
  wire Ftrip1;
  wire Ftrip11_178;
  wire Ftrip12_179;
  wire NlwRenamedSig_OI_LSwitchInt;
  wire N0;
  wire RLS0fr_187;
  wire RLS0fr__or0000;
  wire RLS0r_189;
  wire RLS0r__and0000;
  wire RLS0r__and00001_191;
  wire RLS1fr_193;
  wire RLS1fr__or0000;
  wire RLS1r_195;
  wire RLS1r__and0000;
  wire RLS1r__and00001_197;
  wire Rtrip0;
  wire Rtrip01_200;
  wire Rtrip02_201;
  wire Rtrip1;
  wire Rtrip11_203;
  wire Rtrip12_204;
  wire NlwRenamedSig_OI_fBRK0;
  wire fBRK0r_and0000;
  wire fBRK0r_and00001_207;
  wire fBRK0r_and00002_208;
  wire fBRK0r_not0001;
  wire fBRK0r_or0000;
  wire fBRK0r_or00001_211;
  wire fBRK0r_or00002_212;
  wire fBRK0r_or0001;
  wire fBRK0r_or0002;
  wire NlwRenamedSig_OI_fBRK1;
  wire fBRK1r_and0000;
  wire fBRK1r_and00001_217;
  wire fBRK1r_and00002_218;
  wire fBRK1r_not0001;
  wire fBRK1r_or0000;
  wire fBRK1r_or00001_221;
  wire fBRK1r_or00002_222;
  wire fBRK1r_or0001;
  wire fBRK1r_or0002;
  wire \outDATA_mux0000[0] ;
  wire \outDATA_mux0000<0>1_234 ;
  wire \outDATA_mux0000<0>2_235 ;
  wire \outDATA_mux0000<0>3_236 ;
  wire \outDATA_mux0000<0>4_237 ;
  wire \outDATA_mux0000[1] ;
  wire \outDATA_mux0000<1>1_239 ;
  wire \outDATA_mux0000<1>2_240 ;
  wire \outDATA_mux0000<1>3_241 ;
  wire \outDATA_mux0000<1>4_242 ;
  wire \outDATA_mux0000[2] ;
  wire \outDATA_mux0000[4] ;
  wire \outDATA_mux0000<4>1_245 ;
  wire \outDATA_mux0000<4>2_246 ;
  wire \outDATA_mux0000<4>3_247 ;
  wire \outDATA_mux0000<4>4_248 ;
  wire \outDATA_mux0000[5] ;
  wire \outDATA_mux0000<5>1_250 ;
  wire \outDATA_mux0000<5>2_251 ;
  wire \outDATA_mux0000<5>3_252 ;
  wire \outDATA_mux0000<5>4_253 ;
  wire \outDATA_mux0000[6] ;
  wire outDATA_not0005;
  assign
    fBRK0 = NlwRenamedSig_OI_fBRK0,
    fBRK1 = NlwRenamedSig_OI_fBRK1,
    LSwitchInt = NlwRenamedSig_OI_LSwitchInt;
  GND   XST_GND (
    .G(N0)
  );
  FDCE   fBRK1r (
    .CE(fBRK1r_not0001),
    .CLR(N0),
    .C(DCORIFG_0_not0000),
    .D(fBRK1r_or0002),
    .Q(NlwRenamedSig_OI_fBRK1)
  );
  FDCE   fBRK0r (
    .CE(fBRK0r_not0001),
    .CLR(N0),
    .C(DCORIFG_0_not0000),
    .D(fBRK0r_or0002),
    .Q(NlwRenamedSig_OI_fBRK0)
  );
  BUFE   outDATA_7 (
    .I(NlwRenamedSig_OI_fBRK1),
    .E(outDATA_not0005),
    .O(outDATA[7])
  );
  BUFE   outDATA_6 (
    .I(\outDATA_mux0000[6] ),
    .E(outDATA_not0005),
    .O(outDATA[6])
  );
  BUFE   outDATA_5 (
    .I(\outDATA_mux0000[5] ),
    .E(outDATA_not0005),
    .O(outDATA[5])
  );
  BUFE   outDATA_4 (
    .I(\outDATA_mux0000[4] ),
    .E(outDATA_not0005),
    .O(outDATA[4])
  );
  BUFE   outDATA_3 (
    .I(NlwRenamedSig_OI_fBRK0),
    .E(outDATA_not0005),
    .O(outDATA[3])
  );
  BUFE   outDATA_2 (
    .I(\outDATA_mux0000[2] ),
    .E(outDATA_not0005),
    .O(outDATA[2])
  );
  BUFE   outDATA_1 (
    .I(\outDATA_mux0000[1] ),
    .E(outDATA_not0005),
    .O(outDATA[1])
  );
  BUFE   outDATA_0 (
    .I(\outDATA_mux0000[0] ),
    .E(outDATA_not0005),
    .O(outDATA[0])
  );
  FD   FLS0r (
    .C(DCORIFG_0_not0000),
    .D(FLS0r__and0000),
    .Q(FLS0r_165)
  );
  FD   RLS0r (
    .C(DCORIFG_0_not0000),
    .D(RLS0r__and0000),
    .Q(RLS0r_189)
  );
  FD   FLS1r (
    .C(DCORIFG_0_not0000),
    .D(FLS1r__and0000),
    .Q(FLS1r_171)
  );
  FD   RLS1r (
    .C(DCORIFG_0_not0000),
    .D(RLS1r__and0000),
    .Q(RLS1r_195)
  );
  FDCE   FLS0fr (
    .CE(FLS0fr__or0000),
    .CLR(N0),
    .C(DCORIFG_0_not0000),
    .D(FLS0fr__and0000),
    .Q(FLS0fr_161)
  );
  FDCE   RLS0fr (
    .CE(RLS0fr__or0000),
    .CLR(N0),
    .C(DCORIFG_0_not0000),
    .D(FLS0fr__and0000),
    .Q(RLS0fr_187)
  );
  FDCE   FLS1fr (
    .CE(FLS1fr__or0000),
    .CLR(N0),
    .C(DCORIFG_0_not0000),
    .D(FLS0fr__and0000),
    .Q(FLS1fr_169)
  );
  FDCE   RLS1fr (
    .CE(RLS1fr__or0000),
    .CLR(N0),
    .C(DCORIFG_0_not0000),
    .D(FLS0fr__and0000),
    .Q(RLS1fr_193)
  );
  FDCE   DCORIFG (
    .CE(DCORIFG__or0000),
    .CLR(N0),
    .C(DCORIFG_0_not0000),
    .D(DCORIFG__and0000),
    .Q(NlwRenamedSig_OI_LSwitchInt)
  );
  AND2   \outDATA_mux0000<6>1  (
    .I0(DCORLIMITSr),
    .I1(Home1),
    .O(\outDATA_mux0000[6] )
  );
  INV   \outDATA_mux0000<5>1  (
    .I(DCORLIMITSr),
    .O(\outDATA_mux0000<5>1_250 )
  );
  INV   \outDATA_mux0000<5>2  (
    .I(FLS1),
    .O(\outDATA_mux0000<5>2_251 )
  );
  AND2   \outDATA_mux0000<5>3  (
    .I0(FLS1fr_169),
    .I1(\outDATA_mux0000<5>1_250 ),
    .O(\outDATA_mux0000<5>3_252 )
  );
  AND2   \outDATA_mux0000<5>4  (
    .I0(DCORLIMITSr),
    .I1(\outDATA_mux0000<5>2_251 ),
    .O(\outDATA_mux0000<5>4_253 )
  );
  OR2   \outDATA_mux0000<5>5  (
    .I0(\outDATA_mux0000<5>3_252 ),
    .I1(\outDATA_mux0000<5>4_253 ),
    .O(\outDATA_mux0000[5] )
  );
  INV   \outDATA_mux0000<4>1  (
    .I(DCORLIMITSr),
    .O(\outDATA_mux0000<4>1_245 )
  );
  INV   \outDATA_mux0000<4>2  (
    .I(RLS1),
    .O(\outDATA_mux0000<4>2_246 )
  );
  AND2   \outDATA_mux0000<4>3  (
    .I0(RLS1fr_193),
    .I1(\outDATA_mux0000<4>1_245 ),
    .O(\outDATA_mux0000<4>3_247 )
  );
  AND2   \outDATA_mux0000<4>4  (
    .I0(DCORLIMITSr),
    .I1(\outDATA_mux0000<4>2_246 ),
    .O(\outDATA_mux0000<4>4_248 )
  );
  OR2   \outDATA_mux0000<4>5  (
    .I0(\outDATA_mux0000<4>3_247 ),
    .I1(\outDATA_mux0000<4>4_248 ),
    .O(\outDATA_mux0000[4] )
  );
  AND2   \outDATA_mux0000<2>1  (
    .I0(DCORLIMITSr),
    .I1(Home0),
    .O(\outDATA_mux0000[2] )
  );
  INV   \outDATA_mux0000<1>1  (
    .I(DCORLIMITSr),
    .O(\outDATA_mux0000<1>1_239 )
  );
  INV   \outDATA_mux0000<1>2  (
    .I(FLS0),
    .O(\outDATA_mux0000<1>2_240 )
  );
  AND2   \outDATA_mux0000<1>3  (
    .I0(FLS0fr_161),
    .I1(\outDATA_mux0000<1>1_239 ),
    .O(\outDATA_mux0000<1>3_241 )
  );
  AND2   \outDATA_mux0000<1>4  (
    .I0(DCORLIMITSr),
    .I1(\outDATA_mux0000<1>2_240 ),
    .O(\outDATA_mux0000<1>4_242 )
  );
  OR2   \outDATA_mux0000<1>5  (
    .I0(\outDATA_mux0000<1>3_241 ),
    .I1(\outDATA_mux0000<1>4_242 ),
    .O(\outDATA_mux0000[1] )
  );
  INV   \outDATA_mux0000<0>1  (
    .I(DCORLIMITSr),
    .O(\outDATA_mux0000<0>1_234 )
  );
  INV   \outDATA_mux0000<0>2  (
    .I(RLS0),
    .O(\outDATA_mux0000<0>2_235 )
  );
  AND2   \outDATA_mux0000<0>3  (
    .I0(RLS0fr_187),
    .I1(\outDATA_mux0000<0>1_234 ),
    .O(\outDATA_mux0000<0>3_236 )
  );
  AND2   \outDATA_mux0000<0>4  (
    .I0(DCORLIMITSr),
    .I1(\outDATA_mux0000<0>2_235 ),
    .O(\outDATA_mux0000<0>4_237 )
  );
  OR2   \outDATA_mux0000<0>5  (
    .I0(\outDATA_mux0000<0>3_236 ),
    .I1(\outDATA_mux0000<0>4_237 ),
    .O(\outDATA_mux0000[0] )
  );
  INV   FLS0r__and00001 (
    .I(Reset),
    .O(FLS0r__and00001_167)
  );
  AND2   FLS0r__and00002 (
    .I0(FLS0),
    .I1(FLS0r__and00001_167),
    .O(FLS0r__and0000)
  );
  INV   RLS0r__and00001 (
    .I(Reset),
    .O(RLS0r__and00001_191)
  );
  AND2   RLS0r__and00002 (
    .I0(RLS0),
    .I1(RLS0r__and00001_191),
    .O(RLS0r__and0000)
  );
  INV   FLS1r__and00001 (
    .I(Reset),
    .O(FLS1r__and00001_173)
  );
  AND2   FLS1r__and00002 (
    .I0(FLS1),
    .I1(FLS1r__and00001_173),
    .O(FLS1r__and0000)
  );
  INV   RLS1r__and00001 (
    .I(Reset),
    .O(RLS1r__and00001_197)
  );
  AND2   RLS1r__and00002 (
    .I0(RLS1),
    .I1(RLS1r__and00001_197),
    .O(RLS1r__and0000)
  );
  INV   DCORIFG_0_not00001 (
    .I(Mclk),
    .O(DCORIFG_0_not0000)
  );
  OR3   RLS1fr__or00001 (
    .I0(Rtrip1),
    .I1(DCORLINTr),
    .I2(Reset),
    .O(RLS1fr__or0000)
  );
  OR2   fBRK1r_or00021 (
    .I0(Rtrip1),
    .I1(Ftrip1),
    .O(fBRK1r_or0002)
  );
  INV   Rtrip11 (
    .I(RLS1),
    .O(Rtrip11_203)
  );
  INV   Rtrip12 (
    .I(DIR1),
    .O(Rtrip12_204)
  );
  AND3   Rtrip13 (
    .I0(Rtrip11_203),
    .I1(RLS1r_195),
    .I2(Rtrip12_204),
    .O(Rtrip1)
  );
  OR2   fBRK1r_or00001 (
    .I0(RLS1fr_193),
    .I1(FLS1fr_169),
    .O(fBRK1r_or00001_221)
  );
  INV   fBRK1r_or00002 (
    .I(Brake1),
    .O(fBRK1r_or00002_222)
  );
  OR2   fBRK1r_or00003 (
    .I0(fBRK1r_or00001_221),
    .I1(fBRK1r_or00002_222),
    .O(fBRK1r_or0000)
  );
  INV   fBRK1r_not00011 (
    .I(fBRK1r_or0001),
    .O(fBRK1r_not0001)
  );
  OR3   fBRK1r_or00011 (
    .I0(DCORLINTr),
    .I1(fBRK1r_and0000),
    .I2(Reset),
    .O(fBRK1r_or0001)
  );
  INV   fBRK1r_and00001 (
    .I(Ftrip1),
    .O(fBRK1r_and00001_217)
  );
  INV   fBRK1r_and00002 (
    .I(Rtrip1),
    .O(fBRK1r_and00002_218)
  );
  AND3   fBRK1r_and00003 (
    .I0(fBRK1r_and00001_217),
    .I1(fBRK1r_or0000),
    .I2(fBRK1r_and00002_218),
    .O(fBRK1r_and0000)
  );
  AND2   Ftrip11 (
    .I0(FLS1r_171),
    .I1(DIR1),
    .O(Ftrip11_178)
  );
  INV   Ftrip12 (
    .I(FLS1),
    .O(Ftrip12_179)
  );
  AND2   Ftrip13 (
    .I0(Ftrip11_178),
    .I1(Ftrip12_179),
    .O(Ftrip1)
  );
  OR3   FLS1fr__or00001 (
    .I0(Ftrip1),
    .I1(DCORLINTr),
    .I2(Reset),
    .O(FLS1fr__or0000)
  );
  OR2   FLS0fr__and00001 (
    .I0(DCORLINTr),
    .I1(Reset),
    .O(FLS0fr__and00001_163)
  );
  INV   FLS0fr__and00002 (
    .I(FLS0fr__and00001_163),
    .O(FLS0fr__and0000)
  );
  OR3   FLS0fr__or00001 (
    .I0(Ftrip0),
    .I1(DCORLINTr),
    .I2(Reset),
    .O(FLS0fr__or0000)
  );
  OR3   RLS0fr__or00001 (
    .I0(Rtrip0),
    .I1(DCORLINTr),
    .I2(Reset),
    .O(RLS0fr__or0000)
  );
  OR2   fBRK0r_or00021 (
    .I0(Rtrip0),
    .I1(Ftrip0),
    .O(fBRK0r_or0002)
  );
  INV   Rtrip01 (
    .I(RLS0),
    .O(Rtrip01_200)
  );
  INV   Rtrip02 (
    .I(DIR0),
    .O(Rtrip02_201)
  );
  AND3   Rtrip03 (
    .I0(Rtrip01_200),
    .I1(RLS0r_189),
    .I2(Rtrip02_201),
    .O(Rtrip0)
  );
  OR2   fBRK0r_or00001 (
    .I0(RLS0fr_187),
    .I1(FLS0fr_161),
    .O(fBRK0r_or00001_211)
  );
  INV   fBRK0r_or00002 (
    .I(Brake0),
    .O(fBRK0r_or00002_212)
  );
  OR2   fBRK0r_or00003 (
    .I0(fBRK0r_or00001_211),
    .I1(fBRK0r_or00002_212),
    .O(fBRK0r_or0000)
  );
  INV   fBRK0r_not00011 (
    .I(fBRK0r_or0001),
    .O(fBRK0r_not0001)
  );
  OR3   fBRK0r_or00011 (
    .I0(DCORLINTr),
    .I1(fBRK0r_and0000),
    .I2(Reset),
    .O(fBRK0r_or0001)
  );
  INV   fBRK0r_and00001 (
    .I(Ftrip0),
    .O(fBRK0r_and00001_207)
  );
  INV   fBRK0r_and00002 (
    .I(Rtrip0),
    .O(fBRK0r_and00002_208)
  );
  AND3   fBRK0r_and00003 (
    .I0(fBRK0r_and00001_207),
    .I1(fBRK0r_or0000),
    .I2(fBRK0r_and00002_208),
    .O(fBRK0r_and0000)
  );
  AND2   Ftrip01 (
    .I0(FLS0r_165),
    .I1(DIR0),
    .O(Ftrip01_175)
  );
  INV   Ftrip02 (
    .I(FLS0),
    .O(Ftrip02_176)
  );
  AND2   Ftrip03 (
    .I0(Ftrip01_175),
    .I1(Ftrip02_176),
    .O(Ftrip0)
  );
  INV   DCORIFG__and000011 (
    .I(LIFG),
    .O(DCORIFG__and00001)
  );
  INV   DCORIFG__and000012 (
    .I(DCORIFGw),
    .O(DCORIFG__and000011_149)
  );
  INV   DCORIFG__and000013 (
    .I(Reset),
    .O(DCORIFG__and000012_150)
  );
  AND2   DCORIFG__and000014 (
    .I0(NlwRenamedSig_OI_LSwitchInt),
    .I1(DCORIFG__and00001),
    .O(DCORIFG__and000013_151)
  );
  OR2   DCORIFG__and000015 (
    .I0(DCORIFG__and000013_151),
    .I1(DCORIFG__and000011_149),
    .O(DCORIFG__and000014_152)
  );
  AND2   DCORIFG__and000016 (
    .I0(DCORIFG__and000014_152),
    .I1(DCORIFG__and000012_150),
    .O(DCORIFG__and0000)
  );
  OR3   DCORIFG__or000021 (
    .I0(RLS0fr_187),
    .I1(FLS1fr_169),
    .I2(RLS1fr_193),
    .O(DCORIFG__or0000_bdd0)
  );
  OR4   DCORIFG__or000011 (
    .I0(Reset),
    .I1(DCORIFGw),
    .I2(FLS0fr_161),
    .I3(DCORIFG__or0000_bdd0),
    .O(DCORIFG__or0000)
  );
  OR2   outDATA_not000511 (
    .I0(DCORLIMITSr),
    .I1(DCORLINTr),
    .O(outDATA_not0005)
  );
endmodule

module U21AddDecode (
  DCORENCPWRr, DCOR0CNTLOWr, DCORENCPWRw, DCORENCCTLw, DCOR0THRESLOWr, AS, DCOR0THRESHIGHr, DCOR1CNTHIGHr, DCORLINTr, DCOR0CNTHIGHr, DCOR1THRESHIGHr, 
DCORLIMITSr, DCORSENSORw, DCORCONFIGr, DCORIFGr, DCORIFGw, RD, DCOROUTw, DCORIEw, WR, DCOR1CNTLOWr, DCOR1THRESLOWr, DCORI2CCNTr, ADDR
);
  output DCORENCPWRr;
  output DCOR0CNTLOWr;
  output DCORENCPWRw;
  output DCORENCCTLw;
  output DCOR0THRESLOWr;
  input AS;
  output DCOR0THRESHIGHr;
  output DCOR1CNTHIGHr;
  output DCORLINTr;
  output DCOR0CNTHIGHr;
  output DCOR1THRESHIGHr;
  output DCORLIMITSr;
  output DCORSENSORw;
  output DCORCONFIGr;
  output DCORIFGr;
  output DCORIFGw;
  input RD;
  output DCOROUTw;
  output DCORIEw;
  input WR;
  output DCOR1CNTLOWr;
  output DCOR1THRESLOWr;
  output DCORI2CCNTr;
  input [7 : 0] ADDR;
  wire N0;
  wire N1;
  wire N21;
  wire N31;
  wire SFDecomp_1;
  wire SFDecomp_10;
  wire SFDecomp_101_97;
  wire SFDecomp_102_98;
  wire SFDecomp_103_99;
  wire SFDecomp_11_100;
  wire SFDecomp_12_101;
  wire SFDecomp_13;
  wire SFDecomp_131_103;
  wire SFDecomp_132_104;
  wire SFDecomp_15;
  wire SFDecomp_151_106;
  wire SFDecomp_152_107;
  wire SFDecomp_17;
  wire SFDecomp_19;
  wire SFDecomp_191_110;
  wire SFDecomp_192_111;
  wire SFDecomp_193_112;
  wire SFDecomp_21;
  wire SFDecomp_211_114;
  wire SFDecomp_212_115;
  wire SFDecomp_23;
  wire SFDecomp_231_117;
  wire SFDecomp_232_118;
  wire SFDecomp_25;
  wire SFDecomp_251_120;
  wire SFDecomp_252_121;
  wire Select_10_Select1_122;
  wire Select_17_Select1_123;
  wire Select_cmp_eq0000;
  wire Select_cmp_eq00001_125;
  wire Select_cmp_eq000011_126;
  wire Select_cmp_eq0001;
  wire Select_cmp_eq00011_128;
  wire Select_cmp_eq000111_129;
  wire Select_cmp_eq0002;
  wire Select_cmp_eq0003;
  wire Select_cmp_eq0004;
  wire Select_cmp_eq0005;
  wire Select_cmp_eq0006;
  wire Select_cmp_eq0007;
  wire Select_cmp_eq0008;
  wire Select_cmp_eq0009;
  wire Select_cmp_eq0010;
  wire Select_cmp_eq0011;
  wire Select_cmp_eq0012;
  wire Select_cmp_eq0013;
  wire Select_cmp_eq0014;
  INV   SFDecomp_11 (
    .I(ADDR[1]),
    .O(SFDecomp_11_100)
  );
  INV   SFDecomp_12 (
    .I(ADDR[0]),
    .O(SFDecomp_12_101)
  );
  AND3   SFDecomp_14 (
    .I0(SFDecomp_11_100),
    .I1(ADDR[2]),
    .I2(SFDecomp_12_101),
    .O(SFDecomp_1)
  );
  INV   SFDecomp_101 (
    .I(ADDR[7]),
    .O(SFDecomp_101_97)
  );
  INV   SFDecomp_102 (
    .I(ADDR[6]),
    .O(SFDecomp_102_98)
  );
  INV   SFDecomp_103 (
    .I(ADDR[5]),
    .O(SFDecomp_103_99)
  );
  AND3   SFDecomp_104 (
    .I0(SFDecomp_102_98),
    .I1(SFDecomp_101_97),
    .I2(SFDecomp_103_99),
    .O(SFDecomp_10)
  );
  AND2   SFDecomp_131 (
    .I0(ADDR[2]),
    .I1(ADDR[0]),
    .O(SFDecomp_131_103)
  );
  INV   SFDecomp_132 (
    .I(ADDR[1]),
    .O(SFDecomp_132_104)
  );
  AND2   SFDecomp_133 (
    .I0(SFDecomp_131_103),
    .I1(SFDecomp_132_104),
    .O(SFDecomp_13)
  );
  AND2   SFDecomp_151 (
    .I0(ADDR[1]),
    .I1(ADDR[2]),
    .O(SFDecomp_151_106)
  );
  INV   SFDecomp_152 (
    .I(ADDR[0]),
    .O(SFDecomp_152_107)
  );
  AND2   SFDecomp_153 (
    .I0(SFDecomp_151_106),
    .I1(SFDecomp_152_107),
    .O(SFDecomp_15)
  );
  AND3   SFDecomp_171 (
    .I0(ADDR[0]),
    .I1(ADDR[1]),
    .I2(ADDR[2]),
    .O(SFDecomp_17)
  );
  INV   SFDecomp_191 (
    .I(ADDR[1]),
    .O(SFDecomp_191_110)
  );
  INV   SFDecomp_192 (
    .I(ADDR[0]),
    .O(SFDecomp_192_111)
  );
  INV   SFDecomp_193 (
    .I(ADDR[2]),
    .O(SFDecomp_193_112)
  );
  AND3   SFDecomp_194 (
    .I0(SFDecomp_192_111),
    .I1(SFDecomp_191_110),
    .I2(SFDecomp_193_112),
    .O(SFDecomp_19)
  );
  INV   SFDecomp_211 (
    .I(ADDR[1]),
    .O(SFDecomp_211_114)
  );
  INV   SFDecomp_212 (
    .I(ADDR[2]),
    .O(SFDecomp_212_115)
  );
  AND3   SFDecomp_213 (
    .I0(SFDecomp_211_114),
    .I1(ADDR[0]),
    .I2(SFDecomp_212_115),
    .O(SFDecomp_21)
  );
  INV   SFDecomp_231 (
    .I(ADDR[0]),
    .O(SFDecomp_231_117)
  );
  INV   SFDecomp_232 (
    .I(ADDR[2]),
    .O(SFDecomp_232_118)
  );
  AND3   SFDecomp_233 (
    .I0(SFDecomp_231_117),
    .I1(ADDR[1]),
    .I2(SFDecomp_232_118),
    .O(SFDecomp_23)
  );
  AND2   SFDecomp_251 (
    .I0(ADDR[1]),
    .I1(ADDR[0]),
    .O(SFDecomp_251_120)
  );
  INV   SFDecomp_252 (
    .I(ADDR[2]),
    .O(SFDecomp_252_121)
  );
  AND2   SFDecomp_253 (
    .I0(SFDecomp_251_120),
    .I1(SFDecomp_252_121),
    .O(SFDecomp_25)
  );
  INV   Select_cmp_eq000111 (
    .I(ADDR[3]),
    .O(Select_cmp_eq00011_128)
  );
  INV   Select_cmp_eq000112 (
    .I(ADDR[4]),
    .O(Select_cmp_eq000111_129)
  );
  AND3   Select_cmp_eq000113 (
    .I0(Select_cmp_eq00011_128),
    .I1(SFDecomp_10),
    .I2(Select_cmp_eq000111_129),
    .O(N0)
  );
  AND2   Select_cmp_eq00011 (
    .I0(SFDecomp_19),
    .I1(N0),
    .O(Select_cmp_eq0001)
  );
  AND2   Select_cmp_eq00021 (
    .I0(SFDecomp_21),
    .I1(N0),
    .O(Select_cmp_eq0002)
  );
  AND2   Select_cmp_eq00031 (
    .I0(SFDecomp_25),
    .I1(N0),
    .O(Select_cmp_eq0003)
  );
  AND2   Select_cmp_eq00041 (
    .I0(SFDecomp_23),
    .I1(N0),
    .O(Select_cmp_eq0004)
  );
  AND2   Select_cmp_eq00051 (
    .I0(SFDecomp_1),
    .I1(N0),
    .O(Select_cmp_eq0005)
  );
  AND2   Select_cmp_eq00061 (
    .I0(SFDecomp_13),
    .I1(N0),
    .O(Select_cmp_eq0006)
  );
  AND2   Select_cmp_eq00071 (
    .I0(SFDecomp_15),
    .I1(N0),
    .O(Select_cmp_eq0007)
  );
  AND2   Select_cmp_eq00081 (
    .I0(SFDecomp_17),
    .I1(N0),
    .O(Select_cmp_eq0008)
  );
  AND2   Select_cmp_eq000011 (
    .I0(ADDR[3]),
    .I1(SFDecomp_10),
    .O(Select_cmp_eq00001_125)
  );
  INV   Select_cmp_eq000012 (
    .I(ADDR[4]),
    .O(Select_cmp_eq000011_126)
  );
  AND2   Select_cmp_eq000013 (
    .I0(Select_cmp_eq00001_125),
    .I1(Select_cmp_eq000011_126),
    .O(N1)
  );
  AND2   Select_cmp_eq00001 (
    .I0(SFDecomp_1),
    .I1(N1),
    .O(Select_cmp_eq0000)
  );
  AND2   Select_cmp_eq00091 (
    .I0(SFDecomp_19),
    .I1(N1),
    .O(Select_cmp_eq0009)
  );
  AND2   Select_cmp_eq00101 (
    .I0(SFDecomp_21),
    .I1(N1),
    .O(Select_cmp_eq0010)
  );
  AND2   Select_cmp_eq00111 (
    .I0(SFDecomp_23),
    .I1(N1),
    .O(Select_cmp_eq0011)
  );
  AND2   Select_cmp_eq00121 (
    .I0(SFDecomp_25),
    .I1(N1),
    .O(Select_cmp_eq0012)
  );
  AND2   Select_cmp_eq00131 (
    .I0(SFDecomp_15),
    .I1(N1),
    .O(Select_cmp_eq0013)
  );
  AND2   Select_cmp_eq00141 (
    .I0(SFDecomp_17),
    .I1(N1),
    .O(Select_cmp_eq0014)
  );
  INV   Select_10_Select11 (
    .I(RD),
    .O(Select_10_Select1_122)
  );
  AND2   Select_10_Select12 (
    .I0(WR),
    .I1(Select_10_Select1_122),
    .O(N21)
  );
  AND2   Select_4_Select1 (
    .I0(Select_cmp_eq0002),
    .I1(N21),
    .O(DCORIFGr)
  );
  AND2   Select_5_Select1 (
    .I0(Select_cmp_eq0003),
    .I1(N21),
    .O(DCORLIMITSr)
  );
  AND2   Select_6_Select1 (
    .I0(Select_cmp_eq0004),
    .I1(N21),
    .O(DCORLINTr)
  );
  AND2   Select_8_Select1 (
    .I0(Select_cmp_eq0005),
    .I1(N21),
    .O(DCOR0CNTLOWr)
  );
  AND2   Select_9_Select1 (
    .I0(Select_cmp_eq0006),
    .I1(N21),
    .O(DCOR0CNTHIGHr)
  );
  AND2   Select_10_Select1 (
    .I0(Select_cmp_eq0007),
    .I1(N21),
    .O(DCOR1CNTLOWr)
  );
  AND2   Select_11_Select1 (
    .I0(Select_cmp_eq0008),
    .I1(N21),
    .O(DCOR1CNTHIGHr)
  );
  AND2   Select_12_Select1 (
    .I0(Select_cmp_eq0009),
    .I1(N21),
    .O(DCOR0THRESLOWr)
  );
  AND2   Select_13_Select1 (
    .I0(Select_cmp_eq0010),
    .I1(N21),
    .O(DCOR0THRESHIGHr)
  );
  AND2   Select_14_Select1 (
    .I0(Select_cmp_eq0011),
    .I1(N21),
    .O(DCOR1THRESLOWr)
  );
  AND2   Select_15_Select1 (
    .I0(Select_cmp_eq0012),
    .I1(N21),
    .O(DCOR1THRESHIGHr)
  );
  AND2   Select_16_Select1 (
    .I0(Select_cmp_eq0013),
    .I1(N21),
    .O(DCORENCPWRr)
  );
  AND2   Select_18_Select1 (
    .I0(Select_cmp_eq0014),
    .I1(N21),
    .O(DCORCONFIGr)
  );
  AND2   Select_20_Select1 (
    .I0(Select_cmp_eq0001),
    .I1(N21),
    .O(DCORI2CCNTr)
  );
  INV   Select_17_Select11 (
    .I(WR),
    .O(Select_17_Select1_123)
  );
  AND2   Select_17_Select12 (
    .I0(RD),
    .I1(Select_17_Select1_123),
    .O(N31)
  );
  AND2   Select_1_Select1 (
    .I0(Select_cmp_eq0000),
    .I1(N31),
    .O(DCORSENSORw)
  );
  AND2   Select_2_Select1 (
    .I0(Select_cmp_eq0001),
    .I1(N31),
    .O(DCORIEw)
  );
  AND2   Select_3_Select1 (
    .I0(Select_cmp_eq0002),
    .I1(N31),
    .O(DCORIFGw)
  );
  AND2   Select_7_Select1 (
    .I0(Select_cmp_eq0003),
    .I1(N31),
    .O(DCORENCCTLw)
  );
  AND2   Select_17_Select1 (
    .I0(Select_cmp_eq0013),
    .I1(N31),
    .O(DCORENCPWRw)
  );
  AND2   Select_19_Select1 (
    .I0(Select_cmp_eq0014),
    .I1(N31),
    .O(DCOROUTw)
  );
endmodule

module U21 (
  SCL, Brake0, Brake1, Latch133ctrl, LightSense, MTRpwrn, Home15ctrl, Latch033ctrl, AS, TmpSlct, PhaseB_Encoder0, MSPReset, PhaseB_Encoder1, INTbus, 
LED1, Latch033FLG, Enc05ctrl, LED2, LED3, LED4, LED5, Home05FLG, TP12, TP21, PhaseA_Encoder0, PhaseA_Encoder1, PWM1, Home0, PWM2, Home1, TP26, PWM3, 
PAH0, PWM4, PAH1, RLS0, PWM5, RLS1, Latch133FLG, Enc15ctrl, GP_Motor0_0, GP_Motor0_1, PWM0_out, DIR0_out, TmpEn, PAL0, PAL1, Home15FLG, PBH0, RD, 
Enc05FLG, PBH1, PresEn, GPIO8, GPIO9, GP_Motor1_0, GP_Motor1_1, FLS0, PBL0, FLS1, PBL1, PWM1_out, DIR1_out, WR, GPIO10, Enc15FLG, SCLreset, PresSlct, 
DIR0, DIR1, Home05ctrl, Mclk, INT, SCLinc, MTRpwr, MReset, AD, I2CS
);
  inout SCL;
  input Brake0;
  input Brake1;
  output Latch133ctrl;
  input LightSense;
  output MTRpwrn;
  output Home15ctrl;
  output Latch033ctrl;
  input AS;
  output TmpSlct;
  input PhaseB_Encoder0;
  input MSPReset;
  input PhaseB_Encoder1;
  input INTbus;
  output LED1;
  input Latch033FLG;
  output Enc05ctrl;
  output LED2;
  output LED3;
  output LED4;
  output LED5;
  input Home05FLG;
  output TP12;
  output TP21;
  input PhaseA_Encoder0;
  input PhaseA_Encoder1;
  input PWM1;
  input Home0;
  input PWM2;
  input Home1;
  output TP26;
  input PWM3;
  output PAH0;
  input PWM4;
  output PAH1;
  input RLS0;
  input PWM5;
  input RLS1;
  input Latch133FLG;
  output Enc15ctrl;
  input GP_Motor0_0;
  output GP_Motor0_1;
  output PWM0_out;
  output DIR0_out;
  output TmpEn;
  output PAL0;
  output PAL1;
  input Home15FLG;
  output PBH0;
  input RD;
  input Enc05FLG;
  output PBH1;
  output PresEn;
  output GPIO8;
  output GPIO9;
  input GP_Motor1_0;
  output GP_Motor1_1;
  input FLS0;
  output PBL0;
  input FLS1;
  output PBL1;
  output PWM1_out;
  output DIR1_out;
  input WR;
  output GPIO10;
  input Enc15FLG;
  input SCLreset;
  output PresSlct;
  input DIR0;
  input DIR1;
  output Home05ctrl;
  input Mclk;
  output INT;
  input SCLinc;
  output MTRpwr;
  input MReset;
  inout [7 : 0] AD;
  input [5 : 0] I2CS;
  wire AS_IBUF_2229;
  wire Brake0_IBUF_2231;
  wire Brake1_IBUF_2233;
  wire DCOR0CNTHIGHr;
  wire DCOR0CNTLOWr;
  wire DCOR0THRESHIGHr;
  wire DCOR0THRESLOWr;
  wire DCOR1CNTHIGHr;
  wire DCOR1CNTLOWr;
  wire DCOR1THRESHIGHr;
  wire DCOR1THRESLOWr;
  wire DCORCONFIGr;
  wire DCORENCCTLw;
  wire DCORENCPWRr;
  wire DCORENCPWRw;
  wire DCORI2CCNTr;
  wire DCORIEw;
  wire DCORIFGr;
  wire DCORIFGw;
  wire DCORLIMITSr;
  wire DCORLINTr;
  wire DCOROUTw;
  wire DCORSENSORw;
  wire DIR0_out_OBUF_2256;
  wire DIR1_out_OBUF_2259;
  wire Enc05FLG_IBUF_2261;
  wire Enc05ctrl_OBUF_2263;
  wire Enc15FLG_IBUF_2265;
  wire Enc15ctrl_OBUF_2267;
  wire FLS0_IBUF_2269;
  wire FLS1_IBUF_2271;
  wire GPIO101_2273;
  wire GPIO10_OBUF_2274;
  wire GPIO8_OBUF_2276;
  wire GPIO91_2278;
  wire GPIO9_OBUF_2279;
  wire GP_Motor0_0_IBUF_2281;
  wire GP_Motor0_1_OBUF_2283;
  wire GP_Motor1_0_IBUF_2285;
  wire GP_Motor1_1_OBUF_2287;
  wire Home05FLG_IBUF_2290;
  wire Home05ctrl_OBUF_2292;
  wire Home0_IBUF_2293;
  wire Home15FLG_IBUF_2296;
  wire Home15ctrl_OBUF_2298;
  wire Home1_IBUF_2299;
  wire I2CS_0_IBUF_2306;
  wire I2CS_1_IBUF_2307;
  wire I2CS_2_IBUF_2308;
  wire I2CS_3_IBUF_2309;
  wire I2CS_4_IBUF_2310;
  wire I2CS_5_IBUF_2311;
  wire INT_OBUF_2313;
  wire INTbus_IBUF_2315;
  wire LED1_OBUF_2317;
  wire LED2_OBUF_2319;
  wire LED3_OBUF_2321;
  wire LED4_OBUF_2323;
  wire LED5_OBUF_2325;
  wire Latch033FLG_IBUF_2327;
  wire Latch033ctrl_OBUF_2329;
  wire Latch133FLG_IBUF_2331;
  wire Latch133ctrl_OBUF_2333;
  wire LightSense_IBUF_2335;
  wire MReset_IBUF_2337;
  wire MSPReset_IBUF_2339;
  wire MTRpwr_OBUF_2341;
  wire MTRpwrn_OBUF_2343;
  wire Mclk_IBUF_2345;
  wire N0;
  wire N1;
  wire N10;
  wire N11;
  wire N12;
  wire N13;
  wire N15;
  wire N16;
  wire N17;
  wire N19;
  wire N20;
  wire N21;
  wire N211;
  wire N22;
  wire N23;
  wire N24;
  wire N25;
  wire N26;
  wire N27;
  wire N3;
  wire N4;
  wire N5;
  wire N6;
  wire N7;
  wire N8;
  wire N9;
  wire NET2482;
  wire NET2493;
  wire NET2512;
  wire NET2528;
  wire NET2575;
  wire NET4826;
  wire PAH0_OBUF_2379;
  wire PAH1_OBUF_2381;
  wire PAL0_OBUF_2383;
  wire PAL1_OBUF_2385;
  wire PBH0_OBUF_2387;
  wire PBH1_OBUF_2389;
  wire PBL0_OBUF_2391;
  wire PBL1_OBUF_2393;
  wire PWM0_out_OBUF_2395;
  wire PWM1_IBUF_2397;
  wire PWM1_out_OBUF_2399;
  wire PWM2_IBUF_2401;
  wire PWM3_IBUF_2403;
  wire PWM4_IBUF_2405;
  wire PhaseA_Encoder0_IBUF_2408;
  wire PhaseA_Encoder1_IBUF_2410;
  wire PhaseB_Encoder0_IBUF_2412;
  wire PhaseB_Encoder1_IBUF_2414;
  wire PresEn_OBUF_2416;
  wire PresSlct_OBUF_2418;
  wire RD_IBUF_2420;
  wire RLS0_IBUF_2422;
  wire RLS1_IBUF_2424;
  wire Reset;
  wire SCL_IOBUFE_2427;
  wire SCLinc_IBUF_2429;
  wire SCLreset_IBUF_2431;
  wire SFDecomp_1;
  wire SFDecomp_11_2433;
  wire SFDecomp_12_2434;
  wire SFDecomp_2;
  wire SFDecomp_21_2436;
  wire SFDecomp_3;
  wire SFDecomp_31_2438;
  wire SFDecomp_32_2439;
  wire SFDecomp_33_2440;
  wire SFDecomp_4;
  wire SFDecomp_41_2442;
  wire TP12_OBUF_2444;
  wire TP21_OBUF_2446;
  wire TP26_OBUF_2448;
  wire TmpEn_OBUF_2450;
  wire TmpSlct_OBUF_2452;
  wire U11_Incdetect;
  wire U11_ResetDetect;
  wire U11_SCLdetect;
  wire \U11_U3_Maddsub_counterr_share0000_Mxor_Result<1>__xor0000 ;
  wire \U11_U3_Maddsub_counterr_share0000_Mxor_Result<2>__xor0000 ;
  wire \U11_U3_Maddsub_counterr_share0000_Mxor_Result<3>__xor0000 ;
  wire \U11_U3_Maddsub_counterr_share0000_Mxor_Result<4>__xor0000 ;
  wire \U11_U3_Maddsub_counterr_share0000_Mxor_Result<5>__xor0000 ;
  wire \U11_U3_Maddsub_counterr_share0000_Mxor_Result<5>__xor0001 ;
  wire U11_U3_Maddsub_counterr_share0000__or0000;
  wire U11_U3_Maddsub_counterr_share0000__or0001;
  wire U11_U3_Maddsub_counterr_share0000__or00011_2464;
  wire U11_U3_Maddsub_counterr_share0000__or00012_2465;
  wire U11_U3_Maddsub_counterr_share0000__or0002;
  wire U11_U3_Maddsub_counterr_share0000__or00021_2467;
  wire U11_U3_Maddsub_counterr_share0000__or00022_2468;
  wire U11_U3_Maddsub_counterr_share0000__or0003;
  wire U11_U3_Maddsub_counterr_share0000__or00031_2470;
  wire U11_U3_Maddsub_counterr_share0000__or00032_2471;
  wire U11_U3_Maddsub_counterr_share0000__or0004;
  wire U11_U3_Maddsub_counterr_share0000__or00041_2473;
  wire U11_U3_Maddsub_counterr_share0000__or00042_2474;
  wire U11_U3_Maddsub_counterr_share0000_or0000_xor0000;
  wire U11_U3_Maddsub_counterr_share0000_or0003_xor0000;
  wire U11_U3_SCLint_cmp_eq0000;
  wire U11_U3_SCLint_cmp_eq00001_2479;
  wire U11_U3_SCLint_cmp_eq00002_2480;
  wire \U11_U3_counterr_mux0000<0>1 ;
  wire \U11_U3_counterr_mux0000<0>11_2489 ;
  wire \U11_U3_counterr_mux0000<0>12_2490 ;
  wire \U11_U3_counterr_mux0000<1>1 ;
  wire \U11_U3_counterr_mux0000<1>11_2493 ;
  wire \U11_U3_counterr_mux0000<1>12_2494 ;
  wire \U11_U3_counterr_mux0000<2>1_2496 ;
  wire \U11_U3_counterr_mux0000<3>1 ;
  wire \U11_U3_counterr_mux0000<3>11_2499 ;
  wire \U11_U3_counterr_mux0000<3>12_2500 ;
  wire \U11_U3_counterr_mux0000<4>1 ;
  wire \U11_U3_counterr_mux0000<4>11_2503 ;
  wire \U11_U3_counterr_mux0000<4>12_2504 ;
  wire \U11_U3_counterr_mux0000<4>13_2505 ;
  wire \U11_U3_counterr_mux0000<4>14_2506 ;
  wire \U11_U3_counterr_mux0000<4>2 ;
  wire \U11_U3_counterr_mux0000<4>21_2508 ;
  wire \U11_U3_counterr_mux0000<4>22_2509 ;
  wire \U11_U3_counterr_mux0000<4>3_2510 ;
  wire \U11_U3_counterr_mux0000<4>4_2511 ;
  wire \U11_U3_counterr_mux0000<5>1 ;
  wire \U11_U3_counterr_mux0000<5>11_2514 ;
  wire \U11_U3_counterr_mux0000<5>111_2515 ;
  wire \U11_U3_counterr_mux0000<5>12_2516 ;
  wire \U11_U3_counterr_mux0000<5>121_2517 ;
  wire \U11_U3_counterr_mux0000<5>13 ;
  wire \U11_U3_counterr_mux0000<5>2_2519 ;
  wire \U11_U3_counterr_mux0000<5>3_2520 ;
  wire \U11_U3_counterr_mux0001[2] ;
  wire \U11_U3_counterr_mux0001<2>1_2522 ;
  wire \U11_U3_counterr_mux0001<2>2_2523 ;
  wire \U11_U3_counterr_mux0001[5] ;
  wire \U11_U3_counterr_mux0001<5>1 ;
  wire \U11_U3_counterr_mux0001<5>11_2526 ;
  wire \U11_U3_counterr_mux0001<5>12_2527 ;
  wire \U11_U3_counterr_mux0001<5>13_2528 ;
  wire \U11_U3_counterr_mux0001<5>14_2529 ;
  wire U11_U3_counterr_or00031_2531;
  wire U2_ADDR_in_Range;
  wire U2_ADDR_reg_0_0_not0000;
  wire U2_ADDR_reg_0__and0000;
  wire U2_ADDR_reg_0__or0000;
  wire U2_ADDR_reg_0__or00001_2543;
  wire U2_ADDR_reg_0__or00002_2544;
  wire U2_ADDR_reg_1__and0000;
  wire U2_ADDR_reg_2__and0000;
  wire U2_ADDR_reg_3__and0000;
  wire U2_ADDR_reg_4__and0000;
  wire U2_ADDR_reg_5__and0000;
  wire U2_ADDR_reg_6__and0000;
  wire U2_ADDR_reg_7__and0000;
  wire U2_ADDR_reg_and0000;
  wire U2_ADDR_reg_and00001_2567;
  wire U2_ADDR_reg_and00002_2568;
  wire U2_ADDR_reg_and00003_2569;
  wire U2_ADDR_reg_and0001;
  wire U2_ADDR_reg_and0002;
  wire U2_ADDR_reg_and00021_2572;
  wire U2_ADDR_reg_and00022_2573;
  wire U2_ADDR_reg_cmp_lt0000;
  wire \U2_ADDR_reg_mux0001<0>1_2576 ;
  wire \U2_ADDR_reg_mux0001<0>11_2577 ;
  wire \U2_ADDR_reg_mux0001<0>12_2578 ;
  wire \U2_ADDR_reg_mux0001<0>13_2579 ;
  wire \U2_ADDR_reg_mux0001<0>2_2580 ;
  wire \U2_ADDR_reg_mux0001<0>3_2581 ;
  wire \U2_ADDR_reg_mux0001<0>4_2582 ;
  wire \U2_ADDR_reg_mux0001<0>5_2583 ;
  wire \U2_ADDR_reg_mux0001<1>1_2585 ;
  wire \U2_ADDR_reg_mux0001<1>2_2586 ;
  wire \U2_ADDR_reg_mux0001<1>3_2587 ;
  wire \U2_ADDR_reg_mux0001<2>1_2589 ;
  wire \U2_ADDR_reg_mux0001<2>2_2590 ;
  wire \U2_ADDR_reg_mux0001<3>1_2592 ;
  wire \U2_ADDR_reg_mux0001<3>2_2593 ;
  wire \U2_ADDR_reg_mux0001<4>1_2595 ;
  wire \U2_ADDR_reg_mux0001<4>2_2596 ;
  wire \U2_ADDR_reg_mux0001<5>1_2598 ;
  wire \U2_ADDR_reg_mux0001<5>2_2599 ;
  wire \U2_ADDR_reg_mux0001<6>1_2601 ;
  wire \U2_ADDR_reg_mux0001<6>2_2602 ;
  wire \U2_ADDR_reg_mux0001<7>1_2604 ;
  wire \U2_ADDR_reg_mux0001<7>2_2605 ;
  wire U2_ASedge_2606;
  wire U2_ASleading;
  wire U2_AutoInc_2608;
  wire U2_AutoInc_and0000;
  wire U2_AutoInc_and00001_2610;
  wire U2_AutoInc_not0001;
  wire U2_Enable_AD;
  wire U2_Enable_AD1_2613;
  wire U2_Enable_AD2_2614;
  wire U2_Madd_ADDR_reg_addsub0000__and0000;
  wire U2_Madd_ADDR_reg_addsub0000__and0001;
  wire U2_Madd_ADDR_reg_addsub0000__and0002;
  wire U2_Madd_ADDR_reg_addsub0000__and0003;
  wire U2_Madd_ADDR_reg_addsub0000__and0004;
  wire U2_Madd_ADDR_reg_addsub0000__and0005;
  wire U2_Mcompar_ADDR_reg_cmp_lt0000_ALB;
  wire U2_Mcompar_ADDR_reg_cmp_lt0000_ALB1_2622;
  wire U2_WRRDedge_2627;
  wire U2_WRRDedge_and0000;
  wire WR_IBUF_2630;
  wire fBRK0;
  wire fBRK1;
  wire NLW_U1_TP_UNCONNECTED;
  wire NLW_U4_Enc033ctl_UNCONNECTED;
  wire NLW_U4_Enc033flg_UNCONNECTED;
  wire NLW_U4_Enc133ctl_UNCONNECTED;
  wire NLW_U4_Enc133flg_UNCONNECTED;
  wire [5 : 0] U11_U3_counterr;
  wire [5 : 0] U11_U3_counterr_mux0000;
  wire [5 : 0] U11_U3_counterr_share0000;
  wire [7 : 0] U2_ADDR_reg;
  wire [7 : 1] U2_ADDR_reg_addsub0000;
  wire [7 : 0] U2_ADDR_reg_mux0001;
  wire [3 : 3] U2_Mcompar_ADDR_reg_cmp_lt0000_ALRANDC;
  wire [7 : 5] U2_Mcompar_ADDR_reg_cmp_lt0000_CARRY_IN;
  wire [7 : 0] outDATA;
  GND   XST_GND (
    .G(SCL_IOBUFE_2427)
  );
  FDCE   U2_ADDR_reg_7 (
    .CE(U2_ADDR_reg_0__or0000),
    .CLR(SCL_IOBUFE_2427),
    .C(U2_ADDR_reg_0_0_not0000),
    .D(U2_ADDR_reg_7__and0000),
    .Q(U2_ADDR_reg[7])
  );
  FDCE   U2_ADDR_reg_6 (
    .CE(U2_ADDR_reg_0__or0000),
    .CLR(SCL_IOBUFE_2427),
    .C(U2_ADDR_reg_0_0_not0000),
    .D(U2_ADDR_reg_6__and0000),
    .Q(U2_ADDR_reg[6])
  );
  FDCE   U2_ADDR_reg_5 (
    .CE(U2_ADDR_reg_0__or0000),
    .CLR(SCL_IOBUFE_2427),
    .C(U2_ADDR_reg_0_0_not0000),
    .D(U2_ADDR_reg_5__and0000),
    .Q(U2_ADDR_reg[5])
  );
  FDCE   U2_ADDR_reg_4 (
    .CE(U2_ADDR_reg_0__or0000),
    .CLR(SCL_IOBUFE_2427),
    .C(U2_ADDR_reg_0_0_not0000),
    .D(U2_ADDR_reg_4__and0000),
    .Q(U2_ADDR_reg[4])
  );
  FDCE   U2_ADDR_reg_3 (
    .CE(U2_ADDR_reg_0__or0000),
    .CLR(SCL_IOBUFE_2427),
    .C(U2_ADDR_reg_0_0_not0000),
    .D(U2_ADDR_reg_3__and0000),
    .Q(U2_ADDR_reg[3])
  );
  FDCE   U2_ADDR_reg_2 (
    .CE(U2_ADDR_reg_0__or0000),
    .CLR(SCL_IOBUFE_2427),
    .C(U2_ADDR_reg_0_0_not0000),
    .D(U2_ADDR_reg_2__and0000),
    .Q(U2_ADDR_reg[2])
  );
  FDCE   U2_ADDR_reg_1 (
    .CE(U2_ADDR_reg_0__or0000),
    .CLR(SCL_IOBUFE_2427),
    .C(U2_ADDR_reg_0_0_not0000),
    .D(U2_ADDR_reg_1__and0000),
    .Q(U2_ADDR_reg[1])
  );
  FDCE   U2_ADDR_reg_0 (
    .CE(U2_ADDR_reg_0__or0000),
    .CLR(SCL_IOBUFE_2427),
    .C(U2_ADDR_reg_0_0_not0000),
    .D(U2_ADDR_reg_0__and0000),
    .Q(U2_ADDR_reg[0])
  );
  FDCE   U2_AutoInc (
    .CE(U2_AutoInc_and0000),
    .CLR(SCL_IOBUFE_2427),
    .C(U2_ADDR_reg_0_0_not0000),
    .D(U2_AutoInc_not0001),
    .Q(U2_AutoInc_2608)
  );
  FD   U2_ASedge (
    .C(U2_ADDR_reg_0_0_not0000),
    .D(AS_IBUF_2229),
    .Q(U2_ASedge_2606)
  );
  FD   U2_WRRDedge (
    .C(U2_ADDR_reg_0_0_not0000),
    .D(U2_WRRDedge_and0000),
    .Q(U2_WRRDedge_2627)
  );
  BUFE   U11_U3_outDATA_counterr_7 (
    .I(SCL_IOBUFE_2427),
    .E(DCORI2CCNTr),
    .O(outDATA[7])
  );
  BUFE   U11_U3_outDATA_counterr_6 (
    .I(SCL_IOBUFE_2427),
    .E(DCORI2CCNTr),
    .O(outDATA[6])
  );
  BUFE   U11_U3_outDATA_counterr_5 (
    .I(U11_U3_counterr[5]),
    .E(DCORI2CCNTr),
    .O(outDATA[5])
  );
  BUFE   U11_U3_outDATA_counterr_4 (
    .I(U11_U3_counterr[4]),
    .E(DCORI2CCNTr),
    .O(outDATA[4])
  );
  BUFE   U11_U3_outDATA_counterr_3 (
    .I(U11_U3_counterr[3]),
    .E(DCORI2CCNTr),
    .O(outDATA[3])
  );
  BUFE   U11_U3_outDATA_counterr_2 (
    .I(U11_U3_counterr[2]),
    .E(DCORI2CCNTr),
    .O(outDATA[2])
  );
  BUFE   U11_U3_outDATA_counterr_1 (
    .I(U11_U3_counterr[1]),
    .E(DCORI2CCNTr),
    .O(outDATA[1])
  );
  BUFE   U11_U3_outDATA_counterr_0 (
    .I(U11_U3_counterr[0]),
    .E(DCORI2CCNTr),
    .O(outDATA[0])
  );
  FD   U11_U3_counterr_0 (
    .C(U2_ADDR_reg_0_0_not0000),
    .D(U11_U3_counterr_mux0000[5]),
    .Q(U11_U3_counterr[0])
  );
  FD   U11_U3_counterr_1 (
    .C(U2_ADDR_reg_0_0_not0000),
    .D(U11_U3_counterr_mux0000[4]),
    .Q(U11_U3_counterr[1])
  );
  FD   U11_U3_counterr_2 (
    .C(U2_ADDR_reg_0_0_not0000),
    .D(U11_U3_counterr_mux0000[3]),
    .Q(U11_U3_counterr[2])
  );
  FD   U11_U3_counterr_3 (
    .C(U2_ADDR_reg_0_0_not0000),
    .D(U11_U3_counterr_mux0000[2]),
    .Q(U11_U3_counterr[3])
  );
  FD   U11_U3_counterr_4 (
    .C(U2_ADDR_reg_0_0_not0000),
    .D(U11_U3_counterr_mux0000[1]),
    .Q(U11_U3_counterr[4])
  );
  FD   U11_U3_counterr_5 (
    .C(U2_ADDR_reg_0_0_not0000),
    .D(U11_U3_counterr_mux0000[0]),
    .Q(U11_U3_counterr[5])
  );
  U21AddDecode   U12 (
    .DCORENCPWRr(DCORENCPWRr),
    .DCOR0CNTLOWr(DCOR0CNTLOWr),
    .DCORENCPWRw(DCORENCPWRw),
    .DCORENCCTLw(DCORENCCTLw),
    .DCOR0THRESLOWr(DCOR0THRESLOWr),
    .AS(AS_IBUF_2229),
    .DCOR0THRESHIGHr(DCOR0THRESHIGHr),
    .DCOR1CNTHIGHr(DCOR1CNTHIGHr),
    .DCORLINTr(DCORLINTr),
    .DCOR0CNTHIGHr(DCOR0CNTHIGHr),
    .DCOR1THRESHIGHr(DCOR1THRESHIGHr),
    .DCORLIMITSr(DCORLIMITSr),
    .DCORSENSORw(DCORSENSORw),
    .DCORCONFIGr(DCORCONFIGr),
    .DCORIFGr(DCORIFGr),
    .DCORIFGw(DCORIFGw),
    .RD(RD_IBUF_2420),
    .DCOROUTw(DCOROUTw),
    .DCORIEw(DCORIEw),
    .WR(WR_IBUF_2630),
    .DCOR1CNTLOWr(DCOR1CNTLOWr),
    .DCOR1THRESLOWr(DCOR1THRESLOWr),
    .DCORI2CCNTr(DCORI2CCNTr),
    .ADDR({U2_ADDR_reg[7], U2_ADDR_reg[6], U2_ADDR_reg[5], U2_ADDR_reg[4], U2_ADDR_reg[3], U2_ADDR_reg[2], U2_ADDR_reg[1], U2_ADDR_reg[0]})
  );
  Lswitch   U5 (
    .Brake0(Brake0_IBUF_2231),
    .Brake1(Brake1_IBUF_2233),
    .DCORLINTr(DCORLINTr),
    .Reset(Reset),
    .fBRK0(fBRK0),
    .fBRK1(fBRK1),
    .DCORLIMITSr(DCORLIMITSr),
    .Home0(Home0_IBUF_2293),
    .Home1(Home1_IBUF_2299),
    .RLS0(RLS0_IBUF_2422),
    .RLS1(RLS1_IBUF_2424),
    .DCORIFGw(DCORIFGw),
    .FLS0(FLS0_IBUF_2269),
    .FLS1(FLS1_IBUF_2271),
    .LSwitchInt(NET2575),
    .LIFG(N23),
    .DIR0(DIR0_out_OBUF_2256),
    .DIR1(DIR1_out_OBUF_2259),
    .Mclk(Mclk_IBUF_2345),
    .outDATA({outDATA[7], outDATA[6], outDATA[5], outDATA[4], outDATA[3], outDATA[2], outDATA[1], outDATA[0]})
  );
  I2CAddress   U6 (
    .DCORCONFIGr(DCORCONFIGr),
    .MotorIn0(GP_Motor0_0_IBUF_2281),
    .MotorIn1(GP_Motor1_0_IBUF_2285),
    .outDATA({outDATA[7], outDATA[6], outDATA[5], outDATA[4], outDATA[3], outDATA[2], outDATA[1], outDATA[0]}),
    .I2CS({I2CS_5_IBUF_2311, I2CS_4_IBUF_2310, I2CS_3_IBUF_2309, I2CS_2_IBUF_2308, I2CS_1_IBUF_2307, I2CS_0_IBUF_2306})
  );
  NegDetect   U11_U1 (
    .Line(SCLinc_IBUF_2429),
    .Ndetect(U11_Incdetect),
    .Mclk(Mclk_IBUF_2345)
  );
  NegDetect_INST_1   U11_U2 (
    .Line(N19),
    .Ndetect(U11_SCLdetect),
    .Mclk(Mclk_IBUF_2345)
  );
  NegDetect_INST_2   U11_U4 (
    .Line(SCLreset_IBUF_2431),
    .Ndetect(U11_ResetDetect),
    .Mclk(Mclk_IBUF_2345)
  );
  PWMcontrol   U7 (
    .Brake1(Brake0_IBUF_2231),
    .Brake2(Brake1_IBUF_2233),
    .fBRK1(fBRK0),
    .fBRK2(fBRK1),
    .PWM1(PWM1_IBUF_2397),
    .PWM2(PWM2_IBUF_2401),
    .PAH1(PAH0_OBUF_2379),
    .RLS0(RLS0_IBUF_2422),
    .PAH2(PAH1_OBUF_2381),
    .RLS1(RLS1_IBUF_2424),
    .PWM0_out(PWM0_out_OBUF_2395),
    .PAL1(PAL0_OBUF_2383),
    .PAL2(PAL1_OBUF_2385),
    .PBH1(PBH0_OBUF_2387),
    .PBH2(PBH1_OBUF_2389),
    .FLS0(FLS0_IBUF_2269),
    .FLS1(FLS1_IBUF_2271),
    .PBL1(PBL0_OBUF_2391),
    .PBL2(PBL1_OBUF_2393),
    .PWM1_out(PWM1_out_OBUF_2399),
    .HBRK1(fBRK0),
    .HBRK2(fBRK1),
    .DIR1(DIR0_out_OBUF_2256),
    .DIR2(DIR1_out_OBUF_2259),
    .MTRpwr(MTRpwr_OBUF_2341)
  );
  Interrupt   U3 (
    .PWRint(NET2528),
    .Reset(Reset),
    .I2Cint(TP12_OBUF_2444),
    .DCORIFGr(DCORIFGr),
    .Homed0(NET2482),
    .Homed1(NET2493),
    .BusInt(INTbus_IBUF_2315),
    .TP(TP21_OBUF_2446),
    .DCORIEw(DCORIEw),
    .Thres0(TP26_OBUF_2448),
    .Thres1(NET2512),
    .LSwitchInt(NET2575),
    .Mclk(Mclk_IBUF_2345),
    .INT(INT_OBUF_2313),
    .outDATA({outDATA[7], outDATA[6], outDATA[5], outDATA[4], outDATA[3], outDATA[2], outDATA[1], outDATA[0]}),
    .inDATA({N20, N211, N22, N23, N24, N25, N26, N27})
  );
  PWRreg   U4 (
    .DCORENCPWRr(DCORENCPWRr),
    .DCORENCPWRw(DCORENCPWRw),
    .PWRint(NET2528),
    .Hme05ctl(Home05ctrl_OBUF_2292),
    .Enc033ctl(NLW_U4_Enc033ctl_UNCONNECTED),
    .Hme033ctl(Latch033ctrl_OBUF_2329),
    .Reset(Reset),
    .Hme05flg(Home05FLG_IBUF_2290),
    .Enc05ctl(Enc05ctrl_OBUF_2263),
    .Enc033flg(NLW_U4_Enc033flg_UNCONNECTED),
    .Hme033flg(Latch033FLG_IBUF_2327),
    .Hme15ctl(Home15ctrl_OBUF_2298),
    .Enc133ctl(NLW_U4_Enc133ctl_UNCONNECTED),
    .Hme133ctl(Latch133ctrl_OBUF_2333),
    .DCORIFGr(DCORIFGr),
    .DCORIFGw(DCORIFGw),
    .Enc05flg(Enc05FLG_IBUF_2261),
    .Hme15flg(Home15FLG_IBUF_2296),
    .Enc133flg(NLW_U4_Enc133flg_UNCONNECTED),
    .Hme133flg(Latch133FLG_IBUF_2331),
    .Enc15ctl(Enc15ctrl_OBUF_2267),
    .Enc15flg(Enc15FLG_IBUF_2265),
    .Mclk(Mclk_IBUF_2345),
    .outDATA({outDATA[7], outDATA[6], outDATA[5], outDATA[4], outDATA[3], outDATA[2], outDATA[1], outDATA[0]}),
    .inDATA({N20, N211, N22, N23, N24, N25, N26, N27})
  );
  Sensor   U8 (
    .TmpSlct(TmpSlct_OBUF_2452),
    .Reset(Reset),
    .DCORSENSORw(DCORSENSORw),
    .TmpEn(TmpEn_OBUF_2450),
    .PresEn(PresEn_OBUF_2416),
    .PresSlct(PresSlct_OBUF_2418),
    .Mclk(Mclk_IBUF_2345),
    .MReset(MReset_IBUF_2337),
    .inDATA({N24, N25, N26, N27})
  );
  MISCouts   U9 (
    .LightSense(LightSense_IBUF_2335),
    .MTRpwrn(MTRpwrn_OBUF_2343),
    .LED1(LED1_OBUF_2317),
    .LED2(LED2_OBUF_2319),
    .LED3(LED3_OBUF_2321),
    .LED4(LED4_OBUF_2323),
    .LED5(LED5_OBUF_2325),
    .Reset(Reset),
    .GP_Motor0_1(GP_Motor0_1_OBUF_2283),
    .GP_Motor1_1(GP_Motor1_1_OBUF_2287),
    .DCOROUTw(DCOROUTw),
    .Mclk(Mclk_IBUF_2345),
    .MTRpwr(MTRpwr_OBUF_2341),
    .MReset(MReset_IBUF_2337),
    .inDATA({N20, N211, N22, N23, N24, N25, N26, N27})
  );
  Servos   U1 (
    .DCOR0CNTLOWr(DCOR0CNTLOWr),
    .DCORENCCTLw(DCORENCCTLw),
    .DCOR0THRESLOWr(DCOR0THRESLOWr),
    .PhaseB_Encoder0(PhaseB_Encoder0_IBUF_2412),
    .PhaseB_Encoder1(PhaseB_Encoder1_IBUF_2414),
    .DCOR0THRESHIGHr(DCOR0THRESHIGHr),
    .DCOR1CNTHIGHr(DCOR1CNTHIGHr),
    .Reset(Reset),
    .DCOR0CNTHIGHr(DCOR0CNTHIGHr),
    .DCOR1THRESHIGHr(DCOR1THRESHIGHr),
    .PhaseA_Encoder0(PhaseA_Encoder0_IBUF_2408),
    .PhaseA_Encoder1(PhaseA_Encoder1_IBUF_2410),
    .DCORIFGr(DCORIFGr),
    .Hfound0(NET2482),
    .Hfound1(NET2493),
    .DCORIFGw(DCORIFGw),
    .MotorIn0(GP_Motor0_0_IBUF_2281),
    .Motorin1(GP_Motor1_0_IBUF_2285),
    .TP(NLW_U1_TP_UNCONNECTED),
    .Home_Encoder0(Home0_IBUF_2293),
    .Home_Encoder1(Home1_IBUF_2299),
    .DCOR1CNTLOWr(DCOR1CNTLOWr),
    .ASleading(NET4826),
    .Mclk(Mclk_IBUF_2345),
    .DCOR1THRESLOWr(DCOR1THRESLOWr),
    .Tfound0(TP26_OBUF_2448),
    .Tfound1(NET2512),
    .outDATA({outDATA[7], outDATA[6], outDATA[5], outDATA[4], outDATA[3], outDATA[2], outDATA[1], outDATA[0]}),
    .inDATA({N20, N211, N22, N23, N24, N25, N26, N27})
  );
  INV   Reset1 (
    .I(MSPReset_IBUF_2339),
    .O(Reset)
  );
  INV   GPIO91 (
    .I(TmpEn_OBUF_2450),
    .O(GPIO91_2278)
  );
  AND2   GPIO92 (
    .I0(PWM3_IBUF_2403),
    .I1(GPIO91_2278),
    .O(GPIO9_OBUF_2279)
  );
  INV   GPIO101 (
    .I(TmpEn_OBUF_2450),
    .O(GPIO101_2273)
  );
  AND2   GPIO102 (
    .I0(PWM4_IBUF_2405),
    .I1(GPIO101_2273),
    .O(GPIO10_OBUF_2274)
  );
  AND2   U2_ADDR_reg_7__and00001 (
    .I0(MSPReset_IBUF_2339),
    .I1(U2_ADDR_reg_mux0001[7]),
    .O(U2_ADDR_reg_7__and0000)
  );
  AND2   U2_ADDR_reg_6__and00001 (
    .I0(MSPReset_IBUF_2339),
    .I1(U2_ADDR_reg_mux0001[6]),
    .O(U2_ADDR_reg_6__and0000)
  );
  AND2   U2_ADDR_reg_5__and00001 (
    .I0(MSPReset_IBUF_2339),
    .I1(U2_ADDR_reg_mux0001[5]),
    .O(U2_ADDR_reg_5__and0000)
  );
  AND2   U2_ADDR_reg_4__and00001 (
    .I0(MSPReset_IBUF_2339),
    .I1(U2_ADDR_reg_mux0001[4]),
    .O(U2_ADDR_reg_4__and0000)
  );
  AND2   U2_ADDR_reg_3__and00001 (
    .I0(MSPReset_IBUF_2339),
    .I1(U2_ADDR_reg_mux0001[3]),
    .O(U2_ADDR_reg_3__and0000)
  );
  AND2   U2_ADDR_reg_2__and00001 (
    .I0(MSPReset_IBUF_2339),
    .I1(U2_ADDR_reg_mux0001[2]),
    .O(U2_ADDR_reg_2__and0000)
  );
  AND2   U2_ADDR_reg_1__and00001 (
    .I0(MSPReset_IBUF_2339),
    .I1(U2_ADDR_reg_mux0001[1]),
    .O(U2_ADDR_reg_1__and0000)
  );
  INV   U2_ADDR_reg_0__or00001 (
    .I(U2_ADDR_reg_and0002),
    .O(U2_ADDR_reg_0__or00001_2543)
  );
  INV   U2_ADDR_reg_0__or00002 (
    .I(MSPReset_IBUF_2339),
    .O(U2_ADDR_reg_0__or00002_2544)
  );
  OR2   U2_ADDR_reg_0__or00003 (
    .I0(U2_ADDR_reg_0__or00001_2543),
    .I1(U2_ADDR_reg_0__or00002_2544),
    .O(U2_ADDR_reg_0__or0000)
  );
  AND2   U2_ADDR_reg_0__and00001 (
    .I0(MSPReset_IBUF_2339),
    .I1(U2_ADDR_reg_mux0001[0]),
    .O(U2_ADDR_reg_0__and0000)
  );
  AND2   U2_Madd_ADDR_reg_addsub0000__and00001 (
    .I0(U2_ADDR_reg[1]),
    .I1(U2_ADDR_reg[0]),
    .O(U2_Madd_ADDR_reg_addsub0000__and0000)
  );
  AND2   U2_Madd_ADDR_reg_addsub0000__and00011 (
    .I0(U2_ADDR_reg[2]),
    .I1(U2_Madd_ADDR_reg_addsub0000__and0000),
    .O(U2_Madd_ADDR_reg_addsub0000__and0001)
  );
  AND2   U2_Madd_ADDR_reg_addsub0000__and00021 (
    .I0(U2_ADDR_reg[3]),
    .I1(U2_Madd_ADDR_reg_addsub0000__and0001),
    .O(U2_Madd_ADDR_reg_addsub0000__and0002)
  );
  AND2   U2_Madd_ADDR_reg_addsub0000__and00031 (
    .I0(U2_ADDR_reg[4]),
    .I1(U2_Madd_ADDR_reg_addsub0000__and0002),
    .O(U2_Madd_ADDR_reg_addsub0000__and0003)
  );
  AND2   U2_Madd_ADDR_reg_addsub0000__and00041 (
    .I0(U2_ADDR_reg[5]),
    .I1(U2_Madd_ADDR_reg_addsub0000__and0003),
    .O(U2_Madd_ADDR_reg_addsub0000__and0004)
  );
  AND2   U2_Madd_ADDR_reg_addsub0000__and00051 (
    .I0(U2_ADDR_reg[6]),
    .I1(U2_Madd_ADDR_reg_addsub0000__and0004),
    .O(U2_Madd_ADDR_reg_addsub0000__and0005)
  );
  AND4   \U2_Mcompar_ADDR_reg_cmp_lt0000_ALRANDC<3>1  (
    .I0(U2_ADDR_reg[3]),
    .I1(U2_ADDR_reg[2]),
    .I2(U2_ADDR_reg[1]),
    .I3(U2_ADDR_reg[0]),
    .O(U2_Mcompar_ADDR_reg_cmp_lt0000_ALRANDC[3])
  );
  OR2   \U2_Mcompar_ADDR_reg_cmp_lt0000_CARRY_IN<5>1  (
    .I0(U2_Mcompar_ADDR_reg_cmp_lt0000_ALRANDC[3]),
    .I1(U2_ADDR_reg[4]),
    .O(U2_Mcompar_ADDR_reg_cmp_lt0000_CARRY_IN[5])
  );
  OR2   \U2_Mcompar_ADDR_reg_cmp_lt0000_CARRY_IN<6>1  (
    .I0(U2_Mcompar_ADDR_reg_cmp_lt0000_CARRY_IN[5]),
    .I1(U2_ADDR_reg[5]),
    .O(U2_Mcompar_ADDR_reg_cmp_lt0000_CARRY_IN[6])
  );
  OR2   \U2_Mcompar_ADDR_reg_cmp_lt0000_CARRY_IN<7>1  (
    .I0(U2_Mcompar_ADDR_reg_cmp_lt0000_CARRY_IN[6]),
    .I1(U2_ADDR_reg[6]),
    .O(U2_Mcompar_ADDR_reg_cmp_lt0000_CARRY_IN[7])
  );
  INV   U2_Mcompar_ADDR_reg_cmp_lt0000_ALB1 (
    .I(U2_ADDR_reg[7]),
    .O(U2_Mcompar_ADDR_reg_cmp_lt0000_ALB)
  );
  INV   U2_Mcompar_ADDR_reg_cmp_lt0000_ALB2 (
    .I(U2_Mcompar_ADDR_reg_cmp_lt0000_CARRY_IN[7]),
    .O(U2_Mcompar_ADDR_reg_cmp_lt0000_ALB1_2622)
  );
  AND2   U2_Mcompar_ADDR_reg_cmp_lt0000_ALB3 (
    .I0(U2_Mcompar_ADDR_reg_cmp_lt0000_ALB),
    .I1(U2_Mcompar_ADDR_reg_cmp_lt0000_ALB1_2622),
    .O(U2_ADDR_reg_cmp_lt0000)
  );
  INV   U2_AutoInc_not00011 (
    .I(AS_IBUF_2229),
    .O(U2_AutoInc_not0001)
  );
  INV   U2_ADDR_reg_and00021 (
    .I(U2_ADDR_reg_and0000),
    .O(U2_ADDR_reg_and00021_2572)
  );
  INV   U2_ADDR_reg_and00022 (
    .I(U2_ADDR_reg_and0001),
    .O(U2_ADDR_reg_and00022_2573)
  );
  AND2   U2_ADDR_reg_and00023 (
    .I0(U2_ADDR_reg_and00021_2572),
    .I1(U2_ADDR_reg_and00022_2573),
    .O(U2_ADDR_reg_and0002)
  );
  INV   U2_AutoInc_and00001 (
    .I(U2_WRRDedge_and0000),
    .O(U2_AutoInc_and00001_2610)
  );
  AND2   U2_AutoInc_and00002 (
    .I0(U2_WRRDedge_2627),
    .I1(U2_AutoInc_and00001_2610),
    .O(U2_AutoInc_and0000)
  );
  INV   U2_ASleading1 (
    .I(AS_IBUF_2229),
    .O(U2_ASleading)
  );
  AND2   U2_ASleading2 (
    .I0(U2_ASedge_2606),
    .I1(U2_ASleading),
    .O(NET4826)
  );
  AND2   U2_Enable_AD1 (
    .I0(U2_ADDR_in_Range),
    .I1(WR_IBUF_2630),
    .O(U2_Enable_AD1_2613)
  );
  INV   U2_Enable_AD2 (
    .I(RD_IBUF_2420),
    .O(U2_Enable_AD2_2614)
  );
  AND2   U2_Enable_AD3 (
    .I0(U2_Enable_AD1_2613),
    .I1(U2_Enable_AD2_2614),
    .O(U2_Enable_AD)
  );
  INV   U11_U3_SCLint_cmp_eq00001 (
    .I(U11_U3_counterr[4]),
    .O(U11_U3_SCLint_cmp_eq0000)
  );
  INV   U11_U3_SCLint_cmp_eq00002 (
    .I(U11_U3_counterr[3]),
    .O(U11_U3_SCLint_cmp_eq00001_2479)
  );
  INV   U11_U3_SCLint_cmp_eq00003 (
    .I(U11_U3_counterr[5]),
    .O(U11_U3_SCLint_cmp_eq00002_2480)
  );
  AND4   U11_U3_SCLint_cmp_eq00004 (
    .I0(SFDecomp_3),
    .I1(U11_U3_SCLint_cmp_eq0000),
    .I2(U11_U3_SCLint_cmp_eq00001_2479),
    .I3(U11_U3_SCLint_cmp_eq00002_2480),
    .O(TP12_OBUF_2444)
  );
  INV   U2_ADDR_reg_0_0_not00001 (
    .I(Mclk_IBUF_2345),
    .O(U2_ADDR_reg_0_0_not0000)
  );
  OR2   \U11_U3_counterr_mux0001<2>1  (
    .I0(SCLreset_IBUF_2431),
    .I1(U11_Incdetect),
    .O(\U11_U3_counterr_mux0001<2>1_2522 )
  );
  INV   \U11_U3_counterr_mux0001<2>2  (
    .I(U11_SCLdetect),
    .O(\U11_U3_counterr_mux0001<2>2_2523 )
  );
  OR2   \U11_U3_counterr_mux0001<2>3  (
    .I0(\U11_U3_counterr_mux0001<2>1_2522 ),
    .I1(\U11_U3_counterr_mux0001<2>2_2523 ),
    .O(\U11_U3_counterr_mux0001[2] )
  );
  AND2   \U11_U3_counterr_mux0000<5>2  (
    .I0(SCLinc_IBUF_2429),
    .I1(SCLreset_IBUF_2431),
    .O(\U11_U3_counterr_mux0000<5>1 )
  );
  INV   \U11_U3_counterr_mux0000<5>3  (
    .I(SCLreset_IBUF_2431),
    .O(\U11_U3_counterr_mux0000<5>2_2519 )
  );
  AND2   \U11_U3_counterr_mux0000<5>4  (
    .I0(N1),
    .I1(\U11_U3_counterr_mux0000<5>2_2519 ),
    .O(\U11_U3_counterr_mux0000<5>3_2520 )
  );
  OR2   \U11_U3_counterr_mux0000<5>5  (
    .I0(\U11_U3_counterr_mux0000<5>1 ),
    .I1(\U11_U3_counterr_mux0000<5>3_2520 ),
    .O(U11_U3_counterr_mux0000[5])
  );
  INV   \U11_U3_counterr_mux0001<5>2  (
    .I(SCLreset_IBUF_2431),
    .O(\U11_U3_counterr_mux0001<5>1 )
  );
  AND2   \U11_U3_counterr_mux0001<5>3  (
    .I0(N21),
    .I1(\U11_U3_counterr_mux0001<5>1 ),
    .O(\U11_U3_counterr_mux0001[5] )
  );
  OR2   U11_U3_Maddsub_counterr_share0000__or000011 (
    .I0(\U11_U3_Maddsub_counterr_share0000_Mxor_Result<5>__xor0001 ),
    .I1(U11_U3_Maddsub_counterr_share0000_or0000_xor0000),
    .O(N3)
  );
  AND2   U11_U3_Maddsub_counterr_share0000__or00001 (
    .I0(U11_U3_counterr[0]),
    .I1(N3),
    .O(U11_U3_Maddsub_counterr_share0000__or0000)
  );
  OR2   U11_U3_Maddsub_counterr_share0000__or000111 (
    .I0(U11_U3_Maddsub_counterr_share0000__or0000),
    .I1(\U11_U3_Maddsub_counterr_share0000_Mxor_Result<5>__xor0001 ),
    .O(N4)
  );
  AND2   U11_U3_Maddsub_counterr_share0000__or00011 (
    .I0(U11_U3_Maddsub_counterr_share0000__or0000),
    .I1(\U11_U3_Maddsub_counterr_share0000_Mxor_Result<5>__xor0001 ),
    .O(U11_U3_Maddsub_counterr_share0000__or00011_2464)
  );
  AND2   U11_U3_Maddsub_counterr_share0000__or00012 (
    .I0(U11_U3_counterr[1]),
    .I1(N4),
    .O(U11_U3_Maddsub_counterr_share0000__or00012_2465)
  );
  OR2   U11_U3_Maddsub_counterr_share0000__or00013 (
    .I0(U11_U3_Maddsub_counterr_share0000__or00011_2464),
    .I1(U11_U3_Maddsub_counterr_share0000__or00012_2465),
    .O(U11_U3_Maddsub_counterr_share0000__or0001)
  );
  OR2   U11_U3_Maddsub_counterr_share0000__or000211 (
    .I0(U11_U3_Maddsub_counterr_share0000__or0001),
    .I1(\U11_U3_Maddsub_counterr_share0000_Mxor_Result<5>__xor0001 ),
    .O(N5)
  );
  AND2   U11_U3_Maddsub_counterr_share0000__or00021 (
    .I0(U11_U3_Maddsub_counterr_share0000__or0001),
    .I1(\U11_U3_Maddsub_counterr_share0000_Mxor_Result<5>__xor0001 ),
    .O(U11_U3_Maddsub_counterr_share0000__or00021_2467)
  );
  AND2   U11_U3_Maddsub_counterr_share0000__or00022 (
    .I0(U11_U3_counterr[2]),
    .I1(N5),
    .O(U11_U3_Maddsub_counterr_share0000__or00022_2468)
  );
  OR2   U11_U3_Maddsub_counterr_share0000__or00023 (
    .I0(U11_U3_Maddsub_counterr_share0000__or00021_2467),
    .I1(U11_U3_Maddsub_counterr_share0000__or00022_2468),
    .O(U11_U3_Maddsub_counterr_share0000__or0002)
  );
  OR2   U11_U3_Maddsub_counterr_share0000__or000311 (
    .I0(U11_U3_Maddsub_counterr_share0000__or0002),
    .I1(U11_U3_Maddsub_counterr_share0000_or0003_xor0000),
    .O(N6)
  );
  AND2   U11_U3_Maddsub_counterr_share0000__or00031 (
    .I0(U11_U3_Maddsub_counterr_share0000__or0002),
    .I1(U11_U3_Maddsub_counterr_share0000_or0003_xor0000),
    .O(U11_U3_Maddsub_counterr_share0000__or00031_2470)
  );
  AND2   U11_U3_Maddsub_counterr_share0000__or00032 (
    .I0(U11_U3_counterr[3]),
    .I1(N6),
    .O(U11_U3_Maddsub_counterr_share0000__or00032_2471)
  );
  OR2   U11_U3_Maddsub_counterr_share0000__or00033 (
    .I0(U11_U3_Maddsub_counterr_share0000__or00031_2470),
    .I1(U11_U3_Maddsub_counterr_share0000__or00032_2471),
    .O(U11_U3_Maddsub_counterr_share0000__or0003)
  );
  OR2   U11_U3_Maddsub_counterr_share0000__or000411 (
    .I0(U11_U3_Maddsub_counterr_share0000__or0003),
    .I1(\U11_U3_Maddsub_counterr_share0000_Mxor_Result<5>__xor0001 ),
    .O(N7)
  );
  AND2   U11_U3_Maddsub_counterr_share0000__or00041 (
    .I0(U11_U3_Maddsub_counterr_share0000__or0003),
    .I1(\U11_U3_Maddsub_counterr_share0000_Mxor_Result<5>__xor0001 ),
    .O(U11_U3_Maddsub_counterr_share0000__or00041_2473)
  );
  AND2   U11_U3_Maddsub_counterr_share0000__or00042 (
    .I0(U11_U3_counterr[4]),
    .I1(N7),
    .O(U11_U3_Maddsub_counterr_share0000__or00042_2474)
  );
  OR2   U11_U3_Maddsub_counterr_share0000__or00043 (
    .I0(U11_U3_Maddsub_counterr_share0000__or00041_2473),
    .I1(U11_U3_Maddsub_counterr_share0000__or00042_2474),
    .O(U11_U3_Maddsub_counterr_share0000__or0004)
  );
  INV   \U11_U3_counterr_mux0001<5>111  (
    .I(U11_ResetDetect),
    .O(\U11_U3_counterr_mux0001<5>11_2526 )
  );
  OR2   \U11_U3_counterr_mux0001<5>112  (
    .I0(SCLinc_IBUF_2429),
    .I1(\U11_U3_counterr_mux0001<5>11_2526 ),
    .O(N8)
  );
  INV   \U11_U3_counterr_mux0000<0>2  (
    .I(SCLreset_IBUF_2431),
    .O(\U11_U3_counterr_mux0000<0>1 )
  );
  AND2   \U11_U3_counterr_mux0000<0>3  (
    .I0(N9),
    .I1(\U11_U3_counterr_mux0000<0>1 ),
    .O(U11_U3_counterr_mux0000[0])
  );
  INV   \U11_U3_counterr_mux0000<1>2  (
    .I(SCLreset_IBUF_2431),
    .O(\U11_U3_counterr_mux0000<1>1 )
  );
  AND2   \U11_U3_counterr_mux0000<1>3  (
    .I0(N10),
    .I1(\U11_U3_counterr_mux0000<1>1 ),
    .O(U11_U3_counterr_mux0000[1])
  );
  INV   \U11_U3_counterr_mux0000<3>2  (
    .I(SCLreset_IBUF_2431),
    .O(\U11_U3_counterr_mux0000<3>1 )
  );
  AND2   \U11_U3_counterr_mux0000<3>3  (
    .I0(N11),
    .I1(\U11_U3_counterr_mux0000<3>1 ),
    .O(U11_U3_counterr_mux0000[3])
  );
  INV   \U11_U3_counterr_mux0000<4>3  (
    .I(SCLinc_IBUF_2429),
    .O(\U11_U3_counterr_mux0000<4>1 )
  );
  INV   \U11_U3_counterr_mux0000<4>4  (
    .I(SCLreset_IBUF_2431),
    .O(\U11_U3_counterr_mux0000<4>2 )
  );
  AND2   \U11_U3_counterr_mux0000<4>5  (
    .I0(SCLreset_IBUF_2431),
    .I1(\U11_U3_counterr_mux0000<4>1 ),
    .O(\U11_U3_counterr_mux0000<4>3_2510 )
  );
  AND2   \U11_U3_counterr_mux0000<4>6  (
    .I0(N12),
    .I1(\U11_U3_counterr_mux0000<4>2 ),
    .O(\U11_U3_counterr_mux0000<4>4_2511 )
  );
  OR2   \U11_U3_counterr_mux0000<4>7  (
    .I0(\U11_U3_counterr_mux0000<4>3_2510 ),
    .I1(\U11_U3_counterr_mux0000<4>4_2511 ),
    .O(U11_U3_counterr_mux0000[4])
  );
  INV   \U11_U3_counterr_mux0000<5>111  (
    .I(SCLinc_IBUF_2429),
    .O(\U11_U3_counterr_mux0000<5>11_2514 )
  );
  AND2   \U11_U3_counterr_mux0000<5>112  (
    .I0(U11_ResetDetect),
    .I1(\U11_U3_counterr_mux0000<5>11_2514 ),
    .O(\U11_U3_counterr_mux0000<5>111_2515 )
  );
  OR2   \U11_U3_counterr_mux0000<5>113  (
    .I0(U11_U3_counterr_share0000[0]),
    .I1(\U11_U3_counterr_mux0000<5>111_2515 ),
    .O(N13)
  );
  INV   \U2_ADDR_reg_mux0001<0>11  (
    .I(U2_ADDR_reg[6]),
    .O(\U2_ADDR_reg_mux0001<0>1_2576 )
  );
  INV   \U2_ADDR_reg_mux0001<0>12  (
    .I(U2_ADDR_reg[4]),
    .O(\U2_ADDR_reg_mux0001<0>11_2577 )
  );
  INV   \U2_ADDR_reg_mux0001<0>13  (
    .I(U2_ADDR_reg[5]),
    .O(\U2_ADDR_reg_mux0001<0>12_2578 )
  );
  INV   \U2_ADDR_reg_mux0001<0>14  (
    .I(U2_ADDR_reg[7]),
    .O(\U2_ADDR_reg_mux0001<0>13_2579 )
  );
  AND4   \U2_ADDR_reg_mux0001<0>15  (
    .I0(\U2_ADDR_reg_mux0001<0>1_2576 ),
    .I1(\U2_ADDR_reg_mux0001<0>11_2577 ),
    .I2(\U2_ADDR_reg_mux0001<0>12_2578 ),
    .I3(\U2_ADDR_reg_mux0001<0>13_2579 ),
    .O(U2_ADDR_in_Range)
  );
  AND2   \U2_ADDR_reg_mux0001<0>1  (
    .I0(N27),
    .I1(U2_ADDR_reg_and0001),
    .O(\U2_ADDR_reg_mux0001<0>2_2580 )
  );
  INV   \U2_ADDR_reg_mux0001<0>2  (
    .I(U2_ADDR_reg_and0001),
    .O(\U2_ADDR_reg_mux0001<0>3_2581 )
  );
  INV   \U2_ADDR_reg_mux0001<0>3  (
    .I(U2_ADDR_reg[0]),
    .O(\U2_ADDR_reg_mux0001<0>4_2582 )
  );
  AND3   \U2_ADDR_reg_mux0001<0>4  (
    .I0(\U2_ADDR_reg_mux0001<0>3_2581 ),
    .I1(U2_ADDR_in_Range),
    .I2(\U2_ADDR_reg_mux0001<0>4_2582 ),
    .O(\U2_ADDR_reg_mux0001<0>5_2583 )
  );
  OR2   \U2_ADDR_reg_mux0001<0>5  (
    .I0(\U2_ADDR_reg_mux0001<0>2_2580 ),
    .I1(\U2_ADDR_reg_mux0001<0>5_2583 ),
    .O(U2_ADDR_reg_mux0001[0])
  );
  INV   \U2_ADDR_reg_mux0001<1>11  (
    .I(U2_ADDR_reg_and0001),
    .O(\U2_ADDR_reg_mux0001<1>1_2585 )
  );
  AND2   \U2_ADDR_reg_mux0001<1>12  (
    .I0(U2_ADDR_reg_cmp_lt0000),
    .I1(\U2_ADDR_reg_mux0001<1>1_2585 ),
    .O(N15)
  );
  AND2   \U2_ADDR_reg_mux0001<1>1  (
    .I0(N26),
    .I1(U2_ADDR_reg_and0001),
    .O(\U2_ADDR_reg_mux0001<1>2_2586 )
  );
  AND2   \U2_ADDR_reg_mux0001<1>2  (
    .I0(U2_ADDR_reg_addsub0000[1]),
    .I1(N15),
    .O(\U2_ADDR_reg_mux0001<1>3_2587 )
  );
  OR2   \U2_ADDR_reg_mux0001<1>3  (
    .I0(\U2_ADDR_reg_mux0001<1>2_2586 ),
    .I1(\U2_ADDR_reg_mux0001<1>3_2587 ),
    .O(U2_ADDR_reg_mux0001[1])
  );
  AND2   \U2_ADDR_reg_mux0001<2>1  (
    .I0(N25),
    .I1(U2_ADDR_reg_and0001),
    .O(\U2_ADDR_reg_mux0001<2>1_2589 )
  );
  AND2   \U2_ADDR_reg_mux0001<2>2  (
    .I0(U2_ADDR_reg_addsub0000[2]),
    .I1(N15),
    .O(\U2_ADDR_reg_mux0001<2>2_2590 )
  );
  OR2   \U2_ADDR_reg_mux0001<2>3  (
    .I0(\U2_ADDR_reg_mux0001<2>1_2589 ),
    .I1(\U2_ADDR_reg_mux0001<2>2_2590 ),
    .O(U2_ADDR_reg_mux0001[2])
  );
  AND2   \U2_ADDR_reg_mux0001<3>1  (
    .I0(N24),
    .I1(U2_ADDR_reg_and0001),
    .O(\U2_ADDR_reg_mux0001<3>1_2592 )
  );
  AND2   \U2_ADDR_reg_mux0001<3>2  (
    .I0(U2_ADDR_reg_addsub0000[3]),
    .I1(N15),
    .O(\U2_ADDR_reg_mux0001<3>2_2593 )
  );
  OR2   \U2_ADDR_reg_mux0001<3>3  (
    .I0(\U2_ADDR_reg_mux0001<3>1_2592 ),
    .I1(\U2_ADDR_reg_mux0001<3>2_2593 ),
    .O(U2_ADDR_reg_mux0001[3])
  );
  AND2   \U2_ADDR_reg_mux0001<4>1  (
    .I0(N23),
    .I1(U2_ADDR_reg_and0001),
    .O(\U2_ADDR_reg_mux0001<4>1_2595 )
  );
  AND2   \U2_ADDR_reg_mux0001<4>2  (
    .I0(U2_ADDR_reg_addsub0000[4]),
    .I1(N15),
    .O(\U2_ADDR_reg_mux0001<4>2_2596 )
  );
  OR2   \U2_ADDR_reg_mux0001<4>3  (
    .I0(\U2_ADDR_reg_mux0001<4>1_2595 ),
    .I1(\U2_ADDR_reg_mux0001<4>2_2596 ),
    .O(U2_ADDR_reg_mux0001[4])
  );
  AND2   \U2_ADDR_reg_mux0001<5>1  (
    .I0(N22),
    .I1(U2_ADDR_reg_and0001),
    .O(\U2_ADDR_reg_mux0001<5>1_2598 )
  );
  AND2   \U2_ADDR_reg_mux0001<5>2  (
    .I0(U2_ADDR_reg_addsub0000[5]),
    .I1(N15),
    .O(\U2_ADDR_reg_mux0001<5>2_2599 )
  );
  OR2   \U2_ADDR_reg_mux0001<5>3  (
    .I0(\U2_ADDR_reg_mux0001<5>1_2598 ),
    .I1(\U2_ADDR_reg_mux0001<5>2_2599 ),
    .O(U2_ADDR_reg_mux0001[5])
  );
  AND2   \U2_ADDR_reg_mux0001<6>1  (
    .I0(N211),
    .I1(U2_ADDR_reg_and0001),
    .O(\U2_ADDR_reg_mux0001<6>1_2601 )
  );
  AND2   \U2_ADDR_reg_mux0001<6>2  (
    .I0(U2_ADDR_reg_addsub0000[6]),
    .I1(N15),
    .O(\U2_ADDR_reg_mux0001<6>2_2602 )
  );
  OR2   \U2_ADDR_reg_mux0001<6>3  (
    .I0(\U2_ADDR_reg_mux0001<6>1_2601 ),
    .I1(\U2_ADDR_reg_mux0001<6>2_2602 ),
    .O(U2_ADDR_reg_mux0001[6])
  );
  AND2   \U2_ADDR_reg_mux0001<7>1  (
    .I0(N20),
    .I1(U2_ADDR_reg_and0001),
    .O(\U2_ADDR_reg_mux0001<7>1_2604 )
  );
  AND2   \U2_ADDR_reg_mux0001<7>2  (
    .I0(U2_ADDR_reg_addsub0000[7]),
    .I1(N15),
    .O(\U2_ADDR_reg_mux0001<7>2_2605 )
  );
  OR2   \U2_ADDR_reg_mux0001<7>3  (
    .I0(\U2_ADDR_reg_mux0001<7>1_2604 ),
    .I1(\U2_ADDR_reg_mux0001<7>2_2605 ),
    .O(U2_ADDR_reg_mux0001[7])
  );
  INV   \U11_U3_counterr_mux0000<5>121  (
    .I(U11_Incdetect),
    .O(\U11_U3_counterr_mux0000<5>12_2516 )
  );
  INV   \U11_U3_counterr_mux0000<5>122  (
    .I(U11_SCLdetect),
    .O(\U11_U3_counterr_mux0000<5>121_2517 )
  );
  AND2   \U11_U3_counterr_mux0000<5>123  (
    .I0(\U11_U3_counterr_mux0000<5>12_2516 ),
    .I1(\U11_U3_counterr_mux0000<5>121_2517 ),
    .O(N16)
  );
  AND2   \U11_U3_counterr_mux0000<2>1  (
    .I0(N0),
    .I1(U11_U3_counterr_share0000[3]),
    .O(\U11_U3_counterr_mux0000<2>1_2496 )
  );
  OR2   \U11_U3_counterr_mux0000<2>2  (
    .I0(SFDecomp_4),
    .I1(\U11_U3_counterr_mux0000<2>1_2496 ),
    .O(U11_U3_counterr_mux0000[2])
  );
  AND2   \U11_U3_counterr_mux0000<0>11  (
    .I0(N0),
    .I1(U11_U3_counterr_share0000[5]),
    .O(\U11_U3_counterr_mux0000<0>11_2489 )
  );
  AND2   \U11_U3_counterr_mux0000<0>12  (
    .I0(U11_U3_counterr[5]),
    .I1(N16),
    .O(\U11_U3_counterr_mux0000<0>12_2490 )
  );
  OR2   \U11_U3_counterr_mux0000<0>13  (
    .I0(\U11_U3_counterr_mux0000<0>11_2489 ),
    .I1(\U11_U3_counterr_mux0000<0>12_2490 ),
    .O(N9)
  );
  AND2   \U11_U3_counterr_mux0000<1>11  (
    .I0(N0),
    .I1(U11_U3_counterr_share0000[4]),
    .O(\U11_U3_counterr_mux0000<1>11_2493 )
  );
  AND2   \U11_U3_counterr_mux0000<1>12  (
    .I0(U11_U3_counterr[4]),
    .I1(N16),
    .O(\U11_U3_counterr_mux0000<1>12_2494 )
  );
  OR2   \U11_U3_counterr_mux0000<1>13  (
    .I0(\U11_U3_counterr_mux0000<1>11_2493 ),
    .I1(\U11_U3_counterr_mux0000<1>12_2494 ),
    .O(N10)
  );
  AND2   \U11_U3_counterr_mux0000<3>11  (
    .I0(N0),
    .I1(U11_U3_counterr_share0000[2]),
    .O(\U11_U3_counterr_mux0000<3>11_2499 )
  );
  AND2   \U11_U3_counterr_mux0000<3>12  (
    .I0(U11_U3_counterr[2]),
    .I1(N16),
    .O(\U11_U3_counterr_mux0000<3>12_2500 )
  );
  OR2   \U11_U3_counterr_mux0000<3>13  (
    .I0(\U11_U3_counterr_mux0000<3>11_2499 ),
    .I1(\U11_U3_counterr_mux0000<3>12_2500 ),
    .O(N11)
  );
  AND2   \U11_U3_counterr_mux0000<4>21  (
    .I0(N0),
    .I1(U11_U3_counterr_share0000[1]),
    .O(\U11_U3_counterr_mux0000<4>21_2508 )
  );
  AND2   \U11_U3_counterr_mux0000<4>22  (
    .I0(U11_U3_counterr[1]),
    .I1(N16),
    .O(\U11_U3_counterr_mux0000<4>22_2509 )
  );
  OR2   \U11_U3_counterr_mux0000<4>23  (
    .I0(\U11_U3_counterr_mux0000<4>21_2508 ),
    .I1(\U11_U3_counterr_mux0000<4>22_2509 ),
    .O(N12)
  );
  AND2   \U11_U3_counterr_mux0000<5>11  (
    .I0(N13),
    .I1(U11_Incdetect),
    .O(\U11_U3_counterr_mux0000<5>13 )
  );
  OR2   \U11_U3_counterr_mux0000<5>12  (
    .I0(SFDecomp_2),
    .I1(\U11_U3_counterr_mux0000<5>13 ),
    .O(N1)
  );
  INV   \U11_U3_counterr_mux0000<4>111  (
    .I(U11_Incdetect),
    .O(\U11_U3_counterr_mux0000<4>11_2503 )
  );
  AND2   \U11_U3_counterr_mux0000<4>112  (
    .I0(U11_SCLdetect),
    .I1(\U11_U3_counterr_mux0000<4>11_2503 ),
    .O(N17)
  );
  INV   U11_U3_counterr_or00031 (
    .I(SCLreset_IBUF_2431),
    .O(U11_U3_counterr_or00031_2531)
  );
  AND2   U11_U3_counterr_or00032 (
    .I0(N17),
    .I1(U11_U3_counterr_or00031_2531),
    .O(\U11_U3_Maddsub_counterr_share0000_Mxor_Result<5>__xor0001 )
  );
  AND2   \U11_U3_counterr_mux0000<4>11  (
    .I0(N8),
    .I1(U11_Incdetect),
    .O(\U11_U3_counterr_mux0000<4>12_2504 )
  );
  INV   \U11_U3_counterr_mux0000<4>12  (
    .I(TP12_OBUF_2444),
    .O(\U11_U3_counterr_mux0000<4>13_2505 )
  );
  AND2   \U11_U3_counterr_mux0000<4>13  (
    .I0(N17),
    .I1(\U11_U3_counterr_mux0000<4>13_2505 ),
    .O(\U11_U3_counterr_mux0000<4>14_2506 )
  );
  OR2   \U11_U3_counterr_mux0000<4>14  (
    .I0(\U11_U3_counterr_mux0000<4>12_2504 ),
    .I1(\U11_U3_counterr_mux0000<4>14_2506 ),
    .O(N0)
  );
  AND2   \U11_U3_counterr_mux0001<5>11  (
    .I0(U11_Incdetect),
    .I1(N8),
    .O(\U11_U3_counterr_mux0001<5>12_2527 )
  );
  INV   \U11_U3_counterr_mux0001<5>12  (
    .I(U11_SCLdetect),
    .O(\U11_U3_counterr_mux0001<5>13_2528 )
  );
  AND2   \U11_U3_counterr_mux0001<5>13  (
    .I0(\U11_U3_counterr_mux0001<5>12_2527 ),
    .I1(\U11_U3_counterr_mux0001<5>13_2528 ),
    .O(\U11_U3_counterr_mux0001<5>14_2529 )
  );
  OR2   \U11_U3_counterr_mux0001<5>14  (
    .I0(N17),
    .I1(\U11_U3_counterr_mux0001<5>14_2529 ),
    .O(N21)
  );
  AND2   U2_ADDR_reg_and000011 (
    .I0(RD_IBUF_2420),
    .I1(WR_IBUF_2630),
    .O(U2_WRRDedge_and0000)
  );
  AND2   U2_ADDR_reg_and00011 (
    .I0(NET4826),
    .I1(U2_WRRDedge_and0000),
    .O(U2_ADDR_reg_and0001)
  );
  AND2   U2_ADDR_reg_and00001 (
    .I0(U2_ADDR_in_Range),
    .I1(U2_AutoInc_2608),
    .O(U2_ADDR_reg_and00001_2567)
  );
  INV   U2_ADDR_reg_and00002 (
    .I(U2_WRRDedge_2627),
    .O(U2_ADDR_reg_and00002_2568)
  );
  AND2   U2_ADDR_reg_and00003 (
    .I0(U2_WRRDedge_and0000),
    .I1(U2_ADDR_reg_and00002_2568),
    .O(U2_ADDR_reg_and00003_2569)
  );
  AND2   U2_ADDR_reg_and00004 (
    .I0(U2_ADDR_reg_and00001_2567),
    .I1(U2_ADDR_reg_and00003_2569),
    .O(U2_ADDR_reg_and0000)
  );
  AND2   SFDecomp_11 (
    .I0(U11_SCLdetect),
    .I1(U11_U3_counterr_share0000[0]),
    .O(SFDecomp_11_2433)
  );
  INV   SFDecomp_12 (
    .I(TP12_OBUF_2444),
    .O(SFDecomp_12_2434)
  );
  AND2   SFDecomp_13 (
    .I0(SFDecomp_11_2433),
    .I1(SFDecomp_12_2434),
    .O(SFDecomp_1)
  );
  AND2   SFDecomp_21 (
    .I0(U11_U3_counterr[0]),
    .I1(N16),
    .O(SFDecomp_21_2436)
  );
  OR2   SFDecomp_22 (
    .I0(SFDecomp_1),
    .I1(SFDecomp_21_2436),
    .O(SFDecomp_2)
  );
  INV   SFDecomp_31 (
    .I(U11_U3_counterr[0]),
    .O(SFDecomp_31_2438)
  );
  INV   SFDecomp_32 (
    .I(U11_U3_counterr[2]),
    .O(SFDecomp_32_2439)
  );
  INV   SFDecomp_33 (
    .I(U11_U3_counterr[1]),
    .O(SFDecomp_33_2440)
  );
  AND3   SFDecomp_34 (
    .I0(SFDecomp_32_2439),
    .I1(SFDecomp_31_2438),
    .I2(SFDecomp_33_2440),
    .O(SFDecomp_3)
  );
  AND2   SFDecomp_41 (
    .I0(U11_U3_counterr[3]),
    .I1(N16),
    .O(SFDecomp_41_2442)
  );
  OR2   SFDecomp_42 (
    .I0(SCLreset_IBUF_2431),
    .I1(SFDecomp_41_2442),
    .O(SFDecomp_4)
  );
  IBUF   Brake0_IBUF (
    .I(Brake0),
    .O(Brake0_IBUF_2231)
  );
  IBUF   Brake1_IBUF (
    .I(Brake1),
    .O(Brake1_IBUF_2233)
  );
  IBUF   LightSense_IBUF (
    .I(LightSense),
    .O(LightSense_IBUF_2335)
  );
  IBUF   AS_IBUF (
    .I(AS),
    .O(AS_IBUF_2229)
  );
  IBUF   PhaseB_Encoder0_IBUF (
    .I(PhaseB_Encoder0),
    .O(PhaseB_Encoder0_IBUF_2412)
  );
  IBUF   MSPReset_IBUF (
    .I(MSPReset),
    .O(MSPReset_IBUF_2339)
  );
  IBUF   PhaseB_Encoder1_IBUF (
    .I(PhaseB_Encoder1),
    .O(PhaseB_Encoder1_IBUF_2414)
  );
  IBUF   INTbus_IBUF (
    .I(INTbus),
    .O(INTbus_IBUF_2315)
  );
  IBUF   Latch033FLG_IBUF (
    .I(Latch033FLG),
    .O(Latch033FLG_IBUF_2327)
  );
  IBUF   Home05FLG_IBUF (
    .I(Home05FLG),
    .O(Home05FLG_IBUF_2290)
  );
  IBUF   PhaseA_Encoder0_IBUF (
    .I(PhaseA_Encoder0),
    .O(PhaseA_Encoder0_IBUF_2408)
  );
  IBUF   PhaseA_Encoder1_IBUF (
    .I(PhaseA_Encoder1),
    .O(PhaseA_Encoder1_IBUF_2410)
  );
  IBUF   PWM1_IBUF (
    .I(PWM1),
    .O(PWM1_IBUF_2397)
  );
  IBUF   Home0_IBUF (
    .I(Home0),
    .O(Home0_IBUF_2293)
  );
  IBUF   PWM2_IBUF (
    .I(PWM2),
    .O(PWM2_IBUF_2401)
  );
  IBUF   Home1_IBUF (
    .I(Home1),
    .O(Home1_IBUF_2299)
  );
  IBUF   PWM3_IBUF (
    .I(PWM3),
    .O(PWM3_IBUF_2403)
  );
  IBUF   PWM4_IBUF (
    .I(PWM4),
    .O(PWM4_IBUF_2405)
  );
  IBUF   RLS0_IBUF (
    .I(RLS0),
    .O(RLS0_IBUF_2422)
  );
  IBUF   PWM5_IBUF (
    .I(PWM5),
    .O(GPIO8_OBUF_2276)
  );
  IBUF   RLS1_IBUF (
    .I(RLS1),
    .O(RLS1_IBUF_2424)
  );
  IBUF   Latch133FLG_IBUF (
    .I(Latch133FLG),
    .O(Latch133FLG_IBUF_2331)
  );
  IBUF   GP_Motor0_0_IBUF (
    .I(GP_Motor0_0),
    .O(GP_Motor0_0_IBUF_2281)
  );
  IBUF   Home15FLG_IBUF (
    .I(Home15FLG),
    .O(Home15FLG_IBUF_2296)
  );
  IBUF   RD_IBUF (
    .I(RD),
    .O(RD_IBUF_2420)
  );
  IBUF   Enc05FLG_IBUF (
    .I(Enc05FLG),
    .O(Enc05FLG_IBUF_2261)
  );
  IBUF   GP_Motor1_0_IBUF (
    .I(GP_Motor1_0),
    .O(GP_Motor1_0_IBUF_2285)
  );
  IBUF   FLS0_IBUF (
    .I(FLS0),
    .O(FLS0_IBUF_2269)
  );
  IBUF   FLS1_IBUF (
    .I(FLS1),
    .O(FLS1_IBUF_2271)
  );
  IBUF   WR_IBUF (
    .I(WR),
    .O(WR_IBUF_2630)
  );
  IBUF   Enc15FLG_IBUF (
    .I(Enc15FLG),
    .O(Enc15FLG_IBUF_2265)
  );
  IBUF   SCLreset_IBUF (
    .I(SCLreset),
    .O(SCLreset_IBUF_2431)
  );
  IBUF   DIR0_IBUF (
    .I(DIR0),
    .O(DIR0_out_OBUF_2256)
  );
  IBUF   DIR1_IBUF (
    .I(DIR1),
    .O(DIR1_out_OBUF_2259)
  );
  IBUF   Mclk_IBUF (
    .I(Mclk),
    .O(Mclk_IBUF_2345)
  );
  IBUF   SCLinc_IBUF (
    .I(SCLinc),
    .O(SCLinc_IBUF_2429)
  );
  IBUF   MReset_IBUF (
    .I(MReset),
    .O(MReset_IBUF_2337)
  );
  IBUF   I2CS_5_IBUF (
    .I(I2CS[5]),
    .O(I2CS_5_IBUF_2311)
  );
  IBUF   I2CS_4_IBUF (
    .I(I2CS[4]),
    .O(I2CS_4_IBUF_2310)
  );
  IBUF   I2CS_3_IBUF (
    .I(I2CS[3]),
    .O(I2CS_3_IBUF_2309)
  );
  IBUF   I2CS_2_IBUF (
    .I(I2CS[2]),
    .O(I2CS_2_IBUF_2308)
  );
  IBUF   I2CS_1_IBUF (
    .I(I2CS[1]),
    .O(I2CS_1_IBUF_2307)
  );
  IBUF   I2CS_0_IBUF (
    .I(I2CS[0]),
    .O(I2CS_0_IBUF_2306)
  );
  IOBUFE   SCL_IOBUFE (
    .I(SCL_IOBUFE_2427),
    .E(TP12_OBUF_2444),
    .O(N19),
    .IO(SCL)
  );
  IOBUFE   AD_7_IOBUFE (
    .I(outDATA[7]),
    .E(U2_Enable_AD),
    .O(N20),
    .IO(AD[7])
  );
  IOBUFE   AD_6_IOBUFE (
    .I(outDATA[6]),
    .E(U2_Enable_AD),
    .O(N211),
    .IO(AD[6])
  );
  IOBUFE   AD_5_IOBUFE (
    .I(outDATA[5]),
    .E(U2_Enable_AD),
    .O(N22),
    .IO(AD[5])
  );
  IOBUFE   AD_4_IOBUFE (
    .I(outDATA[4]),
    .E(U2_Enable_AD),
    .O(N23),
    .IO(AD[4])
  );
  IOBUFE   AD_3_IOBUFE (
    .I(outDATA[3]),
    .E(U2_Enable_AD),
    .O(N24),
    .IO(AD[3])
  );
  IOBUFE   AD_2_IOBUFE (
    .I(outDATA[2]),
    .E(U2_Enable_AD),
    .O(N25),
    .IO(AD[2])
  );
  IOBUFE   AD_1_IOBUFE (
    .I(outDATA[1]),
    .E(U2_Enable_AD),
    .O(N26),
    .IO(AD[1])
  );
  IOBUFE   AD_0_IOBUFE (
    .I(outDATA[0]),
    .E(U2_Enable_AD),
    .O(N27),
    .IO(AD[0])
  );
  OBUF   Latch133ctrl_OBUF (
    .I(Latch133ctrl_OBUF_2333),
    .O(Latch133ctrl)
  );
  OBUF   MTRpwrn_OBUF (
    .I(MTRpwrn_OBUF_2343),
    .O(MTRpwrn)
  );
  OBUF   Home15ctrl_OBUF (
    .I(Home15ctrl_OBUF_2298),
    .O(Home15ctrl)
  );
  OBUF   Latch033ctrl_OBUF (
    .I(Latch033ctrl_OBUF_2329),
    .O(Latch033ctrl)
  );
  OBUF   TmpSlct_OBUF (
    .I(TmpSlct_OBUF_2452),
    .O(TmpSlct)
  );
  OBUF   LED1_OBUF (
    .I(LED1_OBUF_2317),
    .O(LED1)
  );
  OBUF   Enc05ctrl_OBUF (
    .I(Enc05ctrl_OBUF_2263),
    .O(Enc05ctrl)
  );
  OBUF   LED2_OBUF (
    .I(LED2_OBUF_2319),
    .O(LED2)
  );
  OBUF   LED3_OBUF (
    .I(LED3_OBUF_2321),
    .O(LED3)
  );
  OBUF   LED4_OBUF (
    .I(LED4_OBUF_2323),
    .O(LED4)
  );
  OBUF   LED5_OBUF (
    .I(LED5_OBUF_2325),
    .O(LED5)
  );
  OBUF   TP12_OBUF (
    .I(TP12_OBUF_2444),
    .O(TP12)
  );
  OBUF   TP21_OBUF (
    .I(TP21_OBUF_2446),
    .O(TP21)
  );
  OBUF   TP26_OBUF (
    .I(TP26_OBUF_2448),
    .O(TP26)
  );
  OBUF   PAH0_OBUF (
    .I(PAH0_OBUF_2379),
    .O(PAH0)
  );
  OBUF   PAH1_OBUF (
    .I(PAH1_OBUF_2381),
    .O(PAH1)
  );
  OBUF   Enc15ctrl_OBUF (
    .I(Enc15ctrl_OBUF_2267),
    .O(Enc15ctrl)
  );
  OBUF   GP_Motor0_1_OBUF (
    .I(GP_Motor0_1_OBUF_2283),
    .O(GP_Motor0_1)
  );
  OBUF   PWM0_out_OBUF (
    .I(PWM0_out_OBUF_2395),
    .O(PWM0_out)
  );
  OBUF   DIR0_out_OBUF (
    .I(DIR0_out_OBUF_2256),
    .O(DIR0_out)
  );
  OBUF   TmpEn_OBUF (
    .I(TmpEn_OBUF_2450),
    .O(TmpEn)
  );
  OBUF   PAL0_OBUF (
    .I(PAL0_OBUF_2383),
    .O(PAL0)
  );
  OBUF   PAL1_OBUF (
    .I(PAL1_OBUF_2385),
    .O(PAL1)
  );
  OBUF   PBH0_OBUF (
    .I(PBH0_OBUF_2387),
    .O(PBH0)
  );
  OBUF   PBH1_OBUF (
    .I(PBH1_OBUF_2389),
    .O(PBH1)
  );
  OBUF   PresEn_OBUF (
    .I(PresEn_OBUF_2416),
    .O(PresEn)
  );
  OBUF   GPIO8_OBUF (
    .I(GPIO8_OBUF_2276),
    .O(GPIO8)
  );
  OBUF   GPIO9_OBUF (
    .I(GPIO9_OBUF_2279),
    .O(GPIO9)
  );
  OBUF   GP_Motor1_1_OBUF (
    .I(GP_Motor1_1_OBUF_2287),
    .O(GP_Motor1_1)
  );
  OBUF   PBL0_OBUF (
    .I(PBL0_OBUF_2391),
    .O(PBL0)
  );
  OBUF   PBL1_OBUF (
    .I(PBL1_OBUF_2393),
    .O(PBL1)
  );
  OBUF   PWM1_out_OBUF (
    .I(PWM1_out_OBUF_2399),
    .O(PWM1_out)
  );
  OBUF   DIR1_out_OBUF (
    .I(DIR1_out_OBUF_2259),
    .O(DIR1_out)
  );
  OBUF   GPIO10_OBUF (
    .I(GPIO10_OBUF_2274),
    .O(GPIO10)
  );
  OBUF   PresSlct_OBUF (
    .I(PresSlct_OBUF_2418),
    .O(PresSlct)
  );
  OBUF   Home05ctrl_OBUF (
    .I(Home05ctrl_OBUF_2292),
    .O(Home05ctrl)
  );
  OBUF   INT_OBUF (
    .I(INT_OBUF_2313),
    .O(INT)
  );
  OBUF   MTRpwr_OBUF (
    .I(MTRpwr_OBUF_2341),
    .O(MTRpwr)
  );
  XOR2   \U11_U3_Maddsub_counterr_share0000_Mxor_Result<1>_Mxor__xor0000/Xo<0>1  (
    .I0(U11_U3_counterr[1]),
    .I1(U11_U3_Maddsub_counterr_share0000__or0000),
    .O(\U11_U3_Maddsub_counterr_share0000_Mxor_Result<1>__xor0000 )
  );
  XOR2   \U11_U3_Maddsub_counterr_share0000_Mxor_Result<1>_Mxor_Result/Xo<0>1  (
    .I0(\U11_U3_Maddsub_counterr_share0000_Mxor_Result<1>__xor0000 ),
    .I1(\U11_U3_Maddsub_counterr_share0000_Mxor_Result<5>__xor0001 ),
    .O(U11_U3_counterr_share0000[1])
  );
  XOR2   \U11_U3_Maddsub_counterr_share0000_Mxor_Result<2>_Mxor__xor0000/Xo<0>1  (
    .I0(U11_U3_counterr[2]),
    .I1(U11_U3_Maddsub_counterr_share0000__or0001),
    .O(\U11_U3_Maddsub_counterr_share0000_Mxor_Result<2>__xor0000 )
  );
  XOR2   \U11_U3_Maddsub_counterr_share0000_Mxor_Result<2>_Mxor_Result/Xo<0>1  (
    .I0(\U11_U3_Maddsub_counterr_share0000_Mxor_Result<2>__xor0000 ),
    .I1(\U11_U3_Maddsub_counterr_share0000_Mxor_Result<5>__xor0001 ),
    .O(U11_U3_counterr_share0000[2])
  );
  XOR2   \U11_U3_Maddsub_counterr_share0000_Mxor_Result<3>_Mxor__xor0000/Xo<0>1  (
    .I0(U11_U3_counterr[3]),
    .I1(U11_U3_Maddsub_counterr_share0000__or0002),
    .O(\U11_U3_Maddsub_counterr_share0000_Mxor_Result<3>__xor0000 )
  );
  XOR2   \U11_U3_Maddsub_counterr_share0000_Mxor_Result<3>_Mxor_Result/Xo<0>1  (
    .I0(\U11_U3_Maddsub_counterr_share0000_Mxor_Result<3>__xor0000 ),
    .I1(U11_U3_Maddsub_counterr_share0000_or0003_xor0000),
    .O(U11_U3_counterr_share0000[3])
  );
  XOR2   \U11_U3_Maddsub_counterr_share0000_Mxor_Result<4>_Mxor__xor0000/Xo<0>1  (
    .I0(U11_U3_counterr[4]),
    .I1(U11_U3_Maddsub_counterr_share0000__or0003),
    .O(\U11_U3_Maddsub_counterr_share0000_Mxor_Result<4>__xor0000 )
  );
  XOR2   \U11_U3_Maddsub_counterr_share0000_Mxor_Result<4>_Mxor_Result/Xo<0>1  (
    .I0(\U11_U3_Maddsub_counterr_share0000_Mxor_Result<4>__xor0000 ),
    .I1(\U11_U3_Maddsub_counterr_share0000_Mxor_Result<5>__xor0001 ),
    .O(U11_U3_counterr_share0000[4])
  );
  XOR2   \U11_U3_Maddsub_counterr_share0000_Mxor_Result<5>_Mxor__xor0000/Xo<0>1  (
    .I0(U11_U3_counterr[5]),
    .I1(U11_U3_Maddsub_counterr_share0000__or0004),
    .O(\U11_U3_Maddsub_counterr_share0000_Mxor_Result<5>__xor0000 )
  );
  XOR2   \U11_U3_Maddsub_counterr_share0000_Mxor_Result<5>_Mxor_Result/Xo<0>1  (
    .I0(\U11_U3_Maddsub_counterr_share0000_Mxor_Result<5>__xor0001 ),
    .I1(\U11_U3_Maddsub_counterr_share0000_Mxor_Result<5>__xor0000 ),
    .O(U11_U3_counterr_share0000[5])
  );
  XOR2   \U11_U3_Maddsub_counterr_share0000_Mxor_or0003_xor0000/Xo<0>1  (
    .I0(\U11_U3_Maddsub_counterr_share0000_Mxor_Result<5>__xor0001 ),
    .I1(\U11_U3_counterr_mux0001[2] ),
    .O(U11_U3_Maddsub_counterr_share0000_or0003_xor0000)
  );
  XOR2   \U11_U3_Maddsub_counterr_share0000_Mxor_or0000_xor0000/Xo<0>1  (
    .I0(\U11_U3_Maddsub_counterr_share0000_Mxor_Result<5>__xor0001 ),
    .I1(\U11_U3_counterr_mux0001[5] ),
    .O(U11_U3_Maddsub_counterr_share0000_or0000_xor0000)
  );
  XOR2   \U11_U3_Maddsub_counterr_share0000_Mxor_Result<0>/Xo<0>1  (
    .I0(U11_U3_counterr[0]),
    .I1(\U11_U3_counterr_mux0001[5] ),
    .O(U11_U3_counterr_share0000[0])
  );
  XOR2   \U2_Madd_ADDR_reg_addsub0000_Mxor_Result<1>/Xo<0>1  (
    .I0(U2_ADDR_reg[0]),
    .I1(U2_ADDR_reg[1]),
    .O(U2_ADDR_reg_addsub0000[1])
  );
  XOR2   \U2_Madd_ADDR_reg_addsub0000_Mxor_Result<2>/Xo<0>1  (
    .I0(U2_Madd_ADDR_reg_addsub0000__and0000),
    .I1(U2_ADDR_reg[2]),
    .O(U2_ADDR_reg_addsub0000[2])
  );
  XOR2   \U2_Madd_ADDR_reg_addsub0000_Mxor_Result<3>/Xo<0>1  (
    .I0(U2_Madd_ADDR_reg_addsub0000__and0001),
    .I1(U2_ADDR_reg[3]),
    .O(U2_ADDR_reg_addsub0000[3])
  );
  XOR2   \U2_Madd_ADDR_reg_addsub0000_Mxor_Result<4>/Xo<0>1  (
    .I0(U2_Madd_ADDR_reg_addsub0000__and0002),
    .I1(U2_ADDR_reg[4]),
    .O(U2_ADDR_reg_addsub0000[4])
  );
  XOR2   \U2_Madd_ADDR_reg_addsub0000_Mxor_Result<5>/Xo<0>1  (
    .I0(U2_Madd_ADDR_reg_addsub0000__and0003),
    .I1(U2_ADDR_reg[5]),
    .O(U2_ADDR_reg_addsub0000[5])
  );
  XOR2   \U2_Madd_ADDR_reg_addsub0000_Mxor_Result<6>/Xo<0>1  (
    .I0(U2_Madd_ADDR_reg_addsub0000__and0004),
    .I1(U2_ADDR_reg[6]),
    .O(U2_ADDR_reg_addsub0000[6])
  );
  XOR2   \U2_Madd_ADDR_reg_addsub0000_Mxor_Result<7>/Xo<0>1  (
    .I0(U2_Madd_ADDR_reg_addsub0000__and0005),
    .I1(U2_ADDR_reg[7]),
    .O(U2_ADDR_reg_addsub0000[7])
  );
endmodule


`timescale  1 ps / 1 ps

module glbl ();

    parameter ROC_WIDTH = 100000;
    parameter TOC_WIDTH = 0;

    wire GSR;
    wire GTS;
    wire PRLD;

    reg GSR_int;
    reg GTS_int;
    reg PRLD_int;

//--------   JTAG Globals --------------
    wire JTAG_TDO_GLBL;
    wire JTAG_TCK_GLBL;
    wire JTAG_TDI_GLBL;
    wire JTAG_TMS_GLBL;
    wire JTAG_TRST_GLBL;

    reg JTAG_CAPTURE_GLBL;
    reg JTAG_RESET_GLBL;
    reg JTAG_SHIFT_GLBL;
    reg JTAG_UPDATE_GLBL;

    reg JTAG_SEL1_GLBL = 0;
    reg JTAG_SEL2_GLBL = 0 ;
    reg JTAG_SEL3_GLBL = 0;
    reg JTAG_SEL4_GLBL = 0;

    reg JTAG_USER_TDO1_GLBL = 1'bz;
    reg JTAG_USER_TDO2_GLBL = 1'bz;
    reg JTAG_USER_TDO3_GLBL = 1'bz;
    reg JTAG_USER_TDO4_GLBL = 1'bz;

    assign (weak1, weak0) GSR = GSR_int;
    assign (weak1, weak0) GTS = GTS_int;
    assign (weak1, weak0) PRLD = PRLD_int;

    initial begin
	GSR_int = 1'b1;
	PRLD_int = 1'b1;
	#(ROC_WIDTH)
	GSR_int = 1'b0;
	PRLD_int = 1'b0;
    end

    initial begin
	GTS_int = 1'b1;
	#(TOC_WIDTH)
	GTS_int = 1'b0;
    end

endmodule