Synthesis Log
Created on 6:46:28 PM 4/17/2009
Running XST Synthesis...
Please wait...
Release 10.1.03 - xst K.39 (nt)
Copyright (c) 1995-2008 Xilinx, Inc. All rights reserved.
--> Parameter TMPDIR set to .
Total REAL time to Xst completion: 0.00 secs
Total CPU time to Xst completion: 0.09 secs
--> Parameter xsthdpdir set to C:\esp\electrical\Dwarf\Core\CPLD\synthesis\xst
Total REAL time to Xst completion: 0.00 secs
Total CPU time to Xst completion: 0.09 secs
-->
TABLE OF CONTENTS
1) Synthesis Options Summary
2) HDL Compilation
3) Design Hierarchy Analysis
4) HDL Analysis
5) HDL Synthesis
5.1) HDL Synthesis Report
6) Advanced HDL Synthesis
6.1) Advanced HDL Synthesis Report
7) Low Level Synthesis
8) Partition Report
9) Final Report
=========================================================================
* Synthesis Options Summary *
=========================================================================
---- Source Parameters
Input File Name : "U21.prj"
Input Format : mixed
Verilog Include Directory : {"c:/dwarf_fpgas/core/src" }
Ignore Synthesis Constraint File : no
---- Target Parameters
Output File Name : "U21"
Output Format : NGC
Target Device : xcr3384xlTQ144-7
---- Source Options
Top Module Name : U21
Generics, Parameters : { }
Verilog Macros : { }
Automatic FSM Extraction : yes
FSM Encoding Algorithm : Auto
Mux Extraction : yes
Safe Implementation : no
Resource Sharing : yes
---- Target Options
Add IO Buffers : yes
Equivalent register Removal : yes
MACRO Preserve : yes
XOR Preserve : yes
---- General Options
Optimization Goal : area
Optimization Effort : 1
RTL Output : yes
Verilog 2001 : yes
Keep Hierarchy : yes
Netlist Hierarchy : as_optimized
Hierarchy Separator : _
Bus Delimiter : <>
Case Specifier : maintain
---- Other Options
Clock Enable : yes
wysiwyg : no
=========================================================================
=========================================================================
* HDL Compilation *
=========================================================================
Compiling verilog file "c:/dwarf_fpgas/core/src/..\compile\U21.v" in library Core
Compiling verilog file "c:/dwarf_fpgas/core/src/..\src\U21AddressMap.v" in library Core
Compiling verilog file "c:/dwarf_fpgas/core/src/..\src\U21AddDecode.v" in library Core
Compiling verilog include file "c:/dwarf_fpgas/core/src/..\src/U21AddressMap.v"
Module <U21> compiled
Compiling verilog file "c:/dwarf_fpgas/core/src/..\compile\Servos.v" in library Core
Module <U21AddDecode> compiled
Compiling verilog file "c:/dwarf_fpgas/core/src/..\src\MISCouts.v" in library Core
Module <Servos> compiled
Compiling verilog file "c:/dwarf_fpgas/core/src/..\src\PWRreg.v" in library Core
Module <MISCouts> compiled
Compiling verilog file "c:/dwarf_fpgas/core/src/..\src\Lswitch.v" in library Core
Module <PWRreg> compiled
Compiling verilog file "c:/dwarf_fpgas/core/src/..\compile\PWMcontrol.v" in library Core
Module <Lswitch> compiled
Compiling verilog file "c:/dwarf_fpgas/core/src/..\src\PWMtranslator.v" in library Core
Module <PWMcontrol> compiled
Compiling verilog file "c:/dwarf_fpgas/core/src/..\compile\I2Cfix.v" in library Core
Module <PWMtranslator> compiled
Compiling verilog file "c:/dwarf_fpgas/core/src/..\src\I2CAddress.v" in library Core
Module <I2Cfix> compiled
Compiling verilog file "c:/dwarf_fpgas/core/src/..\src\counter.v" in library Core
Module <I2CAddress> compiled
Compiling verilog file "c:/dwarf_fpgas/core/src/..\src\holdreg.v" in library Core
Module <Counter> compiled
Compiling verilog file "c:/dwarf_fpgas/core/src/..\src\Interface.v" in library Core
Module <Holdreg> compiled
Compiling verilog file "c:/dwarf_fpgas/core/src/..\src\HomeConfig.v" in library Core
Module <Interface> compiled
Compiling verilog file "c:/dwarf_fpgas/core/src/..\src\negdetect.v" in library Core
Module <HomeConfig> compiled
Compiling verilog file "c:/dwarf_fpgas/core/src/..\src\BitCounter.v" in library Core
Module <NegDetect> compiled
Compiling verilog file "c:/dwarf_fpgas/core/src/..\src\Interrupt.v" in library Core
Module <BitCounter> compiled
Compiling verilog file "c:/dwarf_fpgas/core/src/..\src\Sensor.v" in library Core
Module <Interrupt> compiled
Compiling verilog file "c:/dwarf_fpgas/core/src/..\src\low_pass_filter.v" in library Core
Module <Sensor> compiled
Compiling verilog file "c:/dwarf_fpgas/core/src/..\src\qdecode.v" in library Core
Module <low_pass_filter> compiled
Module <Decode> compiled
No errors in compilation
Analysis of file <"U21.prj"> succeeded.
=========================================================================
* Design Hierarchy Analysis *
=========================================================================
Analyzing hierarchy for module <U21> in library <Core> with parameters.
DANGLING_INPUT_CONSTANT = "Z"
Analyzing hierarchy for module <Servos> in library <Core>.
Analyzing hierarchy for module <I2Cfix> in library <Core>.
Analyzing hierarchy for module <U21AddDecode> in library <Core>.
Analyzing hierarchy for module <Interface> in library <Core>.
Analyzing hierarchy for module <Interrupt> in library <Core>.
Analyzing hierarchy for module <PWRreg> in library <Core>.
Analyzing hierarchy for module <Lswitch> in library <Core>.
Analyzing hierarchy for module <I2CAddress> in library <Core>.
Analyzing hierarchy for module <PWMcontrol> in library <Core>.
Analyzing hierarchy for module <Sensor> in library <Core>.
Analyzing hierarchy for module <MISCouts> in library <Core>.
Analyzing hierarchy for module <Decode> in library <Core> with parameters.
COUNT = "110"
LR1 = "001"
LR2 = "011"
LR3 = "010"
RL1 = "100"
RL2 = "101"
RL3 = "111"
WAIT = "000"
Analyzing hierarchy for module <Counter> in library <Core>.
Analyzing hierarchy for module <Holdreg> in library <Core>.
Analyzing hierarchy for module <HomeConfig> in library <Core>.
Analyzing hierarchy for module <NegDetect> in library <Core>.
Analyzing hierarchy for module <BitCounter> in library <Core>.
Analyzing hierarchy for module <PWMtranslator> in library <Core>.
Analyzing hierarchy for module <low_pass_filter> in library <Core>.
INFO:Xst:2555 - '-hierarchy_separator' switch is being deprecated in a future release.
=========================================================================
* HDL Analysis *
=========================================================================
Analyzing top module <U21>.
DANGLING_INPUT_CONSTANT = 1'bZ
Module <U21> is correct for synthesis.
Analyzing module <Servos> in library <Core>.
Module <Servos> is correct for synthesis.
Analyzing module <Decode> in library <Core>.
COUNT = 3'b110
LR1 = 3'b001
LR2 = 3'b011
LR3 = 3'b010
RL1 = 3'b100
RL2 = 3'b101
RL3 = 3'b111
WAIT = 3'b000
WARNING:Xst:2725 - "c:/dwarf_fpgas/core/src/..\src\qdecode.v" line 56: Size mismatch between case item and case selector.
WARNING:Xst:2725 - "c:/dwarf_fpgas/core/src/..\src\qdecode.v" line 64: Size mismatch between case item and case selector.
WARNING:Xst:2725 - "c:/dwarf_fpgas/core/src/..\src\qdecode.v" line 72: Size mismatch between case item and case selector.
WARNING:Xst:2725 - "c:/dwarf_fpgas/core/src/..\src\qdecode.v" line 80: Size mismatch between case item and case selector.
WARNING:Xst:2725 - "c:/dwarf_fpgas/core/src/..\src\qdecode.v" line 88: Size mismatch between case item and case selector.
WARNING:Xst:2725 - "c:/dwarf_fpgas/core/src/..\src\qdecode.v" line 96: Size mismatch between case item and case selector.
WARNING:Xst:2725 - "c:/dwarf_fpgas/core/src/..\src\qdecode.v" line 104: Size mismatch between case item and case selector.
WARNING:Xst:2725 - "c:/dwarf_fpgas/core/src/..\src\qdecode.v" line 112: Size mismatch between case item and case selector.
Module <Decode> is correct for synthesis.
Analyzing module <low_pass_filter> in library <Core>.
Module <low_pass_filter> is correct for synthesis.
Analyzing module <Counter> in library <Core>.
Module <Counter> is correct for synthesis.
Analyzing module <Holdreg> in library <Core>.
Module <Holdreg> is correct for synthesis.
Set user-defined property "KEEP = TRUE" for signal <interDATA>.
Analyzing module <HomeConfig> in library <Core>.
Module <HomeConfig> is correct for synthesis.
Analyzing module <I2Cfix> in library <Core>.
Module <I2Cfix> is correct for synthesis.
Analyzing module <NegDetect> in library <Core>.
Module <NegDetect> is correct for synthesis.
Analyzing module <BitCounter> in library <Core>.
Module <BitCounter> is correct for synthesis.
Analyzing module <U21AddDecode> in library <Core>.
Calling function <Select>.
Calling function <Select>.
Calling function <Select>.
Calling function <Select>.
Calling function <Select>.
Calling function <Select>.
Calling function <Select>.
Calling function <Select>.
Calling function <Select>.
Calling function <Select>.
Calling function <Select>.
Calling function <Select>.
Calling function <Select>.
Calling function <Select>.
Calling function <Select>.
Calling function <Select>.
Calling function <Select>.
Calling function <Select>.
Calling function <Select>.
Calling function <Select>.
Module <U21AddDecode> is correct for synthesis.
Set user-defined property "KEEP = TRUE" for signal <DCOR0CNTLOWr> in unit <U21AddDecode>.
Set user-defined property "KEEP = TRUE" for signal <DCOR0THRESLOWr> in unit <U21AddDecode>.
Set user-defined property "KEEP = TRUE" for signal <DCOR1CNTLOWr> in unit <U21AddDecode>.
Set user-defined property "KEEP = TRUE" for signal <DCOR1THRESLOWr> in unit <U21AddDecode>.
Set user-defined property "KEEP = TRUE" for signal <DCORENCPWRr> in unit <U21AddDecode>.
Set user-defined property "KEEP = TRUE" for signal <DCORLIMITSr> in unit <U21AddDecode>.
Set user-defined property "KEEP = TRUE" for signal <DCORIEw> in unit <U21AddDecode>.
Set user-defined property "KEEP = TRUE" for signal <DCORENCPWRw> in unit <U21AddDecode>.
Set user-defined property "KEEP = TRUE" for signal <DCOR0CNTHIGHr> in unit <U21AddDecode>.
Set user-defined property "KEEP = TRUE" for signal <DCORIFGr> in unit <U21AddDecode>.
Set user-defined property "KEEP = TRUE" for signal <DCOR1CNTHIGHr> in unit <U21AddDecode>.
Set user-defined property "KEEP = TRUE" for signal <DCOR0THRESHIGHr> in unit <U21AddDecode>.
Set user-defined property "KEEP = TRUE" for signal <DCORCONFIGr> in unit <U21AddDecode>.
Set user-defined property "KEEP = TRUE" for signal <DCORLINTr> in unit <U21AddDecode>.
Set user-defined property "KEEP = TRUE" for signal <DCOR1THRESHIGHr> in unit <U21AddDecode>.
Set user-defined property "KEEP = TRUE" for signal <DCORIFGw> in unit <U21AddDecode>.
Set user-defined property "KEEP = TRUE" for signal <DCOROUTw> in unit <U21AddDecode>.
Set user-defined property "KEEP = TRUE" for signal <DCORENCCTLw> in unit <U21AddDecode>.
Set user-defined property "KEEP = TRUE" for signal <DCORSENSORw> in unit <U21AddDecode>.
Set user-defined property "KEEP = TRUE" for signal <DCORI2CCNTr> in unit <U21AddDecode>.
Analyzing module <Interface> in library <Core>.
Module <Interface> is correct for synthesis.
Set user-defined property "KEEP = true" for signal <Enable_AD>.
Analyzing module <Interrupt> in library <Core>.
Module <Interrupt> is correct for synthesis.
Analyzing module <PWRreg> in library <Core>.
Module <PWRreg> is correct for synthesis.
Analyzing module <Lswitch> in library <Core>.
Module <Lswitch> is correct for synthesis.
Analyzing module <I2CAddress> in library <Core>.
Module <I2CAddress> is correct for synthesis.
Analyzing module <PWMcontrol> in library <Core>.
Module <PWMcontrol> is correct for synthesis.
Analyzing module <PWMtranslator> in library <Core>.
Module <PWMtranslator> is correct for synthesis.
Analyzing module <Sensor> in library <Core>.
Module <Sensor> is correct for synthesis.
Analyzing module <MISCouts> in library <Core>.
Module <MISCouts> is correct for synthesis.
=========================================================================
* HDL Synthesis *
=========================================================================
Performing bidirectional port resolution...
INFO:Xst:2679 - Register <Zero0r> in unit <HomeConfig> has a constant value of 0 during circuit operation. The register is replaced by logic.
INFO:Xst:2679 - Register <Zero1r> in unit <HomeConfig> has a constant value of 0 during circuit operation. The register is replaced by logic.
Synthesizing Unit <U21AddDecode>.
Related source file is "c:/dwarf_fpgas/core/src/..\src\U21AddDecode.v".
WARNING:Xst:647 - Input <AS> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
Unit <U21AddDecode> synthesized.
Synthesizing Unit <Interface>.
Related source file is "c:/dwarf_fpgas/core/src/..\src\Interface.v".
Found 8-bit tristate buffer for signal <AD>.
Found 8-bit comparator lessequal for signal <ADDR_in_Range>.
Found 8-bit register for signal <ADDR_reg>.
Found 8-bit adder for signal <ADDR_reg$addsub0000> created at line 101.
Found 8-bit comparator lessequal for signal <ADDR_reg$cmp_le0000> created at line 101.
Found 8-bit comparator less for signal <ADDR_reg$cmp_lt0000> created at line 101.
Found 1-bit register for signal <ASedge>.
Found 1-bit register for signal <AutoInc>.
Found 1-bit register for signal <WRRDedge>.
Summary:
inferred 3 D-type flip-flop(s).
inferred 1 Adder/Subtractor(s).
inferred 3 Comparator(s).
inferred 8 Tristate(s).
Unit <Interface> synthesized.
Synthesizing Unit <Interrupt>.
Related source file is "c:/dwarf_fpgas/core/src/..\src\Interrupt.v".
Found 8-bit tristate buffer for signal <outDATA>.
Found 8-bit register for signal <DCORIE>.
Summary:
inferred 8 Tristate(s).
Unit <Interrupt> synthesized.
Synthesizing Unit <PWRreg>.
Related source file is "c:/dwarf_fpgas/core/src/..\src\PWRreg.v".
WARNING:Xst:1305 - Output <Enc033ctl> is never assigned. Tied to value 0.
WARNING:Xst:647 - Input <Enc033flg> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:1305 - Output <Enc133ctl> is never assigned. Tied to value 0.
WARNING:Xst:647 - Input <Enc133flg> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:646 - Signal <ctrlr<6>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <ctrlr<2>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
Found 8-bit tristate buffer for signal <outDATA>.
Found 8-bit register for signal <ctrlr>.
Found 1-bit register for signal <DCORIFG>.
Found 8-bit register for signal <Flgreg>.
Summary:
inferred 8 Tristate(s).
Unit <PWRreg> synthesized.
Synthesizing Unit <Lswitch>.
Related source file is "c:/dwarf_fpgas/core/src/..\src\Lswitch.v".
Found 8-bit tristate buffer for signal <outDATA>.
Found 1-bit register for signal <DCORIFG>.
Found 1-bit register for signal <fBRK0r>.
Found 1-bit register for signal <fBRK1r>.
Found 1-bit register for signal <FLS0fr>.
Found 1-bit register for signal <FLS0r>.
Found 1-bit register for signal <FLS1fr>.
Found 1-bit register for signal <FLS1r>.
Found 1-bit register for signal <RLS0fr>.
Found 1-bit register for signal <RLS0r>.
Found 1-bit register for signal <RLS1fr>.
Found 1-bit register for signal <RLS1r>.
Summary:
inferred 2 D-type flip-flop(s).
inferred 8 Tristate(s).
Unit <Lswitch> synthesized.
Synthesizing Unit <I2CAddress>.
Related source file is "c:/dwarf_fpgas/core/src/..\src\I2CAddress.v".
Found 8-bit tristate buffer for signal <outDATA>.
Summary:
inferred 8 Tristate(s).
Unit <I2CAddress> synthesized.
Synthesizing Unit <Sensor>.
Related source file is "c:/dwarf_fpgas/core/src/..\src\Sensor.v".
Found 4-bit register for signal <sensorr>.
Unit <Sensor> synthesized.
Synthesizing Unit <MISCouts>.
Related source file is "c:/dwarf_fpgas/core/src/..\src\MISCouts.v".
Found 8-bit register for signal <MISCr>.
Unit <MISCouts> synthesized.
Synthesizing Unit <Counter>.
Related source file is "c:/dwarf_fpgas/core/src/..\src\counter.v".
Found 16-bit up accumulator for signal <location>.
Summary:
inferred 1 Accumulator(s).
Unit <Counter> synthesized.
Synthesizing Unit <Holdreg>.
Related source file is "c:/dwarf_fpgas/core/src/..\src\holdreg.v".
WARNING:Xst:646 - Signal <RDedge> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
Found 16-bit register for signal <holdingreg0>.
Found 16-bit register for signal <holdingreg1>.
Found 8-bit tristate buffer for signal <interDATA>.
Summary:
inferred 8 Tristate(s).
Unit <Holdreg> synthesized.
Synthesizing Unit <HomeConfig>.
Related source file is "c:/dwarf_fpgas/core/src/..\src\HomeConfig.v".
Found 8-bit tristate buffer for signal <outDATA>.
Found 1-bit register for signal <E0r>.
Found 1-bit register for signal <E1r>.
Found 1-bit register for signal <HE0statelastr>.
Found 1-bit register for signal <HE0stater>.
Found 1-bit register for signal <HE1statelastr>.
Found 1-bit register for signal <HE1stater>.
Found 1-bit register for signal <Hfound0r>.
Found 1-bit register for signal <Hfound1r>.
Found 1-bit register for signal <InEdge0r>.
Found 1-bit register for signal <InEdge1r>.
Found 1-bit register for signal <LastEdge0r>.
Found 1-bit register for signal <LastEdge1r>.
Found 16-bit register for signal <Latch0r>.
Found 16-bit register for signal <Latch1r>.
Found 1-bit register for signal <LatchEdge0r>.
Found 1-bit register for signal <LatchEdge1r>.
Found 1-bit register for signal <latchitH0>.
Found 1-bit register for signal <latchitH1>.
Found 1-bit register for signal <latchitL0>.
Found 1-bit register for signal <latchitL1>.
Found 1-bit register for signal <RF0r>.
Found 1-bit register for signal <RF1r>.
Found 1-bit register for signal <sense0r>.
Found 1-bit register for signal <sense1r>.
Found 1-bit register for signal <Tfound0r>.
Found 1-bit register for signal <Tfound1r>.
Summary:
inferred 10 D-type flip-flop(s).
inferred 8 Tristate(s).
Unit <HomeConfig> synthesized.
Synthesizing Unit <low_pass_filter>.
Related source file is "c:/dwarf_fpgas/core/src/..\src\low_pass_filter.v".
Found 5-bit register for signal <delayed>.
Found 1-bit register for signal <q>.
Unit <low_pass_filter> synthesized.
Synthesizing Unit <NegDetect>.
Related source file is "c:/dwarf_fpgas/core/src/..\src\negdetect.v".
Found 1-bit register for signal <Line_last>.
Found 1-bit register for signal <Ndetectr>.
Summary:
inferred 1 D-type flip-flop(s).
Unit <NegDetect> synthesized.
Synthesizing Unit <BitCounter>.
Related source file is "c:/dwarf_fpgas/core/src/..\src\BitCounter.v".
Found 8-bit tristate buffer for signal <outDATA>.
Found 1-bit tristate buffer for signal <DriveSCL>.
Found 6-bit register for signal <counterr>.
Found 6-bit addsub for signal <counterr$share0000> created at line 70.
Summary:
inferred 1 Adder/Subtractor(s).
inferred 9 Tristate(s).
Unit <BitCounter> synthesized.
Synthesizing Unit <PWMtranslator>.
Related source file is "c:/dwarf_fpgas/core/src/..\src\PWMtranslator.v".
Unit <PWMtranslator> synthesized.
Synthesizing Unit <I2Cfix>.
Related source file is "c:/dwarf_fpgas/core/src/..\compile\I2Cfix.v".
Unit <I2Cfix> synthesized.
Synthesizing Unit <PWMcontrol>.
Related source file is "c:/dwarf_fpgas/core/src/..\compile\PWMcontrol.v".
Unit <PWMcontrol> synthesized.
Synthesizing Unit <Decode>.
Related source file is "c:/dwarf_fpgas/core/src/..\src\qdecode.v".
Found finite state machine <FSM_0> for signal <state>.
-----------------------------------------------------------------------
| States | 8 |
| Transitions | 29 |
| Inputs | 4 |
| Outputs | 7 |
| Clock | Sclk (rising_edge) |
| Reset | Reset (positive) |
| Reset type | synchronous |
| Reset State | 0000 |
| Encoding | automatic |
| Implementation | automatic |
-----------------------------------------------------------------------
Found 1-bit register for signal <ce>.
Found 1-bit register for signal <updown>.
Summary:
inferred 1 Finite State Machine(s).
Unit <Decode> synthesized.
Synthesizing Unit <Servos>.
Related source file is "c:/dwarf_fpgas/core/src/..\compile\Servos.v".
Unit <Servos> synthesized.
Synthesizing Unit <U21>.
Related source file is "c:/dwarf_fpgas/core/src/..\compile\U21.v".
Found 1-bit tristate buffer for signal <Dangling_Input_Signal>.
Summary:
inferred 1 Tristate(s).
Unit <U21> synthesized.
=========================================================================
HDL Synthesis Report
Macro Statistics
# Adders/Subtractors : 2
6-bit addsub : 1
8-bit adder : 1
# Accumulators : 2
16-bit up accumulator : 2
# Registers : 68
1-bit register : 53
16-bit register : 4
4-bit register : 1
5-bit register : 4
6-bit register : 1
8-bit register : 5
# Comparators : 3
8-bit comparator less : 1
8-bit comparator lessequal : 2
# Tristates : 38
1-bit tristate buffer : 34
8-bit tristate buffer : 4
=========================================================================
=========================================================================
* Advanced HDL Synthesis *
=========================================================================
Analyzing FSM <FSM_0> for best encoding.
Optimizing FSM <U1/U1/state/FSM> on signal <state[1:3]> with sequential encoding.
Optimizing FSM <U1/U6/state/FSM> on signal <state[1:3]> with sequential encoding.
-------------------
State | Encoding
-------------------
0000 | 000
0100 | 001
0001 | 010
0011 | 011
0010 | 100
0110 | 101
0101 | 110
0111 | 111
-------------------
WARNING:Xst:1426 - The value init of the FF/Latch 6 hinder the constant cleaning in the block Flgreg.
You should achieve better results by setting this init to 1.
WARNING:Xst:1426 - The value init of the FF/Latch 2 hinder the constant cleaning in the block Flgreg.
You should achieve better results by setting this init to 1.
WARNING:Xst:2677 - Node <6> of sequential type is unconnected in block <ctrlr>.
WARNING:Xst:2677 - Node <2> of sequential type is unconnected in block <ctrlr>.
=========================================================================
Advanced HDL Synthesis Report
Macro Statistics
# Adders/Subtractors : 2
6-bit addsub : 1
8-bit adder : 1
# Accumulators : 2
16-bit up accumulator : 2
# Registers : 93
Flip-Flops : 93
=========================================================================
=========================================================================
* Low Level Synthesis *
=========================================================================
WARNING:Xst:1426 - The value init of the FF/Latch Flgreg_6 hinder the constant cleaning in the block PWRreg.
You should achieve better results by setting this init to 1.
WARNING:Xst:1426 - The value init of the FF/Latch Flgreg_2 hinder the constant cleaning in the block PWRreg.
You should achieve better results by setting this init to 1.
WARNING:Xst:2677 - Node <ctrlr_2> of sequential type is unconnected in block <PWRreg>.
WARNING:Xst:2677 - Node <ctrlr_6> of sequential type is unconnected in block <PWRreg>.
INFO:Xst:2261 - The FF/Latch <Flgreg_2> in Unit <PWRreg> is equivalent to the following FF/Latch, which will be removed : <Flgreg_6>
WARNING:Xst:1348 - Unit BitCounter is merged (output interface has tristates)
WARNING:Xst:1348 - Unit I2Cfix is merged (output interface has tristates)
WARNING:Xst:1348 - Unit Interface is merged (output interface has tristates)
WARNING:Xst:2183 - Unit U21: the following tristate(s) are NOT replaced by logic (Please refer to Answer Record 20048 for more information): outDATA<0>, outDATA<1>, outDATA<2>, outDATA<3>, outDATA<4>, outDATA<5>, outDATA<6>, outDATA<7>.
WARNING:Xst:2183 - Unit HomeConfig: the following tristate(s) are NOT replaced by logic (Please refer to Answer Record 20048 for more information): outDATA<0>, outDATA<1>, outDATA<2>, outDATA<3>, outDATA<4>, outDATA<5>, outDATA<6>, outDATA<7>.
WARNING:Xst:2183 - Unit Holdreg: the following tristate(s) are NOT replaced by logic (Please refer to Answer Record 20048 for more information): interDATA<0>, interDATA<1>, interDATA<2>, interDATA<3>, interDATA<4>, interDATA<5>, interDATA<6>, interDATA<7>.
WARNING:Xst:2183 - Unit PWRreg: the following tristate(s) are NOT replaced by logic (Please refer to Answer Record 20048 for more information): outDATA<0>, outDATA<1>, outDATA<2>, outDATA<3>, outDATA<4>, outDATA<5>, outDATA<6>, outDATA<7>.
WARNING:Xst:2183 - Unit Interrupt: the following tristate(s) are NOT replaced by logic (Please refer to Answer Record 20048 for more information): outDATA<0>, outDATA<1>, outDATA<2>, outDATA<3>, outDATA<4>, outDATA<5>, outDATA<6>, outDATA<7>.
WARNING:Xst:2183 - Unit I2CAddress: the following tristate(s) are NOT replaced by logic (Please refer to Answer Record 20048 for more information): outDATA<0>, outDATA<1>, outDATA<2>, outDATA<3>, outDATA<4>, outDATA<5>, outDATA<6>, outDATA<7>.
WARNING:Xst:2183 - Unit Lswitch: the following tristate(s) are NOT replaced by logic (Please refer to Answer Record 20048 for more information): outDATA<0>, outDATA<1>, outDATA<2>, outDATA<3>, outDATA<4>, outDATA<5>, outDATA<6>, outDATA<7>.
Optimizing unit <U21> ...
implementation constraint: KEEP : U2_Enable_AD
Optimizing unit <U21AddDecode> ...
Optimizing unit <PWMtranslator> ...
Optimizing unit <Lswitch> ...
Optimizing unit <I2CAddress> ...
Optimizing unit <NegDetect> ...
Optimizing unit <PWMcontrol> ...
Optimizing unit <Interrupt> ...
Optimizing unit <PWRreg> ...
Optimizing unit <Sensor> ...
Optimizing unit <MISCouts> ...
Optimizing unit <Holdreg> ...
implementation constraint: KEEP : interDATA<7>
implementation constraint: KEEP : interDATA<6>
implementation constraint: KEEP : interDATA<5>
implementation constraint: KEEP : interDATA<4>
implementation constraint: KEEP : interDATA<3>
implementation constraint: KEEP : interDATA<2>
implementation constraint: KEEP : interDATA<1>
implementation constraint: KEEP : interDATA<0>
Optimizing unit <HomeConfig> ...
Optimizing unit <low_pass_filter> ...
Optimizing unit <Counter> ...
Optimizing unit <Decode> ...
Optimizing unit <Servos> ...
=========================================================================
* Partition Report *
=========================================================================
Partition Implementation Status
-------------------------------
No Partitions were found in this design.
-------------------------------
=========================================================================
* Final Report *
=========================================================================
Final Results
RTL Top Level Output File Name : U21.ngr
Top Level Output File Name : U21
Output Format : NGC
Optimization Goal : area
Keep Hierarchy : yes
Target Technology : xcr3384xlTQ144-7
Macro Preserve : yes
XOR Preserve : yes
Clock Enable : yes
wysiwyg : no
Design Statistics
# IOs : 90
Cell Usage :
# BELS : 1748
# AND2 : 707
# AND3 : 34
# AND4 : 7
# GND : 8
# INV : 624
# OR2 : 293
# OR3 : 27
# OR4 : 11
# VCC : 1
# XOR2 : 36
# FlipFlops/Latches : 222
# FD : 60
# FDCE : 162
# Tri-States : 56
# BUFE : 56
# IO Buffers : 90
# IBUF : 43
# IOBUFE : 9
# OBUF : 38
=========================================================================
Total REAL time to Xst completion: 5.00 secs
Total CPU time to Xst completion: 4.33 secs
-->
Total memory usage is 121540 kilobytes
Number of errors : 0 ( 0 filtered)
Number of warnings : 34 ( 0 filtered)
Number of infos : 4 ( 0 filtered)
WARNING:NetListWriters:306 - Signal bus location_Madd__add0000_CARRY_IN[13 : 4]
on block Counter_INST_1 is not reconstructed, because there are some missing
bus signals.
WARNING:NetListWriters:306 - Signal bus location_Madd__add0000_CARRY_IN[13 : 4]
on block Counter is not reconstructed, because there are some missing bus
signals.
WARNING:NetListWriters:306 - Signal bus sensorr[2 : 0] on block Sensor is not
reconstructed, because there are some missing bus signals.
WARNING:NetListWriters:306 - Signal bus Flgreg[7 : 0] on block PWRreg is not
reconstructed, because there are some missing bus signals.
WARNING:NetListWriters:306 - Signal bus ctrlr[7 : 0] on block PWRreg is not
reconstructed, because there are some missing bus signals.
WARNING:NetListWriters:306 - Signal bus DCORIE[7 : 0] on block Interrupt is not
reconstructed, because there are some missing bus signals.
WARNING:NetListWriters:306 - Signal bus outDATA_mux0000[6 : 0] on block Lswitc
h
is not reconstructed, because there are some missing bus signals.
INFO:NetListWriters:633 - The generated Verilog netlist contains Xilinx UNISIM
simulation primitives and has to be used with UNISIM simulation library for
correct compilation and simulation.
INFO:NetListWriters - Setup Simulation - To perform a setup simulation, specify
values in the Maximum (MAX) field with the following command line modifier:
-SDFMAX
INFO:NetListWriters - Hold Simulation - To perform the most accurate hold
simulation, specify values in the Minimum (MIN) field with the following
command line modifier: -SDFMIN
INFO:NetListWriters:665 - For more information on how to pass the SDF switches
to the simulator, see your Simulator tool documentation.
Synthesis finished with 41 warning(s).