//-----------------------------------------------------------------------------
//
// Title       : PWMcontrol
// Design      : Core
// Author      : mbari###
// Company     : MBARI
//
//-----------------------------------------------------------------------------
//
// File        : E:\ESP\dwarf_fpgas\core\compile\pwmcontrol.v
// Generated   : Mon Mar  9 09:01:53 2009
// From        : E:\ESP\dwarf_fpgas\core\src\pwmcontrol.bde
// By          : Bde2Verilog ver. 2.01
//
//-----------------------------------------------------------------------------
//
// Description : 
//
//-----------------------------------------------------------------------------

`ifdef _VCP
`else
`define library(a,b)
`endif


// ---------- Design Unit Header ---------- //
`timescale 1ns / 1ns

module PWMcontrol (Brake1,Brake2,DIR1,DIR2,FLS0,FLS1,HBRK1,HBRK2,MTRpwr,PWM1,
PWM2,RLS0,RLS1,fBRK1,fBRK2,PAH1,PAH2,PAL1,PAL2,PBH1,
PBH2,PBL1,PBL2) ;

// ------------ Port declarations --------- //
input Brake1;
wire Brake1;
input Brake2;
wire Brake2;
input DIR1;
wire DIR1;
input DIR2;
wire DIR2;
input FLS0;
wire FLS0;
input FLS1;
wire FLS1;
input HBRK1;
wire HBRK1;
input HBRK2;
wire HBRK2;
input MTRpwr;
wire MTRpwr;
input PWM1;
wire PWM1;
input PWM2;
wire PWM2;
input RLS0;
wire RLS0;
input RLS1;
wire RLS1;
input fBRK1;
wire fBRK1;
input fBRK2;
wire fBRK2;
output PAH1;
wire PAH1;
output PAH2;
wire PAH2;
output PAL1;
wire PAL1;
output PAL2;
wire PAL2;
output PBH1;
wire PBH1;
output PBH2;
wire PBH2;
output PBL1;
wire PBL1;
output PBL2;
wire PBL2;

// -------- Component instantiations -------//

PWMtranslator U1
(
	.Brake(Brake1),
	.DIR(DIR1),
	.FLS(FLS0),
	.HBRK(HBRK1),
	.MTRpwr(MTRpwr),
	.PAH(PAH1),
	.PAL(PAL1),
	.PBH(PBH1),
	.PBL(PBL1),
	.PWM(PWM1),
	.RLS(RLS0),
	.fBRK(fBRK1)
);



PWMtranslator U2
(
	.Brake(Brake2),
	.DIR(DIR2),
	.FLS(FLS1),
	.HBRK(HBRK2),
	.MTRpwr(MTRpwr),
	.PAH(PAH2),
	.PAL(PAL2),
	.PBH(PBH2),
	.PBL(PBL2),
	.PWM(PWM2),
	.RLS(RLS1),
	.fBRK(fBRK2)
);



endmodule