//-----------------------------------------------------------------------------
//
// Title       : U4 TestBench
// Design      : Core
// Author      : mbari###
// Company     : MBARI
//
//-----------------------------------------------------------------------------
//
// File        : E:\ESP\dwarf_fpgas\core\compile\u21_tb.v
// Generated   : Mon Mar  9 09:02:01 2009
// From        : E:\ESP\dwarf_fpgas\core\src\testbench\u21_tb.bde
// By          : Bde2Verilog ver. 2.01
//
//-----------------------------------------------------------------------------
//
// Description : 
//
//-----------------------------------------------------------------------------

`ifdef _VCP
`else
`define library(a,b)
`endif


// ---------- Design Unit Header ---------- //
`timescale 1ns / 1ns

module U4_TB (Enc15FLG,FLS1,FLS2,Home1,Home15FLG,Home2,PhaseA_Encoder1,PhaseB_Encoder1,RLS1,RLS2,
Reset,SCL,SCLinc,SCLreset,Enc15ctrl,Home15ctrl) ;

// ------------ Port declarations --------- //
input Enc15FLG;
wire Enc15FLG;
input FLS1;
wire FLS1;
input FLS2;
wire FLS2;
input Home1;
wire Home1;
input Home15FLG;
wire Home15FLG;
input Home2;
wire Home2;
input PhaseA_Encoder1;
wire PhaseA_Encoder1;
input PhaseB_Encoder1;
wire PhaseB_Encoder1;
input RLS1;
wire RLS1;
input RLS2;
wire RLS2;
input Reset;
wire Reset;
input SCL;
wire SCL;
input SCLinc;
wire SCLinc;
input SCLreset;
wire SCLreset;
output Enc15ctrl;
wire Enc15ctrl;
output Home15ctrl;
wire Home15ctrl;

// ----------------- Constants ------------ //
parameter DANGLING_INPUT_CONSTANT = 1'bZ;

// ----------- Signal declarations -------- //
wire AS;
wire Mclk;
wire RD;
wire WR;
wire [7:0] AD;

// ---- Declaration for Dangling inputs ----//
wire Dangling_Input_Signal = DANGLING_INPUT_CONSTANT;

// -------- Component instantiations -------//

// synopsys translate_off
`library("U1","Core")
// synopsys translate_on
Fub24 U1
(
	.AD(AD),
	.AS(AS),
	.Brake0(Dangling_Input_Signal),
	.Brake1(Dangling_Input_Signal),
	.DIR0(Dangling_Input_Signal),
	.DIR1(Dangling_Input_Signal),
	.Enc05FLG(Dangling_Input_Signal),
	.Enc05ctrl(),
	.Enc15FLG(Enc15FLG),
	.Enc15ctrl(Enc15ctrl),
	.FLS0(Dangling_Input_Signal),
	.FLS1(FLS1),
	.GPIO10(),
	.GPIO8(),
	.GPIO9(),
	.GP_Motor0_0(Dangling_Input_Signal),
	.GP_Motor0_1(),
	.GP_Motor1_0(Dangling_Input_Signal),
	.GP_Motor1_1(),
	.Home0(Dangling_Input_Signal),
	.Home05FLG(Dangling_Input_Signal),
	.Home05ctrl(),
	.Home1(Home1),
	.Home15FLG(Home15FLG),
	.Home15ctrl(Home15ctrl),
	.I2CS({6{Dangling_Input_Signal}}),
	.INT(),
	.INTbus(Dangling_Input_Signal),
	.LED1(),
	.LED2(),
	.LED3(),
	.LED4(),
	.LED5(),
	.Latch033FLG(Dangling_Input_Signal),
	.Latch033ctrl(),
	.Latch133FLG(Dangling_Input_Signal),
	.Latch133ctrl(),
	.LightSense(Dangling_Input_Signal),
	.MReset(Dangling_Input_Signal),
	.MSPReset(Reset),
	.MTRpwr(),
	.MTRpwrn(),
	.Mclk(Mclk),
	.PAH0(),
	.PAH1(),
	.PAL0(),
	.PAL1(),
	.PBH0(),
	.PBH1(),
	.PBL0(),
	.PBL1(),
	.PWM1(Dangling_Input_Signal),
	.PWM2(Dangling_Input_Signal),
	.PWM3(Dangling_Input_Signal),
	.PWM4(Dangling_Input_Signal),
	.PWM5(Dangling_Input_Signal),
	.PhaseA_Encoder0(Dangling_Input_Signal),
	.PhaseA_Encoder1(PhaseA_Encoder1),
	.PhaseB_Encoder0(Dangling_Input_Signal),
	.PhaseB_Encoder1(PhaseB_Encoder1),
	.PresEn(),
	.PresSlct(),
	.RD(RD),
	.RLS0(Dangling_Input_Signal),
	.RLS1(RLS1),
	.SCL(SCL),
	.SCLinc(SCLinc),
	.SCLreset(SCLreset),
	.TP12(),
	.TP21(),
	.TP26(),
	.TmpEn(),
	.TmpSlct(),
	.WR(WR)
);



// synopsys translate_off
`library("U2","Core")
// synopsys translate_on
Fub23 U2
(
	.AD(AD),
	.AS(AS),
	.Mclk(Mclk),
	.RD(RD),
	.WR(WR)
);



endmodule