[AHDL]
Type=Implementation
Handle=657064
Project=E:\ESP\dwarf_fpgas\core\Core.adf
[Xilinx]
Path=C:\Xilinx\10.1\ISE\bin\nt
[GUI]
AutoClose=0
[ChipScope]
InserterEnable=0
InserterGuiEnable=1
NetlistMergingEnable=1
InserterProjectPath=E:/ESP/dwarf_fpgas/core/synthesis/U21.cdc
UseInserterBat=0
BinariesFolder=bin/nt
[Design.PartSelector]
Family=COOLRUNNER
Device=r3384xlTQ144
Speed=-7
Part=r3384xlTQ144-7
[Design.Input]
Netlist=E:\ESP\dwarf_fpgas\core\synthesis\U21.ngc
UCF=E:\ESP\dwarf_fpgas\core\constraints\core.ucf
OutputPath=E:\ESP\dwarf_fpgas\core\implement
StdOutputFile=E:\ESP\dwarf_fpgas\core\log\implementation.htm
Version=ver1
Revision=rev1
Format=Verilog
EffortLevel=2
InputTristateTermMode=Keeper
UnusedIOPadTermMode=Keeper
Mode=batch
SDF_path=E:/ESP/dwarf_fpgas/core/implement
Corelate=1
ExeName=ise.exe
ImplToolName=MV_ISE101
SynthToolName=MV_XST101
DirectoryList={E:\ESP\dwarf_fpgas\core\synthesis} {E:\ESP\dwarf_fpgas\core\compile} {E:\ESP\dwarf_fpgas\core\src} {C:\Program Files\Aldec\Active-HDL 8.1\vlib\XC9500\compile}
DestinationPath=E:\ESP\dwarf_fpgas\core\implement
SynthesisPath=E:\ESP\dwarf_fpgas\core\synthesis
ClbPackingStrategy=100
PackClbRegisters=0
UseBufg=0
IgnoreRlocConstr=1
DetailedReport=0
dont_run_translate=0
dont_run_map=0
dont_run_place=0
dont_run_trace=0
dont_run_post_map_trace=0
dont_run_simulation=0
dont_run_fit=0
dont_run_bitgen=0
use_ngdbuild_file=0
use_par_file=0
use_map_file=0
use_post_map_file=0
use_trace_file=0
use_netgen_file=0
use_cpld_ndg2vhdl_file=0
use_cgsm_ndg2vhdl_file=0
use_bitgen_file=0
use_use_cpldfit_file=0
use_hprep6_file=0
use_tsim_file=0
DoCopyGlblFile=1
[Engine.Command]
Command=Implement
[Ngdbuild]
Switches= 
[Cpldfit]
Switches=  -loc on  -slew fast  -init low  -unused pullup  -terminate float  -optimize density  -nofbnand  -inputs  32  -pterms  28  -inreg on  -blkfanin  38 
[CPLDNetgenGeneral]
Switches= 
[CPLDNetgenVerilog]
Switches=  -sdf_anno true  -sdf_path  E:/ESP/dwarf_fpgas/core/implement  -insert_glbl true 
[CPLDBitgen]
Switches= 
[Engine.Implement.Output]
Changed=0
Stage=Bitstream
State=OK
Netlist=E:/ESP/DWARF_FPGAS/CORE/IMPLEMENT/TIME_SIM.V
SDF=E:/ESP/dwarf_fpgas/core/implement/time_sim.sdf
Abort=NO
Errors=0
Warnings=56
Status=Warning
[Engine.Reports.Output]
Path=E:/ESP/dwarf_fpgas/core/implement/ver1/rev1
Files=U21.bld U21.rpt implementation.htm
Names=Translation Fitting {Implement Log}