 
cpldfit:  version K.39                              Xilinx Inc.
                                  Fitter Report
Design Name: U21                                 Date:  3- 9-2009, 10:15AM
Device Used: XCR3384XL-7-TQ144
Fitting Status: Successful

*************************  Mapped Resource Summary  **************************

Macrocells     Product Terms    Function Block   Registers      Pins           
Used/Tot       Used/Tot         Inps Used/Tot    Used/Tot       Used/Tot       
293/384 ( 76%) 715 /1152 ( 62%) 742 /960  ( 77%) 197/384 ( 51%) 86 /114 ( 75%)

** Function Block Resources **

Function  Mcells    FB Inps   Pterms    IO        GCK       
Block     Used/Tot  Used/Tot  Used/Tot  Used/Tot  Used/Tot  
FB1        16/16*    33/40     48/48*    1/ 4      1/2
FB2        16/16*    38/40*    48/48*    0/ 6      1/2
FB3        16/16*    24/40     30/48     4/ 4*     1/2
FB4        16/16*    33/40     47/48     2/ 6      1/2
FB5        16/16*    36/40     30/48     4/ 4*     1/2
FB6        16/16*    19/40     40/48     0/ 2      1/2
FB7        15/16     37/40     37/48     5/ 5*     1/2
FB8         7/16     38/40*    26/48     2/ 2*     1/2
FB9         7/16     38/40*    26/48     1/ 2      1/2
FB10        7/16     38/40*    26/48     3/ 3*     0/2
FB11       16/16*    19/40     45/48     0/ 1      1/2
FB12        5/16     38/40*    27/48     4/ 4*     0/2
FB13       16/16*    24/40     45/48     0/ 4      1/2
FB14       11/16     38/40*    26/48     1/ 4      1/2
FB15       15/16     38/40*    31/48     1/ 2      1/2
FB16       13/16     38/40*    29/48     0/ 2      1/2
FB17       16/16*    33/40     31/48     1/ 1*     1/2
FB18       14/16     38/40*    26/48     3/ 5      1/2
FB19       11/16     37/40     27/48     4/ 4*     1/2
FB20       16/16*    33/40     28/48     1/ 2      1/2
FB21       16/16*    29/40     20/48     2/ 6      1/2
FB22        6/16     11/40     10/48     0/ 5      0/2
FB23        1/16     11/40      2/48     1/ 2      1/2
FB24        5/16     21/40     10/48     3/ 6      1/2
           -----    -------   -------    -----
Total     293/384   742/960   715/1152  43/86 

* - Resource is exhausted

** Local Control Term Resources **

        LCT0     LCT1     LCT2     LCT3     LCT4     LCT5     LCT6     LCT7
FB1                                                                             
FB2                                                                    uct2     
FB3                                                                    uct3     
FB4     oe                                                             uct4     
FB5                                                                             
FB6                                                                             
FB7     sr                                  ce                                  
FB8                                                                             
FB9                                                                             
FB10                                                                            
FB11                                                                            
FB12                                                                            
FB13                                                                            
FB14                                        ce                                  
FB15                                                                            
FB16                                                                            
FB17                                                                            
FB18                                                                            
FB19    sr                                                                      
FB20                                                                            
FB21                                        ce                                  
FB22                                                                            
FB23                                        ce                                  
FB24                                        ce                                  

Legend:
ce   - clock enable
clk  - clock
oe   - output enable
sr   - set/reset
uct1 - universal control term clock
uct2 - universal control term output enable
uct3 - universal control term preset
uct4 - universal control term reset
LCT0 - oe and/or sr can be mapped to this local control term
LCT1 - oe and/or sr can be mapped to this local control term
LCT2 - oe and/or sr can be mapped to this local control term
LCT3 - sr can be mapped to this local control term
LCT4 - ce and/or clk and/or sr can be mapped to this local control term
LCT5 - clk and/or sr can be mapped to this local control term
LCT6 - clk and/or oe can be mapped to this local control term
LCT7 - clk can be mapped to this local control term

** Global Control Resources **

GCK         UCLK        UOE         UPST        URST        
Used/Tot    Used/Tot    Used/Tot    Used/Tot    Used/Tot
1/4         0/1         1/1         1/1         1/1

GCK  - Global Clock
UCLK - Universal Control Term Clock
UOE  - Universal Control Term Output Enable
UPST - Universal Control Term Preset
URST - Universal Control Term Reset

Signal 'Mclk' mapped onto global clock net GCK1.

** Pin Resources **

Signal Type    Required     Mapped  |  Pin Type            Used     Total 
------------------------------------|-------------------------------------
Input         :   42          42    |  I/O              :    85      110
Output        :   34          34    |  GCK/I            :     1        4
Bidirectional :    9           9    |  
GCK           :    1           1    |  
                 ----        ----
        Total    86           86 

End of Mapped Resource Summary
**************************  Errors and Warnings  ***************************

INFO:Cpld - Inferring BUFG constraint for signal 'Mclk' based upon the LOC
   constraint 'P127'. It is recommended that you declare this BUFG explicitedly
   in your design. Note that for certain device families the output of a BUFG
   constraint can not drive a gated clock, and the BUFG constraint will be
   ignored.
WARNING:Cpld:987 - An internal tristate buffer 'outDATA<0>\$WA4' is detected. 
   The logic is being translated to a mux implementation.
WARNING:Cpld:987 - An internal tristate buffer 'outDATA<5>\$WA3' is detected. 
   The logic is being translated to a mux implementation.
WARNING:Cpld:987 - An internal tristate buffer 'outDATA<4>\$WA3' is detected. 
   The logic is being translated to a mux implementation.
WARNING:Cpld:987 - An internal tristate buffer 'outDATA<3>\$WA3' is detected. 
   The logic is being translated to a mux implementation.
WARNING:Cpld:987 - An internal tristate buffer 'outDATA<2>\$WA3' is detected. 
   The logic is being translated to a mux implementation.
WARNING:Cpld:987 - An internal tristate buffer 'outDATA<1>\$WA3' is detected. 
   The logic is being translated to a mux implementation.
WARNING:Cpld:987 - An internal tristate buffer 'outDATA<0>\$WA3' is detected. 
   The logic is being translated to a mux implementation.
WARNING:Cpld:987 - An internal tristate buffer 'outDATA<7>\$WA3' is detected. 
   The logic is being translated to a mux implementation.
WARNING:Cpld:987 - An internal tristate buffer 'outDATA<6>\$WA3' is detected. 
   The logic is being translated to a mux implementation.
WARNING:Cpld:987 - An internal tristate buffer 'outDATA<6>\$WA2' is detected. 
   The logic is being translated to a mux implementation.
WARNING:Cpld:987 - An internal tristate buffer 'outDATA<2>\$WA2' is detected. 
   The logic is being translated to a mux implementation.
WARNING:Cpld:987 - An internal tristate buffer 'outDATA<0>\$WA5' is detected. 
   The logic is being translated to a mux implementation.
WARNING:Cpld:987 - An internal tristate buffer 'outDATA<2>\$WA5' is detected. 
   The logic is being translated to a mux implementation.
WARNING:Cpld:987 - An internal tristate buffer 'outDATA<3>\$WA5' is detected. 
   The logic is being translated to a mux implementation.
WARNING:Cpld:987 - An internal tristate buffer 'outDATA<4>\$WA5' is detected. 
   The logic is being translated to a mux implementation.
WARNING:Cpld:987 - An internal tristate buffer 'outDATA<5>\$WA5' is detected. 
   The logic is being translated to a mux implementation.
WARNING:Cpld:987 - An internal tristate buffer 'outDATA<6>\$WA5' is detected. 
   The logic is being translated to a mux implementation.
WARNING:Cpld:987 - An internal tristate buffer 'outDATA<7>\$WA5' is detected. 
   The logic is being translated to a mux implementation.
WARNING:Cpld:987 - An internal tristate buffer 'outDATA<0>\$WA1' is detected. 
   The logic is being translated to a mux implementation.
WARNING:Cpld:987 - An internal tristate buffer 'outDATA<1>\$WA1' is detected. 
   The logic is being translated to a mux implementation.
WARNING:Cpld:987 - An internal tristate buffer 'outDATA<2>\$WA1' is detected. 
   The logic is being translated to a mux implementation.
WARNING:Cpld:987 - An internal tristate buffer 'outDATA<3>\$WA1' is detected. 
   The logic is being translated to a mux implementation.
WARNING:Cpld:987 - An internal tristate buffer 'outDATA<4>\$WA1' is detected. 
   The logic is being translated to a mux implementation.
WARNING:Cpld:987 - An internal tristate buffer 'outDATA<5>\$WA1' is detected. 
   The logic is being translated to a mux implementation.
WARNING:Cpld:987 - An internal tristate buffer 'outDATA<6>\$WA1' is detected. 
   The logic is being translated to a mux implementation.
WARNING:Cpld:987 - An internal tristate buffer 'outDATA<7>\$WA1' is detected. 
   The logic is being translated to a mux implementation.
WARNING:Cpld:987 - An internal tristate buffer 'outDATA<4>\$WA4' is detected. 
   The logic is being translated to a mux implementation.
WARNING:Cpld:987 - An internal tristate buffer 'outDATA<7>\$WA4' is detected. 
   The logic is being translated to a mux implementation.
WARNING:Cpld:987 - An internal tristate buffer 'outDATA<3>\$WA2' is detected. 
   The logic is being translated to a mux implementation.
WARNING:Cpld:987 - An internal tristate buffer 'outDATA<7>\$WA2' is detected. 
   The logic is being translated to a mux implementation.
WARNING:Cpld:987 - An internal tristate buffer 'outDATA<0>\$WA6' is detected. 
   The logic is being translated to a mux implementation.
WARNING:Cpld:987 - An internal tristate buffer 'outDATA<1>\$WA6' is detected. 
   The logic is being translated to a mux implementation.
WARNING:Cpld:987 - An internal tristate buffer 'outDATA<2>\$WA6' is detected. 
   The logic is being translated to a mux implementation.
WARNING:Cpld:987 - An internal tristate buffer 'outDATA<3>\$WA6' is detected. 
   The logic is being translated to a mux implementation.
WARNING:Cpld:987 - An internal tristate buffer 'outDATA<4>\$WA6' is detected. 
   The logic is being translated to a mux implementation.
WARNING:Cpld:987 - An internal tristate buffer 'outDATA<5>\$WA6' is detected. 
   The logic is being translated to a mux implementation.
WARNING:Cpld:987 - An internal tristate buffer 'outDATA<6>\$WA6' is detected. 
   The logic is being translated to a mux implementation.
WARNING:Cpld:987 - An internal tristate buffer 'outDATA<7>\$WA6' is detected. 
   The logic is being translated to a mux implementation.
WARNING:Cpld:987 - An internal tristate buffer 'outDATA<2>\$WA0' is detected. 
   The logic is being translated to a mux implementation.
WARNING:Cpld:987 - An internal tristate buffer 'outDATA<3>\$WA0' is detected. 
   The logic is being translated to a mux implementation.
WARNING:Cpld:987 - An internal tristate buffer 'outDATA<5>\$WA0' is detected. 
   The logic is being translated to a mux implementation.
WARNING:Cpld:987 - An internal tristate buffer 'outDATA<6>\$WA0' is detected. 
   The logic is being translated to a mux implementation.
WARNING:Cpld:987 - An internal tristate buffer 'outDATA<0>\$WA0' is detected. 
   The logic is being translated to a mux implementation.
WARNING:Cpld:987 - An internal tristate buffer 'outDATA<1>\$WA0' is detected. 
   The logic is being translated to a mux implementation.
WARNING:Cpld:987 - An internal tristate buffer 'outDATA<4>\$WA0' is detected. 
   The logic is being translated to a mux implementation.
WARNING:Cpld:987 - An internal tristate buffer 'outDATA<7>\$WA0' is detected. 
   The logic is being translated to a mux implementation.
WARNING:Cpld:987 - An internal tristate buffer 'outDATA<1>\$WA5' is detected. 
   The logic is being translated to a mux implementation.
WARNING:Cpld:987 - An internal tristate buffer 'outDATA<0>\$WA2' is detected. 
   The logic is being translated to a mux implementation.
WARNING:Cpld:987 - An internal tristate buffer 'outDATA<1>\$WA2' is detected. 
   The logic is being translated to a mux implementation.
WARNING:Cpld:987 - An internal tristate buffer 'outDATA<4>\$WA2' is detected. 
   The logic is being translated to a mux implementation.
WARNING:Cpld:987 - An internal tristate buffer 'outDATA<5>\$WA2' is detected. 
   The logic is being translated to a mux implementation.
WARNING:Cpld:987 - An internal tristate buffer 'outDATA<3>\$WA4' is detected. 
   The logic is being translated to a mux implementation.
WARNING:Cpld:987 - An internal tristate buffer 'outDATA<2>\$WA4' is detected. 
   The logic is being translated to a mux implementation.
WARNING:Cpld:987 - An internal tristate buffer 'outDATA<1>\$WA4' is detected. 
   The logic is being translated to a mux implementation.
WARNING:Cpld:987 - An internal tristate buffer 'outDATA<6>\$WA4' is detected. 
   The logic is being translated to a mux implementation.
WARNING:Cpld:987 - An internal tristate buffer 'outDATA<5>\$WA4' is detected. 
   The logic is being translated to a mux implementation.
*************************  Summary of Mapped Logic  ************************

** 43 Outputs **

Signal                          Total Total Loc     Pin   Pin       Pin     Slew Reg Init
Name                            Pts   Inps          No.   Type      Use     Rate State
TP21                            3     13    FB1_16  91    I/O       O       FAST RESET
PBL0                            2     5     FB3_4   90    I/O       O       FAST 
PBH0                            1     6     FB3_5   89    I/O       O       FAST 
PAL0                            2     5     FB3_14  88    I/O       O       FAST 
PAH0                            1     6     FB3_16  87    I/O       O       FAST 
INT                             8     16    FB4_13  112   I/O       O       FAST 
SCL                             1     1     FB4_15  114   I/O       I/O     FAST RESET
PBL1                            2     5     FB5_5   84    I/O       O       FAST 
PBH1                            1     6     FB5_14  83    I/O       O       FAST 
PAL1                            2     5     FB5_15  82    I/O       O       FAST 
PAH1                            1     6     FB5_16  81    I/O       O       FAST 
MTRpwrn                         4     14    FB7_1   80    I/O       O       FAST SET
LED5                            1     2     FB7_2   79    I/O       O       FAST 
LED4                            1     2     FB7_3   78    I/O       O       FAST 
LED3                            1     2     FB7_4   77    I/O       O       FAST 
LED2                            1     2     FB7_15  75    I/O       O       FAST 
GP_Motor0_1                     4     13    FB8_2   71    I/O       O       FAST RESET
LED1                            1     2     FB8_16  74    I/O       O       FAST 
AD<7>                           8     18    FB9_1   122   I/O       I/O     FAST 
AD<6>                           7     18    FB10_4  132   I/O       I/O     FAST 
AD<5>                           7     18    FB10_15 133   I/O       I/O     FAST 
AD<4>                           8     18    FB10_16 134   I/O       I/O     FAST 
AD<0>                           8     18    FB12_1  139   I/O       I/O     FAST 
AD<1>                           8     17    FB12_3  138   I/O       I/O     FAST 
AD<2>                           7     18    FB12_4  137   I/O       I/O     FAST 
AD<3>                           7     18    FB12_13 136   I/O       I/O     FAST 
Home05ctrl                      3     11    FB14_16 43    I/O       O       FAST SET
GP_Motor1_1                     4     13    FB15_5  56    I/O       O       FAST RESET
GPIO8                           1     1     FB17_3  6     I/O       O       FAST 
GPIO9                           1     2     FB18_1  7     I/O       O       FAST 
GPIO10                          1     2     FB18_2  8     I/O       O       FAST 
MTRpwr                          4     13    FB18_15 11    I/O       O       FAST RESET
PresSlct                        4     13    FB19_2  143   I/O       O       FAST RESET
TmpSlct                         4     13    FB19_4  142   I/O       O       FAST RESET
TmpEn                           4     14    FB19_5  141   I/O       O       FAST SET
PresEn                          4     14    FB19_15 140   I/O       O       FAST SET
TP12                            1     6     FB20_1  14    I/O       O       FAST 
Home15ctrl                      3     11    FB21_13 40    I/O       O       FAST SET
Latch133ctrl                    3     11    FB21_15 38    I/O       O       FAST SET
Latch033ctrl                    3     11    FB23_1  36    I/O       O       FAST SET

Signal                          Total Total Loc     Pin   Pin       Pin     Slew Reg Init
Name                            Pts   Inps          No.   Type      Use     Rate State
Enc15ctrl                       3     11    FB24_2  27    I/O       O       FAST SET
Enc05ctrl                       3     11    FB24_5  30    I/O       O       FAST SET
TP26                            5     17    FB24_16 34    I/O       O       FAST RESET

** 250 Buried Nodes **

Signal                          Total Total Loc     Reg Init
Name                            Pts   Inps          State
N_PZ_1030                       2     10    FB1_1   
U3/DCORIE<2>                    3     13    FB1_2   RESET
U3/DCORIE<1>                    3     13    FB1_3   RESET
U1/U4/LatchEdge0r               3     13    FB1_4   RESET
N_PZ_1202                       2     11    FB1_5   
U9/MISCr<2>                     4     13    FB1_6   RESET
U1/U4/latchitH0                 3     17    FB1_7   RESET
NET2482                         7     17    FB1_8   RESET
U1/U4/E0r                       3     13    FB1_9   RESET
U9/MISCr<1>                     4     13    FB1_10  RESET
U3/DCORIE<0>                    3     13    FB1_11  RESET
U1/U4/RF0r                      3     13    FB1_12  RESET
NET2528                         4     14    FB1_13  RESET
U9/MISCr<0>                     4     13    FB1_14  RESET
U1/U4/E1r                       3     13    FB1_15  RESET
NET2512                         3     17    FB2_1   RESET
N_PZ_1203                       2     5     FB2_2   
U9/MISCr<3>                     4     13    FB2_3   RESET
U1/TP                           3     13    FB2_4   RESET
N_PZ_1195                       2     5     FB2_5   
NET2575                         4     17    FB2_6   RESET
U3/DCORIE<4>                    3     13    FB2_7   RESET
U1/U4/latchitH1                 3     17    FB2_8   RESET
NET2493                         8     17    FB2_9   RESET
U1/U4/RF1r                      3     13    FB2_10  RESET
U9/MISCr<4>                     4     13    FB2_11  RESET
U3/DCORIE<3>                    3     13    FB2_12  RESET
U2_Enable_AD                    1     6     FB2_13  
U3/DCORIE<6>                    3     13    FB2_14  RESET
U1/U4/LatchEdge1r               3     13    FB2_15  RESET
U1/U4/latchitL1                 3     16    FB2_16  RESET
N_PZ_1314                       1     3     FB3_1   
U5/RLS1r                        1     2     FB3_2   RESET
U5/RLS1fr                       2     3     FB3_3   RESET
NET3253                         5     9     FB3_6   RESET
U5/FLS1fr                       2     5     FB3_7   RESET
U5/FLS1r                        1     2     FB3_8   RESET
U5/RLS0r                        1     2     FB3_9   RESET
U5/FLS0r                        1     2     FB3_10  RESET
N_PZ_1313                       1     3     FB3_11  

Signal                          Total Total Loc     Reg Init
Name                            Pts   Inps          State
U5/RLS0fr                       2     3     FB3_12  RESET
U5/FLS0fr                       2     5     FB3_13  RESET
NET3248                         5     9     FB3_15  RESET
U4/Flgreg<6>                    1     3     FB4_1   RESET
outDATA<0>\$WA1.UIM             1     1     FB4_2   
outDATA<7>\$WA4.UIM             1     1     FB4_3   
U11_ResetDetect                 1     2     FB4_4   RESET
U2_ASedge                       0     0     FB4_5   RESET
U11_Incdetect                   1     2     FB4_6   RESET
N_PZ_1142                       3     6     FB4_7   
U11_U3_counterr<2>              3     6     FB4_8   RESET
U11_U3_counterr<5>              4     9     FB4_9   RESET
U11_U3_counterr<4>              4     8     FB4_10  RESET
U11_U3_counterr<3>              7     8     FB4_11  RESET
U11_U3_counterr<1>              4     7     FB4_12  RESET
outDATA<6>\$WA5.UIM             1     2     FB4_14  
U11_U3_counterr<0>              6     7     FB4_16  RESET
U2_WRRDedge_and0000             1     2     FB5_1   
outDATA<7>\$WA2.UIM             1     1     FB5_2   
U2_WRRDedge                     1     2     FB5_3   RESET
N_PZ_1216                       2     4     FB5_4   
N_PZ_1029                       1     4     FB5_6   
outDATA<5>\$WA0.UIM             6     18    FB5_7   
U3/DCORIE<7>                    3     13    FB5_8   RESET
U1/NET3720                      3     13    FB5_9   RESET
U1/U4/latchitL0                 3     16    FB5_10  RESET
U1/U4/LastEdge0r                1     1     FB5_11  RESET
U1/U4/HE1statelastr             1     1     FB5_12  RESET
U1/U4/HE0statelastr             1     1     FB5_13  RESET
U1/U4/LastEdge1r                1     1     FB6_1   RESET
U1/Channel0<11>                 3     15    FB6_2   RESET
U1/Channel0<10>                 3     14    FB6_3   RESET
U1/Channel0<9>                  3     13    FB6_4   RESET
U1/Channel0<8>                  3     12    FB6_5   RESET
U1/Channel0<7>                  3     11    FB6_6   RESET
U1/Channel0<6>                  3     10    FB6_7   RESET
U1/Channel0<5>                  3     9     FB6_8   RESET
U1/Channel0<4>                  3     8     FB6_9   RESET
U1/Channel0<3>                  3     7     FB6_10  RESET
U1/Channel0<2>                  3     6     FB6_11  RESET

Signal                          Total Total Loc     Reg Init
Name                            Pts   Inps          State
U1/Channel0<1>                  3     5     FB6_12  RESET
U1/Channel0<0>                  2     3     FB6_13  RESET
U11_SCLdetect                   1     2     FB6_14  RESET
U1/Channel0<12>                 3     16    FB6_15  RESET
U1/U4/InEdge0r                  0     0     FB6_16  RESET
outDATA<7>\$WA1.UIM             0     0     FB7_6   
outDATA<6>\$WA1.UIM             0     0     FB7_7   
N_PZ_1001                       2     3     FB7_8   
U2_AutoInc                      2     3     FB7_9   RESET
U2_ADDR_reg<5>                  3     6     FB7_10  RESET
outDATA<2>\$WA0.UIM             6     18    FB7_11  
U2_ADDR_reg<0>                  4     13    FB7_12  RESET
U2_ADDR_reg<1>                  4     14    FB7_13  RESET
U2_ADDR_reg<2>                  4     15    FB7_14  RESET
U2_ADDR_reg<3>                  4     16    FB7_16  RESET
outDATA<3>\$WA0.UIM             6     18    FB8_1   
outDATA<6>\$WA0.UIM             6     18    FB8_3   
U1/Channel1<0>                  2     3     FB8_13  RESET
outDATA<1>\$WA0.UIM             4     10    FB8_14  
outDATA<0>\$WA0.UIM             4     10    FB8_15  
outDATA<1>\$WA5.UIM             3     8     FB9_3   
U11_U4/Line_last                0     0     FB9_5   RESET
outDATA<3>\$WA6.UIM             4     10    FB9_13  
outDATA<2>\$WA6.UIM             4     10    FB9_14  
outDATA<1>\$WA6.UIM             4     10    FB9_15  
outDATA<0>\$WA6.UIM             4     10    FB9_16  
outDATA<4>\$WA0.UIM             4     10    FB10_3  
outDATA<0>\$WA4.UIM             1     1     FB10_12 
outDATA<0>\$WA3.UIM             1     1     FB10_13 
outDATA<2>\$WA5.UIM             1     1     FB10_14 
U1/Channel1<15>                 3     19    FB11_1  RESET
U1/Channel1<14>                 3     18    FB11_2  RESET
U1/Channel1<13>                 3     17    FB11_3  RESET
U1/Channel1<12>                 3     16    FB11_4  RESET
U1/Channel1<1>                  3     5     FB11_5  RESET
U1/Channel1<11>                 3     15    FB11_6  RESET
U1/Channel1<10>                 3     14    FB11_7  RESET
U1/Channel1<9>                  3     13    FB11_8  RESET
U1/Channel1<8>                  3     12    FB11_9  RESET
U1/Channel1<7>                  3     11    FB11_10 RESET

Signal                          Total Total Loc     Reg Init
Name                            Pts   Inps          State
U1/Channel1<6>                  3     10    FB11_11 RESET
U1/Channel1<5>                  3     9     FB11_12 RESET
U1/Channel1<4>                  3     8     FB11_13 RESET
U1/Channel1<3>                  3     7     FB11_14 RESET
U1/Channel1<2>                  3     6     FB11_15 RESET
U11_U1/Line_last                0     0     FB11_16 RESET
outDATA<1>\$WA1.UIM             1     1     FB12_16 
U1/U3/holdingreg0<11>           2     6     FB13_1  RESET
U1/U5/location_or0001           4     5     FB13_2  
U1/U3/holdingreg0<10>           2     6     FB13_3  RESET
U1/U1/CurrState_Sreg0_FSM_FFd1  1     6     FB13_4  RESET
N_PZ_1194                       2     5     FB13_5  
U1/U6/CurrState_Sreg0_FSM_FFd3  5     6     FB13_6  RESET
U1/U6/CurrState_Sreg0_FSM_FFd1  1     6     FB13_7  RESET
U1/U6/CurrState_Sreg0_FSM_FFd2  5     6     FB13_8  RESET
U1/U6/CurrState_Sreg0_FSM_FFd4  4     6     FB13_9  RESET
U1/U2/location_or0001           4     5     FB13_10 
N_PZ_1209                       2     5     FB13_11 
U1/U1/CurrState_Sreg0_FSM_FFd3  5     6     FB13_12 RESET
U1/U1/CurrState_Sreg0_FSM_FFd2  5     6     FB13_13 RESET
U1/U4/HE0stater                 0     0     FB13_14 RESET
U1/U1/CurrState_Sreg0_FSM_FFd4  4     6     FB13_15 RESET
U1/U3/holdingreg0<0>            2     6     FB13_16 RESET
U1/U4/HE1stater                 0     0     FB14_2  RESET
outDATA<4>\$WA6.UIM             4     10    FB14_3  
outDATA<3>\$WA1.UIM             1     1     FB14_6  
outDATA<2>\$WA3.UIM             1     1     FB14_7  
outDATA<2>\$WA1.UIM             1     1     FB14_8  
outDATA<1>\$WA3.UIM             1     1     FB14_9  
outDATA<7>\$WA0.UIM             4     10    FB14_10 
outDATA<7>\$WA6.UIM             4     10    FB14_11 
outDATA<6>\$WA6.UIM             4     10    FB14_12 
outDATA<5>\$WA6.UIM             4     10    FB14_15 
outDATA<3>\$WA2.UIM             1     1     FB15_2  
U2_ADDR_reg<7>                  3     6     FB15_3  RESET
U1/U3/holdingreg0<5>            2     6     FB15_4  RESET
U1/U3/holdingreg0<4>            2     6     FB15_6  RESET
U1/U3/holdingreg0<3>            2     6     FB15_7  RESET
U1/U3/holdingreg0<2>            2     6     FB15_8  RESET
U1/U3/holdingreg0<1>            2     6     FB15_9  RESET

Signal                          Total Total Loc     Reg Init
Name                            Pts   Inps          State
U1/U3/holdingreg0<15>           2     6     FB15_10 RESET
U1/U3/holdingreg0<14>           2     6     FB15_11 RESET
U1/U3/holdingreg0<13>           2     6     FB15_12 RESET
U2_ADDR_reg<4>                  3     6     FB15_13 RESET
U1/U3/holdingreg0<12>           2     6     FB15_14 RESET
U2_ADDR_reg<6>                  3     6     FB15_15 RESET
U1/U4/InEdge1r                  0     0     FB15_16 RESET
U1/U3/holdingreg1<14>           2     6     FB16_3  RESET
U1/U3/holdingreg0<6>            2     6     FB16_4  RESET
U1/U3/holdingreg1<13>           2     6     FB16_5  RESET
U1/U3/holdingreg1<12>           2     6     FB16_6  RESET
U1/U3/holdingreg1<11>           2     6     FB16_7  RESET
U1/U3/holdingreg1<10>           2     6     FB16_8  RESET
U1/U3/holdingreg1<0>            2     6     FB16_9  RESET
U1/Channel0<15>                 3     19    FB16_10 RESET
U1/Channel0<14>                 3     18    FB16_11 RESET
U1/Channel0<13>                 3     17    FB16_12 RESET
U1/U3/holdingreg0<9>            2     6     FB16_13 RESET
U1/U3/holdingreg0<8>            2     6     FB16_14 RESET
U1/U3/holdingreg0<7>            2     6     FB16_15 RESET
U1/U4/Latch1r<4>                2     6     FB17_1  RESET
U1/U4/Latch1r<3>                2     6     FB17_2  RESET
U1/U3/holdingreg1<15>           2     6     FB17_4  RESET
U1/U3/holdingreg1<1>            2     6     FB17_5  RESET
U1/U4/Latch1r<2>                2     6     FB17_6  RESET
U1/U4/Latch1r<1>                2     6     FB17_7  RESET
U1/U4/Latch1r<15>               2     6     FB17_8  RESET
U1/U3/holdingreg1<9>            2     6     FB17_9  RESET
U1/U3/holdingreg1<8>            2     6     FB17_10 RESET
U1/U3/holdingreg1<7>            2     6     FB17_11 RESET
U1/U3/holdingreg1<6>            2     6     FB17_12 RESET
U1/U3/holdingreg1<5>            2     6     FB17_13 RESET
U1/U3/holdingreg1<4>            2     6     FB17_14 RESET
U1/U3/holdingreg1<2>            2     6     FB17_15 RESET
U1/U3/holdingreg1<3>            2     6     FB17_16 RESET
U1/U4/Latch0r<0>                2     6     FB18_3  RESET
outDATA<3>\$WA3.UIM             1     1     FB18_5  
N_PZ_1021                       2     3     FB18_6  
U1/U4/Latch0r<2>                2     6     FB18_7  RESET
U1/U4/Latch0r<1>                2     6     FB18_8  RESET

Signal                          Total Total Loc     Reg Init
Name                            Pts   Inps          State
U1/U4/Latch0r<15>               2     6     FB18_9  RESET
U1/U4/Latch0r<14>               2     6     FB18_10 RESET
U1/U4/Latch0r<13>               2     6     FB18_11 RESET
U1/U4/Latch0r<12>               2     6     FB18_12 RESET
U1/U4/Latch0r<11>               2     6     FB18_13 RESET
U1/U4/Latch0r<10>               2     6     FB18_14 RESET
U1/U4/Latch0r<9>                2     6     FB19_9  RESET
U1/U4/Latch0r<8>                2     6     FB19_10 RESET
U1/U4/Latch0r<7>                2     6     FB19_11 RESET
U1/U4/Latch0r<6>                2     6     FB19_12 RESET
U1/U4/Latch0r<5>                2     6     FB19_13 RESET
U1/U4/Latch0r<4>                2     6     FB19_14 RESET
U1/U4/Latch0r<3>                2     6     FB19_16 RESET
N_PZ_1019                       2     3     FB20_2  
U1/U4/Latch1r<9>                2     6     FB20_3  RESET
outDATA<4>\$WA1.UIM             1     1     FB20_4  
U1/U4/Latch1r<8>                2     6     FB20_5  RESET
U1/U4/Latch1r<7>                2     6     FB20_6  RESET
U1/U4/Latch1r<6>                2     6     FB20_7  RESET
U1/U4/Latch1r<5>                2     6     FB20_8  RESET
U1/U4/Latch1r<14>               2     6     FB20_9  RESET
U1/U4/Latch1r<13>               2     6     FB20_10 RESET
U1/U4/Latch1r<12>               2     6     FB20_11 RESET
U1/U4/Latch1r<11>               2     6     FB20_12 RESET
U1/U4/Latch1r<10>               2     6     FB20_13 RESET
outDATA<5>\$WA1.UIM             1     1     FB20_14 
U1/U4/Latch1r<0>                2     6     FB20_15 RESET
outDATA<4>\$WA3.UIM             1     1     FB20_16 
outDATA<7>\$WA3.UIM             1     1     FB21_1  
outDATA<6>\$WA3.UIM             1     1     FB21_2  
U4/Flgreg<1>                    1     2     FB21_3  RESET
U4/Flgreg<5>                    1     2     FB21_4  RESET
outDATA<5>\$WA3.UIM             1     1     FB21_5  
outDATA<4>\$WA4.UIM             1     1     FB21_6  
outDATA<7>\$WA5.UIM             2     3     FB21_7  
outDATA<5>\$WA5.UIM             2     3     FB21_8  
outDATA<4>\$WA5.UIM             2     3     FB21_9  
U4/DCORIFG__or0000_bdd0         1     6     FB21_10 
outDATA<3>\$WA5.UIM             2     3     FB21_11 
outDATA<0>\$WA5.UIM             2     3     FB21_12 

Signal                          Total Total Loc     Reg Init
Name                            Pts   Inps          State
U4/Flgreg<4>                    1     2     FB21_14 RESET
U4/Flgreg<0>                    1     2     FB21_16 RESET
outDATA<2>\$WA2.UIM             1     2     FB22_5  
outDATA<5>\$WA2.UIM             2     3     FB22_10 
outDATA<4>\$WA2.UIM             2     3     FB22_11 
outDATA<1>\$WA2.UIM             2     3     FB22_12 
outDATA<0>\$WA2.UIM             2     3     FB22_14 
outDATA<6>\$WA2.UIM             1     2     FB22_15 
U4/Flgreg<7>                    1     2     FB24_3  RESET
U4/Flgreg<3>                    1     2     FB24_4  RESET

** 43 Inputs **

Signal                          Loc     Pin   Pin       Pin     
Name                                    No.   Type      Use     
Mclk                                    127   GCK/I     GCK              
Brake0                          FB1_1   94    I/O       I                
DIR1                            FB1_5   93    I/O       I                
Brake1                          FB1_13  92    I/O       I                
DIR0                            FB2_2   96    I/O       I                
PWM5                            FB2_5   99    I/O       I                
PWM4                            FB2_13  100   I/O       I                
PWM3                            FB2_14  101   I/O       I                
PWM2                            FB2_15  102   I/O       I                
PWM1                            FB2_16  103   I/O       I                
MSPReset                        FB4_2   106   I/O       I                
RD                              FB4_3   107   I/O       I       PU       
WR                              FB4_4   110   I/O       I       PU       
AS                              FB4_5   111   I/O       I       PU       
PhaseB_Encoder0                 FB6_15  68    I/O       I                
GP_Motor0_0                     FB6_16  69    I/O       I                
SCLreset                        FB9_5   120   I/O       I                
SCLinc                          FB11_16 119   I/O       I                
FLS0                            FB13_1  61    I/O       I                
RLS0                            FB13_3  62    I/O       I                
Home0                           FB13_14 65    I/O       I                
PhaseA_Encoder0                 FB13_16 66    I/O       I                
Home1                           FB14_2  47    I/O       I                
RLS1                            FB14_13 45    I/O       I                
FLS1                            FB14_14 44    I/O       I                
GP_Motor1_0                     FB15_16 54    I/O       I                
PhaseA_Encoder1                 FB16_2  48    I/O       I                
PhaseB_Encoder1                 FB16_16 53    I/O       I                
INTbus                          FB18_4  10    I/O       I                
MReset                          FB18_16 12    I/O       I                
LightSense                      FB20_16 18    I/O       I                
Home05FLG                       FB21_3  42    I/O       I       PU       
Home15FLG                       FB21_4  41    I/O       I       PU       
Latch133FLG                     FB21_14 39    I/O       I       PU       
Latch033FLG                     FB21_16 37    I/O       I       PU       
I2CS<5>                         FB22_1  19    I/O       I                
I2CS<4>                         FB22_3  20    I/O       I                
I2CS<3>                         FB22_4  21    I/O       I                
I2CS<2>                         FB22_13 23    I/O       I                
I2CS<1>                         FB22_16 25    I/O       I                

Signal                          Loc     Pin   Pin       Pin     
Name                                    No.   Type      Use     
I2CS<0>                         FB24_1  26    I/O       I                
Enc15FLG                        FB24_3  28    I/O       I       PU       
Enc05FLG                        FB24_4  29    I/O       I       PU       

Legend:
Pin No. - ~ - User Assigned
PU          - Pull Up
**************************  Function Block Details  ************************
Legend:
Total Pt     - Total product terms used by the macrocell signal
Loc          - Location where logic was mapped in device
Pin Type/Use - I  - Input            GCK - Global clock
               O  - Output           (b) - Buried macrocell
Pin No.      - ~  - User Assigned
*********************************** FB1  ***********************************
Number of function block inputs used/remaining:               33/7
Number of foldback NANDs used/remaining:                      0/8
Number of function block local control terms used/remaining:  0/8
Number of PLA product terms used/remaining:                   48/0
Number of function block global clocks used/remaining:  1/1
Signal                        Total Loc     Pin  Pin     Pin   GCK 
Name                          Pt            No.  Type    Use       
N_PZ_1030                     2     FB1_1   94   I/O     I     
U3/DCORIE<2>                  3     FB1_2        (b)     (b)   Mclk
U3/DCORIE<1>                  3     FB1_3        (b)     (b)   Mclk
U1/U4/LatchEdge0r             3     FB1_4        (b)     (b)   Mclk
N_PZ_1202                     2     FB1_5   93   I/O     I     
U9/MISCr<2>                   4     FB1_6        (b)     (b)   Mclk
U1/U4/latchitH0               3     FB1_7        (b)     (b)   Mclk
NET2482                       7     FB1_8        (b)     (b)   Mclk
U1/U4/E0r                     3     FB1_9        (b)     (b)   Mclk
U9/MISCr<1>                   4     FB1_10       (b)     (b)   Mclk
U3/DCORIE<0>                  3     FB1_11       (b)     (b)   Mclk
U1/U4/RF0r                    3     FB1_12       (b)     (b)   Mclk
NET2528                       4     FB1_13  92   I/O     I     Mclk
U9/MISCr<0>                   4     FB1_14       (b)     (b)   Mclk
U1/U4/E1r                     3     FB1_15       (b)     (b)   Mclk
TP21                          3     FB1_16  91   I/O     O     Mclk

Signals Used by Logic in Function Block
  1: AD<0>.PIN         12: U1/U4/E1r            23: U2_ADDR_reg<5> 
  2: AD<1>.PIN         13: U1/U4/HE0statelastr  24: U2_ADDR_reg<6> 
  3: AD<2>.PIN         14: U1/U4/HE0stater      25: U2_ADDR_reg<7> 
  4: AD<5>.PIN         15: U1/U4/LatchEdge0r    26: U3/DCORIE<0> 
  5: MSPReset          16: U1/U4/RF0r           27: U3/DCORIE<1> 
  6: NET2482           17: U1/U4/latchitH0      28: U3/DCORIE<2> 
  7: NET2528           18: U2_ADDR_reg<0>       29: U4/DCORIFG__or0000_bdd0 
  8: N_PZ_1030         19: U2_ADDR_reg<1>       30: U9/MISCr<0> 
  9: RD                20: U2_ADDR_reg<2>       31: U9/MISCr<1> 
 10: TP21              21: U2_ADDR_reg<3>       32: U9/MISCr<2> 
 11: U1/U4/E0r         22: U2_ADDR_reg<4>       33: WR 

Signal                     1         2         3         4 FB      
Name             0----+----0----+----0----+----0----+----0 Inputs  
N_PZ_1030         ....X...X........X.XXXXXX.......X....... 10      
U3/DCORIE<2>      ..X.X...X........XXXXXXXX..X....X....... 13      
U3/DCORIE<1>      .X..X...X........XXXXXXXX.X.....X....... 13      
U1/U4/LatchEdge0r 
                  ..X.X...X.....X..XXXXXXXX.......X....... 13      
N_PZ_1202         ....X...X........XXXXXXXX.......X....... 11      
U9/MISCr<2>       ..X.X...X........XXXXXXXX......XX....... 13      
U1/U4/latchitH0   ....XX.XX.X.XX.XXX.XXXXXX.......X....... 17      
NET2482           ..X.XX..X.X.XX.X.XXXXXXXX.......X....... 17      
U1/U4/E0r         .X..X...X.X......XXXXXXXX.......X....... 13      
U9/MISCr<1>       .X..X...X........XXXXXXXX.....X.X....... 13      
U3/DCORIE<0>      X...X...X........XXXXXXXXX......X....... 13      
U1/U4/RF0r        X...X...X......X.XXXXXXXX.......X....... 13      
NET2528           .X..X.X.X........XXXXXXXX...X...X....... 14      
U9/MISCr<0>       X...X...X........XXXXXXXX....X..X....... 13      
U1/U4/E1r         ...XX...X..X.....XXXXXXXX.......X....... 13      
TP21              ...XX...XX.......XXXXXXXX.......X....... 13      
                 0----+----1----+----2----+----3----+----4
                           0         0         0         0
*********************************** FB2  ***********************************
Number of function block inputs used/remaining:               38/2
Number of foldback NANDs used/remaining:                      0/8
Number of function block local control terms used/remaining:  1/7
Number of PLA product terms used/remaining:                   48/0
Number of function block global clocks used/remaining:  1/1
Signal                        Total Loc     Pin  Pin     Pin   GCK 
Name                          Pt            No.  Type    Use       
NET2512                       3     FB2_1        (b)     (b)   Mclk
N_PZ_1203                     2     FB2_2   96   I/O     I     
U9/MISCr<3>                   4     FB2_3        (b)     (b)   Mclk
U1/TP                         3     FB2_4        (b)     (b)   Mclk
N_PZ_1195                     2     FB2_5   99   I/O     I     
NET2575                       4     FB2_6        (b)     (b)   Mclk
U3/DCORIE<4>                  3     FB2_7        (b)     (b)   Mclk
U1/U4/latchitH1               3     FB2_8        (b)     (b)   Mclk
NET2493                       8     FB2_9        (b)     (b)   Mclk
U1/U4/RF1r                    3     FB2_10       (b)     (b)   Mclk
U9/MISCr<4>                   4     FB2_11       (b)     (b)   Mclk
U3/DCORIE<3>                  3     FB2_12       (b)     (b)   Mclk
U2_Enable_AD                  1     FB2_13  100  I/O     I     
U3/DCORIE<6>                  3     FB2_14  101  I/O     I     Mclk
U1/U4/LatchEdge1r             3     FB2_15  102  I/O     I     Mclk
U1/U4/latchitL1               3     FB2_16  103  I/O     I     Mclk

Signals Used by Logic in Function Block
  1: AD<3>.PIN            14: U1/U4/InEdge1r     27: U2_ADDR_reg<7> 
  2: AD<4>.PIN            15: U1/U4/LastEdge1r   28: U2_Enable_AD 
  3: AD<6>.PIN            16: U1/U4/LatchEdge1r  29: U3/DCORIE<3> 
  4: MSPReset             17: U1/U4/RF1r         30: U3/DCORIE<4> 
  5: NET2493              18: U1/U4/latchitH1    31: U3/DCORIE<6> 
  6: NET2512              19: U1/U4/latchitL1    32: U5/FLS0fr 
  7: NET2575              20: U2_ADDR_reg<0>     33: U5/FLS1fr 
  8: N_PZ_1030            21: U2_ADDR_reg<1>     34: U5/RLS0fr 
  9: RD                   22: U2_ADDR_reg<2>     35: U5/RLS1fr 
 10: U1/TP                23: U2_ADDR_reg<3>     36: U9/MISCr<3> 
 11: U1/U4/E1r            24: U2_ADDR_reg<4>     37: U9/MISCr<4> 
 12: U1/U4/HE1statelastr  25: U2_ADDR_reg<5>     38: WR 
 13: U1/U4/HE1stater      26: U2_ADDR_reg<6>    

Signal                     1         2         3         4 FB      
Name             0----+----0----+----0----+----0----+----0 Inputs  
NET2512           ..XX.X.XX....XXX...XXXXXXXX..........X.. 17      
N_PZ_1203         ...................XXXX....X............ 5       
U9/MISCr<3>       X..X....X..........XXXXXXXX........X.X.. 13      
U1/TP             X..X....XX.........XXXXXXXX..........X.. 13      
N_PZ_1195         ...................XXXX....X............ 5       
NET2575           .X.X..X.X..........XXXXXXXX....XXXX..X.. 17      
U3/DCORIE<4>      .X.X....X..........XXXXXXXX..X.......X.. 13      
U1/U4/latchitH1   ...XX..XX.XXX...XX.X.XXXXXX..........X.. 17      
NET2493           X..XX...X.XXX...X..XXXXXXXX..........X.. 17      
U1/U4/RF1r        .X.X....X.......X..XXXXXXXX..........X.. 13      
U9/MISCr<4>       .X.X....X..........XXXXXXXX.........XX.. 13      
U3/DCORIE<3>      X..X....X..........XXXXXXXX.X........X.. 13      
U2_Enable_AD      ........X..............XXXX..........X.. 6       
U3/DCORIE<6>      ..XX....X..........XXXXXXXX...X......X.. 13      
U1/U4/LatchEdge1r 
                  ..XX....X......X...XXXXXXXX..........X.. 13      
U1/U4/latchitL1   ...X.X.XX....XXX..XX.XXXXXX..........X.. 16      
                 0----+----1----+----2----+----3----+----4
                           0         0         0         0
*********************************** FB3  ***********************************
Number of function block inputs used/remaining:               24/16
Number of foldback NANDs used/remaining:                      0/8
Number of function block local control terms used/remaining:  1/7
Number of PLA product terms used/remaining:                   30/18
Number of function block global clocks used/remaining:  1/1
Signal                        Total Loc     Pin  Pin     Pin   GCK 
Name                          Pt            No.  Type    Use       
N_PZ_1314                     1     FB3_1        (b)     (b)   
U5/RLS1r                      1     FB3_2        (b)     (b)   Mclk
U5/RLS1fr                     2     FB3_3        (b)     (b)   Mclk
PBL0                          2     FB3_4   90   I/O     O     
PBH0                          1     FB3_5   89   I/O     O     
NET3253                       5     FB3_6        (b)     (b)   Mclk
U5/FLS1fr                     2     FB3_7        (b)     (b)   Mclk
U5/FLS1r                      1     FB3_8        (b)     (b)   Mclk
U5/RLS0r                      1     FB3_9        (b)     (b)   Mclk
U5/FLS0r                      1     FB3_10       (b)     (b)   Mclk
N_PZ_1313                     1     FB3_11       (b)     (b)   
U5/RLS0fr                     2     FB3_12       (b)     (b)   Mclk
U5/FLS0fr                     2     FB3_13       (b)     (b)   Mclk
PAL0                          2     FB3_14  88   I/O     O     
NET3248                       5     FB3_15       (b)     (b)   Mclk
PAH0                          1     FB3_16  87   I/O     O     

Signals Used by Logic in Function Block
  1: Brake0             9: NET3248           17: U5/FLS0fr 
  2: Brake1            10: NET3253           18: U5/FLS0r 
  3: DIR0              11: N_PZ_1202         19: U5/FLS1fr 
  4: DIR1              12: N_PZ_1313         20: U5/FLS1r 
  5: FLS0              13: N_PZ_1314         21: U5/RLS0fr 
  6: FLS1              14: PWM1              22: U5/RLS0r 
  7: MSPReset          15: RLS0              23: U5/RLS1fr 
  8: MTRpwr            16: RLS1              24: U5/RLS1r 

Signal                     1         2         3         4 FB      
Name             0----+----0----+----0----+----0----+----0 Inputs  
N_PZ_1314         ...X...........X.......X................ 3       
U5/RLS1r          ......X........X........................ 2       
U5/RLS1fr         ..........X.X.........X................. 3       
PBL0              X.X....XX....X.......................... 5       
PBH0              X.X.X..XX....X.......................... 6       
NET3253           .X.X.X...XX.X.....XX..X................. 9       
U5/FLS1fr         ...X.X....X.......XX.................... 5       
U5/FLS1r          .....XX................................. 2       
U5/RLS0r          ......X.......X......................... 2       
U5/FLS0r          ....X.X................................. 2       
N_PZ_1313         ..X...........X......X.................. 3       
U5/RLS0fr         ..........XX........X................... 3       
U5/FLS0fr         ..X.X.....X.....XX...................... 5       
PAL0              X.X....XX....X.......................... 5       
NET3248           X.X.X...X.XX....XX..X................... 9       
PAH0              X.X....XX....XX......................... 6       
                 0----+----1----+----2----+----3----+----4
                           0         0         0         0
*********************************** FB4  ***********************************
Number of function block inputs used/remaining:               33/7
Number of foldback NANDs used/remaining:                      0/8
Number of function block local control terms used/remaining:  2/6
Number of PLA product terms used/remaining:                   47/1
Number of function block global clocks used/remaining:  1/1
Signal                        Total Loc     Pin  Pin     Pin   GCK 
Name                          Pt            No.  Type    Use       
U4/Flgreg<6>                  1     FB4_1        (b)     (b)   Mclk
outDATA<0>\$WA1               1     FB4_2   106  I/O     I     
outDATA<7>\$WA4               1     FB4_3   107  I/O     I     
U11_ResetDetect               1     FB4_4   110  I/O     I     Mclk
U2_ASedge                     0     FB4_5   111  I/O     I     Mclk
U11_Incdetect                 1     FB4_6        (b)     (b)   Mclk
N_PZ_1142                     3     FB4_7        (b)     (b)   
U11_U3_counterr<2>            3     FB4_8        (b)     (b)   Mclk
U11_U3_counterr<5>            4     FB4_9        (b)     (b)   Mclk
U11_U3_counterr<4>            4     FB4_10       (b)     (b)   Mclk
U11_U3_counterr<3>            7     FB4_11       (b)     (b)   Mclk
U11_U3_counterr<1>            4     FB4_12       (b)     (b)   Mclk
INT                           8     FB4_13  112  I/O     O     
outDATA<6>\$WA5.UIM           1     FB4_14       (b)     (b)   
SCL                           1     FB4_15  114  I/O     I/O   Mclk
U11_U3_counterr<0>            6     FB4_16       (b)     (b)   Mclk

Signals Used by Logic in Function Block
  1: INTbus            12: TP26                23: U11_U4/Line_last 
  2: NET2482           13: U11_Incdetect       24: U3/DCORIE<0> 
  3: NET2493           14: U11_ResetDetect     25: U3/DCORIE<1> 
  4: NET2512           15: U11_SCLdetect       26: U3/DCORIE<2> 
  5: NET2528           16: U11_U1/Line_last    27: U3/DCORIE<3> 
  6: NET2575           17: U11_U3_counterr<0>  28: U3/DCORIE<4> 
  7: N_PZ_1142         18: U11_U3_counterr<1>  29: U3/DCORIE<6> 
  8: SCLinc            19: U11_U3_counterr<2>  30: U3/DCORIE<7> 
  9: SCLreset          20: U11_U3_counterr<3>  31: U4/DCORIFG__or0000_bdd0 
 10: TP12              21: U11_U3_counterr<4>  32: U4/Flgreg<6> 
 11: TP21              22: U11_U3_counterr<5>  33: outDATA<7>\$WA4.UIM 

Signal                     1         2         3         4 FB      
Name             0----+----0----+----0----+----0----+----0 Inputs  
U4/Flgreg<6>      ....X.........................XX........ 3       
outDATA<0>\$WA1   ................X....................... 1       
outDATA<7>\$WA4   .........X.............................. 1       
U11_ResetDetect   ........X.............X................. 2       
U11_Incdetect     .......X.......X........................ 2       
N_PZ_1142         .......XX...XXX.................X....... 6       
U11_U3_counterr<2> 
                  ......X.....X.X.XXX..................... 6       
U11_U3_counterr<5> 
                  ......X.....X.X.XXXXXX.................. 9       
U11_U3_counterr<4> 
                  ......X.....X.X.XXXXX................... 8       
U11_U3_counterr<3> 
                  ......X.X...X.X.XXXX.................... 8       
U11_U3_counterr<1> 
                  ......XXX...X.X.XX...................... 7       
INT               XXXXXX...XXX...........XXXXXXX.......... 16      
outDATA<6>\$WA5   ....X..........................X........ 2       
SCL               .........X.............................. 1       
U11_U3_counterr<0> 
                  .......XXX..XXX.X....................... 7       
                 0----+----1----+----2----+----3----+----4
                           0         0         0         0
*********************************** FB5  ***********************************
Number of function block inputs used/remaining:               36/4
Number of foldback NANDs used/remaining:                      0/8
Number of function block local control terms used/remaining:  0/8
Number of PLA product terms used/remaining:                   30/18
Number of function block global clocks used/remaining:  1/1
Signal                        Total Loc     Pin  Pin     Pin   GCK 
Name                          Pt            No.  Type    Use       
U2_WRRDedge_and0000           1     FB5_1        (b)     (b)   
outDATA<7>\$WA2               1     FB5_2   86   TCK/I/O (b)   
U2_WRRDedge                   1     FB5_3        (b)     (b)   Mclk
N_PZ_1216                     2     FB5_4        (b)     (b)   
PBL1                          2     FB5_5   84   I/O     O     
N_PZ_1029                     1     FB5_6        (b)     (b)   
outDATA<5>\$WA0.UIM           6     FB5_7        (b)     (b)   
U3/DCORIE<7>                  3     FB5_8        (b)     (b)   Mclk
U1/NET3720                    3     FB5_9        (b)     (b)   Mclk
U1/U4/latchitL0               3     FB5_10       (b)     (b)   Mclk
U1/U4/LastEdge0r              1     FB5_11       (b)     (b)   Mclk
U1/U4/HE1statelastr           1     FB5_12       (b)     (b)   Mclk
U1/U4/HE0statelastr           1     FB5_13       (b)     (b)   Mclk
PBH1                          1     FB5_14  83   I/O     O     
PAL1                          2     FB5_15  82   I/O     O     
PAH1                          1     FB5_16  81   I/O     O     

Signals Used by Logic in Function Block
  1: AD<7>.PIN         13: RLS1               25: U1/U4/latchitL0 
  2: Brake1            14: TP26               26: U2_ADDR_reg<0> 
  3: DIR1              15: U1/NET3720         27: U2_ADDR_reg<1> 
  4: FLS1              16: U1/U4/HE0stater    28: U2_ADDR_reg<2> 
  5: MSPReset          17: U1/U4/HE1stater    29: U2_ADDR_reg<3> 
  6: MTRpwr            18: U1/U4/InEdge0r     30: U2_ADDR_reg<4> 
  7: NET3253           19: U1/U4/LastEdge0r   31: U2_ADDR_reg<5> 
  8: N_PZ_1030         20: U1/U4/Latch0r<13>  32: U2_ADDR_reg<6> 
  9: N_PZ_1203         21: U1/U4/Latch0r<5>   33: U2_ADDR_reg<7> 
 10: N_PZ_1216         22: U1/U4/Latch1r<13>  34: U2_Enable_AD 
 11: PWM2              23: U1/U4/Latch1r<5>   35: U3/DCORIE<7> 
 12: RD                24: U1/U4/LatchEdge0r  36: WR 

Signal                     1         2         3         4 FB      
Name             0----+----0----+----0----+----0----+----0 Inputs  
U2_WRRDedge_and0000 
                  ...........X.......................X.... 2       
outDATA<7>\$WA2   ......X................................. 1       
U2_WRRDedge       ...........X.......................X.... 2       
N_PZ_1216         ........X................XX.X........... 4       
PBL1              .XX..XX...X............................. 5       
N_PZ_1029         ........X................X.X.....X...... 4       
outDATA<5>\$WA0   ........XX.X.X.....XXXX..XXXXXXXXX.X.... 18      
U3/DCORIE<7>      X...X......X.............XXXXXXXX.XX.... 13      
U1/NET3720        X...X......X..X..........XXXXXXXX..X.... 13      
U1/U4/latchitL0   ....X..X...X.X...XX....XXX.XXXXXX..X.... 16      
U1/U4/LastEdge0r  .................X...................... 1       
U1/U4/HE1statelastr 
                  ................X....................... 1       
U1/U4/HE0statelastr 
                  ...............X........................ 1       
PBH1              .XXX.XX...X............................. 6       
PAL1              .XX..XX...X............................. 5       
PAH1              .XX..XX...X.X........................... 6       
                 0----+----1----+----2----+----3----+----4
                           0         0         0         0
*********************************** FB6  ***********************************
Number of function block inputs used/remaining:               19/21
Number of foldback NANDs used/remaining:                      0/8
Number of function block local control terms used/remaining:  0/8
Number of PLA product terms used/remaining:                   40/8
Number of function block global clocks used/remaining:  1/1
Signal                        Total Loc     Pin  Pin     Pin   GCK 
Name                          Pt            No.  Type    Use       
U1/U4/LastEdge1r              1     FB6_1        (b)     (b)   Mclk
U1/Channel0<11>               3     FB6_2        (b)     (b)   Mclk
U1/Channel0<10>               3     FB6_3        (b)     (b)   Mclk
U1/Channel0<9>                3     FB6_4        (b)     (b)   Mclk
U1/Channel0<8>                3     FB6_5        (b)     (b)   Mclk
U1/Channel0<7>                3     FB6_6        (b)     (b)   Mclk
U1/Channel0<6>                3     FB6_7        (b)     (b)   Mclk
U1/Channel0<5>                3     FB6_8        (b)     (b)   Mclk
U1/Channel0<4>                3     FB6_9        (b)     (b)   Mclk
U1/Channel0<3>                3     FB6_10       (b)     (b)   Mclk
U1/Channel0<2>                3     FB6_11       (b)     (b)   Mclk
U1/Channel0<1>                3     FB6_12       (b)     (b)   Mclk
U1/Channel0<0>                2     FB6_13       (b)     (b)   Mclk
U11_SCLdetect                 1     FB6_14       (b)     (b)   Mclk
U1/Channel0<12>               3     FB6_15  68   I/O     I     Mclk
U1/U4/InEdge0r                0     FB6_16  69   I/O     I     Mclk

Signals Used by Logic in Function Block
  1: MSPReset           8: U1/Channel0<12>   14: U1/Channel0<6> 
  2: N_PZ_1209          9: U1/Channel0<1>    15: U1/Channel0<7> 
  3: SCL               10: U1/Channel0<2>    16: U1/Channel0<8> 
  4: SCL.PIN           11: U1/Channel0<3>    17: U1/Channel0<9> 
  5: U1/Channel0<0>    12: U1/Channel0<4>    18: U1/U2/location_or0001 
  6: U1/Channel0<10>   13: U1/Channel0<5>    19: U1/U4/InEdge1r 
  7: U1/Channel0<11>  

Signal                     1         2         3         4 FB      
Name             0----+----0----+----0----+----0----+----0 Inputs  
U1/U4/LastEdge1r  ..................X..................... 1       
U1/Channel0<11>   XX..XXX.XXXXXXXXXX...................... 15      
U1/Channel0<10>   XX..XX..XXXXXXXXXX...................... 14      
U1/Channel0<9>    XX..X...XXXXXXXXXX...................... 13      
U1/Channel0<8>    XX..X...XXXXXXXX.X...................... 12      
U1/Channel0<7>    XX..X...XXXXXXX..X...................... 11      
U1/Channel0<6>    XX..X...XXXXXX...X...................... 10      
U1/Channel0<5>    XX..X...XXXXX....X...................... 9       
U1/Channel0<4>    XX..X...XXXX.....X...................... 8       
U1/Channel0<3>    XX..X...XXX......X...................... 7       
U1/Channel0<2>    XX..X...XX.......X...................... 6       
U1/Channel0<1>    XX..X...X........X...................... 5       
U1/Channel0<0>    XX..X................................... 3       
U11_SCLdetect     ..XX.................................... 2       
U1/Channel0<12>   XX..XXXXXXXXXXXXXX...................... 16      
                 0----+----1----+----2----+----3----+----4
                           0         0         0         0
*********************************** FB7  ***********************************
Number of function block inputs used/remaining:               37/3
Number of foldback NANDs used/remaining:                      0/8
Number of function block local control terms used/remaining:  2/6
Number of PLA product terms used/remaining:                   37/11
Number of function block global clocks used/remaining:  1/1
Signal                        Total Loc     Pin  Pin     Pin   GCK 
Name                          Pt            No.  Type    Use       
MTRpwrn                       4     FB7_1   80   I/O     O     Mclk
LED5                          1     FB7_2   79   I/O     O     
LED4                          1     FB7_3   78   I/O     O     
LED3                          1     FB7_4   77   I/O     O     
(unused)                      0     FB7_5        (b)           
outDATA<7>\$WA1.UIM           0     FB7_6        (b)     (b)   
outDATA<6>\$WA1.UIM           0     FB7_7        (b)     (b)   
N_PZ_1001                     2     FB7_8        (b)     (b)   
U2_AutoInc                    2     FB7_9        (b)     (b)   Mclk
U2_ADDR_reg<5>                3     FB7_10       (b)     (b)   Mclk
outDATA<2>\$WA0.UIM           6     FB7_11       (b)     (b)   
U2_ADDR_reg<0>                4     FB7_12       (b)     (b)   Mclk
U2_ADDR_reg<1>                4     FB7_13       (b)     (b)   Mclk
U2_ADDR_reg<2>                4     FB7_14       (b)     (b)   Mclk
LED2                          1     FB7_15  75   I/O     O     
U2_ADDR_reg<3>                4     FB7_16       (b)     (b)   Mclk

Signals Used by Logic in Function Block
  1: AD<0>.PIN         14: N_PZ_1216          26: U2_ADDR_reg<6> 
  2: AD<1>.PIN         15: RD                 27: U2_ADDR_reg<7> 
  3: AD<2>.PIN         16: U1/U4/Latch0r<10>  28: U2_ASedge 
  4: AD<3>.PIN         17: U1/U4/Latch0r<2>   29: U2_AutoInc 
  5: AD<5>.PIN         18: U1/U4/Latch1r<10>  30: U2_Enable_AD 
  6: AS                19: U1/U4/Latch1r<2>   31: U2_WRRDedge 
  7: LightSense        20: U2_ADDR_reg<0>     32: U2_WRRDedge_and0000 
  8: MReset            21: U2_ADDR_reg<1>     33: U9/MISCr<1> 
  9: MSPReset          22: U2_ADDR_reg<2>     34: U9/MISCr<2> 
 10: MTRpwrn           23: U2_ADDR_reg<3>     35: U9/MISCr<3> 
 11: NET2482           24: U2_ADDR_reg<4>     36: U9/MISCr<4> 
 12: N_PZ_1001         25: U2_ADDR_reg<5>     37: WR 
 13: N_PZ_1203        

Signal                     1         2         3         4 FB      
Name             0----+----0----+----0----+----0----+----0 Inputs  
MTRpwrn           ....X..XXX....X....XXXXXXXX.........X... 14      
LED5              ......X............................X.... 2       
LED4              ......X...........................X..... 2       
LED3              ......X..........................X...... 2       
outDATA<7>\$WA1   ........................................ 0       
outDATA<6>\$WA1   ........................................ 0       
N_PZ_1001         .....X..X..................X............ 3       
U2_AutoInc        .....X........................XX........ 3       
U2_ADDR_reg<5>    ....XX..X...............X..X...X........ 6       
outDATA<2>\$WA0   ..........X.XXXXXXXXXXXXXXX..X......X... 18      
U2_ADDR_reg<0>    X....X..X..X.......X...XXXXXX.XX........ 13      
U2_ADDR_reg<1>    .X...X..X..X.......XX..XXXXXX.XX........ 14      
U2_ADDR_reg<2>    ..X..X..X..X.......XXX.XXXXXX.XX........ 15      
LED2              ......X.........................X....... 2       
U2_ADDR_reg<3>    ...X.X..X..X.......XXXXXXXXXX.XX........ 16      
                 0----+----1----+----2----+----3----+----4
                           0         0         0         0
*********************************** FB8  ***********************************
Number of function block inputs used/remaining:               38/2
Number of foldback NANDs used/remaining:                      0/8
Number of function block local control terms used/remaining:  0/8
Number of PLA product terms used/remaining:                   26/22
Number of function block global clocks used/remaining:  1/1
Signal                        Total Loc     Pin  Pin     Pin   GCK 
Name                          Pt            No.  Type    Use       
outDATA<3>\$WA0.UIM           6     FB8_1        (b)     (b)   
GP_Motor0_1                   4     FB8_2   71   I/O     O     Mclk
outDATA<6>\$WA0.UIM           6     FB8_3        (b)     (b)   
(unused)                      0     FB8_4        (b)           
(unused)                      0     FB8_5        (b)           
(unused)                      0     FB8_6        (b)           
(unused)                      0     FB8_7        (b)           
(unused)                      0     FB8_8        (b)           
(unused)                      0     FB8_9        (b)           
(unused)                      0     FB8_10       (b)           
(unused)                      0     FB8_11       (b)           
(unused)                      0     FB8_12       (b)           
U1/Channel1<0>                2     FB8_13       (b)     (b)   Mclk
outDATA<1>\$WA0.UIM           4     FB8_14       (b)     (b)   
outDATA<0>\$WA0.UIM           4     FB8_15       (b)     (b)   
LED1                          1     FB8_16  74   I/O     O     

Signals Used by Logic in Function Block
  1: AD<6>.PIN          14: U1/U4/Latch0r<14>  27: U1/U4/Latch1r<9> 
  2: GP_Motor0_1        15: U1/U4/Latch0r<1>   28: U2_ADDR_reg<0> 
  3: LightSense         16: U1/U4/Latch0r<3>   29: U2_ADDR_reg<1> 
  4: MSPReset           17: U1/U4/Latch0r<6>   30: U2_ADDR_reg<2> 
  5: NET2493            18: U1/U4/Latch0r<8>   31: U2_ADDR_reg<3> 
  6: NET2512            19: U1/U4/Latch0r<9>   32: U2_ADDR_reg<4> 
  7: N_PZ_1194          20: U1/U4/Latch1r<0>   33: U2_ADDR_reg<5> 
  8: N_PZ_1203          21: U1/U4/Latch1r<11>  34: U2_ADDR_reg<6> 
  9: N_PZ_1216          22: U1/U4/Latch1r<14>  35: U2_ADDR_reg<7> 
 10: RD                 23: U1/U4/Latch1r<1>   36: U2_Enable_AD 
 11: U1/Channel1<0>     24: U1/U4/Latch1r<3>   37: U9/MISCr<0> 
 12: U1/U4/Latch0r<0>   25: U1/U4/Latch1r<6>   38: WR 
 13: U1/U4/Latch0r<11>  26: U1/U4/Latch1r<8>  

Signal                     1         2         3         4 FB      
Name             0----+----0----+----0----+----0----+----0 Inputs  
outDATA<3>\$WA0   ....X..XXX..X..X....X..X...XXXXXXXXX.X.. 18      
GP_Motor0_1       XX.X.....X.................XXXXXXXX..X.. 13      
outDATA<6>\$WA0   .....X.XXX...X..X....X..X..XXXXXXXXX.X.. 18      
U1/Channel1<0>    ...X..X...X............................. 3       
outDATA<1>\$WA0   ........X.....X...X...X...XXXXX....X.... 10      
outDATA<0>\$WA0   ........X..X.....X.X.....X.XXXX....X.... 10      
LED1              ..X.................................X... 2       
                 0----+----1----+----2----+----3----+----4
                           0         0         0         0
*********************************** FB9  ***********************************
Number of function block inputs used/remaining:               38/2
Number of foldback NANDs used/remaining:                      0/8
Number of function block local control terms used/remaining:  0/8
Number of PLA product terms used/remaining:                   26/22
Number of function block global clocks used/remaining:  1/1
Signal                        Total Loc     Pin  Pin     Pin   GCK 
Name                          Pt            No.  Type    Use       
AD<7>                         8     FB9_1   122  I/O     I/O   
(unused)                      0     FB9_2        (b)           
outDATA<1>\$WA5               3     FB9_3   121  TDO/I/O (b)   
(unused)                      0     FB9_4        (b)           
U11_U4/Line_last              0     FB9_5   120  I/O     I     Mclk
(unused)                      0     FB9_6        (b)           
(unused)                      0     FB9_7        (b)           
(unused)                      0     FB9_8        (b)           
(unused)                      0     FB9_9        (b)           
(unused)                      0     FB9_10       (b)           
(unused)                      0     FB9_11       (b)           
(unused)                      0     FB9_12       (b)           
outDATA<3>\$WA6.UIM           4     FB9_13       (b)     (b)   
outDATA<2>\$WA6.UIM           4     FB9_14       (b)     (b)   
outDATA<1>\$WA6.UIM           4     FB9_15       (b)     (b)   
outDATA<0>\$WA6.UIM           4     FB9_16       (b)     (b)   

Signals Used by Logic in Function Block
  1: Home05FLG              14: U1/U3/holdingreg1<10>  27: U2_ADDR_reg<6> 
  2: NET2528                15: U1/U3/holdingreg1<11>  28: U2_ADDR_reg<7> 
  3: N_PZ_1195              16: U1/U3/holdingreg1<1>   29: U2_Enable_AD 
  4: RD                     17: U1/U3/holdingreg1<2>   30: U4/Flgreg<1> 
  5: U1/U3/holdingreg0<0>   18: U1/U3/holdingreg1<3>   31: WR 
  6: U1/U3/holdingreg0<10>  19: U1/U3/holdingreg1<8>   32: outDATA<7>\$WA0.UIM 
  7: U1/U3/holdingreg0<11>  20: U1/U3/holdingreg1<9>   33: outDATA<7>\$WA1.UIM 
  8: U1/U3/holdingreg0<1>   21: U2_ADDR_reg<0>         34: outDATA<7>\$WA2.UIM 
  9: U1/U3/holdingreg0<2>   22: U2_ADDR_reg<1>         35: outDATA<7>\$WA3.UIM 
 10: U1/U3/holdingreg0<3>   23: U2_ADDR_reg<2>         36: outDATA<7>\$WA4.UIM 
 11: U1/U3/holdingreg0<8>   24: U2_ADDR_reg<3>         37: outDATA<7>\$WA5.UIM 
 12: U1/U3/holdingreg0<9>   25: U2_ADDR_reg<4>         38: outDATA<7>\$WA6.UIM 
 13: U1/U3/holdingreg1<0>   26: U2_ADDR_reg<5>        

Signal                     1         2         3         4 FB      
Name             0----+----0----+----0----+----0----+----0 Inputs  
AD<7>             ...X................XXXXXXXXX.XXXXXXXX.. 18      
outDATA<1>\$WA5   XX..................XXXX....XX.......... 8       
outDATA<3>\$WA6   ..X...X..X....X..X..XXXX....X........... 10      
outDATA<2>\$WA6   ..X..X..X....X..X...XXXX....X........... 10      
outDATA<1>\$WA6   ..X....X...X...X...XXXXX....X........... 10      
outDATA<0>\$WA6   ..X.X.....X.X.....X.XXXX....X........... 10      
                 0----+----1----+----2----+----3----+----4
                           0         0         0         0
*********************************** FB10 ***********************************
Number of function block inputs used/remaining:               38/2
Number of foldback NANDs used/remaining:                      0/8
Number of function block local control terms used/remaining:  0/8
Number of PLA product terms used/remaining:                   26/22
Number of function block global clocks used/remaining:  0/2
Signal                        Total Loc     Pin  Pin     Pin   GCK 
Name                          Pt            No.  Type    Use       
(unused)                      0     FB10_1       (b)           
(unused)                      0     FB10_2       (b)           
outDATA<4>\$WA0               4     FB10_3  131  TDI/I/O (b)   
AD<6>                         7     FB10_4  132  I/O     I/O   
(unused)                      0     FB10_5       (b)           
(unused)                      0     FB10_6       (b)           
(unused)                      0     FB10_7       (b)           
(unused)                      0     FB10_8       (b)           
(unused)                      0     FB10_9       (b)           
(unused)                      0     FB10_10      (b)           
(unused)                      0     FB10_11      (b)           
outDATA<0>\$WA4.UIM           1     FB10_12      (b)     (b)   
outDATA<0>\$WA3.UIM           1     FB10_13      (b)     (b)   
outDATA<2>\$WA5.UIM           1     FB10_14      (b)     (b)   
AD<5>                         7     FB10_15 133  I/O     I/O   
AD<4>                         8     FB10_16 134  I/O     I/O   

Signals Used by Logic in Function Block
  1: I2CS<0>            14: U2_ADDR_reg<4>       27: outDATA<5>\$WA0.UIM 
  2: INTbus             15: U2_ADDR_reg<5>       28: outDATA<5>\$WA1.UIM 
  3: N_PZ_1203          16: U2_ADDR_reg<6>       29: outDATA<5>\$WA2.UIM 
  4: N_PZ_1216          17: U2_ADDR_reg<7>       30: outDATA<5>\$WA3.UIM 
  5: RD                 18: U2_Enable_AD         31: outDATA<5>\$WA5.UIM 
  6: U1/U4/Latch0r<12>  19: WR                   32: outDATA<5>\$WA6.UIM 
  7: U1/U4/Latch0r<4>   20: outDATA<4>\$WA0.UIM  33: outDATA<6>\$WA0.UIM 
  8: U1/U4/Latch1r<12>  21: outDATA<4>\$WA1.UIM  34: outDATA<6>\$WA1.UIM 
  9: U1/U4/Latch1r<4>   22: outDATA<4>\$WA2.UIM  35: outDATA<6>\$WA2.UIM 
 10: U2_ADDR_reg<0>     23: outDATA<4>\$WA3.UIM  36: outDATA<6>\$WA3.UIM 
 11: U2_ADDR_reg<1>     24: outDATA<4>\$WA4.UIM  37: outDATA<6>\$WA5.UIM 
 12: U2_ADDR_reg<2>     25: outDATA<4>\$WA5.UIM  38: outDATA<6>\$WA6.UIM 
 13: U2_ADDR_reg<3>     26: outDATA<4>\$WA6.UIM 

Signal                     1         2         3         4 FB      
Name             0----+----0----+----0----+----0----+----0 Inputs  
outDATA<4>\$WA0   ...X.XXXXXXXX....X...................... 10      
AD<6>             ..X.X....XXXXXXXXXX.............XXXXXX.. 18      
outDATA<0>\$WA4   .X...................................... 1       
outDATA<0>\$WA3   X....................................... 1       
outDATA<2>\$WA5   ....................................X... 1       
AD<5>             ..X.X....XXXXXXXXXX.......XXXXXX........ 18      
AD<4>             ....X....XXXXXXXXXXXXXXXXX.............. 18      
                 0----+----1----+----2----+----3----+----4
                           0         0         0         0
*********************************** FB11 ***********************************
Number of function block inputs used/remaining:               19/21
Number of foldback NANDs used/remaining:                      0/8
Number of function block local control terms used/remaining:  0/8
Number of PLA product terms used/remaining:                   45/3
Number of function block global clocks used/remaining:  1/1
Signal                        Total Loc     Pin  Pin     Pin   GCK 
Name                          Pt            No.  Type    Use       
U1/Channel1<15>               3     FB11_1       (b)     (b)   Mclk
U1/Channel1<14>               3     FB11_2       (b)     (b)   Mclk
U1/Channel1<13>               3     FB11_3       (b)     (b)   Mclk
U1/Channel1<12>               3     FB11_4       (b)     (b)   Mclk
U1/Channel1<1>                3     FB11_5       (b)     (b)   Mclk
U1/Channel1<11>               3     FB11_6       (b)     (b)   Mclk
U1/Channel1<10>               3     FB11_7       (b)     (b)   Mclk
U1/Channel1<9>                3     FB11_8       (b)     (b)   Mclk
U1/Channel1<8>                3     FB11_9       (b)     (b)   Mclk
U1/Channel1<7>                3     FB11_10      (b)     (b)   Mclk
U1/Channel1<6>                3     FB11_11      (b)     (b)   Mclk
U1/Channel1<5>                3     FB11_12      (b)     (b)   Mclk
U1/Channel1<4>                3     FB11_13      (b)     (b)   Mclk
U1/Channel1<3>                3     FB11_14      (b)     (b)   Mclk
U1/Channel1<2>                3     FB11_15      (b)     (b)   Mclk
U11_U1/Line_last              0     FB11_16 119  I/O     I     Mclk

Signals Used by Logic in Function Block
  1: MSPReset           8: U1/Channel1<14>   14: U1/Channel1<5> 
  2: N_PZ_1194          9: U1/Channel1<15>   15: U1/Channel1<6> 
  3: U1/Channel1<0>    10: U1/Channel1<1>    16: U1/Channel1<7> 
  4: U1/Channel1<10>   11: U1/Channel1<2>    17: U1/Channel1<8> 
  5: U1/Channel1<11>   12: U1/Channel1<3>    18: U1/Channel1<9> 
  6: U1/Channel1<12>   13: U1/Channel1<4>    19: U1/U5/location_or0001 
  7: U1/Channel1<13>  

Signal                     1         2         3         4 FB      
Name             0----+----0----+----0----+----0----+----0 Inputs  
U1/Channel1<15>   XXXXXXXXXXXXXXXXXXX..................... 19      
U1/Channel1<14>   XXXXXXXX.XXXXXXXXXX..................... 18      
U1/Channel1<13>   XXXXXXX..XXXXXXXXXX..................... 17      
U1/Channel1<12>   XXXXXX...XXXXXXXXXX..................... 16      
U1/Channel1<1>    XXX......X........X..................... 5       
U1/Channel1<11>   XXXXX....XXXXXXXXXX..................... 15      
U1/Channel1<10>   XXXX.....XXXXXXXXXX..................... 14      
U1/Channel1<9>    XXX......XXXXXXXXXX..................... 13      
U1/Channel1<8>    XXX......XXXXXXXX.X..................... 12      
U1/Channel1<7>    XXX......XXXXXXX..X..................... 11      
U1/Channel1<6>    XXX......XXXXXX...X..................... 10      
U1/Channel1<5>    XXX......XXXXX....X..................... 9       
U1/Channel1<4>    XXX......XXXX.....X..................... 8       
U1/Channel1<3>    XXX......XXX......X..................... 7       
U1/Channel1<2>    XXX......XX.......X..................... 6       
                 0----+----1----+----2----+----3----+----4
                           0         0         0         0
*********************************** FB12 ***********************************
Number of function block inputs used/remaining:               38/2
Number of foldback NANDs used/remaining:                      0/8
Number of function block local control terms used/remaining:  0/8
Number of PLA product terms used/remaining:                   27/21
Number of function block global clocks used/remaining:  0/2
Signal                        Total Loc     Pin  Pin     Pin   GCK 
Name                          Pt            No.  Type    Use       
AD<0>                         8     FB12_1  139  I/O     I/O   
(unused)                      0     FB12_2       (b)           
AD<1>                         8     FB12_3  138  I/O     I/O   
AD<2>                         7     FB12_4  137  I/O     I/O   
(unused)                      0     FB12_5       (b)           
(unused)                      0     FB12_6       (b)           
(unused)                      0     FB12_7       (b)           
(unused)                      0     FB12_8       (b)           
(unused)                      0     FB12_9       (b)           
(unused)                      0     FB12_10      (b)           
(unused)                      0     FB12_11      (b)           
(unused)                      0     FB12_12      (b)           
AD<3>                         7     FB12_13 136  I/O     I/O   
(unused)                      0     FB12_14      (b)           
(unused)                      0     FB12_15      (b)           
outDATA<1>\$WA1.UIM           1     FB12_16      (b)     (b)   

Signals Used by Logic in Function Block
  1: N_PZ_1203           14: outDATA<0>\$WA0.UIM  27: outDATA<2>\$WA0.UIM 
  2: RD                  15: outDATA<0>\$WA1.UIM  28: outDATA<2>\$WA1.UIM 
  3: U11_U3_counterr<1>  16: outDATA<0>\$WA2.UIM  29: outDATA<2>\$WA2.UIM 
  4: U2_ADDR_reg<0>      17: outDATA<0>\$WA3.UIM  30: outDATA<2>\$WA3.UIM 
  5: U2_ADDR_reg<1>      18: outDATA<0>\$WA4.UIM  31: outDATA<2>\$WA5.UIM 
  6: U2_ADDR_reg<2>      19: outDATA<0>\$WA5.UIM  32: outDATA<2>\$WA6.UIM 
  7: U2_ADDR_reg<3>      20: outDATA<0>\$WA6.UIM  33: outDATA<3>\$WA0.UIM 
  8: U2_ADDR_reg<4>      21: outDATA<1>\$WA0.UIM  34: outDATA<3>\$WA1.UIM 
  9: U2_ADDR_reg<5>      22: outDATA<1>\$WA1.UIM  35: outDATA<3>\$WA2.UIM 
 10: U2_ADDR_reg<6>      23: outDATA<1>\$WA2.UIM  36: outDATA<3>\$WA3.UIM 
 11: U2_ADDR_reg<7>      24: outDATA<1>\$WA3.UIM  37: outDATA<3>\$WA5.UIM 
 12: U2_Enable_AD        25: outDATA<1>\$WA5.UIM  38: outDATA<3>\$WA6.UIM 
 13: WR                  26: outDATA<1>\$WA6.UIM 

Signal                     1         2         3         4 FB      
Name             0----+----0----+----0----+----0----+----0 Inputs  
AD<0>             .X.XXXXXXXXXXXXXXXXX.................... 18      
AD<1>             .X.XXXXXXXXXX.......XXXXXX.............. 17      
AD<2>             XX.XXXXXXXXXX.............XXXXXX........ 18      
AD<3>             XX.XXXXXXXXXX...................XXXXXX.. 18      
outDATA<1>\$WA1   ..X..................................... 1       
                 0----+----1----+----2----+----3----+----4
                           0         0         0         0
*********************************** FB13 ***********************************
Number of function block inputs used/remaining:               24/16
Number of foldback NANDs used/remaining:                      0/8
Number of function block local control terms used/remaining:  0/8
Number of PLA product terms used/remaining:                   45/3
Number of function block global clocks used/remaining:  1/1
Signal                        Total Loc     Pin  Pin     Pin   GCK 
Name                          Pt            No.  Type    Use       
U1/U3/holdingreg0<11>         2     FB13_1  61   I/O     I     Mclk
U1/U5/location_or0001         4     FB13_2       (b)     (b)   
U1/U3/holdingreg0<10>         2     FB13_3  62   I/O     I     Mclk
U1/U1/CurrState_Sreg0_FSM_FFd1
                              1     FB13_4       (b)     (b)   Mclk
N_PZ_1194                     2     FB13_5       (b)     (b)   
U1/U6/CurrState_Sreg0_FSM_FFd3
                              5     FB13_6       (b)     (b)   Mclk
U1/U6/CurrState_Sreg0_FSM_FFd1
                              1     FB13_7       (b)     (b)   Mclk
U1/U6/CurrState_Sreg0_FSM_FFd2
                              5     FB13_8       (b)     (b)   Mclk
U1/U6/CurrState_Sreg0_FSM_FFd4
                              4     FB13_9       (b)     (b)   Mclk
U1/U2/location_or0001         4     FB13_10      (b)     (b)   
N_PZ_1209                     2     FB13_11      (b)     (b)   
U1/U1/CurrState_Sreg0_FSM_FFd3
                              5     FB13_12      (b)     (b)   Mclk
U1/U1/CurrState_Sreg0_FSM_FFd2
                              5     FB13_13      (b)     (b)   Mclk
U1/U4/HE0stater               0     FB13_14 65   I/O     I     Mclk
U1/U1/CurrState_Sreg0_FSM_FFd4
                              4     FB13_15      (b)     (b)   Mclk
U1/U3/holdingreg0<0>          2     FB13_16 66   I/O     I     Mclk

Signals Used by Logic in Function Block
  1: AS                 9: U1/Channel0<10>                 17: U1/U3/holdingreg0<0> 
  2: MSPReset          10: U1/Channel0<11>                 18: U1/U3/holdingreg0<10> 
  3: N_PZ_1001         11: U1/NET3720                      19: U1/U3/holdingreg0<11> 
  4: PhaseA_Encoder0   12: U1/TP                           20: U1/U6/CurrState_Sreg0_FSM_FFd1 
  5: PhaseA_Encoder1   13: U1/U1/CurrState_Sreg0_FSM_FFd1  21: U1/U6/CurrState_Sreg0_FSM_FFd2 
  6: PhaseB_Encoder0   14: U1/U1/CurrState_Sreg0_FSM_FFd2  22: U1/U6/CurrState_Sreg0_FSM_FFd3 
  7: PhaseB_Encoder1   15: U1/U1/CurrState_Sreg0_FSM_FFd3  23: U1/U6/CurrState_Sreg0_FSM_FFd4 
  8: U1/Channel0<0>    16: U1/U1/CurrState_Sreg0_FSM_FFd4  24: U2_ASedge 

Signal                     1         2         3         4 FB      
Name             0----+----0----+----0----+----0----+----0 Inputs  
U1/U3/holdingreg0<11> 
                  XXX......X........X....X................ 6       
U1/U5/location_or0001 
                  ..........X........XXXX................. 5       
U1/U3/holdingreg0<10> 
                  XXX.....X........X.....X................ 6       
U1/U1/CurrState_Sreg0_FSM_FFd1 
                  .X.X.X.......XXX........................ 6       
N_PZ_1194         .X.................XXXX................. 5       
U1/U6/CurrState_Sreg0_FSM_FFd3 
                  .X..X.X.............XXX................. 6       
U1/U6/CurrState_Sreg0_FSM_FFd1 
                  .X..X.X.............XXX................. 6       
U1/U6/CurrState_Sreg0_FSM_FFd2 
                  .X..X.X.............XXX................. 6       
U1/U6/CurrState_Sreg0_FSM_FFd4 
                  .X..X.X.............XXX................. 6       
U1/U2/location_or0001 
                  ...........XXXXX........................ 5       
N_PZ_1209         .X..........XXXX........................ 5       
U1/U1/CurrState_Sreg0_FSM_FFd3 
                  .X.X.X.......XXX........................ 6       
U1/U1/CurrState_Sreg0_FSM_FFd2 
                  .X.X.X.......XXX........................ 6       
U1/U1/CurrState_Sreg0_FSM_FFd4 
                  .X.X.X.......XXX........................ 6       
U1/U3/holdingreg0<0> 
                  XXX....X........X......X................ 6       
                 0----+----1----+----2----+----3----+----4
                           0         0         0         0
*********************************** FB14 ***********************************
Number of function block inputs used/remaining:               38/2
Number of foldback NANDs used/remaining:                      0/8
Number of function block local control terms used/remaining:  1/7
Number of PLA product terms used/remaining:                   26/22
Number of function block global clocks used/remaining:  1/1
Signal                        Total Loc     Pin  Pin     Pin   GCK 
Name                          Pt            No.  Type    Use       
(unused)                      0     FB14_1       (b)           
U1/U4/HE1stater               0     FB14_2  47   I/O     I     Mclk
outDATA<4>\$WA6.UIM           4     FB14_3       (b)     (b)   
(unused)                      0     FB14_4       (b)           
(unused)                      0     FB14_5       (b)           
outDATA<3>\$WA1.UIM           1     FB14_6       (b)     (b)   
outDATA<2>\$WA3.UIM           1     FB14_7       (b)     (b)   
outDATA<2>\$WA1.UIM           1     FB14_8       (b)     (b)   
outDATA<1>\$WA3.UIM           1     FB14_9       (b)     (b)   
outDATA<7>\$WA0.UIM           4     FB14_10      (b)     (b)   
outDATA<7>\$WA6.UIM           4     FB14_11      (b)     (b)   
outDATA<6>\$WA6.UIM           4     FB14_12      (b)     (b)   
(unused)                      0     FB14_13 45   I/O     I     
(unused)                      0     FB14_14 44   I/O     I     
outDATA<5>\$WA6.UIM           4     FB14_15      (b)     (b)   
Home05ctrl                    3     FB14_16 43   I/O     O     Mclk

Signals Used by Logic in Function Block
  1: AD<1>.PIN              14: U1/U3/holdingreg0<7>   27: U11_U3_counterr<2> 
  2: I2CS<1>                15: U1/U3/holdingreg1<12>  28: U11_U3_counterr<3> 
  3: I2CS<2>                16: U1/U3/holdingreg1<13>  29: U2_ADDR_reg<0> 
  4: N_PZ_1195              17: U1/U3/holdingreg1<14>  30: U2_ADDR_reg<1> 
  5: N_PZ_1216              18: U1/U3/holdingreg1<15>  31: U2_ADDR_reg<2> 
  6: RD                     19: U1/U3/holdingreg1<4>   32: U2_ADDR_reg<3> 
  7: U1/U3/holdingreg0<12>  20: U1/U3/holdingreg1<5>   33: U2_ADDR_reg<4> 
  8: U1/U3/holdingreg0<13>  21: U1/U3/holdingreg1<6>   34: U2_ADDR_reg<5> 
  9: U1/U3/holdingreg0<14>  22: U1/U3/holdingreg1<7>   35: U2_ADDR_reg<6> 
 10: U1/U3/holdingreg0<15>  23: U1/U4/Latch0r<15>      36: U2_ADDR_reg<7> 
 11: U1/U3/holdingreg0<4>   24: U1/U4/Latch0r<7>       37: U2_Enable_AD 
 12: U1/U3/holdingreg0<5>   25: U1/U4/Latch1r<15>      38: WR 
 13: U1/U3/holdingreg0<6>   26: U1/U4/Latch1r<7>      

Signal                     1         2         3         4 FB      
Name             0----+----0----+----0----+----0----+----0 Inputs  
outDATA<4>\$WA6   ...X..X...X...X...X.........XXXX....X... 10      
outDATA<3>\$WA1   ...........................X............ 1       
outDATA<2>\$WA3   ..X..................................... 1       
outDATA<2>\$WA1   ..........................X............. 1       
outDATA<1>\$WA3   .X...................................... 1       
outDATA<7>\$WA0   ....X.................XXXX..XXXX....X... 10      
outDATA<7>\$WA6   ...X.....X...X...X...X......XXXX....X... 10      
outDATA<6>\$WA6   ...X....X...X...X...X.......XXXX....X... 10      
outDATA<5>\$WA6   ...X...X...X...X...X........XXXX....X... 10      
Home05ctrl        X....X......................XXXXXXXX.X.. 11      
                 0----+----1----+----2----+----3----+----4
                           0         0         0         0
*********************************** FB15 ***********************************
Number of function block inputs used/remaining:               38/2
Number of foldback NANDs used/remaining:                      0/8
Number of function block local control terms used/remaining:  0/8
Number of PLA product terms used/remaining:                   31/17
Number of function block global clocks used/remaining:  1/1
Signal                        Total Loc     Pin  Pin     Pin   GCK 
Name                          Pt            No.  Type    Use       
(unused)                      0     FB15_1       (b)           
outDATA<3>\$WA2.UIM           1     FB15_2       (b)     (b)   
U2_ADDR_reg<7>                3     FB15_3       (b)     (b)   Mclk
U1/U3/holdingreg0<5>          2     FB15_4       (b)     (b)   Mclk
GP_Motor1_1                   4     FB15_5  56   I/O     O     Mclk
U1/U3/holdingreg0<4>          2     FB15_6       (b)     (b)   Mclk
U1/U3/holdingreg0<3>          2     FB15_7       (b)     (b)   Mclk
U1/U3/holdingreg0<2>          2     FB15_8       (b)     (b)   Mclk
U1/U3/holdingreg0<1>          2     FB15_9       (b)     (b)   Mclk
U1/U3/holdingreg0<15>         2     FB15_10      (b)     (b)   Mclk
U1/U3/holdingreg0<14>         2     FB15_11      (b)     (b)   Mclk
U1/U3/holdingreg0<13>         2     FB15_12      (b)     (b)   Mclk
U2_ADDR_reg<4>                3     FB15_13      (b)     (b)   Mclk
U1/U3/holdingreg0<12>         2     FB15_14      (b)     (b)   Mclk
U2_ADDR_reg<6>                3     FB15_15      (b)     (b)   Mclk
U1/U4/InEdge1r                0     FB15_16 54   I/O     I     Mclk

Signals Used by Logic in Function Block
  1: AD<4>.PIN         14: U1/Channel0<1>         27: U1/U3/holdingreg0<5> 
  2: AD<6>.PIN         15: U1/Channel0<2>         28: U2_ADDR_reg<0> 
  3: AD<7>.PIN         16: U1/Channel0<3>         29: U2_ADDR_reg<1> 
  4: AS                17: U1/Channel0<4>         30: U2_ADDR_reg<2> 
  5: GP_Motor1_1       18: U1/Channel0<5>         31: U2_ADDR_reg<3> 
  6: MSPReset          19: U1/U3/holdingreg0<12>  32: U2_ADDR_reg<4> 
  7: NET3248           20: U1/U3/holdingreg0<13>  33: U2_ADDR_reg<5> 
  8: N_PZ_1001         21: U1/U3/holdingreg0<14>  34: U2_ADDR_reg<6> 
  9: RD                22: U1/U3/holdingreg0<15>  35: U2_ADDR_reg<7> 
 10: U1/Channel0<12>   23: U1/U3/holdingreg0<1>   36: U2_ASedge 
 11: U1/Channel0<13>   24: U1/U3/holdingreg0<2>   37: U2_WRRDedge_and0000 
 12: U1/Channel0<14>   25: U1/U3/holdingreg0<3>   38: WR 
 13: U1/Channel0<15>   26: U1/U3/holdingreg0<4>  

Signal                     1         2         3         4 FB      
Name             0----+----0----+----0----+----0----+----0 Inputs  
outDATA<3>\$WA2   ......X................................. 1       
U2_ADDR_reg<7>    ..XX.X............................XXX... 6       
U1/U3/holdingreg0<5> 
                  ...X.X.X.........X........X........X.... 6       
GP_Motor1_1       ..X.XX..X..................XXXXXXXX..X.. 13      
U1/U3/holdingreg0<4> 
                  ...X.X.X........X........X.........X.... 6       
U1/U3/holdingreg0<3> 
                  ...X.X.X.......X........X..........X.... 6       
U1/U3/holdingreg0<2> 
                  ...X.X.X......X........X...........X.... 6       
U1/U3/holdingreg0<1> 
                  ...X.X.X.....X........X............X.... 6       
U1/U3/holdingreg0<15> 
                  ...X.X.X....X........X.............X.... 6       
U1/U3/holdingreg0<14> 
                  ...X.X.X...X........X..............X.... 6       
U1/U3/holdingreg0<13> 
                  ...X.X.X..X........X...............X.... 6       
U2_ADDR_reg<4>    X..X.X.........................X...XX... 6       
U1/U3/holdingreg0<12> 
                  ...X.X.X.X........X................X.... 6       
U2_ADDR_reg<6>    .X.X.X...........................X.XX... 6       
                 0----+----1----+----2----+----3----+----4
                           0         0         0         0
*********************************** FB16 ***********************************
Number of function block inputs used/remaining:               38/2
Number of foldback NANDs used/remaining:                      0/8
Number of function block local control terms used/remaining:  0/8
Number of PLA product terms used/remaining:                   29/19
Number of function block global clocks used/remaining:  1/1
Signal                        Total Loc     Pin  Pin     Pin   GCK 
Name                          Pt            No.  Type    Use       
(unused)                      0     FB16_1       (b)           
(unused)                      0     FB16_2  48   I/O     I     
U1/U3/holdingreg1<14>         2     FB16_3       (b)     (b)   Mclk
U1/U3/holdingreg0<6>          2     FB16_4       (b)     (b)   Mclk
U1/U3/holdingreg1<13>         2     FB16_5       (b)     (b)   Mclk
U1/U3/holdingreg1<12>         2     FB16_6       (b)     (b)   Mclk
U1/U3/holdingreg1<11>         2     FB16_7       (b)     (b)   Mclk
U1/U3/holdingreg1<10>         2     FB16_8       (b)     (b)   Mclk
U1/U3/holdingreg1<0>          2     FB16_9       (b)     (b)   Mclk
U1/Channel0<15>               3     FB16_10      (b)     (b)   Mclk
U1/Channel0<14>               3     FB16_11      (b)     (b)   Mclk
U1/Channel0<13>               3     FB16_12      (b)     (b)   Mclk
U1/U3/holdingreg0<9>          2     FB16_13      (b)     (b)   Mclk
U1/U3/holdingreg0<8>          2     FB16_14      (b)     (b)   Mclk
U1/U3/holdingreg0<7>          2     FB16_15      (b)     (b)   Mclk
(unused)                      0     FB16_16 53   I/O     I     

Signals Used by Logic in Function Block
  1: AS                14: U1/Channel0<3>    27: U1/U2/location_or0001 
  2: MSPReset          15: U1/Channel0<4>    28: U1/U3/holdingreg0<6> 
  3: N_PZ_1001         16: U1/Channel0<5>    29: U1/U3/holdingreg0<7> 
  4: N_PZ_1209         17: U1/Channel0<6>    30: U1/U3/holdingreg0<8> 
  5: U1/Channel0<0>    18: U1/Channel0<7>    31: U1/U3/holdingreg0<9> 
  6: U1/Channel0<10>   19: U1/Channel0<8>    32: U1/U3/holdingreg1<0> 
  7: U1/Channel0<11>   20: U1/Channel0<9>    33: U1/U3/holdingreg1<10> 
  8: U1/Channel0<12>   21: U1/Channel1<0>    34: U1/U3/holdingreg1<11> 
  9: U1/Channel0<13>   22: U1/Channel1<10>   35: U1/U3/holdingreg1<12> 
 10: U1/Channel0<14>   23: U1/Channel1<11>   36: U1/U3/holdingreg1<13> 
 11: U1/Channel0<15>   24: U1/Channel1<12>   37: U1/U3/holdingreg1<14> 
 12: U1/Channel0<1>    25: U1/Channel1<13>   38: U2_ASedge 
 13: U1/Channel0<2>    26: U1/Channel1<14>  

Signal                     1         2         3         4 FB      
Name             0----+----0----+----0----+----0----+----0 Inputs  
U1/U3/holdingreg1<14> 
                  XXX......................X..........XX.. 6       
U1/U3/holdingreg0<6> 
                  XXX.............X..........X.........X.. 6       
U1/U3/holdingreg1<13> 
                  XXX.....................X..........X.X.. 6       
U1/U3/holdingreg1<12> 
                  XXX....................X..........X..X.. 6       
U1/U3/holdingreg1<11> 
                  XXX...................X..........X...X.. 6       
U1/U3/holdingreg1<10> 
                  XXX..................X..........X....X.. 6       
U1/U3/holdingreg1<0> 
                  XXX.................X..........X.....X.. 6       
U1/Channel0<15>   .X.XXXXXXXXXXXXXXXXX......X............. 19      
U1/Channel0<14>   .X.XXXXXXX.XXXXXXXXX......X............. 18      
U1/Channel0<13>   .X.XXXXXX..XXXXXXXXX......X............. 17      
U1/U3/holdingreg0<9> 
                  XXX................X..........X......X.. 6       
U1/U3/holdingreg0<8> 
                  XXX...............X..........X.......X.. 6       
U1/U3/holdingreg0<7> 
                  XXX..............X..........X........X.. 6       
                 0----+----1----+----2----+----3----+----4
                           0         0         0         0
*********************************** FB17 ***********************************
Number of function block inputs used/remaining:               33/7
Number of foldback NANDs used/remaining:                      0/8
Number of function block local control terms used/remaining:  0/8
Number of PLA product terms used/remaining:                   31/17
Number of function block global clocks used/remaining:  1/1
Signal                        Total Loc     Pin  Pin     Pin   GCK 
Name                          Pt            No.  Type    Use       
U1/U4/Latch1r<4>              2     FB17_1       (b)     (b)   Mclk
U1/U4/Latch1r<3>              2     FB17_2       (b)     (b)   Mclk
GPIO8                         1     FB17_3  6    I/O     O     
U1/U3/holdingreg1<15>         2     FB17_4       (b)     (b)   Mclk
U1/U3/holdingreg1<1>          2     FB17_5       (b)     (b)   Mclk
U1/U4/Latch1r<2>              2     FB17_6       (b)     (b)   Mclk
U1/U4/Latch1r<1>              2     FB17_7       (b)     (b)   Mclk
U1/U4/Latch1r<15>             2     FB17_8       (b)     (b)   Mclk
U1/U3/holdingreg1<9>          2     FB17_9       (b)     (b)   Mclk
U1/U3/holdingreg1<8>          2     FB17_10      (b)     (b)   Mclk
U1/U3/holdingreg1<7>          2     FB17_11      (b)     (b)   Mclk
U1/U3/holdingreg1<6>          2     FB17_12      (b)     (b)   Mclk
U1/U3/holdingreg1<5>          2     FB17_13      (b)     (b)   Mclk
U1/U3/holdingreg1<4>          2     FB17_14      (b)     (b)   Mclk
U1/U3/holdingreg1<2>          2     FB17_15      (b)     (b)   Mclk
U1/U3/holdingreg1<3>          2     FB17_16      (b)     (b)   Mclk

Signals Used by Logic in Function Block
  1: AS                12: U1/Channel1<6>         23: U1/U3/holdingreg1<7> 
  2: MSPReset          13: U1/Channel1<7>         24: U1/U3/holdingreg1<8> 
  3: N_PZ_1001         14: U1/Channel1<8>         25: U1/U3/holdingreg1<9> 
  4: N_PZ_1019         15: U1/Channel1<9>         26: U1/U4/Latch1r<15> 
  5: PWM5              16: U1/U3/holdingreg1<15>  27: U1/U4/Latch1r<1> 
  6: U1/Channel1<15>   17: U1/U3/holdingreg1<1>   28: U1/U4/Latch1r<2> 
  7: U1/Channel1<1>    18: U1/U3/holdingreg1<2>   29: U1/U4/Latch1r<3> 
  8: U1/Channel1<2>    19: U1/U3/holdingreg1<3>   30: U1/U4/Latch1r<4> 
  9: U1/Channel1<3>    20: U1/U3/holdingreg1<4>   31: U1/U4/latchitH1 
 10: U1/Channel1<4>    21: U1/U3/holdingreg1<5>   32: U1/U4/latchitL1 
 11: U1/Channel1<5>    22: U1/U3/holdingreg1<6>   33: U2_ASedge 

Signal                     1         2         3         4 FB      
Name             0----+----0----+----0----+----0----+----0 Inputs  
U1/U4/Latch1r<4>  .X.X.....X...................XXX........ 6       
U1/U4/Latch1r<3>  .X.X....X...................X.XX........ 6       
GPIO8             ....X................................... 1       
U1/U3/holdingreg1<15> 
                  XXX..X.........X................X....... 6       
U1/U3/holdingreg1<1> 
                  XXX...X.........X...............X....... 6       
U1/U4/Latch1r<2>  .X.X...X...................X..XX........ 6       
U1/U4/Latch1r<1>  .X.X..X...................X...XX........ 6       
U1/U4/Latch1r<15> 
                  .X.X.X...................X....XX........ 6       
U1/U3/holdingreg1<9> 
                  XXX...........X.........X.......X....... 6       
U1/U3/holdingreg1<8> 
                  XXX..........X.........X........X....... 6       
U1/U3/holdingreg1<7> 
                  XXX.........X.........X.........X....... 6       
U1/U3/holdingreg1<6> 
                  XXX........X.........X..........X....... 6       
U1/U3/holdingreg1<5> 
                  XXX.......X.........X...........X....... 6       
U1/U3/holdingreg1<4> 
                  XXX......X.........X............X....... 6       
U1/U3/holdingreg1<2> 
                  XXX....X.........X..............X....... 6       
U1/U3/holdingreg1<3> 
                  XXX.....X.........X.............X....... 6       
                 0----+----1----+----2----+----3----+----4
                           0         0         0         0
*********************************** FB18 ***********************************
Number of function block inputs used/remaining:               38/2
Number of foldback NANDs used/remaining:                      0/8
Number of function block local control terms used/remaining:  0/8
Number of PLA product terms used/remaining:                   26/22
Number of function block global clocks used/remaining:  1/1
Signal                        Total Loc     Pin  Pin     Pin   GCK 
Name                          Pt            No.  Type    Use       
GPIO9                         1     FB18_1  7    I/O     O     
GPIO10                        1     FB18_2  8    I/O     O     
U1/U4/Latch0r<0>              2     FB18_3       (b)     (b)   Mclk
(unused)                      0     FB18_4  10   I/O     I     
outDATA<3>\$WA3.UIM           1     FB18_5       (b)     (b)   
N_PZ_1021                     2     FB18_6       (b)     (b)   
U1/U4/Latch0r<2>              2     FB18_7       (b)     (b)   Mclk
U1/U4/Latch0r<1>              2     FB18_8       (b)     (b)   Mclk
U1/U4/Latch0r<15>             2     FB18_9       (b)     (b)   Mclk
U1/U4/Latch0r<14>             2     FB18_10      (b)     (b)   Mclk
U1/U4/Latch0r<13>             2     FB18_11      (b)     (b)   Mclk
U1/U4/Latch0r<12>             2     FB18_12      (b)     (b)   Mclk
U1/U4/Latch0r<11>             2     FB18_13      (b)     (b)   Mclk
U1/U4/Latch0r<10>             2     FB18_14      (b)     (b)   Mclk
MTRpwr                        4     FB18_15 11   I/O     O     Mclk
(unused)                      0     FB18_16 12   I/O     I     

Signals Used by Logic in Function Block
  1: AD<5>.PIN         14: U1/Channel0<13>    27: U1/U4/Latch0r<2> 
  2: I2CS<3>           15: U1/Channel0<14>    28: U1/U4/latchitH0 
  3: MSPReset          16: U1/Channel0<15>    29: U1/U4/latchitL0 
  4: MTRpwr            17: U1/Channel0<1>     30: U2_ADDR_reg<0> 
  5: N_PZ_1021         18: U1/Channel0<2>     31: U2_ADDR_reg<1> 
  6: PWM3              19: U1/U4/Latch0r<0>   32: U2_ADDR_reg<2> 
  7: PWM4              20: U1/U4/Latch0r<10>  33: U2_ADDR_reg<3> 
  8: RD                21: U1/U4/Latch0r<11>  34: U2_ADDR_reg<4> 
  9: TmpEn             22: U1/U4/Latch0r<12>  35: U2_ADDR_reg<5> 
 10: U1/Channel0<0>    23: U1/U4/Latch0r<13>  36: U2_ADDR_reg<6> 
 11: U1/Channel0<10>   24: U1/U4/Latch0r<14>  37: U2_ADDR_reg<7> 
 12: U1/Channel0<11>   25: U1/U4/Latch0r<15>  38: WR 
 13: U1/Channel0<12>   26: U1/U4/Latch0r<1>  

Signal                     1         2         3         4 FB      
Name             0----+----0----+----0----+----0----+----0 Inputs  
GPIO9             .....X..X............................... 2       
GPIO10            ......X.X............................... 2       
U1/U4/Latch0r<0>  ..X.X....X........X........XX........... 6       
outDATA<3>\$WA3   .X...................................... 1       
N_PZ_1021         ..X........................XX........... 3       
U1/U4/Latch0r<2>  ..X.X............X........XXX........... 6       
U1/U4/Latch0r<1>  ..X.X...........X........X.XX........... 6       
U1/U4/Latch0r<15> 
                  ..X.X..........X........X..XX........... 6       
U1/U4/Latch0r<14> 
                  ..X.X.........X........X...XX........... 6       
U1/U4/Latch0r<13> 
                  ..X.X........X........X....XX........... 6       
U1/U4/Latch0r<12> 
                  ..X.X.......X........X.....XX........... 6       
U1/U4/Latch0r<11> 
                  ..X.X......X........X......XX........... 6       
U1/U4/Latch0r<10> 
                  ..X.X.....X........X.......XX........... 6       
MTRpwr            X.XX...X.....................XXXXXXXXX.. 13      
                 0----+----1----+----2----+----3----+----4
                           0         0         0         0
*********************************** FB19 ***********************************
Number of function block inputs used/remaining:               37/3
Number of foldback NANDs used/remaining:                      0/8
Number of function block local control terms used/remaining:  1/7
Number of PLA product terms used/remaining:                   27/21
Number of function block global clocks used/remaining:  1/1
Signal                        Total Loc     Pin  Pin     Pin   GCK 
Name                          Pt            No.  Type    Use       
(unused)                      0     FB19_1       (b)           
PresSlct                      4     FB19_2  143  I/O     O     Mclk
(unused)                      0     FB19_3       (b)           
TmpSlct                       4     FB19_4  142  I/O     O     Mclk
TmpEn                         4     FB19_5  141  I/O     O     Mclk
(unused)                      0     FB19_6       (b)           
(unused)                      0     FB19_7       (b)           
(unused)                      0     FB19_8       (b)           
U1/U4/Latch0r<9>              2     FB19_9       (b)     (b)   Mclk
U1/U4/Latch0r<8>              2     FB19_10      (b)     (b)   Mclk
U1/U4/Latch0r<7>              2     FB19_11      (b)     (b)   Mclk
U1/U4/Latch0r<6>              2     FB19_12      (b)     (b)   Mclk
U1/U4/Latch0r<5>              2     FB19_13      (b)     (b)   Mclk
U1/U4/Latch0r<4>              2     FB19_14      (b)     (b)   Mclk
PresEn                        4     FB19_15 140  I/O     O     Mclk
U1/U4/Latch0r<3>              2     FB19_16      (b)     (b)   Mclk

Signals Used by Logic in Function Block
  1: AD<0>.PIN         14: U1/Channel0<4>    26: U1/U4/Latch0r<9> 
  2: AD<1>.PIN         15: U1/Channel0<5>    27: U1/U4/latchitH0 
  3: AD<2>.PIN         16: U1/Channel0<6>    28: U1/U4/latchitL0 
  4: AD<3>.PIN         17: U1/Channel0<7>    29: U2_ADDR_reg<0> 
  5: MReset            18: U1/Channel0<8>    30: U2_ADDR_reg<1> 
  6: MSPReset          19: U1/Channel0<9>    31: U2_ADDR_reg<2> 
  7: N_PZ_1021         20: U1/U4/Latch0r<3>  32: U2_ADDR_reg<3> 
  8: PresEn            21: U1/U4/Latch0r<4>  33: U2_ADDR_reg<4> 
  9: PresSlct          22: U1/U4/Latch0r<5>  34: U2_ADDR_reg<5> 
 10: RD                23: U1/U4/Latch0r<6>  35: U2_ADDR_reg<6> 
 11: TmpEn             24: U1/U4/Latch0r<7>  36: U2_ADDR_reg<7> 
 12: TmpSlct           25: U1/U4/Latch0r<8>  37: WR 
 13: U1/Channel0<3>   

Signal                     1         2         3         4 FB      
Name             0----+----0----+----0----+----0----+----0 Inputs  
PresSlct          .X...X..XX..................XXXXXXXXX... 13      
TmpSlct           ...X.X...X.X................XXXXXXXXX... 13      
TmpEn             ..X.XX...XX.................XXXXXXXXX... 14      
U1/U4/Latch0r<9>  .....XX...........X......XXX............ 6       
U1/U4/Latch0r<8>  .....XX..........X......X.XX............ 6       
U1/U4/Latch0r<7>  .....XX.........X......X..XX............ 6       
U1/U4/Latch0r<6>  .....XX........X......X...XX............ 6       
U1/U4/Latch0r<5>  .....XX.......X......X....XX............ 6       
U1/U4/Latch0r<4>  .....XX......X......X.....XX............ 6       
PresEn            X...XX.X.X..................XXXXXXXXX... 14      
U1/U4/Latch0r<3>  .....XX.....X......X......XX............ 6       
                 0----+----1----+----2----+----3----+----4
                           0         0         0         0
*********************************** FB20 ***********************************
Number of function block inputs used/remaining:               33/7
Number of foldback NANDs used/remaining:                      0/8
Number of function block local control terms used/remaining:  0/8
Number of PLA product terms used/remaining:                   28/20
Number of function block global clocks used/remaining:  1/1
Signal                        Total Loc     Pin  Pin     Pin   GCK 
Name                          Pt            No.  Type    Use       
TP12                          1     FB20_1  14   I/O     O     
N_PZ_1019                     2     FB20_2       (b)     (b)   
U1/U4/Latch1r<9>              2     FB20_3       (b)     (b)   Mclk
outDATA<4>\$WA1.UIM           1     FB20_4       (b)     (b)   
U1/U4/Latch1r<8>              2     FB20_5       (b)     (b)   Mclk
U1/U4/Latch1r<7>              2     FB20_6       (b)     (b)   Mclk
U1/U4/Latch1r<6>              2     FB20_7       (b)     (b)   Mclk
U1/U4/Latch1r<5>              2     FB20_8       (b)     (b)   Mclk
U1/U4/Latch1r<14>             2     FB20_9       (b)     (b)   Mclk
U1/U4/Latch1r<13>             2     FB20_10      (b)     (b)   Mclk
U1/U4/Latch1r<12>             2     FB20_11      (b)     (b)   Mclk
U1/U4/Latch1r<11>             2     FB20_12      (b)     (b)   Mclk
U1/U4/Latch1r<10>             2     FB20_13      (b)     (b)   Mclk
outDATA<5>\$WA1.UIM           1     FB20_14      (b)     (b)   
U1/U4/Latch1r<0>              2     FB20_15      (b)     (b)   Mclk
outDATA<4>\$WA3               1     FB20_16 18   I/O     I     

Signals Used by Logic in Function Block
  1: I2CS<4>           12: U1/Channel1<7>     23: U1/U4/Latch1r<7> 
  2: MSPReset          13: U1/Channel1<8>     24: U1/U4/Latch1r<8> 
  3: N_PZ_1019         14: U1/Channel1<9>     25: U1/U4/Latch1r<9> 
  4: U1/Channel1<0>    15: U1/U4/Latch1r<0>   26: U1/U4/latchitH1 
  5: U1/Channel1<10>   16: U1/U4/Latch1r<10>  27: U1/U4/latchitL1 
  6: U1/Channel1<11>   17: U1/U4/Latch1r<11>  28: U11_U3_counterr<0> 
  7: U1/Channel1<12>   18: U1/U4/Latch1r<12>  29: U11_U3_counterr<1> 
  8: U1/Channel1<13>   19: U1/U4/Latch1r<13>  30: U11_U3_counterr<2> 
  9: U1/Channel1<14>   20: U1/U4/Latch1r<14>  31: U11_U3_counterr<3> 
 10: U1/Channel1<5>    21: U1/U4/Latch1r<5>   32: U11_U3_counterr<4> 
 11: U1/Channel1<6>    22: U1/U4/Latch1r<6>   33: U11_U3_counterr<5> 

Signal                     1         2         3         4 FB      
Name             0----+----0----+----0----+----0----+----0 Inputs  
TP12              ...........................XXXXXX....... 6       
N_PZ_1019         .X.......................XX............. 3       
U1/U4/Latch1r<9>  .XX..........X..........XXX............. 6       
outDATA<4>\$WA1   ...............................X........ 1       
U1/U4/Latch1r<8>  .XX.........X..........X.XX............. 6       
U1/U4/Latch1r<7>  .XX........X..........X..XX............. 6       
U1/U4/Latch1r<6>  .XX.......X..........X...XX............. 6       
U1/U4/Latch1r<5>  .XX......X..........X....XX............. 6       
U1/U4/Latch1r<14> 
                  .XX.....X..........X.....XX............. 6       
U1/U4/Latch1r<13> 
                  .XX....X..........X......XX............. 6       
U1/U4/Latch1r<12> 
                  .XX...X..........X.......XX............. 6       
U1/U4/Latch1r<11> 
                  .XX..X..........X........XX............. 6       
U1/U4/Latch1r<10> 
                  .XX.X..........X.........XX............. 6       
outDATA<5>\$WA1   ................................X....... 1       
U1/U4/Latch1r<0>  .XXX..........X..........XX............. 6       
outDATA<4>\$WA3   X....................................... 1       
                 0----+----1----+----2----+----3----+----4
                           0         0         0         0
*********************************** FB21 ***********************************
Number of function block inputs used/remaining:               29/11
Number of foldback NANDs used/remaining:                      0/8
Number of function block local control terms used/remaining:  1/7
Number of PLA product terms used/remaining:                   20/28
Number of function block global clocks used/remaining:  1/1
Signal                        Total Loc     Pin  Pin     Pin   GCK 
Name                          Pt            No.  Type    Use       
outDATA<7>\$WA3.UIM           1     FB21_1       (b)     (b)   
outDATA<6>\$WA3.UIM           1     FB21_2       (b)     (b)   
U4/Flgreg<1>                  1     FB21_3  42   I/O     I     Mclk
U4/Flgreg<5>                  1     FB21_4  41   I/O     I     Mclk
outDATA<5>\$WA3.UIM           1     FB21_5       (b)     (b)   
outDATA<4>\$WA4.UIM           1     FB21_6       (b)     (b)   
outDATA<7>\$WA5.UIM           2     FB21_7       (b)     (b)   
outDATA<5>\$WA5.UIM           2     FB21_8       (b)     (b)   
outDATA<4>\$WA5.UIM           2     FB21_9       (b)     (b)   
U4/DCORIFG__or0000_bdd0       1     FB21_10      (b)     (b)   
outDATA<3>\$WA5.UIM           2     FB21_11      (b)     (b)   
outDATA<0>\$WA5.UIM           2     FB21_12      (b)     (b)   
Home15ctrl                    3     FB21_13 40   I/O     O     Mclk
U4/Flgreg<4>                  1     FB21_14 39   I/O     I     Mclk
Latch133ctrl                  3     FB21_15 38   I/O     O     Mclk
U4/Flgreg<0>                  1     FB21_16 37   I/O     I     Mclk

Signals Used by Logic in Function Block
  1: AD<4>.PIN         11: Latch133FLG       21: U2_ADDR_reg<6> 
  2: AD<5>.PIN         12: NET2528           22: U2_ADDR_reg<7> 
  3: Enc05FLG          13: NET2575           23: U4/DCORIFG__or0000_bdd0 
  4: Enc15FLG          14: RD                24: U4/Flgreg<0> 
  5: GP_Motor0_0       15: U2_ADDR_reg<0>    25: U4/Flgreg<3> 
  6: GP_Motor1_0       16: U2_ADDR_reg<1>    26: U4/Flgreg<4> 
  7: Home05FLG         17: U2_ADDR_reg<2>    27: U4/Flgreg<5> 
  8: Home15FLG         18: U2_ADDR_reg<3>    28: U4/Flgreg<7> 
  9: I2CS<5>           19: U2_ADDR_reg<4>    29: WR 
 10: Latch033FLG       20: U2_ADDR_reg<5>   

Signal                     1         2         3         4 FB      
Name             0----+----0----+----0----+----0----+----0 Inputs  
outDATA<7>\$WA3   .....X.................................. 1       
outDATA<6>\$WA3   ....X................................... 1       
outDATA<5>\$WA3   ........X............................... 1       
outDATA<4>\$WA4   ............X........................... 1       
outDATA<7>\$WA5   ...X.......X...............X............ 3       
outDATA<5>\$WA5   .......X...X..............X............. 3       
outDATA<4>\$WA5   ..........XX.............X.............. 3       
U4/DCORIFG__or0000_bdd0 
                  ..XX..XX.XX............................. 6       
outDATA<3>\$WA5   ..X........X............X............... 3       
outDATA<0>\$WA5   .........X.X...........X................ 3       
Home15ctrl        .X...........XXXXXXXXX......X........... 11      
Latch133ctrl      X............XXXXXXXXX......X........... 11      
                 0----+----1----+----2----+----3----+----4
                           0         0         0         0
*********************************** FB22 ***********************************
Number of function block inputs used/remaining:               11/29
Number of foldback NANDs used/remaining:                      0/8
Number of function block local control terms used/remaining:  0/8
Number of PLA product terms used/remaining:                   10/38
Number of function block global clocks used/remaining:  0/2
Signal                        Total Loc     Pin  Pin     Pin   GCK 
Name                          Pt            No.  Type    Use       
(unused)                      0     FB22_1  19   I/O     I     
(unused)                      0     FB22_2       (b)           
(unused)                      0     FB22_3  20   I/O     I     
(unused)                      0     FB22_4  21   I/O     I     
outDATA<2>\$WA2               1     FB22_5  22   TMS/I/O (b)   
(unused)                      0     FB22_6       (b)           
(unused)                      0     FB22_7       (b)           
(unused)                      0     FB22_8       (b)           
(unused)                      0     FB22_9       (b)           
outDATA<5>\$WA2.UIM           2     FB22_10      (b)     (b)   
outDATA<4>\$WA2.UIM           2     FB22_11      (b)     (b)   
outDATA<1>\$WA2.UIM           2     FB22_12      (b)     (b)   
(unused)                      0     FB22_13 23   I/O     I     
outDATA<0>\$WA2.UIM           2     FB22_14      (b)     (b)   
outDATA<6>\$WA2.UIM           1     FB22_15      (b)     (b)   
(unused)                      0     FB22_16 25   I/O     I     

Signals Used by Logic in Function Block
  1: FLS0               5: N_PZ_1029          9: U5/FLS1fr 
  2: FLS1               6: RLS0              10: U5/RLS0fr 
  3: Home0              7: RLS1              11: U5/RLS1fr 
  4: Home1              8: U5/FLS0fr        

Signal                     1         2         3         4 FB      
Name             0----+----0----+----0----+----0----+----0 Inputs  
outDATA<2>\$WA2   ..X.X................................... 2       
outDATA<5>\$WA2   .X..X...X............................... 3       
outDATA<4>\$WA2   ....X.X...X............................. 3       
outDATA<1>\$WA2   X...X..X................................ 3       
outDATA<0>\$WA2   ....XX...X.............................. 3       
outDATA<6>\$WA2   ...XX................................... 2       
                 0----+----1----+----2----+----3----+----4
                           0         0         0         0
*********************************** FB23 ***********************************
Number of function block inputs used/remaining:               11/29
Number of foldback NANDs used/remaining:                      0/8
Number of function block local control terms used/remaining:  1/7
Number of PLA product terms used/remaining:                   2/46
Number of function block global clocks used/remaining:  1/1
Signal                        Total Loc     Pin  Pin     Pin   GCK 
Name                          Pt            No.  Type    Use       
Latch033ctrl                  3     FB23_1  36   I/O     O     Mclk
(unused)                      0     FB23_2       (b)           
(unused)                      0     FB23_3       (b)           
(unused)                      0     FB23_4       (b)           
(unused)                      0     FB23_5       (b)           
(unused)                      0     FB23_6       (b)           
(unused)                      0     FB23_7       (b)           
(unused)                      0     FB23_8       (b)           
(unused)                      0     FB23_9       (b)           
(unused)                      0     FB23_10      (b)           
(unused)                      0     FB23_11      (b)           
(unused)                      0     FB23_12      (b)           
(unused)                      0     FB23_13      (b)           
(unused)                      0     FB23_14 35   I/O           
(unused)                      0     FB23_15      (b)           
(unused)                      0     FB23_16      (b)           

Signals Used by Logic in Function Block
  1: AD<0>.PIN          5: U2_ADDR_reg<2>     9: U2_ADDR_reg<6> 
  2: RD                 6: U2_ADDR_reg<3>    10: U2_ADDR_reg<7> 
  3: U2_ADDR_reg<0>     7: U2_ADDR_reg<4>    11: WR 
  4: U2_ADDR_reg<1>     8: U2_ADDR_reg<5>   

Signal                     1         2         3         4 FB      
Name             0----+----0----+----0----+----0----+----0 Inputs  
Latch033ctrl      XXXXXXXXXXX............................. 11      
                 0----+----1----+----2----+----3----+----4
                           0         0         0         0
*********************************** FB24 ***********************************
Number of function block inputs used/remaining:               21/19
Number of foldback NANDs used/remaining:                      0/8
Number of function block local control terms used/remaining:  1/7
Number of PLA product terms used/remaining:                   10/38
Number of function block global clocks used/remaining:  1/1
Signal                        Total Loc     Pin  Pin     Pin   GCK 
Name                          Pt            No.  Type    Use       
(unused)                      0     FB24_1  26   I/O     I     
Enc15ctrl                     3     FB24_2  27   I/O     O     Mclk
U4/Flgreg<7>                  1     FB24_3  28   I/O     I     Mclk
U4/Flgreg<3>                  1     FB24_4  29   I/O     I     Mclk
Enc05ctrl                     3     FB24_5  30   I/O     O     Mclk
(unused)                      0     FB24_6       (b)           
(unused)                      0     FB24_7       (b)           
(unused)                      0     FB24_8       (b)           
(unused)                      0     FB24_9       (b)           
(unused)                      0     FB24_10      (b)           
(unused)                      0     FB24_11      (b)           
(unused)                      0     FB24_12      (b)           
(unused)                      0     FB24_13      (b)           
(unused)                      0     FB24_14      (b)           
(unused)                      0     FB24_15      (b)           
TP26                          5     FB24_16 34   I/O     O     Mclk

Signals Used by Logic in Function Block
  1: AD<3>.PIN          8: TP26               15: U2_ADDR_reg<3> 
  2: AD<5>.PIN          9: U1/U4/InEdge0r     16: U2_ADDR_reg<4> 
  3: AD<7>.PIN         10: U1/U4/LastEdge0r   17: U2_ADDR_reg<5> 
  4: MSPReset          11: U1/U4/LatchEdge0r  18: U2_ADDR_reg<6> 
  5: NET2528           12: U2_ADDR_reg<0>     19: U2_ADDR_reg<7> 
  6: N_PZ_1030         13: U2_ADDR_reg<1>     20: U4/DCORIFG__or0000_bdd0 
  7: RD                14: U2_ADDR_reg<2>     21: WR 

Signal                     1         2         3         4 FB      
Name             0----+----0----+----0----+----0----+----0 Inputs  
Enc15ctrl         ..X...X....XXXXXXXX.X................... 11      
Enc05ctrl         X.....X....XXXXXXXX.X................... 11      
TP26              .X.X.XXXXXXXXXXXXXX.X................... 17      
                 0----+----1----+----2----+----3----+----4
                           0         0         0         0
*******************************  Equations  ********************************

********** Mapped Logic **********

!AD<0> = U2_ADDR_reg<2> & !U2_ADDR_reg<3> & U2_Enable_AD & 
	!outDATA<0>\$WA6.UIM
	# !U2_ADDR_reg<2> & U2_ADDR_reg<3> & U2_Enable_AD & 
	!outDATA<0>\$WA0.UIM
	# U2_ADDR_reg<2> & U2_ADDR_reg<0> & U2_ADDR_reg<1> & 
	U2_ADDR_reg<3> & U2_Enable_AD & !outDATA<0>\$WA3.UIM
	# U2_ADDR_reg<2> & !U2_ADDR_reg<0> & U2_ADDR_reg<1> & 
	U2_ADDR_reg<3> & U2_Enable_AD & !outDATA<0>\$WA5.UIM
	# !U2_ADDR_reg<2> & WR & !RD & !U2_ADDR_reg<4> & 
	!U2_ADDR_reg<5> & !U2_ADDR_reg<6> & !U2_ADDR_reg<7> & U2_ADDR_reg<1> & 
	!U2_ADDR_reg<3> & !outDATA<0>\$WA2.UIM
	# !U2_ADDR_reg<2> & WR & !RD & U2_ADDR_reg<0> & 
	!U2_ADDR_reg<4> & !U2_ADDR_reg<5> & !U2_ADDR_reg<6> & !U2_ADDR_reg<7> & 
	!U2_ADDR_reg<1> & !U2_ADDR_reg<3> & !outDATA<0>\$WA4.UIM
	# !U2_ADDR_reg<2> & WR & !RD & !U2_ADDR_reg<0> & 
	!U2_ADDR_reg<4> & !U2_ADDR_reg<5> & !U2_ADDR_reg<6> & !U2_ADDR_reg<7> & 
	!U2_ADDR_reg<1> & !U2_ADDR_reg<3> & !outDATA<0>\$WA1.UIM;	// (7 pt, 18 inp)
    AD<0>.OE = U2_Enable_AD;	// UOE	(1 pt, 1 inp)

!AD<1> = U2_ADDR_reg<2> & !U2_ADDR_reg<3> & U2_Enable_AD & 
	!outDATA<1>\$WA6.UIM
	# !U2_ADDR_reg<2> & U2_ADDR_reg<3> & U2_Enable_AD & 
	!outDATA<1>\$WA0.UIM
	# U2_ADDR_reg<2> & U2_ADDR_reg<0> & U2_ADDR_reg<1> & 
	U2_ADDR_reg<3> & U2_Enable_AD & !outDATA<1>\$WA3.UIM
	# U2_ADDR_reg<2> & !U2_ADDR_reg<0> & U2_ADDR_reg<1> & 
	U2_ADDR_reg<3> & U2_Enable_AD & !outDATA<1>\$WA5.UIM
	# !U2_ADDR_reg<2> & WR & !RD & !U2_ADDR_reg<4> & 
	!U2_ADDR_reg<5> & !U2_ADDR_reg<6> & !U2_ADDR_reg<7> & U2_ADDR_reg<1> & 
	!U2_ADDR_reg<3> & !outDATA<1>\$WA2.UIM
	# !U2_ADDR_reg<2> & WR & !RD & U2_ADDR_reg<0> & 
	!U2_ADDR_reg<4> & !U2_ADDR_reg<5> & !U2_ADDR_reg<6> & !U2_ADDR_reg<7> & 
	!U2_ADDR_reg<1> & !U2_ADDR_reg<3> & !outDATA<1>\$WA5.UIM
	# !U2_ADDR_reg<2> & WR & !RD & !U2_ADDR_reg<0> & 
	!U2_ADDR_reg<4> & !U2_ADDR_reg<5> & !U2_ADDR_reg<6> & !U2_ADDR_reg<7> & 
	!U2_ADDR_reg<1> & !U2_ADDR_reg<3> & !outDATA<1>\$WA1.UIM;	// (7 pt, 17 inp)
    AD<1>.OE = U2_Enable_AD;	// UOE	(1 pt, 1 inp)

!AD<2> = N_PZ_1203 & !outDATA<2>\$WA0.UIM
	# U2_ADDR_reg<2> & !U2_ADDR_reg<3> & U2_Enable_AD & 
	!outDATA<2>\$WA6.UIM
	# U2_ADDR_reg<2> & U2_ADDR_reg<0> & U2_ADDR_reg<1> & 
	U2_ADDR_reg<3> & U2_Enable_AD & !outDATA<2>\$WA3.UIM
	# U2_ADDR_reg<2> & !U2_ADDR_reg<0> & U2_ADDR_reg<1> & 
	U2_ADDR_reg<3> & U2_Enable_AD & !outDATA<2>\$WA5.UIM
	# !U2_ADDR_reg<2> & WR & !RD & !U2_ADDR_reg<4> & 
	!U2_ADDR_reg<5> & !U2_ADDR_reg<6> & !U2_ADDR_reg<7> & U2_ADDR_reg<1> & 
	!U2_ADDR_reg<3> & !outDATA<2>\$WA2.UIM
	# !U2_ADDR_reg<2> & WR & !RD & !U2_ADDR_reg<0> & 
	!U2_ADDR_reg<4> & !U2_ADDR_reg<5> & !U2_ADDR_reg<6> & !U2_ADDR_reg<7> & 
	!U2_ADDR_reg<1> & !U2_ADDR_reg<3> & !outDATA<2>\$WA1.UIM;	// (6 pt, 18 inp)
    AD<2>.OE = U2_Enable_AD;	// UOE	(1 pt, 1 inp)

!AD<3> = N_PZ_1203 & !outDATA<3>\$WA0.UIM
	# U2_ADDR_reg<2> & !U2_ADDR_reg<3> & U2_Enable_AD & 
	!outDATA<3>\$WA6.UIM
	# U2_ADDR_reg<2> & U2_ADDR_reg<0> & U2_ADDR_reg<1> & 
	U2_ADDR_reg<3> & U2_Enable_AD & !outDATA<3>\$WA3.UIM
	# U2_ADDR_reg<2> & !U2_ADDR_reg<0> & U2_ADDR_reg<1> & 
	U2_ADDR_reg<3> & U2_Enable_AD & !outDATA<3>\$WA5.UIM
	# !U2_ADDR_reg<2> & WR & !RD & !U2_ADDR_reg<4> & 
	!U2_ADDR_reg<5> & !U2_ADDR_reg<6> & !U2_ADDR_reg<7> & U2_ADDR_reg<1> & 
	!U2_ADDR_reg<3> & !outDATA<3>\$WA2.UIM
	# !U2_ADDR_reg<2> & WR & !RD & !U2_ADDR_reg<0> & 
	!U2_ADDR_reg<4> & !U2_ADDR_reg<5> & !U2_ADDR_reg<6> & !U2_ADDR_reg<7> & 
	!U2_ADDR_reg<1> & !U2_ADDR_reg<3> & !outDATA<3>\$WA1.UIM;	// (6 pt, 18 inp)
    AD<3>.OE = U2_Enable_AD;	// UOE	(1 pt, 1 inp)

!AD<4> = U2_ADDR_reg<2> & !U2_ADDR_reg<3> & U2_Enable_AD & 
	!outDATA<4>\$WA6.UIM
	# !U2_ADDR_reg<2> & U2_ADDR_reg<3> & U2_Enable_AD & 
	!outDATA<4>\$WA0.UIM
	# U2_ADDR_reg<2> & U2_ADDR_reg<0> & U2_ADDR_reg<1> & 
	U2_ADDR_reg<3> & U2_Enable_AD & !outDATA<4>\$WA3.UIM
	# U2_ADDR_reg<2> & !U2_ADDR_reg<0> & U2_ADDR_reg<1> & 
	U2_ADDR_reg<3> & U2_Enable_AD & !outDATA<4>\$WA5.UIM
	# !U2_ADDR_reg<2> & WR & !RD & !U2_ADDR_reg<4> & 
	!U2_ADDR_reg<5> & !U2_ADDR_reg<6> & !U2_ADDR_reg<7> & U2_ADDR_reg<1> & 
	!U2_ADDR_reg<3> & !outDATA<4>\$WA2.UIM
	# !U2_ADDR_reg<2> & WR & !RD & U2_ADDR_reg<0> & 
	!U2_ADDR_reg<4> & !U2_ADDR_reg<5> & !U2_ADDR_reg<6> & !U2_ADDR_reg<7> & 
	!U2_ADDR_reg<1> & !U2_ADDR_reg<3> & !outDATA<4>\$WA4.UIM
	# !U2_ADDR_reg<2> & WR & !RD & !U2_ADDR_reg<0> & 
	!U2_ADDR_reg<4> & !U2_ADDR_reg<5> & !U2_ADDR_reg<6> & !U2_ADDR_reg<7> & 
	!U2_ADDR_reg<1> & !U2_ADDR_reg<3> & !outDATA<4>\$WA1.UIM;	// (7 pt, 18 inp)
    AD<4>.OE = U2_Enable_AD;	// UOE	(1 pt, 1 inp)

!AD<5> = N_PZ_1203 & !outDATA<5>\$WA0.UIM
	# U2_ADDR_reg<2> & !U2_ADDR_reg<3> & U2_Enable_AD & 
	!outDATA<5>\$WA6.UIM
	# U2_ADDR_reg<2> & U2_ADDR_reg<0> & U2_ADDR_reg<1> & 
	U2_ADDR_reg<3> & U2_Enable_AD & !outDATA<5>\$WA3.UIM
	# U2_ADDR_reg<2> & !U2_ADDR_reg<0> & U2_ADDR_reg<1> & 
	U2_ADDR_reg<3> & U2_Enable_AD & !outDATA<5>\$WA5.UIM
	# !U2_ADDR_reg<2> & WR & !RD & !U2_ADDR_reg<4> & 
	!U2_ADDR_reg<5> & !U2_ADDR_reg<6> & !U2_ADDR_reg<7> & U2_ADDR_reg<1> & 
	!U2_ADDR_reg<3> & !outDATA<5>\$WA2.UIM
	# !U2_ADDR_reg<2> & WR & !RD & !U2_ADDR_reg<0> & 
	!U2_ADDR_reg<4> & !U2_ADDR_reg<5> & !U2_ADDR_reg<6> & !U2_ADDR_reg<7> & 
	!U2_ADDR_reg<1> & !U2_ADDR_reg<3> & !outDATA<5>\$WA1.UIM;	// (6 pt, 18 inp)
    AD<5>.OE = U2_Enable_AD;	// UOE	(1 pt, 1 inp)

!AD<6> = N_PZ_1203 & !outDATA<6>\$WA0.UIM
	# U2_ADDR_reg<2> & !U2_ADDR_reg<3> & U2_Enable_AD & 
	!outDATA<6>\$WA6.UIM
	# U2_ADDR_reg<2> & U2_ADDR_reg<0> & U2_ADDR_reg<1> & 
	U2_ADDR_reg<3> & U2_Enable_AD & !outDATA<6>\$WA3.UIM
	# U2_ADDR_reg<2> & !U2_ADDR_reg<0> & U2_ADDR_reg<1> & 
	U2_ADDR_reg<3> & U2_Enable_AD & outDATA<6>\$WA5.UIM
	# !U2_ADDR_reg<2> & WR & !RD & !U2_ADDR_reg<4> & 
	!U2_ADDR_reg<5> & !U2_ADDR_reg<6> & !U2_ADDR_reg<7> & U2_ADDR_reg<1> & 
	!U2_ADDR_reg<3> & !outDATA<6>\$WA2.UIM
	# !U2_ADDR_reg<2> & WR & !RD & !U2_ADDR_reg<0> & 
	!U2_ADDR_reg<4> & !U2_ADDR_reg<5> & !U2_ADDR_reg<6> & !U2_ADDR_reg<7> & 
	!U2_ADDR_reg<1> & !U2_ADDR_reg<3> & !outDATA<6>\$WA1.UIM;	// (6 pt, 18 inp)
    AD<6>.OE = U2_Enable_AD;	// UOE	(1 pt, 1 inp)

!AD<7> = U2_ADDR_reg<2> & !U2_ADDR_reg<3> & U2_Enable_AD & 
	!outDATA<7>\$WA6.UIM
	# !U2_ADDR_reg<2> & U2_ADDR_reg<3> & U2_Enable_AD & 
	!outDATA<7>\$WA0.UIM
	# U2_ADDR_reg<2> & U2_ADDR_reg<0> & U2_ADDR_reg<1> & 
	U2_ADDR_reg<3> & U2_Enable_AD & !outDATA<7>\$WA3.UIM
	# U2_ADDR_reg<2> & !U2_ADDR_reg<0> & U2_ADDR_reg<1> & 
	U2_ADDR_reg<3> & U2_Enable_AD & !outDATA<7>\$WA5.UIM
	# !U2_ADDR_reg<2> & WR & !RD & !U2_ADDR_reg<4> & 
	!U2_ADDR_reg<5> & !U2_ADDR_reg<6> & !U2_ADDR_reg<7> & U2_ADDR_reg<1> & 
	!U2_ADDR_reg<3> & !outDATA<7>\$WA2.UIM
	# !U2_ADDR_reg<2> & WR & !RD & U2_ADDR_reg<0> & 
	!U2_ADDR_reg<4> & !U2_ADDR_reg<5> & !U2_ADDR_reg<6> & !U2_ADDR_reg<7> & 
	!U2_ADDR_reg<1> & !U2_ADDR_reg<3> & !outDATA<7>\$WA4.UIM
	# !U2_ADDR_reg<2> & WR & !RD & !U2_ADDR_reg<0> & 
	!U2_ADDR_reg<4> & !U2_ADDR_reg<5> & !U2_ADDR_reg<6> & !U2_ADDR_reg<7> & 
	!U2_ADDR_reg<1> & !U2_ADDR_reg<3> & !outDATA<7>\$WA1.UIM;	// (7 pt, 18 inp)
    AD<7>.OE = U2_Enable_AD;	// UOE	(1 pt, 1 inp)

Enc05ctrl := !AD<3>.PIN;	// (1 pt, 1 inp)
   Enc05ctrl.CLK  =  !Mclk;	// GCK	(0 pt, 0 inp)
    Enc05ctrl.CE = U2_ADDR_reg<2> & !WR & RD & !U2_ADDR_reg<0> & 
	!U2_ADDR_reg<4> & !U2_ADDR_reg<5> & !U2_ADDR_reg<6> & !U2_ADDR_reg<7> & 
	U2_ADDR_reg<1> & U2_ADDR_reg<3>;	// (1 pt, 10 inp)
   !Enc05ctrl.AP = MSPReset;	// UPST	(1 pt, 2 inp)

Enc15ctrl := !AD<7>.PIN;	// (1 pt, 1 inp)
   Enc15ctrl.CLK  =  !Mclk;	// GCK	(0 pt, 0 inp)
    Enc15ctrl.CE = U2_ADDR_reg<2> & !WR & RD & !U2_ADDR_reg<0> & 
	!U2_ADDR_reg<4> & !U2_ADDR_reg<5> & !U2_ADDR_reg<6> & !U2_ADDR_reg<7> & 
	U2_ADDR_reg<1> & U2_ADDR_reg<3>;	// (1 pt, 10 inp)
   !Enc15ctrl.AP = MSPReset;	// UPST	(1 pt, 2 inp)

GPIO10 = PWM4 & !TmpEn;	// (1 pt, 2 inp)

GPIO8 = PWM5;	// (1 pt, 1 inp)

GPIO9 = !TmpEn & PWM3;	// (1 pt, 2 inp)

GP_Motor0_1.T := !MSPReset & GP_Motor0_1
	# U2_ADDR_reg<2> & !WR & RD & U2_ADDR_reg<0> & 
	!U2_ADDR_reg<4> & !U2_ADDR_reg<5> & !U2_ADDR_reg<6> & !AD<6>.PIN & 
	!U2_ADDR_reg<7> & U2_ADDR_reg<1> & U2_ADDR_reg<3> & GP_Motor0_1
	# U2_ADDR_reg<2> & MSPReset & !WR & RD & 
	U2_ADDR_reg<0> & !U2_ADDR_reg<4> & !U2_ADDR_reg<5> & !U2_ADDR_reg<6> & 
	AD<6>.PIN & !U2_ADDR_reg<7> & U2_ADDR_reg<1> & U2_ADDR_reg<3> & 
	!GP_Motor0_1;	// (3 pt, 13 inp)
   GP_Motor0_1.CLK  =  !Mclk;	// GCK	(0 pt, 0 inp)
    GP_Motor0_1.AR = MReset;	// URST	(1 pt, 1 inp)

GP_Motor1_1.T := !MSPReset & GP_Motor1_1
	# U2_ADDR_reg<2> & !WR & RD & U2_ADDR_reg<0> & 
	!U2_ADDR_reg<4> & !U2_ADDR_reg<5> & !U2_ADDR_reg<6> & !U2_ADDR_reg<7> & 
	!AD<7>.PIN & U2_ADDR_reg<1> & U2_ADDR_reg<3> & GP_Motor1_1
	# U2_ADDR_reg<2> & MSPReset & !WR & RD & 
	U2_ADDR_reg<0> & !U2_ADDR_reg<4> & !U2_ADDR_reg<5> & !U2_ADDR_reg<6> & 
	!U2_ADDR_reg<7> & AD<7>.PIN & U2_ADDR_reg<1> & U2_ADDR_reg<3> & 
	!GP_Motor1_1;	// (3 pt, 13 inp)
   GP_Motor1_1.CLK  =  !Mclk;	// GCK	(0 pt, 0 inp)
    GP_Motor1_1.AR = MReset;	// URST	(1 pt, 1 inp)

Home05ctrl := !AD<1>.PIN;	// (1 pt, 1 inp)
   Home05ctrl.CLK  =  !Mclk;	// GCK	(0 pt, 0 inp)
    Home05ctrl.CE = U2_ADDR_reg<2> & !WR & RD & !U2_ADDR_reg<0> & 
	!U2_ADDR_reg<4> & !U2_ADDR_reg<5> & !U2_ADDR_reg<6> & !U2_ADDR_reg<7> & 
	U2_ADDR_reg<1> & U2_ADDR_reg<3>;	// (1 pt, 10 inp)
   !Home05ctrl.AP = MSPReset;	// UPST	(1 pt, 2 inp)

Home15ctrl := !AD<5>.PIN;	// (1 pt, 1 inp)
   Home15ctrl.CLK  =  !Mclk;	// GCK	(0 pt, 0 inp)
    Home15ctrl.CE = U2_ADDR_reg<2> & !WR & RD & !U2_ADDR_reg<0> & 
	!U2_ADDR_reg<4> & !U2_ADDR_reg<5> & !U2_ADDR_reg<6> & !U2_ADDR_reg<7> & 
	U2_ADDR_reg<1> & U2_ADDR_reg<3>;	// (1 pt, 10 inp)
   !Home15ctrl.AP = MSPReset;	// UPST	(1 pt, 2 inp)

INT = NET2482 & U3/DCORIE<2>
	# TP26 & TP21
	# NET2493 & U3/DCORIE<3>
	# NET2512 & U3/DCORIE<6>
	# TP12 & U3/DCORIE<7>
	# !INTbus & U3/DCORIE<0>
	# NET2528 & U3/DCORIE<1>
	# NET2575 & U3/DCORIE<4>;	// (8 pt, 16 inp)

!LED1 = LightSense & !U9/MISCr<0>;	// (1 pt, 2 inp)

!LED2 = LightSense & !U9/MISCr<1>;	// (1 pt, 2 inp)

!LED3 = LightSense & !U9/MISCr<2>;	// (1 pt, 2 inp)

!LED4 = LightSense & !U9/MISCr<3>;	// (1 pt, 2 inp)

!LED5 = LightSense & !U9/MISCr<4>;	// (1 pt, 2 inp)

Latch033ctrl := !AD<0>.PIN;	// (1 pt, 1 inp)
   Latch033ctrl.CLK  =  !Mclk;	// GCK	(0 pt, 0 inp)
    Latch033ctrl.CE = U2_ADDR_reg<2> & !WR & RD & !U2_ADDR_reg<0> & 
	!U2_ADDR_reg<4> & !U2_ADDR_reg<5> & !U2_ADDR_reg<6> & !U2_ADDR_reg<7> & 
	U2_ADDR_reg<1> & U2_ADDR_reg<3>;	// (1 pt, 10 inp)
   !Latch033ctrl.AP = MSPReset;	// UPST	(1 pt, 2 inp)

Latch133ctrl := !AD<4>.PIN;	// (1 pt, 1 inp)
   Latch133ctrl.CLK  =  !Mclk;	// GCK	(0 pt, 0 inp)
    Latch133ctrl.CE = U2_ADDR_reg<2> & !WR & RD & !U2_ADDR_reg<0> & 
	!U2_ADDR_reg<4> & !U2_ADDR_reg<5> & !U2_ADDR_reg<6> & !U2_ADDR_reg<7> & 
	U2_ADDR_reg<1> & U2_ADDR_reg<3>;	// (1 pt, 10 inp)
   !Latch133ctrl.AP = MSPReset;	// UPST	(1 pt, 2 inp)

MTRpwr.T := !MSPReset & MTRpwr
	# U2_ADDR_reg<2> & !WR & RD & U2_ADDR_reg<0> & 
	!U2_ADDR_reg<4> & !U2_ADDR_reg<5> & !AD<5>.PIN & !U2_ADDR_reg<6> & 
	!U2_ADDR_reg<7> & U2_ADDR_reg<1> & U2_ADDR_reg<3> & MTRpwr
	# U2_ADDR_reg<2> & MSPReset & !WR & RD & 
	U2_ADDR_reg<0> & !U2_ADDR_reg<4> & !U2_ADDR_reg<5> & AD<5>.PIN & 
	!U2_ADDR_reg<6> & !U2_ADDR_reg<7> & U2_ADDR_reg<1> & U2_ADDR_reg<3> & 
	!MTRpwr;	// (3 pt, 13 inp)
   MTRpwr.CLK  =  !Mclk;	// GCK	(0 pt, 0 inp)
    MTRpwr.AR = MReset;	// URST	(1 pt, 1 inp)

MTRpwrn.T := !MSPReset & !MTRpwrn
	# U2_ADDR_reg<2> & !WR & RD & U2_ADDR_reg<0> & 
	!U2_ADDR_reg<4> & !U2_ADDR_reg<5> & !AD<5>.PIN & !U2_ADDR_reg<6> & 
	!U2_ADDR_reg<7> & U2_ADDR_reg<1> & U2_ADDR_reg<3> & !MTRpwrn
	# U2_ADDR_reg<2> & MSPReset & !WR & RD & 
	U2_ADDR_reg<0> & !U2_ADDR_reg<4> & !U2_ADDR_reg<5> & AD<5>.PIN & 
	!U2_ADDR_reg<6> & !U2_ADDR_reg<7> & U2_ADDR_reg<1> & U2_ADDR_reg<3> & 
	MTRpwrn;	// (3 pt, 13 inp)
   MTRpwrn.CLK  =  !Mclk;	// GCK	(0 pt, 0 inp)
   !MTRpwrn.AP = !MReset;	// LPST	(1 pt, 2 inp)

!NET2482 := !MSPReset
	# !NET2482 & !U1/U4/E0r
	# !NET2482 & U1/U4/RF0r & !U1/U4/HE0stater
	# !NET2482 & !U1/U4/RF0r & !U1/U4/HE0statelastr
	# !NET2482 & U1/U4/HE0stater & U1/U4/HE0statelastr
	# !U2_ADDR_reg<2> & !WR & RD & U2_ADDR_reg<0> & 
	!U2_ADDR_reg<4> & !U2_ADDR_reg<5> & !U2_ADDR_reg<6> & !U2_ADDR_reg<7> & 
	!U2_ADDR_reg<3> & !NET2482
	# !U2_ADDR_reg<2> & AD<2>.PIN & !WR & RD & 
	U2_ADDR_reg<0> & !U2_ADDR_reg<4> & !U2_ADDR_reg<5> & !U2_ADDR_reg<6> & 
	!U2_ADDR_reg<7> & !U2_ADDR_reg<1> & !U2_ADDR_reg<3>;	// (7 pt, 17 inp)
   NET2482.CLK  =  !Mclk;	// GCK	(0 pt, 0 inp)

!NET2493 := !MSPReset
	# !NET2493 & !U1/U4/E1r
	# !NET2493 & U1/U4/RF1r & !U1/U4/HE1stater
	# !NET2493 & U1/U4/RF1r & U1/U4/HE1statelastr
	# !NET2493 & !U1/U4/RF1r & U1/U4/HE1stater
	# !NET2493 & !U1/U4/RF1r & !U1/U4/HE1statelastr
	# !U2_ADDR_reg<2> & !WR & RD & U2_ADDR_reg<0> & 
	!U2_ADDR_reg<4> & !U2_ADDR_reg<5> & !U2_ADDR_reg<6> & !U2_ADDR_reg<7> & 
	!U2_ADDR_reg<3> & !NET2493
	# !U2_ADDR_reg<2> & !WR & RD & U2_ADDR_reg<0> & 
	!U2_ADDR_reg<4> & !U2_ADDR_reg<5> & !U2_ADDR_reg<6> & !U2_ADDR_reg<7> & 
	!U2_ADDR_reg<1> & !U2_ADDR_reg<3> & AD<3>.PIN;	// (8 pt, 17 inp)
   NET2493.CLK  =  !Mclk;	// GCK	(0 pt, 0 inp)

NET2512.T := !N_PZ_1030 & !NET2512 & U1/U4/LatchEdge1r & 
	U1/U4/InEdge1r & !U1/U4/LastEdge1r
	# !N_PZ_1030 & !NET2512 & !U1/U4/LatchEdge1r & 
	!U1/U4/InEdge1r & U1/U4/LastEdge1r
	# !U2_ADDR_reg<2> & MSPReset & !WR & RD & 
	U2_ADDR_reg<0> & !U2_ADDR_reg<4> & !U2_ADDR_reg<5> & !U2_ADDR_reg<6> & 
	AD<6>.PIN & !U2_ADDR_reg<7> & !U2_ADDR_reg<1> & !U2_ADDR_reg<3> & 
	NET2512;	// (3 pt, 17 inp)
   NET2512.CLK  =  !Mclk;	// GCK	(0 pt, 0 inp)

!NET2528 := !MSPReset
	# !NET2528 & U4/DCORIFG__or0000_bdd0
	# !U2_ADDR_reg<2> & !WR & RD & U2_ADDR_reg<0> & 
	!U2_ADDR_reg<4> & !U2_ADDR_reg<5> & !U2_ADDR_reg<6> & !U2_ADDR_reg<7> & 
	!U2_ADDR_reg<1> & AD<1>.PIN & !U2_ADDR_reg<3>
	# !U2_ADDR_reg<2> & !WR & RD & U2_ADDR_reg<0> & 
	!U2_ADDR_reg<4> & !U2_ADDR_reg<5> & !U2_ADDR_reg<6> & !U2_ADDR_reg<7> & 
	!U2_ADDR_reg<1> & !U2_ADDR_reg<3> & !NET2528;	// (4 pt, 14 inp)
   NET2528.CLK  =  !Mclk;	// GCK	(0 pt, 0 inp)

!NET2575 := !MSPReset
	# !U5/RLS0fr & !U5/FLS0fr & !U5/RLS1fr & !NET2575 & 
	!U5/FLS1fr
	# !U2_ADDR_reg<2> & !WR & RD & U2_ADDR_reg<0> & 
	!U2_ADDR_reg<4> & AD<4>.PIN & !U2_ADDR_reg<5> & !U2_ADDR_reg<6> & 
	!U2_ADDR_reg<7> & !U2_ADDR_reg<1> & !U2_ADDR_reg<3>
	# !U2_ADDR_reg<2> & !WR & RD & U2_ADDR_reg<0> & 
	!U2_ADDR_reg<4> & !U2_ADDR_reg<5> & !U2_ADDR_reg<6> & !U2_ADDR_reg<7> & 
	!U2_ADDR_reg<1> & !U2_ADDR_reg<3> & !NET2575;	// (4 pt, 17 inp)
   NET2575.CLK  =  !Mclk;	// GCK	(0 pt, 0 inp)

NET3248.T := !N_PZ_1202 & N_PZ_1313 & !NET3248
	# !N_PZ_1202 & DIR0 & !FLS0 & U5/FLS0r & !NET3248
	# !U5/RLS0fr & !N_PZ_1202 & !N_PZ_1313 & !DIR0 & 
	!U5/FLS0fr & NET3248 & Brake0
	# !U5/RLS0fr & !N_PZ_1202 & !N_PZ_1313 & FLS0 & 
	!U5/FLS0fr & NET3248 & Brake0
	# !U5/RLS0fr & !N_PZ_1202 & !N_PZ_1313 & !U5/FLS0fr & 
	!U5/FLS0r & NET3248 & Brake0;	// (5 pt, 9 inp)
   NET3248.CLK  =  !Mclk;	// GCK	(0 pt, 0 inp)

NET3253.T := !N_PZ_1202 & N_PZ_1314 & !NET3253
	# !N_PZ_1202 & DIR1 & !FLS1 & U5/FLS1r & !NET3253
	# !N_PZ_1202 & !U5/RLS1fr & !N_PZ_1314 & !DIR1 & 
	!U5/FLS1fr & NET3253 & Brake1
	# !N_PZ_1202 & !U5/RLS1fr & !N_PZ_1314 & !U5/FLS1fr & 
	FLS1 & NET3253 & Brake1
	# !N_PZ_1202 & !U5/RLS1fr & !N_PZ_1314 & !U5/FLS1fr & 
	!U5/FLS1r & NET3253 & Brake1;	// (5 pt, 9 inp)
   NET3253.CLK  =  !Mclk;	// GCK	(0 pt, 0 inp)

N_PZ_1001 = MSPReset & AS
	# MSPReset & !U2_ASedge;	// (2 pt, 3 inp)

N_PZ_1019 = MSPReset & U1/U4/latchitH1
	# MSPReset & U1/U4/latchitL1;	// (2 pt, 3 inp)

N_PZ_1021 = MSPReset & U1/U4/latchitH0
	# MSPReset & U1/U4/latchitL0;	// (2 pt, 3 inp)

N_PZ_1029 = !U2_ADDR_reg<2> & U2_ADDR_reg<0> & U2_Enable_AD & 
	!N_PZ_1203;	// (1 pt, 4 inp)

N_PZ_1030 = !MSPReset
	# !U2_ADDR_reg<2> & !WR & RD & U2_ADDR_reg<0> & 
	!U2_ADDR_reg<4> & !U2_ADDR_reg<5> & !U2_ADDR_reg<6> & !U2_ADDR_reg<7> & 
	!U2_ADDR_reg<3>;	// (2 pt, 10 inp)

N_PZ_1142 = SCLreset
	# !SCLinc & U11_Incdetect & U11_ResetDetect
	# !U11_Incdetect & U11_SCLdetect & 
	outDATA<7>\$WA4.UIM;	// (3 pt, 6 inp)

N_PZ_1194 = MSPReset & U1/U6/CurrState_Sreg0_FSM_FFd1
	# MSPReset & !U1/U6/CurrState_Sreg0_FSM_FFd4 & 
	!U1/U6/CurrState_Sreg0_FSM_FFd3 & U1/U6/CurrState_Sreg0_FSM_FFd2;	// (2 pt, 5 inp)

N_PZ_1195 = U2_ADDR_reg<2> & !U2_ADDR_reg<0> & !U2_ADDR_reg<3> & 
	U2_Enable_AD
	# U2_ADDR_reg<2> & !U2_ADDR_reg<1> & !U2_ADDR_reg<3> & 
	U2_Enable_AD;	// (2 pt, 5 inp)

N_PZ_1202 = !MSPReset
	# !U2_ADDR_reg<2> & WR & !RD & !U2_ADDR_reg<0> & 
	!U2_ADDR_reg<4> & !U2_ADDR_reg<5> & !U2_ADDR_reg<6> & !U2_ADDR_reg<7> & 
	U2_ADDR_reg<1> & !U2_ADDR_reg<3>;	// (2 pt, 11 inp)

N_PZ_1203 = !U2_ADDR_reg<2> & U2_ADDR_reg<3> & U2_Enable_AD
	# !U2_ADDR_reg<2> & U2_ADDR_reg<0> & !U2_ADDR_reg<1> & 
	U2_Enable_AD;	// (2 pt, 5 inp)

N_PZ_1209 = MSPReset & U1/U1/CurrState_Sreg0_FSM_FFd1
	# MSPReset & !U1/U1/CurrState_Sreg0_FSM_FFd4 & 
	!U1/U1/CurrState_Sreg0_FSM_FFd3 & U1/U1/CurrState_Sreg0_FSM_FFd2;	// (2 pt, 5 inp)

N_PZ_1216 = !U2_ADDR_reg<0> & U2_ADDR_reg<3> & N_PZ_1203
	# !U2_ADDR_reg<1> & U2_ADDR_reg<3> & N_PZ_1203;	// (2 pt, 4 inp)

N_PZ_1313 = !RLS0 & !DIR0 & U5/RLS0r;	// (1 pt, 3 inp)

N_PZ_1314 = !RLS1 & !DIR1 & U5/RLS1r;	// (1 pt, 3 inp)

PAH0 = RLS0 & !DIR0 & !NET3248 & !Brake0 & MTRpwr & 
	PWM1;	// (1 pt, 6 inp)

PAH1 = RLS1 & !DIR1 & !NET3253 & !Brake1 & MTRpwr & 
	PWM2;	// (1 pt, 6 inp)

PAL0 = DIR0 & !NET3248 & !Brake0 & MTRpwr & !PWM1
	# !DIR0 & !NET3248 & !Brake0 & MTRpwr & PWM1;	// (2 pt, 5 inp)

PAL1 = DIR1 & !NET3253 & !Brake1 & MTRpwr & !PWM2
	# !DIR1 & !NET3253 & !Brake1 & MTRpwr & PWM2;	// (2 pt, 5 inp)

PBH0 = DIR0 & FLS0 & !NET3248 & !Brake0 & MTRpwr & 
	PWM1;	// (1 pt, 6 inp)

PBH1 = DIR1 & FLS1 & !NET3253 & !Brake1 & MTRpwr & 
	PWM2;	// (1 pt, 6 inp)

PBL0 = DIR0 & !NET3248 & !Brake0 & MTRpwr & PWM1
	# !DIR0 & !NET3248 & !Brake0 & MTRpwr & !PWM1;	// (2 pt, 5 inp)

PBL1 = DIR1 & !NET3253 & !Brake1 & MTRpwr & PWM2
	# !DIR1 & !NET3253 & !Brake1 & MTRpwr & !PWM2;	// (2 pt, 5 inp)

PresEn.T := !MSPReset & !PresEn
	# U2_ADDR_reg<2> & !WR & RD & !U2_ADDR_reg<0> & 
	!AD<0>.PIN & !U2_ADDR_reg<4> & !U2_ADDR_reg<5> & !U2_ADDR_reg<6> & 
	!U2_ADDR_reg<7> & !U2_ADDR_reg<1> & U2_ADDR_reg<3> & !PresEn
	# U2_ADDR_reg<2> & MSPReset & !WR & RD & 
	!U2_ADDR_reg<0> & AD<0>.PIN & !U2_ADDR_reg<4> & !U2_ADDR_reg<5> & 
	!U2_ADDR_reg<6> & !U2_ADDR_reg<7> & !U2_ADDR_reg<1> & U2_ADDR_reg<3> & 
	PresEn;	// (3 pt, 13 inp)
   PresEn.CLK  =  !Mclk;	// GCK	(0 pt, 0 inp)
   !PresEn.AP = !MReset;	// LPST	(1 pt, 2 inp)

PresSlct.T := !MSPReset & PresSlct
	# U2_ADDR_reg<2> & !WR & RD & !U2_ADDR_reg<0> & 
	!U2_ADDR_reg<4> & !U2_ADDR_reg<5> & !U2_ADDR_reg<6> & !U2_ADDR_reg<7> & 
	!U2_ADDR_reg<1> & !AD<1>.PIN & U2_ADDR_reg<3> & PresSlct
	# U2_ADDR_reg<2> & MSPReset & !WR & RD & 
	!U2_ADDR_reg<0> & !U2_ADDR_reg<4> & !U2_ADDR_reg<5> & !U2_ADDR_reg<6> & 
	!U2_ADDR_reg<7> & !U2_ADDR_reg<1> & AD<1>.PIN & U2_ADDR_reg<3> & 
	!PresSlct;	// (3 pt, 13 inp)
   PresSlct.CLK  =  !Mclk;	// GCK	(0 pt, 0 inp)
    PresSlct.AR = MReset;	// URST	(1 pt, 1 inp)

TP12 = !U11_U3_counterr<0> & !U11_U3_counterr<1> & 
	!U11_U3_counterr<2> & !U11_U3_counterr<3> & !U11_U3_counterr<4> & 
	!U11_U3_counterr<5>;	// (1 pt, 6 inp)

TP21.T := !MSPReset & TP21
	# !U2_ADDR_reg<2> & !WR & RD & !U2_ADDR_reg<0> & 
	!U2_ADDR_reg<4> & !U2_ADDR_reg<5> & !AD<5>.PIN & !U2_ADDR_reg<6> & 
	!U2_ADDR_reg<7> & !U2_ADDR_reg<1> & !U2_ADDR_reg<3> & TP21
	# !U2_ADDR_reg<2> & MSPReset & !WR & RD & 
	!U2_ADDR_reg<0> & !U2_ADDR_reg<4> & !U2_ADDR_reg<5> & AD<5>.PIN & 
	!U2_ADDR_reg<6> & !U2_ADDR_reg<7> & !U2_ADDR_reg<1> & !U2_ADDR_reg<3> & 
	!TP21;	// (3 pt, 13 inp)
   TP21.CLK  =  !Mclk;	// GCK	(0 pt, 0 inp)

!TP26 := N_PZ_1030 & !TP26
	# !TP26 & U1/U4/LatchEdge0r & !U1/U4/InEdge0r
	# !TP26 & !U1/U4/LatchEdge0r & !U1/U4/LastEdge0r
	# !TP26 & U1/U4/InEdge0r & U1/U4/LastEdge0r
	# !U2_ADDR_reg<2> & MSPReset & !WR & RD & 
	U2_ADDR_reg<0> & !U2_ADDR_reg<4> & !U2_ADDR_reg<5> & AD<5>.PIN & 
	!U2_ADDR_reg<6> & !U2_ADDR_reg<7> & !U2_ADDR_reg<1> & !U2_ADDR_reg<3>;	// (5 pt, 17 inp)
   TP26.CLK  =  !Mclk;	// GCK	(0 pt, 0 inp)

TmpEn.T := !MSPReset & !TmpEn
	# U2_ADDR_reg<2> & !AD<2>.PIN & !WR & RD & 
	!U2_ADDR_reg<0> & !U2_ADDR_reg<4> & !U2_ADDR_reg<5> & !U2_ADDR_reg<6> & 
	!U2_ADDR_reg<7> & !U2_ADDR_reg<1> & U2_ADDR_reg<3> & !TmpEn
	# U2_ADDR_reg<2> & MSPReset & AD<2>.PIN & !WR & 
	RD & !U2_ADDR_reg<0> & !U2_ADDR_reg<4> & !U2_ADDR_reg<5> & 
	!U2_ADDR_reg<6> & !U2_ADDR_reg<7> & !U2_ADDR_reg<1> & U2_ADDR_reg<3> & 
	TmpEn;	// (3 pt, 13 inp)
   TmpEn.CLK  =  !Mclk;	// GCK	(0 pt, 0 inp)
   !TmpEn.AP = !MReset;	// LPST	(1 pt, 2 inp)

TmpSlct.T := !MSPReset & TmpSlct
	# U2_ADDR_reg<2> & !WR & RD & !U2_ADDR_reg<0> & 
	!U2_ADDR_reg<4> & !U2_ADDR_reg<5> & !U2_ADDR_reg<6> & !U2_ADDR_reg<7> & 
	!U2_ADDR_reg<1> & U2_ADDR_reg<3> & !AD<3>.PIN & TmpSlct
	# U2_ADDR_reg<2> & MSPReset & !WR & RD & 
	!U2_ADDR_reg<0> & !U2_ADDR_reg<4> & !U2_ADDR_reg<5> & !U2_ADDR_reg<6> & 
	!U2_ADDR_reg<7> & !U2_ADDR_reg<1> & U2_ADDR_reg<3> & AD<3>.PIN & 
	!TmpSlct;	// (3 pt, 13 inp)
   TmpSlct.CLK  =  !Mclk;	// GCK	(0 pt, 0 inp)
    TmpSlct.AR = MReset;	// URST	(1 pt, 1 inp)

U1/Channel0<0> := !U1/Channel0<0> & N_PZ_1209
	# MSPReset & U1/Channel0<0> & !N_PZ_1209;	// (2 pt, 3 inp)
   U1/Channel0<0>.CLK  =  Mclk;	// GCK	(0 pt, 0 inp)

U1/Channel0<1>.T := !MSPReset & U1/Channel0<1>
	# U1/Channel0<0> & N_PZ_1209 & 
	U1/U2/location_or0001
	# !U1/Channel0<0> & N_PZ_1209 & 
	!U1/U2/location_or0001;	// (3 pt, 5 inp)
   U1/Channel0<1>.CLK  =  Mclk;	// GCK	(0 pt, 0 inp)

U1/Channel0<2>.T := !MSPReset & U1/Channel0<2>
	# U1/Channel0<0> & N_PZ_1209 & U1/Channel0<1> & 
	U1/U2/location_or0001
	# !U1/Channel0<0> & N_PZ_1209 & !U1/Channel0<1> & 
	!U1/U2/location_or0001;	// (3 pt, 6 inp)
   U1/Channel0<2>.CLK  =  Mclk;	// GCK	(0 pt, 0 inp)

U1/Channel0<3>.T := !MSPReset & U1/Channel0<3>
	# U1/Channel0<0> & N_PZ_1209 & U1/Channel0<2> & 
	U1/Channel0<1> & U1/U2/location_or0001
	# !U1/Channel0<0> & N_PZ_1209 & !U1/Channel0<2> & 
	!U1/Channel0<1> & !U1/U2/location_or0001;	// (3 pt, 7 inp)
   U1/Channel0<3>.CLK  =  Mclk;	// GCK	(0 pt, 0 inp)

U1/Channel0<4>.T := !MSPReset & U1/Channel0<4>
	# U1/Channel0<0> & N_PZ_1209 & U1/Channel0<2> & 
	U1/Channel0<1> & U1/U2/location_or0001 & U1/Channel0<3>
	# !U1/Channel0<0> & N_PZ_1209 & !U1/Channel0<2> & 
	!U1/Channel0<1> & !U1/U2/location_or0001 & !U1/Channel0<3>;	// (3 pt, 8 inp)
   U1/Channel0<4>.CLK  =  Mclk;	// GCK	(0 pt, 0 inp)

U1/Channel0<5>.T := !MSPReset & U1/Channel0<5>
	# U1/Channel0<0> & N_PZ_1209 & U1/Channel0<2> & 
	U1/Channel0<1> & U1/U2/location_or0001 & U1/Channel0<4> & 
	U1/Channel0<3>
	# !U1/Channel0<0> & N_PZ_1209 & !U1/Channel0<2> & 
	!U1/Channel0<1> & !U1/U2/location_or0001 & !U1/Channel0<4> & 
	!U1/Channel0<3>;	// (3 pt, 9 inp)
   U1/Channel0<5>.CLK  =  Mclk;	// GCK	(0 pt, 0 inp)

U1/Channel0<6>.T := !MSPReset & U1/Channel0<6>
	# U1/Channel0<0> & N_PZ_1209 & U1/Channel0<2> & 
	U1/Channel0<1> & U1/U2/location_or0001 & U1/Channel0<4> & 
	U1/Channel0<3> & U1/Channel0<5>
	# !U1/Channel0<0> & N_PZ_1209 & !U1/Channel0<2> & 
	!U1/Channel0<1> & !U1/U2/location_or0001 & !U1/Channel0<4> & 
	!U1/Channel0<3> & !U1/Channel0<5>;	// (3 pt, 10 inp)
   U1/Channel0<6>.CLK  =  Mclk;	// GCK	(0 pt, 0 inp)

U1/Channel0<7>.T := !MSPReset & U1/Channel0<7>
	# U1/Channel0<0> & N_PZ_1209 & U1/Channel0<2> & 
	U1/Channel0<1> & U1/U2/location_or0001 & U1/Channel0<4> & 
	U1/Channel0<3> & U1/Channel0<5> & U1/Channel0<6>
	# !U1/Channel0<0> & N_PZ_1209 & !U1/Channel0<2> & 
	!U1/Channel0<1> & !U1/U2/location_or0001 & !U1/Channel0<4> & 
	!U1/Channel0<3> & !U1/Channel0<5> & !U1/Channel0<6>;	// (3 pt, 11 inp)
   U1/Channel0<7>.CLK  =  Mclk;	// GCK	(0 pt, 0 inp)

U1/Channel0<8>.T := !MSPReset & U1/Channel0<8>
	# U1/Channel0<0> & N_PZ_1209 & U1/Channel0<2> & 
	U1/Channel0<1> & U1/U2/location_or0001 & U1/Channel0<4> & 
	U1/Channel0<3> & U1/Channel0<5> & U1/Channel0<7> & U1/Channel0<6>
	# !U1/Channel0<0> & N_PZ_1209 & !U1/Channel0<2> & 
	!U1/Channel0<1> & !U1/U2/location_or0001 & !U1/Channel0<4> & 
	!U1/Channel0<3> & !U1/Channel0<5> & !U1/Channel0<7> & !U1/Channel0<6>;	// (3 pt, 12 inp)
   U1/Channel0<8>.CLK  =  Mclk;	// GCK	(0 pt, 0 inp)

U1/Channel0<9>.T := !MSPReset & U1/Channel0<9>
	# U1/Channel0<0> & N_PZ_1209 & U1/Channel0<8> & 
	U1/Channel0<2> & U1/Channel0<1> & U1/U2/location_or0001 & 
	U1/Channel0<4> & U1/Channel0<3> & U1/Channel0<5> & U1/Channel0<7> & 
	U1/Channel0<6>
	# !U1/Channel0<0> & N_PZ_1209 & !U1/Channel0<8> & 
	!U1/Channel0<2> & !U1/Channel0<1> & !U1/U2/location_or0001 & 
	!U1/Channel0<4> & !U1/Channel0<3> & !U1/Channel0<5> & !U1/Channel0<7> & 
	!U1/Channel0<6>;	// (3 pt, 13 inp)
   U1/Channel0<9>.CLK  =  Mclk;	// GCK	(0 pt, 0 inp)

U1/Channel0<10>.T := !MSPReset & U1/Channel0<10>
	# U1/Channel0<0> & N_PZ_1209 & U1/Channel0<8> & 
	U1/Channel0<2> & U1/Channel0<1> & U1/U2/location_or0001 & 
	U1/Channel0<4> & U1/Channel0<3> & U1/Channel0<5> & U1/Channel0<7> & 
	U1/Channel0<6> & U1/Channel0<9>
	# !U1/Channel0<0> & N_PZ_1209 & !U1/Channel0<8> & 
	!U1/Channel0<2> & !U1/Channel0<1> & !U1/U2/location_or0001 & 
	!U1/Channel0<4> & !U1/Channel0<3> & !U1/Channel0<5> & !U1/Channel0<7> & 
	!U1/Channel0<6> & !U1/Channel0<9>;	// (3 pt, 14 inp)
   U1/Channel0<10>.CLK  =  Mclk;	// GCK	(0 pt, 0 inp)

U1/Channel0<11>.T := !MSPReset & U1/Channel0<11>
	# U1/Channel0<0> & N_PZ_1209 & U1/Channel0<8> & 
	U1/Channel0<2> & U1/Channel0<1> & U1/U2/location_or0001 & 
	U1/Channel0<4> & U1/Channel0<3> & U1/Channel0<5> & U1/Channel0<7> & 
	U1/Channel0<6> & U1/Channel0<9> & U1/Channel0<10>
	# !U1/Channel0<0> & N_PZ_1209 & !U1/Channel0<8> & 
	!U1/Channel0<2> & !U1/Channel0<1> & !U1/U2/location_or0001 & 
	!U1/Channel0<4> & !U1/Channel0<3> & !U1/Channel0<5> & !U1/Channel0<7> & 
	!U1/Channel0<6> & !U1/Channel0<9> & !U1/Channel0<10>;	// (3 pt, 15 inp)
   U1/Channel0<11>.CLK  =  Mclk;	// GCK	(0 pt, 0 inp)

U1/Channel0<12>.T := !MSPReset & U1/Channel0<12>
	# U1/Channel0<0> & N_PZ_1209 & U1/Channel0<8> & 
	U1/Channel0<2> & U1/Channel0<1> & U1/U2/location_or0001 & 
	U1/Channel0<4> & U1/Channel0<3> & U1/Channel0<5> & U1/Channel0<7> & 
	U1/Channel0<6> & U1/Channel0<9> & U1/Channel0<10> & 
	U1/Channel0<11>
	# !U1/Channel0<0> & N_PZ_1209 & !U1/Channel0<8> & 
	!U1/Channel0<2> & !U1/Channel0<1> & !U1/U2/location_or0001 & 
	!U1/Channel0<4> & !U1/Channel0<3> & !U1/Channel0<5> & !U1/Channel0<7> & 
	!U1/Channel0<6> & !U1/Channel0<9> & !U1/Channel0<10> & 
	!U1/Channel0<11>;	// (3 pt, 16 inp)
   U1/Channel0<12>.CLK  =  Mclk;	// GCK	(0 pt, 0 inp)

U1/Channel0<13>.T := !MSPReset & U1/Channel0<13>
	# U1/Channel0<0> & N_PZ_1209 & U1/Channel0<8> & 
	U1/Channel0<2> & U1/Channel0<1> & U1/U2/location_or0001 & 
	U1/Channel0<4> & U1/Channel0<3> & U1/Channel0<5> & U1/Channel0<7> & 
	U1/Channel0<6> & U1/Channel0<9> & U1/Channel0<10> & 
	U1/Channel0<11> & U1/Channel0<12>
	# !U1/Channel0<0> & N_PZ_1209 & !U1/Channel0<8> & 
	!U1/Channel0<2> & !U1/Channel0<1> & !U1/U2/location_or0001 & 
	!U1/Channel0<4> & !U1/Channel0<3> & !U1/Channel0<5> & !U1/Channel0<7> & 
	!U1/Channel0<6> & !U1/Channel0<9> & !U1/Channel0<10> & 
	!U1/Channel0<11> & !U1/Channel0<12>;	// (3 pt, 17 inp)
   U1/Channel0<13>.CLK  =  Mclk;	// GCK	(0 pt, 0 inp)

U1/Channel0<14>.T := !MSPReset & U1/Channel0<14>
	# U1/Channel0<0> & N_PZ_1209 & U1/Channel0<8> & 
	U1/Channel0<2> & U1/Channel0<1> & U1/U2/location_or0001 & 
	U1/Channel0<4> & U1/Channel0<3> & U1/Channel0<5> & U1/Channel0<7> & 
	U1/Channel0<6> & U1/Channel0<9> & U1/Channel0<10> & 
	U1/Channel0<11> & U1/Channel0<12> & U1/Channel0<13>
	# !U1/Channel0<0> & N_PZ_1209 & !U1/Channel0<8> & 
	!U1/Channel0<2> & !U1/Channel0<1> & !U1/U2/location_or0001 & 
	!U1/Channel0<4> & !U1/Channel0<3> & !U1/Channel0<5> & !U1/Channel0<7> & 
	!U1/Channel0<6> & !U1/Channel0<9> & !U1/Channel0<10> & 
	!U1/Channel0<11> & !U1/Channel0<12> & !U1/Channel0<13>;	// (3 pt, 18 inp)
   U1/Channel0<14>.CLK  =  Mclk;	// GCK	(0 pt, 0 inp)

U1/Channel0<15>.T := !MSPReset & U1/Channel0<15>
	# U1/Channel0<0> & N_PZ_1209 & U1/Channel0<8> & 
	U1/Channel0<2> & U1/Channel0<1> & U1/U2/location_or0001 & 
	U1/Channel0<4> & U1/Channel0<3> & U1/Channel0<5> & U1/Channel0<7> & 
	U1/Channel0<6> & U1/Channel0<9> & U1/Channel0<10> & 
	U1/Channel0<11> & U1/Channel0<12> & U1/Channel0<13> & 
	U1/Channel0<14>
	# !U1/Channel0<0> & N_PZ_1209 & !U1/Channel0<8> & 
	!U1/Channel0<2> & !U1/Channel0<1> & !U1/U2/location_or0001 & 
	!U1/Channel0<4> & !U1/Channel0<3> & !U1/Channel0<5> & !U1/Channel0<7> & 
	!U1/Channel0<6> & !U1/Channel0<9> & !U1/Channel0<10> & 
	!U1/Channel0<11> & !U1/Channel0<12> & !U1/Channel0<13> & 
	!U1/Channel0<14>;	// (3 pt, 19 inp)
   U1/Channel0<15>.CLK  =  Mclk;	// GCK	(0 pt, 0 inp)

U1/Channel1<0> := !U1/Channel1<0> & N_PZ_1194
	# MSPReset & U1/Channel1<0> & !N_PZ_1194;	// (2 pt, 3 inp)
   U1/Channel1<0>.CLK  =  Mclk;	// GCK	(0 pt, 0 inp)

U1/Channel1<1>.T := !MSPReset & U1/Channel1<1>
	# U1/Channel1<0> & N_PZ_1194 & 
	U1/U5/location_or0001
	# !U1/Channel1<0> & N_PZ_1194 & 
	!U1/U5/location_or0001;	// (3 pt, 5 inp)
   U1/Channel1<1>.CLK  =  Mclk;	// GCK	(0 pt, 0 inp)

U1/Channel1<2>.T := !MSPReset & U1/Channel1<2>
	# U1/Channel1<0> & N_PZ_1194 & U1/Channel1<1> & 
	U1/U5/location_or0001
	# !U1/Channel1<0> & N_PZ_1194 & !U1/Channel1<1> & 
	!U1/U5/location_or0001;	// (3 pt, 6 inp)
   U1/Channel1<2>.CLK  =  Mclk;	// GCK	(0 pt, 0 inp)

U1/Channel1<3>.T := !MSPReset & U1/Channel1<3>
	# U1/Channel1<0> & N_PZ_1194 & U1/Channel1<2> & 
	U1/Channel1<1> & U1/U5/location_or0001
	# !U1/Channel1<0> & N_PZ_1194 & !U1/Channel1<2> & 
	!U1/Channel1<1> & !U1/U5/location_or0001;	// (3 pt, 7 inp)
   U1/Channel1<3>.CLK  =  Mclk;	// GCK	(0 pt, 0 inp)

U1/Channel1<4>.T := !MSPReset & U1/Channel1<4>
	# U1/Channel1<0> & N_PZ_1194 & U1/Channel1<2> & 
	U1/Channel1<1> & U1/U5/location_or0001 & U1/Channel1<3>
	# !U1/Channel1<0> & N_PZ_1194 & !U1/Channel1<2> & 
	!U1/Channel1<1> & !U1/U5/location_or0001 & !U1/Channel1<3>;	// (3 pt, 8 inp)
   U1/Channel1<4>.CLK  =  Mclk;	// GCK	(0 pt, 0 inp)

U1/Channel1<5>.T := !MSPReset & U1/Channel1<5>
	# U1/Channel1<0> & N_PZ_1194 & U1/Channel1<2> & 
	U1/Channel1<1> & U1/U5/location_or0001 & U1/Channel1<4> & 
	U1/Channel1<3>
	# !U1/Channel1<0> & N_PZ_1194 & !U1/Channel1<2> & 
	!U1/Channel1<1> & !U1/U5/location_or0001 & !U1/Channel1<4> & 
	!U1/Channel1<3>;	// (3 pt, 9 inp)
   U1/Channel1<5>.CLK  =  Mclk;	// GCK	(0 pt, 0 inp)

U1/Channel1<6>.T := !MSPReset & U1/Channel1<6>
	# U1/Channel1<0> & N_PZ_1194 & U1/Channel1<2> & 
	U1/Channel1<1> & U1/U5/location_or0001 & U1/Channel1<4> & 
	U1/Channel1<3> & U1/Channel1<5>
	# !U1/Channel1<0> & N_PZ_1194 & !U1/Channel1<2> & 
	!U1/Channel1<1> & !U1/U5/location_or0001 & !U1/Channel1<4> & 
	!U1/Channel1<3> & !U1/Channel1<5>;	// (3 pt, 10 inp)
   U1/Channel1<6>.CLK  =  Mclk;	// GCK	(0 pt, 0 inp)

U1/Channel1<7>.T := !MSPReset & U1/Channel1<7>
	# U1/Channel1<0> & N_PZ_1194 & U1/Channel1<2> & 
	U1/Channel1<1> & U1/U5/location_or0001 & U1/Channel1<4> & 
	U1/Channel1<3> & U1/Channel1<5> & U1/Channel1<6>
	# !U1/Channel1<0> & N_PZ_1194 & !U1/Channel1<2> & 
	!U1/Channel1<1> & !U1/U5/location_or0001 & !U1/Channel1<4> & 
	!U1/Channel1<3> & !U1/Channel1<5> & !U1/Channel1<6>;	// (3 pt, 11 inp)
   U1/Channel1<7>.CLK  =  Mclk;	// GCK	(0 pt, 0 inp)

U1/Channel1<8>.T := !MSPReset & U1/Channel1<8>
	# U1/Channel1<0> & N_PZ_1194 & U1/Channel1<2> & 
	U1/Channel1<1> & U1/U5/location_or0001 & U1/Channel1<4> & 
	U1/Channel1<3> & U1/Channel1<5> & U1/Channel1<7> & U1/Channel1<6>
	# !U1/Channel1<0> & N_PZ_1194 & !U1/Channel1<2> & 
	!U1/Channel1<1> & !U1/U5/location_or0001 & !U1/Channel1<4> & 
	!U1/Channel1<3> & !U1/Channel1<5> & !U1/Channel1<7> & !U1/Channel1<6>;	// (3 pt, 12 inp)
   U1/Channel1<8>.CLK  =  Mclk;	// GCK	(0 pt, 0 inp)

U1/Channel1<9>.T := !MSPReset & U1/Channel1<9>
	# U1/Channel1<0> & N_PZ_1194 & U1/Channel1<8> & 
	U1/Channel1<2> & U1/Channel1<1> & U1/U5/location_or0001 & 
	U1/Channel1<4> & U1/Channel1<3> & U1/Channel1<5> & U1/Channel1<7> & 
	U1/Channel1<6>
	# !U1/Channel1<0> & N_PZ_1194 & !U1/Channel1<8> & 
	!U1/Channel1<2> & !U1/Channel1<1> & !U1/U5/location_or0001 & 
	!U1/Channel1<4> & !U1/Channel1<3> & !U1/Channel1<5> & !U1/Channel1<7> & 
	!U1/Channel1<6>;	// (3 pt, 13 inp)
   U1/Channel1<9>.CLK  =  Mclk;	// GCK	(0 pt, 0 inp)

U1/Channel1<10>.T := !MSPReset & U1/Channel1<10>
	# U1/Channel1<0> & N_PZ_1194 & U1/Channel1<8> & 
	U1/Channel1<2> & U1/Channel1<1> & U1/U5/location_or0001 & 
	U1/Channel1<4> & U1/Channel1<3> & U1/Channel1<5> & U1/Channel1<7> & 
	U1/Channel1<6> & U1/Channel1<9>
	# !U1/Channel1<0> & N_PZ_1194 & !U1/Channel1<8> & 
	!U1/Channel1<2> & !U1/Channel1<1> & !U1/U5/location_or0001 & 
	!U1/Channel1<4> & !U1/Channel1<3> & !U1/Channel1<5> & !U1/Channel1<7> & 
	!U1/Channel1<6> & !U1/Channel1<9>;	// (3 pt, 14 inp)
   U1/Channel1<10>.CLK  =  Mclk;	// GCK	(0 pt, 0 inp)

U1/Channel1<11>.T := !MSPReset & U1/Channel1<11>
	# U1/Channel1<0> & N_PZ_1194 & U1/Channel1<8> & 
	U1/Channel1<2> & U1/Channel1<1> & U1/U5/location_or0001 & 
	U1/Channel1<4> & U1/Channel1<3> & U1/Channel1<5> & U1/Channel1<7> & 
	U1/Channel1<6> & U1/Channel1<9> & U1/Channel1<10>
	# !U1/Channel1<0> & N_PZ_1194 & !U1/Channel1<8> & 
	!U1/Channel1<2> & !U1/Channel1<1> & !U1/U5/location_or0001 & 
	!U1/Channel1<4> & !U1/Channel1<3> & !U1/Channel1<5> & !U1/Channel1<7> & 
	!U1/Channel1<6> & !U1/Channel1<9> & !U1/Channel1<10>;	// (3 pt, 15 inp)
   U1/Channel1<11>.CLK  =  Mclk;	// GCK	(0 pt, 0 inp)

U1/Channel1<12>.T := !MSPReset & U1/Channel1<12>
	# U1/Channel1<0> & N_PZ_1194 & U1/Channel1<8> & 
	U1/Channel1<2> & U1/Channel1<1> & U1/U5/location_or0001 & 
	U1/Channel1<4> & U1/Channel1<3> & U1/Channel1<5> & U1/Channel1<7> & 
	U1/Channel1<6> & U1/Channel1<9> & U1/Channel1<10> & 
	U1/Channel1<11>
	# !U1/Channel1<0> & N_PZ_1194 & !U1/Channel1<8> & 
	!U1/Channel1<2> & !U1/Channel1<1> & !U1/U5/location_or0001 & 
	!U1/Channel1<4> & !U1/Channel1<3> & !U1/Channel1<5> & !U1/Channel1<7> & 
	!U1/Channel1<6> & !U1/Channel1<9> & !U1/Channel1<10> & 
	!U1/Channel1<11>;	// (3 pt, 16 inp)
   U1/Channel1<12>.CLK  =  Mclk;	// GCK	(0 pt, 0 inp)

U1/Channel1<13>.T := !MSPReset & U1/Channel1<13>
	# U1/Channel1<0> & N_PZ_1194 & U1/Channel1<8> & 
	U1/Channel1<2> & U1/Channel1<1> & U1/U5/location_or0001 & 
	U1/Channel1<4> & U1/Channel1<3> & U1/Channel1<5> & U1/Channel1<7> & 
	U1/Channel1<6> & U1/Channel1<9> & U1/Channel1<10> & 
	U1/Channel1<11> & U1/Channel1<12>
	# !U1/Channel1<0> & N_PZ_1194 & !U1/Channel1<8> & 
	!U1/Channel1<2> & !U1/Channel1<1> & !U1/U5/location_or0001 & 
	!U1/Channel1<4> & !U1/Channel1<3> & !U1/Channel1<5> & !U1/Channel1<7> & 
	!U1/Channel1<6> & !U1/Channel1<9> & !U1/Channel1<10> & 
	!U1/Channel1<11> & !U1/Channel1<12>;	// (3 pt, 17 inp)
   U1/Channel1<13>.CLK  =  Mclk;	// GCK	(0 pt, 0 inp)

U1/Channel1<14>.T := !MSPReset & U1/Channel1<14>
	# U1/Channel1<0> & N_PZ_1194 & U1/Channel1<8> & 
	U1/Channel1<2> & U1/Channel1<1> & U1/U5/location_or0001 & 
	U1/Channel1<4> & U1/Channel1<3> & U1/Channel1<5> & U1/Channel1<7> & 
	U1/Channel1<6> & U1/Channel1<9> & U1/Channel1<10> & 
	U1/Channel1<11> & U1/Channel1<12> & U1/Channel1<13>
	# !U1/Channel1<0> & N_PZ_1194 & !U1/Channel1<8> & 
	!U1/Channel1<2> & !U1/Channel1<1> & !U1/U5/location_or0001 & 
	!U1/Channel1<4> & !U1/Channel1<3> & !U1/Channel1<5> & !U1/Channel1<7> & 
	!U1/Channel1<6> & !U1/Channel1<9> & !U1/Channel1<10> & 
	!U1/Channel1<11> & !U1/Channel1<12> & !U1/Channel1<13>;	// (3 pt, 18 inp)
   U1/Channel1<14>.CLK  =  Mclk;	// GCK	(0 pt, 0 inp)

U1/Channel1<15>.T := !MSPReset & U1/Channel1<15>
	# U1/Channel1<0> & N_PZ_1194 & U1/Channel1<8> & 
	U1/Channel1<2> & U1/Channel1<1> & U1/U5/location_or0001 & 
	U1/Channel1<4> & U1/Channel1<3> & U1/Channel1<5> & U1/Channel1<7> & 
	U1/Channel1<6> & U1/Channel1<9> & U1/Channel1<10> & 
	U1/Channel1<11> & U1/Channel1<12> & U1/Channel1<13> & 
	U1/Channel1<14>
	# !U1/Channel1<0> & N_PZ_1194 & !U1/Channel1<8> & 
	!U1/Channel1<2> & !U1/Channel1<1> & !U1/U5/location_or0001 & 
	!U1/Channel1<4> & !U1/Channel1<3> & !U1/Channel1<5> & !U1/Channel1<7> & 
	!U1/Channel1<6> & !U1/Channel1<9> & !U1/Channel1<10> & 
	!U1/Channel1<11> & !U1/Channel1<12> & !U1/Channel1<13> & 
	!U1/Channel1<14>;	// (3 pt, 19 inp)
   U1/Channel1<15>.CLK  =  Mclk;	// GCK	(0 pt, 0 inp)

U1/NET3720.T := !MSPReset & U1/NET3720
	# !U2_ADDR_reg<2> & !WR & RD & U2_ADDR_reg<0> & 
	!U2_ADDR_reg<4> & !U2_ADDR_reg<5> & !U2_ADDR_reg<6> & !U2_ADDR_reg<7> & 
	!AD<7>.PIN & U2_ADDR_reg<1> & !U2_ADDR_reg<3> & U1/NET3720
	# !U2_ADDR_reg<2> & MSPReset & !WR & RD & 
	U2_ADDR_reg<0> & !U2_ADDR_reg<4> & !U2_ADDR_reg<5> & !U2_ADDR_reg<6> & 
	!U2_ADDR_reg<7> & AD<7>.PIN & U2_ADDR_reg<1> & !U2_ADDR_reg<3> & 
	!U1/NET3720;	// (3 pt, 13 inp)
   U1/NET3720.CLK  =  !Mclk;	// GCK	(0 pt, 0 inp)

U1/TP.T := !MSPReset & U1/TP
	# !U2_ADDR_reg<2> & !WR & RD & U2_ADDR_reg<0> & 
	!U2_ADDR_reg<4> & !U2_ADDR_reg<5> & !U2_ADDR_reg<6> & !U2_ADDR_reg<7> & 
	U2_ADDR_reg<1> & !U2_ADDR_reg<3> & !AD<3>.PIN & U1/TP
	# !U2_ADDR_reg<2> & MSPReset & !WR & RD & 
	U2_ADDR_reg<0> & !U2_ADDR_reg<4> & !U2_ADDR_reg<5> & !U2_ADDR_reg<6> & 
	!U2_ADDR_reg<7> & U2_ADDR_reg<1> & !U2_ADDR_reg<3> & AD<3>.PIN & 
	!U1/TP;	// (3 pt, 13 inp)
   U1/TP.CLK  =  !Mclk;	// GCK	(0 pt, 0 inp)

U1/U1/CurrState_Sreg0_FSM_FFd1 := MSPReset & U1/U1/CurrState_Sreg0_FSM_FFd4 & 
	!PhaseA_Encoder0 & !PhaseB_Encoder0 & U1/U1/CurrState_Sreg0_FSM_FFd3 & 
	U1/U1/CurrState_Sreg0_FSM_FFd2;	// (1 pt, 6 inp)
   U1/U1/CurrState_Sreg0_FSM_FFd1.CLK  =  Mclk;	// GCK	(0 pt, 0 inp)

U1/U1/CurrState_Sreg0_FSM_FFd2.T := !MSPReset & U1/U1/CurrState_Sreg0_FSM_FFd2
	# !U1/U1/CurrState_Sreg0_FSM_FFd4 & 
	!U1/U1/CurrState_Sreg0_FSM_FFd3 & U1/U1/CurrState_Sreg0_FSM_FFd2
	# PhaseA_Encoder0 & PhaseB_Encoder0 & 
	!U1/U1/CurrState_Sreg0_FSM_FFd3 & U1/U1/CurrState_Sreg0_FSM_FFd2
	# MSPReset & !U1/U1/CurrState_Sreg0_FSM_FFd4 & 
	!PhaseA_Encoder0 & PhaseB_Encoder0 & U1/U1/CurrState_Sreg0_FSM_FFd3
	# MSPReset & U1/U1/CurrState_Sreg0_FSM_FFd4 & 
	PhaseA_Encoder0 & PhaseB_Encoder0 & U1/U1/CurrState_Sreg0_FSM_FFd3 & 
	!U1/U1/CurrState_Sreg0_FSM_FFd2;	// (5 pt, 6 inp)
   U1/U1/CurrState_Sreg0_FSM_FFd2.CLK  =  Mclk;	// GCK	(0 pt, 0 inp)

U1/U1/CurrState_Sreg0_FSM_FFd3.T := !MSPReset & U1/U1/CurrState_Sreg0_FSM_FFd3
	# U1/U1/CurrState_Sreg0_FSM_FFd4 & !PhaseA_Encoder0 & 
	!PhaseB_Encoder0 & U1/U1/CurrState_Sreg0_FSM_FFd3
	# MSPReset & U1/U1/CurrState_Sreg0_FSM_FFd4 & 
	PhaseA_Encoder0 & PhaseB_Encoder0 & !U1/U1/CurrState_Sreg0_FSM_FFd3
	# MSPReset & !U1/U1/CurrState_Sreg0_FSM_FFd4 & 
	!PhaseA_Encoder0 & PhaseB_Encoder0 & !U1/U1/CurrState_Sreg0_FSM_FFd2
	# !U1/U1/CurrState_Sreg0_FSM_FFd4 & PhaseA_Encoder0 & 
	!PhaseB_Encoder0 & U1/U1/CurrState_Sreg0_FSM_FFd3 & 
	!U1/U1/CurrState_Sreg0_FSM_FFd2;	// (5 pt, 6 inp)
   U1/U1/CurrState_Sreg0_FSM_FFd3.CLK  =  Mclk;	// GCK	(0 pt, 0 inp)

!U1/U1/CurrState_Sreg0_FSM_FFd4 := !MSPReset
	# PhaseA_Encoder0 & PhaseB_Encoder0
	# !PhaseA_Encoder0 & !PhaseB_Encoder0
	# !U1/U1/CurrState_Sreg0_FSM_FFd4 & 
	!U1/U1/CurrState_Sreg0_FSM_FFd3 & U1/U1/CurrState_Sreg0_FSM_FFd2;	// (4 pt, 6 inp)
   U1/U1/CurrState_Sreg0_FSM_FFd4.CLK  =  Mclk;	// GCK	(0 pt, 0 inp)

U1/U2/location_or0001 = U1/TP
	$ U1/U1/CurrState_Sreg0_FSM_FFd4 & 
	!U1/U1/CurrState_Sreg0_FSM_FFd3
	# !U1/U1/CurrState_Sreg0_FSM_FFd4 & 
	U1/U1/CurrState_Sreg0_FSM_FFd3 & !U1/U1/CurrState_Sreg0_FSM_FFd2
	# !U1/U1/CurrState_Sreg0_FSM_FFd3 & 
	U1/U1/CurrState_Sreg0_FSM_FFd2 & !U1/U1/CurrState_Sreg0_FSM_FFd1;	// (4 pt, 5 inp)

U1/U3/holdingreg0<0> := N_PZ_1001 & U1/U3/holdingreg0<0>
	# MSPReset & !AS & U2_ASedge & U1/Channel0<0>;	// (2 pt, 6 inp)
   U1/U3/holdingreg0<0>.CLK  =  !Mclk;	// GCK	(0 pt, 0 inp)

U1/U3/holdingreg0<1> := N_PZ_1001 & U1/U3/holdingreg0<1>
	# MSPReset & !AS & U2_ASedge & U1/Channel0<1>;	// (2 pt, 6 inp)
   U1/U3/holdingreg0<1>.CLK  =  !Mclk;	// GCK	(0 pt, 0 inp)

U1/U3/holdingreg0<2> := N_PZ_1001 & U1/U3/holdingreg0<2>
	# MSPReset & !AS & U2_ASedge & U1/Channel0<2>;	// (2 pt, 6 inp)
   U1/U3/holdingreg0<2>.CLK  =  !Mclk;	// GCK	(0 pt, 0 inp)

U1/U3/holdingreg0<3> := N_PZ_1001 & U1/U3/holdingreg0<3>
	# MSPReset & !AS & U2_ASedge & U1/Channel0<3>;	// (2 pt, 6 inp)
   U1/U3/holdingreg0<3>.CLK  =  !Mclk;	// GCK	(0 pt, 0 inp)

U1/U3/holdingreg0<4> := N_PZ_1001 & U1/U3/holdingreg0<4>
	# MSPReset & !AS & U2_ASedge & U1/Channel0<4>;	// (2 pt, 6 inp)
   U1/U3/holdingreg0<4>.CLK  =  !Mclk;	// GCK	(0 pt, 0 inp)

U1/U3/holdingreg0<5> := N_PZ_1001 & U1/U3/holdingreg0<5>
	# MSPReset & !AS & U2_ASedge & U1/Channel0<5>;	// (2 pt, 6 inp)
   U1/U3/holdingreg0<5>.CLK  =  !Mclk;	// GCK	(0 pt, 0 inp)

U1/U3/holdingreg0<6> := N_PZ_1001 & U1/U3/holdingreg0<6>
	# MSPReset & !AS & U2_ASedge & U1/Channel0<6>;	// (2 pt, 6 inp)
   U1/U3/holdingreg0<6>.CLK  =  !Mclk;	// GCK	(0 pt, 0 inp)

U1/U3/holdingreg0<7> := N_PZ_1001 & U1/U3/holdingreg0<7>
	# MSPReset & !AS & U2_ASedge & U1/Channel0<7>;	// (2 pt, 6 inp)
   U1/U3/holdingreg0<7>.CLK  =  !Mclk;	// GCK	(0 pt, 0 inp)

U1/U3/holdingreg0<8> := N_PZ_1001 & U1/U3/holdingreg0<8>
	# MSPReset & !AS & U2_ASedge & U1/Channel0<8>;	// (2 pt, 6 inp)
   U1/U3/holdingreg0<8>.CLK  =  !Mclk;	// GCK	(0 pt, 0 inp)

U1/U3/holdingreg0<9> := N_PZ_1001 & U1/U3/holdingreg0<9>
	# MSPReset & !AS & U2_ASedge & U1/Channel0<9>;	// (2 pt, 6 inp)
   U1/U3/holdingreg0<9>.CLK  =  !Mclk;	// GCK	(0 pt, 0 inp)

U1/U3/holdingreg0<10> := N_PZ_1001 & U1/U3/holdingreg0<10>
	# MSPReset & !AS & U2_ASedge & U1/Channel0<10>;	// (2 pt, 6 inp)
   U1/U3/holdingreg0<10>.CLK  =  !Mclk;	// GCK	(0 pt, 0 inp)

U1/U3/holdingreg0<11> := N_PZ_1001 & U1/U3/holdingreg0<11>
	# MSPReset & !AS & U2_ASedge & U1/Channel0<11>;	// (2 pt, 6 inp)
   U1/U3/holdingreg0<11>.CLK  =  !Mclk;	// GCK	(0 pt, 0 inp)

U1/U3/holdingreg0<12> := N_PZ_1001 & U1/U3/holdingreg0<12>
	# MSPReset & !AS & U2_ASedge & U1/Channel0<12>;	// (2 pt, 6 inp)
   U1/U3/holdingreg0<12>.CLK  =  !Mclk;	// GCK	(0 pt, 0 inp)

U1/U3/holdingreg0<13> := N_PZ_1001 & U1/U3/holdingreg0<13>
	# MSPReset & !AS & U2_ASedge & U1/Channel0<13>;	// (2 pt, 6 inp)
   U1/U3/holdingreg0<13>.CLK  =  !Mclk;	// GCK	(0 pt, 0 inp)

U1/U3/holdingreg0<14> := N_PZ_1001 & U1/U3/holdingreg0<14>
	# MSPReset & !AS & U2_ASedge & U1/Channel0<14>;	// (2 pt, 6 inp)
   U1/U3/holdingreg0<14>.CLK  =  !Mclk;	// GCK	(0 pt, 0 inp)

U1/U3/holdingreg0<15> := N_PZ_1001 & U1/U3/holdingreg0<15>
	# MSPReset & !AS & U2_ASedge & U1/Channel0<15>;	// (2 pt, 6 inp)
   U1/U3/holdingreg0<15>.CLK  =  !Mclk;	// GCK	(0 pt, 0 inp)

U1/U3/holdingreg1<0> := N_PZ_1001 & U1/U3/holdingreg1<0>
	# MSPReset & !AS & U2_ASedge & U1/Channel1<0>;	// (2 pt, 6 inp)
   U1/U3/holdingreg1<0>.CLK  =  !Mclk;	// GCK	(0 pt, 0 inp)

U1/U3/holdingreg1<1> := N_PZ_1001 & U1/U3/holdingreg1<1>
	# MSPReset & !AS & U2_ASedge & U1/Channel1<1>;	// (2 pt, 6 inp)
   U1/U3/holdingreg1<1>.CLK  =  !Mclk;	// GCK	(0 pt, 0 inp)

U1/U3/holdingreg1<2> := N_PZ_1001 & U1/U3/holdingreg1<2>
	# MSPReset & !AS & U2_ASedge & U1/Channel1<2>;	// (2 pt, 6 inp)
   U1/U3/holdingreg1<2>.CLK  =  !Mclk;	// GCK	(0 pt, 0 inp)

U1/U3/holdingreg1<3> := N_PZ_1001 & U1/U3/holdingreg1<3>
	# MSPReset & !AS & U2_ASedge & U1/Channel1<3>;	// (2 pt, 6 inp)
   U1/U3/holdingreg1<3>.CLK  =  !Mclk;	// GCK	(0 pt, 0 inp)

U1/U3/holdingreg1<4> := N_PZ_1001 & U1/U3/holdingreg1<4>
	# MSPReset & !AS & U2_ASedge & U1/Channel1<4>;	// (2 pt, 6 inp)
   U1/U3/holdingreg1<4>.CLK  =  !Mclk;	// GCK	(0 pt, 0 inp)

U1/U3/holdingreg1<5> := N_PZ_1001 & U1/U3/holdingreg1<5>
	# MSPReset & !AS & U2_ASedge & U1/Channel1<5>;	// (2 pt, 6 inp)
   U1/U3/holdingreg1<5>.CLK  =  !Mclk;	// GCK	(0 pt, 0 inp)

U1/U3/holdingreg1<6> := N_PZ_1001 & U1/U3/holdingreg1<6>
	# MSPReset & !AS & U2_ASedge & U1/Channel1<6>;	// (2 pt, 6 inp)
   U1/U3/holdingreg1<6>.CLK  =  !Mclk;	// GCK	(0 pt, 0 inp)

U1/U3/holdingreg1<7> := N_PZ_1001 & U1/U3/holdingreg1<7>
	# MSPReset & !AS & U2_ASedge & U1/Channel1<7>;	// (2 pt, 6 inp)
   U1/U3/holdingreg1<7>.CLK  =  !Mclk;	// GCK	(0 pt, 0 inp)

U1/U3/holdingreg1<8> := N_PZ_1001 & U1/U3/holdingreg1<8>
	# MSPReset & !AS & U2_ASedge & U1/Channel1<8>;	// (2 pt, 6 inp)
   U1/U3/holdingreg1<8>.CLK  =  !Mclk;	// GCK	(0 pt, 0 inp)

U1/U3/holdingreg1<9> := N_PZ_1001 & U1/U3/holdingreg1<9>
	# MSPReset & !AS & U2_ASedge & U1/Channel1<9>;	// (2 pt, 6 inp)
   U1/U3/holdingreg1<9>.CLK  =  !Mclk;	// GCK	(0 pt, 0 inp)

U1/U3/holdingreg1<10> := N_PZ_1001 & U1/U3/holdingreg1<10>
	# MSPReset & !AS & U2_ASedge & U1/Channel1<10>;	// (2 pt, 6 inp)
   U1/U3/holdingreg1<10>.CLK  =  !Mclk;	// GCK	(0 pt, 0 inp)

U1/U3/holdingreg1<11> := N_PZ_1001 & U1/U3/holdingreg1<11>
	# MSPReset & !AS & U2_ASedge & U1/Channel1<11>;	// (2 pt, 6 inp)
   U1/U3/holdingreg1<11>.CLK  =  !Mclk;	// GCK	(0 pt, 0 inp)

U1/U3/holdingreg1<12> := N_PZ_1001 & U1/U3/holdingreg1<12>
	# MSPReset & !AS & U2_ASedge & U1/Channel1<12>;	// (2 pt, 6 inp)
   U1/U3/holdingreg1<12>.CLK  =  !Mclk;	// GCK	(0 pt, 0 inp)

U1/U3/holdingreg1<13> := N_PZ_1001 & U1/U3/holdingreg1<13>
	# MSPReset & !AS & U2_ASedge & U1/Channel1<13>;	// (2 pt, 6 inp)
   U1/U3/holdingreg1<13>.CLK  =  !Mclk;	// GCK	(0 pt, 0 inp)

U1/U3/holdingreg1<14> := N_PZ_1001 & U1/U3/holdingreg1<14>
	# MSPReset & !AS & U2_ASedge & U1/Channel1<14>;	// (2 pt, 6 inp)
   U1/U3/holdingreg1<14>.CLK  =  !Mclk;	// GCK	(0 pt, 0 inp)

U1/U3/holdingreg1<15> := N_PZ_1001 & U1/U3/holdingreg1<15>
	# MSPReset & !AS & U2_ASedge & U1/Channel1<15>;	// (2 pt, 6 inp)
   U1/U3/holdingreg1<15>.CLK  =  !Mclk;	// GCK	(0 pt, 0 inp)

U1/U4/E0r.T := !MSPReset & U1/U4/E0r
	# !U2_ADDR_reg<2> & !WR & RD & U2_ADDR_reg<0> & 
	!U2_ADDR_reg<4> & !U2_ADDR_reg<5> & !U2_ADDR_reg<6> & !U2_ADDR_reg<7> & 
	U2_ADDR_reg<1> & !AD<1>.PIN & !U2_ADDR_reg<3> & U1/U4/E0r
	# !U2_ADDR_reg<2> & MSPReset & !WR & RD & 
	U2_ADDR_reg<0> & !U2_ADDR_reg<4> & !U2_ADDR_reg<5> & !U2_ADDR_reg<6> & 
	!U2_ADDR_reg<7> & U2_ADDR_reg<1> & AD<1>.PIN & !U2_ADDR_reg<3> & 
	!U1/U4/E0r;	// (3 pt, 13 inp)
   U1/U4/E0r.CLK  =  !Mclk;	// GCK	(0 pt, 0 inp)

U1/U4/E1r.T := !MSPReset & U1/U4/E1r
	# !U2_ADDR_reg<2> & !WR & RD & U2_ADDR_reg<0> & 
	!U2_ADDR_reg<4> & !U2_ADDR_reg<5> & !AD<5>.PIN & !U2_ADDR_reg<6> & 
	!U2_ADDR_reg<7> & U2_ADDR_reg<1> & !U2_ADDR_reg<3> & U1/U4/E1r
	# !U2_ADDR_reg<2> & MSPReset & !WR & RD & 
	U2_ADDR_reg<0> & !U2_ADDR_reg<4> & !U2_ADDR_reg<5> & AD<5>.PIN & 
	!U2_ADDR_reg<6> & !U2_ADDR_reg<7> & U2_ADDR_reg<1> & !U2_ADDR_reg<3> & 
	!U1/U4/E1r;	// (3 pt, 13 inp)
   U1/U4/E1r.CLK  =  !Mclk;	// GCK	(0 pt, 0 inp)

U1/U4/HE0statelastr := U1/U4/HE0stater;	// (1 pt, 1 inp)
   U1/U4/HE0statelastr.CLK  =  !Mclk;	// GCK	(0 pt, 0 inp)


// Direct Input Register
U1/U4/HE0stater := Home0;	// (0 pt, 0 inp)
   U1/U4/HE0stater.CLK  =  !Mclk;	// GCK	(0 pt, 0 inp)

U1/U4/HE1statelastr := U1/U4/HE1stater;	// (1 pt, 1 inp)
   U1/U4/HE1statelastr.CLK  =  !Mclk;	// GCK	(0 pt, 0 inp)


// Direct Input Register
U1/U4/HE1stater := Home1;	// (0 pt, 0 inp)
   U1/U4/HE1stater.CLK  =  !Mclk;	// GCK	(0 pt, 0 inp)


// Direct Input Register
U1/U4/InEdge0r := GP_Motor0_0;	// (0 pt, 0 inp)
   U1/U4/InEdge0r.CLK  =  !Mclk;	// GCK	(0 pt, 0 inp)


// Direct Input Register
U1/U4/InEdge1r := GP_Motor1_0;	// (0 pt, 0 inp)
   U1/U4/InEdge1r.CLK  =  !Mclk;	// GCK	(0 pt, 0 inp)

U1/U4/LastEdge0r := U1/U4/InEdge0r;	// (1 pt, 1 inp)
   U1/U4/LastEdge0r.CLK  =  !Mclk;	// GCK	(0 pt, 0 inp)

U1/U4/LastEdge1r := U1/U4/InEdge1r;	// (1 pt, 1 inp)
   U1/U4/LastEdge1r.CLK  =  !Mclk;	// GCK	(0 pt, 0 inp)

U1/U4/Latch0r<0> := U1/Channel0<0> & N_PZ_1021
	# MSPReset & U1/U4/Latch0r<0> & !U1/U4/latchitH0 & 
	!U1/U4/latchitL0;	// (2 pt, 6 inp)
   U1/U4/Latch0r<0>.CLK  =  !Mclk;	// GCK	(0 pt, 0 inp)

U1/U4/Latch0r<1> := N_PZ_1021 & U1/Channel0<1>
	# MSPReset & !U1/U4/latchitH0 & !U1/U4/latchitL0 & 
	U1/U4/Latch0r<1>;	// (2 pt, 6 inp)
   U1/U4/Latch0r<1>.CLK  =  !Mclk;	// GCK	(0 pt, 0 inp)

U1/U4/Latch0r<2> := N_PZ_1021 & U1/Channel0<2>
	# MSPReset & !U1/U4/latchitH0 & !U1/U4/latchitL0 & 
	U1/U4/Latch0r<2>;	// (2 pt, 6 inp)
   U1/U4/Latch0r<2>.CLK  =  !Mclk;	// GCK	(0 pt, 0 inp)

U1/U4/Latch0r<3> := N_PZ_1021 & U1/Channel0<3>
	# MSPReset & !U1/U4/latchitH0 & !U1/U4/latchitL0 & 
	U1/U4/Latch0r<3>;	// (2 pt, 6 inp)
   U1/U4/Latch0r<3>.CLK  =  !Mclk;	// GCK	(0 pt, 0 inp)

U1/U4/Latch0r<4> := N_PZ_1021 & U1/Channel0<4>
	# MSPReset & !U1/U4/latchitH0 & !U1/U4/latchitL0 & 
	U1/U4/Latch0r<4>;	// (2 pt, 6 inp)
   U1/U4/Latch0r<4>.CLK  =  !Mclk;	// GCK	(0 pt, 0 inp)

U1/U4/Latch0r<5> := N_PZ_1021 & U1/Channel0<5>
	# MSPReset & !U1/U4/latchitH0 & !U1/U4/latchitL0 & 
	U1/U4/Latch0r<5>;	// (2 pt, 6 inp)
   U1/U4/Latch0r<5>.CLK  =  !Mclk;	// GCK	(0 pt, 0 inp)

U1/U4/Latch0r<6> := N_PZ_1021 & U1/Channel0<6>
	# MSPReset & !U1/U4/latchitH0 & !U1/U4/latchitL0 & 
	U1/U4/Latch0r<6>;	// (2 pt, 6 inp)
   U1/U4/Latch0r<6>.CLK  =  !Mclk;	// GCK	(0 pt, 0 inp)

U1/U4/Latch0r<7> := N_PZ_1021 & U1/Channel0<7>
	# MSPReset & !U1/U4/latchitH0 & !U1/U4/latchitL0 & 
	U1/U4/Latch0r<7>;	// (2 pt, 6 inp)
   U1/U4/Latch0r<7>.CLK  =  !Mclk;	// GCK	(0 pt, 0 inp)

U1/U4/Latch0r<8> := N_PZ_1021 & U1/Channel0<8>
	# MSPReset & !U1/U4/latchitH0 & !U1/U4/latchitL0 & 
	U1/U4/Latch0r<8>;	// (2 pt, 6 inp)
   U1/U4/Latch0r<8>.CLK  =  !Mclk;	// GCK	(0 pt, 0 inp)

U1/U4/Latch0r<9> := N_PZ_1021 & U1/Channel0<9>
	# MSPReset & !U1/U4/latchitH0 & !U1/U4/latchitL0 & 
	U1/U4/Latch0r<9>;	// (2 pt, 6 inp)
   U1/U4/Latch0r<9>.CLK  =  !Mclk;	// GCK	(0 pt, 0 inp)

U1/U4/Latch0r<10> := N_PZ_1021 & U1/Channel0<10>
	# MSPReset & !U1/U4/latchitH0 & !U1/U4/latchitL0 & 
	U1/U4/Latch0r<10>;	// (2 pt, 6 inp)
   U1/U4/Latch0r<10>.CLK  =  !Mclk;	// GCK	(0 pt, 0 inp)

U1/U4/Latch0r<11> := N_PZ_1021 & U1/Channel0<11>
	# MSPReset & !U1/U4/latchitH0 & !U1/U4/latchitL0 & 
	U1/U4/Latch0r<11>;	// (2 pt, 6 inp)
   U1/U4/Latch0r<11>.CLK  =  !Mclk;	// GCK	(0 pt, 0 inp)

U1/U4/Latch0r<12> := N_PZ_1021 & U1/Channel0<12>
	# MSPReset & !U1/U4/latchitH0 & !U1/U4/latchitL0 & 
	U1/U4/Latch0r<12>;	// (2 pt, 6 inp)
   U1/U4/Latch0r<12>.CLK  =  !Mclk;	// GCK	(0 pt, 0 inp)

U1/U4/Latch0r<13> := N_PZ_1021 & U1/Channel0<13>
	# MSPReset & !U1/U4/latchitH0 & !U1/U4/latchitL0 & 
	U1/U4/Latch0r<13>;	// (2 pt, 6 inp)
   U1/U4/Latch0r<13>.CLK  =  !Mclk;	// GCK	(0 pt, 0 inp)

U1/U4/Latch0r<14> := N_PZ_1021 & U1/Channel0<14>
	# MSPReset & !U1/U4/latchitH0 & !U1/U4/latchitL0 & 
	U1/U4/Latch0r<14>;	// (2 pt, 6 inp)
   U1/U4/Latch0r<14>.CLK  =  !Mclk;	// GCK	(0 pt, 0 inp)

U1/U4/Latch0r<15> := N_PZ_1021 & U1/Channel0<15>
	# MSPReset & !U1/U4/latchitH0 & !U1/U4/latchitL0 & 
	U1/U4/Latch0r<15>;	// (2 pt, 6 inp)
   U1/U4/Latch0r<15>.CLK  =  !Mclk;	// GCK	(0 pt, 0 inp)

U1/U4/Latch1r<0> := U1/Channel1<0> & N_PZ_1019
	# MSPReset & U1/U4/Latch1r<0> & !U1/U4/latchitH1 & 
	!U1/U4/latchitL1;	// (2 pt, 6 inp)
   U1/U4/Latch1r<0>.CLK  =  !Mclk;	// GCK	(0 pt, 0 inp)

U1/U4/Latch1r<1> := N_PZ_1019 & U1/Channel1<1>
	# MSPReset & !U1/U4/latchitH1 & !U1/U4/latchitL1 & 
	U1/U4/Latch1r<1>;	// (2 pt, 6 inp)
   U1/U4/Latch1r<1>.CLK  =  !Mclk;	// GCK	(0 pt, 0 inp)

U1/U4/Latch1r<2> := N_PZ_1019 & U1/Channel1<2>
	# MSPReset & !U1/U4/latchitH1 & !U1/U4/latchitL1 & 
	U1/U4/Latch1r<2>;	// (2 pt, 6 inp)
   U1/U4/Latch1r<2>.CLK  =  !Mclk;	// GCK	(0 pt, 0 inp)

U1/U4/Latch1r<3> := N_PZ_1019 & U1/Channel1<3>
	# MSPReset & !U1/U4/latchitH1 & !U1/U4/latchitL1 & 
	U1/U4/Latch1r<3>;	// (2 pt, 6 inp)
   U1/U4/Latch1r<3>.CLK  =  !Mclk;	// GCK	(0 pt, 0 inp)

U1/U4/Latch1r<4> := N_PZ_1019 & U1/Channel1<4>
	# MSPReset & !U1/U4/latchitH1 & !U1/U4/latchitL1 & 
	U1/U4/Latch1r<4>;	// (2 pt, 6 inp)
   U1/U4/Latch1r<4>.CLK  =  !Mclk;	// GCK	(0 pt, 0 inp)

U1/U4/Latch1r<5> := N_PZ_1019 & U1/Channel1<5>
	# MSPReset & !U1/U4/latchitH1 & !U1/U4/latchitL1 & 
	U1/U4/Latch1r<5>;	// (2 pt, 6 inp)
   U1/U4/Latch1r<5>.CLK  =  !Mclk;	// GCK	(0 pt, 0 inp)

U1/U4/Latch1r<6> := N_PZ_1019 & U1/Channel1<6>
	# MSPReset & !U1/U4/latchitH1 & !U1/U4/latchitL1 & 
	U1/U4/Latch1r<6>;	// (2 pt, 6 inp)
   U1/U4/Latch1r<6>.CLK  =  !Mclk;	// GCK	(0 pt, 0 inp)

U1/U4/Latch1r<7> := N_PZ_1019 & U1/Channel1<7>
	# MSPReset & !U1/U4/latchitH1 & !U1/U4/latchitL1 & 
	U1/U4/Latch1r<7>;	// (2 pt, 6 inp)
   U1/U4/Latch1r<7>.CLK  =  !Mclk;	// GCK	(0 pt, 0 inp)

U1/U4/Latch1r<8> := N_PZ_1019 & U1/Channel1<8>
	# MSPReset & !U1/U4/latchitH1 & !U1/U4/latchitL1 & 
	U1/U4/Latch1r<8>;	// (2 pt, 6 inp)
   U1/U4/Latch1r<8>.CLK  =  !Mclk;	// GCK	(0 pt, 0 inp)

U1/U4/Latch1r<9> := N_PZ_1019 & U1/Channel1<9>
	# MSPReset & !U1/U4/latchitH1 & !U1/U4/latchitL1 & 
	U1/U4/Latch1r<9>;	// (2 pt, 6 inp)
   U1/U4/Latch1r<9>.CLK  =  !Mclk;	// GCK	(0 pt, 0 inp)

U1/U4/Latch1r<10> := N_PZ_1019 & U1/Channel1<10>
	# MSPReset & !U1/U4/latchitH1 & !U1/U4/latchitL1 & 
	U1/U4/Latch1r<10>;	// (2 pt, 6 inp)
   U1/U4/Latch1r<10>.CLK  =  !Mclk;	// GCK	(0 pt, 0 inp)

U1/U4/Latch1r<11> := N_PZ_1019 & U1/Channel1<11>
	# MSPReset & !U1/U4/latchitH1 & !U1/U4/latchitL1 & 
	U1/U4/Latch1r<11>;	// (2 pt, 6 inp)
   U1/U4/Latch1r<11>.CLK  =  !Mclk;	// GCK	(0 pt, 0 inp)

U1/U4/Latch1r<12> := N_PZ_1019 & U1/Channel1<12>
	# MSPReset & !U1/U4/latchitH1 & !U1/U4/latchitL1 & 
	U1/U4/Latch1r<12>;	// (2 pt, 6 inp)
   U1/U4/Latch1r<12>.CLK  =  !Mclk;	// GCK	(0 pt, 0 inp)

U1/U4/Latch1r<13> := N_PZ_1019 & U1/Channel1<13>
	# MSPReset & !U1/U4/latchitH1 & !U1/U4/latchitL1 & 
	U1/U4/Latch1r<13>;	// (2 pt, 6 inp)
   U1/U4/Latch1r<13>.CLK  =  !Mclk;	// GCK	(0 pt, 0 inp)

U1/U4/Latch1r<14> := N_PZ_1019 & U1/Channel1<14>
	# MSPReset & !U1/U4/latchitH1 & !U1/U4/latchitL1 & 
	U1/U4/Latch1r<14>;	// (2 pt, 6 inp)
   U1/U4/Latch1r<14>.CLK  =  !Mclk;	// GCK	(0 pt, 0 inp)

U1/U4/Latch1r<15> := N_PZ_1019 & U1/Channel1<15>
	# MSPReset & !U1/U4/latchitH1 & !U1/U4/latchitL1 & 
	U1/U4/Latch1r<15>;	// (2 pt, 6 inp)
   U1/U4/Latch1r<15>.CLK  =  !Mclk;	// GCK	(0 pt, 0 inp)

U1/U4/LatchEdge0r.T := !MSPReset & U1/U4/LatchEdge0r
	# !U2_ADDR_reg<2> & !AD<2>.PIN & !WR & RD & 
	U2_ADDR_reg<0> & !U2_ADDR_reg<4> & !U2_ADDR_reg<5> & !U2_ADDR_reg<6> & 
	!U2_ADDR_reg<7> & U2_ADDR_reg<1> & !U2_ADDR_reg<3> & 
	U1/U4/LatchEdge0r
	# !U2_ADDR_reg<2> & MSPReset & AD<2>.PIN & !WR & 
	RD & U2_ADDR_reg<0> & !U2_ADDR_reg<4> & !U2_ADDR_reg<5> & 
	!U2_ADDR_reg<6> & !U2_ADDR_reg<7> & U2_ADDR_reg<1> & !U2_ADDR_reg<3> & 
	!U1/U4/LatchEdge0r;	// (3 pt, 13 inp)
   U1/U4/LatchEdge0r.CLK  =  !Mclk;	// GCK	(0 pt, 0 inp)

U1/U4/LatchEdge1r.T := !MSPReset & U1/U4/LatchEdge1r
	# !U2_ADDR_reg<2> & !WR & RD & U2_ADDR_reg<0> & 
	!U2_ADDR_reg<4> & !U2_ADDR_reg<5> & !U2_ADDR_reg<6> & !AD<6>.PIN & 
	!U2_ADDR_reg<7> & U2_ADDR_reg<1> & !U2_ADDR_reg<3> & 
	U1/U4/LatchEdge1r
	# !U2_ADDR_reg<2> & MSPReset & !WR & RD & 
	U2_ADDR_reg<0> & !U2_ADDR_reg<4> & !U2_ADDR_reg<5> & !U2_ADDR_reg<6> & 
	AD<6>.PIN & !U2_ADDR_reg<7> & U2_ADDR_reg<1> & !U2_ADDR_reg<3> & 
	!U1/U4/LatchEdge1r;	// (3 pt, 13 inp)
   U1/U4/LatchEdge1r.CLK  =  !Mclk;	// GCK	(0 pt, 0 inp)

U1/U4/RF0r.T := !MSPReset & U1/U4/RF0r
	# !U2_ADDR_reg<2> & !WR & RD & U2_ADDR_reg<0> & 
	!AD<0>.PIN & !U2_ADDR_reg<4> & !U2_ADDR_reg<5> & !U2_ADDR_reg<6> & 
	!U2_ADDR_reg<7> & U2_ADDR_reg<1> & !U2_ADDR_reg<3> & U1/U4/RF0r
	# !U2_ADDR_reg<2> & MSPReset & !WR & RD & 
	U2_ADDR_reg<0> & AD<0>.PIN & !U2_ADDR_reg<4> & !U2_ADDR_reg<5> & 
	!U2_ADDR_reg<6> & !U2_ADDR_reg<7> & U2_ADDR_reg<1> & !U2_ADDR_reg<3> & 
	!U1/U4/RF0r;	// (3 pt, 13 inp)
   U1/U4/RF0r.CLK  =  !Mclk;	// GCK	(0 pt, 0 inp)

U1/U4/RF1r.T := !MSPReset & U1/U4/RF1r
	# !U2_ADDR_reg<2> & !WR & RD & U2_ADDR_reg<0> & 
	!U2_ADDR_reg<4> & !AD<4>.PIN & !U2_ADDR_reg<5> & !U2_ADDR_reg<6> & 
	!U2_ADDR_reg<7> & U2_ADDR_reg<1> & !U2_ADDR_reg<3> & U1/U4/RF1r
	# !U2_ADDR_reg<2> & MSPReset & !WR & RD & 
	U2_ADDR_reg<0> & !U2_ADDR_reg<4> & AD<4>.PIN & !U2_ADDR_reg<5> & 
	!U2_ADDR_reg<6> & !U2_ADDR_reg<7> & U2_ADDR_reg<1> & !U2_ADDR_reg<3> & 
	!U1/U4/RF1r;	// (3 pt, 13 inp)
   U1/U4/RF1r.CLK  =  !Mclk;	// GCK	(0 pt, 0 inp)

U1/U4/latchitH0 := !NET2482 & U1/U4/E0r & U1/U4/RF0r & 
	U1/U4/HE0stater & !U1/U4/HE0statelastr & !N_PZ_1030
	# !NET2482 & U1/U4/E0r & !U1/U4/RF0r & 
	!U1/U4/HE0stater & U1/U4/HE0statelastr & !N_PZ_1030
	# !U2_ADDR_reg<2> & MSPReset & !WR & RD & 
	U2_ADDR_reg<0> & !U2_ADDR_reg<4> & !U2_ADDR_reg<5> & !U2_ADDR_reg<6> & 
	!U2_ADDR_reg<7> & !U2_ADDR_reg<3> & U1/U4/latchitH0;	// (3 pt, 17 inp)
   U1/U4/latchitH0.CLK  =  !Mclk;	// GCK	(0 pt, 0 inp)

U1/U4/latchitH1 := !N_PZ_1030 & !NET2493 & U1/U4/E1r & U1/U4/RF1r & 
	U1/U4/HE1stater & !U1/U4/HE1statelastr
	# !N_PZ_1030 & !NET2493 & U1/U4/E1r & !U1/U4/RF1r & 
	!U1/U4/HE1stater & U1/U4/HE1statelastr
	# !U2_ADDR_reg<2> & MSPReset & !WR & RD & 
	U2_ADDR_reg<0> & !U2_ADDR_reg<4> & !U2_ADDR_reg<5> & !U2_ADDR_reg<6> & 
	!U2_ADDR_reg<7> & !U2_ADDR_reg<3> & U1/U4/latchitH1;	// (3 pt, 17 inp)
   U1/U4/latchitH1.CLK  =  !Mclk;	// GCK	(0 pt, 0 inp)

U1/U4/latchitL0 := !N_PZ_1030 & !TP26 & U1/U4/LatchEdge0r & 
	U1/U4/InEdge0r & !U1/U4/LastEdge0r
	# !N_PZ_1030 & !TP26 & !U1/U4/LatchEdge0r & 
	!U1/U4/InEdge0r & U1/U4/LastEdge0r
	# !U2_ADDR_reg<2> & MSPReset & !WR & RD & 
	U2_ADDR_reg<0> & !U2_ADDR_reg<4> & !U2_ADDR_reg<5> & !U2_ADDR_reg<6> & 
	!U2_ADDR_reg<7> & !U2_ADDR_reg<3> & U1/U4/latchitL0;	// (3 pt, 16 inp)
   U1/U4/latchitL0.CLK  =  !Mclk;	// GCK	(0 pt, 0 inp)

U1/U4/latchitL1 := !N_PZ_1030 & !NET2512 & U1/U4/LatchEdge1r & 
	U1/U4/InEdge1r & !U1/U4/LastEdge1r
	# !N_PZ_1030 & !NET2512 & !U1/U4/LatchEdge1r & 
	!U1/U4/InEdge1r & U1/U4/LastEdge1r
	# !U2_ADDR_reg<2> & MSPReset & !WR & RD & 
	U2_ADDR_reg<0> & !U2_ADDR_reg<4> & !U2_ADDR_reg<5> & !U2_ADDR_reg<6> & 
	!U2_ADDR_reg<7> & !U2_ADDR_reg<3> & U1/U4/latchitL1;	// (3 pt, 16 inp)
   U1/U4/latchitL1.CLK  =  !Mclk;	// GCK	(0 pt, 0 inp)

U1/U5/location_or0001 = U1/NET3720
	$ U1/U6/CurrState_Sreg0_FSM_FFd4 & 
	!U1/U6/CurrState_Sreg0_FSM_FFd3
	# !U1/U6/CurrState_Sreg0_FSM_FFd4 & 
	U1/U6/CurrState_Sreg0_FSM_FFd3 & !U1/U6/CurrState_Sreg0_FSM_FFd2
	# !U1/U6/CurrState_Sreg0_FSM_FFd3 & 
	U1/U6/CurrState_Sreg0_FSM_FFd2 & !U1/U6/CurrState_Sreg0_FSM_FFd1;	// (4 pt, 5 inp)

U1/U6/CurrState_Sreg0_FSM_FFd1 := MSPReset & U1/U6/CurrState_Sreg0_FSM_FFd4 & 
	!PhaseA_Encoder1 & !PhaseB_Encoder1 & U1/U6/CurrState_Sreg0_FSM_FFd3 & 
	U1/U6/CurrState_Sreg0_FSM_FFd2;	// (1 pt, 6 inp)
   U1/U6/CurrState_Sreg0_FSM_FFd1.CLK  =  Mclk;	// GCK	(0 pt, 0 inp)

U1/U6/CurrState_Sreg0_FSM_FFd2.T := !MSPReset & U1/U6/CurrState_Sreg0_FSM_FFd2
	# !U1/U6/CurrState_Sreg0_FSM_FFd4 & 
	!U1/U6/CurrState_Sreg0_FSM_FFd3 & U1/U6/CurrState_Sreg0_FSM_FFd2
	# PhaseA_Encoder1 & PhaseB_Encoder1 & 
	!U1/U6/CurrState_Sreg0_FSM_FFd3 & U1/U6/CurrState_Sreg0_FSM_FFd2
	# MSPReset & !U1/U6/CurrState_Sreg0_FSM_FFd4 & 
	!PhaseA_Encoder1 & PhaseB_Encoder1 & U1/U6/CurrState_Sreg0_FSM_FFd3
	# MSPReset & U1/U6/CurrState_Sreg0_FSM_FFd4 & 
	PhaseA_Encoder1 & PhaseB_Encoder1 & U1/U6/CurrState_Sreg0_FSM_FFd3 & 
	!U1/U6/CurrState_Sreg0_FSM_FFd2;	// (5 pt, 6 inp)
   U1/U6/CurrState_Sreg0_FSM_FFd2.CLK  =  Mclk;	// GCK	(0 pt, 0 inp)

U1/U6/CurrState_Sreg0_FSM_FFd3.T := !MSPReset & U1/U6/CurrState_Sreg0_FSM_FFd3
	# U1/U6/CurrState_Sreg0_FSM_FFd4 & !PhaseA_Encoder1 & 
	!PhaseB_Encoder1 & U1/U6/CurrState_Sreg0_FSM_FFd3
	# MSPReset & U1/U6/CurrState_Sreg0_FSM_FFd4 & 
	PhaseA_Encoder1 & PhaseB_Encoder1 & !U1/U6/CurrState_Sreg0_FSM_FFd3
	# MSPReset & !U1/U6/CurrState_Sreg0_FSM_FFd4 & 
	!PhaseA_Encoder1 & PhaseB_Encoder1 & !U1/U6/CurrState_Sreg0_FSM_FFd2
	# !U1/U6/CurrState_Sreg0_FSM_FFd4 & PhaseA_Encoder1 & 
	!PhaseB_Encoder1 & U1/U6/CurrState_Sreg0_FSM_FFd3 & 
	!U1/U6/CurrState_Sreg0_FSM_FFd2;	// (5 pt, 6 inp)
   U1/U6/CurrState_Sreg0_FSM_FFd3.CLK  =  Mclk;	// GCK	(0 pt, 0 inp)

!U1/U6/CurrState_Sreg0_FSM_FFd4 := !MSPReset
	# PhaseA_Encoder1 & PhaseB_Encoder1
	# !PhaseA_Encoder1 & !PhaseB_Encoder1
	# !U1/U6/CurrState_Sreg0_FSM_FFd4 & 
	!U1/U6/CurrState_Sreg0_FSM_FFd3 & U1/U6/CurrState_Sreg0_FSM_FFd2;	// (4 pt, 6 inp)
   U1/U6/CurrState_Sreg0_FSM_FFd4.CLK  =  Mclk;	// GCK	(0 pt, 0 inp)

U11_Incdetect := !SCLinc & U11_U1/Line_last;	// (1 pt, 2 inp)
   U11_Incdetect.CLK  =  !Mclk;	// GCK	(0 pt, 0 inp)

U11_ResetDetect := !SCLreset & U11_U4/Line_last;	// (1 pt, 2 inp)
   U11_ResetDetect.CLK  =  !Mclk;	// GCK	(0 pt, 0 inp)

U11_SCLdetect := !SCL.PIN & U11_U2/Line_last;	// (1 pt, 2 inp)
   U11_SCLdetect.CLK  =  !Mclk;	// GCK	(0 pt, 0 inp)


// Direct Input Register
U11_U1/Line_last := SCLinc;	// (0 pt, 0 inp)
   U11_U1/Line_last.CLK  =  !Mclk;	// GCK	(0 pt, 0 inp)

SCL =  Gnd;	// (0 pt, 0 inp)
    SCL.OE = TP12;	// LOE	(1 pt, 1 inp)
// Direct Input Register
U11_U2/Line_last := SCL.PIN;	// (0 pt, 0 inp)
   U11_U2/Line_last.CLK  =  !Mclk;	// GCK	(0 pt, 0 inp)

U11_U3_counterr<0> := SCLreset & SCLinc
	# U11_U3_counterr<0> & !SCLreset & U11_Incdetect & 
	U11_SCLdetect
	# U11_U3_counterr<0> & !SCLreset & !U11_Incdetect & 
	!U11_SCLdetect
	# !U11_U3_counterr<0> & !SCLreset & U11_Incdetect & 
	!U11_SCLdetect
	# !SCLreset & !SCLinc & U11_Incdetect & 
	U11_ResetDetect
	# !U11_U3_counterr<0> & !SCLreset & !U11_Incdetect & 
	U11_SCLdetect & !TP12;	// (6 pt, 7 inp)
   U11_U3_counterr<0>.CLK  =  !Mclk;	// GCK	(0 pt, 0 inp)

U11_U3_counterr<1>.T := U11_U3_counterr<1> & N_PZ_1142
	$ SCLreset & !SCLinc & N_PZ_1142
	# U11_U3_counterr<0> & U11_Incdetect & 
	!U11_SCLdetect & !N_PZ_1142
	# !U11_U3_counterr<0> & !U11_Incdetect & 
	U11_SCLdetect & !N_PZ_1142;	// (4 pt, 7 inp)
   U11_U3_counterr<1>.CLK  =  !Mclk;	// GCK	(0 pt, 0 inp)

U11_U3_counterr<2>.T := N_PZ_1142 & U11_U3_counterr<2>
	# U11_U3_counterr<0> & U11_Incdetect & 
	!U11_SCLdetect & U11_U3_counterr<1> & !N_PZ_1142
	# !U11_U3_counterr<0> & !U11_Incdetect & 
	U11_SCLdetect & !U11_U3_counterr<1> & !N_PZ_1142;	// (3 pt, 6 inp)
   U11_U3_counterr<2>.CLK  =  !Mclk;	// GCK	(0 pt, 0 inp)

!U11_U3_counterr<3>.T := SCLreset & U11_U3_counterr<3>
	# U11_U3_counterr<0> & !U11_Incdetect & !N_PZ_1142
	# !SCLreset & N_PZ_1142 & !U11_U3_counterr<3>
	# !U11_Incdetect & !U11_SCLdetect & !N_PZ_1142
	# !U11_Incdetect & U11_U3_counterr<1> & !N_PZ_1142
	# !U11_Incdetect & !N_PZ_1142 & U11_U3_counterr<2>
	# U11_U3_counterr<0> & !U11_SCLdetect & 
	U11_U3_counterr<1> & !N_PZ_1142 & U11_U3_counterr<2>;	// (7 pt, 8 inp)
   U11_U3_counterr<3>.CLK  =  !Mclk;	// GCK	(0 pt, 0 inp)

U11_U3_counterr<4>.T := N_PZ_1142 & U11_U3_counterr<4>
	# U11_Incdetect & !N_PZ_1142 & U11_U3_counterr<3>
	# U11_U3_counterr<0> & U11_Incdetect & 
	!U11_SCLdetect & U11_U3_counterr<1> & !N_PZ_1142 & 
	U11_U3_counterr<2>
	# !U11_U3_counterr<0> & !U11_Incdetect & 
	U11_SCLdetect & !U11_U3_counterr<1> & !N_PZ_1142 & 
	!U11_U3_counterr<2> & !U11_U3_counterr<3>;	// (4 pt, 8 inp)
   U11_U3_counterr<4>.CLK  =  !Mclk;	// GCK	(0 pt, 0 inp)

U11_U3_counterr<5>.T := N_PZ_1142 & U11_U3_counterr<5>
	# U11_Incdetect & !N_PZ_1142 & U11_U3_counterr<3> & 
	U11_U3_counterr<4>
	# U11_U3_counterr<0> & U11_Incdetect & 
	!U11_SCLdetect & U11_U3_counterr<1> & !N_PZ_1142 & 
	U11_U3_counterr<2> & U11_U3_counterr<4>
	# !U11_U3_counterr<0> & !U11_Incdetect & 
	U11_SCLdetect & !U11_U3_counterr<1> & !N_PZ_1142 & 
	!U11_U3_counterr<2> & !U11_U3_counterr<3> & !U11_U3_counterr<4>;	// (4 pt, 9 inp)
   U11_U3_counterr<5>.CLK  =  !Mclk;	// GCK	(0 pt, 0 inp)


// Direct Input Register
U11_U4/Line_last := SCLreset;	// (0 pt, 0 inp)
   U11_U4/Line_last.CLK  =  !Mclk;	// GCK	(0 pt, 0 inp)

U2_ADDR_reg<0>.T := !MSPReset & U2_ADDR_reg<0>
	# !AS & U2_ASedge & U2_WRRDedge_and0000 & 
	U2_ADDR_reg<0> & !AD<0>.PIN
	# MSPReset & !AS & U2_ASedge & U2_WRRDedge_and0000 & 
	!U2_ADDR_reg<0> & AD<0>.PIN
	# U2_WRRDedge_and0000 & !U2_ADDR_reg<4> & 
	!U2_ADDR_reg<5> & !U2_ADDR_reg<6> & !U2_ADDR_reg<7> & U2_AutoInc & 
	!U2_WRRDedge & N_PZ_1001;	// (4 pt, 13 inp)
   U2_ADDR_reg<0>.CLK  =  !Mclk;	// GCK	(0 pt, 0 inp)

U2_ADDR_reg<1>.T := !MSPReset & U2_ADDR_reg<1>
	# !AS & U2_ASedge & U2_WRRDedge_and0000 & 
	U2_ADDR_reg<1> & !AD<1>.PIN
	# MSPReset & !AS & U2_ASedge & U2_WRRDedge_and0000 & 
	!U2_ADDR_reg<1> & AD<1>.PIN
	# U2_WRRDedge_and0000 & U2_ADDR_reg<0> & 
	!U2_ADDR_reg<4> & !U2_ADDR_reg<5> & !U2_ADDR_reg<6> & !U2_ADDR_reg<7> & 
	U2_AutoInc & !U2_WRRDedge & N_PZ_1001;	// (4 pt, 14 inp)
   U2_ADDR_reg<1>.CLK  =  !Mclk;	// GCK	(0 pt, 0 inp)

U2_ADDR_reg<2>.T := U2_ADDR_reg<2> & !MSPReset
	# U2_ADDR_reg<2> & !AD<2>.PIN & !AS & U2_ASedge & 
	U2_WRRDedge_and0000
	# !U2_ADDR_reg<2> & MSPReset & AD<2>.PIN & !AS & 
	U2_ASedge & U2_WRRDedge_and0000
	# U2_WRRDedge_and0000 & U2_ADDR_reg<0> & 
	!U2_ADDR_reg<4> & !U2_ADDR_reg<5> & !U2_ADDR_reg<6> & !U2_ADDR_reg<7> & 
	U2_AutoInc & !U2_WRRDedge & N_PZ_1001 & U2_ADDR_reg<1>;	// (4 pt, 15 inp)
   U2_ADDR_reg<2>.CLK  =  !Mclk;	// GCK	(0 pt, 0 inp)

U2_ADDR_reg<3>.T := !MSPReset & U2_ADDR_reg<3>
	# !AS & U2_ASedge & U2_WRRDedge_and0000 & 
	U2_ADDR_reg<3> & !AD<3>.PIN
	# MSPReset & !AS & U2_ASedge & U2_WRRDedge_and0000 & 
	!U2_ADDR_reg<3> & AD<3>.PIN
	# U2_ADDR_reg<2> & U2_WRRDedge_and0000 & 
	U2_ADDR_reg<0> & !U2_ADDR_reg<4> & !U2_ADDR_reg<5> & !U2_ADDR_reg<6> & 
	!U2_ADDR_reg<7> & U2_AutoInc & !U2_WRRDedge & N_PZ_1001 & 
	U2_ADDR_reg<1>;	// (4 pt, 16 inp)
   U2_ADDR_reg<3>.CLK  =  !Mclk;	// GCK	(0 pt, 0 inp)

U2_ADDR_reg<4>.T := !MSPReset & U2_ADDR_reg<4>
	# !AS & U2_ASedge & U2_WRRDedge_and0000 & 
	U2_ADDR_reg<4> & !AD<4>.PIN
	# MSPReset & !AS & U2_ASedge & U2_WRRDedge_and0000 & 
	!U2_ADDR_reg<4> & AD<4>.PIN;	// (3 pt, 6 inp)
   U2_ADDR_reg<4>.CLK  =  !Mclk;	// GCK	(0 pt, 0 inp)

U2_ADDR_reg<5>.T := !MSPReset & U2_ADDR_reg<5>
	# !AS & U2_ASedge & U2_WRRDedge_and0000 & 
	U2_ADDR_reg<5> & !AD<5>.PIN
	# MSPReset & !AS & U2_ASedge & U2_WRRDedge_and0000 & 
	!U2_ADDR_reg<5> & AD<5>.PIN;	// (3 pt, 6 inp)
   U2_ADDR_reg<5>.CLK  =  !Mclk;	// GCK	(0 pt, 0 inp)

U2_ADDR_reg<6>.T := !MSPReset & U2_ADDR_reg<6>
	# !AS & U2_ASedge & U2_WRRDedge_and0000 & 
	U2_ADDR_reg<6> & !AD<6>.PIN
	# MSPReset & !AS & U2_ASedge & U2_WRRDedge_and0000 & 
	!U2_ADDR_reg<6> & AD<6>.PIN;	// (3 pt, 6 inp)
   U2_ADDR_reg<6>.CLK  =  !Mclk;	// GCK	(0 pt, 0 inp)

U2_ADDR_reg<7>.T := !MSPReset & U2_ADDR_reg<7>
	# !AS & U2_ASedge & U2_WRRDedge_and0000 & 
	U2_ADDR_reg<7> & !AD<7>.PIN
	# MSPReset & !AS & U2_ASedge & U2_WRRDedge_and0000 & 
	!U2_ADDR_reg<7> & AD<7>.PIN;	// (3 pt, 6 inp)
   U2_ADDR_reg<7>.CLK  =  !Mclk;	// GCK	(0 pt, 0 inp)


// Direct Input Register
U2_ASedge := AS;	// (0 pt, 0 inp)
   U2_ASedge.CLK  =  !Mclk;	// GCK	(0 pt, 0 inp)

U2_AutoInc := !AS;	// (1 pt, 1 inp)
   U2_AutoInc.CLK  =  !Mclk;	// GCK	(0 pt, 0 inp)
    U2_AutoInc.CE = !U2_WRRDedge_and0000 & U2_WRRDedge;	// (1 pt, 2 inp)

U2_Enable_AD = WR & !RD & !U2_ADDR_reg<4> & !U2_ADDR_reg<5> & 
	!U2_ADDR_reg<6> & !U2_ADDR_reg<7>;	// (1 pt, 6 inp)

U2_WRRDedge := WR & RD;	// (1 pt, 2 inp)
   U2_WRRDedge.CLK  =  !Mclk;	// GCK	(0 pt, 0 inp)

U2_WRRDedge_and0000 = WR & RD;	// (1 pt, 2 inp)

U3/DCORIE<0>.T := !MSPReset & U3/DCORIE<0>
	# !U2_ADDR_reg<2> & !WR & RD & !U2_ADDR_reg<0> & 
	!AD<0>.PIN & !U2_ADDR_reg<4> & !U2_ADDR_reg<5> & !U2_ADDR_reg<6> & 
	!U2_ADDR_reg<7> & !U2_ADDR_reg<1> & !U2_ADDR_reg<3> & U3/DCORIE<0>
	# !U2_ADDR_reg<2> & MSPReset & !WR & RD & 
	!U2_ADDR_reg<0> & AD<0>.PIN & !U2_ADDR_reg<4> & !U2_ADDR_reg<5> & 
	!U2_ADDR_reg<6> & !U2_ADDR_reg<7> & !U2_ADDR_reg<1> & !U2_ADDR_reg<3> & 
	!U3/DCORIE<0>;	// (3 pt, 13 inp)
   U3/DCORIE<0>.CLK  =  !Mclk;	// GCK	(0 pt, 0 inp)

U3/DCORIE<1>.T := !MSPReset & U3/DCORIE<1>
	# !U2_ADDR_reg<2> & !WR & RD & !U2_ADDR_reg<0> & 
	!U2_ADDR_reg<4> & !U2_ADDR_reg<5> & !U2_ADDR_reg<6> & !U2_ADDR_reg<7> & 
	!U2_ADDR_reg<1> & !AD<1>.PIN & !U2_ADDR_reg<3> & U3/DCORIE<1>
	# !U2_ADDR_reg<2> & MSPReset & !WR & RD & 
	!U2_ADDR_reg<0> & !U2_ADDR_reg<4> & !U2_ADDR_reg<5> & !U2_ADDR_reg<6> & 
	!U2_ADDR_reg<7> & !U2_ADDR_reg<1> & AD<1>.PIN & !U2_ADDR_reg<3> & 
	!U3/DCORIE<1>;	// (3 pt, 13 inp)
   U3/DCORIE<1>.CLK  =  !Mclk;	// GCK	(0 pt, 0 inp)

U3/DCORIE<2>.T := !MSPReset & U3/DCORIE<2>
	# !U2_ADDR_reg<2> & !AD<2>.PIN & !WR & RD & 
	!U2_ADDR_reg<0> & !U2_ADDR_reg<4> & !U2_ADDR_reg<5> & !U2_ADDR_reg<6> & 
	!U2_ADDR_reg<7> & !U2_ADDR_reg<1> & !U2_ADDR_reg<3> & U3/DCORIE<2>
	# !U2_ADDR_reg<2> & MSPReset & AD<2>.PIN & !WR & 
	RD & !U2_ADDR_reg<0> & !U2_ADDR_reg<4> & !U2_ADDR_reg<5> & 
	!U2_ADDR_reg<6> & !U2_ADDR_reg<7> & !U2_ADDR_reg<1> & !U2_ADDR_reg<3> & 
	!U3/DCORIE<2>;	// (3 pt, 13 inp)
   U3/DCORIE<2>.CLK  =  !Mclk;	// GCK	(0 pt, 0 inp)

U3/DCORIE<3>.T := !MSPReset & U3/DCORIE<3>
	# !U2_ADDR_reg<2> & !WR & RD & !U2_ADDR_reg<0> & 
	!U2_ADDR_reg<4> & !U2_ADDR_reg<5> & !U2_ADDR_reg<6> & !U2_ADDR_reg<7> & 
	!U2_ADDR_reg<1> & !U2_ADDR_reg<3> & !AD<3>.PIN & U3/DCORIE<3>
	# !U2_ADDR_reg<2> & MSPReset & !WR & RD & 
	!U2_ADDR_reg<0> & !U2_ADDR_reg<4> & !U2_ADDR_reg<5> & !U2_ADDR_reg<6> & 
	!U2_ADDR_reg<7> & !U2_ADDR_reg<1> & !U2_ADDR_reg<3> & AD<3>.PIN & 
	!U3/DCORIE<3>;	// (3 pt, 13 inp)
   U3/DCORIE<3>.CLK  =  !Mclk;	// GCK	(0 pt, 0 inp)

U3/DCORIE<4>.T := !MSPReset & U3/DCORIE<4>
	# !U2_ADDR_reg<2> & !WR & RD & !U2_ADDR_reg<0> & 
	!U2_ADDR_reg<4> & !AD<4>.PIN & !U2_ADDR_reg<5> & !U2_ADDR_reg<6> & 
	!U2_ADDR_reg<7> & !U2_ADDR_reg<1> & !U2_ADDR_reg<3> & U3/DCORIE<4>
	# !U2_ADDR_reg<2> & MSPReset & !WR & RD & 
	!U2_ADDR_reg<0> & !U2_ADDR_reg<4> & AD<4>.PIN & !U2_ADDR_reg<5> & 
	!U2_ADDR_reg<6> & !U2_ADDR_reg<7> & !U2_ADDR_reg<1> & !U2_ADDR_reg<3> & 
	!U3/DCORIE<4>;	// (3 pt, 13 inp)
   U3/DCORIE<4>.CLK  =  !Mclk;	// GCK	(0 pt, 0 inp)

U3/DCORIE<6>.T := !MSPReset & U3/DCORIE<6>
	# !U2_ADDR_reg<2> & !WR & RD & !U2_ADDR_reg<0> & 
	!U2_ADDR_reg<4> & !U2_ADDR_reg<5> & !U2_ADDR_reg<6> & !AD<6>.PIN & 
	!U2_ADDR_reg<7> & !U2_ADDR_reg<1> & !U2_ADDR_reg<3> & U3/DCORIE<6>
	# !U2_ADDR_reg<2> & MSPReset & !WR & RD & 
	!U2_ADDR_reg<0> & !U2_ADDR_reg<4> & !U2_ADDR_reg<5> & !U2_ADDR_reg<6> & 
	AD<6>.PIN & !U2_ADDR_reg<7> & !U2_ADDR_reg<1> & !U2_ADDR_reg<3> & 
	!U3/DCORIE<6>;	// (3 pt, 13 inp)
   U3/DCORIE<6>.CLK  =  !Mclk;	// GCK	(0 pt, 0 inp)

U3/DCORIE<7>.T := !MSPReset & U3/DCORIE<7>
	# !U2_ADDR_reg<2> & !WR & RD & !U2_ADDR_reg<0> & 
	!U2_ADDR_reg<4> & !U2_ADDR_reg<5> & !U2_ADDR_reg<6> & !U2_ADDR_reg<7> & 
	!AD<7>.PIN & !U2_ADDR_reg<1> & !U2_ADDR_reg<3> & U3/DCORIE<7>
	# !U2_ADDR_reg<2> & MSPReset & !WR & RD & 
	!U2_ADDR_reg<0> & !U2_ADDR_reg<4> & !U2_ADDR_reg<5> & !U2_ADDR_reg<6> & 
	!U2_ADDR_reg<7> & AD<7>.PIN & !U2_ADDR_reg<1> & !U2_ADDR_reg<3> & 
	!U3/DCORIE<7>;	// (3 pt, 13 inp)
   U3/DCORIE<7>.CLK  =  !Mclk;	// GCK	(0 pt, 0 inp)

U4/DCORIFG__or0000_bdd0 = Latch033FLG & Home05FLG & Enc05FLG & 
	Latch133FLG & Home15FLG & Enc15FLG;	// (1 pt, 6 inp)


// Direct Input Register
U4/Flgreg<0> := Latch033FLG;	// (0 pt, 0 inp)
   U4/Flgreg<0>.CLK  =  !Mclk;	// GCK	(0 pt, 0 inp)
    U4/Flgreg<0>.CE = !NET2528 & !U4/DCORIFG__or0000_bdd0;	// (1 pt, 2 inp)


// Direct Input Register
U4/Flgreg<1> := Home05FLG;	// (0 pt, 0 inp)
   U4/Flgreg<1>.CLK  =  !Mclk;	// GCK	(0 pt, 0 inp)
    U4/Flgreg<1>.CE = !NET2528 & !U4/DCORIFG__or0000_bdd0;	// (1 pt, 2 inp)


// Direct Input Register
U4/Flgreg<3> := Enc05FLG;	// (0 pt, 0 inp)
   U4/Flgreg<3>.CLK  =  !Mclk;	// GCK	(0 pt, 0 inp)
    U4/Flgreg<3>.CE = !NET2528 & !U4/DCORIFG__or0000_bdd0;	// (1 pt, 2 inp)


// Direct Input Register
U4/Flgreg<4> := Latch133FLG;	// (0 pt, 0 inp)
   U4/Flgreg<4>.CLK  =  !Mclk;	// GCK	(0 pt, 0 inp)
    U4/Flgreg<4>.CE = !NET2528 & !U4/DCORIFG__or0000_bdd0;	// (1 pt, 2 inp)


// Direct Input Register
U4/Flgreg<5> := Home15FLG;	// (0 pt, 0 inp)
   U4/Flgreg<5>.CLK  =  !Mclk;	// GCK	(0 pt, 0 inp)
    U4/Flgreg<5>.CE = !NET2528 & !U4/DCORIFG__or0000_bdd0;	// (1 pt, 2 inp)

U4/Flgreg<6>.T := !NET2528 & !U4/DCORIFG__or0000_bdd0 & !U4/Flgreg<6>;	// (1 pt, 3 inp)
   U4/Flgreg<6>.CLK  =  !Mclk;	// GCK	(0 pt, 0 inp)


// Direct Input Register
U4/Flgreg<7> := Enc15FLG;	// (0 pt, 0 inp)
   U4/Flgreg<7>.CLK  =  !Mclk;	// GCK	(0 pt, 0 inp)
    U4/Flgreg<7>.CE = !NET2528 & !U4/DCORIFG__or0000_bdd0;	// (1 pt, 2 inp)

U5/FLS0fr := !N_PZ_1202 & U5/FLS0fr
	# !N_PZ_1202 & DIR0 & !FLS0 & U5/FLS0r;	// (2 pt, 5 inp)
   U5/FLS0fr.CLK  =  !Mclk;	// GCK	(0 pt, 0 inp)

U5/FLS0r := MSPReset & FLS0;	// (1 pt, 2 inp)
   U5/FLS0r.CLK  =  !Mclk;	// GCK	(0 pt, 0 inp)

U5/FLS1fr := !N_PZ_1202 & U5/FLS1fr
	# !N_PZ_1202 & DIR1 & !FLS1 & U5/FLS1r;	// (2 pt, 5 inp)
   U5/FLS1fr.CLK  =  !Mclk;	// GCK	(0 pt, 0 inp)

U5/FLS1r := MSPReset & FLS1;	// (1 pt, 2 inp)
   U5/FLS1r.CLK  =  !Mclk;	// GCK	(0 pt, 0 inp)

!U5/RLS0fr := N_PZ_1202
	# !U5/RLS0fr & !N_PZ_1313;	// (2 pt, 3 inp)
   U5/RLS0fr.CLK  =  !Mclk;	// GCK	(0 pt, 0 inp)

U5/RLS0r := MSPReset & RLS0;	// (1 pt, 2 inp)
   U5/RLS0r.CLK  =  !Mclk;	// GCK	(0 pt, 0 inp)

!U5/RLS1fr := N_PZ_1202
	# !U5/RLS1fr & !N_PZ_1314;	// (2 pt, 3 inp)
   U5/RLS1fr.CLK  =  !Mclk;	// GCK	(0 pt, 0 inp)

U5/RLS1r := MSPReset & RLS1;	// (1 pt, 2 inp)
   U5/RLS1r.CLK  =  !Mclk;	// GCK	(0 pt, 0 inp)

U9/MISCr<0>.T := !MSPReset & U9/MISCr<0>
	# U2_ADDR_reg<2> & !WR & RD & U2_ADDR_reg<0> & 
	!AD<0>.PIN & !U2_ADDR_reg<4> & !U2_ADDR_reg<5> & !U2_ADDR_reg<6> & 
	!U2_ADDR_reg<7> & U2_ADDR_reg<1> & U2_ADDR_reg<3> & U9/MISCr<0>
	# U2_ADDR_reg<2> & MSPReset & !WR & RD & 
	U2_ADDR_reg<0> & AD<0>.PIN & !U2_ADDR_reg<4> & !U2_ADDR_reg<5> & 
	!U2_ADDR_reg<6> & !U2_ADDR_reg<7> & U2_ADDR_reg<1> & U2_ADDR_reg<3> & 
	!U9/MISCr<0>;	// (3 pt, 13 inp)
   U9/MISCr<0>.CLK  =  !Mclk;	// GCK	(0 pt, 0 inp)
    U9/MISCr<0>.AR = MReset;	// URST	(1 pt, 1 inp)

U9/MISCr<1>.T := !MSPReset & U9/MISCr<1>
	# U2_ADDR_reg<2> & !WR & RD & U2_ADDR_reg<0> & 
	!U2_ADDR_reg<4> & !U2_ADDR_reg<5> & !U2_ADDR_reg<6> & !U2_ADDR_reg<7> & 
	U2_ADDR_reg<1> & !AD<1>.PIN & U2_ADDR_reg<3> & U9/MISCr<1>
	# U2_ADDR_reg<2> & MSPReset & !WR & RD & 
	U2_ADDR_reg<0> & !U2_ADDR_reg<4> & !U2_ADDR_reg<5> & !U2_ADDR_reg<6> & 
	!U2_ADDR_reg<7> & U2_ADDR_reg<1> & AD<1>.PIN & U2_ADDR_reg<3> & 
	!U9/MISCr<1>;	// (3 pt, 13 inp)
   U9/MISCr<1>.CLK  =  !Mclk;	// GCK	(0 pt, 0 inp)
    U9/MISCr<1>.AR = MReset;	// URST	(1 pt, 1 inp)

U9/MISCr<2>.T := !MSPReset & U9/MISCr<2>
	# U2_ADDR_reg<2> & !AD<2>.PIN & !WR & RD & 
	U2_ADDR_reg<0> & !U2_ADDR_reg<4> & !U2_ADDR_reg<5> & !U2_ADDR_reg<6> & 
	!U2_ADDR_reg<7> & U2_ADDR_reg<1> & U2_ADDR_reg<3> & U9/MISCr<2>
	# U2_ADDR_reg<2> & MSPReset & AD<2>.PIN & !WR & 
	RD & U2_ADDR_reg<0> & !U2_ADDR_reg<4> & !U2_ADDR_reg<5> & 
	!U2_ADDR_reg<6> & !U2_ADDR_reg<7> & U2_ADDR_reg<1> & U2_ADDR_reg<3> & 
	!U9/MISCr<2>;	// (3 pt, 13 inp)
   U9/MISCr<2>.CLK  =  !Mclk;	// GCK	(0 pt, 0 inp)
    U9/MISCr<2>.AR = MReset;	// URST	(1 pt, 1 inp)

U9/MISCr<3>.T := !MSPReset & U9/MISCr<3>
	# U2_ADDR_reg<2> & !WR & RD & U2_ADDR_reg<0> & 
	!U2_ADDR_reg<4> & !U2_ADDR_reg<5> & !U2_ADDR_reg<6> & !U2_ADDR_reg<7> & 
	U2_ADDR_reg<1> & U2_ADDR_reg<3> & !AD<3>.PIN & U9/MISCr<3>
	# U2_ADDR_reg<2> & MSPReset & !WR & RD & 
	U2_ADDR_reg<0> & !U2_ADDR_reg<4> & !U2_ADDR_reg<5> & !U2_ADDR_reg<6> & 
	!U2_ADDR_reg<7> & U2_ADDR_reg<1> & U2_ADDR_reg<3> & AD<3>.PIN & 
	!U9/MISCr<3>;	// (3 pt, 13 inp)
   U9/MISCr<3>.CLK  =  !Mclk;	// GCK	(0 pt, 0 inp)
    U9/MISCr<3>.AR = MReset;	// URST	(1 pt, 1 inp)

U9/MISCr<4>.T := !MSPReset & U9/MISCr<4>
	# U2_ADDR_reg<2> & !WR & RD & U2_ADDR_reg<0> & 
	!U2_ADDR_reg<4> & !AD<4>.PIN & !U2_ADDR_reg<5> & !U2_ADDR_reg<6> & 
	!U2_ADDR_reg<7> & U2_ADDR_reg<1> & U2_ADDR_reg<3> & U9/MISCr<4>
	# U2_ADDR_reg<2> & MSPReset & !WR & RD & 
	U2_ADDR_reg<0> & !U2_ADDR_reg<4> & AD<4>.PIN & !U2_ADDR_reg<5> & 
	!U2_ADDR_reg<6> & !U2_ADDR_reg<7> & U2_ADDR_reg<1> & U2_ADDR_reg<3> & 
	!U9/MISCr<4>;	// (3 pt, 13 inp)
   U9/MISCr<4>.CLK  =  !Mclk;	// GCK	(0 pt, 0 inp)
    U9/MISCr<4>.AR = MReset;	// URST	(1 pt, 1 inp)

outDATA<0>\$WA0.UIM = U1/U4/Latch1r<8> & !N_PZ_1216
	# !U2_ADDR_reg<2> & U2_ADDR_reg<0> & !U2_ADDR_reg<1> & 
	U2_ADDR_reg<3> & U2_Enable_AD & U1/U4/Latch0r<8>
	# !U2_ADDR_reg<2> & !U2_ADDR_reg<0> & U2_ADDR_reg<1> & 
	U2_ADDR_reg<3> & U2_Enable_AD & U1/U4/Latch1r<0>
	# !U2_ADDR_reg<2> & !U2_ADDR_reg<0> & !U2_ADDR_reg<1> & 
	U2_ADDR_reg<3> & U2_Enable_AD & U1/U4/Latch0r<0>;	// (4 pt, 10 inp)

outDATA<0>\$WA6.UIM = U1/U3/holdingreg1<8> & !N_PZ_1195
	# U2_ADDR_reg<2> & U2_ADDR_reg<0> & !U2_ADDR_reg<1> & 
	!U2_ADDR_reg<3> & U2_Enable_AD & U1/U3/holdingreg0<8>
	# U2_ADDR_reg<2> & !U2_ADDR_reg<0> & U2_ADDR_reg<1> & 
	!U2_ADDR_reg<3> & U2_Enable_AD & U1/U3/holdingreg1<0>
	# U2_ADDR_reg<2> & !U2_ADDR_reg<0> & !U2_ADDR_reg<1> & 
	!U2_ADDR_reg<3> & U2_Enable_AD & U1/U3/holdingreg0<0>;	// (4 pt, 10 inp)

outDATA<0>\$WA5.UIM = Latch033FLG & !NET2528
	# NET2528 & U4/Flgreg<0>;	// (2 pt, 3 inp)

outDATA<0>\$WA4.UIM = INTbus;	// (1 pt, 1 inp)

outDATA<0>\$WA3.UIM = I2CS<0>;	// (1 pt, 1 inp)

outDATA<0>\$WA2.UIM = !RLS0 & N_PZ_1029
	# !N_PZ_1029 & U5/RLS0fr;	// (2 pt, 3 inp)

outDATA<0>\$WA1.UIM = U11_U3_counterr<0>;	// (1 pt, 1 inp)

outDATA<1>\$WA2.UIM = N_PZ_1029 & !FLS0
	# !N_PZ_1029 & U5/FLS0fr;	// (2 pt, 3 inp)

outDATA<1>\$WA3.UIM = I2CS<1>;	// (1 pt, 1 inp)

outDATA<1>\$WA1.UIM = U11_U3_counterr<1>;	// (1 pt, 1 inp)

outDATA<1>\$WA5.UIM = NET2528
	$ U2_ADDR_reg<2> & !U2_ADDR_reg<0> & U2_ADDR_reg<1> & 
	U2_ADDR_reg<3> & U2_Enable_AD & NET2528 & !U4/Flgreg<1>
	# U2_ADDR_reg<2> & !U2_ADDR_reg<0> & U2_ADDR_reg<1> & 
	U2_ADDR_reg<3> & U2_Enable_AD & !NET2528 & Home05FLG;	// (3 pt, 8 inp)

outDATA<1>\$WA6.UIM = !N_PZ_1195 & U1/U3/holdingreg1<9>
	# U2_ADDR_reg<2> & U2_ADDR_reg<0> & !U2_ADDR_reg<1> & 
	!U2_ADDR_reg<3> & U2_Enable_AD & U1/U3/holdingreg0<9>
	# U2_ADDR_reg<2> & !U2_ADDR_reg<0> & U2_ADDR_reg<1> & 
	!U2_ADDR_reg<3> & U2_Enable_AD & U1/U3/holdingreg1<1>
	# U2_ADDR_reg<2> & !U2_ADDR_reg<0> & !U2_ADDR_reg<1> & 
	!U2_ADDR_reg<3> & U2_Enable_AD & U1/U3/holdingreg0<1>;	// (4 pt, 10 inp)

outDATA<1>\$WA0.UIM = !N_PZ_1216 & U1/U4/Latch1r<9>
	# !U2_ADDR_reg<2> & U2_ADDR_reg<0> & !U2_ADDR_reg<1> & 
	U2_ADDR_reg<3> & U2_Enable_AD & U1/U4/Latch0r<9>
	# !U2_ADDR_reg<2> & !U2_ADDR_reg<0> & U2_ADDR_reg<1> & 
	U2_ADDR_reg<3> & U2_Enable_AD & U1/U4/Latch1r<1>
	# !U2_ADDR_reg<2> & !U2_ADDR_reg<0> & !U2_ADDR_reg<1> & 
	U2_ADDR_reg<3> & U2_Enable_AD & U1/U4/Latch0r<1>;	// (4 pt, 10 inp)

outDATA<2>\$WA0.UIM = !N_PZ_1203 & U1/U4/Latch1r<10>
	# U2_ADDR_reg<1> & !N_PZ_1216 & U1/U4/Latch1r<10>
	# !U2_ADDR_reg<2> & U2_ADDR_reg<0> & !U2_ADDR_reg<1> & 
	U2_ADDR_reg<3> & U2_Enable_AD & U1/U4/Latch0r<10>
	# !U2_ADDR_reg<2> & !U2_ADDR_reg<0> & U2_ADDR_reg<1> & 
	U2_ADDR_reg<3> & U2_Enable_AD & U1/U4/Latch1r<2>
	# !U2_ADDR_reg<2> & !U2_ADDR_reg<0> & !U2_ADDR_reg<1> & 
	U2_ADDR_reg<3> & U2_Enable_AD & U1/U4/Latch0r<2>
	# !U2_ADDR_reg<2> & WR & !RD & U2_ADDR_reg<0> & 
	!U2_ADDR_reg<4> & !U2_ADDR_reg<5> & !U2_ADDR_reg<6> & !U2_ADDR_reg<7> & 
	!U2_ADDR_reg<1> & !U2_ADDR_reg<3> & NET2482;	// (6 pt, 18 inp)

outDATA<2>\$WA1.UIM = U11_U3_counterr<2>;	// (1 pt, 1 inp)

outDATA<2>\$WA2.UIM = N_PZ_1029 & Home0;	// (1 pt, 2 inp)

outDATA<2>\$WA3.UIM = I2CS<2>;	// (1 pt, 1 inp)

outDATA<2>\$WA5.UIM = !outDATA<6>\$WA5.UIM;	// (1 pt, 1 inp)

outDATA<2>\$WA6.UIM = !N_PZ_1195 & U1/U3/holdingreg1<10>
	# U2_ADDR_reg<2> & U2_ADDR_reg<0> & !U2_ADDR_reg<1> & 
	!U2_ADDR_reg<3> & U2_Enable_AD & U1/U3/holdingreg0<10>
	# U2_ADDR_reg<2> & !U2_ADDR_reg<0> & U2_ADDR_reg<1> & 
	!U2_ADDR_reg<3> & U2_Enable_AD & U1/U3/holdingreg1<2>
	# U2_ADDR_reg<2> & !U2_ADDR_reg<0> & !U2_ADDR_reg<1> & 
	!U2_ADDR_reg<3> & U2_Enable_AD & U1/U3/holdingreg0<2>;	// (4 pt, 10 inp)

outDATA<3>\$WA3.UIM = I2CS<3>;	// (1 pt, 1 inp)

outDATA<3>\$WA6.UIM = !N_PZ_1195 & U1/U3/holdingreg1<11>
	# U2_ADDR_reg<2> & U2_ADDR_reg<0> & !U2_ADDR_reg<1> & 
	!U2_ADDR_reg<3> & U2_Enable_AD & U1/U3/holdingreg0<11>
	# U2_ADDR_reg<2> & !U2_ADDR_reg<0> & U2_ADDR_reg<1> & 
	!U2_ADDR_reg<3> & U2_Enable_AD & U1/U3/holdingreg1<3>
	# U2_ADDR_reg<2> & !U2_ADDR_reg<0> & !U2_ADDR_reg<1> & 
	!U2_ADDR_reg<3> & U2_Enable_AD & U1/U3/holdingreg0<3>;	// (4 pt, 10 inp)

outDATA<3>\$WA0.UIM = !N_PZ_1203 & U1/U4/Latch1r<11>
	# U2_ADDR_reg<1> & !N_PZ_1216 & U1/U4/Latch1r<11>
	# !U2_ADDR_reg<2> & U2_ADDR_reg<0> & !U2_ADDR_reg<1> & 
	U2_ADDR_reg<3> & U2_Enable_AD & U1/U4/Latch0r<11>
	# !U2_ADDR_reg<2> & !U2_ADDR_reg<0> & U2_ADDR_reg<1> & 
	U2_ADDR_reg<3> & U2_Enable_AD & U1/U4/Latch1r<3>
	# !U2_ADDR_reg<2> & !U2_ADDR_reg<0> & !U2_ADDR_reg<1> & 
	U2_ADDR_reg<3> & U2_Enable_AD & U1/U4/Latch0r<3>
	# !U2_ADDR_reg<2> & WR & !RD & U2_ADDR_reg<0> & 
	!U2_ADDR_reg<4> & !U2_ADDR_reg<5> & !U2_ADDR_reg<6> & !U2_ADDR_reg<7> & 
	!U2_ADDR_reg<1> & !U2_ADDR_reg<3> & NET2493;	// (6 pt, 18 inp)

outDATA<3>\$WA1.UIM = U11_U3_counterr<3>;	// (1 pt, 1 inp)

outDATA<3>\$WA2.UIM = NET3248;	// (1 pt, 1 inp)

outDATA<3>\$WA5.UIM = NET2528 & U4/Flgreg<3>
	# !NET2528 & Enc05FLG;	// (2 pt, 3 inp)

outDATA<4>\$WA6.UIM = !N_PZ_1195 & U1/U3/holdingreg1<12>
	# U2_ADDR_reg<2> & U2_ADDR_reg<0> & !U2_ADDR_reg<1> & 
	!U2_ADDR_reg<3> & U2_Enable_AD & U1/U3/holdingreg0<12>
	# U2_ADDR_reg<2> & !U2_ADDR_reg<0> & U2_ADDR_reg<1> & 
	!U2_ADDR_reg<3> & U2_Enable_AD & U1/U3/holdingreg1<4>
	# U2_ADDR_reg<2> & !U2_ADDR_reg<0> & !U2_ADDR_reg<1> & 
	!U2_ADDR_reg<3> & U2_Enable_AD & U1/U3/holdingreg0<4>;	// (4 pt, 10 inp)

outDATA<4>\$WA4.UIM = NET2575;	// (1 pt, 1 inp)

outDATA<4>\$WA5.UIM = NET2528 & U4/Flgreg<4>
	# !NET2528 & Latch133FLG;	// (2 pt, 3 inp)

outDATA<4>\$WA2.UIM = N_PZ_1029 & !RLS1
	# !N_PZ_1029 & U5/RLS1fr;	// (2 pt, 3 inp)

outDATA<4>\$WA1.UIM = U11_U3_counterr<4>;	// (1 pt, 1 inp)

outDATA<4>\$WA0.UIM = !N_PZ_1216 & U1/U4/Latch1r<12>
	# !U2_ADDR_reg<2> & U2_ADDR_reg<0> & !U2_ADDR_reg<1> & 
	U2_ADDR_reg<3> & U2_Enable_AD & U1/U4/Latch0r<12>
	# !U2_ADDR_reg<2> & !U2_ADDR_reg<0> & U2_ADDR_reg<1> & 
	U2_ADDR_reg<3> & U2_Enable_AD & U1/U4/Latch1r<4>
	# !U2_ADDR_reg<2> & !U2_ADDR_reg<0> & !U2_ADDR_reg<1> & 
	U2_ADDR_reg<3> & U2_Enable_AD & U1/U4/Latch0r<4>;	// (4 pt, 10 inp)

outDATA<4>\$WA3.UIM = I2CS<4>;	// (1 pt, 1 inp)

outDATA<5>\$WA1.UIM = U11_U3_counterr<5>;	// (1 pt, 1 inp)

outDATA<5>\$WA5.UIM = NET2528 & U4/Flgreg<5>
	# !NET2528 & Home15FLG;	// (2 pt, 3 inp)

outDATA<5>\$WA3.UIM = I2CS<5>;	// (1 pt, 1 inp)

outDATA<5>\$WA2.UIM = N_PZ_1029 & !FLS1
	# !N_PZ_1029 & U5/FLS1fr;	// (2 pt, 3 inp)

outDATA<5>\$WA6.UIM = !N_PZ_1195 & U1/U3/holdingreg1<13>
	# U2_ADDR_reg<2> & U2_ADDR_reg<0> & !U2_ADDR_reg<1> & 
	!U2_ADDR_reg<3> & U2_Enable_AD & U1/U3/holdingreg0<13>
	# U2_ADDR_reg<2> & !U2_ADDR_reg<0> & U2_ADDR_reg<1> & 
	!U2_ADDR_reg<3> & U2_Enable_AD & U1/U3/holdingreg1<5>
	# U2_ADDR_reg<2> & !U2_ADDR_reg<0> & !U2_ADDR_reg<1> & 
	!U2_ADDR_reg<3> & U2_Enable_AD & U1/U3/holdingreg0<5>;	// (4 pt, 10 inp)

outDATA<5>\$WA0.UIM = !N_PZ_1203 & U1/U4/Latch1r<13>
	# U2_ADDR_reg<1> & !N_PZ_1216 & U1/U4/Latch1r<13>
	# !U2_ADDR_reg<2> & U2_ADDR_reg<0> & !U2_ADDR_reg<1> & 
	U2_ADDR_reg<3> & U2_Enable_AD & U1/U4/Latch0r<13>
	# !U2_ADDR_reg<2> & !U2_ADDR_reg<0> & U2_ADDR_reg<1> & 
	U2_ADDR_reg<3> & U2_Enable_AD & U1/U4/Latch1r<5>
	# !U2_ADDR_reg<2> & !U2_ADDR_reg<0> & !U2_ADDR_reg<1> & 
	U2_ADDR_reg<3> & U2_Enable_AD & U1/U4/Latch0r<5>
	# !U2_ADDR_reg<2> & WR & !RD & U2_ADDR_reg<0> & 
	!U2_ADDR_reg<4> & !U2_ADDR_reg<5> & !U2_ADDR_reg<6> & !U2_ADDR_reg<7> & 
	!U2_ADDR_reg<1> & !U2_ADDR_reg<3> & TP26;	// (6 pt, 18 inp)

outDATA<6>\$WA6.UIM = !N_PZ_1195 & U1/U3/holdingreg1<14>
	# U2_ADDR_reg<2> & U2_ADDR_reg<0> & !U2_ADDR_reg<1> & 
	!U2_ADDR_reg<3> & U2_Enable_AD & U1/U3/holdingreg0<14>
	# U2_ADDR_reg<2> & !U2_ADDR_reg<0> & U2_ADDR_reg<1> & 
	!U2_ADDR_reg<3> & U2_Enable_AD & U1/U3/holdingreg1<6>
	# U2_ADDR_reg<2> & !U2_ADDR_reg<0> & !U2_ADDR_reg<1> & 
	!U2_ADDR_reg<3> & U2_Enable_AD & U1/U3/holdingreg0<6>;	// (4 pt, 10 inp)

outDATA<6>\$WA5.UIM = NET2528 & !U4/Flgreg<6>;	// (1 pt, 2 inp)

outDATA<6>\$WA2.UIM = N_PZ_1029 & Home1;	// (1 pt, 2 inp)

outDATA<6>\$WA3.UIM = GP_Motor0_0;	// (1 pt, 1 inp)

outDATA<6>\$WA1.UIM = Gnd;	// (0 pt, 0 inp)

outDATA<6>\$WA0.UIM = !N_PZ_1203 & U1/U4/Latch1r<14>
	# U2_ADDR_reg<1> & !N_PZ_1216 & U1/U4/Latch1r<14>
	# !U2_ADDR_reg<2> & U2_ADDR_reg<0> & !U2_ADDR_reg<1> & 
	U2_ADDR_reg<3> & U2_Enable_AD & U1/U4/Latch0r<14>
	# !U2_ADDR_reg<2> & !U2_ADDR_reg<0> & U2_ADDR_reg<1> & 
	U2_ADDR_reg<3> & U2_Enable_AD & U1/U4/Latch1r<6>
	# !U2_ADDR_reg<2> & !U2_ADDR_reg<0> & !U2_ADDR_reg<1> & 
	U2_ADDR_reg<3> & U2_Enable_AD & U1/U4/Latch0r<6>
	# !U2_ADDR_reg<2> & WR & !RD & U2_ADDR_reg<0> & 
	!U2_ADDR_reg<4> & !U2_ADDR_reg<5> & !U2_ADDR_reg<6> & !U2_ADDR_reg<7> & 
	!U2_ADDR_reg<1> & !U2_ADDR_reg<3> & NET2512;	// (6 pt, 18 inp)

outDATA<7>\$WA1.UIM = Gnd;	// (0 pt, 0 inp)

outDATA<7>\$WA2.UIM = NET3253;	// (1 pt, 1 inp)

outDATA<7>\$WA3.UIM = GP_Motor1_0;	// (1 pt, 1 inp)

outDATA<7>\$WA6.UIM = !N_PZ_1195 & U1/U3/holdingreg1<15>
	# U2_ADDR_reg<2> & U2_ADDR_reg<0> & !U2_ADDR_reg<1> & 
	!U2_ADDR_reg<3> & U2_Enable_AD & U1/U3/holdingreg0<15>
	# U2_ADDR_reg<2> & !U2_ADDR_reg<0> & U2_ADDR_reg<1> & 
	!U2_ADDR_reg<3> & U2_Enable_AD & U1/U3/holdingreg1<7>
	# U2_ADDR_reg<2> & !U2_ADDR_reg<0> & !U2_ADDR_reg<1> & 
	!U2_ADDR_reg<3> & U2_Enable_AD & U1/U3/holdingreg0<7>;	// (4 pt, 10 inp)

outDATA<7>\$WA5.UIM = NET2528 & U4/Flgreg<7>
	# !NET2528 & Enc15FLG;	// (2 pt, 3 inp)

outDATA<7>\$WA0.UIM = !N_PZ_1216 & U1/U4/Latch1r<15>
	# !U2_ADDR_reg<2> & U2_ADDR_reg<0> & !U2_ADDR_reg<1> & 
	U2_ADDR_reg<3> & U2_Enable_AD & U1/U4/Latch0r<15>
	# !U2_ADDR_reg<2> & !U2_ADDR_reg<0> & U2_ADDR_reg<1> & 
	U2_ADDR_reg<3> & U2_Enable_AD & U1/U4/Latch1r<7>
	# !U2_ADDR_reg<2> & !U2_ADDR_reg<0> & !U2_ADDR_reg<1> & 
	U2_ADDR_reg<3> & U2_Enable_AD & U1/U4/Latch0r<7>;	// (4 pt, 10 inp)

outDATA<7>\$WA4.UIM = TP12;	// (1 pt, 1 inp)

Control Term Legend:
Clock         - GCK   - Global Clock
                UCLK  - Universal Control Term Clock
                LCLK  - Local Control Term Clock
                PTCLK - Product Term Clock
Preset        - UPST  - Universal Control Term Preset
                LPST  - Local Control Term Preset
                PTPST - Product Term Preset
Reset         - URST  - Universal Control Term Reset
                LRST  - Local Control Term Reset
                PTRST - Product Term Reset
Output Enable - UOE   - Universal Control Term Output Enable
                LOE   - Local Control Term Output Enable
                PTOE  - Product Term Output Enable

Legend:  <signame>.COMB = combinational node mapped to the same physical macrocell
                          as the FastInput "signal" (not logically related)
******************************  Device Pin Out *****************************

Device : XCR3384XL-7-TQ144


Pin Signal                         Pin Signal                        
No. Name                           No. Name                          
  1 PROHIBITED                       73 VCC                           
  2 PROHIBITED                       74 LED1                          
  3 GND                              75 LED2                          
  4 PROHIBITED                       76 VCC                           
  5 PROHIBITED                       77 LED3                          
  6 GPIO8                            78 LED4                          
  7 GPIO9                            79 LED5                          
  8 GPIO10                           80 MTRpwrn                       
  9 PROHIBITED                       81 PAH1                          
 10 INTbus                           82 PAL1                          
 11 MTRpwr                           83 PBH1                          
 12 MReset                           84 PBL1                          
 13 GND                              85 GND                           
 14 TP12                             86 TCK                           
 15 PROHIBITED                       87 PAH0                          
 16 PROHIBITED                       88 PAL0                          
 17 GND                              89 PBH0                          
 18 LightSense                       90 PBL0                          
 19 I2CS<5>                          91 TP21                          
 20 I2CS<4>                          92 Brake1                        
 21 I2CS<3>                          93 DIR1                          
 22 TMS                              94 Brake0                        
 23 I2CS<2>                          95 VCC                           
 24 VCC                              96 DIR0                          
 25 I2CS<1>                          97 PROHIBITED                    
 26 I2CS<0>                          98 PROHIBITED                    
 27 Enc15ctrl                        99 PWM5                          
 28 Enc15FLG                        100 PWM4                          
 29 Enc05FLG                        101 PWM3                          
 30 Enc05ctrl                       102 PWM2                          
 31 PROHIBITED                      103 PWM1                          
 32 PROHIBITED                      104 PROHIBITED                    
 33 PE                              105 GND                           
 34 TP26                            106 MSPReset                      
 35 WPU                             107 RD                            
 36 Latch033ctrl                    108 NC                            
 37 Latch033FLG                     109 NC                            
 38 Latch133ctrl                    110 WR                            
 39 Latch133FLG                     111 AS                            
 40 Home15ctrl                      112 INT                           
 41 Home15FLG                       113 PROHIBITED                    
 42 Home05FLG                       114 SCL                           
 43 Home05ctrl                      115 VCC                           
 44 FLS1                            116 PROHIBITED                    
 45 RLS1                            117 PROHIBITED                    
 46 PROHIBITED                      118 PROHIBITED                    
 47 Home1                           119 SCLinc                        
 48 PhaseA_Encoder1                 120 SCLreset                      
 49 PROHIBITED                      121 TDO                           
 50 VCC                             122 AD<7>                         
 51 VCC                             123 VCC                           
 52 GND                             124 GND                           
 53 PhaseB_Encoder1                 125 PROHIBITED                    
 54 GP_Motor1_0                     126 PROHIBITED                    
 55 PROHIBITED                      127 Mclk                          
 56 GP_Motor1_1                     128 PROHIBITED                    
 57 GND                             129 GND                           
 58 VCC                             130 VCC                           
 59 GND                             131 TDI                           
 60 PROHIBITED                      132 AD<6>                         
 61 FLS0                            133 AD<5>                         
 62 RLS0                            134 AD<4>                         
 63 PROHIBITED                      135 GND                           
 64 GND                             136 AD<3>                         
 65 Home0                           137 AD<2>                         
 66 PhaseA_Encoder0                 138 AD<1>                         
 67 PROHIBITED                      139 AD<0>                         
 68 PhaseB_Encoder0                 140 PresEn                        
 69 GP_Motor0_0                     141 TmpEn                         
 70 PROHIBITED                      142 TmpSlct                       
 71 GP_Motor0_1                     143 PresSlct                      
 72 PROHIBITED                      144 VCC                           


Legend :  NC  = Not Connected, unbonded pin
          PE  = Port Enable pin
         WPU  = Unused with Internal Weak Pull Up
         TIE  = Unused I/O floating -- must tie to VCC, GND or other signal
         VCC  = Dedicated Power Pin
         GND  = Dedicated Ground Pin
         TDI  = Test Data In, JTAG pin
         TDO  = Test Data Out, JTAG pin
         TCK  = Test Clock, JTAG pin
         TMS  = Test Mode Select, JTAG pin
  PROHIBITED  = User reserved pin
****************************  Compiler Options  ****************************

Following is a list of all global compiler options used by the fitter run.

Device(s) Specified                         : XCR3384XL-7-TQ144
Optimization Method                         : DENSITY
Multi-Level Logic Optimization              : ON
Ignore Timing Specifications                : OFF
Default Register Power Up Value             : LOW
Keep User Location Constraints              : ON
What-You-See-Is-What-You-Get                : OFF
Exhaustive Fitting                          : OFF
Keep Unused Inputs                          : OFF
Slew Rate                                   : FAST
Set Unused I/O Pin Termination              : PULLUP
Set Input-Only Termination                  : FLOAT
Set Universal Control Term Optimization     : OFF
Enable Foldback NANDs                       : OFF
Reserve ISP Pins                            : ON
Enable Input Registers                      : ON
Function Block Fan-in Limit                 : 38
Input Limit                                 : 32
Pterm Limit                                 : 28
