//--------------------------------------------------------------------------------------------------
//
// Title       : NegSCL
// Design      : I2Cfix
// Author      : mbari###
// Company     : MBARI
//
//-------------------------------------------------------------------------------------------------
//
// File        : C:\Projects\genosensor\2g\CPLDs\Core\I2Cfix\I2Cfix\src\NegSCL.v
// Generated   : Fri Feb 20 12:08:45 2004
// From        : interface description file
// By          : Itf2Vhdl ver. 1.20
//
//-------------------------------------------------------------------------------------------------
//
// Description : 
//
//-------------------------------------------------------------------------------------------------
`timescale 1ps / 1ps

//{{ Section below this comment is automatically maintained
//   and may be overwritten
//{module {NegSCL}}
module NegSCL ( NSCL ,SCL ,MCLK );

input SCL ;
wire SCL ;
input MCLK ;
wire MCLK ;

output NSCL ;
wire NSCL ;

//}} End of automatically maintained section

// -- Enter your statements here -- //	   

reg SCL_last;
reg NSCLr;

assign NSCL = NSCLr;

always @ (negedge MCLK)
	begin
		SCL_last <= SCL;
		if (!SCL  & SCL_last) NSCLr <= 1'b1;
		else NSCLr <= 1'b0;
	end

endmodule