//--------------------------------------------------------------------------------------------------
//
// Title       : PWRreg
// Design      : U21
// Author      : mbari###
// Company     : MBARI
//
//-------------------------------------------------------------------------------------------------
//
// File        : c:\Projects\genosensor\2g\CPLDs\Core\U21\src\PWRreg.v
// Generated   : Thu Mar  4 06:58:03 2004
// From        : interface description file
// By          : Itf2Vhdl ver. 1.20
//
//-------------------------------------------------------------------------------------------------
//
// Description : 
//
//-------------------------------------------------------------------------------------------------
`timescale 1ps / 1ps

//{{ Section below this comment is automatically maintained
//   and may be overwritten
//{module {PWRreg}}
module PWRreg ( Hme05ctl ,Hme15ctl ,Reset ,PWRint ,Enc033flg ,Enc133flg ,Mclk ,Hme033flg ,DCORENCPWRr ,Hme133flg ,DCORENCPWRw ,Enc033ctl ,Enc133ctl ,DCORIFGr ,inDATA ,outDATA ,Hme033ctl ,Hme133ctl ,Enc05flg ,Enc15flg ,DCORIFGw ,Hme05flg ,Hme15flg ,Enc05ctl ,Enc15ctl );

input DCORIFGr ;
wire DCORIFGr ;
input [7:0] inDATA ;
wire [7:0] inDATA ;
input Reset ;
wire Reset ;
input Enc05flg ;
wire Enc05flg ;
input DCORIFGw ;
wire DCORIFGw ;
input Enc033flg ;
wire Enc033flg ;
input Enc15flg ;
wire Enc15flg ;
input Enc133flg ;
wire Enc133flg ;
input Mclk ;
wire Mclk ;
input Hme05flg ;
wire Hme05flg ;
input Hme15flg ;
wire Hme15flg ;
input Hme033flg ;
wire Hme033flg ;
input DCORENCPWRr ;
wire DCORENCPWRr ;
input Hme133flg ;
wire Hme133flg ;
input DCORENCPWRw ;
wire DCORENCPWRw ;

output Enc133ctl ;
wire Enc133ctl ;
output [7:0] outDATA ;
wire [7:0] outDATA ;
output Hme05ctl ;
wire Hme05ctl ;
output Hme15ctl ;
wire Hme15ctl ;
output Hme033ctl ;
wire Hme033ctl ;
output PWRint ;
wire PWRint ;
output Hme133ctl ;
wire Hme133ctl ;
output Enc05ctl ;
wire Enc05ctl ;
output Enc15ctl ;
wire Enc15ctl ;
output Enc033ctl ;
wire Enc033ctl ;

//}} End of automatically maintained section

// -- Enter your statements here -- //
reg [7:0] ctrlr;
reg [7:0] Flgreg;
reg DCORIFG;								  
wire orFLGs;

assign outDATA = (DCORENCPWRr) ? (DCORIFG) ? Flgreg : ({Enc15flg, 1'b1, Hme15flg, Hme133flg, Enc05flg, 1'b1, Hme05flg, Hme033flg}) :
					(DCORIFGr) ? ({6'bz,DCORIFG, 1'bz}) : 8'bz;
assign PWRint = DCORIFG;
assign orFLGs =  (!Enc15flg | !Hme15flg | !Hme133flg | !Enc05flg |!Hme05flg | !Hme033flg);

assign Enc15ctl = ~(ctrlr[7]); // & ~ctrlr[6]);
//assign Enc133ctl = ~(ctrlr[6] & ctrlr[7]);
assign Hme15ctl = ~(ctrlr[5]);// & ~ctrlr[4]);
assign Hme133ctl = ~(ctrlr[4]);// & ~ctrlr[5]);
assign Enc05ctl = ~(ctrlr[3]); // & ~ctrlr[2]);
//assign Enc033ctl = ~(ctrlr[2] & ~ctrlr[3]);
assign Hme05ctl = ~(ctrlr[1]); //& ~ctrlr[0]);
assign Hme033ctl = ~(ctrlr[0]); //& ~ctrlr[1]);

always @ (negedge Mclk)
	begin
		if (Reset) DCORIFG <= 1'b0;
		else if (DCORIFGw) DCORIFG <= DCORIFG & ~inDATA[1]; 
		else if (orFLGs) DCORIFG <= 1'b1;
		else DCORIFG <= DCORIFG;
	
		if (orFLGs & !DCORIFG) Flgreg <=  {Enc15flg, 1'b1, Hme15flg, Hme133flg, Enc05flg, 1'b1, Hme05flg, Hme033flg};
			
	end							
	
always @ (negedge Mclk or posedge Reset)//added to make reset async to shut off when reset high
	begin
		if (Reset) ctrlr <= 4'b0;
		else if (DCORENCPWRw) ctrlr <= inDATA;
	end	
endmodule