SCHM0102 HEADER { FREEID 10505 VARIABLES { #BLOCKTABLE_FILE="#table.bde" #BLOCKTABLE_INCLUDED="1" #LANGUAGE="VERILOG" #MODULE="U21" AUTHOR="mbari###" COMPANY="MBARI" CREATIONDATE="3/3/2004" TITLE="Dwarf Core CPLD U21" } SYMBOL "#default" "I2CAddress" "I2CAddress" { HEADER { VARIABLES { #DESCRIPTION="" #FUB="1" #LANGUAGE="VERILOG" #MODIFIED="1078432023" } } PAGE "" { PAGEHEADER { RECT (100,0,280,300) FREEID 47 } BODY { RECT 1, -1, 0 { VARIABLES { #OUTLINE_FILLING="1" } AREA (100,0,280,300) } TEXT 14, 0, 0 { TEXT "$#NAME" RECT (148,201,172,286) ALIGN 9 MARGINS (1,1) PARENT 13 ORIENTATION 8 } TEXT 19, 0, 0 { TEXT "$#NAME" RECT (208,13,232,132) ALIGN 1 MARGINS (1,1) PARENT 18 ORIENTATION 6 } TEXT 37, 0, 0 { TEXT "$#NAME" RECT (148,13,172,153) ALIGN 1 MARGINS (1,1) PARENT 36 ORIENTATION 6 } TEXT 40, 0, 0 { TEXT "$#NAME" RECT (208,209,232,286) ALIGN 9 MARGINS (1,1) PARENT 39 ORIENTATION 8 } TEXT 45, 0, 0 { TEXT "$#NAME" RECT (228,209,252,286) ALIGN 9 MARGINS (1,1) PARENT 44 ORIENTATION 8 } PIN 13, 0, 0 { COORD (160,300) VARIABLES { #DIRECTION="IN" #LABEL="Bus In" #MODIFIED="1" #NAME="I2CS(5:0)" #NUMBER="1" #SIDE="bottom" #VERILOG_DELAY="" #VERILOG_TYPE="wire" } LINE 1, 0, 0 { POINTS ( (-10,0), (10,0), (0,-10), (-10,0) ) FILL (0,(0,0,0),0) } } PIN 18, 0, 0 { COORD (220,0) VARIABLES { #DIRECTION="OUT" #LABEL="Bus Out" #MODIFIED="1" #NAME="outDATA(7:0)" #NUMBER="2" #SIDE="top" #VERILOG_DELAY="" #VERILOG_TYPE="wire" } LINE 1, 0, 0 { POINTS ( (0,0), (10,10), (-10,10), (0,0) ) FILL (0,(0,0,0),0) } } PIN 36, 0, 0 { COORD (160,0) VARIABLES { #DIRECTION="IN" #LABEL="In" #MODIFIED="1" #NAME="DCORCONFIGr" #NUMBER="3" #SIDE="top" #VERILOG_DELAY="" #VERILOG_TYPE="wire" } LINE 1, 0, 0 { POINTS ( (10,0), (-10,0), (0,10), (10,0) ) FILL (0,(0,0,0),0) } } PIN 39, 0, 0 { COORD (220,300) VARIABLES { #DIRECTION="IN" #LABEL="In" #MODIFIED="1" #NAME="MotorIn0" #NUMBER="4" #SIDE="bottom" #VERILOG_DELAY="" #VERILOG_TYPE="wire" } LINE 1, 0, 0 { POINTS ( (-10,0), (10,0), (0,-10), (-10,0) ) FILL (0,(0,0,0),0) } } PIN 44, 0, 0 { COORD (240,300) VARIABLES { #DIRECTION="IN" #LABEL="In" #MODIFIED="1" #NAME="MotorIn1" #NUMBER="5" #SIDE="bottom" #VERILOG_DELAY="" #VERILOG_TYPE="wire" } LINE 1, 0, 0 { POINTS ( (-10,0), (10,0), (0,-10), (-10,0) ) FILL (0,(0,0,0),0) } } } } } SYMBOL "#default" "I2Cfix" "I2Cfix" { HEADER { VARIABLES { #DESCRIPTION="" #FUB="1" #LANGUAGE="VERILOG" #MODIFIED="1078857388" } } PAGE "" { PAGEHEADER { RECT (80,0,280,240) FREEID 30 } BODY { RECT 1, -1, 0 { VARIABLES { #OUTLINE_FILLING="1" } AREA (80,0,279,239) } TEXT 3, 0, 0 { TEXT "$#NAME" RECT (230,197,254,225) ALIGN 9 MARGINS (1,1) PARENT 2 ORIENTATION 8 } TEXT 5, 0, 0 { TEXT "$#NAME" RECT (95,110,135,134) ALIGN 4 MARGINS (1,1) PARENT 4 } TEXT 7, 0, 0 { TEXT "$#NAME" RECT (190,142,214,225) ALIGN 9 MARGINS (1,1) PARENT 6 ORIENTATION 8 } TEXT 11, 0, 0 { TEXT "$#NAME" RECT (150,175,174,215) ALIGN 9 MARGINS (1,1) PARENT 10 ORIENTATION 7 } TEXT 16, 0, 0 { TEXT "$#NAME" RECT (228,13,252,72) ALIGN 1 MARGINS (1,1) PARENT 15 ORIENTATION 6 } TEXT 24, 0, 0 { TEXT "$#NAME" RECT (146,15,170,150) ALIGN 1 MARGINS (1,1) PARENT 23 ORIENTATION 5 } TEXT 26, 0, 0 { TEXT "$#NAME" RECT (186,15,210,134) ALIGN 1 MARGINS (1,1) PARENT 25 ORIENTATION 6 } TEXT 28, 0, 0 { TEXT "$#NAME" RECT (110,128,134,225) ALIGN 9 MARGINS (1,1) PARENT 27 ORIENTATION 7 } PIN 2, 0, 0 { COORD (240,240) VARIABLES { #DIRECTION="IN" #LENGTH="0" #MODIFIED="1" #NAME="Inc" #NUMBER="1" #SIDE="bottom" } LINE 2, 0, 0 { POINTS ( (-10,0), (10,0), (0,-10), (-10,0) ) } } PIN 4, 0, 0 { COORD (80,120) VARIABLES { #DIRECTION="IN" #LENGTH="0" #MODIFIED="1" #NAME="Mclk" #NUMBER="2" #SIDE="left" #VERILOG_DELAY="" } LINE 2, 0, 0 { POINTS ( (0,-10), (0,10), (10,0), (0,-10) ) } } PIN 6, 0, 0 { COORD (200,240) VARIABLES { #DIRECTION="IN" #LENGTH="0" #MODIFIED="1" #NAME="SCLreset" #NUMBER="3" #SIDE="bottom" #VERILOG_DELAY="" } LINE 2, 0, 0 { POINTS ( (-10,0), (10,0), (0,-10), (-10,0) ) } } PIN 10, 0, 0 { COORD (160,240) VARIABLES { #DIRECTION="INOUT" #LABEL="InOut" #LENGTH="0" #MODIFIED="1" #NAME="SCL" #NUMBER="4" #SIDE="bottom" #VERILOG_DELAY="" } LINE 2, 0, 0 { POINTS ( (0,0), (-10,-10), (0,-20), (10,-10), (0,0) ) } } PIN 15, 0, 0 { COORD (240,0) VARIABLES { #DIRECTION="OUT" #LABEL="Out" #MODIFIED="1" #NAME="SCLint" #NUMBER="6" #SIDE="top" #VERILOG_DELAY="" } LINE 2, 0, 0 { POINTS ( (0,0), (10,10), (-10,10), (0,0) ) } } PIN 23, 0, 0 { COORD (160,0) VARIABLES { #DIRECTION="IN" #LENGTH="0" #MODIFIED="1" #NAME="DCORI2CCNTr" #NUMBER="0" #SIDE="top" } LINE 2, 0, 0 { POINTS ( (10,0), (-10,0), (0,10), (10,0) ) } } PIN 25, 0, 0 { COORD (200,0) VARIABLES { #DIRECTION="OUT" #DOWNTO="1" #LENGTH="0" #MODIFIED="1" #NAME="outDATA(7:0)" #NUMBER="0" #SIDE="top" } LINE 2, 0, 0 { POINTS ( (0,0), (10,10), (-10,10), (0,0) ) } } PIN 27, 0, 0 { COORD (120,240) VARIABLES { #DIRECTION="OUT" #LENGTH="0" #MODIFIED="1" #NAME="SCLenable" #NUMBER="0" #SIDE="bottom" #VERILOG_TYPE="wire" } LINE 2, 0, 0 { POINTS ( (0,0), (10,-10), (-10,-10), (0,0) ) } } } } } SYMBOL "#default" "Interface" "Interface" { HEADER { VARIABLES { #DESCRIPTION="" #FUB="1" #LANGUAGE="VERILOG" #MODIFIED="1079725196" } } PAGE "" { PAGEHEADER { RECT (-160,140,100,360) FREEID 50 } BODY { RECT 1, -1, 0 { VARIABLES { #OUTLINE_FILLING="1" } AREA (-160,140,99,360) } TEXT 4, 0, 0 { TEXT "$#NAME" RECT (-92,269,-68,337) ALIGN 9 MARGINS (1,1) PARENT 3 ORIENTATION 7 } TEXT 9, 0, 0 { TEXT "$#NAME" RECT (28,319,52,347) ALIGN 9 MARGINS (1,1) PARENT 8 ORIENTATION 7 } TEXT 14, 0, 0 { TEXT "$#NAME" RECT (-12,317,12,347) ALIGN 9 MARGINS (1,1) PARENT 13 ORIENTATION 7 } TEXT 19, 0, 0 { TEXT "$#NAME" RECT (-52,312,-28,347) ALIGN 9 MARGINS (1,1) PARENT 18 ORIENTATION 7 } TEXT 29, 0, 0 { TEXT "$#NAME" RECT (-112,154,-88,250) ALIGN 1 MARGINS (1,1) PARENT 28 ORIENTATION 5 } TEXT 34, 0, 0 { TEXT "$#NAME" RECT (-12,164,12,271) ALIGN 1 MARGINS (1,1) PARENT 33 ORIENTATION 5 } TEXT 37, 0, 0 { TEXT "$#NAME" RECT (-146,248,-106,272) ALIGN 4 MARGINS (1,1) PARENT 36 } TEXT 42, 0, 0 { TEXT "$#NAME" RECT (-146,268,-93,292) ALIGN 4 MARGINS (1,1) PARENT 41 } TEXT 45, 0, 0 { TEXT "$#NAME" RECT (-52,154,-28,273) ALIGN 1 MARGINS (1,1) PARENT 44 ORIENTATION 5 } TEXT 48, 0, 0 { TEXT "$#NAME" RECT (28,154,52,243) ALIGN 1 MARGINS (1,1) PARENT 47 ORIENTATION 5 } PIN 3, 0, 0 { COORD (-80,360) VARIABLES { #DIRECTION="INOUT" #LABEL="Bus InOut" #MODIFIED="1" #NAME="AD(7:0)" #NUMBER="1" #SIDE="bottom" #VERILOG_TYPE="wire" } LINE 1, 0, 0 { POINTS ( (0,0), (-10,-10), (0,-20), (10,-10), (0,0) ) FILL (0,(0,0,0),0) } } PIN 8, 0, 0 { COORD (40,360) VARIABLES { #DIRECTION="IN" #LABEL="In" #MODIFIED="1" #NAME="AS" #NUMBER="2" #SIDE="bottom" #VERILOG_TYPE="wire" } LINE 1, 0, 0 { POINTS ( (-10,0), (10,0), (0,-10), (-10,0) ) FILL (0,(0,0,0),0) } } PIN 13, 0, 0 { COORD (0,360) VARIABLES { #DIRECTION="IN" #LABEL="In" #MODIFIED="1" #NAME="RD" #NUMBER="3" #SIDE="bottom" #VERILOG_TYPE="wire" } LINE 1, 0, 0 { POINTS ( (-10,0), (10,0), (0,-10), (-10,0) ) FILL (0,(0,0,0),0) } } PIN 18, 0, 0 { COORD (-40,360) VARIABLES { #DIRECTION="IN" #LABEL="In" #MODIFIED="1" #NAME="WR" #NUMBER="4" #SIDE="bottom" #VERILOG_TYPE="wire" } LINE 1, 0, 0 { POINTS ( (-10,0), (10,0), (0,-10), (-10,0) ) FILL (0,(0,0,0),0) } } PIN 28, 0, 0 { COORD (-100,140) VARIABLES { #DIRECTION="OUT" #LABEL="Bus Out" #MODIFIED="1" #NAME="ADDR(7:0)" #NUMBER="5" #SIDE="top" #VERILOG_TYPE="wire" } LINE 1, 0, 0 { POINTS ( (0,0), (10,10), (-10,10), (0,0) ) FILL (0,(0,0,0),0) } } PIN 33, 0, 0 { COORD (0,140) VARIABLES { #DIRECTION="OUT" #LABEL="Bus Out" #MODIFIED="1" #NAME="inDATA(7:0)" #NUMBER="6" #SIDE="top" #VERILOG_DELAY="" #VERILOG_TYPE="wire" } LINE 1, 0, 0 { POINTS ( (0,0), (10,10), (-10,10), (0,0) ) FILL (0,(0,0,0),0) } } PIN 36, 0, 0 { COORD (-160,260) VARIABLES { #DIRECTION="IN" #LABEL="In" #MODIFIED="1" #NAME="Mclk" #NUMBER="7" #SIDE="left" #VERILOG_TYPE="wire" } LINE 1, 0, 0 { POINTS ( (0,-10), (0,10), (10,0), (0,-10) ) FILL (0,(0,0,0),0) } } PIN 41, 0, 0 { COORD (-160,280) VARIABLES { #DIRECTION="IN" #LABEL="In" #MODIFIED="1" #NAME="Reset" #NUMBER="8" #SIDE="left" #VERILOG_TYPE="wire" } LINE 1, 0, 0 { POINTS ( (0,-10), (0,10), (10,0), (0,-10) ) FILL (0,(0,0,0),0) } } PIN 44, 0, 0 { COORD (-40,140) VARIABLES { #DIRECTION="IN" #LABEL="Bus In" #MODIFIED="1" #NAME="outDATA(7:0)" #NUMBER="9" #SIDE="top" #VERILOG_DELAY="" #VERILOG_TYPE="wire" } LINE 1, 0, 0 { POINTS ( (10,0), (-10,0), (0,10), (10,0) ) FILL (0,(0,0,0),0) } } PIN 47, 0, 0 { COORD (40,140) VARIABLES { #DIRECTION="OUT" #LABEL="Out" #MODIFIED="1" #NAME="ASleading" #NUMBER="10" #SIDE="top" #VERILOG_DELAY="" #VERILOG_TYPE="wire" } LINE 1, 0, 0 { POINTS ( (0,0), (10,10), (-10,10), (0,0) ) FILL (0,(0,0,0),0) } } } } } SYMBOL "#default" "Interrupt" "Interrupt" { HEADER { VARIABLES { #DESCRIPTION="" #FUB="1" #LANGUAGE="VERILOG" #MODIFIED="1114710254" } } PAGE "" { PAGEHEADER { RECT (0,0,280,220) FREEID 84 } BODY { RECT 1, -1, 0 { VARIABLES { #OUTLINE_FILLING="1" } AREA (0,0,280,220) } TEXT 4, 0, 0 { TEXT "$#NAME" RECT (168,14,192,66) ALIGN 1 MARGINS (1,1) PARENT 3 ORIENTATION 5 } TEXT 9, 0, 0 { TEXT "$#NAME" RECT (128,14,152,76) ALIGN 1 MARGINS (1,1) PARENT 8 ORIENTATION 5 } TEXT 14, 0, 0 { TEXT "$#NAME" RECT (108,14,132,76) ALIGN 1 MARGINS (1,1) PARENT 13 ORIENTATION 5 } TEXT 19, 0, 0 { TEXT "$#NAME" RECT (148,14,172,103) ALIGN 1 MARGINS (1,1) PARENT 18 ORIENTATION 5 } TEXT 24, 0, 0 { TEXT "$#NAME" RECT (88,14,112,89) ALIGN 1 MARGINS (1,1) PARENT 23 ORIENTATION 5 } TEXT 29, 0, 0 { TEXT "$#NAME" RECT (68,14,92,89) ALIGN 1 MARGINS (1,1) PARENT 28 ORIENTATION 5 } TEXT 34, 0, 0 { TEXT "$#NAME" RECT (48,14,72,81) ALIGN 1 MARGINS (1,1) PARENT 33 ORIENTATION 5 } TEXT 39, 0, 0 { TEXT "$#NAME" RECT (208,150,232,206) ALIGN 9 MARGINS (1,1) PARENT 38 ORIENTATION 8 } TEXT 44, 0, 0 { TEXT "$#NAME" RECT (14,98,54,122) ALIGN 4 MARGINS (1,1) PARENT 43 } TEXT 49, 0, 0 { TEXT "$#NAME" RECT (14,118,67,142) ALIGN 4 MARGINS (1,1) PARENT 48 } TEXT 54, 0, 0 { TEXT "$#NAME" RECT (148,174,172,207) ALIGN 9 MARGINS (1,1) PARENT 53 ORIENTATION 7 } TEXT 59, 0, 0 { TEXT "$#NAME" RECT (248,13,272,120) ALIGN 1 MARGINS (1,1) PARENT 58 ORIENTATION 6 } TEXT 64, 0, 0 { TEXT "$#NAME" RECT (208,13,232,104) ALIGN 1 MARGINS (1,1) PARENT 63 ORIENTATION 6 } TEXT 73, 0, 0 { TEXT "$#NAME" RECT (188,20,212,118) ALIGN 1 MARGINS (1,1) PARENT 72 ORIENTATION 5 } TEXT 79, 0, 0 { TEXT "$#NAME" RECT (228,14,252,133) ALIGN 1 MARGINS (1,1) PARENT 78 ORIENTATION 5 } TEXT 82, 0, 0 { TEXT "$#NAME" RECT (88,180,112,207) ALIGN 9 MARGINS (1,1) PARENT 81 ORIENTATION 5 } PIN 3, 0, 0 { COORD (180,0) VARIABLES { #DIRECTION="IN" #LABEL="In" #MODIFIED="1" #NAME="I2Cint" #NUMBER="1" #SIDE="top" #VERILOG_DELAY="" #VERILOG_TYPE="wire" } LINE 1, 0, 0 { POINTS ( (10,0), (-10,0), (0,10), (10,0) ) FILL (0,(0,0,0),0) } } PIN 8, 0, 0 { COORD (140,0) VARIABLES { #DIRECTION="IN" #LABEL="In" #MODIFIED="1" #NAME="Thres1" #NUMBER="2" #SIDE="top" #VERILOG_DELAY="" #VERILOG_TYPE="wire" } LINE 1, 0, 0 { POINTS ( (10,0), (-10,0), (0,10), (10,0) ) FILL (0,(0,0,0),0) } } PIN 13, 0, 0 { COORD (120,0) VARIABLES { #DIRECTION="IN" #LABEL="In" #MODIFIED="1" #NAME="Thres0" #NUMBER="3" #SIDE="top" #VERILOG_DELAY="" #VERILOG_TYPE="wire" } LINE 1, 0, 0 { POINTS ( (10,0), (-10,0), (0,10), (10,0) ) FILL (0,(0,0,0),0) } } PIN 18, 0, 0 { COORD (160,0) VARIABLES { #DIRECTION="IN" #LABEL="In" #MODIFIED="1" #NAME="LSwitchInt" #NUMBER="4" #SIDE="top" #VERILOG_DELAY="" #VERILOG_TYPE="wire" } LINE 1, 0, 0 { POINTS ( (10,0), (-10,0), (0,10), (10,0) ) FILL (0,(0,0,0),0) } } PIN 23, 0, 0 { COORD (100,0) VARIABLES { #DIRECTION="IN" #LABEL="In" #MODIFIED="1" #NAME="Homed1" #NUMBER="5" #SIDE="top" #VERILOG_DELAY="" #VERILOG_TYPE="wire" } LINE 1, 0, 0 { POINTS ( (10,0), (-10,0), (0,10), (10,0) ) FILL (0,(0,0,0),0) } } PIN 28, 0, 0 { COORD (80,0) VARIABLES { #DIRECTION="IN" #LABEL="In" #MODIFIED="1" #NAME="Homed0" #NUMBER="6" #SIDE="top" #VERILOG_DELAY="" #VERILOG_TYPE="wire" } LINE 1, 0, 0 { POINTS ( (10,0), (-10,0), (0,10), (10,0) ) FILL (0,(0,0,0),0) } } PIN 33, 0, 0 { COORD (60,0) VARIABLES { #DIRECTION="IN" #LABEL="In" #MODIFIED="1" #NAME="PWRint" #NUMBER="7" #SIDE="top" #VERILOG_DELAY="" #VERILOG_TYPE="wire" } LINE 1, 0, 0 { POINTS ( (10,0), (-10,0), (0,10), (10,0) ) FILL (0,(0,0,0),0) } } PIN 38, 0, 0 { COORD (220,220) VARIABLES { #DIRECTION="IN" #LABEL="In" #MODIFIED="1" #NAME="BusInt" #NUMBER="8" #SIDE="bottom" #VERILOG_DELAY="" #VERILOG_TYPE="wire" } LINE 1, 0, 0 { POINTS ( (-10,0), (10,0), (0,-10), (-10,0) ) FILL (0,(0,0,0),0) } } PIN 43, 0, 0 { COORD (0,110) VARIABLES { #DIRECTION="IN" #LABEL="In" #MODIFIED="1" #NAME="Mclk" #NUMBER="9" #SIDE="left" #VERILOG_DELAY="" #VERILOG_TYPE="wire" } LINE 1, 0, 0 { POINTS ( (0,-10), (0,10), (10,0), (0,-10) ) FILL (0,(0,0,0),0) } } PIN 48, 0, 0 { COORD (0,130) VARIABLES { #DIRECTION="IN" #LABEL="In" #MODIFIED="1" #NAME="Reset" #NUMBER="10" #SIDE="left" #VERILOG_DELAY="" #VERILOG_TYPE="wire" } LINE 1, 0, 0 { POINTS ( (0,-10), (0,10), (10,0), (0,-10) ) FILL (0,(0,0,0),0) } } PIN 53, 0, 0 { COORD (160,220) VARIABLES { #DIRECTION="OUT" #LABEL="Out" #MODIFIED="1" #NAME="INT" #NUMBER="11" #SIDE="bottom" #VERILOG_DELAY="" #VERILOG_TYPE="wire" } LINE 1, 0, 0 { POINTS ( (0,0), (-10,-10), (10,-10), (0,0) ) FILL (0,(0,0,0),0) } } PIN 58, 0, 0 { COORD (260,0) VARIABLES { #DIRECTION="IN" #LABEL="Bus In" #MODIFIED="1" #NAME="inDATA(7:0)" #NUMBER="12" #SIDE="top" #VERILOG_DELAY="" #VERILOG_TYPE="wire" } LINE 1, 0, 0 { POINTS ( (10,0), (-10,0), (0,10), (10,0) ) FILL (0,(0,0,0),0) } } PIN 63, 0, 0 { COORD (220,0) VARIABLES { #DIRECTION="IN" #LABEL="In" #MODIFIED="1" #NAME="DCORIEw" #NUMBER="13" #SIDE="top" #VERILOG_DELAY="" #VERILOG_TYPE="wire" } LINE 1, 0, 0 { POINTS ( (10,0), (-10,0), (0,10), (10,0) ) FILL (0,(0,0,0),0) } } PIN 72, 0, 0 { COORD (200,0) VARIABLES { #DIRECTION="IN" #FAMILY="Fub" #NAME="DCORIFGr" #NUMBER="0" #SIDE="top" #VERILOG_TYPE="wire" } LINE 1, 0, 0 { POINTS ( (-10,1), (10,1), (0,11) ) } } PIN 78, 0, 0 { COORD (240,0) VARIABLES { #DIRECTION="OUT" #FAMILY="Fub" #LABEL="Bus Out" #NAME="outDATA(7:0)" #NUMBER="0" #SIDE="top" #VERILOG_DELAY="" #VERILOG_TYPE="wire" } LINE 1, 0, 0 { POINTS ( (0,0), (10,10), (-10,10), (0,0) ) FILL (0,(0,0,0),0) } } PIN 81, 0, 0 { COORD (100,220) VARIABLES { #DIRECTION="OUT" #LABEL="Out" #MODIFIED="1" #NAME="TP" #NUMBER="14" #SIDE="bottom" #VERILOG_DELAY="" #VERILOG_TYPE="wire" } LINE 1, 0, 0 { POINTS ( (0,0), (-10,-10), (10,-10), (0,0) ) FILL (0,(0,0,0),0) } } } } } SYMBOL "#default" "Lswitch" "Lswitch" { HEADER { VARIABLES { #DESCRIPTION="" #FUB="1" #LANGUAGE="VERILOG" #MODIFIED="1100810507" } } PAGE "" { PAGEHEADER { RECT (-160,0,200,340) FREEID 117 } BODY { RECT 1, -1, 0 { VARIABLES { #OUTLINE_FILLING="1" } AREA (-160,0,200,338) } TEXT 27, 0, 0 { TEXT "$#NAME" RECT (-146,128,-106,152) ALIGN 4 MARGINS (1,1) PARENT 26 } TEXT 32, 0, 0 { TEXT "$#NAME" RECT (-146,108,-93,132) ALIGN 4 MARGINS (1,1) PARENT 31 } TEXT 37, 0, 0 { TEXT "$#NAME" RECT (88,262,112,326) ALIGN 9 MARGINS (1,1) PARENT 36 ORIENTATION 8 } TEXT 42, 0, 0 { TEXT "$#NAME" RECT (68,277,92,326) ALIGN 9 MARGINS (1,1) PARENT 41 ORIENTATION 8 } TEXT 47, 0, 0 { TEXT "$#NAME" RECT (48,275,72,326) ALIGN 9 MARGINS (1,1) PARENT 46 ORIENTATION 8 } TEXT 52, 0, 0 { TEXT "$#NAME" RECT (-32,262,-8,326) ALIGN 9 MARGINS (1,1) PARENT 51 ORIENTATION 8 } TEXT 57, 0, 0 { TEXT "$#NAME" RECT (-52,277,-28,326) ALIGN 9 MARGINS (1,1) PARENT 56 ORIENTATION 8 } TEXT 62, 0, 0 { TEXT "$#NAME" RECT (-72,275,-48,326) ALIGN 9 MARGINS (1,1) PARENT 61 ORIENTATION 8 } TEXT 68, 0, 0 { TEXT "$#NAME" RECT (148,13,172,132) ALIGN 1 MARGINS (1,1) PARENT 67 ORIENTATION 6 } TEXT 71, 0, 0 { TEXT "$#NAME" RECT (-92,279,-68,326) ALIGN 9 MARGINS (1,1) PARENT 70 ORIENTATION 8 } TEXT 76, 0, 0 { TEXT "$#NAME" RECT (28,279,52,326) ALIGN 9 MARGINS (1,1) PARENT 75 ORIENTATION 8 } TEXT 79, 0, 0 { TEXT "$#NAME" RECT (-92,13,-68,72) ALIGN 1 MARGINS (1,1) PARENT 78 ORIENTATION 6 } TEXT 84, 0, 0 { TEXT "$#NAME" RECT (-72,13,-48,72) ALIGN 1 MARGINS (1,1) PARENT 83 ORIENTATION 6 } TEXT 87, 0, 0 { TEXT "$#NAME" RECT (8,264,32,326) ALIGN 9 MARGINS (1,1) PARENT 86 ORIENTATION 8 } TEXT 92, 0, 0 { TEXT "$#NAME" RECT (-112,264,-88,326) ALIGN 9 MARGINS (1,1) PARENT 91 ORIENTATION 8 } TEXT 95, 0, 0 { TEXT "$#NAME" RECT (8,13,32,141) ALIGN 1 MARGINS (1,1) PARENT 94 ORIENTATION 6 } TEXT 103, 0, 0 { TEXT "$#NAME" RECT (48,13,72,118) ALIGN 1 MARGINS (1,1) PARENT 102 ORIENTATION 6 } TEXT 109, 0, 0 { TEXT "$#NAME" RECT (-32,14,-8,103) ALIGN 1 MARGINS (1,1) PARENT 108 ORIENTATION 5 } TEXT 112, 0, 0 { TEXT "$#NAME" RECT (68,14,92,121) ALIGN 1 MARGINS (1,1) PARENT 111 ORIENTATION 5 } TEXT 115, 0, 0 { TEXT "$#NAME" RECT (108,14,132,60) ALIGN 1 MARGINS (1,1) PARENT 114 ORIENTATION 5 } PIN 26, 0, 0 { COORD (-160,140) VARIABLES { #DIRECTION="IN" #LABEL="In" #MODIFIED="1" #NAME="Mclk" #NUMBER="1" #SIDE="left" #VERILOG_DELAY="" #VERILOG_TYPE="wire" } LINE 1, 0, 0 { POINTS ( (0,-10), (0,10), (10,0), (0,-10) ) FILL (0,(0,0,0),0) } } PIN 31, 0, 0 { COORD (-160,120) VARIABLES { #DIRECTION="IN" #LABEL="In" #MODIFIED="1" #NAME="Reset" #NUMBER="2" #SIDE="left" #VERILOG_DELAY="" #VERILOG_TYPE="wire" } LINE 1, 0, 0 { POINTS ( (0,-10), (0,10), (10,0), (0,-10) ) FILL (0,(0,0,0),0) } } PIN 36, 0, 0 { COORD (100,340) VARIABLES { #DIRECTION="IN" #LABEL="In" #MODIFIED="1" #NAME="Home1" #NUMBER="3" #SIDE="bottom" #VERILOG_DELAY="" #VERILOG_TYPE="wire" } LINE 1, 0, 0 { POINTS ( (-10,0), (10,0), (0,-10), (-10,0) ) FILL (0,(0,0,0),0) } } PIN 41, 0, 0 { COORD (80,340) VARIABLES { #DIRECTION="IN" #LABEL="In" #MODIFIED="1" #NAME="FLS1" #NUMBER="4" #SIDE="bottom" #VERILOG_DELAY="" #VERILOG_TYPE="wire" } LINE 1, 0, 0 { POINTS ( (-10,0), (10,0), (0,-10), (-10,0) ) FILL (0,(0,0,0),0) } } PIN 46, 0, 0 { COORD (60,340) VARIABLES { #DIRECTION="IN" #LABEL="In" #MODIFIED="1" #NAME="RLS1" #NUMBER="5" #SIDE="bottom" #VERILOG_DELAY="" #VERILOG_TYPE="wire" } LINE 1, 0, 0 { POINTS ( (-10,0), (10,0), (0,-10), (-10,0) ) FILL (0,(0,0,0),0) } } PIN 51, 0, 0 { COORD (-20,340) VARIABLES { #DIRECTION="IN" #LABEL="In" #MODIFIED="1" #NAME="Home0" #NUMBER="6" #SIDE="bottom" #VERILOG_DELAY="" #VERILOG_TYPE="wire" } LINE 1, 0, 0 { POINTS ( (-10,0), (10,0), (0,-10), (-10,0) ) FILL (0,(0,0,0),0) } } PIN 56, 0, 0 { COORD (-40,340) VARIABLES { #DIRECTION="IN" #LABEL="In" #MODIFIED="1" #NAME="FLS0" #NUMBER="7" #SIDE="bottom" #VERILOG_DELAY="" #VERILOG_TYPE="wire" } LINE 1, 0, 0 { POINTS ( (-10,0), (10,0), (0,-10), (-10,0) ) FILL (0,(0,0,0),0) } } PIN 61, 0, 0 { COORD (-60,340) VARIABLES { #DIRECTION="IN" #LABEL="In" #MODIFIED="1" #NAME="RLS0" #NUMBER="8" #SIDE="bottom" #VERILOG_DELAY="" #VERILOG_TYPE="wire" } LINE 1, 0, 0 { POINTS ( (-10,0), (10,0), (0,-10), (-10,0) ) FILL (0,(0,0,0),0) } } PIN 67, 0, 0 { COORD (160,0) VARIABLES { #DIRECTION="OUT" #LABEL="Bus Out" #MODIFIED="1" #NAME="outDATA(7:0)" #NUMBER="9" #SIDE="top" #VERILOG_DELAY="" #VERILOG_TYPE="wire" } LINE 1, 0, 0 { POINTS ( (0,0), (10,10), (-10,10), (0,0) ) FILL (0,(0,0,0),0) } } PIN 70, 0, 0 { COORD (-80,340) VARIABLES { #DIRECTION="IN" #LABEL="In" #MODIFIED="1" #NAME="DIR0" #NUMBER="10" #SIDE="bottom" #VERILOG_DELAY="" #VERILOG_TYPE="wire" } LINE 1, 0, 0 { POINTS ( (-10,0), (10,0), (0,-10), (-10,0) ) FILL (0,(0,0,0),0) } } PIN 75, 0, 0 { COORD (40,340) VARIABLES { #DIRECTION="IN" #LABEL="In" #MODIFIED="1" #NAME="DIR1" #NUMBER="11" #SIDE="bottom" #VERILOG_DELAY="" #VERILOG_TYPE="wire" } LINE 1, 0, 0 { POINTS ( (-10,0), (10,0), (0,-10), (-10,0) ) FILL (0,(0,0,0),0) } } PIN 78, 0, 0 { COORD (-80,0) VARIABLES { #DIRECTION="OUT" #LABEL="Out" #MODIFIED="1" #NAME="fBRK1" #NUMBER="12" #SIDE="top" #VERILOG_DELAY="" #VERILOG_TYPE="wire" } LINE 1, 0, 0 { POINTS ( (0,0), (10,10), (-10,10), (0,0) ) FILL (0,(0,0,0),0) } } PIN 83, 0, 0 { COORD (-60,0) VARIABLES { #DIRECTION="OUT" #LABEL="Out" #MODIFIED="1" #NAME="fBRK0" #NUMBER="13" #SIDE="top" #VERILOG_DELAY="" #VERILOG_TYPE="wire" } LINE 1, 0, 0 { POINTS ( (0,0), (10,10), (-10,10), (0,0) ) FILL (0,(0,0,0),0) } } PIN 86, 0, 0 { COORD (20,340) VARIABLES { #DIRECTION="IN" #LABEL="In" #MODIFIED="1" #NAME="Brake1" #NUMBER="14" #SIDE="bottom" #VERILOG_DELAY="" #VERILOG_TYPE="wire" } LINE 1, 0, 0 { POINTS ( (-10,0), (10,0), (0,-10), (-10,0) ) FILL (0,(0,0,0),0) } } PIN 91, 0, 0 { COORD (-100,340) VARIABLES { #DIRECTION="IN" #LABEL="In" #MODIFIED="1" #NAME="Brake0" #NUMBER="15" #SIDE="bottom" #VERILOG_DELAY="" #VERILOG_TYPE="wire" } LINE 1, 0, 0 { POINTS ( (-10,0), (10,0), (0,-10), (-10,0) ) FILL (0,(0,0,0),0) } } PIN 94, 0, 0 { COORD (20,0) VARIABLES { #DIRECTION="IN" #LABEL="In" #MODIFIED="1" #NAME="DCORLIMITSr" #NUMBER="16" #SIDE="top" #VERILOG_DELAY="" #VERILOG_TYPE="wire" } LINE 1, 0, 0 { POINTS ( (10,0), (-10,0), (0,10), (10,0) ) FILL (0,(0,0,0),0) } } PIN 102, 0, 0 { COORD (60,0) VARIABLES { #DIRECTION="IN" #LABEL="In" #MODIFIED="1" #NAME="DCORIFGw" #NUMBER="18" #SIDE="top" #VERILOG_DELAY="" #VERILOG_TYPE="wire" } LINE 1, 0, 0 { POINTS ( (10,0), (-10,0), (0,10), (10,0) ) FILL (0,(0,0,0),0) } } PIN 108, 0, 0 { COORD (-20,0) VARIABLES { #DIRECTION="OUT" #LABEL="Out" #MODIFIED="1" #NAME="LSwitchInt" #NUMBER="20" #SIDE="top" #VERILOG_DELAY="" #VERILOG_TYPE="wire" } LINE 1, 0, 0 { POINTS ( (0,0), (10,10), (-10,10), (0,0) ) FILL (0,(0,0,0),0) } } PIN 111, 0, 0 { COORD (80,0) VARIABLES { #DIRECTION="IN" #LABEL="In" #MODIFIED="1" #NAME="DCORLINTr" #NUMBER="21" #SIDE="top" #VERILOG_DELAY="" #VERILOG_TYPE="wire" } LINE 1, 0, 0 { POINTS ( (10,0), (-10,0), (0,10), (10,0) ) FILL (0,(0,0,0),0) } } PIN 114, 0, 0 { COORD (120,0) VARIABLES { #DIRECTION="IN" #LABEL="In" #MODIFIED="1" #NAME="LIFG" #NUMBER="22" #SIDE="top" #VERILOG_DELAY="" #VERILOG_TYPE="wire" } LINE 1, 0, 0 { POINTS ( (10,0), (-10,0), (0,10), (10,0) ) FILL (0,(0,0,0),0) } } } } } SYMBOL "#default" "MISCouts" "MISCouts" { HEADER { VARIABLES { #DESCRIPTION="" #FUB="1" #LANGUAGE="VERILOG" #MODIFIED="1096639853" } } PAGE "" { PAGEHEADER { RECT (-140,0,240,320) FREEID 87 } BODY { RECT 1, -1, 0 { VARIABLES { #OUTLINE_FILLING="1" } AREA (-140,0,240,320) } TEXT 9, 0, 0 { TEXT "$#NAME" RECT (148,13,172,120) ALIGN 1 MARGINS (1,1) PARENT 8 ORIENTATION 6 } TEXT 14, 0, 0 { TEXT "$#NAME" RECT (108,255,132,306) ALIGN 9 MARGINS (1,1) PARENT 13 ORIENTATION 8 } TEXT 19, 0, 0 { TEXT "$#NAME" RECT (88,249,112,300) ALIGN 9 MARGINS (1,1) PARENT 18 ORIENTATION 8 } TEXT 24, 0, 0 { TEXT "$#NAME" RECT (68,249,92,300) ALIGN 9 MARGINS (1,1) PARENT 23 ORIENTATION 8 } TEXT 29, 0, 0 { TEXT "$#NAME" RECT (48,255,72,306) ALIGN 9 MARGINS (1,1) PARENT 28 ORIENTATION 8 } TEXT 34, 0, 0 { TEXT "$#NAME" RECT (28,255,52,306) ALIGN 9 MARGINS (1,1) PARENT 33 ORIENTATION 8 } TEXT 39, 0, 0 { TEXT "$#NAME" RECT (-32,233,-8,306) ALIGN 9 MARGINS (1,1) PARENT 38 ORIENTATION 8 } TEXT 44, 0, 0 { TEXT "$#NAME" RECT (-52,223,-28,306) ALIGN 9 MARGINS (1,1) PARENT 43 ORIENTATION 8 } TEXT 64, 0, 0 { TEXT "$#NAME" RECT (-126,108,-86,132) ALIGN 4 MARGINS (1,1) PARENT 63 } TEXT 69, 0, 0 { TEXT "$#NAME" RECT (-126,148,-58,172) ALIGN 4 MARGINS (1,1) PARENT 68 } TEXT 72, 0, 0 { TEXT "$#NAME" RECT (88,13,112,125) ALIGN 1 MARGINS (1,1) PARENT 71 ORIENTATION 6 } TEXT 75, 0, 0 { TEXT "$#NAME" RECT (8,184,32,306) ALIGN 9 MARGINS (1,1) PARENT 74 ORIENTATION 8 } TEXT 80, 0, 0 { TEXT "$#NAME" RECT (-12,184,12,306) ALIGN 9 MARGINS (1,1) PARENT 79 ORIENTATION 8 } TEXT 83, 0, 0 { TEXT "$#NAME" RECT (168,209,192,307) ALIGN 9 MARGINS (1,1) PARENT 82 ORIENTATION 5 } TEXT 86, 0, 0 { TEXT "$#NAME" RECT (-126,168,-73,192) ALIGN 4 MARGINS (1,1) PARENT 85 } PIN 8, 0, 0 { COORD (160,0) VARIABLES { #DIRECTION="IN" #LABEL="Bus In" #MODIFIED="1" #NAME="inDATA(7:0)" #NUMBER="1" #SIDE="top" #VERILOG_DELAY="" #VERILOG_TYPE="wire" } LINE 1, 0, 0 { POINTS ( (10,0), (-10,0), (0,10), (10,0) ) FILL (0,(0,0,0),0) } } PIN 13, 0, 0 { COORD (120,320) VARIABLES { #DIRECTION="OUT" #LABEL="Out" #MODIFIED="1" #NAME="LED1" #NUMBER="2" #SIDE="bottom" #VERILOG_DELAY="" #VERILOG_TYPE="wire" } LINE 1, 0, 0 { POINTS ( (0,0), (-10,-10), (10,-10), (0,0) ) FILL (0,(0,0,0),0) } } PIN 18, 0, 0 { COORD (100,320) VARIABLES { #DIRECTION="OUT" #LABEL="Out" #MODIFIED="1" #NAME="LED2" #NUMBER="3" #SIDE="bottom" #VERILOG_DELAY="" #VERILOG_TYPE="wire" } LINE 1, 0, 0 { POINTS ( (0,0), (-10,-10), (10,-10), (0,0) ) FILL (0,(0,0,0),0) } } PIN 23, 0, 0 { COORD (80,320) VARIABLES { #DIRECTION="OUT" #LABEL="Out" #MODIFIED="1" #NAME="LED3" #NUMBER="4" #SIDE="bottom" #VERILOG_DELAY="" #VERILOG_TYPE="wire" } LINE 1, 0, 0 { POINTS ( (0,0), (-10,-10), (10,-10), (0,0) ) FILL (0,(0,0,0),0) } } PIN 28, 0, 0 { COORD (60,320) VARIABLES { #DIRECTION="OUT" #LABEL="Out" #MODIFIED="1" #NAME="LED4" #NUMBER="5" #SIDE="bottom" #VERILOG_DELAY="" #VERILOG_TYPE="wire" } LINE 1, 0, 0 { POINTS ( (0,0), (-10,-10), (10,-10), (0,0) ) FILL (0,(0,0,0),0) } } PIN 33, 0, 0 { COORD (40,320) VARIABLES { #DIRECTION="OUT" #LABEL="Out" #MODIFIED="1" #NAME="LED5" #NUMBER="6" #SIDE="bottom" #VERILOG_DELAY="" #VERILOG_TYPE="wire" } LINE 1, 0, 0 { POINTS ( (0,0), (-10,-10), (10,-10), (0,0) ) FILL (0,(0,0,0),0) } } PIN 38, 0, 0 { COORD (-20,320) VARIABLES { #DIRECTION="OUT" #LABEL="Out" #MODIFIED="1" #NAME="MTRpwr" #NUMBER="7" #SIDE="bottom" #VERILOG_DELAY="" #VERILOG_TYPE="wire" } LINE 1, 0, 0 { POINTS ( (0,0), (-10,-10), (10,-10), (0,0) ) FILL (0,(0,0,0),0) } } PIN 43, 0, 0 { COORD (-40,320) VARIABLES { #DIRECTION="OUT" #LABEL="Out" #MODIFIED="1" #NAME="MTRpwrn" #NUMBER="8" #SIDE="bottom" #VERILOG_DELAY="" #VERILOG_TYPE="wire" } LINE 1, 0, 0 { POINTS ( (0,0), (-10,-10), (10,-10), (0,0) ) FILL (0,(0,0,0),0) } } PIN 63, 0, 0 { COORD (-140,120) VARIABLES { #DIRECTION="IN" #LABEL="In" #MODIFIED="1" #NAME="Mclk" #NUMBER="9" #SIDE="left" #VERILOG_DELAY="" #VERILOG_TYPE="wire" } LINE 1, 0, 0 { POINTS ( (0,-10), (0,10), (10,0), (0,-10) ) FILL (0,(0,0,0),0) } } PIN 68, 0, 0 { COORD (-140,160) VARIABLES { #DIRECTION="IN" #LABEL="In" #MODIFIED="1" #NAME="MReset" #NUMBER="10" #SIDE="left" #VERILOG_DELAY="" #VERILOG_TYPE="wire" } LINE 1, 0, 0 { POINTS ( (0,-10), (0,10), (10,0), (0,-10) ) FILL (0,(0,0,0),0) } } PIN 71, 0, 0 { COORD (100,0) VARIABLES { #DIRECTION="IN" #LABEL="In" #MODIFIED="1" #NAME="DCOROUTw" #NUMBER="11" #SIDE="top" #VERILOG_DELAY="" #VERILOG_TYPE="wire" } LINE 1, 0, 0 { POINTS ( (10,0), (-10,0), (0,10), (10,0) ) FILL (0,(0,0,0),0) } } PIN 74, 0, 0 { COORD (20,320) VARIABLES { #DIRECTION="OUT" #LABEL="Out" #MODIFIED="1" #NAME="GP_Motor0_1" #NUMBER="12" #SIDE="bottom" #VERILOG_DELAY="" #VERILOG_TYPE="wire" } LINE 1, 0, 0 { POINTS ( (0,0), (-10,-10), (10,-10), (0,0) ) FILL (0,(0,0,0),0) } } PIN 79, 0, 0 { COORD (0,320) VARIABLES { #DIRECTION="OUT" #LABEL="Out" #MODIFIED="1" #NAME="GP_Motor1_1" #NUMBER="13" #SIDE="bottom" #VERILOG_DELAY="" #VERILOG_TYPE="wire" } LINE 1, 0, 0 { POINTS ( (0,0), (-10,-10), (10,-10), (0,0) ) FILL (0,(0,0,0),0) } } PIN 82, 0, 0 { COORD (180,320) VARIABLES { #DIRECTION="IN" #LABEL="In" #MODIFIED="1" #NAME="LightSense" #NUMBER="14" #SIDE="bottom" #VERILOG_DELAY="" #VERILOG_TYPE="wire" } LINE 1, 0, 0 { POINTS ( (-10,0), (10,0), (0,-10), (-10,0) ) FILL (0,(0,0,0),0) } } PIN 85, 0, 0 { COORD (-140,180) VARIABLES { #DIRECTION="IN" #LABEL="In" #MODIFIED="1" #NAME="Reset" #NUMBER="15" #SIDE="left" #VERILOG_DELAY="" #VERILOG_TYPE="wire" } LINE 1, 0, 0 { POINTS ( (0,-10), (0,10), (10,0), (0,-10) ) FILL (0,(0,0,0),0) } } } } } SYMBOL "#default" "PWMcontrol" "PWMcontrol" { HEADER { VARIABLES { #DESCRIPTION="" #FUB="1" #LANGUAGE="VERILOG" #MODIFIED="1098111484" } } PAGE "" { PAGEHEADER { RECT (0,0,400,240) FREEID 122 } BODY { RECT 1, -1, 0 { VARIABLES { #OUTLINE_FILLING="1" } AREA (0,0,400,240) } TEXT 14, 0, 0 { TEXT "$#NAME" RECT (308,175,332,227) ALIGN 9 MARGINS (1,1) PARENT 13 ORIENTATION 7 } TEXT 19, 0, 0 { TEXT "$#NAME" RECT (328,177,352,227) ALIGN 9 MARGINS (1,1) PARENT 18 ORIENTATION 7 } TEXT 24, 0, 0 { TEXT "$#NAME" RECT (348,175,372,227) ALIGN 9 MARGINS (1,1) PARENT 23 ORIENTATION 7 } TEXT 29, 0, 0 { TEXT "$#NAME" RECT (168,175,192,227) ALIGN 9 MARGINS (1,1) PARENT 28 ORIENTATION 7 } TEXT 34, 0, 0 { TEXT "$#NAME" RECT (128,175,152,227) ALIGN 9 MARGINS (1,1) PARENT 33 ORIENTATION 7 } TEXT 39, 0, 0 { TEXT "$#NAME" RECT (148,177,172,227) ALIGN 9 MARGINS (1,1) PARENT 38 ORIENTATION 7 } TEXT 44, 0, 0 { TEXT "$#NAME" RECT (288,166,312,226) ALIGN 9 MARGINS (1,1) PARENT 43 ORIENTATION 8 } TEXT 49, 0, 0 { TEXT "$#NAME" RECT (268,179,292,226) ALIGN 9 MARGINS (1,1) PARENT 48 ORIENTATION 8 } TEXT 54, 0, 0 { TEXT "$#NAME" RECT (248,164,272,226) ALIGN 9 MARGINS (1,1) PARENT 53 ORIENTATION 8 } TEXT 59, 0, 0 { TEXT "$#NAME" RECT (88,166,112,226) ALIGN 9 MARGINS (1,1) PARENT 58 ORIENTATION 8 } TEXT 64, 0, 0 { TEXT "$#NAME" RECT (68,179,92,226) ALIGN 9 MARGINS (1,1) PARENT 63 ORIENTATION 8 } TEXT 69, 0, 0 { TEXT "$#NAME" RECT (48,164,72,226) ALIGN 9 MARGINS (1,1) PARENT 68 ORIENTATION 8 } TEXT 79, 0, 0 { TEXT "$#NAME" RECT (288,20,312,79) ALIGN 1 MARGINS (1,1) PARENT 78 ORIENTATION 5 } TEXT 84, 0, 0 { TEXT "$#NAME" RECT (148,14,172,73) ALIGN 1 MARGINS (1,1) PARENT 83 ORIENTATION 5 } TEXT 87, 0, 0 { TEXT "$#NAME" RECT (368,177,392,227) ALIGN 9 MARGINS (1,1) PARENT 86 ORIENTATION 7 } TEXT 92, 0, 0 { TEXT "$#NAME" RECT (108,177,132,227) ALIGN 9 MARGINS (1,1) PARENT 91 ORIENTATION 7 } TEXT 95, 0, 0 { TEXT "$#NAME" RECT (268,14,292,80) ALIGN 1 MARGINS (1,1) PARENT 94 ORIENTATION 5 } TEXT 100, 0, 0 { TEXT "$#NAME" RECT (128,14,152,80) ALIGN 1 MARGINS (1,1) PARENT 99 ORIENTATION 5 } TEXT 103, 0, 0 { TEXT "$#NAME" RECT (228,153,252,226) ALIGN 9 MARGINS (1,1) PARENT 102 ORIENTATION 5 } TEXT 106, 0, 0 { TEXT "$#NAME" RECT (208,178,232,227) ALIGN 9 MARGINS (1,1) PARENT 105 ORIENTATION 5 } TEXT 111, 0, 0 { TEXT "$#NAME" RECT (188,176,212,227) ALIGN 9 MARGINS (1,1) PARENT 110 ORIENTATION 5 } TEXT 116, 0, 0 { TEXT "$#NAME" RECT (28,178,52,227) ALIGN 9 MARGINS (1,1) PARENT 115 ORIENTATION 5 } TEXT 121, 0, 0 { TEXT "$#NAME" RECT (8,176,32,227) ALIGN 9 MARGINS (1,1) PARENT 120 ORIENTATION 5 } PIN 13, 0, 0 { COORD (320,240) VARIABLES { #DIRECTION="OUT" #LABEL="Out" #MODIFIED="1" #NAME="PAH1" #NUMBER="1" #SIDE="bottom" #VERILOG_DELAY="" #VERILOG_TYPE="wire" } LINE 2, 0, 0 { POINTS ( (0,0), (10,-10), (-10,-10), (0,0) ) } } PIN 18, 0, 0 { COORD (340,240) VARIABLES { #DIRECTION="OUT" #LABEL="Out" #MODIFIED="1" #NAME="PAL1" #NUMBER="2" #SIDE="bottom" #VERILOG_DELAY="" #VERILOG_TYPE="wire" } LINE 2, 0, 0 { POINTS ( (0,0), (10,-10), (-10,-10), (0,0) ) } } PIN 23, 0, 0 { COORD (360,240) VARIABLES { #DIRECTION="OUT" #LABEL="Out" #MODIFIED="1" #NAME="PBH1" #NUMBER="3" #SIDE="bottom" #VERILOG_DELAY="" #VERILOG_TYPE="wire" } LINE 2, 0, 0 { POINTS ( (0,0), (10,-10), (-10,-10), (0,0) ) } } PIN 28, 0, 0 { COORD (180,240) VARIABLES { #DIRECTION="OUT" #LABEL="Out" #MODIFIED="1" #NAME="PAH2" #NUMBER="4" #SIDE="bottom" #VERILOG_DELAY="" #VERILOG_TYPE="wire" } LINE 2, 0, 0 { POINTS ( (0,0), (10,-10), (-10,-10), (0,0) ) } } PIN 33, 0, 0 { COORD (140,240) VARIABLES { #DIRECTION="OUT" #LABEL="Out" #MODIFIED="1" #NAME="PBH2" #NUMBER="5" #SIDE="bottom" #VERILOG_DELAY="" #VERILOG_TYPE="wire" } LINE 2, 0, 0 { POINTS ( (0,0), (10,-10), (-10,-10), (0,0) ) } } PIN 38, 0, 0 { COORD (160,240) VARIABLES { #DIRECTION="OUT" #LABEL="Out" #MODIFIED="1" #NAME="PAL2" #NUMBER="6" #SIDE="bottom" #VERILOG_DELAY="" #VERILOG_TYPE="wire" } LINE 2, 0, 0 { POINTS ( (0,0), (10,-10), (-10,-10), (0,0) ) } } PIN 43, 0, 0 { COORD (300,240) VARIABLES { #DIRECTION="IN" #LABEL="In" #MODIFIED="1" #NAME="PWM1" #NUMBER="7" #SIDE="bottom" #VERILOG_DELAY="" #VERILOG_TYPE="wire" } LINE 2, 0, 0 { POINTS ( (-10,0), (10,0), (0,-10), (-10,0) ) } } PIN 48, 0, 0 { COORD (280,240) VARIABLES { #DIRECTION="IN" #LABEL="In" #MODIFIED="1" #NAME="DIR1" #NUMBER="8" #SIDE="bottom" #VERILOG_DELAY="" #VERILOG_TYPE="wire" } LINE 2, 0, 0 { POINTS ( (-10,0), (10,0), (0,-10), (-10,0) ) } } PIN 53, 0, 0 { COORD (260,240) VARIABLES { #DIRECTION="IN" #LABEL="In" #MODIFIED="1" #NAME="Brake1" #NUMBER="9" #SIDE="bottom" #VERILOG_DELAY="" #VERILOG_TYPE="wire" } LINE 2, 0, 0 { POINTS ( (-10,0), (10,0), (0,-10), (-10,0) ) } } PIN 58, 0, 0 { COORD (100,240) VARIABLES { #DIRECTION="IN" #LABEL="In" #MODIFIED="1" #NAME="PWM2" #NUMBER="10" #SIDE="bottom" #VERILOG_DELAY="" #VERILOG_TYPE="wire" } LINE 2, 0, 0 { POINTS ( (-10,0), (10,0), (0,-10), (-10,0) ) } } PIN 63, 0, 0 { COORD (80,240) VARIABLES { #DIRECTION="IN" #LABEL="In" #MODIFIED="1" #NAME="DIR2" #NUMBER="11" #SIDE="bottom" #VERILOG_DELAY="" #VERILOG_TYPE="wire" } LINE 2, 0, 0 { POINTS ( (-10,0), (10,0), (0,-10), (-10,0) ) } } PIN 68, 0, 0 { COORD (60,240) VARIABLES { #DIRECTION="IN" #LABEL="In" #MODIFIED="1" #NAME="Brake2" #NUMBER="12" #SIDE="bottom" #VERILOG_DELAY="" #VERILOG_TYPE="wire" } LINE 2, 0, 0 { POINTS ( (-10,0), (10,0), (0,-10), (-10,0) ) } } PIN 78, 0, 0 { COORD (300,0) VARIABLES { #DIRECTION="IN" #LABEL="In" #MODIFIED="1" #NAME="fBRK1" #NUMBER="13" #SIDE="top" #VERILOG_DELAY="" #VERILOG_TYPE="wire" } LINE 2, 0, 0 { POINTS ( (10,0), (-10,0), (0,10), (10,0) ) } } PIN 83, 0, 0 { COORD (160,0) VARIABLES { #DIRECTION="IN" #LABEL="In" #MODIFIED="1" #NAME="fBRK2" #NUMBER="14" #SIDE="top" #VERILOG_DELAY="" #VERILOG_TYPE="wire" } LINE 2, 0, 0 { POINTS ( (10,0), (-10,0), (0,10), (10,0) ) } } PIN 86, 0, 0 { COORD (380,240) VARIABLES { #DIRECTION="OUT" #LABEL="Out" #MODIFIED="1" #NAME="PBL1" #NUMBER="15" #SIDE="bottom" #VERILOG_DELAY="" #VERILOG_TYPE="wire" } LINE 2, 0, 0 { POINTS ( (0,0), (10,-10), (-10,-10), (0,0) ) } } PIN 91, 0, 0 { COORD (120,240) VARIABLES { #DIRECTION="OUT" #LABEL="Out" #MODIFIED="1" #NAME="PBL2" #NUMBER="16" #SIDE="bottom" #VERILOG_DELAY="" #VERILOG_TYPE="wire" } LINE 2, 0, 0 { POINTS ( (0,0), (10,-10), (-10,-10), (0,0) ) } } PIN 94, 0, 0 { COORD (280,0) VARIABLES { #DIRECTION="IN" #LABEL="In" #MODIFIED="1" #NAME="HBRK1" #NUMBER="17" #SIDE="top" #VERILOG_DELAY="" #VERILOG_TYPE="wire" } LINE 1, 0, 0 { POINTS ( (10,0), (-10,0), (0,10), (10,0) ) FILL (0,(0,0,0),0) } } PIN 99, 0, 0 { COORD (140,0) VARIABLES { #DIRECTION="IN" #LABEL="In" #MODIFIED="1" #NAME="HBRK2" #NUMBER="18" #SIDE="top" #VERILOG_DELAY="" #VERILOG_TYPE="wire" } LINE 1, 0, 0 { POINTS ( (10,0), (-10,0), (0,10), (10,0) ) FILL (0,(0,0,0),0) } } PIN 102, 0, 0 { COORD (240,240) VARIABLES { #DIRECTION="IN" #FAMILY="Fub" #NAME="MTRpwr" #NUMBER="0" #VERILOG_TYPE="wire" } LINE 1, 0, 0 { POINTS ( (-10,-1), (10,-1), (0,-11) ) } } PIN 105, 0, 0 { COORD (220,240) VARIABLES { #DIRECTION="IN" #LABEL="In" #MODIFIED="1" #NAME="FLS0" #NUMBER="19" #SIDE="bottom" #VERILOG_DELAY="" #VERILOG_TYPE="wire" } LINE 1, 0, 0 { POINTS ( (-10,0), (10,0), (0,-10), (-10,0) ) FILL (0,(0,0,0),0) } } PIN 110, 0, 0 { COORD (200,240) VARIABLES { #DIRECTION="IN" #LABEL="In" #MODIFIED="1" #NAME="RLS0" #NUMBER="20" #SIDE="bottom" #VERILOG_DELAY="" #VERILOG_TYPE="wire" } LINE 1, 0, 0 { POINTS ( (-10,0), (10,0), (0,-10), (-10,0) ) FILL (0,(0,0,0),0) } } PIN 115, 0, 0 { COORD (40,240) VARIABLES { #DIRECTION="IN" #LABEL="In" #MODIFIED="1" #NAME="FLS1" #NUMBER="21" #SIDE="bottom" #VERILOG_DELAY="" #VERILOG_TYPE="wire" } LINE 1, 0, 0 { POINTS ( (-10,0), (10,0), (0,-10), (-10,0) ) FILL (0,(0,0,0),0) } } PIN 120, 0, 0 { COORD (20,240) VARIABLES { #DIRECTION="IN" #LABEL="In" #MODIFIED="1" #NAME="RLS1" #NUMBER="22" #SIDE="bottom" #VERILOG_DELAY="" #VERILOG_TYPE="wire" } LINE 1, 0, 0 { POINTS ( (-10,0), (10,0), (0,-10), (-10,0) ) FILL (0,(0,0,0),0) } } } } } SYMBOL "#default" "PWRreg" "PWRreg" { HEADER { VARIABLES { #DESCRIPTION="" #FUB="1" #LANGUAGE="VERILOG" #MODIFIED="1078424882" } } PAGE "" { PAGEHEADER { RECT (140,0,640,400) FREEID 126 } BODY { RECT 1, -1, 0 { VARIABLES { #OUTLINE_FILLING="1" } AREA (140,0,640,400) } TEXT 4, 0, 0 { TEXT "$#NAME" RECT (588,308,612,386) ALIGN 9 MARGINS (1,1) PARENT 3 ORIENTATION 8 } TEXT 9, 0, 0 { TEXT "$#NAME" RECT (568,297,592,386) ALIGN 9 MARGINS (1,1) PARENT 8 ORIENTATION 8 } TEXT 14, 0, 0 { TEXT "$#NAME" RECT (548,301,572,386) ALIGN 9 MARGINS (1,1) PARENT 13 ORIENTATION 8 } TEXT 19, 0, 0 { TEXT "$#NAME" RECT (528,290,552,386) ALIGN 9 MARGINS (1,1) PARENT 18 ORIENTATION 8 } TEXT 24, 0, 0 { TEXT "$#NAME" RECT (508,308,532,386) ALIGN 9 MARGINS (1,1) PARENT 23 ORIENTATION 8 } TEXT 29, 0, 0 { TEXT "$#NAME" RECT (488,297,512,386) ALIGN 9 MARGINS (1,1) PARENT 28 ORIENTATION 8 } TEXT 34, 0, 0 { TEXT "$#NAME" RECT (468,301,492,386) ALIGN 9 MARGINS (1,1) PARENT 33 ORIENTATION 8 } TEXT 39, 0, 0 { TEXT "$#NAME" RECT (448,290,472,386) ALIGN 9 MARGINS (1,1) PARENT 38 ORIENTATION 8 } TEXT 44, 0, 0 { TEXT "$#NAME" RECT (308,292,332,386) ALIGN 9 MARGINS (1,1) PARENT 43 ORIENTATION 8 } TEXT 49, 0, 0 { TEXT "$#NAME" RECT (288,303,312,386) ALIGN 9 MARGINS (1,1) PARENT 48 ORIENTATION 8 } TEXT 54, 0, 0 { TEXT "$#NAME" RECT (268,299,292,386) ALIGN 9 MARGINS (1,1) PARENT 53 ORIENTATION 8 } TEXT 59, 0, 0 { TEXT "$#NAME" RECT (248,310,272,386) ALIGN 9 MARGINS (1,1) PARENT 58 ORIENTATION 8 } TEXT 64, 0, 0 { TEXT "$#NAME" RECT (228,292,252,386) ALIGN 9 MARGINS (1,1) PARENT 63 ORIENTATION 8 } TEXT 69, 0, 0 { TEXT "$#NAME" RECT (208,303,232,386) ALIGN 9 MARGINS (1,1) PARENT 68 ORIENTATION 8 } TEXT 74, 0, 0 { TEXT "$#NAME" RECT (188,299,212,386) ALIGN 9 MARGINS (1,1) PARENT 73 ORIENTATION 8 } TEXT 79, 0, 0 { TEXT "$#NAME" RECT (168,310,192,386) ALIGN 9 MARGINS (1,1) PARENT 78 ORIENTATION 8 } TEXT 84, 0, 0 { TEXT "$#NAME" RECT (448,13,472,118) ALIGN 1 MARGINS (1,1) PARENT 83 ORIENTATION 6 } TEXT 89, 0, 0 { TEXT "$#NAME" RECT (428,13,452,111) ALIGN 1 MARGINS (1,1) PARENT 88 ORIENTATION 6 } TEXT 94, 0, 0 { TEXT "$#NAME" RECT (408,13,432,171) ALIGN 1 MARGINS (1,1) PARENT 93 ORIENTATION 6 } TEXT 99, 0, 0 { TEXT "$#NAME" RECT (388,13,412,164) ALIGN 1 MARGINS (1,1) PARENT 98 ORIENTATION 6 } TEXT 104, 0, 0 { TEXT "$#NAME" RECT (588,13,612,120) ALIGN 1 MARGINS (1,1) PARENT 103 ORIENTATION 6 } TEXT 109, 0, 0 { TEXT "$#NAME" RECT (568,13,592,132) ALIGN 1 MARGINS (1,1) PARENT 108 ORIENTATION 6 } TEXT 114, 0, 0 { TEXT "$#NAME" RECT (154,108,194,132) ALIGN 4 MARGINS (1,1) PARENT 113 } TEXT 119, 0, 0 { TEXT "$#NAME" RECT (154,148,207,172) ALIGN 4 MARGINS (1,1) PARENT 118 } TEXT 124, 0, 0 { TEXT "$#NAME" RECT (508,13,532,80) ALIGN 1 MARGINS (1,1) PARENT 123 ORIENTATION 6 } PIN 3, 0, 0 { COORD (600,400) VARIABLES { #DIRECTION="IN" #LABEL="In" #MODIFIED="1" #NAME="Enc15flg" #NUMBER="1" #SIDE="bottom" #VERILOG_DELAY="" #VERILOG_TYPE="wire" } LINE 1, 0, 0 { POINTS ( (-10,0), (10,0), (0,-10), (-10,0) ) FILL (0,(0,0,0),0) } } PIN 8, 0, 0 { COORD (580,400) VARIABLES { #DIRECTION="IN" #LABEL="In" #MODIFIED="1" #NAME="Enc133flg" #NUMBER="2" #SIDE="bottom" #VERILOG_DELAY="" #VERILOG_TYPE="wire" } LINE 1, 0, 0 { POINTS ( (-10,0), (10,0), (0,-10), (-10,0) ) FILL (0,(0,0,0),0) } } PIN 13, 0, 0 { COORD (560,400) VARIABLES { #DIRECTION="IN" #LABEL="In" #MODIFIED="1" #NAME="Hme15flg" #NUMBER="3" #SIDE="bottom" #VERILOG_DELAY="" #VERILOG_TYPE="wire" } LINE 1, 0, 0 { POINTS ( (-10,0), (10,0), (0,-10), (-10,0) ) FILL (0,(0,0,0),0) } } PIN 18, 0, 0 { COORD (540,400) VARIABLES { #DIRECTION="IN" #LABEL="In" #MODIFIED="1" #NAME="Hme133flg" #NUMBER="4" #SIDE="bottom" #VERILOG_DELAY="" #VERILOG_TYPE="wire" } LINE 1, 0, 0 { POINTS ( (-10,0), (10,0), (0,-10), (-10,0) ) FILL (0,(0,0,0),0) } } PIN 23, 0, 0 { COORD (520,400) VARIABLES { #DIRECTION="IN" #LABEL="In" #MODIFIED="1" #NAME="Enc05flg" #NUMBER="5" #SIDE="bottom" #VERILOG_DELAY="" #VERILOG_TYPE="wire" } LINE 1, 0, 0 { POINTS ( (-10,0), (10,0), (0,-10), (-10,0) ) FILL (0,(0,0,0),0) } } PIN 28, 0, 0 { COORD (500,400) VARIABLES { #DIRECTION="IN" #LABEL="In" #MODIFIED="1" #NAME="Enc033flg" #NUMBER="6" #SIDE="bottom" #VERILOG_DELAY="" #VERILOG_TYPE="wire" } LINE 1, 0, 0 { POINTS ( (-10,0), (10,0), (0,-10), (-10,0) ) FILL (0,(0,0,0),0) } } PIN 33, 0, 0 { COORD (480,400) VARIABLES { #DIRECTION="IN" #LABEL="In" #MODIFIED="1" #NAME="Hme05flg" #NUMBER="7" #SIDE="bottom" #VERILOG_DELAY="" #VERILOG_TYPE="wire" } LINE 1, 0, 0 { POINTS ( (-10,0), (10,0), (0,-10), (-10,0) ) FILL (0,(0,0,0),0) } } PIN 38, 0, 0 { COORD (460,400) VARIABLES { #DIRECTION="IN" #LABEL="In" #MODIFIED="1" #NAME="Hme033flg" #NUMBER="8" #SIDE="bottom" #VERILOG_DELAY="" #VERILOG_TYPE="wire" } LINE 1, 0, 0 { POINTS ( (-10,0), (10,0), (0,-10), (-10,0) ) FILL (0,(0,0,0),0) } } PIN 43, 0, 0 { COORD (320,400) VARIABLES { #DIRECTION="OUT" #LABEL="Out" #MODIFIED="1" #NAME="Hme033ctl" #NUMBER="9" #SIDE="bottom" #VERILOG_DELAY="" #VERILOG_TYPE="wire" } LINE 1, 0, 0 { POINTS ( (0,0), (-10,-10), (10,-10), (0,0) ) FILL (0,(0,0,0),0) } } PIN 48, 0, 0 { COORD (300,400) VARIABLES { #DIRECTION="OUT" #LABEL="Out" #MODIFIED="1" #NAME="Hme05ctl" #NUMBER="10" #SIDE="bottom" #VERILOG_DELAY="" #VERILOG_TYPE="wire" } LINE 1, 0, 0 { POINTS ( (0,0), (-10,-10), (10,-10), (0,0) ) FILL (0,(0,0,0),0) } } PIN 53, 0, 0 { COORD (280,400) VARIABLES { #DIRECTION="OUT" #LABEL="Out" #MODIFIED="1" #NAME="Enc033ctl" #NUMBER="11" #SIDE="bottom" #VERILOG_DELAY="" #VERILOG_TYPE="wire" } LINE 1, 0, 0 { POINTS ( (0,0), (-10,-10), (10,-10), (0,0) ) FILL (0,(0,0,0),0) } } PIN 58, 0, 0 { COORD (260,400) VARIABLES { #DIRECTION="OUT" #LABEL="Out" #MODIFIED="1" #NAME="Enc05ctl" #NUMBER="12" #SIDE="bottom" #VERILOG_DELAY="" #VERILOG_TYPE="wire" } LINE 1, 0, 0 { POINTS ( (0,0), (-10,-10), (10,-10), (0,0) ) FILL (0,(0,0,0),0) } } PIN 63, 0, 0 { COORD (240,400) VARIABLES { #DIRECTION="OUT" #LABEL="Out" #MODIFIED="1" #NAME="Hme133ctl" #NUMBER="13" #SIDE="bottom" #VERILOG_DELAY="" #VERILOG_TYPE="wire" } LINE 1, 0, 0 { POINTS ( (0,0), (-10,-10), (10,-10), (0,0) ) FILL (0,(0,0,0),0) } } PIN 68, 0, 0 { COORD (220,400) VARIABLES { #DIRECTION="OUT" #LABEL="Out" #MODIFIED="1" #NAME="Hme15ctl" #NUMBER="14" #SIDE="bottom" #VERILOG_DELAY="" #VERILOG_TYPE="wire" } LINE 1, 0, 0 { POINTS ( (0,0), (-10,-10), (10,-10), (0,0) ) FILL (0,(0,0,0),0) } } PIN 73, 0, 0 { COORD (200,400) VARIABLES { #DIRECTION="OUT" #LABEL="Out" #MODIFIED="1" #NAME="Enc133ctl" #NUMBER="15" #SIDE="bottom" #VERILOG_DELAY="" #VERILOG_TYPE="wire" } LINE 1, 0, 0 { POINTS ( (0,0), (-10,-10), (10,-10), (0,0) ) FILL (0,(0,0,0),0) } } PIN 78, 0, 0 { COORD (180,400) VARIABLES { #DIRECTION="OUT" #LABEL="Out" #MODIFIED="1" #NAME="Enc15ctl" #NUMBER="16" #SIDE="bottom" #VERILOG_DELAY="" #VERILOG_TYPE="wire" } LINE 1, 0, 0 { POINTS ( (0,0), (-10,-10), (10,-10), (0,0) ) FILL (0,(0,0,0),0) } } PIN 83, 0, 0 { COORD (460,0) VARIABLES { #DIRECTION="IN" #LABEL="In" #MODIFIED="1" #NAME="DCORIFGw" #NUMBER="17" #SIDE="top" #VERILOG_DELAY="" #VERILOG_TYPE="wire" } LINE 1, 0, 0 { POINTS ( (10,0), (-10,0), (0,10), (10,0) ) FILL (0,(0,0,0),0) } } PIN 88, 0, 0 { COORD (440,0) VARIABLES { #DIRECTION="IN" #LABEL="In" #MODIFIED="1" #NAME="DCORIFGr" #NUMBER="18" #SIDE="top" #VERILOG_DELAY="" #VERILOG_TYPE="wire" } LINE 1, 0, 0 { POINTS ( (10,0), (-10,0), (0,10), (10,0) ) FILL (0,(0,0,0),0) } } PIN 93, 0, 0 { COORD (420,0) VARIABLES { #DIRECTION="IN" #LABEL="In" #MODIFIED="1" #NAME="DCORENCPWRw" #NUMBER="19" #SIDE="top" #VERILOG_DELAY="" #VERILOG_TYPE="wire" } LINE 1, 0, 0 { POINTS ( (10,0), (-10,0), (0,10), (10,0) ) FILL (0,(0,0,0),0) } } PIN 98, 0, 0 { COORD (400,0) VARIABLES { #DIRECTION="IN" #LABEL="In" #MODIFIED="1" #NAME="DCORENCPWRr" #NUMBER="20" #SIDE="top" #VERILOG_DELAY="" #VERILOG_TYPE="wire" } LINE 1, 0, 0 { POINTS ( (10,0), (-10,0), (0,10), (10,0) ) FILL (0,(0,0,0),0) } } PIN 103, 0, 0 { COORD (600,0) VARIABLES { #DIRECTION="IN" #LABEL="Bus In" #MODIFIED="1" #NAME="inDATA(7:0)" #NUMBER="21" #SIDE="top" #VERILOG_DELAY="" #VERILOG_TYPE="wire" } LINE 1, 0, 0 { POINTS ( (10,0), (-10,0), (0,10), (10,0) ) FILL (0,(0,0,0),0) } } PIN 108, 0, 0 { COORD (580,0) VARIABLES { #DIRECTION="OUT" #LABEL="Bus Out" #MODIFIED="1" #NAME="outDATA(7:0)" #NUMBER="22" #SIDE="top" #VERILOG_DELAY="" #VERILOG_TYPE="wire" } LINE 1, 0, 0 { POINTS ( (0,0), (10,10), (-10,10), (0,0) ) FILL (0,(0,0,0),0) } } PIN 113, 0, 0 { COORD (140,120) VARIABLES { #DIRECTION="IN" #LABEL="In" #MODIFIED="1" #NAME="Mclk" #NUMBER="23" #SIDE="left" #VERILOG_DELAY="" #VERILOG_TYPE="wire" } LINE 1, 0, 0 { POINTS ( (0,-10), (0,10), (10,0), (0,-10) ) FILL (0,(0,0,0),0) } } PIN 118, 0, 0 { COORD (140,160) VARIABLES { #DIRECTION="IN" #LABEL="In" #MODIFIED="1" #NAME="Reset" #NUMBER="24" #SIDE="left" #VERILOG_DELAY="" #VERILOG_TYPE="wire" } LINE 1, 0, 0 { POINTS ( (0,-10), (0,10), (10,0), (0,-10) ) FILL (0,(0,0,0),0) } } PIN 123, 0, 0 { COORD (520,0) VARIABLES { #DIRECTION="OUT" #LABEL="Out" #MODIFIED="1" #NAME="PWRint" #NUMBER="25" #SIDE="top" #VERILOG_DELAY="" #VERILOG_TYPE="wire" } LINE 1, 0, 0 { POINTS ( (0,0), (10,10), (-10,10), (0,0) ) FILL (0,(0,0,0),0) } } } } } SYMBOL "#default" "Sensor" "Sensor" { HEADER { VARIABLES { #DESCRIPTION="" #FUB="1" #LANGUAGE="VERILOG" #MODIFIED="1100806702" } } PAGE "" { PAGEHEADER { RECT (0,0,200,300) FREEID 43 } BODY { RECT 1, -1, 0 { VARIABLES { #OUTLINE_FILLING="1" } AREA (0,0,200,300) } TEXT 4, 0, 0 { TEXT "$#NAME" RECT (14,68,54,92) ALIGN 4 MARGINS (1,1) PARENT 3 } TEXT 9, 0, 0 { TEXT "$#NAME" RECT (14,108,67,132) ALIGN 4 MARGINS (1,1) PARENT 8 } TEXT 14, 0, 0 { TEXT "$#NAME" RECT (148,14,172,121) ALIGN 1 MARGINS (1,1) PARENT 13 ORIENTATION 5 } TEXT 19, 0, 0 { TEXT "$#NAME" RECT (108,14,132,167) ALIGN 1 MARGINS (1,1) PARENT 18 ORIENTATION 5 } TEXT 24, 0, 0 { TEXT "$#NAME" RECT (148,214,172,287) ALIGN 9 MARGINS (1,1) PARENT 23 ORIENTATION 5 } TEXT 29, 0, 0 { TEXT "$#NAME" RECT (108,223,132,287) ALIGN 9 MARGINS (1,1) PARENT 28 ORIENTATION 5 } TEXT 34, 0, 0 { TEXT "$#NAME" RECT (68,222,92,287) ALIGN 9 MARGINS (1,1) PARENT 33 ORIENTATION 5 } TEXT 39, 0, 0 { TEXT "$#NAME" RECT (28,213,52,287) ALIGN 9 MARGINS (1,1) PARENT 38 ORIENTATION 5 } TEXT 42, 0, 0 { TEXT "$#NAME" RECT (14,148,82,172) ALIGN 4 MARGINS (1,1) PARENT 41 } PIN 3, 0, 0 { COORD (0,80) VARIABLES { #DIRECTION="IN" #LABEL="In" #MODIFIED="1" #NAME="Mclk" #NUMBER="1" #SIDE="left" #VERILOG_DELAY="" #VERILOG_TYPE="wire" } LINE 1, 0, 0 { POINTS ( (0,-10), (0,10), (10,0), (0,-10) ) FILL (0,(0,0,0),0) } } PIN 8, 0, 0 { COORD (0,120) VARIABLES { #DIRECTION="IN" #LABEL="In" #MODIFIED="1" #NAME="Reset" #NUMBER="2" #SIDE="left" #VERILOG_DELAY="" #VERILOG_TYPE="wire" } LINE 1, 0, 0 { POINTS ( (0,-10), (0,10), (10,0), (0,-10) ) FILL (0,(0,0,0),0) } } PIN 13, 0, 0 { COORD (160,0) VARIABLES { #DIRECTION="IN" #LABEL="Bus In" #MODIFIED="1" #NAME="inDATA(3:0)" #NUMBER="3" #SIDE="top" #VERILOG_DELAY="" #VERILOG_TYPE="wire" } LINE 1, 0, 0 { POINTS ( (10,0), (-10,0), (0,10), (10,0) ) FILL (0,(0,0,0),0) } } PIN 18, 0, 0 { COORD (120,0) VARIABLES { #DIRECTION="IN" #LABEL="In" #MODIFIED="1" #NAME="DCORSENSORw" #NUMBER="4" #SIDE="top" #VERILOG_DELAY="" #VERILOG_TYPE="wire" } LINE 1, 0, 0 { POINTS ( (10,0), (-10,0), (0,10), (10,0) ) FILL (0,(0,0,0),0) } } PIN 23, 0, 0 { COORD (160,300) VARIABLES { #DIRECTION="OUT" #LABEL="Out" #MODIFIED="1" #NAME="TmpSlct" #NUMBER="5" #SIDE="bottom" #VERILOG_DELAY="" #VERILOG_TYPE="wire" } LINE 1, 0, 0 { POINTS ( (0,0), (-10,-10), (10,-10), (0,0) ) FILL (0,(0,0,0),0) } } PIN 28, 0, 0 { COORD (120,300) VARIABLES { #DIRECTION="OUT" #LABEL="Out" #MODIFIED="1" #NAME="TmpEn" #NUMBER="6" #SIDE="bottom" #VERILOG_DELAY="" #VERILOG_TYPE="wire" } LINE 1, 0, 0 { POINTS ( (0,0), (-10,-10), (10,-10), (0,0) ) FILL (0,(0,0,0),0) } } PIN 33, 0, 0 { COORD (80,300) VARIABLES { #DIRECTION="OUT" #LABEL="Out" #MODIFIED="1" #NAME="PresEn" #NUMBER="7" #SIDE="bottom" #VERILOG_DELAY="" #VERILOG_TYPE="wire" } LINE 1, 0, 0 { POINTS ( (0,0), (-10,-10), (10,-10), (0,0) ) FILL (0,(0,0,0),0) } } PIN 38, 0, 0 { COORD (40,300) VARIABLES { #DIRECTION="OUT" #LABEL="Out" #MODIFIED="1" #NAME="PresSlct" #NUMBER="8" #SIDE="bottom" #VERILOG_DELAY="" #VERILOG_TYPE="wire" } LINE 1, 0, 0 { POINTS ( (0,0), (-10,-10), (10,-10), (0,0) ) FILL (0,(0,0,0),0) } } PIN 41, 0, 0 { COORD (0,160) VARIABLES { #DIRECTION="IN" #LABEL="In" #MODIFIED="1" #NAME="MReset" #NUMBER="9" #SIDE="left" #VERILOG_DELAY="" #VERILOG_TYPE="wire" } LINE 1, 0, 0 { POINTS ( (0,-10), (0,10), (10,0), (0,-10) ) FILL (0,(0,0,0),0) } } } } } SYMBOL "#default" "Servos" "Servos" { HEADER { VARIABLES { #DESCRIPTION="" #FUB="1" #LANGUAGE="VERILOG" #MODIFIED="1101740901" } } PAGE "" { PAGEHEADER { RECT (0,0,600,580) FREEID 174 } BODY { RECT 1, -1, 0 { VARIABLES { #OUTLINE_FILLING="1" } AREA (0,0,600,579) } TEXT 7, 0, 0 { TEXT "$#NAME" RECT (15,350,68,374) ALIGN 4 MARGINS (1,1) PARENT 6 } TEXT 9, 0, 0 { TEXT "$#NAME" RECT (15,310,55,334) ALIGN 4 MARGINS (1,1) PARENT 8 } TEXT 15, 0, 0 { TEXT "$#NAME" RECT (410,418,434,565) ALIGN 9 MARGINS (1,1) PARENT 14 ORIENTATION 8 } TEXT 17, 0, 0 { TEXT "$#NAME" RECT (450,402,474,565) ALIGN 9 MARGINS (1,1) PARENT 16 ORIENTATION 8 } TEXT 19, 0, 0 { TEXT "$#NAME" RECT (430,402,454,565) ALIGN 9 MARGINS (1,1) PARENT 18 ORIENTATION 8 } TEXT 21, 0, 0 { TEXT "$#NAME" RECT (546,15,570,122) ALIGN 1 MARGINS (1,1) PARENT 20 ORIENTATION 6 } TEXT 48, 0, 0 { TEXT "$#NAME" RECT (508,13,532,132) ALIGN 1 MARGINS (1,1) PARENT 47 ORIENTATION 6 } TEXT 119, 0, 0 { TEXT "$#NAME" RECT (366,15,390,177) ALIGN 1 MARGINS (1,1) PARENT 118 ORIENTATION 5 } TEXT 121, 0, 0 { TEXT "$#NAME" RECT (406,15,430,175) ALIGN 1 MARGINS (1,1) PARENT 120 ORIENTATION 5 } TEXT 125, 0, 0 { TEXT "$#NAME" RECT (346,15,370,177) ALIGN 1 MARGINS (1,1) PARENT 124 ORIENTATION 5 } TEXT 127, 0, 0 { TEXT "$#NAME" RECT (326,15,350,175) ALIGN 1 MARGINS (1,1) PARENT 126 ORIENTATION 5 } TEXT 131, 0, 0 { TEXT "$#NAME" RECT (446,15,470,201) ALIGN 1 MARGINS (1,1) PARENT 130 ORIENTATION 5 } TEXT 135, 0, 0 { TEXT "$#NAME" RECT (266,15,290,201) ALIGN 1 MARGINS (1,1) PARENT 134 ORIENTATION 5 } TEXT 139, 0, 0 { TEXT "$#NAME" RECT (246,15,270,164) ALIGN 1 MARGINS (1,1) PARENT 138 ORIENTATION 5 } TEXT 141, 0, 0 { TEXT "$#NAME" RECT (226,15,250,113) ALIGN 1 MARGINS (1,1) PARENT 140 ORIENTATION 5 } TEXT 143, 0, 0 { TEXT "$#NAME" RECT (208,20,232,125) ALIGN 1 MARGINS (1,1) PARENT 142 ORIENTATION 5 } TEXT 145, 0, 0 { TEXT "$#NAME" RECT (390,490,414,565) ALIGN 9 MARGINS (1,1) PARENT 144 ORIENTATION 8 } TEXT 149, 0, 0 { TEXT "$#NAME" RECT (250,418,274,565) ALIGN 9 MARGINS (1,1) PARENT 148 ORIENTATION 8 } TEXT 151, 0, 0 { TEXT "$#NAME" RECT (230,488,254,565) ALIGN 9 MARGINS (1,1) PARENT 150 ORIENTATION 8 } TEXT 153, 0, 0 { TEXT "$#NAME" RECT (290,402,314,565) ALIGN 9 MARGINS (1,1) PARENT 152 ORIENTATION 8 } TEXT 155, 0, 0 { TEXT "$#NAME" RECT (270,402,294,565) ALIGN 9 MARGINS (1,1) PARENT 154 ORIENTATION 8 } TEXT 157, 0, 0 { TEXT "$#NAME" RECT (106,15,130,89) ALIGN 1 MARGINS (1,1) PARENT 156 ORIENTATION 6 } TEXT 159, 0, 0 { TEXT "$#NAME" RECT (86,15,110,89) ALIGN 1 MARGINS (1,1) PARENT 158 ORIENTATION 6 } TEXT 161, 0, 0 { TEXT "$#NAME" RECT (46,15,70,88) ALIGN 1 MARGINS (1,1) PARENT 160 ORIENTATION 6 } TEXT 163, 0, 0 { TEXT "$#NAME" RECT (26,15,50,88) ALIGN 1 MARGINS (1,1) PARENT 162 ORIENTATION 6 } TEXT 166, 0, 0 { TEXT "$#NAME" RECT (148,14,172,103) ALIGN 1 MARGINS (1,1) PARENT 165 ORIENTATION 5 } TEXT 168, 0, 0 { TEXT "$#NAME" RECT (426,15,450,203) ALIGN 1 MARGINS (1,1) PARENT 167 ORIENTATION 5 } TEXT 170, 0, 0 { TEXT "$#NAME" RECT (286,15,310,203) ALIGN 1 MARGINS (1,1) PARENT 169 ORIENTATION 5 } TEXT 172, 0, 0 { TEXT "$#NAME" RECT (550,538,574,565) ALIGN 9 MARGINS (1,1) PARENT 171 ORIENTATION 7 } PIN 6, 0, 0 { COORD (0,360) VARIABLES { #DIRECTION="IN" #LENGTH="0" #MODIFIED="1" #NAME="Reset" #NUMBER="1" #SIDE="left" } LINE 2, 0, 0 { POINTS ( (0,-10), (0,10), (10,0), (0,-10) ) } } PIN 8, 0, 0 { COORD (0,320) VARIABLES { #DIRECTION="IN" #LENGTH="0" #MODIFIED="1" #NAME="Mclk" #NUMBER="2" #SIDE="left" #VERILOG_DELAY="" } LINE 2, 0, 0 { POINTS ( (0,-10), (0,10), (10,0), (0,-10) ) } } PIN 14, 0, 0 { COORD (420,580) VARIABLES { #DIRECTION="IN" #LENGTH="0" #MODIFIED="1" #NAME="Home_Encoder1" #NUMBER="3" #SIDE="bottom" } LINE 2, 0, 0 { POINTS ( (-10,0), (10,0), (0,-10), (-10,0) ) } } PIN 16, 0, 0 { COORD (460,580) VARIABLES { #DIRECTION="IN" #LENGTH="0" #MODIFIED="1" #NAME="PhaseA_Encoder1" #NUMBER="4" #SIDE="bottom" } LINE 2, 0, 0 { POINTS ( (-10,0), (10,0), (0,-10), (-10,0) ) } } PIN 18, 0, 0 { COORD (440,580) VARIABLES { #DIRECTION="IN" #LENGTH="0" #MODIFIED="1" #NAME="PhaseB_Encoder1" #NUMBER="5" #SIDE="bottom" } LINE 2, 0, 0 { POINTS ( (-10,0), (10,0), (0,-10), (-10,0) ) } } PIN 20, 0, 0 { COORD (560,0) VARIABLES { #DIRECTION="IN" #DOWNTO="1" #LABEL="Bus In" #LENGTH="0" #MODIFIED="1" #NAME="inDATA(7:0)" #NUMBER="6" #SIDE="top" #VERILOG_DELAY="" } LINE 2, 0, 0 { POINTS ( (10,0), (-10,0), (0,10), (10,0) ) } } PIN 47, 0, 0 { COORD (520,0) VARIABLES { #DIRECTION="OUT" #DOWNTO="1" #LABEL="Bus Out" #MODIFIED="1" #NAME="outDATA(7:0)" #NUMBER="10" #SIDE="top" #VERILOG_DELAY="" } LINE 2, 0, 0 { POINTS ( (0,0), (10,10), (-10,10), (0,0) ) } } PIN 118, 0, 0 { COORD (380,0) VARIABLES { #DIRECTION="IN" #LENGTH="0" #MODIFIED="1" #NAME="DCOR0CNTHIGHr" #NUMBER="13" #SIDE="top" } LINE 2, 0, 0 { POINTS ( (10,0), (-10,0), (0,10), (10,0) ) } } PIN 120, 0, 0 { COORD (420,0) VARIABLES { #DIRECTION="IN" #LENGTH="0" #MODIFIED="1" #NAME="DCOR0CNTLOWr" #NUMBER="14" #SIDE="top" } LINE 2, 0, 0 { POINTS ( (10,0), (-10,0), (0,10), (10,0) ) } } PIN 124, 0, 0 { COORD (360,0) VARIABLES { #DIRECTION="IN" #LENGTH="0" #MODIFIED="1" #NAME="DCOR1CNTHIGHr" #NUMBER="16" #SIDE="top" } LINE 2, 0, 0 { POINTS ( (10,0), (-10,0), (0,10), (10,0) ) } } PIN 126, 0, 0 { COORD (340,0) VARIABLES { #DIRECTION="IN" #LENGTH="0" #MODIFIED="1" #NAME="DCOR1CNTLOWr" #NUMBER="17" #SIDE="top" } LINE 2, 0, 0 { POINTS ( (10,0), (-10,0), (0,10), (10,0) ) } } PIN 130, 0, 0 { COORD (460,0) VARIABLES { #DIRECTION="IN" #LENGTH="0" #MODIFIED="1" #NAME="DCOR0THRESLOWr" #NUMBER="19" #SIDE="top" } LINE 2, 0, 0 { POINTS ( (10,0), (-10,0), (0,10), (10,0) ) } } PIN 134, 0, 0 { COORD (280,0) VARIABLES { #DIRECTION="IN" #LENGTH="0" #MODIFIED="1" #NAME="DCOR1THRESLOWr" #NUMBER="21" #SIDE="top" } LINE 2, 0, 0 { POINTS ( (10,0), (-10,0), (0,10), (10,0) ) } } PIN 138, 0, 0 { COORD (260,0) VARIABLES { #DIRECTION="IN" #LENGTH="0" #MODIFIED="1" #NAME="DCORENCCTLw" #NUMBER="23" #SIDE="top" } LINE 2, 0, 0 { POINTS ( (10,0), (-10,0), (0,10), (10,0) ) } } PIN 140, 0, 0 { COORD (240,0) VARIABLES { #DIRECTION="IN" #LENGTH="0" #MODIFIED="1" #NAME="DCORIFGr" #NUMBER="24" #SIDE="top" } LINE 2, 0, 0 { POINTS ( (10,0), (-10,0), (0,10), (10,0) ) } } PIN 142, 0, 0 { COORD (220,0) VARIABLES { #DIRECTION="IN" #LENGTH="0" #MODIFIED="1" #NAME="DCORIFGw" #NUMBER="25" #SIDE="top" } LINE 2, 0, 0 { POINTS ( (10,0), (-10,0), (0,10), (10,0) ) } } PIN 144, 0, 0 { COORD (400,580) VARIABLES { #DIRECTION="IN" #LENGTH="0" #MODIFIED="1" #NAME="Motorin1" #NUMBER="26" #SIDE="bottom" } LINE 2, 0, 0 { POINTS ( (-10,0), (10,0), (0,-10), (-10,0) ) } } PIN 148, 0, 0 { COORD (260,580) VARIABLES { #DIRECTION="IN" #LENGTH="0" #MODIFIED="1" #NAME="Home_Encoder0" #NUMBER="0" #SIDE="bottom" } LINE 2, 0, 0 { POINTS ( (-10,0), (10,0), (0,-10), (-10,0) ) } } PIN 150, 0, 0 { COORD (240,580) VARIABLES { #DIRECTION="IN" #LENGTH="0" #MODIFIED="1" #NAME="MotorIn0" #NUMBER="0" #SIDE="bottom" } LINE 2, 0, 0 { POINTS ( (-10,0), (10,0), (0,-10), (-10,0) ) } } PIN 152, 0, 0 { COORD (300,580) VARIABLES { #DIRECTION="IN" #LENGTH="0" #MODIFIED="1" #NAME="PhaseA_Encoder0" #NUMBER="0" #SIDE="bottom" } LINE 2, 0, 0 { POINTS ( (-10,0), (10,0), (0,-10), (-10,0) ) } } PIN 154, 0, 0 { COORD (280,580) VARIABLES { #DIRECTION="IN" #LENGTH="0" #MODIFIED="1" #NAME="PhaseB_Encoder0" #NUMBER="0" #SIDE="bottom" } LINE 2, 0, 0 { POINTS ( (-10,0), (10,0), (0,-10), (-10,0) ) } } PIN 156, 0, 0 { COORD (120,0) VARIABLES { #DIRECTION="OUT" #LENGTH="0" #MODIFIED="1" #NAME="Hfound0" #NUMBER="0" #SIDE="top" } LINE 2, 0, 0 { POINTS ( (0,0), (10,10), (-10,10), (0,0) ) } } PIN 158, 0, 0 { COORD (100,0) VARIABLES { #DIRECTION="OUT" #LENGTH="0" #MODIFIED="1" #NAME="Hfound1" #NUMBER="0" #SIDE="top" } LINE 2, 0, 0 { POINTS ( (0,0), (10,10), (-10,10), (0,0) ) } } PIN 160, 0, 0 { COORD (60,0) VARIABLES { #DIRECTION="OUT" #LENGTH="0" #MODIFIED="1" #NAME="Tfound0" #NUMBER="0" #SIDE="top" } LINE 2, 0, 0 { POINTS ( (0,0), (10,10), (-10,10), (0,0) ) } } PIN 162, 0, 0 { COORD (40,0) VARIABLES { #DIRECTION="OUT" #LENGTH="0" #MODIFIED="1" #NAME="Tfound1" #NUMBER="0" #SIDE="top" } LINE 2, 0, 0 { POINTS ( (0,0), (10,10), (-10,10), (0,0) ) } } PIN 165, 0, 0 { COORD (160,0) VARIABLES { #DIRECTION="IN" #FAMILY="Fub" #MODIFIED="1" #NAME="ASleading" #NUMBER="0" #SIDE="top" #VERILOG_DELAY="" } LINE 2, 0, 0 { POINTS ( (10,0), (-10,0), (0,10), (10,0) ) } } PIN 167, 0, 0 { COORD (440,0) VARIABLES { #DIRECTION="IN" #LENGTH="0" #MODIFIED="1" #NAME="DCOR0THRESHIGHr" #NUMBER="0" #SIDE="top" } LINE 2, 0, 0 { POINTS ( (10,0), (-10,0), (0,10), (10,0) ) } } PIN 169, 0, 0 { COORD (300,0) VARIABLES { #DIRECTION="IN" #LENGTH="0" #MODIFIED="1" #NAME="DCOR1THRESHIGHr" #NUMBER="0" #SIDE="top" } LINE 2, 0, 0 { POINTS ( (10,0), (-10,0), (0,10), (10,0) ) } } PIN 171, 0, 0 { COORD (560,580) VARIABLES { #DIRECTION="OUT" #LENGTH="0" #MODIFIED="1" #NAME="TP" #NUMBER="0" #SIDE="bottom" #VERILOG_TYPE="wire" } LINE 2, 0, 0 { POINTS ( (0,0), (10,-10), (-10,-10), (0,0) ) } } } } } SYMBOL "#default" "U21AddDecode" "U21AddDecode" { HEADER { VARIABLES { #DESCRIPTION="" #FUB="1" #LANGUAGE="VERILOG" #MODIFIED="1083165271" } } PAGE "" { PAGEHEADER { RECT (0,0,560,320) FREEID 137 } BODY { RECT 1, -1, 0 { VARIABLES { #OUTLINE_FILLING="1" } AREA (0,0,560,320) } TEXT 4, 0, 0 { TEXT "$#NAME" RECT (28,14,52,105) ALIGN 1 MARGINS (1,1) PARENT 3 ORIENTATION 5 } TEXT 9, 0, 0 { TEXT "$#NAME" RECT (288,14,312,119) ALIGN 1 MARGINS (1,1) PARENT 8 ORIENTATION 5 } TEXT 14, 0, 0 { TEXT "$#NAME" RECT (268,14,292,112) ALIGN 1 MARGINS (1,1) PARENT 13 ORIENTATION 5 } TEXT 29, 0, 0 { TEXT "$#NAME" RECT (88,14,112,174) ALIGN 1 MARGINS (1,1) PARENT 28 ORIENTATION 5 } TEXT 39, 0, 0 { TEXT "$#NAME" RECT (128,14,152,176) ALIGN 1 MARGINS (1,1) PARENT 38 ORIENTATION 5 } TEXT 44, 0, 0 { TEXT "$#NAME" RECT (168,14,192,174) ALIGN 1 MARGINS (1,1) PARENT 43 ORIENTATION 5 } TEXT 54, 0, 0 { TEXT "$#NAME" RECT (148,20,172,182) ALIGN 1 MARGINS (1,1) PARENT 53 ORIENTATION 5 } TEXT 59, 0, 0 { TEXT "$#NAME" RECT (48,14,72,200) ALIGN 1 MARGINS (1,1) PARENT 58 ORIENTATION 5 } TEXT 64, 0, 0 { TEXT "$#NAME" RECT (68,14,92,202) ALIGN 1 MARGINS (1,1) PARENT 63 ORIENTATION 5 } TEXT 69, 0, 0 { TEXT "$#NAME" RECT (228,14,252,200) ALIGN 1 MARGINS (1,1) PARENT 68 ORIENTATION 5 } TEXT 74, 0, 0 { TEXT "$#NAME" RECT (208,14,232,202) ALIGN 1 MARGINS (1,1) PARENT 73 ORIENTATION 5 } TEXT 79, 0, 0 { TEXT "$#NAME" RECT (348,14,372,165) ALIGN 1 MARGINS (1,1) PARENT 78 ORIENTATION 5 } TEXT 84, 0, 0 { TEXT "$#NAME" RECT (328,14,352,172) ALIGN 1 MARGINS (1,1) PARENT 83 ORIENTATION 5 } TEXT 89, 0, 0 { TEXT "$#NAME" RECT (408,14,432,154) ALIGN 1 MARGINS (1,1) PARENT 88 ORIENTATION 5 } TEXT 94, 0, 0 { TEXT "$#NAME" RECT (308,14,332,126) ALIGN 1 MARGINS (1,1) PARENT 93 ORIENTATION 5 } TEXT 104, 0, 0 { TEXT "$#NAME" RECT (448,14,472,110) ALIGN 1 MARGINS (1,1) PARENT 103 ORIENTATION 5 } TEXT 109, 0, 0 { TEXT "$#NAME" RECT (348,279,372,307) ALIGN 9 MARGINS (1,1) PARENT 108 ORIENTATION 7 } TEXT 114, 0, 0 { TEXT "$#NAME" RECT (388,277,412,307) ALIGN 9 MARGINS (1,1) PARENT 113 ORIENTATION 7 } TEXT 119, 0, 0 { TEXT "$#NAME" RECT (428,272,452,307) ALIGN 9 MARGINS (1,1) PARENT 118 ORIENTATION 7 } TEXT 121, 0, 0 { TEXT "$#NAME" RECT (366,15,390,143) ALIGN 1 MARGINS (1,1) PARENT 120 ORIENTATION 6 } TEXT 123, 0, 0 { TEXT "$#NAME" RECT (246,15,270,164) ALIGN 1 MARGINS (1,1) PARENT 122 ORIENTATION 6 } TEXT 126, 0, 0 { TEXT "$#NAME" RECT (388,14,412,149) ALIGN 1 MARGINS (1,1) PARENT 125 ORIENTATION 5 } TEXT 129, 0, 0 { TEXT "$#NAME" RECT (188,14,212,167) ALIGN 1 MARGINS (1,1) PARENT 128 ORIENTATION 5 } TEXT 132, 0, 0 { TEXT "$#NAME" RECT (428,14,452,121) ALIGN 1 MARGINS (1,1) PARENT 131 ORIENTATION 5 } PIN 3, 0, 0 { COORD (40,0) VARIABLES { #DIRECTION="OUT" #LABEL="Out" #MODIFIED="1" #NAME="DCORIEw" #NUMBER="1" #SIDE="top" #VERILOG_DELAY="" #VERILOG_TYPE="wire" } LINE 2, 0, 0 { POINTS ( (0,0), (10,10), (-10,10), (0,0) ) } } PIN 8, 0, 0 { COORD (300,0) VARIABLES { #DIRECTION="OUT" #LABEL="Out" #MODIFIED="1" #NAME="DCORIFGw" #NUMBER="2" #SIDE="top" #VERILOG_DELAY="" #VERILOG_TYPE="wire" } LINE 2, 0, 0 { POINTS ( (0,0), (10,10), (-10,10), (0,0) ) } } PIN 13, 0, 0 { COORD (280,0) VARIABLES { #DIRECTION="OUT" #LABEL="Out" #MODIFIED="1" #NAME="DCORIFGr" #NUMBER="3" #SIDE="top" #VERILOG_DELAY="" #VERILOG_TYPE="wire" } LINE 2, 0, 0 { POINTS ( (0,0), (10,10), (-10,10), (0,0) ) } } PIN 28, 0, 0 { COORD (100,0) VARIABLES { #DIRECTION="OUT" #LABEL="Out" #MODIFIED="1" #NAME="DCOR0CNTLOWr" #NUMBER="4" #SIDE="top" #VERILOG_DELAY="" #VERILOG_TYPE="wire" } LINE 2, 0, 0 { POINTS ( (0,0), (10,10), (-10,10), (0,0) ) } } PIN 38, 0, 0 { COORD (140,0) VARIABLES { #DIRECTION="OUT" #LABEL="Out" #MODIFIED="1" #NAME="DCOR0CNTHIGHr" #NUMBER="6" #SIDE="top" #VERILOG_DELAY="" #VERILOG_TYPE="wire" } LINE 2, 0, 0 { POINTS ( (0,0), (10,10), (-10,10), (0,0) ) } } PIN 43, 0, 0 { COORD (180,0) VARIABLES { #DIRECTION="OUT" #LABEL="Out" #MODIFIED="1" #NAME="DCOR1CNTLOWr" #NUMBER="7" #SIDE="top" #VERILOG_DELAY="" #VERILOG_TYPE="wire" } LINE 2, 0, 0 { POINTS ( (0,0), (10,10), (-10,10), (0,0) ) } } PIN 53, 0, 0 { COORD (160,0) VARIABLES { #DIRECTION="OUT" #LABEL="Out" #MODIFIED="1" #NAME="DCOR1CNTHIGHr" #NUMBER="9" #SIDE="top" #VERILOG_DELAY="" #VERILOG_TYPE="wire" } LINE 2, 0, 0 { POINTS ( (0,0), (10,10), (-10,10), (0,0) ) } } PIN 58, 0, 0 { COORD (60,0) VARIABLES { #DIRECTION="OUT" #LABEL="Out" #MODIFIED="1" #NAME="DCOR0THRESLOWr" #NUMBER="10" #SIDE="top" #VERILOG_DELAY="" #VERILOG_TYPE="wire" } LINE 2, 0, 0 { POINTS ( (0,0), (10,10), (-10,10), (0,0) ) } } PIN 63, 0, 0 { COORD (80,0) VARIABLES { #DIRECTION="OUT" #LABEL="Out" #MODIFIED="1" #NAME="DCOR0THRESHIGHr" #NUMBER="11" #SIDE="top" #VERILOG_DELAY="" #VERILOG_TYPE="wire" } LINE 2, 0, 0 { POINTS ( (0,0), (10,10), (-10,10), (0,0) ) } } PIN 68, 0, 0 { COORD (240,0) VARIABLES { #DIRECTION="OUT" #LABEL="Out" #MODIFIED="1" #NAME="DCOR1THRESLOWr" #NUMBER="12" #SIDE="top" #VERILOG_DELAY="" #VERILOG_TYPE="wire" } LINE 2, 0, 0 { POINTS ( (0,0), (10,10), (-10,10), (0,0) ) } } PIN 73, 0, 0 { COORD (220,0) VARIABLES { #DIRECTION="OUT" #LABEL="Out" #MODIFIED="1" #NAME="DCOR1THRESHIGHr" #NUMBER="13" #SIDE="top" #VERILOG_DELAY="" #VERILOG_TYPE="wire" } LINE 2, 0, 0 { POINTS ( (0,0), (10,10), (-10,10), (0,0) ) } } PIN 78, 0, 0 { COORD (360,0) VARIABLES { #DIRECTION="OUT" #LABEL="Out" #MODIFIED="1" #NAME="DCORENCPWRr" #NUMBER="14" #SIDE="top" #VERILOG_DELAY="" #VERILOG_TYPE="wire" } LINE 2, 0, 0 { POINTS ( (0,0), (10,10), (-10,10), (0,0) ) } } PIN 83, 0, 0 { COORD (340,0) VARIABLES { #DIRECTION="OUT" #LABEL="Out" #MODIFIED="1" #NAME="DCORENCPWRw" #NUMBER="15" #SIDE="top" #VERILOG_DELAY="" #VERILOG_TYPE="wire" } LINE 2, 0, 0 { POINTS ( (0,0), (10,10), (-10,10), (0,0) ) } } PIN 88, 0, 0 { COORD (420,0) VARIABLES { #DIRECTION="OUT" #LABEL="Out" #MODIFIED="1" #NAME="DCORCONFIGr" #NUMBER="16" #SIDE="top" #VERILOG_DELAY="" #VERILOG_TYPE="wire" } LINE 2, 0, 0 { POINTS ( (0,0), (10,10), (-10,10), (0,0) ) } } PIN 93, 0, 0 { COORD (320,0) VARIABLES { #DIRECTION="OUT" #LABEL="Out" #MODIFIED="1" #NAME="DCOROUTw" #NUMBER="17" #SIDE="top" #VERILOG_DELAY="" #VERILOG_TYPE="wire" } LINE 2, 0, 0 { POINTS ( (0,0), (10,10), (-10,10), (0,0) ) } } PIN 103, 0, 0 { COORD (460,0) VARIABLES { #DIRECTION="IN" #DOWNTO="1" #LABEL="Bus In" #MODIFIED="1" #NAME="ADDR(7:0)" #NUMBER="18" #SIDE="top" #VERILOG_DELAY="" #VERILOG_TYPE="wire" } LINE 2, 0, 0 { POINTS ( (-10,0), (10,0), (0,10), (-10,0) ) } } PIN 108, 0, 0 { COORD (360,320) VARIABLES { #DIRECTION="IN" #LABEL="In" #MODIFIED="1" #NAME="AS" #NUMBER="19" #SIDE="bottom" #VERILOG_DELAY="" #VERILOG_TYPE="wire" } LINE 2, 0, 0 { POINTS ( (10,0), (-10,0), (0,-10), (10,0) ) } } PIN 113, 0, 0 { COORD (400,320) VARIABLES { #DIRECTION="IN" #LABEL="In" #MODIFIED="1" #NAME="RD" #NUMBER="20" #SIDE="bottom" #VERILOG_DELAY="" #VERILOG_TYPE="wire" } LINE 2, 0, 0 { POINTS ( (10,0), (-10,0), (0,-10), (10,0) ) } } PIN 118, 0, 0 { COORD (440,320) VARIABLES { #DIRECTION="IN" #LABEL="In" #MODIFIED="1" #NAME="WR" #NUMBER="21" #SIDE="bottom" #VERILOG_DELAY="" #VERILOG_TYPE="wire" } LINE 2, 0, 0 { POINTS ( (10,0), (-10,0), (0,-10), (10,0) ) } } PIN 120, 0, 0 { COORD (380,0) VARIABLES { #DIRECTION="OUT" #LENGTH="0" #MODIFIED="1" #NAME="DCORLIMITSr" #NUMBER="22" #SIDE="top" #VERILOG_TYPE="wire" } LINE 2, 0, 0 { POINTS ( (0,0), (-10,10), (10,10), (0,0) ) } } PIN 122, 0, 0 { COORD (260,0) VARIABLES { #DIRECTION="OUT" #LENGTH="0" #MODIFIED="1" #NAME="DCORENCCTLw" #NUMBER="23" #SIDE="top" #VERILOG_TYPE="wire" } LINE 2, 0, 0 { POINTS ( (0,0), (-10,10), (10,10), (0,0) ) } } PIN 125, 0, 0 { COORD (400,0) VARIABLES { #DIRECTION="OUT" #LABEL="Out" #MODIFIED="1" #NAME="DCORI2CCNTr" #NUMBER="24" #SIDE="top" #VERILOG_DELAY="" #VERILOG_TYPE="wire" } LINE 1, 0, 0 { POINTS ( (0,0), (10,10), (-10,10), (0,0) ) FILL (0,(0,0,0),0) } } PIN 128, 0, 0 { COORD (200,0) VARIABLES { #DIRECTION="OUT" #LABEL="Out" #MODIFIED="1" #NAME="DCORSENSORw" #NUMBER="25" #SIDE="top" #VERILOG_DELAY="" #VERILOG_TYPE="wire" } LINE 1, 0, 0 { POINTS ( (0,0), (10,10), (-10,10), (0,0) ) FILL (0,(0,0,0),0) } } PIN 131, 0, 0 { COORD (440,0) VARIABLES { #DIRECTION="OUT" #FAMILY="Fub" #NAME="DCORLINTr" #NUMBER="0" #VERILOG_TYPE="wire" } LINE 1, 0, 0 { POINTS ( (-10,10), (10,10), (0,0) ) } } } } } } PAGE "" { PAGEHEADER { PAGESIZE (6800,4400) MARGINS (200,200,200,200) RECT (0,0,100,200) } BODY { INSTANCE 29, 0, 0 { VARIABLES { #COMPONENT="Servos" #LIBRARY="#default" #REFERENCE="U1" #SYMBOL="Servos" } COORD (3660,1800) VERTEXES ( (14,7042), (16,7044), (18,7046), (20,7047), (47,7048), (118,7050), (120,7052), (124,7054), (126,7056), (130,7058), (134,7060), (138,7062), (140,7063), (142,7064), (144,7065), (148,7066), (150,7067), (152,7069), (154,7071), (156,7073), (158,7075), (160,7077), (162,7079), (165,7081), (167,7083), (169,7085) ) } TEXT 30, 0, 0 { TEXT "$#COMPONENT" RECT (3660,2380,3751,2415) MARGINS (1,1) PARENT 29 } TEXT 31, 0, 0 { TEXT "$#REFERENCE" RECT (3660,1764,3699,1799) ALIGN 8 MARGINS (1,1) PARENT 29 } INSTANCE 116, 0, 0 { VARIABLES { #COMPONENT="Interface" #LIBRARY="#default" #REFERENCE="U2" #SYMBOL="Interface" } COORD (5500,1640) VERTEXES ( (3,2882), (28,1562), (33,3543), (44,1918), (47,7080) ) } TEXT 117, 0, 0 { TEXT "$#COMPONENT" RECT (5280,2000,5394,2035) MARGINS (1,1) PARENT 116 } TEXT 118, 0, 0 { TEXT "$#REFERENCE" RECT (5340,1744,5379,1779) ALIGN 8 MARGINS (1,1) PARENT 116 } INSTANCE 119, 0, 0 { VARIABLES { #COMPONENT="BusBidirectional" #LIBRARY="#terminals" #REFERENCE="AD(7:0)" #SYMBOL="BusBidirectional" } COORD (5420,2780) ORIENTATION 5 VERTEXES ( (2,2883) ) } TEXT 120, 0, 0 { TEXT "$#REFERENCE" RECT (5402,2842,5437,2944) ALIGN 1 MARGINS (1,1) PARENT 119 ORIENTATION 5 } INSTANCE 128, 0, 0 { VARIABLES { #COMPONENT="U21AddDecode" #LIBRARY="#default" #REFERENCE="U12" #SYMBOL="U21AddDecode" } COORD (4700,1780) VERTEXES ( (3,2115), (8,2232), (13,2184), (28,7051), (38,7049), (43,7055), (53,7053), (58,7057), (63,7082), (68,7059), (73,7084), (78,2251), (83,2249), (88,2270), (93,2196), (103,1566), (120,2268), (122,7061), (125,2318), (128,8376), (131,9265) ) } TEXT 129, 0, 0 { TEXT "$#COMPONENT" RECT (4700,2100,4906,2135) MARGINS (1,1) PARENT 128 } TEXT 130, 0, 0 { TEXT "$#REFERENCE" RECT (4700,1744,4755,1779) ALIGN 8 MARGINS (1,1) PARENT 128 } INSTANCE 144, 0, 0 { VARIABLES { #COMPONENT="Interrupt" #LIBRARY="#default" #REFERENCE="U3" #SYMBOL="Interrupt" } COORD (4340,1780) VERTEXES ( (3,2543), (8,7078), (13,7076), (18,2814), (23,7074), (28,7072), (33,2526), (38,8535), (53,2876), (58,1828), (63,2114), (72,5299), (78,5333), (81,10418) ) PINPROP 3,"#PIN_STATE","0" PINPROP 8,"#PIN_STATE","0" PINPROP 13,"#PIN_STATE","0" PINPROP 18,"#PIN_STATE","0" PINPROP 23,"#PIN_STATE","0" PINPROP 28,"#PIN_STATE","0" PINPROP 33,"#PIN_STATE","0" PINPROP 38,"#PIN_STATE","0" PINPROP 43,"#PIN_STATE","0" PINPROP 48,"#PIN_STATE","0" PINPROP 53,"#PIN_STATE","0" PINPROP 58,"#PIN_STATE","0" PINPROP 63,"#PIN_STATE","0" } TEXT 145, 0, 0 { TEXT "$#COMPONENT" RECT (4330,2010,4439,2045) MARGINS (1,1) PARENT 144 } TEXT 149, 0, 0 { TEXT "$#REFERENCE" RECT (4300,1745,4339,1780) ALIGN 8 MARGINS (1,1) PARENT 144 } INSTANCE 209, 0, 0 { VARIABLES { #COMPONENT="MISCouts" #LIBRARY="#default" #REFERENCE="U9" #SYMBOL="MISCouts" } COORD (3340,1780) VERTEXES ( (8,1846), (13,825), (18,827), (23,829), (28,831), (33,833), (38,839), (43,841), (71,2195), (74,835), (79,837), (82,823) ) } TEXT 210, 0, 0 { TEXT "$#COMPONENT" RECT (3160,2100,3287,2135) MARGINS (1,1) PARENT 209 } TEXT 211, 0, 0 { TEXT "$#REFERENCE" RECT (3200,1725,3239,1760) ALIGN 8 MARGINS (1,1) PARENT 209 } INSTANCE 306, 0, 0 { VARIABLES { #COMPONENT="PWRreg" #LIBRARY="#default" #REFERENCE="U4" #SYMBOL="PWRreg" } COORD (2480,1780) VERTEXES ( (38,958), (33,956), (23,952), (18,950), (13,948), (3,944), (108,1617), (103,1867), (83,1995), (88,1999), (98,2250), (93,2248), (123,2532), (78,4896), (68,4900), (63,4902), (58,4904), (48,4908), (43,4910) ) } TEXT 311, 0, 0 { TEXT "$#REFERENCE" RECT (2620,1744,2659,1779) ALIGN 8 MARGINS (1,1) PARENT 306 } TEXT 315, 0, 0 { TEXT "$#COMPONENT" RECT (2820,2180,2932,2213) PARENT 306 } INSTANCE 347, 0, 0 { VARIABLES { #COMPONENT="Lswitch" #LIBRARY="#default" #REFERENCE="U5" #SYMBOL="Lswitch" } COORD (2340,1780) VERTEXES ( (36,1182), (41,1184), (46,1186), (51,1192), (56,1194), (61,1196), (67,1943), (70,1198), (75,1188), (78,2427), (83,2419), (86,9898), (91,1200), (94,2267), (102,2007), (108,2813), (111,9256), (114,9859) ) } TEXT 348, 0, 0 { TEXT "$#COMPONENT" RECT (2460,2120,2560,2155) MARGINS (1,1) PARENT 347 } TEXT 349, 0, 0 { TEXT "$#REFERENCE" RECT (2180,1744,2219,1779) ALIGN 8 MARGINS (1,1) PARENT 347 } INSTANCE 434, 0, 0 { VARIABLES { #COMPONENT="I2CAddress" #LIBRARY="#default" #REFERENCE="U6" #SYMBOL="I2CAddress" } COORD (1100,1780) VERTEXES ( (18,1963), (36,2269), (39,1526), (44,1516), (13,2351) ) } TEXT 435, 0, 0 { TEXT "$#COMPONENT" RECT (1040,1880,1193,1915) MARGINS (1,1) PARENT 434 } TEXT 436, 0, 0 { TEXT "$#REFERENCE" RECT (1200,1744,1239,1779) ALIGN 8 MARGINS (1,1) PARENT 434 } INSTANCE 521, 0, 0 { VARIABLES { #COMPONENT="I2Cfix" #LIBRARY="#default" #REFERENCE="U11" #SYMBOL="I2Cfix" } COORD (1380,1780) VERTEXES ( (6,1489), (10,1493), (23,2309), (25,1958), (2,1491), (15,10362) ) } TEXT 522, 0, 0 { TEXT "$#COMPONENT" RECT (1400,2020,1474,2055) MARGINS (1,1) PARENT 521 } TEXT 523, 0, 0 { TEXT "$#REFERENCE" RECT (1460,1744,1515,1779) ALIGN 8 MARGINS (1,1) PARENT 521 } INSTANCE 524, 0, 0 { VARIABLES { #COMPONENT="PWMcontrol" #LIBRARY="#default" #REFERENCE="U7" #SYMBOL="PWMcontrol" } COORD (1720,1780) VERTEXES ( (13,9355), (18,9353), (23,9351), (28,9432), (33,9430), (38,9428), (43,9343), (48,9341), (53,9340), (58,9426), (63,9424), (68,9423), (78,2425), (83,2431), (86,9335), (91,9422), (94,3241), (99,3249), (102,9331), (105,9794), (110,9804), (115,9812), (120,9822) ) } TEXT 525, 0, 0 { TEXT "$#COMPONENT" RECT (1680,1700,1842,1735) MARGINS (1,1) PARENT 524 } TEXT 526, 0, 0 { TEXT "$#REFERENCE" RECT (1720,1744,1759,1779) ALIGN 8 MARGINS (1,1) PARENT 524 } INSTANCE 586, 0, 0 { VARIABLES { #COMPONENT="Global" #LIBRARY="#connectors" #REFERENCE="Reset" #SYMBOL="Global" } COORD (6000,3160) } TEXT 587, 0, 0 { TEXT "$#REFERENCE" RECT (6015,3143,6093,3178) ALIGN 4 MARGINS (1,1) PARENT 586 } INSTANCE 590, 0, 0 { VARIABLES { #COMPONENT="Global" #LIBRARY="#connectors" #REFERENCE="Mclk" #SYMBOL="Global" } COORD (5900,3380) } TEXT 591, 0, 0 { TEXT "$#REFERENCE" RECT (5915,3363,5976,3398) ALIGN 4 MARGINS (1,1) PARENT 590 } INSTANCE 592, 0, 0 { VARIABLES { #COMPONENT="Input" #LIBRARY="#terminals" #REFERENCE="Mclk" #SYMBOL="Input" } COORD (5880,3380) } TEXT 593, 0, 0 { TEXT "$#REFERENCE" RECT (5768,3363,5829,3398) ALIGN 6 MARGINS (1,1) PARENT 592 } INSTANCE 594, 0, 0 { VARIABLES { #COMPONENT="Input" #LIBRARY="#terminals" #REFERENCE="AS" #SYMBOL="Input" } COORD (5880,3480) } TEXT 595, 0, 0 { TEXT "$#REFERENCE" RECT (5789,3463,5829,3498) ALIGN 6 MARGINS (1,1) PARENT 594 } INSTANCE 596, 0, 0 { VARIABLES { #COMPONENT="Input" #LIBRARY="#terminals" #REFERENCE="RD" #SYMBOL="Input" } COORD (5880,3520) } TEXT 597, 0, 0 { TEXT "$#REFERENCE" RECT (5785,3503,5829,3538) ALIGN 6 MARGINS (1,1) PARENT 596 } INSTANCE 598, 0, 0 { VARIABLES { #COMPONENT="Input" #LIBRARY="#terminals" #REFERENCE="WR" #SYMBOL="Input" } COORD (5880,3560) } TEXT 599, 0, 0 { TEXT "$#REFERENCE" RECT (5776,3543,5829,3578) ALIGN 6 MARGINS (1,1) PARENT 598 } INSTANCE 600, 0, 0 { VARIABLES { #COMPONENT="Global" #LIBRARY="#connectors" #REFERENCE="AS" #SYMBOL="Global" } COORD (5900,3480) } TEXT 601, 0, 0 { TEXT "$#REFERENCE" RECT (5915,3463,5955,3498) ALIGN 4 MARGINS (1,1) PARENT 600 } INSTANCE 602, 0, 0 { VARIABLES { #COMPONENT="Global" #LIBRARY="#connectors" #REFERENCE="RD" #SYMBOL="Global" } COORD (5900,3520) } TEXT 603, 0, 0 { TEXT "$#REFERENCE" RECT (5915,3503,5959,3538) ALIGN 4 MARGINS (1,1) PARENT 602 } INSTANCE 604, 0, 0 { VARIABLES { #COMPONENT="Global" #LIBRARY="#connectors" #REFERENCE="WR" #SYMBOL="Global" } COORD (5900,3560) } TEXT 605, 0, 0 { TEXT "$#REFERENCE" RECT (5915,3543,5968,3578) ALIGN 4 MARGINS (1,1) PARENT 604 } NET BUS 642, 0, 0 INSTANCE 656, 0, 0 { VARIABLES { #COMPONENT="Output" #LIBRARY="#terminals" #REFERENCE="INT" #SYMBOL="Output" #VERILOG_TYPE="wire" } COORD (4500,2800) ORIENTATION 5 VERTEXES ( (2,2877) ) } TEXT 657, 0, 0 { TEXT "$#REFERENCE" RECT (4482,2852,4517,2901) ALIGN 1 MARGINS (1,1) PARENT 656 ORIENTATION 5 } NET WIRE 665, 0, 0 INSTANCE 684, 0, 0 { VARIABLES { #COMPONENT="Input" #LIBRARY="#terminals" #REFERENCE="PhaseA_Encoder1" #SYMBOL="Input" #VERILOG_TYPE="wire" } COORD (4120,2800) ORIENTATION 8 VERTEXES ( (2,7043) ) } TEXT 685, 0, 0 { TEXT "$#REFERENCE" RECT (4103,2851,4138,3094) ALIGN 1 MARGINS (1,1) PARENT 684 ORIENTATION 8 } NET WIRE 689, 0, 0 INSTANCE 693, 0, 0 { VARIABLES { #COMPONENT="Input" #LIBRARY="#terminals" #REFERENCE="PhaseB_Encoder1" #SYMBOL="Input" #VERILOG_TYPE="wire" } COORD (4100,2800) ORIENTATION 8 VERTEXES ( (2,7045) ) } TEXT 694, 0, 0 { TEXT "$#REFERENCE" RECT (4083,2851,4118,3094) ALIGN 1 MARGINS (1,1) PARENT 693 ORIENTATION 8 } NET WIRE 695, 0, 0 INSTANCE 699, 0, 0 { VARIABLES { #COMPONENT="Input" #LIBRARY="#terminals" #REFERENCE="PhaseA_Encoder0" #SYMBOL="Input" #VERILOG_TYPE="wire" } COORD (3960,2800) ORIENTATION 8 VERTEXES ( (2,7068) ) } TEXT 700, 0, 0 { TEXT "$#REFERENCE" RECT (3943,2851,3978,3094) ALIGN 1 MARGINS (1,1) PARENT 699 ORIENTATION 8 } INSTANCE 701, 0, 0 { VARIABLES { #COMPONENT="Input" #LIBRARY="#terminals" #REFERENCE="PhaseB_Encoder0" #SYMBOL="Input" #VERILOG_TYPE="wire" } COORD (3940,2800) ORIENTATION 8 VERTEXES ( (2,7070) ) } TEXT 702, 0, 0 { TEXT "$#REFERENCE" RECT (3923,2851,3958,3094) ALIGN 1 MARGINS (1,1) PARENT 701 ORIENTATION 8 } NET WIRE 703, 0, 0 NET WIRE 707, 0, 0 INSTANCE 713, 0, 0 { VARIABLES { #COMPONENT="Input" #LIBRARY="#terminals" #REFERENCE="GP_Motor1_0" #SYMBOL="Input" #VERILOG_TYPE="wire" } COORD (4060,2800) ORIENTATION 8 VERTEXES ( (2,745) ) } TEXT 714, 0, 0 { TEXT "$#REFERENCE" RECT (4043,2851,4078,3032) ALIGN 1 MARGINS (1,1) PARENT 713 ORIENTATION 8 } INSTANCE 717, 0, 0 { VARIABLES { #COMPONENT="Input" #LIBRARY="#terminals" #REFERENCE="GP_Motor0_0" #SYMBOL="Input" #VERILOG_TYPE="wire" } COORD (3900,2800) ORIENTATION 8 VERTEXES ( (2,749) ) } TEXT 718, 0, 0 { TEXT "$#REFERENCE" RECT (3883,2851,3918,3032) ALIGN 1 MARGINS (1,1) PARENT 717 ORIENTATION 8 } VTX 745, 0, 0 { COORD (4060,2800) } VTX 749, 0, 0 { COORD (3900,2800) } INSTANCE 759, 0, 0 { VARIABLES { #COMPONENT="Input" #LIBRARY="#terminals" #REFERENCE="LightSense" #SYMBOL="Input" #VERILOG_TYPE="wire" } COORD (3520,2820) ORIENTATION 8 VERTEXES ( (2,822) ) } TEXT 760, 0, 0 { TEXT "$#REFERENCE" RECT (3503,2880,3538,3027) ALIGN 1 MARGINS (1,1) PARENT 759 ORIENTATION 8 } NET WIRE 761, 0, 0 INSTANCE 765, 0, 0 { VARIABLES { #COMPONENT="Output" #LIBRARY="#terminals" #REFERENCE="LED1" #SYMBOL="Output" #VERILOG_TYPE="wire" } COORD (3460,2820) ORIENTATION 7 VERTEXES ( (2,824) ) } TEXT 766, 0, 0 { TEXT "$#REFERENCE" RECT (3443,2872,3478,2946) ALIGN 1 MARGINS (1,1) PARENT 765 ORIENTATION 7 } NET WIRE 770, 0, 0 INSTANCE 774, 0, 0 { VARIABLES { #COMPONENT="Output" #LIBRARY="#terminals" #REFERENCE="LED2" #SYMBOL="Output" #VERILOG_TYPE="wire" } COORD (3440,2820) ORIENTATION 7 VERTEXES ( (2,826) ) } TEXT 775, 0, 0 { TEXT "$#REFERENCE" RECT (3423,2872,3458,2946) ALIGN 1 MARGINS (1,1) PARENT 774 ORIENTATION 7 } NET WIRE 776, 0, 0 INSTANCE 780, 0, 0 { VARIABLES { #COMPONENT="Output" #LIBRARY="#terminals" #REFERENCE="LED3" #SYMBOL="Output" #VERILOG_TYPE="wire" } COORD (3420,2820) ORIENTATION 7 VERTEXES ( (2,828) ) } TEXT 781, 0, 0 { TEXT "$#REFERENCE" RECT (3403,2872,3438,2946) ALIGN 1 MARGINS (1,1) PARENT 780 ORIENTATION 7 } NET WIRE 782, 0, 0 INSTANCE 786, 0, 0 { VARIABLES { #COMPONENT="Output" #LIBRARY="#terminals" #REFERENCE="LED4" #SYMBOL="Output" #VERILOG_TYPE="wire" } COORD (3400,2820) ORIENTATION 7 VERTEXES ( (2,830) ) } TEXT 787, 0, 0 { TEXT "$#REFERENCE" RECT (3383,2872,3418,2946) ALIGN 1 MARGINS (1,1) PARENT 786 ORIENTATION 7 } NET WIRE 788, 0, 0 INSTANCE 792, 0, 0 { VARIABLES { #COMPONENT="Output" #LIBRARY="#terminals" #REFERENCE="LED5" #SYMBOL="Output" #VERILOG_TYPE="wire" } COORD (3380,2820) ORIENTATION 7 VERTEXES ( (2,832) ) } TEXT 793, 0, 0 { TEXT "$#REFERENCE" RECT (3363,2872,3398,2946) ALIGN 1 MARGINS (1,1) PARENT 792 ORIENTATION 7 } NET WIRE 794, 0, 0 INSTANCE 798, 0, 0 { VARIABLES { #COMPONENT="Output" #LIBRARY="#terminals" #REFERENCE="GP_Motor0_1" #SYMBOL="Output" #VERILOG_TYPE="wire" } COORD (3360,2820) ORIENTATION 7 VERTEXES ( (2,834) ) } TEXT 799, 0, 0 { TEXT "$#REFERENCE" RECT (3343,2872,3378,3053) ALIGN 1 MARGINS (1,1) PARENT 798 ORIENTATION 7 } INSTANCE 800, 0, 0 { VARIABLES { #COMPONENT="Output" #LIBRARY="#terminals" #REFERENCE="GP_Motor1_1" #SYMBOL="Output" #VERILOG_TYPE="wire" } COORD (3340,2820) ORIENTATION 7 VERTEXES ( (2,836) ) } TEXT 801, 0, 0 { TEXT "$#REFERENCE" RECT (3323,2872,3358,3053) ALIGN 1 MARGINS (1,1) PARENT 800 ORIENTATION 7 } INSTANCE 802, 0, 0 { VARIABLES { #COMPONENT="Output" #LIBRARY="#terminals" #REFERENCE="MTRpwr" #SYMBOL="Output" #VERILOG_TYPE="wire" } COORD (3320,2820) ORIENTATION 7 VERTEXES ( (2,838) ) } TEXT 803, 0, 0 { TEXT "$#REFERENCE" RECT (3303,2872,3338,2984) ALIGN 1 MARGINS (1,1) PARENT 802 ORIENTATION 7 } INSTANCE 804, 0, 0 { VARIABLES { #COMPONENT="Output" #LIBRARY="#terminals" #REFERENCE="MTRpwrn" #SYMBOL="Output" #VERILOG_TYPE="wire" } COORD (3300,2820) ORIENTATION 7 VERTEXES ( (2,840) ) } TEXT 805, 0, 0 { TEXT "$#REFERENCE" RECT (3283,2872,3318,3000) ALIGN 1 MARGINS (1,1) PARENT 804 ORIENTATION 7 } NET WIRE 806, 0, 0 NET WIRE 810, 0, 0 NET WIRE 818, 0, 0 VTX 822, 0, 0 { COORD (3520,2820) } VTX 823, 0, 0 { COORD (3520,2100) } VTX 824, 0, 0 { COORD (3460,2820) } VTX 825, 0, 0 { COORD (3460,2100) } VTX 826, 0, 0 { COORD (3440,2820) } VTX 827, 0, 0 { COORD (3440,2100) } VTX 828, 0, 0 { COORD (3420,2820) } VTX 829, 0, 0 { COORD (3420,2100) } VTX 830, 0, 0 { COORD (3400,2820) } VTX 831, 0, 0 { COORD (3400,2100) } VTX 832, 0, 0 { COORD (3380,2820) } VTX 833, 0, 0 { COORD (3380,2100) } VTX 834, 0, 0 { COORD (3360,2820) } VTX 835, 0, 0 { COORD (3360,2100) } VTX 836, 0, 0 { COORD (3340,2820) } VTX 837, 0, 0 { COORD (3340,2100) } VTX 838, 0, 0 { COORD (3320,2820) } VTX 839, 0, 0 { COORD (3320,2100) } VTX 840, 0, 0 { COORD (3300,2820) } VTX 841, 0, 0 { COORD (3300,2100) } WIRE 842, 0, 0 { NET 761 VTX 822, 823 } WIRE 843, 0, 0 { NET 770 VTX 824, 825 } WIRE 844, 0, 0 { NET 776 VTX 826, 827 } WIRE 845, 0, 0 { NET 782 VTX 828, 829 } WIRE 846, 0, 0 { NET 788 VTX 830, 831 } WIRE 847, 0, 0 { NET 794 VTX 832, 833 } WIRE 848, 0, 0 { NET 806 VTX 834, 835 } WIRE 849, 0, 0 { NET 810 VTX 836, 837 } WIRE 851, 0, 0 { NET 818 VTX 840, 841 } INSTANCE 880, 0, 0 { VARIABLES { #COMPONENT="Input" #LIBRARY="#terminals" #REFERENCE="Enc15FLG" #SYMBOL="Input" #VERILOG_TYPE="wire" } COORD (3080,2820) ORIENTATION 8 VERTEXES ( (2,945) ) } TEXT 881, 0, 0 { TEXT "$#REFERENCE" RECT (3063,2871,3098,3012) ALIGN 1 MARGINS (1,1) PARENT 880 ORIENTATION 8 } INSTANCE 884, 0, 0 { VARIABLES { #COMPONENT="Input" #LIBRARY="#terminals" #REFERENCE="Home15FLG" #SYMBOL="Input" #VERILOG_TYPE="wire" } COORD (3040,2820) ORIENTATION 8 VERTEXES ( (2,949) ) } TEXT 885, 0, 0 { TEXT "$#REFERENCE" RECT (3023,2871,3058,3040) ALIGN 1 MARGINS (1,1) PARENT 884 ORIENTATION 8 } INSTANCE 886, 0, 0 { VARIABLES { #COMPONENT="Input" #LIBRARY="#terminals" #REFERENCE="Latch133FLG" #SYMBOL="Input" #VERILOG_TYPE="wire" } COORD (3020,2820) ORIENTATION 8 VERTEXES ( (2,951) ) } TEXT 887, 0, 0 { TEXT "$#REFERENCE" RECT (3003,2871,3038,3049) ALIGN 1 MARGINS (1,1) PARENT 886 ORIENTATION 8 } INSTANCE 904, 0, 0 { VARIABLES { #COMPONENT="Input" #LIBRARY="#terminals" #REFERENCE="Enc05FLG" #SYMBOL="Input" #VERILOG_TYPE="wire" } COORD (3000,2820) ORIENTATION 8 VERTEXES ( (2,953) ) } TEXT 905, 0, 0 { TEXT "$#REFERENCE" RECT (2983,2871,3018,3012) ALIGN 1 MARGINS (1,1) PARENT 904 ORIENTATION 8 } INSTANCE 908, 0, 0 { VARIABLES { #COMPONENT="Input" #LIBRARY="#terminals" #REFERENCE="Home05FLG" #SYMBOL="Input" #VERILOG_TYPE="wire" } COORD (2960,2820) ORIENTATION 8 VERTEXES ( (2,957) ) } TEXT 909, 0, 0 { TEXT "$#REFERENCE" RECT (2943,2871,2978,3040) ALIGN 1 MARGINS (1,1) PARENT 908 ORIENTATION 8 } INSTANCE 910, 0, 0 { VARIABLES { #COMPONENT="Input" #LIBRARY="#terminals" #REFERENCE="Latch033FLG" #SYMBOL="Input" #VERILOG_TYPE="wire" } COORD (2940,2820) ORIENTATION 8 VERTEXES ( (2,959) ) } TEXT 911, 0, 0 { TEXT "$#REFERENCE" RECT (2923,2871,2958,3049) ALIGN 1 MARGINS (1,1) PARENT 910 ORIENTATION 8 } NET WIRE 912, 0, 0 NET WIRE 920, 0, 0 NET WIRE 924, 0, 0 NET WIRE 928, 0, 0 NET WIRE 936, 0, 0 NET WIRE 940, 0, 0 VTX 944, 0, 0 { COORD (3080,2180) } VTX 945, 0, 0 { COORD (3080,2820) } VTX 948, 0, 0 { COORD (3040,2180) } VTX 949, 0, 0 { COORD (3040,2820) } VTX 950, 0, 0 { COORD (3020,2180) } VTX 951, 0, 0 { COORD (3020,2820) } VTX 952, 0, 0 { COORD (3000,2180) } VTX 953, 0, 0 { COORD (3000,2820) } VTX 956, 0, 0 { COORD (2960,2180) } VTX 957, 0, 0 { COORD (2960,2820) } VTX 958, 0, 0 { COORD (2940,2180) } VTX 959, 0, 0 { COORD (2940,2820) } WIRE 960, 0, 0 { NET 912 VTX 944, 945 } WIRE 962, 0, 0 { NET 920 VTX 948, 949 } WIRE 963, 0, 0 { NET 924 VTX 950, 951 } WIRE 964, 0, 0 { NET 928 VTX 952, 953 } WIRE 966, 0, 0 { NET 936 VTX 956, 957 } WIRE 967, 0, 0 { NET 940 VTX 958, 959 } INSTANCE 968, 0, 0 { VARIABLES { #COMPONENT="Output" #LIBRARY="#terminals" #REFERENCE="Enc15ctrl" #SYMBOL="Output" #VERILOG_TYPE="wire" } COORD (2660,2820) ORIENTATION 7 VERTEXES ( (2,4895) ) } TEXT 969, 0, 0 { TEXT "$#REFERENCE" RECT (2643,2872,2678,2996) ALIGN 1 MARGINS (1,1) PARENT 968 ORIENTATION 8 } INSTANCE 972, 0, 0 { VARIABLES { #COMPONENT="Output" #LIBRARY="#terminals" #REFERENCE="Home15ctrl" #SYMBOL="Output" #VERILOG_TYPE="wire" } COORD (2700,2820) ORIENTATION 7 VERTEXES ( (2,4899) ) } TEXT 973, 0, 0 { TEXT "$#REFERENCE" RECT (2683,2872,2718,3024) ALIGN 1 MARGINS (1,1) PARENT 972 ORIENTATION 8 } INSTANCE 974, 0, 0 { VARIABLES { #COMPONENT="Output" #LIBRARY="#terminals" #REFERENCE="Latch133ctrl" #SYMBOL="Output" #VERILOG_TYPE="wire" } COORD (2720,2820) ORIENTATION 7 VERTEXES ( (2,4901) ) } TEXT 975, 0, 0 { TEXT "$#REFERENCE" RECT (2703,2880,2738,3041) ALIGN 1 MARGINS (1,1) PARENT 974 ORIENTATION 8 } INSTANCE 976, 0, 0 { VARIABLES { #COMPONENT="Output" #LIBRARY="#terminals" #REFERENCE="Enc05ctrl" #SYMBOL="Output" #VERILOG_TYPE="wire" } COORD (2740,2820) ORIENTATION 7 VERTEXES ( (2,4903) ) } TEXT 977, 0, 0 { TEXT "$#REFERENCE" RECT (2723,2872,2758,2996) ALIGN 1 MARGINS (1,1) PARENT 976 ORIENTATION 8 } INSTANCE 980, 0, 0 { VARIABLES { #COMPONENT="Output" #LIBRARY="#terminals" #REFERENCE="Home05ctrl" #SYMBOL="Output" #VERILOG_TYPE="wire" } COORD (2780,2820) ORIENTATION 7 VERTEXES ( (2,4907) ) } TEXT 981, 0, 0 { TEXT "$#REFERENCE" RECT (2763,2872,2798,3024) ALIGN 1 MARGINS (1,1) PARENT 980 ORIENTATION 8 } INSTANCE 982, 0, 0 { VARIABLES { #COMPONENT="Output" #LIBRARY="#terminals" #REFERENCE="Latch033ctrl" #SYMBOL="Output" #VERILOG_TYPE="wire" } COORD (2800,2820) ORIENTATION 7 VERTEXES ( (2,4909) ) } TEXT 983, 0, 0 { TEXT "$#REFERENCE" RECT (2783,2872,2818,3033) ALIGN 1 MARGINS (1,1) PARENT 982 ORIENTATION 8 } INSTANCE 1072, 0, 0 { VARIABLES { #COMPONENT="Input" #LIBRARY="#terminals" #REFERENCE="Home1" #SYMBOL="Input" #VERILOG_TYPE="wire" } COORD (2440,2840) ORIENTATION 8 VERTEXES ( (2,1181) ) } TEXT 1073, 0, 0 { TEXT "$#REFERENCE" RECT (2423,2891,2458,2987) ALIGN 1 MARGINS (1,1) PARENT 1072 ORIENTATION 8 } INSTANCE 1074, 0, 0 { VARIABLES { #COMPONENT="Input" #LIBRARY="#terminals" #REFERENCE="FLS1" #SYMBOL="Input" #VERILOG_TYPE="wire" } COORD (2420,2840) ORIENTATION 8 VERTEXES ( (2,1183) ) } TEXT 1075, 0, 0 { TEXT "$#REFERENCE" RECT (2403,2891,2438,2962) ALIGN 1 MARGINS (1,1) PARENT 1074 ORIENTATION 8 } INSTANCE 1076, 0, 0 { VARIABLES { #COMPONENT="Input" #LIBRARY="#terminals" #REFERENCE="RLS1" #SYMBOL="Input" #VERILOG_TYPE="wire" } COORD (2400,2840) ORIENTATION 8 VERTEXES ( (2,1185) ) } TEXT 1077, 0, 0 { TEXT "$#REFERENCE" RECT (2383,2891,2418,2965) ALIGN 1 MARGINS (1,1) PARENT 1076 ORIENTATION 8 } INSTANCE 1078, 0, 0 { VARIABLES { #COMPONENT="Input" #LIBRARY="#terminals" #REFERENCE="DIR1" #SYMBOL="Input" #VERILOG_TYPE="wire" } COORD (2380,2840) ORIENTATION 8 VERTEXES ( (2,1187) ) } TEXT 1079, 0, 0 { TEXT "$#REFERENCE" RECT (2363,2891,2398,2958) ALIGN 1 MARGINS (1,1) PARENT 1078 ORIENTATION 8 } INSTANCE 1080, 0, 0 { VARIABLES { #COMPONENT="Input" #LIBRARY="#terminals" #REFERENCE="Brake1" #SYMBOL="Input" #VERILOG_TYPE="wire" } COORD (2360,2840) ORIENTATION 8 VERTEXES ( (2,1189) ) } TEXT 1081, 0, 0 { TEXT "$#REFERENCE" RECT (2343,2891,2378,2984) ALIGN 1 MARGINS (1,1) PARENT 1080 ORIENTATION 8 } INSTANCE 1120, 0, 0 { VARIABLES { #COMPONENT="Input" #LIBRARY="#terminals" #REFERENCE="Home0" #SYMBOL="Input" #VERILOG_TYPE="wire" } COORD (2320,2840) ORIENTATION 8 VERTEXES ( (2,1191) ) } TEXT 1122, 0, 0 { TEXT "$#REFERENCE" RECT (2303,2891,2338,2987) ALIGN 1 MARGINS (1,1) PARENT 1120 ORIENTATION 8 } INSTANCE 1123, 0, 0 { VARIABLES { #COMPONENT="Input" #LIBRARY="#terminals" #REFERENCE="FLS0" #SYMBOL="Input" #VERILOG_TYPE="wire" } COORD (2300,2840) ORIENTATION 8 VERTEXES ( (2,1193) ) } TEXT 1125, 0, 0 { TEXT "$#REFERENCE" RECT (2283,2891,2318,2962) ALIGN 1 MARGINS (1,1) PARENT 1123 ORIENTATION 8 } INSTANCE 1126, 0, 0 { VARIABLES { #COMPONENT="Input" #LIBRARY="#terminals" #REFERENCE="RLS0" #SYMBOL="Input" #VERILOG_TYPE="wire" } COORD (2280,2840) ORIENTATION 8 VERTEXES ( (2,1195) ) } TEXT 1128, 0, 0 { TEXT "$#REFERENCE" RECT (2263,2891,2298,2965) ALIGN 1 MARGINS (1,1) PARENT 1126 ORIENTATION 8 } INSTANCE 1129, 0, 0 { VARIABLES { #COMPONENT="Input" #LIBRARY="#terminals" #REFERENCE="DIR0" #SYMBOL="Input" #VERILOG_TYPE="wire" } COORD (2260,2840) ORIENTATION 8 VERTEXES ( (2,1197) ) } TEXT 1131, 0, 0 { TEXT "$#REFERENCE" RECT (2243,2891,2278,2958) ALIGN 1 MARGINS (1,1) PARENT 1129 ORIENTATION 8 } INSTANCE 1132, 0, 0 { VARIABLES { #COMPONENT="Input" #LIBRARY="#terminals" #REFERENCE="Brake0" #SYMBOL="Input" #VERILOG_TYPE="wire" } COORD (2240,2840) ORIENTATION 8 VERTEXES ( (2,1199) ) } TEXT 1134, 0, 0 { TEXT "$#REFERENCE" RECT (2223,2891,2258,2984) ALIGN 1 MARGINS (1,1) PARENT 1132 ORIENTATION 8 } VTX 1181, 0, 0 { COORD (2440,2840) } VTX 1182, 0, 0 { COORD (2440,2120) } VTX 1183, 0, 0 { COORD (2420,2840) } VTX 1184, 0, 0 { COORD (2420,2120) } VTX 1185, 0, 0 { COORD (2400,2840) } VTX 1186, 0, 0 { COORD (2400,2120) } VTX 1187, 0, 0 { COORD (2380,2840) } VTX 1188, 0, 0 { COORD (2380,2120) } VTX 1189, 0, 0 { COORD (2360,2840) } VTX 1191, 0, 0 { COORD (2320,2840) } VTX 1192, 0, 0 { COORD (2320,2120) } VTX 1193, 0, 0 { COORD (2300,2840) } VTX 1194, 0, 0 { COORD (2300,2120) } VTX 1195, 0, 0 { COORD (2280,2840) } VTX 1196, 0, 0 { COORD (2280,2120) } VTX 1197, 0, 0 { COORD (2260,2840) } VTX 1198, 0, 0 { COORD (2260,2120) } VTX 1199, 0, 0 { COORD (2240,2840) } VTX 1200, 0, 0 { COORD (2240,2120) } INSTANCE 1221, 0, 0 { VARIABLES { #COMPONENT="Output" #LIBRARY="#terminals" #REFERENCE="PBL0" #SYMBOL="Output" #VERILOG_TYPE="wire" } COORD (2080,2840) ORIENTATION 5 VERTEXES ( (2,9334) ) } TEXT 1222, 0, 0 { TEXT "$#REFERENCE" RECT (2062,2892,2097,2964) ALIGN 1 MARGINS (1,1) PARENT 1221 ORIENTATION 5 } NET WIRE 1226, 0, 0 INSTANCE 1230, 0, 0 { VARIABLES { #COMPONENT="Output" #LIBRARY="#terminals" #REFERENCE="PBH0" #SYMBOL="Output" #VERILOG_TYPE="wire" } COORD (2060,2840) ORIENTATION 5 VERTEXES ( (2,9350) ) } TEXT 1231, 0, 0 { TEXT "$#REFERENCE" RECT (2042,2892,2077,2969) ALIGN 1 MARGINS (1,1) PARENT 1230 ORIENTATION 5 } NET WIRE 1232, 0, 0 INSTANCE 1236, 0, 0 { VARIABLES { #COMPONENT="Output" #LIBRARY="#terminals" #REFERENCE="PAL0" #SYMBOL="Output" #VERILOG_TYPE="wire" } COORD (2040,2840) ORIENTATION 5 VERTEXES ( (2,9352) ) } TEXT 1237, 0, 0 { TEXT "$#REFERENCE" RECT (2022,2892,2057,2964) ALIGN 1 MARGINS (1,1) PARENT 1236 ORIENTATION 5 } NET WIRE 1238, 0, 0 INSTANCE 1242, 0, 0 { VARIABLES { #COMPONENT="Output" #LIBRARY="#terminals" #REFERENCE="PAH0" #SYMBOL="Output" #VERILOG_TYPE="wire" } COORD (2020,2840) ORIENTATION 5 VERTEXES ( (2,9354) ) } TEXT 1243, 0, 0 { TEXT "$#REFERENCE" RECT (2002,2892,2037,2969) ALIGN 1 MARGINS (1,1) PARENT 1242 ORIENTATION 5 } NET WIRE 1244, 0, 0 INSTANCE 1248, 0, 0 { VARIABLES { #COMPONENT="Input" #LIBRARY="#terminals" #REFERENCE="PWM1" #SYMBOL="Input" #VERILOG_TYPE="wire" } COORD (2000,2840) ORIENTATION 8 VERTEXES ( (2,9342) ) } TEXT 1249, 0, 0 { TEXT "$#REFERENCE" RECT (1983,2891,2018,2981) ALIGN 1 MARGINS (1,1) PARENT 1248 ORIENTATION 8 } NET WIRE 1253, 0, 0 INSTANCE 1279, 0, 0 { VARIABLES { #COMPONENT="Output" #LIBRARY="#terminals" #REFERENCE="PBL1" #SYMBOL="Output" #VERILOG_TYPE="wire" } COORD (1840,2840) ORIENTATION 5 VERTEXES ( (2,9421) ) } TEXT 1281, 0, 0 { TEXT "$#REFERENCE" RECT (1822,2892,1857,2964) ALIGN 1 MARGINS (1,1) PARENT 1279 ORIENTATION 5 } INSTANCE 1286, 0, 0 { VARIABLES { #COMPONENT="Output" #LIBRARY="#terminals" #REFERENCE="PBH1" #SYMBOL="Output" #VERILOG_TYPE="wire" } COORD (1860,2840) ORIENTATION 5 VERTEXES ( (2,9429) ) } TEXT 1288, 0, 0 { TEXT "$#REFERENCE" RECT (1842,2892,1877,2969) ALIGN 1 MARGINS (1,1) PARENT 1286 ORIENTATION 5 } INSTANCE 1292, 0, 0 { VARIABLES { #COMPONENT="Output" #LIBRARY="#terminals" #REFERENCE="PAL1" #SYMBOL="Output" #VERILOG_TYPE="wire" } COORD (1880,2840) ORIENTATION 5 VERTEXES ( (2,9427) ) } TEXT 1294, 0, 0 { TEXT "$#REFERENCE" RECT (1862,2892,1897,2964) ALIGN 1 MARGINS (1,1) PARENT 1292 ORIENTATION 5 } INSTANCE 1298, 0, 0 { VARIABLES { #COMPONENT="Output" #LIBRARY="#terminals" #REFERENCE="PAH1" #SYMBOL="Output" #VERILOG_TYPE="wire" } COORD (1900,2840) ORIENTATION 5 VERTEXES ( (2,9431) ) } TEXT 1300, 0, 0 { TEXT "$#REFERENCE" RECT (1882,2892,1917,2969) ALIGN 1 MARGINS (1,1) PARENT 1298 ORIENTATION 5 } INSTANCE 1304, 0, 0 { VARIABLES { #COMPONENT="Input" #LIBRARY="#terminals" #REFERENCE="PWM2" #SYMBOL="Input" #VERILOG_TYPE="wire" } COORD (1820,2840) ORIENTATION 8 VERTEXES ( (2,9425) ) } TEXT 1306, 0, 0 { TEXT "$#REFERENCE" RECT (1803,2891,1838,2981) ALIGN 1 MARGINS (1,1) PARENT 1304 ORIENTATION 8 } NET WIRE 1357, 0, 0 NET WIRE 1358, 0, 0 NET WIRE 1359, 0, 0 NET WIRE 1360, 0, 0 NET WIRE 1363, 0, 0 VTX 1365, 0, 0 { COORD (2260,2260) } WIRE 1366, 0, 0 { NET 1372 VTX 1197, 1365 } WIRE 1367, 0, 0 { NET 1372 VTX 1365, 1198 } NET WIRE 1372, 0, 0 VTX 1374, 0, 0 { COORD (2240,2280) } WIRE 1375, 0, 0 { NET 1381 VTX 1199, 1374 } WIRE 1376, 0, 0 { NET 1381 VTX 1374, 1200 } NET WIRE 1381, 0, 0 VTX 1383, 0, 0 { COORD (2380,2300) } WIRE 1384, 0, 0 { NET 1390 VTX 1187, 1383 } WIRE 1385, 0, 0 { NET 1390 VTX 1383, 1188 } NET WIRE 1390, 0, 0 VTX 1392, 0, 0 { COORD (2360,2320) } WIRE 1393, 0, 0 { NET 1399 VTX 1189, 1392 } NET WIRE 1399, 0, 0 INSTANCE 1440, 0, 0 { VARIABLES { #COMPONENT="Input" #LIBRARY="#terminals" #REFERENCE="SCLreset" #SYMBOL="Input" #VERILOG_TYPE="wire" } COORD (1580,2840) ORIENTATION 8 VERTEXES ( (2,1488) ) } TEXT 1441, 0, 0 { TEXT "$#REFERENCE" RECT (1563,2891,1598,3014) ALIGN 1 MARGINS (1,1) PARENT 1440 ORIENTATION 8 } INSTANCE 1445, 0, 0 { VARIABLES { #COMPONENT="Input" #LIBRARY="#terminals" #REFERENCE="SCLinc" #SYMBOL="Input" #VERILOG_TYPE="wire" } COORD (1620,2840) ORIENTATION 8 VERTEXES ( (2,1490) ) } TEXT 1446, 0, 0 { TEXT "$#REFERENCE" RECT (1603,2891,1638,2987) ALIGN 1 MARGINS (1,1) PARENT 1445 ORIENTATION 8 } INSTANCE 1458, 0, 0 { VARIABLES { #COMPONENT="Bidirectional" #LIBRARY="#terminals" #REFERENCE="SCL" #SYMBOL="Bidirectional" #VERILOG_TYPE="wire" } COORD (1540,2840) ORIENTATION 5 VERTEXES ( (2,1492) ) } TEXT 1459, 0, 0 { TEXT "$#REFERENCE" RECT (1522,2902,1557,2960) ALIGN 1 MARGINS (1,1) PARENT 1458 ORIENTATION 5 } VTX 1488, 0, 0 { COORD (1580,2840) } VTX 1489, 0, 0 { COORD (1580,2020) } VTX 1490, 0, 0 { COORD (1620,2840) } VTX 1491, 0, 0 { COORD (1620,2020) } VTX 1492, 0, 0 { COORD (1540,2840) } VTX 1493, 0, 0 { COORD (1540,2020) } INSTANCE 1497, 0, 0 { VARIABLES { #COMPONENT="BusInput" #LIBRARY="#terminals" #REFERENCE="I2CS(5:0)" #SYMBOL="BusInput" #VERILOG_TYPE="wire" } COORD (1260,2840) ORIENTATION 8 VERTEXES ( (2,2352) ) } TEXT 1498, 0, 0 { TEXT "$#REFERENCE" RECT (1243,2891,1278,3016) ALIGN 1 MARGINS (1,1) PARENT 1497 ORIENTATION 8 } NET BUS 1512, 0, 0 VTX 1516, 0, 0 { COORD (1340,2080) } VTX 1517, 0, 0 { COORD (4060,2500) } WIRE 1518, 0, 0 { NET 1524 VTX 745, 1517 } VTX 1521, 0, 0 { COORD (1340,2500) } WIRE 1522, 0, 0 { NET 1524 VTX 1516, 1521 } WIRE 1523, 0, 0 { NET 1524 VTX 1521, 1517 } NET WIRE 1524, 0, 0 VTX 1525, 0, 0 { COORD (3900,2520) } VTX 1526, 0, 0 { COORD (1320,2080) } WIRE 1527, 0, 0 { NET 1533 VTX 749, 1525 } VTX 1530, 0, 0 { COORD (1320,2520) } WIRE 1531, 0, 0 { NET 1533 VTX 1525, 1530 } WIRE 1532, 0, 0 { NET 1533 VTX 1530, 1526 } NET WIRE 1533, 0, 0 VTX 1562, 0, 0 { COORD (5400,1780) } VTX 1563, 0, 0 { COORD (5400,1680) } NET BUS 1564, 0, 0 BUS 1565, 0, 0 { NET 1564 VTX 1562, 1563 } VTX 1566, 0, 0 { COORD (5160,1780) } VTX 1567, 0, 0 { COORD (5160,1680) } BUS 1568, 0, 0 { NET 1564 VTX 1563, 1567 } BUS 1569, 0, 0 { NET 1564 VTX 1567, 1566 } VTX 1617, 0, 0 { COORD (3060,1780) } VTX 1804, 0, 0 { COORD (4220,1220) } VTX 1824, 0, 0 { COORD (4600,1220) } BUS 1827, 0, 0 { NET 3547 VTX 1804, 1824 } VTX 1828, 0, 0 { COORD (4600,1780) } BUS 1829, 0, 0 { NET 3547 VTX 1824, 1828 } VTX 1846, 0, 0 { COORD (3500,1780) } VTX 1847, 0, 0 { COORD (3500,1220) } BUS 1848, 0, 0 { NET 3547 VTX 1804, 1847 } BUS 1850, 0, 0 { NET 3547 VTX 1846, 1847 } VTX 1867, 0, 0 { COORD (3080,1780) } VTX 1868, 0, 0 { COORD (3080,1220) } BUS 1869, 0, 0 { NET 3547 VTX 1847, 1868 } BUS 1871, 0, 0 { NET 3547 VTX 1867, 1868 } VTX 1886, 0, 0 { COORD (3060,1260) } VTX 1918, 0, 0 { COORD (5460,1780) } VTX 1919, 0, 0 { COORD (5460,1260) } BUS 1920, 0, 0 { NET 3538 VTX 1918, 1919 VARIABLES { #NAMED="1" } } VTX 1925, 0, 0 { COORD (4180,1260) } BUS 1927, 0, 0 { NET 3538 VTX 1925, 1886 } BUS 1932, 0, 0 { NET 3538 VTX 1617, 1886 } VTX 1943, 0, 0 { COORD (2500,1780) } VTX 1944, 0, 0 { COORD (2500,1260) } BUS 1945, 0, 0 { NET 3538 VTX 1943, 1944 } BUS 1946, 0, 0 { NET 3538 VTX 1886, 1944 } VTX 1958, 0, 0 { COORD (1580,1780) } VTX 1959, 0, 0 { COORD (1580,1260) } BUS 1960, 0, 0 { NET 3538 VTX 1958, 1959 } BUS 1961, 0, 0 { NET 3538 VTX 1944, 1959 } VTX 1963, 0, 0 { COORD (1320,1780) } VTX 1964, 0, 0 { COORD (1320,1260) } BUS 1965, 0, 0 { NET 3538 VTX 1963, 1964 } BUS 1966, 0, 0 { NET 3538 VTX 1964, 1959 } VTX 1979, 0, 0 { COORD (3900,1480) } VTX 1990, 0, 0 { COORD (3880,1460) } VTX 1995, 0, 0 { COORD (2940,1780) } VTX 1996, 0, 0 { COORD (2940,1460) } WIRE 1997, 0, 0 { NET 5076 VTX 1990, 1996 } WIRE 1998, 0, 0 { NET 5076 VTX 1996, 1995 } VTX 1999, 0, 0 { COORD (2920,1780) } VTX 2000, 0, 0 { COORD (2920,1480) } WIRE 2001, 0, 0 { NET 5081 VTX 1979, 2000 } WIRE 2002, 0, 0 { NET 5081 VTX 2000, 1999 } VTX 2007, 0, 0 { COORD (2400,1780) } VTX 2008, 0, 0 { COORD (2400,1460) } WIRE 2009, 0, 0 { NET 5076 VTX 1996, 2008 } WIRE 2010, 0, 0 { NET 5076 VTX 2008, 2007 } VTX 2114, 0, 0 { COORD (4560,1780) } VTX 2115, 0, 0 { COORD (4740,1780) } VTX 2121, 0, 0 { COORD (4560,1720) } WIRE 2122, 0, 0 { NET 5170 VTX 2114, 2121 } VTX 2123, 0, 0 { COORD (4740,1720) } WIRE 2124, 0, 0 { NET 5170 VTX 2121, 2123 VARIABLES { #NAMED="1" } } WIRE 2125, 0, 0 { NET 5170 VTX 2123, 2115 } VTX 2184, 0, 0 { COORD (4980,1780) } VTX 2190, 0, 0 { COORD (4980,1480) } WIRE 2192, 0, 0 { NET 5081 VTX 2190, 2184 } VTX 2195, 0, 0 { COORD (3440,1780) } VTX 2196, 0, 0 { COORD (5020,1780) } VTX 2208, 0, 0 { COORD (3440,1440) } WIRE 2209, 0, 0 { NET 5071 VTX 2195, 2208 } VTX 2210, 0, 0 { COORD (5020,1440) } WIRE 2211, 0, 0 { NET 5071 VTX 2208, 2210 VARIABLES { #NAMED="1" } } WIRE 2212, 0, 0 { NET 5071 VTX 2210, 2196 } VTX 2232, 0, 0 { COORD (5000,1780) } VTX 2243, 0, 0 { COORD (5000,1460) } WIRE 2244, 0, 0 { NET 5076 VTX 1990, 2243 VARIABLES { #NAMED="1" } } WIRE 2245, 0, 0 { NET 5076 VTX 2243, 2232 } VTX 2248, 0, 0 { COORD (2900,1780) } VTX 2249, 0, 0 { COORD (5040,1780) } VTX 2250, 0, 0 { COORD (2880,1780) } VTX 2251, 0, 0 { COORD (5060,1780) } VTX 2257, 0, 0 { COORD (2900,1420) } WIRE 2258, 0, 0 { NET 5066 VTX 2248, 2257 } VTX 2259, 0, 0 { COORD (5040,1420) } WIRE 2260, 0, 0 { NET 5066 VTX 2257, 2259 VARIABLES { #NAMED="1" } } WIRE 2261, 0, 0 { NET 5066 VTX 2259, 2249 } VTX 2262, 0, 0 { COORD (2880,1400) } WIRE 2263, 0, 0 { NET 5061 VTX 2250, 2262 } VTX 2264, 0, 0 { COORD (5060,1400) } WIRE 2265, 0, 0 { NET 5061 VTX 2262, 2264 VARIABLES { #NAMED="1" } } WIRE 2266, 0, 0 { NET 5061 VTX 2264, 2251 } VTX 2267, 0, 0 { COORD (2360,1780) } VTX 2268, 0, 0 { COORD (5080,1780) } VTX 2269, 0, 0 { COORD (1260,1780) } VTX 2270, 0, 0 { COORD (5120,1780) } VTX 2271, 0, 0 { COORD (2360,1380) } WIRE 2272, 0, 0 { NET 5056 VTX 2267, 2271 } VTX 2273, 0, 0 { COORD (5080,1380) } WIRE 2274, 0, 0 { NET 5056 VTX 2271, 2273 VARIABLES { #NAMED="1" } } WIRE 2275, 0, 0 { NET 5056 VTX 2273, 2268 } VTX 2276, 0, 0 { COORD (1260,1340) } WIRE 2277, 0, 0 { NET 5046 VTX 2269, 2276 } VTX 2278, 0, 0 { COORD (5120,1340) } WIRE 2279, 0, 0 { NET 5046 VTX 2276, 2278 VARIABLES { #NAMED="1" } } WIRE 2280, 0, 0 { NET 5046 VTX 2278, 2270 } VTX 2309, 0, 0 { COORD (1540,1780) } VTX 2312, 0, 0 { COORD (1540,1360) } WIRE 2313, 0, 0 { NET 5051 VTX 2309, 2312 } VTX 2318, 0, 0 { COORD (5100,1780) } VTX 2319, 0, 0 { COORD (5100,1360) } WIRE 2321, 0, 0 { NET 5051 VTX 2319, 2318 } WIRE 2322, 0, 0 { NET 5051 VTX 2312, 2319 VARIABLES { #NAMED="1" } } VTX 2351, 0, 0 { COORD (1260,2080) } VTX 2352, 0, 0 { COORD (1260,2840) } BUS 2353, 0, 0 { NET 1512 VTX 2351, 2352 } VTX 2419, 0, 0 { COORD (2280,1780) } VTX 2420, 0, 0 { COORD (2020,1620) } VTX 2422, 0, 0 { COORD (2280,1620) } WIRE 2423, 0, 0 { NET 3248 VTX 2419, 2422 } WIRE 2424, 0, 0 { NET 3248 VTX 2422, 2420 } VTX 2425, 0, 0 { COORD (2020,1780) } VTX 2427, 0, 0 { COORD (2260,1780) } VTX 2428, 0, 0 { COORD (2260,1640) } WIRE 2430, 0, 0 { NET 3253 VTX 2427, 2428 } VTX 2431, 0, 0 { COORD (1880,1780) } VTX 2432, 0, 0 { COORD (1880,1640) } WIRE 2433, 0, 0 { NET 3253 VTX 2428, 2432 } WIRE 2434, 0, 0 { NET 3253 VTX 2432, 2431 } NET WIRE 2482, 0, 0 NET WIRE 2493, 0, 0 NET WIRE 2512, 0, 0 VTX 2526, 0, 0 { COORD (4400,1780) } NET WIRE 2528, 0, 0 VTX 2529, 0, 0 { COORD (4400,1200) } WIRE 2530, 0, 0 { NET 2528 VTX 2526, 2529 } VTX 2532, 0, 0 { COORD (3000,1780) } VTX 2533, 0, 0 { COORD (3000,1200) } WIRE 2535, 0, 0 { NET 2528 VTX 2533, 2532 } WIRE 2536, 0, 0 { NET 2528 VTX 2529, 2533 } VTX 2538, 0, 0 { COORD (4520,1080) } VTX 2540, 0, 0 { COORD (1620,1080) } WIRE 2542, 0, 0 { NET 8122 VTX 2540, 2538 OUTLINE 0,1, (0,4,255) } VTX 2543, 0, 0 { COORD (4520,1780) } WIRE 2544, 0, 0 { NET 8122 VTX 2538, 2543 OUTLINE 0,1, (0,4,255) } NET WIRE 2575, 0, 0 VTX 2769, 0, 0 { COORD (2320,2560) } WIRE 2770, 0, 0 { NET 2773 VTX 1191, 2769 } WIRE 2771, 0, 0 { NET 2773 VTX 2769, 1192 } NET WIRE 2773, 0, 0 VTX 2778, 0, 0 { COORD (2440,2580) } WIRE 2779, 0, 0 { NET 2784 VTX 1181, 2778 } WIRE 2780, 0, 0 { NET 2784 VTX 2778, 1182 } NET WIRE 2784, 0, 0 VTX 2813, 0, 0 { COORD (2320,1780) } VTX 2814, 0, 0 { COORD (4500,1780) } VTX 2819, 0, 0 { COORD (2320,1100) } WIRE 2820, 0, 0 { NET 2575 VTX 2813, 2819 } VTX 2821, 0, 0 { COORD (4500,1100) } WIRE 2822, 0, 0 { NET 2575 VTX 2819, 2821 } WIRE 2823, 0, 0 { NET 2575 VTX 2821, 2814 } VTX 2876, 0, 0 { COORD (4500,2000) } VTX 2877, 0, 0 { COORD (4500,2800) } WIRE 2878, 0, 0 { NET 665 VTX 2876, 2877 } VTX 2882, 0, 0 { COORD (5420,2000) } VTX 2883, 0, 0 { COORD (5420,2780) } BUS 2884, 0, 0 { NET 642 VTX 2882, 2883 } VTX 3241, 0, 0 { COORD (2000,1780) } VTX 3242, 0, 0 { COORD (2020,1700) } WIRE 3243, 0, 0 { NET 3248 VTX 2420, 3242 } WIRE 3244, 0, 0 { NET 3248 VTX 3242, 2425 } VTX 3245, 0, 0 { COORD (2000,1700) } WIRE 3246, 0, 0 { NET 3248 VTX 3241, 3245 } WIRE 3247, 0, 0 { NET 3248 VTX 3245, 3242 } NET WIRE 3248, 0, 0 VTX 3249, 0, 0 { COORD (1860,1780) } VTX 3250, 0, 0 { COORD (1860,1640) } WIRE 3251, 0, 0 { NET 3253 VTX 3249, 3250 } WIRE 3252, 0, 0 { NET 3253 VTX 3250, 2432 } NET WIRE 3253, 0, 0 NET BUS 3538, 0, 0 { VARIABLES { #NAME="outDATA(7:0)" #VERILOG_TYPE="wire" } } TEXT 3539, 0, 0 { TEXT "$#NAME" RECT (5020,1226,5166,1255) ALIGN 4 MARGINS (1,1) PARENT 1920 } VTX 3543, 0, 0 { COORD (5500,1780) } VTX 3544, 0, 0 { COORD (5500,1220) } BUS 3545, 0, 0 { NET 3547 VTX 1824, 3544 } BUS 3546, 0, 0 { NET 3547 VTX 3544, 3543 } NET BUS 3547, 0, 0 { VARIABLES { #NAME="inDATA(7:0)" #VERILOG_TYPE="wire" } } TEXT 3548, 0, 0 { TEXT "$#NAME" RECT (5040,1186,5171,1215) ALIGN 4 MARGINS (1,1) PARENT 7091 } NET WIRE 3919, 0, 0 INSTANCE 3955, 0, 0 { VARIABLES { #COMPONENT="Output" #LIBRARY="#terminals" #REFERENCE="TP12" #SYMBOL="Output" #VERILOG_TYPE="wire" } COORD (1640,1580) VERTEXES ( (2,8116) ) } TEXT 3956, 0, 0 { TEXT "$#REFERENCE" RECT (1700,1562,1772,1597) ALIGN 4 MARGINS (1,1) PARENT 3955 } TEXT 4277, 0, 0 { TEXT "$#NAME" RECT (1480,2611,1528,2640) ALIGN 8 MARGINS (1,1) PARENT 10219 } NET WIRE 4281, 0, 0 { VARIABLES { #NAME="SCL" #VERILOG_TYPE="wire" } } NET WIRE 4826, 0, 0 NET WIRE 4863, 0, 0 NET WIRE 4871, 0, 0 NET WIRE 4875, 0, 0 NET WIRE 4879, 0, 0 NET WIRE 4887, 0, 0 NET WIRE 4891, 0, 0 VTX 4895, 0, 0 { COORD (2660,2820) } VTX 4896, 0, 0 { COORD (2660,2180) } VTX 4899, 0, 0 { COORD (2700,2820) } VTX 4900, 0, 0 { COORD (2700,2180) } VTX 4901, 0, 0 { COORD (2720,2820) } VTX 4902, 0, 0 { COORD (2720,2180) } VTX 4903, 0, 0 { COORD (2740,2820) } VTX 4904, 0, 0 { COORD (2740,2180) } VTX 4907, 0, 0 { COORD (2780,2820) } VTX 4908, 0, 0 { COORD (2780,2180) } VTX 4909, 0, 0 { COORD (2800,2820) } VTX 4910, 0, 0 { COORD (2800,2180) } WIRE 4911, 0, 0 { NET 4863 VTX 4895, 4896 } WIRE 4913, 0, 0 { NET 4871 VTX 4899, 4900 } WIRE 4914, 0, 0 { NET 4875 VTX 4901, 4902 } WIRE 4915, 0, 0 { NET 4879 VTX 4903, 4904 } WIRE 4917, 0, 0 { NET 4887 VTX 4907, 4908 } WIRE 4918, 0, 0 { NET 4891 VTX 4909, 4910 } NET WIRE 5046, 0, 0 { VARIABLES { #NAME="DCORCONFIGr" } } TEXT 5047, 0, 0 { TEXT "$#NAME" RECT (3104,1310,3277,1339) ALIGN 9 MARGINS (1,1) PARENT 2279 } NET WIRE 5051, 0, 0 { VARIABLES { #NAME="DCORI2CCNTr" } } TEXT 5052, 0, 0 { TEXT "$#NAME" RECT (3238,1330,3402,1359) ALIGN 9 MARGINS (1,1) PARENT 2322 } NET WIRE 5056, 0, 0 { VARIABLES { #NAME="DCORLIMITSr" } } TEXT 5057, 0, 0 { TEXT "$#NAME" RECT (3643,1350,3797,1379) ALIGN 9 MARGINS (1,1) PARENT 2274 } NET WIRE 5061, 0, 0 { VARIABLES { #NAME="DCORENCPWRr" } } TEXT 5062, 0, 0 { TEXT "$#NAME" RECT (3877,1370,4063,1399) ALIGN 9 MARGINS (1,1) PARENT 2265 } NET WIRE 5066, 0, 0 { VARIABLES { #NAME="DCORENCPWRw" } } TEXT 5067, 0, 0 { TEXT "$#NAME" RECT (3873,1390,4068,1419) ALIGN 9 MARGINS (1,1) PARENT 2260 } NET WIRE 5071, 0, 0 { VARIABLES { #NAME="DCOROUTw" } } TEXT 5072, 0, 0 { TEXT "$#NAME" RECT (4161,1410,4300,1439) ALIGN 9 MARGINS (1,1) PARENT 2211 } NET WIRE 5076, 0, 0 { VARIABLES { #NAME="DCORIFGw" } } TEXT 5077, 0, 0 { TEXT "$#NAME" RECT (4376,1430,4505,1459) ALIGN 9 MARGINS (1,1) PARENT 2244 } NET WIRE 5081, 0, 0 { VARIABLES { #NAME="DCORIFGr" } } TEXT 5082, 0, 0 { TEXT "$#NAME" RECT (4380,1450,4500,1479) ALIGN 9 MARGINS (1,1) PARENT 7970 } TEXT 5087, 0, 0 { TEXT "$#NAME" RECT (4349,1470,4532,1499) ALIGN 9 MARGINS (1,1) PARENT 7126 } NET WIRE 5091, 0, 0 { VARIABLES { #NAME="DCOR1THRESLOWr" } } TEXT 5092, 0, 0 { TEXT "$#NAME" RECT (4326,1490,4554,1519) ALIGN 9 MARGINS (1,1) PARENT 7121 } TEXT 5097, 0, 0 { TEXT "$#NAME" RECT (4324,1511,4556,1540) ALIGN 9 MARGINS (1,1) PARENT 7170 } TEXT 5107, 0, 0 { TEXT "$#NAME" RECT (4342,1550,4538,1579) ALIGN 9 MARGINS (1,1) PARENT 7111 } VERILOGDESIGNUNITHDR 5111, 0, 0 { LABEL "Design Unit Header" TEXT "`timescale 1ns / 1ns\n"+ "//synthesis attribute KEEP of DCORIEw is TRUE;\n"+ "//synthesis attribute KEEP of DCORIFGw is TRUE;\n"+ "//synthesis attribute KEEP of DCORIFGr is TRUE;\n"+ "//synthesis attribute KEEP of DCORLIMITSr is TRUE;\n"+ "//synthesis attribute KEEP of DCORENCCTLw is TRUE;\n"+ "//synthesis attribute KEEP of DCOR1CNTLOWr is TRUE;\n"+ "//s-ynthesis attribute KEEP of DCOR1CNTMIDr is TRUE;\n"+ "//synthesis attribute KEEP of DCOR1THRESLOWr is TRUE;\n"+ "//synthesis attribute KEEP of DCOR1THRESHIGHr is TRUE;\n"+ "//synthesis attribute KEEP of DCOR0CNTLOWr is TRUE;\n"+ "//s-ynthesis attribute KEEP of DCOR0CNTMIDr is TRUE;\n"+ "//synthesis attribute KEEP of DCOR0CNTHIGHr is TRUE;\n"+ "//synthesis attribute KEEP of DCOR1CNTHIGHr is TRUE;\n"+ "//synthesis attribute KEEP of DCOR0THRESLOWr is TRUE;\n"+ "//synthesis attribute KEEP of DCOR0THRESHIGHr is TRUE\n"+ "//synthesis attribute KEEP of DCORENCPWRr is TRUE;\n"+ "//synthesis attribute KEEP of DCORENCPWRw is TRUE;\n"+ "//synthesis attribute KEEP of DCORCONFIGr is TRUE;\n"+ "//synthesis attribute KEEP of DCOROUTw is TRUE;\n"+ "//synthesis attribute KEEP of DCORI2CCNTr is TRUE;\n"+ "//synthesis attribute KEEP of DCORSENSORw is TRUE;\n"+ "//synthesis attribute KEEP of DCORLINTr is TRUE;\n"+ "" RECT (5680,1060,6560,1960) MARGINS (20,20) MULTILINE SYNTAXCOLORED SHOWLABEL SHOWTEXT CORNER 10 } NET WIRE 5140, 0, 0 { VARIABLES { #NAME="DCORENCCTLw" } } NET WIRE 5141, 0, 0 { VARIABLES { #NAME="DCOR1CNTLOWr" } } NET WIRE 5170, 0, 0 { VARIABLES { #NAME="DCORIEw" } } TEXT 5171, 0, 0 { TEXT "$#NAME" RECT (4595,1690,4706,1719) ALIGN 9 MARGINS (1,1) PARENT 2124 } NET WIRE 5203, 0, 0 { VARIABLES { #NAME="DCOR1CNTHIGHr" } } TEXT 5204, 0, 0 { TEXT "$#NAME" RECT (4340,1570,4540,1599) ALIGN 9 MARGINS (1,1) PARENT 7106 } NET WIRE 5208, 0, 0 { VARIABLES { #NAME="DCOR0CNTHIGHr" } } TEXT 5209, 0, 0 { TEXT "$#NAME" RECT (4340,1590,4540,1619) ALIGN 9 MARGINS (1,1) PARENT 7096 } NET WIRE 5218, 0, 0 { VARIABLES { #NAME="DCOR0CNTLOWr" } } TEXT 5219, 0, 0 { TEXT "$#NAME" RECT (4342,1630,4538,1659) ALIGN 9 MARGINS (1,1) PARENT 7101 } TEXT 5224, 0, 0 { TEXT "$#NAME" RECT (4324,1650,4556,1679) ALIGN 9 MARGINS (1,1) PARENT 7165 } NET WIRE 5228, 0, 0 { VARIABLES { #NAME="DCOR0THRESLOWr" } } TEXT 5229, 0, 0 { TEXT "$#NAME" RECT (4326,1670,4554,1699) ALIGN 9 MARGINS (1,1) PARENT 7116 } VTX 5298, 0, 0 { COORD (4540,1480) } VTX 5299, 0, 0 { COORD (4540,1780) } WIRE 5301, 0, 0 { NET 5081 VTX 5298, 2190 } WIRE 5303, 0, 0 { NET 5081 VTX 5298, 5299 } VTX 5332, 0, 0 { COORD (4560,1260) } VTX 5333, 0, 0 { COORD (4580,1780) } BUS 5334, 0, 0 { NET 3538 VTX 1919, 5332 } BUS 5335, 0, 0 { NET 3538 VTX 5332, 1925 } VTX 5337, 0, 0 { COORD (4560,1320) } BUS 5338, 0, 0 { NET 3538 VTX 5332, 5337 } VTX 5339, 0, 0 { COORD (4580,1320) } BUS 5340, 0, 0 { NET 3538 VTX 5337, 5339 } BUS 5341, 0, 0 { NET 3538 VTX 5339, 5333 } NET WIRE 5520, 0, 0 { VARIABLES { #NAME="DCOR1THRESHIGHr" } } NET WIRE 5521, 0, 0 { VARIABLES { #NAME="DCOR0THRESHIGHr" } } VTX 7042, 0, 0 { COORD (4080,2380) } VTX 7043, 0, 0 { COORD (4120,2800) } VTX 7044, 0, 0 { COORD (4120,2380) } VTX 7045, 0, 0 { COORD (4100,2800) } VTX 7046, 0, 0 { COORD (4100,2380) } VTX 7047, 0, 0 { COORD (4220,1800) } VTX 7048, 0, 0 { COORD (4180,1800) } VTX 7049, 0, 0 { COORD (4840,1780) } VTX 7050, 0, 0 { COORD (4040,1800) } VTX 7051, 0, 0 { COORD (4800,1780) } VTX 7052, 0, 0 { COORD (4080,1800) } VTX 7053, 0, 0 { COORD (4860,1780) } VTX 7054, 0, 0 { COORD (4020,1800) } VTX 7055, 0, 0 { COORD (4880,1780) } VTX 7056, 0, 0 { COORD (4000,1800) } VTX 7057, 0, 0 { COORD (4760,1780) } VTX 7058, 0, 0 { COORD (4120,1800) } VTX 7059, 0, 0 { COORD (4940,1780) } VTX 7060, 0, 0 { COORD (3940,1800) } VTX 7061, 0, 0 { COORD (4960,1780) } VTX 7062, 0, 0 { COORD (3920,1800) } VTX 7063, 0, 0 { COORD (3900,1800) } VTX 7064, 0, 0 { COORD (3880,1800) } VTX 7065, 0, 0 { COORD (4060,2380) } VTX 7066, 0, 0 { COORD (3920,2380) } VTX 7067, 0, 0 { COORD (3900,2380) } VTX 7068, 0, 0 { COORD (3960,2800) } VTX 7069, 0, 0 { COORD (3960,2380) } VTX 7070, 0, 0 { COORD (3940,2800) } VTX 7071, 0, 0 { COORD (3940,2380) } VTX 7072, 0, 0 { COORD (4420,1780) } VTX 7073, 0, 0 { COORD (3780,1800) } VTX 7074, 0, 0 { COORD (4440,1780) } VTX 7075, 0, 0 { COORD (3760,1800) } VTX 7076, 0, 0 { COORD (4460,1780) } VTX 7077, 0, 0 { COORD (3720,1800) } VTX 7078, 0, 0 { COORD (4480,1780) } VTX 7079, 0, 0 { COORD (3700,1800) } VTX 7080, 0, 0 { COORD (5540,1780) } VTX 7081, 0, 0 { COORD (3820,1800) } VTX 7082, 0, 0 { COORD (4780,1780) } VTX 7083, 0, 0 { COORD (4100,1800) } VTX 7084, 0, 0 { COORD (4920,1780) } VTX 7085, 0, 0 { COORD (3960,1800) } VTX 7086, 0, 0 { COORD (4080,2580) } WIRE 7087, 0, 0 { NET 2784 VTX 2778, 7086 } WIRE 7088, 0, 0 { NET 2784 VTX 7086, 7042 } WIRE 7089, 0, 0 { NET 689 VTX 7043, 7044 } WIRE 7090, 0, 0 { NET 695 VTX 7045, 7046 } BUS 7091, 0, 0 { NET 3547 VTX 1804, 7047 VARIABLES { #NAMED="1" } } BUS 7092, 0, 0 { NET 3538 VTX 1925, 7048 } VTX 7093, 0, 0 { COORD (4840,1620) } WIRE 7094, 0, 0 { NET 5208 VTX 7049, 7093 } VTX 7095, 0, 0 { COORD (4040,1620) } WIRE 7096, 0, 0 { NET 5208 VTX 7093, 7095 VARIABLES { #NAMED="1" } } WIRE 7097, 0, 0 { NET 5208 VTX 7095, 7050 } VTX 7098, 0, 0 { COORD (4800,1660) } WIRE 7099, 0, 0 { NET 5218 VTX 7051, 7098 } VTX 7100, 0, 0 { COORD (4080,1660) } WIRE 7101, 0, 0 { NET 5218 VTX 7098, 7100 VARIABLES { #NAMED="1" } } WIRE 7102, 0, 0 { NET 5218 VTX 7100, 7052 } VTX 7103, 0, 0 { COORD (4860,1600) } WIRE 7104, 0, 0 { NET 5203 VTX 7053, 7103 } VTX 7105, 0, 0 { COORD (4020,1600) } WIRE 7106, 0, 0 { NET 5203 VTX 7103, 7105 VARIABLES { #NAMED="1" } } WIRE 7107, 0, 0 { NET 5203 VTX 7105, 7054 } VTX 7108, 0, 0 { COORD (4880,1580) } WIRE 7109, 0, 0 { NET 5141 VTX 7055, 7108 } VTX 7110, 0, 0 { COORD (4000,1580) } WIRE 7111, 0, 0 { NET 5141 VTX 7108, 7110 VARIABLES { #NAMED="1" } } WIRE 7112, 0, 0 { NET 5141 VTX 7110, 7056 } VTX 7113, 0, 0 { COORD (4760,1700) } WIRE 7114, 0, 0 { NET 5228 VTX 7057, 7113 } VTX 7115, 0, 0 { COORD (4120,1700) } WIRE 7116, 0, 0 { NET 5228 VTX 7113, 7115 VARIABLES { #NAMED="1" } } WIRE 7117, 0, 0 { NET 5228 VTX 7115, 7058 } VTX 7118, 0, 0 { COORD (4940,1520) } WIRE 7119, 0, 0 { NET 5091 VTX 7059, 7118 } VTX 7120, 0, 0 { COORD (3940,1520) } WIRE 7121, 0, 0 { NET 5091 VTX 7118, 7120 VARIABLES { #NAMED="1" } } WIRE 7122, 0, 0 { NET 5091 VTX 7120, 7060 } VTX 7123, 0, 0 { COORD (4960,1500) } WIRE 7124, 0, 0 { NET 5140 VTX 7061, 7123 } VTX 7125, 0, 0 { COORD (3920,1500) } WIRE 7126, 0, 0 { NET 5140 VTX 7123, 7125 VARIABLES { #NAMED="1" } } WIRE 7127, 0, 0 { NET 5140 VTX 7125, 7062 } WIRE 7128, 0, 0 { NET 5081 VTX 1979, 7063 } WIRE 7129, 0, 0 { NET 5076 VTX 1990, 7064 } WIRE 7130, 0, 0 { NET 1524 VTX 1517, 7065 } VTX 7131, 0, 0 { COORD (3920,2560) } WIRE 7132, 0, 0 { NET 2773 VTX 2769, 7131 } WIRE 7133, 0, 0 { NET 2773 VTX 7131, 7066 } WIRE 7134, 0, 0 { NET 1533 VTX 1525, 7067 } WIRE 7135, 0, 0 { NET 703 VTX 7068, 7069 } WIRE 7136, 0, 0 { NET 707 VTX 7070, 7071 } VTX 7137, 0, 0 { COORD (4420,1180) } WIRE 7138, 0, 0 { NET 2482 VTX 7072, 7137 } VTX 7139, 0, 0 { COORD (3780,1180) } WIRE 7140, 0, 0 { NET 2482 VTX 7137, 7139 } WIRE 7141, 0, 0 { NET 2482 VTX 7139, 7073 } VTX 7142, 0, 0 { COORD (4440,1160) } WIRE 7143, 0, 0 { NET 2493 VTX 7074, 7142 } VTX 7144, 0, 0 { COORD (3760,1160) } WIRE 7145, 0, 0 { NET 2493 VTX 7142, 7144 } WIRE 7146, 0, 0 { NET 2493 VTX 7144, 7075 } VTX 7147, 0, 0 { COORD (4460,1140) } WIRE 7148, 0, 0 { NET 10376 VTX 7076, 7147 } VTX 7149, 0, 0 { COORD (3720,1140) } WIRE 7150, 0, 0 { NET 10376 VTX 7147, 7149 } VTX 7152, 0, 0 { COORD (4480,1120) } WIRE 7153, 0, 0 { NET 2512 VTX 7078, 7152 } VTX 7154, 0, 0 { COORD (3700,1120) } WIRE 7155, 0, 0 { NET 2512 VTX 7152, 7154 } WIRE 7156, 0, 0 { NET 2512 VTX 7154, 7079 } VTX 7157, 0, 0 { COORD (5540,1040) } WIRE 7158, 0, 0 { NET 4826 VTX 7080, 7157 } VTX 7159, 0, 0 { COORD (3820,1040) } WIRE 7160, 0, 0 { NET 4826 VTX 7157, 7159 } WIRE 7161, 0, 0 { NET 4826 VTX 7159, 7081 } VTX 7162, 0, 0 { COORD (4780,1680) } WIRE 7163, 0, 0 { NET 5521 VTX 7082, 7162 } VTX 7164, 0, 0 { COORD (4100,1680) } WIRE 7165, 0, 0 { NET 5521 VTX 7162, 7164 VARIABLES { #NAMED="1" } } WIRE 7166, 0, 0 { NET 5521 VTX 7164, 7083 } VTX 7167, 0, 0 { COORD (4920,1540) } WIRE 7168, 0, 0 { NET 5520 VTX 7084, 7167 } VTX 7169, 0, 0 { COORD (3960,1540) } WIRE 7170, 0, 0 { NET 5520 VTX 7167, 7169 VARIABLES { #NAMED="1" } } WIRE 7171, 0, 0 { NET 5520 VTX 7169, 7085 } WIRE 7970, 0, 0 { NET 5081 VTX 1979, 5298 VARIABLES { #NAMED="1" } } VTX 8116, 0, 0 { COORD (1640,1580) } VTX 8117, 0, 0 { COORD (1620,1580) } WIRE 8119, 0, 0 { NET 8122 VTX 8117, 2540 OUTLINE 0,1, (0,4,255) } WIRE 8121, 0, 0 { NET 8122 VTX 8116, 8117 } NET WIRE 8122, 0, 0 NET WIRE 8129, 0, 0 INSTANCE 8158, 0, 0 { VARIABLES { #COMPONENT="Input" #LIBRARY="#terminals" #REFERENCE="PWM3" #SYMBOL="Input" #VERILOG_TYPE="wire" } COORD (4060,3640) VERTEXES ( (2,9987) ) } TEXT 8159, 0, 0 { TEXT "$#REFERENCE" RECT (3919,3623,4009,3658) ALIGN 6 MARGINS (1,1) PARENT 8158 } INSTANCE 8163, 0, 0 { VARIABLES { #COMPONENT="Output" #LIBRARY="#terminals" #REFERENCE="GPIO9" #SYMBOL="Output" } COORD (4260,3660) VERTEXES ( (2,9720) ) } TEXT 8164, 0, 0 { TEXT "$#REFERENCE" RECT (4312,3643,4402,3678) ALIGN 4 MARGINS (1,1) PARENT 8163 } INSTANCE 8259, 0, 0 { VARIABLES { #COMPONENT="Sensor" #LIBRARY="#default" #REFERENCE="U8" #SYMBOL="Sensor" } COORD (840,1780) VERTEXES ( (13,8316), (18,8377), (23,8305), (28,8307), (33,8309), (38,8311) ) } TEXT 8260, 0, 0 { TEXT "$#COMPONENT" RECT (1040,2100,1134,2135) MARGINS (1,1) PARENT 8259 } TEXT 8264, 0, 0 { TEXT "$#REFERENCE" RECT (840,1744,879,1779) ALIGN 8 MARGINS (1,1) PARENT 8259 } INSTANCE 8268, 0, 0 { VARIABLES { #COMPONENT="Output" #LIBRARY="#terminals" #REFERENCE="TmpSlct" #SYMBOL="Output" #VERILOG_TYPE="wire" } COORD (1000,2840) ORIENTATION 5 VERTEXES ( (2,8304) ) } TEXT 8269, 0, 0 { TEXT "$#REFERENCE" RECT (982,2892,1017,3003) ALIGN 1 MARGINS (1,1) PARENT 8268 ORIENTATION 5 } INSTANCE 8273, 0, 0 { VARIABLES { #COMPONENT="Output" #LIBRARY="#terminals" #REFERENCE="TmpEn" #SYMBOL="Output" #VERILOG_TYPE="wire" } COORD (960,2840) ORIENTATION 5 VERTEXES ( (2,8306) ) } TEXT 8274, 0, 0 { TEXT "$#REFERENCE" RECT (942,2892,977,2989) ALIGN 1 MARGINS (1,1) PARENT 8273 ORIENTATION 5 } INSTANCE 8278, 0, 0 { VARIABLES { #COMPONENT="Output" #LIBRARY="#terminals" #REFERENCE="PresEn" #SYMBOL="Output" #VERILOG_TYPE="wire" } COORD (920,2840) ORIENTATION 5 VERTEXES ( (2,8308) ) } TEXT 8279, 0, 0 { TEXT "$#REFERENCE" RECT (902,2892,937,2989) ALIGN 1 MARGINS (1,1) PARENT 8278 ORIENTATION 5 } INSTANCE 8283, 0, 0 { VARIABLES { #COMPONENT="Output" #LIBRARY="#terminals" #REFERENCE="PresSlct" #SYMBOL="Output" #VERILOG_TYPE="wire" } COORD (880,2840) ORIENTATION 5 VERTEXES ( (2,8310) ) } TEXT 8284, 0, 0 { TEXT "$#REFERENCE" RECT (862,2892,897,3003) ALIGN 1 MARGINS (1,1) PARENT 8283 ORIENTATION 5 } NET WIRE 8288, 0, 0 NET WIRE 8296, 0, 0 NET WIRE 8300, 0, 0 VTX 8304, 0, 0 { COORD (1000,2840) } VTX 8305, 0, 0 { COORD (1000,2080) } VTX 8306, 0, 0 { COORD (960,2840) } VTX 8307, 0, 0 { COORD (960,2080) } VTX 8308, 0, 0 { COORD (920,2840) } VTX 8309, 0, 0 { COORD (920,2080) } VTX 8310, 0, 0 { COORD (880,2840) } VTX 8311, 0, 0 { COORD (880,2080) } WIRE 8312, 0, 0 { NET 8288 VTX 8304, 8305 } WIRE 8314, 0, 0 { NET 8296 VTX 8308, 8309 } WIRE 8315, 0, 0 { NET 8300 VTX 8310, 8311 } VTX 8316, 0, 0 { COORD (1000,1780) } VTX 8317, 0, 0 { COORD (1000,1220) } BUS 8319, 0, 0 { NET 8493 VTX 8317, 8316 VARIABLES { #NAMED="1" } } NET WIRE 8332, 0, 0 { VARIABLES { #NAME="DCORSENSORw" } } TEXT 8333, 0, 0 { TEXT "$#NAME" RECT (3515,1530,3705,1559) ALIGN 9 MARGINS (1,1) PARENT 8381 } VTX 8376, 0, 0 { COORD (4900,1780) } VTX 8377, 0, 0 { COORD (960,1780) } VTX 8378, 0, 0 { COORD (4900,1560) } WIRE 8379, 0, 0 { NET 8332 VTX 8376, 8378 } VTX 8380, 0, 0 { COORD (960,1560) } WIRE 8381, 0, 0 { NET 8332 VTX 8378, 8380 VARIABLES { #NAMED="1" } } VTX 8447, 0, 0 { COORD (5960,3160) } NET WIRE 8450, 0, 0 { VARIABLES { #NAME="Reset" } } TEXT 8451, 0, 0 { TEXT "$#NAME" RECT (5898,3130,5962,3159) ALIGN 9 MARGINS (1,1) PARENT 10082 } NET BUS 8493, 0, 0 { VARIABLES { #NAME="inDATA(3:0)" #VERILOG_TYPE="wire" } } TEXT 8494, 0, 0 { TEXT "$#NAME" RECT (1002,1486,1133,1515) ALIGN 4 MARGINS (1,1) PARENT 8319 } INSTANCE 8526, 0, 0 { VARIABLES { #COMPONENT="Input" #LIBRARY="#terminals" #REFERENCE="INTbus" #SYMBOL="Input" #VERILOG_TYPE="wire" } COORD (4560,2800) ORIENTATION 6 VERTEXES ( (2,8536) ) } TEXT 8527, 0, 0 { TEXT "$#REFERENCE" RECT (4542,2851,4577,2947) ALIGN 1 MARGINS (1,1) PARENT 8526 ORIENTATION 6 } NET WIRE 8531, 0, 0 VTX 8535, 0, 0 { COORD (4560,2000) } VTX 8536, 0, 0 { COORD (4560,2800) } WIRE 8537, 0, 0 { NET 8531 VTX 8535, 8536 } INSTANCE 8594, 0, 0 { VARIABLES { #COMPONENT="Output" #LIBRARY="#terminals" #REFERENCE="GPIO8" #SYMBOL="Output" } COORD (4220,3920) VERTEXES ( (2,10041) ) } TEXT 8595, 0, 0 { TEXT "$#REFERENCE" RECT (4272,3903,4362,3938) ALIGN 4 MARGINS (1,1) PARENT 8594 } INSTANCE 8599, 0, 0 { VARIABLES { #COMPONENT="Input" #LIBRARY="#terminals" #REFERENCE="PWM5" #SYMBOL="Input" #VERILOG_TYPE="wire" } COORD (4060,3920) VERTEXES ( (2,10042) ) } TEXT 8600, 0, 0 { TEXT "$#REFERENCE" RECT (3919,3903,4009,3938) ALIGN 6 MARGINS (1,1) PARENT 8599 } INSTANCE 8639, 0, 0 { VARIABLES { #COMPONENT="Input" #LIBRARY="#terminals" #REFERENCE="MSPReset" #SYMBOL="Input" } COORD (5720,3160) VERTEXES ( (2,9014) ) } TEXT 8640, 0, 0 { TEXT "$#REFERENCE" RECT (5530,3143,5669,3178) ALIGN 6 MARGINS (1,1) PARENT 8639 } WIRE 8933, 0, 0 { NET 8129 VTX 1490, 1491 } WIRE 8968, 0, 0 { NET 8332 VTX 8380, 8377 } INSTANCE 9006, 0, 0 { VARIABLES { #COMPONENT="inv" #LIBRARY="#builtin" #REFERENCE="U10" #SYMBOL="inv" } COORD (5780,3140) VERTEXES ( (2,9015), (4,9017) ) } NET WIRE 9007, 0, 0 VTX 9014, 0, 0 { COORD (5720,3160) } VTX 9015, 0, 0 { COORD (5780,3160) } WIRE 9016, 0, 0 { NET 9007 VTX 9014, 9015 } VTX 9017, 0, 0 { COORD (5900,3160) } INSTANCE 9153, 0, 0 { VARIABLES { #COMPONENT="Input" #LIBRARY="#terminals" #REFERENCE="MReset" #SYMBOL="Input" #VERILOG_TYPE="wire" } COORD (5720,3100) } TEXT 9154, 0, 0 { TEXT "$#REFERENCE" RECT (5568,3083,5669,3118) ALIGN 6 MARGINS (1,1) PARENT 9153 } INSTANCE 9158, 0, 0 { VARIABLES { #COMPONENT="Global" #LIBRARY="#connectors" #REFERENCE="MReset" #SYMBOL="Global" #VERILOG_TYPE="wire" } COORD (5760,3100) } TEXT 9159, 0, 0 { TEXT "$#REFERENCE" RECT (5775,3083,5876,3118) ALIGN 4 MARGINS (1,1) PARENT 9158 } VTX 9191, 0, 0 { COORD (3320,2420) } WIRE 9193, 0, 0 { NET 9199 VTX 838, 9191 } WIRE 9194, 0, 0 { NET 9199 VTX 9191, 839 } NET WIRE 9199, 0, 0 VTX 9256, 0, 0 { COORD (2420,1780) } VTX 9260, 0, 0 { COORD (2420,1020) } WIRE 9262, 0, 0 { NET 9270 VTX 9256, 9260 } VTX 9265, 0, 0 { COORD (5140,1780) } VTX 9266, 0, 0 { COORD (5140,1020) } WIRE 9268, 0, 0 { NET 9270 VTX 9266, 9265 } WIRE 9269, 0, 0 { NET 9270 VTX 9260, 9266 VARIABLES { #NAMED="1" } } NET WIRE 9270, 0, 0 { VARIABLES { #NAME="DCORLINTr" } } TEXT 9271, 0, 0 { TEXT "$#NAME" RECT (3715,990,3845,1019) ALIGN 9 MARGINS (1,1) PARENT 9269 } VTX 9331, 0, 0 { COORD (1960,2020) } VTX 9334, 0, 0 { COORD (2080,2840) } VTX 9335, 0, 0 { COORD (2100,2020) } VTX 9340, 0, 0 { COORD (1980,2020) } VTX 9341, 0, 0 { COORD (2000,2020) } VTX 9342, 0, 0 { COORD (2000,2840) } VTX 9343, 0, 0 { COORD (2020,2020) } VTX 9350, 0, 0 { COORD (2060,2840) } VTX 9351, 0, 0 { COORD (2080,2020) } VTX 9352, 0, 0 { COORD (2040,2840) } VTX 9353, 0, 0 { COORD (2060,2020) } VTX 9354, 0, 0 { COORD (2020,2840) } VTX 9355, 0, 0 { COORD (2040,2020) } VTX 9356, 0, 0 { COORD (1960,2420) } WIRE 9357, 0, 0 { NET 9199 VTX 9191, 9356 } WIRE 9358, 0, 0 { NET 9199 VTX 9356, 9331 } VTX 9364, 0, 0 { COORD (2080,2440) } WIRE 9365, 0, 0 { NET 1226 VTX 9334, 9364 } VTX 9366, 0, 0 { COORD (2100,2440) } WIRE 9367, 0, 0 { NET 1226 VTX 9364, 9366 } WIRE 9368, 0, 0 { NET 1226 VTX 9366, 9335 } VTX 9380, 0, 0 { COORD (1980,2280) } WIRE 9381, 0, 0 { NET 1381 VTX 1374, 9380 } WIRE 9382, 0, 0 { NET 1381 VTX 9380, 9340 } VTX 9383, 0, 0 { COORD (2000,2260) } WIRE 9384, 0, 0 { NET 1372 VTX 1365, 9383 } WIRE 9385, 0, 0 { NET 1372 VTX 9383, 9341 } VTX 9386, 0, 0 { COORD (2000,2340) } WIRE 9387, 0, 0 { NET 1253 VTX 9342, 9386 } VTX 9388, 0, 0 { COORD (2020,2340) } WIRE 9389, 0, 0 { NET 1253 VTX 9386, 9388 } WIRE 9390, 0, 0 { NET 1253 VTX 9388, 9343 } VTX 9406, 0, 0 { COORD (2060,2400) } WIRE 9407, 0, 0 { NET 1232 VTX 9350, 9406 } VTX 9408, 0, 0 { COORD (2080,2400) } WIRE 9409, 0, 0 { NET 1232 VTX 9406, 9408 } WIRE 9410, 0, 0 { NET 1232 VTX 9408, 9351 } VTX 9411, 0, 0 { COORD (2040,2380) } WIRE 9412, 0, 0 { NET 1238 VTX 9352, 9411 } VTX 9413, 0, 0 { COORD (2060,2380) } WIRE 9414, 0, 0 { NET 1238 VTX 9411, 9413 } WIRE 9415, 0, 0 { NET 1238 VTX 9413, 9353 } VTX 9416, 0, 0 { COORD (2020,2360) } WIRE 9417, 0, 0 { NET 1244 VTX 9354, 9416 } VTX 9418, 0, 0 { COORD (2040,2360) } WIRE 9419, 0, 0 { NET 1244 VTX 9416, 9418 } WIRE 9420, 0, 0 { NET 1244 VTX 9418, 9355 } VTX 9421, 0, 0 { COORD (1840,2840) } VTX 9422, 0, 0 { COORD (1840,2020) } VTX 9423, 0, 0 { COORD (1780,2020) } VTX 9424, 0, 0 { COORD (1800,2020) } VTX 9425, 0, 0 { COORD (1820,2840) } VTX 9426, 0, 0 { COORD (1820,2020) } VTX 9427, 0, 0 { COORD (1880,2840) } VTX 9428, 0, 0 { COORD (1880,2020) } VTX 9429, 0, 0 { COORD (1860,2840) } VTX 9430, 0, 0 { COORD (1860,2020) } VTX 9431, 0, 0 { COORD (1900,2840) } VTX 9432, 0, 0 { COORD (1900,2020) } WIRE 9433, 0, 0 { NET 1359 VTX 9421, 9422 } VTX 9434, 0, 0 { COORD (1780,2320) } WIRE 9435, 0, 0 { NET 1399 VTX 1392, 9434 } WIRE 9436, 0, 0 { NET 1399 VTX 9434, 9423 } VTX 9437, 0, 0 { COORD (1800,2300) } WIRE 9438, 0, 0 { NET 1390 VTX 1383, 9437 } WIRE 9439, 0, 0 { NET 1390 VTX 9437, 9424 } WIRE 9440, 0, 0 { NET 1360 VTX 9425, 9426 } WIRE 9441, 0, 0 { NET 1357 VTX 9427, 9428 } WIRE 9442, 0, 0 { NET 1358 VTX 9429, 9430 } WIRE 9443, 0, 0 { NET 1363 VTX 9431, 9432 } VTX 9499, 0, 0 { COORD (4060,3680) } VTX 9502, 0, 0 { COORD (3920,3680) } WIRE 9503, 0, 0 { NET 9527 VTX 9499, 9502 } VTX 9507, 0, 0 { COORD (3920,3720) } WIRE 9509, 0, 0 { NET 9527 VTX 9502, 9507 } VTX 9519, 0, 0 { COORD (960,2820) } WIRE 9520, 0, 0 { NET 9527 VTX 8306, 9519 } WIRE 9521, 0, 0 { NET 9527 VTX 9519, 8307 } NET WIRE 9527, 0, 0 VTX 9528, 0, 0 { COORD (1120,2820) } WIRE 9529, 0, 0 { NET 9527 VTX 9519, 9528 } VTX 9530, 0, 0 { COORD (1120,3720) } WIRE 9531, 0, 0 { NET 9527 VTX 9528, 9530 } WIRE 9532, 0, 0 { NET 9527 VTX 9530, 9507 } NET WIRE 9715, 0, 0 VTX 9719, 0, 0 { COORD (4220,3660) } VTX 9720, 0, 0 { COORD (4260,3660) } WIRE 9721, 0, 0 { NET 9715 VTX 9719, 9720 } VTX 9759, 0, 0 { COORD (4020,3740) } VTX 9760, 0, 0 { COORD (3920,3740) } WIRE 9761, 0, 0 { NET 9527 VTX 9507, 9760 } WIRE 9762, 0, 0 { NET 9527 VTX 9760, 9759 } VTX 9794, 0, 0 { COORD (1940,2020) } VTX 9795, 0, 0 { COORD (2300,2180) } WIRE 9796, 0, 0 { NET 9802 VTX 1193, 9795 } WIRE 9797, 0, 0 { NET 9802 VTX 9795, 1194 } VTX 9799, 0, 0 { COORD (1940,2180) } WIRE 9800, 0, 0 { NET 9802 VTX 9794, 9799 } WIRE 9801, 0, 0 { NET 9802 VTX 9799, 9795 } NET WIRE 9802, 0, 0 VTX 9803, 0, 0 { COORD (2280,2200) } VTX 9804, 0, 0 { COORD (1920,2020) } WIRE 9805, 0, 0 { NET 9811 VTX 1195, 9803 } WIRE 9806, 0, 0 { NET 9811 VTX 9803, 1196 } VTX 9808, 0, 0 { COORD (1920,2200) } WIRE 9809, 0, 0 { NET 9811 VTX 9803, 9808 } WIRE 9810, 0, 0 { NET 9811 VTX 9808, 9804 } NET WIRE 9811, 0, 0 VTX 9812, 0, 0 { COORD (1760,2020) } VTX 9813, 0, 0 { COORD (2420,2220) } WIRE 9814, 0, 0 { NET 9820 VTX 1183, 9813 } WIRE 9815, 0, 0 { NET 9820 VTX 9813, 1184 } VTX 9817, 0, 0 { COORD (1760,2220) } WIRE 9818, 0, 0 { NET 9820 VTX 9812, 9817 } WIRE 9819, 0, 0 { NET 9820 VTX 9817, 9813 } NET WIRE 9820, 0, 0 VTX 9821, 0, 0 { COORD (2400,2240) } VTX 9822, 0, 0 { COORD (1740,2020) } WIRE 9823, 0, 0 { NET 9829 VTX 1185, 9821 } WIRE 9824, 0, 0 { NET 9829 VTX 9821, 1186 } VTX 9826, 0, 0 { COORD (1740,2240) } WIRE 9827, 0, 0 { NET 9829 VTX 9821, 9826 } WIRE 9828, 0, 0 { NET 9829 VTX 9826, 9822 } NET WIRE 9829, 0, 0 BUS 9858, 0, 0 { NET 8493 VTX 8317, 1868 BUSTAPS ( 9860 ) } VTX 9859, 0, 0 { COORD (2460,1780) } VTX 9860, 0, 0 { COORD (2460,1220) } WIRE 9862, 0, 0 { NET 9863 VTX 9859, 9860 VARIABLES { #NAMED="1" } } NET WIRE 9863, 0, 0 { VARIABLES { #NAME="inDATA(4)" } } TEXT 9864, 0, 0 { TEXT "$#NAME" RECT (2466,1580,2495,1691) ALIGN 1 MARGINS (1,1) PARENT 9862 ORIENTATION 5 } VTX 9898, 0, 0 { COORD (2360,2120) } WIRE 9899, 0, 0 { NET 1399 VTX 1392, 9898 } INSTANCE 9984, 0, 0 { VARIABLES { #COMPONENT="and2b1" #LIBRARY="#builtin" #REFERENCE="U13" #SYMBOL="and2b1" } COORD (4060,3620) VERTEXES ( (2,9499), (4,9719), (6,9986) ) } NET WIRE 9985, 0, 0 VTX 9986, 0, 0 { COORD (4060,3640) } VTX 9987, 0, 0 { COORD (4060,3640) } WIRE 9988, 0, 0 { NET 9985 VTX 9986, 9987 } INSTANCE 9989, 0, 0 { VARIABLES { #COMPONENT="and2b1" #LIBRARY="#builtin" #REFERENCE="U14" #SYMBOL="and2b1" } COORD (4020,3800) ORIENTATION 3 VERTEXES ( (2,9759), (4,10031), (6,10051) ) } INSTANCE 10022, 0, 0 { VARIABLES { #COMPONENT="Output" #LIBRARY="#terminals" #REFERENCE="GPIO10" #SYMBOL="Output" } COORD (4240,3760) VERTEXES ( (2,10032) ) } TEXT 10023, 0, 0 { TEXT "$#REFERENCE" RECT (4292,3743,4398,3778) ALIGN 4 MARGINS (1,1) PARENT 10022 } NET WIRE 10027, 0, 0 VTX 10031, 0, 0 { COORD (4180,3760) } VTX 10032, 0, 0 { COORD (4240,3760) } WIRE 10033, 0, 0 { NET 10027 VTX 10031, 10032 } NET WIRE 10037, 0, 0 VTX 10041, 0, 0 { COORD (4220,3920) } VTX 10042, 0, 0 { COORD (4060,3920) } WIRE 10043, 0, 0 { NET 10037 VTX 10041, 10042 } INSTANCE 10044, 0, 0 { VARIABLES { #COMPONENT="Input" #LIBRARY="#terminals" #REFERENCE="PWM4" #SYMBOL="Input" #VERILOG_TYPE="wire" } COORD (4020,3780) VERTEXES ( (2,10050) ) } TEXT 10045, 0, 0 { TEXT "$#REFERENCE" RECT (3879,3763,3969,3798) ALIGN 6 MARGINS (1,1) PARENT 10044 } NET WIRE 10049, 0, 0 VTX 10050, 0, 0 { COORD (4020,3780) } VTX 10051, 0, 0 { COORD (4020,3780) } WIRE 10052, 0, 0 { NET 10049 VTX 10050, 10051 } WIRE 10082, 0, 0 { NET 8450 VTX 9017, 8447 VARIABLES { #NAMED="1" } } WIRE 10181, 0, 0 { NET 3919 VTX 1488, 1489 } WIRE 10219, 0, 0 { NET 4281 VTX 1492, 1493 VARIABLES { #NAMED="1" } } VTX 10362, 0, 0 { COORD (1620,1780) } WIRE 10363, 0, 0 { NET 8122 VTX 10362, 8117 OUTLINE 0,1, (0,4,255) } INSTANCE 10364, 0, 0 { VARIABLES { #COMPONENT="Output" #LIBRARY="#terminals" #REFERENCE="TP26" #SYMBOL="Output" } COORD (3680,1680) ORIENTATION 2 VERTEXES ( (2,10369) ) } TEXT 10365, 0, 0 { TEXT "$#REFERENCE" RECT (3556,1663,3628,1698) ALIGN 6 MARGINS (1,1) PARENT 10364 ORIENTATION 2 } VTX 10369, 0, 0 { COORD (3680,1680) } VTX 10370, 0, 0 { COORD (3720,1680) } WIRE 10371, 0, 0 { NET 10376 VTX 7149, 10370 VARIABLES { #NAMED="1" } } WIRE 10372, 0, 0 { NET 10376 VTX 10370, 7077 } WIRE 10374, 0, 0 { NET 10376 VTX 10369, 10370 } NET WIRE 10376, 0, 0 { VARIABLES { #NAME="Tfound0" } } TEXT 10377, 0, 0 { TEXT "$#NAME" RECT (3720,1646,3811,1675) ALIGN 4 MARGINS (1,1) PARENT 10371 } INSTANCE 10409, 0, 0 { VARIABLES { #COMPONENT="Output" #LIBRARY="#terminals" #REFERENCE="TP21" #SYMBOL="Output" #VERILOG_TYPE="wire" } COORD (4440,2120) ORIENTATION 5 VERTEXES ( (2,10419) ) } TEXT 10410, 0, 0 { TEXT "$#REFERENCE" RECT (4422,2172,4457,2244) ALIGN 1 MARGINS (1,1) PARENT 10409 ORIENTATION 5 } NET WIRE 10414, 0, 0 VTX 10418, 0, 0 { COORD (4440,2000) } VTX 10419, 0, 0 { COORD (4440,2120) } WIRE 10420, 0, 0 { NET 10414 VTX 10418, 10419 } } } PAGE "" { PAGEHEADER { PAGESIZE (6800,4400) MARGINS (200,200,200,200) RECT (0,0,0,0) VARIABLES { #ARCHITECTURE="\\#TABLE\\" #BLOCKTABLE_PAGE="1" #BLOCKTABLE_TEMPL="1" #BLOCKTABLE_VISIBLE="0" #ENTITY="\\#TABLE\\" #MODIFIED="1076623972" } } BODY { TEXT 10477, 0, 0 { PAGEALIGN 10 OUTLINE 5,1, (0,0,0) TEXT "Created:" RECT (5740,4086,5857,4139) ALIGN 4 MARGINS (1,10) COLOR (0,0,0) FONT (12,0,0,700,0,0,0,"Arial") } TEXT 10478, 0, 0 { PAGEALIGN 10 TEXT "$CREATIONDATE" RECT (5910,4080,6580,4140) ALIGN 4 MARGINS (1,1) COLOR (0,0,0) FONT (12,0,0,700,0,128,0,"Arial") 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