//--------------------------------------------------------------------------------------------------
//
// Title       : Interrupt
// Design      : U21
// Author      : mbari###
// Company     : MBARI
//
//-------------------------------------------------------------------------------------------------
//
// File        : c:\Projects\genosensor\2g\CPLDs\Core\U21\src\Interrupt.v
// Generated   : Thu Mar  4 06:27:20 2004
// From        : interface description file
// By          : Itf2Vhdl ver. 1.20
//
//-------------------------------------------------------------------------------------------------
//
// Description : 
//
//-------------------------------------------------------------------------------------------------
`timescale 1ps / 1ps

//{{ Section below this comment is automatically maintained
//   and may be overwritten
//{module {Interrupt}}
module Interrupt ( DCORIFGr ,inDATA ,outDATA ,Reset ,TP ,PWRint ,BusInt ,Thres0 ,Mclk ,Thres1 ,I2Cint ,LSwitchInt ,INT ,DCORIEw ,Homed0 ,Homed1 );

input DCORIFGr ;
wire DCORIFGr ;
input [7:0] inDATA ;
wire [7:0] inDATA ;
input Reset ;
wire Reset ;
input PWRint ;
wire PWRint ;
input BusInt ;
wire BusInt ;
input Thres0 ;
wire Thres0 ;
input Mclk ;
wire Mclk ;
input Thres1 ;
wire Thres1 ;
input I2Cint ;
wire I2Cint ;
input LSwitchInt ;
wire LSwitchInt ;
input DCORIEw ;
wire DCORIEw ;
input Homed0 ;
wire Homed0 ;
input Homed1 ;
wire Homed1 ;

output [7:0] outDATA ;
wire [7:0] outDATA ;
output INT ;
wire INT ;
output TP ;
wire TP ;

//}} End of automatically maintained section

// -- Enter your statements here -- //

reg [7:0] DCORIE;	  

assign outDATA = (DCORIFGr) ? {I2Cint, 2'bz,LSwitchInt,3'bz,BusInt} : 8'bz;
 assign TP = DCORIE[5];
assign INT =    ((DCORIE[7] & I2Cint) | 
				(DCORIE[6] & Thres1) | 
				(DCORIE[5] & Thres0) | 
				(DCORIE[4] & LSwitchInt) | 
				(DCORIE[3] & Homed1) | 
				(DCORIE[2] & Homed0) | 
				(DCORIE[1] & PWRint) | 
				(DCORIE[0] & !BusInt));

always @ (negedge Mclk)
	begin
		if (Reset) DCORIE <= 8'b0;
		else if (DCORIEw) DCORIE <= (inDATA);
	end

endmodule