//--------------------------------------------------------------------------------------------------
//
// Title       : Lswitch
// Design      : U4
// Author      : mbari###
// Company     : MBARI
//
//-------------------------------------------------------------------------------------------------
//
// File        : c:\Projects\genosensor\2g\CPLDs\Core\U4\src\Lswitch.v
// Generated   : Wed Dec 17 14:13:49 2003
// From        : interface description file
// By          : Itf2Vhdl ver. 1.20
//
//-------------------------------------------------------------------------------------------------
//
// Description : 
//
//-------------------------------------------------------------------------------------------------
`timescale 1ps / 1ps

//{{ Section below this comment is automatically maintained
//   and may be overwritten
//{module {Lswitch}}
module Lswitch ( DIR1 ,DCORLINTr ,RLS0 ,outDATA ,LIFG ,RLS1 ,Reset ,fBRK0 ,DCORIFGw ,Brake0 ,FLS0 ,fBRK1 ,Brake1 ,FLS1 ,Mclk ,LSwitchInt ,Home0 ,Home1 ,DCORLIMITSr ,DIR0 );

input DIR1 ;
wire DIR1 ;
input DCORLINTr ;
wire DCORLINTr ;
input RLS0 ;
wire RLS0 ;
input LIFG ;
wire LIFG ;
input RLS1 ;
wire RLS1 ;
input Reset ;
wire Reset ;
input DCORIFGw ;
wire DCORIFGw ;
input Brake0 ;
wire Brake0 ;
input FLS0 ;
wire FLS0 ;
input Brake1 ;
wire Brake1 ;
input FLS1 ;
wire FLS1 ;
input Mclk ;
wire Mclk ;
input Home0 ;
wire Home0 ;
input Home1 ;
wire Home1 ;
input DCORLIMITSr ;
wire DCORLIMITSr ;
input DIR0 ;
wire DIR0 ;

output LSwitchInt ;
wire LSwitchInt ;
output [7:0] outDATA ;
wire [7:0] outDATA ;
output fBRK0 ;
wire fBRK0 ;
output fBRK1 ;
wire fBRK1 ;

//}} End of automatically maintained section

// -- Enter your statements here -- //						 

reg DCORIFG;		
//LSxr = delayed one state limit switch register   
//LSxfr = flag register which has detected a falling edge
reg FLS0r,RLS0r,FLS0fr,RLS0fr,FLS1r,RLS1r,FLS1fr,RLS1fr;
reg fBRK0r,fBRK1r;
wire Ftrip0, Ftrip1,Rtrip0, Rtrip1;

assign outDATA = (DCORLIMITSr) ?  {fBRK1r, Home1, !FLS1, !RLS1, fBRK0r, Home0, !FLS0, !RLS0} :
(DCORLINTr) ? {fBRK1r,1'b0,FLS1fr,RLS1fr,fBRK0r,1'b0,FLS0fr,RLS0fr} : 8'bz;

//assign trip1 =  ((DIR1 & !FLS1) | (!DIR1 & !RLS1));
//assign trip0 =  ((DIR0 & !FLS0) | (!DIR0 & !RLS0));

assign Ftrip0 =  (DIR0 && !FLS0 && FLS0r);
assign Rtrip0 =  (!DIR0 && !RLS0 && RLS0r);
assign Ftrip1 =  (DIR1 && !FLS1 && FLS1r);
assign Rtrip1 =  (!DIR1 && !RLS1 && RLS1r);


assign fBRK1 = fBRK1r;
assign fBRK0 = fBRK0r;

assign LSwitchInt = DCORIFG;

always @ (negedge Mclk)
	begin
		if (Reset) DCORIFG <= 1'b0;
		else 
			begin
				if (DCORIFGw) DCORIFG <= DCORIFG & ~LIFG;	 //This first so that flag can be reset
				else if  (FLS0fr|RLS0fr|FLS1fr|RLS1fr) DCORIFG <= 1'b1;
				else DCORIFG <= DCORIFG;
			end
	end							

 
always @ (negedge Mclk)
	begin
		if (Reset) {FLS0r,RLS0r,FLS0fr,RLS0fr,FLS1r,RLS1r,FLS1fr,RLS1fr} <= 8'b0;
		else 
			begin
			 FLS0r <= FLS0;
			 RLS0r <= RLS0;
			 FLS1r <= FLS1;
			 RLS1r <= RLS1;
			 if (DCORLINTr)
				 begin
					 {FLS0fr,RLS0fr,FLS1fr,RLS1fr} <= 4'b0;
			     end
		     else
				 begin
					 if (Ftrip0)  FLS0fr <= 1'b1;  //set the flag 
				     else  FLS0fr <= FLS0fr;		  //leave the flag as is

					 if (Rtrip0)  RLS0fr <= 1'b1;  //set the flag 
				     else  RLS0fr <= RLS0fr;		  //leave the flag as is
				     
					 if (Ftrip0 | Rtrip0) fBRK0r <= 1'b1;  //and set the brake
						else if ((Brake0) & (!FLS0fr) & (!RLS0fr)) fBRK0r <= 1'b0;   //release if manual brake applied 
					         else fBRK0r <= fBRK0r;    ///leave as is.
							 
					 if (Ftrip1)  FLS1fr <= 1'b1;  //set the flag 
				     else  FLS1fr <= FLS1fr;		  //leave the flag as is
					
					 if (Rtrip1)  RLS1fr <= 1'b1;  //set the flag 
				     else  RLS1fr <= RLS1fr;		  //leave the flag as is
				     
					 if (Ftrip1 | Rtrip1) fBRK1r <= 1'b1;  //and set the brake
						else if ((Brake1) & (!FLS1fr) & (!RLS1fr)) fBRK1r <= 1'b0;   //release if manual brake applied 
					         else fBRK1r <= fBRK1r;    ///leave as is.
			     end
			end
	end
 /*
always @ (negedge Mclk)
	begin
		if (Reset) {fBRK1r, fBRK0r} <= 2'b0;
		else
			begin
				if (trip1) fBRK1r <= 1'b1;  //apply brake
				else 
					if (Brake1) fBRK1r <= 1'b0;   //release if manual brake applied 
					else fBRK1r <= fBRK1r;    ///leave as is.

				if (trip0) fBRK0r <= 1'b1;  //apply brake
				else 
					if (Brake0) fBRK0r <= 1'b0;   //release if manual brake applied 
					else fBRK0r <= fBRK0r;    ///leave as is.
			end
	end	   
	*/
endmodule