////////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995-2008 Xilinx, Inc.  All rights reserved.
////////////////////////////////////////////////////////////////////////////////
//   ____  ____
//  /   /\/   /
// /___/  \  /    Vendor: Xilinx
// \   \   \/     Version: K.39
//  \   \         Application: netgen
//  /   /         Filename: U21.v
// /___/   /\     Timestamp: Mon Mar 09 10:11:44 2009
// \   \  /  \ 
//  \___\/\___\
//             
// Command	: -ofmt verilog -intstyle silent -w U21.ngc U21.v 
// Device	: xpla3
// Input file	: U21.ngc
// Output file	: U21.v
// # of Modules	: 21
// Design Name	: U21
// Xilinx        : C:\Xilinx\10.1\ISE
//             
// Purpose:    
//     This verilog netlist is a verification model and uses simulation 
//     primitives which may not represent the true implementation of the 
//     device, however the netlist is functionally correct and should not 
//     be modified. This file cannot be synthesized and should only be used 
//     with supported simulation tools.
//             
// Reference:  
//     Development System Reference Guide, Chapter 23 and Synthesis and Simulation Design Guide, Chapter 6
//             
////////////////////////////////////////////////////////////////////////////////

`timescale 1 ns/1 ps

module Counter_INST_1 (
  sense, ce, Reset, updown, Zero, Sclk, count
);
  input sense;
  input ce;
  input Reset;
  input updown;
  input Zero;
  input Sclk;
  output [15 : 0] count;
  wire N0;
  wire N01;
  wire N10;
  wire N11;
  wire N111;
  wire N12;
  wire N13;
  wire N14;
  wire N15;
  wire N16;
  wire N17;
  wire N18;
  wire N19;
  wire N2;
  wire N20;
  wire N21;
  wire N22;
  wire N23;
  wire N24;
  wire N25;
  wire N26;
  wire N27;
  wire N28;
  wire N3;
  wire N4;
  wire N5;
  wire N6;
  wire N7;
  wire N8;
  wire N9;
  wire SFDecomp_84;
  wire SFDecomp_85;
  wire SFDecomp_86;
  wire SFDecomp_87;
  wire location_0__and0000;
  wire location_0__and00001_1744;
  wire location_0__and00002_1745;
  wire location_0__or0000;
  wire location_10__and0000;
  wire location_10__and00001_1748;
  wire location_11__and0000;
  wire location_11__and00001_1750;
  wire location_12__and0000;
  wire location_12__and00001_1752;
  wire location_13__and0000;
  wire location_13__and00001_1754;
  wire location_14__and0000;
  wire location_14__and00001_1756;
  wire location_15__and0000;
  wire location_15__and00001_1758;
  wire location_1__and0000;
  wire location_1__and00001_1760;
  wire location_2__and0000;
  wire location_2__and00001_1762;
  wire location_3__and0000;
  wire location_3__and00001_1764;
  wire location_4__and0000;
  wire location_4__and00001_1766;
  wire location_5__and0000;
  wire location_5__and00001_1768;
  wire location_6__and0000;
  wire location_6__and00001_1770;
  wire location_7__and0000;
  wire location_7__and00001_1772;
  wire location_8__and0000;
  wire location_8__and00001_1774;
  wire location_9__and0000;
  wire location_9__and00001_1776;
  wire \location_Madd__add0000_CARRY_IN[10] ;
  wire \location_Madd__add0000_CARRY_IN<10>1_1778 ;
  wire \location_Madd__add0000_CARRY_IN<10>2_1779 ;
  wire \location_Madd__add0000_CARRY_IN<10>3_1780 ;
  wire \location_Madd__add0000_CARRY_IN[13] ;
  wire \location_Madd__add0000_CARRY_IN<13>1_1782 ;
  wire \location_Madd__add0000_CARRY_IN<13>2_1783 ;
  wire \location_Madd__add0000_CARRY_IN<13>3_1784 ;
  wire \location_Madd__add0000_CARRY_IN[4] ;
  wire \location_Madd__add0000_CARRY_IN<4>1_1786 ;
  wire \location_Madd__add0000_CARRY_IN<4>2_1787 ;
  wire \location_Madd__add0000_CARRY_IN<4>3_1788 ;
  wire \location_Madd__add0000_CARRY_IN[7] ;
  wire \location_Madd__add0000_CARRY_IN<7>1_1790 ;
  wire \location_Madd__add0000_CARRY_IN<7>2_1791 ;
  wire \location_Madd__add0000_CARRY_IN<7>3_1792 ;
  wire \location_Madd__add0000_Result<10>1_1794 ;
  wire \location_Madd__add0000_Result<10>2_1795 ;
  wire \location_Madd__add0000_Result<10>3_1796 ;
  wire \location_Madd__add0000_Result<11>1 ;
  wire \location_Madd__add0000_Result<11>11_1799 ;
  wire \location_Madd__add0000_Result<11>111_1800 ;
  wire \location_Madd__add0000_Result<11>12_1801 ;
  wire \location_Madd__add0000_Result<11>13_1802 ;
  wire \location_Madd__add0000_Result<11>14_1803 ;
  wire \location_Madd__add0000_Result<11>2_1804 ;
  wire \location_Madd__add0000_Result<11>3_1805 ;
  wire \location_Madd__add0000_Result<12>1 ;
  wire \location_Madd__add0000_Result<12>11_1808 ;
  wire \location_Madd__add0000_Result<12>12_1809 ;
  wire \location_Madd__add0000_Result<12>13_1810 ;
  wire \location_Madd__add0000_Result<12>14_1811 ;
  wire \location_Madd__add0000_Result<12>2_1812 ;
  wire \location_Madd__add0000_Result<12>3_1813 ;
  wire \location_Madd__add0000_Result<13>1_1815 ;
  wire \location_Madd__add0000_Result<13>2_1816 ;
  wire \location_Madd__add0000_Result<13>3_1817 ;
  wire \location_Madd__add0000_Result<14>1 ;
  wire \location_Madd__add0000_Result<14>11_1820 ;
  wire \location_Madd__add0000_Result<14>111_1821 ;
  wire \location_Madd__add0000_Result<14>12_1822 ;
  wire \location_Madd__add0000_Result<14>13_1823 ;
  wire \location_Madd__add0000_Result<14>14_1824 ;
  wire \location_Madd__add0000_Result<14>2_1825 ;
  wire \location_Madd__add0000_Result<14>3_1826 ;
  wire \location_Madd__add0000_Result<15>1 ;
  wire \location_Madd__add0000_Result<15>11_1829 ;
  wire \location_Madd__add0000_Result<15>12_1830 ;
  wire \location_Madd__add0000_Result<15>13_1831 ;
  wire \location_Madd__add0000_Result<15>14_1832 ;
  wire \location_Madd__add0000_Result<15>2_1833 ;
  wire \location_Madd__add0000_Result<15>3_1834 ;
  wire \location_Madd__add0000_Result<1>1_1836 ;
  wire \location_Madd__add0000_Result<1>2_1837 ;
  wire \location_Madd__add0000_Result<1>3_1838 ;
  wire \location_Madd__add0000_Result<2>1 ;
  wire \location_Madd__add0000_Result<2>11_1841 ;
  wire \location_Madd__add0000_Result<2>111_1842 ;
  wire \location_Madd__add0000_Result<2>12_1843 ;
  wire \location_Madd__add0000_Result<2>13_1844 ;
  wire \location_Madd__add0000_Result<2>14_1845 ;
  wire \location_Madd__add0000_Result<2>2_1846 ;
  wire \location_Madd__add0000_Result<2>3_1847 ;
  wire \location_Madd__add0000_Result<3>1 ;
  wire \location_Madd__add0000_Result<3>11_1850 ;
  wire \location_Madd__add0000_Result<3>12_1851 ;
  wire \location_Madd__add0000_Result<3>13_1852 ;
  wire \location_Madd__add0000_Result<3>14_1853 ;
  wire \location_Madd__add0000_Result<3>2_1854 ;
  wire \location_Madd__add0000_Result<3>3_1855 ;
  wire \location_Madd__add0000_Result<4>1_1857 ;
  wire \location_Madd__add0000_Result<4>2_1858 ;
  wire \location_Madd__add0000_Result<4>3_1859 ;
  wire \location_Madd__add0000_Result<5>1 ;
  wire \location_Madd__add0000_Result<5>11_1862 ;
  wire \location_Madd__add0000_Result<5>111_1863 ;
  wire \location_Madd__add0000_Result<5>12_1864 ;
  wire \location_Madd__add0000_Result<5>13_1865 ;
  wire \location_Madd__add0000_Result<5>14_1866 ;
  wire \location_Madd__add0000_Result<5>2_1867 ;
  wire \location_Madd__add0000_Result<5>3_1868 ;
  wire \location_Madd__add0000_Result<6>1 ;
  wire \location_Madd__add0000_Result<6>11_1871 ;
  wire \location_Madd__add0000_Result<6>12_1872 ;
  wire \location_Madd__add0000_Result<6>13_1873 ;
  wire \location_Madd__add0000_Result<6>14_1874 ;
  wire \location_Madd__add0000_Result<6>2_1875 ;
  wire \location_Madd__add0000_Result<6>3_1876 ;
  wire \location_Madd__add0000_Result<7>1_1878 ;
  wire \location_Madd__add0000_Result<7>2_1879 ;
  wire \location_Madd__add0000_Result<7>3_1880 ;
  wire \location_Madd__add0000_Result<8>1 ;
  wire \location_Madd__add0000_Result<8>11_1883 ;
  wire \location_Madd__add0000_Result<8>111_1884 ;
  wire \location_Madd__add0000_Result<8>12_1885 ;
  wire \location_Madd__add0000_Result<8>13_1886 ;
  wire \location_Madd__add0000_Result<8>14_1887 ;
  wire \location_Madd__add0000_Result<8>2_1888 ;
  wire \location_Madd__add0000_Result<8>3_1889 ;
  wire \location_Madd__add0000_Result<9>1 ;
  wire \location_Madd__add0000_Result<9>11_1892 ;
  wire \location_Madd__add0000_Result<9>12_1893 ;
  wire \location_Madd__add0000_Result<9>13_1894 ;
  wire \location_Madd__add0000_Result<9>14_1895 ;
  wire \location_Madd__add0000_Result<9>2_1896 ;
  wire \location_Madd__add0000_Result<9>3_1897 ;
  wire location_or0001;
  wire [15 : 0] NlwRenamedSig_OI_count;
  wire [15 : 1] location_Madd__add0000_Result;
  wire [15 : 1] location__add0000;
  assign
    count[15] = NlwRenamedSig_OI_count[15],
    count[14] = NlwRenamedSig_OI_count[14],
    count[13] = NlwRenamedSig_OI_count[13],
    count[12] = NlwRenamedSig_OI_count[12],
    count[11] = NlwRenamedSig_OI_count[11],
    count[10] = NlwRenamedSig_OI_count[10],
    count[9] = NlwRenamedSig_OI_count[9],
    count[8] = NlwRenamedSig_OI_count[8],
    count[7] = NlwRenamedSig_OI_count[7],
    count[6] = NlwRenamedSig_OI_count[6],
    count[5] = NlwRenamedSig_OI_count[5],
    count[4] = NlwRenamedSig_OI_count[4],
    count[3] = NlwRenamedSig_OI_count[3],
    count[2] = NlwRenamedSig_OI_count[2],
    count[1] = NlwRenamedSig_OI_count[1],
    count[0] = NlwRenamedSig_OI_count[0];
  GND   XST_GND (
    .G(N0)
  );
  FDCE   location_15 (
    .CE(location_0__or0000),
    .CLR(N0),
    .C(Sclk),
    .D(location_15__and0000),
    .Q(NlwRenamedSig_OI_count[15])
  );
  FDCE   location_14 (
    .CE(location_0__or0000),
    .CLR(N0),
    .C(Sclk),
    .D(location_14__and0000),
    .Q(NlwRenamedSig_OI_count[14])
  );
  FDCE   location_13 (
    .CE(location_0__or0000),
    .CLR(N0),
    .C(Sclk),
    .D(location_13__and0000),
    .Q(NlwRenamedSig_OI_count[13])
  );
  FDCE   location_12 (
    .CE(location_0__or0000),
    .CLR(N0),
    .C(Sclk),
    .D(location_12__and0000),
    .Q(NlwRenamedSig_OI_count[12])
  );
  FDCE   location_11 (
    .CE(location_0__or0000),
    .CLR(N0),
    .C(Sclk),
    .D(location_11__and0000),
    .Q(NlwRenamedSig_OI_count[11])
  );
  FDCE   location_10 (
    .CE(location_0__or0000),
    .CLR(N0),
    .C(Sclk),
    .D(location_10__and0000),
    .Q(NlwRenamedSig_OI_count[10])
  );
  FDCE   location_9 (
    .CE(location_0__or0000),
    .CLR(N0),
    .C(Sclk),
    .D(location_9__and0000),
    .Q(NlwRenamedSig_OI_count[9])
  );
  FDCE   location_8 (
    .CE(location_0__or0000),
    .CLR(N0),
    .C(Sclk),
    .D(location_8__and0000),
    .Q(NlwRenamedSig_OI_count[8])
  );
  FDCE   location_7 (
    .CE(location_0__or0000),
    .CLR(N0),
    .C(Sclk),
    .D(location_7__and0000),
    .Q(NlwRenamedSig_OI_count[7])
  );
  FDCE   location_6 (
    .CE(location_0__or0000),
    .CLR(N0),
    .C(Sclk),
    .D(location_6__and0000),
    .Q(NlwRenamedSig_OI_count[6])
  );
  FDCE   location_5 (
    .CE(location_0__or0000),
    .CLR(N0),
    .C(Sclk),
    .D(location_5__and0000),
    .Q(NlwRenamedSig_OI_count[5])
  );
  FDCE   location_4 (
    .CE(location_0__or0000),
    .CLR(N0),
    .C(Sclk),
    .D(location_4__and0000),
    .Q(NlwRenamedSig_OI_count[4])
  );
  FDCE   location_3 (
    .CE(location_0__or0000),
    .CLR(N0),
    .C(Sclk),
    .D(location_3__and0000),
    .Q(NlwRenamedSig_OI_count[3])
  );
  FDCE   location_2 (
    .CE(location_0__or0000),
    .CLR(N0),
    .C(Sclk),
    .D(location_2__and0000),
    .Q(NlwRenamedSig_OI_count[2])
  );
  FDCE   location_1 (
    .CE(location_0__or0000),
    .CLR(N0),
    .C(Sclk),
    .D(location_1__and0000),
    .Q(NlwRenamedSig_OI_count[1])
  );
  FDCE   location_0 (
    .CE(location_0__or0000),
    .CLR(N0),
    .C(Sclk),
    .D(location_0__and0000),
    .Q(NlwRenamedSig_OI_count[0])
  );
  INV   location_15__and00001 (
    .I(Reset),
    .O(location_15__and00001_1758)
  );
  AND2   location_15__and00002 (
    .I0(location__add0000[15]),
    .I1(location_15__and00001_1758),
    .O(location_15__and0000)
  );
  INV   location_14__and00001 (
    .I(Reset),
    .O(location_14__and00001_1756)
  );
  AND2   location_14__and00002 (
    .I0(location__add0000[14]),
    .I1(location_14__and00001_1756),
    .O(location_14__and0000)
  );
  INV   location_13__and00001 (
    .I(Reset),
    .O(location_13__and00001_1754)
  );
  AND2   location_13__and00002 (
    .I0(location__add0000[13]),
    .I1(location_13__and00001_1754),
    .O(location_13__and0000)
  );
  INV   location_12__and00001 (
    .I(Reset),
    .O(location_12__and00001_1752)
  );
  AND2   location_12__and00002 (
    .I0(location__add0000[12]),
    .I1(location_12__and00001_1752),
    .O(location_12__and0000)
  );
  INV   location_11__and00001 (
    .I(Reset),
    .O(location_11__and00001_1750)
  );
  AND2   location_11__and00002 (
    .I0(location__add0000[11]),
    .I1(location_11__and00001_1750),
    .O(location_11__and0000)
  );
  INV   location_10__and00001 (
    .I(Reset),
    .O(location_10__and00001_1748)
  );
  AND2   location_10__and00002 (
    .I0(location__add0000[10]),
    .I1(location_10__and00001_1748),
    .O(location_10__and0000)
  );
  INV   location_9__and00001 (
    .I(Reset),
    .O(location_9__and00001_1776)
  );
  AND2   location_9__and00002 (
    .I0(location__add0000[9]),
    .I1(location_9__and00001_1776),
    .O(location_9__and0000)
  );
  INV   location_8__and00001 (
    .I(Reset),
    .O(location_8__and00001_1774)
  );
  AND2   location_8__and00002 (
    .I0(location__add0000[8]),
    .I1(location_8__and00001_1774),
    .O(location_8__and0000)
  );
  INV   location_7__and00001 (
    .I(Reset),
    .O(location_7__and00001_1772)
  );
  AND2   location_7__and00002 (
    .I0(location__add0000[7]),
    .I1(location_7__and00001_1772),
    .O(location_7__and0000)
  );
  INV   location_6__and00001 (
    .I(Reset),
    .O(location_6__and00001_1770)
  );
  AND2   location_6__and00002 (
    .I0(location__add0000[6]),
    .I1(location_6__and00001_1770),
    .O(location_6__and0000)
  );
  INV   location_5__and00001 (
    .I(Reset),
    .O(location_5__and00001_1768)
  );
  AND2   location_5__and00002 (
    .I0(location__add0000[5]),
    .I1(location_5__and00001_1768),
    .O(location_5__and0000)
  );
  INV   location_4__and00001 (
    .I(Reset),
    .O(location_4__and00001_1766)
  );
  AND2   location_4__and00002 (
    .I0(location__add0000[4]),
    .I1(location_4__and00001_1766),
    .O(location_4__and0000)
  );
  INV   location_3__and00001 (
    .I(Reset),
    .O(location_3__and00001_1764)
  );
  AND2   location_3__and00002 (
    .I0(location__add0000[3]),
    .I1(location_3__and00001_1764),
    .O(location_3__and0000)
  );
  INV   location_2__and00001 (
    .I(Reset),
    .O(location_2__and00001_1762)
  );
  AND2   location_2__and00002 (
    .I0(location__add0000[2]),
    .I1(location_2__and00001_1762),
    .O(location_2__and0000)
  );
  INV   location_1__and00001 (
    .I(Reset),
    .O(location_1__and00001_1760)
  );
  AND2   location_1__and00002 (
    .I0(location__add0000[1]),
    .I1(location_1__and00001_1760),
    .O(location_1__and0000)
  );
  OR2   location_0__or00001 (
    .I0(ce),
    .I1(Reset),
    .O(location_0__or0000)
  );
  INV   location_0__and00001 (
    .I(Reset),
    .O(location_0__and00001_1744)
  );
  INV   location_0__and00002 (
    .I(NlwRenamedSig_OI_count[0]),
    .O(location_0__and00002_1745)
  );
  AND2   location_0__and00003 (
    .I0(location_0__and00001_1744),
    .I1(location_0__and00002_1745),
    .O(location_0__and0000)
  );
  XOR2   location_or00011 (
    .I0(sense),
    .I1(updown),
    .O(location_or0001)
  );
  AND2   \location_Madd__add0000_Result<3>2  (
    .I0(NlwRenamedSig_OI_count[3]),
    .I1(N01),
    .O(location_Madd__add0000_Result[3])
  );
  INV   \location_Madd__add0000_Result<3>3  (
    .I(NlwRenamedSig_OI_count[3]),
    .O(\location_Madd__add0000_Result<3>1 )
  );
  INV   \location_Madd__add0000_Result<3>4  (
    .I(N01),
    .O(\location_Madd__add0000_Result<3>2_1854 )
  );
  AND2   \location_Madd__add0000_Result<3>5  (
    .I0(\location_Madd__add0000_Result<3>1 ),
    .I1(\location_Madd__add0000_Result<3>2_1854 ),
    .O(\location_Madd__add0000_Result<3>3_1855 )
  );
  OR2   \location_Madd__add0000_Result<3>6  (
    .I0(location_Madd__add0000_Result[3]),
    .I1(\location_Madd__add0000_Result<3>3_1855 ),
    .O(location__add0000[3])
  );
  AND2   \location_Madd__add0000_Result<6>2  (
    .I0(NlwRenamedSig_OI_count[6]),
    .I1(N11),
    .O(location_Madd__add0000_Result[6])
  );
  INV   \location_Madd__add0000_Result<6>3  (
    .I(NlwRenamedSig_OI_count[6]),
    .O(\location_Madd__add0000_Result<6>1 )
  );
  INV   \location_Madd__add0000_Result<6>4  (
    .I(N11),
    .O(\location_Madd__add0000_Result<6>2_1875 )
  );
  AND2   \location_Madd__add0000_Result<6>5  (
    .I0(\location_Madd__add0000_Result<6>1 ),
    .I1(\location_Madd__add0000_Result<6>2_1875 ),
    .O(\location_Madd__add0000_Result<6>3_1876 )
  );
  OR2   \location_Madd__add0000_Result<6>6  (
    .I0(location_Madd__add0000_Result[6]),
    .I1(\location_Madd__add0000_Result<6>3_1876 ),
    .O(location__add0000[6])
  );
  AND2   \location_Madd__add0000_Result<9>2  (
    .I0(NlwRenamedSig_OI_count[9]),
    .I1(N2),
    .O(location_Madd__add0000_Result[9])
  );
  INV   \location_Madd__add0000_Result<9>3  (
    .I(NlwRenamedSig_OI_count[9]),
    .O(\location_Madd__add0000_Result<9>1 )
  );
  INV   \location_Madd__add0000_Result<9>4  (
    .I(N2),
    .O(\location_Madd__add0000_Result<9>2_1896 )
  );
  AND2   \location_Madd__add0000_Result<9>5  (
    .I0(\location_Madd__add0000_Result<9>1 ),
    .I1(\location_Madd__add0000_Result<9>2_1896 ),
    .O(\location_Madd__add0000_Result<9>3_1897 )
  );
  OR2   \location_Madd__add0000_Result<9>6  (
    .I0(location_Madd__add0000_Result[9]),
    .I1(\location_Madd__add0000_Result<9>3_1897 ),
    .O(location__add0000[9])
  );
  AND2   \location_Madd__add0000_Result<12>2  (
    .I0(NlwRenamedSig_OI_count[12]),
    .I1(N3),
    .O(location_Madd__add0000_Result[12])
  );
  INV   \location_Madd__add0000_Result<12>3  (
    .I(NlwRenamedSig_OI_count[12]),
    .O(\location_Madd__add0000_Result<12>1 )
  );
  INV   \location_Madd__add0000_Result<12>4  (
    .I(N3),
    .O(\location_Madd__add0000_Result<12>2_1812 )
  );
  AND2   \location_Madd__add0000_Result<12>5  (
    .I0(\location_Madd__add0000_Result<12>1 ),
    .I1(\location_Madd__add0000_Result<12>2_1812 ),
    .O(\location_Madd__add0000_Result<12>3_1813 )
  );
  OR2   \location_Madd__add0000_Result<12>6  (
    .I0(location_Madd__add0000_Result[12]),
    .I1(\location_Madd__add0000_Result<12>3_1813 ),
    .O(location__add0000[12])
  );
  AND2   \location_Madd__add0000_Result<15>2  (
    .I0(NlwRenamedSig_OI_count[15]),
    .I1(N4),
    .O(location_Madd__add0000_Result[15])
  );
  INV   \location_Madd__add0000_Result<15>3  (
    .I(NlwRenamedSig_OI_count[15]),
    .O(\location_Madd__add0000_Result<15>1 )
  );
  INV   \location_Madd__add0000_Result<15>4  (
    .I(N4),
    .O(\location_Madd__add0000_Result<15>2_1833 )
  );
  AND2   \location_Madd__add0000_Result<15>5  (
    .I0(\location_Madd__add0000_Result<15>1 ),
    .I1(\location_Madd__add0000_Result<15>2_1833 ),
    .O(\location_Madd__add0000_Result<15>3_1834 )
  );
  OR2   \location_Madd__add0000_Result<15>6  (
    .I0(location_Madd__add0000_Result[15]),
    .I1(\location_Madd__add0000_Result<15>3_1834 ),
    .O(location__add0000[15])
  );
  AND2   \location_Madd__add0000_Result<2>2  (
    .I0(NlwRenamedSig_OI_count[2]),
    .I1(N5),
    .O(location_Madd__add0000_Result[2])
  );
  INV   \location_Madd__add0000_Result<2>3  (
    .I(NlwRenamedSig_OI_count[2]),
    .O(\location_Madd__add0000_Result<2>1 )
  );
  INV   \location_Madd__add0000_Result<2>4  (
    .I(N5),
    .O(\location_Madd__add0000_Result<2>2_1846 )
  );
  AND2   \location_Madd__add0000_Result<2>5  (
    .I0(\location_Madd__add0000_Result<2>1 ),
    .I1(\location_Madd__add0000_Result<2>2_1846 ),
    .O(\location_Madd__add0000_Result<2>3_1847 )
  );
  OR2   \location_Madd__add0000_Result<2>6  (
    .I0(location_Madd__add0000_Result[2]),
    .I1(\location_Madd__add0000_Result<2>3_1847 ),
    .O(location__add0000[2])
  );
  AND2   \location_Madd__add0000_Result<5>2  (
    .I0(NlwRenamedSig_OI_count[5]),
    .I1(N6),
    .O(location_Madd__add0000_Result[5])
  );
  INV   \location_Madd__add0000_Result<5>3  (
    .I(NlwRenamedSig_OI_count[5]),
    .O(\location_Madd__add0000_Result<5>1 )
  );
  INV   \location_Madd__add0000_Result<5>4  (
    .I(N6),
    .O(\location_Madd__add0000_Result<5>2_1867 )
  );
  AND2   \location_Madd__add0000_Result<5>5  (
    .I0(\location_Madd__add0000_Result<5>1 ),
    .I1(\location_Madd__add0000_Result<5>2_1867 ),
    .O(\location_Madd__add0000_Result<5>3_1868 )
  );
  OR2   \location_Madd__add0000_Result<5>6  (
    .I0(location_Madd__add0000_Result[5]),
    .I1(\location_Madd__add0000_Result<5>3_1868 ),
    .O(location__add0000[5])
  );
  AND2   \location_Madd__add0000_Result<8>2  (
    .I0(NlwRenamedSig_OI_count[8]),
    .I1(N7),
    .O(location_Madd__add0000_Result[8])
  );
  INV   \location_Madd__add0000_Result<8>3  (
    .I(NlwRenamedSig_OI_count[8]),
    .O(\location_Madd__add0000_Result<8>1 )
  );
  INV   \location_Madd__add0000_Result<8>4  (
    .I(N7),
    .O(\location_Madd__add0000_Result<8>2_1888 )
  );
  AND2   \location_Madd__add0000_Result<8>5  (
    .I0(\location_Madd__add0000_Result<8>1 ),
    .I1(\location_Madd__add0000_Result<8>2_1888 ),
    .O(\location_Madd__add0000_Result<8>3_1889 )
  );
  OR2   \location_Madd__add0000_Result<8>6  (
    .I0(location_Madd__add0000_Result[8]),
    .I1(\location_Madd__add0000_Result<8>3_1889 ),
    .O(location__add0000[8])
  );
  AND2   \location_Madd__add0000_Result<11>2  (
    .I0(NlwRenamedSig_OI_count[11]),
    .I1(N8),
    .O(location_Madd__add0000_Result[11])
  );
  INV   \location_Madd__add0000_Result<11>3  (
    .I(NlwRenamedSig_OI_count[11]),
    .O(\location_Madd__add0000_Result<11>1 )
  );
  INV   \location_Madd__add0000_Result<11>4  (
    .I(N8),
    .O(\location_Madd__add0000_Result<11>2_1804 )
  );
  AND2   \location_Madd__add0000_Result<11>5  (
    .I0(\location_Madd__add0000_Result<11>1 ),
    .I1(\location_Madd__add0000_Result<11>2_1804 ),
    .O(\location_Madd__add0000_Result<11>3_1805 )
  );
  OR2   \location_Madd__add0000_Result<11>6  (
    .I0(location_Madd__add0000_Result[11]),
    .I1(\location_Madd__add0000_Result<11>3_1805 ),
    .O(location__add0000[11])
  );
  AND2   \location_Madd__add0000_Result<14>2  (
    .I0(NlwRenamedSig_OI_count[14]),
    .I1(N9),
    .O(location_Madd__add0000_Result[14])
  );
  INV   \location_Madd__add0000_Result<14>3  (
    .I(NlwRenamedSig_OI_count[14]),
    .O(\location_Madd__add0000_Result<14>1 )
  );
  INV   \location_Madd__add0000_Result<14>4  (
    .I(N9),
    .O(\location_Madd__add0000_Result<14>2_1825 )
  );
  AND2   \location_Madd__add0000_Result<14>5  (
    .I0(\location_Madd__add0000_Result<14>1 ),
    .I1(\location_Madd__add0000_Result<14>2_1825 ),
    .O(\location_Madd__add0000_Result<14>3_1826 )
  );
  OR2   \location_Madd__add0000_Result<14>6  (
    .I0(location_Madd__add0000_Result[14]),
    .I1(\location_Madd__add0000_Result<14>3_1826 ),
    .O(location__add0000[14])
  );
  XOR2   \location_Madd__add0000_Result<13>11  (
    .I0(location_or0001),
    .I1(\location_Madd__add0000_CARRY_IN[13] ),
    .O(N10)
  );
  AND2   \location_Madd__add0000_Result<13>1  (
    .I0(NlwRenamedSig_OI_count[13]),
    .I1(N10),
    .O(location_Madd__add0000_Result[13])
  );
  INV   \location_Madd__add0000_Result<13>2  (
    .I(NlwRenamedSig_OI_count[13]),
    .O(\location_Madd__add0000_Result<13>1_1815 )
  );
  INV   \location_Madd__add0000_Result<13>3  (
    .I(N10),
    .O(\location_Madd__add0000_Result<13>2_1816 )
  );
  AND2   \location_Madd__add0000_Result<13>4  (
    .I0(\location_Madd__add0000_Result<13>1_1815 ),
    .I1(\location_Madd__add0000_Result<13>2_1816 ),
    .O(\location_Madd__add0000_Result<13>3_1817 )
  );
  OR2   \location_Madd__add0000_Result<13>5  (
    .I0(location_Madd__add0000_Result[13]),
    .I1(\location_Madd__add0000_Result<13>3_1817 ),
    .O(location__add0000[13])
  );
  XOR2   \location_Madd__add0000_Result<10>11  (
    .I0(location_or0001),
    .I1(\location_Madd__add0000_CARRY_IN[10] ),
    .O(N111)
  );
  AND2   \location_Madd__add0000_Result<10>1  (
    .I0(NlwRenamedSig_OI_count[10]),
    .I1(N111),
    .O(location_Madd__add0000_Result[10])
  );
  INV   \location_Madd__add0000_Result<10>2  (
    .I(NlwRenamedSig_OI_count[10]),
    .O(\location_Madd__add0000_Result<10>1_1794 )
  );
  INV   \location_Madd__add0000_Result<10>3  (
    .I(N111),
    .O(\location_Madd__add0000_Result<10>2_1795 )
  );
  AND2   \location_Madd__add0000_Result<10>4  (
    .I0(\location_Madd__add0000_Result<10>1_1794 ),
    .I1(\location_Madd__add0000_Result<10>2_1795 ),
    .O(\location_Madd__add0000_Result<10>3_1796 )
  );
  OR2   \location_Madd__add0000_Result<10>5  (
    .I0(location_Madd__add0000_Result[10]),
    .I1(\location_Madd__add0000_Result<10>3_1796 ),
    .O(location__add0000[10])
  );
  XOR2   \location_Madd__add0000_Result<7>11  (
    .I0(location_or0001),
    .I1(\location_Madd__add0000_CARRY_IN[7] ),
    .O(N12)
  );
  AND2   \location_Madd__add0000_Result<7>1  (
    .I0(NlwRenamedSig_OI_count[7]),
    .I1(N12),
    .O(location_Madd__add0000_Result[7])
  );
  INV   \location_Madd__add0000_Result<7>2  (
    .I(NlwRenamedSig_OI_count[7]),
    .O(\location_Madd__add0000_Result<7>1_1878 )
  );
  INV   \location_Madd__add0000_Result<7>3  (
    .I(N12),
    .O(\location_Madd__add0000_Result<7>2_1879 )
  );
  AND2   \location_Madd__add0000_Result<7>4  (
    .I0(\location_Madd__add0000_Result<7>1_1878 ),
    .I1(\location_Madd__add0000_Result<7>2_1879 ),
    .O(\location_Madd__add0000_Result<7>3_1880 )
  );
  OR2   \location_Madd__add0000_Result<7>5  (
    .I0(location_Madd__add0000_Result[7]),
    .I1(\location_Madd__add0000_Result<7>3_1880 ),
    .O(location__add0000[7])
  );
  XOR2   \location_Madd__add0000_Result<4>11  (
    .I0(location_or0001),
    .I1(\location_Madd__add0000_CARRY_IN[4] ),
    .O(N13)
  );
  AND2   \location_Madd__add0000_Result<4>1  (
    .I0(NlwRenamedSig_OI_count[4]),
    .I1(N13),
    .O(location_Madd__add0000_Result[4])
  );
  INV   \location_Madd__add0000_Result<4>2  (
    .I(NlwRenamedSig_OI_count[4]),
    .O(\location_Madd__add0000_Result<4>1_1857 )
  );
  INV   \location_Madd__add0000_Result<4>3  (
    .I(N13),
    .O(\location_Madd__add0000_Result<4>2_1858 )
  );
  AND2   \location_Madd__add0000_Result<4>4  (
    .I0(\location_Madd__add0000_Result<4>1_1857 ),
    .I1(\location_Madd__add0000_Result<4>2_1858 ),
    .O(\location_Madd__add0000_Result<4>3_1859 )
  );
  OR2   \location_Madd__add0000_Result<4>5  (
    .I0(location_Madd__add0000_Result[4]),
    .I1(\location_Madd__add0000_Result<4>3_1859 ),
    .O(location__add0000[4])
  );
  XOR2   \location_Madd__add0000_Result<1>11  (
    .I0(location_or0001),
    .I1(NlwRenamedSig_OI_count[1]),
    .O(N14)
  );
  AND2   \location_Madd__add0000_Result<1>1  (
    .I0(NlwRenamedSig_OI_count[0]),
    .I1(N14),
    .O(location_Madd__add0000_Result[1])
  );
  INV   \location_Madd__add0000_Result<1>2  (
    .I(NlwRenamedSig_OI_count[0]),
    .O(\location_Madd__add0000_Result<1>1_1836 )
  );
  INV   \location_Madd__add0000_Result<1>3  (
    .I(N14),
    .O(\location_Madd__add0000_Result<1>2_1837 )
  );
  AND2   \location_Madd__add0000_Result<1>4  (
    .I0(\location_Madd__add0000_Result<1>1_1836 ),
    .I1(\location_Madd__add0000_Result<1>2_1837 ),
    .O(\location_Madd__add0000_Result<1>3_1838 )
  );
  OR2   \location_Madd__add0000_Result<1>5  (
    .I0(location_Madd__add0000_Result[1]),
    .I1(\location_Madd__add0000_Result<1>3_1838 ),
    .O(location__add0000[1])
  );
  OR4   \location_Madd__add0000_CARRY_IN<4>11  (
    .I0(NlwRenamedSig_OI_count[0]),
    .I1(NlwRenamedSig_OI_count[1]),
    .I2(NlwRenamedSig_OI_count[2]),
    .I3(NlwRenamedSig_OI_count[3]),
    .O(N15)
  );
  AND2   \location_Madd__add0000_CARRY_IN<4>1  (
    .I0(SFDecomp_84),
    .I1(NlwRenamedSig_OI_count[3]),
    .O(\location_Madd__add0000_CARRY_IN<4>1_1786 )
  );
  INV   \location_Madd__add0000_CARRY_IN<4>2  (
    .I(location_or0001),
    .O(\location_Madd__add0000_CARRY_IN<4>2_1787 )
  );
  AND2   \location_Madd__add0000_CARRY_IN<4>3  (
    .I0(N15),
    .I1(\location_Madd__add0000_CARRY_IN<4>2_1787 ),
    .O(\location_Madd__add0000_CARRY_IN<4>3_1788 )
  );
  OR2   \location_Madd__add0000_CARRY_IN<4>4  (
    .I0(\location_Madd__add0000_CARRY_IN<4>1_1786 ),
    .I1(\location_Madd__add0000_CARRY_IN<4>3_1788 ),
    .O(\location_Madd__add0000_CARRY_IN[4] )
  );
  OR4   \location_Madd__add0000_CARRY_IN<7>11  (
    .I0(NlwRenamedSig_OI_count[4]),
    .I1(NlwRenamedSig_OI_count[5]),
    .I2(NlwRenamedSig_OI_count[6]),
    .I3(\location_Madd__add0000_CARRY_IN[4] ),
    .O(N16)
  );
  AND2   \location_Madd__add0000_CARRY_IN<7>1  (
    .I0(SFDecomp_85),
    .I1(\location_Madd__add0000_CARRY_IN[4] ),
    .O(\location_Madd__add0000_CARRY_IN<7>1_1790 )
  );
  INV   \location_Madd__add0000_CARRY_IN<7>2  (
    .I(location_or0001),
    .O(\location_Madd__add0000_CARRY_IN<7>2_1791 )
  );
  AND2   \location_Madd__add0000_CARRY_IN<7>3  (
    .I0(N16),
    .I1(\location_Madd__add0000_CARRY_IN<7>2_1791 ),
    .O(\location_Madd__add0000_CARRY_IN<7>3_1792 )
  );
  OR2   \location_Madd__add0000_CARRY_IN<7>4  (
    .I0(\location_Madd__add0000_CARRY_IN<7>1_1790 ),
    .I1(\location_Madd__add0000_CARRY_IN<7>3_1792 ),
    .O(\location_Madd__add0000_CARRY_IN[7] )
  );
  OR4   \location_Madd__add0000_CARRY_IN<10>11  (
    .I0(NlwRenamedSig_OI_count[7]),
    .I1(NlwRenamedSig_OI_count[8]),
    .I2(NlwRenamedSig_OI_count[9]),
    .I3(\location_Madd__add0000_CARRY_IN[7] ),
    .O(N17)
  );
  AND2   \location_Madd__add0000_CARRY_IN<10>1  (
    .I0(SFDecomp_86),
    .I1(\location_Madd__add0000_CARRY_IN[7] ),
    .O(\location_Madd__add0000_CARRY_IN<10>1_1778 )
  );
  INV   \location_Madd__add0000_CARRY_IN<10>2  (
    .I(location_or0001),
    .O(\location_Madd__add0000_CARRY_IN<10>2_1779 )
  );
  AND2   \location_Madd__add0000_CARRY_IN<10>3  (
    .I0(N17),
    .I1(\location_Madd__add0000_CARRY_IN<10>2_1779 ),
    .O(\location_Madd__add0000_CARRY_IN<10>3_1780 )
  );
  OR2   \location_Madd__add0000_CARRY_IN<10>4  (
    .I0(\location_Madd__add0000_CARRY_IN<10>1_1778 ),
    .I1(\location_Madd__add0000_CARRY_IN<10>3_1780 ),
    .O(\location_Madd__add0000_CARRY_IN[10] )
  );
  OR4   \location_Madd__add0000_CARRY_IN<13>11  (
    .I0(NlwRenamedSig_OI_count[10]),
    .I1(NlwRenamedSig_OI_count[11]),
    .I2(NlwRenamedSig_OI_count[12]),
    .I3(\location_Madd__add0000_CARRY_IN[10] ),
    .O(N18)
  );
  AND2   \location_Madd__add0000_CARRY_IN<13>1  (
    .I0(SFDecomp_87),
    .I1(\location_Madd__add0000_CARRY_IN[10] ),
    .O(\location_Madd__add0000_CARRY_IN<13>1_1782 )
  );
  INV   \location_Madd__add0000_CARRY_IN<13>2  (
    .I(location_or0001),
    .O(\location_Madd__add0000_CARRY_IN<13>2_1783 )
  );
  AND2   \location_Madd__add0000_CARRY_IN<13>3  (
    .I0(N18),
    .I1(\location_Madd__add0000_CARRY_IN<13>2_1783 ),
    .O(\location_Madd__add0000_CARRY_IN<13>3_1784 )
  );
  OR2   \location_Madd__add0000_CARRY_IN<13>4  (
    .I0(\location_Madd__add0000_CARRY_IN<13>1_1782 ),
    .I1(\location_Madd__add0000_CARRY_IN<13>3_1784 ),
    .O(\location_Madd__add0000_CARRY_IN[13] )
  );
  INV   \location_Madd__add0000_Result<12>11  (
    .I(location_or0001),
    .O(\location_Madd__add0000_Result<12>11_1808 )
  );
  INV   \location_Madd__add0000_Result<12>12  (
    .I(NlwRenamedSig_OI_count[11]),
    .O(\location_Madd__add0000_Result<12>12_1809 )
  );
  AND2   \location_Madd__add0000_Result<12>13  (
    .I0(NlwRenamedSig_OI_count[11]),
    .I1(\location_Madd__add0000_Result<12>11_1808 ),
    .O(\location_Madd__add0000_Result<12>13_1810 )
  );
  AND2   \location_Madd__add0000_Result<12>14  (
    .I0(location_or0001),
    .I1(\location_Madd__add0000_Result<12>12_1809 ),
    .O(\location_Madd__add0000_Result<12>14_1811 )
  );
  OR3   \location_Madd__add0000_Result<12>15  (
    .I0(\location_Madd__add0000_Result<12>13_1810 ),
    .I1(N8),
    .I2(\location_Madd__add0000_Result<12>14_1811 ),
    .O(N3)
  );
  INV   \location_Madd__add0000_Result<15>11  (
    .I(location_or0001),
    .O(\location_Madd__add0000_Result<15>11_1829 )
  );
  INV   \location_Madd__add0000_Result<15>12  (
    .I(NlwRenamedSig_OI_count[14]),
    .O(\location_Madd__add0000_Result<15>12_1830 )
  );
  AND2   \location_Madd__add0000_Result<15>13  (
    .I0(NlwRenamedSig_OI_count[14]),
    .I1(\location_Madd__add0000_Result<15>11_1829 ),
    .O(\location_Madd__add0000_Result<15>13_1831 )
  );
  AND2   \location_Madd__add0000_Result<15>14  (
    .I0(location_or0001),
    .I1(\location_Madd__add0000_Result<15>12_1830 ),
    .O(\location_Madd__add0000_Result<15>14_1832 )
  );
  OR3   \location_Madd__add0000_Result<15>15  (
    .I0(\location_Madd__add0000_Result<15>13_1831 ),
    .I1(N9),
    .I2(\location_Madd__add0000_Result<15>14_1832 ),
    .O(N4)
  );
  INV   \location_Madd__add0000_Result<3>11  (
    .I(location_or0001),
    .O(\location_Madd__add0000_Result<3>11_1850 )
  );
  INV   \location_Madd__add0000_Result<3>12  (
    .I(NlwRenamedSig_OI_count[2]),
    .O(\location_Madd__add0000_Result<3>12_1851 )
  );
  AND2   \location_Madd__add0000_Result<3>13  (
    .I0(NlwRenamedSig_OI_count[2]),
    .I1(\location_Madd__add0000_Result<3>11_1850 ),
    .O(\location_Madd__add0000_Result<3>13_1852 )
  );
  AND2   \location_Madd__add0000_Result<3>14  (
    .I0(location_or0001),
    .I1(\location_Madd__add0000_Result<3>12_1851 ),
    .O(\location_Madd__add0000_Result<3>14_1853 )
  );
  OR3   \location_Madd__add0000_Result<3>15  (
    .I0(\location_Madd__add0000_Result<3>13_1852 ),
    .I1(N5),
    .I2(\location_Madd__add0000_Result<3>14_1853 ),
    .O(N01)
  );
  INV   \location_Madd__add0000_Result<6>11  (
    .I(location_or0001),
    .O(\location_Madd__add0000_Result<6>11_1871 )
  );
  INV   \location_Madd__add0000_Result<6>12  (
    .I(NlwRenamedSig_OI_count[5]),
    .O(\location_Madd__add0000_Result<6>12_1872 )
  );
  AND2   \location_Madd__add0000_Result<6>13  (
    .I0(NlwRenamedSig_OI_count[5]),
    .I1(\location_Madd__add0000_Result<6>11_1871 ),
    .O(\location_Madd__add0000_Result<6>13_1873 )
  );
  AND2   \location_Madd__add0000_Result<6>14  (
    .I0(location_or0001),
    .I1(\location_Madd__add0000_Result<6>12_1872 ),
    .O(\location_Madd__add0000_Result<6>14_1874 )
  );
  OR3   \location_Madd__add0000_Result<6>15  (
    .I0(\location_Madd__add0000_Result<6>13_1873 ),
    .I1(N6),
    .I2(\location_Madd__add0000_Result<6>14_1874 ),
    .O(N11)
  );
  INV   \location_Madd__add0000_Result<9>11  (
    .I(location_or0001),
    .O(\location_Madd__add0000_Result<9>11_1892 )
  );
  INV   \location_Madd__add0000_Result<9>12  (
    .I(NlwRenamedSig_OI_count[8]),
    .O(\location_Madd__add0000_Result<9>12_1893 )
  );
  AND2   \location_Madd__add0000_Result<9>13  (
    .I0(NlwRenamedSig_OI_count[8]),
    .I1(\location_Madd__add0000_Result<9>11_1892 ),
    .O(\location_Madd__add0000_Result<9>13_1894 )
  );
  AND2   \location_Madd__add0000_Result<9>14  (
    .I0(location_or0001),
    .I1(\location_Madd__add0000_Result<9>12_1893 ),
    .O(\location_Madd__add0000_Result<9>14_1895 )
  );
  OR3   \location_Madd__add0000_Result<9>15  (
    .I0(\location_Madd__add0000_Result<9>13_1894 ),
    .I1(N7),
    .I2(\location_Madd__add0000_Result<9>14_1895 ),
    .O(N2)
  );
  INV   \location_Madd__add0000_Result<11>111  (
    .I(NlwRenamedSig_OI_count[10]),
    .O(\location_Madd__add0000_Result<11>11_1799 )
  );
  INV   \location_Madd__add0000_Result<11>112  (
    .I(\location_Madd__add0000_CARRY_IN[10] ),
    .O(\location_Madd__add0000_Result<11>111_1800 )
  );
  OR2   \location_Madd__add0000_Result<11>113  (
    .I0(\location_Madd__add0000_Result<11>11_1799 ),
    .I1(\location_Madd__add0000_Result<11>111_1800 ),
    .O(N19)
  );
  INV   \location_Madd__add0000_Result<14>111  (
    .I(NlwRenamedSig_OI_count[13]),
    .O(\location_Madd__add0000_Result<14>11_1820 )
  );
  INV   \location_Madd__add0000_Result<14>112  (
    .I(\location_Madd__add0000_CARRY_IN[13] ),
    .O(\location_Madd__add0000_Result<14>111_1821 )
  );
  OR2   \location_Madd__add0000_Result<14>113  (
    .I0(\location_Madd__add0000_Result<14>11_1820 ),
    .I1(\location_Madd__add0000_Result<14>111_1821 ),
    .O(N20)
  );
  INV   \location_Madd__add0000_Result<2>111  (
    .I(NlwRenamedSig_OI_count[0]),
    .O(\location_Madd__add0000_Result<2>11_1841 )
  );
  INV   \location_Madd__add0000_Result<2>112  (
    .I(NlwRenamedSig_OI_count[1]),
    .O(\location_Madd__add0000_Result<2>111_1842 )
  );
  OR2   \location_Madd__add0000_Result<2>113  (
    .I0(\location_Madd__add0000_Result<2>11_1841 ),
    .I1(\location_Madd__add0000_Result<2>111_1842 ),
    .O(N21)
  );
  INV   \location_Madd__add0000_Result<5>111  (
    .I(NlwRenamedSig_OI_count[4]),
    .O(\location_Madd__add0000_Result<5>11_1862 )
  );
  INV   \location_Madd__add0000_Result<5>112  (
    .I(\location_Madd__add0000_CARRY_IN[4] ),
    .O(\location_Madd__add0000_Result<5>111_1863 )
  );
  OR2   \location_Madd__add0000_Result<5>113  (
    .I0(\location_Madd__add0000_Result<5>11_1862 ),
    .I1(\location_Madd__add0000_Result<5>111_1863 ),
    .O(N22)
  );
  INV   \location_Madd__add0000_Result<8>111  (
    .I(NlwRenamedSig_OI_count[7]),
    .O(\location_Madd__add0000_Result<8>11_1883 )
  );
  INV   \location_Madd__add0000_Result<8>112  (
    .I(\location_Madd__add0000_CARRY_IN[7] ),
    .O(\location_Madd__add0000_Result<8>111_1884 )
  );
  OR2   \location_Madd__add0000_Result<8>113  (
    .I0(\location_Madd__add0000_Result<8>11_1883 ),
    .I1(\location_Madd__add0000_Result<8>111_1884 ),
    .O(N23)
  );
  OR2   \location_Madd__add0000_Result<11>121  (
    .I0(NlwRenamedSig_OI_count[10]),
    .I1(\location_Madd__add0000_CARRY_IN[10] ),
    .O(N24)
  );
  AND2   \location_Madd__add0000_Result<11>11  (
    .I0(location_or0001),
    .I1(N19),
    .O(\location_Madd__add0000_Result<11>12_1801 )
  );
  INV   \location_Madd__add0000_Result<11>12  (
    .I(location_or0001),
    .O(\location_Madd__add0000_Result<11>13_1802 )
  );
  AND2   \location_Madd__add0000_Result<11>13  (
    .I0(N24),
    .I1(\location_Madd__add0000_Result<11>13_1802 ),
    .O(\location_Madd__add0000_Result<11>14_1803 )
  );
  OR2   \location_Madd__add0000_Result<11>14  (
    .I0(\location_Madd__add0000_Result<11>12_1801 ),
    .I1(\location_Madd__add0000_Result<11>14_1803 ),
    .O(N8)
  );
  OR2   \location_Madd__add0000_Result<14>121  (
    .I0(NlwRenamedSig_OI_count[13]),
    .I1(\location_Madd__add0000_CARRY_IN[13] ),
    .O(N25)
  );
  AND2   \location_Madd__add0000_Result<14>11  (
    .I0(location_or0001),
    .I1(N20),
    .O(\location_Madd__add0000_Result<14>12_1822 )
  );
  INV   \location_Madd__add0000_Result<14>12  (
    .I(location_or0001),
    .O(\location_Madd__add0000_Result<14>13_1823 )
  );
  AND2   \location_Madd__add0000_Result<14>13  (
    .I0(N25),
    .I1(\location_Madd__add0000_Result<14>13_1823 ),
    .O(\location_Madd__add0000_Result<14>14_1824 )
  );
  OR2   \location_Madd__add0000_Result<14>14  (
    .I0(\location_Madd__add0000_Result<14>12_1822 ),
    .I1(\location_Madd__add0000_Result<14>14_1824 ),
    .O(N9)
  );
  OR2   \location_Madd__add0000_Result<2>121  (
    .I0(NlwRenamedSig_OI_count[0]),
    .I1(NlwRenamedSig_OI_count[1]),
    .O(N26)
  );
  AND2   \location_Madd__add0000_Result<2>11  (
    .I0(location_or0001),
    .I1(N21),
    .O(\location_Madd__add0000_Result<2>12_1843 )
  );
  INV   \location_Madd__add0000_Result<2>12  (
    .I(location_or0001),
    .O(\location_Madd__add0000_Result<2>13_1844 )
  );
  AND2   \location_Madd__add0000_Result<2>13  (
    .I0(N26),
    .I1(\location_Madd__add0000_Result<2>13_1844 ),
    .O(\location_Madd__add0000_Result<2>14_1845 )
  );
  OR2   \location_Madd__add0000_Result<2>14  (
    .I0(\location_Madd__add0000_Result<2>12_1843 ),
    .I1(\location_Madd__add0000_Result<2>14_1845 ),
    .O(N5)
  );
  OR2   \location_Madd__add0000_Result<5>121  (
    .I0(NlwRenamedSig_OI_count[4]),
    .I1(\location_Madd__add0000_CARRY_IN[4] ),
    .O(N27)
  );
  AND2   \location_Madd__add0000_Result<5>11  (
    .I0(location_or0001),
    .I1(N22),
    .O(\location_Madd__add0000_Result<5>12_1864 )
  );
  INV   \location_Madd__add0000_Result<5>12  (
    .I(location_or0001),
    .O(\location_Madd__add0000_Result<5>13_1865 )
  );
  AND2   \location_Madd__add0000_Result<5>13  (
    .I0(N27),
    .I1(\location_Madd__add0000_Result<5>13_1865 ),
    .O(\location_Madd__add0000_Result<5>14_1866 )
  );
  OR2   \location_Madd__add0000_Result<5>14  (
    .I0(\location_Madd__add0000_Result<5>12_1864 ),
    .I1(\location_Madd__add0000_Result<5>14_1866 ),
    .O(N6)
  );
  OR2   \location_Madd__add0000_Result<8>121  (
    .I0(NlwRenamedSig_OI_count[7]),
    .I1(\location_Madd__add0000_CARRY_IN[7] ),
    .O(N28)
  );
  AND2   \location_Madd__add0000_Result<8>11  (
    .I0(location_or0001),
    .I1(N23),
    .O(\location_Madd__add0000_Result<8>12_1885 )
  );
  INV   \location_Madd__add0000_Result<8>12  (
    .I(location_or0001),
    .O(\location_Madd__add0000_Result<8>13_1886 )
  );
  AND2   \location_Madd__add0000_Result<8>13  (
    .I0(N28),
    .I1(\location_Madd__add0000_Result<8>13_1886 ),
    .O(\location_Madd__add0000_Result<8>14_1887 )
  );
  OR2   \location_Madd__add0000_Result<8>14  (
    .I0(\location_Madd__add0000_Result<8>12_1885 ),
    .I1(\location_Madd__add0000_Result<8>14_1887 ),
    .O(N7)
  );
  AND3   SFDecomp_841 (
    .I0(NlwRenamedSig_OI_count[0]),
    .I1(NlwRenamedSig_OI_count[1]),
    .I2(NlwRenamedSig_OI_count[2]),
    .O(SFDecomp_84)
  );
  AND3   SFDecomp_851 (
    .I0(NlwRenamedSig_OI_count[4]),
    .I1(NlwRenamedSig_OI_count[5]),
    .I2(NlwRenamedSig_OI_count[6]),
    .O(SFDecomp_85)
  );
  AND3   SFDecomp_861 (
    .I0(NlwRenamedSig_OI_count[7]),
    .I1(NlwRenamedSig_OI_count[8]),
    .I2(NlwRenamedSig_OI_count[9]),
    .O(SFDecomp_86)
  );
  AND3   SFDecomp_871 (
    .I0(NlwRenamedSig_OI_count[10]),
    .I1(NlwRenamedSig_OI_count[11]),
    .I2(NlwRenamedSig_OI_count[12]),
    .O(SFDecomp_87)
  );
endmodule

module Counter (
  sense, ce, Reset, updown, Zero, Sclk, count
);
  input sense;
  input ce;
  input Reset;
  input updown;
  input Zero;
  input Sclk;
  output [15 : 0] count;
  wire N0;
  wire N01;
  wire N10;
  wire N11;
  wire N111;
  wire N12;
  wire N13;
  wire N14;
  wire N15;
  wire N16;
  wire N17;
  wire N18;
  wire N19;
  wire N2;
  wire N20;
  wire N21;
  wire N22;
  wire N23;
  wire N24;
  wire N25;
  wire N26;
  wire N27;
  wire N28;
  wire N3;
  wire N4;
  wire N5;
  wire N6;
  wire N7;
  wire N8;
  wire N9;
  wire SFDecomp_84;
  wire SFDecomp_85;
  wire SFDecomp_86;
  wire SFDecomp_87;
  wire location_0__and0000;
  wire location_0__and00001_1518;
  wire location_0__and00002_1519;
  wire location_0__or0000;
  wire location_10__and0000;
  wire location_10__and00001_1522;
  wire location_11__and0000;
  wire location_11__and00001_1524;
  wire location_12__and0000;
  wire location_12__and00001_1526;
  wire location_13__and0000;
  wire location_13__and00001_1528;
  wire location_14__and0000;
  wire location_14__and00001_1530;
  wire location_15__and0000;
  wire location_15__and00001_1532;
  wire location_1__and0000;
  wire location_1__and00001_1534;
  wire location_2__and0000;
  wire location_2__and00001_1536;
  wire location_3__and0000;
  wire location_3__and00001_1538;
  wire location_4__and0000;
  wire location_4__and00001_1540;
  wire location_5__and0000;
  wire location_5__and00001_1542;
  wire location_6__and0000;
  wire location_6__and00001_1544;
  wire location_7__and0000;
  wire location_7__and00001_1546;
  wire location_8__and0000;
  wire location_8__and00001_1548;
  wire location_9__and0000;
  wire location_9__and00001_1550;
  wire \location_Madd__add0000_CARRY_IN[10] ;
  wire \location_Madd__add0000_CARRY_IN<10>1_1552 ;
  wire \location_Madd__add0000_CARRY_IN<10>2_1553 ;
  wire \location_Madd__add0000_CARRY_IN<10>3_1554 ;
  wire \location_Madd__add0000_CARRY_IN[13] ;
  wire \location_Madd__add0000_CARRY_IN<13>1_1556 ;
  wire \location_Madd__add0000_CARRY_IN<13>2_1557 ;
  wire \location_Madd__add0000_CARRY_IN<13>3_1558 ;
  wire \location_Madd__add0000_CARRY_IN[4] ;
  wire \location_Madd__add0000_CARRY_IN<4>1_1560 ;
  wire \location_Madd__add0000_CARRY_IN<4>2_1561 ;
  wire \location_Madd__add0000_CARRY_IN<4>3_1562 ;
  wire \location_Madd__add0000_CARRY_IN[7] ;
  wire \location_Madd__add0000_CARRY_IN<7>1_1564 ;
  wire \location_Madd__add0000_CARRY_IN<7>2_1565 ;
  wire \location_Madd__add0000_CARRY_IN<7>3_1566 ;
  wire \location_Madd__add0000_Result<10>1_1568 ;
  wire \location_Madd__add0000_Result<10>2_1569 ;
  wire \location_Madd__add0000_Result<10>3_1570 ;
  wire \location_Madd__add0000_Result<11>1 ;
  wire \location_Madd__add0000_Result<11>11_1573 ;
  wire \location_Madd__add0000_Result<11>111_1574 ;
  wire \location_Madd__add0000_Result<11>12_1575 ;
  wire \location_Madd__add0000_Result<11>13_1576 ;
  wire \location_Madd__add0000_Result<11>14_1577 ;
  wire \location_Madd__add0000_Result<11>2_1578 ;
  wire \location_Madd__add0000_Result<11>3_1579 ;
  wire \location_Madd__add0000_Result<12>1 ;
  wire \location_Madd__add0000_Result<12>11_1582 ;
  wire \location_Madd__add0000_Result<12>12_1583 ;
  wire \location_Madd__add0000_Result<12>13_1584 ;
  wire \location_Madd__add0000_Result<12>14_1585 ;
  wire \location_Madd__add0000_Result<12>2_1586 ;
  wire \location_Madd__add0000_Result<12>3_1587 ;
  wire \location_Madd__add0000_Result<13>1_1589 ;
  wire \location_Madd__add0000_Result<13>2_1590 ;
  wire \location_Madd__add0000_Result<13>3_1591 ;
  wire \location_Madd__add0000_Result<14>1 ;
  wire \location_Madd__add0000_Result<14>11_1594 ;
  wire \location_Madd__add0000_Result<14>111_1595 ;
  wire \location_Madd__add0000_Result<14>12_1596 ;
  wire \location_Madd__add0000_Result<14>13_1597 ;
  wire \location_Madd__add0000_Result<14>14_1598 ;
  wire \location_Madd__add0000_Result<14>2_1599 ;
  wire \location_Madd__add0000_Result<14>3_1600 ;
  wire \location_Madd__add0000_Result<15>1 ;
  wire \location_Madd__add0000_Result<15>11_1603 ;
  wire \location_Madd__add0000_Result<15>12_1604 ;
  wire \location_Madd__add0000_Result<15>13_1605 ;
  wire \location_Madd__add0000_Result<15>14_1606 ;
  wire \location_Madd__add0000_Result<15>2_1607 ;
  wire \location_Madd__add0000_Result<15>3_1608 ;
  wire \location_Madd__add0000_Result<1>1_1610 ;
  wire \location_Madd__add0000_Result<1>2_1611 ;
  wire \location_Madd__add0000_Result<1>3_1612 ;
  wire \location_Madd__add0000_Result<2>1 ;
  wire \location_Madd__add0000_Result<2>11_1615 ;
  wire \location_Madd__add0000_Result<2>111_1616 ;
  wire \location_Madd__add0000_Result<2>12_1617 ;
  wire \location_Madd__add0000_Result<2>13_1618 ;
  wire \location_Madd__add0000_Result<2>14_1619 ;
  wire \location_Madd__add0000_Result<2>2_1620 ;
  wire \location_Madd__add0000_Result<2>3_1621 ;
  wire \location_Madd__add0000_Result<3>1 ;
  wire \location_Madd__add0000_Result<3>11_1624 ;
  wire \location_Madd__add0000_Result<3>12_1625 ;
  wire \location_Madd__add0000_Result<3>13_1626 ;
  wire \location_Madd__add0000_Result<3>14_1627 ;
  wire \location_Madd__add0000_Result<3>2_1628 ;
  wire \location_Madd__add0000_Result<3>3_1629 ;
  wire \location_Madd__add0000_Result<4>1_1631 ;
  wire \location_Madd__add0000_Result<4>2_1632 ;
  wire \location_Madd__add0000_Result<4>3_1633 ;
  wire \location_Madd__add0000_Result<5>1 ;
  wire \location_Madd__add0000_Result<5>11_1636 ;
  wire \location_Madd__add0000_Result<5>111_1637 ;
  wire \location_Madd__add0000_Result<5>12_1638 ;
  wire \location_Madd__add0000_Result<5>13_1639 ;
  wire \location_Madd__add0000_Result<5>14_1640 ;
  wire \location_Madd__add0000_Result<5>2_1641 ;
  wire \location_Madd__add0000_Result<5>3_1642 ;
  wire \location_Madd__add0000_Result<6>1 ;
  wire \location_Madd__add0000_Result<6>11_1645 ;
  wire \location_Madd__add0000_Result<6>12_1646 ;
  wire \location_Madd__add0000_Result<6>13_1647 ;
  wire \location_Madd__add0000_Result<6>14_1648 ;
  wire \location_Madd__add0000_Result<6>2_1649 ;
  wire \location_Madd__add0000_Result<6>3_1650 ;
  wire \location_Madd__add0000_Result<7>1_1652 ;
  wire \location_Madd__add0000_Result<7>2_1653 ;
  wire \location_Madd__add0000_Result<7>3_1654 ;
  wire \location_Madd__add0000_Result<8>1 ;
  wire \location_Madd__add0000_Result<8>11_1657 ;
  wire \location_Madd__add0000_Result<8>111_1658 ;
  wire \location_Madd__add0000_Result<8>12_1659 ;
  wire \location_Madd__add0000_Result<8>13_1660 ;
  wire \location_Madd__add0000_Result<8>14_1661 ;
  wire \location_Madd__add0000_Result<8>2_1662 ;
  wire \location_Madd__add0000_Result<8>3_1663 ;
  wire \location_Madd__add0000_Result<9>1 ;
  wire \location_Madd__add0000_Result<9>11_1666 ;
  wire \location_Madd__add0000_Result<9>12_1667 ;
  wire \location_Madd__add0000_Result<9>13_1668 ;
  wire \location_Madd__add0000_Result<9>14_1669 ;
  wire \location_Madd__add0000_Result<9>2_1670 ;
  wire \location_Madd__add0000_Result<9>3_1671 ;
  wire location_or0001;
  wire [15 : 0] NlwRenamedSig_OI_count;
  wire [15 : 1] location_Madd__add0000_Result;
  wire [15 : 1] location__add0000;
  assign
    count[15] = NlwRenamedSig_OI_count[15],
    count[14] = NlwRenamedSig_OI_count[14],
    count[13] = NlwRenamedSig_OI_count[13],
    count[12] = NlwRenamedSig_OI_count[12],
    count[11] = NlwRenamedSig_OI_count[11],
    count[10] = NlwRenamedSig_OI_count[10],
    count[9] = NlwRenamedSig_OI_count[9],
    count[8] = NlwRenamedSig_OI_count[8],
    count[7] = NlwRenamedSig_OI_count[7],
    count[6] = NlwRenamedSig_OI_count[6],
    count[5] = NlwRenamedSig_OI_count[5],
    count[4] = NlwRenamedSig_OI_count[4],
    count[3] = NlwRenamedSig_OI_count[3],
    count[2] = NlwRenamedSig_OI_count[2],
    count[1] = NlwRenamedSig_OI_count[1],
    count[0] = NlwRenamedSig_OI_count[0];
  GND   XST_GND (
    .G(N0)
  );
  FDCE   location_15 (
    .CE(location_0__or0000),
    .CLR(N0),
    .C(Sclk),
    .D(location_15__and0000),
    .Q(NlwRenamedSig_OI_count[15])
  );
  FDCE   location_14 (
    .CE(location_0__or0000),
    .CLR(N0),
    .C(Sclk),
    .D(location_14__and0000),
    .Q(NlwRenamedSig_OI_count[14])
  );
  FDCE   location_13 (
    .CE(location_0__or0000),
    .CLR(N0),
    .C(Sclk),
    .D(location_13__and0000),
    .Q(NlwRenamedSig_OI_count[13])
  );
  FDCE   location_12 (
    .CE(location_0__or0000),
    .CLR(N0),
    .C(Sclk),
    .D(location_12__and0000),
    .Q(NlwRenamedSig_OI_count[12])
  );
  FDCE   location_11 (
    .CE(location_0__or0000),
    .CLR(N0),
    .C(Sclk),
    .D(location_11__and0000),
    .Q(NlwRenamedSig_OI_count[11])
  );
  FDCE   location_10 (
    .CE(location_0__or0000),
    .CLR(N0),
    .C(Sclk),
    .D(location_10__and0000),
    .Q(NlwRenamedSig_OI_count[10])
  );
  FDCE   location_9 (
    .CE(location_0__or0000),
    .CLR(N0),
    .C(Sclk),
    .D(location_9__and0000),
    .Q(NlwRenamedSig_OI_count[9])
  );
  FDCE   location_8 (
    .CE(location_0__or0000),
    .CLR(N0),
    .C(Sclk),
    .D(location_8__and0000),
    .Q(NlwRenamedSig_OI_count[8])
  );
  FDCE   location_7 (
    .CE(location_0__or0000),
    .CLR(N0),
    .C(Sclk),
    .D(location_7__and0000),
    .Q(NlwRenamedSig_OI_count[7])
  );
  FDCE   location_6 (
    .CE(location_0__or0000),
    .CLR(N0),
    .C(Sclk),
    .D(location_6__and0000),
    .Q(NlwRenamedSig_OI_count[6])
  );
  FDCE   location_5 (
    .CE(location_0__or0000),
    .CLR(N0),
    .C(Sclk),
    .D(location_5__and0000),
    .Q(NlwRenamedSig_OI_count[5])
  );
  FDCE   location_4 (
    .CE(location_0__or0000),
    .CLR(N0),
    .C(Sclk),
    .D(location_4__and0000),
    .Q(NlwRenamedSig_OI_count[4])
  );
  FDCE   location_3 (
    .CE(location_0__or0000),
    .CLR(N0),
    .C(Sclk),
    .D(location_3__and0000),
    .Q(NlwRenamedSig_OI_count[3])
  );
  FDCE   location_2 (
    .CE(location_0__or0000),
    .CLR(N0),
    .C(Sclk),
    .D(location_2__and0000),
    .Q(NlwRenamedSig_OI_count[2])
  );
  FDCE   location_1 (
    .CE(location_0__or0000),
    .CLR(N0),
    .C(Sclk),
    .D(location_1__and0000),
    .Q(NlwRenamedSig_OI_count[1])
  );
  FDCE   location_0 (
    .CE(location_0__or0000),
    .CLR(N0),
    .C(Sclk),
    .D(location_0__and0000),
    .Q(NlwRenamedSig_OI_count[0])
  );
  INV   location_15__and00001 (
    .I(Reset),
    .O(location_15__and00001_1532)
  );
  AND2   location_15__and00002 (
    .I0(location__add0000[15]),
    .I1(location_15__and00001_1532),
    .O(location_15__and0000)
  );
  INV   location_14__and00001 (
    .I(Reset),
    .O(location_14__and00001_1530)
  );
  AND2   location_14__and00002 (
    .I0(location__add0000[14]),
    .I1(location_14__and00001_1530),
    .O(location_14__and0000)
  );
  INV   location_13__and00001 (
    .I(Reset),
    .O(location_13__and00001_1528)
  );
  AND2   location_13__and00002 (
    .I0(location__add0000[13]),
    .I1(location_13__and00001_1528),
    .O(location_13__and0000)
  );
  INV   location_12__and00001 (
    .I(Reset),
    .O(location_12__and00001_1526)
  );
  AND2   location_12__and00002 (
    .I0(location__add0000[12]),
    .I1(location_12__and00001_1526),
    .O(location_12__and0000)
  );
  INV   location_11__and00001 (
    .I(Reset),
    .O(location_11__and00001_1524)
  );
  AND2   location_11__and00002 (
    .I0(location__add0000[11]),
    .I1(location_11__and00001_1524),
    .O(location_11__and0000)
  );
  INV   location_10__and00001 (
    .I(Reset),
    .O(location_10__and00001_1522)
  );
  AND2   location_10__and00002 (
    .I0(location__add0000[10]),
    .I1(location_10__and00001_1522),
    .O(location_10__and0000)
  );
  INV   location_9__and00001 (
    .I(Reset),
    .O(location_9__and00001_1550)
  );
  AND2   location_9__and00002 (
    .I0(location__add0000[9]),
    .I1(location_9__and00001_1550),
    .O(location_9__and0000)
  );
  INV   location_8__and00001 (
    .I(Reset),
    .O(location_8__and00001_1548)
  );
  AND2   location_8__and00002 (
    .I0(location__add0000[8]),
    .I1(location_8__and00001_1548),
    .O(location_8__and0000)
  );
  INV   location_7__and00001 (
    .I(Reset),
    .O(location_7__and00001_1546)
  );
  AND2   location_7__and00002 (
    .I0(location__add0000[7]),
    .I1(location_7__and00001_1546),
    .O(location_7__and0000)
  );
  INV   location_6__and00001 (
    .I(Reset),
    .O(location_6__and00001_1544)
  );
  AND2   location_6__and00002 (
    .I0(location__add0000[6]),
    .I1(location_6__and00001_1544),
    .O(location_6__and0000)
  );
  INV   location_5__and00001 (
    .I(Reset),
    .O(location_5__and00001_1542)
  );
  AND2   location_5__and00002 (
    .I0(location__add0000[5]),
    .I1(location_5__and00001_1542),
    .O(location_5__and0000)
  );
  INV   location_4__and00001 (
    .I(Reset),
    .O(location_4__and00001_1540)
  );
  AND2   location_4__and00002 (
    .I0(location__add0000[4]),
    .I1(location_4__and00001_1540),
    .O(location_4__and0000)
  );
  INV   location_3__and00001 (
    .I(Reset),
    .O(location_3__and00001_1538)
  );
  AND2   location_3__and00002 (
    .I0(location__add0000[3]),
    .I1(location_3__and00001_1538),
    .O(location_3__and0000)
  );
  INV   location_2__and00001 (
    .I(Reset),
    .O(location_2__and00001_1536)
  );
  AND2   location_2__and00002 (
    .I0(location__add0000[2]),
    .I1(location_2__and00001_1536),
    .O(location_2__and0000)
  );
  INV   location_1__and00001 (
    .I(Reset),
    .O(location_1__and00001_1534)
  );
  AND2   location_1__and00002 (
    .I0(location__add0000[1]),
    .I1(location_1__and00001_1534),
    .O(location_1__and0000)
  );
  OR2   location_0__or00001 (
    .I0(ce),
    .I1(Reset),
    .O(location_0__or0000)
  );
  INV   location_0__and00001 (
    .I(Reset),
    .O(location_0__and00001_1518)
  );
  INV   location_0__and00002 (
    .I(NlwRenamedSig_OI_count[0]),
    .O(location_0__and00002_1519)
  );
  AND2   location_0__and00003 (
    .I0(location_0__and00001_1518),
    .I1(location_0__and00002_1519),
    .O(location_0__and0000)
  );
  XOR2   location_or00011 (
    .I0(sense),
    .I1(updown),
    .O(location_or0001)
  );
  AND2   \location_Madd__add0000_Result<3>2  (
    .I0(NlwRenamedSig_OI_count[3]),
    .I1(N01),
    .O(location_Madd__add0000_Result[3])
  );
  INV   \location_Madd__add0000_Result<3>3  (
    .I(NlwRenamedSig_OI_count[3]),
    .O(\location_Madd__add0000_Result<3>1 )
  );
  INV   \location_Madd__add0000_Result<3>4  (
    .I(N01),
    .O(\location_Madd__add0000_Result<3>2_1628 )
  );
  AND2   \location_Madd__add0000_Result<3>5  (
    .I0(\location_Madd__add0000_Result<3>1 ),
    .I1(\location_Madd__add0000_Result<3>2_1628 ),
    .O(\location_Madd__add0000_Result<3>3_1629 )
  );
  OR2   \location_Madd__add0000_Result<3>6  (
    .I0(location_Madd__add0000_Result[3]),
    .I1(\location_Madd__add0000_Result<3>3_1629 ),
    .O(location__add0000[3])
  );
  AND2   \location_Madd__add0000_Result<6>2  (
    .I0(NlwRenamedSig_OI_count[6]),
    .I1(N11),
    .O(location_Madd__add0000_Result[6])
  );
  INV   \location_Madd__add0000_Result<6>3  (
    .I(NlwRenamedSig_OI_count[6]),
    .O(\location_Madd__add0000_Result<6>1 )
  );
  INV   \location_Madd__add0000_Result<6>4  (
    .I(N11),
    .O(\location_Madd__add0000_Result<6>2_1649 )
  );
  AND2   \location_Madd__add0000_Result<6>5  (
    .I0(\location_Madd__add0000_Result<6>1 ),
    .I1(\location_Madd__add0000_Result<6>2_1649 ),
    .O(\location_Madd__add0000_Result<6>3_1650 )
  );
  OR2   \location_Madd__add0000_Result<6>6  (
    .I0(location_Madd__add0000_Result[6]),
    .I1(\location_Madd__add0000_Result<6>3_1650 ),
    .O(location__add0000[6])
  );
  AND2   \location_Madd__add0000_Result<9>2  (
    .I0(NlwRenamedSig_OI_count[9]),
    .I1(N2),
    .O(location_Madd__add0000_Result[9])
  );
  INV   \location_Madd__add0000_Result<9>3  (
    .I(NlwRenamedSig_OI_count[9]),
    .O(\location_Madd__add0000_Result<9>1 )
  );
  INV   \location_Madd__add0000_Result<9>4  (
    .I(N2),
    .O(\location_Madd__add0000_Result<9>2_1670 )
  );
  AND2   \location_Madd__add0000_Result<9>5  (
    .I0(\location_Madd__add0000_Result<9>1 ),
    .I1(\location_Madd__add0000_Result<9>2_1670 ),
    .O(\location_Madd__add0000_Result<9>3_1671 )
  );
  OR2   \location_Madd__add0000_Result<9>6  (
    .I0(location_Madd__add0000_Result[9]),
    .I1(\location_Madd__add0000_Result<9>3_1671 ),
    .O(location__add0000[9])
  );
  AND2   \location_Madd__add0000_Result<12>2  (
    .I0(NlwRenamedSig_OI_count[12]),
    .I1(N3),
    .O(location_Madd__add0000_Result[12])
  );
  INV   \location_Madd__add0000_Result<12>3  (
    .I(NlwRenamedSig_OI_count[12]),
    .O(\location_Madd__add0000_Result<12>1 )
  );
  INV   \location_Madd__add0000_Result<12>4  (
    .I(N3),
    .O(\location_Madd__add0000_Result<12>2_1586 )
  );
  AND2   \location_Madd__add0000_Result<12>5  (
    .I0(\location_Madd__add0000_Result<12>1 ),
    .I1(\location_Madd__add0000_Result<12>2_1586 ),
    .O(\location_Madd__add0000_Result<12>3_1587 )
  );
  OR2   \location_Madd__add0000_Result<12>6  (
    .I0(location_Madd__add0000_Result[12]),
    .I1(\location_Madd__add0000_Result<12>3_1587 ),
    .O(location__add0000[12])
  );
  AND2   \location_Madd__add0000_Result<15>2  (
    .I0(NlwRenamedSig_OI_count[15]),
    .I1(N4),
    .O(location_Madd__add0000_Result[15])
  );
  INV   \location_Madd__add0000_Result<15>3  (
    .I(NlwRenamedSig_OI_count[15]),
    .O(\location_Madd__add0000_Result<15>1 )
  );
  INV   \location_Madd__add0000_Result<15>4  (
    .I(N4),
    .O(\location_Madd__add0000_Result<15>2_1607 )
  );
  AND2   \location_Madd__add0000_Result<15>5  (
    .I0(\location_Madd__add0000_Result<15>1 ),
    .I1(\location_Madd__add0000_Result<15>2_1607 ),
    .O(\location_Madd__add0000_Result<15>3_1608 )
  );
  OR2   \location_Madd__add0000_Result<15>6  (
    .I0(location_Madd__add0000_Result[15]),
    .I1(\location_Madd__add0000_Result<15>3_1608 ),
    .O(location__add0000[15])
  );
  AND2   \location_Madd__add0000_Result<2>2  (
    .I0(NlwRenamedSig_OI_count[2]),
    .I1(N5),
    .O(location_Madd__add0000_Result[2])
  );
  INV   \location_Madd__add0000_Result<2>3  (
    .I(NlwRenamedSig_OI_count[2]),
    .O(\location_Madd__add0000_Result<2>1 )
  );
  INV   \location_Madd__add0000_Result<2>4  (
    .I(N5),
    .O(\location_Madd__add0000_Result<2>2_1620 )
  );
  AND2   \location_Madd__add0000_Result<2>5  (
    .I0(\location_Madd__add0000_Result<2>1 ),
    .I1(\location_Madd__add0000_Result<2>2_1620 ),
    .O(\location_Madd__add0000_Result<2>3_1621 )
  );
  OR2   \location_Madd__add0000_Result<2>6  (
    .I0(location_Madd__add0000_Result[2]),
    .I1(\location_Madd__add0000_Result<2>3_1621 ),
    .O(location__add0000[2])
  );
  AND2   \location_Madd__add0000_Result<5>2  (
    .I0(NlwRenamedSig_OI_count[5]),
    .I1(N6),
    .O(location_Madd__add0000_Result[5])
  );
  INV   \location_Madd__add0000_Result<5>3  (
    .I(NlwRenamedSig_OI_count[5]),
    .O(\location_Madd__add0000_Result<5>1 )
  );
  INV   \location_Madd__add0000_Result<5>4  (
    .I(N6),
    .O(\location_Madd__add0000_Result<5>2_1641 )
  );
  AND2   \location_Madd__add0000_Result<5>5  (
    .I0(\location_Madd__add0000_Result<5>1 ),
    .I1(\location_Madd__add0000_Result<5>2_1641 ),
    .O(\location_Madd__add0000_Result<5>3_1642 )
  );
  OR2   \location_Madd__add0000_Result<5>6  (
    .I0(location_Madd__add0000_Result[5]),
    .I1(\location_Madd__add0000_Result<5>3_1642 ),
    .O(location__add0000[5])
  );
  AND2   \location_Madd__add0000_Result<8>2  (
    .I0(NlwRenamedSig_OI_count[8]),
    .I1(N7),
    .O(location_Madd__add0000_Result[8])
  );
  INV   \location_Madd__add0000_Result<8>3  (
    .I(NlwRenamedSig_OI_count[8]),
    .O(\location_Madd__add0000_Result<8>1 )
  );
  INV   \location_Madd__add0000_Result<8>4  (
    .I(N7),
    .O(\location_Madd__add0000_Result<8>2_1662 )
  );
  AND2   \location_Madd__add0000_Result<8>5  (
    .I0(\location_Madd__add0000_Result<8>1 ),
    .I1(\location_Madd__add0000_Result<8>2_1662 ),
    .O(\location_Madd__add0000_Result<8>3_1663 )
  );
  OR2   \location_Madd__add0000_Result<8>6  (
    .I0(location_Madd__add0000_Result[8]),
    .I1(\location_Madd__add0000_Result<8>3_1663 ),
    .O(location__add0000[8])
  );
  AND2   \location_Madd__add0000_Result<11>2  (
    .I0(NlwRenamedSig_OI_count[11]),
    .I1(N8),
    .O(location_Madd__add0000_Result[11])
  );
  INV   \location_Madd__add0000_Result<11>3  (
    .I(NlwRenamedSig_OI_count[11]),
    .O(\location_Madd__add0000_Result<11>1 )
  );
  INV   \location_Madd__add0000_Result<11>4  (
    .I(N8),
    .O(\location_Madd__add0000_Result<11>2_1578 )
  );
  AND2   \location_Madd__add0000_Result<11>5  (
    .I0(\location_Madd__add0000_Result<11>1 ),
    .I1(\location_Madd__add0000_Result<11>2_1578 ),
    .O(\location_Madd__add0000_Result<11>3_1579 )
  );
  OR2   \location_Madd__add0000_Result<11>6  (
    .I0(location_Madd__add0000_Result[11]),
    .I1(\location_Madd__add0000_Result<11>3_1579 ),
    .O(location__add0000[11])
  );
  AND2   \location_Madd__add0000_Result<14>2  (
    .I0(NlwRenamedSig_OI_count[14]),
    .I1(N9),
    .O(location_Madd__add0000_Result[14])
  );
  INV   \location_Madd__add0000_Result<14>3  (
    .I(NlwRenamedSig_OI_count[14]),
    .O(\location_Madd__add0000_Result<14>1 )
  );
  INV   \location_Madd__add0000_Result<14>4  (
    .I(N9),
    .O(\location_Madd__add0000_Result<14>2_1599 )
  );
  AND2   \location_Madd__add0000_Result<14>5  (
    .I0(\location_Madd__add0000_Result<14>1 ),
    .I1(\location_Madd__add0000_Result<14>2_1599 ),
    .O(\location_Madd__add0000_Result<14>3_1600 )
  );
  OR2   \location_Madd__add0000_Result<14>6  (
    .I0(location_Madd__add0000_Result[14]),
    .I1(\location_Madd__add0000_Result<14>3_1600 ),
    .O(location__add0000[14])
  );
  XOR2   \location_Madd__add0000_Result<13>11  (
    .I0(location_or0001),
    .I1(\location_Madd__add0000_CARRY_IN[13] ),
    .O(N10)
  );
  AND2   \location_Madd__add0000_Result<13>1  (
    .I0(NlwRenamedSig_OI_count[13]),
    .I1(N10),
    .O(location_Madd__add0000_Result[13])
  );
  INV   \location_Madd__add0000_Result<13>2  (
    .I(NlwRenamedSig_OI_count[13]),
    .O(\location_Madd__add0000_Result<13>1_1589 )
  );
  INV   \location_Madd__add0000_Result<13>3  (
    .I(N10),
    .O(\location_Madd__add0000_Result<13>2_1590 )
  );
  AND2   \location_Madd__add0000_Result<13>4  (
    .I0(\location_Madd__add0000_Result<13>1_1589 ),
    .I1(\location_Madd__add0000_Result<13>2_1590 ),
    .O(\location_Madd__add0000_Result<13>3_1591 )
  );
  OR2   \location_Madd__add0000_Result<13>5  (
    .I0(location_Madd__add0000_Result[13]),
    .I1(\location_Madd__add0000_Result<13>3_1591 ),
    .O(location__add0000[13])
  );
  XOR2   \location_Madd__add0000_Result<10>11  (
    .I0(location_or0001),
    .I1(\location_Madd__add0000_CARRY_IN[10] ),
    .O(N111)
  );
  AND2   \location_Madd__add0000_Result<10>1  (
    .I0(NlwRenamedSig_OI_count[10]),
    .I1(N111),
    .O(location_Madd__add0000_Result[10])
  );
  INV   \location_Madd__add0000_Result<10>2  (
    .I(NlwRenamedSig_OI_count[10]),
    .O(\location_Madd__add0000_Result<10>1_1568 )
  );
  INV   \location_Madd__add0000_Result<10>3  (
    .I(N111),
    .O(\location_Madd__add0000_Result<10>2_1569 )
  );
  AND2   \location_Madd__add0000_Result<10>4  (
    .I0(\location_Madd__add0000_Result<10>1_1568 ),
    .I1(\location_Madd__add0000_Result<10>2_1569 ),
    .O(\location_Madd__add0000_Result<10>3_1570 )
  );
  OR2   \location_Madd__add0000_Result<10>5  (
    .I0(location_Madd__add0000_Result[10]),
    .I1(\location_Madd__add0000_Result<10>3_1570 ),
    .O(location__add0000[10])
  );
  XOR2   \location_Madd__add0000_Result<7>11  (
    .I0(location_or0001),
    .I1(\location_Madd__add0000_CARRY_IN[7] ),
    .O(N12)
  );
  AND2   \location_Madd__add0000_Result<7>1  (
    .I0(NlwRenamedSig_OI_count[7]),
    .I1(N12),
    .O(location_Madd__add0000_Result[7])
  );
  INV   \location_Madd__add0000_Result<7>2  (
    .I(NlwRenamedSig_OI_count[7]),
    .O(\location_Madd__add0000_Result<7>1_1652 )
  );
  INV   \location_Madd__add0000_Result<7>3  (
    .I(N12),
    .O(\location_Madd__add0000_Result<7>2_1653 )
  );
  AND2   \location_Madd__add0000_Result<7>4  (
    .I0(\location_Madd__add0000_Result<7>1_1652 ),
    .I1(\location_Madd__add0000_Result<7>2_1653 ),
    .O(\location_Madd__add0000_Result<7>3_1654 )
  );
  OR2   \location_Madd__add0000_Result<7>5  (
    .I0(location_Madd__add0000_Result[7]),
    .I1(\location_Madd__add0000_Result<7>3_1654 ),
    .O(location__add0000[7])
  );
  XOR2   \location_Madd__add0000_Result<4>11  (
    .I0(location_or0001),
    .I1(\location_Madd__add0000_CARRY_IN[4] ),
    .O(N13)
  );
  AND2   \location_Madd__add0000_Result<4>1  (
    .I0(NlwRenamedSig_OI_count[4]),
    .I1(N13),
    .O(location_Madd__add0000_Result[4])
  );
  INV   \location_Madd__add0000_Result<4>2  (
    .I(NlwRenamedSig_OI_count[4]),
    .O(\location_Madd__add0000_Result<4>1_1631 )
  );
  INV   \location_Madd__add0000_Result<4>3  (
    .I(N13),
    .O(\location_Madd__add0000_Result<4>2_1632 )
  );
  AND2   \location_Madd__add0000_Result<4>4  (
    .I0(\location_Madd__add0000_Result<4>1_1631 ),
    .I1(\location_Madd__add0000_Result<4>2_1632 ),
    .O(\location_Madd__add0000_Result<4>3_1633 )
  );
  OR2   \location_Madd__add0000_Result<4>5  (
    .I0(location_Madd__add0000_Result[4]),
    .I1(\location_Madd__add0000_Result<4>3_1633 ),
    .O(location__add0000[4])
  );
  XOR2   \location_Madd__add0000_Result<1>11  (
    .I0(location_or0001),
    .I1(NlwRenamedSig_OI_count[1]),
    .O(N14)
  );
  AND2   \location_Madd__add0000_Result<1>1  (
    .I0(NlwRenamedSig_OI_count[0]),
    .I1(N14),
    .O(location_Madd__add0000_Result[1])
  );
  INV   \location_Madd__add0000_Result<1>2  (
    .I(NlwRenamedSig_OI_count[0]),
    .O(\location_Madd__add0000_Result<1>1_1610 )
  );
  INV   \location_Madd__add0000_Result<1>3  (
    .I(N14),
    .O(\location_Madd__add0000_Result<1>2_1611 )
  );
  AND2   \location_Madd__add0000_Result<1>4  (
    .I0(\location_Madd__add0000_Result<1>1_1610 ),
    .I1(\location_Madd__add0000_Result<1>2_1611 ),
    .O(\location_Madd__add0000_Result<1>3_1612 )
  );
  OR2   \location_Madd__add0000_Result<1>5  (
    .I0(location_Madd__add0000_Result[1]),
    .I1(\location_Madd__add0000_Result<1>3_1612 ),
    .O(location__add0000[1])
  );
  OR4   \location_Madd__add0000_CARRY_IN<4>11  (
    .I0(NlwRenamedSig_OI_count[0]),
    .I1(NlwRenamedSig_OI_count[1]),
    .I2(NlwRenamedSig_OI_count[2]),
    .I3(NlwRenamedSig_OI_count[3]),
    .O(N15)
  );
  AND2   \location_Madd__add0000_CARRY_IN<4>1  (
    .I0(SFDecomp_84),
    .I1(NlwRenamedSig_OI_count[3]),
    .O(\location_Madd__add0000_CARRY_IN<4>1_1560 )
  );
  INV   \location_Madd__add0000_CARRY_IN<4>2  (
    .I(location_or0001),
    .O(\location_Madd__add0000_CARRY_IN<4>2_1561 )
  );
  AND2   \location_Madd__add0000_CARRY_IN<4>3  (
    .I0(N15),
    .I1(\location_Madd__add0000_CARRY_IN<4>2_1561 ),
    .O(\location_Madd__add0000_CARRY_IN<4>3_1562 )
  );
  OR2   \location_Madd__add0000_CARRY_IN<4>4  (
    .I0(\location_Madd__add0000_CARRY_IN<4>1_1560 ),
    .I1(\location_Madd__add0000_CARRY_IN<4>3_1562 ),
    .O(\location_Madd__add0000_CARRY_IN[4] )
  );
  OR4   \location_Madd__add0000_CARRY_IN<7>11  (
    .I0(NlwRenamedSig_OI_count[4]),
    .I1(NlwRenamedSig_OI_count[5]),
    .I2(NlwRenamedSig_OI_count[6]),
    .I3(\location_Madd__add0000_CARRY_IN[4] ),
    .O(N16)
  );
  AND2   \location_Madd__add0000_CARRY_IN<7>1  (
    .I0(SFDecomp_85),
    .I1(\location_Madd__add0000_CARRY_IN[4] ),
    .O(\location_Madd__add0000_CARRY_IN<7>1_1564 )
  );
  INV   \location_Madd__add0000_CARRY_IN<7>2  (
    .I(location_or0001),
    .O(\location_Madd__add0000_CARRY_IN<7>2_1565 )
  );
  AND2   \location_Madd__add0000_CARRY_IN<7>3  (
    .I0(N16),
    .I1(\location_Madd__add0000_CARRY_IN<7>2_1565 ),
    .O(\location_Madd__add0000_CARRY_IN<7>3_1566 )
  );
  OR2   \location_Madd__add0000_CARRY_IN<7>4  (
    .I0(\location_Madd__add0000_CARRY_IN<7>1_1564 ),
    .I1(\location_Madd__add0000_CARRY_IN<7>3_1566 ),
    .O(\location_Madd__add0000_CARRY_IN[7] )
  );
  OR4   \location_Madd__add0000_CARRY_IN<10>11  (
    .I0(NlwRenamedSig_OI_count[7]),
    .I1(NlwRenamedSig_OI_count[8]),
    .I2(NlwRenamedSig_OI_count[9]),
    .I3(\location_Madd__add0000_CARRY_IN[7] ),
    .O(N17)
  );
  AND2   \location_Madd__add0000_CARRY_IN<10>1  (
    .I0(SFDecomp_86),
    .I1(\location_Madd__add0000_CARRY_IN[7] ),
    .O(\location_Madd__add0000_CARRY_IN<10>1_1552 )
  );
  INV   \location_Madd__add0000_CARRY_IN<10>2  (
    .I(location_or0001),
    .O(\location_Madd__add0000_CARRY_IN<10>2_1553 )
  );
  AND2   \location_Madd__add0000_CARRY_IN<10>3  (
    .I0(N17),
    .I1(\location_Madd__add0000_CARRY_IN<10>2_1553 ),
    .O(\location_Madd__add0000_CARRY_IN<10>3_1554 )
  );
  OR2   \location_Madd__add0000_CARRY_IN<10>4  (
    .I0(\location_Madd__add0000_CARRY_IN<10>1_1552 ),
    .I1(\location_Madd__add0000_CARRY_IN<10>3_1554 ),
    .O(\location_Madd__add0000_CARRY_IN[10] )
  );
  OR4   \location_Madd__add0000_CARRY_IN<13>11  (
    .I0(NlwRenamedSig_OI_count[10]),
    .I1(NlwRenamedSig_OI_count[11]),
    .I2(NlwRenamedSig_OI_count[12]),
    .I3(\location_Madd__add0000_CARRY_IN[10] ),
    .O(N18)
  );
  AND2   \location_Madd__add0000_CARRY_IN<13>1  (
    .I0(SFDecomp_87),
    .I1(\location_Madd__add0000_CARRY_IN[10] ),
    .O(\location_Madd__add0000_CARRY_IN<13>1_1556 )
  );
  INV   \location_Madd__add0000_CARRY_IN<13>2  (
    .I(location_or0001),
    .O(\location_Madd__add0000_CARRY_IN<13>2_1557 )
  );
  AND2   \location_Madd__add0000_CARRY_IN<13>3  (
    .I0(N18),
    .I1(\location_Madd__add0000_CARRY_IN<13>2_1557 ),
    .O(\location_Madd__add0000_CARRY_IN<13>3_1558 )
  );
  OR2   \location_Madd__add0000_CARRY_IN<13>4  (
    .I0(\location_Madd__add0000_CARRY_IN<13>1_1556 ),
    .I1(\location_Madd__add0000_CARRY_IN<13>3_1558 ),
    .O(\location_Madd__add0000_CARRY_IN[13] )
  );
  INV   \location_Madd__add0000_Result<12>11  (
    .I(location_or0001),
    .O(\location_Madd__add0000_Result<12>11_1582 )
  );
  INV   \location_Madd__add0000_Result<12>12  (
    .I(NlwRenamedSig_OI_count[11]),
    .O(\location_Madd__add0000_Result<12>12_1583 )
  );
  AND2   \location_Madd__add0000_Result<12>13  (
    .I0(NlwRenamedSig_OI_count[11]),
    .I1(\location_Madd__add0000_Result<12>11_1582 ),
    .O(\location_Madd__add0000_Result<12>13_1584 )
  );
  AND2   \location_Madd__add0000_Result<12>14  (
    .I0(location_or0001),
    .I1(\location_Madd__add0000_Result<12>12_1583 ),
    .O(\location_Madd__add0000_Result<12>14_1585 )
  );
  OR3   \location_Madd__add0000_Result<12>15  (
    .I0(\location_Madd__add0000_Result<12>13_1584 ),
    .I1(N8),
    .I2(\location_Madd__add0000_Result<12>14_1585 ),
    .O(N3)
  );
  INV   \location_Madd__add0000_Result<15>11  (
    .I(location_or0001),
    .O(\location_Madd__add0000_Result<15>11_1603 )
  );
  INV   \location_Madd__add0000_Result<15>12  (
    .I(NlwRenamedSig_OI_count[14]),
    .O(\location_Madd__add0000_Result<15>12_1604 )
  );
  AND2   \location_Madd__add0000_Result<15>13  (
    .I0(NlwRenamedSig_OI_count[14]),
    .I1(\location_Madd__add0000_Result<15>11_1603 ),
    .O(\location_Madd__add0000_Result<15>13_1605 )
  );
  AND2   \location_Madd__add0000_Result<15>14  (
    .I0(location_or0001),
    .I1(\location_Madd__add0000_Result<15>12_1604 ),
    .O(\location_Madd__add0000_Result<15>14_1606 )
  );
  OR3   \location_Madd__add0000_Result<15>15  (
    .I0(\location_Madd__add0000_Result<15>13_1605 ),
    .I1(N9),
    .I2(\location_Madd__add0000_Result<15>14_1606 ),
    .O(N4)
  );
  INV   \location_Madd__add0000_Result<3>11  (
    .I(location_or0001),
    .O(\location_Madd__add0000_Result<3>11_1624 )
  );
  INV   \location_Madd__add0000_Result<3>12  (
    .I(NlwRenamedSig_OI_count[2]),
    .O(\location_Madd__add0000_Result<3>12_1625 )
  );
  AND2   \location_Madd__add0000_Result<3>13  (
    .I0(NlwRenamedSig_OI_count[2]),
    .I1(\location_Madd__add0000_Result<3>11_1624 ),
    .O(\location_Madd__add0000_Result<3>13_1626 )
  );
  AND2   \location_Madd__add0000_Result<3>14  (
    .I0(location_or0001),
    .I1(\location_Madd__add0000_Result<3>12_1625 ),
    .O(\location_Madd__add0000_Result<3>14_1627 )
  );
  OR3   \location_Madd__add0000_Result<3>15  (
    .I0(\location_Madd__add0000_Result<3>13_1626 ),
    .I1(N5),
    .I2(\location_Madd__add0000_Result<3>14_1627 ),
    .O(N01)
  );
  INV   \location_Madd__add0000_Result<6>11  (
    .I(location_or0001),
    .O(\location_Madd__add0000_Result<6>11_1645 )
  );
  INV   \location_Madd__add0000_Result<6>12  (
    .I(NlwRenamedSig_OI_count[5]),
    .O(\location_Madd__add0000_Result<6>12_1646 )
  );
  AND2   \location_Madd__add0000_Result<6>13  (
    .I0(NlwRenamedSig_OI_count[5]),
    .I1(\location_Madd__add0000_Result<6>11_1645 ),
    .O(\location_Madd__add0000_Result<6>13_1647 )
  );
  AND2   \location_Madd__add0000_Result<6>14  (
    .I0(location_or0001),
    .I1(\location_Madd__add0000_Result<6>12_1646 ),
    .O(\location_Madd__add0000_Result<6>14_1648 )
  );
  OR3   \location_Madd__add0000_Result<6>15  (
    .I0(\location_Madd__add0000_Result<6>13_1647 ),
    .I1(N6),
    .I2(\location_Madd__add0000_Result<6>14_1648 ),
    .O(N11)
  );
  INV   \location_Madd__add0000_Result<9>11  (
    .I(location_or0001),
    .O(\location_Madd__add0000_Result<9>11_1666 )
  );
  INV   \location_Madd__add0000_Result<9>12  (
    .I(NlwRenamedSig_OI_count[8]),
    .O(\location_Madd__add0000_Result<9>12_1667 )
  );
  AND2   \location_Madd__add0000_Result<9>13  (
    .I0(NlwRenamedSig_OI_count[8]),
    .I1(\location_Madd__add0000_Result<9>11_1666 ),
    .O(\location_Madd__add0000_Result<9>13_1668 )
  );
  AND2   \location_Madd__add0000_Result<9>14  (
    .I0(location_or0001),
    .I1(\location_Madd__add0000_Result<9>12_1667 ),
    .O(\location_Madd__add0000_Result<9>14_1669 )
  );
  OR3   \location_Madd__add0000_Result<9>15  (
    .I0(\location_Madd__add0000_Result<9>13_1668 ),
    .I1(N7),
    .I2(\location_Madd__add0000_Result<9>14_1669 ),
    .O(N2)
  );
  INV   \location_Madd__add0000_Result<11>111  (
    .I(NlwRenamedSig_OI_count[10]),
    .O(\location_Madd__add0000_Result<11>11_1573 )
  );
  INV   \location_Madd__add0000_Result<11>112  (
    .I(\location_Madd__add0000_CARRY_IN[10] ),
    .O(\location_Madd__add0000_Result<11>111_1574 )
  );
  OR2   \location_Madd__add0000_Result<11>113  (
    .I0(\location_Madd__add0000_Result<11>11_1573 ),
    .I1(\location_Madd__add0000_Result<11>111_1574 ),
    .O(N19)
  );
  INV   \location_Madd__add0000_Result<14>111  (
    .I(NlwRenamedSig_OI_count[13]),
    .O(\location_Madd__add0000_Result<14>11_1594 )
  );
  INV   \location_Madd__add0000_Result<14>112  (
    .I(\location_Madd__add0000_CARRY_IN[13] ),
    .O(\location_Madd__add0000_Result<14>111_1595 )
  );
  OR2   \location_Madd__add0000_Result<14>113  (
    .I0(\location_Madd__add0000_Result<14>11_1594 ),
    .I1(\location_Madd__add0000_Result<14>111_1595 ),
    .O(N20)
  );
  INV   \location_Madd__add0000_Result<2>111  (
    .I(NlwRenamedSig_OI_count[0]),
    .O(\location_Madd__add0000_Result<2>11_1615 )
  );
  INV   \location_Madd__add0000_Result<2>112  (
    .I(NlwRenamedSig_OI_count[1]),
    .O(\location_Madd__add0000_Result<2>111_1616 )
  );
  OR2   \location_Madd__add0000_Result<2>113  (
    .I0(\location_Madd__add0000_Result<2>11_1615 ),
    .I1(\location_Madd__add0000_Result<2>111_1616 ),
    .O(N21)
  );
  INV   \location_Madd__add0000_Result<5>111  (
    .I(NlwRenamedSig_OI_count[4]),
    .O(\location_Madd__add0000_Result<5>11_1636 )
  );
  INV   \location_Madd__add0000_Result<5>112  (
    .I(\location_Madd__add0000_CARRY_IN[4] ),
    .O(\location_Madd__add0000_Result<5>111_1637 )
  );
  OR2   \location_Madd__add0000_Result<5>113  (
    .I0(\location_Madd__add0000_Result<5>11_1636 ),
    .I1(\location_Madd__add0000_Result<5>111_1637 ),
    .O(N22)
  );
  INV   \location_Madd__add0000_Result<8>111  (
    .I(NlwRenamedSig_OI_count[7]),
    .O(\location_Madd__add0000_Result<8>11_1657 )
  );
  INV   \location_Madd__add0000_Result<8>112  (
    .I(\location_Madd__add0000_CARRY_IN[7] ),
    .O(\location_Madd__add0000_Result<8>111_1658 )
  );
  OR2   \location_Madd__add0000_Result<8>113  (
    .I0(\location_Madd__add0000_Result<8>11_1657 ),
    .I1(\location_Madd__add0000_Result<8>111_1658 ),
    .O(N23)
  );
  OR2   \location_Madd__add0000_Result<11>121  (
    .I0(NlwRenamedSig_OI_count[10]),
    .I1(\location_Madd__add0000_CARRY_IN[10] ),
    .O(N24)
  );
  AND2   \location_Madd__add0000_Result<11>11  (
    .I0(location_or0001),
    .I1(N19),
    .O(\location_Madd__add0000_Result<11>12_1575 )
  );
  INV   \location_Madd__add0000_Result<11>12  (
    .I(location_or0001),
    .O(\location_Madd__add0000_Result<11>13_1576 )
  );
  AND2   \location_Madd__add0000_Result<11>13  (
    .I0(N24),
    .I1(\location_Madd__add0000_Result<11>13_1576 ),
    .O(\location_Madd__add0000_Result<11>14_1577 )
  );
  OR2   \location_Madd__add0000_Result<11>14  (
    .I0(\location_Madd__add0000_Result<11>12_1575 ),
    .I1(\location_Madd__add0000_Result<11>14_1577 ),
    .O(N8)
  );
  OR2   \location_Madd__add0000_Result<14>121  (
    .I0(NlwRenamedSig_OI_count[13]),
    .I1(\location_Madd__add0000_CARRY_IN[13] ),
    .O(N25)
  );
  AND2   \location_Madd__add0000_Result<14>11  (
    .I0(location_or0001),
    .I1(N20),
    .O(\location_Madd__add0000_Result<14>12_1596 )
  );
  INV   \location_Madd__add0000_Result<14>12  (
    .I(location_or0001),
    .O(\location_Madd__add0000_Result<14>13_1597 )
  );
  AND2   \location_Madd__add0000_Result<14>13  (
    .I0(N25),
    .I1(\location_Madd__add0000_Result<14>13_1597 ),
    .O(\location_Madd__add0000_Result<14>14_1598 )
  );
  OR2   \location_Madd__add0000_Result<14>14  (
    .I0(\location_Madd__add0000_Result<14>12_1596 ),
    .I1(\location_Madd__add0000_Result<14>14_1598 ),
    .O(N9)
  );
  OR2   \location_Madd__add0000_Result<2>121  (
    .I0(NlwRenamedSig_OI_count[0]),
    .I1(NlwRenamedSig_OI_count[1]),
    .O(N26)
  );
  AND2   \location_Madd__add0000_Result<2>11  (
    .I0(location_or0001),
    .I1(N21),
    .O(\location_Madd__add0000_Result<2>12_1617 )
  );
  INV   \location_Madd__add0000_Result<2>12  (
    .I(location_or0001),
    .O(\location_Madd__add0000_Result<2>13_1618 )
  );
  AND2   \location_Madd__add0000_Result<2>13  (
    .I0(N26),
    .I1(\location_Madd__add0000_Result<2>13_1618 ),
    .O(\location_Madd__add0000_Result<2>14_1619 )
  );
  OR2   \location_Madd__add0000_Result<2>14  (
    .I0(\location_Madd__add0000_Result<2>12_1617 ),
    .I1(\location_Madd__add0000_Result<2>14_1619 ),
    .O(N5)
  );
  OR2   \location_Madd__add0000_Result<5>121  (
    .I0(NlwRenamedSig_OI_count[4]),
    .I1(\location_Madd__add0000_CARRY_IN[4] ),
    .O(N27)
  );
  AND2   \location_Madd__add0000_Result<5>11  (
    .I0(location_or0001),
    .I1(N22),
    .O(\location_Madd__add0000_Result<5>12_1638 )
  );
  INV   \location_Madd__add0000_Result<5>12  (
    .I(location_or0001),
    .O(\location_Madd__add0000_Result<5>13_1639 )
  );
  AND2   \location_Madd__add0000_Result<5>13  (
    .I0(N27),
    .I1(\location_Madd__add0000_Result<5>13_1639 ),
    .O(\location_Madd__add0000_Result<5>14_1640 )
  );
  OR2   \location_Madd__add0000_Result<5>14  (
    .I0(\location_Madd__add0000_Result<5>12_1638 ),
    .I1(\location_Madd__add0000_Result<5>14_1640 ),
    .O(N6)
  );
  OR2   \location_Madd__add0000_Result<8>121  (
    .I0(NlwRenamedSig_OI_count[7]),
    .I1(\location_Madd__add0000_CARRY_IN[7] ),
    .O(N28)
  );
  AND2   \location_Madd__add0000_Result<8>11  (
    .I0(location_or0001),
    .I1(N23),
    .O(\location_Madd__add0000_Result<8>12_1659 )
  );
  INV   \location_Madd__add0000_Result<8>12  (
    .I(location_or0001),
    .O(\location_Madd__add0000_Result<8>13_1660 )
  );
  AND2   \location_Madd__add0000_Result<8>13  (
    .I0(N28),
    .I1(\location_Madd__add0000_Result<8>13_1660 ),
    .O(\location_Madd__add0000_Result<8>14_1661 )
  );
  OR2   \location_Madd__add0000_Result<8>14  (
    .I0(\location_Madd__add0000_Result<8>12_1659 ),
    .I1(\location_Madd__add0000_Result<8>14_1661 ),
    .O(N7)
  );
  AND3   SFDecomp_841 (
    .I0(NlwRenamedSig_OI_count[0]),
    .I1(NlwRenamedSig_OI_count[1]),
    .I2(NlwRenamedSig_OI_count[2]),
    .O(SFDecomp_84)
  );
  AND3   SFDecomp_851 (
    .I0(NlwRenamedSig_OI_count[4]),
    .I1(NlwRenamedSig_OI_count[5]),
    .I2(NlwRenamedSig_OI_count[6]),
    .O(SFDecomp_85)
  );
  AND3   SFDecomp_861 (
    .I0(NlwRenamedSig_OI_count[7]),
    .I1(NlwRenamedSig_OI_count[8]),
    .I2(NlwRenamedSig_OI_count[9]),
    .O(SFDecomp_86)
  );
  AND3   SFDecomp_871 (
    .I0(NlwRenamedSig_OI_count[10]),
    .I1(NlwRenamedSig_OI_count[11]),
    .I2(NlwRenamedSig_OI_count[12]),
    .O(SFDecomp_87)
  );
endmodule

module HomeConfig (
  Zero0, Zero1, DCORENCCTLw, DCOR0THRESLOWr, DCOR0THRESHIGHr, Reset, DCOR1THRESHIGHr, DCORIFGr, Hfound0, Hfound1, DCORIFGw, MotorIn0, MotorIn1, 
Home_Encoder0, Home_Encoder1, sense0, sense1, Sclk, DCOR1THRESLOWr, Tfound0, Tfound1, outDATA, inDATA, Channel0, Channel1
);
  output Zero0;
  output Zero1;
  input DCORENCCTLw;
  input DCOR0THRESLOWr;
  input DCOR0THRESHIGHr;
  input Reset;
  input DCOR1THRESHIGHr;
  input DCORIFGr;
  output Hfound0;
  output Hfound1;
  input DCORIFGw;
  input MotorIn0;
  input MotorIn1;
  input Home_Encoder0;
  input Home_Encoder1;
  output sense0;
  output sense1;
  input Sclk;
  input DCOR1THRESLOWr;
  output Tfound0;
  output Tfound1;
  output [7 : 0] outDATA;
  input [7 : 0] inDATA;
  input [15 : 0] Channel0;
  input [15 : 0] Channel1;
  wire E0r_1072;
  wire E0r_0_not0000;
  wire E0r__and0000;
  wire E0r__and00001_1075;
  wire E0r__or0000;
  wire E1r_1077;
  wire E1r__and0000;
  wire E1r__and00001_1079;
  wire HE0statelastr_1080;
  wire HE0stater_1081;
  wire HE1statelastr_1082;
  wire HE1stater_1083;
  wire NlwRenamedSig_OI_Hfound0;
  wire Hfound0r__and0000;
  wire Hfound0r__and00001;
  wire Hfound0r__and000011_1087;
  wire Hfound0r__and000012_1088;
  wire Hfound0r__and000013_1089;
  wire Hfound0r__and000014_1090;
  wire Hfound0r__or0000;
  wire Hfound0r__or00001;
  wire Hfound0r__or000011_1093;
  wire Hfound0r__or00002;
  wire Hfound0r__or000021_1095;
  wire Hfound0r__or000022_1096;
  wire Hfound0r__or000023_1097;
  wire Hfound0r__or000024_1098;
  wire Hfound0r__or00003;
  wire Hfound0r__or000031_1100;
  wire Hfound0r__or00004;
  wire Hfound0r__or000041_1102;
  wire Hfound0r__or0000_bdd0;
  wire Hfound0r__or0000_bdd2;
  wire Hfound0r__or0000_bdd3;
  wire NlwRenamedSig_OI_Hfound1;
  wire Hfound1r__and0000;
  wire Hfound1r__and00001;
  wire Hfound1r__and000011_1109;
  wire Hfound1r__and000012_1110;
  wire Hfound1r__and000013_1111;
  wire Hfound1r__and000014_1112;
  wire Hfound1r__or0000;
  wire Hfound1r__or00001;
  wire Hfound1r__or000011_1115;
  wire Hfound1r__or00002;
  wire Hfound1r__or000021_1117;
  wire Hfound1r__or000022_1118;
  wire Hfound1r__or000023_1119;
  wire Hfound1r__or000024_1120;
  wire Hfound1r__or00003;
  wire Hfound1r__or000031_1122;
  wire Hfound1r__or00004;
  wire Hfound1r__or000041_1124;
  wire Hfound1r__or0000_bdd0;
  wire Hfound1r__or0000_bdd2;
  wire Hfound1r__or0000_bdd3;
  wire InEdge0r_1130;
  wire InEdge1r_1131;
  wire LastEdge0r_1132;
  wire LastEdge1r_1133;
  wire Latch0r_0__and0000;
  wire Latch0r_0__and00001_1136;
  wire Latch0r_0__or0000;
  wire Latch0r_10__and0000;
  wire Latch0r_10__and00001_1141;
  wire Latch0r_11__and0000;
  wire Latch0r_11__and00001_1144;
  wire Latch0r_12__and0000;
  wire Latch0r_12__and00001_1147;
  wire Latch0r_13__and0000;
  wire Latch0r_13__and00001_1150;
  wire Latch0r_14__and0000;
  wire Latch0r_14__and00001_1153;
  wire Latch0r_15__and0000;
  wire Latch0r_15__and00001_1156;
  wire Latch0r_1__and0000;
  wire Latch0r_1__and00001_1158;
  wire Latch0r_2__and0000;
  wire Latch0r_2__and00001_1161;
  wire Latch0r_3__and0000;
  wire Latch0r_3__and00001_1164;
  wire Latch0r_4__and0000;
  wire Latch0r_4__and00001_1167;
  wire Latch0r_5__and0000;
  wire Latch0r_5__and00001_1170;
  wire Latch0r_6__and0000;
  wire Latch0r_6__and00001_1173;
  wire Latch0r_7__and0000;
  wire Latch0r_7__and00001_1176;
  wire Latch0r_8__and0000;
  wire Latch0r_8__and00001_1179;
  wire Latch0r_9__and0000;
  wire Latch0r_9__and00001_1182;
  wire Latch1r_0__and0000;
  wire Latch1r_0__and00001_1185;
  wire Latch1r_0__or0000;
  wire Latch1r_10__and0000;
  wire Latch1r_10__and00001_1190;
  wire Latch1r_11__and0000;
  wire Latch1r_11__and00001_1193;
  wire Latch1r_12__and0000;
  wire Latch1r_12__and00001_1196;
  wire Latch1r_13__and0000;
  wire Latch1r_13__and00001_1199;
  wire Latch1r_14__and0000;
  wire Latch1r_14__and00001_1202;
  wire Latch1r_15__and0000;
  wire Latch1r_15__and00001_1205;
  wire Latch1r_1__and0000;
  wire Latch1r_1__and00001_1207;
  wire Latch1r_2__and0000;
  wire Latch1r_2__and00001_1210;
  wire Latch1r_3__and0000;
  wire Latch1r_3__and00001_1213;
  wire Latch1r_4__and0000;
  wire Latch1r_4__and00001_1216;
  wire Latch1r_5__and0000;
  wire Latch1r_5__and00001_1219;
  wire Latch1r_6__and0000;
  wire Latch1r_6__and00001_1222;
  wire Latch1r_7__and0000;
  wire Latch1r_7__and00001_1225;
  wire Latch1r_8__and0000;
  wire Latch1r_8__and00001_1228;
  wire Latch1r_9__and0000;
  wire Latch1r_9__and00001_1231;
  wire LatchEdge0r_1232;
  wire LatchEdge0r__and0000;
  wire LatchEdge0r__and00001_1234;
  wire LatchEdge1r_1235;
  wire LatchEdge1r__and0000;
  wire LatchEdge1r__and00001_1237;
  wire RF0r_1240;
  wire RF0r__and0000;
  wire RF0r__and00001_1242;
  wire RF1r_1243;
  wire RF1r__and0000;
  wire RF1r__and00001_1245;
  wire SFDecomp_40;
  wire SFDecomp_401_1248;
  wire SFDecomp_402_1249;
  wire SFDecomp_403_1250;
  wire SFDecomp_42;
  wire SFDecomp_421_1252;
  wire SFDecomp_422_1253;
  wire SFDecomp_423_1254;
  wire SFDecomp_43;
  wire SFDecomp_431_1256;
  wire SFDecomp_432_1257;
  wire SFDecomp_433_1258;
  wire SFDecomp_45;
  wire SFDecomp_451_1260;
  wire SFDecomp_452_1261;
  wire SFDecomp_453_1262;
  wire SFDecomp_46;
  wire SFDecomp_461_1264;
  wire SFDecomp_462_1265;
  wire SFDecomp_463_1266;
  wire SFDecomp_48;
  wire SFDecomp_481_1268;
  wire SFDecomp_482_1269;
  wire SFDecomp_483_1270;
  wire SFDecomp_49;
  wire SFDecomp_491_1272;
  wire SFDecomp_492_1273;
  wire SFDecomp_493_1274;
  wire SFDecomp_51;
  wire SFDecomp_511_1276;
  wire SFDecomp_512_1277;
  wire SFDecomp_513_1278;
  wire SFDecomp_53;
  wire SFDecomp_531_1280;
  wire SFDecomp_532_1281;
  wire SFDecomp_533_1282;
  wire SFDecomp_54;
  wire SFDecomp_57;
  wire SFDecomp_571_1285;
  wire SFDecomp_572_1286;
  wire SFDecomp_59;
  wire SFDecomp_591_1288;
  wire SFDecomp_592_1289;
  wire SFDecomp_593_1290;
  wire SFDecomp_60;
  wire SFDecomp_63;
  wire SFDecomp_631_1293;
  wire SFDecomp_632_1294;
  wire SFDecomp_65;
  wire SFDecomp_651_1296;
  wire SFDecomp_652_1297;
  wire SFDecomp_653_1298;
  wire SFDecomp_66;
  wire SFDecomp_69;
  wire SFDecomp_691_1301;
  wire SFDecomp_692_1302;
  wire SFDecomp_71;
  wire SFDecomp_711_1304;
  wire SFDecomp_712_1305;
  wire SFDecomp_713_1306;
  wire SFDecomp_72;
  wire SFDecomp_75;
  wire SFDecomp_751_1309;
  wire SFDecomp_752_1310;
  wire SFDecomp_76;
  wire SFDecomp_761_1312;
  wire SFDecomp_77;
  wire SFDecomp_771_1314;
  wire SFDecomp_80;
  wire SFDecomp_801_1316;
  wire SFDecomp_802_1317;
  wire SFDecomp_803_1318;
  wire SFDecomp_83;
  wire SFDecomp_831_1320;
  wire SFDecomp_832_1321;
  wire SFDecomp_833_1322;
  wire NlwRenamedSig_OI_Tfound0;
  wire Tfound0r_and0000;
  wire Tfound0r_and00001_1326;
  wire Tfound0r_and00002_1327;
  wire Tfound0r_and00003_1328;
  wire Tfound0r_mux0000;
  wire Tfound0r_mux00001;
  wire Tfound0r_mux000011_1331;
  wire Tfound0r_mux000012_1332;
  wire Tfound0r_not0001;
  wire Tfound0r_or0000;
  wire NlwRenamedSig_OI_Tfound1;
  wire Tfound1r_and0000;
  wire Tfound1r_and00001_1337;
  wire Tfound1r_and00002_1338;
  wire Tfound1r_and00003_1339;
  wire Tfound1r_mux0000;
  wire Tfound1r_mux00001;
  wire Tfound1r_mux000011_1342;
  wire Tfound1r_mux000012_1343;
  wire Tfound1r_not0001;
  wire Tfound1r_or0000;
  wire NlwRenamedSig_OI_Zero1;
  wire latchitH0_1355;
  wire latchitH0__and0000;
  wire latchitH0__and00001;
  wire latchitH0__and000011_1358;
  wire latchitH0__and000012_1359;
  wire latchitH0__and000013_1360;
  wire latchitH0__or0000;
  wire latchitH0__or00001;
  wire latchitH0__or000011_1363;
  wire latchitH0__or000012_1364;
  wire latchitH1_1365;
  wire latchitH1__and0000;
  wire latchitH1__and00001;
  wire latchitH1__and000011_1368;
  wire latchitH1__and000012_1369;
  wire latchitH1__and000013_1370;
  wire latchitL0_1371;
  wire latchitL0__and0000;
  wire latchitL0__and00001_1373;
  wire latchitL0__and00002_1374;
  wire latchitL0_cmp_eq0000;
  wire latchitL0_cmp_eq00001_1376;
  wire latchitL0_cmp_eq00002_1377;
  wire latchitL0_cmp_eq00003_1378;
  wire latchitL0_cmp_eq00004_1379;
  wire latchitL0_cmp_eq0001;
  wire latchitL0_cmp_eq00011_1381;
  wire latchitL0_cmp_eq00012_1382;
  wire latchitL0_cmp_eq00013_1383;
  wire latchitL1_1384;
  wire latchitL1__and0000;
  wire latchitL1__and00001_1386;
  wire latchitL1__and00002_1387;
  wire latchitL1_cmp_eq0000;
  wire latchitL1_cmp_eq00001_1389;
  wire latchitL1_cmp_eq00002_1390;
  wire latchitL1_cmp_eq00003_1391;
  wire latchitL1_cmp_eq00004_1392;
  wire latchitL1_cmp_eq0001;
  wire latchitL1_cmp_eq00011_1394;
  wire latchitL1_cmp_eq00012_1395;
  wire latchitL1_cmp_eq00013_1396;
  wire \outDATA<6>_not0000 ;
  wire \outDATA<6>_not0000_bdd0 ;
  wire \outDATA<7>_not0000 ;
  wire \outDATA<7>_not00001 ;
  wire \outDATA<7>_not000011_1409 ;
  wire outDATA_0_mux0000;
  wire outDATA_0_mux00001;
  wire outDATA_0_mux000011_1412;
  wire outDATA_0_mux000012_1413;
  wire outDATA_1_mux0000;
  wire outDATA_1_mux00001;
  wire outDATA_1_mux000011_1416;
  wire outDATA_1_mux000012_1417;
  wire outDATA_2_mux0000;
  wire outDATA_2_mux00001;
  wire outDATA_2_mux000011_1420;
  wire outDATA_2_mux000012_1421;
  wire outDATA_2_mux00002;
  wire outDATA_2_mux000021_1423;
  wire outDATA_2_mux000022_1424;
  wire outDATA_2_mux0000_bdd0;
  wire outDATA_3_mux0000;
  wire outDATA_3_mux00001;
  wire outDATA_3_mux000011_1428;
  wire outDATA_3_mux000012_1429;
  wire outDATA_3_mux00002;
  wire outDATA_3_mux000021_1431;
  wire outDATA_3_mux000022_1432;
  wire outDATA_3_mux0000_bdd0;
  wire outDATA_4_mux0000;
  wire outDATA_4_mux00001;
  wire outDATA_4_mux000011_1436;
  wire outDATA_4_mux000012_1437;
  wire outDATA_5_mux0000;
  wire outDATA_5_mux00001;
  wire outDATA_5_mux000011_1440;
  wire outDATA_5_mux000012_1441;
  wire outDATA_5_mux00002;
  wire outDATA_5_mux000021_1443;
  wire outDATA_5_mux000022_1444;
  wire outDATA_5_mux0000_bdd0;
  wire outDATA_6_mux0000;
  wire outDATA_6_mux00001;
  wire outDATA_6_mux000011_1448;
  wire outDATA_6_mux000012_1449;
  wire outDATA_6_mux00002;
  wire outDATA_6_mux000021_1451;
  wire outDATA_6_mux000022_1452;
  wire outDATA_6_mux0000_bdd0;
  wire outDATA_7_mux0000;
  wire outDATA_7_mux00001;
  wire outDATA_7_mux000011_1456;
  wire outDATA_7_mux000012_1457;
  wire sense0r__and0000;
  wire sense0r__and00001_1460;
  wire sense1r__and0000;
  wire sense1r__and00001_1463;
  wire [15 : 0] Latch0r;
  wire [15 : 0] Latch1r;
  assign
    Zero0 = NlwRenamedSig_OI_Zero1,
    Zero1 = NlwRenamedSig_OI_Zero1,
    Hfound0 = NlwRenamedSig_OI_Hfound0,
    Hfound1 = NlwRenamedSig_OI_Hfound1,
    Tfound0 = NlwRenamedSig_OI_Tfound0,
    Tfound1 = NlwRenamedSig_OI_Tfound1;
  GND   XST_GND (
    .G(NlwRenamedSig_OI_Zero1)
  );
  BUFE   \outDATA<0>_0  (
    .I(outDATA_0_mux0000),
    .E(\outDATA<7>_not0000 ),
    .O(outDATA[0])
  );
  BUFE   \outDATA<1>_0  (
    .I(outDATA_1_mux0000),
    .E(\outDATA<7>_not0000 ),
    .O(outDATA[1])
  );
  BUFE   \outDATA<2>_0  (
    .I(outDATA_2_mux0000),
    .E(\outDATA<6>_not0000 ),
    .O(outDATA[2])
  );
  BUFE   \outDATA<3>_0  (
    .I(outDATA_3_mux0000),
    .E(\outDATA<6>_not0000 ),
    .O(outDATA[3])
  );
  BUFE   \outDATA<4>_0  (
    .I(outDATA_4_mux0000),
    .E(\outDATA<7>_not0000 ),
    .O(outDATA[4])
  );
  BUFE   \outDATA<5>_0  (
    .I(outDATA_5_mux0000),
    .E(\outDATA<6>_not0000 ),
    .O(outDATA[5])
  );
  BUFE   \outDATA<6>_0  (
    .I(outDATA_6_mux0000),
    .E(\outDATA<6>_not0000 ),
    .O(outDATA[6])
  );
  BUFE   \outDATA<7>_0  (
    .I(outDATA_7_mux0000),
    .E(\outDATA<7>_not0000 ),
    .O(outDATA[7])
  );
  FDCE   latchitH0 (
    .CE(latchitH0__or0000),
    .CLR(NlwRenamedSig_OI_Zero1),
    .C(E0r_0_not0000),
    .D(latchitH0__and0000),
    .Q(latchitH0_1355)
  );
  FDCE   latchitH1 (
    .CE(latchitH0__or0000),
    .CLR(NlwRenamedSig_OI_Zero1),
    .C(E0r_0_not0000),
    .D(latchitH1__and0000),
    .Q(latchitH1_1365)
  );
  FDCE   latchitL0 (
    .CE(latchitH0__or0000),
    .CLR(NlwRenamedSig_OI_Zero1),
    .C(E0r_0_not0000),
    .D(latchitL0__and0000),
    .Q(latchitL0_1371)
  );
  FDCE   latchitL1 (
    .CE(latchitH0__or0000),
    .CLR(NlwRenamedSig_OI_Zero1),
    .C(E0r_0_not0000),
    .D(latchitL1__and0000),
    .Q(latchitL1_1384)
  );
  FDCE   Latch0r_0 (
    .CE(Latch0r_0__or0000),
    .CLR(NlwRenamedSig_OI_Zero1),
    .C(E0r_0_not0000),
    .D(Latch0r_0__and0000),
    .Q(Latch0r[0])
  );
  FDCE   Latch0r_1 (
    .CE(Latch0r_0__or0000),
    .CLR(NlwRenamedSig_OI_Zero1),
    .C(E0r_0_not0000),
    .D(Latch0r_1__and0000),
    .Q(Latch0r[1])
  );
  FDCE   Latch0r_2 (
    .CE(Latch0r_0__or0000),
    .CLR(NlwRenamedSig_OI_Zero1),
    .C(E0r_0_not0000),
    .D(Latch0r_2__and0000),
    .Q(Latch0r[2])
  );
  FDCE   Latch0r_3 (
    .CE(Latch0r_0__or0000),
    .CLR(NlwRenamedSig_OI_Zero1),
    .C(E0r_0_not0000),
    .D(Latch0r_3__and0000),
    .Q(Latch0r[3])
  );
  FDCE   Latch0r_4 (
    .CE(Latch0r_0__or0000),
    .CLR(NlwRenamedSig_OI_Zero1),
    .C(E0r_0_not0000),
    .D(Latch0r_4__and0000),
    .Q(Latch0r[4])
  );
  FDCE   Latch0r_5 (
    .CE(Latch0r_0__or0000),
    .CLR(NlwRenamedSig_OI_Zero1),
    .C(E0r_0_not0000),
    .D(Latch0r_5__and0000),
    .Q(Latch0r[5])
  );
  FDCE   Latch0r_6 (
    .CE(Latch0r_0__or0000),
    .CLR(NlwRenamedSig_OI_Zero1),
    .C(E0r_0_not0000),
    .D(Latch0r_6__and0000),
    .Q(Latch0r[6])
  );
  FDCE   Latch0r_7 (
    .CE(Latch0r_0__or0000),
    .CLR(NlwRenamedSig_OI_Zero1),
    .C(E0r_0_not0000),
    .D(Latch0r_7__and0000),
    .Q(Latch0r[7])
  );
  FDCE   Latch0r_8 (
    .CE(Latch0r_0__or0000),
    .CLR(NlwRenamedSig_OI_Zero1),
    .C(E0r_0_not0000),
    .D(Latch0r_8__and0000),
    .Q(Latch0r[8])
  );
  FDCE   Latch0r_9 (
    .CE(Latch0r_0__or0000),
    .CLR(NlwRenamedSig_OI_Zero1),
    .C(E0r_0_not0000),
    .D(Latch0r_9__and0000),
    .Q(Latch0r[9])
  );
  FDCE   Latch0r_10 (
    .CE(Latch0r_0__or0000),
    .CLR(NlwRenamedSig_OI_Zero1),
    .C(E0r_0_not0000),
    .D(Latch0r_10__and0000),
    .Q(Latch0r[10])
  );
  FDCE   Latch0r_11 (
    .CE(Latch0r_0__or0000),
    .CLR(NlwRenamedSig_OI_Zero1),
    .C(E0r_0_not0000),
    .D(Latch0r_11__and0000),
    .Q(Latch0r[11])
  );
  FDCE   Latch0r_12 (
    .CE(Latch0r_0__or0000),
    .CLR(NlwRenamedSig_OI_Zero1),
    .C(E0r_0_not0000),
    .D(Latch0r_12__and0000),
    .Q(Latch0r[12])
  );
  FDCE   Latch0r_13 (
    .CE(Latch0r_0__or0000),
    .CLR(NlwRenamedSig_OI_Zero1),
    .C(E0r_0_not0000),
    .D(Latch0r_13__and0000),
    .Q(Latch0r[13])
  );
  FDCE   Latch0r_14 (
    .CE(Latch0r_0__or0000),
    .CLR(NlwRenamedSig_OI_Zero1),
    .C(E0r_0_not0000),
    .D(Latch0r_14__and0000),
    .Q(Latch0r[14])
  );
  FDCE   Latch0r_15 (
    .CE(Latch0r_0__or0000),
    .CLR(NlwRenamedSig_OI_Zero1),
    .C(E0r_0_not0000),
    .D(Latch0r_15__and0000),
    .Q(Latch0r[15])
  );
  FDCE   Latch1r_0 (
    .CE(Latch1r_0__or0000),
    .CLR(NlwRenamedSig_OI_Zero1),
    .C(E0r_0_not0000),
    .D(Latch1r_0__and0000),
    .Q(Latch1r[0])
  );
  FDCE   Latch1r_1 (
    .CE(Latch1r_0__or0000),
    .CLR(NlwRenamedSig_OI_Zero1),
    .C(E0r_0_not0000),
    .D(Latch1r_1__and0000),
    .Q(Latch1r[1])
  );
  FDCE   Latch1r_2 (
    .CE(Latch1r_0__or0000),
    .CLR(NlwRenamedSig_OI_Zero1),
    .C(E0r_0_not0000),
    .D(Latch1r_2__and0000),
    .Q(Latch1r[2])
  );
  FDCE   Latch1r_3 (
    .CE(Latch1r_0__or0000),
    .CLR(NlwRenamedSig_OI_Zero1),
    .C(E0r_0_not0000),
    .D(Latch1r_3__and0000),
    .Q(Latch1r[3])
  );
  FDCE   Latch1r_4 (
    .CE(Latch1r_0__or0000),
    .CLR(NlwRenamedSig_OI_Zero1),
    .C(E0r_0_not0000),
    .D(Latch1r_4__and0000),
    .Q(Latch1r[4])
  );
  FDCE   Latch1r_5 (
    .CE(Latch1r_0__or0000),
    .CLR(NlwRenamedSig_OI_Zero1),
    .C(E0r_0_not0000),
    .D(Latch1r_5__and0000),
    .Q(Latch1r[5])
  );
  FDCE   Latch1r_6 (
    .CE(Latch1r_0__or0000),
    .CLR(NlwRenamedSig_OI_Zero1),
    .C(E0r_0_not0000),
    .D(Latch1r_6__and0000),
    .Q(Latch1r[6])
  );
  FDCE   Latch1r_7 (
    .CE(Latch1r_0__or0000),
    .CLR(NlwRenamedSig_OI_Zero1),
    .C(E0r_0_not0000),
    .D(Latch1r_7__and0000),
    .Q(Latch1r[7])
  );
  FDCE   Latch1r_8 (
    .CE(Latch1r_0__or0000),
    .CLR(NlwRenamedSig_OI_Zero1),
    .C(E0r_0_not0000),
    .D(Latch1r_8__and0000),
    .Q(Latch1r[8])
  );
  FDCE   Latch1r_9 (
    .CE(Latch1r_0__or0000),
    .CLR(NlwRenamedSig_OI_Zero1),
    .C(E0r_0_not0000),
    .D(Latch1r_9__and0000),
    .Q(Latch1r[9])
  );
  FDCE   Latch1r_10 (
    .CE(Latch1r_0__or0000),
    .CLR(NlwRenamedSig_OI_Zero1),
    .C(E0r_0_not0000),
    .D(Latch1r_10__and0000),
    .Q(Latch1r[10])
  );
  FDCE   Latch1r_11 (
    .CE(Latch1r_0__or0000),
    .CLR(NlwRenamedSig_OI_Zero1),
    .C(E0r_0_not0000),
    .D(Latch1r_11__and0000),
    .Q(Latch1r[11])
  );
  FDCE   Latch1r_12 (
    .CE(Latch1r_0__or0000),
    .CLR(NlwRenamedSig_OI_Zero1),
    .C(E0r_0_not0000),
    .D(Latch1r_12__and0000),
    .Q(Latch1r[12])
  );
  FDCE   Latch1r_13 (
    .CE(Latch1r_0__or0000),
    .CLR(NlwRenamedSig_OI_Zero1),
    .C(E0r_0_not0000),
    .D(Latch1r_13__and0000),
    .Q(Latch1r[13])
  );
  FDCE   Latch1r_14 (
    .CE(Latch1r_0__or0000),
    .CLR(NlwRenamedSig_OI_Zero1),
    .C(E0r_0_not0000),
    .D(Latch1r_14__and0000),
    .Q(Latch1r[14])
  );
  FDCE   Latch1r_15 (
    .CE(Latch1r_0__or0000),
    .CLR(NlwRenamedSig_OI_Zero1),
    .C(E0r_0_not0000),
    .D(Latch1r_15__and0000),
    .Q(Latch1r[15])
  );
  FDCE   RF0r (
    .CE(E0r__or0000),
    .CLR(NlwRenamedSig_OI_Zero1),
    .C(E0r_0_not0000),
    .D(RF0r__and0000),
    .Q(RF0r_1240)
  );
  FDCE   E0r (
    .CE(E0r__or0000),
    .CLR(NlwRenamedSig_OI_Zero1),
    .C(E0r_0_not0000),
    .D(E0r__and0000),
    .Q(E0r_1072)
  );
  FDCE   LatchEdge0r (
    .CE(E0r__or0000),
    .CLR(NlwRenamedSig_OI_Zero1),
    .C(E0r_0_not0000),
    .D(LatchEdge0r__and0000),
    .Q(LatchEdge0r_1232)
  );
  FDCE   sense0r (
    .CE(E0r__or0000),
    .CLR(NlwRenamedSig_OI_Zero1),
    .C(E0r_0_not0000),
    .D(sense0r__and0000),
    .Q(sense0)
  );
  FDCE   RF1r (
    .CE(E0r__or0000),
    .CLR(NlwRenamedSig_OI_Zero1),
    .C(E0r_0_not0000),
    .D(RF1r__and0000),
    .Q(RF1r_1243)
  );
  FDCE   E1r (
    .CE(E0r__or0000),
    .CLR(NlwRenamedSig_OI_Zero1),
    .C(E0r_0_not0000),
    .D(E1r__and0000),
    .Q(E1r_1077)
  );
  FDCE   LatchEdge1r (
    .CE(E0r__or0000),
    .CLR(NlwRenamedSig_OI_Zero1),
    .C(E0r_0_not0000),
    .D(LatchEdge1r__and0000),
    .Q(LatchEdge1r_1235)
  );
  FDCE   sense1r (
    .CE(E0r__or0000),
    .CLR(NlwRenamedSig_OI_Zero1),
    .C(E0r_0_not0000),
    .D(sense1r__and0000),
    .Q(sense1)
  );
  FDCE   Hfound0r (
    .CE(Hfound0r__or0000),
    .CLR(NlwRenamedSig_OI_Zero1),
    .C(E0r_0_not0000),
    .D(Hfound0r__and0000),
    .Q(NlwRenamedSig_OI_Hfound0)
  );
  FDCE   Hfound1r (
    .CE(Hfound1r__or0000),
    .CLR(NlwRenamedSig_OI_Zero1),
    .C(E0r_0_not0000),
    .D(Hfound1r__and0000),
    .Q(NlwRenamedSig_OI_Hfound1)
  );
  FD   LastEdge1r (
    .C(E0r_0_not0000),
    .D(InEdge1r_1131),
    .Q(LastEdge1r_1133)
  );
  FD   LastEdge0r (
    .C(E0r_0_not0000),
    .D(InEdge0r_1130),
    .Q(LastEdge0r_1132)
  );
  FD   InEdge1r (
    .C(E0r_0_not0000),
    .D(MotorIn1),
    .Q(InEdge1r_1131)
  );
  FD   InEdge0r (
    .C(E0r_0_not0000),
    .D(MotorIn0),
    .Q(InEdge0r_1130)
  );
  FD   HE1statelastr (
    .C(E0r_0_not0000),
    .D(HE1stater_1083),
    .Q(HE1statelastr_1082)
  );
  FD   HE1stater (
    .C(E0r_0_not0000),
    .D(Home_Encoder1),
    .Q(HE1stater_1083)
  );
  FD   HE0statelastr (
    .C(E0r_0_not0000),
    .D(HE0stater_1081),
    .Q(HE0statelastr_1080)
  );
  FD   HE0stater (
    .C(E0r_0_not0000),
    .D(Home_Encoder0),
    .Q(HE0stater_1081)
  );
  FDCE   Tfound1r (
    .CE(Tfound1r_not0001),
    .CLR(NlwRenamedSig_OI_Zero1),
    .C(E0r_0_not0000),
    .D(Tfound1r_mux0000),
    .Q(NlwRenamedSig_OI_Tfound1)
  );
  FDCE   Tfound0r (
    .CE(Tfound0r_not0001),
    .CLR(NlwRenamedSig_OI_Zero1),
    .C(E0r_0_not0000),
    .D(Tfound0r_mux0000),
    .Q(NlwRenamedSig_OI_Tfound0)
  );
  INV   sense1r__and00001 (
    .I(Reset),
    .O(sense1r__and00001_1463)
  );
  AND2   sense1r__and00002 (
    .I0(inDATA[7]),
    .I1(sense1r__and00001_1463),
    .O(sense1r__and0000)
  );
  INV   LatchEdge1r__and00001 (
    .I(Reset),
    .O(LatchEdge1r__and00001_1237)
  );
  AND2   LatchEdge1r__and00002 (
    .I0(inDATA[6]),
    .I1(LatchEdge1r__and00001_1237),
    .O(LatchEdge1r__and0000)
  );
  INV   E1r__and00001 (
    .I(Reset),
    .O(E1r__and00001_1079)
  );
  AND2   E1r__and00002 (
    .I0(inDATA[5]),
    .I1(E1r__and00001_1079),
    .O(E1r__and0000)
  );
  INV   RF1r__and00001 (
    .I(Reset),
    .O(RF1r__and00001_1245)
  );
  AND2   RF1r__and00002 (
    .I0(inDATA[4]),
    .I1(RF1r__and00001_1245),
    .O(RF1r__and0000)
  );
  INV   sense0r__and00001 (
    .I(Reset),
    .O(sense0r__and00001_1460)
  );
  AND2   sense0r__and00002 (
    .I0(inDATA[3]),
    .I1(sense0r__and00001_1460),
    .O(sense0r__and0000)
  );
  INV   LatchEdge0r__and00001 (
    .I(Reset),
    .O(LatchEdge0r__and00001_1234)
  );
  AND2   LatchEdge0r__and00002 (
    .I0(inDATA[2]),
    .I1(LatchEdge0r__and00001_1234),
    .O(LatchEdge0r__and0000)
  );
  INV   E0r_0_not00001 (
    .I(Sclk),
    .O(E0r_0_not0000)
  );
  OR2   E0r__or00001 (
    .I0(DCORENCCTLw),
    .I1(Reset),
    .O(E0r__or0000)
  );
  INV   E0r__and00001 (
    .I(Reset),
    .O(E0r__and00001_1075)
  );
  AND2   E0r__and00002 (
    .I0(inDATA[1]),
    .I1(E0r__and00001_1075),
    .O(E0r__and0000)
  );
  INV   RF0r__and00001 (
    .I(Reset),
    .O(RF0r__and00001_1242)
  );
  AND2   RF0r__and00002 (
    .I0(inDATA[0]),
    .I1(RF0r__and00001_1242),
    .O(RF0r__and0000)
  );
  INV   Latch1r_0__and00001 (
    .I(Reset),
    .O(Latch1r_0__and00001_1185)
  );
  AND2   Latch1r_0__and00002 (
    .I0(Channel1[0]),
    .I1(Latch1r_0__and00001_1185),
    .O(Latch1r_0__and0000)
  );
  INV   Latch1r_1__and00001 (
    .I(Reset),
    .O(Latch1r_1__and00001_1207)
  );
  AND2   Latch1r_1__and00002 (
    .I0(Channel1[1]),
    .I1(Latch1r_1__and00001_1207),
    .O(Latch1r_1__and0000)
  );
  INV   Latch1r_2__and00001 (
    .I(Reset),
    .O(Latch1r_2__and00001_1210)
  );
  AND2   Latch1r_2__and00002 (
    .I0(Channel1[2]),
    .I1(Latch1r_2__and00001_1210),
    .O(Latch1r_2__and0000)
  );
  INV   Latch1r_3__and00001 (
    .I(Reset),
    .O(Latch1r_3__and00001_1213)
  );
  AND2   Latch1r_3__and00002 (
    .I0(Channel1[3]),
    .I1(Latch1r_3__and00001_1213),
    .O(Latch1r_3__and0000)
  );
  INV   Latch1r_4__and00001 (
    .I(Reset),
    .O(Latch1r_4__and00001_1216)
  );
  AND2   Latch1r_4__and00002 (
    .I0(Channel1[4]),
    .I1(Latch1r_4__and00001_1216),
    .O(Latch1r_4__and0000)
  );
  INV   Latch1r_5__and00001 (
    .I(Reset),
    .O(Latch1r_5__and00001_1219)
  );
  AND2   Latch1r_5__and00002 (
    .I0(Channel1[5]),
    .I1(Latch1r_5__and00001_1219),
    .O(Latch1r_5__and0000)
  );
  INV   Latch1r_6__and00001 (
    .I(Reset),
    .O(Latch1r_6__and00001_1222)
  );
  AND2   Latch1r_6__and00002 (
    .I0(Channel1[6]),
    .I1(Latch1r_6__and00001_1222),
    .O(Latch1r_6__and0000)
  );
  INV   Latch1r_7__and00001 (
    .I(Reset),
    .O(Latch1r_7__and00001_1225)
  );
  AND2   Latch1r_7__and00002 (
    .I0(Channel1[7]),
    .I1(Latch1r_7__and00001_1225),
    .O(Latch1r_7__and0000)
  );
  INV   Latch1r_8__and00001 (
    .I(Reset),
    .O(Latch1r_8__and00001_1228)
  );
  AND2   Latch1r_8__and00002 (
    .I0(Channel1[8]),
    .I1(Latch1r_8__and00001_1228),
    .O(Latch1r_8__and0000)
  );
  INV   Latch1r_9__and00001 (
    .I(Reset),
    .O(Latch1r_9__and00001_1231)
  );
  AND2   Latch1r_9__and00002 (
    .I0(Channel1[9]),
    .I1(Latch1r_9__and00001_1231),
    .O(Latch1r_9__and0000)
  );
  INV   Latch1r_10__and00001 (
    .I(Reset),
    .O(Latch1r_10__and00001_1190)
  );
  AND2   Latch1r_10__and00002 (
    .I0(Channel1[10]),
    .I1(Latch1r_10__and00001_1190),
    .O(Latch1r_10__and0000)
  );
  INV   Latch1r_11__and00001 (
    .I(Reset),
    .O(Latch1r_11__and00001_1193)
  );
  AND2   Latch1r_11__and00002 (
    .I0(Channel1[11]),
    .I1(Latch1r_11__and00001_1193),
    .O(Latch1r_11__and0000)
  );
  INV   Latch1r_12__and00001 (
    .I(Reset),
    .O(Latch1r_12__and00001_1196)
  );
  AND2   Latch1r_12__and00002 (
    .I0(Channel1[12]),
    .I1(Latch1r_12__and00001_1196),
    .O(Latch1r_12__and0000)
  );
  INV   Latch1r_13__and00001 (
    .I(Reset),
    .O(Latch1r_13__and00001_1199)
  );
  AND2   Latch1r_13__and00002 (
    .I0(Channel1[13]),
    .I1(Latch1r_13__and00001_1199),
    .O(Latch1r_13__and0000)
  );
  INV   Latch1r_14__and00001 (
    .I(Reset),
    .O(Latch1r_14__and00001_1202)
  );
  AND2   Latch1r_14__and00002 (
    .I0(Channel1[14]),
    .I1(Latch1r_14__and00001_1202),
    .O(Latch1r_14__and0000)
  );
  INV   Latch1r_15__and00001 (
    .I(Reset),
    .O(Latch1r_15__and00001_1205)
  );
  AND2   Latch1r_15__and00002 (
    .I0(Channel1[15]),
    .I1(Latch1r_15__and00001_1205),
    .O(Latch1r_15__and0000)
  );
  INV   Latch0r_0__and00001 (
    .I(Reset),
    .O(Latch0r_0__and00001_1136)
  );
  AND2   Latch0r_0__and00002 (
    .I0(Channel0[0]),
    .I1(Latch0r_0__and00001_1136),
    .O(Latch0r_0__and0000)
  );
  INV   Latch0r_1__and00001 (
    .I(Reset),
    .O(Latch0r_1__and00001_1158)
  );
  AND2   Latch0r_1__and00002 (
    .I0(Channel0[1]),
    .I1(Latch0r_1__and00001_1158),
    .O(Latch0r_1__and0000)
  );
  INV   Latch0r_2__and00001 (
    .I(Reset),
    .O(Latch0r_2__and00001_1161)
  );
  AND2   Latch0r_2__and00002 (
    .I0(Channel0[2]),
    .I1(Latch0r_2__and00001_1161),
    .O(Latch0r_2__and0000)
  );
  INV   Latch0r_3__and00001 (
    .I(Reset),
    .O(Latch0r_3__and00001_1164)
  );
  AND2   Latch0r_3__and00002 (
    .I0(Channel0[3]),
    .I1(Latch0r_3__and00001_1164),
    .O(Latch0r_3__and0000)
  );
  INV   Latch0r_4__and00001 (
    .I(Reset),
    .O(Latch0r_4__and00001_1167)
  );
  AND2   Latch0r_4__and00002 (
    .I0(Channel0[4]),
    .I1(Latch0r_4__and00001_1167),
    .O(Latch0r_4__and0000)
  );
  INV   Latch0r_5__and00001 (
    .I(Reset),
    .O(Latch0r_5__and00001_1170)
  );
  AND2   Latch0r_5__and00002 (
    .I0(Channel0[5]),
    .I1(Latch0r_5__and00001_1170),
    .O(Latch0r_5__and0000)
  );
  INV   Latch0r_6__and00001 (
    .I(Reset),
    .O(Latch0r_6__and00001_1173)
  );
  AND2   Latch0r_6__and00002 (
    .I0(Channel0[6]),
    .I1(Latch0r_6__and00001_1173),
    .O(Latch0r_6__and0000)
  );
  INV   Latch0r_7__and00001 (
    .I(Reset),
    .O(Latch0r_7__and00001_1176)
  );
  AND2   Latch0r_7__and00002 (
    .I0(Channel0[7]),
    .I1(Latch0r_7__and00001_1176),
    .O(Latch0r_7__and0000)
  );
  INV   Latch0r_8__and00001 (
    .I(Reset),
    .O(Latch0r_8__and00001_1179)
  );
  AND2   Latch0r_8__and00002 (
    .I0(Channel0[8]),
    .I1(Latch0r_8__and00001_1179),
    .O(Latch0r_8__and0000)
  );
  INV   Latch0r_9__and00001 (
    .I(Reset),
    .O(Latch0r_9__and00001_1182)
  );
  AND2   Latch0r_9__and00002 (
    .I0(Channel0[9]),
    .I1(Latch0r_9__and00001_1182),
    .O(Latch0r_9__and0000)
  );
  INV   Latch0r_10__and00001 (
    .I(Reset),
    .O(Latch0r_10__and00001_1141)
  );
  AND2   Latch0r_10__and00002 (
    .I0(Channel0[10]),
    .I1(Latch0r_10__and00001_1141),
    .O(Latch0r_10__and0000)
  );
  INV   Latch0r_11__and00001 (
    .I(Reset),
    .O(Latch0r_11__and00001_1144)
  );
  AND2   Latch0r_11__and00002 (
    .I0(Channel0[11]),
    .I1(Latch0r_11__and00001_1144),
    .O(Latch0r_11__and0000)
  );
  INV   Latch0r_12__and00001 (
    .I(Reset),
    .O(Latch0r_12__and00001_1147)
  );
  AND2   Latch0r_12__and00002 (
    .I0(Channel0[12]),
    .I1(Latch0r_12__and00001_1147),
    .O(Latch0r_12__and0000)
  );
  INV   Latch0r_13__and00001 (
    .I(Reset),
    .O(Latch0r_13__and00001_1150)
  );
  AND2   Latch0r_13__and00002 (
    .I0(Channel0[13]),
    .I1(Latch0r_13__and00001_1150),
    .O(Latch0r_13__and0000)
  );
  INV   Latch0r_14__and00001 (
    .I(Reset),
    .O(Latch0r_14__and00001_1153)
  );
  AND2   Latch0r_14__and00002 (
    .I0(Channel0[14]),
    .I1(Latch0r_14__and00001_1153),
    .O(Latch0r_14__and0000)
  );
  INV   Latch0r_15__and00001 (
    .I(Reset),
    .O(Latch0r_15__and00001_1156)
  );
  AND2   Latch0r_15__and00002 (
    .I0(Channel0[15]),
    .I1(Latch0r_15__and00001_1156),
    .O(Latch0r_15__and0000)
  );
  INV   Tfound1r_mux000011 (
    .I(inDATA[6]),
    .O(Tfound1r_mux00001)
  );
  INV   Tfound1r_mux000012 (
    .I(DCORIFGw),
    .O(Tfound1r_mux000011_1342)
  );
  AND2   Tfound1r_mux000013 (
    .I0(NlwRenamedSig_OI_Tfound1),
    .I1(Tfound1r_mux00001),
    .O(Tfound1r_mux000012_1343)
  );
  OR2   Tfound1r_mux000014 (
    .I0(Tfound1r_mux000012_1343),
    .I1(Tfound1r_mux000011_1342),
    .O(Tfound1r_mux0000)
  );
  INV   Tfound0r_mux000011 (
    .I(inDATA[5]),
    .O(Tfound0r_mux00001)
  );
  INV   Tfound0r_mux000012 (
    .I(DCORIFGw),
    .O(Tfound0r_mux000011_1331)
  );
  AND2   Tfound0r_mux000013 (
    .I0(NlwRenamedSig_OI_Tfound0),
    .I1(Tfound0r_mux00001),
    .O(Tfound0r_mux000012_1332)
  );
  OR2   Tfound0r_mux000014 (
    .I0(Tfound0r_mux000012_1332),
    .I1(Tfound0r_mux000011_1331),
    .O(Tfound0r_mux0000)
  );
  INV   Hfound1r__and000011 (
    .I(inDATA[3]),
    .O(Hfound1r__and00001)
  );
  INV   Hfound1r__and000012 (
    .I(DCORIFGw),
    .O(Hfound1r__and000011_1109)
  );
  INV   Hfound1r__and000013 (
    .I(Reset),
    .O(Hfound1r__and000012_1110)
  );
  AND2   Hfound1r__and000014 (
    .I0(NlwRenamedSig_OI_Hfound1),
    .I1(Hfound1r__and00001),
    .O(Hfound1r__and000013_1111)
  );
  OR2   Hfound1r__and000015 (
    .I0(Hfound1r__and000013_1111),
    .I1(Hfound1r__and000011_1109),
    .O(Hfound1r__and000014_1112)
  );
  AND2   Hfound1r__and000016 (
    .I0(Hfound1r__and000014_1112),
    .I1(Hfound1r__and000012_1110),
    .O(Hfound1r__and0000)
  );
  INV   Hfound0r__and000011 (
    .I(inDATA[2]),
    .O(Hfound0r__and00001)
  );
  INV   Hfound0r__and000012 (
    .I(DCORIFGw),
    .O(Hfound0r__and000011_1087)
  );
  INV   Hfound0r__and000013 (
    .I(Reset),
    .O(Hfound0r__and000012_1088)
  );
  AND2   Hfound0r__and000014 (
    .I0(NlwRenamedSig_OI_Hfound0),
    .I1(Hfound0r__and00001),
    .O(Hfound0r__and000013_1089)
  );
  OR2   Hfound0r__and000015 (
    .I0(Hfound0r__and000013_1089),
    .I1(Hfound0r__and000011_1087),
    .O(Hfound0r__and000014_1090)
  );
  AND2   Hfound0r__and000016 (
    .I0(Hfound0r__and000014_1090),
    .I1(Hfound0r__and000012_1088),
    .O(Hfound0r__and0000)
  );
  OR3   Latch0r_0__or000011 (
    .I0(Reset),
    .I1(latchitH0_1355),
    .I2(latchitL0_1371),
    .O(Latch0r_0__or0000)
  );
  OR3   Latch1r_0__or000011 (
    .I0(Reset),
    .I1(latchitH1_1365),
    .I2(latchitL1_1384),
    .O(Latch1r_0__or0000)
  );
  INV   latchitH0__or000011 (
    .I(DCORIFGw),
    .O(latchitH0__or00001)
  );
  INV   latchitH0__or000012 (
    .I(DCORENCCTLw),
    .O(latchitH0__or000011_1363)
  );
  AND2   latchitH0__or000013 (
    .I0(latchitH0__or00001),
    .I1(latchitH0__or000011_1363),
    .O(latchitH0__or000012_1364)
  );
  OR2   latchitH0__or000014 (
    .I0(Reset),
    .I1(latchitH0__or000012_1364),
    .O(latchitH0__or0000)
  );
  AND2   outDATA_7_mux000011 (
    .I0(DCOR0THRESLOWr),
    .I1(Latch0r[7]),
    .O(outDATA_7_mux00001)
  );
  INV   outDATA_7_mux000012 (
    .I(DCOR0THRESLOWr),
    .O(outDATA_7_mux000011_1456)
  );
  AND2   outDATA_7_mux000013 (
    .I0(SFDecomp_42),
    .I1(outDATA_7_mux000011_1456),
    .O(outDATA_7_mux000012_1457)
  );
  OR2   outDATA_7_mux000014 (
    .I0(outDATA_7_mux00001),
    .I1(outDATA_7_mux000012_1457),
    .O(outDATA_7_mux0000)
  );
  AND2   outDATA_6_mux000021 (
    .I0(DCOR1THRESLOWr),
    .I1(Latch1r[6]),
    .O(outDATA_6_mux00002)
  );
  INV   outDATA_6_mux000022 (
    .I(DCOR1THRESLOWr),
    .O(outDATA_6_mux000021_1451)
  );
  AND2   outDATA_6_mux000023 (
    .I0(Latch1r[14]),
    .I1(outDATA_6_mux000021_1451),
    .O(outDATA_6_mux000022_1452)
  );
  OR2   outDATA_6_mux000024 (
    .I0(outDATA_6_mux00002),
    .I1(outDATA_6_mux000022_1452),
    .O(outDATA_6_mux0000_bdd0)
  );
  AND2   outDATA_6_mux000011 (
    .I0(DCOR0THRESLOWr),
    .I1(Latch0r[6]),
    .O(outDATA_6_mux00001)
  );
  INV   outDATA_6_mux000012 (
    .I(DCOR0THRESLOWr),
    .O(outDATA_6_mux000011_1448)
  );
  AND2   outDATA_6_mux000013 (
    .I0(SFDecomp_57),
    .I1(outDATA_6_mux000011_1448),
    .O(outDATA_6_mux000012_1449)
  );
  OR2   outDATA_6_mux000014 (
    .I0(outDATA_6_mux00001),
    .I1(outDATA_6_mux000012_1449),
    .O(outDATA_6_mux0000)
  );
  AND2   outDATA_5_mux000021 (
    .I0(DCOR1THRESLOWr),
    .I1(Latch1r[5]),
    .O(outDATA_5_mux00002)
  );
  INV   outDATA_5_mux000022 (
    .I(DCOR1THRESLOWr),
    .O(outDATA_5_mux000021_1443)
  );
  AND2   outDATA_5_mux000023 (
    .I0(Latch1r[13]),
    .I1(outDATA_5_mux000021_1443),
    .O(outDATA_5_mux000022_1444)
  );
  OR2   outDATA_5_mux000024 (
    .I0(outDATA_5_mux00002),
    .I1(outDATA_5_mux000022_1444),
    .O(outDATA_5_mux0000_bdd0)
  );
  AND2   outDATA_5_mux000011 (
    .I0(DCOR0THRESLOWr),
    .I1(Latch0r[5]),
    .O(outDATA_5_mux00001)
  );
  INV   outDATA_5_mux000012 (
    .I(DCOR0THRESLOWr),
    .O(outDATA_5_mux000011_1440)
  );
  AND2   outDATA_5_mux000013 (
    .I0(SFDecomp_63),
    .I1(outDATA_5_mux000011_1440),
    .O(outDATA_5_mux000012_1441)
  );
  OR2   outDATA_5_mux000014 (
    .I0(outDATA_5_mux00001),
    .I1(outDATA_5_mux000012_1441),
    .O(outDATA_5_mux0000)
  );
  AND2   outDATA_4_mux000011 (
    .I0(DCOR0THRESLOWr),
    .I1(Latch0r[4]),
    .O(outDATA_4_mux00001)
  );
  INV   outDATA_4_mux000012 (
    .I(DCOR0THRESLOWr),
    .O(outDATA_4_mux000011_1436)
  );
  AND2   outDATA_4_mux000013 (
    .I0(SFDecomp_45),
    .I1(outDATA_4_mux000011_1436),
    .O(outDATA_4_mux000012_1437)
  );
  OR2   outDATA_4_mux000014 (
    .I0(outDATA_4_mux00001),
    .I1(outDATA_4_mux000012_1437),
    .O(outDATA_4_mux0000)
  );
  AND2   outDATA_3_mux000021 (
    .I0(DCOR1THRESLOWr),
    .I1(Latch1r[3]),
    .O(outDATA_3_mux00002)
  );
  INV   outDATA_3_mux000022 (
    .I(DCOR1THRESLOWr),
    .O(outDATA_3_mux000021_1431)
  );
  AND2   outDATA_3_mux000023 (
    .I0(Latch1r[11]),
    .I1(outDATA_3_mux000021_1431),
    .O(outDATA_3_mux000022_1432)
  );
  OR2   outDATA_3_mux000024 (
    .I0(outDATA_3_mux00002),
    .I1(outDATA_3_mux000022_1432),
    .O(outDATA_3_mux0000_bdd0)
  );
  AND2   outDATA_3_mux000011 (
    .I0(DCOR0THRESLOWr),
    .I1(Latch0r[3]),
    .O(outDATA_3_mux00001)
  );
  INV   outDATA_3_mux000012 (
    .I(DCOR0THRESLOWr),
    .O(outDATA_3_mux000011_1428)
  );
  AND2   outDATA_3_mux000013 (
    .I0(SFDecomp_69),
    .I1(outDATA_3_mux000011_1428),
    .O(outDATA_3_mux000012_1429)
  );
  OR2   outDATA_3_mux000014 (
    .I0(outDATA_3_mux00001),
    .I1(outDATA_3_mux000012_1429),
    .O(outDATA_3_mux0000)
  );
  AND2   outDATA_2_mux000021 (
    .I0(DCOR1THRESLOWr),
    .I1(Latch1r[2]),
    .O(outDATA_2_mux00002)
  );
  INV   outDATA_2_mux000022 (
    .I(DCOR1THRESLOWr),
    .O(outDATA_2_mux000021_1423)
  );
  AND2   outDATA_2_mux000023 (
    .I0(Latch1r[10]),
    .I1(outDATA_2_mux000021_1423),
    .O(outDATA_2_mux000022_1424)
  );
  OR2   outDATA_2_mux000024 (
    .I0(outDATA_2_mux00002),
    .I1(outDATA_2_mux000022_1424),
    .O(outDATA_2_mux0000_bdd0)
  );
  AND2   outDATA_2_mux000011 (
    .I0(DCOR0THRESLOWr),
    .I1(Latch0r[2]),
    .O(outDATA_2_mux00001)
  );
  INV   outDATA_2_mux000012 (
    .I(DCOR0THRESLOWr),
    .O(outDATA_2_mux000011_1420)
  );
  AND2   outDATA_2_mux000013 (
    .I0(SFDecomp_75),
    .I1(outDATA_2_mux000011_1420),
    .O(outDATA_2_mux000012_1421)
  );
  OR2   outDATA_2_mux000014 (
    .I0(outDATA_2_mux00001),
    .I1(outDATA_2_mux000012_1421),
    .O(outDATA_2_mux0000)
  );
  AND2   outDATA_1_mux000011 (
    .I0(DCOR0THRESLOWr),
    .I1(Latch0r[1]),
    .O(outDATA_1_mux00001)
  );
  INV   outDATA_1_mux000012 (
    .I(DCOR0THRESLOWr),
    .O(outDATA_1_mux000011_1416)
  );
  AND2   outDATA_1_mux000013 (
    .I0(SFDecomp_48),
    .I1(outDATA_1_mux000011_1416),
    .O(outDATA_1_mux000012_1417)
  );
  OR2   outDATA_1_mux000014 (
    .I0(outDATA_1_mux00001),
    .I1(outDATA_1_mux000012_1417),
    .O(outDATA_1_mux0000)
  );
  AND2   outDATA_0_mux000011 (
    .I0(DCOR0THRESLOWr),
    .I1(Latch0r[0]),
    .O(outDATA_0_mux00001)
  );
  INV   outDATA_0_mux000012 (
    .I(DCOR0THRESLOWr),
    .O(outDATA_0_mux000011_1412)
  );
  AND2   outDATA_0_mux000013 (
    .I0(SFDecomp_51),
    .I1(outDATA_0_mux000011_1412),
    .O(outDATA_0_mux000012_1413)
  );
  OR2   outDATA_0_mux000014 (
    .I0(outDATA_0_mux00001),
    .I1(outDATA_0_mux000012_1413),
    .O(outDATA_0_mux0000)
  );
  OR2   latchitH0__and000011 (
    .I0(RF0r_1240),
    .I1(Hfound0r__or0000_bdd3),
    .O(latchitH0__and00001)
  );
  INV   latchitH0__and000012 (
    .I(RF0r_1240),
    .O(latchitH0__and000011_1358)
  );
  AND2   latchitH0__and000013 (
    .I0(SFDecomp_76),
    .I1(latchitH0__and00001),
    .O(latchitH0__and000012_1359)
  );
  OR2   latchitH0__and000014 (
    .I0(Hfound0r__or0000_bdd2),
    .I1(latchitH0__and000011_1358),
    .O(latchitH0__and000013_1360)
  );
  AND2   latchitH0__and000015 (
    .I0(latchitH0__and000012_1359),
    .I1(latchitH0__and000013_1360),
    .O(latchitH0__and0000)
  );
  INV   Hfound0r__or000041 (
    .I(HE0stater_1081),
    .O(Hfound0r__or00004)
  );
  INV   Hfound0r__or000042 (
    .I(NlwRenamedSig_OI_Hfound0),
    .O(Hfound0r__or000041_1102)
  );
  AND3   Hfound0r__or000043 (
    .I0(Hfound0r__or00004),
    .I1(HE0statelastr_1080),
    .I2(Hfound0r__or000041_1102),
    .O(Hfound0r__or0000_bdd3)
  );
  INV   Hfound0r__or000031 (
    .I(NlwRenamedSig_OI_Hfound0),
    .O(Hfound0r__or00003)
  );
  INV   Hfound0r__or000032 (
    .I(HE0statelastr_1080),
    .O(Hfound0r__or000031_1100)
  );
  AND3   Hfound0r__or000033 (
    .I0(Hfound0r__or00003),
    .I1(HE0stater_1081),
    .I2(Hfound0r__or000031_1100),
    .O(Hfound0r__or0000_bdd2)
  );
  OR2   Hfound0r__or000021 (
    .I0(DCORIFGw),
    .I1(Hfound0r__or0000_bdd2),
    .O(Hfound0r__or00002)
  );
  OR2   Hfound0r__or000022 (
    .I0(DCORIFGw),
    .I1(Hfound0r__or0000_bdd3),
    .O(Hfound0r__or000021_1095)
  );
  INV   Hfound0r__or000023 (
    .I(RF0r_1240),
    .O(Hfound0r__or000022_1096)
  );
  AND2   Hfound0r__or000024 (
    .I0(RF0r_1240),
    .I1(Hfound0r__or00002),
    .O(Hfound0r__or000023_1097)
  );
  AND2   Hfound0r__or000025 (
    .I0(Hfound0r__or000021_1095),
    .I1(Hfound0r__or000022_1096),
    .O(Hfound0r__or000024_1098)
  );
  OR2   Hfound0r__or000026 (
    .I0(Hfound0r__or000023_1097),
    .I1(Hfound0r__or000024_1098),
    .O(Hfound0r__or0000_bdd0)
  );
  INV   Hfound0r__or000011 (
    .I(DCORENCCTLw),
    .O(Hfound0r__or00001)
  );
  AND2   Hfound0r__or000012 (
    .I0(SFDecomp_80),
    .I1(Hfound0r__or00001),
    .O(Hfound0r__or000011_1093)
  );
  OR2   Hfound0r__or000013 (
    .I0(Reset),
    .I1(Hfound0r__or000011_1093),
    .O(Hfound0r__or0000)
  );
  OR2   latchitH1__and000011 (
    .I0(RF1r_1243),
    .I1(Hfound1r__or0000_bdd3),
    .O(latchitH1__and00001)
  );
  INV   latchitH1__and000012 (
    .I(RF1r_1243),
    .O(latchitH1__and000011_1368)
  );
  AND2   latchitH1__and000013 (
    .I0(SFDecomp_77),
    .I1(latchitH1__and00001),
    .O(latchitH1__and000012_1369)
  );
  OR2   latchitH1__and000014 (
    .I0(Hfound1r__or0000_bdd2),
    .I1(latchitH1__and000011_1368),
    .O(latchitH1__and000013_1370)
  );
  AND2   latchitH1__and000015 (
    .I0(latchitH1__and000012_1369),
    .I1(latchitH1__and000013_1370),
    .O(latchitH1__and0000)
  );
  INV   Hfound1r__or000041 (
    .I(HE1stater_1083),
    .O(Hfound1r__or00004)
  );
  INV   Hfound1r__or000042 (
    .I(NlwRenamedSig_OI_Hfound1),
    .O(Hfound1r__or000041_1124)
  );
  AND3   Hfound1r__or000043 (
    .I0(Hfound1r__or00004),
    .I1(HE1statelastr_1082),
    .I2(Hfound1r__or000041_1124),
    .O(Hfound1r__or0000_bdd3)
  );
  INV   Hfound1r__or000031 (
    .I(NlwRenamedSig_OI_Hfound1),
    .O(Hfound1r__or00003)
  );
  INV   Hfound1r__or000032 (
    .I(HE1statelastr_1082),
    .O(Hfound1r__or000031_1122)
  );
  AND3   Hfound1r__or000033 (
    .I0(Hfound1r__or00003),
    .I1(HE1stater_1083),
    .I2(Hfound1r__or000031_1122),
    .O(Hfound1r__or0000_bdd2)
  );
  OR2   Hfound1r__or000021 (
    .I0(DCORIFGw),
    .I1(Hfound1r__or0000_bdd2),
    .O(Hfound1r__or00002)
  );
  OR2   Hfound1r__or000022 (
    .I0(DCORIFGw),
    .I1(Hfound1r__or0000_bdd3),
    .O(Hfound1r__or000021_1117)
  );
  INV   Hfound1r__or000023 (
    .I(RF1r_1243),
    .O(Hfound1r__or000022_1118)
  );
  AND2   Hfound1r__or000024 (
    .I0(RF1r_1243),
    .I1(Hfound1r__or00002),
    .O(Hfound1r__or000023_1119)
  );
  AND2   Hfound1r__or000025 (
    .I0(Hfound1r__or000021_1117),
    .I1(Hfound1r__or000022_1118),
    .O(Hfound1r__or000024_1120)
  );
  OR2   Hfound1r__or000026 (
    .I0(Hfound1r__or000023_1119),
    .I1(Hfound1r__or000024_1120),
    .O(Hfound1r__or0000_bdd0)
  );
  INV   Hfound1r__or000011 (
    .I(DCORENCCTLw),
    .O(Hfound1r__or00001)
  );
  AND2   Hfound1r__or000012 (
    .I0(SFDecomp_83),
    .I1(Hfound1r__or00001),
    .O(Hfound1r__or000011_1115)
  );
  OR2   Hfound1r__or000013 (
    .I0(Reset),
    .I1(Hfound1r__or000011_1115),
    .O(Hfound1r__or0000)
  );
  INV   Tfound0r_not00011 (
    .I(Tfound0r_or0000),
    .O(Tfound0r_not0001)
  );
  OR3   Tfound0r_or00001 (
    .I0(DCORENCCTLw),
    .I1(Tfound0r_and0000),
    .I2(Reset),
    .O(Tfound0r_or0000)
  );
  INV   Tfound0r_and00001 (
    .I(latchitL0_cmp_eq0001),
    .O(Tfound0r_and00001_1326)
  );
  INV   Tfound0r_and00002 (
    .I(latchitL0_cmp_eq0000),
    .O(Tfound0r_and00002_1327)
  );
  INV   Tfound0r_and00003 (
    .I(DCORIFGw),
    .O(Tfound0r_and00003_1328)
  );
  AND3   Tfound0r_and00004 (
    .I0(Tfound0r_and00002_1327),
    .I1(Tfound0r_and00001_1326),
    .I2(Tfound0r_and00003_1328),
    .O(Tfound0r_and0000)
  );
  INV   latchitL0_cmp_eq00011 (
    .I(LatchEdge0r_1232),
    .O(latchitL0_cmp_eq00011_1381)
  );
  INV   latchitL0_cmp_eq00012 (
    .I(InEdge0r_1130),
    .O(latchitL0_cmp_eq00012_1382)
  );
  INV   latchitL0_cmp_eq00013 (
    .I(NlwRenamedSig_OI_Tfound0),
    .O(latchitL0_cmp_eq00013_1383)
  );
  AND4   latchitL0_cmp_eq00014 (
    .I0(LastEdge0r_1132),
    .I1(latchitL0_cmp_eq00011_1381),
    .I2(latchitL0_cmp_eq00012_1382),
    .I3(latchitL0_cmp_eq00013_1383),
    .O(latchitL0_cmp_eq0001)
  );
  OR2   latchitL0__and00001 (
    .I0(latchitL0_cmp_eq0001),
    .I1(latchitL0_cmp_eq0000),
    .O(latchitL0__and00001_1373)
  );
  INV   latchitL0__and00002 (
    .I(Reset),
    .O(latchitL0__and00002_1374)
  );
  AND2   latchitL0__and00003 (
    .I0(latchitL0__and00001_1373),
    .I1(latchitL0__and00002_1374),
    .O(latchitL0__and0000)
  );
  AND2   latchitL0_cmp_eq00001 (
    .I0(LatchEdge0r_1232),
    .I1(InEdge0r_1130),
    .O(latchitL0_cmp_eq00001_1376)
  );
  INV   latchitL0_cmp_eq00002 (
    .I(LastEdge0r_1132),
    .O(latchitL0_cmp_eq00002_1377)
  );
  INV   latchitL0_cmp_eq00003 (
    .I(NlwRenamedSig_OI_Tfound0),
    .O(latchitL0_cmp_eq00003_1378)
  );
  AND2   latchitL0_cmp_eq00004 (
    .I0(latchitL0_cmp_eq00002_1377),
    .I1(latchitL0_cmp_eq00003_1378),
    .O(latchitL0_cmp_eq00004_1379)
  );
  AND2   latchitL0_cmp_eq00005 (
    .I0(latchitL0_cmp_eq00001_1376),
    .I1(latchitL0_cmp_eq00004_1379),
    .O(latchitL0_cmp_eq0000)
  );
  INV   Tfound1r_not00011 (
    .I(Tfound1r_or0000),
    .O(Tfound1r_not0001)
  );
  OR3   Tfound1r_or00001 (
    .I0(DCORENCCTLw),
    .I1(Tfound1r_and0000),
    .I2(Reset),
    .O(Tfound1r_or0000)
  );
  INV   Tfound1r_and00001 (
    .I(latchitL1_cmp_eq0001),
    .O(Tfound1r_and00001_1337)
  );
  INV   Tfound1r_and00002 (
    .I(latchitL1_cmp_eq0000),
    .O(Tfound1r_and00002_1338)
  );
  INV   Tfound1r_and00003 (
    .I(DCORIFGw),
    .O(Tfound1r_and00003_1339)
  );
  AND3   Tfound1r_and00004 (
    .I0(Tfound1r_and00002_1338),
    .I1(Tfound1r_and00001_1337),
    .I2(Tfound1r_and00003_1339),
    .O(Tfound1r_and0000)
  );
  INV   latchitL1_cmp_eq00011 (
    .I(LatchEdge1r_1235),
    .O(latchitL1_cmp_eq00011_1394)
  );
  INV   latchitL1_cmp_eq00012 (
    .I(InEdge1r_1131),
    .O(latchitL1_cmp_eq00012_1395)
  );
  INV   latchitL1_cmp_eq00013 (
    .I(NlwRenamedSig_OI_Tfound1),
    .O(latchitL1_cmp_eq00013_1396)
  );
  AND4   latchitL1_cmp_eq00014 (
    .I0(LastEdge1r_1133),
    .I1(latchitL1_cmp_eq00011_1394),
    .I2(latchitL1_cmp_eq00012_1395),
    .I3(latchitL1_cmp_eq00013_1396),
    .O(latchitL1_cmp_eq0001)
  );
  OR2   latchitL1__and00001 (
    .I0(latchitL1_cmp_eq0001),
    .I1(latchitL1_cmp_eq0000),
    .O(latchitL1__and00001_1386)
  );
  INV   latchitL1__and00002 (
    .I(Reset),
    .O(latchitL1__and00002_1387)
  );
  AND2   latchitL1__and00003 (
    .I0(latchitL1__and00001_1386),
    .I1(latchitL1__and00002_1387),
    .O(latchitL1__and0000)
  );
  AND2   latchitL1_cmp_eq00001 (
    .I0(LatchEdge1r_1235),
    .I1(InEdge1r_1131),
    .O(latchitL1_cmp_eq00001_1389)
  );
  INV   latchitL1_cmp_eq00002 (
    .I(LastEdge1r_1133),
    .O(latchitL1_cmp_eq00002_1390)
  );
  INV   latchitL1_cmp_eq00003 (
    .I(NlwRenamedSig_OI_Tfound1),
    .O(latchitL1_cmp_eq00003_1391)
  );
  AND2   latchitL1_cmp_eq00004 (
    .I0(latchitL1_cmp_eq00002_1390),
    .I1(latchitL1_cmp_eq00003_1391),
    .O(latchitL1_cmp_eq00004_1392)
  );
  AND2   latchitL1_cmp_eq00005 (
    .I0(latchitL1_cmp_eq00001_1389),
    .I1(latchitL1_cmp_eq00004_1392),
    .O(latchitL1_cmp_eq0000)
  );
  INV   \outDATA<7>_not000011  (
    .I(DCORIFGr),
    .O(\outDATA<7>_not00001 )
  );
  AND2   \outDATA<7>_not000012  (
    .I0(\outDATA<6>_not0000_bdd0 ),
    .I1(\outDATA<7>_not00001 ),
    .O(\outDATA<7>_not000011_1409 )
  );
  OR2   \outDATA<7>_not000013  (
    .I0(DCOR0THRESLOWr),
    .I1(\outDATA<7>_not000011_1409 ),
    .O(\outDATA<7>_not0000 )
  );
  OR3   \outDATA<6>_not000021  (
    .I0(DCOR0THRESHIGHr),
    .I1(DCOR1THRESHIGHr),
    .I2(DCOR1THRESLOWr),
    .O(\outDATA<6>_not0000_bdd0 )
  );
  OR3   \outDATA<6>_not000011  (
    .I0(DCOR0THRESLOWr),
    .I1(DCORIFGr),
    .I2(\outDATA<6>_not0000_bdd0 ),
    .O(\outDATA<6>_not0000 )
  );
  AND2   SFDecomp_401 (
    .I0(DCOR1THRESLOWr),
    .I1(Latch1r[7]),
    .O(SFDecomp_401_1248)
  );
  INV   SFDecomp_402 (
    .I(DCOR1THRESLOWr),
    .O(SFDecomp_402_1249)
  );
  AND2   SFDecomp_403 (
    .I0(Latch1r[15]),
    .I1(SFDecomp_402_1249),
    .O(SFDecomp_403_1250)
  );
  OR2   SFDecomp_404 (
    .I0(SFDecomp_401_1248),
    .I1(SFDecomp_403_1250),
    .O(SFDecomp_40)
  );
  AND2   SFDecomp_421 (
    .I0(DCOR0THRESHIGHr),
    .I1(Latch0r[15]),
    .O(SFDecomp_421_1252)
  );
  INV   SFDecomp_422 (
    .I(DCOR0THRESHIGHr),
    .O(SFDecomp_422_1253)
  );
  AND2   SFDecomp_423 (
    .I0(SFDecomp_40),
    .I1(SFDecomp_422_1253),
    .O(SFDecomp_423_1254)
  );
  OR2   SFDecomp_424 (
    .I0(SFDecomp_421_1252),
    .I1(SFDecomp_423_1254),
    .O(SFDecomp_42)
  );
  AND2   SFDecomp_431 (
    .I0(DCOR1THRESLOWr),
    .I1(Latch1r[4]),
    .O(SFDecomp_431_1256)
  );
  INV   SFDecomp_432 (
    .I(DCOR1THRESLOWr),
    .O(SFDecomp_432_1257)
  );
  AND2   SFDecomp_433 (
    .I0(Latch1r[12]),
    .I1(SFDecomp_432_1257),
    .O(SFDecomp_433_1258)
  );
  OR2   SFDecomp_434 (
    .I0(SFDecomp_431_1256),
    .I1(SFDecomp_433_1258),
    .O(SFDecomp_43)
  );
  AND2   SFDecomp_451 (
    .I0(DCOR0THRESHIGHr),
    .I1(Latch0r[12]),
    .O(SFDecomp_451_1260)
  );
  INV   SFDecomp_452 (
    .I(DCOR0THRESHIGHr),
    .O(SFDecomp_452_1261)
  );
  AND2   SFDecomp_453 (
    .I0(SFDecomp_43),
    .I1(SFDecomp_452_1261),
    .O(SFDecomp_453_1262)
  );
  OR2   SFDecomp_454 (
    .I0(SFDecomp_451_1260),
    .I1(SFDecomp_453_1262),
    .O(SFDecomp_45)
  );
  AND2   SFDecomp_461 (
    .I0(DCOR1THRESLOWr),
    .I1(Latch1r[1]),
    .O(SFDecomp_461_1264)
  );
  INV   SFDecomp_462 (
    .I(DCOR1THRESLOWr),
    .O(SFDecomp_462_1265)
  );
  AND2   SFDecomp_463 (
    .I0(Latch1r[9]),
    .I1(SFDecomp_462_1265),
    .O(SFDecomp_463_1266)
  );
  OR2   SFDecomp_464 (
    .I0(SFDecomp_461_1264),
    .I1(SFDecomp_463_1266),
    .O(SFDecomp_46)
  );
  AND2   SFDecomp_481 (
    .I0(DCOR0THRESHIGHr),
    .I1(Latch0r[9]),
    .O(SFDecomp_481_1268)
  );
  INV   SFDecomp_482 (
    .I(DCOR0THRESHIGHr),
    .O(SFDecomp_482_1269)
  );
  AND2   SFDecomp_483 (
    .I0(SFDecomp_46),
    .I1(SFDecomp_482_1269),
    .O(SFDecomp_483_1270)
  );
  OR2   SFDecomp_484 (
    .I0(SFDecomp_481_1268),
    .I1(SFDecomp_483_1270),
    .O(SFDecomp_48)
  );
  AND2   SFDecomp_491 (
    .I0(DCOR1THRESLOWr),
    .I1(Latch1r[0]),
    .O(SFDecomp_491_1272)
  );
  INV   SFDecomp_492 (
    .I(DCOR1THRESLOWr),
    .O(SFDecomp_492_1273)
  );
  AND2   SFDecomp_493 (
    .I0(Latch1r[8]),
    .I1(SFDecomp_492_1273),
    .O(SFDecomp_493_1274)
  );
  OR2   SFDecomp_494 (
    .I0(SFDecomp_491_1272),
    .I1(SFDecomp_493_1274),
    .O(SFDecomp_49)
  );
  AND2   SFDecomp_511 (
    .I0(DCOR0THRESHIGHr),
    .I1(Latch0r[8]),
    .O(SFDecomp_511_1276)
  );
  INV   SFDecomp_512 (
    .I(DCOR0THRESHIGHr),
    .O(SFDecomp_512_1277)
  );
  AND2   SFDecomp_513 (
    .I0(SFDecomp_49),
    .I1(SFDecomp_512_1277),
    .O(SFDecomp_513_1278)
  );
  OR2   SFDecomp_514 (
    .I0(SFDecomp_511_1276),
    .I1(SFDecomp_513_1278),
    .O(SFDecomp_51)
  );
  AND2   SFDecomp_531 (
    .I0(DCOR0THRESHIGHr),
    .I1(Latch0r[14]),
    .O(SFDecomp_531_1280)
  );
  INV   SFDecomp_532 (
    .I(DCOR0THRESHIGHr),
    .O(SFDecomp_532_1281)
  );
  AND2   SFDecomp_533 (
    .I0(outDATA_6_mux0000_bdd0),
    .I1(SFDecomp_532_1281),
    .O(SFDecomp_533_1282)
  );
  OR2   SFDecomp_534 (
    .I0(SFDecomp_531_1280),
    .I1(SFDecomp_533_1282),
    .O(SFDecomp_53)
  );
  AND2   SFDecomp_541 (
    .I0(DCORIFGr),
    .I1(NlwRenamedSig_OI_Tfound1),
    .O(SFDecomp_54)
  );
  INV   SFDecomp_571 (
    .I(DCORIFGr),
    .O(SFDecomp_571_1285)
  );
  AND2   SFDecomp_572 (
    .I0(SFDecomp_53),
    .I1(SFDecomp_571_1285),
    .O(SFDecomp_572_1286)
  );
  OR2   SFDecomp_573 (
    .I0(SFDecomp_54),
    .I1(SFDecomp_572_1286),
    .O(SFDecomp_57)
  );
  AND2   SFDecomp_591 (
    .I0(DCOR0THRESHIGHr),
    .I1(Latch0r[13]),
    .O(SFDecomp_591_1288)
  );
  INV   SFDecomp_592 (
    .I(DCOR0THRESHIGHr),
    .O(SFDecomp_592_1289)
  );
  AND2   SFDecomp_593 (
    .I0(outDATA_5_mux0000_bdd0),
    .I1(SFDecomp_592_1289),
    .O(SFDecomp_593_1290)
  );
  OR2   SFDecomp_594 (
    .I0(SFDecomp_591_1288),
    .I1(SFDecomp_593_1290),
    .O(SFDecomp_59)
  );
  AND2   SFDecomp_601 (
    .I0(DCORIFGr),
    .I1(NlwRenamedSig_OI_Tfound0),
    .O(SFDecomp_60)
  );
  INV   SFDecomp_631 (
    .I(DCORIFGr),
    .O(SFDecomp_631_1293)
  );
  AND2   SFDecomp_632 (
    .I0(SFDecomp_59),
    .I1(SFDecomp_631_1293),
    .O(SFDecomp_632_1294)
  );
  OR2   SFDecomp_633 (
    .I0(SFDecomp_60),
    .I1(SFDecomp_632_1294),
    .O(SFDecomp_63)
  );
  AND2   SFDecomp_651 (
    .I0(DCOR0THRESHIGHr),
    .I1(Latch0r[11]),
    .O(SFDecomp_651_1296)
  );
  INV   SFDecomp_652 (
    .I(DCOR0THRESHIGHr),
    .O(SFDecomp_652_1297)
  );
  AND2   SFDecomp_653 (
    .I0(outDATA_3_mux0000_bdd0),
    .I1(SFDecomp_652_1297),
    .O(SFDecomp_653_1298)
  );
  OR2   SFDecomp_654 (
    .I0(SFDecomp_651_1296),
    .I1(SFDecomp_653_1298),
    .O(SFDecomp_65)
  );
  AND2   SFDecomp_661 (
    .I0(DCORIFGr),
    .I1(NlwRenamedSig_OI_Hfound1),
    .O(SFDecomp_66)
  );
  INV   SFDecomp_691 (
    .I(DCORIFGr),
    .O(SFDecomp_691_1301)
  );
  AND2   SFDecomp_692 (
    .I0(SFDecomp_65),
    .I1(SFDecomp_691_1301),
    .O(SFDecomp_692_1302)
  );
  OR2   SFDecomp_693 (
    .I0(SFDecomp_66),
    .I1(SFDecomp_692_1302),
    .O(SFDecomp_69)
  );
  AND2   SFDecomp_711 (
    .I0(DCOR0THRESHIGHr),
    .I1(Latch0r[10]),
    .O(SFDecomp_711_1304)
  );
  INV   SFDecomp_712 (
    .I(DCOR0THRESHIGHr),
    .O(SFDecomp_712_1305)
  );
  AND2   SFDecomp_713 (
    .I0(outDATA_2_mux0000_bdd0),
    .I1(SFDecomp_712_1305),
    .O(SFDecomp_713_1306)
  );
  OR2   SFDecomp_714 (
    .I0(SFDecomp_711_1304),
    .I1(SFDecomp_713_1306),
    .O(SFDecomp_71)
  );
  AND2   SFDecomp_721 (
    .I0(DCORIFGr),
    .I1(NlwRenamedSig_OI_Hfound0),
    .O(SFDecomp_72)
  );
  INV   SFDecomp_751 (
    .I(DCORIFGr),
    .O(SFDecomp_751_1309)
  );
  AND2   SFDecomp_752 (
    .I0(SFDecomp_71),
    .I1(SFDecomp_751_1309),
    .O(SFDecomp_752_1310)
  );
  OR2   SFDecomp_753 (
    .I0(SFDecomp_72),
    .I1(SFDecomp_752_1310),
    .O(SFDecomp_75)
  );
  INV   SFDecomp_761 (
    .I(Reset),
    .O(SFDecomp_761_1312)
  );
  AND2   SFDecomp_762 (
    .I0(E0r_1072),
    .I1(SFDecomp_761_1312),
    .O(SFDecomp_76)
  );
  INV   SFDecomp_771 (
    .I(Reset),
    .O(SFDecomp_771_1314)
  );
  AND2   SFDecomp_772 (
    .I0(E1r_1077),
    .I1(SFDecomp_771_1314),
    .O(SFDecomp_77)
  );
  AND2   SFDecomp_801 (
    .I0(E0r_1072),
    .I1(Hfound0r__or0000_bdd0),
    .O(SFDecomp_801_1316)
  );
  INV   SFDecomp_802 (
    .I(E0r_1072),
    .O(SFDecomp_802_1317)
  );
  AND2   SFDecomp_803 (
    .I0(DCORIFGw),
    .I1(SFDecomp_802_1317),
    .O(SFDecomp_803_1318)
  );
  OR2   SFDecomp_804 (
    .I0(SFDecomp_801_1316),
    .I1(SFDecomp_803_1318),
    .O(SFDecomp_80)
  );
  AND2   SFDecomp_831 (
    .I0(E1r_1077),
    .I1(Hfound1r__or0000_bdd0),
    .O(SFDecomp_831_1320)
  );
  INV   SFDecomp_832 (
    .I(E1r_1077),
    .O(SFDecomp_832_1321)
  );
  AND2   SFDecomp_833 (
    .I0(DCORIFGw),
    .I1(SFDecomp_832_1321),
    .O(SFDecomp_833_1322)
  );
  OR2   SFDecomp_834 (
    .I0(SFDecomp_831_1320),
    .I1(SFDecomp_833_1322),
    .O(SFDecomp_83)
  );
endmodule

module Holdreg (
  DCOR0CNTLOWr, DCOR1CNTHIGHr, Reset, DCOR0CNTHIGHr, Sclk, DCOR1CNTLOWr, ASleading, outDATA, ch0in, ch1in
);
  input DCOR0CNTLOWr;
  input DCOR1CNTHIGHr;
  input Reset;
  input DCOR0CNTHIGHr;
  input Sclk;
  input DCOR1CNTLOWr;
  input ASleading;
  output [7 : 0] outDATA;
  input [15 : 0] ch0in;
  input [15 : 0] ch1in;
  wire N0;
  wire SFDecomp_16;
  wire SFDecomp_161_798;
  wire SFDecomp_162_799;
  wire SFDecomp_163_800;
  wire SFDecomp_18;
  wire SFDecomp_181_802;
  wire SFDecomp_182_803;
  wire SFDecomp_183_804;
  wire SFDecomp_19;
  wire SFDecomp_191_806;
  wire SFDecomp_192_807;
  wire SFDecomp_193_808;
  wire SFDecomp_21;
  wire SFDecomp_211_810;
  wire SFDecomp_212_811;
  wire SFDecomp_213_812;
  wire SFDecomp_22;
  wire SFDecomp_221_814;
  wire SFDecomp_222_815;
  wire SFDecomp_223_816;
  wire SFDecomp_24;
  wire SFDecomp_241_818;
  wire SFDecomp_242_819;
  wire SFDecomp_243_820;
  wire SFDecomp_25;
  wire SFDecomp_251_822;
  wire SFDecomp_252_823;
  wire SFDecomp_253_824;
  wire SFDecomp_27;
  wire SFDecomp_271_826;
  wire SFDecomp_272_827;
  wire SFDecomp_273_828;
  wire SFDecomp_28;
  wire SFDecomp_281_830;
  wire SFDecomp_282_831;
  wire SFDecomp_283_832;
  wire SFDecomp_30;
  wire SFDecomp_301_834;
  wire SFDecomp_302_835;
  wire SFDecomp_303_836;
  wire SFDecomp_31;
  wire SFDecomp_311_838;
  wire SFDecomp_312_839;
  wire SFDecomp_313_840;
  wire SFDecomp_33;
  wire SFDecomp_331_842;
  wire SFDecomp_332_843;
  wire SFDecomp_333_844;
  wire SFDecomp_34;
  wire SFDecomp_341_846;
  wire SFDecomp_342_847;
  wire SFDecomp_343_848;
  wire SFDecomp_36;
  wire SFDecomp_361_850;
  wire SFDecomp_362_851;
  wire SFDecomp_363_852;
  wire SFDecomp_37;
  wire SFDecomp_371_854;
  wire SFDecomp_372_855;
  wire SFDecomp_373_856;
  wire SFDecomp_39;
  wire SFDecomp_391_858;
  wire SFDecomp_392_859;
  wire SFDecomp_393_860;
  wire holdingreg0_0_0_not0000;
  wire holdingreg0_0__and0000;
  wire holdingreg0_0__and00001_897;
  wire holdingreg0_0__or0000;
  wire holdingreg0_10__and0000;
  wire holdingreg0_10__and00001_902;
  wire holdingreg0_11__and0000;
  wire holdingreg0_11__and00001_905;
  wire holdingreg0_12__and0000;
  wire holdingreg0_12__and00001_908;
  wire holdingreg0_13__and0000;
  wire holdingreg0_13__and00001_911;
  wire holdingreg0_14__and0000;
  wire holdingreg0_14__and00001_914;
  wire holdingreg0_15__and0000;
  wire holdingreg0_15__and00001_917;
  wire holdingreg0_1__and0000;
  wire holdingreg0_1__and00001_919;
  wire holdingreg0_2__and0000;
  wire holdingreg0_2__and00001_922;
  wire holdingreg0_3__and0000;
  wire holdingreg0_3__and00001_925;
  wire holdingreg0_4__and0000;
  wire holdingreg0_4__and00001_928;
  wire holdingreg0_5__and0000;
  wire holdingreg0_5__and00001_931;
  wire holdingreg0_6__and0000;
  wire holdingreg0_6__and00001_934;
  wire holdingreg0_7__and0000;
  wire holdingreg0_7__and00001_937;
  wire holdingreg0_8__and0000;
  wire holdingreg0_8__and00001_940;
  wire holdingreg0_9__and0000;
  wire holdingreg0_9__and00001_943;
  wire holdingreg1_0__and0000;
  wire holdingreg1_0__and00001_946;
  wire holdingreg1_10__and0000;
  wire holdingreg1_10__and00001_950;
  wire holdingreg1_11__and0000;
  wire holdingreg1_11__and00001_953;
  wire holdingreg1_12__and0000;
  wire holdingreg1_12__and00001_956;
  wire holdingreg1_13__and0000;
  wire holdingreg1_13__and00001_959;
  wire holdingreg1_14__and0000;
  wire holdingreg1_14__and00001_962;
  wire holdingreg1_15__and0000;
  wire holdingreg1_15__and00001_965;
  wire holdingreg1_1__and0000;
  wire holdingreg1_1__and00001_967;
  wire holdingreg1_2__and0000;
  wire holdingreg1_2__and00001_970;
  wire holdingreg1_3__and0000;
  wire holdingreg1_3__and00001_973;
  wire holdingreg1_4__and0000;
  wire holdingreg1_4__and00001_976;
  wire holdingreg1_5__and0000;
  wire holdingreg1_5__and00001_979;
  wire holdingreg1_6__and0000;
  wire holdingreg1_6__and00001_982;
  wire holdingreg1_7__and0000;
  wire holdingreg1_7__and00001_985;
  wire holdingreg1_8__and0000;
  wire holdingreg1_8__and00001_988;
  wire holdingreg1_9__and0000;
  wire holdingreg1_9__and00001_991;
  wire \interDATA_mux0000<0>1 ;
  wire \interDATA_mux0000<0>11_1002 ;
  wire \interDATA_mux0000<0>12_1003 ;
  wire \interDATA_mux0000<1>1 ;
  wire \interDATA_mux0000<1>11_1006 ;
  wire \interDATA_mux0000<1>12_1007 ;
  wire \interDATA_mux0000<2>1 ;
  wire \interDATA_mux0000<2>11_1010 ;
  wire \interDATA_mux0000<2>12_1011 ;
  wire \interDATA_mux0000<3>1 ;
  wire \interDATA_mux0000<3>11_1014 ;
  wire \interDATA_mux0000<3>12_1015 ;
  wire \interDATA_mux0000<4>1 ;
  wire \interDATA_mux0000<4>11_1018 ;
  wire \interDATA_mux0000<4>12_1019 ;
  wire \interDATA_mux0000<5>1 ;
  wire \interDATA_mux0000<5>11_1022 ;
  wire \interDATA_mux0000<5>12_1023 ;
  wire \interDATA_mux0000<6>1 ;
  wire \interDATA_mux0000<6>11_1026 ;
  wire \interDATA_mux0000<6>12_1027 ;
  wire \interDATA_mux0000<7>1 ;
  wire \interDATA_mux0000<7>11_1030 ;
  wire \interDATA_mux0000<7>12_1031 ;
  wire interDATA_not0001;
  wire [15 : 0] holdingreg0;
  wire [15 : 0] holdingreg1;
  wire [7 : 0] interDATA;
  wire [7 : 0] interDATA_mux0000;
  assign
    outDATA[7] = interDATA[7],
    outDATA[6] = interDATA[6],
    outDATA[5] = interDATA[5],
    outDATA[4] = interDATA[4],
    outDATA[3] = interDATA[3],
    outDATA[2] = interDATA[2],
    outDATA[1] = interDATA[1],
    outDATA[0] = interDATA[0];
  GND   XST_GND (
    .G(N0)
  );
  FDCE   holdingreg0_0 (
    .CE(holdingreg0_0__or0000),
    .CLR(N0),
    .C(holdingreg0_0_0_not0000),
    .D(holdingreg0_0__and0000),
    .Q(holdingreg0[0])
  );
  FDCE   holdingreg0_1 (
    .CE(holdingreg0_0__or0000),
    .CLR(N0),
    .C(holdingreg0_0_0_not0000),
    .D(holdingreg0_1__and0000),
    .Q(holdingreg0[1])
  );
  FDCE   holdingreg0_2 (
    .CE(holdingreg0_0__or0000),
    .CLR(N0),
    .C(holdingreg0_0_0_not0000),
    .D(holdingreg0_2__and0000),
    .Q(holdingreg0[2])
  );
  FDCE   holdingreg0_3 (
    .CE(holdingreg0_0__or0000),
    .CLR(N0),
    .C(holdingreg0_0_0_not0000),
    .D(holdingreg0_3__and0000),
    .Q(holdingreg0[3])
  );
  FDCE   holdingreg0_4 (
    .CE(holdingreg0_0__or0000),
    .CLR(N0),
    .C(holdingreg0_0_0_not0000),
    .D(holdingreg0_4__and0000),
    .Q(holdingreg0[4])
  );
  FDCE   holdingreg0_5 (
    .CE(holdingreg0_0__or0000),
    .CLR(N0),
    .C(holdingreg0_0_0_not0000),
    .D(holdingreg0_5__and0000),
    .Q(holdingreg0[5])
  );
  FDCE   holdingreg0_6 (
    .CE(holdingreg0_0__or0000),
    .CLR(N0),
    .C(holdingreg0_0_0_not0000),
    .D(holdingreg0_6__and0000),
    .Q(holdingreg0[6])
  );
  FDCE   holdingreg0_7 (
    .CE(holdingreg0_0__or0000),
    .CLR(N0),
    .C(holdingreg0_0_0_not0000),
    .D(holdingreg0_7__and0000),
    .Q(holdingreg0[7])
  );
  FDCE   holdingreg0_8 (
    .CE(holdingreg0_0__or0000),
    .CLR(N0),
    .C(holdingreg0_0_0_not0000),
    .D(holdingreg0_8__and0000),
    .Q(holdingreg0[8])
  );
  FDCE   holdingreg0_9 (
    .CE(holdingreg0_0__or0000),
    .CLR(N0),
    .C(holdingreg0_0_0_not0000),
    .D(holdingreg0_9__and0000),
    .Q(holdingreg0[9])
  );
  FDCE   holdingreg0_10 (
    .CE(holdingreg0_0__or0000),
    .CLR(N0),
    .C(holdingreg0_0_0_not0000),
    .D(holdingreg0_10__and0000),
    .Q(holdingreg0[10])
  );
  FDCE   holdingreg0_11 (
    .CE(holdingreg0_0__or0000),
    .CLR(N0),
    .C(holdingreg0_0_0_not0000),
    .D(holdingreg0_11__and0000),
    .Q(holdingreg0[11])
  );
  FDCE   holdingreg0_12 (
    .CE(holdingreg0_0__or0000),
    .CLR(N0),
    .C(holdingreg0_0_0_not0000),
    .D(holdingreg0_12__and0000),
    .Q(holdingreg0[12])
  );
  FDCE   holdingreg0_13 (
    .CE(holdingreg0_0__or0000),
    .CLR(N0),
    .C(holdingreg0_0_0_not0000),
    .D(holdingreg0_13__and0000),
    .Q(holdingreg0[13])
  );
  FDCE   holdingreg0_14 (
    .CE(holdingreg0_0__or0000),
    .CLR(N0),
    .C(holdingreg0_0_0_not0000),
    .D(holdingreg0_14__and0000),
    .Q(holdingreg0[14])
  );
  FDCE   holdingreg0_15 (
    .CE(holdingreg0_0__or0000),
    .CLR(N0),
    .C(holdingreg0_0_0_not0000),
    .D(holdingreg0_15__and0000),
    .Q(holdingreg0[15])
  );
  FDCE   holdingreg1_0 (
    .CE(holdingreg0_0__or0000),
    .CLR(N0),
    .C(holdingreg0_0_0_not0000),
    .D(holdingreg1_0__and0000),
    .Q(holdingreg1[0])
  );
  FDCE   holdingreg1_1 (
    .CE(holdingreg0_0__or0000),
    .CLR(N0),
    .C(holdingreg0_0_0_not0000),
    .D(holdingreg1_1__and0000),
    .Q(holdingreg1[1])
  );
  FDCE   holdingreg1_2 (
    .CE(holdingreg0_0__or0000),
    .CLR(N0),
    .C(holdingreg0_0_0_not0000),
    .D(holdingreg1_2__and0000),
    .Q(holdingreg1[2])
  );
  FDCE   holdingreg1_3 (
    .CE(holdingreg0_0__or0000),
    .CLR(N0),
    .C(holdingreg0_0_0_not0000),
    .D(holdingreg1_3__and0000),
    .Q(holdingreg1[3])
  );
  FDCE   holdingreg1_4 (
    .CE(holdingreg0_0__or0000),
    .CLR(N0),
    .C(holdingreg0_0_0_not0000),
    .D(holdingreg1_4__and0000),
    .Q(holdingreg1[4])
  );
  FDCE   holdingreg1_5 (
    .CE(holdingreg0_0__or0000),
    .CLR(N0),
    .C(holdingreg0_0_0_not0000),
    .D(holdingreg1_5__and0000),
    .Q(holdingreg1[5])
  );
  FDCE   holdingreg1_6 (
    .CE(holdingreg0_0__or0000),
    .CLR(N0),
    .C(holdingreg0_0_0_not0000),
    .D(holdingreg1_6__and0000),
    .Q(holdingreg1[6])
  );
  FDCE   holdingreg1_7 (
    .CE(holdingreg0_0__or0000),
    .CLR(N0),
    .C(holdingreg0_0_0_not0000),
    .D(holdingreg1_7__and0000),
    .Q(holdingreg1[7])
  );
  FDCE   holdingreg1_8 (
    .CE(holdingreg0_0__or0000),
    .CLR(N0),
    .C(holdingreg0_0_0_not0000),
    .D(holdingreg1_8__and0000),
    .Q(holdingreg1[8])
  );
  FDCE   holdingreg1_9 (
    .CE(holdingreg0_0__or0000),
    .CLR(N0),
    .C(holdingreg0_0_0_not0000),
    .D(holdingreg1_9__and0000),
    .Q(holdingreg1[9])
  );
  FDCE   holdingreg1_10 (
    .CE(holdingreg0_0__or0000),
    .CLR(N0),
    .C(holdingreg0_0_0_not0000),
    .D(holdingreg1_10__and0000),
    .Q(holdingreg1[10])
  );
  FDCE   holdingreg1_11 (
    .CE(holdingreg0_0__or0000),
    .CLR(N0),
    .C(holdingreg0_0_0_not0000),
    .D(holdingreg1_11__and0000),
    .Q(holdingreg1[11])
  );
  FDCE   holdingreg1_12 (
    .CE(holdingreg0_0__or0000),
    .CLR(N0),
    .C(holdingreg0_0_0_not0000),
    .D(holdingreg1_12__and0000),
    .Q(holdingreg1[12])
  );
  FDCE   holdingreg1_13 (
    .CE(holdingreg0_0__or0000),
    .CLR(N0),
    .C(holdingreg0_0_0_not0000),
    .D(holdingreg1_13__and0000),
    .Q(holdingreg1[13])
  );
  FDCE   holdingreg1_14 (
    .CE(holdingreg0_0__or0000),
    .CLR(N0),
    .C(holdingreg0_0_0_not0000),
    .D(holdingreg1_14__and0000),
    .Q(holdingreg1[14])
  );
  FDCE   holdingreg1_15 (
    .CE(holdingreg0_0__or0000),
    .CLR(N0),
    .C(holdingreg0_0_0_not0000),
    .D(holdingreg1_15__and0000),
    .Q(holdingreg1[15])
  );
  BUFE   interDATA_7 (
    .I(interDATA_mux0000[7]),
    .E(interDATA_not0001),
    .O(interDATA[7])
  );
  BUFE   interDATA_6 (
    .I(interDATA_mux0000[6]),
    .E(interDATA_not0001),
    .O(interDATA[6])
  );
  BUFE   interDATA_5 (
    .I(interDATA_mux0000[5]),
    .E(interDATA_not0001),
    .O(interDATA[5])
  );
  BUFE   interDATA_4 (
    .I(interDATA_mux0000[4]),
    .E(interDATA_not0001),
    .O(interDATA[4])
  );
  BUFE   interDATA_3 (
    .I(interDATA_mux0000[3]),
    .E(interDATA_not0001),
    .O(interDATA[3])
  );
  BUFE   interDATA_2 (
    .I(interDATA_mux0000[2]),
    .E(interDATA_not0001),
    .O(interDATA[2])
  );
  BUFE   interDATA_1 (
    .I(interDATA_mux0000[1]),
    .E(interDATA_not0001),
    .O(interDATA[1])
  );
  BUFE   interDATA_0 (
    .I(interDATA_mux0000[0]),
    .E(interDATA_not0001),
    .O(interDATA[0])
  );
  INV   holdingreg1_0__and00001 (
    .I(Reset),
    .O(holdingreg1_0__and00001_946)
  );
  AND2   holdingreg1_0__and00002 (
    .I0(ch1in[0]),
    .I1(holdingreg1_0__and00001_946),
    .O(holdingreg1_0__and0000)
  );
  INV   holdingreg1_1__and00001 (
    .I(Reset),
    .O(holdingreg1_1__and00001_967)
  );
  AND2   holdingreg1_1__and00002 (
    .I0(ch1in[1]),
    .I1(holdingreg1_1__and00001_967),
    .O(holdingreg1_1__and0000)
  );
  INV   holdingreg1_2__and00001 (
    .I(Reset),
    .O(holdingreg1_2__and00001_970)
  );
  AND2   holdingreg1_2__and00002 (
    .I0(ch1in[2]),
    .I1(holdingreg1_2__and00001_970),
    .O(holdingreg1_2__and0000)
  );
  INV   holdingreg1_3__and00001 (
    .I(Reset),
    .O(holdingreg1_3__and00001_973)
  );
  AND2   holdingreg1_3__and00002 (
    .I0(ch1in[3]),
    .I1(holdingreg1_3__and00001_973),
    .O(holdingreg1_3__and0000)
  );
  INV   holdingreg1_4__and00001 (
    .I(Reset),
    .O(holdingreg1_4__and00001_976)
  );
  AND2   holdingreg1_4__and00002 (
    .I0(ch1in[4]),
    .I1(holdingreg1_4__and00001_976),
    .O(holdingreg1_4__and0000)
  );
  INV   holdingreg1_5__and00001 (
    .I(Reset),
    .O(holdingreg1_5__and00001_979)
  );
  AND2   holdingreg1_5__and00002 (
    .I0(ch1in[5]),
    .I1(holdingreg1_5__and00001_979),
    .O(holdingreg1_5__and0000)
  );
  INV   holdingreg1_6__and00001 (
    .I(Reset),
    .O(holdingreg1_6__and00001_982)
  );
  AND2   holdingreg1_6__and00002 (
    .I0(ch1in[6]),
    .I1(holdingreg1_6__and00001_982),
    .O(holdingreg1_6__and0000)
  );
  INV   holdingreg1_7__and00001 (
    .I(Reset),
    .O(holdingreg1_7__and00001_985)
  );
  AND2   holdingreg1_7__and00002 (
    .I0(ch1in[7]),
    .I1(holdingreg1_7__and00001_985),
    .O(holdingreg1_7__and0000)
  );
  INV   holdingreg1_8__and00001 (
    .I(Reset),
    .O(holdingreg1_8__and00001_988)
  );
  AND2   holdingreg1_8__and00002 (
    .I0(ch1in[8]),
    .I1(holdingreg1_8__and00001_988),
    .O(holdingreg1_8__and0000)
  );
  INV   holdingreg1_9__and00001 (
    .I(Reset),
    .O(holdingreg1_9__and00001_991)
  );
  AND2   holdingreg1_9__and00002 (
    .I0(ch1in[9]),
    .I1(holdingreg1_9__and00001_991),
    .O(holdingreg1_9__and0000)
  );
  INV   holdingreg1_10__and00001 (
    .I(Reset),
    .O(holdingreg1_10__and00001_950)
  );
  AND2   holdingreg1_10__and00002 (
    .I0(ch1in[10]),
    .I1(holdingreg1_10__and00001_950),
    .O(holdingreg1_10__and0000)
  );
  INV   holdingreg1_11__and00001 (
    .I(Reset),
    .O(holdingreg1_11__and00001_953)
  );
  AND2   holdingreg1_11__and00002 (
    .I0(ch1in[11]),
    .I1(holdingreg1_11__and00001_953),
    .O(holdingreg1_11__and0000)
  );
  INV   holdingreg1_12__and00001 (
    .I(Reset),
    .O(holdingreg1_12__and00001_956)
  );
  AND2   holdingreg1_12__and00002 (
    .I0(ch1in[12]),
    .I1(holdingreg1_12__and00001_956),
    .O(holdingreg1_12__and0000)
  );
  INV   holdingreg1_13__and00001 (
    .I(Reset),
    .O(holdingreg1_13__and00001_959)
  );
  AND2   holdingreg1_13__and00002 (
    .I0(ch1in[13]),
    .I1(holdingreg1_13__and00001_959),
    .O(holdingreg1_13__and0000)
  );
  INV   holdingreg1_14__and00001 (
    .I(Reset),
    .O(holdingreg1_14__and00001_962)
  );
  AND2   holdingreg1_14__and00002 (
    .I0(ch1in[14]),
    .I1(holdingreg1_14__and00001_962),
    .O(holdingreg1_14__and0000)
  );
  INV   holdingreg1_15__and00001 (
    .I(Reset),
    .O(holdingreg1_15__and00001_965)
  );
  AND2   holdingreg1_15__and00002 (
    .I0(ch1in[15]),
    .I1(holdingreg1_15__and00001_965),
    .O(holdingreg1_15__and0000)
  );
  INV   holdingreg0_0__and00001 (
    .I(Reset),
    .O(holdingreg0_0__and00001_897)
  );
  AND2   holdingreg0_0__and00002 (
    .I0(ch0in[0]),
    .I1(holdingreg0_0__and00001_897),
    .O(holdingreg0_0__and0000)
  );
  OR2   holdingreg0_0__or00001 (
    .I0(ASleading),
    .I1(Reset),
    .O(holdingreg0_0__or0000)
  );
  INV   holdingreg0_0_0_not00001 (
    .I(Sclk),
    .O(holdingreg0_0_0_not0000)
  );
  INV   holdingreg0_1__and00001 (
    .I(Reset),
    .O(holdingreg0_1__and00001_919)
  );
  AND2   holdingreg0_1__and00002 (
    .I0(ch0in[1]),
    .I1(holdingreg0_1__and00001_919),
    .O(holdingreg0_1__and0000)
  );
  INV   holdingreg0_2__and00001 (
    .I(Reset),
    .O(holdingreg0_2__and00001_922)
  );
  AND2   holdingreg0_2__and00002 (
    .I0(ch0in[2]),
    .I1(holdingreg0_2__and00001_922),
    .O(holdingreg0_2__and0000)
  );
  INV   holdingreg0_3__and00001 (
    .I(Reset),
    .O(holdingreg0_3__and00001_925)
  );
  AND2   holdingreg0_3__and00002 (
    .I0(ch0in[3]),
    .I1(holdingreg0_3__and00001_925),
    .O(holdingreg0_3__and0000)
  );
  INV   holdingreg0_4__and00001 (
    .I(Reset),
    .O(holdingreg0_4__and00001_928)
  );
  AND2   holdingreg0_4__and00002 (
    .I0(ch0in[4]),
    .I1(holdingreg0_4__and00001_928),
    .O(holdingreg0_4__and0000)
  );
  INV   holdingreg0_5__and00001 (
    .I(Reset),
    .O(holdingreg0_5__and00001_931)
  );
  AND2   holdingreg0_5__and00002 (
    .I0(ch0in[5]),
    .I1(holdingreg0_5__and00001_931),
    .O(holdingreg0_5__and0000)
  );
  INV   holdingreg0_6__and00001 (
    .I(Reset),
    .O(holdingreg0_6__and00001_934)
  );
  AND2   holdingreg0_6__and00002 (
    .I0(ch0in[6]),
    .I1(holdingreg0_6__and00001_934),
    .O(holdingreg0_6__and0000)
  );
  INV   holdingreg0_7__and00001 (
    .I(Reset),
    .O(holdingreg0_7__and00001_937)
  );
  AND2   holdingreg0_7__and00002 (
    .I0(ch0in[7]),
    .I1(holdingreg0_7__and00001_937),
    .O(holdingreg0_7__and0000)
  );
  INV   holdingreg0_8__and00001 (
    .I(Reset),
    .O(holdingreg0_8__and00001_940)
  );
  AND2   holdingreg0_8__and00002 (
    .I0(ch0in[8]),
    .I1(holdingreg0_8__and00001_940),
    .O(holdingreg0_8__and0000)
  );
  INV   holdingreg0_9__and00001 (
    .I(Reset),
    .O(holdingreg0_9__and00001_943)
  );
  AND2   holdingreg0_9__and00002 (
    .I0(ch0in[9]),
    .I1(holdingreg0_9__and00001_943),
    .O(holdingreg0_9__and0000)
  );
  INV   holdingreg0_10__and00001 (
    .I(Reset),
    .O(holdingreg0_10__and00001_902)
  );
  AND2   holdingreg0_10__and00002 (
    .I0(ch0in[10]),
    .I1(holdingreg0_10__and00001_902),
    .O(holdingreg0_10__and0000)
  );
  INV   holdingreg0_11__and00001 (
    .I(Reset),
    .O(holdingreg0_11__and00001_905)
  );
  AND2   holdingreg0_11__and00002 (
    .I0(ch0in[11]),
    .I1(holdingreg0_11__and00001_905),
    .O(holdingreg0_11__and0000)
  );
  INV   holdingreg0_12__and00001 (
    .I(Reset),
    .O(holdingreg0_12__and00001_908)
  );
  AND2   holdingreg0_12__and00002 (
    .I0(ch0in[12]),
    .I1(holdingreg0_12__and00001_908),
    .O(holdingreg0_12__and0000)
  );
  INV   holdingreg0_13__and00001 (
    .I(Reset),
    .O(holdingreg0_13__and00001_911)
  );
  AND2   holdingreg0_13__and00002 (
    .I0(ch0in[13]),
    .I1(holdingreg0_13__and00001_911),
    .O(holdingreg0_13__and0000)
  );
  INV   holdingreg0_14__and00001 (
    .I(Reset),
    .O(holdingreg0_14__and00001_914)
  );
  AND2   holdingreg0_14__and00002 (
    .I0(ch0in[14]),
    .I1(holdingreg0_14__and00001_914),
    .O(holdingreg0_14__and0000)
  );
  INV   holdingreg0_15__and00001 (
    .I(Reset),
    .O(holdingreg0_15__and00001_917)
  );
  AND2   holdingreg0_15__and00002 (
    .I0(ch0in[15]),
    .I1(holdingreg0_15__and00001_917),
    .O(holdingreg0_15__and0000)
  );
  AND2   \interDATA_mux0000<7>11  (
    .I0(DCOR0CNTLOWr),
    .I1(holdingreg0[7]),
    .O(\interDATA_mux0000<7>1 )
  );
  INV   \interDATA_mux0000<7>12  (
    .I(DCOR0CNTLOWr),
    .O(\interDATA_mux0000<7>11_1030 )
  );
  AND2   \interDATA_mux0000<7>13  (
    .I0(SFDecomp_21),
    .I1(\interDATA_mux0000<7>11_1030 ),
    .O(\interDATA_mux0000<7>12_1031 )
  );
  OR2   \interDATA_mux0000<7>14  (
    .I0(\interDATA_mux0000<7>1 ),
    .I1(\interDATA_mux0000<7>12_1031 ),
    .O(interDATA_mux0000[7])
  );
  AND2   \interDATA_mux0000<6>11  (
    .I0(DCOR0CNTLOWr),
    .I1(holdingreg0[6]),
    .O(\interDATA_mux0000<6>1 )
  );
  INV   \interDATA_mux0000<6>12  (
    .I(DCOR0CNTLOWr),
    .O(\interDATA_mux0000<6>11_1026 )
  );
  AND2   \interDATA_mux0000<6>13  (
    .I0(SFDecomp_18),
    .I1(\interDATA_mux0000<6>11_1026 ),
    .O(\interDATA_mux0000<6>12_1027 )
  );
  OR2   \interDATA_mux0000<6>14  (
    .I0(\interDATA_mux0000<6>1 ),
    .I1(\interDATA_mux0000<6>12_1027 ),
    .O(interDATA_mux0000[6])
  );
  AND2   \interDATA_mux0000<5>11  (
    .I0(DCOR0CNTLOWr),
    .I1(holdingreg0[5]),
    .O(\interDATA_mux0000<5>1 )
  );
  INV   \interDATA_mux0000<5>12  (
    .I(DCOR0CNTLOWr),
    .O(\interDATA_mux0000<5>11_1022 )
  );
  AND2   \interDATA_mux0000<5>13  (
    .I0(SFDecomp_24),
    .I1(\interDATA_mux0000<5>11_1022 ),
    .O(\interDATA_mux0000<5>12_1023 )
  );
  OR2   \interDATA_mux0000<5>14  (
    .I0(\interDATA_mux0000<5>1 ),
    .I1(\interDATA_mux0000<5>12_1023 ),
    .O(interDATA_mux0000[5])
  );
  AND2   \interDATA_mux0000<4>11  (
    .I0(DCOR0CNTLOWr),
    .I1(holdingreg0[4]),
    .O(\interDATA_mux0000<4>1 )
  );
  INV   \interDATA_mux0000<4>12  (
    .I(DCOR0CNTLOWr),
    .O(\interDATA_mux0000<4>11_1018 )
  );
  AND2   \interDATA_mux0000<4>13  (
    .I0(SFDecomp_27),
    .I1(\interDATA_mux0000<4>11_1018 ),
    .O(\interDATA_mux0000<4>12_1019 )
  );
  OR2   \interDATA_mux0000<4>14  (
    .I0(\interDATA_mux0000<4>1 ),
    .I1(\interDATA_mux0000<4>12_1019 ),
    .O(interDATA_mux0000[4])
  );
  AND2   \interDATA_mux0000<3>11  (
    .I0(DCOR0CNTLOWr),
    .I1(holdingreg0[3]),
    .O(\interDATA_mux0000<3>1 )
  );
  INV   \interDATA_mux0000<3>12  (
    .I(DCOR0CNTLOWr),
    .O(\interDATA_mux0000<3>11_1014 )
  );
  AND2   \interDATA_mux0000<3>13  (
    .I0(SFDecomp_33),
    .I1(\interDATA_mux0000<3>11_1014 ),
    .O(\interDATA_mux0000<3>12_1015 )
  );
  OR2   \interDATA_mux0000<3>14  (
    .I0(\interDATA_mux0000<3>1 ),
    .I1(\interDATA_mux0000<3>12_1015 ),
    .O(interDATA_mux0000[3])
  );
  AND2   \interDATA_mux0000<2>11  (
    .I0(DCOR0CNTLOWr),
    .I1(holdingreg0[2]),
    .O(\interDATA_mux0000<2>1 )
  );
  INV   \interDATA_mux0000<2>12  (
    .I(DCOR0CNTLOWr),
    .O(\interDATA_mux0000<2>11_1010 )
  );
  AND2   \interDATA_mux0000<2>13  (
    .I0(SFDecomp_36),
    .I1(\interDATA_mux0000<2>11_1010 ),
    .O(\interDATA_mux0000<2>12_1011 )
  );
  OR2   \interDATA_mux0000<2>14  (
    .I0(\interDATA_mux0000<2>1 ),
    .I1(\interDATA_mux0000<2>12_1011 ),
    .O(interDATA_mux0000[2])
  );
  AND2   \interDATA_mux0000<1>11  (
    .I0(DCOR0CNTLOWr),
    .I1(holdingreg0[1]),
    .O(\interDATA_mux0000<1>1 )
  );
  INV   \interDATA_mux0000<1>12  (
    .I(DCOR0CNTLOWr),
    .O(\interDATA_mux0000<1>11_1006 )
  );
  AND2   \interDATA_mux0000<1>13  (
    .I0(SFDecomp_30),
    .I1(\interDATA_mux0000<1>11_1006 ),
    .O(\interDATA_mux0000<1>12_1007 )
  );
  OR2   \interDATA_mux0000<1>14  (
    .I0(\interDATA_mux0000<1>1 ),
    .I1(\interDATA_mux0000<1>12_1007 ),
    .O(interDATA_mux0000[1])
  );
  AND2   \interDATA_mux0000<0>11  (
    .I0(DCOR0CNTLOWr),
    .I1(holdingreg0[0]),
    .O(\interDATA_mux0000<0>1 )
  );
  INV   \interDATA_mux0000<0>12  (
    .I(DCOR0CNTLOWr),
    .O(\interDATA_mux0000<0>11_1002 )
  );
  AND2   \interDATA_mux0000<0>13  (
    .I0(SFDecomp_39),
    .I1(\interDATA_mux0000<0>11_1002 ),
    .O(\interDATA_mux0000<0>12_1003 )
  );
  OR2   \interDATA_mux0000<0>14  (
    .I0(\interDATA_mux0000<0>1 ),
    .I1(\interDATA_mux0000<0>12_1003 ),
    .O(interDATA_mux0000[0])
  );
  OR4   interDATA_not000111 (
    .I0(DCOR0CNTHIGHr),
    .I1(DCOR1CNTHIGHr),
    .I2(DCOR0CNTLOWr),
    .I3(DCOR1CNTLOWr),
    .O(interDATA_not0001)
  );
  AND2   SFDecomp_161 (
    .I0(DCOR0CNTHIGHr),
    .I1(holdingreg0[14]),
    .O(SFDecomp_161_798)
  );
  INV   SFDecomp_162 (
    .I(DCOR0CNTHIGHr),
    .O(SFDecomp_162_799)
  );
  AND2   SFDecomp_163 (
    .I0(holdingreg1[14]),
    .I1(SFDecomp_162_799),
    .O(SFDecomp_163_800)
  );
  OR2   SFDecomp_164 (
    .I0(SFDecomp_161_798),
    .I1(SFDecomp_163_800),
    .O(SFDecomp_16)
  );
  AND2   SFDecomp_181 (
    .I0(DCOR1CNTLOWr),
    .I1(holdingreg1[6]),
    .O(SFDecomp_181_802)
  );
  INV   SFDecomp_182 (
    .I(DCOR1CNTLOWr),
    .O(SFDecomp_182_803)
  );
  AND2   SFDecomp_183 (
    .I0(SFDecomp_16),
    .I1(SFDecomp_182_803),
    .O(SFDecomp_183_804)
  );
  OR2   SFDecomp_184 (
    .I0(SFDecomp_181_802),
    .I1(SFDecomp_183_804),
    .O(SFDecomp_18)
  );
  AND2   SFDecomp_191 (
    .I0(DCOR0CNTHIGHr),
    .I1(holdingreg0[15]),
    .O(SFDecomp_191_806)
  );
  INV   SFDecomp_192 (
    .I(DCOR0CNTHIGHr),
    .O(SFDecomp_192_807)
  );
  AND2   SFDecomp_193 (
    .I0(holdingreg1[15]),
    .I1(SFDecomp_192_807),
    .O(SFDecomp_193_808)
  );
  OR2   SFDecomp_194 (
    .I0(SFDecomp_191_806),
    .I1(SFDecomp_193_808),
    .O(SFDecomp_19)
  );
  AND2   SFDecomp_211 (
    .I0(DCOR1CNTLOWr),
    .I1(holdingreg1[7]),
    .O(SFDecomp_211_810)
  );
  INV   SFDecomp_212 (
    .I(DCOR1CNTLOWr),
    .O(SFDecomp_212_811)
  );
  AND2   SFDecomp_213 (
    .I0(SFDecomp_19),
    .I1(SFDecomp_212_811),
    .O(SFDecomp_213_812)
  );
  OR2   SFDecomp_214 (
    .I0(SFDecomp_211_810),
    .I1(SFDecomp_213_812),
    .O(SFDecomp_21)
  );
  AND2   SFDecomp_221 (
    .I0(DCOR0CNTHIGHr),
    .I1(holdingreg0[13]),
    .O(SFDecomp_221_814)
  );
  INV   SFDecomp_222 (
    .I(DCOR0CNTHIGHr),
    .O(SFDecomp_222_815)
  );
  AND2   SFDecomp_223 (
    .I0(holdingreg1[13]),
    .I1(SFDecomp_222_815),
    .O(SFDecomp_223_816)
  );
  OR2   SFDecomp_224 (
    .I0(SFDecomp_221_814),
    .I1(SFDecomp_223_816),
    .O(SFDecomp_22)
  );
  AND2   SFDecomp_241 (
    .I0(DCOR1CNTLOWr),
    .I1(holdingreg1[5]),
    .O(SFDecomp_241_818)
  );
  INV   SFDecomp_242 (
    .I(DCOR1CNTLOWr),
    .O(SFDecomp_242_819)
  );
  AND2   SFDecomp_243 (
    .I0(SFDecomp_22),
    .I1(SFDecomp_242_819),
    .O(SFDecomp_243_820)
  );
  OR2   SFDecomp_244 (
    .I0(SFDecomp_241_818),
    .I1(SFDecomp_243_820),
    .O(SFDecomp_24)
  );
  AND2   SFDecomp_251 (
    .I0(DCOR0CNTHIGHr),
    .I1(holdingreg0[12]),
    .O(SFDecomp_251_822)
  );
  INV   SFDecomp_252 (
    .I(DCOR0CNTHIGHr),
    .O(SFDecomp_252_823)
  );
  AND2   SFDecomp_253 (
    .I0(holdingreg1[12]),
    .I1(SFDecomp_252_823),
    .O(SFDecomp_253_824)
  );
  OR2   SFDecomp_254 (
    .I0(SFDecomp_251_822),
    .I1(SFDecomp_253_824),
    .O(SFDecomp_25)
  );
  AND2   SFDecomp_271 (
    .I0(DCOR1CNTLOWr),
    .I1(holdingreg1[4]),
    .O(SFDecomp_271_826)
  );
  INV   SFDecomp_272 (
    .I(DCOR1CNTLOWr),
    .O(SFDecomp_272_827)
  );
  AND2   SFDecomp_273 (
    .I0(SFDecomp_25),
    .I1(SFDecomp_272_827),
    .O(SFDecomp_273_828)
  );
  OR2   SFDecomp_274 (
    .I0(SFDecomp_271_826),
    .I1(SFDecomp_273_828),
    .O(SFDecomp_27)
  );
  AND2   SFDecomp_281 (
    .I0(DCOR0CNTHIGHr),
    .I1(holdingreg0[9]),
    .O(SFDecomp_281_830)
  );
  INV   SFDecomp_282 (
    .I(DCOR0CNTHIGHr),
    .O(SFDecomp_282_831)
  );
  AND2   SFDecomp_283 (
    .I0(holdingreg1[9]),
    .I1(SFDecomp_282_831),
    .O(SFDecomp_283_832)
  );
  OR2   SFDecomp_284 (
    .I0(SFDecomp_281_830),
    .I1(SFDecomp_283_832),
    .O(SFDecomp_28)
  );
  AND2   SFDecomp_301 (
    .I0(DCOR1CNTLOWr),
    .I1(holdingreg1[1]),
    .O(SFDecomp_301_834)
  );
  INV   SFDecomp_302 (
    .I(DCOR1CNTLOWr),
    .O(SFDecomp_302_835)
  );
  AND2   SFDecomp_303 (
    .I0(SFDecomp_28),
    .I1(SFDecomp_302_835),
    .O(SFDecomp_303_836)
  );
  OR2   SFDecomp_304 (
    .I0(SFDecomp_301_834),
    .I1(SFDecomp_303_836),
    .O(SFDecomp_30)
  );
  AND2   SFDecomp_311 (
    .I0(DCOR0CNTHIGHr),
    .I1(holdingreg0[11]),
    .O(SFDecomp_311_838)
  );
  INV   SFDecomp_312 (
    .I(DCOR0CNTHIGHr),
    .O(SFDecomp_312_839)
  );
  AND2   SFDecomp_313 (
    .I0(holdingreg1[11]),
    .I1(SFDecomp_312_839),
    .O(SFDecomp_313_840)
  );
  OR2   SFDecomp_314 (
    .I0(SFDecomp_311_838),
    .I1(SFDecomp_313_840),
    .O(SFDecomp_31)
  );
  AND2   SFDecomp_331 (
    .I0(DCOR1CNTLOWr),
    .I1(holdingreg1[3]),
    .O(SFDecomp_331_842)
  );
  INV   SFDecomp_332 (
    .I(DCOR1CNTLOWr),
    .O(SFDecomp_332_843)
  );
  AND2   SFDecomp_333 (
    .I0(SFDecomp_31),
    .I1(SFDecomp_332_843),
    .O(SFDecomp_333_844)
  );
  OR2   SFDecomp_334 (
    .I0(SFDecomp_331_842),
    .I1(SFDecomp_333_844),
    .O(SFDecomp_33)
  );
  AND2   SFDecomp_341 (
    .I0(DCOR0CNTHIGHr),
    .I1(holdingreg0[10]),
    .O(SFDecomp_341_846)
  );
  INV   SFDecomp_342 (
    .I(DCOR0CNTHIGHr),
    .O(SFDecomp_342_847)
  );
  AND2   SFDecomp_343 (
    .I0(holdingreg1[10]),
    .I1(SFDecomp_342_847),
    .O(SFDecomp_343_848)
  );
  OR2   SFDecomp_344 (
    .I0(SFDecomp_341_846),
    .I1(SFDecomp_343_848),
    .O(SFDecomp_34)
  );
  AND2   SFDecomp_361 (
    .I0(DCOR1CNTLOWr),
    .I1(holdingreg1[2]),
    .O(SFDecomp_361_850)
  );
  INV   SFDecomp_362 (
    .I(DCOR1CNTLOWr),
    .O(SFDecomp_362_851)
  );
  AND2   SFDecomp_363 (
    .I0(SFDecomp_34),
    .I1(SFDecomp_362_851),
    .O(SFDecomp_363_852)
  );
  OR2   SFDecomp_364 (
    .I0(SFDecomp_361_850),
    .I1(SFDecomp_363_852),
    .O(SFDecomp_36)
  );
  AND2   SFDecomp_371 (
    .I0(DCOR0CNTHIGHr),
    .I1(holdingreg0[8]),
    .O(SFDecomp_371_854)
  );
  INV   SFDecomp_372 (
    .I(DCOR0CNTHIGHr),
    .O(SFDecomp_372_855)
  );
  AND2   SFDecomp_373 (
    .I0(holdingreg1[8]),
    .I1(SFDecomp_372_855),
    .O(SFDecomp_373_856)
  );
  OR2   SFDecomp_374 (
    .I0(SFDecomp_371_854),
    .I1(SFDecomp_373_856),
    .O(SFDecomp_37)
  );
  AND2   SFDecomp_391 (
    .I0(DCOR1CNTLOWr),
    .I1(holdingreg1[0]),
    .O(SFDecomp_391_858)
  );
  INV   SFDecomp_392 (
    .I(DCOR1CNTLOWr),
    .O(SFDecomp_392_859)
  );
  AND2   SFDecomp_393 (
    .I0(SFDecomp_37),
    .I1(SFDecomp_392_859),
    .O(SFDecomp_393_860)
  );
  OR2   SFDecomp_394 (
    .I0(SFDecomp_391_858),
    .I1(SFDecomp_393_860),
    .O(SFDecomp_39)
  );
endmodule

module Decode_INST_1 (
  ce, Reset, updown, phaseA, phaseB, Sclk
);
  output ce;
  input Reset;
  output updown;
  input phaseA;
  input phaseB;
  input Sclk;
  wire CurrState_Sreg0_FSM_FFd1_700;
  wire CurrState_Sreg0_FSM_FFd1_N2;
  wire CurrState_Sreg0_FSM_FFd1_N21_702;
  wire CurrState_Sreg0_FSM_FFd1_N211_703;
  wire CurrState_Sreg0_FSM_FFd1_N22_704;
  wire CurrState_Sreg0_FSM_FFd1_N23_705;
  wire CurrState_Sreg0_FSM_FFd1_N24_706;
  wire CurrState_Sreg0_FSM_FFd1_N25_707;
  wire CurrState_Sreg0_FSM_FFd1_N2_bdd0;
  wire CurrState_Sreg0_FSM_FFd2_709;
  wire CurrState_Sreg0_FSM_FFd2_N2;
  wire CurrState_Sreg0_FSM_FFd2_N21_711;
  wire CurrState_Sreg0_FSM_FFd2_N211_712;
  wire CurrState_Sreg0_FSM_FFd2_N22_713;
  wire CurrState_Sreg0_FSM_FFd2_N23_714;
  wire CurrState_Sreg0_FSM_FFd2_N231_715;
  wire CurrState_Sreg0_FSM_FFd2_N24_716;
  wire CurrState_Sreg0_FSM_FFd2_N25;
  wire CurrState_Sreg0_FSM_FFd2_N251_718;
  wire CurrState_Sreg0_FSM_FFd2_N252_719;
  wire CurrState_Sreg0_FSM_FFd2_N253_720;
  wire CurrState_Sreg0_FSM_FFd2_N254_721;
  wire CurrState_Sreg0_FSM_FFd2_N255_722;
  wire CurrState_Sreg0_FSM_FFd2_N26;
  wire CurrState_Sreg0_FSM_FFd2_N2_bdd0;
  wire CurrState_Sreg0_FSM_FFd2_N2_bdd1;
  wire CurrState_Sreg0_FSM_FFd2_N2_bdd2;
  wire CurrState_Sreg0_FSM_FFd3_727;
  wire CurrState_Sreg0_FSM_FFd3_N2;
  wire CurrState_Sreg0_FSM_FFd3_N21_729;
  wire CurrState_Sreg0_FSM_FFd3_N22_730;
  wire CurrState_Sreg0_FSM_FFd3_N23_731;
  wire CurrState_Sreg0_FSM_FFd3_N231_732;
  wire CurrState_Sreg0_FSM_FFd3_N232_733;
  wire CurrState_Sreg0_FSM_FFd3_N233_734;
  wire CurrState_Sreg0_FSM_FFd3_N234_735;
  wire CurrState_Sreg0_FSM_FFd3_N24_736;
  wire CurrState_Sreg0_FSM_FFd3_N241_737;
  wire CurrState_Sreg0_FSM_FFd3_N242_738;
  wire CurrState_Sreg0_FSM_FFd3_N243_739;
  wire CurrState_Sreg0_FSM_FFd3_N244_740;
  wire CurrState_Sreg0_FSM_FFd3_N25;
  wire CurrState_Sreg0_FSM_FFd3_N2_bdd0;
  wire CurrState_Sreg0_FSM_FFd3_N2_bdd1;
  wire CurrState_Sreg0_FSM_FFd3_N2_bdd2;
  wire CurrState_Sreg0_FSM_FFd4_745;
  wire CurrState_Sreg0_FSM_FFd4_N2;
  wire CurrState_Sreg0_FSM_FFd4_N21_747;
  wire CurrState_Sreg0_FSM_FFd4_N210_748;
  wire CurrState_Sreg0_FSM_FFd4_N211_749;
  wire CurrState_Sreg0_FSM_FFd4_N22_750;
  wire CurrState_Sreg0_FSM_FFd4_N23_751;
  wire CurrState_Sreg0_FSM_FFd4_N24_752;
  wire CurrState_Sreg0_FSM_FFd4_N25_753;
  wire CurrState_Sreg0_FSM_FFd4_N26_754;
  wire CurrState_Sreg0_FSM_FFd4_N27_755;
  wire CurrState_Sreg0_FSM_FFd4_N28_756;
  wire CurrState_Sreg0_FSM_FFd4_N29_757;
  wire CurrState_Sreg0_FSM_FFd4_N2_bdd0;
  wire SFDecomp_10;
  wire SFDecomp_101_761;
  wire SFDecomp_102_762;
  wire SFDecomp_6;
  wire SFDecomp_61_764;
  wire SFDecomp_62_765;
  wire SFDecomp_63_766;
  wire SFDecomp_7;
  wire SFDecomp_71_768;
  wire SFDecomp_72_769;
  wire SFDecomp_9;
  wire SFDecomp_91_771;
  wire SFDecomp_92_772;
  wire SFDecomp_93_773;
  wire ce1_776;
  wire ce2_777;
  wire ce3_778;
  wire updown1_782;
  wire updown2_783;
  wire updown3_784;
  wire updown4_785;
  wire updown5_786;
  wire updown6_787;
  wire updown7_788;
  wire updown8_789;
  FD   CurrState_Sreg0_FSM_FFd1 (
    .C(Sclk),
    .D(CurrState_Sreg0_FSM_FFd1_N2),
    .Q(CurrState_Sreg0_FSM_FFd1_700)
  );
  FD   CurrState_Sreg0_FSM_FFd2 (
    .C(Sclk),
    .D(CurrState_Sreg0_FSM_FFd2_N2),
    .Q(CurrState_Sreg0_FSM_FFd2_709)
  );
  FD   CurrState_Sreg0_FSM_FFd3 (
    .C(Sclk),
    .D(CurrState_Sreg0_FSM_FFd3_N2),
    .Q(CurrState_Sreg0_FSM_FFd3_727)
  );
  FD   CurrState_Sreg0_FSM_FFd4 (
    .C(Sclk),
    .D(CurrState_Sreg0_FSM_FFd4_N2),
    .Q(CurrState_Sreg0_FSM_FFd4_745)
  );
  INV   ce1 (
    .I(CurrState_Sreg0_FSM_FFd3_727),
    .O(ce1_776)
  );
  INV   ce2 (
    .I(CurrState_Sreg0_FSM_FFd4_745),
    .O(ce2_777)
  );
  AND3   ce3 (
    .I0(ce1_776),
    .I1(CurrState_Sreg0_FSM_FFd2_709),
    .I2(ce2_777),
    .O(ce3_778)
  );
  OR2   ce4 (
    .I0(CurrState_Sreg0_FSM_FFd1_700),
    .I1(ce3_778),
    .O(ce)
  );
  INV   updown1 (
    .I(CurrState_Sreg0_FSM_FFd3_727),
    .O(updown1_782)
  );
  INV   updown2 (
    .I(CurrState_Sreg0_FSM_FFd3_727),
    .O(updown2_783)
  );
  INV   updown3 (
    .I(CurrState_Sreg0_FSM_FFd1_700),
    .O(updown3_784)
  );
  INV   updown4 (
    .I(CurrState_Sreg0_FSM_FFd4_745),
    .O(updown4_785)
  );
  INV   updown5 (
    .I(CurrState_Sreg0_FSM_FFd2_709),
    .O(updown5_786)
  );
  AND2   updown6 (
    .I0(CurrState_Sreg0_FSM_FFd4_745),
    .I1(updown1_782),
    .O(updown6_787)
  );
  AND3   updown7 (
    .I0(updown2_783),
    .I1(CurrState_Sreg0_FSM_FFd2_709),
    .I2(updown3_784),
    .O(updown7_788)
  );
  AND3   updown8 (
    .I0(updown4_785),
    .I1(CurrState_Sreg0_FSM_FFd3_727),
    .I2(updown5_786),
    .O(updown8_789)
  );
  OR3   updown9 (
    .I0(updown7_788),
    .I1(updown6_787),
    .I2(updown8_789),
    .O(updown)
  );
  INV   CurrState_Sreg0_FSM_FFd4_N211 (
    .I(CurrState_Sreg0_FSM_FFd3_727),
    .O(CurrState_Sreg0_FSM_FFd4_N21_747)
  );
  INV   CurrState_Sreg0_FSM_FFd4_N212 (
    .I(CurrState_Sreg0_FSM_FFd4_745),
    .O(CurrState_Sreg0_FSM_FFd4_N211_749)
  );
  AND3   CurrState_Sreg0_FSM_FFd4_N213 (
    .I0(CurrState_Sreg0_FSM_FFd4_N21_747),
    .I1(CurrState_Sreg0_FSM_FFd2_709),
    .I2(CurrState_Sreg0_FSM_FFd4_N211_749),
    .O(CurrState_Sreg0_FSM_FFd4_N2_bdd0)
  );
  INV   CurrState_Sreg0_FSM_FFd4_N21 (
    .I(CurrState_Sreg0_FSM_FFd4_N2_bdd0),
    .O(CurrState_Sreg0_FSM_FFd4_N22_750)
  );
  INV   CurrState_Sreg0_FSM_FFd4_N22 (
    .I(phaseB),
    .O(CurrState_Sreg0_FSM_FFd4_N23_751)
  );
  INV   CurrState_Sreg0_FSM_FFd4_N23 (
    .I(CurrState_Sreg0_FSM_FFd4_N2_bdd0),
    .O(CurrState_Sreg0_FSM_FFd4_N24_752)
  );
  INV   CurrState_Sreg0_FSM_FFd4_N24 (
    .I(phaseA),
    .O(CurrState_Sreg0_FSM_FFd4_N25_753)
  );
  INV   CurrState_Sreg0_FSM_FFd4_N25 (
    .I(Reset),
    .O(CurrState_Sreg0_FSM_FFd4_N26_754)
  );
  AND2   CurrState_Sreg0_FSM_FFd4_N26 (
    .I0(phaseB),
    .I1(CurrState_Sreg0_FSM_FFd4_N22_750),
    .O(CurrState_Sreg0_FSM_FFd4_N27_755)
  );
  AND2   CurrState_Sreg0_FSM_FFd4_N27 (
    .I0(CurrState_Sreg0_FSM_FFd4_N23_751),
    .I1(CurrState_Sreg0_FSM_FFd4_N24_752),
    .O(CurrState_Sreg0_FSM_FFd4_N28_756)
  );
  OR2   CurrState_Sreg0_FSM_FFd4_N28 (
    .I0(phaseA),
    .I1(CurrState_Sreg0_FSM_FFd4_N27_755),
    .O(CurrState_Sreg0_FSM_FFd4_N29_757)
  );
  OR2   CurrState_Sreg0_FSM_FFd4_N29 (
    .I0(CurrState_Sreg0_FSM_FFd4_N28_756),
    .I1(CurrState_Sreg0_FSM_FFd4_N25_753),
    .O(CurrState_Sreg0_FSM_FFd4_N210_748)
  );
  AND3   CurrState_Sreg0_FSM_FFd4_N210 (
    .I0(CurrState_Sreg0_FSM_FFd4_N210_748),
    .I1(CurrState_Sreg0_FSM_FFd4_N29_757),
    .I2(CurrState_Sreg0_FSM_FFd4_N26_754),
    .O(CurrState_Sreg0_FSM_FFd4_N2)
  );
  OR2   CurrState_Sreg0_FSM_FFd1_N211 (
    .I0(phaseA),
    .I1(phaseB),
    .O(CurrState_Sreg0_FSM_FFd1_N21_702)
  );
  INV   CurrState_Sreg0_FSM_FFd1_N212 (
    .I(CurrState_Sreg0_FSM_FFd4_745),
    .O(CurrState_Sreg0_FSM_FFd1_N211_703)
  );
  OR2   CurrState_Sreg0_FSM_FFd1_N213 (
    .I0(CurrState_Sreg0_FSM_FFd1_N21_702),
    .I1(CurrState_Sreg0_FSM_FFd1_N211_703),
    .O(CurrState_Sreg0_FSM_FFd1_N2_bdd0)
  );
  AND2   CurrState_Sreg0_FSM_FFd1_N21 (
    .I0(CurrState_Sreg0_FSM_FFd2_709),
    .I1(CurrState_Sreg0_FSM_FFd3_727),
    .O(CurrState_Sreg0_FSM_FFd1_N22_704)
  );
  INV   CurrState_Sreg0_FSM_FFd1_N22 (
    .I(Reset),
    .O(CurrState_Sreg0_FSM_FFd1_N23_705)
  );
  INV   CurrState_Sreg0_FSM_FFd1_N23 (
    .I(CurrState_Sreg0_FSM_FFd1_N2_bdd0),
    .O(CurrState_Sreg0_FSM_FFd1_N24_706)
  );
  AND2   CurrState_Sreg0_FSM_FFd1_N24 (
    .I0(CurrState_Sreg0_FSM_FFd1_N23_705),
    .I1(CurrState_Sreg0_FSM_FFd1_N24_706),
    .O(CurrState_Sreg0_FSM_FFd1_N25_707)
  );
  AND2   CurrState_Sreg0_FSM_FFd1_N25 (
    .I0(CurrState_Sreg0_FSM_FFd1_N22_704),
    .I1(CurrState_Sreg0_FSM_FFd1_N25_707),
    .O(CurrState_Sreg0_FSM_FFd1_N2)
  );
  AND3   CurrState_Sreg0_FSM_FFd2_N251 (
    .I0(CurrState_Sreg0_FSM_FFd4_745),
    .I1(phaseA),
    .I2(phaseB),
    .O(CurrState_Sreg0_FSM_FFd2_N25)
  );
  INV   CurrState_Sreg0_FSM_FFd2_N252 (
    .I(CurrState_Sreg0_FSM_FFd4_745),
    .O(CurrState_Sreg0_FSM_FFd2_N251_718)
  );
  INV   CurrState_Sreg0_FSM_FFd2_N253 (
    .I(phaseB),
    .O(CurrState_Sreg0_FSM_FFd2_N252_719)
  );
  OR2   CurrState_Sreg0_FSM_FFd2_N254 (
    .I0(phaseA),
    .I1(CurrState_Sreg0_FSM_FFd2_N252_719),
    .O(CurrState_Sreg0_FSM_FFd2_N253_720)
  );
  INV   CurrState_Sreg0_FSM_FFd2_N255 (
    .I(CurrState_Sreg0_FSM_FFd2_N253_720),
    .O(CurrState_Sreg0_FSM_FFd2_N254_721)
  );
  AND2   CurrState_Sreg0_FSM_FFd2_N256 (
    .I0(CurrState_Sreg0_FSM_FFd2_N251_718),
    .I1(CurrState_Sreg0_FSM_FFd2_N254_721),
    .O(CurrState_Sreg0_FSM_FFd2_N255_722)
  );
  OR2   CurrState_Sreg0_FSM_FFd2_N257 (
    .I0(CurrState_Sreg0_FSM_FFd2_N25),
    .I1(CurrState_Sreg0_FSM_FFd2_N255_722),
    .O(CurrState_Sreg0_FSM_FFd2_N2_bdd2)
  );
  AND2   CurrState_Sreg0_FSM_FFd2_N231 (
    .I0(phaseA),
    .I1(phaseB),
    .O(CurrState_Sreg0_FSM_FFd2_N23_714)
  );
  INV   CurrState_Sreg0_FSM_FFd2_N232 (
    .I(CurrState_Sreg0_FSM_FFd2_N23_714),
    .O(CurrState_Sreg0_FSM_FFd2_N231_715)
  );
  AND2   CurrState_Sreg0_FSM_FFd2_N233 (
    .I0(CurrState_Sreg0_FSM_FFd4_745),
    .I1(CurrState_Sreg0_FSM_FFd2_N231_715),
    .O(CurrState_Sreg0_FSM_FFd2_N2_bdd1)
  );
  OR2   CurrState_Sreg0_FSM_FFd2_N211 (
    .I0(phaseA),
    .I1(CurrState_Sreg0_FSM_FFd4_745),
    .O(CurrState_Sreg0_FSM_FFd2_N21_711)
  );
  INV   CurrState_Sreg0_FSM_FFd2_N212 (
    .I(phaseB),
    .O(CurrState_Sreg0_FSM_FFd2_N211_712)
  );
  OR2   CurrState_Sreg0_FSM_FFd2_N213 (
    .I0(CurrState_Sreg0_FSM_FFd2_N21_711),
    .I1(CurrState_Sreg0_FSM_FFd2_N211_712),
    .O(CurrState_Sreg0_FSM_FFd2_N2_bdd0)
  );
  AND2   CurrState_Sreg0_FSM_FFd2_N21 (
    .I0(SFDecomp_6),
    .I1(CurrState_Sreg0_FSM_FFd2_709),
    .O(CurrState_Sreg0_FSM_FFd2_N22_713)
  );
  INV   CurrState_Sreg0_FSM_FFd2_N22 (
    .I(Reset),
    .O(CurrState_Sreg0_FSM_FFd2_N24_716)
  );
  OR2   CurrState_Sreg0_FSM_FFd2_N23 (
    .I0(SFDecomp_7),
    .I1(CurrState_Sreg0_FSM_FFd2_N22_713),
    .O(CurrState_Sreg0_FSM_FFd2_N26)
  );
  AND2   CurrState_Sreg0_FSM_FFd2_N24 (
    .I0(CurrState_Sreg0_FSM_FFd2_N26),
    .I1(CurrState_Sreg0_FSM_FFd2_N24_716),
    .O(CurrState_Sreg0_FSM_FFd2_N2)
  );
  AND2   CurrState_Sreg0_FSM_FFd3_N241 (
    .I0(phaseA),
    .I1(CurrState_Sreg0_FSM_FFd4_745),
    .O(CurrState_Sreg0_FSM_FFd3_N24_736)
  );
  INV   CurrState_Sreg0_FSM_FFd3_N242 (
    .I(phaseA),
    .O(CurrState_Sreg0_FSM_FFd3_N241_737)
  );
  OR2   CurrState_Sreg0_FSM_FFd3_N243 (
    .I0(CurrState_Sreg0_FSM_FFd4_745),
    .I1(CurrState_Sreg0_FSM_FFd2_709),
    .O(CurrState_Sreg0_FSM_FFd3_N242_738)
  );
  INV   CurrState_Sreg0_FSM_FFd3_N244 (
    .I(CurrState_Sreg0_FSM_FFd3_N242_738),
    .O(CurrState_Sreg0_FSM_FFd3_N243_739)
  );
  AND2   CurrState_Sreg0_FSM_FFd3_N245 (
    .I0(CurrState_Sreg0_FSM_FFd3_N241_737),
    .I1(CurrState_Sreg0_FSM_FFd3_N243_739),
    .O(CurrState_Sreg0_FSM_FFd3_N244_740)
  );
  OR2   CurrState_Sreg0_FSM_FFd3_N246 (
    .I0(CurrState_Sreg0_FSM_FFd3_N24_736),
    .I1(CurrState_Sreg0_FSM_FFd3_N244_740),
    .O(CurrState_Sreg0_FSM_FFd3_N2_bdd2)
  );
  OR2   CurrState_Sreg0_FSM_FFd3_N231 (
    .I0(CurrState_Sreg0_FSM_FFd4_745),
    .I1(CurrState_Sreg0_FSM_FFd2_709),
    .O(CurrState_Sreg0_FSM_FFd3_N23_731)
  );
  INV   CurrState_Sreg0_FSM_FFd3_N232 (
    .I(phaseA),
    .O(CurrState_Sreg0_FSM_FFd3_N231_732)
  );
  INV   CurrState_Sreg0_FSM_FFd3_N233 (
    .I(CurrState_Sreg0_FSM_FFd4_745),
    .O(CurrState_Sreg0_FSM_FFd3_N232_733)
  );
  AND2   CurrState_Sreg0_FSM_FFd3_N234 (
    .I0(phaseA),
    .I1(CurrState_Sreg0_FSM_FFd3_N23_731),
    .O(CurrState_Sreg0_FSM_FFd3_N233_734)
  );
  AND2   CurrState_Sreg0_FSM_FFd3_N235 (
    .I0(CurrState_Sreg0_FSM_FFd3_N231_732),
    .I1(CurrState_Sreg0_FSM_FFd3_N232_733),
    .O(CurrState_Sreg0_FSM_FFd3_N234_735)
  );
  OR2   CurrState_Sreg0_FSM_FFd3_N236 (
    .I0(CurrState_Sreg0_FSM_FFd3_N233_734),
    .I1(CurrState_Sreg0_FSM_FFd3_N234_735),
    .O(CurrState_Sreg0_FSM_FFd3_N2_bdd1)
  );
  OR3   CurrState_Sreg0_FSM_FFd3_N211 (
    .I0(phaseA),
    .I1(CurrState_Sreg0_FSM_FFd4_745),
    .I2(CurrState_Sreg0_FSM_FFd2_709),
    .O(CurrState_Sreg0_FSM_FFd3_N2_bdd0)
  );
  AND2   CurrState_Sreg0_FSM_FFd3_N21 (
    .I0(SFDecomp_9),
    .I1(CurrState_Sreg0_FSM_FFd3_727),
    .O(CurrState_Sreg0_FSM_FFd3_N21_729)
  );
  INV   CurrState_Sreg0_FSM_FFd3_N22 (
    .I(Reset),
    .O(CurrState_Sreg0_FSM_FFd3_N22_730)
  );
  OR2   CurrState_Sreg0_FSM_FFd3_N23 (
    .I0(SFDecomp_10),
    .I1(CurrState_Sreg0_FSM_FFd3_N21_729),
    .O(CurrState_Sreg0_FSM_FFd3_N25)
  );
  AND2   CurrState_Sreg0_FSM_FFd3_N24 (
    .I0(CurrState_Sreg0_FSM_FFd3_N25),
    .I1(CurrState_Sreg0_FSM_FFd3_N22_730),
    .O(CurrState_Sreg0_FSM_FFd3_N2)
  );
  AND2   SFDecomp_61 (
    .I0(CurrState_Sreg0_FSM_FFd3_727),
    .I1(CurrState_Sreg0_FSM_FFd2_N2_bdd0),
    .O(SFDecomp_61_764)
  );
  INV   SFDecomp_62 (
    .I(CurrState_Sreg0_FSM_FFd3_727),
    .O(SFDecomp_62_765)
  );
  AND2   SFDecomp_63 (
    .I0(CurrState_Sreg0_FSM_FFd2_N2_bdd1),
    .I1(SFDecomp_62_765),
    .O(SFDecomp_63_766)
  );
  OR2   SFDecomp_64 (
    .I0(SFDecomp_61_764),
    .I1(SFDecomp_63_766),
    .O(SFDecomp_6)
  );
  AND2   SFDecomp_71 (
    .I0(CurrState_Sreg0_FSM_FFd3_727),
    .I1(CurrState_Sreg0_FSM_FFd2_N2_bdd2),
    .O(SFDecomp_71_768)
  );
  INV   SFDecomp_72 (
    .I(CurrState_Sreg0_FSM_FFd2_709),
    .O(SFDecomp_72_769)
  );
  AND2   SFDecomp_73 (
    .I0(SFDecomp_71_768),
    .I1(SFDecomp_72_769),
    .O(SFDecomp_7)
  );
  AND2   SFDecomp_91 (
    .I0(phaseB),
    .I1(CurrState_Sreg0_FSM_FFd3_N2_bdd0),
    .O(SFDecomp_91_771)
  );
  INV   SFDecomp_92 (
    .I(phaseB),
    .O(SFDecomp_92_772)
  );
  AND2   SFDecomp_93 (
    .I0(CurrState_Sreg0_FSM_FFd3_N2_bdd1),
    .I1(SFDecomp_92_772),
    .O(SFDecomp_93_773)
  );
  OR2   SFDecomp_94 (
    .I0(SFDecomp_91_771),
    .I1(SFDecomp_93_773),
    .O(SFDecomp_9)
  );
  AND2   SFDecomp_101 (
    .I0(phaseB),
    .I1(CurrState_Sreg0_FSM_FFd3_N2_bdd2),
    .O(SFDecomp_101_761)
  );
  INV   SFDecomp_102 (
    .I(CurrState_Sreg0_FSM_FFd3_727),
    .O(SFDecomp_102_762)
  );
  AND2   SFDecomp_103 (
    .I0(SFDecomp_101_761),
    .I1(SFDecomp_102_762),
    .O(SFDecomp_10)
  );
endmodule

module Decode (
  ce, Reset, updown, phaseA, phaseB, Sclk
);
  output ce;
  input Reset;
  output updown;
  input phaseA;
  input phaseB;
  input Sclk;
  wire CurrState_Sreg0_FSM_FFd1_610;
  wire CurrState_Sreg0_FSM_FFd1_N2;
  wire CurrState_Sreg0_FSM_FFd1_N21_612;
  wire CurrState_Sreg0_FSM_FFd1_N211_613;
  wire CurrState_Sreg0_FSM_FFd1_N22_614;
  wire CurrState_Sreg0_FSM_FFd1_N23_615;
  wire CurrState_Sreg0_FSM_FFd1_N24_616;
  wire CurrState_Sreg0_FSM_FFd1_N25_617;
  wire CurrState_Sreg0_FSM_FFd1_N2_bdd0;
  wire CurrState_Sreg0_FSM_FFd2_619;
  wire CurrState_Sreg0_FSM_FFd2_N2;
  wire CurrState_Sreg0_FSM_FFd2_N21_621;
  wire CurrState_Sreg0_FSM_FFd2_N211_622;
  wire CurrState_Sreg0_FSM_FFd2_N22_623;
  wire CurrState_Sreg0_FSM_FFd2_N23_624;
  wire CurrState_Sreg0_FSM_FFd2_N231_625;
  wire CurrState_Sreg0_FSM_FFd2_N24_626;
  wire CurrState_Sreg0_FSM_FFd2_N25;
  wire CurrState_Sreg0_FSM_FFd2_N251_628;
  wire CurrState_Sreg0_FSM_FFd2_N252_629;
  wire CurrState_Sreg0_FSM_FFd2_N253_630;
  wire CurrState_Sreg0_FSM_FFd2_N254_631;
  wire CurrState_Sreg0_FSM_FFd2_N255_632;
  wire CurrState_Sreg0_FSM_FFd2_N26;
  wire CurrState_Sreg0_FSM_FFd2_N2_bdd0;
  wire CurrState_Sreg0_FSM_FFd2_N2_bdd1;
  wire CurrState_Sreg0_FSM_FFd2_N2_bdd2;
  wire CurrState_Sreg0_FSM_FFd3_637;
  wire CurrState_Sreg0_FSM_FFd3_N2;
  wire CurrState_Sreg0_FSM_FFd3_N21_639;
  wire CurrState_Sreg0_FSM_FFd3_N22_640;
  wire CurrState_Sreg0_FSM_FFd3_N23_641;
  wire CurrState_Sreg0_FSM_FFd3_N231_642;
  wire CurrState_Sreg0_FSM_FFd3_N232_643;
  wire CurrState_Sreg0_FSM_FFd3_N233_644;
  wire CurrState_Sreg0_FSM_FFd3_N234_645;
  wire CurrState_Sreg0_FSM_FFd3_N24_646;
  wire CurrState_Sreg0_FSM_FFd3_N241_647;
  wire CurrState_Sreg0_FSM_FFd3_N242_648;
  wire CurrState_Sreg0_FSM_FFd3_N243_649;
  wire CurrState_Sreg0_FSM_FFd3_N244_650;
  wire CurrState_Sreg0_FSM_FFd3_N25;
  wire CurrState_Sreg0_FSM_FFd3_N2_bdd0;
  wire CurrState_Sreg0_FSM_FFd3_N2_bdd1;
  wire CurrState_Sreg0_FSM_FFd3_N2_bdd2;
  wire CurrState_Sreg0_FSM_FFd4_655;
  wire CurrState_Sreg0_FSM_FFd4_N2;
  wire CurrState_Sreg0_FSM_FFd4_N21_657;
  wire CurrState_Sreg0_FSM_FFd4_N210_658;
  wire CurrState_Sreg0_FSM_FFd4_N211_659;
  wire CurrState_Sreg0_FSM_FFd4_N22_660;
  wire CurrState_Sreg0_FSM_FFd4_N23_661;
  wire CurrState_Sreg0_FSM_FFd4_N24_662;
  wire CurrState_Sreg0_FSM_FFd4_N25_663;
  wire CurrState_Sreg0_FSM_FFd4_N26_664;
  wire CurrState_Sreg0_FSM_FFd4_N27_665;
  wire CurrState_Sreg0_FSM_FFd4_N28_666;
  wire CurrState_Sreg0_FSM_FFd4_N29_667;
  wire CurrState_Sreg0_FSM_FFd4_N2_bdd0;
  wire SFDecomp_10;
  wire SFDecomp_101_671;
  wire SFDecomp_102_672;
  wire SFDecomp_6;
  wire SFDecomp_61_674;
  wire SFDecomp_62_675;
  wire SFDecomp_63_676;
  wire SFDecomp_7;
  wire SFDecomp_71_678;
  wire SFDecomp_72_679;
  wire SFDecomp_9;
  wire SFDecomp_91_681;
  wire SFDecomp_92_682;
  wire SFDecomp_93_683;
  wire ce1_686;
  wire ce2_687;
  wire ce3_688;
  wire updown1_692;
  wire updown2_693;
  wire updown3_694;
  wire updown4_695;
  wire updown5_696;
  wire updown6_697;
  wire updown7_698;
  wire updown8_699;
  FD   CurrState_Sreg0_FSM_FFd1 (
    .C(Sclk),
    .D(CurrState_Sreg0_FSM_FFd1_N2),
    .Q(CurrState_Sreg0_FSM_FFd1_610)
  );
  FD   CurrState_Sreg0_FSM_FFd2 (
    .C(Sclk),
    .D(CurrState_Sreg0_FSM_FFd2_N2),
    .Q(CurrState_Sreg0_FSM_FFd2_619)
  );
  FD   CurrState_Sreg0_FSM_FFd3 (
    .C(Sclk),
    .D(CurrState_Sreg0_FSM_FFd3_N2),
    .Q(CurrState_Sreg0_FSM_FFd3_637)
  );
  FD   CurrState_Sreg0_FSM_FFd4 (
    .C(Sclk),
    .D(CurrState_Sreg0_FSM_FFd4_N2),
    .Q(CurrState_Sreg0_FSM_FFd4_655)
  );
  INV   ce1 (
    .I(CurrState_Sreg0_FSM_FFd3_637),
    .O(ce1_686)
  );
  INV   ce2 (
    .I(CurrState_Sreg0_FSM_FFd4_655),
    .O(ce2_687)
  );
  AND3   ce3 (
    .I0(ce1_686),
    .I1(CurrState_Sreg0_FSM_FFd2_619),
    .I2(ce2_687),
    .O(ce3_688)
  );
  OR2   ce4 (
    .I0(CurrState_Sreg0_FSM_FFd1_610),
    .I1(ce3_688),
    .O(ce)
  );
  INV   updown1 (
    .I(CurrState_Sreg0_FSM_FFd3_637),
    .O(updown1_692)
  );
  INV   updown2 (
    .I(CurrState_Sreg0_FSM_FFd3_637),
    .O(updown2_693)
  );
  INV   updown3 (
    .I(CurrState_Sreg0_FSM_FFd1_610),
    .O(updown3_694)
  );
  INV   updown4 (
    .I(CurrState_Sreg0_FSM_FFd4_655),
    .O(updown4_695)
  );
  INV   updown5 (
    .I(CurrState_Sreg0_FSM_FFd2_619),
    .O(updown5_696)
  );
  AND2   updown6 (
    .I0(CurrState_Sreg0_FSM_FFd4_655),
    .I1(updown1_692),
    .O(updown6_697)
  );
  AND3   updown7 (
    .I0(updown2_693),
    .I1(CurrState_Sreg0_FSM_FFd2_619),
    .I2(updown3_694),
    .O(updown7_698)
  );
  AND3   updown8 (
    .I0(updown4_695),
    .I1(CurrState_Sreg0_FSM_FFd3_637),
    .I2(updown5_696),
    .O(updown8_699)
  );
  OR3   updown9 (
    .I0(updown7_698),
    .I1(updown6_697),
    .I2(updown8_699),
    .O(updown)
  );
  INV   CurrState_Sreg0_FSM_FFd4_N211 (
    .I(CurrState_Sreg0_FSM_FFd3_637),
    .O(CurrState_Sreg0_FSM_FFd4_N21_657)
  );
  INV   CurrState_Sreg0_FSM_FFd4_N212 (
    .I(CurrState_Sreg0_FSM_FFd4_655),
    .O(CurrState_Sreg0_FSM_FFd4_N211_659)
  );
  AND3   CurrState_Sreg0_FSM_FFd4_N213 (
    .I0(CurrState_Sreg0_FSM_FFd4_N21_657),
    .I1(CurrState_Sreg0_FSM_FFd2_619),
    .I2(CurrState_Sreg0_FSM_FFd4_N211_659),
    .O(CurrState_Sreg0_FSM_FFd4_N2_bdd0)
  );
  INV   CurrState_Sreg0_FSM_FFd4_N21 (
    .I(CurrState_Sreg0_FSM_FFd4_N2_bdd0),
    .O(CurrState_Sreg0_FSM_FFd4_N22_660)
  );
  INV   CurrState_Sreg0_FSM_FFd4_N22 (
    .I(phaseB),
    .O(CurrState_Sreg0_FSM_FFd4_N23_661)
  );
  INV   CurrState_Sreg0_FSM_FFd4_N23 (
    .I(CurrState_Sreg0_FSM_FFd4_N2_bdd0),
    .O(CurrState_Sreg0_FSM_FFd4_N24_662)
  );
  INV   CurrState_Sreg0_FSM_FFd4_N24 (
    .I(phaseA),
    .O(CurrState_Sreg0_FSM_FFd4_N25_663)
  );
  INV   CurrState_Sreg0_FSM_FFd4_N25 (
    .I(Reset),
    .O(CurrState_Sreg0_FSM_FFd4_N26_664)
  );
  AND2   CurrState_Sreg0_FSM_FFd4_N26 (
    .I0(phaseB),
    .I1(CurrState_Sreg0_FSM_FFd4_N22_660),
    .O(CurrState_Sreg0_FSM_FFd4_N27_665)
  );
  AND2   CurrState_Sreg0_FSM_FFd4_N27 (
    .I0(CurrState_Sreg0_FSM_FFd4_N23_661),
    .I1(CurrState_Sreg0_FSM_FFd4_N24_662),
    .O(CurrState_Sreg0_FSM_FFd4_N28_666)
  );
  OR2   CurrState_Sreg0_FSM_FFd4_N28 (
    .I0(phaseA),
    .I1(CurrState_Sreg0_FSM_FFd4_N27_665),
    .O(CurrState_Sreg0_FSM_FFd4_N29_667)
  );
  OR2   CurrState_Sreg0_FSM_FFd4_N29 (
    .I0(CurrState_Sreg0_FSM_FFd4_N28_666),
    .I1(CurrState_Sreg0_FSM_FFd4_N25_663),
    .O(CurrState_Sreg0_FSM_FFd4_N210_658)
  );
  AND3   CurrState_Sreg0_FSM_FFd4_N210 (
    .I0(CurrState_Sreg0_FSM_FFd4_N210_658),
    .I1(CurrState_Sreg0_FSM_FFd4_N29_667),
    .I2(CurrState_Sreg0_FSM_FFd4_N26_664),
    .O(CurrState_Sreg0_FSM_FFd4_N2)
  );
  OR2   CurrState_Sreg0_FSM_FFd1_N211 (
    .I0(phaseA),
    .I1(phaseB),
    .O(CurrState_Sreg0_FSM_FFd1_N21_612)
  );
  INV   CurrState_Sreg0_FSM_FFd1_N212 (
    .I(CurrState_Sreg0_FSM_FFd4_655),
    .O(CurrState_Sreg0_FSM_FFd1_N211_613)
  );
  OR2   CurrState_Sreg0_FSM_FFd1_N213 (
    .I0(CurrState_Sreg0_FSM_FFd1_N21_612),
    .I1(CurrState_Sreg0_FSM_FFd1_N211_613),
    .O(CurrState_Sreg0_FSM_FFd1_N2_bdd0)
  );
  AND2   CurrState_Sreg0_FSM_FFd1_N21 (
    .I0(CurrState_Sreg0_FSM_FFd2_619),
    .I1(CurrState_Sreg0_FSM_FFd3_637),
    .O(CurrState_Sreg0_FSM_FFd1_N22_614)
  );
  INV   CurrState_Sreg0_FSM_FFd1_N22 (
    .I(Reset),
    .O(CurrState_Sreg0_FSM_FFd1_N23_615)
  );
  INV   CurrState_Sreg0_FSM_FFd1_N23 (
    .I(CurrState_Sreg0_FSM_FFd1_N2_bdd0),
    .O(CurrState_Sreg0_FSM_FFd1_N24_616)
  );
  AND2   CurrState_Sreg0_FSM_FFd1_N24 (
    .I0(CurrState_Sreg0_FSM_FFd1_N23_615),
    .I1(CurrState_Sreg0_FSM_FFd1_N24_616),
    .O(CurrState_Sreg0_FSM_FFd1_N25_617)
  );
  AND2   CurrState_Sreg0_FSM_FFd1_N25 (
    .I0(CurrState_Sreg0_FSM_FFd1_N22_614),
    .I1(CurrState_Sreg0_FSM_FFd1_N25_617),
    .O(CurrState_Sreg0_FSM_FFd1_N2)
  );
  AND3   CurrState_Sreg0_FSM_FFd2_N251 (
    .I0(CurrState_Sreg0_FSM_FFd4_655),
    .I1(phaseA),
    .I2(phaseB),
    .O(CurrState_Sreg0_FSM_FFd2_N25)
  );
  INV   CurrState_Sreg0_FSM_FFd2_N252 (
    .I(CurrState_Sreg0_FSM_FFd4_655),
    .O(CurrState_Sreg0_FSM_FFd2_N251_628)
  );
  INV   CurrState_Sreg0_FSM_FFd2_N253 (
    .I(phaseB),
    .O(CurrState_Sreg0_FSM_FFd2_N252_629)
  );
  OR2   CurrState_Sreg0_FSM_FFd2_N254 (
    .I0(phaseA),
    .I1(CurrState_Sreg0_FSM_FFd2_N252_629),
    .O(CurrState_Sreg0_FSM_FFd2_N253_630)
  );
  INV   CurrState_Sreg0_FSM_FFd2_N255 (
    .I(CurrState_Sreg0_FSM_FFd2_N253_630),
    .O(CurrState_Sreg0_FSM_FFd2_N254_631)
  );
  AND2   CurrState_Sreg0_FSM_FFd2_N256 (
    .I0(CurrState_Sreg0_FSM_FFd2_N251_628),
    .I1(CurrState_Sreg0_FSM_FFd2_N254_631),
    .O(CurrState_Sreg0_FSM_FFd2_N255_632)
  );
  OR2   CurrState_Sreg0_FSM_FFd2_N257 (
    .I0(CurrState_Sreg0_FSM_FFd2_N25),
    .I1(CurrState_Sreg0_FSM_FFd2_N255_632),
    .O(CurrState_Sreg0_FSM_FFd2_N2_bdd2)
  );
  AND2   CurrState_Sreg0_FSM_FFd2_N231 (
    .I0(phaseA),
    .I1(phaseB),
    .O(CurrState_Sreg0_FSM_FFd2_N23_624)
  );
  INV   CurrState_Sreg0_FSM_FFd2_N232 (
    .I(CurrState_Sreg0_FSM_FFd2_N23_624),
    .O(CurrState_Sreg0_FSM_FFd2_N231_625)
  );
  AND2   CurrState_Sreg0_FSM_FFd2_N233 (
    .I0(CurrState_Sreg0_FSM_FFd4_655),
    .I1(CurrState_Sreg0_FSM_FFd2_N231_625),
    .O(CurrState_Sreg0_FSM_FFd2_N2_bdd1)
  );
  OR2   CurrState_Sreg0_FSM_FFd2_N211 (
    .I0(phaseA),
    .I1(CurrState_Sreg0_FSM_FFd4_655),
    .O(CurrState_Sreg0_FSM_FFd2_N21_621)
  );
  INV   CurrState_Sreg0_FSM_FFd2_N212 (
    .I(phaseB),
    .O(CurrState_Sreg0_FSM_FFd2_N211_622)
  );
  OR2   CurrState_Sreg0_FSM_FFd2_N213 (
    .I0(CurrState_Sreg0_FSM_FFd2_N21_621),
    .I1(CurrState_Sreg0_FSM_FFd2_N211_622),
    .O(CurrState_Sreg0_FSM_FFd2_N2_bdd0)
  );
  AND2   CurrState_Sreg0_FSM_FFd2_N21 (
    .I0(SFDecomp_6),
    .I1(CurrState_Sreg0_FSM_FFd2_619),
    .O(CurrState_Sreg0_FSM_FFd2_N22_623)
  );
  INV   CurrState_Sreg0_FSM_FFd2_N22 (
    .I(Reset),
    .O(CurrState_Sreg0_FSM_FFd2_N24_626)
  );
  OR2   CurrState_Sreg0_FSM_FFd2_N23 (
    .I0(SFDecomp_7),
    .I1(CurrState_Sreg0_FSM_FFd2_N22_623),
    .O(CurrState_Sreg0_FSM_FFd2_N26)
  );
  AND2   CurrState_Sreg0_FSM_FFd2_N24 (
    .I0(CurrState_Sreg0_FSM_FFd2_N26),
    .I1(CurrState_Sreg0_FSM_FFd2_N24_626),
    .O(CurrState_Sreg0_FSM_FFd2_N2)
  );
  AND2   CurrState_Sreg0_FSM_FFd3_N241 (
    .I0(phaseA),
    .I1(CurrState_Sreg0_FSM_FFd4_655),
    .O(CurrState_Sreg0_FSM_FFd3_N24_646)
  );
  INV   CurrState_Sreg0_FSM_FFd3_N242 (
    .I(phaseA),
    .O(CurrState_Sreg0_FSM_FFd3_N241_647)
  );
  OR2   CurrState_Sreg0_FSM_FFd3_N243 (
    .I0(CurrState_Sreg0_FSM_FFd4_655),
    .I1(CurrState_Sreg0_FSM_FFd2_619),
    .O(CurrState_Sreg0_FSM_FFd3_N242_648)
  );
  INV   CurrState_Sreg0_FSM_FFd3_N244 (
    .I(CurrState_Sreg0_FSM_FFd3_N242_648),
    .O(CurrState_Sreg0_FSM_FFd3_N243_649)
  );
  AND2   CurrState_Sreg0_FSM_FFd3_N245 (
    .I0(CurrState_Sreg0_FSM_FFd3_N241_647),
    .I1(CurrState_Sreg0_FSM_FFd3_N243_649),
    .O(CurrState_Sreg0_FSM_FFd3_N244_650)
  );
  OR2   CurrState_Sreg0_FSM_FFd3_N246 (
    .I0(CurrState_Sreg0_FSM_FFd3_N24_646),
    .I1(CurrState_Sreg0_FSM_FFd3_N244_650),
    .O(CurrState_Sreg0_FSM_FFd3_N2_bdd2)
  );
  OR2   CurrState_Sreg0_FSM_FFd3_N231 (
    .I0(CurrState_Sreg0_FSM_FFd4_655),
    .I1(CurrState_Sreg0_FSM_FFd2_619),
    .O(CurrState_Sreg0_FSM_FFd3_N23_641)
  );
  INV   CurrState_Sreg0_FSM_FFd3_N232 (
    .I(phaseA),
    .O(CurrState_Sreg0_FSM_FFd3_N231_642)
  );
  INV   CurrState_Sreg0_FSM_FFd3_N233 (
    .I(CurrState_Sreg0_FSM_FFd4_655),
    .O(CurrState_Sreg0_FSM_FFd3_N232_643)
  );
  AND2   CurrState_Sreg0_FSM_FFd3_N234 (
    .I0(phaseA),
    .I1(CurrState_Sreg0_FSM_FFd3_N23_641),
    .O(CurrState_Sreg0_FSM_FFd3_N233_644)
  );
  AND2   CurrState_Sreg0_FSM_FFd3_N235 (
    .I0(CurrState_Sreg0_FSM_FFd3_N231_642),
    .I1(CurrState_Sreg0_FSM_FFd3_N232_643),
    .O(CurrState_Sreg0_FSM_FFd3_N234_645)
  );
  OR2   CurrState_Sreg0_FSM_FFd3_N236 (
    .I0(CurrState_Sreg0_FSM_FFd3_N233_644),
    .I1(CurrState_Sreg0_FSM_FFd3_N234_645),
    .O(CurrState_Sreg0_FSM_FFd3_N2_bdd1)
  );
  OR3   CurrState_Sreg0_FSM_FFd3_N211 (
    .I0(phaseA),
    .I1(CurrState_Sreg0_FSM_FFd4_655),
    .I2(CurrState_Sreg0_FSM_FFd2_619),
    .O(CurrState_Sreg0_FSM_FFd3_N2_bdd0)
  );
  AND2   CurrState_Sreg0_FSM_FFd3_N21 (
    .I0(SFDecomp_9),
    .I1(CurrState_Sreg0_FSM_FFd3_637),
    .O(CurrState_Sreg0_FSM_FFd3_N21_639)
  );
  INV   CurrState_Sreg0_FSM_FFd3_N22 (
    .I(Reset),
    .O(CurrState_Sreg0_FSM_FFd3_N22_640)
  );
  OR2   CurrState_Sreg0_FSM_FFd3_N23 (
    .I0(SFDecomp_10),
    .I1(CurrState_Sreg0_FSM_FFd3_N21_639),
    .O(CurrState_Sreg0_FSM_FFd3_N25)
  );
  AND2   CurrState_Sreg0_FSM_FFd3_N24 (
    .I0(CurrState_Sreg0_FSM_FFd3_N25),
    .I1(CurrState_Sreg0_FSM_FFd3_N22_640),
    .O(CurrState_Sreg0_FSM_FFd3_N2)
  );
  AND2   SFDecomp_61 (
    .I0(CurrState_Sreg0_FSM_FFd3_637),
    .I1(CurrState_Sreg0_FSM_FFd2_N2_bdd0),
    .O(SFDecomp_61_674)
  );
  INV   SFDecomp_62 (
    .I(CurrState_Sreg0_FSM_FFd3_637),
    .O(SFDecomp_62_675)
  );
  AND2   SFDecomp_63 (
    .I0(CurrState_Sreg0_FSM_FFd2_N2_bdd1),
    .I1(SFDecomp_62_675),
    .O(SFDecomp_63_676)
  );
  OR2   SFDecomp_64 (
    .I0(SFDecomp_61_674),
    .I1(SFDecomp_63_676),
    .O(SFDecomp_6)
  );
  AND2   SFDecomp_71 (
    .I0(CurrState_Sreg0_FSM_FFd3_637),
    .I1(CurrState_Sreg0_FSM_FFd2_N2_bdd2),
    .O(SFDecomp_71_678)
  );
  INV   SFDecomp_72 (
    .I(CurrState_Sreg0_FSM_FFd2_619),
    .O(SFDecomp_72_679)
  );
  AND2   SFDecomp_73 (
    .I0(SFDecomp_71_678),
    .I1(SFDecomp_72_679),
    .O(SFDecomp_7)
  );
  AND2   SFDecomp_91 (
    .I0(phaseB),
    .I1(CurrState_Sreg0_FSM_FFd3_N2_bdd0),
    .O(SFDecomp_91_681)
  );
  INV   SFDecomp_92 (
    .I(phaseB),
    .O(SFDecomp_92_682)
  );
  AND2   SFDecomp_93 (
    .I0(CurrState_Sreg0_FSM_FFd3_N2_bdd1),
    .I1(SFDecomp_92_682),
    .O(SFDecomp_93_683)
  );
  OR2   SFDecomp_94 (
    .I0(SFDecomp_91_681),
    .I1(SFDecomp_93_683),
    .O(SFDecomp_9)
  );
  AND2   SFDecomp_101 (
    .I0(phaseB),
    .I1(CurrState_Sreg0_FSM_FFd3_N2_bdd2),
    .O(SFDecomp_101_671)
  );
  INV   SFDecomp_102 (
    .I(CurrState_Sreg0_FSM_FFd3_637),
    .O(SFDecomp_102_672)
  );
  AND2   SFDecomp_103 (
    .I0(SFDecomp_101_671),
    .I1(SFDecomp_102_672),
    .O(SFDecomp_10)
  );
endmodule

module Servos (
  DCOR0CNTLOWr, DCORENCCTLw, DCOR0THRESLOWr, PhaseB_Encoder0, PhaseB_Encoder1, DCOR0THRESHIGHr, DCOR1CNTHIGHr, Reset, DCOR0CNTHIGHr, DCOR1THRESHIGHr, 
PhaseA_Encoder0, PhaseA_Encoder1, DCORIFGr, Hfound0, Hfound1, DCORIFGw, MotorIn0, Motorin1, TP, Home_Encoder0, Home_Encoder1, DCOR1CNTLOWr, ASleading
, Mclk, DCOR1THRESLOWr, Tfound0, Tfound1, outDATA, inDATA
);
  input DCOR0CNTLOWr;
  input DCORENCCTLw;
  input DCOR0THRESLOWr;
  input PhaseB_Encoder0;
  input PhaseB_Encoder1;
  input DCOR0THRESHIGHr;
  input DCOR1CNTHIGHr;
  input Reset;
  input DCOR0CNTHIGHr;
  input DCOR1THRESHIGHr;
  input PhaseA_Encoder0;
  input PhaseA_Encoder1;
  input DCORIFGr;
  output Hfound0;
  output Hfound1;
  input DCORIFGw;
  input MotorIn0;
  input Motorin1;
  output TP;
  input Home_Encoder0;
  input Home_Encoder1;
  input DCOR1CNTLOWr;
  input ASleading;
  input Mclk;
  input DCOR1THRESLOWr;
  output Tfound0;
  output Tfound1;
  output [7 : 0] outDATA;
  input [7 : 0] inDATA;
  wire NET3720;
  wire NlwRenamedSig_OI_TP;
  wire Zero0;
  wire Zero1;
  wire ce0;
  wire ce1;
  wire updown0;
  wire updown1;
  wire [15 : 0] Channel0;
  wire [15 : 0] Channel1;
  assign
    TP = NlwRenamedSig_OI_TP;
  Decode   U6 (
    .ce(ce1),
    .Reset(Reset),
    .updown(updown1),
    .phaseA(PhaseA_Encoder1),
    .phaseB(PhaseB_Encoder1),
    .Sclk(Mclk)
  );
  Decode_INST_1   U1 (
    .ce(ce0),
    .Reset(Reset),
    .updown(updown0),
    .phaseA(PhaseA_Encoder0),
    .phaseB(PhaseB_Encoder0),
    .Sclk(Mclk)
  );
  Holdreg   U3 (
    .DCOR0CNTLOWr(DCOR0CNTLOWr),
    .DCOR1CNTHIGHr(DCOR1CNTHIGHr),
    .Reset(Reset),
    .DCOR0CNTHIGHr(DCOR0CNTHIGHr),
    .Sclk(Mclk),
    .DCOR1CNTLOWr(DCOR1CNTLOWr),
    .ASleading(ASleading),
    .outDATA({outDATA[7], outDATA[6], outDATA[5], outDATA[4], outDATA[3], outDATA[2], outDATA[1], outDATA[0]}),
    .ch0in({Channel0[15], Channel0[14], Channel0[13], Channel0[12], Channel0[11], Channel0[10], Channel0[9], Channel0[8], Channel0[7], Channel0[6], 
Channel0[5], Channel0[4], Channel0[3], Channel0[2], Channel0[1], Channel0[0]}),
    .ch1in({Channel1[15], Channel1[14], Channel1[13], Channel1[12], Channel1[11], Channel1[10], Channel1[9], Channel1[8], Channel1[7], Channel1[6], 
Channel1[5], Channel1[4], Channel1[3], Channel1[2], Channel1[1], Channel1[0]})
  );
  HomeConfig   U4 (
    .Zero0(Zero0),
    .Zero1(Zero1),
    .DCORENCCTLw(DCORENCCTLw),
    .DCOR0THRESLOWr(DCOR0THRESLOWr),
    .DCOR0THRESHIGHr(DCOR0THRESHIGHr),
    .Reset(Reset),
    .DCOR1THRESHIGHr(DCOR1THRESHIGHr),
    .DCORIFGr(DCORIFGr),
    .Hfound0(Hfound0),
    .Hfound1(Hfound1),
    .DCORIFGw(DCORIFGw),
    .MotorIn0(MotorIn0),
    .MotorIn1(Motorin1),
    .Home_Encoder0(Home_Encoder0),
    .Home_Encoder1(Home_Encoder1),
    .sense0(NlwRenamedSig_OI_TP),
    .sense1(NET3720),
    .Sclk(Mclk),
    .DCOR1THRESLOWr(DCOR1THRESLOWr),
    .Tfound0(Tfound0),
    .Tfound1(Tfound1),
    .outDATA({outDATA[7], outDATA[6], outDATA[5], outDATA[4], outDATA[3], outDATA[2], outDATA[1], outDATA[0]}),
    .inDATA({inDATA[7], inDATA[6], inDATA[5], inDATA[4], inDATA[3], inDATA[2], inDATA[1], inDATA[0]}),
    .Channel0({Channel0[15], Channel0[14], Channel0[13], Channel0[12], Channel0[11], Channel0[10], Channel0[9], Channel0[8], Channel0[7], Channel0[6]
, Channel0[5], Channel0[4], Channel0[3], Channel0[2], Channel0[1], Channel0[0]}),
    .Channel1({Channel1[15], Channel1[14], Channel1[13], Channel1[12], Channel1[11], Channel1[10], Channel1[9], Channel1[8], Channel1[7], Channel1[6]
, Channel1[5], Channel1[4], Channel1[3], Channel1[2], Channel1[1], Channel1[0]})
  );
  Counter   U5 (
    .sense(NET3720),
    .ce(ce1),
    .Reset(Reset),
    .updown(updown1),
    .Zero(Zero1),
    .Sclk(Mclk),
    .count({Channel1[15], Channel1[14], Channel1[13], Channel1[12], Channel1[11], Channel1[10], Channel1[9], Channel1[8], Channel1[7], Channel1[6], 
Channel1[5], Channel1[4], Channel1[3], Channel1[2], Channel1[1], Channel1[0]})
  );
  Counter_INST_1   U2 (
    .sense(NlwRenamedSig_OI_TP),
    .ce(ce0),
    .Reset(Reset),
    .updown(updown0),
    .Zero(Zero0),
    .Sclk(Mclk),
    .count({Channel0[15], Channel0[14], Channel0[13], Channel0[12], Channel0[11], Channel0[10], Channel0[9], Channel0[8], Channel0[7], Channel0[6], 
Channel0[5], Channel0[4], Channel0[3], Channel0[2], Channel0[1], Channel0[0]})
  );
endmodule

module MISCouts (
  LightSense, MTRpwrn, LED1, LED2, LED3, LED4, LED5, Reset, GP_Motor0_1, GP_Motor1_1, DCOROUTw, Mclk, MTRpwr, MReset, inDATA
);
  input LightSense;
  output MTRpwrn;
  output LED1;
  output LED2;
  output LED3;
  output LED4;
  output LED5;
  input Reset;
  output GP_Motor0_1;
  output GP_Motor1_1;
  input DCOROUTw;
  input Mclk;
  output MTRpwr;
  input MReset;
  input [7 : 0] inDATA;
  wire LED11_564;
  wire LED21_566;
  wire LED31_568;
  wire LED41_570;
  wire LED51_572;
  wire MISCr_0_N0;
  wire \MISCr_mux0000<0>1_581 ;
  wire \MISCr_mux0000<1>1_583 ;
  wire \MISCr_mux0000<2>1_585 ;
  wire \MISCr_mux0000<3>1_587 ;
  wire \MISCr_mux0000<4>1_589 ;
  wire \MISCr_mux0000<5>1_591 ;
  wire \MISCr_mux0000<6>1_593 ;
  wire \MISCr_mux0000<7>1_595 ;
  wire MISCr_not0001;
  wire NlwRenamedSig_OI_MTRpwr;
  wire [4 : 0] MISCr;
  wire [7 : 0] MISCr_mux0000;
  assign
    MTRpwr = NlwRenamedSig_OI_MTRpwr;
  FDCE   MISCr_7 (
    .CE(MISCr_not0001),
    .CLR(MReset),
    .C(MISCr_0_N0),
    .D(MISCr_mux0000[0]),
    .Q(GP_Motor1_1)
  );
  FDCE   MISCr_6 (
    .CE(MISCr_not0001),
    .CLR(MReset),
    .C(MISCr_0_N0),
    .D(MISCr_mux0000[1]),
    .Q(GP_Motor0_1)
  );
  FDCE   MISCr_5 (
    .CE(MISCr_not0001),
    .CLR(MReset),
    .C(MISCr_0_N0),
    .D(MISCr_mux0000[2]),
    .Q(NlwRenamedSig_OI_MTRpwr)
  );
  FDCE   MISCr_4 (
    .CE(MISCr_not0001),
    .CLR(MReset),
    .C(MISCr_0_N0),
    .D(MISCr_mux0000[3]),
    .Q(MISCr[4])
  );
  FDCE   MISCr_3 (
    .CE(MISCr_not0001),
    .CLR(MReset),
    .C(MISCr_0_N0),
    .D(MISCr_mux0000[4]),
    .Q(MISCr[3])
  );
  FDCE   MISCr_2 (
    .CE(MISCr_not0001),
    .CLR(MReset),
    .C(MISCr_0_N0),
    .D(MISCr_mux0000[5]),
    .Q(MISCr[2])
  );
  FDCE   MISCr_1 (
    .CE(MISCr_not0001),
    .CLR(MReset),
    .C(MISCr_0_N0),
    .D(MISCr_mux0000[6]),
    .Q(MISCr[1])
  );
  FDCE   MISCr_0 (
    .CE(MISCr_not0001),
    .CLR(MReset),
    .C(MISCr_0_N0),
    .D(MISCr_mux0000[7]),
    .Q(MISCr[0])
  );
  INV   LED11 (
    .I(LightSense),
    .O(LED11_564)
  );
  OR2   LED12 (
    .I0(MISCr[0]),
    .I1(LED11_564),
    .O(LED1)
  );
  INV   LED21 (
    .I(LightSense),
    .O(LED21_566)
  );
  OR2   LED22 (
    .I0(MISCr[1]),
    .I1(LED21_566),
    .O(LED2)
  );
  INV   LED31 (
    .I(LightSense),
    .O(LED31_568)
  );
  OR2   LED32 (
    .I0(MISCr[2]),
    .I1(LED31_568),
    .O(LED3)
  );
  INV   LED41 (
    .I(LightSense),
    .O(LED41_570)
  );
  OR2   LED42 (
    .I0(MISCr[3]),
    .I1(LED41_570),
    .O(LED4)
  );
  INV   LED51 (
    .I(LightSense),
    .O(LED51_572)
  );
  OR2   LED52 (
    .I0(MISCr[4]),
    .I1(LED51_572),
    .O(LED5)
  );
  INV   MTRpwrn1 (
    .I(NlwRenamedSig_OI_MTRpwr),
    .O(MTRpwrn)
  );
  INV   \MISCr_mux0000<0>1  (
    .I(Reset),
    .O(\MISCr_mux0000<0>1_581 )
  );
  AND2   \MISCr_mux0000<0>2  (
    .I0(inDATA[7]),
    .I1(\MISCr_mux0000<0>1_581 ),
    .O(MISCr_mux0000[0])
  );
  INV   \MISCr_mux0000<1>1  (
    .I(Reset),
    .O(\MISCr_mux0000<1>1_583 )
  );
  AND2   \MISCr_mux0000<1>2  (
    .I0(inDATA[6]),
    .I1(\MISCr_mux0000<1>1_583 ),
    .O(MISCr_mux0000[1])
  );
  INV   \MISCr_mux0000<2>1  (
    .I(Reset),
    .O(\MISCr_mux0000<2>1_585 )
  );
  AND2   \MISCr_mux0000<2>2  (
    .I0(inDATA[5]),
    .I1(\MISCr_mux0000<2>1_585 ),
    .O(MISCr_mux0000[2])
  );
  INV   \MISCr_mux0000<3>1  (
    .I(Reset),
    .O(\MISCr_mux0000<3>1_587 )
  );
  AND2   \MISCr_mux0000<3>2  (
    .I0(inDATA[4]),
    .I1(\MISCr_mux0000<3>1_587 ),
    .O(MISCr_mux0000[3])
  );
  INV   \MISCr_mux0000<4>1  (
    .I(Reset),
    .O(\MISCr_mux0000<4>1_589 )
  );
  AND2   \MISCr_mux0000<4>2  (
    .I0(inDATA[3]),
    .I1(\MISCr_mux0000<4>1_589 ),
    .O(MISCr_mux0000[4])
  );
  INV   \MISCr_mux0000<5>1  (
    .I(Reset),
    .O(\MISCr_mux0000<5>1_591 )
  );
  AND2   \MISCr_mux0000<5>2  (
    .I0(inDATA[2]),
    .I1(\MISCr_mux0000<5>1_591 ),
    .O(MISCr_mux0000[5])
  );
  INV   \MISCr_mux0000<6>1  (
    .I(Reset),
    .O(\MISCr_mux0000<6>1_593 )
  );
  AND2   \MISCr_mux0000<6>2  (
    .I0(inDATA[1]),
    .I1(\MISCr_mux0000<6>1_593 ),
    .O(MISCr_mux0000[6])
  );
  INV   \MISCr_mux0000<7>1  (
    .I(Reset),
    .O(\MISCr_mux0000<7>1_595 )
  );
  AND2   \MISCr_mux0000<7>2  (
    .I0(inDATA[0]),
    .I1(\MISCr_mux0000<7>1_595 ),
    .O(MISCr_mux0000[7])
  );
  INV   MISCr_0_N01 (
    .I(Mclk),
    .O(MISCr_0_N0)
  );
  OR2   MISCr_not000111 (
    .I0(Reset),
    .I1(DCOROUTw),
    .O(MISCr_not0001)
  );
endmodule

module Sensor (
  TmpSlct, Reset, DCORSENSORw, TmpEn, PresEn, PresSlct, Mclk, MReset, inDATA
);
  output TmpSlct;
  input Reset;
  input DCORSENSORw;
  output TmpEn;
  output PresEn;
  output PresSlct;
  input Mclk;
  input MReset;
  input [3 : 0] inDATA;
  wire \sensorr[0] ;
  wire sensorr_0_N0;
  wire \sensorr[2] ;
  wire \sensorr_mux0000<0>1_552 ;
  wire \sensorr_mux0000<1>1_554 ;
  wire \sensorr_mux0000<2>1_556 ;
  wire \sensorr_mux0000<3>1_558 ;
  wire sensorr_not0001;
  wire [3 : 0] sensorr_mux0000;
  FDCE   sensorr_3 (
    .CE(sensorr_not0001),
    .CLR(MReset),
    .C(sensorr_0_N0),
    .D(sensorr_mux0000[0]),
    .Q(TmpSlct)
  );
  FDCE   sensorr_2 (
    .CE(sensorr_not0001),
    .CLR(MReset),
    .C(sensorr_0_N0),
    .D(sensorr_mux0000[1]),
    .Q(\sensorr[2] )
  );
  FDCE   sensorr_1 (
    .CE(sensorr_not0001),
    .CLR(MReset),
    .C(sensorr_0_N0),
    .D(sensorr_mux0000[2]),
    .Q(PresSlct)
  );
  FDCE   sensorr_0 (
    .CE(sensorr_not0001),
    .CLR(MReset),
    .C(sensorr_0_N0),
    .D(sensorr_mux0000[3]),
    .Q(\sensorr[0] )
  );
  INV   PresEn1 (
    .I(\sensorr[0] ),
    .O(PresEn)
  );
  INV   TmpEn1 (
    .I(\sensorr[2] ),
    .O(TmpEn)
  );
  INV   \sensorr_mux0000<0>1  (
    .I(Reset),
    .O(\sensorr_mux0000<0>1_552 )
  );
  AND2   \sensorr_mux0000<0>2  (
    .I0(inDATA[3]),
    .I1(\sensorr_mux0000<0>1_552 ),
    .O(sensorr_mux0000[0])
  );
  INV   \sensorr_mux0000<1>1  (
    .I(Reset),
    .O(\sensorr_mux0000<1>1_554 )
  );
  AND2   \sensorr_mux0000<1>2  (
    .I0(inDATA[2]),
    .I1(\sensorr_mux0000<1>1_554 ),
    .O(sensorr_mux0000[1])
  );
  INV   \sensorr_mux0000<2>1  (
    .I(Reset),
    .O(\sensorr_mux0000<2>1_556 )
  );
  AND2   \sensorr_mux0000<2>2  (
    .I0(inDATA[1]),
    .I1(\sensorr_mux0000<2>1_556 ),
    .O(sensorr_mux0000[2])
  );
  INV   \sensorr_mux0000<3>1  (
    .I(Reset),
    .O(\sensorr_mux0000<3>1_558 )
  );
  AND2   \sensorr_mux0000<3>2  (
    .I0(inDATA[0]),
    .I1(\sensorr_mux0000<3>1_558 ),
    .O(sensorr_mux0000[3])
  );
  INV   sensorr_0_N01 (
    .I(Mclk),
    .O(sensorr_0_N0)
  );
  OR2   sensorr_not000111 (
    .I0(Reset),
    .I1(DCORSENSORw),
    .O(sensorr_not0001)
  );
endmodule

module PWRreg (
  DCORENCPWRr, DCORENCPWRw, PWRint, Hme05ctl, Enc033ctl, Hme033ctl, Reset, Hme05flg, Enc05ctl, Enc033flg, Hme033flg, Hme15ctl, Enc133ctl, Hme133ctl, 
DCORIFGr, DCORIFGw, Enc05flg, Hme15flg, Enc133flg, Hme133flg, Enc15ctl, Enc15flg, Mclk, outDATA, inDATA
);
  input DCORENCPWRr;
  input DCORENCPWRw;
  output PWRint;
  output Hme05ctl;
  output Enc033ctl;
  output Hme033ctl;
  input Reset;
  input Hme05flg;
  output Enc05ctl;
  input Enc033flg;
  input Hme033flg;
  output Hme15ctl;
  output Enc133ctl;
  output Hme133ctl;
  input DCORIFGr;
  input DCORIFGw;
  input Enc05flg;
  input Hme15flg;
  input Enc133flg;
  input Hme133flg;
  output Enc15ctl;
  input Enc15flg;
  input Mclk;
  output [7 : 0] outDATA;
  input [7 : 0] inDATA;
  wire DCORIFG_0_not0000;
  wire DCORIFG__and0000;
  wire DCORIFG__and00001;
  wire DCORIFG__and000011_447;
  wire DCORIFG__and000012_448;
  wire DCORIFG__and000013_449;
  wire DCORIFG__and000014_450;
  wire DCORIFG__or0000;
  wire DCORIFG__or00002;
  wire DCORIFG__or000021_453;
  wire DCORIFG__or000022_454;
  wire DCORIFG__or000023_455;
  wire DCORIFG__or0000_bdd0;
  wire DCORIFG__or0000_bdd2;
  wire NlwRenamedSig_OI_Enc133ctl;
  wire \Flgreg[0] ;
  wire \Flgreg[1] ;
  wire \Flgreg[3] ;
  wire \Flgreg[4] ;
  wire \Flgreg[5] ;
  wire \Flgreg[6] ;
  wire \Flgreg[7] ;
  wire Flgreg_and0000;
  wire Flgreg_and00001;
  wire N1;
  wire NlwRenamedSig_OI_PWRint;
  wire \ctrlr[0] ;
  wire \ctrlr[1] ;
  wire \ctrlr[3] ;
  wire \ctrlr[4] ;
  wire \ctrlr[5] ;
  wire \ctrlr[7] ;
  wire \outDATA<1>_not0000 ;
  wire outDATA_0_mux0000;
  wire outDATA_0_mux00001_508;
  wire outDATA_0_mux00002_509;
  wire outDATA_0_mux00003_510;
  wire outDATA_1_mux0000;
  wire outDATA_1_mux00001_512;
  wire outDATA_1_mux00002_513;
  wire outDATA_1_mux00003_514;
  wire outDATA_1_mux00004_515;
  wire outDATA_1_mux00005_516;
  wire outDATA_1_mux00006_517;
  wire outDATA_2_mux0000;
  wire outDATA_2_mux00001_519;
  wire outDATA_3_mux0000;
  wire outDATA_3_mux00001_521;
  wire outDATA_3_mux00002_522;
  wire outDATA_3_mux00003_523;
  wire outDATA_4_mux0000;
  wire outDATA_4_mux00001_525;
  wire outDATA_4_mux00002_526;
  wire outDATA_4_mux00003_527;
  wire outDATA_5_mux0000;
  wire outDATA_5_mux00001_529;
  wire outDATA_5_mux00002_530;
  wire outDATA_5_mux00003_531;
  wire outDATA_7_mux0000;
  wire outDATA_7_mux00001_533;
  wire outDATA_7_mux00002_534;
  wire outDATA_7_mux00003_535;
  assign
    PWRint = NlwRenamedSig_OI_PWRint,
    Enc033ctl = NlwRenamedSig_OI_Enc133ctl,
    Enc133ctl = NlwRenamedSig_OI_Enc133ctl;
  GND   XST_GND (
    .G(NlwRenamedSig_OI_Enc133ctl)
  );
  VCC   XST_VCC (
    .P(N1)
  );
  BUFE   \outDATA<0>_0  (
    .I(outDATA_0_mux0000),
    .E(DCORENCPWRr),
    .O(outDATA[0])
  );
  BUFE   \outDATA<1>_0  (
    .I(outDATA_1_mux0000),
    .E(\outDATA<1>_not0000 ),
    .O(outDATA[1])
  );
  BUFE   \outDATA<2>_0  (
    .I(outDATA_2_mux0000),
    .E(DCORENCPWRr),
    .O(outDATA[2])
  );
  BUFE   \outDATA<3>_0  (
    .I(outDATA_3_mux0000),
    .E(DCORENCPWRr),
    .O(outDATA[3])
  );
  BUFE   \outDATA<4>_0  (
    .I(outDATA_4_mux0000),
    .E(DCORENCPWRr),
    .O(outDATA[4])
  );
  BUFE   \outDATA<5>_0  (
    .I(outDATA_5_mux0000),
    .E(DCORENCPWRr),
    .O(outDATA[5])
  );
  BUFE   \outDATA<6>_0  (
    .I(outDATA_2_mux0000),
    .E(DCORENCPWRr),
    .O(outDATA[6])
  );
  BUFE   \outDATA<7>_0  (
    .I(outDATA_7_mux0000),
    .E(DCORENCPWRr),
    .O(outDATA[7])
  );
  FDCE   DCORIFG (
    .CE(DCORIFG__or0000),
    .CLR(NlwRenamedSig_OI_Enc133ctl),
    .C(DCORIFG_0_not0000),
    .D(DCORIFG__and0000),
    .Q(NlwRenamedSig_OI_PWRint)
  );
  FDCE   ctrlr_7 (
    .CE(DCORENCPWRw),
    .CLR(Reset),
    .C(DCORIFG_0_not0000),
    .D(inDATA[7]),
    .Q(\ctrlr[7] )
  );
  FDCE   ctrlr_5 (
    .CE(DCORENCPWRw),
    .CLR(Reset),
    .C(DCORIFG_0_not0000),
    .D(inDATA[5]),
    .Q(\ctrlr[5] )
  );
  FDCE   ctrlr_4 (
    .CE(DCORENCPWRw),
    .CLR(Reset),
    .C(DCORIFG_0_not0000),
    .D(inDATA[4]),
    .Q(\ctrlr[4] )
  );
  FDCE   ctrlr_3 (
    .CE(DCORENCPWRw),
    .CLR(Reset),
    .C(DCORIFG_0_not0000),
    .D(inDATA[3]),
    .Q(\ctrlr[3] )
  );
  FDCE   ctrlr_1 (
    .CE(DCORENCPWRw),
    .CLR(Reset),
    .C(DCORIFG_0_not0000),
    .D(inDATA[1]),
    .Q(\ctrlr[1] )
  );
  FDCE   ctrlr_0 (
    .CE(DCORENCPWRw),
    .CLR(Reset),
    .C(DCORIFG_0_not0000),
    .D(inDATA[0]),
    .Q(\ctrlr[0] )
  );
  FDCE   Flgreg_7 (
    .CE(Flgreg_and0000),
    .CLR(NlwRenamedSig_OI_Enc133ctl),
    .C(DCORIFG_0_not0000),
    .D(Enc15flg),
    .Q(\Flgreg[7] )
  );
  FDCE   Flgreg_6 (
    .CE(Flgreg_and0000),
    .CLR(NlwRenamedSig_OI_Enc133ctl),
    .C(DCORIFG_0_not0000),
    .D(N1),
    .Q(\Flgreg[6] )
  );
  FDCE   Flgreg_5 (
    .CE(Flgreg_and0000),
    .CLR(NlwRenamedSig_OI_Enc133ctl),
    .C(DCORIFG_0_not0000),
    .D(Hme15flg),
    .Q(\Flgreg[5] )
  );
  FDCE   Flgreg_4 (
    .CE(Flgreg_and0000),
    .CLR(NlwRenamedSig_OI_Enc133ctl),
    .C(DCORIFG_0_not0000),
    .D(Hme133flg),
    .Q(\Flgreg[4] )
  );
  FDCE   Flgreg_3 (
    .CE(Flgreg_and0000),
    .CLR(NlwRenamedSig_OI_Enc133ctl),
    .C(DCORIFG_0_not0000),
    .D(Enc05flg),
    .Q(\Flgreg[3] )
  );
  FDCE   Flgreg_1 (
    .CE(Flgreg_and0000),
    .CLR(NlwRenamedSig_OI_Enc133ctl),
    .C(DCORIFG_0_not0000),
    .D(Hme05flg),
    .Q(\Flgreg[1] )
  );
  FDCE   Flgreg_0 (
    .CE(Flgreg_and0000),
    .CLR(NlwRenamedSig_OI_Enc133ctl),
    .C(DCORIFG_0_not0000),
    .D(Hme033flg),
    .Q(\Flgreg[0] )
  );
  INV   Enc15ctl1 (
    .I(\ctrlr[7] ),
    .O(Enc15ctl)
  );
  INV   Hme15ctl1 (
    .I(\ctrlr[5] ),
    .O(Hme15ctl)
  );
  INV   Hme133ctl1 (
    .I(\ctrlr[4] ),
    .O(Hme133ctl)
  );
  INV   Enc05ctl1 (
    .I(\ctrlr[3] ),
    .O(Enc05ctl)
  );
  INV   Hme05ctl1 (
    .I(\ctrlr[1] ),
    .O(Hme05ctl)
  );
  INV   Hme033ctl1 (
    .I(\ctrlr[0] ),
    .O(Hme033ctl)
  );
  AND2   outDATA_7_mux00001 (
    .I0(NlwRenamedSig_OI_PWRint),
    .I1(\Flgreg[7] ),
    .O(outDATA_7_mux00001_533)
  );
  INV   outDATA_7_mux00002 (
    .I(NlwRenamedSig_OI_PWRint),
    .O(outDATA_7_mux00002_534)
  );
  AND2   outDATA_7_mux00003 (
    .I0(Enc15flg),
    .I1(outDATA_7_mux00002_534),
    .O(outDATA_7_mux00003_535)
  );
  OR2   outDATA_7_mux00004 (
    .I0(outDATA_7_mux00001_533),
    .I1(outDATA_7_mux00003_535),
    .O(outDATA_7_mux0000)
  );
  AND2   outDATA_5_mux00001 (
    .I0(NlwRenamedSig_OI_PWRint),
    .I1(\Flgreg[5] ),
    .O(outDATA_5_mux00001_529)
  );
  INV   outDATA_5_mux00002 (
    .I(NlwRenamedSig_OI_PWRint),
    .O(outDATA_5_mux00002_530)
  );
  AND2   outDATA_5_mux00003 (
    .I0(Hme15flg),
    .I1(outDATA_5_mux00002_530),
    .O(outDATA_5_mux00003_531)
  );
  OR2   outDATA_5_mux00004 (
    .I0(outDATA_5_mux00001_529),
    .I1(outDATA_5_mux00003_531),
    .O(outDATA_5_mux0000)
  );
  AND2   outDATA_4_mux00001 (
    .I0(NlwRenamedSig_OI_PWRint),
    .I1(\Flgreg[4] ),
    .O(outDATA_4_mux00001_525)
  );
  INV   outDATA_4_mux00002 (
    .I(NlwRenamedSig_OI_PWRint),
    .O(outDATA_4_mux00002_526)
  );
  AND2   outDATA_4_mux00003 (
    .I0(Hme133flg),
    .I1(outDATA_4_mux00002_526),
    .O(outDATA_4_mux00003_527)
  );
  OR2   outDATA_4_mux00004 (
    .I0(outDATA_4_mux00001_525),
    .I1(outDATA_4_mux00003_527),
    .O(outDATA_4_mux0000)
  );
  AND2   outDATA_3_mux00001 (
    .I0(NlwRenamedSig_OI_PWRint),
    .I1(\Flgreg[3] ),
    .O(outDATA_3_mux00001_521)
  );
  INV   outDATA_3_mux00002 (
    .I(NlwRenamedSig_OI_PWRint),
    .O(outDATA_3_mux00002_522)
  );
  AND2   outDATA_3_mux00003 (
    .I0(Enc05flg),
    .I1(outDATA_3_mux00002_522),
    .O(outDATA_3_mux00003_523)
  );
  OR2   outDATA_3_mux00004 (
    .I0(outDATA_3_mux00001_521),
    .I1(outDATA_3_mux00003_523),
    .O(outDATA_3_mux0000)
  );
  INV   outDATA_2_mux00001 (
    .I(NlwRenamedSig_OI_PWRint),
    .O(outDATA_2_mux00001_519)
  );
  OR2   outDATA_2_mux00002 (
    .I0(\Flgreg[6] ),
    .I1(outDATA_2_mux00001_519),
    .O(outDATA_2_mux0000)
  );
  AND2   outDATA_1_mux00001 (
    .I0(NlwRenamedSig_OI_PWRint),
    .I1(\Flgreg[1] ),
    .O(outDATA_1_mux00001_512)
  );
  INV   outDATA_1_mux00002 (
    .I(DCORENCPWRr),
    .O(outDATA_1_mux00002_513)
  );
  AND2   outDATA_1_mux00003 (
    .I0(Hme05flg),
    .I1(DCORENCPWRr),
    .O(outDATA_1_mux00003_514)
  );
  INV   outDATA_1_mux00004 (
    .I(NlwRenamedSig_OI_PWRint),
    .O(outDATA_1_mux00004_515)
  );
  AND2   outDATA_1_mux00005 (
    .I0(NlwRenamedSig_OI_PWRint),
    .I1(outDATA_1_mux00002_513),
    .O(outDATA_1_mux00005_516)
  );
  AND2   outDATA_1_mux00006 (
    .I0(outDATA_1_mux00003_514),
    .I1(outDATA_1_mux00004_515),
    .O(outDATA_1_mux00006_517)
  );
  OR3   outDATA_1_mux00007 (
    .I0(outDATA_1_mux00005_516),
    .I1(outDATA_1_mux00001_512),
    .I2(outDATA_1_mux00006_517),
    .O(outDATA_1_mux0000)
  );
  AND2   outDATA_0_mux00001 (
    .I0(NlwRenamedSig_OI_PWRint),
    .I1(\Flgreg[0] ),
    .O(outDATA_0_mux00001_508)
  );
  INV   outDATA_0_mux00002 (
    .I(NlwRenamedSig_OI_PWRint),
    .O(outDATA_0_mux00002_509)
  );
  AND2   outDATA_0_mux00003 (
    .I0(Hme033flg),
    .I1(outDATA_0_mux00002_509),
    .O(outDATA_0_mux00003_510)
  );
  OR2   outDATA_0_mux00004 (
    .I0(outDATA_0_mux00001_508),
    .I1(outDATA_0_mux00003_510),
    .O(outDATA_0_mux0000)
  );
  INV   DCORIFG_0_not00001 (
    .I(Mclk),
    .O(DCORIFG_0_not0000)
  );
  INV   Flgreg_and000011 (
    .I(NlwRenamedSig_OI_PWRint),
    .O(Flgreg_and00001)
  );
  AND2   Flgreg_and000012 (
    .I0(DCORIFG__or0000_bdd0),
    .I1(Flgreg_and00001),
    .O(Flgreg_and0000)
  );
  AND3   DCORIFG__or000031 (
    .I0(Hme133flg),
    .I1(Enc15flg),
    .I2(Hme15flg),
    .O(DCORIFG__or0000_bdd2)
  );
  INV   DCORIFG__or000021 (
    .I(Hme033flg),
    .O(DCORIFG__or00002)
  );
  INV   DCORIFG__or000022 (
    .I(Enc05flg),
    .O(DCORIFG__or000021_453)
  );
  INV   DCORIFG__or000023 (
    .I(Hme05flg),
    .O(DCORIFG__or000022_454)
  );
  INV   DCORIFG__or000024 (
    .I(DCORIFG__or0000_bdd2),
    .O(DCORIFG__or000023_455)
  );
  OR4   DCORIFG__or000025 (
    .I0(DCORIFG__or00002),
    .I1(DCORIFG__or000021_453),
    .I2(DCORIFG__or000022_454),
    .I3(DCORIFG__or000023_455),
    .O(DCORIFG__or0000_bdd0)
  );
  OR3   DCORIFG__or000011 (
    .I0(Reset),
    .I1(DCORIFGw),
    .I2(DCORIFG__or0000_bdd0),
    .O(DCORIFG__or0000)
  );
  INV   DCORIFG__and000011 (
    .I(inDATA[1]),
    .O(DCORIFG__and00001)
  );
  INV   DCORIFG__and000012 (
    .I(DCORIFGw),
    .O(DCORIFG__and000011_447)
  );
  INV   DCORIFG__and000013 (
    .I(Reset),
    .O(DCORIFG__and000012_448)
  );
  AND2   DCORIFG__and000014 (
    .I0(NlwRenamedSig_OI_PWRint),
    .I1(DCORIFG__and00001),
    .O(DCORIFG__and000013_449)
  );
  OR2   DCORIFG__and000015 (
    .I0(DCORIFG__and000013_449),
    .I1(DCORIFG__and000011_447),
    .O(DCORIFG__and000014_450)
  );
  AND2   DCORIFG__and000016 (
    .I0(DCORIFG__and000014_450),
    .I1(DCORIFG__and000012_448),
    .O(DCORIFG__and0000)
  );
  OR2   \outDATA<1>_not000011  (
    .I0(DCORIFGr),
    .I1(DCORENCPWRr),
    .O(\outDATA<1>_not0000 )
  );
endmodule

module Interrupt (
  PWRint, Reset, I2Cint, DCORIFGr, Homed0, Homed1, BusInt, TP, DCORIEw, Thres0, Thres1, LSwitchInt, Mclk, INT, outDATA, inDATA
);
  input PWRint;
  input Reset;
  input I2Cint;
  input DCORIFGr;
  input Homed0;
  input Homed1;
  input BusInt;
  output TP;
  input DCORIEw;
  input Thres0;
  input Thres1;
  input LSwitchInt;
  input Mclk;
  output INT;
  output [7 : 0] outDATA;
  input [7 : 0] inDATA;
  wire \DCORIE[0] ;
  wire DCORIE_0_0_not0000;
  wire DCORIE_0__and0000;
  wire DCORIE_0__and00001_375;
  wire DCORIE_0__or0000;
  wire \DCORIE[1] ;
  wire DCORIE_1__and0000;
  wire DCORIE_1__and00001_379;
  wire \DCORIE[2] ;
  wire DCORIE_2__and0000;
  wire DCORIE_2__and00001_382;
  wire \DCORIE[3] ;
  wire DCORIE_3__and0000;
  wire DCORIE_3__and00001_385;
  wire \DCORIE[4] ;
  wire DCORIE_4__and0000;
  wire DCORIE_4__and00001_388;
  wire DCORIE_5__and0000;
  wire DCORIE_5__and00001_390;
  wire \DCORIE[6] ;
  wire DCORIE_6__and0000;
  wire DCORIE_6__and00001_393;
  wire \DCORIE[7] ;
  wire DCORIE_7__and0000;
  wire DCORIE_7__and00001_396;
  wire INT1_403;
  wire INT2_404;
  wire N0;
  wire SFDecomp_1;
  wire SFDecomp_11;
  wire SFDecomp_12;
  wire SFDecomp_121_413;
  wire SFDecomp_13;
  wire SFDecomp_14;
  wire SFDecomp_141_416;
  wire SFDecomp_15;
  wire SFDecomp_151_418;
  wire SFDecomp_16_419;
  wire SFDecomp_2;
  wire SFDecomp_21_421;
  wire SFDecomp_22_422;
  wire NlwRenamedSig_OI_TP;
  assign
    TP = NlwRenamedSig_OI_TP;
  GND   XST_GND (
    .G(N0)
  );
  BUFE   \outDATA<0>_BusInt_0  (
    .I(BusInt),
    .E(DCORIFGr),
    .O(outDATA[0])
  );
  BUFE   \outDATA<1>_0  (
    .I(N0),
    .E(N0),
    .O(outDATA[1])
  );
  BUFE   \outDATA<2>_0  (
    .I(N0),
    .E(N0),
    .O(outDATA[2])
  );
  BUFE   \outDATA<3>_0  (
    .I(N0),
    .E(N0),
    .O(outDATA[3])
  );
  BUFE   \outDATA<4>_LSwitchInt_0  (
    .I(LSwitchInt),
    .E(DCORIFGr),
    .O(outDATA[4])
  );
  BUFE   \outDATA<5>_0  (
    .I(N0),
    .E(N0),
    .O(outDATA[5])
  );
  BUFE   \outDATA<6>_0  (
    .I(N0),
    .E(N0),
    .O(outDATA[6])
  );
  BUFE   \outDATA<7>_I2Cint_0  (
    .I(I2Cint),
    .E(DCORIFGr),
    .O(outDATA[7])
  );
  FDCE   DCORIE_0 (
    .CE(DCORIE_0__or0000),
    .CLR(N0),
    .C(DCORIE_0_0_not0000),
    .D(DCORIE_0__and0000),
    .Q(\DCORIE[0] )
  );
  FDCE   DCORIE_1 (
    .CE(DCORIE_0__or0000),
    .CLR(N0),
    .C(DCORIE_0_0_not0000),
    .D(DCORIE_1__and0000),
    .Q(\DCORIE[1] )
  );
  FDCE   DCORIE_2 (
    .CE(DCORIE_0__or0000),
    .CLR(N0),
    .C(DCORIE_0_0_not0000),
    .D(DCORIE_2__and0000),
    .Q(\DCORIE[2] )
  );
  FDCE   DCORIE_3 (
    .CE(DCORIE_0__or0000),
    .CLR(N0),
    .C(DCORIE_0_0_not0000),
    .D(DCORIE_3__and0000),
    .Q(\DCORIE[3] )
  );
  FDCE   DCORIE_4 (
    .CE(DCORIE_0__or0000),
    .CLR(N0),
    .C(DCORIE_0_0_not0000),
    .D(DCORIE_4__and0000),
    .Q(\DCORIE[4] )
  );
  FDCE   DCORIE_5 (
    .CE(DCORIE_0__or0000),
    .CLR(N0),
    .C(DCORIE_0_0_not0000),
    .D(DCORIE_5__and0000),
    .Q(NlwRenamedSig_OI_TP)
  );
  FDCE   DCORIE_6 (
    .CE(DCORIE_0__or0000),
    .CLR(N0),
    .C(DCORIE_0_0_not0000),
    .D(DCORIE_6__and0000),
    .Q(\DCORIE[6] )
  );
  FDCE   DCORIE_7 (
    .CE(DCORIE_0__or0000),
    .CLR(N0),
    .C(DCORIE_0_0_not0000),
    .D(DCORIE_7__and0000),
    .Q(\DCORIE[7] )
  );
  INV   DCORIE_0__and00001 (
    .I(Reset),
    .O(DCORIE_0__and00001_375)
  );
  AND2   DCORIE_0__and00002 (
    .I0(inDATA[0]),
    .I1(DCORIE_0__and00001_375),
    .O(DCORIE_0__and0000)
  );
  OR2   DCORIE_0__or00001 (
    .I0(DCORIEw),
    .I1(Reset),
    .O(DCORIE_0__or0000)
  );
  INV   DCORIE_0_0_not00001 (
    .I(Mclk),
    .O(DCORIE_0_0_not0000)
  );
  INV   DCORIE_1__and00001 (
    .I(Reset),
    .O(DCORIE_1__and00001_379)
  );
  AND2   DCORIE_1__and00002 (
    .I0(inDATA[1]),
    .I1(DCORIE_1__and00001_379),
    .O(DCORIE_1__and0000)
  );
  INV   DCORIE_2__and00001 (
    .I(Reset),
    .O(DCORIE_2__and00001_382)
  );
  AND2   DCORIE_2__and00002 (
    .I0(inDATA[2]),
    .I1(DCORIE_2__and00001_382),
    .O(DCORIE_2__and0000)
  );
  INV   DCORIE_3__and00001 (
    .I(Reset),
    .O(DCORIE_3__and00001_385)
  );
  AND2   DCORIE_3__and00002 (
    .I0(inDATA[3]),
    .I1(DCORIE_3__and00001_385),
    .O(DCORIE_3__and0000)
  );
  INV   DCORIE_4__and00001 (
    .I(Reset),
    .O(DCORIE_4__and00001_388)
  );
  AND2   DCORIE_4__and00002 (
    .I0(inDATA[4]),
    .I1(DCORIE_4__and00001_388),
    .O(DCORIE_4__and0000)
  );
  INV   DCORIE_5__and00001 (
    .I(Reset),
    .O(DCORIE_5__and00001_390)
  );
  AND2   DCORIE_5__and00002 (
    .I0(inDATA[5]),
    .I1(DCORIE_5__and00001_390),
    .O(DCORIE_5__and0000)
  );
  INV   DCORIE_6__and00001 (
    .I(Reset),
    .O(DCORIE_6__and00001_393)
  );
  AND2   DCORIE_6__and00002 (
    .I0(inDATA[6]),
    .I1(DCORIE_6__and00001_393),
    .O(DCORIE_6__and0000)
  );
  INV   DCORIE_7__and00001 (
    .I(Reset),
    .O(DCORIE_7__and00001_396)
  );
  AND2   DCORIE_7__and00002 (
    .I0(inDATA[7]),
    .I1(DCORIE_7__and00001_396),
    .O(DCORIE_7__and0000)
  );
  INV   SFDecomp_21 (
    .I(BusInt),
    .O(SFDecomp_21_421)
  );
  AND2   SFDecomp_22 (
    .I0(\DCORIE[0] ),
    .I1(SFDecomp_21_421),
    .O(SFDecomp_22_422)
  );
  OR2   SFDecomp_23 (
    .I0(SFDecomp_12),
    .I1(SFDecomp_22_422),
    .O(SFDecomp_2)
  );
  AND2   SFDecomp_16 (
    .I0(\DCORIE[6] ),
    .I1(Thres1),
    .O(SFDecomp_16_419)
  );
  OR2   SFDecomp_17 (
    .I0(SFDecomp_14),
    .I1(SFDecomp_16_419),
    .O(SFDecomp_1)
  );
  OR2   INT1 (
    .I0(SFDecomp_2),
    .I1(SFDecomp_15),
    .O(INT1_403)
  );
  AND2   INT2 (
    .I0(\DCORIE[4] ),
    .I1(LSwitchInt),
    .O(INT2_404)
  );
  OR2   INT3 (
    .I0(INT1_403),
    .I1(INT2_404),
    .O(INT)
  );
  AND2   SFDecomp_111 (
    .I0(\DCORIE[1] ),
    .I1(PWRint),
    .O(SFDecomp_11)
  );
  AND2   SFDecomp_121 (
    .I0(\DCORIE[2] ),
    .I1(Homed0),
    .O(SFDecomp_121_413)
  );
  OR2   SFDecomp_122 (
    .I0(SFDecomp_11),
    .I1(SFDecomp_121_413),
    .O(SFDecomp_12)
  );
  AND2   SFDecomp_131 (
    .I0(\DCORIE[7] ),
    .I1(I2Cint),
    .O(SFDecomp_13)
  );
  AND2   SFDecomp_141 (
    .I0(NlwRenamedSig_OI_TP),
    .I1(Thres0),
    .O(SFDecomp_141_416)
  );
  OR2   SFDecomp_142 (
    .I0(SFDecomp_13),
    .I1(SFDecomp_141_416),
    .O(SFDecomp_14)
  );
  AND2   SFDecomp_151 (
    .I0(\DCORIE[3] ),
    .I1(Homed1),
    .O(SFDecomp_151_418)
  );
  OR2   SFDecomp_152 (
    .I0(SFDecomp_1),
    .I1(SFDecomp_151_418),
    .O(SFDecomp_15)
  );
endmodule

module PWMtranslator_INST_1 (
  PWM, RLS, DIR, fBRK, PAH, PAL, PBH, FLS, PBL, Brake, HBRK, MTRpwr
);
  input PWM;
  input RLS;
  input DIR;
  input fBRK;
  output PAH;
  output PAL;
  output PBH;
  input FLS;
  output PBL;
  input Brake;
  input HBRK;
  input MTRpwr;
  wire BRK;
  wire N01;
  wire PAH1_329;
  wire PAH2_330;
  wire PAL_or0000;
  wire PAL_or00001_333;
  wire PBH1_335;
  wire PBH2_336;
  wire PBL_or0000;
  wire PBL_or00001_339;
  wire PBL_or00002_340;
  wire SFDecomp_1;
  wire SFDecomp_11_344;
  wire SFDecomp_12_345;
  wire SFDecomp_2;
  OR3   BRK1 (
    .I0(Brake),
    .I1(HBRK),
    .I2(fBRK),
    .O(BRK)
  );
  AND2   PAH1 (
    .I0(MTRpwr),
    .I1(SFDecomp_1),
    .O(PAH1_329)
  );
  INV   PAH2 (
    .I(BRK),
    .O(PAH2_330)
  );
  AND2   PAH3 (
    .I0(PAH1_329),
    .I1(PAH2_330),
    .O(PAH)
  );
  AND2   PAL1 (
    .I0(PAL_or0000),
    .I1(MTRpwr),
    .O(PAL)
  );
  AND2   PBH1 (
    .I0(MTRpwr),
    .I1(SFDecomp_2),
    .O(PBH1_335)
  );
  INV   PBH2 (
    .I(BRK),
    .O(PBH2_336)
  );
  AND2   PBH3 (
    .I0(PBH1_335),
    .I1(PBH2_336),
    .O(PBH)
  );
  AND2   PBL1 (
    .I0(PBL_or0000),
    .I1(MTRpwr),
    .O(PBL)
  );
  AND2   SFDecomp_11 (
    .I0(RLS),
    .I1(PWM),
    .O(SFDecomp_11_344)
  );
  INV   SFDecomp_12 (
    .I(DIR),
    .O(SFDecomp_12_345)
  );
  AND2   SFDecomp_13 (
    .I0(SFDecomp_11_344),
    .I1(SFDecomp_12_345),
    .O(SFDecomp_1)
  );
  AND3   SFDecomp_21 (
    .I0(PWM),
    .I1(DIR),
    .I2(FLS),
    .O(SFDecomp_2)
  );
  XOR2   PAL_or000011 (
    .I0(PWM),
    .I1(DIR),
    .O(N01)
  );
  INV   PAL_or00001 (
    .I(BRK),
    .O(PAL_or00001_333)
  );
  AND2   PAL_or00002 (
    .I0(N01),
    .I1(PAL_or00001_333),
    .O(PAL_or0000)
  );
  INV   PBL_or00001 (
    .I(BRK),
    .O(PBL_or00001_339)
  );
  INV   PBL_or00002 (
    .I(N01),
    .O(PBL_or00002_340)
  );
  AND2   PBL_or00003 (
    .I0(PBL_or00001_339),
    .I1(PBL_or00002_340),
    .O(PBL_or0000)
  );
endmodule

module PWMtranslator (
  PWM, RLS, DIR, fBRK, PAH, PAL, PBH, FLS, PBL, Brake, HBRK, MTRpwr
);
  input PWM;
  input RLS;
  input DIR;
  input fBRK;
  output PAH;
  output PAL;
  output PBH;
  input FLS;
  output PBL;
  input Brake;
  input HBRK;
  input MTRpwr;
  wire BRK;
  wire N01;
  wire PAH1_302;
  wire PAH2_303;
  wire PAL_or0000;
  wire PAL_or00001_306;
  wire PBH1_308;
  wire PBH2_309;
  wire PBL_or0000;
  wire PBL_or00001_312;
  wire PBL_or00002_313;
  wire SFDecomp_1;
  wire SFDecomp_11_317;
  wire SFDecomp_12_318;
  wire SFDecomp_2;
  OR3   BRK1 (
    .I0(Brake),
    .I1(HBRK),
    .I2(fBRK),
    .O(BRK)
  );
  AND2   PAH1 (
    .I0(MTRpwr),
    .I1(SFDecomp_1),
    .O(PAH1_302)
  );
  INV   PAH2 (
    .I(BRK),
    .O(PAH2_303)
  );
  AND2   PAH3 (
    .I0(PAH1_302),
    .I1(PAH2_303),
    .O(PAH)
  );
  AND2   PAL1 (
    .I0(PAL_or0000),
    .I1(MTRpwr),
    .O(PAL)
  );
  AND2   PBH1 (
    .I0(MTRpwr),
    .I1(SFDecomp_2),
    .O(PBH1_308)
  );
  INV   PBH2 (
    .I(BRK),
    .O(PBH2_309)
  );
  AND2   PBH3 (
    .I0(PBH1_308),
    .I1(PBH2_309),
    .O(PBH)
  );
  AND2   PBL1 (
    .I0(PBL_or0000),
    .I1(MTRpwr),
    .O(PBL)
  );
  AND2   SFDecomp_11 (
    .I0(RLS),
    .I1(PWM),
    .O(SFDecomp_11_317)
  );
  INV   SFDecomp_12 (
    .I(DIR),
    .O(SFDecomp_12_318)
  );
  AND2   SFDecomp_13 (
    .I0(SFDecomp_11_317),
    .I1(SFDecomp_12_318),
    .O(SFDecomp_1)
  );
  AND3   SFDecomp_21 (
    .I0(PWM),
    .I1(DIR),
    .I2(FLS),
    .O(SFDecomp_2)
  );
  XOR2   PAL_or000011 (
    .I0(PWM),
    .I1(DIR),
    .O(N01)
  );
  INV   PAL_or00001 (
    .I(BRK),
    .O(PAL_or00001_306)
  );
  AND2   PAL_or00002 (
    .I0(N01),
    .I1(PAL_or00001_306),
    .O(PAL_or0000)
  );
  INV   PBL_or00001 (
    .I(BRK),
    .O(PBL_or00001_312)
  );
  INV   PBL_or00002 (
    .I(N01),
    .O(PBL_or00002_313)
  );
  AND2   PBL_or00003 (
    .I0(PBL_or00001_312),
    .I1(PBL_or00002_313),
    .O(PBL_or0000)
  );
endmodule

module PWMcontrol (
  Brake1, Brake2, fBRK1, fBRK2, PWM1, PWM2, PAH1, RLS0, PAH2, RLS1, PAL1, PAL2, PBH1, PBH2, FLS0, FLS1, PBL1, PBL2, HBRK1, HBRK2, DIR1, DIR2, MTRpwr
);
  input Brake1;
  input Brake2;
  input fBRK1;
  input fBRK2;
  input PWM1;
  input PWM2;
  output PAH1;
  input RLS0;
  output PAH2;
  input RLS1;
  output PAL1;
  output PAL2;
  output PBH1;
  output PBH2;
  input FLS0;
  input FLS1;
  output PBL1;
  output PBL2;
  input HBRK1;
  input HBRK2;
  input DIR1;
  input DIR2;
  input MTRpwr;
  PWMtranslator   U2 (
    .PWM(PWM2),
    .RLS(RLS1),
    .DIR(DIR2),
    .fBRK(fBRK2),
    .PAH(PAH2),
    .PAL(PAL2),
    .PBH(PBH2),
    .FLS(FLS1),
    .PBL(PBL2),
    .Brake(Brake2),
    .HBRK(HBRK2),
    .MTRpwr(MTRpwr)
  );
  PWMtranslator_INST_1   U1 (
    .PWM(PWM1),
    .RLS(RLS0),
    .DIR(DIR1),
    .fBRK(fBRK1),
    .PAH(PAH1),
    .PAL(PAL1),
    .PBH(PBH1),
    .FLS(FLS0),
    .PBL(PBL1),
    .Brake(Brake1),
    .HBRK(HBRK1),
    .MTRpwr(MTRpwr)
  );
endmodule

module NegDetect_INST_2 (
  Line, Ndetect, Mclk
);
  input Line;
  output Ndetect;
  input Mclk;
  wire Line_last_288;
  wire Ndetectr_0_not0000;
  wire Ndetectr__and0000;
  wire Ndetectr_and0000;
  FD   Ndetectr (
    .C(Ndetectr_0_not0000),
    .D(Ndetectr__and0000),
    .Q(Ndetect)
  );
  FD   Line_last (
    .C(Ndetectr_0_not0000),
    .D(Line),
    .Q(Line_last_288)
  );
  INV   Ndetectr_and00001 (
    .I(Line),
    .O(Ndetectr_and0000)
  );
  AND2   Ndetectr_and00002 (
    .I0(Line_last_288),
    .I1(Ndetectr_and0000),
    .O(Ndetectr__and0000)
  );
  INV   Ndetectr_0_not00001 (
    .I(Mclk),
    .O(Ndetectr_0_not0000)
  );
endmodule

module NegDetect_INST_1 (
  Line, Ndetect, Mclk
);
  input Line;
  output Ndetect;
  input Mclk;
  wire Line_last_281;
  wire Ndetectr_0_not0000;
  wire Ndetectr__and0000;
  wire Ndetectr_and0000;
  FD   Ndetectr (
    .C(Ndetectr_0_not0000),
    .D(Ndetectr__and0000),
    .Q(Ndetect)
  );
  FD   Line_last (
    .C(Ndetectr_0_not0000),
    .D(Line),
    .Q(Line_last_281)
  );
  INV   Ndetectr_and00001 (
    .I(Line),
    .O(Ndetectr_and0000)
  );
  AND2   Ndetectr_and00002 (
    .I0(Line_last_281),
    .I1(Ndetectr_and0000),
    .O(Ndetectr__and0000)
  );
  INV   Ndetectr_0_not00001 (
    .I(Mclk),
    .O(Ndetectr_0_not0000)
  );
endmodule

module NegDetect (
  Line, Ndetect, Mclk
);
  input Line;
  output Ndetect;
  input Mclk;
  wire Line_last_274;
  wire Ndetectr_0_not0000;
  wire Ndetectr__and0000;
  wire Ndetectr_and0000;
  FD   Ndetectr (
    .C(Ndetectr_0_not0000),
    .D(Ndetectr__and0000),
    .Q(Ndetect)
  );
  FD   Line_last (
    .C(Ndetectr_0_not0000),
    .D(Line),
    .Q(Line_last_274)
  );
  INV   Ndetectr_and00001 (
    .I(Line),
    .O(Ndetectr_and0000)
  );
  AND2   Ndetectr_and00002 (
    .I0(Line_last_274),
    .I1(Ndetectr_and0000),
    .O(Ndetectr__and0000)
  );
  INV   Ndetectr_0_not00001 (
    .I(Mclk),
    .O(Ndetectr_0_not0000)
  );
endmodule

module I2CAddress (
  DCORCONFIGr, MotorIn0, MotorIn1, outDATA, I2CS
);
  input DCORCONFIGr;
  input MotorIn0;
  input MotorIn1;
  output [7 : 0] outDATA;
  input [5 : 0] I2CS;
  BUFE   \outDATA<7>_MotorIn1_0  (
    .I(MotorIn1),
    .E(DCORCONFIGr),
    .O(outDATA[7])
  );
  BUFE   \outDATA<6>_MotorIn0_0  (
    .I(MotorIn0),
    .E(DCORCONFIGr),
    .O(outDATA[6])
  );
  BUFE   \outDATA<5>_I2CS<5>_0  (
    .I(I2CS[5]),
    .E(DCORCONFIGr),
    .O(outDATA[5])
  );
  BUFE   \outDATA<4>_I2CS<4>_0  (
    .I(I2CS[4]),
    .E(DCORCONFIGr),
    .O(outDATA[4])
  );
  BUFE   \outDATA<3>_I2CS<3>_0  (
    .I(I2CS[3]),
    .E(DCORCONFIGr),
    .O(outDATA[3])
  );
  BUFE   \outDATA<2>_I2CS<2>_0  (
    .I(I2CS[2]),
    .E(DCORCONFIGr),
    .O(outDATA[2])
  );
  BUFE   \outDATA<1>_I2CS<1>_0  (
    .I(I2CS[1]),
    .E(DCORCONFIGr),
    .O(outDATA[1])
  );
  BUFE   \outDATA<0>_I2CS<0>_0  (
    .I(I2CS[0]),
    .E(DCORCONFIGr),
    .O(outDATA[0])
  );
endmodule

module Lswitch (
  Brake0, Brake1, DCORLINTr, Reset, fBRK0, fBRK1, DCORLIMITSr, Home0, Home1, RLS0, RLS1, DCORIFGw, FLS0, FLS1, LSwitchInt, LIFG, DIR0, DIR1, Mclk, 
outDATA
);
  input Brake0;
  input Brake1;
  input DCORLINTr;
  input Reset;
  output fBRK0;
  output fBRK1;
  input DCORLIMITSr;
  input Home0;
  input Home1;
  input RLS0;
  input RLS1;
  input DCORIFGw;
  input FLS0;
  input FLS1;
  output LSwitchInt;
  input LIFG;
  input DIR0;
  input DIR1;
  input Mclk;
  output [7 : 0] outDATA;
  wire DCORIFG_0_not0000;
  wire DCORIFG__and0000;
  wire DCORIFG__and00001;
  wire DCORIFG__and000011_149;
  wire DCORIFG__and000012_150;
  wire DCORIFG__and000013_151;
  wire DCORIFG__and000014_152;
  wire DCORIFG__or0000;
  wire DCORIFG__or0000_bdd0;
  wire FLS0fr_161;
  wire FLS0fr__and0000;
  wire FLS0fr__and00001_163;
  wire FLS0fr__or0000;
  wire FLS0r_165;
  wire FLS0r__and0000;
  wire FLS0r__and00001_167;
  wire FLS1fr_169;
  wire FLS1fr__or0000;
  wire FLS1r_171;
  wire FLS1r__and0000;
  wire FLS1r__and00001_173;
  wire Ftrip0;
  wire Ftrip01_175;
  wire Ftrip02_176;
  wire Ftrip1;
  wire Ftrip11_178;
  wire Ftrip12_179;
  wire NlwRenamedSig_OI_LSwitchInt;
  wire N0;
  wire RLS0fr_187;
  wire RLS0fr__or0000;
  wire RLS0r_189;
  wire RLS0r__and0000;
  wire RLS0r__and00001_191;
  wire RLS1fr_193;
  wire RLS1fr__or0000;
  wire RLS1r_195;
  wire RLS1r__and0000;
  wire RLS1r__and00001_197;
  wire Rtrip0;
  wire Rtrip01_200;
  wire Rtrip02_201;
  wire Rtrip1;
  wire Rtrip11_203;
  wire Rtrip12_204;
  wire NlwRenamedSig_OI_fBRK0;
  wire fBRK0r_and0000;
  wire fBRK0r_and00001_207;
  wire fBRK0r_and00002_208;
  wire fBRK0r_not0001;
  wire fBRK0r_or0000;
  wire fBRK0r_or00001_211;
  wire fBRK0r_or00002_212;
  wire fBRK0r_or0001;
  wire fBRK0r_or0002;
  wire NlwRenamedSig_OI_fBRK1;
  wire fBRK1r_and0000;
  wire fBRK1r_and00001_217;
  wire fBRK1r_and00002_218;
  wire fBRK1r_not0001;
  wire fBRK1r_or0000;
  wire fBRK1r_or00001_221;
  wire fBRK1r_or00002_222;
  wire fBRK1r_or0001;
  wire fBRK1r_or0002;
  wire \outDATA_mux0000[0] ;
  wire \outDATA_mux0000<0>1_234 ;
  wire \outDATA_mux0000<0>2_235 ;
  wire \outDATA_mux0000<0>3_236 ;
  wire \outDATA_mux0000<0>4_237 ;
  wire \outDATA_mux0000[1] ;
  wire \outDATA_mux0000<1>1_239 ;
  wire \outDATA_mux0000<1>2_240 ;
  wire \outDATA_mux0000<1>3_241 ;
  wire \outDATA_mux0000<1>4_242 ;
  wire \outDATA_mux0000[2] ;
  wire \outDATA_mux0000[4] ;
  wire \outDATA_mux0000<4>1_245 ;
  wire \outDATA_mux0000<4>2_246 ;
  wire \outDATA_mux0000<4>3_247 ;
  wire \outDATA_mux0000<4>4_248 ;
  wire \outDATA_mux0000[5] ;
  wire \outDATA_mux0000<5>1_250 ;
  wire \outDATA_mux0000<5>2_251 ;
  wire \outDATA_mux0000<5>3_252 ;
  wire \outDATA_mux0000<5>4_253 ;
  wire \outDATA_mux0000[6] ;
  wire outDATA_not0005;
  assign
    fBRK0 = NlwRenamedSig_OI_fBRK0,
    fBRK1 = NlwRenamedSig_OI_fBRK1,
    LSwitchInt = NlwRenamedSig_OI_LSwitchInt;
  GND   XST_GND (
    .G(N0)
  );
  FD   RLS1r (
    .C(DCORIFG_0_not0000),
    .D(RLS1r__and0000),
    .Q(RLS1r_195)
  );
  FD   FLS1r (
    .C(DCORIFG_0_not0000),
    .D(FLS1r__and0000),
    .Q(FLS1r_171)
  );
  FD   RLS0r (
    .C(DCORIFG_0_not0000),
    .D(RLS0r__and0000),
    .Q(RLS0r_189)
  );
  FD   FLS0r (
    .C(DCORIFG_0_not0000),
    .D(FLS0r__and0000),
    .Q(FLS0r_165)
  );
  FDCE   DCORIFG (
    .CE(DCORIFG__or0000),
    .CLR(N0),
    .C(DCORIFG_0_not0000),
    .D(DCORIFG__and0000),
    .Q(NlwRenamedSig_OI_LSwitchInt)
  );
  FDCE   RLS1fr (
    .CE(RLS1fr__or0000),
    .CLR(N0),
    .C(DCORIFG_0_not0000),
    .D(FLS0fr__and0000),
    .Q(RLS1fr_193)
  );
  FDCE   FLS1fr (
    .CE(FLS1fr__or0000),
    .CLR(N0),
    .C(DCORIFG_0_not0000),
    .D(FLS0fr__and0000),
    .Q(FLS1fr_169)
  );
  FDCE   RLS0fr (
    .CE(RLS0fr__or0000),
    .CLR(N0),
    .C(DCORIFG_0_not0000),
    .D(FLS0fr__and0000),
    .Q(RLS0fr_187)
  );
  FDCE   FLS0fr (
    .CE(FLS0fr__or0000),
    .CLR(N0),
    .C(DCORIFG_0_not0000),
    .D(FLS0fr__and0000),
    .Q(FLS0fr_161)
  );
  FDCE   fBRK1r (
    .CE(fBRK1r_not0001),
    .CLR(N0),
    .C(DCORIFG_0_not0000),
    .D(fBRK1r_or0002),
    .Q(NlwRenamedSig_OI_fBRK1)
  );
  FDCE   fBRK0r (
    .CE(fBRK0r_not0001),
    .CLR(N0),
    .C(DCORIFG_0_not0000),
    .D(fBRK0r_or0002),
    .Q(NlwRenamedSig_OI_fBRK0)
  );
  BUFE   outDATA_7 (
    .I(NlwRenamedSig_OI_fBRK1),
    .E(outDATA_not0005),
    .O(outDATA[7])
  );
  BUFE   outDATA_6 (
    .I(\outDATA_mux0000[6] ),
    .E(outDATA_not0005),
    .O(outDATA[6])
  );
  BUFE   outDATA_5 (
    .I(\outDATA_mux0000[5] ),
    .E(outDATA_not0005),
    .O(outDATA[5])
  );
  BUFE   outDATA_4 (
    .I(\outDATA_mux0000[4] ),
    .E(outDATA_not0005),
    .O(outDATA[4])
  );
  BUFE   outDATA_3 (
    .I(NlwRenamedSig_OI_fBRK0),
    .E(outDATA_not0005),
    .O(outDATA[3])
  );
  BUFE   outDATA_2 (
    .I(\outDATA_mux0000[2] ),
    .E(outDATA_not0005),
    .O(outDATA[2])
  );
  BUFE   outDATA_1 (
    .I(\outDATA_mux0000[1] ),
    .E(outDATA_not0005),
    .O(outDATA[1])
  );
  BUFE   outDATA_0 (
    .I(\outDATA_mux0000[0] ),
    .E(outDATA_not0005),
    .O(outDATA[0])
  );
  AND2   \outDATA_mux0000<6>1  (
    .I0(DCORLIMITSr),
    .I1(Home1),
    .O(\outDATA_mux0000[6] )
  );
  INV   \outDATA_mux0000<5>1  (
    .I(DCORLIMITSr),
    .O(\outDATA_mux0000<5>1_250 )
  );
  INV   \outDATA_mux0000<5>2  (
    .I(FLS1),
    .O(\outDATA_mux0000<5>2_251 )
  );
  AND2   \outDATA_mux0000<5>3  (
    .I0(FLS1fr_169),
    .I1(\outDATA_mux0000<5>1_250 ),
    .O(\outDATA_mux0000<5>3_252 )
  );
  AND2   \outDATA_mux0000<5>4  (
    .I0(DCORLIMITSr),
    .I1(\outDATA_mux0000<5>2_251 ),
    .O(\outDATA_mux0000<5>4_253 )
  );
  OR2   \outDATA_mux0000<5>5  (
    .I0(\outDATA_mux0000<5>3_252 ),
    .I1(\outDATA_mux0000<5>4_253 ),
    .O(\outDATA_mux0000[5] )
  );
  INV   \outDATA_mux0000<4>1  (
    .I(DCORLIMITSr),
    .O(\outDATA_mux0000<4>1_245 )
  );
  INV   \outDATA_mux0000<4>2  (
    .I(RLS1),
    .O(\outDATA_mux0000<4>2_246 )
  );
  AND2   \outDATA_mux0000<4>3  (
    .I0(RLS1fr_193),
    .I1(\outDATA_mux0000<4>1_245 ),
    .O(\outDATA_mux0000<4>3_247 )
  );
  AND2   \outDATA_mux0000<4>4  (
    .I0(DCORLIMITSr),
    .I1(\outDATA_mux0000<4>2_246 ),
    .O(\outDATA_mux0000<4>4_248 )
  );
  OR2   \outDATA_mux0000<4>5  (
    .I0(\outDATA_mux0000<4>3_247 ),
    .I1(\outDATA_mux0000<4>4_248 ),
    .O(\outDATA_mux0000[4] )
  );
  AND2   \outDATA_mux0000<2>1  (
    .I0(DCORLIMITSr),
    .I1(Home0),
    .O(\outDATA_mux0000[2] )
  );
  INV   \outDATA_mux0000<1>1  (
    .I(DCORLIMITSr),
    .O(\outDATA_mux0000<1>1_239 )
  );
  INV   \outDATA_mux0000<1>2  (
    .I(FLS0),
    .O(\outDATA_mux0000<1>2_240 )
  );
  AND2   \outDATA_mux0000<1>3  (
    .I0(FLS0fr_161),
    .I1(\outDATA_mux0000<1>1_239 ),
    .O(\outDATA_mux0000<1>3_241 )
  );
  AND2   \outDATA_mux0000<1>4  (
    .I0(DCORLIMITSr),
    .I1(\outDATA_mux0000<1>2_240 ),
    .O(\outDATA_mux0000<1>4_242 )
  );
  OR2   \outDATA_mux0000<1>5  (
    .I0(\outDATA_mux0000<1>3_241 ),
    .I1(\outDATA_mux0000<1>4_242 ),
    .O(\outDATA_mux0000[1] )
  );
  INV   \outDATA_mux0000<0>1  (
    .I(DCORLIMITSr),
    .O(\outDATA_mux0000<0>1_234 )
  );
  INV   \outDATA_mux0000<0>2  (
    .I(RLS0),
    .O(\outDATA_mux0000<0>2_235 )
  );
  AND2   \outDATA_mux0000<0>3  (
    .I0(RLS0fr_187),
    .I1(\outDATA_mux0000<0>1_234 ),
    .O(\outDATA_mux0000<0>3_236 )
  );
  AND2   \outDATA_mux0000<0>4  (
    .I0(DCORLIMITSr),
    .I1(\outDATA_mux0000<0>2_235 ),
    .O(\outDATA_mux0000<0>4_237 )
  );
  OR2   \outDATA_mux0000<0>5  (
    .I0(\outDATA_mux0000<0>3_236 ),
    .I1(\outDATA_mux0000<0>4_237 ),
    .O(\outDATA_mux0000[0] )
  );
  INV   FLS0r__and00001 (
    .I(Reset),
    .O(FLS0r__and00001_167)
  );
  AND2   FLS0r__and00002 (
    .I0(FLS0),
    .I1(FLS0r__and00001_167),
    .O(FLS0r__and0000)
  );
  INV   RLS0r__and00001 (
    .I(Reset),
    .O(RLS0r__and00001_191)
  );
  AND2   RLS0r__and00002 (
    .I0(RLS0),
    .I1(RLS0r__and00001_191),
    .O(RLS0r__and0000)
  );
  INV   FLS1r__and00001 (
    .I(Reset),
    .O(FLS1r__and00001_173)
  );
  AND2   FLS1r__and00002 (
    .I0(FLS1),
    .I1(FLS1r__and00001_173),
    .O(FLS1r__and0000)
  );
  INV   RLS1r__and00001 (
    .I(Reset),
    .O(RLS1r__and00001_197)
  );
  AND2   RLS1r__and00002 (
    .I0(RLS1),
    .I1(RLS1r__and00001_197),
    .O(RLS1r__and0000)
  );
  INV   DCORIFG_0_not00001 (
    .I(Mclk),
    .O(DCORIFG_0_not0000)
  );
  OR3   RLS1fr__or00001 (
    .I0(Rtrip1),
    .I1(DCORLINTr),
    .I2(Reset),
    .O(RLS1fr__or0000)
  );
  OR2   fBRK1r_or00021 (
    .I0(Rtrip1),
    .I1(Ftrip1),
    .O(fBRK1r_or0002)
  );
  INV   Rtrip11 (
    .I(RLS1),
    .O(Rtrip11_203)
  );
  INV   Rtrip12 (
    .I(DIR1),
    .O(Rtrip12_204)
  );
  AND3   Rtrip13 (
    .I0(Rtrip11_203),
    .I1(RLS1r_195),
    .I2(Rtrip12_204),
    .O(Rtrip1)
  );
  OR2   fBRK1r_or00001 (
    .I0(RLS1fr_193),
    .I1(FLS1fr_169),
    .O(fBRK1r_or00001_221)
  );
  INV   fBRK1r_or00002 (
    .I(Brake1),
    .O(fBRK1r_or00002_222)
  );
  OR2   fBRK1r_or00003 (
    .I0(fBRK1r_or00001_221),
    .I1(fBRK1r_or00002_222),
    .O(fBRK1r_or0000)
  );
  INV   fBRK1r_not00011 (
    .I(fBRK1r_or0001),
    .O(fBRK1r_not0001)
  );
  OR3   fBRK1r_or00011 (
    .I0(DCORLINTr),
    .I1(fBRK1r_and0000),
    .I2(Reset),
    .O(fBRK1r_or0001)
  );
  INV   fBRK1r_and00001 (
    .I(Ftrip1),
    .O(fBRK1r_and00001_217)
  );
  INV   fBRK1r_and00002 (
    .I(Rtrip1),
    .O(fBRK1r_and00002_218)
  );
  AND3   fBRK1r_and00003 (
    .I0(fBRK1r_and00001_217),
    .I1(fBRK1r_or0000),
    .I2(fBRK1r_and00002_218),
    .O(fBRK1r_and0000)
  );
  AND2   Ftrip11 (
    .I0(FLS1r_171),
    .I1(DIR1),
    .O(Ftrip11_178)
  );
  INV   Ftrip12 (
    .I(FLS1),
    .O(Ftrip12_179)
  );
  AND2   Ftrip13 (
    .I0(Ftrip11_178),
    .I1(Ftrip12_179),
    .O(Ftrip1)
  );
  OR3   FLS1fr__or00001 (
    .I0(Ftrip1),
    .I1(DCORLINTr),
    .I2(Reset),
    .O(FLS1fr__or0000)
  );
  OR2   FLS0fr__and00001 (
    .I0(DCORLINTr),
    .I1(Reset),
    .O(FLS0fr__and00001_163)
  );
  INV   FLS0fr__and00002 (
    .I(FLS0fr__and00001_163),
    .O(FLS0fr__and0000)
  );
  OR3   FLS0fr__or00001 (
    .I0(Ftrip0),
    .I1(DCORLINTr),
    .I2(Reset),
    .O(FLS0fr__or0000)
  );
  OR3   RLS0fr__or00001 (
    .I0(Rtrip0),
    .I1(DCORLINTr),
    .I2(Reset),
    .O(RLS0fr__or0000)
  );
  OR2   fBRK0r_or00021 (
    .I0(Rtrip0),
    .I1(Ftrip0),
    .O(fBRK0r_or0002)
  );
  INV   Rtrip01 (
    .I(RLS0),
    .O(Rtrip01_200)
  );
  INV   Rtrip02 (
    .I(DIR0),
    .O(Rtrip02_201)
  );
  AND3   Rtrip03 (
    .I0(Rtrip01_200),
    .I1(RLS0r_189),
    .I2(Rtrip02_201),
    .O(Rtrip0)
  );
  OR2   fBRK0r_or00001 (
    .I0(RLS0fr_187),
    .I1(FLS0fr_161),
    .O(fBRK0r_or00001_211)
  );
  INV   fBRK0r_or00002 (
    .I(Brake0),
    .O(fBRK0r_or00002_212)
  );
  OR2   fBRK0r_or00003 (
    .I0(fBRK0r_or00001_211),
    .I1(fBRK0r_or00002_212),
    .O(fBRK0r_or0000)
  );
  INV   fBRK0r_not00011 (
    .I(fBRK0r_or0001),
    .O(fBRK0r_not0001)
  );
  OR3   fBRK0r_or00011 (
    .I0(DCORLINTr),
    .I1(fBRK0r_and0000),
    .I2(Reset),
    .O(fBRK0r_or0001)
  );
  INV   fBRK0r_and00001 (
    .I(Ftrip0),
    .O(fBRK0r_and00001_207)
  );
  INV   fBRK0r_and00002 (
    .I(Rtrip0),
    .O(fBRK0r_and00002_208)
  );
  AND3   fBRK0r_and00003 (
    .I0(fBRK0r_and00001_207),
    .I1(fBRK0r_or0000),
    .I2(fBRK0r_and00002_208),
    .O(fBRK0r_and0000)
  );
  AND2   Ftrip01 (
    .I0(FLS0r_165),
    .I1(DIR0),
    .O(Ftrip01_175)
  );
  INV   Ftrip02 (
    .I(FLS0),
    .O(Ftrip02_176)
  );
  AND2   Ftrip03 (
    .I0(Ftrip01_175),
    .I1(Ftrip02_176),
    .O(Ftrip0)
  );
  INV   DCORIFG__and000011 (
    .I(LIFG),
    .O(DCORIFG__and00001)
  );
  INV   DCORIFG__and000012 (
    .I(DCORIFGw),
    .O(DCORIFG__and000011_149)
  );
  INV   DCORIFG__and000013 (
    .I(Reset),
    .O(DCORIFG__and000012_150)
  );
  AND2   DCORIFG__and000014 (
    .I0(NlwRenamedSig_OI_LSwitchInt),
    .I1(DCORIFG__and00001),
    .O(DCORIFG__and000013_151)
  );
  OR2   DCORIFG__and000015 (
    .I0(DCORIFG__and000013_151),
    .I1(DCORIFG__and000011_149),
    .O(DCORIFG__and000014_152)
  );
  AND2   DCORIFG__and000016 (
    .I0(DCORIFG__and000014_152),
    .I1(DCORIFG__and000012_150),
    .O(DCORIFG__and0000)
  );
  OR3   DCORIFG__or000021 (
    .I0(RLS0fr_187),
    .I1(FLS1fr_169),
    .I2(RLS1fr_193),
    .O(DCORIFG__or0000_bdd0)
  );
  OR4   DCORIFG__or000011 (
    .I0(Reset),
    .I1(DCORIFGw),
    .I2(FLS0fr_161),
    .I3(DCORIFG__or0000_bdd0),
    .O(DCORIFG__or0000)
  );
  OR2   outDATA_not000511 (
    .I0(DCORLIMITSr),
    .I1(DCORLINTr),
    .O(outDATA_not0005)
  );
endmodule

module U21AddDecode (
  DCORENCPWRr, DCOR0CNTLOWr, DCORENCPWRw, DCORENCCTLw, DCOR0THRESLOWr, AS, DCOR0THRESHIGHr, DCOR1CNTHIGHr, DCORLINTr, DCOR0CNTHIGHr, DCOR1THRESHIGHr, 
DCORLIMITSr, DCORSENSORw, DCORCONFIGr, DCORIFGr, DCORIFGw, RD, DCOROUTw, DCORIEw, WR, DCOR1CNTLOWr, DCOR1THRESLOWr, DCORI2CCNTr, ADDR
);
  output DCORENCPWRr;
  output DCOR0CNTLOWr;
  output DCORENCPWRw;
  output DCORENCCTLw;
  output DCOR0THRESLOWr;
  input AS;
  output DCOR0THRESHIGHr;
  output DCOR1CNTHIGHr;
  output DCORLINTr;
  output DCOR0CNTHIGHr;
  output DCOR1THRESHIGHr;
  output DCORLIMITSr;
  output DCORSENSORw;
  output DCORCONFIGr;
  output DCORIFGr;
  output DCORIFGw;
  input RD;
  output DCOROUTw;
  output DCORIEw;
  input WR;
  output DCOR1CNTLOWr;
  output DCOR1THRESLOWr;
  output DCORI2CCNTr;
  input [7 : 0] ADDR;
  wire N01;
  wire N11;
  wire N2;
  wire N3;
  wire SFDecomp_1;
  wire SFDecomp_10;
  wire SFDecomp_101_97;
  wire SFDecomp_102_98;
  wire SFDecomp_103_99;
  wire SFDecomp_11_100;
  wire SFDecomp_12_101;
  wire SFDecomp_13;
  wire SFDecomp_131_103;
  wire SFDecomp_132_104;
  wire SFDecomp_15;
  wire SFDecomp_151_106;
  wire SFDecomp_152_107;
  wire SFDecomp_17;
  wire SFDecomp_19;
  wire SFDecomp_191_110;
  wire SFDecomp_192_111;
  wire SFDecomp_193_112;
  wire SFDecomp_21;
  wire SFDecomp_211_114;
  wire SFDecomp_212_115;
  wire SFDecomp_23;
  wire SFDecomp_231_117;
  wire SFDecomp_232_118;
  wire SFDecomp_25;
  wire SFDecomp_251_120;
  wire SFDecomp_252_121;
  wire Select_10_Select1_122;
  wire Select_17_Select1_123;
  wire Select_cmp_eq0000;
  wire Select_cmp_eq00001_125;
  wire Select_cmp_eq000011_126;
  wire Select_cmp_eq0001;
  wire Select_cmp_eq00011_128;
  wire Select_cmp_eq000111_129;
  wire Select_cmp_eq0002;
  wire Select_cmp_eq0003;
  wire Select_cmp_eq0004;
  wire Select_cmp_eq0005;
  wire Select_cmp_eq0006;
  wire Select_cmp_eq0007;
  wire Select_cmp_eq0008;
  wire Select_cmp_eq0009;
  wire Select_cmp_eq0010;
  wire Select_cmp_eq0011;
  wire Select_cmp_eq0012;
  wire Select_cmp_eq0013;
  wire Select_cmp_eq0014;
  INV   SFDecomp_11 (
    .I(ADDR[1]),
    .O(SFDecomp_11_100)
  );
  INV   SFDecomp_12 (
    .I(ADDR[0]),
    .O(SFDecomp_12_101)
  );
  AND3   SFDecomp_14 (
    .I0(SFDecomp_11_100),
    .I1(ADDR[2]),
    .I2(SFDecomp_12_101),
    .O(SFDecomp_1)
  );
  INV   SFDecomp_101 (
    .I(ADDR[7]),
    .O(SFDecomp_101_97)
  );
  INV   SFDecomp_102 (
    .I(ADDR[6]),
    .O(SFDecomp_102_98)
  );
  INV   SFDecomp_103 (
    .I(ADDR[5]),
    .O(SFDecomp_103_99)
  );
  AND3   SFDecomp_104 (
    .I0(SFDecomp_102_98),
    .I1(SFDecomp_101_97),
    .I2(SFDecomp_103_99),
    .O(SFDecomp_10)
  );
  AND2   SFDecomp_131 (
    .I0(ADDR[2]),
    .I1(ADDR[0]),
    .O(SFDecomp_131_103)
  );
  INV   SFDecomp_132 (
    .I(ADDR[1]),
    .O(SFDecomp_132_104)
  );
  AND2   SFDecomp_133 (
    .I0(SFDecomp_131_103),
    .I1(SFDecomp_132_104),
    .O(SFDecomp_13)
  );
  AND2   SFDecomp_151 (
    .I0(ADDR[1]),
    .I1(ADDR[2]),
    .O(SFDecomp_151_106)
  );
  INV   SFDecomp_152 (
    .I(ADDR[0]),
    .O(SFDecomp_152_107)
  );
  AND2   SFDecomp_153 (
    .I0(SFDecomp_151_106),
    .I1(SFDecomp_152_107),
    .O(SFDecomp_15)
  );
  AND3   SFDecomp_171 (
    .I0(ADDR[0]),
    .I1(ADDR[1]),
    .I2(ADDR[2]),
    .O(SFDecomp_17)
  );
  INV   SFDecomp_191 (
    .I(ADDR[1]),
    .O(SFDecomp_191_110)
  );
  INV   SFDecomp_192 (
    .I(ADDR[0]),
    .O(SFDecomp_192_111)
  );
  INV   SFDecomp_193 (
    .I(ADDR[2]),
    .O(SFDecomp_193_112)
  );
  AND3   SFDecomp_194 (
    .I0(SFDecomp_192_111),
    .I1(SFDecomp_191_110),
    .I2(SFDecomp_193_112),
    .O(SFDecomp_19)
  );
  INV   SFDecomp_211 (
    .I(ADDR[1]),
    .O(SFDecomp_211_114)
  );
  INV   SFDecomp_212 (
    .I(ADDR[2]),
    .O(SFDecomp_212_115)
  );
  AND3   SFDecomp_213 (
    .I0(SFDecomp_211_114),
    .I1(ADDR[0]),
    .I2(SFDecomp_212_115),
    .O(SFDecomp_21)
  );
  INV   SFDecomp_231 (
    .I(ADDR[0]),
    .O(SFDecomp_231_117)
  );
  INV   SFDecomp_232 (
    .I(ADDR[2]),
    .O(SFDecomp_232_118)
  );
  AND3   SFDecomp_233 (
    .I0(SFDecomp_231_117),
    .I1(ADDR[1]),
    .I2(SFDecomp_232_118),
    .O(SFDecomp_23)
  );
  AND2   SFDecomp_251 (
    .I0(ADDR[1]),
    .I1(ADDR[0]),
    .O(SFDecomp_251_120)
  );
  INV   SFDecomp_252 (
    .I(ADDR[2]),
    .O(SFDecomp_252_121)
  );
  AND2   SFDecomp_253 (
    .I0(SFDecomp_251_120),
    .I1(SFDecomp_252_121),
    .O(SFDecomp_25)
  );
  INV   Select_cmp_eq000111 (
    .I(ADDR[3]),
    .O(Select_cmp_eq00011_128)
  );
  INV   Select_cmp_eq000112 (
    .I(ADDR[4]),
    .O(Select_cmp_eq000111_129)
  );
  AND3   Select_cmp_eq000113 (
    .I0(Select_cmp_eq00011_128),
    .I1(SFDecomp_10),
    .I2(Select_cmp_eq000111_129),
    .O(N01)
  );
  AND2   Select_cmp_eq00011 (
    .I0(SFDecomp_19),
    .I1(N01),
    .O(Select_cmp_eq0001)
  );
  AND2   Select_cmp_eq00021 (
    .I0(SFDecomp_21),
    .I1(N01),
    .O(Select_cmp_eq0002)
  );
  AND2   Select_cmp_eq00031 (
    .I0(SFDecomp_25),
    .I1(N01),
    .O(Select_cmp_eq0003)
  );
  AND2   Select_cmp_eq00041 (
    .I0(SFDecomp_23),
    .I1(N01),
    .O(Select_cmp_eq0004)
  );
  AND2   Select_cmp_eq00051 (
    .I0(SFDecomp_1),
    .I1(N01),
    .O(Select_cmp_eq0005)
  );
  AND2   Select_cmp_eq00061 (
    .I0(SFDecomp_13),
    .I1(N01),
    .O(Select_cmp_eq0006)
  );
  AND2   Select_cmp_eq00071 (
    .I0(SFDecomp_15),
    .I1(N01),
    .O(Select_cmp_eq0007)
  );
  AND2   Select_cmp_eq00081 (
    .I0(SFDecomp_17),
    .I1(N01),
    .O(Select_cmp_eq0008)
  );
  AND2   Select_cmp_eq000011 (
    .I0(ADDR[3]),
    .I1(SFDecomp_10),
    .O(Select_cmp_eq00001_125)
  );
  INV   Select_cmp_eq000012 (
    .I(ADDR[4]),
    .O(Select_cmp_eq000011_126)
  );
  AND2   Select_cmp_eq000013 (
    .I0(Select_cmp_eq00001_125),
    .I1(Select_cmp_eq000011_126),
    .O(N11)
  );
  AND2   Select_cmp_eq00001 (
    .I0(SFDecomp_1),
    .I1(N11),
    .O(Select_cmp_eq0000)
  );
  AND2   Select_cmp_eq00091 (
    .I0(SFDecomp_19),
    .I1(N11),
    .O(Select_cmp_eq0009)
  );
  AND2   Select_cmp_eq00101 (
    .I0(SFDecomp_21),
    .I1(N11),
    .O(Select_cmp_eq0010)
  );
  AND2   Select_cmp_eq00111 (
    .I0(SFDecomp_23),
    .I1(N11),
    .O(Select_cmp_eq0011)
  );
  AND2   Select_cmp_eq00121 (
    .I0(SFDecomp_25),
    .I1(N11),
    .O(Select_cmp_eq0012)
  );
  AND2   Select_cmp_eq00131 (
    .I0(SFDecomp_15),
    .I1(N11),
    .O(Select_cmp_eq0013)
  );
  AND2   Select_cmp_eq00141 (
    .I0(SFDecomp_17),
    .I1(N11),
    .O(Select_cmp_eq0014)
  );
  INV   Select_10_Select11 (
    .I(RD),
    .O(Select_10_Select1_122)
  );
  AND2   Select_10_Select12 (
    .I0(WR),
    .I1(Select_10_Select1_122),
    .O(N2)
  );
  AND2   Select_4_Select1 (
    .I0(Select_cmp_eq0002),
    .I1(N2),
    .O(DCORIFGr)
  );
  AND2   Select_5_Select1 (
    .I0(Select_cmp_eq0003),
    .I1(N2),
    .O(DCORLIMITSr)
  );
  AND2   Select_6_Select1 (
    .I0(Select_cmp_eq0004),
    .I1(N2),
    .O(DCORLINTr)
  );
  AND2   Select_8_Select1 (
    .I0(Select_cmp_eq0005),
    .I1(N2),
    .O(DCOR0CNTLOWr)
  );
  AND2   Select_9_Select1 (
    .I0(Select_cmp_eq0006),
    .I1(N2),
    .O(DCOR0CNTHIGHr)
  );
  AND2   Select_10_Select1 (
    .I0(Select_cmp_eq0007),
    .I1(N2),
    .O(DCOR1CNTLOWr)
  );
  AND2   Select_11_Select1 (
    .I0(Select_cmp_eq0008),
    .I1(N2),
    .O(DCOR1CNTHIGHr)
  );
  AND2   Select_12_Select1 (
    .I0(Select_cmp_eq0009),
    .I1(N2),
    .O(DCOR0THRESLOWr)
  );
  AND2   Select_13_Select1 (
    .I0(Select_cmp_eq0010),
    .I1(N2),
    .O(DCOR0THRESHIGHr)
  );
  AND2   Select_14_Select1 (
    .I0(Select_cmp_eq0011),
    .I1(N2),
    .O(DCOR1THRESLOWr)
  );
  AND2   Select_15_Select1 (
    .I0(Select_cmp_eq0012),
    .I1(N2),
    .O(DCOR1THRESHIGHr)
  );
  AND2   Select_16_Select1 (
    .I0(Select_cmp_eq0013),
    .I1(N2),
    .O(DCORENCPWRr)
  );
  AND2   Select_18_Select1 (
    .I0(Select_cmp_eq0014),
    .I1(N2),
    .O(DCORCONFIGr)
  );
  AND2   Select_20_Select1 (
    .I0(Select_cmp_eq0001),
    .I1(N2),
    .O(DCORI2CCNTr)
  );
  INV   Select_17_Select11 (
    .I(WR),
    .O(Select_17_Select1_123)
  );
  AND2   Select_17_Select12 (
    .I0(RD),
    .I1(Select_17_Select1_123),
    .O(N3)
  );
  AND2   Select_1_Select1 (
    .I0(Select_cmp_eq0000),
    .I1(N3),
    .O(DCORSENSORw)
  );
  AND2   Select_2_Select1 (
    .I0(Select_cmp_eq0001),
    .I1(N3),
    .O(DCORIEw)
  );
  AND2   Select_3_Select1 (
    .I0(Select_cmp_eq0002),
    .I1(N3),
    .O(DCORIFGw)
  );
  AND2   Select_7_Select1 (
    .I0(Select_cmp_eq0003),
    .I1(N3),
    .O(DCORENCCTLw)
  );
  AND2   Select_17_Select1 (
    .I0(Select_cmp_eq0013),
    .I1(N3),
    .O(DCORENCPWRw)
  );
  AND2   Select_19_Select1 (
    .I0(Select_cmp_eq0014),
    .I1(N3),
    .O(DCOROUTw)
  );
endmodule

module U21 (
  SCL, Brake0, Brake1, Latch133ctrl, LightSense, MTRpwrn, Home15ctrl, Latch033ctrl, AS, TmpSlct, PhaseB_Encoder0, MSPReset, PhaseB_Encoder1, INTbus, 
LED1, Latch033FLG, Enc05ctrl, LED2, LED3, LED4, LED5, Home05FLG, TP12, TP21, PhaseA_Encoder0, PhaseA_Encoder1, PWM1, Home0, PWM2, Home1, TP26, PWM3, 
PAH0, PWM4, PAH1, RLS0, PWM5, RLS1, Latch133FLG, Enc15ctrl, GP_Motor0_0, GP_Motor0_1, TmpEn, PAL0, PAL1, Home15FLG, PBH0, RD, Enc05FLG, PBH1, PresEn, 
GPIO8, GPIO9, GP_Motor1_0, GP_Motor1_1, FLS0, PBL0, FLS1, PBL1, WR, GPIO10, Enc15FLG, SCLreset, PresSlct, DIR0, DIR1, Home05ctrl, Mclk, INT, SCLinc, 
MTRpwr, MReset, AD, I2CS
);
  inout SCL;
  input Brake0;
  input Brake1;
  output Latch133ctrl;
  input LightSense;
  output MTRpwrn;
  output Home15ctrl;
  output Latch033ctrl;
  input AS;
  output TmpSlct;
  input PhaseB_Encoder0;
  input MSPReset;
  input PhaseB_Encoder1;
  input INTbus;
  output LED1;
  input Latch033FLG;
  output Enc05ctrl;
  output LED2;
  output LED3;
  output LED4;
  output LED5;
  input Home05FLG;
  output TP12;
  output TP21;
  input PhaseA_Encoder0;
  input PhaseA_Encoder1;
  input PWM1;
  input Home0;
  input PWM2;
  input Home1;
  output TP26;
  input PWM3;
  output PAH0;
  input PWM4;
  output PAH1;
  input RLS0;
  input PWM5;
  input RLS1;
  input Latch133FLG;
  output Enc15ctrl;
  input GP_Motor0_0;
  output GP_Motor0_1;
  output TmpEn;
  output PAL0;
  output PAL1;
  input Home15FLG;
  output PBH0;
  input RD;
  input Enc05FLG;
  output PBH1;
  output PresEn;
  output GPIO8;
  output GPIO9;
  input GP_Motor1_0;
  output GP_Motor1_1;
  input FLS0;
  output PBL0;
  input FLS1;
  output PBL1;
  input WR;
  output GPIO10;
  input Enc15FLG;
  input SCLreset;
  output PresSlct;
  input DIR0;
  input DIR1;
  output Home05ctrl;
  input Mclk;
  output INT;
  input SCLinc;
  output MTRpwr;
  input MReset;
  inout [7 : 0] AD;
  input [5 : 0] I2CS;
  wire AS_IBUF_2007;
  wire Brake0_IBUF_2009;
  wire Brake1_IBUF_2011;
  wire DCOR0CNTHIGHr;
  wire DCOR0CNTLOWr;
  wire DCOR0THRESHIGHr;
  wire DCOR0THRESLOWr;
  wire DCOR1CNTHIGHr;
  wire DCOR1CNTLOWr;
  wire DCOR1THRESHIGHr;
  wire DCOR1THRESLOWr;
  wire DCORCONFIGr;
  wire DCORENCCTLw;
  wire DCORENCPWRr;
  wire DCORENCPWRw;
  wire DCORI2CCNTr;
  wire DCORIEw;
  wire DCORIFGr;
  wire DCORIFGw;
  wire DCORLIMITSr;
  wire DCORLINTr;
  wire DCOROUTw;
  wire DCORSENSORw;
  wire DIR0_IBUF_2033;
  wire DIR1_IBUF_2035;
  wire Enc05FLG_IBUF_2037;
  wire Enc05ctrl_OBUF_2039;
  wire Enc15FLG_IBUF_2041;
  wire Enc15ctrl_OBUF_2043;
  wire FLS0_IBUF_2045;
  wire FLS1_IBUF_2047;
  wire GPIO101_2049;
  wire GPIO10_OBUF_2050;
  wire GPIO8_OBUF_2052;
  wire GPIO91_2054;
  wire GPIO9_OBUF_2055;
  wire GP_Motor0_0_IBUF_2057;
  wire GP_Motor0_1_OBUF_2059;
  wire GP_Motor1_0_IBUF_2061;
  wire GP_Motor1_1_OBUF_2063;
  wire Home05FLG_IBUF_2066;
  wire Home05ctrl_OBUF_2068;
  wire Home0_IBUF_2069;
  wire Home15FLG_IBUF_2072;
  wire Home15ctrl_OBUF_2074;
  wire Home1_IBUF_2075;
  wire I2CS_0_IBUF_2082;
  wire I2CS_1_IBUF_2083;
  wire I2CS_2_IBUF_2084;
  wire I2CS_3_IBUF_2085;
  wire I2CS_4_IBUF_2086;
  wire I2CS_5_IBUF_2087;
  wire INT_OBUF_2089;
  wire INTbus_IBUF_2091;
  wire LED1_OBUF_2093;
  wire LED2_OBUF_2095;
  wire LED3_OBUF_2097;
  wire LED4_OBUF_2099;
  wire LED5_OBUF_2101;
  wire Latch033FLG_IBUF_2103;
  wire Latch033ctrl_OBUF_2105;
  wire Latch133FLG_IBUF_2107;
  wire Latch133ctrl_OBUF_2109;
  wire LightSense_IBUF_2111;
  wire MReset_IBUF_2113;
  wire MSPReset_IBUF_2115;
  wire MTRpwr_OBUF_2117;
  wire MTRpwrn_OBUF_2119;
  wire Mclk_IBUF_2121;
  wire N0;
  wire N01;
  wire N1;
  wire N10;
  wire N11;
  wire N12;
  wire N13;
  wire N15;
  wire N16;
  wire N17;
  wire N19;
  wire N2;
  wire N20;
  wire N21;
  wire N22;
  wire N23;
  wire N24;
  wire N25;
  wire N26;
  wire N27;
  wire N3;
  wire N4;
  wire N5;
  wire N6;
  wire N7;
  wire N8;
  wire N9;
  wire NET2482;
  wire NET2493;
  wire NET2512;
  wire NET2528;
  wire NET2575;
  wire NET3248;
  wire NET3253;
  wire NET4826;
  wire PAH0_OBUF_2158;
  wire PAH1_OBUF_2160;
  wire PAL0_OBUF_2162;
  wire PAL1_OBUF_2164;
  wire PBH0_OBUF_2166;
  wire PBH1_OBUF_2168;
  wire PBL0_OBUF_2170;
  wire PBL1_OBUF_2172;
  wire PWM1_IBUF_2174;
  wire PWM2_IBUF_2176;
  wire PWM3_IBUF_2178;
  wire PWM4_IBUF_2180;
  wire PhaseA_Encoder0_IBUF_2183;
  wire PhaseA_Encoder1_IBUF_2185;
  wire PhaseB_Encoder0_IBUF_2187;
  wire PhaseB_Encoder1_IBUF_2189;
  wire PresEn_OBUF_2191;
  wire PresSlct_OBUF_2193;
  wire RD_IBUF_2195;
  wire RLS0_IBUF_2197;
  wire RLS1_IBUF_2199;
  wire Reset;
  wire SCLinc_IBUF_2203;
  wire SCLreset_IBUF_2205;
  wire SFDecomp_1;
  wire SFDecomp_11_2207;
  wire SFDecomp_12_2208;
  wire SFDecomp_2;
  wire SFDecomp_21_2210;
  wire SFDecomp_3;
  wire SFDecomp_31_2212;
  wire SFDecomp_32_2213;
  wire SFDecomp_33_2214;
  wire SFDecomp_4;
  wire SFDecomp_41_2216;
  wire TP12_OBUF_2218;
  wire TP21_OBUF_2220;
  wire TP26_OBUF_2222;
  wire TmpEn_OBUF_2224;
  wire TmpSlct_OBUF_2226;
  wire U11_Incdetect;
  wire U11_ResetDetect;
  wire U11_SCLdetect;
  wire \U11_U3_Maddsub_counterr_share0000_Mxor_Result<1>__xor0000 ;
  wire \U11_U3_Maddsub_counterr_share0000_Mxor_Result<2>__xor0000 ;
  wire \U11_U3_Maddsub_counterr_share0000_Mxor_Result<3>__xor0000 ;
  wire \U11_U3_Maddsub_counterr_share0000_Mxor_Result<4>__xor0000 ;
  wire \U11_U3_Maddsub_counterr_share0000_Mxor_Result<5>__xor0000 ;
  wire \U11_U3_Maddsub_counterr_share0000_Mxor_Result<5>__xor0001 ;
  wire U11_U3_Maddsub_counterr_share0000__or0000;
  wire U11_U3_Maddsub_counterr_share0000__or0001;
  wire U11_U3_Maddsub_counterr_share0000__or00011_2238;
  wire U11_U3_Maddsub_counterr_share0000__or00012_2239;
  wire U11_U3_Maddsub_counterr_share0000__or0002;
  wire U11_U3_Maddsub_counterr_share0000__or00021_2241;
  wire U11_U3_Maddsub_counterr_share0000__or00022_2242;
  wire U11_U3_Maddsub_counterr_share0000__or0003;
  wire U11_U3_Maddsub_counterr_share0000__or00031_2244;
  wire U11_U3_Maddsub_counterr_share0000__or00032_2245;
  wire U11_U3_Maddsub_counterr_share0000__or0004;
  wire U11_U3_Maddsub_counterr_share0000__or00041_2247;
  wire U11_U3_Maddsub_counterr_share0000__or00042_2248;
  wire U11_U3_Maddsub_counterr_share0000_or0000_xor0000;
  wire U11_U3_Maddsub_counterr_share0000_or0003_xor0000;
  wire U11_U3_SCLint_cmp_eq0000;
  wire U11_U3_SCLint_cmp_eq00001_2253;
  wire U11_U3_SCLint_cmp_eq00002_2254;
  wire \U11_U3_counterr_mux0000<0>1 ;
  wire \U11_U3_counterr_mux0000<0>11_2263 ;
  wire \U11_U3_counterr_mux0000<0>12_2264 ;
  wire \U11_U3_counterr_mux0000<1>1 ;
  wire \U11_U3_counterr_mux0000<1>11_2267 ;
  wire \U11_U3_counterr_mux0000<1>12_2268 ;
  wire \U11_U3_counterr_mux0000<2>1_2270 ;
  wire \U11_U3_counterr_mux0000<3>1 ;
  wire \U11_U3_counterr_mux0000<3>11_2273 ;
  wire \U11_U3_counterr_mux0000<3>12_2274 ;
  wire \U11_U3_counterr_mux0000<4>1 ;
  wire \U11_U3_counterr_mux0000<4>11_2277 ;
  wire \U11_U3_counterr_mux0000<4>12_2278 ;
  wire \U11_U3_counterr_mux0000<4>13_2279 ;
  wire \U11_U3_counterr_mux0000<4>14_2280 ;
  wire \U11_U3_counterr_mux0000<4>2 ;
  wire \U11_U3_counterr_mux0000<4>21_2282 ;
  wire \U11_U3_counterr_mux0000<4>22_2283 ;
  wire \U11_U3_counterr_mux0000<4>3_2284 ;
  wire \U11_U3_counterr_mux0000<4>4_2285 ;
  wire \U11_U3_counterr_mux0000<5>1 ;
  wire \U11_U3_counterr_mux0000<5>11_2288 ;
  wire \U11_U3_counterr_mux0000<5>111_2289 ;
  wire \U11_U3_counterr_mux0000<5>12_2290 ;
  wire \U11_U3_counterr_mux0000<5>121_2291 ;
  wire \U11_U3_counterr_mux0000<5>13 ;
  wire \U11_U3_counterr_mux0000<5>2_2293 ;
  wire \U11_U3_counterr_mux0000<5>3_2294 ;
  wire \U11_U3_counterr_mux0001[2] ;
  wire \U11_U3_counterr_mux0001<2>1_2296 ;
  wire \U11_U3_counterr_mux0001<2>2_2297 ;
  wire \U11_U3_counterr_mux0001[5] ;
  wire \U11_U3_counterr_mux0001<5>1 ;
  wire \U11_U3_counterr_mux0001<5>11_2300 ;
  wire \U11_U3_counterr_mux0001<5>12_2301 ;
  wire \U11_U3_counterr_mux0001<5>13_2302 ;
  wire \U11_U3_counterr_mux0001<5>14_2303 ;
  wire U11_U3_counterr_or00031_2305;
  wire U2_ADDR_in_Range;
  wire U2_ADDR_reg_0_0_not0000;
  wire U2_ADDR_reg_0__and0000;
  wire U2_ADDR_reg_0__or0000;
  wire U2_ADDR_reg_0__or00001_2317;
  wire U2_ADDR_reg_0__or00002_2318;
  wire U2_ADDR_reg_1__and0000;
  wire U2_ADDR_reg_2__and0000;
  wire U2_ADDR_reg_3__and0000;
  wire U2_ADDR_reg_4__and0000;
  wire U2_ADDR_reg_5__and0000;
  wire U2_ADDR_reg_6__and0000;
  wire U2_ADDR_reg_7__and0000;
  wire U2_ADDR_reg_and0000;
  wire U2_ADDR_reg_and00001_2341;
  wire U2_ADDR_reg_and00002_2342;
  wire U2_ADDR_reg_and00003_2343;
  wire U2_ADDR_reg_and0001;
  wire U2_ADDR_reg_and0002;
  wire U2_ADDR_reg_and00021_2346;
  wire U2_ADDR_reg_and00022_2347;
  wire U2_ADDR_reg_cmp_lt0000;
  wire \U2_ADDR_reg_mux0001<0>1_2350 ;
  wire \U2_ADDR_reg_mux0001<0>11_2351 ;
  wire \U2_ADDR_reg_mux0001<0>12_2352 ;
  wire \U2_ADDR_reg_mux0001<0>13_2353 ;
  wire \U2_ADDR_reg_mux0001<0>2_2354 ;
  wire \U2_ADDR_reg_mux0001<0>3_2355 ;
  wire \U2_ADDR_reg_mux0001<0>4_2356 ;
  wire \U2_ADDR_reg_mux0001<0>5_2357 ;
  wire \U2_ADDR_reg_mux0001<1>1_2359 ;
  wire \U2_ADDR_reg_mux0001<1>2_2360 ;
  wire \U2_ADDR_reg_mux0001<1>3_2361 ;
  wire \U2_ADDR_reg_mux0001<2>1_2363 ;
  wire \U2_ADDR_reg_mux0001<2>2_2364 ;
  wire \U2_ADDR_reg_mux0001<3>1_2366 ;
  wire \U2_ADDR_reg_mux0001<3>2_2367 ;
  wire \U2_ADDR_reg_mux0001<4>1_2369 ;
  wire \U2_ADDR_reg_mux0001<4>2_2370 ;
  wire \U2_ADDR_reg_mux0001<5>1_2372 ;
  wire \U2_ADDR_reg_mux0001<5>2_2373 ;
  wire \U2_ADDR_reg_mux0001<6>1_2375 ;
  wire \U2_ADDR_reg_mux0001<6>2_2376 ;
  wire \U2_ADDR_reg_mux0001<7>1_2378 ;
  wire \U2_ADDR_reg_mux0001<7>2_2379 ;
  wire U2_ASedge_2380;
  wire U2_ASleading;
  wire U2_AutoInc_2382;
  wire U2_AutoInc_and0000;
  wire U2_AutoInc_and00001_2384;
  wire U2_AutoInc_not0001;
  wire U2_Enable_AD;
  wire U2_Enable_AD1_2387;
  wire U2_Enable_AD2_2388;
  wire U2_Madd_ADDR_reg_addsub0000__and0000;
  wire U2_Madd_ADDR_reg_addsub0000__and0001;
  wire U2_Madd_ADDR_reg_addsub0000__and0002;
  wire U2_Madd_ADDR_reg_addsub0000__and0003;
  wire U2_Madd_ADDR_reg_addsub0000__and0004;
  wire U2_Madd_ADDR_reg_addsub0000__and0005;
  wire U2_Mcompar_ADDR_reg_cmp_lt0000_ALB;
  wire U2_Mcompar_ADDR_reg_cmp_lt0000_ALB1_2396;
  wire U2_WRRDedge_2401;
  wire U2_WRRDedge_and0000;
  wire WR_IBUF_2404;
  wire NLW_U1_TP_UNCONNECTED;
  wire NLW_U4_Enc033ctl_UNCONNECTED;
  wire NLW_U4_Enc033flg_UNCONNECTED;
  wire NLW_U4_Enc133ctl_UNCONNECTED;
  wire NLW_U4_Enc133flg_UNCONNECTED;
  wire [5 : 0] U11_U3_counterr;
  wire [5 : 0] U11_U3_counterr_mux0000;
  wire [5 : 0] U11_U3_counterr_share0000;
  wire [7 : 0] U2_ADDR_reg;
  wire [7 : 1] U2_ADDR_reg_addsub0000;
  wire [7 : 0] U2_ADDR_reg_mux0001;
  wire [3 : 3] U2_Mcompar_ADDR_reg_cmp_lt0000_ALRANDC;
  wire [7 : 5] U2_Mcompar_ADDR_reg_cmp_lt0000_CARRY_IN;
  wire [7 : 0] outDATA;
  GND   XST_GND (
    .G(N0)
  );
  FDCE   U2_AutoInc (
    .CE(U2_AutoInc_and0000),
    .CLR(N0),
    .C(U2_ADDR_reg_0_0_not0000),
    .D(U2_AutoInc_not0001),
    .Q(U2_AutoInc_2382)
  );
  FD   U2_ASedge (
    .C(U2_ADDR_reg_0_0_not0000),
    .D(AS_IBUF_2007),
    .Q(U2_ASedge_2380)
  );
  FD   U2_WRRDedge (
    .C(U2_ADDR_reg_0_0_not0000),
    .D(U2_WRRDedge_and0000),
    .Q(U2_WRRDedge_2401)
  );
  FDCE   U2_ADDR_reg_7 (
    .CE(U2_ADDR_reg_0__or0000),
    .CLR(N0),
    .C(U2_ADDR_reg_0_0_not0000),
    .D(U2_ADDR_reg_7__and0000),
    .Q(U2_ADDR_reg[7])
  );
  FDCE   U2_ADDR_reg_6 (
    .CE(U2_ADDR_reg_0__or0000),
    .CLR(N0),
    .C(U2_ADDR_reg_0_0_not0000),
    .D(U2_ADDR_reg_6__and0000),
    .Q(U2_ADDR_reg[6])
  );
  FDCE   U2_ADDR_reg_5 (
    .CE(U2_ADDR_reg_0__or0000),
    .CLR(N0),
    .C(U2_ADDR_reg_0_0_not0000),
    .D(U2_ADDR_reg_5__and0000),
    .Q(U2_ADDR_reg[5])
  );
  FDCE   U2_ADDR_reg_4 (
    .CE(U2_ADDR_reg_0__or0000),
    .CLR(N0),
    .C(U2_ADDR_reg_0_0_not0000),
    .D(U2_ADDR_reg_4__and0000),
    .Q(U2_ADDR_reg[4])
  );
  FDCE   U2_ADDR_reg_3 (
    .CE(U2_ADDR_reg_0__or0000),
    .CLR(N0),
    .C(U2_ADDR_reg_0_0_not0000),
    .D(U2_ADDR_reg_3__and0000),
    .Q(U2_ADDR_reg[3])
  );
  FDCE   U2_ADDR_reg_2 (
    .CE(U2_ADDR_reg_0__or0000),
    .CLR(N0),
    .C(U2_ADDR_reg_0_0_not0000),
    .D(U2_ADDR_reg_2__and0000),
    .Q(U2_ADDR_reg[2])
  );
  FDCE   U2_ADDR_reg_1 (
    .CE(U2_ADDR_reg_0__or0000),
    .CLR(N0),
    .C(U2_ADDR_reg_0_0_not0000),
    .D(U2_ADDR_reg_1__and0000),
    .Q(U2_ADDR_reg[1])
  );
  FDCE   U2_ADDR_reg_0 (
    .CE(U2_ADDR_reg_0__or0000),
    .CLR(N0),
    .C(U2_ADDR_reg_0_0_not0000),
    .D(U2_ADDR_reg_0__and0000),
    .Q(U2_ADDR_reg[0])
  );
  FD   U11_U3_counterr_5 (
    .C(U2_ADDR_reg_0_0_not0000),
    .D(U11_U3_counterr_mux0000[0]),
    .Q(U11_U3_counterr[5])
  );
  FD   U11_U3_counterr_4 (
    .C(U2_ADDR_reg_0_0_not0000),
    .D(U11_U3_counterr_mux0000[1]),
    .Q(U11_U3_counterr[4])
  );
  FD   U11_U3_counterr_3 (
    .C(U2_ADDR_reg_0_0_not0000),
    .D(U11_U3_counterr_mux0000[2]),
    .Q(U11_U3_counterr[3])
  );
  FD   U11_U3_counterr_2 (
    .C(U2_ADDR_reg_0_0_not0000),
    .D(U11_U3_counterr_mux0000[3]),
    .Q(U11_U3_counterr[2])
  );
  FD   U11_U3_counterr_1 (
    .C(U2_ADDR_reg_0_0_not0000),
    .D(U11_U3_counterr_mux0000[4]),
    .Q(U11_U3_counterr[1])
  );
  FD   U11_U3_counterr_0 (
    .C(U2_ADDR_reg_0_0_not0000),
    .D(U11_U3_counterr_mux0000[5]),
    .Q(U11_U3_counterr[0])
  );
  BUFE   U11_U3_outDATA_counterr_7 (
    .I(N0),
    .E(DCORI2CCNTr),
    .O(outDATA[7])
  );
  BUFE   U11_U3_outDATA_counterr_6 (
    .I(N0),
    .E(DCORI2CCNTr),
    .O(outDATA[6])
  );
  BUFE   U11_U3_outDATA_counterr_5 (
    .I(U11_U3_counterr[5]),
    .E(DCORI2CCNTr),
    .O(outDATA[5])
  );
  BUFE   U11_U3_outDATA_counterr_4 (
    .I(U11_U3_counterr[4]),
    .E(DCORI2CCNTr),
    .O(outDATA[4])
  );
  BUFE   U11_U3_outDATA_counterr_3 (
    .I(U11_U3_counterr[3]),
    .E(DCORI2CCNTr),
    .O(outDATA[3])
  );
  BUFE   U11_U3_outDATA_counterr_2 (
    .I(U11_U3_counterr[2]),
    .E(DCORI2CCNTr),
    .O(outDATA[2])
  );
  BUFE   U11_U3_outDATA_counterr_1 (
    .I(U11_U3_counterr[1]),
    .E(DCORI2CCNTr),
    .O(outDATA[1])
  );
  BUFE   U11_U3_outDATA_counterr_0 (
    .I(U11_U3_counterr[0]),
    .E(DCORI2CCNTr),
    .O(outDATA[0])
  );
  U21AddDecode   U12 (
    .DCORENCPWRr(DCORENCPWRr),
    .DCOR0CNTLOWr(DCOR0CNTLOWr),
    .DCORENCPWRw(DCORENCPWRw),
    .DCORENCCTLw(DCORENCCTLw),
    .DCOR0THRESLOWr(DCOR0THRESLOWr),
    .AS(AS_IBUF_2007),
    .DCOR0THRESHIGHr(DCOR0THRESHIGHr),
    .DCOR1CNTHIGHr(DCOR1CNTHIGHr),
    .DCORLINTr(DCORLINTr),
    .DCOR0CNTHIGHr(DCOR0CNTHIGHr),
    .DCOR1THRESHIGHr(DCOR1THRESHIGHr),
    .DCORLIMITSr(DCORLIMITSr),
    .DCORSENSORw(DCORSENSORw),
    .DCORCONFIGr(DCORCONFIGr),
    .DCORIFGr(DCORIFGr),
    .DCORIFGw(DCORIFGw),
    .RD(RD_IBUF_2195),
    .DCOROUTw(DCOROUTw),
    .DCORIEw(DCORIEw),
    .WR(WR_IBUF_2404),
    .DCOR1CNTLOWr(DCOR1CNTLOWr),
    .DCOR1THRESLOWr(DCOR1THRESLOWr),
    .DCORI2CCNTr(DCORI2CCNTr),
    .ADDR({U2_ADDR_reg[7], U2_ADDR_reg[6], U2_ADDR_reg[5], U2_ADDR_reg[4], U2_ADDR_reg[3], U2_ADDR_reg[2], U2_ADDR_reg[1], U2_ADDR_reg[0]})
  );
  Lswitch   U5 (
    .Brake0(Brake0_IBUF_2009),
    .Brake1(Brake1_IBUF_2011),
    .DCORLINTr(DCORLINTr),
    .Reset(Reset),
    .fBRK0(NET3248),
    .fBRK1(NET3253),
    .DCORLIMITSr(DCORLIMITSr),
    .Home0(Home0_IBUF_2069),
    .Home1(Home1_IBUF_2075),
    .RLS0(RLS0_IBUF_2197),
    .RLS1(RLS1_IBUF_2199),
    .DCORIFGw(DCORIFGw),
    .FLS0(FLS0_IBUF_2045),
    .FLS1(FLS1_IBUF_2047),
    .LSwitchInt(NET2575),
    .LIFG(N23),
    .DIR0(DIR0_IBUF_2033),
    .DIR1(DIR1_IBUF_2035),
    .Mclk(Mclk_IBUF_2121),
    .outDATA({outDATA[7], outDATA[6], outDATA[5], outDATA[4], outDATA[3], outDATA[2], outDATA[1], outDATA[0]})
  );
  I2CAddress   U6 (
    .DCORCONFIGr(DCORCONFIGr),
    .MotorIn0(GP_Motor0_0_IBUF_2057),
    .MotorIn1(GP_Motor1_0_IBUF_2061),
    .outDATA({outDATA[7], outDATA[6], outDATA[5], outDATA[4], outDATA[3], outDATA[2], outDATA[1], outDATA[0]}),
    .I2CS({I2CS_5_IBUF_2087, I2CS_4_IBUF_2086, I2CS_3_IBUF_2085, I2CS_2_IBUF_2084, I2CS_1_IBUF_2083, I2CS_0_IBUF_2082})
  );
  NegDetect   U11_U1 (
    .Line(SCLinc_IBUF_2203),
    .Ndetect(U11_Incdetect),
    .Mclk(Mclk_IBUF_2121)
  );
  NegDetect_INST_1   U11_U2 (
    .Line(N19),
    .Ndetect(U11_SCLdetect),
    .Mclk(Mclk_IBUF_2121)
  );
  NegDetect_INST_2   U11_U4 (
    .Line(SCLreset_IBUF_2205),
    .Ndetect(U11_ResetDetect),
    .Mclk(Mclk_IBUF_2121)
  );
  PWMcontrol   U7 (
    .Brake1(Brake0_IBUF_2009),
    .Brake2(Brake1_IBUF_2011),
    .fBRK1(NET3248),
    .fBRK2(NET3253),
    .PWM1(PWM1_IBUF_2174),
    .PWM2(PWM2_IBUF_2176),
    .PAH1(PAH0_OBUF_2158),
    .RLS0(RLS0_IBUF_2197),
    .PAH2(PAH1_OBUF_2160),
    .RLS1(RLS1_IBUF_2199),
    .PAL1(PAL0_OBUF_2162),
    .PAL2(PAL1_OBUF_2164),
    .PBH1(PBH0_OBUF_2166),
    .PBH2(PBH1_OBUF_2168),
    .FLS0(FLS0_IBUF_2045),
    .FLS1(FLS1_IBUF_2047),
    .PBL1(PBL0_OBUF_2170),
    .PBL2(PBL1_OBUF_2172),
    .HBRK1(NET3248),
    .HBRK2(NET3253),
    .DIR1(DIR0_IBUF_2033),
    .DIR2(DIR1_IBUF_2035),
    .MTRpwr(MTRpwr_OBUF_2117)
  );
  Interrupt   U3 (
    .PWRint(NET2528),
    .Reset(Reset),
    .I2Cint(TP12_OBUF_2218),
    .DCORIFGr(DCORIFGr),
    .Homed0(NET2482),
    .Homed1(NET2493),
    .BusInt(INTbus_IBUF_2091),
    .TP(TP21_OBUF_2220),
    .DCORIEw(DCORIEw),
    .Thres0(TP26_OBUF_2222),
    .Thres1(NET2512),
    .LSwitchInt(NET2575),
    .Mclk(Mclk_IBUF_2121),
    .INT(INT_OBUF_2089),
    .outDATA({outDATA[7], outDATA[6], outDATA[5], outDATA[4], outDATA[3], outDATA[2], outDATA[1], outDATA[0]}),
    .inDATA({N20, N21, N22, N23, N24, N25, N26, N27})
  );
  PWRreg   U4 (
    .DCORENCPWRr(DCORENCPWRr),
    .DCORENCPWRw(DCORENCPWRw),
    .PWRint(NET2528),
    .Hme05ctl(Home05ctrl_OBUF_2068),
    .Enc033ctl(NLW_U4_Enc033ctl_UNCONNECTED),
    .Hme033ctl(Latch033ctrl_OBUF_2105),
    .Reset(Reset),
    .Hme05flg(Home05FLG_IBUF_2066),
    .Enc05ctl(Enc05ctrl_OBUF_2039),
    .Enc033flg(NLW_U4_Enc033flg_UNCONNECTED),
    .Hme033flg(Latch033FLG_IBUF_2103),
    .Hme15ctl(Home15ctrl_OBUF_2074),
    .Enc133ctl(NLW_U4_Enc133ctl_UNCONNECTED),
    .Hme133ctl(Latch133ctrl_OBUF_2109),
    .DCORIFGr(DCORIFGr),
    .DCORIFGw(DCORIFGw),
    .Enc05flg(Enc05FLG_IBUF_2037),
    .Hme15flg(Home15FLG_IBUF_2072),
    .Enc133flg(NLW_U4_Enc133flg_UNCONNECTED),
    .Hme133flg(Latch133FLG_IBUF_2107),
    .Enc15ctl(Enc15ctrl_OBUF_2043),
    .Enc15flg(Enc15FLG_IBUF_2041),
    .Mclk(Mclk_IBUF_2121),
    .outDATA({outDATA[7], outDATA[6], outDATA[5], outDATA[4], outDATA[3], outDATA[2], outDATA[1], outDATA[0]}),
    .inDATA({N20, N21, N22, N23, N24, N25, N26, N27})
  );
  Sensor   U8 (
    .TmpSlct(TmpSlct_OBUF_2226),
    .Reset(Reset),
    .DCORSENSORw(DCORSENSORw),
    .TmpEn(TmpEn_OBUF_2224),
    .PresEn(PresEn_OBUF_2191),
    .PresSlct(PresSlct_OBUF_2193),
    .Mclk(Mclk_IBUF_2121),
    .MReset(MReset_IBUF_2113),
    .inDATA({N24, N25, N26, N27})
  );
  MISCouts   U9 (
    .LightSense(LightSense_IBUF_2111),
    .MTRpwrn(MTRpwrn_OBUF_2119),
    .LED1(LED1_OBUF_2093),
    .LED2(LED2_OBUF_2095),
    .LED3(LED3_OBUF_2097),
    .LED4(LED4_OBUF_2099),
    .LED5(LED5_OBUF_2101),
    .Reset(Reset),
    .GP_Motor0_1(GP_Motor0_1_OBUF_2059),
    .GP_Motor1_1(GP_Motor1_1_OBUF_2063),
    .DCOROUTw(DCOROUTw),
    .Mclk(Mclk_IBUF_2121),
    .MTRpwr(MTRpwr_OBUF_2117),
    .MReset(MReset_IBUF_2113),
    .inDATA({N20, N21, N22, N23, N24, N25, N26, N27})
  );
  Servos   U1 (
    .DCOR0CNTLOWr(DCOR0CNTLOWr),
    .DCORENCCTLw(DCORENCCTLw),
    .DCOR0THRESLOWr(DCOR0THRESLOWr),
    .PhaseB_Encoder0(PhaseB_Encoder0_IBUF_2187),
    .PhaseB_Encoder1(PhaseB_Encoder1_IBUF_2189),
    .DCOR0THRESHIGHr(DCOR0THRESHIGHr),
    .DCOR1CNTHIGHr(DCOR1CNTHIGHr),
    .Reset(Reset),
    .DCOR0CNTHIGHr(DCOR0CNTHIGHr),
    .DCOR1THRESHIGHr(DCOR1THRESHIGHr),
    .PhaseA_Encoder0(PhaseA_Encoder0_IBUF_2183),
    .PhaseA_Encoder1(PhaseA_Encoder1_IBUF_2185),
    .DCORIFGr(DCORIFGr),
    .Hfound0(NET2482),
    .Hfound1(NET2493),
    .DCORIFGw(DCORIFGw),
    .MotorIn0(GP_Motor0_0_IBUF_2057),
    .Motorin1(GP_Motor1_0_IBUF_2061),
    .TP(NLW_U1_TP_UNCONNECTED),
    .Home_Encoder0(Home0_IBUF_2069),
    .Home_Encoder1(Home1_IBUF_2075),
    .DCOR1CNTLOWr(DCOR1CNTLOWr),
    .ASleading(NET4826),
    .Mclk(Mclk_IBUF_2121),
    .DCOR1THRESLOWr(DCOR1THRESLOWr),
    .Tfound0(TP26_OBUF_2222),
    .Tfound1(NET2512),
    .outDATA({outDATA[7], outDATA[6], outDATA[5], outDATA[4], outDATA[3], outDATA[2], outDATA[1], outDATA[0]}),
    .inDATA({N20, N21, N22, N23, N24, N25, N26, N27})
  );
  INV   Reset1 (
    .I(MSPReset_IBUF_2115),
    .O(Reset)
  );
  INV   GPIO91 (
    .I(TmpEn_OBUF_2224),
    .O(GPIO91_2054)
  );
  AND2   GPIO92 (
    .I0(PWM3_IBUF_2178),
    .I1(GPIO91_2054),
    .O(GPIO9_OBUF_2055)
  );
  INV   GPIO101 (
    .I(TmpEn_OBUF_2224),
    .O(GPIO101_2049)
  );
  AND2   GPIO102 (
    .I0(PWM4_IBUF_2180),
    .I1(GPIO101_2049),
    .O(GPIO10_OBUF_2050)
  );
  AND4   \U2_Mcompar_ADDR_reg_cmp_lt0000_ALRANDC<3>1  (
    .I0(U2_ADDR_reg[3]),
    .I1(U2_ADDR_reg[2]),
    .I2(U2_ADDR_reg[1]),
    .I3(U2_ADDR_reg[0]),
    .O(U2_Mcompar_ADDR_reg_cmp_lt0000_ALRANDC[3])
  );
  OR2   \U2_Mcompar_ADDR_reg_cmp_lt0000_CARRY_IN<5>1  (
    .I0(U2_Mcompar_ADDR_reg_cmp_lt0000_ALRANDC[3]),
    .I1(U2_ADDR_reg[4]),
    .O(U2_Mcompar_ADDR_reg_cmp_lt0000_CARRY_IN[5])
  );
  OR2   \U2_Mcompar_ADDR_reg_cmp_lt0000_CARRY_IN<6>1  (
    .I0(U2_Mcompar_ADDR_reg_cmp_lt0000_CARRY_IN[5]),
    .I1(U2_ADDR_reg[5]),
    .O(U2_Mcompar_ADDR_reg_cmp_lt0000_CARRY_IN[6])
  );
  OR2   \U2_Mcompar_ADDR_reg_cmp_lt0000_CARRY_IN<7>1  (
    .I0(U2_Mcompar_ADDR_reg_cmp_lt0000_CARRY_IN[6]),
    .I1(U2_ADDR_reg[6]),
    .O(U2_Mcompar_ADDR_reg_cmp_lt0000_CARRY_IN[7])
  );
  INV   U2_Mcompar_ADDR_reg_cmp_lt0000_ALB1 (
    .I(U2_ADDR_reg[7]),
    .O(U2_Mcompar_ADDR_reg_cmp_lt0000_ALB)
  );
  INV   U2_Mcompar_ADDR_reg_cmp_lt0000_ALB2 (
    .I(U2_Mcompar_ADDR_reg_cmp_lt0000_CARRY_IN[7]),
    .O(U2_Mcompar_ADDR_reg_cmp_lt0000_ALB1_2396)
  );
  AND2   U2_Mcompar_ADDR_reg_cmp_lt0000_ALB3 (
    .I0(U2_Mcompar_ADDR_reg_cmp_lt0000_ALB),
    .I1(U2_Mcompar_ADDR_reg_cmp_lt0000_ALB1_2396),
    .O(U2_ADDR_reg_cmp_lt0000)
  );
  AND2   U2_ADDR_reg_7__and00001 (
    .I0(MSPReset_IBUF_2115),
    .I1(U2_ADDR_reg_mux0001[7]),
    .O(U2_ADDR_reg_7__and0000)
  );
  AND2   U2_ADDR_reg_6__and00001 (
    .I0(MSPReset_IBUF_2115),
    .I1(U2_ADDR_reg_mux0001[6]),
    .O(U2_ADDR_reg_6__and0000)
  );
  AND2   U2_ADDR_reg_5__and00001 (
    .I0(MSPReset_IBUF_2115),
    .I1(U2_ADDR_reg_mux0001[5]),
    .O(U2_ADDR_reg_5__and0000)
  );
  AND2   U2_ADDR_reg_4__and00001 (
    .I0(MSPReset_IBUF_2115),
    .I1(U2_ADDR_reg_mux0001[4]),
    .O(U2_ADDR_reg_4__and0000)
  );
  AND2   U2_ADDR_reg_3__and00001 (
    .I0(MSPReset_IBUF_2115),
    .I1(U2_ADDR_reg_mux0001[3]),
    .O(U2_ADDR_reg_3__and0000)
  );
  AND2   U2_ADDR_reg_2__and00001 (
    .I0(MSPReset_IBUF_2115),
    .I1(U2_ADDR_reg_mux0001[2]),
    .O(U2_ADDR_reg_2__and0000)
  );
  AND2   U2_ADDR_reg_1__and00001 (
    .I0(MSPReset_IBUF_2115),
    .I1(U2_ADDR_reg_mux0001[1]),
    .O(U2_ADDR_reg_1__and0000)
  );
  INV   U2_ADDR_reg_0__or00001 (
    .I(U2_ADDR_reg_and0002),
    .O(U2_ADDR_reg_0__or00001_2317)
  );
  INV   U2_ADDR_reg_0__or00002 (
    .I(MSPReset_IBUF_2115),
    .O(U2_ADDR_reg_0__or00002_2318)
  );
  OR2   U2_ADDR_reg_0__or00003 (
    .I0(U2_ADDR_reg_0__or00001_2317),
    .I1(U2_ADDR_reg_0__or00002_2318),
    .O(U2_ADDR_reg_0__or0000)
  );
  AND2   U2_ADDR_reg_0__and00001 (
    .I0(MSPReset_IBUF_2115),
    .I1(U2_ADDR_reg_mux0001[0]),
    .O(U2_ADDR_reg_0__and0000)
  );
  AND2   U2_Madd_ADDR_reg_addsub0000__and00001 (
    .I0(U2_ADDR_reg[1]),
    .I1(U2_ADDR_reg[0]),
    .O(U2_Madd_ADDR_reg_addsub0000__and0000)
  );
  AND2   U2_Madd_ADDR_reg_addsub0000__and00011 (
    .I0(U2_ADDR_reg[2]),
    .I1(U2_Madd_ADDR_reg_addsub0000__and0000),
    .O(U2_Madd_ADDR_reg_addsub0000__and0001)
  );
  AND2   U2_Madd_ADDR_reg_addsub0000__and00021 (
    .I0(U2_ADDR_reg[3]),
    .I1(U2_Madd_ADDR_reg_addsub0000__and0001),
    .O(U2_Madd_ADDR_reg_addsub0000__and0002)
  );
  AND2   U2_Madd_ADDR_reg_addsub0000__and00031 (
    .I0(U2_ADDR_reg[4]),
    .I1(U2_Madd_ADDR_reg_addsub0000__and0002),
    .O(U2_Madd_ADDR_reg_addsub0000__and0003)
  );
  AND2   U2_Madd_ADDR_reg_addsub0000__and00041 (
    .I0(U2_ADDR_reg[5]),
    .I1(U2_Madd_ADDR_reg_addsub0000__and0003),
    .O(U2_Madd_ADDR_reg_addsub0000__and0004)
  );
  AND2   U2_Madd_ADDR_reg_addsub0000__and00051 (
    .I0(U2_ADDR_reg[6]),
    .I1(U2_Madd_ADDR_reg_addsub0000__and0004),
    .O(U2_Madd_ADDR_reg_addsub0000__and0005)
  );
  INV   U2_AutoInc_not00011 (
    .I(AS_IBUF_2007),
    .O(U2_AutoInc_not0001)
  );
  INV   U2_ADDR_reg_and00021 (
    .I(U2_ADDR_reg_and0000),
    .O(U2_ADDR_reg_and00021_2346)
  );
  INV   U2_ADDR_reg_and00022 (
    .I(U2_ADDR_reg_and0001),
    .O(U2_ADDR_reg_and00022_2347)
  );
  AND2   U2_ADDR_reg_and00023 (
    .I0(U2_ADDR_reg_and00021_2346),
    .I1(U2_ADDR_reg_and00022_2347),
    .O(U2_ADDR_reg_and0002)
  );
  INV   U2_AutoInc_and00001 (
    .I(U2_WRRDedge_and0000),
    .O(U2_AutoInc_and00001_2384)
  );
  AND2   U2_AutoInc_and00002 (
    .I0(U2_WRRDedge_2401),
    .I1(U2_AutoInc_and00001_2384),
    .O(U2_AutoInc_and0000)
  );
  INV   U2_ASleading1 (
    .I(AS_IBUF_2007),
    .O(U2_ASleading)
  );
  AND2   U2_ASleading2 (
    .I0(U2_ASedge_2380),
    .I1(U2_ASleading),
    .O(NET4826)
  );
  AND2   U2_Enable_AD1 (
    .I0(U2_ADDR_in_Range),
    .I1(WR_IBUF_2404),
    .O(U2_Enable_AD1_2387)
  );
  INV   U2_Enable_AD2 (
    .I(RD_IBUF_2195),
    .O(U2_Enable_AD2_2388)
  );
  AND2   U2_Enable_AD3 (
    .I0(U2_Enable_AD1_2387),
    .I1(U2_Enable_AD2_2388),
    .O(U2_Enable_AD)
  );
  INV   U11_U3_SCLint_cmp_eq00001 (
    .I(U11_U3_counterr[4]),
    .O(U11_U3_SCLint_cmp_eq0000)
  );
  INV   U11_U3_SCLint_cmp_eq00002 (
    .I(U11_U3_counterr[3]),
    .O(U11_U3_SCLint_cmp_eq00001_2253)
  );
  INV   U11_U3_SCLint_cmp_eq00003 (
    .I(U11_U3_counterr[5]),
    .O(U11_U3_SCLint_cmp_eq00002_2254)
  );
  AND4   U11_U3_SCLint_cmp_eq00004 (
    .I0(SFDecomp_3),
    .I1(U11_U3_SCLint_cmp_eq0000),
    .I2(U11_U3_SCLint_cmp_eq00001_2253),
    .I3(U11_U3_SCLint_cmp_eq00002_2254),
    .O(TP12_OBUF_2218)
  );
  INV   U2_ADDR_reg_0_0_not00001 (
    .I(Mclk_IBUF_2121),
    .O(U2_ADDR_reg_0_0_not0000)
  );
  OR2   \U11_U3_counterr_mux0001<2>1  (
    .I0(SCLreset_IBUF_2205),
    .I1(U11_Incdetect),
    .O(\U11_U3_counterr_mux0001<2>1_2296 )
  );
  INV   \U11_U3_counterr_mux0001<2>2  (
    .I(U11_SCLdetect),
    .O(\U11_U3_counterr_mux0001<2>2_2297 )
  );
  OR2   \U11_U3_counterr_mux0001<2>3  (
    .I0(\U11_U3_counterr_mux0001<2>1_2296 ),
    .I1(\U11_U3_counterr_mux0001<2>2_2297 ),
    .O(\U11_U3_counterr_mux0001[2] )
  );
  AND2   \U11_U3_counterr_mux0000<5>2  (
    .I0(SCLinc_IBUF_2203),
    .I1(SCLreset_IBUF_2205),
    .O(\U11_U3_counterr_mux0000<5>1 )
  );
  INV   \U11_U3_counterr_mux0000<5>3  (
    .I(SCLreset_IBUF_2205),
    .O(\U11_U3_counterr_mux0000<5>2_2293 )
  );
  AND2   \U11_U3_counterr_mux0000<5>4  (
    .I0(N1),
    .I1(\U11_U3_counterr_mux0000<5>2_2293 ),
    .O(\U11_U3_counterr_mux0000<5>3_2294 )
  );
  OR2   \U11_U3_counterr_mux0000<5>5  (
    .I0(\U11_U3_counterr_mux0000<5>1 ),
    .I1(\U11_U3_counterr_mux0000<5>3_2294 ),
    .O(U11_U3_counterr_mux0000[5])
  );
  INV   \U11_U3_counterr_mux0001<5>2  (
    .I(SCLreset_IBUF_2205),
    .O(\U11_U3_counterr_mux0001<5>1 )
  );
  AND2   \U11_U3_counterr_mux0001<5>3  (
    .I0(N2),
    .I1(\U11_U3_counterr_mux0001<5>1 ),
    .O(\U11_U3_counterr_mux0001[5] )
  );
  OR2   U11_U3_Maddsub_counterr_share0000__or000011 (
    .I0(\U11_U3_Maddsub_counterr_share0000_Mxor_Result<5>__xor0001 ),
    .I1(U11_U3_Maddsub_counterr_share0000_or0000_xor0000),
    .O(N3)
  );
  AND2   U11_U3_Maddsub_counterr_share0000__or00001 (
    .I0(U11_U3_counterr[0]),
    .I1(N3),
    .O(U11_U3_Maddsub_counterr_share0000__or0000)
  );
  OR2   U11_U3_Maddsub_counterr_share0000__or000111 (
    .I0(U11_U3_Maddsub_counterr_share0000__or0000),
    .I1(\U11_U3_Maddsub_counterr_share0000_Mxor_Result<5>__xor0001 ),
    .O(N4)
  );
  AND2   U11_U3_Maddsub_counterr_share0000__or00011 (
    .I0(U11_U3_Maddsub_counterr_share0000__or0000),
    .I1(\U11_U3_Maddsub_counterr_share0000_Mxor_Result<5>__xor0001 ),
    .O(U11_U3_Maddsub_counterr_share0000__or00011_2238)
  );
  AND2   U11_U3_Maddsub_counterr_share0000__or00012 (
    .I0(U11_U3_counterr[1]),
    .I1(N4),
    .O(U11_U3_Maddsub_counterr_share0000__or00012_2239)
  );
  OR2   U11_U3_Maddsub_counterr_share0000__or00013 (
    .I0(U11_U3_Maddsub_counterr_share0000__or00011_2238),
    .I1(U11_U3_Maddsub_counterr_share0000__or00012_2239),
    .O(U11_U3_Maddsub_counterr_share0000__or0001)
  );
  OR2   U11_U3_Maddsub_counterr_share0000__or000211 (
    .I0(U11_U3_Maddsub_counterr_share0000__or0001),
    .I1(\U11_U3_Maddsub_counterr_share0000_Mxor_Result<5>__xor0001 ),
    .O(N5)
  );
  AND2   U11_U3_Maddsub_counterr_share0000__or00021 (
    .I0(U11_U3_Maddsub_counterr_share0000__or0001),
    .I1(\U11_U3_Maddsub_counterr_share0000_Mxor_Result<5>__xor0001 ),
    .O(U11_U3_Maddsub_counterr_share0000__or00021_2241)
  );
  AND2   U11_U3_Maddsub_counterr_share0000__or00022 (
    .I0(U11_U3_counterr[2]),
    .I1(N5),
    .O(U11_U3_Maddsub_counterr_share0000__or00022_2242)
  );
  OR2   U11_U3_Maddsub_counterr_share0000__or00023 (
    .I0(U11_U3_Maddsub_counterr_share0000__or00021_2241),
    .I1(U11_U3_Maddsub_counterr_share0000__or00022_2242),
    .O(U11_U3_Maddsub_counterr_share0000__or0002)
  );
  OR2   U11_U3_Maddsub_counterr_share0000__or000311 (
    .I0(U11_U3_Maddsub_counterr_share0000__or0002),
    .I1(U11_U3_Maddsub_counterr_share0000_or0003_xor0000),
    .O(N6)
  );
  AND2   U11_U3_Maddsub_counterr_share0000__or00031 (
    .I0(U11_U3_Maddsub_counterr_share0000__or0002),
    .I1(U11_U3_Maddsub_counterr_share0000_or0003_xor0000),
    .O(U11_U3_Maddsub_counterr_share0000__or00031_2244)
  );
  AND2   U11_U3_Maddsub_counterr_share0000__or00032 (
    .I0(U11_U3_counterr[3]),
    .I1(N6),
    .O(U11_U3_Maddsub_counterr_share0000__or00032_2245)
  );
  OR2   U11_U3_Maddsub_counterr_share0000__or00033 (
    .I0(U11_U3_Maddsub_counterr_share0000__or00031_2244),
    .I1(U11_U3_Maddsub_counterr_share0000__or00032_2245),
    .O(U11_U3_Maddsub_counterr_share0000__or0003)
  );
  OR2   U11_U3_Maddsub_counterr_share0000__or000411 (
    .I0(U11_U3_Maddsub_counterr_share0000__or0003),
    .I1(\U11_U3_Maddsub_counterr_share0000_Mxor_Result<5>__xor0001 ),
    .O(N7)
  );
  AND2   U11_U3_Maddsub_counterr_share0000__or00041 (
    .I0(U11_U3_Maddsub_counterr_share0000__or0003),
    .I1(\U11_U3_Maddsub_counterr_share0000_Mxor_Result<5>__xor0001 ),
    .O(U11_U3_Maddsub_counterr_share0000__or00041_2247)
  );
  AND2   U11_U3_Maddsub_counterr_share0000__or00042 (
    .I0(U11_U3_counterr[4]),
    .I1(N7),
    .O(U11_U3_Maddsub_counterr_share0000__or00042_2248)
  );
  OR2   U11_U3_Maddsub_counterr_share0000__or00043 (
    .I0(U11_U3_Maddsub_counterr_share0000__or00041_2247),
    .I1(U11_U3_Maddsub_counterr_share0000__or00042_2248),
    .O(U11_U3_Maddsub_counterr_share0000__or0004)
  );
  INV   \U11_U3_counterr_mux0001<5>111  (
    .I(U11_ResetDetect),
    .O(\U11_U3_counterr_mux0001<5>11_2300 )
  );
  OR2   \U11_U3_counterr_mux0001<5>112  (
    .I0(SCLinc_IBUF_2203),
    .I1(\U11_U3_counterr_mux0001<5>11_2300 ),
    .O(N8)
  );
  INV   \U11_U3_counterr_mux0000<0>2  (
    .I(SCLreset_IBUF_2205),
    .O(\U11_U3_counterr_mux0000<0>1 )
  );
  AND2   \U11_U3_counterr_mux0000<0>3  (
    .I0(N9),
    .I1(\U11_U3_counterr_mux0000<0>1 ),
    .O(U11_U3_counterr_mux0000[0])
  );
  INV   \U11_U3_counterr_mux0000<1>2  (
    .I(SCLreset_IBUF_2205),
    .O(\U11_U3_counterr_mux0000<1>1 )
  );
  AND2   \U11_U3_counterr_mux0000<1>3  (
    .I0(N10),
    .I1(\U11_U3_counterr_mux0000<1>1 ),
    .O(U11_U3_counterr_mux0000[1])
  );
  INV   \U11_U3_counterr_mux0000<3>2  (
    .I(SCLreset_IBUF_2205),
    .O(\U11_U3_counterr_mux0000<3>1 )
  );
  AND2   \U11_U3_counterr_mux0000<3>3  (
    .I0(N11),
    .I1(\U11_U3_counterr_mux0000<3>1 ),
    .O(U11_U3_counterr_mux0000[3])
  );
  INV   \U11_U3_counterr_mux0000<4>3  (
    .I(SCLinc_IBUF_2203),
    .O(\U11_U3_counterr_mux0000<4>1 )
  );
  INV   \U11_U3_counterr_mux0000<4>4  (
    .I(SCLreset_IBUF_2205),
    .O(\U11_U3_counterr_mux0000<4>2 )
  );
  AND2   \U11_U3_counterr_mux0000<4>5  (
    .I0(SCLreset_IBUF_2205),
    .I1(\U11_U3_counterr_mux0000<4>1 ),
    .O(\U11_U3_counterr_mux0000<4>3_2284 )
  );
  AND2   \U11_U3_counterr_mux0000<4>6  (
    .I0(N12),
    .I1(\U11_U3_counterr_mux0000<4>2 ),
    .O(\U11_U3_counterr_mux0000<4>4_2285 )
  );
  OR2   \U11_U3_counterr_mux0000<4>7  (
    .I0(\U11_U3_counterr_mux0000<4>3_2284 ),
    .I1(\U11_U3_counterr_mux0000<4>4_2285 ),
    .O(U11_U3_counterr_mux0000[4])
  );
  INV   \U11_U3_counterr_mux0000<5>111  (
    .I(SCLinc_IBUF_2203),
    .O(\U11_U3_counterr_mux0000<5>11_2288 )
  );
  AND2   \U11_U3_counterr_mux0000<5>112  (
    .I0(U11_ResetDetect),
    .I1(\U11_U3_counterr_mux0000<5>11_2288 ),
    .O(\U11_U3_counterr_mux0000<5>111_2289 )
  );
  OR2   \U11_U3_counterr_mux0000<5>113  (
    .I0(U11_U3_counterr_share0000[0]),
    .I1(\U11_U3_counterr_mux0000<5>111_2289 ),
    .O(N13)
  );
  INV   \U2_ADDR_reg_mux0001<0>11  (
    .I(U2_ADDR_reg[6]),
    .O(\U2_ADDR_reg_mux0001<0>1_2350 )
  );
  INV   \U2_ADDR_reg_mux0001<0>12  (
    .I(U2_ADDR_reg[4]),
    .O(\U2_ADDR_reg_mux0001<0>11_2351 )
  );
  INV   \U2_ADDR_reg_mux0001<0>13  (
    .I(U2_ADDR_reg[5]),
    .O(\U2_ADDR_reg_mux0001<0>12_2352 )
  );
  INV   \U2_ADDR_reg_mux0001<0>14  (
    .I(U2_ADDR_reg[7]),
    .O(\U2_ADDR_reg_mux0001<0>13_2353 )
  );
  AND4   \U2_ADDR_reg_mux0001<0>15  (
    .I0(\U2_ADDR_reg_mux0001<0>1_2350 ),
    .I1(\U2_ADDR_reg_mux0001<0>11_2351 ),
    .I2(\U2_ADDR_reg_mux0001<0>12_2352 ),
    .I3(\U2_ADDR_reg_mux0001<0>13_2353 ),
    .O(U2_ADDR_in_Range)
  );
  AND2   \U2_ADDR_reg_mux0001<0>1  (
    .I0(N27),
    .I1(U2_ADDR_reg_and0001),
    .O(\U2_ADDR_reg_mux0001<0>2_2354 )
  );
  INV   \U2_ADDR_reg_mux0001<0>2  (
    .I(U2_ADDR_reg_and0001),
    .O(\U2_ADDR_reg_mux0001<0>3_2355 )
  );
  INV   \U2_ADDR_reg_mux0001<0>3  (
    .I(U2_ADDR_reg[0]),
    .O(\U2_ADDR_reg_mux0001<0>4_2356 )
  );
  AND3   \U2_ADDR_reg_mux0001<0>4  (
    .I0(\U2_ADDR_reg_mux0001<0>3_2355 ),
    .I1(U2_ADDR_in_Range),
    .I2(\U2_ADDR_reg_mux0001<0>4_2356 ),
    .O(\U2_ADDR_reg_mux0001<0>5_2357 )
  );
  OR2   \U2_ADDR_reg_mux0001<0>5  (
    .I0(\U2_ADDR_reg_mux0001<0>2_2354 ),
    .I1(\U2_ADDR_reg_mux0001<0>5_2357 ),
    .O(U2_ADDR_reg_mux0001[0])
  );
  INV   \U2_ADDR_reg_mux0001<1>11  (
    .I(U2_ADDR_reg_and0001),
    .O(\U2_ADDR_reg_mux0001<1>1_2359 )
  );
  AND2   \U2_ADDR_reg_mux0001<1>12  (
    .I0(U2_ADDR_reg_cmp_lt0000),
    .I1(\U2_ADDR_reg_mux0001<1>1_2359 ),
    .O(N15)
  );
  AND2   \U2_ADDR_reg_mux0001<1>1  (
    .I0(N26),
    .I1(U2_ADDR_reg_and0001),
    .O(\U2_ADDR_reg_mux0001<1>2_2360 )
  );
  AND2   \U2_ADDR_reg_mux0001<1>2  (
    .I0(U2_ADDR_reg_addsub0000[1]),
    .I1(N15),
    .O(\U2_ADDR_reg_mux0001<1>3_2361 )
  );
  OR2   \U2_ADDR_reg_mux0001<1>3  (
    .I0(\U2_ADDR_reg_mux0001<1>2_2360 ),
    .I1(\U2_ADDR_reg_mux0001<1>3_2361 ),
    .O(U2_ADDR_reg_mux0001[1])
  );
  AND2   \U2_ADDR_reg_mux0001<2>1  (
    .I0(N25),
    .I1(U2_ADDR_reg_and0001),
    .O(\U2_ADDR_reg_mux0001<2>1_2363 )
  );
  AND2   \U2_ADDR_reg_mux0001<2>2  (
    .I0(U2_ADDR_reg_addsub0000[2]),
    .I1(N15),
    .O(\U2_ADDR_reg_mux0001<2>2_2364 )
  );
  OR2   \U2_ADDR_reg_mux0001<2>3  (
    .I0(\U2_ADDR_reg_mux0001<2>1_2363 ),
    .I1(\U2_ADDR_reg_mux0001<2>2_2364 ),
    .O(U2_ADDR_reg_mux0001[2])
  );
  AND2   \U2_ADDR_reg_mux0001<3>1  (
    .I0(N24),
    .I1(U2_ADDR_reg_and0001),
    .O(\U2_ADDR_reg_mux0001<3>1_2366 )
  );
  AND2   \U2_ADDR_reg_mux0001<3>2  (
    .I0(U2_ADDR_reg_addsub0000[3]),
    .I1(N15),
    .O(\U2_ADDR_reg_mux0001<3>2_2367 )
  );
  OR2   \U2_ADDR_reg_mux0001<3>3  (
    .I0(\U2_ADDR_reg_mux0001<3>1_2366 ),
    .I1(\U2_ADDR_reg_mux0001<3>2_2367 ),
    .O(U2_ADDR_reg_mux0001[3])
  );
  AND2   \U2_ADDR_reg_mux0001<4>1  (
    .I0(N23),
    .I1(U2_ADDR_reg_and0001),
    .O(\U2_ADDR_reg_mux0001<4>1_2369 )
  );
  AND2   \U2_ADDR_reg_mux0001<4>2  (
    .I0(U2_ADDR_reg_addsub0000[4]),
    .I1(N15),
    .O(\U2_ADDR_reg_mux0001<4>2_2370 )
  );
  OR2   \U2_ADDR_reg_mux0001<4>3  (
    .I0(\U2_ADDR_reg_mux0001<4>1_2369 ),
    .I1(\U2_ADDR_reg_mux0001<4>2_2370 ),
    .O(U2_ADDR_reg_mux0001[4])
  );
  AND2   \U2_ADDR_reg_mux0001<5>1  (
    .I0(N22),
    .I1(U2_ADDR_reg_and0001),
    .O(\U2_ADDR_reg_mux0001<5>1_2372 )
  );
  AND2   \U2_ADDR_reg_mux0001<5>2  (
    .I0(U2_ADDR_reg_addsub0000[5]),
    .I1(N15),
    .O(\U2_ADDR_reg_mux0001<5>2_2373 )
  );
  OR2   \U2_ADDR_reg_mux0001<5>3  (
    .I0(\U2_ADDR_reg_mux0001<5>1_2372 ),
    .I1(\U2_ADDR_reg_mux0001<5>2_2373 ),
    .O(U2_ADDR_reg_mux0001[5])
  );
  AND2   \U2_ADDR_reg_mux0001<6>1  (
    .I0(N21),
    .I1(U2_ADDR_reg_and0001),
    .O(\U2_ADDR_reg_mux0001<6>1_2375 )
  );
  AND2   \U2_ADDR_reg_mux0001<6>2  (
    .I0(U2_ADDR_reg_addsub0000[6]),
    .I1(N15),
    .O(\U2_ADDR_reg_mux0001<6>2_2376 )
  );
  OR2   \U2_ADDR_reg_mux0001<6>3  (
    .I0(\U2_ADDR_reg_mux0001<6>1_2375 ),
    .I1(\U2_ADDR_reg_mux0001<6>2_2376 ),
    .O(U2_ADDR_reg_mux0001[6])
  );
  AND2   \U2_ADDR_reg_mux0001<7>1  (
    .I0(N20),
    .I1(U2_ADDR_reg_and0001),
    .O(\U2_ADDR_reg_mux0001<7>1_2378 )
  );
  AND2   \U2_ADDR_reg_mux0001<7>2  (
    .I0(U2_ADDR_reg_addsub0000[7]),
    .I1(N15),
    .O(\U2_ADDR_reg_mux0001<7>2_2379 )
  );
  OR2   \U2_ADDR_reg_mux0001<7>3  (
    .I0(\U2_ADDR_reg_mux0001<7>1_2378 ),
    .I1(\U2_ADDR_reg_mux0001<7>2_2379 ),
    .O(U2_ADDR_reg_mux0001[7])
  );
  INV   \U11_U3_counterr_mux0000<5>121  (
    .I(U11_Incdetect),
    .O(\U11_U3_counterr_mux0000<5>12_2290 )
  );
  INV   \U11_U3_counterr_mux0000<5>122  (
    .I(U11_SCLdetect),
    .O(\U11_U3_counterr_mux0000<5>121_2291 )
  );
  AND2   \U11_U3_counterr_mux0000<5>123  (
    .I0(\U11_U3_counterr_mux0000<5>12_2290 ),
    .I1(\U11_U3_counterr_mux0000<5>121_2291 ),
    .O(N16)
  );
  AND2   \U11_U3_counterr_mux0000<2>1  (
    .I0(N01),
    .I1(U11_U3_counterr_share0000[3]),
    .O(\U11_U3_counterr_mux0000<2>1_2270 )
  );
  OR2   \U11_U3_counterr_mux0000<2>2  (
    .I0(SFDecomp_4),
    .I1(\U11_U3_counterr_mux0000<2>1_2270 ),
    .O(U11_U3_counterr_mux0000[2])
  );
  AND2   \U11_U3_counterr_mux0000<0>11  (
    .I0(N01),
    .I1(U11_U3_counterr_share0000[5]),
    .O(\U11_U3_counterr_mux0000<0>11_2263 )
  );
  AND2   \U11_U3_counterr_mux0000<0>12  (
    .I0(U11_U3_counterr[5]),
    .I1(N16),
    .O(\U11_U3_counterr_mux0000<0>12_2264 )
  );
  OR2   \U11_U3_counterr_mux0000<0>13  (
    .I0(\U11_U3_counterr_mux0000<0>11_2263 ),
    .I1(\U11_U3_counterr_mux0000<0>12_2264 ),
    .O(N9)
  );
  AND2   \U11_U3_counterr_mux0000<1>11  (
    .I0(N01),
    .I1(U11_U3_counterr_share0000[4]),
    .O(\U11_U3_counterr_mux0000<1>11_2267 )
  );
  AND2   \U11_U3_counterr_mux0000<1>12  (
    .I0(U11_U3_counterr[4]),
    .I1(N16),
    .O(\U11_U3_counterr_mux0000<1>12_2268 )
  );
  OR2   \U11_U3_counterr_mux0000<1>13  (
    .I0(\U11_U3_counterr_mux0000<1>11_2267 ),
    .I1(\U11_U3_counterr_mux0000<1>12_2268 ),
    .O(N10)
  );
  AND2   \U11_U3_counterr_mux0000<3>11  (
    .I0(N01),
    .I1(U11_U3_counterr_share0000[2]),
    .O(\U11_U3_counterr_mux0000<3>11_2273 )
  );
  AND2   \U11_U3_counterr_mux0000<3>12  (
    .I0(U11_U3_counterr[2]),
    .I1(N16),
    .O(\U11_U3_counterr_mux0000<3>12_2274 )
  );
  OR2   \U11_U3_counterr_mux0000<3>13  (
    .I0(\U11_U3_counterr_mux0000<3>11_2273 ),
    .I1(\U11_U3_counterr_mux0000<3>12_2274 ),
    .O(N11)
  );
  AND2   \U11_U3_counterr_mux0000<4>21  (
    .I0(N01),
    .I1(U11_U3_counterr_share0000[1]),
    .O(\U11_U3_counterr_mux0000<4>21_2282 )
  );
  AND2   \U11_U3_counterr_mux0000<4>22  (
    .I0(U11_U3_counterr[1]),
    .I1(N16),
    .O(\U11_U3_counterr_mux0000<4>22_2283 )
  );
  OR2   \U11_U3_counterr_mux0000<4>23  (
    .I0(\U11_U3_counterr_mux0000<4>21_2282 ),
    .I1(\U11_U3_counterr_mux0000<4>22_2283 ),
    .O(N12)
  );
  AND2   \U11_U3_counterr_mux0000<5>11  (
    .I0(N13),
    .I1(U11_Incdetect),
    .O(\U11_U3_counterr_mux0000<5>13 )
  );
  OR2   \U11_U3_counterr_mux0000<5>12  (
    .I0(SFDecomp_2),
    .I1(\U11_U3_counterr_mux0000<5>13 ),
    .O(N1)
  );
  INV   \U11_U3_counterr_mux0000<4>111  (
    .I(U11_Incdetect),
    .O(\U11_U3_counterr_mux0000<4>11_2277 )
  );
  AND2   \U11_U3_counterr_mux0000<4>112  (
    .I0(U11_SCLdetect),
    .I1(\U11_U3_counterr_mux0000<4>11_2277 ),
    .O(N17)
  );
  INV   U11_U3_counterr_or00031 (
    .I(SCLreset_IBUF_2205),
    .O(U11_U3_counterr_or00031_2305)
  );
  AND2   U11_U3_counterr_or00032 (
    .I0(N17),
    .I1(U11_U3_counterr_or00031_2305),
    .O(\U11_U3_Maddsub_counterr_share0000_Mxor_Result<5>__xor0001 )
  );
  AND2   \U11_U3_counterr_mux0000<4>11  (
    .I0(N8),
    .I1(U11_Incdetect),
    .O(\U11_U3_counterr_mux0000<4>12_2278 )
  );
  INV   \U11_U3_counterr_mux0000<4>12  (
    .I(TP12_OBUF_2218),
    .O(\U11_U3_counterr_mux0000<4>13_2279 )
  );
  AND2   \U11_U3_counterr_mux0000<4>13  (
    .I0(N17),
    .I1(\U11_U3_counterr_mux0000<4>13_2279 ),
    .O(\U11_U3_counterr_mux0000<4>14_2280 )
  );
  OR2   \U11_U3_counterr_mux0000<4>14  (
    .I0(\U11_U3_counterr_mux0000<4>12_2278 ),
    .I1(\U11_U3_counterr_mux0000<4>14_2280 ),
    .O(N01)
  );
  AND2   \U11_U3_counterr_mux0001<5>11  (
    .I0(U11_Incdetect),
    .I1(N8),
    .O(\U11_U3_counterr_mux0001<5>12_2301 )
  );
  INV   \U11_U3_counterr_mux0001<5>12  (
    .I(U11_SCLdetect),
    .O(\U11_U3_counterr_mux0001<5>13_2302 )
  );
  AND2   \U11_U3_counterr_mux0001<5>13  (
    .I0(\U11_U3_counterr_mux0001<5>12_2301 ),
    .I1(\U11_U3_counterr_mux0001<5>13_2302 ),
    .O(\U11_U3_counterr_mux0001<5>14_2303 )
  );
  OR2   \U11_U3_counterr_mux0001<5>14  (
    .I0(N17),
    .I1(\U11_U3_counterr_mux0001<5>14_2303 ),
    .O(N2)
  );
  AND2   U2_ADDR_reg_and000011 (
    .I0(RD_IBUF_2195),
    .I1(WR_IBUF_2404),
    .O(U2_WRRDedge_and0000)
  );
  AND2   U2_ADDR_reg_and00011 (
    .I0(NET4826),
    .I1(U2_WRRDedge_and0000),
    .O(U2_ADDR_reg_and0001)
  );
  AND2   U2_ADDR_reg_and00001 (
    .I0(U2_ADDR_in_Range),
    .I1(U2_AutoInc_2382),
    .O(U2_ADDR_reg_and00001_2341)
  );
  INV   U2_ADDR_reg_and00002 (
    .I(U2_WRRDedge_2401),
    .O(U2_ADDR_reg_and00002_2342)
  );
  AND2   U2_ADDR_reg_and00003 (
    .I0(U2_WRRDedge_and0000),
    .I1(U2_ADDR_reg_and00002_2342),
    .O(U2_ADDR_reg_and00003_2343)
  );
  AND2   U2_ADDR_reg_and00004 (
    .I0(U2_ADDR_reg_and00001_2341),
    .I1(U2_ADDR_reg_and00003_2343),
    .O(U2_ADDR_reg_and0000)
  );
  AND2   SFDecomp_11 (
    .I0(U11_SCLdetect),
    .I1(U11_U3_counterr_share0000[0]),
    .O(SFDecomp_11_2207)
  );
  INV   SFDecomp_12 (
    .I(TP12_OBUF_2218),
    .O(SFDecomp_12_2208)
  );
  AND2   SFDecomp_13 (
    .I0(SFDecomp_11_2207),
    .I1(SFDecomp_12_2208),
    .O(SFDecomp_1)
  );
  AND2   SFDecomp_21 (
    .I0(U11_U3_counterr[0]),
    .I1(N16),
    .O(SFDecomp_21_2210)
  );
  OR2   SFDecomp_22 (
    .I0(SFDecomp_1),
    .I1(SFDecomp_21_2210),
    .O(SFDecomp_2)
  );
  INV   SFDecomp_31 (
    .I(U11_U3_counterr[0]),
    .O(SFDecomp_31_2212)
  );
  INV   SFDecomp_32 (
    .I(U11_U3_counterr[2]),
    .O(SFDecomp_32_2213)
  );
  INV   SFDecomp_33 (
    .I(U11_U3_counterr[1]),
    .O(SFDecomp_33_2214)
  );
  AND3   SFDecomp_34 (
    .I0(SFDecomp_32_2213),
    .I1(SFDecomp_31_2212),
    .I2(SFDecomp_33_2214),
    .O(SFDecomp_3)
  );
  AND2   SFDecomp_41 (
    .I0(U11_U3_counterr[3]),
    .I1(N16),
    .O(SFDecomp_41_2216)
  );
  OR2   SFDecomp_42 (
    .I0(SCLreset_IBUF_2205),
    .I1(SFDecomp_41_2216),
    .O(SFDecomp_4)
  );
  IBUF   Brake0_IBUF (
    .I(Brake0),
    .O(Brake0_IBUF_2009)
  );
  IBUF   Brake1_IBUF (
    .I(Brake1),
    .O(Brake1_IBUF_2011)
  );
  IBUF   LightSense_IBUF (
    .I(LightSense),
    .O(LightSense_IBUF_2111)
  );
  IBUF   AS_IBUF (
    .I(AS),
    .O(AS_IBUF_2007)
  );
  IBUF   PhaseB_Encoder0_IBUF (
    .I(PhaseB_Encoder0),
    .O(PhaseB_Encoder0_IBUF_2187)
  );
  IBUF   MSPReset_IBUF (
    .I(MSPReset),
    .O(MSPReset_IBUF_2115)
  );
  IBUF   PhaseB_Encoder1_IBUF (
    .I(PhaseB_Encoder1),
    .O(PhaseB_Encoder1_IBUF_2189)
  );
  IBUF   INTbus_IBUF (
    .I(INTbus),
    .O(INTbus_IBUF_2091)
  );
  IBUF   Latch033FLG_IBUF (
    .I(Latch033FLG),
    .O(Latch033FLG_IBUF_2103)
  );
  IBUF   Home05FLG_IBUF (
    .I(Home05FLG),
    .O(Home05FLG_IBUF_2066)
  );
  IBUF   PhaseA_Encoder0_IBUF (
    .I(PhaseA_Encoder0),
    .O(PhaseA_Encoder0_IBUF_2183)
  );
  IBUF   PhaseA_Encoder1_IBUF (
    .I(PhaseA_Encoder1),
    .O(PhaseA_Encoder1_IBUF_2185)
  );
  IBUF   PWM1_IBUF (
    .I(PWM1),
    .O(PWM1_IBUF_2174)
  );
  IBUF   Home0_IBUF (
    .I(Home0),
    .O(Home0_IBUF_2069)
  );
  IBUF   PWM2_IBUF (
    .I(PWM2),
    .O(PWM2_IBUF_2176)
  );
  IBUF   Home1_IBUF (
    .I(Home1),
    .O(Home1_IBUF_2075)
  );
  IBUF   PWM3_IBUF (
    .I(PWM3),
    .O(PWM3_IBUF_2178)
  );
  IBUF   PWM4_IBUF (
    .I(PWM4),
    .O(PWM4_IBUF_2180)
  );
  IBUF   RLS0_IBUF (
    .I(RLS0),
    .O(RLS0_IBUF_2197)
  );
  IBUF   PWM5_IBUF (
    .I(PWM5),
    .O(GPIO8_OBUF_2052)
  );
  IBUF   RLS1_IBUF (
    .I(RLS1),
    .O(RLS1_IBUF_2199)
  );
  IBUF   Latch133FLG_IBUF (
    .I(Latch133FLG),
    .O(Latch133FLG_IBUF_2107)
  );
  IBUF   GP_Motor0_0_IBUF (
    .I(GP_Motor0_0),
    .O(GP_Motor0_0_IBUF_2057)
  );
  IBUF   Home15FLG_IBUF (
    .I(Home15FLG),
    .O(Home15FLG_IBUF_2072)
  );
  IBUF   RD_IBUF (
    .I(RD),
    .O(RD_IBUF_2195)
  );
  IBUF   Enc05FLG_IBUF (
    .I(Enc05FLG),
    .O(Enc05FLG_IBUF_2037)
  );
  IBUF   GP_Motor1_0_IBUF (
    .I(GP_Motor1_0),
    .O(GP_Motor1_0_IBUF_2061)
  );
  IBUF   FLS0_IBUF (
    .I(FLS0),
    .O(FLS0_IBUF_2045)
  );
  IBUF   FLS1_IBUF (
    .I(FLS1),
    .O(FLS1_IBUF_2047)
  );
  IBUF   WR_IBUF (
    .I(WR),
    .O(WR_IBUF_2404)
  );
  IBUF   Enc15FLG_IBUF (
    .I(Enc15FLG),
    .O(Enc15FLG_IBUF_2041)
  );
  IBUF   SCLreset_IBUF (
    .I(SCLreset),
    .O(SCLreset_IBUF_2205)
  );
  IBUF   DIR0_IBUF (
    .I(DIR0),
    .O(DIR0_IBUF_2033)
  );
  IBUF   DIR1_IBUF (
    .I(DIR1),
    .O(DIR1_IBUF_2035)
  );
  IBUF   Mclk_IBUF (
    .I(Mclk),
    .O(Mclk_IBUF_2121)
  );
  IBUF   SCLinc_IBUF (
    .I(SCLinc),
    .O(SCLinc_IBUF_2203)
  );
  IBUF   MReset_IBUF (
    .I(MReset),
    .O(MReset_IBUF_2113)
  );
  IBUF   I2CS_5_IBUF (
    .I(I2CS[5]),
    .O(I2CS_5_IBUF_2087)
  );
  IBUF   I2CS_4_IBUF (
    .I(I2CS[4]),
    .O(I2CS_4_IBUF_2086)
  );
  IBUF   I2CS_3_IBUF (
    .I(I2CS[3]),
    .O(I2CS_3_IBUF_2085)
  );
  IBUF   I2CS_2_IBUF (
    .I(I2CS[2]),
    .O(I2CS_2_IBUF_2084)
  );
  IBUF   I2CS_1_IBUF (
    .I(I2CS[1]),
    .O(I2CS_1_IBUF_2083)
  );
  IBUF   I2CS_0_IBUF (
    .I(I2CS[0]),
    .O(I2CS_0_IBUF_2082)
  );
  IOBUFE   SCL_IOBUFE (
    .I(N0),
    .E(TP12_OBUF_2218),
    .O(N19),
    .IO(SCL)
  );
  IOBUFE   AD_7_IOBUFE (
    .I(outDATA[7]),
    .E(U2_Enable_AD),
    .O(N20),
    .IO(AD[7])
  );
  IOBUFE   AD_6_IOBUFE (
    .I(outDATA[6]),
    .E(U2_Enable_AD),
    .O(N21),
    .IO(AD[6])
  );
  IOBUFE   AD_5_IOBUFE (
    .I(outDATA[5]),
    .E(U2_Enable_AD),
    .O(N22),
    .IO(AD[5])
  );
  IOBUFE   AD_4_IOBUFE (
    .I(outDATA[4]),
    .E(U2_Enable_AD),
    .O(N23),
    .IO(AD[4])
  );
  IOBUFE   AD_3_IOBUFE (
    .I(outDATA[3]),
    .E(U2_Enable_AD),
    .O(N24),
    .IO(AD[3])
  );
  IOBUFE   AD_2_IOBUFE (
    .I(outDATA[2]),
    .E(U2_Enable_AD),
    .O(N25),
    .IO(AD[2])
  );
  IOBUFE   AD_1_IOBUFE (
    .I(outDATA[1]),
    .E(U2_Enable_AD),
    .O(N26),
    .IO(AD[1])
  );
  IOBUFE   AD_0_IOBUFE (
    .I(outDATA[0]),
    .E(U2_Enable_AD),
    .O(N27),
    .IO(AD[0])
  );
  OBUF   Latch133ctrl_OBUF (
    .I(Latch133ctrl_OBUF_2109),
    .O(Latch133ctrl)
  );
  OBUF   MTRpwrn_OBUF (
    .I(MTRpwrn_OBUF_2119),
    .O(MTRpwrn)
  );
  OBUF   Home15ctrl_OBUF (
    .I(Home15ctrl_OBUF_2074),
    .O(Home15ctrl)
  );
  OBUF   Latch033ctrl_OBUF (
    .I(Latch033ctrl_OBUF_2105),
    .O(Latch033ctrl)
  );
  OBUF   TmpSlct_OBUF (
    .I(TmpSlct_OBUF_2226),
    .O(TmpSlct)
  );
  OBUF   LED1_OBUF (
    .I(LED1_OBUF_2093),
    .O(LED1)
  );
  OBUF   Enc05ctrl_OBUF (
    .I(Enc05ctrl_OBUF_2039),
    .O(Enc05ctrl)
  );
  OBUF   LED2_OBUF (
    .I(LED2_OBUF_2095),
    .O(LED2)
  );
  OBUF   LED3_OBUF (
    .I(LED3_OBUF_2097),
    .O(LED3)
  );
  OBUF   LED4_OBUF (
    .I(LED4_OBUF_2099),
    .O(LED4)
  );
  OBUF   LED5_OBUF (
    .I(LED5_OBUF_2101),
    .O(LED5)
  );
  OBUF   TP12_OBUF (
    .I(TP12_OBUF_2218),
    .O(TP12)
  );
  OBUF   TP21_OBUF (
    .I(TP21_OBUF_2220),
    .O(TP21)
  );
  OBUF   TP26_OBUF (
    .I(TP26_OBUF_2222),
    .O(TP26)
  );
  OBUF   PAH0_OBUF (
    .I(PAH0_OBUF_2158),
    .O(PAH0)
  );
  OBUF   PAH1_OBUF (
    .I(PAH1_OBUF_2160),
    .O(PAH1)
  );
  OBUF   Enc15ctrl_OBUF (
    .I(Enc15ctrl_OBUF_2043),
    .O(Enc15ctrl)
  );
  OBUF   GP_Motor0_1_OBUF (
    .I(GP_Motor0_1_OBUF_2059),
    .O(GP_Motor0_1)
  );
  OBUF   TmpEn_OBUF (
    .I(TmpEn_OBUF_2224),
    .O(TmpEn)
  );
  OBUF   PAL0_OBUF (
    .I(PAL0_OBUF_2162),
    .O(PAL0)
  );
  OBUF   PAL1_OBUF (
    .I(PAL1_OBUF_2164),
    .O(PAL1)
  );
  OBUF   PBH0_OBUF (
    .I(PBH0_OBUF_2166),
    .O(PBH0)
  );
  OBUF   PBH1_OBUF (
    .I(PBH1_OBUF_2168),
    .O(PBH1)
  );
  OBUF   PresEn_OBUF (
    .I(PresEn_OBUF_2191),
    .O(PresEn)
  );
  OBUF   GPIO8_OBUF (
    .I(GPIO8_OBUF_2052),
    .O(GPIO8)
  );
  OBUF   GPIO9_OBUF (
    .I(GPIO9_OBUF_2055),
    .O(GPIO9)
  );
  OBUF   GP_Motor1_1_OBUF (
    .I(GP_Motor1_1_OBUF_2063),
    .O(GP_Motor1_1)
  );
  OBUF   PBL0_OBUF (
    .I(PBL0_OBUF_2170),
    .O(PBL0)
  );
  OBUF   PBL1_OBUF (
    .I(PBL1_OBUF_2172),
    .O(PBL1)
  );
  OBUF   GPIO10_OBUF (
    .I(GPIO10_OBUF_2050),
    .O(GPIO10)
  );
  OBUF   PresSlct_OBUF (
    .I(PresSlct_OBUF_2193),
    .O(PresSlct)
  );
  OBUF   Home05ctrl_OBUF (
    .I(Home05ctrl_OBUF_2068),
    .O(Home05ctrl)
  );
  OBUF   INT_OBUF (
    .I(INT_OBUF_2089),
    .O(INT)
  );
  OBUF   MTRpwr_OBUF (
    .I(MTRpwr_OBUF_2117),
    .O(MTRpwr)
  );
  XOR2   \U11_U3_Maddsub_counterr_share0000_Mxor_Result<1>_Mxor__xor0000/Xo<0>1  (
    .I0(U11_U3_counterr[1]),
    .I1(U11_U3_Maddsub_counterr_share0000__or0000),
    .O(\U11_U3_Maddsub_counterr_share0000_Mxor_Result<1>__xor0000 )
  );
  XOR2   \U11_U3_Maddsub_counterr_share0000_Mxor_Result<1>_Mxor_Result/Xo<0>1  (
    .I0(\U11_U3_Maddsub_counterr_share0000_Mxor_Result<1>__xor0000 ),
    .I1(\U11_U3_Maddsub_counterr_share0000_Mxor_Result<5>__xor0001 ),
    .O(U11_U3_counterr_share0000[1])
  );
  XOR2   \U11_U3_Maddsub_counterr_share0000_Mxor_Result<2>_Mxor__xor0000/Xo<0>1  (
    .I0(U11_U3_counterr[2]),
    .I1(U11_U3_Maddsub_counterr_share0000__or0001),
    .O(\U11_U3_Maddsub_counterr_share0000_Mxor_Result<2>__xor0000 )
  );
  XOR2   \U11_U3_Maddsub_counterr_share0000_Mxor_Result<2>_Mxor_Result/Xo<0>1  (
    .I0(\U11_U3_Maddsub_counterr_share0000_Mxor_Result<2>__xor0000 ),
    .I1(\U11_U3_Maddsub_counterr_share0000_Mxor_Result<5>__xor0001 ),
    .O(U11_U3_counterr_share0000[2])
  );
  XOR2   \U11_U3_Maddsub_counterr_share0000_Mxor_Result<3>_Mxor__xor0000/Xo<0>1  (
    .I0(U11_U3_counterr[3]),
    .I1(U11_U3_Maddsub_counterr_share0000__or0002),
    .O(\U11_U3_Maddsub_counterr_share0000_Mxor_Result<3>__xor0000 )
  );
  XOR2   \U11_U3_Maddsub_counterr_share0000_Mxor_Result<3>_Mxor_Result/Xo<0>1  (
    .I0(\U11_U3_Maddsub_counterr_share0000_Mxor_Result<3>__xor0000 ),
    .I1(U11_U3_Maddsub_counterr_share0000_or0003_xor0000),
    .O(U11_U3_counterr_share0000[3])
  );
  XOR2   \U11_U3_Maddsub_counterr_share0000_Mxor_Result<4>_Mxor__xor0000/Xo<0>1  (
    .I0(U11_U3_counterr[4]),
    .I1(U11_U3_Maddsub_counterr_share0000__or0003),
    .O(\U11_U3_Maddsub_counterr_share0000_Mxor_Result<4>__xor0000 )
  );
  XOR2   \U11_U3_Maddsub_counterr_share0000_Mxor_Result<4>_Mxor_Result/Xo<0>1  (
    .I0(\U11_U3_Maddsub_counterr_share0000_Mxor_Result<4>__xor0000 ),
    .I1(\U11_U3_Maddsub_counterr_share0000_Mxor_Result<5>__xor0001 ),
    .O(U11_U3_counterr_share0000[4])
  );
  XOR2   \U11_U3_Maddsub_counterr_share0000_Mxor_Result<5>_Mxor__xor0000/Xo<0>1  (
    .I0(U11_U3_counterr[5]),
    .I1(U11_U3_Maddsub_counterr_share0000__or0004),
    .O(\U11_U3_Maddsub_counterr_share0000_Mxor_Result<5>__xor0000 )
  );
  XOR2   \U11_U3_Maddsub_counterr_share0000_Mxor_Result<5>_Mxor_Result/Xo<0>1  (
    .I0(\U11_U3_Maddsub_counterr_share0000_Mxor_Result<5>__xor0001 ),
    .I1(\U11_U3_Maddsub_counterr_share0000_Mxor_Result<5>__xor0000 ),
    .O(U11_U3_counterr_share0000[5])
  );
  XOR2   \U11_U3_Maddsub_counterr_share0000_Mxor_or0003_xor0000/Xo<0>1  (
    .I0(\U11_U3_Maddsub_counterr_share0000_Mxor_Result<5>__xor0001 ),
    .I1(\U11_U3_counterr_mux0001[2] ),
    .O(U11_U3_Maddsub_counterr_share0000_or0003_xor0000)
  );
  XOR2   \U11_U3_Maddsub_counterr_share0000_Mxor_or0000_xor0000/Xo<0>1  (
    .I0(\U11_U3_Maddsub_counterr_share0000_Mxor_Result<5>__xor0001 ),
    .I1(\U11_U3_counterr_mux0001[5] ),
    .O(U11_U3_Maddsub_counterr_share0000_or0000_xor0000)
  );
  XOR2   \U11_U3_Maddsub_counterr_share0000_Mxor_Result<0>/Xo<0>1  (
    .I0(U11_U3_counterr[0]),
    .I1(\U11_U3_counterr_mux0001[5] ),
    .O(U11_U3_counterr_share0000[0])
  );
  XOR2   \U2_Madd_ADDR_reg_addsub0000_Mxor_Result<1>/Xo<0>1  (
    .I0(U2_ADDR_reg[0]),
    .I1(U2_ADDR_reg[1]),
    .O(U2_ADDR_reg_addsub0000[1])
  );
  XOR2   \U2_Madd_ADDR_reg_addsub0000_Mxor_Result<2>/Xo<0>1  (
    .I0(U2_Madd_ADDR_reg_addsub0000__and0000),
    .I1(U2_ADDR_reg[2]),
    .O(U2_ADDR_reg_addsub0000[2])
  );
  XOR2   \U2_Madd_ADDR_reg_addsub0000_Mxor_Result<3>/Xo<0>1  (
    .I0(U2_Madd_ADDR_reg_addsub0000__and0001),
    .I1(U2_ADDR_reg[3]),
    .O(U2_ADDR_reg_addsub0000[3])
  );
  XOR2   \U2_Madd_ADDR_reg_addsub0000_Mxor_Result<4>/Xo<0>1  (
    .I0(U2_Madd_ADDR_reg_addsub0000__and0002),
    .I1(U2_ADDR_reg[4]),
    .O(U2_ADDR_reg_addsub0000[4])
  );
  XOR2   \U2_Madd_ADDR_reg_addsub0000_Mxor_Result<5>/Xo<0>1  (
    .I0(U2_Madd_ADDR_reg_addsub0000__and0003),
    .I1(U2_ADDR_reg[5]),
    .O(U2_ADDR_reg_addsub0000[5])
  );
  XOR2   \U2_Madd_ADDR_reg_addsub0000_Mxor_Result<6>/Xo<0>1  (
    .I0(U2_Madd_ADDR_reg_addsub0000__and0004),
    .I1(U2_ADDR_reg[6]),
    .O(U2_ADDR_reg_addsub0000[6])
  );
  XOR2   \U2_Madd_ADDR_reg_addsub0000_Mxor_Result<7>/Xo<0>1  (
    .I0(U2_Madd_ADDR_reg_addsub0000__and0005),
    .I1(U2_ADDR_reg[7]),
    .O(U2_ADDR_reg_addsub0000[7])
  );
endmodule


`timescale  1 ps / 1 ps

module glbl ();

    parameter ROC_WIDTH = 100000;
    parameter TOC_WIDTH = 0;

    wire GSR;
    wire GTS;
    wire PRLD;

    reg GSR_int;
    reg GTS_int;
    reg PRLD_int;

//--------   JTAG Globals --------------
    wire JTAG_TDO_GLBL;
    wire JTAG_TCK_GLBL;
    wire JTAG_TDI_GLBL;
    wire JTAG_TMS_GLBL;
    wire JTAG_TRST_GLBL;

    reg JTAG_CAPTURE_GLBL;
    reg JTAG_RESET_GLBL;
    reg JTAG_SHIFT_GLBL;
    reg JTAG_UPDATE_GLBL;

    reg JTAG_SEL1_GLBL = 0;
    reg JTAG_SEL2_GLBL = 0 ;
    reg JTAG_SEL3_GLBL = 0;
    reg JTAG_SEL4_GLBL = 0;

    reg JTAG_USER_TDO1_GLBL = 1'bz;
    reg JTAG_USER_TDO2_GLBL = 1'bz;
    reg JTAG_USER_TDO3_GLBL = 1'bz;
    reg JTAG_USER_TDO4_GLBL = 1'bz;

    assign (weak1, weak0) GSR = GSR_int;
    assign (weak1, weak0) GTS = GTS_int;
    assign (weak1, weak0) PRLD = PRLD_int;

    initial begin
	GSR_int = 1'b1;
	PRLD_int = 1'b1;
	#(ROC_WIDTH)
	GSR_int = 1'b0;
	PRLD_int = 1'b0;
    end

    initial begin
	GTS_int = 1'b1;
	#(TOC_WIDTH)
	GTS_int = 1'b0;
    end

endmodule