dpress.rptC:/Xilinx/10.1/ISE/xpla3/data/xcr3384xl.chpdpress.mfdINFO:Cpld - Inferring BUFG constraint for signal 'baclk_ipad' based upon the LOC constraint 'P128'. It is recommended that you declare this BUFG explicitedly in your design. Note that for certain device families the output of a BUFG constraint can not drive a gated clock, and the BUFG constraint will be ignored.INFO:Cpld - Inferring BUFG constraint for signal 'bsmclk_ipad' based upon the LOC constraint 'P127'. It is recommended that you declare this BUFG explicitedly in your design. Note that for certain device families the output of a BUFG constraint can not drive a gated clock, and the BUFG constraint will be ignored.Cpld - Unable to map all desired signals into function block, FB18. Buffering output signal ad_iopad<5> to allow all signals assigned to this function block to be placed.