`timescale 1ps / 1ps
module debouncer_tb;

//Internal signals declarations:

// wire smclk;	

wire aclk; 
reg  reset;
reg  raw;
wire clean;
wire negated;
wire asserted;

oscillator #(.HALF_PERIOD(15258)) fast_clock (
	.clock_o(aclk)
);

task power_on_reset;
	begin	  
		@(posedge aclk);
	  	@(posedge aclk);
	  	@(posedge aclk);
	  	reset <= 1'b1;
	  	@(posedge aclk);
	  	@(posedge aclk);
	  	@(posedge aclk);
	  	reset <= 1'b0;
	end
endtask

task execute;
	integer i;
begin
	@(posedge aclk);
	raw <= 1'b1;
	@(posedge aclk);
	raw <= 1'b0;
	@(posedge aclk);
	raw <= 1'b1;
	for (i = 0; i < 10; i = i + 1)
		@(posedge aclk);
	raw <= 1'b0;
	for (i = 0; i < 10; i = i + 1)
		@(posedge aclk);
end	
endtask

initial begin 
	reset <= 1'b0;
	raw <= 1'b0;
	power_on_reset;
	execute;
	$finish;
end

endmodule