[SETTINGS]
UUT_module%debouncer%
TB_module%debouncer_tb%
DSN_PATH%$DSN\src\TestBench%
OUTPUT_DIRECTORY%E:\ESP\dwarf_fpgas\dpress\src\TestBench%
STIMULUS%NO%
VECTORS_FILE%%
AWF_FILE%%
TB_FILE%debouncer_TB.v%
MACRO_FILE%debouncer_TB_runtest.do%
UUT_module_FILE%dpress/src/debouncer.v%
LIBRARY_NAME%dpress%
LIBRARY_TYPE%work%
TestBench_TYPE%simple%
ENABLE_FILE%none%
RESULT_FILE%none%

[GENERICS]

[PORTS]
clock_i%in%wire%NO%NOCLK%
raw_i%in%wire%NO%NOCLK%
clean_o%out%reg%NO%NOCLK%
up_o%out%wire%NO%NOCLK%
down_o%out%wire%NO%NOCLK%

[SDF]

[INCLUDE]
[Verilog_FILES]
$DSN\src\debouncer.v