`timescale 1 ns / 1 ns

module reset_synchronizer (
	input		clock_i,
	input		async_reset_i,
	output reg	sync_reset_o
);

reg		reset_delayed;

always @(negedge clock_i or negedge async_reset_i)
	if (!async_reset_i)	{sync_reset_o, reset_delayed} <= 2'b11;
	else    	 		{sync_reset_o, reset_delayed} <= {reset_delayed, 1'b0};
		
endmodule