`timescale 1 ns / 1 ns

module resynchronizer_h ( 
	input 		clock_i,
	input 		reset_i,
	input 		raw_i,
	output reg	clean_o
);

reg	delayed; 

always @(negedge clock_i or posedge reset_i)
	if (reset_i)	{clean_o, delayed} <= 2'b11;
	else    	 	{clean_o, delayed} <= {delayed, raw_i};	 
		
endmodule