module timer (
	input		clock_i, 
	input		reset_i,
	output		tick_o	  	
);

reg [15:0] debounce_timer;

always @(posedge clock_i)
	if (reset_i) debounce_timer <= 0;
	else debounce_timer <= debounce_timer + 1; 
		
assign tick_o = &debounce_timer;

endmodule