`timescale 1 ns / 1 ns

module warning_logic #(	
	// Switch Encoding
	parameter OPEN				= 1'b0,
	parameter CLOSED			= 1'b1,
	// Warning Encoding
	parameter NO_FAULT			= 2'b00,
	parameter DISCONNECTED		= 2'b01,
	parameter SHORTED			= 2'b10,
	parameter BAD_COMPARATOR	= 2'b11
)(	
	input		aclk_i,
	input		smclk_i,
	input		reset_wrt_smclk_i,
	input		reset_wrt_aclk_i,
	   
	// Pressure switch inputs
	input		raw_comparator_1_i,
	input		raw_comparator_2_i,
	input		raw_comparator_3_i,	   
	
	output[1:0] status_o,
	output 		warning_o,
	output		position_o
);

wire	debounced_comparator_1;
wire	debounced_comparator_2;
wire	debounced_comparator_3;		

// Synchronize the asychronous comparator inputs to the 
// ACLK clock domain, ACLK runs continuously at 4 KHz

resynchronizer	local_1 (
	.clock_i(aclk_i), 
	.reset_i(reset_wrt_aclk_i),
	.raw_i(raw_comparator_1_i),
	.clean_o(debounced_comparator_1)			  	
);		

resynchronizer	local_2 (
	.clock_i(aclk_i), 
	.reset_i(reset_wrt_aclk_i),
	.raw_i(raw_comparator_2_i),
	.clean_o(debounced_comparator_2)			  	
); 

resynchronizer_h	local_3 (
	.clock_i(aclk_i), 
	.reset_i(reset_wrt_aclk_i),
	.raw_i(raw_comparator_3_i),
	.clean_o(debounced_comparator_3)	  	
);

reg[1:0]	status; 
reg			warning; 
reg			position;  		  

always @* 	
	case ({debounced_comparator_1, debounced_comparator_2, debounced_comparator_3})
		3'b000	:	{status, warning, position} <= { DISCONNECTED,		1'b1, 1'b0};
		3'b001	:	{status, warning, position} <= { NO_FAULT,			1'b0, OPEN};  
		3'b011	:	{status, warning, position} <= { NO_FAULT,			1'b0, CLOSED};
		3'b111	:	{status, warning, position} <= { SHORTED,			1'b1, 1'b0};
		default	:	{status, warning, position} <= { BAD_COMPARATOR,	1'b1, 1'b0};
	endcase	  

// Synchronize the switch info to the SMCLK clock domain
// SMCLK runs only when the MSP430 accesses tbe core, rvalve or dpress CPLDs
// SMCLK runs at 4 MHz
resynchronizer	rs_warning (
	.clock_i(smclk_i), 
	.reset_i(reset_wrt_smclk_i),
	.raw_i(warning),
	.clean_o(warning_o)	  	
);	 

resynchronizer	rs_position (
	.clock_i(smclk_i), 
	.reset_i(reset_wrt_smclk_i),
	.raw_i(position),
	.clean_o(position_o)	  	
);

resynchronizer	rs_status_1 (
	.clock_i(smclk_i), 
	.reset_i(reset_wrt_smclk_i),
	.raw_i(status[1]),
	.clean_o(status_o[1])	  	
);

resynchronizer	rs_status_0 (
	.clock_i(smclk_i), 
	.reset_i(reset_wrt_smclk_i),
	.raw_i(status[0]),
	.clean_o(status_o[0])	  	
);
 	
endmodule