//////////////////////////////////////////////////////////////////////////////// // Copyright (c) 1995-2008 Xilinx, Inc. All rights reserved. //////////////////////////////////////////////////////////////////////////////// // ____ ____ // / /\/ / // /___/ \ / Vendor: Xilinx // \ \ \/ Version: K.39 // \ \ Application: netgen // / / Filename: dpress.v // /___/ /\ Timestamp: Fri Apr 17 16:18:59 2009 // \ \ / \ // \___\/\___\ // // Command : -ofmt verilog -intstyle silent -w dpress.ngc dpress.v // Device : xcr3384xlTQ144-7 // Input file : dpress.ngc // Output file : dpress.v // # of Modules : 33 // Design Name : dpress // Xilinx : C:\Xilinx\10.1\ISE // // Purpose: // This verilog netlist is a verification model and uses simulation // primitives which may not represent the true implementation of the // device, however the netlist is functionally correct and should not // be modified. This file cannot be synthesized and should only be used // with supported simulation tools. // // Reference: // Development System Reference Guide, Chapter 23 and Synthesis and Simulation Design Guide, Chapter 6 // //////////////////////////////////////////////////////////////////////////////// `timescale 1 ns/1 ps module cpu_interface ( reset_i, water_faults_o, home_configuration_o, motors_disabled_o, water_alarm_enable_o, rd_n_i, pressure_sensor_enable_o, remote_squeeze_i, clock_i , resample_o, remote_burst_i, wr_n_i, as_n_i, drive_bus_o, remote_empty_i, pressure_sensor_select_o, outgoing_data_o, faults_o, emptys_i, faults_i, bursts_i, switches_i, incoming_data_i, squeezes_i, warnings_i ); input reset_i; output water_faults_o; output home_configuration_o; output motors_disabled_o; output water_alarm_enable_o; input rd_n_i; output pressure_sensor_enable_o; input remote_squeeze_i; input clock_i; output resample_o; input remote_burst_i; input wr_n_i; input as_n_i; output drive_bus_o; input remote_empty_i; output pressure_sensor_select_o; output [7 : 0] outgoing_data_o; output [7 : 0] faults_o; input [2 : 0] emptys_i; input [7 : 0] faults_i; input [2 : 0] bursts_i; input [5 : 0] switches_i; input [7 : 0] incoming_data_i; input [2 : 0] squeezes_i; input [2 : 0] warnings_i; wire address_register_0_N0; wire address_register_Madd__add0000__and0000; wire address_register_Madd__add0000__and0001; wire address_register_Madd__add0000__and0002; wire address_register_Madd__add0000__and0003; wire address_register_Madd__add0000__and0004; wire address_register_Madd__add0000__and0005; wire \address_register_Q_mux0000<0>1_310 ; wire \address_register_Q_mux0000<0>2_311 ; wire \address_register_Q_mux0000<0>3_312 ; wire \address_register_Q_mux0000<0>4_313 ; wire \address_register_Q_mux0000<1>1_315 ; wire \address_register_Q_mux0000<1>2_316 ; wire \address_register_Q_mux0000<1>3_317 ; wire \address_register_Q_mux0000<2>1_319 ; wire \address_register_Q_mux0000<2>2_320 ; wire \address_register_Q_mux0000<2>3_321 ; wire \address_register_Q_mux0000<3>1_323 ; wire \address_register_Q_mux0000<3>2_324 ; wire \address_register_Q_mux0000<3>3_325 ; wire \address_register_Q_mux0000<4>1_327 ; wire \address_register_Q_mux0000<4>2_328 ; wire \address_register_Q_mux0000<4>3_329 ; wire \address_register_Q_mux0000<5>1_331 ; wire \address_register_Q_mux0000<5>2_332 ; wire \address_register_Q_mux0000<5>3_333 ; wire \address_register_Q_mux0000<6>1_335 ; wire \address_register_Q_mux0000<6>2_336 ; wire \address_register_Q_mux0000<6>3_337 ; wire \address_register_Q_mux0000<7>1_339 ; wire \address_register_Q_mux0000<7>2_340 ; wire \address_register_Q_mux0000<7>3_341 ; wire address_register_and0000; wire address_register_and00001_350; wire address_register_and0001; wire address_register_and00011_352; wire address_register_and00012_353; wire address_register_and0002; wire address_register_and00021_355; wire address_register_and00022_356; wire address_register_and0003; wire address_register_and00031_358; wire address_register_and00032_359; wire address_register_and00033_360; wire address_register_not0001; wire command_register_and0000; wire command_register_and00001_368; wire command_register_and00002_369; wire command_register_and00003_370; wire command_register_and00004_371; wire command_register_and00005_372; wire command_register_and00006_373; wire command_register_and00007_374; wire command_register_and00008_375; wire command_register_and00009_376; wire diagnostic_register_and0000; wire diagnostic_register_and00001_386; wire diagnostic_register_and000010_387; wire diagnostic_register_and000011_388; wire diagnostic_register_and000012_389; wire diagnostic_register_and000013_390; wire diagnostic_register_and00002_391; wire diagnostic_register_and00003_392; wire diagnostic_register_and00004_393; wire diagnostic_register_and00005_394; wire diagnostic_register_and00006_395; wire diagnostic_register_and00007_396; wire diagnostic_register_and00008_397; wire diagnostic_register_and00009_398; wire drive_bus_o1_400; wire drive_bus_o10_401; wire drive_bus_o11_402; wire drive_bus_o12_403; wire drive_bus_o13_404; wire drive_bus_o2_405; wire drive_bus_o3_406; wire drive_bus_o4_407; wire drive_bus_o5_408; wire drive_bus_o6_409; wire drive_bus_o7_410; wire drive_bus_o8_411; wire drive_bus_o9_412; wire faults_0_and0001; wire faults_0_and00011_417; wire faults_0_and000110_418; wire faults_0_and00012_419; wire faults_0_and00013_420; wire faults_0_and00014_421; wire faults_0_and00015_422; wire faults_0_and00016_423; wire faults_0_and00017_424; wire faults_0_and00018_425; wire faults_0_and00019_426; wire faults_0_mux0000; wire faults_0_not0001; wire faults_0_not00011_429; wire faults_0_not00012_430; wire faults_1_and0001; wire faults_1_and00011_432; wire faults_1_and000110_433; wire faults_1_and00012_434; wire faults_1_and00013_435; wire faults_1_and00014_436; wire faults_1_and00015_437; wire faults_1_and00016_438; wire faults_1_and00017_439; wire faults_1_and00018_440; wire faults_1_and00019_441; wire faults_1_mux0000; wire faults_1_not0001; wire faults_1_not00011_444; wire faults_1_not00012_445; wire faults_2_and0001; wire faults_2_and00011_447; wire faults_2_and000110_448; wire faults_2_and00012_449; wire faults_2_and00013_450; wire faults_2_and00014_451; wire faults_2_and00015_452; wire faults_2_and00016_453; wire faults_2_and00017_454; wire faults_2_and00018_455; wire faults_2_and00019_456; wire faults_2_mux0000; wire faults_2_not0001; wire faults_2_not00011_459; wire faults_2_not00012_460; wire faults_3_and0001; wire faults_3_and00011_462; wire faults_3_and000110_463; wire faults_3_and00012_464; wire faults_3_and00013_465; wire faults_3_and00014_466; wire faults_3_and00015_467; wire faults_3_and00016_468; wire faults_3_and00017_469; wire faults_3_and00018_470; wire faults_3_and00019_471; wire faults_3_mux0000; wire faults_3_not0001; wire faults_3_not00011_474; wire faults_3_not00012_475; wire faults_4_and0001; wire faults_4_and00011_477; wire faults_4_and000110_478; wire faults_4_and00012_479; wire faults_4_and00013_480; wire faults_4_and00014_481; wire faults_4_and00015_482; wire faults_4_and00016_483; wire faults_4_and00017_484; wire faults_4_and00018_485; wire faults_4_and00019_486; wire faults_4_mux0000; wire faults_4_not0001; wire faults_4_not00011_489; wire faults_4_not00012_490; wire faults_5_and0001; wire faults_5_and00011_492; wire faults_5_and000110_493; wire faults_5_and00012_494; wire faults_5_and00013_495; wire faults_5_and00014_496; wire faults_5_and00015_497; wire faults_5_and00016_498; wire faults_5_and00017_499; wire faults_5_and00018_500; wire faults_5_and00019_501; wire faults_5_mux0000; wire faults_5_not0001; wire faults_5_not00011_504; wire faults_5_not00012_505; wire faults_6_and0001; wire faults_6_and00011_507; wire faults_6_and000110_508; wire faults_6_and00012_509; wire faults_6_and00013_510; wire faults_6_and00014_511; wire faults_6_and00015_512; wire faults_6_and00016_513; wire faults_6_and00017_514; wire faults_6_and00018_515; wire faults_6_and00019_516; wire faults_6_mux0000; wire faults_6_not0001; wire faults_6_not00011_519; wire faults_6_not00012_520; wire faults_7_and0001; wire faults_7_and00011_522; wire faults_7_and000110_523; wire faults_7_and00012_524; wire faults_7_and00013_525; wire faults_7_and00014_526; wire faults_7_and00015_527; wire faults_7_and00016_528; wire faults_7_and00017_529; wire faults_7_and00018_530; wire faults_7_and00019_531; wire faults_7_mux0000; wire faults_7_not0001; wire faults_7_not00011_534; wire faults_7_not00012_535; wire NlwRenamedSig_OI_motors_disabled_o; wire \outgoing_data_o<0>1_563 ; wire \outgoing_data_o<0>10_564 ; wire \outgoing_data_o<0>11_565 ; wire \outgoing_data_o<0>12_566 ; wire \outgoing_data_o<0>13_567 ; wire \outgoing_data_o<0>14_568 ; wire \outgoing_data_o<0>15_569 ; wire \outgoing_data_o<0>16_570 ; wire \outgoing_data_o<0>17_571 ; wire \outgoing_data_o<0>18_572 ; wire \outgoing_data_o<0>19_573 ; wire \outgoing_data_o<0>2_574 ; wire \outgoing_data_o<0>20_575 ; wire \outgoing_data_o<0>21_576 ; wire \outgoing_data_o<0>22_577 ; wire \outgoing_data_o<0>23_578 ; wire \outgoing_data_o<0>24_579 ; wire \outgoing_data_o<0>25_580 ; wire \outgoing_data_o<0>26_581 ; wire \outgoing_data_o<0>27_582 ; wire \outgoing_data_o<0>28_583 ; wire \outgoing_data_o<0>29_584 ; wire \outgoing_data_o<0>3_585 ; wire \outgoing_data_o<0>30_586 ; wire \outgoing_data_o<0>31_587 ; wire \outgoing_data_o<0>32_588 ; wire \outgoing_data_o<0>4_589 ; wire \outgoing_data_o<0>5_590 ; wire \outgoing_data_o<0>6_591 ; wire \outgoing_data_o<0>7_592 ; wire \outgoing_data_o<0>8_593 ; wire \outgoing_data_o<0>9_594 ; wire \outgoing_data_o<1>1_596 ; wire \outgoing_data_o<1>10_597 ; wire \outgoing_data_o<1>11_598 ; wire \outgoing_data_o<1>12_599 ; wire \outgoing_data_o<1>13_600 ; wire \outgoing_data_o<1>14_601 ; wire \outgoing_data_o<1>15_602 ; wire \outgoing_data_o<1>16_603 ; wire \outgoing_data_o<1>17_604 ; wire \outgoing_data_o<1>18_605 ; wire \outgoing_data_o<1>19_606 ; wire \outgoing_data_o<1>2_607 ; wire \outgoing_data_o<1>20_608 ; wire \outgoing_data_o<1>21_609 ; wire \outgoing_data_o<1>22_610 ; wire \outgoing_data_o<1>23_611 ; wire \outgoing_data_o<1>24_612 ; wire \outgoing_data_o<1>25_613 ; wire \outgoing_data_o<1>26_614 ; wire \outgoing_data_o<1>27_615 ; wire \outgoing_data_o<1>28_616 ; wire \outgoing_data_o<1>29_617 ; wire \outgoing_data_o<1>3_618 ; wire \outgoing_data_o<1>30_619 ; wire \outgoing_data_o<1>31_620 ; wire \outgoing_data_o<1>32_621 ; wire \outgoing_data_o<1>4_622 ; wire \outgoing_data_o<1>5_623 ; wire \outgoing_data_o<1>6_624 ; wire \outgoing_data_o<1>7_625 ; wire \outgoing_data_o<1>8_626 ; wire \outgoing_data_o<1>9_627 ; wire \outgoing_data_o<2>1_629 ; wire \outgoing_data_o<2>10_630 ; wire \outgoing_data_o<2>11_631 ; wire \outgoing_data_o<2>12_632 ; wire \outgoing_data_o<2>13_633 ; wire \outgoing_data_o<2>14_634 ; wire \outgoing_data_o<2>15_635 ; wire \outgoing_data_o<2>16_636 ; wire \outgoing_data_o<2>17_637 ; wire \outgoing_data_o<2>18_638 ; wire \outgoing_data_o<2>19_639 ; wire \outgoing_data_o<2>2_640 ; wire \outgoing_data_o<2>20_641 ; wire \outgoing_data_o<2>21_642 ; wire \outgoing_data_o<2>22_643 ; wire \outgoing_data_o<2>23_644 ; wire \outgoing_data_o<2>24_645 ; wire \outgoing_data_o<2>25_646 ; wire \outgoing_data_o<2>26_647 ; wire \outgoing_data_o<2>27_648 ; wire \outgoing_data_o<2>28_649 ; wire \outgoing_data_o<2>29_650 ; wire \outgoing_data_o<2>3_651 ; wire \outgoing_data_o<2>30_652 ; wire \outgoing_data_o<2>31_653 ; wire \outgoing_data_o<2>32_654 ; wire \outgoing_data_o<2>4_655 ; wire \outgoing_data_o<2>5_656 ; wire \outgoing_data_o<2>6_657 ; wire \outgoing_data_o<2>7_658 ; wire \outgoing_data_o<2>8_659 ; wire \outgoing_data_o<2>9_660 ; wire \outgoing_data_o<3>1_662 ; wire \outgoing_data_o<3>10_663 ; wire \outgoing_data_o<3>11_664 ; wire \outgoing_data_o<3>12_665 ; wire \outgoing_data_o<3>13_666 ; wire \outgoing_data_o<3>14_667 ; wire \outgoing_data_o<3>15_668 ; wire \outgoing_data_o<3>16_669 ; wire \outgoing_data_o<3>17_670 ; wire \outgoing_data_o<3>18_671 ; wire \outgoing_data_o<3>19_672 ; wire \outgoing_data_o<3>2_673 ; wire \outgoing_data_o<3>20_674 ; wire \outgoing_data_o<3>3_675 ; wire \outgoing_data_o<3>4_676 ; wire \outgoing_data_o<3>5_677 ; wire \outgoing_data_o<3>6_678 ; wire \outgoing_data_o<3>7_679 ; wire \outgoing_data_o<3>8_680 ; wire \outgoing_data_o<3>9_681 ; wire \outgoing_data_o<4>1_683 ; wire \outgoing_data_o<4>10_684 ; wire \outgoing_data_o<4>11_685 ; wire \outgoing_data_o<4>12_686 ; wire \outgoing_data_o<4>13_687 ; wire \outgoing_data_o<4>14_688 ; wire \outgoing_data_o<4>15_689 ; wire \outgoing_data_o<4>16_690 ; wire \outgoing_data_o<4>17_691 ; wire \outgoing_data_o<4>18_692 ; wire \outgoing_data_o<4>19_693 ; wire \outgoing_data_o<4>2_694 ; wire \outgoing_data_o<4>20_695 ; wire \outgoing_data_o<4>21_696 ; wire \outgoing_data_o<4>22_697 ; wire \outgoing_data_o<4>23_698 ; wire \outgoing_data_o<4>24_699 ; wire \outgoing_data_o<4>25_700 ; wire \outgoing_data_o<4>26_701 ; wire \outgoing_data_o<4>27_702 ; wire \outgoing_data_o<4>28_703 ; wire \outgoing_data_o<4>29_704 ; wire \outgoing_data_o<4>3_705 ; wire \outgoing_data_o<4>4_706 ; wire \outgoing_data_o<4>5_707 ; wire \outgoing_data_o<4>6_708 ; wire \outgoing_data_o<4>7_709 ; wire \outgoing_data_o<4>8_710 ; wire \outgoing_data_o<4>9_711 ; wire \outgoing_data_o<5>1_713 ; wire \outgoing_data_o<5>10_714 ; wire \outgoing_data_o<5>11_715 ; wire \outgoing_data_o<5>12_716 ; wire \outgoing_data_o<5>13_717 ; wire \outgoing_data_o<5>14_718 ; wire \outgoing_data_o<5>15_719 ; wire \outgoing_data_o<5>16_720 ; wire \outgoing_data_o<5>17_721 ; wire \outgoing_data_o<5>18_722 ; wire \outgoing_data_o<5>19_723 ; wire \outgoing_data_o<5>2_724 ; wire \outgoing_data_o<5>20_725 ; wire \outgoing_data_o<5>21_726 ; wire \outgoing_data_o<5>22_727 ; wire \outgoing_data_o<5>23_728 ; wire \outgoing_data_o<5>24_729 ; wire \outgoing_data_o<5>25_730 ; wire \outgoing_data_o<5>26_731 ; wire \outgoing_data_o<5>27_732 ; wire \outgoing_data_o<5>28_733 ; wire \outgoing_data_o<5>29_734 ; wire \outgoing_data_o<5>3_735 ; wire \outgoing_data_o<5>4_736 ; wire \outgoing_data_o<5>5_737 ; wire \outgoing_data_o<5>6_738 ; wire \outgoing_data_o<5>7_739 ; wire \outgoing_data_o<5>8_740 ; wire \outgoing_data_o<5>9_741 ; wire \outgoing_data_o<6>1_743 ; wire \outgoing_data_o<6>10_744 ; wire \outgoing_data_o<6>11_745 ; wire \outgoing_data_o<6>12_746 ; wire \outgoing_data_o<6>13_747 ; wire \outgoing_data_o<6>14_748 ; wire \outgoing_data_o<6>15_749 ; wire \outgoing_data_o<6>16_750 ; wire \outgoing_data_o<6>17_751 ; wire \outgoing_data_o<6>18_752 ; wire \outgoing_data_o<6>19_753 ; wire \outgoing_data_o<6>2_754 ; wire \outgoing_data_o<6>20_755 ; wire \outgoing_data_o<6>21_756 ; wire \outgoing_data_o<6>22_757 ; wire \outgoing_data_o<6>23_758 ; wire \outgoing_data_o<6>24_759 ; wire \outgoing_data_o<6>25_760 ; wire \outgoing_data_o<6>26_761 ; wire \outgoing_data_o<6>27_762 ; wire \outgoing_data_o<6>28_763 ; wire \outgoing_data_o<6>29_764 ; wire \outgoing_data_o<6>3_765 ; wire \outgoing_data_o<6>4_766 ; wire \outgoing_data_o<6>5_767 ; wire \outgoing_data_o<6>6_768 ; wire \outgoing_data_o<6>7_769 ; wire \outgoing_data_o<6>8_770 ; wire \outgoing_data_o<6>9_771 ; wire \outgoing_data_o<7>1_773 ; wire \outgoing_data_o<7>10_774 ; wire \outgoing_data_o<7>11_775 ; wire \outgoing_data_o<7>12_776 ; wire \outgoing_data_o<7>13_777 ; wire \outgoing_data_o<7>14_778 ; wire \outgoing_data_o<7>15_779 ; wire \outgoing_data_o<7>16_780 ; wire \outgoing_data_o<7>17_781 ; wire \outgoing_data_o<7>18_782 ; wire \outgoing_data_o<7>19_783 ; wire \outgoing_data_o<7>2_784 ; wire \outgoing_data_o<7>20_785 ; wire \outgoing_data_o<7>21_786 ; wire \outgoing_data_o<7>22_787 ; wire \outgoing_data_o<7>23_788 ; wire \outgoing_data_o<7>3_789 ; wire \outgoing_data_o<7>4_790 ; wire \outgoing_data_o<7>5_791 ; wire \outgoing_data_o<7>6_792 ; wire \outgoing_data_o<7>7_793 ; wire \outgoing_data_o<7>8_794 ; wire \outgoing_data_o<7>9_795 ; wire previous_as_n_798; wire previous_rd_n_799; wire previous_wr_n_800; wire NlwRenamedSig_OI_resample_o; wire warnings_0_and0001; wire warnings_0_and00011_818; wire warnings_0_and000110_819; wire warnings_0_and00012_820; wire warnings_0_and00013_821; wire warnings_0_and00014_822; wire warnings_0_and00015_823; wire warnings_0_and00016_824; wire warnings_0_and00017_825; wire warnings_0_and00018_826; wire warnings_0_and00019_827; wire warnings_0_mux0000; wire warnings_0_not0001; wire warnings_0_not00011_830; wire warnings_0_not00012_831; wire warnings_1_and0001; wire warnings_1_and00011_834; wire warnings_1_and000110_835; wire warnings_1_and00012_836; wire warnings_1_and00013_837; wire warnings_1_and00014_838; wire warnings_1_and00015_839; wire warnings_1_and00016_840; wire warnings_1_and00017_841; wire warnings_1_and00018_842; wire warnings_1_and00019_843; wire warnings_1_mux0000; wire warnings_1_not0001; wire warnings_1_not00011_846; wire warnings_1_not00012_847; wire warnings_2_and0001; wire warnings_2_and00011_850; wire warnings_2_and000110_851; wire warnings_2_and00012_852; wire warnings_2_and00013_853; wire warnings_2_and00014_854; wire warnings_2_and00015_855; wire warnings_2_and00016_856; wire warnings_2_and00017_857; wire warnings_2_and00018_858; wire warnings_2_and00019_859; wire warnings_2_mux0000; wire warnings_2_not0001; wire warnings_2_not00011_862; wire warnings_2_not00012_863; wire warnings_3_and0001; wire warnings_3_and00011_866; wire warnings_3_and000110_867; wire warnings_3_and00012_868; wire warnings_3_and00013_869; wire warnings_3_and00014_870; wire warnings_3_and00015_871; wire warnings_3_and00016_872; wire warnings_3_and00017_873; wire warnings_3_and00018_874; wire warnings_3_and00019_875; wire warnings_3_mux0000; wire warnings_3_not0001; wire warnings_3_not00011_878; wire warnings_3_not00012_879; wire warnings_4_and0001; wire warnings_4_and00011_882; wire warnings_4_and000110_883; wire warnings_4_and00012_884; wire warnings_4_and00013_885; wire warnings_4_and00014_886; wire warnings_4_and00015_887; wire warnings_4_and00016_888; wire warnings_4_and00017_889; wire warnings_4_and00018_890; wire warnings_4_and00019_891; wire warnings_4_mux0000; wire warnings_4_not0001; wire warnings_4_not00011_894; wire warnings_4_not00012_895; wire warnings_5_and0001; wire warnings_5_and00011_898; wire warnings_5_and000110_899; wire warnings_5_and00012_900; wire warnings_5_and00013_901; wire warnings_5_and00014_902; wire warnings_5_and00015_903; wire warnings_5_and00016_904; wire warnings_5_and00017_905; wire warnings_5_and00018_906; wire warnings_5_and00019_907; wire warnings_5_mux0000; wire warnings_5_not0001; wire warnings_5_not00011_910; wire warnings_5_not00012_911; wire [7 : 0] address_register; wire [7 : 0] address_register_Q_mux0000; wire [7 : 1] address_register__add0000; wire [7 : 0] diagnostic_register; wire [7 : 0] NlwRenamedSig_OI_faults_o; wire [5 : 0] warnings; assign motors_disabled_o = NlwRenamedSig_OI_motors_disabled_o, resample_o = NlwRenamedSig_OI_resample_o, faults_o[7] = NlwRenamedSig_OI_faults_o[7], faults_o[6] = NlwRenamedSig_OI_faults_o[6], faults_o[5] = NlwRenamedSig_OI_faults_o[5], faults_o[4] = NlwRenamedSig_OI_faults_o[4], faults_o[3] = NlwRenamedSig_OI_faults_o[3], faults_o[2] = NlwRenamedSig_OI_faults_o[2], faults_o[1] = NlwRenamedSig_OI_faults_o[1], faults_o[0] = NlwRenamedSig_OI_faults_o[0]; FDCE warnings_5 ( .CE(warnings_5_not0001), .CLR(reset_i), .C(address_register_0_N0), .D(warnings_5_mux0000), .Q(warnings[5]) ); FDCE warnings_4 ( .CE(warnings_4_not0001), .CLR(reset_i), .C(address_register_0_N0), .D(warnings_4_mux0000), .Q(warnings[4]) ); FDCE warnings_3 ( .CE(warnings_3_not0001), .CLR(reset_i), .C(address_register_0_N0), .D(warnings_3_mux0000), .Q(warnings[3]) ); FDCE warnings_2 ( .CE(warnings_2_not0001), .CLR(reset_i), .C(address_register_0_N0), .D(warnings_2_mux0000), .Q(warnings[2]) ); FDCE warnings_1 ( .CE(warnings_1_not0001), .CLR(reset_i), .C(address_register_0_N0), .D(warnings_1_mux0000), .Q(warnings[1]) ); FDCE warnings_0 ( .CE(warnings_0_not0001), .CLR(reset_i), .C(address_register_0_N0), .D(warnings_0_mux0000), .Q(warnings[0]) ); FDCE faults_7 ( .CE(faults_7_not0001), .CLR(reset_i), .C(address_register_0_N0), .D(faults_7_mux0000), .Q(NlwRenamedSig_OI_faults_o[7]) ); FDCE faults_6 ( .CE(faults_6_not0001), .CLR(reset_i), .C(address_register_0_N0), .D(faults_6_mux0000), .Q(NlwRenamedSig_OI_faults_o[6]) ); FDCE faults_5 ( .CE(faults_5_not0001), .CLR(reset_i), .C(address_register_0_N0), .D(faults_5_mux0000), .Q(NlwRenamedSig_OI_faults_o[5]) ); FDCE faults_4 ( .CE(faults_4_not0001), .CLR(reset_i), .C(address_register_0_N0), .D(faults_4_mux0000), .Q(NlwRenamedSig_OI_faults_o[4]) ); FDCE faults_3 ( .CE(faults_3_not0001), .CLR(reset_i), .C(address_register_0_N0), .D(faults_3_mux0000), .Q(NlwRenamedSig_OI_faults_o[3]) ); FDCE faults_2 ( .CE(faults_2_not0001), .CLR(reset_i), .C(address_register_0_N0), .D(faults_2_mux0000), .Q(NlwRenamedSig_OI_faults_o[2]) ); FDCE faults_1 ( .CE(faults_1_not0001), .CLR(reset_i), .C(address_register_0_N0), .D(faults_1_mux0000), .Q(NlwRenamedSig_OI_faults_o[1]) ); FDCE faults_0 ( .CE(faults_0_not0001), .CLR(reset_i), .C(address_register_0_N0), .D(faults_0_mux0000), .Q(NlwRenamedSig_OI_faults_o[0]) ); FDP previous_wr_n ( .C(address_register_0_N0), .D(wr_n_i), .PRE(reset_i), .Q(previous_wr_n_800) ); FDP previous_rd_n ( .C(address_register_0_N0), .D(rd_n_i), .PRE(reset_i), .Q(previous_rd_n_799) ); FDP previous_as_n ( .C(address_register_0_N0), .D(as_n_i), .PRE(reset_i), .Q(previous_as_n_798) ); FDPE command_register_5 ( .CE(command_register_and0000), .C(address_register_0_N0), .D(incoming_data_i[7]), .PRE(reset_i), .Q(NlwRenamedSig_OI_motors_disabled_o) ); FDCE command_register_0 ( .CE(command_register_and0000), .CLR(reset_i), .C(address_register_0_N0), .D(incoming_data_i[0]), .Q(pressure_sensor_select_o) ); FDCE command_register_1 ( .CE(command_register_and0000), .CLR(reset_i), .C(address_register_0_N0), .D(incoming_data_i[1]), .Q(pressure_sensor_enable_o) ); FDCE command_register_2 ( .CE(command_register_and0000), .CLR(reset_i), .C(address_register_0_N0), .D(incoming_data_i[2]), .Q(water_alarm_enable_o) ); FDCE command_register_3 ( .CE(command_register_and0000), .CLR(reset_i), .C(address_register_0_N0), .D(incoming_data_i[5]), .Q(home_configuration_o) ); FDCE command_register_4 ( .CE(command_register_and0000), .CLR(reset_i), .C(address_register_0_N0), .D(incoming_data_i[6]), .Q(NlwRenamedSig_OI_resample_o) ); FDCE diagnostic_register_0 ( .CE(diagnostic_register_and0000), .CLR(reset_i), .C(address_register_0_N0), .D(incoming_data_i[0]), .Q(diagnostic_register[0]) ); FDCE diagnostic_register_1 ( .CE(diagnostic_register_and0000), .CLR(reset_i), .C(address_register_0_N0), .D(incoming_data_i[1]), .Q(diagnostic_register[1]) ); FDCE diagnostic_register_2 ( .CE(diagnostic_register_and0000), .CLR(reset_i), .C(address_register_0_N0), .D(incoming_data_i[2]), .Q(diagnostic_register[2]) ); FDCE diagnostic_register_3 ( .CE(diagnostic_register_and0000), .CLR(reset_i), .C(address_register_0_N0), .D(incoming_data_i[3]), .Q(diagnostic_register[3]) ); FDCE diagnostic_register_4 ( .CE(diagnostic_register_and0000), .CLR(reset_i), .C(address_register_0_N0), .D(incoming_data_i[4]), .Q(diagnostic_register[4]) ); FDCE diagnostic_register_5 ( .CE(diagnostic_register_and0000), .CLR(reset_i), .C(address_register_0_N0), .D(incoming_data_i[5]), .Q(diagnostic_register[5]) ); FDCE diagnostic_register_6 ( .CE(diagnostic_register_and0000), .CLR(reset_i), .C(address_register_0_N0), .D(incoming_data_i[6]), .Q(diagnostic_register[6]) ); FDCE diagnostic_register_7 ( .CE(diagnostic_register_and0000), .CLR(reset_i), .C(address_register_0_N0), .D(incoming_data_i[7]), .Q(diagnostic_register[7]) ); FDCE address_register_7 ( .CE(address_register_not0001), .CLR(reset_i), .C(address_register_0_N0), .D(address_register_Q_mux0000[7]), .Q(address_register[7]) ); FDCE address_register_6 ( .CE(address_register_not0001), .CLR(reset_i), .C(address_register_0_N0), .D(address_register_Q_mux0000[6]), .Q(address_register[6]) ); FDCE address_register_5 ( .CE(address_register_not0001), .CLR(reset_i), .C(address_register_0_N0), .D(address_register_Q_mux0000[5]), .Q(address_register[5]) ); FDCE address_register_4 ( .CE(address_register_not0001), .CLR(reset_i), .C(address_register_0_N0), .D(address_register_Q_mux0000[4]), .Q(address_register[4]) ); FDCE address_register_3 ( .CE(address_register_not0001), .CLR(reset_i), .C(address_register_0_N0), .D(address_register_Q_mux0000[3]), .Q(address_register[3]) ); FDCE address_register_2 ( .CE(address_register_not0001), .CLR(reset_i), .C(address_register_0_N0), .D(address_register_Q_mux0000[2]), .Q(address_register[2]) ); FDCE address_register_1 ( .CE(address_register_not0001), .CLR(reset_i), .C(address_register_0_N0), .D(address_register_Q_mux0000[1]), .Q(address_register[1]) ); FDCE address_register_0 ( .CE(address_register_not0001), .CLR(reset_i), .C(address_register_0_N0), .D(address_register_Q_mux0000[0]), .Q(address_register[0]) ); OR2 water_faults_o1 ( .I0(NlwRenamedSig_OI_faults_o[6]), .I1(NlwRenamedSig_OI_faults_o[7]), .O(water_faults_o) ); INV address_register_and00001 ( .I(as_n_i), .O(address_register_and00001_350) ); AND2 address_register_and00002 ( .I0(previous_as_n_798), .I1(address_register_and00001_350), .O(address_register_and0000) ); INV faults_0_mux00001 ( .I(faults_0_and0001), .O(faults_0_mux0000) ); INV faults_1_mux00001 ( .I(faults_1_and0001), .O(faults_1_mux0000) ); INV faults_2_mux00001 ( .I(faults_2_and0001), .O(faults_2_mux0000) ); INV faults_3_mux00001 ( .I(faults_3_and0001), .O(faults_3_mux0000) ); INV faults_4_mux00001 ( .I(faults_4_and0001), .O(faults_4_mux0000) ); INV faults_5_mux00001 ( .I(faults_5_and0001), .O(faults_5_mux0000) ); INV faults_6_mux00001 ( .I(faults_6_and0001), .O(faults_6_mux0000) ); INV faults_7_mux00001 ( .I(faults_7_and0001), .O(faults_7_mux0000) ); INV warnings_0_mux00001 ( .I(warnings_0_and0001), .O(warnings_0_mux0000) ); INV warnings_1_mux00001 ( .I(warnings_1_and0001), .O(warnings_1_mux0000) ); INV warnings_2_mux00001 ( .I(warnings_2_and0001), .O(warnings_2_mux0000) ); INV warnings_3_mux00001 ( .I(warnings_3_and0001), .O(warnings_3_mux0000) ); INV warnings_4_mux00001 ( .I(warnings_4_and0001), .O(warnings_4_mux0000) ); INV warnings_5_mux00001 ( .I(warnings_5_and0001), .O(warnings_5_mux0000) ); INV address_register_not00011 ( .I(address_register_and0003), .O(address_register_not0001) ); INV address_register_0_N01 ( .I(clock_i), .O(address_register_0_N0) ); AND2 address_register_Madd__add0000__and00001 ( .I0(address_register[1]), .I1(address_register[0]), .O(address_register_Madd__add0000__and0000) ); AND2 address_register_Madd__add0000__and00011 ( .I0(address_register[2]), .I1(address_register_Madd__add0000__and0000), .O(address_register_Madd__add0000__and0001) ); AND2 address_register_Madd__add0000__and00021 ( .I0(address_register[3]), .I1(address_register_Madd__add0000__and0001), .O(address_register_Madd__add0000__and0002) ); AND2 address_register_Madd__add0000__and00031 ( .I0(address_register[4]), .I1(address_register_Madd__add0000__and0002), .O(address_register_Madd__add0000__and0003) ); AND2 address_register_Madd__add0000__and00041 ( .I0(address_register[5]), .I1(address_register_Madd__add0000__and0003), .O(address_register_Madd__add0000__and0004) ); AND2 address_register_Madd__add0000__and00051 ( .I0(address_register[6]), .I1(address_register_Madd__add0000__and0004), .O(address_register_Madd__add0000__and0005) ); INV address_register_and00011 ( .I(previous_wr_n_800), .O(address_register_and00011_352) ); INV address_register_and00012 ( .I(previous_as_n_798), .O(address_register_and00012_353) ); AND3 address_register_and00013 ( .I0(address_register_and00011_352), .I1(wr_n_i), .I2(address_register_and00012_353), .O(address_register_and0001) ); INV address_register_and00021 ( .I(previous_rd_n_799), .O(address_register_and00021_355) ); INV address_register_and00022 ( .I(previous_as_n_798), .O(address_register_and00022_356) ); AND3 address_register_and00023 ( .I0(address_register_and00021_355), .I1(rd_n_i), .I2(address_register_and00022_356), .O(address_register_and0002) ); INV address_register_and00031 ( .I(address_register_and0002), .O(address_register_and00031_358) ); INV address_register_and00032 ( .I(address_register_and0001), .O(address_register_and00032_359) ); INV address_register_and00033 ( .I(address_register_and0000), .O(address_register_and00033_360) ); AND3 address_register_and00034 ( .I0(address_register_and00032_359), .I1(address_register_and00031_358), .I2(address_register_and00033_360), .O(address_register_and0003) ); AND2 \address_register_Q_mux0000<0>1 ( .I0(address_register_and0000), .I1(incoming_data_i[0]), .O(\address_register_Q_mux0000<0>1_310 ) ); INV \address_register_Q_mux0000<0>2 ( .I(address_register_and0000), .O(\address_register_Q_mux0000<0>2_311 ) ); INV \address_register_Q_mux0000<0>3 ( .I(address_register[0]), .O(\address_register_Q_mux0000<0>3_312 ) ); AND2 \address_register_Q_mux0000<0>4 ( .I0(\address_register_Q_mux0000<0>2_311 ), .I1(\address_register_Q_mux0000<0>3_312 ), .O(\address_register_Q_mux0000<0>4_313 ) ); OR2 \address_register_Q_mux0000<0>5 ( .I0(\address_register_Q_mux0000<0>1_310 ), .I1(\address_register_Q_mux0000<0>4_313 ), .O(address_register_Q_mux0000[0]) ); AND2 \address_register_Q_mux0000<1>1 ( .I0(address_register_and0000), .I1(incoming_data_i[1]), .O(\address_register_Q_mux0000<1>1_315 ) ); INV \address_register_Q_mux0000<1>2 ( .I(address_register_and0000), .O(\address_register_Q_mux0000<1>2_316 ) ); AND2 \address_register_Q_mux0000<1>3 ( .I0(address_register__add0000[1]), .I1(\address_register_Q_mux0000<1>2_316 ), .O(\address_register_Q_mux0000<1>3_317 ) ); OR2 \address_register_Q_mux0000<1>4 ( .I0(\address_register_Q_mux0000<1>1_315 ), .I1(\address_register_Q_mux0000<1>3_317 ), .O(address_register_Q_mux0000[1]) ); AND2 \address_register_Q_mux0000<2>1 ( .I0(address_register_and0000), .I1(incoming_data_i[2]), .O(\address_register_Q_mux0000<2>1_319 ) ); INV \address_register_Q_mux0000<2>2 ( .I(address_register_and0000), .O(\address_register_Q_mux0000<2>2_320 ) ); AND2 \address_register_Q_mux0000<2>3 ( .I0(address_register__add0000[2]), .I1(\address_register_Q_mux0000<2>2_320 ), .O(\address_register_Q_mux0000<2>3_321 ) ); OR2 \address_register_Q_mux0000<2>4 ( .I0(\address_register_Q_mux0000<2>1_319 ), .I1(\address_register_Q_mux0000<2>3_321 ), .O(address_register_Q_mux0000[2]) ); AND2 \address_register_Q_mux0000<3>1 ( .I0(address_register_and0000), .I1(incoming_data_i[3]), .O(\address_register_Q_mux0000<3>1_323 ) ); INV \address_register_Q_mux0000<3>2 ( .I(address_register_and0000), .O(\address_register_Q_mux0000<3>2_324 ) ); AND2 \address_register_Q_mux0000<3>3 ( .I0(address_register__add0000[3]), .I1(\address_register_Q_mux0000<3>2_324 ), .O(\address_register_Q_mux0000<3>3_325 ) ); OR2 \address_register_Q_mux0000<3>4 ( .I0(\address_register_Q_mux0000<3>1_323 ), .I1(\address_register_Q_mux0000<3>3_325 ), .O(address_register_Q_mux0000[3]) ); AND2 \address_register_Q_mux0000<4>1 ( .I0(address_register_and0000), .I1(incoming_data_i[4]), .O(\address_register_Q_mux0000<4>1_327 ) ); INV \address_register_Q_mux0000<4>2 ( .I(address_register_and0000), .O(\address_register_Q_mux0000<4>2_328 ) ); AND2 \address_register_Q_mux0000<4>3 ( .I0(address_register__add0000[4]), .I1(\address_register_Q_mux0000<4>2_328 ), .O(\address_register_Q_mux0000<4>3_329 ) ); OR2 \address_register_Q_mux0000<4>4 ( .I0(\address_register_Q_mux0000<4>1_327 ), .I1(\address_register_Q_mux0000<4>3_329 ), .O(address_register_Q_mux0000[4]) ); AND2 \address_register_Q_mux0000<5>1 ( .I0(address_register_and0000), .I1(incoming_data_i[5]), .O(\address_register_Q_mux0000<5>1_331 ) ); INV \address_register_Q_mux0000<5>2 ( .I(address_register_and0000), .O(\address_register_Q_mux0000<5>2_332 ) ); AND2 \address_register_Q_mux0000<5>3 ( .I0(address_register__add0000[5]), .I1(\address_register_Q_mux0000<5>2_332 ), .O(\address_register_Q_mux0000<5>3_333 ) ); OR2 \address_register_Q_mux0000<5>4 ( .I0(\address_register_Q_mux0000<5>1_331 ), .I1(\address_register_Q_mux0000<5>3_333 ), .O(address_register_Q_mux0000[5]) ); AND2 \address_register_Q_mux0000<6>1 ( .I0(address_register_and0000), .I1(incoming_data_i[6]), .O(\address_register_Q_mux0000<6>1_335 ) ); INV \address_register_Q_mux0000<6>2 ( .I(address_register_and0000), .O(\address_register_Q_mux0000<6>2_336 ) ); AND2 \address_register_Q_mux0000<6>3 ( .I0(address_register__add0000[6]), .I1(\address_register_Q_mux0000<6>2_336 ), .O(\address_register_Q_mux0000<6>3_337 ) ); OR2 \address_register_Q_mux0000<6>4 ( .I0(\address_register_Q_mux0000<6>1_335 ), .I1(\address_register_Q_mux0000<6>3_337 ), .O(address_register_Q_mux0000[6]) ); AND2 \address_register_Q_mux0000<7>1 ( .I0(address_register_and0000), .I1(incoming_data_i[7]), .O(\address_register_Q_mux0000<7>1_339 ) ); INV \address_register_Q_mux0000<7>2 ( .I(address_register_and0000), .O(\address_register_Q_mux0000<7>2_340 ) ); AND2 \address_register_Q_mux0000<7>3 ( .I0(address_register__add0000[7]), .I1(\address_register_Q_mux0000<7>2_340 ), .O(\address_register_Q_mux0000<7>3_341 ) ); OR2 \address_register_Q_mux0000<7>4 ( .I0(\address_register_Q_mux0000<7>1_339 ), .I1(\address_register_Q_mux0000<7>3_341 ), .O(address_register_Q_mux0000[7]) ); AND2 diagnostic_register_and00001 ( .I0(previous_wr_n_800), .I1(address_register[5]), .O(diagnostic_register_and00001_386) ); INV diagnostic_register_and00002 ( .I(wr_n_i), .O(diagnostic_register_and00002_391) ); INV diagnostic_register_and00003 ( .I(address_register[0]), .O(diagnostic_register_and00003_392) ); INV diagnostic_register_and00004 ( .I(address_register[1]), .O(diagnostic_register_and00004_393) ); INV diagnostic_register_and00005 ( .I(address_register[2]), .O(diagnostic_register_and00005_394) ); INV diagnostic_register_and00006 ( .I(address_register[4]), .O(diagnostic_register_and00006_395) ); INV diagnostic_register_and00007 ( .I(address_register[3]), .O(diagnostic_register_and00007_396) ); INV diagnostic_register_and00008 ( .I(address_register[6]), .O(diagnostic_register_and00008_397) ); INV diagnostic_register_and00009 ( .I(address_register[7]), .O(diagnostic_register_and00009_398) ); AND2 diagnostic_register_and000010 ( .I0(diagnostic_register_and00002_391), .I1(diagnostic_register_and00003_392), .O(diagnostic_register_and000010_387) ); AND4 diagnostic_register_and000011 ( .I0(diagnostic_register_and00004_393), .I1(diagnostic_register_and00005_394), .I2(diagnostic_register_and00006_395), .I3(diagnostic_register_and00007_396), .O(diagnostic_register_and000011_388) ); AND2 diagnostic_register_and000012 ( .I0(diagnostic_register_and00008_397), .I1(diagnostic_register_and00009_398), .O(diagnostic_register_and000012_389) ); AND3 diagnostic_register_and000013 ( .I0(diagnostic_register_and000010_387), .I1(diagnostic_register_and00001_386), .I2(diagnostic_register_and000011_388), .O(diagnostic_register_and000013_390) ); AND2 diagnostic_register_and000014 ( .I0(diagnostic_register_and000013_390), .I1(diagnostic_register_and000012_389), .O(diagnostic_register_and0000) ); AND4 command_register_and00001 ( .I0(previous_wr_n_800), .I1(address_register[2]), .I2(address_register[4]), .I3(address_register[3]), .O(command_register_and00001_368) ); INV command_register_and00002 ( .I(wr_n_i), .O(command_register_and00002_369) ); INV command_register_and00003 ( .I(address_register[0]), .O(command_register_and00003_370) ); INV command_register_and00004 ( .I(address_register[1]), .O(command_register_and00004_371) ); INV command_register_and00005 ( .I(address_register[5]), .O(command_register_and00005_372) ); INV command_register_and00006 ( .I(address_register[6]), .O(command_register_and00006_373) ); INV command_register_and00007 ( .I(address_register[7]), .O(command_register_and00007_374) ); AND4 command_register_and00008 ( .I0(command_register_and00002_369), .I1(command_register_and00003_370), .I2(command_register_and00004_371), .I3(command_register_and00005_372), .O(command_register_and00008_375) ); AND2 command_register_and00009 ( .I0(command_register_and00006_373), .I1(command_register_and00007_374), .O(command_register_and00009_376) ); AND3 command_register_and000010 ( .I0(command_register_and00008_375), .I1(command_register_and00001_368), .I2(command_register_and00009_376), .O(command_register_and0000) ); AND2 \outgoing_data_o<3>1 ( .I0(address_register[3]), .I1(address_register[2]), .O(\outgoing_data_o<3>1_662 ) ); AND2 \outgoing_data_o<3>2 ( .I0(NlwRenamedSig_OI_faults_o[3]), .I1(address_register[0]), .O(\outgoing_data_o<3>2_673 ) ); INV \outgoing_data_o<3>3 ( .I(address_register[1]), .O(\outgoing_data_o<3>3_675 ) ); AND2 \outgoing_data_o<3>4 ( .I0(address_register[1]), .I1(warnings[3]), .O(\outgoing_data_o<3>4_676 ) ); INV \outgoing_data_o<3>5 ( .I(address_register[0]), .O(\outgoing_data_o<3>5_677 ) ); INV \outgoing_data_o<3>6 ( .I(address_register[5]), .O(\outgoing_data_o<3>6_678 ) ); AND2 \outgoing_data_o<3>7 ( .I0(address_register[5]), .I1(diagnostic_register[3]), .O(\outgoing_data_o<3>7_679 ) ); INV \outgoing_data_o<3>8 ( .I(address_register[0]), .O(\outgoing_data_o<3>8_680 ) ); INV \outgoing_data_o<3>9 ( .I(address_register[1]), .O(\outgoing_data_o<3>9_681 ) ); INV \outgoing_data_o<3>10 ( .I(address_register[2]), .O(\outgoing_data_o<3>10_663 ) ); INV \outgoing_data_o<3>11 ( .I(address_register[3]), .O(\outgoing_data_o<3>11_664 ) ); INV \outgoing_data_o<3>12 ( .I(address_register[4]), .O(\outgoing_data_o<3>12_665 ) ); AND2 \outgoing_data_o<3>13 ( .I0(\outgoing_data_o<3>2_673 ), .I1(\outgoing_data_o<3>3_675 ), .O(\outgoing_data_o<3>13_666 ) ); AND2 \outgoing_data_o<3>14 ( .I0(\outgoing_data_o<3>4_676 ), .I1(\outgoing_data_o<3>5_677 ), .O(\outgoing_data_o<3>14_667 ) ); AND2 \outgoing_data_o<3>15 ( .I0(\outgoing_data_o<3>8_680 ), .I1(\outgoing_data_o<3>9_681 ), .O(\outgoing_data_o<3>15_668 ) ); AND3 \outgoing_data_o<3>16 ( .I0(\outgoing_data_o<3>11_664 ), .I1(\outgoing_data_o<3>10_663 ), .I2(\outgoing_data_o<3>12_665 ), .O(\outgoing_data_o<3>16_669 ) ); OR2 \outgoing_data_o<3>17 ( .I0(\outgoing_data_o<3>13_666 ), .I1(\outgoing_data_o<3>14_667 ), .O(\outgoing_data_o<3>17_670 ) ); AND3 \outgoing_data_o<3>18 ( .I0(\outgoing_data_o<3>15_668 ), .I1(\outgoing_data_o<3>7_679 ), .I2(\outgoing_data_o<3>16_669 ), .O(\outgoing_data_o<3>18_671 ) ); AND2 \outgoing_data_o<3>19 ( .I0(address_register[4]), .I1(\outgoing_data_o<3>17_670 ), .O(\outgoing_data_o<3>19_672 ) ); AND3 \outgoing_data_o<3>20 ( .I0(\outgoing_data_o<3>19_672 ), .I1(\outgoing_data_o<3>1_662 ), .I2(\outgoing_data_o<3>6_678 ), .O(\outgoing_data_o<3>20_674 ) ); OR2 \outgoing_data_o<3>21 ( .I0(\outgoing_data_o<3>20_674 ), .I1(\outgoing_data_o<3>18_671 ), .O(outgoing_data_o[3]) ); AND2 \outgoing_data_o<4>1 ( .I0(address_register[3]), .I1(address_register[2]), .O(\outgoing_data_o<4>1_683 ) ); AND2 \outgoing_data_o<4>2 ( .I0(NlwRenamedSig_OI_faults_o[4]), .I1(address_register[0]), .O(\outgoing_data_o<4>2_694 ) ); INV \outgoing_data_o<4>3 ( .I(address_register[1]), .O(\outgoing_data_o<4>3_705 ) ); AND2 \outgoing_data_o<4>4 ( .I0(address_register[1]), .I1(warnings[4]), .O(\outgoing_data_o<4>4_706 ) ); INV \outgoing_data_o<4>5 ( .I(address_register[0]), .O(\outgoing_data_o<4>5_707 ) ); INV \outgoing_data_o<4>6 ( .I(address_register[5]), .O(\outgoing_data_o<4>6_708 ) ); AND2 \outgoing_data_o<4>7 ( .I0(address_register[1]), .I1(switches_i[2]), .O(\outgoing_data_o<4>7_709 ) ); INV \outgoing_data_o<4>8 ( .I(address_register[1]), .O(\outgoing_data_o<4>8_710 ) ); AND2 \outgoing_data_o<4>9 ( .I0(address_register[1]), .I1(switches_i[4]), .O(\outgoing_data_o<4>9_711 ) ); INV \outgoing_data_o<4>10 ( .I(address_register[1]), .O(\outgoing_data_o<4>10_684 ) ); INV \outgoing_data_o<4>11 ( .I(address_register[0]), .O(\outgoing_data_o<4>11_685 ) ); INV \outgoing_data_o<4>12 ( .I(address_register[3]), .O(\outgoing_data_o<4>12_686 ) ); INV \outgoing_data_o<4>13 ( .I(address_register[2]), .O(\outgoing_data_o<4>13_687 ) ); INV \outgoing_data_o<4>14 ( .I(address_register[4]), .O(\outgoing_data_o<4>14_688 ) ); AND2 \outgoing_data_o<4>15 ( .I0(\outgoing_data_o<4>2_694 ), .I1(\outgoing_data_o<4>3_705 ), .O(\outgoing_data_o<4>15_689 ) ); AND2 \outgoing_data_o<4>16 ( .I0(\outgoing_data_o<4>4_706 ), .I1(\outgoing_data_o<4>5_707 ), .O(\outgoing_data_o<4>16_690 ) ); AND2 \outgoing_data_o<4>17 ( .I0(switches_i[0]), .I1(\outgoing_data_o<4>8_710 ), .O(\outgoing_data_o<4>17_691 ) ); AND2 \outgoing_data_o<4>18 ( .I0(diagnostic_register[4]), .I1(\outgoing_data_o<4>10_684 ), .O(\outgoing_data_o<4>18_692 ) ); AND2 \outgoing_data_o<4>19 ( .I0(\outgoing_data_o<4>12_686 ), .I1(\outgoing_data_o<4>13_687 ), .O(\outgoing_data_o<4>19_693 ) ); OR2 \outgoing_data_o<4>20 ( .I0(\outgoing_data_o<4>15_689 ), .I1(\outgoing_data_o<4>16_690 ), .O(\outgoing_data_o<4>20_695 ) ); OR2 \outgoing_data_o<4>21 ( .I0(\outgoing_data_o<4>7_709 ), .I1(\outgoing_data_o<4>17_691 ), .O(\outgoing_data_o<4>21_696 ) ); OR2 \outgoing_data_o<4>22 ( .I0(\outgoing_data_o<4>9_711 ), .I1(\outgoing_data_o<4>18_692 ), .O(\outgoing_data_o<4>22_697 ) ); AND2 \outgoing_data_o<4>23 ( .I0(address_register[4]), .I1(\outgoing_data_o<4>20_695 ), .O(\outgoing_data_o<4>23_698 ) ); AND2 \outgoing_data_o<4>24 ( .I0(address_register[0]), .I1(\outgoing_data_o<4>21_696 ), .O(\outgoing_data_o<4>24_699 ) ); AND2 \outgoing_data_o<4>25 ( .I0(\outgoing_data_o<4>22_697 ), .I1(\outgoing_data_o<4>11_685 ), .O(\outgoing_data_o<4>25_700 ) ); AND3 \outgoing_data_o<4>26 ( .I0(\outgoing_data_o<4>23_698 ), .I1(\outgoing_data_o<4>1_683 ), .I2(\outgoing_data_o<4>6_708 ), .O(\outgoing_data_o<4>26_701 ) ); OR2 \outgoing_data_o<4>27 ( .I0(\outgoing_data_o<4>24_699 ), .I1(\outgoing_data_o<4>25_700 ), .O(\outgoing_data_o<4>27_702 ) ); AND3 \outgoing_data_o<4>28 ( .I0(\outgoing_data_o<4>27_702 ), .I1(address_register[5]), .I2(\outgoing_data_o<4>19_693 ), .O(\outgoing_data_o<4>28_703 ) ); AND2 \outgoing_data_o<4>29 ( .I0(\outgoing_data_o<4>28_703 ), .I1(\outgoing_data_o<4>14_688 ), .O(\outgoing_data_o<4>29_704 ) ); OR2 \outgoing_data_o<4>30 ( .I0(\outgoing_data_o<4>26_701 ), .I1(\outgoing_data_o<4>29_704 ), .O(outgoing_data_o[4]) ); AND2 \outgoing_data_o<6>1 ( .I0(address_register[2]), .I1(address_register[3]), .O(\outgoing_data_o<6>1_743 ) ); AND2 \outgoing_data_o<6>2 ( .I0(address_register[0]), .I1(NlwRenamedSig_OI_faults_o[6]), .O(\outgoing_data_o<6>2_754 ) ); OR6 \outgoing_data_o<6>3 ( .I0(warnings[0]), .I1(warnings[1]), .I2(warnings[2]), .I3(warnings[3]), .I4(warnings[4]), .I5(warnings[5]), .O(\outgoing_data_o<6>3_765 ) ); INV \outgoing_data_o<6>4 ( .I(address_register[0]), .O(\outgoing_data_o<6>4_766 ) ); INV \outgoing_data_o<6>5 ( .I(address_register[1]), .O(\outgoing_data_o<6>5_767 ) ); INV \outgoing_data_o<6>6 ( .I(address_register[5]), .O(\outgoing_data_o<6>6_768 ) ); AND2 \outgoing_data_o<6>7 ( .I0(address_register[1]), .I1(warnings_i[1]), .O(\outgoing_data_o<6>7_769 ) ); INV \outgoing_data_o<6>8 ( .I(address_register[1]), .O(\outgoing_data_o<6>8_770 ) ); AND2 \outgoing_data_o<6>9 ( .I0(address_register[1]), .I1(warnings_i[2]), .O(\outgoing_data_o<6>9_771 ) ); INV \outgoing_data_o<6>10 ( .I(address_register[1]), .O(\outgoing_data_o<6>10_744 ) ); INV \outgoing_data_o<6>11 ( .I(address_register[0]), .O(\outgoing_data_o<6>11_745 ) ); INV \outgoing_data_o<6>12 ( .I(address_register[3]), .O(\outgoing_data_o<6>12_746 ) ); INV \outgoing_data_o<6>13 ( .I(address_register[2]), .O(\outgoing_data_o<6>13_747 ) ); INV \outgoing_data_o<6>14 ( .I(address_register[4]), .O(\outgoing_data_o<6>14_748 ) ); AND2 \outgoing_data_o<6>15 ( .I0(\outgoing_data_o<6>3_765 ), .I1(\outgoing_data_o<6>4_766 ), .O(\outgoing_data_o<6>15_749 ) ); AND2 \outgoing_data_o<6>16 ( .I0(\outgoing_data_o<6>5_767 ), .I1(\outgoing_data_o<6>6_768 ), .O(\outgoing_data_o<6>16_750 ) ); AND2 \outgoing_data_o<6>17 ( .I0(warnings_i[0]), .I1(\outgoing_data_o<6>8_770 ), .O(\outgoing_data_o<6>17_751 ) ); AND2 \outgoing_data_o<6>18 ( .I0(diagnostic_register[6]), .I1(\outgoing_data_o<6>10_744 ), .O(\outgoing_data_o<6>18_752 ) ); AND2 \outgoing_data_o<6>19 ( .I0(\outgoing_data_o<6>12_746 ), .I1(\outgoing_data_o<6>13_747 ), .O(\outgoing_data_o<6>19_753 ) ); OR2 \outgoing_data_o<6>20 ( .I0(\outgoing_data_o<6>2_754 ), .I1(\outgoing_data_o<6>15_749 ), .O(\outgoing_data_o<6>20_755 ) ); OR2 \outgoing_data_o<6>21 ( .I0(\outgoing_data_o<6>7_769 ), .I1(\outgoing_data_o<6>17_751 ), .O(\outgoing_data_o<6>21_756 ) ); OR2 \outgoing_data_o<6>22 ( .I0(\outgoing_data_o<6>9_771 ), .I1(\outgoing_data_o<6>18_752 ), .O(\outgoing_data_o<6>22_757 ) ); AND2 \outgoing_data_o<6>23 ( .I0(address_register[4]), .I1(\outgoing_data_o<6>20_755 ), .O(\outgoing_data_o<6>23_758 ) ); AND2 \outgoing_data_o<6>24 ( .I0(address_register[0]), .I1(\outgoing_data_o<6>21_756 ), .O(\outgoing_data_o<6>24_759 ) ); AND2 \outgoing_data_o<6>25 ( .I0(\outgoing_data_o<6>22_757 ), .I1(\outgoing_data_o<6>11_745 ), .O(\outgoing_data_o<6>25_760 ) ); AND3 \outgoing_data_o<6>26 ( .I0(\outgoing_data_o<6>23_758 ), .I1(\outgoing_data_o<6>1_743 ), .I2(\outgoing_data_o<6>16_750 ), .O(\outgoing_data_o<6>26_761 ) ); OR2 \outgoing_data_o<6>27 ( .I0(\outgoing_data_o<6>24_759 ), .I1(\outgoing_data_o<6>25_760 ), .O(\outgoing_data_o<6>27_762 ) ); AND3 \outgoing_data_o<6>28 ( .I0(\outgoing_data_o<6>27_762 ), .I1(address_register[5]), .I2(\outgoing_data_o<6>19_753 ), .O(\outgoing_data_o<6>28_763 ) ); AND2 \outgoing_data_o<6>29 ( .I0(\outgoing_data_o<6>28_763 ), .I1(\outgoing_data_o<6>14_748 ), .O(\outgoing_data_o<6>29_764 ) ); OR2 \outgoing_data_o<6>30 ( .I0(\outgoing_data_o<6>26_761 ), .I1(\outgoing_data_o<6>29_764 ), .O(outgoing_data_o[6]) ); AND2 \outgoing_data_o<5>1 ( .I0(address_register[3]), .I1(address_register[2]), .O(\outgoing_data_o<5>1_713 ) ); AND2 \outgoing_data_o<5>2 ( .I0(NlwRenamedSig_OI_faults_o[5]), .I1(address_register[0]), .O(\outgoing_data_o<5>2_724 ) ); INV \outgoing_data_o<5>3 ( .I(address_register[1]), .O(\outgoing_data_o<5>3_735 ) ); AND2 \outgoing_data_o<5>4 ( .I0(address_register[1]), .I1(warnings[5]), .O(\outgoing_data_o<5>4_736 ) ); INV \outgoing_data_o<5>5 ( .I(address_register[0]), .O(\outgoing_data_o<5>5_737 ) ); INV \outgoing_data_o<5>6 ( .I(address_register[5]), .O(\outgoing_data_o<5>6_738 ) ); AND2 \outgoing_data_o<5>7 ( .I0(address_register[1]), .I1(switches_i[3]), .O(\outgoing_data_o<5>7_739 ) ); INV \outgoing_data_o<5>8 ( .I(address_register[1]), .O(\outgoing_data_o<5>8_740 ) ); AND2 \outgoing_data_o<5>9 ( .I0(address_register[1]), .I1(switches_i[5]), .O(\outgoing_data_o<5>9_741 ) ); INV \outgoing_data_o<5>10 ( .I(address_register[1]), .O(\outgoing_data_o<5>10_714 ) ); INV \outgoing_data_o<5>11 ( .I(address_register[0]), .O(\outgoing_data_o<5>11_715 ) ); INV \outgoing_data_o<5>12 ( .I(address_register[3]), .O(\outgoing_data_o<5>12_716 ) ); INV \outgoing_data_o<5>13 ( .I(address_register[2]), .O(\outgoing_data_o<5>13_717 ) ); INV \outgoing_data_o<5>14 ( .I(address_register[4]), .O(\outgoing_data_o<5>14_718 ) ); AND2 \outgoing_data_o<5>15 ( .I0(\outgoing_data_o<5>2_724 ), .I1(\outgoing_data_o<5>3_735 ), .O(\outgoing_data_o<5>15_719 ) ); AND2 \outgoing_data_o<5>16 ( .I0(\outgoing_data_o<5>4_736 ), .I1(\outgoing_data_o<5>5_737 ), .O(\outgoing_data_o<5>16_720 ) ); AND2 \outgoing_data_o<5>17 ( .I0(switches_i[1]), .I1(\outgoing_data_o<5>8_740 ), .O(\outgoing_data_o<5>17_721 ) ); AND2 \outgoing_data_o<5>18 ( .I0(diagnostic_register[5]), .I1(\outgoing_data_o<5>10_714 ), .O(\outgoing_data_o<5>18_722 ) ); AND2 \outgoing_data_o<5>19 ( .I0(\outgoing_data_o<5>12_716 ), .I1(\outgoing_data_o<5>13_717 ), .O(\outgoing_data_o<5>19_723 ) ); OR2 \outgoing_data_o<5>20 ( .I0(\outgoing_data_o<5>15_719 ), .I1(\outgoing_data_o<5>16_720 ), .O(\outgoing_data_o<5>20_725 ) ); OR2 \outgoing_data_o<5>21 ( .I0(\outgoing_data_o<5>7_739 ), .I1(\outgoing_data_o<5>17_721 ), .O(\outgoing_data_o<5>21_726 ) ); OR2 \outgoing_data_o<5>22 ( .I0(\outgoing_data_o<5>9_741 ), .I1(\outgoing_data_o<5>18_722 ), .O(\outgoing_data_o<5>22_727 ) ); AND2 \outgoing_data_o<5>23 ( .I0(address_register[4]), .I1(\outgoing_data_o<5>20_725 ), .O(\outgoing_data_o<5>23_728 ) ); AND2 \outgoing_data_o<5>24 ( .I0(address_register[0]), .I1(\outgoing_data_o<5>21_726 ), .O(\outgoing_data_o<5>24_729 ) ); AND2 \outgoing_data_o<5>25 ( .I0(\outgoing_data_o<5>22_727 ), .I1(\outgoing_data_o<5>11_715 ), .O(\outgoing_data_o<5>25_730 ) ); AND3 \outgoing_data_o<5>26 ( .I0(\outgoing_data_o<5>23_728 ), .I1(\outgoing_data_o<5>1_713 ), .I2(\outgoing_data_o<5>6_738 ), .O(\outgoing_data_o<5>26_731 ) ); OR2 \outgoing_data_o<5>27 ( .I0(\outgoing_data_o<5>24_729 ), .I1(\outgoing_data_o<5>25_730 ), .O(\outgoing_data_o<5>27_732 ) ); AND3 \outgoing_data_o<5>28 ( .I0(\outgoing_data_o<5>27_732 ), .I1(address_register[5]), .I2(\outgoing_data_o<5>19_723 ), .O(\outgoing_data_o<5>28_733 ) ); AND2 \outgoing_data_o<5>29 ( .I0(\outgoing_data_o<5>28_733 ), .I1(\outgoing_data_o<5>14_718 ), .O(\outgoing_data_o<5>29_734 ) ); OR2 \outgoing_data_o<5>30 ( .I0(\outgoing_data_o<5>26_731 ), .I1(\outgoing_data_o<5>29_734 ), .O(outgoing_data_o[5]) ); AND2 \outgoing_data_o<1>1 ( .I0(address_register[3]), .I1(address_register[2]), .O(\outgoing_data_o<1>1_596 ) ); AND2 \outgoing_data_o<1>2 ( .I0(address_register[1]), .I1(warnings[1]), .O(\outgoing_data_o<1>2_607 ) ); INV \outgoing_data_o<1>3 ( .I(address_register[1]), .O(\outgoing_data_o<1>3_618 ) ); INV \outgoing_data_o<1>4 ( .I(address_register[0]), .O(\outgoing_data_o<1>4_622 ) ); AND2 \outgoing_data_o<1>5 ( .I0(NlwRenamedSig_OI_faults_o[1]), .I1(address_register[0]), .O(\outgoing_data_o<1>5_623 ) ); INV \outgoing_data_o<1>6 ( .I(address_register[1]), .O(\outgoing_data_o<1>6_624 ) ); INV \outgoing_data_o<1>7 ( .I(address_register[5]), .O(\outgoing_data_o<1>7_625 ) ); AND2 \outgoing_data_o<1>8 ( .I0(address_register[1]), .I1(squeezes_i[1]), .O(\outgoing_data_o<1>8_626 ) ); INV \outgoing_data_o<1>9 ( .I(address_register[1]), .O(\outgoing_data_o<1>9_627 ) ); AND2 \outgoing_data_o<1>10 ( .I0(address_register[1]), .I1(bursts_i[1]), .O(\outgoing_data_o<1>10_597 ) ); INV \outgoing_data_o<1>11 ( .I(address_register[1]), .O(\outgoing_data_o<1>11_598 ) ); INV \outgoing_data_o<1>12 ( .I(address_register[0]), .O(\outgoing_data_o<1>12_599 ) ); INV \outgoing_data_o<1>13 ( .I(address_register[3]), .O(\outgoing_data_o<1>13_600 ) ); INV \outgoing_data_o<1>14 ( .I(address_register[2]), .O(\outgoing_data_o<1>14_601 ) ); INV \outgoing_data_o<1>15 ( .I(address_register[4]), .O(\outgoing_data_o<1>15_602 ) ); AND2 \outgoing_data_o<1>16 ( .I0(remote_squeeze_i), .I1(\outgoing_data_o<1>3_618 ), .O(\outgoing_data_o<1>16_603 ) ); AND2 \outgoing_data_o<1>17 ( .I0(\outgoing_data_o<1>5_623 ), .I1(\outgoing_data_o<1>6_624 ), .O(\outgoing_data_o<1>17_604 ) ); AND2 \outgoing_data_o<1>18 ( .I0(emptys_i[1]), .I1(\outgoing_data_o<1>9_627 ), .O(\outgoing_data_o<1>18_605 ) ); AND2 \outgoing_data_o<1>19 ( .I0(diagnostic_register[1]), .I1(\outgoing_data_o<1>11_598 ), .O(\outgoing_data_o<1>19_606 ) ); AND2 \outgoing_data_o<1>20 ( .I0(\outgoing_data_o<1>13_600 ), .I1(\outgoing_data_o<1>14_601 ), .O(\outgoing_data_o<1>20_608 ) ); OR2 \outgoing_data_o<1>21 ( .I0(\outgoing_data_o<1>2_607 ), .I1(\outgoing_data_o<1>16_603 ), .O(\outgoing_data_o<1>21_609 ) ); OR2 \outgoing_data_o<1>22 ( .I0(\outgoing_data_o<1>8_626 ), .I1(\outgoing_data_o<1>18_605 ), .O(\outgoing_data_o<1>22_610 ) ); OR2 \outgoing_data_o<1>23 ( .I0(\outgoing_data_o<1>10_597 ), .I1(\outgoing_data_o<1>19_606 ), .O(\outgoing_data_o<1>23_611 ) ); AND2 \outgoing_data_o<1>24 ( .I0(\outgoing_data_o<1>21_609 ), .I1(\outgoing_data_o<1>4_622 ), .O(\outgoing_data_o<1>24_612 ) ); AND2 \outgoing_data_o<1>25 ( .I0(address_register[0]), .I1(\outgoing_data_o<1>22_610 ), .O(\outgoing_data_o<1>25_613 ) ); AND2 \outgoing_data_o<1>26 ( .I0(\outgoing_data_o<1>23_611 ), .I1(\outgoing_data_o<1>12_599 ), .O(\outgoing_data_o<1>26_614 ) ); OR2 \outgoing_data_o<1>27 ( .I0(\outgoing_data_o<1>24_612 ), .I1(\outgoing_data_o<1>17_604 ), .O(\outgoing_data_o<1>27_615 ) ); OR2 \outgoing_data_o<1>28 ( .I0(\outgoing_data_o<1>25_613 ), .I1(\outgoing_data_o<1>26_614 ), .O(\outgoing_data_o<1>28_616 ) ); AND2 \outgoing_data_o<1>29 ( .I0(address_register[4]), .I1(\outgoing_data_o<1>27_615 ), .O(\outgoing_data_o<1>29_617 ) ); AND3 \outgoing_data_o<1>30 ( .I0(\outgoing_data_o<1>28_616 ), .I1(address_register[5]), .I2(\outgoing_data_o<1>20_608 ), .O(\outgoing_data_o<1>30_619 ) ); AND3 \outgoing_data_o<1>31 ( .I0(\outgoing_data_o<1>29_617 ), .I1(\outgoing_data_o<1>1_596 ), .I2(\outgoing_data_o<1>7_625 ), .O(\outgoing_data_o<1>31_620 ) ); AND2 \outgoing_data_o<1>32 ( .I0(\outgoing_data_o<1>30_619 ), .I1(\outgoing_data_o<1>15_602 ), .O(\outgoing_data_o<1>32_621 ) ); OR2 \outgoing_data_o<1>33 ( .I0(\outgoing_data_o<1>31_620 ), .I1(\outgoing_data_o<1>32_621 ), .O(outgoing_data_o[1]) ); AND2 \outgoing_data_o<2>1 ( .I0(address_register[3]), .I1(address_register[2]), .O(\outgoing_data_o<2>1_629 ) ); AND2 \outgoing_data_o<2>2 ( .I0(address_register[1]), .I1(warnings[2]), .O(\outgoing_data_o<2>2_640 ) ); INV \outgoing_data_o<2>3 ( .I(address_register[1]), .O(\outgoing_data_o<2>3_651 ) ); INV \outgoing_data_o<2>4 ( .I(address_register[0]), .O(\outgoing_data_o<2>4_655 ) ); AND2 \outgoing_data_o<2>5 ( .I0(NlwRenamedSig_OI_faults_o[2]), .I1(address_register[0]), .O(\outgoing_data_o<2>5_656 ) ); INV \outgoing_data_o<2>6 ( .I(address_register[1]), .O(\outgoing_data_o<2>6_657 ) ); INV \outgoing_data_o<2>7 ( .I(address_register[5]), .O(\outgoing_data_o<2>7_658 ) ); AND2 \outgoing_data_o<2>8 ( .I0(address_register[1]), .I1(squeezes_i[2]), .O(\outgoing_data_o<2>8_659 ) ); INV \outgoing_data_o<2>9 ( .I(address_register[1]), .O(\outgoing_data_o<2>9_660 ) ); AND2 \outgoing_data_o<2>10 ( .I0(address_register[1]), .I1(bursts_i[2]), .O(\outgoing_data_o<2>10_630 ) ); INV \outgoing_data_o<2>11 ( .I(address_register[1]), .O(\outgoing_data_o<2>11_631 ) ); INV \outgoing_data_o<2>12 ( .I(address_register[0]), .O(\outgoing_data_o<2>12_632 ) ); INV \outgoing_data_o<2>13 ( .I(address_register[3]), .O(\outgoing_data_o<2>13_633 ) ); INV \outgoing_data_o<2>14 ( .I(address_register[2]), .O(\outgoing_data_o<2>14_634 ) ); INV \outgoing_data_o<2>15 ( .I(address_register[4]), .O(\outgoing_data_o<2>15_635 ) ); AND2 \outgoing_data_o<2>16 ( .I0(remote_burst_i), .I1(\outgoing_data_o<2>3_651 ), .O(\outgoing_data_o<2>16_636 ) ); AND2 \outgoing_data_o<2>17 ( .I0(\outgoing_data_o<2>5_656 ), .I1(\outgoing_data_o<2>6_657 ), .O(\outgoing_data_o<2>17_637 ) ); AND2 \outgoing_data_o<2>18 ( .I0(emptys_i[2]), .I1(\outgoing_data_o<2>9_660 ), .O(\outgoing_data_o<2>18_638 ) ); AND2 \outgoing_data_o<2>19 ( .I0(diagnostic_register[2]), .I1(\outgoing_data_o<2>11_631 ), .O(\outgoing_data_o<2>19_639 ) ); AND2 \outgoing_data_o<2>20 ( .I0(\outgoing_data_o<2>13_633 ), .I1(\outgoing_data_o<2>14_634 ), .O(\outgoing_data_o<2>20_641 ) ); OR2 \outgoing_data_o<2>21 ( .I0(\outgoing_data_o<2>2_640 ), .I1(\outgoing_data_o<2>16_636 ), .O(\outgoing_data_o<2>21_642 ) ); OR2 \outgoing_data_o<2>22 ( .I0(\outgoing_data_o<2>8_659 ), .I1(\outgoing_data_o<2>18_638 ), .O(\outgoing_data_o<2>22_643 ) ); OR2 \outgoing_data_o<2>23 ( .I0(\outgoing_data_o<2>10_630 ), .I1(\outgoing_data_o<2>19_639 ), .O(\outgoing_data_o<2>23_644 ) ); AND2 \outgoing_data_o<2>24 ( .I0(\outgoing_data_o<2>21_642 ), .I1(\outgoing_data_o<2>4_655 ), .O(\outgoing_data_o<2>24_645 ) ); AND2 \outgoing_data_o<2>25 ( .I0(address_register[0]), .I1(\outgoing_data_o<2>22_643 ), .O(\outgoing_data_o<2>25_646 ) ); AND2 \outgoing_data_o<2>26 ( .I0(\outgoing_data_o<2>23_644 ), .I1(\outgoing_data_o<2>12_632 ), .O(\outgoing_data_o<2>26_647 ) ); OR2 \outgoing_data_o<2>27 ( .I0(\outgoing_data_o<2>24_645 ), .I1(\outgoing_data_o<2>17_637 ), .O(\outgoing_data_o<2>27_648 ) ); OR2 \outgoing_data_o<2>28 ( .I0(\outgoing_data_o<2>25_646 ), .I1(\outgoing_data_o<2>26_647 ), .O(\outgoing_data_o<2>28_649 ) ); AND2 \outgoing_data_o<2>29 ( .I0(address_register[4]), .I1(\outgoing_data_o<2>27_648 ), .O(\outgoing_data_o<2>29_650 ) ); AND3 \outgoing_data_o<2>30 ( .I0(\outgoing_data_o<2>28_649 ), .I1(address_register[5]), .I2(\outgoing_data_o<2>20_641 ), .O(\outgoing_data_o<2>30_652 ) ); AND3 \outgoing_data_o<2>31 ( .I0(\outgoing_data_o<2>29_650 ), .I1(\outgoing_data_o<2>1_629 ), .I2(\outgoing_data_o<2>7_658 ), .O(\outgoing_data_o<2>31_653 ) ); AND2 \outgoing_data_o<2>32 ( .I0(\outgoing_data_o<2>30_652 ), .I1(\outgoing_data_o<2>15_635 ), .O(\outgoing_data_o<2>32_654 ) ); OR2 \outgoing_data_o<2>33 ( .I0(\outgoing_data_o<2>31_653 ), .I1(\outgoing_data_o<2>32_654 ), .O(outgoing_data_o[2]) ); AND2 \outgoing_data_o<0>1 ( .I0(address_register[3]), .I1(address_register[2]), .O(\outgoing_data_o<0>1_563 ) ); AND2 \outgoing_data_o<0>2 ( .I0(address_register[1]), .I1(warnings[0]), .O(\outgoing_data_o<0>2_574 ) ); INV \outgoing_data_o<0>3 ( .I(address_register[1]), .O(\outgoing_data_o<0>3_585 ) ); INV \outgoing_data_o<0>4 ( .I(address_register[0]), .O(\outgoing_data_o<0>4_589 ) ); AND2 \outgoing_data_o<0>5 ( .I0(NlwRenamedSig_OI_faults_o[0]), .I1(address_register[0]), .O(\outgoing_data_o<0>5_590 ) ); INV \outgoing_data_o<0>6 ( .I(address_register[1]), .O(\outgoing_data_o<0>6_591 ) ); INV \outgoing_data_o<0>7 ( .I(address_register[5]), .O(\outgoing_data_o<0>7_592 ) ); AND2 \outgoing_data_o<0>8 ( .I0(address_register[1]), .I1(squeezes_i[0]), .O(\outgoing_data_o<0>8_593 ) ); INV \outgoing_data_o<0>9 ( .I(address_register[1]), .O(\outgoing_data_o<0>9_594 ) ); AND2 \outgoing_data_o<0>10 ( .I0(address_register[1]), .I1(bursts_i[0]), .O(\outgoing_data_o<0>10_564 ) ); INV \outgoing_data_o<0>11 ( .I(address_register[1]), .O(\outgoing_data_o<0>11_565 ) ); INV \outgoing_data_o<0>12 ( .I(address_register[0]), .O(\outgoing_data_o<0>12_566 ) ); INV \outgoing_data_o<0>13 ( .I(address_register[3]), .O(\outgoing_data_o<0>13_567 ) ); INV \outgoing_data_o<0>14 ( .I(address_register[2]), .O(\outgoing_data_o<0>14_568 ) ); INV \outgoing_data_o<0>15 ( .I(address_register[4]), .O(\outgoing_data_o<0>15_569 ) ); AND2 \outgoing_data_o<0>16 ( .I0(remote_empty_i), .I1(\outgoing_data_o<0>3_585 ), .O(\outgoing_data_o<0>16_570 ) ); AND2 \outgoing_data_o<0>17 ( .I0(\outgoing_data_o<0>5_590 ), .I1(\outgoing_data_o<0>6_591 ), .O(\outgoing_data_o<0>17_571 ) ); AND2 \outgoing_data_o<0>18 ( .I0(emptys_i[0]), .I1(\outgoing_data_o<0>9_594 ), .O(\outgoing_data_o<0>18_572 ) ); AND2 \outgoing_data_o<0>19 ( .I0(diagnostic_register[0]), .I1(\outgoing_data_o<0>11_565 ), .O(\outgoing_data_o<0>19_573 ) ); AND2 \outgoing_data_o<0>20 ( .I0(\outgoing_data_o<0>13_567 ), .I1(\outgoing_data_o<0>14_568 ), .O(\outgoing_data_o<0>20_575 ) ); OR2 \outgoing_data_o<0>21 ( .I0(\outgoing_data_o<0>2_574 ), .I1(\outgoing_data_o<0>16_570 ), .O(\outgoing_data_o<0>21_576 ) ); OR2 \outgoing_data_o<0>22 ( .I0(\outgoing_data_o<0>8_593 ), .I1(\outgoing_data_o<0>18_572 ), .O(\outgoing_data_o<0>22_577 ) ); OR2 \outgoing_data_o<0>23 ( .I0(\outgoing_data_o<0>10_564 ), .I1(\outgoing_data_o<0>19_573 ), .O(\outgoing_data_o<0>23_578 ) ); AND2 \outgoing_data_o<0>24 ( .I0(\outgoing_data_o<0>21_576 ), .I1(\outgoing_data_o<0>4_589 ), .O(\outgoing_data_o<0>24_579 ) ); AND2 \outgoing_data_o<0>25 ( .I0(address_register[0]), .I1(\outgoing_data_o<0>22_577 ), .O(\outgoing_data_o<0>25_580 ) ); AND2 \outgoing_data_o<0>26 ( .I0(\outgoing_data_o<0>23_578 ), .I1(\outgoing_data_o<0>12_566 ), .O(\outgoing_data_o<0>26_581 ) ); OR2 \outgoing_data_o<0>27 ( .I0(\outgoing_data_o<0>24_579 ), .I1(\outgoing_data_o<0>17_571 ), .O(\outgoing_data_o<0>27_582 ) ); OR2 \outgoing_data_o<0>28 ( .I0(\outgoing_data_o<0>25_580 ), .I1(\outgoing_data_o<0>26_581 ), .O(\outgoing_data_o<0>28_583 ) ); AND2 \outgoing_data_o<0>29 ( .I0(address_register[4]), .I1(\outgoing_data_o<0>27_582 ), .O(\outgoing_data_o<0>29_584 ) ); AND3 \outgoing_data_o<0>30 ( .I0(\outgoing_data_o<0>28_583 ), .I1(address_register[5]), .I2(\outgoing_data_o<0>20_575 ), .O(\outgoing_data_o<0>30_586 ) ); AND3 \outgoing_data_o<0>31 ( .I0(\outgoing_data_o<0>29_584 ), .I1(\outgoing_data_o<0>1_563 ), .I2(\outgoing_data_o<0>7_592 ), .O(\outgoing_data_o<0>31_587 ) ); AND2 \outgoing_data_o<0>32 ( .I0(\outgoing_data_o<0>30_586 ), .I1(\outgoing_data_o<0>15_569 ), .O(\outgoing_data_o<0>32_588 ) ); OR2 \outgoing_data_o<0>33 ( .I0(\outgoing_data_o<0>31_587 ), .I1(\outgoing_data_o<0>32_588 ), .O(outgoing_data_o[0]) ); AND4 faults_0_and00011 ( .I0(previous_wr_n_800), .I1(incoming_data_i[0]), .I2(address_register[2]), .I3(address_register[0]), .O(faults_0_and00011_417) ); AND2 faults_0_and00012 ( .I0(address_register[4]), .I1(address_register[3]), .O(faults_0_and00012_419) ); INV faults_0_and00013 ( .I(wr_n_i), .O(faults_0_and00013_420) ); INV faults_0_and00014 ( .I(address_register[1]), .O(faults_0_and00014_421) ); INV faults_0_and00015 ( .I(address_register[5]), .O(faults_0_and00015_422) ); INV faults_0_and00016 ( .I(address_register[6]), .O(faults_0_and00016_423) ); INV faults_0_and00017 ( .I(address_register[7]), .O(faults_0_and00017_424) ); AND2 faults_0_and00018 ( .I0(faults_0_and00013_420), .I1(faults_0_and00014_421), .O(faults_0_and00018_425) ); AND3 faults_0_and00019 ( .I0(faults_0_and00016_423), .I1(faults_0_and00015_422), .I2(faults_0_and00017_424), .O(faults_0_and00019_426) ); AND2 faults_0_and000110 ( .I0(faults_0_and00012_419), .I1(faults_0_and00018_425), .O(faults_0_and000110_418) ); AND3 faults_0_and000111 ( .I0(faults_0_and000110_418), .I1(faults_0_and00011_417), .I2(faults_0_and00019_426), .O(faults_0_and0001) ); AND4 faults_1_and00011 ( .I0(previous_wr_n_800), .I1(incoming_data_i[1]), .I2(address_register[2]), .I3(address_register[0]), .O(faults_1_and00011_432) ); AND2 faults_1_and00012 ( .I0(address_register[4]), .I1(address_register[3]), .O(faults_1_and00012_434) ); INV faults_1_and00013 ( .I(wr_n_i), .O(faults_1_and00013_435) ); INV faults_1_and00014 ( .I(address_register[1]), .O(faults_1_and00014_436) ); INV faults_1_and00015 ( .I(address_register[5]), .O(faults_1_and00015_437) ); INV faults_1_and00016 ( .I(address_register[6]), .O(faults_1_and00016_438) ); INV faults_1_and00017 ( .I(address_register[7]), .O(faults_1_and00017_439) ); AND2 faults_1_and00018 ( .I0(faults_1_and00013_435), .I1(faults_1_and00014_436), .O(faults_1_and00018_440) ); AND3 faults_1_and00019 ( .I0(faults_1_and00016_438), .I1(faults_1_and00015_437), .I2(faults_1_and00017_439), .O(faults_1_and00019_441) ); AND2 faults_1_and000110 ( .I0(faults_1_and00012_434), .I1(faults_1_and00018_440), .O(faults_1_and000110_433) ); AND3 faults_1_and000111 ( .I0(faults_1_and000110_433), .I1(faults_1_and00011_432), .I2(faults_1_and00019_441), .O(faults_1_and0001) ); AND4 faults_2_and00011 ( .I0(previous_wr_n_800), .I1(incoming_data_i[2]), .I2(address_register[2]), .I3(address_register[0]), .O(faults_2_and00011_447) ); AND2 faults_2_and00012 ( .I0(address_register[4]), .I1(address_register[3]), .O(faults_2_and00012_449) ); INV faults_2_and00013 ( .I(wr_n_i), .O(faults_2_and00013_450) ); INV faults_2_and00014 ( .I(address_register[1]), .O(faults_2_and00014_451) ); INV faults_2_and00015 ( .I(address_register[5]), .O(faults_2_and00015_452) ); INV faults_2_and00016 ( .I(address_register[6]), .O(faults_2_and00016_453) ); INV faults_2_and00017 ( .I(address_register[7]), .O(faults_2_and00017_454) ); AND2 faults_2_and00018 ( .I0(faults_2_and00013_450), .I1(faults_2_and00014_451), .O(faults_2_and00018_455) ); AND3 faults_2_and00019 ( .I0(faults_2_and00016_453), .I1(faults_2_and00015_452), .I2(faults_2_and00017_454), .O(faults_2_and00019_456) ); AND2 faults_2_and000110 ( .I0(faults_2_and00012_449), .I1(faults_2_and00018_455), .O(faults_2_and000110_448) ); AND3 faults_2_and000111 ( .I0(faults_2_and000110_448), .I1(faults_2_and00011_447), .I2(faults_2_and00019_456), .O(faults_2_and0001) ); AND4 faults_3_and00011 ( .I0(previous_wr_n_800), .I1(incoming_data_i[3]), .I2(address_register[2]), .I3(address_register[0]), .O(faults_3_and00011_462) ); AND2 faults_3_and00012 ( .I0(address_register[4]), .I1(address_register[3]), .O(faults_3_and00012_464) ); INV faults_3_and00013 ( .I(wr_n_i), .O(faults_3_and00013_465) ); INV faults_3_and00014 ( .I(address_register[1]), .O(faults_3_and00014_466) ); INV faults_3_and00015 ( .I(address_register[5]), .O(faults_3_and00015_467) ); INV faults_3_and00016 ( .I(address_register[6]), .O(faults_3_and00016_468) ); INV faults_3_and00017 ( .I(address_register[7]), .O(faults_3_and00017_469) ); AND2 faults_3_and00018 ( .I0(faults_3_and00013_465), .I1(faults_3_and00014_466), .O(faults_3_and00018_470) ); AND3 faults_3_and00019 ( .I0(faults_3_and00016_468), .I1(faults_3_and00015_467), .I2(faults_3_and00017_469), .O(faults_3_and00019_471) ); AND2 faults_3_and000110 ( .I0(faults_3_and00012_464), .I1(faults_3_and00018_470), .O(faults_3_and000110_463) ); AND3 faults_3_and000111 ( .I0(faults_3_and000110_463), .I1(faults_3_and00011_462), .I2(faults_3_and00019_471), .O(faults_3_and0001) ); AND4 faults_4_and00011 ( .I0(previous_wr_n_800), .I1(incoming_data_i[4]), .I2(address_register[2]), .I3(address_register[0]), .O(faults_4_and00011_477) ); AND2 faults_4_and00012 ( .I0(address_register[4]), .I1(address_register[3]), .O(faults_4_and00012_479) ); INV faults_4_and00013 ( .I(wr_n_i), .O(faults_4_and00013_480) ); INV faults_4_and00014 ( .I(address_register[1]), .O(faults_4_and00014_481) ); INV faults_4_and00015 ( .I(address_register[5]), .O(faults_4_and00015_482) ); INV faults_4_and00016 ( .I(address_register[6]), .O(faults_4_and00016_483) ); INV faults_4_and00017 ( .I(address_register[7]), .O(faults_4_and00017_484) ); AND2 faults_4_and00018 ( .I0(faults_4_and00013_480), .I1(faults_4_and00014_481), .O(faults_4_and00018_485) ); AND3 faults_4_and00019 ( .I0(faults_4_and00016_483), .I1(faults_4_and00015_482), .I2(faults_4_and00017_484), .O(faults_4_and00019_486) ); AND2 faults_4_and000110 ( .I0(faults_4_and00012_479), .I1(faults_4_and00018_485), .O(faults_4_and000110_478) ); AND3 faults_4_and000111 ( .I0(faults_4_and000110_478), .I1(faults_4_and00011_477), .I2(faults_4_and00019_486), .O(faults_4_and0001) ); AND4 faults_5_and00011 ( .I0(previous_wr_n_800), .I1(incoming_data_i[5]), .I2(address_register[2]), .I3(address_register[0]), .O(faults_5_and00011_492) ); AND2 faults_5_and00012 ( .I0(address_register[4]), .I1(address_register[3]), .O(faults_5_and00012_494) ); INV faults_5_and00013 ( .I(wr_n_i), .O(faults_5_and00013_495) ); INV faults_5_and00014 ( .I(address_register[1]), .O(faults_5_and00014_496) ); INV faults_5_and00015 ( .I(address_register[5]), .O(faults_5_and00015_497) ); INV faults_5_and00016 ( .I(address_register[6]), .O(faults_5_and00016_498) ); INV faults_5_and00017 ( .I(address_register[7]), .O(faults_5_and00017_499) ); AND2 faults_5_and00018 ( .I0(faults_5_and00013_495), .I1(faults_5_and00014_496), .O(faults_5_and00018_500) ); AND3 faults_5_and00019 ( .I0(faults_5_and00016_498), .I1(faults_5_and00015_497), .I2(faults_5_and00017_499), .O(faults_5_and00019_501) ); AND2 faults_5_and000110 ( .I0(faults_5_and00012_494), .I1(faults_5_and00018_500), .O(faults_5_and000110_493) ); AND3 faults_5_and000111 ( .I0(faults_5_and000110_493), .I1(faults_5_and00011_492), .I2(faults_5_and00019_501), .O(faults_5_and0001) ); AND4 faults_6_and00011 ( .I0(previous_wr_n_800), .I1(incoming_data_i[6]), .I2(address_register[2]), .I3(address_register[0]), .O(faults_6_and00011_507) ); AND2 faults_6_and00012 ( .I0(address_register[4]), .I1(address_register[3]), .O(faults_6_and00012_509) ); INV faults_6_and00013 ( .I(wr_n_i), .O(faults_6_and00013_510) ); INV faults_6_and00014 ( .I(address_register[1]), .O(faults_6_and00014_511) ); INV faults_6_and00015 ( .I(address_register[5]), .O(faults_6_and00015_512) ); INV faults_6_and00016 ( .I(address_register[6]), .O(faults_6_and00016_513) ); INV faults_6_and00017 ( .I(address_register[7]), .O(faults_6_and00017_514) ); AND2 faults_6_and00018 ( .I0(faults_6_and00013_510), .I1(faults_6_and00014_511), .O(faults_6_and00018_515) ); AND3 faults_6_and00019 ( .I0(faults_6_and00016_513), .I1(faults_6_and00015_512), .I2(faults_6_and00017_514), .O(faults_6_and00019_516) ); AND2 faults_6_and000110 ( .I0(faults_6_and00012_509), .I1(faults_6_and00018_515), .O(faults_6_and000110_508) ); AND3 faults_6_and000111 ( .I0(faults_6_and000110_508), .I1(faults_6_and00011_507), .I2(faults_6_and00019_516), .O(faults_6_and0001) ); AND4 faults_7_and00011 ( .I0(previous_wr_n_800), .I1(incoming_data_i[7]), .I2(address_register[2]), .I3(address_register[0]), .O(faults_7_and00011_522) ); AND2 faults_7_and00012 ( .I0(address_register[4]), .I1(address_register[3]), .O(faults_7_and00012_524) ); INV faults_7_and00013 ( .I(wr_n_i), .O(faults_7_and00013_525) ); INV faults_7_and00014 ( .I(address_register[1]), .O(faults_7_and00014_526) ); INV faults_7_and00015 ( .I(address_register[5]), .O(faults_7_and00015_527) ); INV faults_7_and00016 ( .I(address_register[6]), .O(faults_7_and00016_528) ); INV faults_7_and00017 ( .I(address_register[7]), .O(faults_7_and00017_529) ); AND2 faults_7_and00018 ( .I0(faults_7_and00013_525), .I1(faults_7_and00014_526), .O(faults_7_and00018_530) ); AND3 faults_7_and00019 ( .I0(faults_7_and00016_528), .I1(faults_7_and00015_527), .I2(faults_7_and00017_529), .O(faults_7_and00019_531) ); AND2 faults_7_and000110 ( .I0(faults_7_and00012_524), .I1(faults_7_and00018_530), .O(faults_7_and000110_523) ); AND3 faults_7_and000111 ( .I0(faults_7_and000110_523), .I1(faults_7_and00011_522), .I2(faults_7_and00019_531), .O(faults_7_and0001) ); AND4 warnings_0_and00011 ( .I0(previous_wr_n_800), .I1(incoming_data_i[0]), .I2(address_register[1]), .I3(address_register[2]), .O(warnings_0_and00011_818) ); AND2 warnings_0_and00012 ( .I0(address_register[4]), .I1(address_register[3]), .O(warnings_0_and00012_820) ); INV warnings_0_and00013 ( .I(wr_n_i), .O(warnings_0_and00013_821) ); INV warnings_0_and00014 ( .I(address_register[0]), .O(warnings_0_and00014_822) ); INV warnings_0_and00015 ( .I(address_register[5]), .O(warnings_0_and00015_823) ); INV warnings_0_and00016 ( .I(address_register[6]), .O(warnings_0_and00016_824) ); INV warnings_0_and00017 ( .I(address_register[7]), .O(warnings_0_and00017_825) ); AND2 warnings_0_and00018 ( .I0(warnings_0_and00013_821), .I1(warnings_0_and00014_822), .O(warnings_0_and00018_826) ); AND3 warnings_0_and00019 ( .I0(warnings_0_and00016_824), .I1(warnings_0_and00015_823), .I2(warnings_0_and00017_825), .O(warnings_0_and00019_827) ); AND2 warnings_0_and000110 ( .I0(warnings_0_and00012_820), .I1(warnings_0_and00018_826), .O(warnings_0_and000110_819) ); AND3 warnings_0_and000111 ( .I0(warnings_0_and000110_819), .I1(warnings_0_and00011_818), .I2(warnings_0_and00019_827), .O(warnings_0_and0001) ); AND4 warnings_1_and00011 ( .I0(previous_wr_n_800), .I1(incoming_data_i[1]), .I2(address_register[1]), .I3(address_register[2]), .O(warnings_1_and00011_834) ); AND2 warnings_1_and00012 ( .I0(address_register[4]), .I1(address_register[3]), .O(warnings_1_and00012_836) ); INV warnings_1_and00013 ( .I(wr_n_i), .O(warnings_1_and00013_837) ); INV warnings_1_and00014 ( .I(address_register[0]), .O(warnings_1_and00014_838) ); INV warnings_1_and00015 ( .I(address_register[5]), .O(warnings_1_and00015_839) ); INV warnings_1_and00016 ( .I(address_register[6]), .O(warnings_1_and00016_840) ); INV warnings_1_and00017 ( .I(address_register[7]), .O(warnings_1_and00017_841) ); AND2 warnings_1_and00018 ( .I0(warnings_1_and00013_837), .I1(warnings_1_and00014_838), .O(warnings_1_and00018_842) ); AND3 warnings_1_and00019 ( .I0(warnings_1_and00016_840), .I1(warnings_1_and00015_839), .I2(warnings_1_and00017_841), .O(warnings_1_and00019_843) ); AND2 warnings_1_and000110 ( .I0(warnings_1_and00012_836), .I1(warnings_1_and00018_842), .O(warnings_1_and000110_835) ); AND3 warnings_1_and000111 ( .I0(warnings_1_and000110_835), .I1(warnings_1_and00011_834), .I2(warnings_1_and00019_843), .O(warnings_1_and0001) ); AND4 warnings_2_and00011 ( .I0(previous_wr_n_800), .I1(incoming_data_i[2]), .I2(address_register[1]), .I3(address_register[2]), .O(warnings_2_and00011_850) ); AND2 warnings_2_and00012 ( .I0(address_register[4]), .I1(address_register[3]), .O(warnings_2_and00012_852) ); INV warnings_2_and00013 ( .I(wr_n_i), .O(warnings_2_and00013_853) ); INV warnings_2_and00014 ( .I(address_register[0]), .O(warnings_2_and00014_854) ); INV warnings_2_and00015 ( .I(address_register[5]), .O(warnings_2_and00015_855) ); INV warnings_2_and00016 ( .I(address_register[6]), .O(warnings_2_and00016_856) ); INV warnings_2_and00017 ( .I(address_register[7]), .O(warnings_2_and00017_857) ); AND2 warnings_2_and00018 ( .I0(warnings_2_and00013_853), .I1(warnings_2_and00014_854), .O(warnings_2_and00018_858) ); AND3 warnings_2_and00019 ( .I0(warnings_2_and00016_856), .I1(warnings_2_and00015_855), .I2(warnings_2_and00017_857), .O(warnings_2_and00019_859) ); AND2 warnings_2_and000110 ( .I0(warnings_2_and00012_852), .I1(warnings_2_and00018_858), .O(warnings_2_and000110_851) ); AND3 warnings_2_and000111 ( .I0(warnings_2_and000110_851), .I1(warnings_2_and00011_850), .I2(warnings_2_and00019_859), .O(warnings_2_and0001) ); AND4 warnings_3_and00011 ( .I0(previous_wr_n_800), .I1(incoming_data_i[3]), .I2(address_register[1]), .I3(address_register[2]), .O(warnings_3_and00011_866) ); AND2 warnings_3_and00012 ( .I0(address_register[4]), .I1(address_register[3]), .O(warnings_3_and00012_868) ); INV warnings_3_and00013 ( .I(wr_n_i), .O(warnings_3_and00013_869) ); INV warnings_3_and00014 ( .I(address_register[0]), .O(warnings_3_and00014_870) ); INV warnings_3_and00015 ( .I(address_register[5]), .O(warnings_3_and00015_871) ); INV warnings_3_and00016 ( .I(address_register[6]), .O(warnings_3_and00016_872) ); INV warnings_3_and00017 ( .I(address_register[7]), .O(warnings_3_and00017_873) ); AND2 warnings_3_and00018 ( .I0(warnings_3_and00013_869), .I1(warnings_3_and00014_870), .O(warnings_3_and00018_874) ); AND3 warnings_3_and00019 ( .I0(warnings_3_and00016_872), .I1(warnings_3_and00015_871), .I2(warnings_3_and00017_873), .O(warnings_3_and00019_875) ); AND2 warnings_3_and000110 ( .I0(warnings_3_and00012_868), .I1(warnings_3_and00018_874), .O(warnings_3_and000110_867) ); AND3 warnings_3_and000111 ( .I0(warnings_3_and000110_867), .I1(warnings_3_and00011_866), .I2(warnings_3_and00019_875), .O(warnings_3_and0001) ); AND4 warnings_4_and00011 ( .I0(previous_wr_n_800), .I1(incoming_data_i[4]), .I2(address_register[1]), .I3(address_register[2]), .O(warnings_4_and00011_882) ); AND2 warnings_4_and00012 ( .I0(address_register[4]), .I1(address_register[3]), .O(warnings_4_and00012_884) ); INV warnings_4_and00013 ( .I(wr_n_i), .O(warnings_4_and00013_885) ); INV warnings_4_and00014 ( .I(address_register[0]), .O(warnings_4_and00014_886) ); INV warnings_4_and00015 ( .I(address_register[5]), .O(warnings_4_and00015_887) ); INV warnings_4_and00016 ( .I(address_register[6]), .O(warnings_4_and00016_888) ); INV warnings_4_and00017 ( .I(address_register[7]), .O(warnings_4_and00017_889) ); AND2 warnings_4_and00018 ( .I0(warnings_4_and00013_885), .I1(warnings_4_and00014_886), .O(warnings_4_and00018_890) ); AND3 warnings_4_and00019 ( .I0(warnings_4_and00016_888), .I1(warnings_4_and00015_887), .I2(warnings_4_and00017_889), .O(warnings_4_and00019_891) ); AND2 warnings_4_and000110 ( .I0(warnings_4_and00012_884), .I1(warnings_4_and00018_890), .O(warnings_4_and000110_883) ); AND3 warnings_4_and000111 ( .I0(warnings_4_and000110_883), .I1(warnings_4_and00011_882), .I2(warnings_4_and00019_891), .O(warnings_4_and0001) ); AND4 warnings_5_and00011 ( .I0(previous_wr_n_800), .I1(incoming_data_i[5]), .I2(address_register[1]), .I3(address_register[2]), .O(warnings_5_and00011_898) ); AND2 warnings_5_and00012 ( .I0(address_register[4]), .I1(address_register[3]), .O(warnings_5_and00012_900) ); INV warnings_5_and00013 ( .I(wr_n_i), .O(warnings_5_and00013_901) ); INV warnings_5_and00014 ( .I(address_register[0]), .O(warnings_5_and00014_902) ); INV warnings_5_and00015 ( .I(address_register[5]), .O(warnings_5_and00015_903) ); INV warnings_5_and00016 ( .I(address_register[6]), .O(warnings_5_and00016_904) ); INV warnings_5_and00017 ( .I(address_register[7]), .O(warnings_5_and00017_905) ); AND2 warnings_5_and00018 ( .I0(warnings_5_and00013_901), .I1(warnings_5_and00014_902), .O(warnings_5_and00018_906) ); AND3 warnings_5_and00019 ( .I0(warnings_5_and00016_904), .I1(warnings_5_and00015_903), .I2(warnings_5_and00017_905), .O(warnings_5_and00019_907) ); AND2 warnings_5_and000110 ( .I0(warnings_5_and00012_900), .I1(warnings_5_and00018_906), .O(warnings_5_and000110_899) ); AND3 warnings_5_and000111 ( .I0(warnings_5_and000110_899), .I1(warnings_5_and00011_898), .I2(warnings_5_and00019_907), .O(warnings_5_and0001) ); AND2 drive_bus_o1 ( .I0(address_register[2]), .I1(address_register[3]), .O(drive_bus_o1_400) ); INV drive_bus_o2 ( .I(address_register[5]), .O(drive_bus_o2_405) ); INV drive_bus_o3 ( .I(address_register[2]), .O(drive_bus_o3_406) ); INV drive_bus_o4 ( .I(address_register[3]), .O(drive_bus_o4_407) ); INV drive_bus_o5 ( .I(address_register[4]), .O(drive_bus_o5_408) ); INV drive_bus_o6 ( .I(address_register[6]), .O(drive_bus_o6_409) ); INV drive_bus_o7 ( .I(address_register[7]), .O(drive_bus_o7_410) ); INV drive_bus_o8 ( .I(rd_n_i), .O(drive_bus_o8_411) ); AND2 drive_bus_o9 ( .I0(address_register[4]), .I1(drive_bus_o2_405), .O(drive_bus_o9_412) ); AND4 drive_bus_o10 ( .I0(address_register[5]), .I1(drive_bus_o3_406), .I2(drive_bus_o4_407), .I3(drive_bus_o5_408), .O(drive_bus_o10_401) ); AND2 drive_bus_o11 ( .I0(drive_bus_o7_410), .I1(drive_bus_o8_411), .O(drive_bus_o11_402) ); AND2 drive_bus_o12 ( .I0(drive_bus_o1_400), .I1(drive_bus_o9_412), .O(drive_bus_o12_403) ); OR2 drive_bus_o13 ( .I0(drive_bus_o12_403), .I1(drive_bus_o10_401), .O(drive_bus_o13_404) ); AND3 drive_bus_o14 ( .I0(drive_bus_o6_409), .I1(drive_bus_o13_404), .I2(drive_bus_o11_402), .O(drive_bus_o) ); AND2 \outgoing_data_o<7>1 ( .I0(address_register[3]), .I1(address_register[2]), .O(\outgoing_data_o<7>1_773 ) ); OR4 \outgoing_data_o<7>2 ( .I0(NlwRenamedSig_OI_faults_o[2]), .I1(NlwRenamedSig_OI_faults_o[3]), .I2(NlwRenamedSig_OI_faults_o[4]), .I3(NlwRenamedSig_OI_faults_o[5]), .O(\outgoing_data_o<7>2_784 ) ); OR2 \outgoing_data_o<7>3 ( .I0(NlwRenamedSig_OI_faults_o[0]), .I1(NlwRenamedSig_OI_faults_o[1]), .O(\outgoing_data_o<7>3_789 ) ); INV \outgoing_data_o<7>4 ( .I(NlwRenamedSig_OI_resample_o), .O(\outgoing_data_o<7>4_790 ) ); INV \outgoing_data_o<7>5 ( .I(address_register[0]), .O(\outgoing_data_o<7>5_791 ) ); INV \outgoing_data_o<7>6 ( .I(address_register[5]), .O(\outgoing_data_o<7>6_792 ) ); AND2 \outgoing_data_o<7>7 ( .I0(address_register[5]), .I1(diagnostic_register[7]), .O(\outgoing_data_o<7>7_793 ) ); INV \outgoing_data_o<7>8 ( .I(address_register[2]), .O(\outgoing_data_o<7>8_794 ) ); INV \outgoing_data_o<7>9 ( .I(address_register[0]), .O(\outgoing_data_o<7>9_795 ) ); INV \outgoing_data_o<7>10 ( .I(address_register[3]), .O(\outgoing_data_o<7>10_774 ) ); INV \outgoing_data_o<7>11 ( .I(address_register[4]), .O(\outgoing_data_o<7>11_775 ) ); INV \outgoing_data_o<7>12 ( .I(address_register[1]), .O(\outgoing_data_o<7>12_776 ) ); AND2 \outgoing_data_o<7>13 ( .I0(NlwRenamedSig_OI_resample_o), .I1(\outgoing_data_o<7>2_784 ), .O(\outgoing_data_o<7>13_777 ) ); AND2 \outgoing_data_o<7>14 ( .I0(\outgoing_data_o<7>3_789 ), .I1(\outgoing_data_o<7>4_790 ), .O(\outgoing_data_o<7>14_778 ) ); AND2 \outgoing_data_o<7>15 ( .I0(\outgoing_data_o<7>8_794 ), .I1(\outgoing_data_o<7>9_795 ), .O(\outgoing_data_o<7>15_779 ) ); AND2 \outgoing_data_o<7>16 ( .I0(\outgoing_data_o<7>10_774 ), .I1(\outgoing_data_o<7>11_775 ), .O(\outgoing_data_o<7>16_780 ) ); OR3 \outgoing_data_o<7>17 ( .I0(\outgoing_data_o<7>13_777 ), .I1(NlwRenamedSig_OI_faults_o[6]), .I2(\outgoing_data_o<7>14_778 ), .O(\outgoing_data_o<7>17_781 ) ); AND3 \outgoing_data_o<7>18 ( .I0(\outgoing_data_o<7>15_779 ), .I1(\outgoing_data_o<7>7_793 ), .I2(\outgoing_data_o<7>16_780 ), .O(\outgoing_data_o<7>18_782 ) ); AND2 \outgoing_data_o<7>19 ( .I0(\outgoing_data_o<7>17_781 ), .I1(\outgoing_data_o<7>5_791 ), .O(\outgoing_data_o<7>19_783 ) ); OR2 \outgoing_data_o<7>20 ( .I0(NlwRenamedSig_OI_faults_o[7]), .I1(\outgoing_data_o<7>19_783 ), .O(\outgoing_data_o<7>20_785 ) ); AND2 \outgoing_data_o<7>21 ( .I0(address_register[4]), .I1(\outgoing_data_o<7>20_785 ), .O(\outgoing_data_o<7>21_786 ) ); AND3 \outgoing_data_o<7>22 ( .I0(\outgoing_data_o<7>21_786 ), .I1(\outgoing_data_o<7>1_773 ), .I2(\outgoing_data_o<7>6_792 ), .O(\outgoing_data_o<7>22_787 ) ); OR2 \outgoing_data_o<7>23 ( .I0(\outgoing_data_o<7>22_787 ), .I1(\outgoing_data_o<7>18_782 ), .O(\outgoing_data_o<7>23_788 ) ); AND2 \outgoing_data_o<7>24 ( .I0(\outgoing_data_o<7>23_788 ), .I1(\outgoing_data_o<7>12_776 ), .O(outgoing_data_o[7]) ); INV faults_1_not00011 ( .I(NlwRenamedSig_OI_motors_disabled_o), .O(faults_1_not00011_444) ); AND2 faults_1_not00012 ( .I0(faults_i[1]), .I1(faults_1_not00011_444), .O(faults_1_not00012_445) ); OR2 faults_1_not00013 ( .I0(faults_1_and0001), .I1(faults_1_not00012_445), .O(faults_1_not0001) ); INV faults_0_not00011 ( .I(NlwRenamedSig_OI_motors_disabled_o), .O(faults_0_not00011_429) ); AND2 faults_0_not00012 ( .I0(faults_i[0]), .I1(faults_0_not00011_429), .O(faults_0_not00012_430) ); OR2 faults_0_not00013 ( .I0(faults_0_and0001), .I1(faults_0_not00012_430), .O(faults_0_not0001) ); INV faults_2_not00011 ( .I(NlwRenamedSig_OI_motors_disabled_o), .O(faults_2_not00011_459) ); AND2 faults_2_not00012 ( .I0(faults_i[2]), .I1(faults_2_not00011_459), .O(faults_2_not00012_460) ); OR2 faults_2_not00013 ( .I0(faults_2_and0001), .I1(faults_2_not00012_460), .O(faults_2_not0001) ); INV faults_3_not00011 ( .I(NlwRenamedSig_OI_motors_disabled_o), .O(faults_3_not00011_474) ); AND2 faults_3_not00012 ( .I0(faults_i[3]), .I1(faults_3_not00011_474), .O(faults_3_not00012_475) ); OR2 faults_3_not00013 ( .I0(faults_3_and0001), .I1(faults_3_not00012_475), .O(faults_3_not0001) ); INV faults_4_not00011 ( .I(NlwRenamedSig_OI_motors_disabled_o), .O(faults_4_not00011_489) ); AND2 faults_4_not00012 ( .I0(faults_i[4]), .I1(faults_4_not00011_489), .O(faults_4_not00012_490) ); OR2 faults_4_not00013 ( .I0(faults_4_and0001), .I1(faults_4_not00012_490), .O(faults_4_not0001) ); INV faults_5_not00011 ( .I(NlwRenamedSig_OI_motors_disabled_o), .O(faults_5_not00011_504) ); AND2 faults_5_not00012 ( .I0(faults_i[5]), .I1(faults_5_not00011_504), .O(faults_5_not00012_505) ); OR2 faults_5_not00013 ( .I0(faults_5_and0001), .I1(faults_5_not00012_505), .O(faults_5_not0001) ); INV faults_6_not00011 ( .I(NlwRenamedSig_OI_motors_disabled_o), .O(faults_6_not00011_519) ); AND2 faults_6_not00012 ( .I0(faults_i[6]), .I1(faults_6_not00011_519), .O(faults_6_not00012_520) ); OR2 faults_6_not00013 ( .I0(faults_6_and0001), .I1(faults_6_not00012_520), .O(faults_6_not0001) ); INV faults_7_not00011 ( .I(NlwRenamedSig_OI_motors_disabled_o), .O(faults_7_not00011_534) ); AND2 faults_7_not00012 ( .I0(faults_i[7]), .I1(faults_7_not00011_534), .O(faults_7_not00012_535) ); OR2 faults_7_not00013 ( .I0(faults_7_and0001), .I1(faults_7_not00012_535), .O(faults_7_not0001) ); INV warnings_0_not00011 ( .I(NlwRenamedSig_OI_motors_disabled_o), .O(warnings_0_not00011_830) ); AND2 warnings_0_not00012 ( .I0(switches_i[0]), .I1(warnings_0_not00011_830), .O(warnings_0_not00012_831) ); OR2 warnings_0_not00013 ( .I0(warnings_0_and0001), .I1(warnings_0_not00012_831), .O(warnings_0_not0001) ); INV warnings_1_not00011 ( .I(NlwRenamedSig_OI_motors_disabled_o), .O(warnings_1_not00011_846) ); AND2 warnings_1_not00012 ( .I0(switches_i[1]), .I1(warnings_1_not00011_846), .O(warnings_1_not00012_847) ); OR2 warnings_1_not00013 ( .I0(warnings_1_and0001), .I1(warnings_1_not00012_847), .O(warnings_1_not0001) ); INV warnings_2_not00011 ( .I(NlwRenamedSig_OI_motors_disabled_o), .O(warnings_2_not00011_862) ); AND2 warnings_2_not00012 ( .I0(switches_i[2]), .I1(warnings_2_not00011_862), .O(warnings_2_not00012_863) ); OR2 warnings_2_not00013 ( .I0(warnings_2_and0001), .I1(warnings_2_not00012_863), .O(warnings_2_not0001) ); INV warnings_3_not00011 ( .I(NlwRenamedSig_OI_motors_disabled_o), .O(warnings_3_not00011_878) ); AND2 warnings_3_not00012 ( .I0(switches_i[3]), .I1(warnings_3_not00011_878), .O(warnings_3_not00012_879) ); OR2 warnings_3_not00013 ( .I0(warnings_3_and0001), .I1(warnings_3_not00012_879), .O(warnings_3_not0001) ); INV warnings_4_not00011 ( .I(NlwRenamedSig_OI_motors_disabled_o), .O(warnings_4_not00011_894) ); AND2 warnings_4_not00012 ( .I0(switches_i[4]), .I1(warnings_4_not00011_894), .O(warnings_4_not00012_895) ); OR2 warnings_4_not00013 ( .I0(warnings_4_and0001), .I1(warnings_4_not00012_895), .O(warnings_4_not0001) ); INV warnings_5_not00011 ( .I(NlwRenamedSig_OI_motors_disabled_o), .O(warnings_5_not00011_910) ); AND2 warnings_5_not00012 ( .I0(switches_i[5]), .I1(warnings_5_not00011_910), .O(warnings_5_not00012_911) ); OR2 warnings_5_not00013 ( .I0(warnings_5_and0001), .I1(warnings_5_not00012_911), .O(warnings_5_not0001) ); XOR2 \address_register_Madd__add0000_Mxor_Result<7>/Xo<0>1 ( .I0(address_register[7]), .I1(address_register_Madd__add0000__and0005), .O(address_register__add0000[7]) ); XOR2 \address_register_Madd__add0000_Mxor_Result<6>/Xo<0>1 ( .I0(address_register[6]), .I1(address_register_Madd__add0000__and0004), .O(address_register__add0000[6]) ); XOR2 \address_register_Madd__add0000_Mxor_Result<5>/Xo<0>1 ( .I0(address_register[5]), .I1(address_register_Madd__add0000__and0003), .O(address_register__add0000[5]) ); XOR2 \address_register_Madd__add0000_Mxor_Result<4>/Xo<0>1 ( .I0(address_register[4]), .I1(address_register_Madd__add0000__and0002), .O(address_register__add0000[4]) ); XOR2 \address_register_Madd__add0000_Mxor_Result<3>/Xo<0>1 ( .I0(address_register[3]), .I1(address_register_Madd__add0000__and0001), .O(address_register__add0000[3]) ); XOR2 \address_register_Madd__add0000_Mxor_Result<2>/Xo<0>1 ( .I0(address_register[2]), .I1(address_register_Madd__add0000__and0000), .O(address_register__add0000[2]) ); XOR2 \address_register_Madd__add0000_Mxor_Result<1>/Xo<0>1 ( .I0(address_register[1]), .I1(address_register[0]), .O(address_register__add0000[1]) ); endmodule module resynchronizer_h_INST_2 ( reset_i, clean_o, clock_i, raw_i ); input reset_i; output clean_o; input clock_i; input raw_i; wire clean_o_N0; wire delayed_244; FDP clean_o_166 ( .C(clean_o_N0), .D(delayed_244), .PRE(reset_i), .Q(clean_o) ); FDP delayed ( .C(clean_o_N0), .D(raw_i), .PRE(reset_i), .Q(delayed_244) ); INV clean_o_N01 ( .I(clock_i), .O(clean_o_N0) ); endmodule module resynchronizer_INST_17 ( reset_i, clean_o, clock_i, raw_i ); input reset_i; output clean_o; input clock_i; input raw_i; wire clean_o_N0; wire delayed_238; FDC clean_o_162 ( .CLR(reset_i), .C(clean_o_N0), .D(delayed_238), .Q(clean_o) ); FDC delayed ( .CLR(reset_i), .C(clean_o_N0), .D(raw_i), .Q(delayed_238) ); INV clean_o_N01 ( .I(clock_i), .O(clean_o_N0) ); endmodule module resynchronizer_INST_16 ( reset_i, clean_o, clock_i, raw_i ); input reset_i; output clean_o; input clock_i; input raw_i; wire clean_o_N0; wire delayed_232; FDC clean_o_158 ( .CLR(reset_i), .C(clean_o_N0), .D(delayed_232), .Q(clean_o) ); FDC delayed ( .CLR(reset_i), .C(clean_o_N0), .D(raw_i), .Q(delayed_232) ); INV clean_o_N01 ( .I(clock_i), .O(clean_o_N0) ); endmodule module resynchronizer_INST_15 ( reset_i, clean_o, clock_i, raw_i ); input reset_i; output clean_o; input clock_i; input raw_i; wire clean_o_N0; wire delayed_226; FDC clean_o_154 ( .CLR(reset_i), .C(clean_o_N0), .D(delayed_226), .Q(clean_o) ); FDC delayed ( .CLR(reset_i), .C(clean_o_N0), .D(raw_i), .Q(delayed_226) ); INV clean_o_N01 ( .I(clock_i), .O(clean_o_N0) ); endmodule module resynchronizer_INST_14 ( reset_i, clean_o, clock_i, raw_i ); input reset_i; output clean_o; input clock_i; input raw_i; wire clean_o_N0; wire delayed_220; FDC clean_o_150 ( .CLR(reset_i), .C(clean_o_N0), .D(delayed_220), .Q(clean_o) ); FDC delayed ( .CLR(reset_i), .C(clean_o_N0), .D(raw_i), .Q(delayed_220) ); INV clean_o_N01 ( .I(clock_i), .O(clean_o_N0) ); endmodule module resynchronizer_INST_13 ( reset_i, clean_o, clock_i, raw_i ); input reset_i; output clean_o; input clock_i; input raw_i; wire clean_o_N0; wire delayed_214; FDC clean_o_146 ( .CLR(reset_i), .C(clean_o_N0), .D(delayed_214), .Q(clean_o) ); FDC delayed ( .CLR(reset_i), .C(clean_o_N0), .D(raw_i), .Q(delayed_214) ); INV clean_o_N01 ( .I(clock_i), .O(clean_o_N0) ); endmodule module resynchronizer_INST_12 ( reset_i, clean_o, clock_i, raw_i ); input reset_i; output clean_o; input clock_i; input raw_i; wire clean_o_N0; wire delayed_208; FDC clean_o_142 ( .CLR(reset_i), .C(clean_o_N0), .D(delayed_208), .Q(clean_o) ); FDC delayed ( .CLR(reset_i), .C(clean_o_N0), .D(raw_i), .Q(delayed_208) ); INV clean_o_N01 ( .I(clock_i), .O(clean_o_N0) ); endmodule module warning_logic_INST_2 ( position_o, smclk_i, aclk_i, reset_wrt_smclk_i, raw_comparator_1_i, raw_comparator_2_i, raw_comparator_3_i, reset_wrt_aclk_i, warning_o, status_o ); output position_o; input smclk_i; input aclk_i; input reset_wrt_smclk_i; input raw_comparator_1_i; input raw_comparator_2_i; input raw_comparator_3_i; input reset_wrt_aclk_i; output warning_o; output [1 : 0] status_o; wire debounced_comparator_1; wire debounced_comparator_2; wire debounced_comparator_3; wire position; wire position_cmp_eq0000; wire position_cmp_eq00001_253; wire \status<0>1_262 ; wire \status<0>2_263 ; wire \status<0>3_264 ; wire \status<1>1_266 ; wire \status<1>2_267 ; wire warning; wire warning1_271; wire [1 : 0] status; resynchronizer_INST_12 rs_status_0 ( .reset_i(reset_wrt_smclk_i), .clean_o(status_o[0]), .clock_i(smclk_i), .raw_i(status[0]) ); resynchronizer_INST_13 rs_status_1 ( .reset_i(reset_wrt_smclk_i), .clean_o(status_o[1]), .clock_i(smclk_i), .raw_i(status[1]) ); resynchronizer_INST_14 rs_position ( .reset_i(reset_wrt_smclk_i), .clean_o(position_o), .clock_i(smclk_i), .raw_i(position) ); resynchronizer_INST_15 rs_warning ( .reset_i(reset_wrt_smclk_i), .clean_o(warning_o), .clock_i(smclk_i), .raw_i(warning) ); resynchronizer_INST_16 local_2 ( .reset_i(reset_wrt_aclk_i), .clean_o(debounced_comparator_2), .clock_i(aclk_i), .raw_i(raw_comparator_2_i) ); resynchronizer_INST_17 local_1 ( .reset_i(reset_wrt_aclk_i), .clean_o(debounced_comparator_1), .clock_i(aclk_i), .raw_i(raw_comparator_1_i) ); resynchronizer_h_INST_2 local_3 ( .reset_i(reset_wrt_aclk_i), .clean_o(debounced_comparator_3), .clock_i(aclk_i), .raw_i(raw_comparator_3_i) ); INV warning1 ( .I(debounced_comparator_3), .O(warning1_271) ); OR2 warning2 ( .I0(debounced_comparator_1), .I1(warning1_271), .O(warning) ); AND2 position_cmp_eq00001 ( .I0(debounced_comparator_2), .I1(debounced_comparator_3), .O(position_cmp_eq0000) ); INV position_cmp_eq00002 ( .I(debounced_comparator_1), .O(position_cmp_eq00001_253) ); AND2 position_cmp_eq00003 ( .I0(position_cmp_eq0000), .I1(position_cmp_eq00001_253), .O(position) ); INV \status<0>1 ( .I(debounced_comparator_2), .O(\status<0>1_262 ) ); INV \status<0>2 ( .I(debounced_comparator_3), .O(\status<0>2_263 ) ); AND2 \status<0>3 ( .I0(debounced_comparator_1), .I1(\status<0>1_262 ), .O(\status<0>3_264 ) ); OR2 \status<0>4 ( .I0(\status<0>3_264 ), .I1(\status<0>2_263 ), .O(status[0]) ); INV \status<1>1 ( .I(debounced_comparator_3), .O(\status<1>1_266 ) ); AND2 \status<1>2 ( .I0(debounced_comparator_2), .I1(\status<1>1_266 ), .O(\status<1>2_267 ) ); OR2 \status<1>3 ( .I0(debounced_comparator_1), .I1(\status<1>2_267 ), .O(status[1]) ); endmodule module resynchronizer_h_INST_1 ( reset_i, clean_o, clock_i, raw_i ); input reset_i; output clean_o; input clock_i; input raw_i; wire clean_o_N0; wire delayed_176; FDP clean_o_125 ( .C(clean_o_N0), .D(delayed_176), .PRE(reset_i), .Q(clean_o) ); FDP delayed ( .C(clean_o_N0), .D(raw_i), .PRE(reset_i), .Q(delayed_176) ); INV clean_o_N01 ( .I(clock_i), .O(clean_o_N0) ); endmodule module resynchronizer_INST_11 ( reset_i, clean_o, clock_i, raw_i ); input reset_i; output clean_o; input clock_i; input raw_i; wire clean_o_N0; wire delayed_170; FDC clean_o_121 ( .CLR(reset_i), .C(clean_o_N0), .D(delayed_170), .Q(clean_o) ); FDC delayed ( .CLR(reset_i), .C(clean_o_N0), .D(raw_i), .Q(delayed_170) ); INV clean_o_N01 ( .I(clock_i), .O(clean_o_N0) ); endmodule module resynchronizer_INST_10 ( reset_i, clean_o, clock_i, raw_i ); input reset_i; output clean_o; input clock_i; input raw_i; wire clean_o_N0; wire delayed_164; FDC clean_o_117 ( .CLR(reset_i), .C(clean_o_N0), .D(delayed_164), .Q(clean_o) ); FDC delayed ( .CLR(reset_i), .C(clean_o_N0), .D(raw_i), .Q(delayed_164) ); INV clean_o_N01 ( .I(clock_i), .O(clean_o_N0) ); endmodule module resynchronizer_INST_9 ( reset_i, clean_o, clock_i, raw_i ); input reset_i; output clean_o; input clock_i; input raw_i; wire clean_o_N0; wire delayed_158; FDC clean_o_113 ( .CLR(reset_i), .C(clean_o_N0), .D(delayed_158), .Q(clean_o) ); FDC delayed ( .CLR(reset_i), .C(clean_o_N0), .D(raw_i), .Q(delayed_158) ); INV clean_o_N01 ( .I(clock_i), .O(clean_o_N0) ); endmodule module resynchronizer_INST_8 ( reset_i, clean_o, clock_i, raw_i ); input reset_i; output clean_o; input clock_i; input raw_i; wire clean_o_N0; wire delayed_152; FDC clean_o_109 ( .CLR(reset_i), .C(clean_o_N0), .D(delayed_152), .Q(clean_o) ); FDC delayed ( .CLR(reset_i), .C(clean_o_N0), .D(raw_i), .Q(delayed_152) ); INV clean_o_N01 ( .I(clock_i), .O(clean_o_N0) ); endmodule module resynchronizer_INST_7 ( reset_i, clean_o, clock_i, raw_i ); input reset_i; output clean_o; input clock_i; input raw_i; wire clean_o_N0; wire delayed_146; FDC clean_o_105 ( .CLR(reset_i), .C(clean_o_N0), .D(delayed_146), .Q(clean_o) ); FDC delayed ( .CLR(reset_i), .C(clean_o_N0), .D(raw_i), .Q(delayed_146) ); INV clean_o_N01 ( .I(clock_i), .O(clean_o_N0) ); endmodule module resynchronizer_INST_6 ( reset_i, clean_o, clock_i, raw_i ); input reset_i; output clean_o; input clock_i; input raw_i; wire clean_o_N0; wire delayed_140; FDC clean_o_101 ( .CLR(reset_i), .C(clean_o_N0), .D(delayed_140), .Q(clean_o) ); FDC delayed ( .CLR(reset_i), .C(clean_o_N0), .D(raw_i), .Q(delayed_140) ); INV clean_o_N01 ( .I(clock_i), .O(clean_o_N0) ); endmodule module warning_logic_INST_1 ( position_o, smclk_i, aclk_i, reset_wrt_smclk_i, raw_comparator_1_i, raw_comparator_2_i, raw_comparator_3_i, reset_wrt_aclk_i, warning_o, status_o ); output position_o; input smclk_i; input aclk_i; input reset_wrt_smclk_i; input raw_comparator_1_i; input raw_comparator_2_i; input raw_comparator_3_i; input reset_wrt_aclk_i; output warning_o; output [1 : 0] status_o; wire debounced_comparator_1; wire debounced_comparator_2; wire debounced_comparator_3; wire position; wire position_cmp_eq0000; wire position_cmp_eq00001_185; wire \status<0>1_194 ; wire \status<0>2_195 ; wire \status<0>3_196 ; wire \status<1>1_198 ; wire \status<1>2_199 ; wire warning; wire warning1_203; wire [1 : 0] status; resynchronizer_INST_6 rs_status_0 ( .reset_i(reset_wrt_smclk_i), .clean_o(status_o[0]), .clock_i(smclk_i), .raw_i(status[0]) ); resynchronizer_INST_7 rs_status_1 ( .reset_i(reset_wrt_smclk_i), .clean_o(status_o[1]), .clock_i(smclk_i), .raw_i(status[1]) ); resynchronizer_INST_8 rs_position ( .reset_i(reset_wrt_smclk_i), .clean_o(position_o), .clock_i(smclk_i), .raw_i(position) ); resynchronizer_INST_9 rs_warning ( .reset_i(reset_wrt_smclk_i), .clean_o(warning_o), .clock_i(smclk_i), .raw_i(warning) ); resynchronizer_INST_10 local_2 ( .reset_i(reset_wrt_aclk_i), .clean_o(debounced_comparator_2), .clock_i(aclk_i), .raw_i(raw_comparator_2_i) ); resynchronizer_INST_11 local_1 ( .reset_i(reset_wrt_aclk_i), .clean_o(debounced_comparator_1), .clock_i(aclk_i), .raw_i(raw_comparator_1_i) ); resynchronizer_h_INST_1 local_3 ( .reset_i(reset_wrt_aclk_i), .clean_o(debounced_comparator_3), .clock_i(aclk_i), .raw_i(raw_comparator_3_i) ); INV warning1 ( .I(debounced_comparator_3), .O(warning1_203) ); OR2 warning2 ( .I0(debounced_comparator_1), .I1(warning1_203), .O(warning) ); AND2 position_cmp_eq00001 ( .I0(debounced_comparator_2), .I1(debounced_comparator_3), .O(position_cmp_eq0000) ); INV position_cmp_eq00002 ( .I(debounced_comparator_1), .O(position_cmp_eq00001_185) ); AND2 position_cmp_eq00003 ( .I0(position_cmp_eq0000), .I1(position_cmp_eq00001_185), .O(position) ); INV \status<0>1 ( .I(debounced_comparator_2), .O(\status<0>1_194 ) ); INV \status<0>2 ( .I(debounced_comparator_3), .O(\status<0>2_195 ) ); AND2 \status<0>3 ( .I0(debounced_comparator_1), .I1(\status<0>1_194 ), .O(\status<0>3_196 ) ); OR2 \status<0>4 ( .I0(\status<0>3_196 ), .I1(\status<0>2_195 ), .O(status[0]) ); INV \status<1>1 ( .I(debounced_comparator_3), .O(\status<1>1_198 ) ); AND2 \status<1>2 ( .I0(debounced_comparator_2), .I1(\status<1>1_198 ), .O(\status<1>2_199 ) ); OR2 \status<1>3 ( .I0(debounced_comparator_1), .I1(\status<1>2_199 ), .O(status[1]) ); endmodule module resynchronizer_h ( reset_i, clean_o, clock_i, raw_i ); input reset_i; output clean_o; input clock_i; input raw_i; wire clean_o_N0; wire delayed_108; FDP clean_o_84 ( .C(clean_o_N0), .D(delayed_108), .PRE(reset_i), .Q(clean_o) ); FDP delayed ( .C(clean_o_N0), .D(raw_i), .PRE(reset_i), .Q(delayed_108) ); INV clean_o_N01 ( .I(clock_i), .O(clean_o_N0) ); endmodule module resynchronizer_INST_5 ( reset_i, clean_o, clock_i, raw_i ); input reset_i; output clean_o; input clock_i; input raw_i; wire clean_o_N0; wire delayed_102; FDC clean_o_80 ( .CLR(reset_i), .C(clean_o_N0), .D(delayed_102), .Q(clean_o) ); FDC delayed ( .CLR(reset_i), .C(clean_o_N0), .D(raw_i), .Q(delayed_102) ); INV clean_o_N01 ( .I(clock_i), .O(clean_o_N0) ); endmodule module resynchronizer_INST_4 ( reset_i, clean_o, clock_i, raw_i ); input reset_i; output clean_o; input clock_i; input raw_i; wire clean_o_N0; wire delayed_96; FDC clean_o_76 ( .CLR(reset_i), .C(clean_o_N0), .D(delayed_96), .Q(clean_o) ); FDC delayed ( .CLR(reset_i), .C(clean_o_N0), .D(raw_i), .Q(delayed_96) ); INV clean_o_N01 ( .I(clock_i), .O(clean_o_N0) ); endmodule module resynchronizer_INST_3 ( reset_i, clean_o, clock_i, raw_i ); input reset_i; output clean_o; input clock_i; input raw_i; wire clean_o_N0; wire delayed_90; FDC clean_o_72 ( .CLR(reset_i), .C(clean_o_N0), .D(delayed_90), .Q(clean_o) ); FDC delayed ( .CLR(reset_i), .C(clean_o_N0), .D(raw_i), .Q(delayed_90) ); INV clean_o_N01 ( .I(clock_i), .O(clean_o_N0) ); endmodule module resynchronizer_INST_2 ( reset_i, clean_o, clock_i, raw_i ); input reset_i; output clean_o; input clock_i; input raw_i; wire clean_o_N0; wire delayed_84; FDC clean_o_68 ( .CLR(reset_i), .C(clean_o_N0), .D(delayed_84), .Q(clean_o) ); FDC delayed ( .CLR(reset_i), .C(clean_o_N0), .D(raw_i), .Q(delayed_84) ); INV clean_o_N01 ( .I(clock_i), .O(clean_o_N0) ); endmodule module resynchronizer_INST_1 ( reset_i, clean_o, clock_i, raw_i ); input reset_i; output clean_o; input clock_i; input raw_i; wire clean_o_N0; wire delayed_78; FDC clean_o_64 ( .CLR(reset_i), .C(clean_o_N0), .D(delayed_78), .Q(clean_o) ); FDC delayed ( .CLR(reset_i), .C(clean_o_N0), .D(raw_i), .Q(delayed_78) ); INV clean_o_N01 ( .I(clock_i), .O(clean_o_N0) ); endmodule module resynchronizer ( reset_i, clean_o, clock_i, raw_i ); input reset_i; output clean_o; input clock_i; input raw_i; wire clean_o_N0; wire delayed_72; FDC clean_o_60 ( .CLR(reset_i), .C(clean_o_N0), .D(delayed_72), .Q(clean_o) ); FDC delayed ( .CLR(reset_i), .C(clean_o_N0), .D(raw_i), .Q(delayed_72) ); INV clean_o_N01 ( .I(clock_i), .O(clean_o_N0) ); endmodule module warning_logic ( position_o, smclk_i, aclk_i, reset_wrt_smclk_i, raw_comparator_1_i, raw_comparator_2_i, raw_comparator_3_i, reset_wrt_aclk_i, warning_o, status_o ); output position_o; input smclk_i; input aclk_i; input reset_wrt_smclk_i; input raw_comparator_1_i; input raw_comparator_2_i; input raw_comparator_3_i; input reset_wrt_aclk_i; output warning_o; output [1 : 0] status_o; wire debounced_comparator_1; wire debounced_comparator_2; wire debounced_comparator_3; wire position; wire position_cmp_eq0000; wire position_cmp_eq00001_117; wire \status<0>1_126 ; wire \status<0>2_127 ; wire \status<0>3_128 ; wire \status<1>1_130 ; wire \status<1>2_131 ; wire warning; wire warning1_135; wire [1 : 0] status; resynchronizer rs_status_0 ( .reset_i(reset_wrt_smclk_i), .clean_o(status_o[0]), .clock_i(smclk_i), .raw_i(status[0]) ); resynchronizer_INST_1 rs_status_1 ( .reset_i(reset_wrt_smclk_i), .clean_o(status_o[1]), .clock_i(smclk_i), .raw_i(status[1]) ); resynchronizer_INST_2 rs_position ( .reset_i(reset_wrt_smclk_i), .clean_o(position_o), .clock_i(smclk_i), .raw_i(position) ); resynchronizer_INST_3 rs_warning ( .reset_i(reset_wrt_smclk_i), .clean_o(warning_o), .clock_i(smclk_i), .raw_i(warning) ); resynchronizer_INST_4 local_2 ( .reset_i(reset_wrt_aclk_i), .clean_o(debounced_comparator_2), .clock_i(aclk_i), .raw_i(raw_comparator_2_i) ); resynchronizer_INST_5 local_1 ( .reset_i(reset_wrt_aclk_i), .clean_o(debounced_comparator_1), .clock_i(aclk_i), .raw_i(raw_comparator_1_i) ); resynchronizer_h local_3 ( .reset_i(reset_wrt_aclk_i), .clean_o(debounced_comparator_3), .clock_i(aclk_i), .raw_i(raw_comparator_3_i) ); INV warning1 ( .I(debounced_comparator_3), .O(warning1_135) ); OR2 warning2 ( .I0(debounced_comparator_1), .I1(warning1_135), .O(warning) ); AND2 position_cmp_eq00001 ( .I0(debounced_comparator_2), .I1(debounced_comparator_3), .O(position_cmp_eq0000) ); INV position_cmp_eq00002 ( .I(debounced_comparator_1), .O(position_cmp_eq00001_117) ); AND2 position_cmp_eq00003 ( .I0(position_cmp_eq0000), .I1(position_cmp_eq00001_117), .O(position) ); INV \status<0>1 ( .I(debounced_comparator_2), .O(\status<0>1_126 ) ); INV \status<0>2 ( .I(debounced_comparator_3), .O(\status<0>2_127 ) ); AND2 \status<0>3 ( .I0(debounced_comparator_1), .I1(\status<0>1_126 ), .O(\status<0>3_128 ) ); OR2 \status<0>4 ( .I0(\status<0>3_128 ), .I1(\status<0>2_127 ), .O(status[0]) ); INV \status<1>1 ( .I(debounced_comparator_3), .O(\status<1>1_130 ) ); AND2 \status<1>2 ( .I0(debounced_comparator_2), .I1(\status<1>1_130 ), .O(\status<1>2_131 ) ); OR2 \status<1>3 ( .I0(debounced_comparator_1), .I1(\status<1>2_131 ), .O(status[1]) ); endmodule module low_pass_filter_INST_4 ( reset_i, clean_o, clock_i, raw_i ); input reset_i; output clean_o; input clock_i; input raw_i; wire delayed_0_N0; wire jk; wire [4 : 0] delayed; FDC q ( .CLR(reset_i), .C(delayed_0_N0), .D(jk), .Q(clean_o) ); FDC delayed_0 ( .CLR(reset_i), .C(delayed_0_N0), .D(raw_i), .Q(delayed[0]) ); FDC delayed_1 ( .CLR(reset_i), .C(delayed_0_N0), .D(delayed[0]), .Q(delayed[1]) ); FDC delayed_2 ( .CLR(reset_i), .C(delayed_0_N0), .D(delayed[1]), .Q(delayed[2]) ); FDC delayed_3 ( .CLR(reset_i), .C(delayed_0_N0), .D(delayed[2]), .Q(delayed[3]) ); FDC delayed_4 ( .CLR(reset_i), .C(delayed_0_N0), .D(delayed[3]), .Q(delayed[4]) ); INV delayed_0_N01 ( .I(clock_i), .O(delayed_0_N0) ); AND3 jk11 ( .I0(delayed[2]), .I1(delayed[3]), .I2(delayed[4]), .O(jk) ); endmodule module low_pass_filter_INST_3 ( reset_i, clean_o, clock_i, raw_i ); input reset_i; output clean_o; input clock_i; input raw_i; wire delayed_0_N0; wire jk; wire [4 : 0] delayed; FDC q ( .CLR(reset_i), .C(delayed_0_N0), .D(jk), .Q(clean_o) ); FDC delayed_0 ( .CLR(reset_i), .C(delayed_0_N0), .D(raw_i), .Q(delayed[0]) ); FDC delayed_1 ( .CLR(reset_i), .C(delayed_0_N0), .D(delayed[0]), .Q(delayed[1]) ); FDC delayed_2 ( .CLR(reset_i), .C(delayed_0_N0), .D(delayed[1]), .Q(delayed[2]) ); FDC delayed_3 ( .CLR(reset_i), .C(delayed_0_N0), .D(delayed[2]), .Q(delayed[3]) ); FDC delayed_4 ( .CLR(reset_i), .C(delayed_0_N0), .D(delayed[3]), .Q(delayed[4]) ); INV delayed_0_N01 ( .I(clock_i), .O(delayed_0_N0) ); AND3 jk11 ( .I0(delayed[2]), .I1(delayed[3]), .I2(delayed[4]), .O(jk) ); endmodule module low_pass_filter_INST_2 ( reset_i, clean_o, clock_i, raw_i ); input reset_i; output clean_o; input clock_i; input raw_i; wire delayed_0_N0; wire jk; wire [4 : 0] delayed; FDC q ( .CLR(reset_i), .C(delayed_0_N0), .D(jk), .Q(clean_o) ); FDC delayed_0 ( .CLR(reset_i), .C(delayed_0_N0), .D(raw_i), .Q(delayed[0]) ); FDC delayed_1 ( .CLR(reset_i), .C(delayed_0_N0), .D(delayed[0]), .Q(delayed[1]) ); FDC delayed_2 ( .CLR(reset_i), .C(delayed_0_N0), .D(delayed[1]), .Q(delayed[2]) ); FDC delayed_3 ( .CLR(reset_i), .C(delayed_0_N0), .D(delayed[2]), .Q(delayed[3]) ); FDC delayed_4 ( .CLR(reset_i), .C(delayed_0_N0), .D(delayed[3]), .Q(delayed[4]) ); INV delayed_0_N01 ( .I(clock_i), .O(delayed_0_N0) ); AND3 jk11 ( .I0(delayed[2]), .I1(delayed[3]), .I2(delayed[4]), .O(jk) ); endmodule module low_pass_filter_INST_1 ( reset_i, clean_o, clock_i, raw_i ); input reset_i; output clean_o; input clock_i; input raw_i; wire delayed_0_N0; wire jk; wire [4 : 0] delayed; FDC q ( .CLR(reset_i), .C(delayed_0_N0), .D(jk), .Q(clean_o) ); FDC delayed_0 ( .CLR(reset_i), .C(delayed_0_N0), .D(raw_i), .Q(delayed[0]) ); FDC delayed_1 ( .CLR(reset_i), .C(delayed_0_N0), .D(delayed[0]), .Q(delayed[1]) ); FDC delayed_2 ( .CLR(reset_i), .C(delayed_0_N0), .D(delayed[1]), .Q(delayed[2]) ); FDC delayed_3 ( .CLR(reset_i), .C(delayed_0_N0), .D(delayed[2]), .Q(delayed[3]) ); FDC delayed_4 ( .CLR(reset_i), .C(delayed_0_N0), .D(delayed[3]), .Q(delayed[4]) ); INV delayed_0_N01 ( .I(clock_i), .O(delayed_0_N0) ); AND3 jk11 ( .I0(delayed[2]), .I1(delayed[3]), .I2(delayed[4]), .O(jk) ); endmodule module low_pass_filter ( reset_i, clean_o, clock_i, raw_i ); input reset_i; output clean_o; input clock_i; input raw_i; wire delayed_0_N0; wire jk; wire [4 : 0] delayed; FDC q ( .CLR(reset_i), .C(delayed_0_N0), .D(jk), .Q(clean_o) ); FDC delayed_0 ( .CLR(reset_i), .C(delayed_0_N0), .D(raw_i), .Q(delayed[0]) ); FDC delayed_1 ( .CLR(reset_i), .C(delayed_0_N0), .D(delayed[0]), .Q(delayed[1]) ); FDC delayed_2 ( .CLR(reset_i), .C(delayed_0_N0), .D(delayed[1]), .Q(delayed[2]) ); FDC delayed_3 ( .CLR(reset_i), .C(delayed_0_N0), .D(delayed[2]), .Q(delayed[3]) ); FDC delayed_4 ( .CLR(reset_i), .C(delayed_0_N0), .D(delayed[3]), .Q(delayed[4]) ); INV delayed_0_N01 ( .I(clock_i), .O(delayed_0_N0) ); AND3 jk11 ( .I0(delayed[2]), .I1(delayed[3]), .I2(delayed[4]), .O(jk) ); endmodule module reset_synchronizer_INST_1 ( async_reset_i, sync_reset_o, clock_i ); input async_reset_i; output sync_reset_o; input clock_i; wire N0; wire reset_delayed_10; wire reset_delayed_N0; wire reset_delayed_N1; GND XST_GND ( .G(N0) ); FDP sync_reset_o_9 ( .C(reset_delayed_N0), .D(reset_delayed_10), .PRE(reset_delayed_N1), .Q(sync_reset_o) ); FDP reset_delayed ( .C(reset_delayed_N0), .D(N0), .PRE(reset_delayed_N1), .Q(reset_delayed_10) ); INV reset_delayed_N11 ( .I(async_reset_i), .O(reset_delayed_N1) ); INV reset_delayed_N01 ( .I(clock_i), .O(reset_delayed_N0) ); endmodule module reset_synchronizer ( async_reset_i, sync_reset_o, clock_i ); input async_reset_i; output sync_reset_o; input clock_i; wire N0; wire reset_delayed_3; wire reset_delayed_N0; wire reset_delayed_N1; GND XST_GND ( .G(N0) ); FDP sync_reset_o_3 ( .C(reset_delayed_N0), .D(reset_delayed_3), .PRE(reset_delayed_N1), .Q(sync_reset_o) ); FDP reset_delayed ( .C(reset_delayed_N0), .D(N0), .PRE(reset_delayed_N1), .Q(reset_delayed_3) ); INV reset_delayed_N11 ( .I(async_reset_i), .O(reset_delayed_N1) ); INV reset_delayed_N01 ( .I(clock_i), .O(reset_delayed_N0) ); endmodule module dpress ( water_in_air_n_ipad, local_burst_comp_1_ipad, local_squeeze_comp_3_ipad, local_squeeze_opad, wr_n_ipad, local_empty_comp_1_ipad, bus_reset_n_ipad, ch1_rls_n_opad, water_alarm_enable_n_opad, rd_n_ipad, ch1_home_n_opad, baclk_ipad, local_burst_comp_2_ipad, ch1_fls_n_opad, local_empty_comp_2_ipad, pressure_sensor_enable_n_opad, local_burst_comp_3_ipad, local_empty_comp_3_ipad, pressure_sensor_select_opad, remote_burst_ipad, remote_empty_ipad, local_burst_opad, ch0_rls_n_opad, local_empty_opad, as_n_ipad, local_squeeze_comp_1_ipad, remote_squeeze_ipad, water_in_oil_n_ipad, ch0_fls_n_opad, ch0_home_n_opad, bsmclk_ipad, local_squeeze_comp_2_ipad, ad_iopad ); input water_in_air_n_ipad; input local_burst_comp_1_ipad; input local_squeeze_comp_3_ipad; output local_squeeze_opad; input wr_n_ipad; input local_empty_comp_1_ipad; input bus_reset_n_ipad; output ch1_rls_n_opad; output water_alarm_enable_n_opad; input rd_n_ipad; output ch1_home_n_opad; input baclk_ipad; input local_burst_comp_2_ipad; output ch1_fls_n_opad; input local_empty_comp_2_ipad; output pressure_sensor_enable_n_opad; input local_burst_comp_3_ipad; input local_empty_comp_3_ipad; output pressure_sensor_select_opad; input remote_burst_ipad; input remote_empty_ipad; output local_burst_opad; output ch0_rls_n_opad; output local_empty_opad; input as_n_ipad; input local_squeeze_comp_1_ipad; input remote_squeeze_ipad; input water_in_oil_n_ipad; output ch0_fls_n_opad; output ch0_home_n_opad; input bsmclk_ipad; input local_squeeze_comp_2_ipad; inout [7 : 0] ad_iopad; wire N0; wire N1; wire N21; wire N31; wire N4; wire N5; wire N6; wire N7; wire as_n_ipad_IBUF_935; wire baclk_ipad_IBUF_937; wire bsmclk_ipad_IBUF_939; wire bus_reset_n_ipad_IBUF_941; wire ch0_fls_n_opad1_943; wire ch0_fls_n_opad2_944; wire ch0_fls_n_opad3_945; wire ch0_fls_n_opad4_946; wire ch0_fls_n_opad5_947; wire ch0_fls_n_opad6_948; wire ch0_fls_n_opad7_949; wire ch0_fls_n_opad8_950; wire ch0_fls_n_opad_OBUF_951; wire ch0_home; wire ch0_home1_953; wire ch0_home_n_opad_OBUF_955; wire ch0_rls_n_opad1_957; wire ch0_rls_n_opad2_958; wire ch0_rls_n_opad3_959; wire ch0_rls_n_opad4_960; wire ch0_rls_n_opad5_961; wire ch0_rls_n_opad6_962; wire ch0_rls_n_opad7_963; wire ch0_rls_n_opad8_964; wire ch0_rls_n_opad_OBUF_965; wire ch1_fls_n_opad1_967; wire ch1_fls_n_opad2_968; wire ch1_fls_n_opad3_969; wire ch1_fls_n_opad4_970; wire ch1_fls_n_opad5_971; wire ch1_fls_n_opad_OBUF_972; wire ch1_home; wire ch1_home_n_opad_OBUF_975; wire ch1_rls_n_opad1_977; wire ch1_rls_n_opad2_978; wire ch1_rls_n_opad3_979; wire ch1_rls_n_opad4_980; wire ch1_rls_n_opad5_981; wire ch1_rls_n_opad_OBUF_982; wire drive_bus; wire \faults<3>1_988 ; wire faults_0_mux0000; wire faults_0_mux00001_990; wire faults_1_mux0000; wire faults_1_mux00001_992; wire faults_2_mux0000; wire home_configuration; wire intake_exhaust_pump_home; wire intake_exhaust_pump_home1_996; wire intake_exhaust_pump_home2_997; wire intake_exhaust_pump_home3_998; wire local_burst_comp_1_ipad_IBUF_1006; wire local_burst_comp_2_ipad_IBUF_1008; wire local_burst_comp_3_ipad_IBUF_1010; wire local_burst_opad_OBUF_1012; wire local_burst_warning; wire local_empty_comp_1_ipad_IBUF_1017; wire local_empty_comp_2_ipad_IBUF_1019; wire local_empty_comp_3_ipad_IBUF_1021; wire local_empty_opad_OBUF_1023; wire local_empty_warning; wire local_squeeze_comp_1_ipad_IBUF_1028; wire local_squeeze_comp_2_ipad_IBUF_1030; wire local_squeeze_comp_3_ipad_IBUF_1032; wire local_squeeze_opad_OBUF_1034; wire local_squeeze_warning; wire lpf_water_in_air_not0000; wire lpf_water_in_oil_not0000; wire motors_disabled; wire pressure_sensor_enable; wire pressure_sensor_enable_n_opad_OBUF_1051; wire pressure_sensor_select_opad_OBUF_1053; wire rd_n_ipad_IBUF_1055; wire remote_burst; wire remote_burst_ipad_IBUF_1058; wire remote_empty; wire remote_empty_ipad_IBUF_1061; wire remote_squeeze; wire remote_squeeze_ipad_IBUF_1064; wire resample; wire smclk_reset_synch_not0000; wire synced_reset; wire synced_reset_wrt_aclk; wire water_alarm_enable; wire water_alarm_enable_n_opad_OBUF_1071; wire water_faults; wire water_in_air; wire water_in_air_n_ipad_IBUF_1075; wire water_in_oil; wire water_in_oil_n_ipad_IBUF_1078; wire wr_n_ipad_IBUF_1080; wire \NLW_msp430_io_faults_o<7>_UNCONNECTED ; wire \NLW_msp430_io_faults_o<6>_UNCONNECTED ; wire [3 : 0] faults; wire [5 : 0] latched_faults; wire [1 : 0] local_burst_switch_status; wire [1 : 0] local_empty_switch_status; wire [1 : 0] local_squeeze_switch_status; wire [7 : 0] outgoing_data; reset_synchronizer aclk_reset_synch ( .async_reset_i(bus_reset_n_ipad_IBUF_941), .sync_reset_o(synced_reset_wrt_aclk), .clock_i(baclk_ipad_IBUF_937) ); reset_synchronizer_INST_1 smclk_reset_synch ( .async_reset_i(smclk_reset_synch_not0000), .sync_reset_o(synced_reset), .clock_i(bsmclk_ipad_IBUF_939) ); low_pass_filter lpf_water_in_oil ( .reset_i(synced_reset_wrt_aclk), .clean_o(water_in_oil), .clock_i(baclk_ipad_IBUF_937), .raw_i(lpf_water_in_oil_not0000) ); low_pass_filter_INST_1 lpf_water_in_air ( .reset_i(synced_reset_wrt_aclk), .clean_o(water_in_air), .clock_i(baclk_ipad_IBUF_937), .raw_i(lpf_water_in_air_not0000) ); low_pass_filter_INST_2 lpf_remote_empty ( .reset_i(synced_reset_wrt_aclk), .clean_o(remote_empty), .clock_i(baclk_ipad_IBUF_937), .raw_i(remote_empty_ipad_IBUF_1061) ); low_pass_filter_INST_3 lpf_remote_squeeze ( .reset_i(synced_reset_wrt_aclk), .clean_o(remote_squeeze), .clock_i(baclk_ipad_IBUF_937), .raw_i(remote_squeeze_ipad_IBUF_1064) ); low_pass_filter_INST_4 lpf_remote_burst ( .reset_i(synced_reset_wrt_aclk), .clean_o(remote_burst), .clock_i(baclk_ipad_IBUF_937), .raw_i(remote_burst_ipad_IBUF_1058) ); warning_logic empty ( .position_o(local_empty_opad_OBUF_1023), .smclk_i(bsmclk_ipad_IBUF_939), .aclk_i(baclk_ipad_IBUF_937), .reset_wrt_smclk_i(synced_reset), .raw_comparator_1_i(local_empty_comp_1_ipad_IBUF_1017), .raw_comparator_2_i(local_empty_comp_2_ipad_IBUF_1019), .raw_comparator_3_i(local_empty_comp_3_ipad_IBUF_1021), .reset_wrt_aclk_i(synced_reset_wrt_aclk), .warning_o(local_empty_warning), .status_o({local_empty_switch_status[1], local_empty_switch_status[0]}) ); warning_logic_INST_1 squeeze ( .position_o(local_squeeze_opad_OBUF_1034), .smclk_i(bsmclk_ipad_IBUF_939), .aclk_i(baclk_ipad_IBUF_937), .reset_wrt_smclk_i(synced_reset), .raw_comparator_1_i(local_squeeze_comp_1_ipad_IBUF_1028), .raw_comparator_2_i(local_squeeze_comp_2_ipad_IBUF_1030), .raw_comparator_3_i(local_squeeze_comp_3_ipad_IBUF_1032), .reset_wrt_aclk_i(synced_reset_wrt_aclk), .warning_o(local_squeeze_warning), .status_o({local_squeeze_switch_status[1], local_squeeze_switch_status[0]}) ); warning_logic_INST_2 burst ( .position_o(local_burst_opad_OBUF_1012), .smclk_i(bsmclk_ipad_IBUF_939), .aclk_i(baclk_ipad_IBUF_937), .reset_wrt_smclk_i(synced_reset), .raw_comparator_1_i(local_burst_comp_1_ipad_IBUF_1006), .raw_comparator_2_i(local_burst_comp_2_ipad_IBUF_1008), .raw_comparator_3_i(local_burst_comp_3_ipad_IBUF_1010), .reset_wrt_aclk_i(synced_reset_wrt_aclk), .warning_o(local_burst_warning), .status_o({local_burst_switch_status[1], local_burst_switch_status[0]}) ); cpu_interface msp430_io ( .reset_i(synced_reset), .water_faults_o(water_faults), .home_configuration_o(home_configuration), .motors_disabled_o(motors_disabled), .water_alarm_enable_o(water_alarm_enable), .rd_n_i(rd_n_ipad_IBUF_1055), .pressure_sensor_enable_o(pressure_sensor_enable), .remote_squeeze_i(remote_squeeze), .clock_i(bsmclk_ipad_IBUF_939), .resample_o(resample), .remote_burst_i(remote_burst), .wr_n_i(wr_n_ipad_IBUF_1080), .as_n_i(as_n_ipad_IBUF_935), .drive_bus_o(drive_bus), .remote_empty_i(remote_empty), .pressure_sensor_select_o(pressure_sensor_select_opad_OBUF_1053), .outgoing_data_o({outgoing_data[7], outgoing_data[6], outgoing_data[5], outgoing_data[4], outgoing_data[3], outgoing_data[2], outgoing_data[1], outgoing_data[0]}), .faults_o({\NLW_msp430_io_faults_o<7>_UNCONNECTED , \NLW_msp430_io_faults_o<6>_UNCONNECTED , latched_faults[5], latched_faults[4], latched_faults[3], latched_faults[2], latched_faults[1], latched_faults[0]}), .emptys_i({local_empty_comp_1_ipad_IBUF_1017, local_empty_comp_2_ipad_IBUF_1019, local_empty_comp_3_ipad_IBUF_1021}), .faults_i({water_in_air, water_in_oil, faults[3], faults[3], faults[3], faults[2], faults[1], faults[0]}), .bursts_i({local_burst_comp_1_ipad_IBUF_1006, local_burst_comp_2_ipad_IBUF_1008, local_burst_comp_3_ipad_IBUF_1010}), .switches_i({local_burst_switch_status[1], local_burst_switch_status[0], local_squeeze_switch_status[1], local_squeeze_switch_status[0], local_empty_switch_status[1], local_empty_switch_status[0]}), .incoming_data_i({N0, N1, N21, N31, N4, N5, N6, N7}), .squeezes_i({local_squeeze_comp_1_ipad_IBUF_1028, local_squeeze_comp_2_ipad_IBUF_1030, local_squeeze_comp_3_ipad_IBUF_1032}), .warnings_i({local_burst_warning, local_squeeze_warning, local_empty_warning}) ); INV ch0_home1 ( .I(resample), .O(ch0_home1_953) ); AND2 ch0_home2 ( .I0(intake_exhaust_pump_home), .I1(ch0_home1_953), .O(ch0_home) ); AND2 ch1_home1 ( .I0(resample), .I1(intake_exhaust_pump_home), .O(ch1_home) ); INV ch0_home_n_opad1 ( .I(ch0_home), .O(ch0_home_n_opad_OBUF_955) ); INV ch1_home_n_opad1 ( .I(ch1_home), .O(ch1_home_n_opad_OBUF_975) ); INV water_alarm_enable_n_opad1 ( .I(water_alarm_enable), .O(water_alarm_enable_n_opad_OBUF_1071) ); INV pressure_sensor_enable_n_opad1 ( .I(pressure_sensor_enable), .O(pressure_sensor_enable_n_opad_OBUF_1051) ); INV smclk_reset_synch_not00001 ( .I(synced_reset_wrt_aclk), .O(smclk_reset_synch_not0000) ); INV lpf_water_in_air_not00001 ( .I(water_in_air_n_ipad_IBUF_1075), .O(lpf_water_in_air_not0000) ); INV lpf_water_in_oil_not00001 ( .I(water_in_oil_n_ipad_IBUF_1078), .O(lpf_water_in_oil_not0000) ); OR2 \faults<3>1 ( .I0(local_burst_opad_OBUF_1012), .I1(remote_burst), .O(\faults<3>1_988 ) ); AND2 \faults<3>2 ( .I0(resample), .I1(\faults<3>1_988 ), .O(faults[3]) ); OR2 faults_2_mux00001 ( .I0(local_squeeze_opad_OBUF_1034), .I1(remote_squeeze), .O(faults_2_mux0000) ); AND2 faults_2_mux00002 ( .I0(resample), .I1(faults_2_mux0000), .O(faults[2]) ); OR2 faults_1_mux00001 ( .I0(local_squeeze_opad_OBUF_1034), .I1(remote_burst), .O(faults_1_mux0000) ); INV faults_1_mux00002 ( .I(resample), .O(faults_1_mux00001_992) ); AND2 faults_1_mux00003 ( .I0(faults_1_mux0000), .I1(faults_1_mux00001_992), .O(faults[1]) ); OR2 faults_0_mux00001 ( .I0(local_burst_opad_OBUF_1012), .I1(remote_squeeze), .O(faults_0_mux0000) ); INV faults_0_mux00002 ( .I(resample), .O(faults_0_mux00001_990) ); AND2 faults_0_mux00003 ( .I0(faults_0_mux0000), .I1(faults_0_mux00001_990), .O(faults[0]) ); AND2 intake_exhaust_pump_home1 ( .I0(local_empty_opad_OBUF_1023), .I1(remote_empty), .O(intake_exhaust_pump_home1_996) ); OR2 intake_exhaust_pump_home2 ( .I0(local_empty_opad_OBUF_1023), .I1(remote_empty), .O(intake_exhaust_pump_home2_997) ); AND2 intake_exhaust_pump_home3 ( .I0(home_configuration), .I1(intake_exhaust_pump_home2_997), .O(intake_exhaust_pump_home3_998) ); OR2 intake_exhaust_pump_home4 ( .I0(intake_exhaust_pump_home1_996), .I1(intake_exhaust_pump_home3_998), .O(intake_exhaust_pump_home) ); INV ch0_fls_n_opad1 ( .I(latched_faults[5]), .O(ch0_fls_n_opad1_943) ); INV ch0_fls_n_opad2 ( .I(latched_faults[1]), .O(ch0_fls_n_opad2_944) ); INV ch0_fls_n_opad3 ( .I(resample), .O(ch0_fls_n_opad3_945) ); INV ch0_fls_n_opad4 ( .I(water_faults), .O(ch0_fls_n_opad4_946) ); INV ch0_fls_n_opad5 ( .I(motors_disabled), .O(ch0_fls_n_opad5_947) ); AND2 ch0_fls_n_opad6 ( .I0(resample), .I1(ch0_fls_n_opad1_943), .O(ch0_fls_n_opad6_948) ); AND2 ch0_fls_n_opad7 ( .I0(ch0_fls_n_opad2_944), .I1(ch0_fls_n_opad3_945), .O(ch0_fls_n_opad7_949) ); OR2 ch0_fls_n_opad8 ( .I0(ch0_fls_n_opad6_948), .I1(ch0_fls_n_opad7_949), .O(ch0_fls_n_opad8_950) ); AND3 ch0_fls_n_opad9 ( .I0(ch0_fls_n_opad4_946), .I1(ch0_fls_n_opad8_950), .I2(ch0_fls_n_opad5_947), .O(ch0_fls_n_opad_OBUF_951) ); INV ch1_rls_n_opad1 ( .I(latched_faults[2]), .O(ch1_rls_n_opad1_977) ); INV ch1_rls_n_opad2 ( .I(resample), .O(ch1_rls_n_opad2_978) ); INV ch1_rls_n_opad3 ( .I(water_faults), .O(ch1_rls_n_opad3_979) ); INV ch1_rls_n_opad4 ( .I(motors_disabled), .O(ch1_rls_n_opad4_980) ); OR2 ch1_rls_n_opad5 ( .I0(ch1_rls_n_opad1_977), .I1(ch1_rls_n_opad2_978), .O(ch1_rls_n_opad5_981) ); AND3 ch1_rls_n_opad6 ( .I0(ch1_rls_n_opad3_979), .I1(ch1_rls_n_opad5_981), .I2(ch1_rls_n_opad4_980), .O(ch1_rls_n_opad_OBUF_982) ); INV ch0_rls_n_opad1 ( .I(latched_faults[4]), .O(ch0_rls_n_opad1_957) ); INV ch0_rls_n_opad2 ( .I(latched_faults[0]), .O(ch0_rls_n_opad2_958) ); INV ch0_rls_n_opad3 ( .I(resample), .O(ch0_rls_n_opad3_959) ); INV ch0_rls_n_opad4 ( .I(water_faults), .O(ch0_rls_n_opad4_960) ); INV ch0_rls_n_opad5 ( .I(motors_disabled), .O(ch0_rls_n_opad5_961) ); AND2 ch0_rls_n_opad6 ( .I0(resample), .I1(ch0_rls_n_opad1_957), .O(ch0_rls_n_opad6_962) ); AND2 ch0_rls_n_opad7 ( .I0(ch0_rls_n_opad2_958), .I1(ch0_rls_n_opad3_959), .O(ch0_rls_n_opad7_963) ); OR2 ch0_rls_n_opad8 ( .I0(ch0_rls_n_opad6_962), .I1(ch0_rls_n_opad7_963), .O(ch0_rls_n_opad8_964) ); AND3 ch0_rls_n_opad9 ( .I0(ch0_rls_n_opad4_960), .I1(ch0_rls_n_opad8_964), .I2(ch0_rls_n_opad5_961), .O(ch0_rls_n_opad_OBUF_965) ); INV ch1_fls_n_opad1 ( .I(latched_faults[3]), .O(ch1_fls_n_opad1_967) ); INV ch1_fls_n_opad2 ( .I(resample), .O(ch1_fls_n_opad2_968) ); INV ch1_fls_n_opad3 ( .I(water_faults), .O(ch1_fls_n_opad3_969) ); INV ch1_fls_n_opad4 ( .I(motors_disabled), .O(ch1_fls_n_opad4_970) ); OR2 ch1_fls_n_opad5 ( .I0(ch1_fls_n_opad1_967), .I1(ch1_fls_n_opad2_968), .O(ch1_fls_n_opad5_971) ); AND3 ch1_fls_n_opad6 ( .I0(ch1_fls_n_opad3_969), .I1(ch1_fls_n_opad5_971), .I2(ch1_fls_n_opad4_970), .O(ch1_fls_n_opad_OBUF_972) ); IBUF water_in_air_n_ipad_IBUF ( .I(water_in_air_n_ipad), .O(water_in_air_n_ipad_IBUF_1075) ); IBUF local_burst_comp_1_ipad_IBUF ( .I(local_burst_comp_1_ipad), .O(local_burst_comp_1_ipad_IBUF_1006) ); IBUF local_squeeze_comp_3_ipad_IBUF ( .I(local_squeeze_comp_3_ipad), .O(local_squeeze_comp_3_ipad_IBUF_1032) ); IBUF wr_n_ipad_IBUF ( .I(wr_n_ipad), .O(wr_n_ipad_IBUF_1080) ); IBUF local_empty_comp_1_ipad_IBUF ( .I(local_empty_comp_1_ipad), .O(local_empty_comp_1_ipad_IBUF_1017) ); IBUF bus_reset_n_ipad_IBUF ( .I(bus_reset_n_ipad), .O(bus_reset_n_ipad_IBUF_941) ); IBUF rd_n_ipad_IBUF ( .I(rd_n_ipad), .O(rd_n_ipad_IBUF_1055) ); IBUF baclk_ipad_IBUF ( .I(baclk_ipad), .O(baclk_ipad_IBUF_937) ); IBUF local_burst_comp_2_ipad_IBUF ( .I(local_burst_comp_2_ipad), .O(local_burst_comp_2_ipad_IBUF_1008) ); IBUF local_empty_comp_2_ipad_IBUF ( .I(local_empty_comp_2_ipad), .O(local_empty_comp_2_ipad_IBUF_1019) ); IBUF local_burst_comp_3_ipad_IBUF ( .I(local_burst_comp_3_ipad), .O(local_burst_comp_3_ipad_IBUF_1010) ); IBUF local_empty_comp_3_ipad_IBUF ( .I(local_empty_comp_3_ipad), .O(local_empty_comp_3_ipad_IBUF_1021) ); IBUF remote_burst_ipad_IBUF ( .I(remote_burst_ipad), .O(remote_burst_ipad_IBUF_1058) ); IBUF remote_empty_ipad_IBUF ( .I(remote_empty_ipad), .O(remote_empty_ipad_IBUF_1061) ); IBUF as_n_ipad_IBUF ( .I(as_n_ipad), .O(as_n_ipad_IBUF_935) ); IBUF local_squeeze_comp_1_ipad_IBUF ( .I(local_squeeze_comp_1_ipad), .O(local_squeeze_comp_1_ipad_IBUF_1028) ); IBUF remote_squeeze_ipad_IBUF ( .I(remote_squeeze_ipad), .O(remote_squeeze_ipad_IBUF_1064) ); IBUF water_in_oil_n_ipad_IBUF ( .I(water_in_oil_n_ipad), .O(water_in_oil_n_ipad_IBUF_1078) ); IBUF bsmclk_ipad_IBUF ( .I(bsmclk_ipad), .O(bsmclk_ipad_IBUF_939) ); IBUF local_squeeze_comp_2_ipad_IBUF ( .I(local_squeeze_comp_2_ipad), .O(local_squeeze_comp_2_ipad_IBUF_1030) ); IOBUFE ad_iopad_7_IOBUFE ( .I(outgoing_data[7]), .E(drive_bus), .O(N0), .IO(ad_iopad[7]) ); IOBUFE ad_iopad_6_IOBUFE ( .I(outgoing_data[6]), .E(drive_bus), .O(N1), .IO(ad_iopad[6]) ); IOBUFE ad_iopad_5_IOBUFE ( .I(outgoing_data[5]), .E(drive_bus), .O(N21), .IO(ad_iopad[5]) ); IOBUFE ad_iopad_4_IOBUFE ( .I(outgoing_data[4]), .E(drive_bus), .O(N31), .IO(ad_iopad[4]) ); IOBUFE ad_iopad_3_IOBUFE ( .I(outgoing_data[3]), .E(drive_bus), .O(N4), .IO(ad_iopad[3]) ); IOBUFE ad_iopad_2_IOBUFE ( .I(outgoing_data[2]), .E(drive_bus), .O(N5), .IO(ad_iopad[2]) ); IOBUFE ad_iopad_1_IOBUFE ( .I(outgoing_data[1]), .E(drive_bus), .O(N6), .IO(ad_iopad[1]) ); IOBUFE ad_iopad_0_IOBUFE ( .I(outgoing_data[0]), .E(drive_bus), .O(N7), .IO(ad_iopad[0]) ); OBUF local_squeeze_opad_OBUF ( .I(local_squeeze_opad_OBUF_1034), .O(local_squeeze_opad) ); OBUF ch1_rls_n_opad_OBUF ( .I(ch1_rls_n_opad_OBUF_982), .O(ch1_rls_n_opad) ); OBUF water_alarm_enable_n_opad_OBUF ( .I(water_alarm_enable_n_opad_OBUF_1071), .O(water_alarm_enable_n_opad) ); OBUF ch1_home_n_opad_OBUF ( .I(ch1_home_n_opad_OBUF_975), .O(ch1_home_n_opad) ); OBUF ch1_fls_n_opad_OBUF ( .I(ch1_fls_n_opad_OBUF_972), .O(ch1_fls_n_opad) ); OBUF pressure_sensor_enable_n_opad_OBUF ( .I(pressure_sensor_enable_n_opad_OBUF_1051), .O(pressure_sensor_enable_n_opad) ); OBUF pressure_sensor_select_opad_OBUF ( .I(pressure_sensor_select_opad_OBUF_1053), .O(pressure_sensor_select_opad) ); OBUF local_burst_opad_OBUF ( .I(local_burst_opad_OBUF_1012), .O(local_burst_opad) ); OBUF ch0_rls_n_opad_OBUF ( .I(ch0_rls_n_opad_OBUF_965), .O(ch0_rls_n_opad) ); OBUF local_empty_opad_OBUF ( .I(local_empty_opad_OBUF_1023), .O(local_empty_opad) ); OBUF ch0_fls_n_opad_OBUF ( .I(ch0_fls_n_opad_OBUF_951), .O(ch0_fls_n_opad) ); OBUF ch0_home_n_opad_OBUF ( .I(ch0_home_n_opad_OBUF_955), .O(ch0_home_n_opad) ); endmodule `timescale 1 ps / 1 ps module glbl (); parameter ROC_WIDTH = 100000; parameter TOC_WIDTH = 0; wire GSR; wire GTS; wire PRLD; reg GSR_int; reg GTS_int; reg PRLD_int; //-------- JTAG Globals -------------- wire JTAG_TDO_GLBL; wire JTAG_TCK_GLBL; wire JTAG_TDI_GLBL; wire JTAG_TMS_GLBL; wire JTAG_TRST_GLBL; reg JTAG_CAPTURE_GLBL; reg JTAG_RESET_GLBL; reg JTAG_SHIFT_GLBL; reg JTAG_UPDATE_GLBL; reg JTAG_SEL1_GLBL = 0; reg JTAG_SEL2_GLBL = 0 ; reg JTAG_SEL3_GLBL = 0; reg JTAG_SEL4_GLBL = 0; reg JTAG_USER_TDO1_GLBL = 1'bz; reg JTAG_USER_TDO2_GLBL = 1'bz; reg JTAG_USER_TDO3_GLBL = 1'bz; reg JTAG_USER_TDO4_GLBL = 1'bz; assign (weak1, weak0) GSR = GSR_int; assign (weak1, weak0) GTS = GTS_int; assign (weak1, weak0) PRLD = PRLD_int; initial begin GSR_int = 1'b1; PRLD_int = 1'b1; #(ROC_WIDTH) GSR_int = 1'b0; PRLD_int = 1'b0; end initial begin GTS_int = 1'b1; #(TOC_WIDTH) GTS_int = 1'b0; end endmodule