Synthesis Log
Created on 4:19:02 PM 4/17/2009
Running XST Synthesis...
Please wait...
Release 10.1.03 - xst K.39 (nt)
Copyright (c) 1995-2008 Xilinx, Inc. All rights reserved.
--> Parameter TMPDIR set to .
Total REAL time to Xst completion: 0.00 secs
Total CPU time to Xst completion: 0.09 secs
--> Parameter xsthdpdir set to C:\dwarf_fpgas\dpress
Total REAL time to Xst completion: 0.00 secs
Total CPU time to Xst completion: 0.09 secs
-->
TABLE OF CONTENTS
1) Synthesis Options Summary
2) HDL Compilation
3) Design Hierarchy Analysis
4) HDL Analysis
5) HDL Synthesis
5.1) HDL Synthesis Report
6) Advanced HDL Synthesis
6.1) Advanced HDL Synthesis Report
7) Low Level Synthesis
8) Partition Report
9) Final Report
=========================================================================
* Synthesis Options Summary *
=========================================================================
---- Source Parameters
Input File Name : "dpress.prj"
Input Format : mixed
Ignore Synthesis Constraint File : no
---- Target Parameters
Output File Name : "dpress"
Output Format : NGC
Target Device : xcr3384xlTQ144-7
---- Source Options
Top Module Name : dpress
Generics, Parameters : { }
Verilog Macros : { }
Automatic FSM Extraction : yes
FSM Encoding Algorithm : Auto
Mux Extraction : yes
CASE Implementation Style : full-parallel
Safe Implementation : no
Resource Sharing : yes
---- Target Options
Add IO Buffers : yes
Equivalent register Removal : yes
MACRO Preserve : yes
XOR Preserve : yes
---- General Options
Optimization Goal : speed
Optimization Effort : 1
RTL Output : yes
Verilog 2001 : yes
Keep Hierarchy : yes
Netlist Hierarchy : as_optimized
Hierarchy Separator : /
Bus Delimiter : <>
Case Specifier : maintain
---- Other Options
Clock Enable : yes
wysiwyg : no
=========================================================================
=========================================================================
* HDL Compilation *
=========================================================================
Compiling verilog file "..\src\dpress.v" in library dpress
Compiling verilog file "..\src\resynchronizer.v" in library dpress
Module <dpress> compiled
Compiling verilog file "..\src\cpu_interface.v" in library dpress
Module <resynchronizer> compiled
Compiling verilog file "..\src\warning_logic.v" in library dpress
Module <cpu_interface> compiled
Compiling verilog file "..\src\reset_synchronizer.v" in library dpress
Module <warning_logic> compiled
Compiling verilog file "..\src\low_pass_filter.v" in library dpress
Module <reset_synchronizer> compiled
Compiling verilog file "..\src\resynchronizer_h.v" in library dpress
Module <low_pass_filter> compiled
Module <resynchronizer_h> compiled
No errors in compilation
Analysis of file <"dpress.prj"> succeeded.
=========================================================================
* Design Hierarchy Analysis *
=========================================================================
Analyzing hierarchy for module <dpress> in library <dpress>.
Analyzing hierarchy for module <reset_synchronizer> in library <dpress>.
Analyzing hierarchy for module <low_pass_filter> in library <dpress>.
Analyzing hierarchy for module <warning_logic> in library <dpress> with parameters.
BAD_COMPARATOR = "11"
CLOSED = "1"
DISCONNECTED = "01"
NO_FAULT = "00"
OPEN = "0"
SHORTED = "10"
Analyzing hierarchy for module <cpu_interface> in library <dpress> with parameters.
COMMAND_REGISTER = "00011100"
FAULTS = "00000000000000000000000000001000"
FAULT_REGISTER = "00011101"
STATUS_REGISTER = "00011100"
SWITCH_REGISTER = "00011111"
TEST_REGISTER = "00100000"
WARNINGS = "00000000000000000000000000000110"
WARNING_REGISTER = "00011110"
Analyzing hierarchy for module <resynchronizer> in library <dpress>.
Analyzing hierarchy for module <resynchronizer_h> in library <dpress>.
=========================================================================
* HDL Analysis *
=========================================================================
Analyzing top module <dpress>.
Module <dpress> is correct for synthesis.
Analyzing module <reset_synchronizer> in library <dpress>.
Module <reset_synchronizer> is correct for synthesis.
Analyzing module <low_pass_filter> in library <dpress>.
Module <low_pass_filter> is correct for synthesis.
Analyzing module <warning_logic> in library <dpress>.
BAD_COMPARATOR = 2'b11
CLOSED = 1'b1
DISCONNECTED = 2'b01
NO_FAULT = 2'b00
OPEN = 1'b0
SHORTED = 2'b10
"..\src\warning_logic.v" line 61: Found FullParallel Case directive in module <warning_logic>.
Module <warning_logic> is correct for synthesis.
Analyzing module <resynchronizer> in library <dpress>.
Module <resynchronizer> is correct for synthesis.
Analyzing module <resynchronizer_h> in library <dpress>.
Module <resynchronizer_h> is correct for synthesis.
Analyzing module <cpu_interface> in library <dpress>.
COMMAND_REGISTER = 8'b00011100
FAULTS = 32'sb00000000000000000000000000001000
FAULT_REGISTER = 8'b00011101
STATUS_REGISTER = 8'b00011100
SWITCH_REGISTER = 8'b00011111
TEST_REGISTER = 8'b00100000
WARNINGS = 32'sb00000000000000000000000000000110
WARNING_REGISTER = 8'b00011110
"..\src\cpu_interface.v" line 144: Found FullParallel Case directive in module <cpu_interface>.
Module <cpu_interface> is correct for synthesis.
=========================================================================
* HDL Synthesis *
=========================================================================
Performing bidirectional port resolution...
Synthesizing Unit <reset_synchronizer>.
Related source file is "..\src\reset_synchronizer.v".
Found 1-bit register for signal <sync_reset_o>.
Found 1-bit register for signal <reset_delayed>.
Summary:
inferred 2 D-type flip-flop(s).
Unit <reset_synchronizer> synthesized.
Synthesizing Unit <low_pass_filter>.
Related source file is "..\src\low_pass_filter.v".
Found 5-bit register for signal <delayed>.
Found 1-bit register for signal <q>.
Summary:
inferred 1 D-type flip-flop(s).
Unit <low_pass_filter> synthesized.
Synthesizing Unit <cpu_interface>.
Related source file is "..\src\cpu_interface.v".
Found 8-bit up counter for signal <address_register>.
Found 6-bit register for signal <command_register>.
Found 8-bit register for signal <diagnostic_register>.
Found 8-bit comparator greatequal for signal <drive_bus_o$cmp_ge0000> created at line 74.
Found 8-bit comparator lessequal for signal <drive_bus_o$cmp_le0000> created at line 74.
Found 8-bit register for signal <faults>.
Found 1-bit register for signal <previous_as_n>.
Found 1-bit register for signal <previous_rd_n>.
Found 1-bit register for signal <previous_wr_n>.
Found 6-bit register for signal <warnings>.
Summary:
inferred 1 Counter(s).
inferred 17 D-type flip-flop(s).
inferred 2 Comparator(s).
Unit <cpu_interface> synthesized.
Synthesizing Unit <resynchronizer>.
Related source file is "..\src\resynchronizer.v".
Found 1-bit register for signal <clean_o>.
Found 1-bit register for signal <delayed>.
Summary:
inferred 2 D-type flip-flop(s).
Unit <resynchronizer> synthesized.
Synthesizing Unit <resynchronizer_h>.
Related source file is "..\src\resynchronizer_h.v".
Found 1-bit register for signal <clean_o>.
Found 1-bit register for signal <delayed>.
Summary:
inferred 2 D-type flip-flop(s).
Unit <resynchronizer_h> synthesized.
Synthesizing Unit <warning_logic>.
Related source file is "..\src\warning_logic.v".
Unit <warning_logic> synthesized.
Synthesizing Unit <dpress>.
Related source file is "..\src\dpress.v".
Found 8-bit tristate buffer for signal <ad_iopad>.
Summary:
inferred 8 Tristate(s).
Unit <dpress> synthesized.
=========================================================================
HDL Synthesis Report
Macro Statistics
# Counters : 1
8-bit up counter : 1
# Registers : 75
1-bit register : 68
5-bit register : 5
6-bit register : 1
8-bit register : 1
# Comparators : 2
8-bit comparator greatequal : 1
8-bit comparator lessequal : 1
# Tristates : 1
8-bit tristate buffer : 1
=========================================================================
=========================================================================
* Advanced HDL Synthesis *
=========================================================================
=========================================================================
Advanced HDL Synthesis Report
Macro Statistics
# Counters : 1
8-bit up counter : 1
# Registers : 107
Flip-Flops : 107
=========================================================================
=========================================================================
* Low Level Synthesis *
=========================================================================
Optimizing unit <dpress> ...
Optimizing unit <reset_synchronizer> ...
Optimizing unit <resynchronizer> ...
Optimizing unit <resynchronizer_h> ...
Optimizing unit <low_pass_filter> ...
Optimizing unit <warning_logic> ...
Optimizing unit <cpu_interface> ...
=========================================================================
* Partition Report *
=========================================================================
Partition Implementation Status
-------------------------------
No Partitions were found in this design.
-------------------------------
=========================================================================
* Final Report *
=========================================================================
Final Results
RTL Top Level Output File Name : dpress.ngr
Top Level Output File Name : dpress
Output Format : NGC
Optimization Goal : speed
Keep Hierarchy : yes
Target Technology : xcr3384xlTQ144-7
Macro Preserve : yes
XOR Preserve : yes
Clock Enable : yes
wysiwyg : no
Design Statistics
# IOs : 40
Cell Usage :
# BELS : 670
# AND2 : 215
# AND3 : 60
# AND4 : 18
# GND : 2
# INV : 284
# OR2 : 81
# OR3 : 1
# OR4 : 1
# OR6 : 1
# XOR2 : 7
# FlipFlops/Latches : 115
# FDC : 66
# FDCE : 35
# FDP : 13
# FDPE : 1
# IO Buffers : 40
# IBUF : 20
# IOBUFE : 8
# OBUF : 12
=========================================================================
Total REAL time to Xst completion: 3.00 secs
Total CPU time to Xst completion: 3.20 secs
-->
Total memory usage is 113348 kilobytes
Number of errors : 0 ( 0 filtered)
Number of warnings : 1 ( 0 filtered)
Number of infos : 0 ( 0 filtered)
INFO:NetListWriters:633 - The generated Verilog netlist contains Xilinx UNISIM
simulation primitives and has to be used with UNISIM simulation library for
correct compilation and simulation.
INFO:NetListWriters - Setup Simulation - To perform a setup simulation, specify
values in the Maximum (MAX) field with the following command line modifier:
-SDFMAX
INFO:NetListWriters - Hold Simulation - To perform the most accurate hold
simulation, specify values in the Minimum (MIN) field with the following
command line modifier: -SDFMIN
INFO:NetListWriters:665 - For more information on how to pass the SDF switches
to the simulator, see your Simulator tool documentation.
Synthesis finished successfully.