I 000046 55 1806          1237573722702 $root
(_unit VERILOG 6.1285.6.606 ($root 0 0 ($root 0 0 ))
	(_version v147)
	(_time 1237573722513 2009.03.20 11:28:42)
	(_use (std(standard))(vl(verilog_logic)))
	(_base (E 1))
	(_code cc9fc0989d9bceda9acbd89299)
	(_entity
		(_time 1237573722513)
		(_use )
	)
	(_parameters top_design   dbg   accs      )
	(_attribute top_design )
	(_object
		(_subprogram
			

		)
		(_type (_external ~wire (vl verilog_logic wire)))
		(_type (_external ~reg (vl verilog_logic reg)))
		(_type (_external ~vbit (vl verilog_logic vbit)))
		(_type (_external ~event (vl verilog_logic event)))
		(_type (_external ~wand (vl verilog_logic wand)))
		(_type (_external ~wor (vl verilog_logic wor)))
		(_type (_external ~tri1 (vl verilog_logic tri1)))
		(_type (_external ~tri0 (vl verilog_logic tri0)))
		(_type (_external ~trireg (vl verilog_logic trireg)))
		(_type (_external ~supply0 (vl verilog_logic supply0)))
		(_type (_external ~supply1 (vl verilog_logic supply1)))
		(_type (_external ~real (vl verilog_logic real)))
		(_type (_external ~realtime (vl verilog_logic realtime)))
		(_type (_external ~tri (vl verilog_logic tri)))
		(_type (_external ~triand (vl verilog_logic triand)))
		(_type (_external ~trior (vl verilog_logic trior)))
		(_type (_external ~bit (vl verilog_logic bit)))
		(_type (_external ~logic (vl verilog_logic logic)))			
		(_type (_external ~logic_reg (vl verilog_logic logic)))			
		(_type (_external ~logic_bit (vl verilog_logic vbit)))
		(_type (_external ~shortreal (vl verilog_logic real)))				
		(_type (_external ~string (vl verilog_logic string)))	
		(_type (_external ~extstd.standard.integer (std standard integer)))
		(_type (_external ~extstd.standard.bit (std standard bit)))
	)
	
	
	(_defparam
	)
	(_scope
	)
	(_instantiation gentest 0 0 (_entity .  gentest)
	)
	(_model . $root 1 -1)

)
I 000048 55 3795          1237573722706 gentest
(_unit VERILOG 6.1285.6.606 (gentest 0 1 (gentest 0 1 ))
	(_version v147)
	(_time 1237573722513 2009.03.20 11:28:42)
	(_source (\./src/gen_test.v\ VERILOG (\./src/gen_test.v\ VERILOG)))
	(_use (std(standard))(vl(verilog_logic)))
	(_base (E 4))
	(_code cc9bc3999a9bcddbcacad9979e)
	(_entity
		(_time 1237573722513)
		(_use )
	)
	(_parameters    dbg   accs      )
	(_attribute nb_assign )
	(_generate 1generateblock 0 18 (_verilogfor  (_code  9) (_code  10) (_code  11))
	  (_object
	  	(_type (_internal ~vector~0 0 15 (_array ~bit ((_uto (i 0) (i 0))))(_attribute signed)))
	  	(_generic (_internal i ~vector~0 0 15  \0\ (_entity -1 (_constant \0\)))(_constant))
	  	(_subprogram


	  	)
	  	(_process
	  		(@ALWAYS#20_2@ (_architecture 2 0 20 (_process 
				(_target(7(_index 4))(7(_index 6))(7(_index 8)))
				(_read(0)(1)(4)(3(_index 5))(2(_index 7))(5))
				(_need_init)
	  		)))
	  		(@INTERNAL#0_3@ (_internal 3 0 0 0 (_process (_virtual))))
	  	)
	  )
	
	
	  (_defparam
	  )
	)
	(_object
		(_type (_internal ~vector~0 0 3 (_array ~bit ((_uto (i 0) (i 0))))))
		(_generic (_internal SIZE ~vector~0 0 3 \8\ (_entity -1 (_code  12))))
		(_port (_internal clock_i ~wire 0 4 (_architecture (_in ))) (_net  (_scalared) ) (_nonbaction) (_noforceassign))
		(_port (_internal reset_i ~wire 0 5 (_architecture (_in ))) (_net  (_scalared) ) (_nonbaction) (_noforceassign))
		(_type (_internal ~[SIZE-1:0]wire~ 0 6 (_array ~wire ((_range  13)))))
		(_port (_internal warnings_i ~[SIZE-1:0]wire~ 0 6 (_architecture (_in ))) (_net  (_scalared) ) (_simple) (_flags1))
		(_port (_internal incoming_data_i ~[SIZE-1:0]wire~ 0 7 (_architecture (_in ))) (_net  (_scalared) ) (_simple) (_flags1))
		(_port (_internal clear_warnings_i ~wire 0 8 (_architecture (_in ))) (_net  (_scalared) ) (_simple) (_flags1))
		(_port (_internal armed_i ~wire 0 9 (_architecture (_in ))) (_net  (_scalared) ) (_simple) (_flags1))
		(_port (_internal out ~[SIZE-1:0]wire~ 0 10 (_architecture (_out ))) (_net  (_scalared) ) (_simple) (_flags1))
		(_type (_internal ~[SIZE-1:0]reg~ 0 13 (_array ~reg ((_range  14)))))
		(_signal (_internal warning_register ~[SIZE-1:0]reg~ 0 13 (_architecture (_uni ))) (_reg ) (_flags1))
		(_subprogram
			

		)
		(_type (_external ~wire (vl verilog_logic wire)))
		(_type (_external ~reg (vl verilog_logic reg)))
		(_type (_external ~vbit (vl verilog_logic vbit)))
		(_type (_external ~event (vl verilog_logic event)))
		(_type (_external ~wand (vl verilog_logic wand)))
		(_type (_external ~wor (vl verilog_logic wor)))
		(_type (_external ~tri1 (vl verilog_logic tri1)))
		(_type (_external ~tri0 (vl verilog_logic tri0)))
		(_type (_external ~trireg (vl verilog_logic trireg)))
		(_type (_external ~supply0 (vl verilog_logic supply0)))
		(_type (_external ~supply1 (vl verilog_logic supply1)))
		(_type (_external ~real (vl verilog_logic real)))
		(_type (_external ~realtime (vl verilog_logic realtime)))
		(_type (_external ~tri (vl verilog_logic tri)))
		(_type (_external ~triand (vl verilog_logic triand)))
		(_type (_external ~trior (vl verilog_logic trior)))
		(_type (_external ~bit (vl verilog_logic bit)))
		(_type (_external ~logic (vl verilog_logic logic)))			
		(_type (_external ~logic_reg (vl verilog_logic logic)))			
		(_type (_external ~logic_bit (vl verilog_logic vbit)))
		(_type (_external ~shortreal (vl verilog_logic real)))				
		(_type (_external ~string (vl verilog_logic string)))	
		(_type (_external ~extstd.standard.integer (std standard integer)))
		(_type (_external ~extstd.standard.bit (std standard bit)))
		(_process
			(@ASSIGN#30_0@ (_architecture 0 0 30 (_process (_simple)
				(_target(6))
				(_sensitivity(7))
			)))
			(@INTERNAL#0_1@ (_internal 1 0 0 0 (_process (_virtual))))
		)
	)
	
	
	(_defparam
	)
	(_scope
	)
	(_model . gentest 15 -1)

)
V 000046 55 1806          1237573850593 $root
(_unit VERILOG 6.1285.6.606 ($root 0 0 ($root 0 0 ))
	(_version v147)
	(_time 1237573850404 2009.03.20 11:30:50)
	(_use (std(standard))(vl(verilog_logic)))
	(_base (E 1))
	(_code 5f54085d0b085d4909584b010a)
	(_entity
		(_time 1237573850404)
		(_use )
	)
	(_parameters top_design   dbg   accs      )
	(_attribute top_design )
	(_object
		(_subprogram
			

		)
		(_type (_external ~wire (vl verilog_logic wire)))
		(_type (_external ~reg (vl verilog_logic reg)))
		(_type (_external ~vbit (vl verilog_logic vbit)))
		(_type (_external ~event (vl verilog_logic event)))
		(_type (_external ~wand (vl verilog_logic wand)))
		(_type (_external ~wor (vl verilog_logic wor)))
		(_type (_external ~tri1 (vl verilog_logic tri1)))
		(_type (_external ~tri0 (vl verilog_logic tri0)))
		(_type (_external ~trireg (vl verilog_logic trireg)))
		(_type (_external ~supply0 (vl verilog_logic supply0)))
		(_type (_external ~supply1 (vl verilog_logic supply1)))
		(_type (_external ~real (vl verilog_logic real)))
		(_type (_external ~realtime (vl verilog_logic realtime)))
		(_type (_external ~tri (vl verilog_logic tri)))
		(_type (_external ~triand (vl verilog_logic triand)))
		(_type (_external ~trior (vl verilog_logic trior)))
		(_type (_external ~bit (vl verilog_logic bit)))
		(_type (_external ~logic (vl verilog_logic logic)))			
		(_type (_external ~logic_reg (vl verilog_logic logic)))			
		(_type (_external ~logic_bit (vl verilog_logic vbit)))
		(_type (_external ~shortreal (vl verilog_logic real)))				
		(_type (_external ~string (vl verilog_logic string)))	
		(_type (_external ~extstd.standard.integer (std standard integer)))
		(_type (_external ~extstd.standard.bit (std standard bit)))
	)
	
	
	(_defparam
	)
	(_scope
	)
	(_instantiation gentest 0 0 (_entity .  gentest)
	)
	(_model . $root 1 -1)

)
V 000048 55 3802          1237573850597 gentest
(_unit VERILOG 6.1285.6.606 (gentest 0 1 (gentest 0 1 ))
	(_version v147)
	(_time 1237573850404 2009.03.20 11:30:50)
	(_source (\./src/gen_test.v\ VERILOG (\./src/gen_test.v\ VERILOG)))
	(_use (std(standard))(vl(verilog_logic)))
	(_base (E 4))
	(_code 6e613a6e3e396f7968687b353c)
	(_entity
		(_time 1237573850404)
		(_use )
	)
	(_parameters    dbg   accs      )
	(_attribute nb_assign )
	(_generate warning_register_bits 0 18 (_verilogfor  (_code  9) (_code  10) (_code  11))
	  (_object
	  	(_type (_internal ~vector~0 0 15 (_array ~bit ((_uto (i 0) (i 0))))(_attribute signed)))
	  	(_generic (_internal i ~vector~0 0 15  \0\ (_entity -1 (_constant \0\)))(_constant))
	  	(_subprogram


	  	)
	  	(_process
	  		(@ALWAYS#20_2@ (_architecture 2 0 20 (_process 
				(_target(7(_index 4))(7(_index 6))(7(_index 8)))
				(_read(0)(1)(4)(3(_index 5))(2(_index 7))(5))
				(_need_init)
	  		)))
	  		(@INTERNAL#0_3@ (_internal 3 0 0 0 (_process (_virtual))))
	  	)
	  )
	
	
	  (_defparam
	  )
	)
	(_object
		(_type (_internal ~vector~0 0 3 (_array ~bit ((_uto (i 0) (i 0))))))
		(_generic (_internal SIZE ~vector~0 0 3 \8\ (_entity -1 (_code  12))))
		(_port (_internal clock_i ~wire 0 4 (_architecture (_in ))) (_net  (_scalared) ) (_nonbaction) (_noforceassign))
		(_port (_internal reset_i ~wire 0 5 (_architecture (_in ))) (_net  (_scalared) ) (_nonbaction) (_noforceassign))
		(_type (_internal ~[SIZE-1:0]wire~ 0 6 (_array ~wire ((_range  13)))))
		(_port (_internal warnings_i ~[SIZE-1:0]wire~ 0 6 (_architecture (_in ))) (_net  (_scalared) ) (_simple) (_flags1))
		(_port (_internal incoming_data_i ~[SIZE-1:0]wire~ 0 7 (_architecture (_in ))) (_net  (_scalared) ) (_simple) (_flags1))
		(_port (_internal clear_warnings_i ~wire 0 8 (_architecture (_in ))) (_net  (_scalared) ) (_simple) (_flags1))
		(_port (_internal armed_i ~wire 0 9 (_architecture (_in ))) (_net  (_scalared) ) (_simple) (_flags1))
		(_port (_internal out ~[SIZE-1:0]wire~ 0 10 (_architecture (_out ))) (_net  (_scalared) ) (_simple) (_flags1))
		(_type (_internal ~[SIZE-1:0]reg~ 0 13 (_array ~reg ((_range  14)))))
		(_signal (_internal warning_register ~[SIZE-1:0]reg~ 0 13 (_architecture (_uni ))) (_reg ) (_flags1))
		(_subprogram
			

		)
		(_type (_external ~wire (vl verilog_logic wire)))
		(_type (_external ~reg (vl verilog_logic reg)))
		(_type (_external ~vbit (vl verilog_logic vbit)))
		(_type (_external ~event (vl verilog_logic event)))
		(_type (_external ~wand (vl verilog_logic wand)))
		(_type (_external ~wor (vl verilog_logic wor)))
		(_type (_external ~tri1 (vl verilog_logic tri1)))
		(_type (_external ~tri0 (vl verilog_logic tri0)))
		(_type (_external ~trireg (vl verilog_logic trireg)))
		(_type (_external ~supply0 (vl verilog_logic supply0)))
		(_type (_external ~supply1 (vl verilog_logic supply1)))
		(_type (_external ~real (vl verilog_logic real)))
		(_type (_external ~realtime (vl verilog_logic realtime)))
		(_type (_external ~tri (vl verilog_logic tri)))
		(_type (_external ~triand (vl verilog_logic triand)))
		(_type (_external ~trior (vl verilog_logic trior)))
		(_type (_external ~bit (vl verilog_logic bit)))
		(_type (_external ~logic (vl verilog_logic logic)))			
		(_type (_external ~logic_reg (vl verilog_logic logic)))			
		(_type (_external ~logic_bit (vl verilog_logic vbit)))
		(_type (_external ~shortreal (vl verilog_logic real)))				
		(_type (_external ~string (vl verilog_logic string)))	
		(_type (_external ~extstd.standard.integer (std standard integer)))
		(_type (_external ~extstd.standard.bit (std standard bit)))
		(_process
			(@ASSIGN#30_0@ (_architecture 0 0 30 (_process (_simple)
				(_target(6))
				(_sensitivity(7))
			)))
			(@INTERNAL#0_1@ (_internal 1 0 0 0 (_process (_virtual))))
		)
	)
	
	
	(_defparam
	)
	(_scope
	)
	(_model . gentest 15 -1)

)