[Project]
Current Flow=Multivendor
VCS=0
version=1
Current Config=compile

[Configurations]
compile=gen_test

[Library]
gen_test=.\gen_test.LIB
gen_test_post_synthesis=.\gen_test_post_synthesis\gen_test_post_synthesis.lib
gen_test_timing=.\gen_test_timing\gen_test_timing.lib

[$LibMap$]
gen_test=.
Active_lib=XC9500
xilinxun=XC9500
UnlinkedDesignLibrary=XC9500
DESIGNS=XC9500

[Settings]
SYNTH_TOOL=MV_XST101
IMPL_TOOL=MV_ISE101
CSYNTH_TOOL=<none>
PHYSSYNTH_TOOL=<none>
FLOW_TYPE=HDL
LANGUAGE=VERILOG
FLOWTOOLS=IMPL_WITH_SYNTH
ON_SERVERFARM_SYNTH=0
ON_SERVERFARM_IMPL=0
ON_SERVERFARM_SIM=0
DVM_DISPLAY=NO
VerilogDirsChanged=1
REFRESH_FLOW=1
FAMILY=Xilinx10x COOLRUNNER
RUN_MODE_SYNTH=0
SYNTH_STATUS=ok
PHYSSYNTH_STATUS=none
IMPL_STATUS=ok
FUNC_LIB=gen_test
POST_LIB=gen_test_post_synthesis
RUN_MODE_IMPL=0
TIM_LIB=gen_test_timing

[IMPLEMENTATION]
UCF=C:\PROGRA~1\Aldec\ACTIVE~1.1\Dat\Template.ucf
FLOW_STEPS_RESET=0
FAMILY=Xilinx10x COOLRUNNER
DEVICE=r3384xlTQ144
SPEED=-7
NETLIST=C:\dwarf_fpgas\gen_test\synthesis\gentest.ngc
IS_BAT_MODE=0
BAT_FILE=
DEF_UCF=0
OLD_FAMILY=Xilinx10x COOLRUNNER
wasChanged_Change_Device_Speed=0
wasChanged_Change_Device_Speed_To=0
wasChanged_Change_Device_Speed_To2=0
Place_And_Route_Mode_old_value=
JOB_DESCRIPTION=ImplementationJob1
SERVERFARM_INCLUDE_INPUT_FILES=*.*
SERVERFARM_EXCLUDE_INPUT_FILES=log\*.*
SYNTH_TOOL_RESET=0
LAST_RUN=1237573906
OUTPUT_NETLIST=IMPLEMENT\TIME_SIM.V
OUTPUT_SDF=

[Verilog Library]
XC9500=

[IMPLEMENTATION_XILINX10]
impl_opt(dont_run_translate)=0
impl_opt(dont_run_map)=0
impl_opt(dont_run_place)=0
impl_opt(dont_run_trace)=0
impl_opt(dont_run_simulation)=0
impl_opt(dont_run_fit)=0
impl_opt(dont_run_bitgen)=1
Macro_Search_Path=
impl_opt(edif_str)=C:\dwarf_fpgas\gen_test\synthesis\gentest.ngc
impl_opt(_family_sel)=Xilinx10x COOLRUNNER
impl_opt(_device_sel)=r3384xlTQ144
impl_opt(_speed_sel)=-7
impl_opt(netlist_format)=2
impl_opt(auto_close)=0
impl_opt(override_existing_project)=1
impl_opt(bat_file_name)=
impl_opt(is_bat_mode)=0
impl_opt(def_ucf)=Always use Aldec constraint template
impl_opt(ucf_str)=C:\PROGRA~1\Aldec\ACTIVE~1.1\Dat\Template.ucf
impl_opt(version_sel)=ver1
impl_opt(revision_sel)=rev1
impl_opt(Use_Location_Constraints)=Always
impl_opt(Output_Slew_Rate)=Fast
impl_opt(Default_PowerUp)=Low
impl_opt(fit_mode)=0
impl_opt(log_opt)=1
impl_opt(Use_Fast_Input_For_Registers)=1
impl_opt(Collapsing_Input_Limit_4_40)=32
impl_opt(Collapsing_Pterm_Limit_3_48)=28
impl_opt(ngdbuild_file_str)=
impl_opt(use_ngdbuild_file)=0
impl_opt(netgen_file_str)=
impl_opt(use_netgen_file)=0
impl_opt(cpldfit_file_str)=
impl_opt(use_cpldfit_file)=0
impl_opt(hprep6_file_str)=
impl_opt(use_hprep6_file)=0
impl_opt(Allow_Unmatched_LOC_Constraint)=0
impl_opt(Show_Bring_Out_Global_Set_Reset_Net_As_Ports)=
impl_opt(Use_Show_Bring_Out_Global_Set_Reset_Net_As_Ports)=0
impl_opt(Show_Generate_Testbench_File)=UUT
impl_opt(Use_Show_Generate_Testbench_File)=0
impl_opt(Function_Block_Input_Limit)=38
impl_opt(Input_Pin_Termination)=Float
impl_opt(Unused_Pin_Termination_Mode)=Pullup
impl_opt(Show_Use_Timing_Constraint)=1
impl_opt(Other_Ngdbuild_Options)=
impl_opt(Implementation_Template_1)=Optimize Density
impl_opt(Logic_Optimization_1)=Density
impl_opt(Preserve_Unused_Inputs)=0
impl_opt(Use_Function_Block_Clock)=1
impl_opt(Use_Foldback_Nands)=0
impl_opt(Reserve_Isp_Pins)=1
impl_opt(Other_Fitter_Commands)=
impl_opt(Retain_Hiearchy)=1
impl_opt(Reset_Configuration_Pulsee)=100
impl_opt(Generate_Architecture_Only)=0
impl_opt(Include_Uselib_Directive)=0
impl_opt(Do_Not_Escape_Signal)=0
impl_opt(Other_Netgen_Command)=
impl_opt(Macro_Search_Path)=
impl_opt(Path_Used_In_Sdf)=C:/dwarf_fpgas/gen_test/implement
impl_opt(Insert_ChipScope_Core)=0
impl_opt(Run_ChipScope_Core_Inserter_GUI)=1
impl_opt(ChipScope_Core_Inserter_Project_File)=
impl_opt(_use_filter_messages)=0
impl_opt(_filter_messages)=
impl_opt(Include_Function_In_Verilog_File)=1
impl_opt(Include_Simprim_Models_In_Verilog_File)=0
impl_opt(autosignature_generation)=0
impl_opt(other_program_com_line_opt)=
impl_opt(merge_netlists_before_insertion)=1
impl_opt(chipscope_bat_file_str)=
impl_opt(use_chipscope_bat_file)=0
impl_opt(Rename_Top_Level_Architecture_to)=Structure
impl_opt(Rename_Top_Level_Entity_to)=
impl_opt(Rename_Top_Level_Module_to)=
impl_opt(automatically_insert_glbl_module)=1
impl_opt(Output_Extended_Identifiers)=0
impl_opt(ChipScope_Overwrite_Project_File)=0
impl_opt(chipscope_install_folder)=

[SYNTHESIS]
OBSOLETE_ALIASES=1
TOPLEVEL=gentest
FAMILY=Xilinx10x COOLRUNNER
DEVICE=r3384xlTQ144
SPEED=-7
FILTER_MESSAGES=
FSM_ENCODE=
PACK_IO_REGISTERS=
SIMOUTFORM=2
AUTO_CLOSE_GUI=0
USE_DEF_UCF_FILE=1
UCF_FILENAME=
LSO_FILENAME=
HDL_INI_FILENAME=
XST_INCLUDE_PATH=C:/dwarf_fpgas/gen_test/src
CORES_SEARCH_DIR=
OTHER_COMMAND_LINE_OPT=
XST_WORK_DIR=C:/dwarf_fpgas/gen_test/synthesis/xst
Show_OptimizationGoalCombo=Speed
Show_OptimizationEffortCombo=Normal
Show_FSM_Encoding_Algorithm=Auto
Show_MuxExtractionCombo=Yes
Show_Resource_Sharing=1
Show_Add_IO_Buffer=1
Show_Equivalent_Register_Removal=1
Show_Clock_Enable=1
Show_Macro_Preserve=1
Show_Xor_Preserve=1
Show_WysiwygCombo=None
Show_Case_Implementation_Style=Full-parallel
Show_JobDescription=JobDesc1
Show_IncludeInputFiles=*.*
Show_ExcludeInputFiles=log*.*:implement*.*
Show_UseSynthesisConstraintsFile=1
Show_HierarchySeparator=/
Show_BusDelimiter=<>
Show_CaseVhdl=Maintain
Show_Verilog2001=1
Show_SimulationOutputFormat=2
Show_KeepHierarchyCPLD=Yes
Show_SafeImplementation=No
Show_FilterMessages=0
Show_NetlistHierarchy=As Optimized
RAM_STYLE=Auto
ROM_STYLE=Auto
MUX_STYLE=Auto
MOVE_FIRST_FF_STAGE=1
MOVE_LAST_FF_STAGE=1
JOB_DESCRIPTION=JobDesc1
SERVERFARM_INCLUDE_INPUT_FILES=*.*
SERVERFARM_EXCLUDE_INPUT_FILES=log*.*:implement*.*
LAST_RUN=1237573859
OUTPUT_NETLIST=C:\dwarf_fpgas\gen_test\synthesis\gentest.ngc
OUTPUT_SIMUL_NETLIST=synthesis\gentest.v

[PHYS_SYNTHESIS]
FAMILY=Xilinx10x COOLRUNNER
DEVICE=r3384xlTQ144
SPEED=-7
IN_DESIGN=C:\dwarf_fpgas\gen_test\synthesis\gentest.ngc
OUT_DESIGN=
IN_CONSTRAINT=
OUT_CONSTRAINT=
REPORT=

[Groups]
post-synthesis=1
timing=1

[SIM.POST]
TOPLEVEL=gentest glbl

[SIM.TIME]
SDF_PATH=
TOPLEVEL=gentest glbl

[Folders]
Name3=Makefiles
Directory3=C:\dwarf_fpgas\gen_test\
Extension3=mak
Name4=Memory
Directory4=C:\dwarf_fpgas\gen_test\src
Extension4=mem;mif;hex
Name5=Dll Libraries
Directory5=C:\dwarf_fpgas\gen_test\
Extension5=dll
Name6=PDF
Directory6=C:\dwarf_fpgas\gen_test\
Extension6=pdf
Name7=HTML
Directory7=C:\dwarf_fpgas\gen_test\
Extension7=

[Files]
/gen_test.v=-1
post-synthesis/..\..\synthesis\glbl.v=-1
post-synthesis/..\..\synthesis\gentest.v=-1
timing/..\..\IMPLEMENT\TIME_SIM.V=-1
timing/..\..\implement\time_sim.sdf=-1
timing/..\..\implement\glbl.v=-1

[Files.Data]
.\src\gen_test.v=Verilog Source Code
.\synthesis\glbl.v=VERILOG SOURCE CODE
.\synthesis\gentest.v=Verilog Source Code
.\IMPLEMENT\TIME_SIM.V=VERILOG SOURCE CODE
.\implement\time_sim.sdf=SDF FILE
.\implement\glbl.v=VERILOG SOURCE CODE