////////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995-2008 Xilinx, Inc.  All rights reserved.
////////////////////////////////////////////////////////////////////////////////
//   ____  ____
//  /   /\/   /
// /___/  \  /    Vendor: Xilinx
// \   \   \/     Version: K.39
//  \   \         Application: netgen
//  /   /         Filename: time_sim.v
// /___/   /\     Timestamp: Fri Mar 20 11:31:58 2009
// \   \  /  \ 
//  \___\/\___\
//             
// Command	: -w -sim -ofmt verilog -sdf_anno true -sdf_path C:\dwarf_fpgas\gen_test\implement -insert_glbl true gentest.nga time_sim.v 
// Device	: XCR3384XL-7-TQ144 (Speed File: Version 6.0)
// Input file	: gentest.nga
// Output file	: time_sim.v
// # of Modules	: 1
// Design Name	: gentest.nga
// Xilinx        : C:\Xilinx\10.1\ISE
//             
// Purpose:    
//     This verilog netlist is a verification model and uses simulation 
//     primitives which may not represent the true implementation of the 
//     device, however the netlist is functionally correct and should not 
//     be modified. This file cannot be synthesized and should only be used 
//     with supported simulation tools.
//             
// Reference:  
//     Development System Reference Guide, Chapter 23 and Synthesis and Simulation Design Guide, Chapter 6
//             
////////////////////////////////////////////////////////////////////////////////

`timescale 1 ns/1 ps

module gentest (
  armed_i, clear_warnings_i, clock_i, reset_i, incoming_data_i, warnings_i, out
);
  input armed_i;
  input clear_warnings_i;
  input clock_i;
  input reset_i;
  input [7 : 0] incoming_data_i;
  input [7 : 0] warnings_i;
  output [7 : 0] out;
  wire \armed_i_II/UIM_1 ;
  wire \clear_warnings_i_II/UIM_3 ;
  wire \clock_i_II/FCLK_5 ;
  wire \incoming_data_i<0>_II/UIM_7 ;
  wire \incoming_data_i<1>_II/UIM_9 ;
  wire \incoming_data_i<2>_II/UIM_11 ;
  wire \incoming_data_i<3>_II/UIM_13 ;
  wire \incoming_data_i<4>_II/UIM_15 ;
  wire \incoming_data_i<5>_II/UIM_17 ;
  wire \incoming_data_i<6>_II/UIM_19 ;
  wire \incoming_data_i<7>_II/UIM_21 ;
  wire \warnings_i<0>_II/UIM_23 ;
  wire \reset_i_II/UIM_25 ;
  wire \warnings_i<1>_II/UIM_27 ;
  wire \warnings_i<2>_II/UIM_29 ;
  wire \warnings_i<3>_II/UIM_31 ;
  wire \warnings_i<4>_II/UIM_33 ;
  wire \warnings_i<5>_II/UIM_35 ;
  wire \warnings_i<6>_II/UIM_37 ;
  wire \warnings_i<7>_II/UIM_39 ;
  wire \out<0>_MC.Q_41 ;
  wire \out<1>_MC.Q_43 ;
  wire \out<2>_MC.Q_45 ;
  wire \out<3>_MC.Q_47 ;
  wire \out<4>_MC.Q_49 ;
  wire \out<5>_MC.Q_51 ;
  wire \out<6>_MC.Q_53 ;
  wire \out<7>_MC.Q_55 ;
  wire \out<0>_MC.Q_tsimrenamed_net_ ;
  wire \out<0>_MC.UIM_57 ;
  wire \FOOBAR1__ctinst/7_58 ;
  wire Gnd_59;
  wire \out<0>_MC_tsimcreated_prld__60 ;
  wire \out<0>_MC.D_61 ;
  wire \out<0>_MC.REG_tsimcreated_inv_clock_i_II/FCLK_62 ;
  wire Vcc_63;
  wire \out<0>_MC.D1_64 ;
  wire \out<0>_MC.D2_65 ;
  wire \out<0>_MC.D2_PT_0_66 ;
  wire \out<0>_MC.D2_PT_1_67 ;
  wire \out<0>_MC.D2_PT_2_68 ;
  wire \out<1>_MC.Q_tsimrenamed_net_ ;
  wire \out<1>_MC.UIM_70 ;
  wire \out<1>_MC_tsimcreated_prld__71 ;
  wire \out<1>_MC.D_72 ;
  wire \out<1>_MC.REG_tsimcreated_inv_clock_i_II/FCLK_73 ;
  wire \out<1>_MC.D1_74 ;
  wire \out<1>_MC.D2_75 ;
  wire \out<1>_MC.D2_PT_0_76 ;
  wire \out<1>_MC.D2_PT_1_77 ;
  wire \out<1>_MC.D2_PT_2_78 ;
  wire \out<2>_MC.Q_tsimrenamed_net_ ;
  wire \out<2>_MC.UIM_80 ;
  wire \out<2>_MC_tsimcreated_prld__81 ;
  wire \out<2>_MC.D_82 ;
  wire \out<2>_MC.REG_tsimcreated_inv_clock_i_II/FCLK_83 ;
  wire \out<2>_MC.D1_84 ;
  wire \out<2>_MC.D2_85 ;
  wire \out<2>_MC.D2_PT_0_86 ;
  wire \out<2>_MC.D2_PT_1_87 ;
  wire \out<2>_MC.D2_PT_2_88 ;
  wire \out<3>_MC.Q_tsimrenamed_net_ ;
  wire \out<3>_MC.UIM_90 ;
  wire \out<3>_MC_tsimcreated_prld__91 ;
  wire \out<3>_MC.D_92 ;
  wire \out<3>_MC.REG_tsimcreated_inv_clock_i_II/FCLK_93 ;
  wire \out<3>_MC.D1_94 ;
  wire \out<3>_MC.D2_95 ;
  wire \out<3>_MC.D2_PT_0_96 ;
  wire \out<3>_MC.D2_PT_1_97 ;
  wire \out<3>_MC.D2_PT_2_98 ;
  wire \out<4>_MC.Q_tsimrenamed_net_ ;
  wire \out<4>_MC.UIM_100 ;
  wire \out<4>_MC_tsimcreated_prld__101 ;
  wire \out<4>_MC.D_102 ;
  wire \out<4>_MC.REG_tsimcreated_inv_clock_i_II/FCLK_103 ;
  wire \out<4>_MC.D1_104 ;
  wire \out<4>_MC.D2_105 ;
  wire \out<4>_MC.D2_PT_0_106 ;
  wire \out<4>_MC.D2_PT_1_107 ;
  wire \out<4>_MC.D2_PT_2_108 ;
  wire \out<5>_MC.Q_tsimrenamed_net_ ;
  wire \out<5>_MC.UIM_110 ;
  wire \out<5>_MC_tsimcreated_prld__111 ;
  wire \out<5>_MC.D_112 ;
  wire \out<5>_MC.REG_tsimcreated_inv_clock_i_II/FCLK_113 ;
  wire \out<5>_MC.D1_114 ;
  wire \out<5>_MC.D2_115 ;
  wire \out<5>_MC.D2_PT_0_116 ;
  wire \out<5>_MC.D2_PT_1_117 ;
  wire \out<5>_MC.D2_PT_2_118 ;
  wire \out<6>_MC.Q_tsimrenamed_net_ ;
  wire \out<6>_MC.UIM_120 ;
  wire \out<6>_MC_tsimcreated_prld__121 ;
  wire \out<6>_MC.D_122 ;
  wire \out<6>_MC.REG_tsimcreated_inv_clock_i_II/FCLK_123 ;
  wire \out<6>_MC.D1_124 ;
  wire \out<6>_MC.D2_125 ;
  wire \out<6>_MC.D2_PT_0_126 ;
  wire \out<6>_MC.D2_PT_1_127 ;
  wire \out<6>_MC.D2_PT_2_128 ;
  wire \out<7>_MC.Q_tsimrenamed_net_ ;
  wire \out<7>_MC.UIM_130 ;
  wire \out<7>_MC_tsimcreated_prld__131 ;
  wire \out<7>_MC.D_132 ;
  wire \out<7>_MC.REG_tsimcreated_inv_clock_i_II/FCLK_133 ;
  wire \out<7>_MC.D1_134 ;
  wire \out<7>_MC.D2_135 ;
  wire \out<7>_MC.D2_PT_0_136 ;
  wire \out<7>_MC.D2_PT_1_137 ;
  wire \out<7>_MC.D2_PT_2_138 ;
  wire \NlwInverterSignal_out<0>_MC.D/IN0 ;
  wire \NlwInverterSignal_out<0>_MC.D2_PT_0/IN0 ;
  wire \NlwInverterSignal_out<0>_MC.D2_PT_0/IN1 ;
  wire \NlwInverterSignal_out<0>_MC.D2_PT_2/IN0 ;
  wire \NlwInverterSignal_out<0>_MC.D2_PT_2/IN1 ;
  wire \NlwInverterSignal_out<1>_MC.D/IN0 ;
  wire \NlwInverterSignal_out<1>_MC.D2_PT_0/IN0 ;
  wire \NlwInverterSignal_out<1>_MC.D2_PT_0/IN1 ;
  wire \NlwInverterSignal_out<1>_MC.D2_PT_2/IN0 ;
  wire \NlwInverterSignal_out<1>_MC.D2_PT_2/IN1 ;
  wire \NlwInverterSignal_out<2>_MC.D/IN0 ;
  wire \NlwInverterSignal_out<2>_MC.D2_PT_0/IN0 ;
  wire \NlwInverterSignal_out<2>_MC.D2_PT_0/IN1 ;
  wire \NlwInverterSignal_out<2>_MC.D2_PT_2/IN0 ;
  wire \NlwInverterSignal_out<2>_MC.D2_PT_2/IN1 ;
  wire \NlwInverterSignal_out<3>_MC.D/IN0 ;
  wire \NlwInverterSignal_out<3>_MC.D2_PT_0/IN0 ;
  wire \NlwInverterSignal_out<3>_MC.D2_PT_0/IN1 ;
  wire \NlwInverterSignal_out<3>_MC.D2_PT_2/IN0 ;
  wire \NlwInverterSignal_out<3>_MC.D2_PT_2/IN1 ;
  wire \NlwInverterSignal_out<4>_MC.D/IN0 ;
  wire \NlwInverterSignal_out<4>_MC.D2_PT_0/IN0 ;
  wire \NlwInverterSignal_out<4>_MC.D2_PT_0/IN1 ;
  wire \NlwInverterSignal_out<4>_MC.D2_PT_2/IN0 ;
  wire \NlwInverterSignal_out<4>_MC.D2_PT_2/IN1 ;
  wire \NlwInverterSignal_out<5>_MC.D/IN0 ;
  wire \NlwInverterSignal_out<5>_MC.D2_PT_0/IN0 ;
  wire \NlwInverterSignal_out<5>_MC.D2_PT_0/IN1 ;
  wire \NlwInverterSignal_out<5>_MC.D2_PT_2/IN0 ;
  wire \NlwInverterSignal_out<5>_MC.D2_PT_2/IN1 ;
  wire \NlwInverterSignal_out<6>_MC.D/IN0 ;
  wire \NlwInverterSignal_out<6>_MC.D2_PT_0/IN0 ;
  wire \NlwInverterSignal_out<6>_MC.D2_PT_0/IN1 ;
  wire \NlwInverterSignal_out<6>_MC.D2_PT_2/IN0 ;
  wire \NlwInverterSignal_out<6>_MC.D2_PT_2/IN1 ;
  wire \NlwInverterSignal_out<7>_MC.D/IN0 ;
  wire \NlwInverterSignal_out<7>_MC.D2_PT_0/IN0 ;
  wire \NlwInverterSignal_out<7>_MC.D2_PT_0/IN1 ;
  wire \NlwInverterSignal_out<7>_MC.D2_PT_2/IN0 ;
  wire \NlwInverterSignal_out<7>_MC.D2_PT_2/IN1 ;
  initial $sdf_annotate("c:/dwarf_fpgas/gen_test/implement/time_sim.sdf");
  X_IPAD   \armed_i.PAD  (
    .PAD(armed_i)
  );
  X_BUF   \armed_i_II/UIM  (
    .I(armed_i),
    .O(\armed_i_II/UIM_1 )
  );
  X_IPAD   \clear_warnings_i.PAD  (
    .PAD(clear_warnings_i)
  );
  X_BUF   \clear_warnings_i_II/UIM  (
    .I(clear_warnings_i),
    .O(\clear_warnings_i_II/UIM_3 )
  );
  X_IPAD   \clock_i.PAD  (
    .PAD(clock_i)
  );
  X_BUF   \clock_i_II/FCLK  (
    .I(clock_i),
    .O(\clock_i_II/FCLK_5 )
  );
  X_IPAD   \incoming_data_i<0>.PAD  (
    .PAD(incoming_data_i[0])
  );
  X_BUF   \incoming_data_i<0>_II/UIM  (
    .I(incoming_data_i[0]),
    .O(\incoming_data_i<0>_II/UIM_7 )
  );
  X_IPAD   \incoming_data_i<1>.PAD  (
    .PAD(incoming_data_i[1])
  );
  X_BUF   \incoming_data_i<1>_II/UIM  (
    .I(incoming_data_i[1]),
    .O(\incoming_data_i<1>_II/UIM_9 )
  );
  X_IPAD   \incoming_data_i<2>.PAD  (
    .PAD(incoming_data_i[2])
  );
  X_BUF   \incoming_data_i<2>_II/UIM  (
    .I(incoming_data_i[2]),
    .O(\incoming_data_i<2>_II/UIM_11 )
  );
  X_IPAD   \incoming_data_i<3>.PAD  (
    .PAD(incoming_data_i[3])
  );
  X_BUF   \incoming_data_i<3>_II/UIM  (
    .I(incoming_data_i[3]),
    .O(\incoming_data_i<3>_II/UIM_13 )
  );
  X_IPAD   \incoming_data_i<4>.PAD  (
    .PAD(incoming_data_i[4])
  );
  X_BUF   \incoming_data_i<4>_II/UIM  (
    .I(incoming_data_i[4]),
    .O(\incoming_data_i<4>_II/UIM_15 )
  );
  X_IPAD   \incoming_data_i<5>.PAD  (
    .PAD(incoming_data_i[5])
  );
  X_BUF   \incoming_data_i<5>_II/UIM  (
    .I(incoming_data_i[5]),
    .O(\incoming_data_i<5>_II/UIM_17 )
  );
  X_IPAD   \incoming_data_i<6>.PAD  (
    .PAD(incoming_data_i[6])
  );
  X_BUF   \incoming_data_i<6>_II/UIM  (
    .I(incoming_data_i[6]),
    .O(\incoming_data_i<6>_II/UIM_19 )
  );
  X_IPAD   \incoming_data_i<7>.PAD  (
    .PAD(incoming_data_i[7])
  );
  X_BUF   \incoming_data_i<7>_II/UIM  (
    .I(incoming_data_i[7]),
    .O(\incoming_data_i<7>_II/UIM_21 )
  );
  X_IPAD   \warnings_i<0>.PAD  (
    .PAD(warnings_i[0])
  );
  X_BUF   \warnings_i<0>_II/UIM  (
    .I(warnings_i[0]),
    .O(\warnings_i<0>_II/UIM_23 )
  );
  X_IPAD   \reset_i.PAD  (
    .PAD(reset_i)
  );
  X_BUF   \reset_i_II/UIM  (
    .I(reset_i),
    .O(\reset_i_II/UIM_25 )
  );
  X_IPAD   \warnings_i<1>.PAD  (
    .PAD(warnings_i[1])
  );
  X_BUF   \warnings_i<1>_II/UIM  (
    .I(warnings_i[1]),
    .O(\warnings_i<1>_II/UIM_27 )
  );
  X_IPAD   \warnings_i<2>.PAD  (
    .PAD(warnings_i[2])
  );
  X_BUF   \warnings_i<2>_II/UIM  (
    .I(warnings_i[2]),
    .O(\warnings_i<2>_II/UIM_29 )
  );
  X_IPAD   \warnings_i<3>.PAD  (
    .PAD(warnings_i[3])
  );
  X_BUF   \warnings_i<3>_II/UIM  (
    .I(warnings_i[3]),
    .O(\warnings_i<3>_II/UIM_31 )
  );
  X_IPAD   \warnings_i<4>.PAD  (
    .PAD(warnings_i[4])
  );
  X_BUF   \warnings_i<4>_II/UIM  (
    .I(warnings_i[4]),
    .O(\warnings_i<4>_II/UIM_33 )
  );
  X_IPAD   \warnings_i<5>.PAD  (
    .PAD(warnings_i[5])
  );
  X_BUF   \warnings_i<5>_II/UIM  (
    .I(warnings_i[5]),
    .O(\warnings_i<5>_II/UIM_35 )
  );
  X_IPAD   \warnings_i<6>.PAD  (
    .PAD(warnings_i[6])
  );
  X_BUF   \warnings_i<6>_II/UIM  (
    .I(warnings_i[6]),
    .O(\warnings_i<6>_II/UIM_37 )
  );
  X_IPAD   \warnings_i<7>.PAD  (
    .PAD(warnings_i[7])
  );
  X_BUF   \warnings_i<7>_II/UIM  (
    .I(warnings_i[7]),
    .O(\warnings_i<7>_II/UIM_39 )
  );
  X_OPAD   \out<0>.PAD  (
    .PAD(out[0])
  );
  X_BUF   \out<0>  (
    .I(\out<0>_MC.Q_41 ),
    .O(out[0])
  );
  X_OPAD   \out<1>.PAD  (
    .PAD(out[1])
  );
  X_BUF   \out<1>  (
    .I(\out<1>_MC.Q_43 ),
    .O(out[1])
  );
  X_OPAD   \out<2>.PAD  (
    .PAD(out[2])
  );
  X_BUF   \out<2>  (
    .I(\out<2>_MC.Q_45 ),
    .O(out[2])
  );
  X_OPAD   \out<3>.PAD  (
    .PAD(out[3])
  );
  X_BUF   \out<3>  (
    .I(\out<3>_MC.Q_47 ),
    .O(out[3])
  );
  X_OPAD   \out<4>.PAD  (
    .PAD(out[4])
  );
  X_BUF   \out<4>  (
    .I(\out<4>_MC.Q_49 ),
    .O(out[4])
  );
  X_OPAD   \out<5>.PAD  (
    .PAD(out[5])
  );
  X_BUF   \out<5>  (
    .I(\out<5>_MC.Q_51 ),
    .O(out[5])
  );
  X_OPAD   \out<6>.PAD  (
    .PAD(out[6])
  );
  X_BUF   \out<6>  (
    .I(\out<6>_MC.Q_53 ),
    .O(out[6])
  );
  X_OPAD   \out<7>.PAD  (
    .PAD(out[7])
  );
  X_BUF   \out<7>  (
    .I(\out<7>_MC.Q_55 ),
    .O(out[7])
  );
  X_BUF   \out<0>_MC.Q  (
    .I(\out<0>_MC.Q_tsimrenamed_net_ ),
    .O(\out<0>_MC.Q_41 )
  );
  X_BUF   \out<0>_MC.UIM  (
    .I(\out<0>_MC.Q_tsimrenamed_net_ ),
    .O(\out<0>_MC.UIM_57 )
  );
  X_OR2   \out<0>_MC_tsimcreated_prld_  (
    .I0(\FOOBAR1__ctinst/7_58 ),
    .I1(Gnd_59),
    .O(\out<0>_MC_tsimcreated_prld__60 )
  );
  X_ZERO   Gnd (
    .O(Gnd_59)
  );
  X_FF #(
    .INIT ( 1'b0 ))
  \out<0>_MC.REG  (
    .I(\out<0>_MC.D_61 ),
    .CE(Vcc_63),
    .CLK(\out<0>_MC.REG_tsimcreated_inv_clock_i_II/FCLK_62 ),
    .SET(Gnd_59),
    .RST(\out<0>_MC_tsimcreated_prld__60 ),
    .O(\out<0>_MC.Q_tsimrenamed_net_ )
  );
  X_INV   \out<0>_MC.REG_tsimcreated_inv_clock_i_II/FCLK  (
    .I(\clock_i_II/FCLK_5 ),
    .O(\out<0>_MC.REG_tsimcreated_inv_clock_i_II/FCLK_62 )
  );
  X_ONE   Vcc (
    .O(Vcc_63)
  );
  X_XOR2   \out<0>_MC.D  (
    .I0(\NlwInverterSignal_out<0>_MC.D/IN0 ),
    .I1(\out<0>_MC.D2_65 ),
    .O(\out<0>_MC.D_61 )
  );
  X_ZERO   \out<0>_MC.D1  (
    .O(\out<0>_MC.D1_64 )
  );
  X_AND2   \out<0>_MC.D2_PT_0  (
    .I0(\NlwInverterSignal_out<0>_MC.D2_PT_0/IN0 ),
    .I1(\NlwInverterSignal_out<0>_MC.D2_PT_0/IN1 ),
    .O(\out<0>_MC.D2_PT_0_66 )
  );
  X_AND2   \out<0>_MC.D2_PT_1  (
    .I0(\clear_warnings_i_II/UIM_3 ),
    .I1(\incoming_data_i<0>_II/UIM_7 ),
    .O(\out<0>_MC.D2_PT_1_67 )
  );
  X_AND2   \out<0>_MC.D2_PT_2  (
    .I0(\NlwInverterSignal_out<0>_MC.D2_PT_2/IN0 ),
    .I1(\NlwInverterSignal_out<0>_MC.D2_PT_2/IN1 ),
    .O(\out<0>_MC.D2_PT_2_68 )
  );
  X_OR3   \out<0>_MC.D2  (
    .I0(\out<0>_MC.D2_PT_0_66 ),
    .I1(\out<0>_MC.D2_PT_1_67 ),
    .I2(\out<0>_MC.D2_PT_2_68 ),
    .O(\out<0>_MC.D2_65 )
  );
  X_BUF   \out<1>_MC.Q  (
    .I(\out<1>_MC.Q_tsimrenamed_net_ ),
    .O(\out<1>_MC.Q_43 )
  );
  X_BUF   \out<1>_MC.UIM  (
    .I(\out<1>_MC.Q_tsimrenamed_net_ ),
    .O(\out<1>_MC.UIM_70 )
  );
  X_OR2   \out<1>_MC_tsimcreated_prld_  (
    .I0(\FOOBAR1__ctinst/7_58 ),
    .I1(Gnd_59),
    .O(\out<1>_MC_tsimcreated_prld__71 )
  );
  X_FF #(
    .INIT ( 1'b0 ))
  \out<1>_MC.REG  (
    .I(\out<1>_MC.D_72 ),
    .CE(Vcc_63),
    .CLK(\out<1>_MC.REG_tsimcreated_inv_clock_i_II/FCLK_73 ),
    .SET(Gnd_59),
    .RST(\out<1>_MC_tsimcreated_prld__71 ),
    .O(\out<1>_MC.Q_tsimrenamed_net_ )
  );
  X_INV   \out<1>_MC.REG_tsimcreated_inv_clock_i_II/FCLK  (
    .I(\clock_i_II/FCLK_5 ),
    .O(\out<1>_MC.REG_tsimcreated_inv_clock_i_II/FCLK_73 )
  );
  X_XOR2   \out<1>_MC.D  (
    .I0(\NlwInverterSignal_out<1>_MC.D/IN0 ),
    .I1(\out<1>_MC.D2_75 ),
    .O(\out<1>_MC.D_72 )
  );
  X_ZERO   \out<1>_MC.D1  (
    .O(\out<1>_MC.D1_74 )
  );
  X_AND2   \out<1>_MC.D2_PT_0  (
    .I0(\NlwInverterSignal_out<1>_MC.D2_PT_0/IN0 ),
    .I1(\NlwInverterSignal_out<1>_MC.D2_PT_0/IN1 ),
    .O(\out<1>_MC.D2_PT_0_76 )
  );
  X_AND2   \out<1>_MC.D2_PT_1  (
    .I0(\clear_warnings_i_II/UIM_3 ),
    .I1(\incoming_data_i<1>_II/UIM_9 ),
    .O(\out<1>_MC.D2_PT_1_77 )
  );
  X_AND2   \out<1>_MC.D2_PT_2  (
    .I0(\NlwInverterSignal_out<1>_MC.D2_PT_2/IN0 ),
    .I1(\NlwInverterSignal_out<1>_MC.D2_PT_2/IN1 ),
    .O(\out<1>_MC.D2_PT_2_78 )
  );
  X_OR3   \out<1>_MC.D2  (
    .I0(\out<1>_MC.D2_PT_0_76 ),
    .I1(\out<1>_MC.D2_PT_1_77 ),
    .I2(\out<1>_MC.D2_PT_2_78 ),
    .O(\out<1>_MC.D2_75 )
  );
  X_BUF   \out<2>_MC.Q  (
    .I(\out<2>_MC.Q_tsimrenamed_net_ ),
    .O(\out<2>_MC.Q_45 )
  );
  X_BUF   \out<2>_MC.UIM  (
    .I(\out<2>_MC.Q_tsimrenamed_net_ ),
    .O(\out<2>_MC.UIM_80 )
  );
  X_OR2   \out<2>_MC_tsimcreated_prld_  (
    .I0(\FOOBAR1__ctinst/7_58 ),
    .I1(Gnd_59),
    .O(\out<2>_MC_tsimcreated_prld__81 )
  );
  X_FF #(
    .INIT ( 1'b0 ))
  \out<2>_MC.REG  (
    .I(\out<2>_MC.D_82 ),
    .CE(Vcc_63),
    .CLK(\out<2>_MC.REG_tsimcreated_inv_clock_i_II/FCLK_83 ),
    .SET(Gnd_59),
    .RST(\out<2>_MC_tsimcreated_prld__81 ),
    .O(\out<2>_MC.Q_tsimrenamed_net_ )
  );
  X_INV   \out<2>_MC.REG_tsimcreated_inv_clock_i_II/FCLK  (
    .I(\clock_i_II/FCLK_5 ),
    .O(\out<2>_MC.REG_tsimcreated_inv_clock_i_II/FCLK_83 )
  );
  X_XOR2   \out<2>_MC.D  (
    .I0(\NlwInverterSignal_out<2>_MC.D/IN0 ),
    .I1(\out<2>_MC.D2_85 ),
    .O(\out<2>_MC.D_82 )
  );
  X_ZERO   \out<2>_MC.D1  (
    .O(\out<2>_MC.D1_84 )
  );
  X_AND2   \out<2>_MC.D2_PT_0  (
    .I0(\NlwInverterSignal_out<2>_MC.D2_PT_0/IN0 ),
    .I1(\NlwInverterSignal_out<2>_MC.D2_PT_0/IN1 ),
    .O(\out<2>_MC.D2_PT_0_86 )
  );
  X_AND2   \out<2>_MC.D2_PT_1  (
    .I0(\clear_warnings_i_II/UIM_3 ),
    .I1(\incoming_data_i<2>_II/UIM_11 ),
    .O(\out<2>_MC.D2_PT_1_87 )
  );
  X_AND2   \out<2>_MC.D2_PT_2  (
    .I0(\NlwInverterSignal_out<2>_MC.D2_PT_2/IN0 ),
    .I1(\NlwInverterSignal_out<2>_MC.D2_PT_2/IN1 ),
    .O(\out<2>_MC.D2_PT_2_88 )
  );
  X_OR3   \out<2>_MC.D2  (
    .I0(\out<2>_MC.D2_PT_0_86 ),
    .I1(\out<2>_MC.D2_PT_1_87 ),
    .I2(\out<2>_MC.D2_PT_2_88 ),
    .O(\out<2>_MC.D2_85 )
  );
  X_BUF   \out<3>_MC.Q  (
    .I(\out<3>_MC.Q_tsimrenamed_net_ ),
    .O(\out<3>_MC.Q_47 )
  );
  X_BUF   \out<3>_MC.UIM  (
    .I(\out<3>_MC.Q_tsimrenamed_net_ ),
    .O(\out<3>_MC.UIM_90 )
  );
  X_OR2   \out<3>_MC_tsimcreated_prld_  (
    .I0(\FOOBAR1__ctinst/7_58 ),
    .I1(Gnd_59),
    .O(\out<3>_MC_tsimcreated_prld__91 )
  );
  X_FF #(
    .INIT ( 1'b0 ))
  \out<3>_MC.REG  (
    .I(\out<3>_MC.D_92 ),
    .CE(Vcc_63),
    .CLK(\out<3>_MC.REG_tsimcreated_inv_clock_i_II/FCLK_93 ),
    .SET(Gnd_59),
    .RST(\out<3>_MC_tsimcreated_prld__91 ),
    .O(\out<3>_MC.Q_tsimrenamed_net_ )
  );
  X_INV   \out<3>_MC.REG_tsimcreated_inv_clock_i_II/FCLK  (
    .I(\clock_i_II/FCLK_5 ),
    .O(\out<3>_MC.REG_tsimcreated_inv_clock_i_II/FCLK_93 )
  );
  X_XOR2   \out<3>_MC.D  (
    .I0(\NlwInverterSignal_out<3>_MC.D/IN0 ),
    .I1(\out<3>_MC.D2_95 ),
    .O(\out<3>_MC.D_92 )
  );
  X_ZERO   \out<3>_MC.D1  (
    .O(\out<3>_MC.D1_94 )
  );
  X_AND2   \out<3>_MC.D2_PT_0  (
    .I0(\NlwInverterSignal_out<3>_MC.D2_PT_0/IN0 ),
    .I1(\NlwInverterSignal_out<3>_MC.D2_PT_0/IN1 ),
    .O(\out<3>_MC.D2_PT_0_96 )
  );
  X_AND2   \out<3>_MC.D2_PT_1  (
    .I0(\clear_warnings_i_II/UIM_3 ),
    .I1(\incoming_data_i<3>_II/UIM_13 ),
    .O(\out<3>_MC.D2_PT_1_97 )
  );
  X_AND2   \out<3>_MC.D2_PT_2  (
    .I0(\NlwInverterSignal_out<3>_MC.D2_PT_2/IN0 ),
    .I1(\NlwInverterSignal_out<3>_MC.D2_PT_2/IN1 ),
    .O(\out<3>_MC.D2_PT_2_98 )
  );
  X_OR3   \out<3>_MC.D2  (
    .I0(\out<3>_MC.D2_PT_0_96 ),
    .I1(\out<3>_MC.D2_PT_1_97 ),
    .I2(\out<3>_MC.D2_PT_2_98 ),
    .O(\out<3>_MC.D2_95 )
  );
  X_BUF   \out<4>_MC.Q  (
    .I(\out<4>_MC.Q_tsimrenamed_net_ ),
    .O(\out<4>_MC.Q_49 )
  );
  X_BUF   \out<4>_MC.UIM  (
    .I(\out<4>_MC.Q_tsimrenamed_net_ ),
    .O(\out<4>_MC.UIM_100 )
  );
  X_OR2   \out<4>_MC_tsimcreated_prld_  (
    .I0(\FOOBAR1__ctinst/7_58 ),
    .I1(Gnd_59),
    .O(\out<4>_MC_tsimcreated_prld__101 )
  );
  X_FF #(
    .INIT ( 1'b0 ))
  \out<4>_MC.REG  (
    .I(\out<4>_MC.D_102 ),
    .CE(Vcc_63),
    .CLK(\out<4>_MC.REG_tsimcreated_inv_clock_i_II/FCLK_103 ),
    .SET(Gnd_59),
    .RST(\out<4>_MC_tsimcreated_prld__101 ),
    .O(\out<4>_MC.Q_tsimrenamed_net_ )
  );
  X_INV   \out<4>_MC.REG_tsimcreated_inv_clock_i_II/FCLK  (
    .I(\clock_i_II/FCLK_5 ),
    .O(\out<4>_MC.REG_tsimcreated_inv_clock_i_II/FCLK_103 )
  );
  X_XOR2   \out<4>_MC.D  (
    .I0(\NlwInverterSignal_out<4>_MC.D/IN0 ),
    .I1(\out<4>_MC.D2_105 ),
    .O(\out<4>_MC.D_102 )
  );
  X_ZERO   \out<4>_MC.D1  (
    .O(\out<4>_MC.D1_104 )
  );
  X_AND2   \out<4>_MC.D2_PT_0  (
    .I0(\NlwInverterSignal_out<4>_MC.D2_PT_0/IN0 ),
    .I1(\NlwInverterSignal_out<4>_MC.D2_PT_0/IN1 ),
    .O(\out<4>_MC.D2_PT_0_106 )
  );
  X_AND2   \out<4>_MC.D2_PT_1  (
    .I0(\clear_warnings_i_II/UIM_3 ),
    .I1(\incoming_data_i<4>_II/UIM_15 ),
    .O(\out<4>_MC.D2_PT_1_107 )
  );
  X_AND2   \out<4>_MC.D2_PT_2  (
    .I0(\NlwInverterSignal_out<4>_MC.D2_PT_2/IN0 ),
    .I1(\NlwInverterSignal_out<4>_MC.D2_PT_2/IN1 ),
    .O(\out<4>_MC.D2_PT_2_108 )
  );
  X_OR3   \out<4>_MC.D2  (
    .I0(\out<4>_MC.D2_PT_0_106 ),
    .I1(\out<4>_MC.D2_PT_1_107 ),
    .I2(\out<4>_MC.D2_PT_2_108 ),
    .O(\out<4>_MC.D2_105 )
  );
  X_BUF   \out<5>_MC.Q  (
    .I(\out<5>_MC.Q_tsimrenamed_net_ ),
    .O(\out<5>_MC.Q_51 )
  );
  X_BUF   \out<5>_MC.UIM  (
    .I(\out<5>_MC.Q_tsimrenamed_net_ ),
    .O(\out<5>_MC.UIM_110 )
  );
  X_OR2   \out<5>_MC_tsimcreated_prld_  (
    .I0(\FOOBAR1__ctinst/7_58 ),
    .I1(Gnd_59),
    .O(\out<5>_MC_tsimcreated_prld__111 )
  );
  X_FF #(
    .INIT ( 1'b0 ))
  \out<5>_MC.REG  (
    .I(\out<5>_MC.D_112 ),
    .CE(Vcc_63),
    .CLK(\out<5>_MC.REG_tsimcreated_inv_clock_i_II/FCLK_113 ),
    .SET(Gnd_59),
    .RST(\out<5>_MC_tsimcreated_prld__111 ),
    .O(\out<5>_MC.Q_tsimrenamed_net_ )
  );
  X_INV   \out<5>_MC.REG_tsimcreated_inv_clock_i_II/FCLK  (
    .I(\clock_i_II/FCLK_5 ),
    .O(\out<5>_MC.REG_tsimcreated_inv_clock_i_II/FCLK_113 )
  );
  X_XOR2   \out<5>_MC.D  (
    .I0(\NlwInverterSignal_out<5>_MC.D/IN0 ),
    .I1(\out<5>_MC.D2_115 ),
    .O(\out<5>_MC.D_112 )
  );
  X_ZERO   \out<5>_MC.D1  (
    .O(\out<5>_MC.D1_114 )
  );
  X_AND2   \out<5>_MC.D2_PT_0  (
    .I0(\NlwInverterSignal_out<5>_MC.D2_PT_0/IN0 ),
    .I1(\NlwInverterSignal_out<5>_MC.D2_PT_0/IN1 ),
    .O(\out<5>_MC.D2_PT_0_116 )
  );
  X_AND2   \out<5>_MC.D2_PT_1  (
    .I0(\clear_warnings_i_II/UIM_3 ),
    .I1(\incoming_data_i<5>_II/UIM_17 ),
    .O(\out<5>_MC.D2_PT_1_117 )
  );
  X_AND2   \out<5>_MC.D2_PT_2  (
    .I0(\NlwInverterSignal_out<5>_MC.D2_PT_2/IN0 ),
    .I1(\NlwInverterSignal_out<5>_MC.D2_PT_2/IN1 ),
    .O(\out<5>_MC.D2_PT_2_118 )
  );
  X_OR3   \out<5>_MC.D2  (
    .I0(\out<5>_MC.D2_PT_0_116 ),
    .I1(\out<5>_MC.D2_PT_1_117 ),
    .I2(\out<5>_MC.D2_PT_2_118 ),
    .O(\out<5>_MC.D2_115 )
  );
  X_BUF   \out<6>_MC.Q  (
    .I(\out<6>_MC.Q_tsimrenamed_net_ ),
    .O(\out<6>_MC.Q_53 )
  );
  X_BUF   \out<6>_MC.UIM  (
    .I(\out<6>_MC.Q_tsimrenamed_net_ ),
    .O(\out<6>_MC.UIM_120 )
  );
  X_OR2   \out<6>_MC_tsimcreated_prld_  (
    .I0(\FOOBAR1__ctinst/7_58 ),
    .I1(Gnd_59),
    .O(\out<6>_MC_tsimcreated_prld__121 )
  );
  X_FF #(
    .INIT ( 1'b0 ))
  \out<6>_MC.REG  (
    .I(\out<6>_MC.D_122 ),
    .CE(Vcc_63),
    .CLK(\out<6>_MC.REG_tsimcreated_inv_clock_i_II/FCLK_123 ),
    .SET(Gnd_59),
    .RST(\out<6>_MC_tsimcreated_prld__121 ),
    .O(\out<6>_MC.Q_tsimrenamed_net_ )
  );
  X_INV   \out<6>_MC.REG_tsimcreated_inv_clock_i_II/FCLK  (
    .I(\clock_i_II/FCLK_5 ),
    .O(\out<6>_MC.REG_tsimcreated_inv_clock_i_II/FCLK_123 )
  );
  X_XOR2   \out<6>_MC.D  (
    .I0(\NlwInverterSignal_out<6>_MC.D/IN0 ),
    .I1(\out<6>_MC.D2_125 ),
    .O(\out<6>_MC.D_122 )
  );
  X_ZERO   \out<6>_MC.D1  (
    .O(\out<6>_MC.D1_124 )
  );
  X_AND2   \out<6>_MC.D2_PT_0  (
    .I0(\NlwInverterSignal_out<6>_MC.D2_PT_0/IN0 ),
    .I1(\NlwInverterSignal_out<6>_MC.D2_PT_0/IN1 ),
    .O(\out<6>_MC.D2_PT_0_126 )
  );
  X_AND2   \out<6>_MC.D2_PT_1  (
    .I0(\clear_warnings_i_II/UIM_3 ),
    .I1(\incoming_data_i<6>_II/UIM_19 ),
    .O(\out<6>_MC.D2_PT_1_127 )
  );
  X_AND2   \out<6>_MC.D2_PT_2  (
    .I0(\NlwInverterSignal_out<6>_MC.D2_PT_2/IN0 ),
    .I1(\NlwInverterSignal_out<6>_MC.D2_PT_2/IN1 ),
    .O(\out<6>_MC.D2_PT_2_128 )
  );
  X_OR3   \out<6>_MC.D2  (
    .I0(\out<6>_MC.D2_PT_0_126 ),
    .I1(\out<6>_MC.D2_PT_1_127 ),
    .I2(\out<6>_MC.D2_PT_2_128 ),
    .O(\out<6>_MC.D2_125 )
  );
  X_BUF   \out<7>_MC.Q  (
    .I(\out<7>_MC.Q_tsimrenamed_net_ ),
    .O(\out<7>_MC.Q_55 )
  );
  X_BUF   \out<7>_MC.UIM  (
    .I(\out<7>_MC.Q_tsimrenamed_net_ ),
    .O(\out<7>_MC.UIM_130 )
  );
  X_OR2   \out<7>_MC_tsimcreated_prld_  (
    .I0(\FOOBAR1__ctinst/7_58 ),
    .I1(Gnd_59),
    .O(\out<7>_MC_tsimcreated_prld__131 )
  );
  X_FF #(
    .INIT ( 1'b0 ))
  \out<7>_MC.REG  (
    .I(\out<7>_MC.D_132 ),
    .CE(Vcc_63),
    .CLK(\out<7>_MC.REG_tsimcreated_inv_clock_i_II/FCLK_133 ),
    .SET(Gnd_59),
    .RST(\out<7>_MC_tsimcreated_prld__131 ),
    .O(\out<7>_MC.Q_tsimrenamed_net_ )
  );
  X_INV   \out<7>_MC.REG_tsimcreated_inv_clock_i_II/FCLK  (
    .I(\clock_i_II/FCLK_5 ),
    .O(\out<7>_MC.REG_tsimcreated_inv_clock_i_II/FCLK_133 )
  );
  X_XOR2   \out<7>_MC.D  (
    .I0(\NlwInverterSignal_out<7>_MC.D/IN0 ),
    .I1(\out<7>_MC.D2_135 ),
    .O(\out<7>_MC.D_132 )
  );
  X_ZERO   \out<7>_MC.D1  (
    .O(\out<7>_MC.D1_134 )
  );
  X_AND2   \out<7>_MC.D2_PT_0  (
    .I0(\NlwInverterSignal_out<7>_MC.D2_PT_0/IN0 ),
    .I1(\NlwInverterSignal_out<7>_MC.D2_PT_0/IN1 ),
    .O(\out<7>_MC.D2_PT_0_136 )
  );
  X_AND2   \out<7>_MC.D2_PT_1  (
    .I0(\clear_warnings_i_II/UIM_3 ),
    .I1(\incoming_data_i<7>_II/UIM_21 ),
    .O(\out<7>_MC.D2_PT_1_137 )
  );
  X_AND2   \out<7>_MC.D2_PT_2  (
    .I0(\NlwInverterSignal_out<7>_MC.D2_PT_2/IN0 ),
    .I1(\NlwInverterSignal_out<7>_MC.D2_PT_2/IN1 ),
    .O(\out<7>_MC.D2_PT_2_138 )
  );
  X_OR3   \out<7>_MC.D2  (
    .I0(\out<7>_MC.D2_PT_0_136 ),
    .I1(\out<7>_MC.D2_PT_1_137 ),
    .I2(\out<7>_MC.D2_PT_2_138 ),
    .O(\out<7>_MC.D2_135 )
  );
  X_AND2   \FOOBAR1__ctinst/7  (
    .I0(\reset_i_II/UIM_25 ),
    .I1(\reset_i_II/UIM_25 ),
    .O(\FOOBAR1__ctinst/7_58 )
  );
  X_INV   \NlwInverterBlock_out<0>_MC.D/IN0  (
    .I(\out<0>_MC.D1_64 ),
    .O(\NlwInverterSignal_out<0>_MC.D/IN0 )
  );
  X_INV   \NlwInverterBlock_out<0>_MC.D2_PT_0/IN0  (
    .I(\armed_i_II/UIM_1 ),
    .O(\NlwInverterSignal_out<0>_MC.D2_PT_0/IN0 )
  );
  X_INV   \NlwInverterBlock_out<0>_MC.D2_PT_0/IN1  (
    .I(\out<0>_MC.UIM_57 ),
    .O(\NlwInverterSignal_out<0>_MC.D2_PT_0/IN1 )
  );
  X_INV   \NlwInverterBlock_out<0>_MC.D2_PT_2/IN0  (
    .I(\warnings_i<0>_II/UIM_23 ),
    .O(\NlwInverterSignal_out<0>_MC.D2_PT_2/IN0 )
  );
  X_INV   \NlwInverterBlock_out<0>_MC.D2_PT_2/IN1  (
    .I(\out<0>_MC.UIM_57 ),
    .O(\NlwInverterSignal_out<0>_MC.D2_PT_2/IN1 )
  );
  X_INV   \NlwInverterBlock_out<1>_MC.D/IN0  (
    .I(\out<1>_MC.D1_74 ),
    .O(\NlwInverterSignal_out<1>_MC.D/IN0 )
  );
  X_INV   \NlwInverterBlock_out<1>_MC.D2_PT_0/IN0  (
    .I(\armed_i_II/UIM_1 ),
    .O(\NlwInverterSignal_out<1>_MC.D2_PT_0/IN0 )
  );
  X_INV   \NlwInverterBlock_out<1>_MC.D2_PT_0/IN1  (
    .I(\out<1>_MC.UIM_70 ),
    .O(\NlwInverterSignal_out<1>_MC.D2_PT_0/IN1 )
  );
  X_INV   \NlwInverterBlock_out<1>_MC.D2_PT_2/IN0  (
    .I(\out<1>_MC.UIM_70 ),
    .O(\NlwInverterSignal_out<1>_MC.D2_PT_2/IN0 )
  );
  X_INV   \NlwInverterBlock_out<1>_MC.D2_PT_2/IN1  (
    .I(\warnings_i<1>_II/UIM_27 ),
    .O(\NlwInverterSignal_out<1>_MC.D2_PT_2/IN1 )
  );
  X_INV   \NlwInverterBlock_out<2>_MC.D/IN0  (
    .I(\out<2>_MC.D1_84 ),
    .O(\NlwInverterSignal_out<2>_MC.D/IN0 )
  );
  X_INV   \NlwInverterBlock_out<2>_MC.D2_PT_0/IN0  (
    .I(\armed_i_II/UIM_1 ),
    .O(\NlwInverterSignal_out<2>_MC.D2_PT_0/IN0 )
  );
  X_INV   \NlwInverterBlock_out<2>_MC.D2_PT_0/IN1  (
    .I(\out<2>_MC.UIM_80 ),
    .O(\NlwInverterSignal_out<2>_MC.D2_PT_0/IN1 )
  );
  X_INV   \NlwInverterBlock_out<2>_MC.D2_PT_2/IN0  (
    .I(\out<2>_MC.UIM_80 ),
    .O(\NlwInverterSignal_out<2>_MC.D2_PT_2/IN0 )
  );
  X_INV   \NlwInverterBlock_out<2>_MC.D2_PT_2/IN1  (
    .I(\warnings_i<2>_II/UIM_29 ),
    .O(\NlwInverterSignal_out<2>_MC.D2_PT_2/IN1 )
  );
  X_INV   \NlwInverterBlock_out<3>_MC.D/IN0  (
    .I(\out<3>_MC.D1_94 ),
    .O(\NlwInverterSignal_out<3>_MC.D/IN0 )
  );
  X_INV   \NlwInverterBlock_out<3>_MC.D2_PT_0/IN0  (
    .I(\armed_i_II/UIM_1 ),
    .O(\NlwInverterSignal_out<3>_MC.D2_PT_0/IN0 )
  );
  X_INV   \NlwInverterBlock_out<3>_MC.D2_PT_0/IN1  (
    .I(\out<3>_MC.UIM_90 ),
    .O(\NlwInverterSignal_out<3>_MC.D2_PT_0/IN1 )
  );
  X_INV   \NlwInverterBlock_out<3>_MC.D2_PT_2/IN0  (
    .I(\out<3>_MC.UIM_90 ),
    .O(\NlwInverterSignal_out<3>_MC.D2_PT_2/IN0 )
  );
  X_INV   \NlwInverterBlock_out<3>_MC.D2_PT_2/IN1  (
    .I(\warnings_i<3>_II/UIM_31 ),
    .O(\NlwInverterSignal_out<3>_MC.D2_PT_2/IN1 )
  );
  X_INV   \NlwInverterBlock_out<4>_MC.D/IN0  (
    .I(\out<4>_MC.D1_104 ),
    .O(\NlwInverterSignal_out<4>_MC.D/IN0 )
  );
  X_INV   \NlwInverterBlock_out<4>_MC.D2_PT_0/IN0  (
    .I(\armed_i_II/UIM_1 ),
    .O(\NlwInverterSignal_out<4>_MC.D2_PT_0/IN0 )
  );
  X_INV   \NlwInverterBlock_out<4>_MC.D2_PT_0/IN1  (
    .I(\out<4>_MC.UIM_100 ),
    .O(\NlwInverterSignal_out<4>_MC.D2_PT_0/IN1 )
  );
  X_INV   \NlwInverterBlock_out<4>_MC.D2_PT_2/IN0  (
    .I(\out<4>_MC.UIM_100 ),
    .O(\NlwInverterSignal_out<4>_MC.D2_PT_2/IN0 )
  );
  X_INV   \NlwInverterBlock_out<4>_MC.D2_PT_2/IN1  (
    .I(\warnings_i<4>_II/UIM_33 ),
    .O(\NlwInverterSignal_out<4>_MC.D2_PT_2/IN1 )
  );
  X_INV   \NlwInverterBlock_out<5>_MC.D/IN0  (
    .I(\out<5>_MC.D1_114 ),
    .O(\NlwInverterSignal_out<5>_MC.D/IN0 )
  );
  X_INV   \NlwInverterBlock_out<5>_MC.D2_PT_0/IN0  (
    .I(\armed_i_II/UIM_1 ),
    .O(\NlwInverterSignal_out<5>_MC.D2_PT_0/IN0 )
  );
  X_INV   \NlwInverterBlock_out<5>_MC.D2_PT_0/IN1  (
    .I(\out<5>_MC.UIM_110 ),
    .O(\NlwInverterSignal_out<5>_MC.D2_PT_0/IN1 )
  );
  X_INV   \NlwInverterBlock_out<5>_MC.D2_PT_2/IN0  (
    .I(\out<5>_MC.UIM_110 ),
    .O(\NlwInverterSignal_out<5>_MC.D2_PT_2/IN0 )
  );
  X_INV   \NlwInverterBlock_out<5>_MC.D2_PT_2/IN1  (
    .I(\warnings_i<5>_II/UIM_35 ),
    .O(\NlwInverterSignal_out<5>_MC.D2_PT_2/IN1 )
  );
  X_INV   \NlwInverterBlock_out<6>_MC.D/IN0  (
    .I(\out<6>_MC.D1_124 ),
    .O(\NlwInverterSignal_out<6>_MC.D/IN0 )
  );
  X_INV   \NlwInverterBlock_out<6>_MC.D2_PT_0/IN0  (
    .I(\armed_i_II/UIM_1 ),
    .O(\NlwInverterSignal_out<6>_MC.D2_PT_0/IN0 )
  );
  X_INV   \NlwInverterBlock_out<6>_MC.D2_PT_0/IN1  (
    .I(\out<6>_MC.UIM_120 ),
    .O(\NlwInverterSignal_out<6>_MC.D2_PT_0/IN1 )
  );
  X_INV   \NlwInverterBlock_out<6>_MC.D2_PT_2/IN0  (
    .I(\out<6>_MC.UIM_120 ),
    .O(\NlwInverterSignal_out<6>_MC.D2_PT_2/IN0 )
  );
  X_INV   \NlwInverterBlock_out<6>_MC.D2_PT_2/IN1  (
    .I(\warnings_i<6>_II/UIM_37 ),
    .O(\NlwInverterSignal_out<6>_MC.D2_PT_2/IN1 )
  );
  X_INV   \NlwInverterBlock_out<7>_MC.D/IN0  (
    .I(\out<7>_MC.D1_134 ),
    .O(\NlwInverterSignal_out<7>_MC.D/IN0 )
  );
  X_INV   \NlwInverterBlock_out<7>_MC.D2_PT_0/IN0  (
    .I(\armed_i_II/UIM_1 ),
    .O(\NlwInverterSignal_out<7>_MC.D2_PT_0/IN0 )
  );
  X_INV   \NlwInverterBlock_out<7>_MC.D2_PT_0/IN1  (
    .I(\out<7>_MC.UIM_130 ),
    .O(\NlwInverterSignal_out<7>_MC.D2_PT_0/IN1 )
  );
  X_INV   \NlwInverterBlock_out<7>_MC.D2_PT_2/IN0  (
    .I(\out<7>_MC.UIM_130 ),
    .O(\NlwInverterSignal_out<7>_MC.D2_PT_2/IN0 )
  );
  X_INV   \NlwInverterBlock_out<7>_MC.D2_PT_2/IN1  (
    .I(\warnings_i<7>_II/UIM_39 ),
    .O(\NlwInverterSignal_out<7>_MC.D2_PT_2/IN1 )
  );
endmodule


`timescale  1 ps / 1 ps

module glbl ();

    parameter ROC_WIDTH = 100000;
    parameter TOC_WIDTH = 0;

    wire GSR;
    wire GTS;
    wire PRLD;

    reg GSR_int;
    reg GTS_int;
    reg PRLD_int;

//--------   JTAG Globals --------------
    wire JTAG_TDO_GLBL;
    wire JTAG_TCK_GLBL;
    wire JTAG_TDI_GLBL;
    wire JTAG_TMS_GLBL;
    wire JTAG_TRST_GLBL;

    reg JTAG_CAPTURE_GLBL;
    reg JTAG_RESET_GLBL;
    reg JTAG_SHIFT_GLBL;
    reg JTAG_UPDATE_GLBL;

    reg JTAG_SEL1_GLBL = 0;
    reg JTAG_SEL2_GLBL = 0 ;
    reg JTAG_SEL3_GLBL = 0;
    reg JTAG_SEL4_GLBL = 0;

    reg JTAG_USER_TDO1_GLBL = 1'bz;
    reg JTAG_USER_TDO2_GLBL = 1'bz;
    reg JTAG_USER_TDO3_GLBL = 1'bz;
    reg JTAG_USER_TDO4_GLBL = 1'bz;

    assign (weak1, weak0) GSR = GSR_int;
    assign (weak1, weak0) GTS = GTS_int;
    assign (weak1, weak0) PRLD = PRLD_int;

    initial begin
	GSR_int = 1'b1;
	PRLD_int = 1'b1;
	#(ROC_WIDTH)
	GSR_int = 1'b0;
	PRLD_int = 1'b0;
    end

    initial begin
	GTS_int = 1'b1;
	#(TOC_WIDTH)
	GTS_int = 1'b0;
    end

endmodule