module gentest #(
	parameter 		SIZE = 8
)(
	input				clock_i,
	input				reset_i,  
	input[SIZE-1:0]		warnings_i, 
	input[SIZE-1:0]		incoming_data_i,
	input				clear_warnings_i,	
	input				armed_i,
	output[SIZE-1:0]	out
);

reg[SIZE-1:0]	warning_register;

genvar i;

generate
	for(i =0 ; i <SIZE ; i = i + 1)
		begin : warning_register_bits
			always @(negedge clock_i or posedge reset_i)
				if (reset_i) 
					warning_register[i] <= 1'b0;	  									
				else if (clear_warnings_i & incoming_data_i[i]) 
					warning_register[i] <= 1'b0;									    
				else if (warnings_i[i] & armed_i)
					warning_register[i] <= 1'b1;	
		end
endgenerate	  

assign out = warning_register;

endmodule